[rustc.git] / src / llvm / lib / Target / Sparc / SparcInstrInfo.cpp

//===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the Sparc implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//

#include "SparcInstrInfo.h"
#include "Sparc.h"
#include "SparcMachineFunctionInfo.h"
#include "SparcSubtarget.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TargetRegistry.h"

using namespace llvm;

#define GET_INSTRINFO_CTOR_DTOR
#include "SparcGenInstrInfo.inc"

// Pin the vtable to this file.
void SparcInstrInfo::anchor() {}

SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
  : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
    RI(ST), Subtarget(ST) {
}

/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot.  If
/// not, return 0.  This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot.
unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
                                             int &FrameIndex) const {
  if (MI->getOpcode() == SP::LDri ||
      MI->getOpcode() == SP::LDXri ||
      MI->getOpcode() == SP::LDFri ||
      MI->getOpcode() == SP::LDDFri ||
      MI->getOpcode() == SP::LDQFri) {
    if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
        MI->getOperand(2).getImm() == 0) {
      FrameIndex = MI->getOperand(1).getIndex();
      return MI->getOperand(0).getReg();
    }
  }
  return 0;
}

/// isStoreToStackSlot - If the specified machine instruction is a direct
/// store to a stack slot, return the virtual or physical register number of
/// the source reg along with the FrameIndex of the loaded stack slot.  If
/// not, return 0.  This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot.
unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
                                            int &FrameIndex) const {
  if (MI->getOpcode() == SP::STri ||
      MI->getOpcode() == SP::STXri ||
      MI->getOpcode() == SP::STFri ||
      MI->getOpcode() == SP::STDFri ||
      MI->getOpcode() == SP::STQFri) {
    if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
        MI->getOperand(1).getImm() == 0) {
      FrameIndex = MI->getOperand(0).getIndex();
      return MI->getOperand(2).getReg();
    }
  }
  return 0;
}

static bool IsIntegerCC(unsigned CC)
{
  return  (CC <= SPCC::ICC_VC);
}


static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
{
  switch(CC) {
  case SPCC::ICC_A:    return SPCC::ICC_N;
  case SPCC::ICC_N:    return SPCC::ICC_A;
  case SPCC::ICC_NE:   return SPCC::ICC_E;
  case SPCC::ICC_E:    return SPCC::ICC_NE;
  case SPCC::ICC_G:    return SPCC::ICC_LE;
  case SPCC::ICC_LE:   return SPCC::ICC_G;
  case SPCC::ICC_GE:   return SPCC::ICC_L;
  case SPCC::ICC_L:    return SPCC::ICC_GE;
  case SPCC::ICC_GU:   return SPCC::ICC_LEU;
  case SPCC::ICC_LEU:  return SPCC::ICC_GU;
  case SPCC::ICC_CC:   return SPCC::ICC_CS;
  case SPCC::ICC_CS:   return SPCC::ICC_CC;
  case SPCC::ICC_POS:  return SPCC::ICC_NEG;
  case SPCC::ICC_NEG:  return SPCC::ICC_POS;
  case SPCC::ICC_VC:   return SPCC::ICC_VS;
  case SPCC::ICC_VS:   return SPCC::ICC_VC;

  case SPCC::FCC_A:    return SPCC::FCC_N;
  case SPCC::FCC_N:    return SPCC::FCC_A;
  case SPCC::FCC_U:    return SPCC::FCC_O;
  case SPCC::FCC_O:    return SPCC::FCC_U;
  case SPCC::FCC_G:    return SPCC::FCC_ULE;
  case SPCC::FCC_LE:   return SPCC::FCC_UG;
  case SPCC::FCC_UG:   return SPCC::FCC_LE;
  case SPCC::FCC_ULE:  return SPCC::FCC_G;
  case SPCC::FCC_L:    return SPCC::FCC_UGE;
  case SPCC::FCC_GE:   return SPCC::FCC_UL;
  case SPCC::FCC_UL:   return SPCC::FCC_GE;
  case SPCC::FCC_UGE:  return SPCC::FCC_L;
  case SPCC::FCC_LG:   return SPCC::FCC_UE;
  case SPCC::FCC_UE:   return SPCC::FCC_LG;
  case SPCC::FCC_NE:   return SPCC::FCC_E;
  case SPCC::FCC_E:    return SPCC::FCC_NE;
  }
  llvm_unreachable("Invalid cond code");
}

bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
                                   MachineBasicBlock *&TBB,
                                   MachineBasicBlock *&FBB,
                                   SmallVectorImpl<MachineOperand> &Cond,
                                   bool AllowModify) const
{

  MachineBasicBlock::iterator I = MBB.end();
  MachineBasicBlock::iterator UnCondBrIter = MBB.end();
  while (I != MBB.begin()) {
    --I;

    if (I->isDebugValue())
      continue;

    // When we see a non-terminator, we are done.
    if (!isUnpredicatedTerminator(I))
      break;

    // Terminator is not a branch.
    if (!I->isBranch())
      return true;

    // Handle Unconditional branches.
    if (I->getOpcode() == SP::BA) {
      UnCondBrIter = I;

      if (!AllowModify) {
        TBB = I->getOperand(0).getMBB();
        continue;
      }

      while (std::next(I) != MBB.end())
        std::next(I)->eraseFromParent();

      Cond.clear();
      FBB = nullptr;

      if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
        TBB = nullptr;
        I->eraseFromParent();
        I = MBB.end();
        UnCondBrIter = MBB.end();
        continue;
      }

      TBB = I->getOperand(0).getMBB();
      continue;
    }

    unsigned Opcode = I->getOpcode();
    if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
      return true; // Unknown Opcode.

    SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();

    if (Cond.empty()) {
      MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
      if (AllowModify && UnCondBrIter != MBB.end() &&
          MBB.isLayoutSuccessor(TargetBB)) {

        // Transform the code
        //
        //    brCC L1
        //    ba L2
        // L1:
        //    ..
        // L2:
        //
        // into
        //
        //   brnCC L2
        // L1:
        //   ...
        // L2:
        //
        BranchCode = GetOppositeBranchCondition(BranchCode);
        MachineBasicBlock::iterator OldInst = I;
        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
          .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
          .addMBB(TargetBB);

        OldInst->eraseFromParent();
        UnCondBrIter->eraseFromParent();

        UnCondBrIter = MBB.end();
        I = MBB.end();
        continue;
      }
      FBB = TBB;
      TBB = I->getOperand(0).getMBB();
      Cond.push_back(MachineOperand::CreateImm(BranchCode));
      continue;
    }
    // FIXME: Handle subsequent conditional branches.
    // For now, we can't handle multiple conditional branches.
    return true;
  }
  return false;
}

unsigned
SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
                             MachineBasicBlock *FBB,
                             const SmallVectorImpl<MachineOperand> &Cond,
                             DebugLoc DL) const {
  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
  assert((Cond.size() == 1 || Cond.size() == 0) &&
         "Sparc branch conditions should have one component!");

  if (Cond.empty()) {
    assert(!FBB && "Unconditional branch with multiple successors!");
    BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
    return 1;
  }

  // Conditional branch
  unsigned CC = Cond[0].getImm();

  if (IsIntegerCC(CC))
    BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
  else
    BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
  if (!FBB)
    return 1;

  BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
  return 2;
}

unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
{
  MachineBasicBlock::iterator I = MBB.end();
  unsigned Count = 0;
  while (I != MBB.begin()) {
    --I;

    if (I->isDebugValue())
      continue;

    if (I->getOpcode() != SP::BA
        && I->getOpcode() != SP::BCOND
        && I->getOpcode() != SP::FBCOND)
      break; // Not a branch

    I->eraseFromParent();
    I = MBB.end();
    ++Count;
  }
  return Count;
}

void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator I, DebugLoc DL,
                                 unsigned DestReg, unsigned SrcReg,
                                 bool KillSrc) const {
  unsigned numSubRegs = 0;
  unsigned movOpc     = 0;
  const unsigned *subRegIdx = nullptr;

  const unsigned DFP_FP_SubRegsIdx[]  = { SP::sub_even, SP::sub_odd };
  const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };
  const unsigned QFP_FP_SubRegsIdx[]  = { SP::sub_even, SP::sub_odd,
                                          SP::sub_odd64_then_sub_even,
                                          SP::sub_odd64_then_sub_odd };

  if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
    BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
      .addReg(SrcReg, getKillRegState(KillSrc));
  else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
    BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
      .addReg(SrcReg, getKillRegState(KillSrc));
  else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
    if (Subtarget.isV9()) {
      BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
        .addReg(SrcReg, getKillRegState(KillSrc));
    } else {
      // Use two FMOVS instructions.
      subRegIdx  = DFP_FP_SubRegsIdx;
      numSubRegs = 2;
      movOpc     = SP::FMOVS;
    }
  } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
    if (Subtarget.isV9()) {
      if (Subtarget.hasHardQuad()) {
        BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
          .addReg(SrcReg, getKillRegState(KillSrc));
      } else {
        // Use two FMOVD instructions.
        subRegIdx  = QFP_DFP_SubRegsIdx;
        numSubRegs = 2;
        movOpc     = SP::FMOVD;
      }
    } else {
      // Use four FMOVS instructions.
      subRegIdx  = QFP_FP_SubRegsIdx;
      numSubRegs = 4;
      movOpc     = SP::FMOVS;
    }
  } else
    llvm_unreachable("Impossible reg-to-reg copy");

  if (numSubRegs == 0 || subRegIdx == nullptr || movOpc == 0)
    return;

  const TargetRegisterInfo *TRI = &getRegisterInfo();
  MachineInstr *MovMI = nullptr;

  for (unsigned i = 0; i != numSubRegs; ++i) {
    unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
    unsigned Src = TRI->getSubReg(SrcReg,  subRegIdx[i]);
    assert(Dst && Src && "Bad sub-register");

    MovMI = BuildMI(MBB, I, DL, get(movOpc), Dst).addReg(Src);
  }
  // Add implicit super-register defs and kills to the last MovMI.
  MovMI->addRegisterDefined(DestReg, TRI);
  if (KillSrc)
    MovMI->addRegisterKilled(SrcReg, TRI);
}

void SparcInstrInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                    unsigned SrcReg, bool isKill, int FI,
                    const TargetRegisterClass *RC,
                    const TargetRegisterInfo *TRI) const {
  DebugLoc DL;
  if (I != MBB.end()) DL = I->getDebugLoc();

  MachineFunction *MF = MBB.getParent();
  const MachineFrameInfo &MFI = *MF->getFrameInfo();
  MachineMemOperand *MMO =
    MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
                             MachineMemOperand::MOStore,
                             MFI.getObjectSize(FI),
                             MFI.getObjectAlignment(FI));

  // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
 if (RC == &SP::I64RegsRegClass)
    BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
      .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
  else if (RC == &SP::IntRegsRegClass)
    BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
      .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
  else if (RC == &SP::FPRegsRegClass)
    BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
      .addReg(SrcReg,  getKillRegState(isKill)).addMemOperand(MMO);
  else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
    BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
      .addReg(SrcReg,  getKillRegState(isKill)).addMemOperand(MMO);
  else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
    // Use STQFri irrespective of its legality. If STQ is not legal, it will be
    // lowered into two STDs in eliminateFrameIndex.
    BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)
      .addReg(SrcReg,  getKillRegState(isKill)).addMemOperand(MMO);
  else
    llvm_unreachable("Can't store this register to stack slot");
}

void SparcInstrInfo::
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                     unsigned DestReg, int FI,
                     const TargetRegisterClass *RC,
                     const TargetRegisterInfo *TRI) const {
  DebugLoc DL;
  if (I != MBB.end()) DL = I->getDebugLoc();

  MachineFunction *MF = MBB.getParent();
  const MachineFrameInfo &MFI = *MF->getFrameInfo();
  MachineMemOperand *MMO =
    MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
                             MachineMemOperand::MOLoad,
                             MFI.getObjectSize(FI),
                             MFI.getObjectAlignment(FI));

  if (RC == &SP::I64RegsRegClass)
    BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0)
      .addMemOperand(MMO);
  else if (RC == &SP::IntRegsRegClass)
    BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0)
      .addMemOperand(MMO);
  else if (RC == &SP::FPRegsRegClass)
    BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
      .addMemOperand(MMO);
  else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
    BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0)
      .addMemOperand(MMO);
  else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
    // Use LDQFri irrespective of its legality. If LDQ is not legal, it will be
    // lowered into two LDDs in eliminateFrameIndex.
    BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
      .addMemOperand(MMO);
  else
    llvm_unreachable("Can't load this register from stack slot");
}

unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
{
  SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
  unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg();
  if (GlobalBaseReg != 0)
    return GlobalBaseReg;

  // Insert the set of GlobalBaseReg into the first MBB of the function
  MachineBasicBlock &FirstMBB = MF->front();
  MachineBasicBlock::iterator MBBI = FirstMBB.begin();
  MachineRegisterInfo &RegInfo = MF->getRegInfo();

  const TargetRegisterClass *PtrRC =
    Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
  GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);

  DebugLoc dl;

  BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
  SparcFI->setGlobalBaseReg(GlobalBaseReg);
  return GlobalBaseReg;
}
Commit	Line	Data
223e47cc LB	1	//===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===//
	2	//
	3	// The LLVM Compiler Infrastructure
	4	//
	5	// This file is distributed under the University of Illinois Open Source
	6	// License. See LICENSE.TXT for details.
	7	//
	8	//===----------------------------------------------------------------------===//
	9	//
	10	// This file contains the Sparc implementation of the TargetInstrInfo class.
	11	//
	12	//===----------------------------------------------------------------------===//
	13
	14	#include "SparcInstrInfo.h"
	15	#include "Sparc.h"
	16	#include "SparcMachineFunctionInfo.h"
	17	#include "SparcSubtarget.h"
970d7e83 LB	18	#include "llvm/ADT/STLExtras.h"
970d7e83 LB	19	#include "llvm/ADT/SmallVector.h"
1a4d82fc	20	#include "llvm/CodeGen/MachineFrameInfo.h"
223e47cc	21	#include "llvm/CodeGen/MachineInstrBuilder.h"
1a4d82fc	22	#include "llvm/CodeGen/MachineMemOperand.h"
223e47cc LB	23	#include "llvm/CodeGen/MachineRegisterInfo.h"
	24	#include "llvm/Support/ErrorHandling.h"
	25	#include "llvm/Support/TargetRegistry.h"
223e47cc	26
1a4d82fc JJ	27	using namespace llvm;
	28
	29	#define GET_INSTRINFO_CTOR_DTOR
223e47cc LB	30	#include "SparcGenInstrInfo.inc"
223e47cc LB	31
1a4d82fc JJ	32	// Pin the vtable to this file.
1a4d82fc JJ	33	void SparcInstrInfo::anchor() {}
223e47cc LB	34
	35	SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
	36	: SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
1a4d82fc	37	RI(ST), Subtarget(ST) {
223e47cc LB	38	}
	39
	40	/// isLoadFromStackSlot - If the specified machine instruction is a direct
	41	/// load from a stack slot, return the virtual or physical register number of
	42	/// the destination along with the FrameIndex of the loaded stack slot. If
	43	/// not, return 0. This predicate must return 0 if the instruction has
	44	/// any side effects other than loading from the stack slot.
	45	unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
	46	int &FrameIndex) const {
	47	if (MI->getOpcode() == SP::LDri \|\|
1a4d82fc	48	MI->getOpcode() == SP::LDXri \|\|
223e47cc	49	MI->getOpcode() == SP::LDFri \|\|
1a4d82fc JJ	50	MI->getOpcode() == SP::LDDFri \|\|
1a4d82fc JJ	51	MI->getOpcode() == SP::LDQFri) {
223e47cc LB	52	if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
	53	MI->getOperand(2).getImm() == 0) {
	54	FrameIndex = MI->getOperand(1).getIndex();
	55	return MI->getOperand(0).getReg();
	56	}
	57	}
	58	return 0;
	59	}
	60
	61	/// isStoreToStackSlot - If the specified machine instruction is a direct
	62	/// store to a stack slot, return the virtual or physical register number of
	63	/// the source reg along with the FrameIndex of the loaded stack slot. If
	64	/// not, return 0. This predicate must return 0 if the instruction has
	65	/// any side effects other than storing to the stack slot.
	66	unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
	67	int &FrameIndex) const {
	68	if (MI->getOpcode() == SP::STri \|\|
1a4d82fc	69	MI->getOpcode() == SP::STXri \|\|
223e47cc	70	MI->getOpcode() == SP::STFri \|\|
1a4d82fc JJ	71	MI->getOpcode() == SP::STDFri \|\|
1a4d82fc JJ	72	MI->getOpcode() == SP::STQFri) {
223e47cc LB	73	if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
	74	MI->getOperand(1).getImm() == 0) {
	75	FrameIndex = MI->getOperand(0).getIndex();
	76	return MI->getOperand(2).getReg();
	77	}
	78	}
	79	return 0;
	80	}
	81
	82	static bool IsIntegerCC(unsigned CC)
	83	{
	84	return (CC <= SPCC::ICC_VC);
	85	}
	86
	87
	88	static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
	89	{
	90	switch(CC) {
1a4d82fc JJ	91	case SPCC::ICC_A: return SPCC::ICC_N;
1a4d82fc JJ	92	case SPCC::ICC_N: return SPCC::ICC_A;
223e47cc LB	93	case SPCC::ICC_NE: return SPCC::ICC_E;
	94	case SPCC::ICC_E: return SPCC::ICC_NE;
	95	case SPCC::ICC_G: return SPCC::ICC_LE;
	96	case SPCC::ICC_LE: return SPCC::ICC_G;
	97	case SPCC::ICC_GE: return SPCC::ICC_L;
	98	case SPCC::ICC_L: return SPCC::ICC_GE;
	99	case SPCC::ICC_GU: return SPCC::ICC_LEU;
	100	case SPCC::ICC_LEU: return SPCC::ICC_GU;
	101	case SPCC::ICC_CC: return SPCC::ICC_CS;
	102	case SPCC::ICC_CS: return SPCC::ICC_CC;
	103	case SPCC::ICC_POS: return SPCC::ICC_NEG;
	104	case SPCC::ICC_NEG: return SPCC::ICC_POS;
	105	case SPCC::ICC_VC: return SPCC::ICC_VS;
	106	case SPCC::ICC_VS: return SPCC::ICC_VC;
	107
1a4d82fc JJ	108	case SPCC::FCC_A: return SPCC::FCC_N;
1a4d82fc JJ	109	case SPCC::FCC_N: return SPCC::FCC_A;
223e47cc LB	110	case SPCC::FCC_U: return SPCC::FCC_O;
223e47cc LB	111	case SPCC::FCC_O: return SPCC::FCC_U;
1a4d82fc JJ	112	case SPCC::FCC_G: return SPCC::FCC_ULE;
	113	case SPCC::FCC_LE: return SPCC::FCC_UG;
	114	case SPCC::FCC_UG: return SPCC::FCC_LE;
	115	case SPCC::FCC_ULE: return SPCC::FCC_G;
	116	case SPCC::FCC_L: return SPCC::FCC_UGE;
	117	case SPCC::FCC_GE: return SPCC::FCC_UL;
	118	case SPCC::FCC_UL: return SPCC::FCC_GE;
	119	case SPCC::FCC_UGE: return SPCC::FCC_L;
223e47cc LB	120	case SPCC::FCC_LG: return SPCC::FCC_UE;
	121	case SPCC::FCC_UE: return SPCC::FCC_LG;
	122	case SPCC::FCC_NE: return SPCC::FCC_E;
	123	case SPCC::FCC_E: return SPCC::FCC_NE;
	124	}
	125	llvm_unreachable("Invalid cond code");
	126	}
	127
223e47cc LB	128	bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
	129	MachineBasicBlock *&TBB,
	130	MachineBasicBlock *&FBB,
	131	SmallVectorImpl<MachineOperand> &Cond,
	132	bool AllowModify) const
	133	{
	134
	135	MachineBasicBlock::iterator I = MBB.end();
	136	MachineBasicBlock::iterator UnCondBrIter = MBB.end();
	137	while (I != MBB.begin()) {
	138	--I;
	139
	140	if (I->isDebugValue())
	141	continue;
	142
1a4d82fc	143	// When we see a non-terminator, we are done.
223e47cc LB	144	if (!isUnpredicatedTerminator(I))
	145	break;
	146
1a4d82fc	147	// Terminator is not a branch.
223e47cc LB	148	if (!I->isBranch())
	149	return true;
	150
1a4d82fc	151	// Handle Unconditional branches.
223e47cc LB	152	if (I->getOpcode() == SP::BA) {
	153	UnCondBrIter = I;
	154
	155	if (!AllowModify) {
	156	TBB = I->getOperand(0).getMBB();
	157	continue;
	158	}
	159
1a4d82fc JJ	160	while (std::next(I) != MBB.end())
1a4d82fc JJ	161	std::next(I)->eraseFromParent();
223e47cc LB	162
223e47cc LB	163	Cond.clear();
1a4d82fc	164	FBB = nullptr;
223e47cc LB	165
223e47cc LB	166	if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1a4d82fc	167	TBB = nullptr;
223e47cc LB	168	I->eraseFromParent();
	169	I = MBB.end();
	170	UnCondBrIter = MBB.end();
	171	continue;
	172	}
	173
	174	TBB = I->getOperand(0).getMBB();
	175	continue;
	176	}
	177
	178	unsigned Opcode = I->getOpcode();
	179	if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
1a4d82fc	180	return true; // Unknown Opcode.
223e47cc LB	181
	182	SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
	183
	184	if (Cond.empty()) {
	185	MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
	186	if (AllowModify && UnCondBrIter != MBB.end() &&
	187	MBB.isLayoutSuccessor(TargetBB)) {
	188
1a4d82fc	189	// Transform the code
223e47cc LB	190	//
	191	// brCC L1
	192	// ba L2
	193	// L1:
	194	// ..
	195	// L2:
	196	//
	197	// into
	198	//
	199	// brnCC L2
	200	// L1:
	201	// ...
	202	// L2:
	203	//
	204	BranchCode = GetOppositeBranchCondition(BranchCode);
	205	MachineBasicBlock::iterator OldInst = I;
	206	BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
	207	.addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
	208	BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
	209	.addMBB(TargetBB);
	210
	211	OldInst->eraseFromParent();
	212	UnCondBrIter->eraseFromParent();
	213
	214	UnCondBrIter = MBB.end();
	215	I = MBB.end();
	216	continue;
	217	}
	218	FBB = TBB;
	219	TBB = I->getOperand(0).getMBB();
	220	Cond.push_back(MachineOperand::CreateImm(BranchCode));
	221	continue;
	222	}
1a4d82fc JJ	223	// FIXME: Handle subsequent conditional branches.
1a4d82fc JJ	224	// For now, we can't handle multiple conditional branches.
223e47cc LB	225	return true;
	226	}
	227	return false;
	228	}
	229
	230	unsigned
	231	SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
	232	MachineBasicBlock *FBB,
	233	const SmallVectorImpl<MachineOperand> &Cond,
	234	DebugLoc DL) const {
	235	assert(TBB && "InsertBranch must not be told to insert a fallthrough");
	236	assert((Cond.size() == 1 \|\| Cond.size() == 0) &&
	237	"Sparc branch conditions should have one component!");
	238
	239	if (Cond.empty()) {
	240	assert(!FBB && "Unconditional branch with multiple successors!");
	241	BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
	242	return 1;
	243	}
	244
1a4d82fc	245	// Conditional branch
223e47cc LB	246	unsigned CC = Cond[0].getImm();
	247
	248	if (IsIntegerCC(CC))
	249	BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
	250	else
	251	BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
	252	if (!FBB)
	253	return 1;
	254
	255	BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
	256	return 2;
	257	}
	258
	259	unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
	260	{
	261	MachineBasicBlock::iterator I = MBB.end();
	262	unsigned Count = 0;
	263	while (I != MBB.begin()) {
	264	--I;
	265
	266	if (I->isDebugValue())
	267	continue;
	268
	269	if (I->getOpcode() != SP::BA
	270	&& I->getOpcode() != SP::BCOND
	271	&& I->getOpcode() != SP::FBCOND)
	272	break; // Not a branch
	273
	274	I->eraseFromParent();
	275	I = MBB.end();
	276	++Count;
	277	}
	278	return Count;
	279	}
	280
	281	void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
	282	MachineBasicBlock::iterator I, DebugLoc DL,
	283	unsigned DestReg, unsigned SrcReg,
	284	bool KillSrc) const {
1a4d82fc JJ	285	unsigned numSubRegs = 0;
	286	unsigned movOpc = 0;
	287	const unsigned *subRegIdx = nullptr;
	288
	289	const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
	290	const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };
	291	const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd,
	292	SP::sub_odd64_then_sub_even,
	293	SP::sub_odd64_then_sub_odd };
	294
223e47cc LB	295	if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
	296	BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
	297	.addReg(SrcReg, getKillRegState(KillSrc));
	298	else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
	299	BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
	300	.addReg(SrcReg, getKillRegState(KillSrc));
1a4d82fc JJ	301	else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
	302	if (Subtarget.isV9()) {
	303	BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
	304	.addReg(SrcReg, getKillRegState(KillSrc));
	305	} else {
	306	// Use two FMOVS instructions.
	307	subRegIdx = DFP_FP_SubRegsIdx;
	308	numSubRegs = 2;
	309	movOpc = SP::FMOVS;
	310	}
	311	} else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
	312	if (Subtarget.isV9()) {
	313	if (Subtarget.hasHardQuad()) {
	314	BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
	315	.addReg(SrcReg, getKillRegState(KillSrc));
	316	} else {
	317	// Use two FMOVD instructions.
	318	subRegIdx = QFP_DFP_SubRegsIdx;
	319	numSubRegs = 2;
	320	movOpc = SP::FMOVD;
	321	}
	322	} else {
	323	// Use four FMOVS instructions.
	324	subRegIdx = QFP_FP_SubRegsIdx;
	325	numSubRegs = 4;
	326	movOpc = SP::FMOVS;
	327	}
	328	} else
223e47cc	329	llvm_unreachable("Impossible reg-to-reg copy");
1a4d82fc JJ	330
	331	if (numSubRegs == 0 \|\| subRegIdx == nullptr \|\| movOpc == 0)
	332	return;
	333
	334	const TargetRegisterInfo *TRI = &getRegisterInfo();
	335	MachineInstr *MovMI = nullptr;
	336
	337	for (unsigned i = 0; i != numSubRegs; ++i) {
	338	unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
	339	unsigned Src = TRI->getSubReg(SrcReg, subRegIdx[i]);
	340	assert(Dst && Src && "Bad sub-register");
	341
	342	MovMI = BuildMI(MBB, I, DL, get(movOpc), Dst).addReg(Src);
	343	}
	344	// Add implicit super-register defs and kills to the last MovMI.
	345	MovMI->addRegisterDefined(DestReg, TRI);
	346	if (KillSrc)
	347	MovMI->addRegisterKilled(SrcReg, TRI);
223e47cc LB	348	}
	349
	350	void SparcInstrInfo::
	351	storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
	352	unsigned SrcReg, bool isKill, int FI,
	353	const TargetRegisterClass *RC,
	354	const TargetRegisterInfo *TRI) const {
	355	DebugLoc DL;
	356	if (I != MBB.end()) DL = I->getDebugLoc();
	357
1a4d82fc JJ	358	MachineFunction *MF = MBB.getParent();
	359	const MachineFrameInfo &MFI = *MF->getFrameInfo();
	360	MachineMemOperand *MMO =
	361	MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
	362	MachineMemOperand::MOStore,
	363	MFI.getObjectSize(FI),
	364	MFI.getObjectAlignment(FI));
	365
223e47cc	366	// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
1a4d82fc JJ	367	if (RC == &SP::I64RegsRegClass)
	368	BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
	369	.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
	370	else if (RC == &SP::IntRegsRegClass)
223e47cc	371	BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
1a4d82fc	372	.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
223e47cc LB	373	else if (RC == &SP::FPRegsRegClass)
223e47cc LB	374	BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
1a4d82fc JJ	375	.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
1a4d82fc JJ	376	else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
223e47cc	377	BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
1a4d82fc JJ	378	.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
	379	else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
	380	// Use STQFri irrespective of its legality. If STQ is not legal, it will be
	381	// lowered into two STDs in eliminateFrameIndex.
	382	BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)
	383	.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
223e47cc LB	384	else
	385	llvm_unreachable("Can't store this register to stack slot");
	386	}
	387
	388	void SparcInstrInfo::
	389	loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
	390	unsigned DestReg, int FI,
	391	const TargetRegisterClass *RC,
	392	const TargetRegisterInfo *TRI) const {
	393	DebugLoc DL;
	394	if (I != MBB.end()) DL = I->getDebugLoc();
	395
1a4d82fc JJ	396	MachineFunction *MF = MBB.getParent();
	397	const MachineFrameInfo &MFI = *MF->getFrameInfo();
	398	MachineMemOperand *MMO =
	399	MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
	400	MachineMemOperand::MOLoad,
	401	MFI.getObjectSize(FI),
	402	MFI.getObjectAlignment(FI));
	403
	404	if (RC == &SP::I64RegsRegClass)
	405	BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0)
	406	.addMemOperand(MMO);
	407	else if (RC == &SP::IntRegsRegClass)
	408	BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0)
	409	.addMemOperand(MMO);
223e47cc	410	else if (RC == &SP::FPRegsRegClass)
1a4d82fc JJ	411	BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
	412	.addMemOperand(MMO);
	413	else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
	414	BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0)
	415	.addMemOperand(MMO);
	416	else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
	417	// Use LDQFri irrespective of its legality. If LDQ is not legal, it will be
	418	// lowered into two LDDs in eliminateFrameIndex.
	419	BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
	420	.addMemOperand(MMO);
223e47cc LB	421	else
	422	llvm_unreachable("Can't load this register from stack slot");
	423	}
	424
	425	unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
	426	{
	427	SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
	428	unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg();
	429	if (GlobalBaseReg != 0)
	430	return GlobalBaseReg;
	431
	432	// Insert the set of GlobalBaseReg into the first MBB of the function
	433	MachineBasicBlock &FirstMBB = MF->front();
	434	MachineBasicBlock::iterator MBBI = FirstMBB.begin();
	435	MachineRegisterInfo &RegInfo = MF->getRegInfo();
	436
1a4d82fc JJ	437	const TargetRegisterClass *PtrRC =
	438	Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
	439	GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
223e47cc LB	440
	441	DebugLoc dl;
	442
	443	BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
	444	SparcFI->setGlobalBaseReg(GlobalBaseReg);
	445	return GlobalBaseReg;
	446	}