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1 | //===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===// |
2 | // | |
3 | // The LLVM Compiler Infrastructure | |
4 | // | |
5 | // This file is distributed under the University of Illinois Open Source | |
6 | // License. See LICENSE.TXT for details. | |
7 | // | |
8 | //===----------------------------------------------------------------------===// | |
9 | // | |
10 | // This file provides X86 specific target descriptions. | |
11 | // | |
12 | //===----------------------------------------------------------------------===// | |
13 | ||
1a4d82fc JJ |
14 | #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H |
15 | #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H | |
223e47cc LB |
16 | |
17 | #include "llvm/Support/DataTypes.h" | |
18 | #include <string> | |
19 | ||
20 | namespace llvm { | |
21 | class MCAsmBackend; | |
22 | class MCCodeEmitter; | |
23 | class MCContext; | |
24 | class MCInstrInfo; | |
25 | class MCObjectWriter; | |
26 | class MCRegisterInfo; | |
27 | class MCSubtargetInfo; | |
1a4d82fc JJ |
28 | class MCRelocationInfo; |
29 | class MCStreamer; | |
223e47cc | 30 | class Target; |
1a4d82fc | 31 | class Triple; |
223e47cc LB |
32 | class StringRef; |
33 | class raw_ostream; | |
34 | ||
35 | extern Target TheX86_32Target, TheX86_64Target; | |
36 | ||
37 | /// DWARFFlavour - Flavour of dwarf regnumbers | |
38 | /// | |
39 | namespace DWARFFlavour { | |
40 | enum { | |
41 | X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2 | |
42 | }; | |
85aaf69f SL |
43 | } |
44 | ||
223e47cc LB |
45 | /// N86 namespace - Native X86 register numbers |
46 | /// | |
47 | namespace N86 { | |
48 | enum { | |
49 | EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 | |
50 | }; | |
51 | } | |
52 | ||
53 | namespace X86_MC { | |
54 | std::string ParseX86Triple(StringRef TT); | |
55 | ||
56 | /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in | |
57 | /// the specified arguments. If we can't run cpuid on the host, return true. | |
58 | bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX, | |
59 | unsigned *rEBX, unsigned *rECX, unsigned *rEDX); | |
60 | /// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return | |
61 | /// the 4 values in the specified arguments. If we can't run cpuid on the | |
62 | /// host, return true. | |
63 | bool GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX, | |
64 | unsigned *rEBX, unsigned *rECX, unsigned *rEDX); | |
65 | ||
66 | void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model); | |
67 | ||
1a4d82fc | 68 | unsigned getDwarfRegFlavour(Triple TT, bool isEH); |
223e47cc | 69 | |
223e47cc LB |
70 | void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI); |
71 | ||
72 | /// createX86MCSubtargetInfo - Create a X86 MCSubtargetInfo instance. | |
73 | /// This is exposed so Asm parser, etc. do not need to go through | |
74 | /// TargetRegistry. | |
75 | MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, | |
76 | StringRef FS); | |
77 | } | |
78 | ||
79 | MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, | |
80 | const MCRegisterInfo &MRI, | |
81 | const MCSubtargetInfo &STI, | |
82 | MCContext &Ctx); | |
83 | ||
1a4d82fc JJ |
84 | MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, |
85 | StringRef TT, StringRef CPU); | |
86 | MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, | |
87 | StringRef TT, StringRef CPU); | |
88 | ||
89 | /// createX86WinCOFFStreamer - Construct an X86 Windows COFF machine code | |
90 | /// streamer which will generate PE/COFF format object files. | |
91 | /// | |
92 | /// Takes ownership of \p AB and \p CE. | |
93 | MCStreamer *createX86WinCOFFStreamer(MCContext &C, MCAsmBackend &AB, | |
94 | MCCodeEmitter *CE, raw_ostream &OS, | |
95 | bool RelaxAll); | |
223e47cc LB |
96 | |
97 | /// createX86MachObjectWriter - Construct an X86 Mach-O object writer. | |
98 | MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS, | |
99 | bool Is64Bit, | |
100 | uint32_t CPUType, | |
101 | uint32_t CPUSubtype); | |
102 | ||
103 | /// createX86ELFObjectWriter - Construct an X86 ELF object writer. | |
104 | MCObjectWriter *createX86ELFObjectWriter(raw_ostream &OS, | |
970d7e83 LB |
105 | bool IsELF64, |
106 | uint8_t OSABI, | |
107 | uint16_t EMachine); | |
223e47cc LB |
108 | /// createX86WinCOFFObjectWriter - Construct an X86 Win COFF object writer. |
109 | MCObjectWriter *createX86WinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit); | |
1a4d82fc JJ |
110 | |
111 | /// createX86_64MachORelocationInfo - Construct X86-64 Mach-O relocation info. | |
112 | MCRelocationInfo *createX86_64MachORelocationInfo(MCContext &Ctx); | |
113 | ||
114 | /// createX86_64ELFORelocationInfo - Construct X86-64 ELF relocation info. | |
115 | MCRelocationInfo *createX86_64ELFRelocationInfo(MCContext &Ctx); | |
223e47cc LB |
116 | } // End llvm namespace |
117 | ||
118 | ||
119 | // Defines symbolic names for X86 registers. This defines a mapping from | |
120 | // register name to register number. | |
121 | // | |
122 | #define GET_REGINFO_ENUM | |
123 | #include "X86GenRegisterInfo.inc" | |
124 | ||
125 | // Defines symbolic names for the X86 instructions. | |
126 | // | |
127 | #define GET_INSTRINFO_ENUM | |
128 | #include "X86GenInstrInfo.inc" | |
129 | ||
130 | #define GET_SUBTARGETINFO_ENUM | |
131 | #include "X86GenSubtargetInfo.inc" | |
132 | ||
133 | #endif |