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1 | //===-- X86Instr3DNow.td - The 3DNow! Instruction Set ------*- tablegen -*-===// |
2 | // | |
3 | // The LLVM Compiler Infrastructure | |
4 | // | |
5 | // This file is distributed under the University of Illinois Open Source | |
6 | // License. See LICENSE.TXT for details. | |
7 | // | |
8 | //===----------------------------------------------------------------------===// | |
9 | // | |
10 | // This file describes the 3DNow! instruction set, which extends MMX to support | |
11 | // floating point and also adds a few more random instructions for good measure. | |
12 | // | |
13 | //===----------------------------------------------------------------------===// | |
14 | ||
15 | class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pat> | |
16 | : I<o, F, outs, ins, asm, pat>, TB, Requires<[Has3DNow]> { | |
17 | } | |
18 | ||
19 | class I3DNow_binop<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat> | |
20 | : I3DNow<o, F, (outs VR64:$dst), ins, | |
21 | !strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), pat>, | |
22 | Has3DNow0F0FOpcode { | |
23 | // FIXME: The disassembler doesn't support Has3DNow0F0FOpcode yet. | |
24 | let isAsmParserOnly = 1; | |
25 | let Constraints = "$src1 = $dst"; | |
26 | } | |
27 | ||
28 | class I3DNow_conv<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat> | |
29 | : I3DNow<o, F, (outs VR64:$dst), ins, | |
30 | !strconcat(Mnemonic, "\t{$src, $dst|$dst, $src}"), pat>, | |
31 | Has3DNow0F0FOpcode { | |
32 | // FIXME: The disassembler doesn't support Has3DNow0F0FOpcode yet. | |
33 | let isAsmParserOnly = 1; | |
34 | } | |
35 | ||
36 | multiclass I3DNow_binop_rm<bits<8> opc, string Mn> { | |
37 | def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, []>; | |
38 | def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn, []>; | |
39 | } | |
40 | ||
41 | multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn, string Ver = ""> { | |
42 | def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, | |
43 | [(set VR64:$dst, (!cast<Intrinsic>( | |
44 | !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, VR64:$src2))]>; | |
45 | def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn, | |
46 | [(set VR64:$dst, (!cast<Intrinsic>( | |
47 | !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, | |
48 | (bitconvert (load_mmx addr:$src2))))]>; | |
49 | } | |
50 | ||
51 | multiclass I3DNow_conv_rm<bits<8> opc, string Mn> { | |
52 | def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src1), Mn, []>; | |
53 | def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src1), Mn, []>; | |
54 | } | |
55 | ||
56 | multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn, string Ver = ""> { | |
57 | def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn, | |
58 | [(set VR64:$dst, (!cast<Intrinsic>( | |
59 | !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src))]>; | |
60 | def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src), Mn, | |
61 | [(set VR64:$dst, (!cast<Intrinsic>( | |
62 | !strconcat("int_x86_3dnow", Ver, "_", Mn)) | |
63 | (bitconvert (load_mmx addr:$src))))]>; | |
64 | } | |
65 | ||
66 | defm PAVGUSB : I3DNow_binop_rm_int<0xBF, "pavgusb">; | |
67 | defm PF2ID : I3DNow_conv_rm_int<0x1D, "pf2id">; | |
68 | defm PFACC : I3DNow_binop_rm_int<0xAE, "pfacc">; | |
69 | defm PFADD : I3DNow_binop_rm_int<0x9E, "pfadd">; | |
70 | defm PFCMPEQ : I3DNow_binop_rm_int<0xB0, "pfcmpeq">; | |
71 | defm PFCMPGE : I3DNow_binop_rm_int<0x90, "pfcmpge">; | |
72 | defm PFCMPGT : I3DNow_binop_rm_int<0xA0, "pfcmpgt">; | |
73 | defm PFMAX : I3DNow_binop_rm_int<0xA4, "pfmax">; | |
74 | defm PFMIN : I3DNow_binop_rm_int<0x94, "pfmin">; | |
75 | defm PFMUL : I3DNow_binop_rm_int<0xB4, "pfmul">; | |
76 | defm PFRCP : I3DNow_conv_rm_int<0x96, "pfrcp">; | |
77 | defm PFRCPIT1 : I3DNow_binop_rm_int<0xA6, "pfrcpit1">; | |
78 | defm PFRCPIT2 : I3DNow_binop_rm_int<0xB6, "pfrcpit2">; | |
79 | defm PFRSQIT1 : I3DNow_binop_rm_int<0xA7, "pfrsqit1">; | |
80 | defm PFRSQRT : I3DNow_conv_rm_int<0x97, "pfrsqrt">; | |
81 | defm PFSUB : I3DNow_binop_rm_int<0x9A, "pfsub">; | |
82 | defm PFSUBR : I3DNow_binop_rm_int<0xAA, "pfsubr">; | |
83 | defm PI2FD : I3DNow_conv_rm_int<0x0D, "pi2fd">; | |
84 | defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw">; | |
85 | ||
86 | ||
1a4d82fc JJ |
87 | def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms", |
88 | [(int_x86_mmx_femms)]>; | |
223e47cc | 89 | |
1a4d82fc JJ |
90 | def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr), |
91 | "prefetch\t$addr", | |
92 | [(prefetch addr:$addr, (i32 0), imm, (i32 1))]>; | |
223e47cc | 93 | |
1a4d82fc JJ |
94 | def PREFETCHW : I<0x0D, MRM1m, (outs), (ins i8mem:$addr), "prefetchw\t$addr", |
95 | [(prefetch addr:$addr, (i32 1), (i32 3), (i32 1))]>, TB, | |
96 | Requires<[HasPrefetchW]>; | |
223e47cc LB |
97 | |
98 | // "3DNowA" instructions | |
99 | defm PF2IW : I3DNow_conv_rm_int<0x1C, "pf2iw", "a">; | |
100 | defm PI2FW : I3DNow_conv_rm_int<0x0C, "pi2fw", "a">; | |
101 | defm PFNACC : I3DNow_binop_rm_int<0x8A, "pfnacc", "a">; | |
102 | defm PFPNACC : I3DNow_binop_rm_int<0x8E, "pfpnacc", "a">; | |
103 | defm PSWAPD : I3DNow_conv_rm_int<0xBB, "pswapd", "a">; |