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1 | //===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===// |
2 | // | |
3 | // The LLVM Compiler Infrastructure | |
4 | // | |
5 | // This file is distributed under the University of Illinois Open Source | |
6 | // License. See LICENSE.TXT for details. | |
7 | // | |
8 | //===----------------------------------------------------------------------===// | |
9 | // | |
10 | // This file describes the X86 x87 FPU instruction set, defining the | |
11 | // instructions, and properties of the instructions which are needed for code | |
12 | // generation, machine code emission, and analysis. | |
13 | // | |
14 | //===----------------------------------------------------------------------===// | |
15 | ||
16 | //===----------------------------------------------------------------------===// | |
17 | // FPStack specific DAG Nodes. | |
18 | //===----------------------------------------------------------------------===// | |
19 | ||
85aaf69f | 20 | def SDTX86FpGet2 : SDTypeProfile<2, 0, [SDTCisVT<0, f80>, |
223e47cc LB |
21 | SDTCisVT<1, f80>]>; |
22 | def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>, | |
85aaf69f | 23 | SDTCisPtrTy<1>, |
223e47cc LB |
24 | SDTCisVT<2, OtherVT>]>; |
25 | def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>, | |
85aaf69f | 26 | SDTCisPtrTy<1>, |
223e47cc LB |
27 | SDTCisVT<2, OtherVT>]>; |
28 | def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>, | |
29 | SDTCisVT<2, OtherVT>]>; | |
30 | def SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; | |
31 | def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; | |
32 | ||
33 | def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; | |
34 | ||
35 | def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, | |
36 | [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; | |
37 | def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, | |
38 | [SDNPHasChain, SDNPInGlue, SDNPMayStore, | |
39 | SDNPMemOperand]>; | |
40 | def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, | |
41 | [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; | |
42 | def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild, | |
43 | [SDNPHasChain, SDNPOutGlue, SDNPMayLoad, | |
44 | SDNPMemOperand]>; | |
45 | def X86fp_stsw : SDNode<"X86ISD::FNSTSW16r", SDTX86Fnstsw>; | |
46 | def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem, | |
47 | [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; | |
48 | def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem, | |
49 | [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; | |
50 | def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem, | |
51 | [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; | |
52 | def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, | |
53 | [SDNPHasChain, SDNPMayStore, SDNPSideEffect, | |
54 | SDNPMemOperand]>; | |
55 | ||
56 | //===----------------------------------------------------------------------===// | |
57 | // FPStack pattern fragments | |
58 | //===----------------------------------------------------------------------===// | |
59 | ||
60 | def fpimm0 : PatLeaf<(fpimm), [{ | |
61 | return N->isExactlyValue(+0.0); | |
62 | }]>; | |
63 | ||
64 | def fpimmneg0 : PatLeaf<(fpimm), [{ | |
65 | return N->isExactlyValue(-0.0); | |
66 | }]>; | |
67 | ||
68 | def fpimm1 : PatLeaf<(fpimm), [{ | |
69 | return N->isExactlyValue(+1.0); | |
70 | }]>; | |
71 | ||
72 | def fpimmneg1 : PatLeaf<(fpimm), [{ | |
73 | return N->isExactlyValue(-1.0); | |
74 | }]>; | |
75 | ||
76 | // Some 'special' instructions | |
77 | let usesCustomInserter = 1 in { // Expanded after instruction selection. | |
78 | def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src), | |
79 | [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>; | |
80 | def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src), | |
81 | [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>; | |
82 | def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src), | |
83 | [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>; | |
84 | def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src), | |
85 | [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>; | |
86 | def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src), | |
87 | [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>; | |
88 | def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src), | |
89 | [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>; | |
90 | def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src), | |
91 | [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>; | |
92 | def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src), | |
93 | [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>; | |
94 | def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src), | |
95 | [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>; | |
96 | } | |
97 | ||
98 | // All FP Stack operations are represented with four instructions here. The | |
99 | // first three instructions, generated by the instruction selector, use "RFP32" | |
100 | // "RFP64" or "RFP80" registers: traditional register files to reference 32-bit, | |
85aaf69f | 101 | // 64-bit or 80-bit floating point values. These sizes apply to the values, |
223e47cc LB |
102 | // not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be |
103 | // copied to each other without losing information. These instructions are all | |
104 | // pseudo instructions and use the "_Fp" suffix. | |
105 | // In some cases there are additional variants with a mixture of different | |
106 | // register sizes. | |
107 | // The second instruction is defined with FPI, which is the actual instruction | |
108 | // emitted by the assembler. These use "RST" registers, although frequently | |
109 | // the actual register(s) used are implicit. These are always 80 bits. | |
85aaf69f | 110 | // The FP stackifier pass converts one to the other after register allocation |
223e47cc LB |
111 | // occurs. |
112 | // | |
113 | // Note that the FpI instruction should have instruction selection info (e.g. | |
114 | // a pattern) and the FPI instruction should have emission info (e.g. opcode | |
115 | // encoding and asm printing info). | |
116 | ||
223e47cc LB |
117 | // FpIf32, FpIf64 - Floating Point Pseudo Instruction template. |
118 | // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. | |
119 | // f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2. | |
120 | // f80 instructions cannot use SSE and use neither of these. | |
121 | class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> : | |
122 | FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>; | |
123 | class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> : | |
124 | FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>; | |
125 | ||
126 | // Factoring for arithmetic. | |
127 | multiclass FPBinary_rr<SDNode OpNode> { | |
128 | // Register op register -> register | |
129 | // These are separated out because they have no reversed form. | |
130 | def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP, | |
131 | [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>; | |
132 | def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP, | |
133 | [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>; | |
134 | def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP, | |
135 | [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>; | |
136 | } | |
137 | // The FopST0 series are not included here because of the irregularities | |
138 | // in where the 'r' goes in assembly output. | |
139 | // These instructions cannot address 80-bit memory. | |
140 | multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> { | |
141 | // ST(0) = ST(0) + [mem] | |
85aaf69f | 142 | def _Fp32m : FpIf32<(outs RFP32:$dst), |
223e47cc | 143 | (ins RFP32:$src1, f32mem:$src2), OneArgFPRW, |
85aaf69f | 144 | [(set RFP32:$dst, |
223e47cc | 145 | (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>; |
85aaf69f | 146 | def _Fp64m : FpIf64<(outs RFP64:$dst), |
223e47cc | 147 | (ins RFP64:$src1, f64mem:$src2), OneArgFPRW, |
85aaf69f | 148 | [(set RFP64:$dst, |
223e47cc | 149 | (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>; |
85aaf69f | 150 | def _Fp64m32: FpIf64<(outs RFP64:$dst), |
223e47cc | 151 | (ins RFP64:$src1, f32mem:$src2), OneArgFPRW, |
85aaf69f | 152 | [(set RFP64:$dst, |
223e47cc | 153 | (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2))))]>; |
85aaf69f | 154 | def _Fp80m32: FpI_<(outs RFP80:$dst), |
223e47cc | 155 | (ins RFP80:$src1, f32mem:$src2), OneArgFPRW, |
85aaf69f | 156 | [(set RFP80:$dst, |
223e47cc | 157 | (OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2))))]>; |
85aaf69f | 158 | def _Fp80m64: FpI_<(outs RFP80:$dst), |
223e47cc | 159 | (ins RFP80:$src1, f64mem:$src2), OneArgFPRW, |
85aaf69f | 160 | [(set RFP80:$dst, |
223e47cc | 161 | (OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2))))]>; |
85aaf69f SL |
162 | def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src), |
163 | !strconcat("f", asmstring, "{s}\t$src")> { | |
164 | let mayLoad = 1; | |
223e47cc | 165 | } |
85aaf69f SL |
166 | def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src), |
167 | !strconcat("f", asmstring, "{l}\t$src")> { | |
168 | let mayLoad = 1; | |
223e47cc LB |
169 | } |
170 | // ST(0) = ST(0) + [memint] | |
85aaf69f | 171 | def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), |
223e47cc LB |
172 | OneArgFPRW, |
173 | [(set RFP32:$dst, (OpNode RFP32:$src1, | |
174 | (X86fild addr:$src2, i16)))]>; | |
85aaf69f | 175 | def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), |
223e47cc LB |
176 | OneArgFPRW, |
177 | [(set RFP32:$dst, (OpNode RFP32:$src1, | |
178 | (X86fild addr:$src2, i32)))]>; | |
85aaf69f | 179 | def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), |
223e47cc LB |
180 | OneArgFPRW, |
181 | [(set RFP64:$dst, (OpNode RFP64:$src1, | |
182 | (X86fild addr:$src2, i16)))]>; | |
85aaf69f | 183 | def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), |
223e47cc LB |
184 | OneArgFPRW, |
185 | [(set RFP64:$dst, (OpNode RFP64:$src1, | |
186 | (X86fild addr:$src2, i32)))]>; | |
85aaf69f | 187 | def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), |
223e47cc LB |
188 | OneArgFPRW, |
189 | [(set RFP80:$dst, (OpNode RFP80:$src1, | |
190 | (X86fild addr:$src2, i16)))]>; | |
85aaf69f | 191 | def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), |
223e47cc LB |
192 | OneArgFPRW, |
193 | [(set RFP80:$dst, (OpNode RFP80:$src1, | |
194 | (X86fild addr:$src2, i32)))]>; | |
85aaf69f SL |
195 | def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src), |
196 | !strconcat("fi", asmstring, "{s}\t$src")> { | |
197 | let mayLoad = 1; | |
223e47cc | 198 | } |
85aaf69f SL |
199 | def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), |
200 | !strconcat("fi", asmstring, "{l}\t$src")> { | |
201 | let mayLoad = 1; | |
223e47cc LB |
202 | } |
203 | } | |
204 | ||
205 | let Defs = [FPSW] in { | |
1a4d82fc JJ |
206 | // FPBinary_rr just defines pseudo-instructions, no need to set a scheduling |
207 | // resources. | |
223e47cc LB |
208 | defm ADD : FPBinary_rr<fadd>; |
209 | defm SUB : FPBinary_rr<fsub>; | |
210 | defm MUL : FPBinary_rr<fmul>; | |
211 | defm DIV : FPBinary_rr<fdiv>; | |
1a4d82fc JJ |
212 | // Sets the scheduling resources for the actual NAME#_F<size>m defintions. |
213 | let SchedRW = [WriteFAddLd] in { | |
223e47cc LB |
214 | defm ADD : FPBinary<fadd, MRM0m, "add">; |
215 | defm SUB : FPBinary<fsub, MRM4m, "sub">; | |
216 | defm SUBR: FPBinary<fsub ,MRM5m, "subr">; | |
1a4d82fc JJ |
217 | } |
218 | let SchedRW = [WriteFMulLd] in { | |
223e47cc | 219 | defm MUL : FPBinary<fmul, MRM1m, "mul">; |
1a4d82fc JJ |
220 | } |
221 | let SchedRW = [WriteFDivLd] in { | |
223e47cc LB |
222 | defm DIV : FPBinary<fdiv, MRM6m, "div">; |
223 | defm DIVR: FPBinary<fdiv, MRM7m, "divr">; | |
224 | } | |
1a4d82fc | 225 | } |
223e47cc | 226 | |
1a4d82fc JJ |
227 | class FPST0rInst<Format fp, string asm> |
228 | : FPI<0xD8, fp, (outs), (ins RST:$op), asm>; | |
229 | class FPrST0Inst<Format fp, string asm> | |
230 | : FPI<0xDC, fp, (outs), (ins RST:$op), asm>; | |
231 | class FPrST0PInst<Format fp, string asm> | |
232 | : FPI<0xDE, fp, (outs), (ins RST:$op), asm>; | |
223e47cc LB |
233 | |
234 | // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion | |
235 | // of some of the 'reverse' forms of the fsub and fdiv instructions. As such, | |
236 | // we have to put some 'r's in and take them out of weird places. | |
1a4d82fc JJ |
237 | let SchedRW = [WriteFAdd] in { |
238 | def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t$op">; | |
239 | def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st(0), $op|$op, st(0)}">; | |
240 | def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t$op">; | |
241 | def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t$op">; | |
242 | def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st(0), $op|$op, st(0)}">; | |
243 | def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t$op">; | |
244 | def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t$op">; | |
245 | def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st(0), $op|$op, st(0)}">; | |
246 | def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t$op">; | |
247 | } // SchedRW | |
248 | let SchedRW = [WriteFMul] in { | |
249 | def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t$op">; | |
250 | def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st(0), $op|$op, st(0)}">; | |
251 | def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t$op">; | |
252 | } // SchedRW | |
253 | let SchedRW = [WriteFDiv] in { | |
254 | def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t$op">; | |
255 | def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st(0), $op|$op, st(0)}">; | |
256 | def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t$op">; | |
257 | def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t$op">; | |
258 | def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">; | |
259 | def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t$op">; | |
260 | } // SchedRW | |
261 | ||
262 | def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">; | |
263 | def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">; | |
223e47cc LB |
264 | |
265 | // Unary operations. | |
1a4d82fc | 266 | multiclass FPUnary<SDNode OpNode, Format fp, string asmstring> { |
223e47cc LB |
267 | def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW, |
268 | [(set RFP32:$dst, (OpNode RFP32:$src))]>; | |
269 | def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW, | |
270 | [(set RFP64:$dst, (OpNode RFP64:$src))]>; | |
271 | def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW, | |
272 | [(set RFP80:$dst, (OpNode RFP80:$src))]>; | |
1a4d82fc | 273 | def _F : FPI<0xD9, fp, (outs), (ins), asmstring>; |
223e47cc LB |
274 | } |
275 | ||
276 | let Defs = [FPSW] in { | |
1a4d82fc JJ |
277 | defm CHS : FPUnary<fneg, MRM_E0, "fchs">; |
278 | defm ABS : FPUnary<fabs, MRM_E1, "fabs">; | |
279 | let SchedRW = [WriteFSqrt] in { | |
280 | defm SQRT: FPUnary<fsqrt,MRM_FA, "fsqrt">; | |
281 | } | |
282 | defm SIN : FPUnary<fsin, MRM_FE, "fsin">; | |
283 | defm COS : FPUnary<fcos, MRM_FF, "fcos">; | |
223e47cc | 284 | |
85aaf69f | 285 | let hasSideEffects = 0 in { |
223e47cc LB |
286 | def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>; |
287 | def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>; | |
288 | def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>; | |
289 | } | |
1a4d82fc | 290 | def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">; |
223e47cc LB |
291 | } // Defs = [FPSW] |
292 | ||
293 | // Versions of FP instructions that take a single memory operand. Added for the | |
294 | // disassembler; remove as they are included with patterns elsewhere. | |
295 | def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">; | |
296 | def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">; | |
297 | ||
298 | def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">; | |
299 | def FSTENVm : FPI<0xD9, MRM6m, (outs f32mem:$dst), (ins), "fnstenv\t$dst">; | |
300 | ||
301 | def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">; | |
302 | def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">; | |
303 | ||
304 | def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">; | |
305 | def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; | |
306 | ||
307 | def FRSTORm : FPI<0xDD, MRM4m, (outs f32mem:$dst), (ins), "frstor\t$dst">; | |
308 | def FSAVEm : FPI<0xDD, MRM6m, (outs f32mem:$dst), (ins), "fnsave\t$dst">; | |
309 | def FNSTSWm : FPI<0xDD, MRM7m, (outs f32mem:$dst), (ins), "fnstsw\t$dst">; | |
310 | ||
311 | def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; | |
312 | def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; | |
313 | ||
314 | def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f32mem:$src), "fbld\t$src">; | |
315 | def FBSTPm : FPI<0xDF, MRM6m, (outs f32mem:$dst), (ins), "fbstp\t$dst">; | |
316 | ||
317 | // Floating point cmovs. | |
318 | class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : | |
319 | FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>; | |
320 | class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> : | |
321 | FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>; | |
322 | ||
323 | multiclass FPCMov<PatLeaf cc> { | |
324 | def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), | |
325 | CondMovFP, | |
326 | [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, | |
327 | cc, EFLAGS))]>; | |
328 | def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), | |
329 | CondMovFP, | |
330 | [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, | |
331 | cc, EFLAGS))]>; | |
332 | def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), | |
333 | CondMovFP, | |
334 | [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, | |
335 | cc, EFLAGS))]>, | |
336 | Requires<[HasCMov]>; | |
337 | } | |
338 | ||
339 | let Defs = [FPSW] in { | |
340 | let Uses = [EFLAGS], Constraints = "$src1 = $dst" in { | |
341 | defm CMOVB : FPCMov<X86_COND_B>; | |
342 | defm CMOVBE : FPCMov<X86_COND_BE>; | |
343 | defm CMOVE : FPCMov<X86_COND_E>; | |
344 | defm CMOVP : FPCMov<X86_COND_P>; | |
345 | defm CMOVNB : FPCMov<X86_COND_AE>; | |
346 | defm CMOVNBE: FPCMov<X86_COND_A>; | |
347 | defm CMOVNE : FPCMov<X86_COND_NE>; | |
348 | defm CMOVNP : FPCMov<X86_COND_NP>; | |
349 | } // Uses = [EFLAGS], Constraints = "$src1 = $dst" | |
350 | ||
351 | let Predicates = [HasCMov] in { | |
352 | // These are not factored because there's no clean way to pass DA/DB. | |
1a4d82fc JJ |
353 | def CMOVB_F : FPI<0xDA, MRM0r, (outs RST:$op), (ins), |
354 | "fcmovb\t{$op, %st(0)|st(0), $op}">; | |
355 | def CMOVBE_F : FPI<0xDA, MRM2r, (outs RST:$op), (ins), | |
356 | "fcmovbe\t{$op, %st(0)|st(0), $op}">; | |
357 | def CMOVE_F : FPI<0xDA, MRM1r, (outs RST:$op), (ins), | |
358 | "fcmove\t{$op, %st(0)|st(0), $op}">; | |
359 | def CMOVP_F : FPI<0xDA, MRM3r, (outs RST:$op), (ins), | |
360 | "fcmovu\t{$op, %st(0)|st(0), $op}">; | |
361 | def CMOVNB_F : FPI<0xDB, MRM0r, (outs RST:$op), (ins), | |
362 | "fcmovnb\t{$op, %st(0)|st(0), $op}">; | |
363 | def CMOVNBE_F: FPI<0xDB, MRM2r, (outs RST:$op), (ins), | |
364 | "fcmovnbe\t{$op, %st(0)|st(0), $op}">; | |
365 | def CMOVNE_F : FPI<0xDB, MRM1r, (outs RST:$op), (ins), | |
366 | "fcmovne\t{$op, %st(0)|st(0), $op}">; | |
367 | def CMOVNP_F : FPI<0xDB, MRM3r, (outs RST:$op), (ins), | |
368 | "fcmovnu\t{$op, %st(0)|st(0), $op}">; | |
223e47cc LB |
369 | } // Predicates = [HasCMov] |
370 | ||
371 | // Floating point loads & stores. | |
372 | let canFoldAsLoad = 1 in { | |
373 | def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, | |
374 | [(set RFP32:$dst, (loadf32 addr:$src))]>; | |
375 | let isReMaterializable = 1 in | |
376 | def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP, | |
377 | [(set RFP64:$dst, (loadf64 addr:$src))]>; | |
378 | def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP, | |
379 | [(set RFP80:$dst, (loadf80 addr:$src))]>; | |
380 | } | |
381 | def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP, | |
382 | [(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>; | |
383 | def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP, | |
384 | [(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>; | |
385 | def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP, | |
386 | [(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>; | |
387 | def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP, | |
388 | [(set RFP32:$dst, (X86fild addr:$src, i16))]>; | |
389 | def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP, | |
390 | [(set RFP32:$dst, (X86fild addr:$src, i32))]>; | |
391 | def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP, | |
392 | [(set RFP32:$dst, (X86fild addr:$src, i64))]>; | |
393 | def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP, | |
394 | [(set RFP64:$dst, (X86fild addr:$src, i16))]>; | |
395 | def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP, | |
396 | [(set RFP64:$dst, (X86fild addr:$src, i32))]>; | |
397 | def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP, | |
398 | [(set RFP64:$dst, (X86fild addr:$src, i64))]>; | |
399 | def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP, | |
400 | [(set RFP80:$dst, (X86fild addr:$src, i16))]>; | |
401 | def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP, | |
402 | [(set RFP80:$dst, (X86fild addr:$src, i32))]>; | |
403 | def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP, | |
404 | [(set RFP80:$dst, (X86fild addr:$src, i64))]>; | |
405 | ||
406 | def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, | |
407 | [(store RFP32:$src, addr:$op)]>; | |
408 | def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, | |
409 | [(truncstoref32 RFP64:$src, addr:$op)]>; | |
410 | def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, | |
411 | [(store RFP64:$src, addr:$op)]>; | |
412 | def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, | |
413 | [(truncstoref32 RFP80:$src, addr:$op)]>; | |
414 | def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, | |
415 | [(truncstoref64 RFP80:$src, addr:$op)]>; | |
416 | // FST does not support 80-bit memory target; FSTP must be used. | |
417 | ||
85aaf69f | 418 | let mayStore = 1, hasSideEffects = 0 in { |
223e47cc LB |
419 | def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>; |
420 | def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>; | |
421 | def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>; | |
422 | def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>; | |
423 | def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>; | |
424 | } | |
425 | def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP, | |
426 | [(store RFP80:$src, addr:$op)]>; | |
85aaf69f | 427 | let mayStore = 1, hasSideEffects = 0 in { |
223e47cc LB |
428 | def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>; |
429 | def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>; | |
430 | def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>; | |
431 | def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>; | |
432 | def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>; | |
433 | def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>; | |
434 | def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>; | |
435 | def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>; | |
436 | def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>; | |
437 | } | |
438 | ||
1a4d82fc | 439 | let mayLoad = 1, SchedRW = [WriteLoad] in { |
223e47cc LB |
440 | def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src", |
441 | IIC_FLD>; | |
442 | def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src", | |
443 | IIC_FLD>; | |
444 | def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src", | |
445 | IIC_FLD80>; | |
446 | def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src", | |
447 | IIC_FILD>; | |
448 | def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src", | |
449 | IIC_FILD>; | |
450 | def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src", | |
451 | IIC_FILD>; | |
452 | } | |
1a4d82fc | 453 | let mayStore = 1, SchedRW = [WriteStore] in { |
223e47cc LB |
454 | def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst", |
455 | IIC_FST>; | |
456 | def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst", | |
457 | IIC_FST>; | |
458 | def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst", | |
459 | IIC_FST>; | |
460 | def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst", | |
461 | IIC_FST>; | |
462 | def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst", | |
463 | IIC_FST80>; | |
464 | def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst", | |
465 | IIC_FIST>; | |
466 | def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst", | |
467 | IIC_FIST>; | |
468 | def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst", | |
469 | IIC_FIST>; | |
470 | def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst", | |
471 | IIC_FIST>; | |
472 | def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst", | |
473 | IIC_FIST>; | |
474 | } | |
475 | ||
476 | // FISTTP requires SSE3 even though it's a FPStack op. | |
477 | let Predicates = [HasSSE3] in { | |
478 | def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, | |
479 | [(X86fp_to_i16mem RFP32:$src, addr:$op)]>; | |
480 | def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, | |
481 | [(X86fp_to_i32mem RFP32:$src, addr:$op)]>; | |
482 | def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, | |
483 | [(X86fp_to_i64mem RFP32:$src, addr:$op)]>; | |
484 | def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, | |
485 | [(X86fp_to_i16mem RFP64:$src, addr:$op)]>; | |
486 | def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, | |
487 | [(X86fp_to_i32mem RFP64:$src, addr:$op)]>; | |
488 | def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, | |
489 | [(X86fp_to_i64mem RFP64:$src, addr:$op)]>; | |
490 | def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, | |
491 | [(X86fp_to_i16mem RFP80:$src, addr:$op)]>; | |
492 | def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, | |
493 | [(X86fp_to_i32mem RFP80:$src, addr:$op)]>; | |
494 | def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, | |
495 | [(X86fp_to_i64mem RFP80:$src, addr:$op)]>; | |
496 | } // Predicates = [HasSSE3] | |
497 | ||
1a4d82fc | 498 | let mayStore = 1, SchedRW = [WriteStore] in { |
223e47cc LB |
499 | def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst", |
500 | IIC_FST>; | |
501 | def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst", | |
502 | IIC_FST>; | |
85aaf69f | 503 | def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), |
223e47cc LB |
504 | "fisttp{ll}\t$dst", IIC_FST>; |
505 | } | |
506 | ||
507 | // FP Stack manipulation instructions. | |
1a4d82fc JJ |
508 | let SchedRW = [WriteMove] in { |
509 | def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RST:$op), "fld\t$op", IIC_FLD>; | |
510 | def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RST:$op), "fst\t$op", IIC_FST>; | |
511 | def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RST:$op), "fstp\t$op", IIC_FST>; | |
512 | def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RST:$op), "fxch\t$op", IIC_FXCH>; | |
513 | } | |
223e47cc LB |
514 | |
515 | // Floating point constant loads. | |
516 | let isReMaterializable = 1 in { | |
517 | def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, | |
518 | [(set RFP32:$dst, fpimm0)]>; | |
519 | def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP, | |
520 | [(set RFP32:$dst, fpimm1)]>; | |
521 | def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, | |
522 | [(set RFP64:$dst, fpimm0)]>; | |
523 | def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP, | |
524 | [(set RFP64:$dst, fpimm1)]>; | |
525 | def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, | |
526 | [(set RFP80:$dst, fpimm0)]>; | |
527 | def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP, | |
528 | [(set RFP80:$dst, fpimm1)]>; | |
529 | } | |
530 | ||
1a4d82fc JJ |
531 | let SchedRW = [WriteZero] in { |
532 | def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz", IIC_FLDZ>; | |
533 | def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1", IIC_FIST>; | |
534 | } | |
223e47cc LB |
535 | |
536 | // Floating point compares. | |
1a4d82fc | 537 | let SchedRW = [WriteFAdd] in { |
223e47cc LB |
538 | def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, |
539 | [(set FPSW, (trunc (X86cmp RFP32:$lhs, RFP32:$rhs)))]>; | |
540 | def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, | |
541 | [(set FPSW, (trunc (X86cmp RFP64:$lhs, RFP64:$rhs)))]>; | |
542 | def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, | |
543 | [(set FPSW, (trunc (X86cmp RFP80:$lhs, RFP80:$rhs)))]>; | |
1a4d82fc | 544 | } // SchedRW |
223e47cc LB |
545 | } // Defs = [FPSW] |
546 | ||
1a4d82fc | 547 | let SchedRW = [WriteFAdd] in { |
223e47cc LB |
548 | // CC = ST(0) cmp ST(i) |
549 | let Defs = [EFLAGS, FPSW] in { | |
550 | def UCOM_FpIr32: FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP, | |
551 | [(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>; | |
552 | def UCOM_FpIr64: FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP, | |
553 | [(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>; | |
554 | def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP, | |
555 | [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>; | |
556 | } | |
557 | ||
558 | let Defs = [FPSW], Uses = [ST0] in { | |
1a4d82fc JJ |
559 | def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i) |
560 | (outs), (ins RST:$reg), "fucom\t$reg", IIC_FUCOM>; | |
561 | def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop | |
562 | (outs), (ins RST:$reg), "fucomp\t$reg", IIC_FUCOM>; | |
563 | def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop | |
564 | (outs), (ins), "fucompp", IIC_FUCOM>; | |
223e47cc LB |
565 | } |
566 | ||
567 | let Defs = [EFLAGS, FPSW], Uses = [ST0] in { | |
1a4d82fc JJ |
568 | def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i) |
569 | (outs), (ins RST:$reg), "fucomi\t$reg", IIC_FUCOMI>; | |
570 | def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop | |
571 | (outs), (ins RST:$reg), "fucompi\t$reg", IIC_FUCOMI>; | |
223e47cc LB |
572 | } |
573 | ||
574 | let Defs = [EFLAGS, FPSW] in { | |
1a4d82fc JJ |
575 | def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RST:$reg), |
576 | "fcomi\t$reg", IIC_FCOMI>; | |
577 | def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RST:$reg), | |
578 | "fcompi\t$reg", IIC_FCOMI>; | |
223e47cc | 579 | } |
1a4d82fc | 580 | } // SchedRW |
223e47cc LB |
581 | |
582 | // Floating point flag ops. | |
1a4d82fc | 583 | let SchedRW = [WriteALU] in { |
223e47cc | 584 | let Defs = [AX], Uses = [FPSW] in |
1a4d82fc JJ |
585 | def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags |
586 | (outs), (ins), "fnstsw\t{%ax|ax}", | |
587 | [(set AX, (X86fp_stsw FPSW))], IIC_FNSTSW>; | |
223e47cc LB |
588 | |
589 | def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world | |
590 | (outs), (ins i16mem:$dst), "fnstcw\t$dst", | |
591 | [(X86fp_cwd_get16 addr:$dst)], IIC_FNSTCW>; | |
1a4d82fc | 592 | } // SchedRW |
223e47cc LB |
593 | let mayLoad = 1 in |
594 | def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] | |
1a4d82fc JJ |
595 | (outs), (ins i16mem:$dst), "fldcw\t$dst", [], IIC_FLDCW>, |
596 | Sched<[WriteLoad]>; | |
223e47cc LB |
597 | |
598 | // FPU control instructions | |
1a4d82fc | 599 | let SchedRW = [WriteMicrocoded] in { |
223e47cc | 600 | let Defs = [FPSW] in |
1a4d82fc JJ |
601 | def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", [], IIC_FNINIT>; |
602 | def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg), | |
603 | "ffree\t$reg", IIC_FFREE>; | |
223e47cc LB |
604 | // Clear exceptions |
605 | ||
606 | let Defs = [FPSW] in | |
1a4d82fc JJ |
607 | def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", [], IIC_FNCLEX>; |
608 | } // SchedRW | |
223e47cc LB |
609 | |
610 | // Operandless floating-point instructions for the disassembler. | |
1a4d82fc | 611 | let SchedRW = [WriteMicrocoded] in { |
223e47cc LB |
612 | def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", [], IIC_WAIT>; |
613 | ||
1a4d82fc JJ |
614 | def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", [], IIC_FNOP>; |
615 | def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", [], IIC_FXAM>; | |
616 | def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", [], IIC_FLDL>; | |
617 | def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", [], IIC_FLDL>; | |
618 | def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", [], IIC_FLDL>; | |
619 | def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", [], IIC_FLDL>; | |
620 | def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", [], IIC_FLDL>; | |
621 | def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", [], IIC_F2XM1>; | |
622 | def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", [], IIC_FYL2X>; | |
623 | def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", [], IIC_FPTAN>; | |
624 | def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", [], IIC_FPATAN>; | |
625 | def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", [], IIC_FXTRACT>; | |
626 | def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", [], IIC_FPREM1>; | |
627 | def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", [], IIC_FPSTP>; | |
628 | def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", [], IIC_FPSTP>; | |
629 | def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", [], IIC_FPREM>; | |
630 | def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", [], IIC_FYL2XP1>; | |
631 | def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", [], IIC_FSINCOS>; | |
632 | def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", [], IIC_FRNDINT>; | |
633 | def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", [], IIC_FSCALE>; | |
634 | def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", [], IIC_FCOMPP>; | |
223e47cc LB |
635 | |
636 | def FXSAVE : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins), | |
637 | "fxsave\t$dst", [], IIC_FXSAVE>, TB; | |
1a4d82fc | 638 | def FXSAVE64 : RI<0xAE, MRM0m, (outs opaque512mem:$dst), (ins), |
85aaf69f | 639 | "fxsave{q|64}\t$dst", [], IIC_FXSAVE>, TB, |
1a4d82fc | 640 | Requires<[In64BitMode]>; |
223e47cc LB |
641 | def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaque512mem:$src), |
642 | "fxrstor\t$src", [], IIC_FXRSTOR>, TB; | |
1a4d82fc JJ |
643 | def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaque512mem:$src), |
644 | "fxrstor{q|64}\t$src", [], IIC_FXRSTOR>, TB, | |
223e47cc | 645 | Requires<[In64BitMode]>; |
1a4d82fc | 646 | } // SchedRW |
223e47cc LB |
647 | |
648 | //===----------------------------------------------------------------------===// | |
649 | // Non-Instruction Patterns | |
650 | //===----------------------------------------------------------------------===// | |
651 | ||
652 | // Required for RET of f32 / f64 / f80 values. | |
653 | def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>; | |
654 | def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>; | |
655 | def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>; | |
656 | ||
657 | // Required for CALL which return f32 / f64 / f80 values. | |
658 | def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>; | |
85aaf69f | 659 | def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, |
223e47cc LB |
660 | RFP64:$src)>; |
661 | def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>; | |
85aaf69f | 662 | def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, |
223e47cc | 663 | RFP80:$src)>; |
85aaf69f | 664 | def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, |
223e47cc LB |
665 | RFP80:$src)>; |
666 | def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, | |
667 | RFP80:$src)>; | |
668 | ||
669 | // Floating point constant -0.0 and -1.0 | |
670 | def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>; | |
671 | def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>; | |
672 | def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>; | |
673 | def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>; | |
674 | def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>; | |
675 | def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>; | |
676 | ||
677 | // Used to conv. i64 to f64 since there isn't a SSE version. | |
678 | def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>; | |
679 | ||
680 | // FP extensions map onto simple pseudo-value conversions if they are to/from | |
681 | // the FP stack. | |
682 | def : Pat<(f64 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>, | |
683 | Requires<[FPStackf32]>; | |
684 | def : Pat<(f80 (fextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>, | |
685 | Requires<[FPStackf32]>; | |
686 | def : Pat<(f80 (fextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>, | |
687 | Requires<[FPStackf64]>; | |
688 | ||
689 | // FP truncations map onto simple pseudo-value conversions if they are to/from | |
690 | // the FP stack. We have validated that only value-preserving truncations make | |
691 | // it through isel. | |
692 | def : Pat<(f32 (fround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>, | |
693 | Requires<[FPStackf32]>; | |
694 | def : Pat<(f32 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>, | |
695 | Requires<[FPStackf32]>; | |
696 | def : Pat<(f64 (fround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>, | |
697 | Requires<[FPStackf64]>; |