[rustc.git] / src / llvm / lib / Target / X86 / X86InstrSGX.td

//===-- X86InstrSGX.td - SGX Instruction Set Extension -----*- tablegen -*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the instructions that make up the Intel SGX instruction
// set.
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// SGX instructions

// ENCLS - Execute an Enclave System Function of Specified Leaf Number
def ENCLS : I<0x01, MRM_CF, (outs), (ins),
             "encls", []>, TB, Requires<[HasSGX]>;

// ENCLU - Execute an Enclave User Function of Specified Leaf Number
def ENCLU : I<0x01, MRM_D7, (outs), (ins),
             "enclu", []>, TB, Requires<[HasSGX]>;
Commit	Line	Data
1a4d82fc JJ	1	//===-- X86InstrSGX.td - SGX Instruction Set Extension ------ tablegen --===//
	2	//
	3	// The LLVM Compiler Infrastructure
	4	//
	5	// This file is distributed under the University of Illinois Open Source
	6	// License. See LICENSE.TXT for details.
	7	//
	8	//===----------------------------------------------------------------------===//
	9	//
	10	// This file describes the instructions that make up the Intel SGX instruction
	11	// set.
	12	//
	13	//===----------------------------------------------------------------------===//
	14
	15	//===----------------------------------------------------------------------===//
	16	// SGX instructions
	17
	18	// ENCLS - Execute an Enclave System Function of Specified Leaf Number
	19	def ENCLS : I<0x01, MRM_CF, (outs), (ins),
	20	"encls", []>, TB, Requires<[HasSGX]>;
	21
	22	// ENCLU - Execute an Enclave User Function of Specified Leaf Number
	23	def ENCLU : I<0x01, MRM_D7, (outs), (ins),
	24	"enclu", []>, TB, Requires<[HasSGX]>;