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Commit | Line | Data |
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1a4d82fc JJ |
1 | # These spawn another process so they're rather expensive. Not many. |
2 | ||
3 | # LDR/STR: undefined if option field is 10x or 00x. | |
4 | # RUN: echo "0x00 0x08 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s | |
5 | # RUN: echo "0x00 0x88 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s | |
6 | ||
7 | # Instructions notionally in the add/sub (extended register) sheet, but with | |
8 | # invalid shift amount or "opt" field. | |
9 | # RUN: echo "0x00 0x10 0xa0 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s | |
10 | # RUN: echo "0x00 0x10 0x60 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s | |
11 | # RUN: echo "0x00 0x14 0x20 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s | |
12 | ||
13 | # MOVK with sf == 0 and hw<1> == 1 is unallocated. | |
14 | # RUN: echo "0x00 0x00 0xc0 0x72" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s | |
15 | ||
16 | # ADD/SUB (shifted register) are reserved if shift == '11' or sf == '0' and imm6<5> == '1'. | |
17 | # RUN: echo "0x00 0x00 0xc0 0xeb" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s | |
18 | # RUN: echo "0x00 0x80 0x80 0x6b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s | |
19 | ||
20 | # UBFM is undefined when s == 0 and imms<5> or immr<5> is 1. | |
21 | # RUN: echo "0x00 0x80 0x00 0x53" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s | |
22 | ||
23 | # EXT on vectors of i8 must have imm<3> = 0. | |
24 | # RUN: echo "0x00 0x40 0x00 0x2e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s | |
25 | ||
26 | # SCVTF on fixed point W-registers is undefined if scale<5> == 0. | |
27 | # Same with FCVTZS and FCVTZU. | |
28 | # RUN: echo "0x00 0x00 0x02 0x1e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s | |
29 | # RUN: echo "0x00 0x00 0x18 0x1e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s | |
30 | ||
31 | # CHECK: invalid instruction encoding |