[rustc.git] / src / llvm / test / MC / Disassembler / ARM / invalid-because-armv7.txt

# RUN: not llvm-mc -disassemble -triple armv7 -show-encoding < %s 2>&1 | FileCheck %s

# This file is checking encodings that are valid on some triples, but not on the
# ARMv7 triple, probably because the relevant instruction is v8, though there
# could be other reasons.

# Would be vcvtt.f64.f16 d3, s1
[0xe0 0x3b 0xb2 0xee]
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0xe0 0x3b 0xb2 0xee]

# Would be vcvtb.f16.f64 s4, d1
[0x41 0x2b 0xb3 0xee]
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x41 0x2b 0xb3 0xee]

# Would be vcvtblt.f16.f64 s4, d1
[0x41 0x2b 0xb3 0xbe]
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x41 0x2b 0xb3 0xbe]

# Would be vmrs r0, mvfr2
[0x10 0xa 0xf5 0xee]
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x10 0xa 0xf5 0xee]
Commit	Line	Data
1a4d82fc JJ	1	# RUN: not llvm-mc -disassemble -triple armv7 -show-encoding < %s 2>&1 \| FileCheck %s
	2
	3	# This file is checking encodings that are valid on some triples, but not on the
	4	# ARMv7 triple, probably because the relevant instruction is v8, though there
	5	# could be other reasons.
	6
	7	# Would be vcvtt.f64.f16 d3, s1
	8	[0xe0 0x3b 0xb2 0xee]
	9	# CHECK: invalid instruction encoding
	10	# CHECK-NEXT: [0xe0 0x3b 0xb2 0xee]
	11
	12	# Would be vcvtb.f16.f64 s4, d1
	13	[0x41 0x2b 0xb3 0xee]
	14	# CHECK: invalid instruction encoding
	15	# CHECK-NEXT: [0x41 0x2b 0xb3 0xee]
	16
	17	# Would be vcvtblt.f16.f64 s4, d1
	18	[0x41 0x2b 0xb3 0xbe]
	19	# CHECK: invalid instruction encoding
	20	# CHECK-NEXT: [0x41 0x2b 0xb3 0xbe]
	21
	22	# Would be vmrs r0, mvfr2
	23	[0x10 0xa 0xf5 0xee]
	24	# CHECK: invalid instruction encoding
	25	# CHECK-NEXT: [0x10 0xa 0xf5 0xee]
	26