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Commit | Line | Data |
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0531ce1d XL |
1 | //! ARMv8 ASIMD intrinsics |
2 | ||
3 | // FIXME: replace neon with asimd | |
4 | ||
83c7162d | 5 | use coresimd::arm::*; |
83c7162d | 6 | use coresimd::simd_llvm::simd_add; |
0531ce1d XL |
7 | #[cfg(test)] |
8 | use stdsimd_test::assert_instr; | |
0531ce1d | 9 | |
83c7162d XL |
10 | types! { |
11 | /// ARM-specific 64-bit wide vector of one packed `f64`. | |
12 | pub struct float64x1_t(f64); // FIXME: check this! | |
13 | /// ARM-specific 128-bit wide vector of two packed `f64`. | |
14 | pub struct float64x2_t(f64, f64); | |
15 | } | |
0531ce1d XL |
16 | |
17 | #[allow(improper_ctypes)] | |
18 | extern "C" { | |
19 | #[link_name = "llvm.aarch64.neon.smaxv.i8.v8i8"] | |
83c7162d | 20 | fn vmaxv_s8_(a: int8x8_t) -> i8; |
0531ce1d | 21 | #[link_name = "llvm.aarch64.neon.smaxv.i8.6i8"] |
83c7162d | 22 | fn vmaxvq_s8_(a: int8x16_t) -> i8; |
0531ce1d | 23 | #[link_name = "llvm.aarch64.neon.smaxv.i16.v4i16"] |
83c7162d | 24 | fn vmaxv_s16_(a: int16x4_t) -> i16; |
0531ce1d | 25 | #[link_name = "llvm.aarch64.neon.smaxv.i16.v8i16"] |
83c7162d | 26 | fn vmaxvq_s16_(a: int16x8_t) -> i16; |
0531ce1d | 27 | #[link_name = "llvm.aarch64.neon.smaxv.i32.v2i32"] |
83c7162d | 28 | fn vmaxv_s32_(a: int32x2_t) -> i32; |
0531ce1d | 29 | #[link_name = "llvm.aarch64.neon.smaxv.i32.v4i32"] |
83c7162d | 30 | fn vmaxvq_s32_(a: int32x4_t) -> i32; |
0531ce1d XL |
31 | |
32 | #[link_name = "llvm.aarch64.neon.umaxv.i8.v8i8"] | |
83c7162d | 33 | fn vmaxv_u8_(a: uint8x8_t) -> u8; |
0531ce1d | 34 | #[link_name = "llvm.aarch64.neon.umaxv.i8.6i8"] |
83c7162d | 35 | fn vmaxvq_u8_(a: uint8x16_t) -> u8; |
0531ce1d | 36 | #[link_name = "llvm.aarch64.neon.umaxv.i16.v4i16"] |
83c7162d | 37 | fn vmaxv_u16_(a: uint16x4_t) -> u16; |
0531ce1d | 38 | #[link_name = "llvm.aarch64.neon.umaxv.i16.v8i16"] |
83c7162d | 39 | fn vmaxvq_u16_(a: uint16x8_t) -> u16; |
0531ce1d | 40 | #[link_name = "llvm.aarch64.neon.umaxv.i32.v2i32"] |
83c7162d | 41 | fn vmaxv_u32_(a: uint32x2_t) -> u32; |
0531ce1d | 42 | #[link_name = "llvm.aarch64.neon.umaxv.i32.v4i32"] |
83c7162d | 43 | fn vmaxvq_u32_(a: uint32x4_t) -> u32; |
0531ce1d XL |
44 | |
45 | #[link_name = "llvm.aarch64.neon.fmaxv.f32.v2f32"] | |
83c7162d | 46 | fn vmaxv_f32_(a: float32x2_t) -> f32; |
0531ce1d | 47 | #[link_name = "llvm.aarch64.neon.fmaxv.f32.v4f32"] |
83c7162d | 48 | fn vmaxvq_f32_(a: float32x4_t) -> f32; |
0531ce1d | 49 | #[link_name = "llvm.aarch64.neon.fmaxv.f64.v2f64"] |
83c7162d | 50 | fn vmaxvq_f64_(a: float64x2_t) -> f64; |
0531ce1d XL |
51 | |
52 | #[link_name = "llvm.aarch64.neon.sminv.i8.v8i8"] | |
83c7162d | 53 | fn vminv_s8_(a: int8x8_t) -> i8; |
0531ce1d | 54 | #[link_name = "llvm.aarch64.neon.sminv.i8.6i8"] |
83c7162d | 55 | fn vminvq_s8_(a: int8x16_t) -> i8; |
0531ce1d | 56 | #[link_name = "llvm.aarch64.neon.sminv.i16.v4i16"] |
83c7162d | 57 | fn vminv_s16_(a: int16x4_t) -> i16; |
0531ce1d | 58 | #[link_name = "llvm.aarch64.neon.sminv.i16.v8i16"] |
83c7162d | 59 | fn vminvq_s16_(a: int16x8_t) -> i16; |
0531ce1d | 60 | #[link_name = "llvm.aarch64.neon.sminv.i32.v2i32"] |
83c7162d | 61 | fn vminv_s32_(a: int32x2_t) -> i32; |
0531ce1d | 62 | #[link_name = "llvm.aarch64.neon.sminv.i32.v4i32"] |
83c7162d | 63 | fn vminvq_s32_(a: int32x4_t) -> i32; |
0531ce1d XL |
64 | |
65 | #[link_name = "llvm.aarch64.neon.uminv.i8.v8i8"] | |
83c7162d | 66 | fn vminv_u8_(a: uint8x8_t) -> u8; |
0531ce1d | 67 | #[link_name = "llvm.aarch64.neon.uminv.i8.6i8"] |
83c7162d | 68 | fn vminvq_u8_(a: uint8x16_t) -> u8; |
0531ce1d | 69 | #[link_name = "llvm.aarch64.neon.uminv.i16.v4i16"] |
83c7162d | 70 | fn vminv_u16_(a: uint16x4_t) -> u16; |
0531ce1d | 71 | #[link_name = "llvm.aarch64.neon.uminv.i16.v8i16"] |
83c7162d | 72 | fn vminvq_u16_(a: uint16x8_t) -> u16; |
0531ce1d | 73 | #[link_name = "llvm.aarch64.neon.uminv.i32.v2i32"] |
83c7162d | 74 | fn vminv_u32_(a: uint32x2_t) -> u32; |
0531ce1d | 75 | #[link_name = "llvm.aarch64.neon.uminv.i32.v4i32"] |
83c7162d | 76 | fn vminvq_u32_(a: uint32x4_t) -> u32; |
0531ce1d XL |
77 | |
78 | #[link_name = "llvm.aarch64.neon.fminv.f32.v2f32"] | |
83c7162d | 79 | fn vminv_f32_(a: float32x2_t) -> f32; |
0531ce1d | 80 | #[link_name = "llvm.aarch64.neon.fminv.f32.v4f32"] |
83c7162d | 81 | fn vminvq_f32_(a: float32x4_t) -> f32; |
0531ce1d | 82 | #[link_name = "llvm.aarch64.neon.fminv.f64.v2f64"] |
83c7162d XL |
83 | fn vminvq_f64_(a: float64x2_t) -> f64; |
84 | ||
85 | #[link_name = "llvm.aarch64.neon.sminp.v16i8"] | |
86 | fn vpminq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t; | |
87 | #[link_name = "llvm.aarch64.neon.sminp.v8i16"] | |
88 | fn vpminq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t; | |
89 | #[link_name = "llvm.aarch64.neon.sminp.v4i32"] | |
90 | fn vpminq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t; | |
91 | #[link_name = "llvm.aarch64.neon.uminp.v16i8"] | |
92 | fn vpminq_u8_(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; | |
93 | #[link_name = "llvm.aarch64.neon.uminp.v8i16"] | |
94 | fn vpminq_u16_(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; | |
95 | #[link_name = "llvm.aarch64.neon.uminp.v4i32"] | |
96 | fn vpminq_u32_(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; | |
97 | #[link_name = "llvm.aarch64.neon.fminp.4f32"] | |
98 | fn vpminq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; | |
99 | #[link_name = "llvm.aarch64.neon.fminp.v2f64"] | |
100 | fn vpminq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; | |
101 | ||
102 | #[link_name = "llvm.aarch64.neon.smaxp.v16i8"] | |
103 | fn vpmaxq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t; | |
104 | #[link_name = "llvm.aarch64.neon.smaxp.v8i16"] | |
105 | fn vpmaxq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t; | |
106 | #[link_name = "llvm.aarch64.neon.smaxp.v4i32"] | |
107 | fn vpmaxq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t; | |
108 | #[link_name = "llvm.aarch64.neon.umaxp.v16i8"] | |
109 | fn vpmaxq_u8_(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; | |
110 | #[link_name = "llvm.aarch64.neon.umaxp.v8i16"] | |
111 | fn vpmaxq_u16_(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; | |
112 | #[link_name = "llvm.aarch64.neon.umaxp.v4i32"] | |
113 | fn vpmaxq_u32_(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; | |
114 | #[link_name = "llvm.aarch64.neon.fmaxp.4f32"] | |
115 | fn vpmaxq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; | |
116 | #[link_name = "llvm.aarch64.neon.fmaxp.v2f64"] | |
117 | fn vpmaxq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; | |
118 | } | |
119 | ||
120 | /// Vector add. | |
121 | #[inline] | |
122 | #[target_feature(enable = "neon")] | |
123 | #[cfg_attr(test, assert_instr(fadd))] | |
124 | pub unsafe fn vadd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { | |
125 | simd_add(a, b) | |
126 | } | |
127 | ||
128 | /// Vector add. | |
129 | #[inline] | |
130 | #[target_feature(enable = "neon")] | |
131 | #[cfg_attr(test, assert_instr(fadd))] | |
132 | pub unsafe fn vaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
133 | simd_add(a, b) | |
134 | } | |
135 | ||
136 | /// Vector add. | |
137 | #[inline] | |
138 | #[target_feature(enable = "neon")] | |
139 | #[cfg_attr(test, assert_instr(add))] | |
140 | pub unsafe fn vaddd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { | |
141 | simd_add(a, b) | |
142 | } | |
0531ce1d | 143 | |
83c7162d XL |
144 | /// Vector add. |
145 | #[inline] | |
146 | #[target_feature(enable = "neon")] | |
147 | #[cfg_attr(test, assert_instr(add))] | |
148 | pub unsafe fn vaddd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { | |
149 | simd_add(a, b) | |
0531ce1d XL |
150 | } |
151 | ||
152 | /// Horizontal vector max. | |
153 | #[inline] | |
154 | #[target_feature(enable = "neon")] | |
155 | #[cfg_attr(test, assert_instr(smaxv))] | |
83c7162d | 156 | pub unsafe fn vmaxv_s8(a: int8x8_t) -> i8 { |
0531ce1d XL |
157 | vmaxv_s8_(a) |
158 | } | |
159 | ||
160 | /// Horizontal vector max. | |
161 | #[inline] | |
162 | #[target_feature(enable = "neon")] | |
163 | #[cfg_attr(test, assert_instr(smaxv))] | |
83c7162d | 164 | pub unsafe fn vmaxvq_s8(a: int8x16_t) -> i8 { |
0531ce1d XL |
165 | vmaxvq_s8_(a) |
166 | } | |
167 | ||
168 | /// Horizontal vector max. | |
169 | #[inline] | |
170 | #[target_feature(enable = "neon")] | |
171 | #[cfg_attr(test, assert_instr(smaxv))] | |
83c7162d | 172 | pub unsafe fn vmaxv_s16(a: int16x4_t) -> i16 { |
0531ce1d XL |
173 | vmaxv_s16_(a) |
174 | } | |
175 | ||
176 | /// Horizontal vector max. | |
177 | #[inline] | |
178 | #[target_feature(enable = "neon")] | |
179 | #[cfg_attr(test, assert_instr(smaxv))] | |
83c7162d | 180 | pub unsafe fn vmaxvq_s16(a: int16x8_t) -> i16 { |
0531ce1d XL |
181 | vmaxvq_s16_(a) |
182 | } | |
183 | ||
184 | /// Horizontal vector max. | |
185 | #[inline] | |
186 | #[target_feature(enable = "neon")] | |
187 | #[cfg_attr(test, assert_instr(smaxp))] | |
83c7162d | 188 | pub unsafe fn vmaxv_s32(a: int32x2_t) -> i32 { |
0531ce1d XL |
189 | vmaxv_s32_(a) |
190 | } | |
191 | ||
192 | /// Horizontal vector max. | |
193 | #[inline] | |
194 | #[target_feature(enable = "neon")] | |
195 | #[cfg_attr(test, assert_instr(smaxv))] | |
83c7162d | 196 | pub unsafe fn vmaxvq_s32(a: int32x4_t) -> i32 { |
0531ce1d XL |
197 | vmaxvq_s32_(a) |
198 | } | |
199 | ||
200 | /// Horizontal vector max. | |
201 | #[inline] | |
202 | #[target_feature(enable = "neon")] | |
203 | #[cfg_attr(test, assert_instr(umaxv))] | |
83c7162d | 204 | pub unsafe fn vmaxv_u8(a: uint8x8_t) -> u8 { |
0531ce1d XL |
205 | vmaxv_u8_(a) |
206 | } | |
207 | ||
208 | /// Horizontal vector max. | |
209 | #[inline] | |
210 | #[target_feature(enable = "neon")] | |
211 | #[cfg_attr(test, assert_instr(umaxv))] | |
83c7162d | 212 | pub unsafe fn vmaxvq_u8(a: uint8x16_t) -> u8 { |
0531ce1d XL |
213 | vmaxvq_u8_(a) |
214 | } | |
215 | ||
216 | /// Horizontal vector max. | |
217 | #[inline] | |
218 | #[target_feature(enable = "neon")] | |
219 | #[cfg_attr(test, assert_instr(umaxv))] | |
83c7162d | 220 | pub unsafe fn vmaxv_u16(a: uint16x4_t) -> u16 { |
0531ce1d XL |
221 | vmaxv_u16_(a) |
222 | } | |
223 | ||
224 | /// Horizontal vector max. | |
225 | #[inline] | |
226 | #[target_feature(enable = "neon")] | |
227 | #[cfg_attr(test, assert_instr(umaxv))] | |
83c7162d | 228 | pub unsafe fn vmaxvq_u16(a: uint16x8_t) -> u16 { |
0531ce1d XL |
229 | vmaxvq_u16_(a) |
230 | } | |
231 | ||
232 | /// Horizontal vector max. | |
233 | #[inline] | |
234 | #[target_feature(enable = "neon")] | |
235 | #[cfg_attr(test, assert_instr(umaxp))] | |
83c7162d | 236 | pub unsafe fn vmaxv_u32(a: uint32x2_t) -> u32 { |
0531ce1d XL |
237 | vmaxv_u32_(a) |
238 | } | |
239 | ||
240 | /// Horizontal vector max. | |
241 | #[inline] | |
242 | #[target_feature(enable = "neon")] | |
243 | #[cfg_attr(test, assert_instr(umaxv))] | |
83c7162d | 244 | pub unsafe fn vmaxvq_u32(a: uint32x4_t) -> u32 { |
0531ce1d XL |
245 | vmaxvq_u32_(a) |
246 | } | |
247 | ||
248 | /// Horizontal vector max. | |
249 | #[inline] | |
250 | #[target_feature(enable = "neon")] | |
251 | #[cfg_attr(test, assert_instr(fmaxp))] | |
83c7162d | 252 | pub unsafe fn vmaxv_f32(a: float32x2_t) -> f32 { |
0531ce1d XL |
253 | vmaxv_f32_(a) |
254 | } | |
255 | ||
256 | /// Horizontal vector max. | |
257 | #[inline] | |
258 | #[target_feature(enable = "neon")] | |
259 | #[cfg_attr(test, assert_instr(fmaxv))] | |
83c7162d | 260 | pub unsafe fn vmaxvq_f32(a: float32x4_t) -> f32 { |
0531ce1d XL |
261 | vmaxvq_f32_(a) |
262 | } | |
263 | ||
264 | /// Horizontal vector max. | |
265 | #[inline] | |
266 | #[target_feature(enable = "neon")] | |
267 | #[cfg_attr(test, assert_instr(fmaxp))] | |
83c7162d | 268 | pub unsafe fn vmaxvq_f64(a: float64x2_t) -> f64 { |
0531ce1d XL |
269 | vmaxvq_f64_(a) |
270 | } | |
271 | ||
272 | /// Horizontal vector min. | |
273 | #[inline] | |
274 | #[target_feature(enable = "neon")] | |
275 | #[cfg_attr(test, assert_instr(sminv))] | |
83c7162d | 276 | pub unsafe fn vminv_s8(a: int8x8_t) -> i8 { |
0531ce1d XL |
277 | vminv_s8_(a) |
278 | } | |
279 | ||
280 | /// Horizontal vector min. | |
281 | #[inline] | |
282 | #[target_feature(enable = "neon")] | |
283 | #[cfg_attr(test, assert_instr(sminv))] | |
83c7162d | 284 | pub unsafe fn vminvq_s8(a: int8x16_t) -> i8 { |
0531ce1d XL |
285 | vminvq_s8_(a) |
286 | } | |
287 | ||
288 | /// Horizontal vector min. | |
289 | #[inline] | |
290 | #[target_feature(enable = "neon")] | |
291 | #[cfg_attr(test, assert_instr(sminv))] | |
83c7162d | 292 | pub unsafe fn vminv_s16(a: int16x4_t) -> i16 { |
0531ce1d XL |
293 | vminv_s16_(a) |
294 | } | |
295 | ||
296 | /// Horizontal vector min. | |
297 | #[inline] | |
298 | #[target_feature(enable = "neon")] | |
299 | #[cfg_attr(test, assert_instr(sminv))] | |
83c7162d | 300 | pub unsafe fn vminvq_s16(a: int16x8_t) -> i16 { |
0531ce1d XL |
301 | vminvq_s16_(a) |
302 | } | |
303 | ||
304 | /// Horizontal vector min. | |
305 | #[inline] | |
306 | #[target_feature(enable = "neon")] | |
307 | #[cfg_attr(test, assert_instr(sminp))] | |
83c7162d | 308 | pub unsafe fn vminv_s32(a: int32x2_t) -> i32 { |
0531ce1d XL |
309 | vminv_s32_(a) |
310 | } | |
311 | ||
312 | /// Horizontal vector min. | |
313 | #[inline] | |
314 | #[target_feature(enable = "neon")] | |
315 | #[cfg_attr(test, assert_instr(sminv))] | |
83c7162d | 316 | pub unsafe fn vminvq_s32(a: int32x4_t) -> i32 { |
0531ce1d XL |
317 | vminvq_s32_(a) |
318 | } | |
319 | ||
320 | /// Horizontal vector min. | |
321 | #[inline] | |
322 | #[target_feature(enable = "neon")] | |
323 | #[cfg_attr(test, assert_instr(uminv))] | |
83c7162d | 324 | pub unsafe fn vminv_u8(a: uint8x8_t) -> u8 { |
0531ce1d XL |
325 | vminv_u8_(a) |
326 | } | |
327 | ||
328 | /// Horizontal vector min. | |
329 | #[inline] | |
330 | #[target_feature(enable = "neon")] | |
331 | #[cfg_attr(test, assert_instr(uminv))] | |
83c7162d | 332 | pub unsafe fn vminvq_u8(a: uint8x16_t) -> u8 { |
0531ce1d XL |
333 | vminvq_u8_(a) |
334 | } | |
335 | ||
336 | /// Horizontal vector min. | |
337 | #[inline] | |
338 | #[target_feature(enable = "neon")] | |
339 | #[cfg_attr(test, assert_instr(uminv))] | |
83c7162d | 340 | pub unsafe fn vminv_u16(a: uint16x4_t) -> u16 { |
0531ce1d XL |
341 | vminv_u16_(a) |
342 | } | |
343 | ||
344 | /// Horizontal vector min. | |
345 | #[inline] | |
346 | #[target_feature(enable = "neon")] | |
347 | #[cfg_attr(test, assert_instr(uminv))] | |
83c7162d | 348 | pub unsafe fn vminvq_u16(a: uint16x8_t) -> u16 { |
0531ce1d XL |
349 | vminvq_u16_(a) |
350 | } | |
351 | ||
352 | /// Horizontal vector min. | |
353 | #[inline] | |
354 | #[target_feature(enable = "neon")] | |
355 | #[cfg_attr(test, assert_instr(uminp))] | |
83c7162d | 356 | pub unsafe fn vminv_u32(a: uint32x2_t) -> u32 { |
0531ce1d XL |
357 | vminv_u32_(a) |
358 | } | |
359 | ||
360 | /// Horizontal vector min. | |
361 | #[inline] | |
362 | #[target_feature(enable = "neon")] | |
363 | #[cfg_attr(test, assert_instr(uminv))] | |
83c7162d | 364 | pub unsafe fn vminvq_u32(a: uint32x4_t) -> u32 { |
0531ce1d XL |
365 | vminvq_u32_(a) |
366 | } | |
367 | ||
368 | /// Horizontal vector min. | |
369 | #[inline] | |
370 | #[target_feature(enable = "neon")] | |
371 | #[cfg_attr(test, assert_instr(fminp))] | |
83c7162d | 372 | pub unsafe fn vminv_f32(a: float32x2_t) -> f32 { |
0531ce1d XL |
373 | vminv_f32_(a) |
374 | } | |
375 | ||
376 | /// Horizontal vector min. | |
377 | #[inline] | |
378 | #[target_feature(enable = "neon")] | |
379 | #[cfg_attr(test, assert_instr(fminv))] | |
83c7162d | 380 | pub unsafe fn vminvq_f32(a: float32x4_t) -> f32 { |
0531ce1d XL |
381 | vminvq_f32_(a) |
382 | } | |
383 | ||
384 | /// Horizontal vector min. | |
385 | #[inline] | |
386 | #[target_feature(enable = "neon")] | |
387 | #[cfg_attr(test, assert_instr(fminp))] | |
83c7162d | 388 | pub unsafe fn vminvq_f64(a: float64x2_t) -> f64 { |
0531ce1d XL |
389 | vminvq_f64_(a) |
390 | } | |
391 | ||
83c7162d XL |
392 | /// Folding minimum of adjacent pairs |
393 | #[inline] | |
394 | #[target_feature(enable = "neon")] | |
395 | #[cfg_attr(test, assert_instr(sminp))] | |
396 | pub unsafe fn vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { | |
397 | vpminq_s8_(a, b) | |
398 | } | |
399 | ||
400 | /// Folding minimum of adjacent pairs | |
401 | #[inline] | |
402 | #[target_feature(enable = "neon")] | |
403 | #[cfg_attr(test, assert_instr(sminp))] | |
404 | pub unsafe fn vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { | |
405 | vpminq_s16_(a, b) | |
406 | } | |
407 | ||
408 | /// Folding minimum of adjacent pairs | |
409 | #[inline] | |
410 | #[target_feature(enable = "neon")] | |
411 | #[cfg_attr(test, assert_instr(sminp))] | |
412 | pub unsafe fn vpminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { | |
413 | vpminq_s32_(a, b) | |
414 | } | |
415 | ||
416 | /// Folding minimum of adjacent pairs | |
417 | #[inline] | |
418 | #[target_feature(enable = "neon")] | |
419 | #[cfg_attr(test, assert_instr(uminp))] | |
420 | pub unsafe fn vpminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { | |
421 | vpminq_u8_(a, b) | |
422 | } | |
423 | ||
424 | /// Folding minimum of adjacent pairs | |
425 | #[inline] | |
426 | #[target_feature(enable = "neon")] | |
427 | #[cfg_attr(test, assert_instr(uminp))] | |
428 | pub unsafe fn vpminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { | |
429 | vpminq_u16_(a, b) | |
430 | } | |
431 | ||
432 | /// Folding minimum of adjacent pairs | |
433 | #[inline] | |
434 | #[target_feature(enable = "neon")] | |
435 | #[cfg_attr(test, assert_instr(uminp))] | |
436 | pub unsafe fn vpminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { | |
437 | vpminq_u32_(a, b) | |
438 | } | |
439 | ||
440 | /// Folding minimum of adjacent pairs | |
441 | #[inline] | |
442 | #[target_feature(enable = "neon")] | |
443 | #[cfg_attr(test, assert_instr(fminp))] | |
444 | pub unsafe fn vpminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
445 | vpminq_f32_(a, b) | |
446 | } | |
447 | ||
448 | /// Folding minimum of adjacent pairs | |
449 | #[inline] | |
450 | #[target_feature(enable = "neon")] | |
451 | #[cfg_attr(test, assert_instr(fminp))] | |
452 | pub unsafe fn vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
453 | vpminq_f64_(a, b) | |
454 | } | |
455 | ||
456 | /// Folding maximum of adjacent pairs | |
457 | #[inline] | |
458 | #[target_feature(enable = "neon")] | |
459 | #[cfg_attr(test, assert_instr(smaxp))] | |
460 | pub unsafe fn vpmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { | |
461 | vpmaxq_s8_(a, b) | |
462 | } | |
463 | ||
464 | /// Folding maximum of adjacent pairs | |
465 | #[inline] | |
466 | #[target_feature(enable = "neon")] | |
467 | #[cfg_attr(test, assert_instr(smaxp))] | |
468 | pub unsafe fn vpmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { | |
469 | vpmaxq_s16_(a, b) | |
470 | } | |
471 | ||
472 | /// Folding maximum of adjacent pairs | |
473 | #[inline] | |
474 | #[target_feature(enable = "neon")] | |
475 | #[cfg_attr(test, assert_instr(smaxp))] | |
476 | pub unsafe fn vpmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { | |
477 | vpmaxq_s32_(a, b) | |
478 | } | |
479 | ||
480 | /// Folding maximum of adjacent pairs | |
481 | #[inline] | |
482 | #[target_feature(enable = "neon")] | |
483 | #[cfg_attr(test, assert_instr(umaxp))] | |
484 | pub unsafe fn vpmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { | |
485 | vpmaxq_u8_(a, b) | |
486 | } | |
487 | ||
488 | /// Folding maximum of adjacent pairs | |
489 | #[inline] | |
490 | #[target_feature(enable = "neon")] | |
491 | #[cfg_attr(test, assert_instr(umaxp))] | |
492 | pub unsafe fn vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { | |
493 | vpmaxq_u16_(a, b) | |
494 | } | |
495 | ||
496 | /// Folding maximum of adjacent pairs | |
497 | #[inline] | |
498 | #[target_feature(enable = "neon")] | |
499 | #[cfg_attr(test, assert_instr(umaxp))] | |
500 | pub unsafe fn vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { | |
501 | vpmaxq_u32_(a, b) | |
502 | } | |
503 | ||
504 | /// Folding maximum of adjacent pairs | |
505 | #[inline] | |
506 | #[target_feature(enable = "neon")] | |
507 | #[cfg_attr(test, assert_instr(fmaxp))] | |
508 | pub unsafe fn vpmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { | |
509 | vpmaxq_f32_(a, b) | |
510 | } | |
511 | ||
512 | /// Folding maximum of adjacent pairs | |
513 | #[inline] | |
514 | #[target_feature(enable = "neon")] | |
515 | #[cfg_attr(test, assert_instr(fmaxp))] | |
516 | pub unsafe fn vpmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { | |
517 | vpmaxq_f64_(a, b) | |
518 | } | |
519 | ||
0531ce1d XL |
520 | #[cfg(test)] |
521 | mod tests { | |
83c7162d | 522 | use coresimd::aarch64::*; |
8faf50e0 | 523 | use coresimd::simd::*; |
83c7162d | 524 | use std::mem; |
0531ce1d XL |
525 | use stdsimd_test::simd_test; |
526 | ||
83c7162d XL |
527 | #[simd_test(enable = "neon")] |
528 | unsafe fn test_vadd_f64() { | |
0531ce1d XL |
529 | let a = 1.; |
530 | let b = 8.; | |
531 | let e = 9.; | |
83c7162d XL |
532 | let r: f64 = |
533 | mem::transmute(vadd_f64(mem::transmute(a), mem::transmute(b))); | |
0531ce1d XL |
534 | assert_eq!(r, e); |
535 | } | |
536 | ||
83c7162d XL |
537 | #[simd_test(enable = "neon")] |
538 | unsafe fn test_vaddq_f64() { | |
0531ce1d XL |
539 | let a = f64x2::new(1., 2.); |
540 | let b = f64x2::new(8., 7.); | |
541 | let e = f64x2::new(9., 9.); | |
8faf50e0 | 542 | let r: f64x2 = ::mem::transmute(vaddq_f64(::mem::transmute(a), ::mem::transmute(b))); |
0531ce1d XL |
543 | assert_eq!(r, e); |
544 | } | |
545 | ||
83c7162d XL |
546 | #[simd_test(enable = "neon")] |
547 | unsafe fn test_vaddd_s64() { | |
548 | let a = 1_i64; | |
549 | let b = 8_i64; | |
550 | let e = 9_i64; | |
551 | let r: i64 = | |
552 | mem::transmute(vaddd_s64(mem::transmute(a), mem::transmute(b))); | |
0531ce1d XL |
553 | assert_eq!(r, e); |
554 | } | |
555 | ||
83c7162d XL |
556 | #[simd_test(enable = "neon")] |
557 | unsafe fn test_vaddd_u64() { | |
558 | let a = 1_u64; | |
559 | let b = 8_u64; | |
560 | let e = 9_u64; | |
561 | let r: u64 = | |
562 | mem::transmute(vaddd_u64(mem::transmute(a), mem::transmute(b))); | |
0531ce1d XL |
563 | assert_eq!(r, e); |
564 | } | |
565 | ||
83c7162d XL |
566 | #[simd_test(enable = "neon")] |
567 | unsafe fn test_vmaxv_s8() { | |
8faf50e0 | 568 | let r = vmaxv_s8(::mem::transmute(i8x8::new(1, 2, 3, 4, -8, 6, 7, 5))); |
0531ce1d XL |
569 | assert_eq!(r, 7_i8); |
570 | } | |
571 | ||
83c7162d XL |
572 | #[simd_test(enable = "neon")] |
573 | unsafe fn test_vmaxvq_s8() { | |
0531ce1d | 574 | #[cfg_attr(rustfmt, rustfmt_skip)] |
8faf50e0 | 575 | let r = vmaxvq_s8(::mem::transmute(i8x16::new( |
0531ce1d XL |
576 | 1, 2, 3, 4, |
577 | -16, 6, 7, 5, | |
578 | 8, 1, 1, 1, | |
579 | 1, 1, 1, 1, | |
8faf50e0 | 580 | ))); |
0531ce1d XL |
581 | assert_eq!(r, 8_i8); |
582 | } | |
583 | ||
83c7162d XL |
584 | #[simd_test(enable = "neon")] |
585 | unsafe fn test_vmaxv_s16() { | |
8faf50e0 | 586 | let r = vmaxv_s16(::mem::transmute(i16x4::new(1, 2, -4, 3))); |
0531ce1d XL |
587 | assert_eq!(r, 3_i16); |
588 | } | |
589 | ||
83c7162d XL |
590 | #[simd_test(enable = "neon")] |
591 | unsafe fn test_vmaxvq_s16() { | |
8faf50e0 | 592 | let r = vmaxvq_s16(::mem::transmute(i16x8::new(1, 2, 7, 4, -16, 6, 7, 5))); |
0531ce1d XL |
593 | assert_eq!(r, 7_i16); |
594 | } | |
595 | ||
83c7162d XL |
596 | #[simd_test(enable = "neon")] |
597 | unsafe fn test_vmaxv_s32() { | |
8faf50e0 | 598 | let r = vmaxv_s32(::mem::transmute(i32x2::new(1, -4))); |
0531ce1d XL |
599 | assert_eq!(r, 1_i32); |
600 | } | |
601 | ||
83c7162d XL |
602 | #[simd_test(enable = "neon")] |
603 | unsafe fn test_vmaxvq_s32() { | |
8faf50e0 | 604 | let r = vmaxvq_s32(::mem::transmute(i32x4::new(1, 2, -32, 4))); |
0531ce1d XL |
605 | assert_eq!(r, 4_i32); |
606 | } | |
607 | ||
83c7162d XL |
608 | #[simd_test(enable = "neon")] |
609 | unsafe fn test_vmaxv_u8() { | |
8faf50e0 | 610 | let r = vmaxv_u8(::mem::transmute(u8x8::new(1, 2, 3, 4, 8, 6, 7, 5))); |
0531ce1d XL |
611 | assert_eq!(r, 8_u8); |
612 | } | |
613 | ||
83c7162d XL |
614 | #[simd_test(enable = "neon")] |
615 | unsafe fn test_vmaxvq_u8() { | |
0531ce1d | 616 | #[cfg_attr(rustfmt, rustfmt_skip)] |
8faf50e0 | 617 | let r = vmaxvq_u8(::mem::transmute(u8x16::new( |
0531ce1d XL |
618 | 1, 2, 3, 4, |
619 | 16, 6, 7, 5, | |
620 | 8, 1, 1, 1, | |
621 | 1, 1, 1, 1, | |
8faf50e0 | 622 | ))); |
0531ce1d XL |
623 | assert_eq!(r, 16_u8); |
624 | } | |
625 | ||
83c7162d XL |
626 | #[simd_test(enable = "neon")] |
627 | unsafe fn test_vmaxv_u16() { | |
8faf50e0 | 628 | let r = vmaxv_u16(::mem::transmute(u16x4::new(1, 2, 4, 3))); |
0531ce1d XL |
629 | assert_eq!(r, 4_u16); |
630 | } | |
631 | ||
83c7162d XL |
632 | #[simd_test(enable = "neon")] |
633 | unsafe fn test_vmaxvq_u16() { | |
8faf50e0 | 634 | let r = vmaxvq_u16(::mem::transmute(u16x8::new(1, 2, 7, 4, 16, 6, 7, 5))); |
0531ce1d XL |
635 | assert_eq!(r, 16_u16); |
636 | } | |
637 | ||
83c7162d XL |
638 | #[simd_test(enable = "neon")] |
639 | unsafe fn test_vmaxv_u32() { | |
8faf50e0 | 640 | let r = vmaxv_u32(::mem::transmute(u32x2::new(1, 4))); |
0531ce1d XL |
641 | assert_eq!(r, 4_u32); |
642 | } | |
643 | ||
83c7162d XL |
644 | #[simd_test(enable = "neon")] |
645 | unsafe fn test_vmaxvq_u32() { | |
8faf50e0 | 646 | let r = vmaxvq_u32(::mem::transmute(u32x4::new(1, 2, 32, 4))); |
0531ce1d XL |
647 | assert_eq!(r, 32_u32); |
648 | } | |
649 | ||
83c7162d XL |
650 | #[simd_test(enable = "neon")] |
651 | unsafe fn test_vmaxv_f32() { | |
8faf50e0 | 652 | let r = vmaxv_f32(::mem::transmute(f32x2::new(1., 4.))); |
0531ce1d XL |
653 | assert_eq!(r, 4_f32); |
654 | } | |
655 | ||
83c7162d XL |
656 | #[simd_test(enable = "neon")] |
657 | unsafe fn test_vmaxvq_f32() { | |
8faf50e0 | 658 | let r = vmaxvq_f32(::mem::transmute(f32x4::new(1., 2., 32., 4.))); |
0531ce1d XL |
659 | assert_eq!(r, 32_f32); |
660 | } | |
661 | ||
83c7162d XL |
662 | #[simd_test(enable = "neon")] |
663 | unsafe fn test_vmaxvq_f64() { | |
8faf50e0 | 664 | let r = vmaxvq_f64(::mem::transmute(f64x2::new(1., 4.))); |
0531ce1d XL |
665 | assert_eq!(r, 4_f64); |
666 | } | |
667 | ||
83c7162d XL |
668 | #[simd_test(enable = "neon")] |
669 | unsafe fn test_vminv_s8() { | |
8faf50e0 | 670 | let r = vminv_s8(::mem::transmute(i8x8::new(1, 2, 3, 4, -8, 6, 7, 5))); |
0531ce1d XL |
671 | assert_eq!(r, -8_i8); |
672 | } | |
673 | ||
83c7162d XL |
674 | #[simd_test(enable = "neon")] |
675 | unsafe fn test_vminvq_s8() { | |
0531ce1d | 676 | #[cfg_attr(rustfmt, rustfmt_skip)] |
8faf50e0 | 677 | let r = vminvq_s8(::mem::transmute(i8x16::new( |
0531ce1d XL |
678 | 1, 2, 3, 4, |
679 | -16, 6, 7, 5, | |
680 | 8, 1, 1, 1, | |
681 | 1, 1, 1, 1, | |
8faf50e0 | 682 | ))); |
0531ce1d XL |
683 | assert_eq!(r, -16_i8); |
684 | } | |
685 | ||
83c7162d XL |
686 | #[simd_test(enable = "neon")] |
687 | unsafe fn test_vminv_s16() { | |
8faf50e0 | 688 | let r = vminv_s16(::mem::transmute(i16x4::new(1, 2, -4, 3))); |
0531ce1d XL |
689 | assert_eq!(r, -4_i16); |
690 | } | |
691 | ||
83c7162d XL |
692 | #[simd_test(enable = "neon")] |
693 | unsafe fn test_vminvq_s16() { | |
8faf50e0 | 694 | let r = vminvq_s16(::mem::transmute(i16x8::new(1, 2, 7, 4, -16, 6, 7, 5))); |
0531ce1d XL |
695 | assert_eq!(r, -16_i16); |
696 | } | |
697 | ||
83c7162d XL |
698 | #[simd_test(enable = "neon")] |
699 | unsafe fn test_vminv_s32() { | |
8faf50e0 | 700 | let r = vminv_s32(::mem::transmute(i32x2::new(1, -4))); |
0531ce1d XL |
701 | assert_eq!(r, -4_i32); |
702 | } | |
703 | ||
83c7162d XL |
704 | #[simd_test(enable = "neon")] |
705 | unsafe fn test_vminvq_s32() { | |
8faf50e0 | 706 | let r = vminvq_s32(::mem::transmute(i32x4::new(1, 2, -32, 4))); |
0531ce1d XL |
707 | assert_eq!(r, -32_i32); |
708 | } | |
709 | ||
83c7162d XL |
710 | #[simd_test(enable = "neon")] |
711 | unsafe fn test_vminv_u8() { | |
8faf50e0 | 712 | let r = vminv_u8(::mem::transmute(u8x8::new(1, 2, 3, 4, 8, 6, 7, 5))); |
0531ce1d XL |
713 | assert_eq!(r, 1_u8); |
714 | } | |
715 | ||
83c7162d XL |
716 | #[simd_test(enable = "neon")] |
717 | unsafe fn test_vminvq_u8() { | |
0531ce1d | 718 | #[cfg_attr(rustfmt, rustfmt_skip)] |
8faf50e0 | 719 | let r = vminvq_u8(::mem::transmute(u8x16::new( |
0531ce1d XL |
720 | 1, 2, 3, 4, |
721 | 16, 6, 7, 5, | |
722 | 8, 1, 1, 1, | |
723 | 1, 1, 1, 1, | |
8faf50e0 | 724 | ))); |
0531ce1d XL |
725 | assert_eq!(r, 1_u8); |
726 | } | |
727 | ||
83c7162d XL |
728 | #[simd_test(enable = "neon")] |
729 | unsafe fn test_vminv_u16() { | |
8faf50e0 | 730 | let r = vminv_u16(::mem::transmute(u16x4::new(1, 2, 4, 3))); |
0531ce1d XL |
731 | assert_eq!(r, 1_u16); |
732 | } | |
733 | ||
83c7162d XL |
734 | #[simd_test(enable = "neon")] |
735 | unsafe fn test_vminvq_u16() { | |
8faf50e0 | 736 | let r = vminvq_u16(::mem::transmute(u16x8::new(1, 2, 7, 4, 16, 6, 7, 5))); |
0531ce1d XL |
737 | assert_eq!(r, 1_u16); |
738 | } | |
739 | ||
83c7162d XL |
740 | #[simd_test(enable = "neon")] |
741 | unsafe fn test_vminv_u32() { | |
8faf50e0 | 742 | let r = vminv_u32(::mem::transmute(u32x2::new(1, 4))); |
0531ce1d XL |
743 | assert_eq!(r, 1_u32); |
744 | } | |
745 | ||
83c7162d XL |
746 | #[simd_test(enable = "neon")] |
747 | unsafe fn test_vminvq_u32() { | |
8faf50e0 | 748 | let r = vminvq_u32(::mem::transmute(u32x4::new(1, 2, 32, 4))); |
0531ce1d XL |
749 | assert_eq!(r, 1_u32); |
750 | } | |
751 | ||
83c7162d XL |
752 | #[simd_test(enable = "neon")] |
753 | unsafe fn test_vminv_f32() { | |
8faf50e0 | 754 | let r = vminv_f32(::mem::transmute(f32x2::new(1., 4.))); |
0531ce1d XL |
755 | assert_eq!(r, 1_f32); |
756 | } | |
757 | ||
83c7162d XL |
758 | #[simd_test(enable = "neon")] |
759 | unsafe fn test_vminvq_f32() { | |
8faf50e0 | 760 | let r = vminvq_f32(::mem::transmute(f32x4::new(1., 2., 32., 4.))); |
0531ce1d XL |
761 | assert_eq!(r, 1_f32); |
762 | } | |
763 | ||
83c7162d XL |
764 | #[simd_test(enable = "neon")] |
765 | unsafe fn test_vminvq_f64() { | |
8faf50e0 | 766 | let r = vminvq_f64(::mem::transmute(f64x2::new(1., 4.))); |
0531ce1d XL |
767 | assert_eq!(r, 1_f64); |
768 | } | |
83c7162d XL |
769 | |
770 | #[simd_test(enable = "neon")] | |
771 | unsafe fn test_vpminq_s8() { | |
772 | #[cfg_attr(rustfmt, skip)] | |
8faf50e0 | 773 | let a = i8x16::new(1, -2, 3, -4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8); |
83c7162d | 774 | #[cfg_attr(rustfmt, skip)] |
8faf50e0 | 775 | let b = i8x16::new(0, 3, 2, 5, 4, 7, 6, 9, 0, 3, 2, 5, 4, 7, 6, 9); |
83c7162d | 776 | #[cfg_attr(rustfmt, skip)] |
8faf50e0 XL |
777 | let e = i8x16::new(-2, -4, 5, 7, 1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6); |
778 | let r: i8x16 = ::mem::transmute(vpminq_s8(::mem::transmute(a), ::mem::transmute(b))); | |
83c7162d XL |
779 | assert_eq!(r, e); |
780 | } | |
781 | ||
782 | #[simd_test(enable = "neon")] | |
783 | unsafe fn test_vpminq_s16() { | |
784 | let a = i16x8::new(1, -2, 3, 4, 5, 6, 7, 8); | |
785 | let b = i16x8::new(0, 3, 2, 5, 4, 7, 6, 9); | |
786 | let e = i16x8::new(-2, 3, 5, 7, 0, 2, 4, 6); | |
8faf50e0 | 787 | let r: i16x8 = ::mem::transmute(vpminq_s16(::mem::transmute(a), ::mem::transmute(b))); |
83c7162d XL |
788 | assert_eq!(r, e); |
789 | } | |
790 | ||
791 | #[simd_test(enable = "neon")] | |
792 | unsafe fn test_vpminq_s32() { | |
793 | let a = i32x4::new(1, -2, 3, 4); | |
794 | let b = i32x4::new(0, 3, 2, 5); | |
795 | let e = i32x4::new(-2, 3, 0, 2); | |
8faf50e0 | 796 | let r: i32x4 = ::mem::transmute(vpminq_s32(::mem::transmute(a), ::mem::transmute(b))); |
83c7162d XL |
797 | assert_eq!(r, e); |
798 | } | |
799 | ||
800 | #[simd_test(enable = "neon")] | |
801 | unsafe fn test_vpminq_u8() { | |
802 | #[cfg_attr(rustfmt, skip)] | |
8faf50e0 | 803 | let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8); |
83c7162d | 804 | #[cfg_attr(rustfmt, skip)] |
8faf50e0 | 805 | let b = u8x16::new(0, 3, 2, 5, 4, 7, 6, 9, 0, 3, 2, 5, 4, 7, 6, 9); |
83c7162d | 806 | #[cfg_attr(rustfmt, skip)] |
8faf50e0 XL |
807 | let e = u8x16::new(1, 3, 5, 7, 1, 3, 5, 7, 0, 2, 4, 6, 0, 2, 4, 6); |
808 | let r: u8x16 = ::mem::transmute(vpminq_u8(::mem::transmute(a), ::mem::transmute(b))); | |
83c7162d XL |
809 | assert_eq!(r, e); |
810 | } | |
811 | ||
812 | #[simd_test(enable = "neon")] | |
813 | unsafe fn test_vpminq_u16() { | |
814 | let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
815 | let b = u16x8::new(0, 3, 2, 5, 4, 7, 6, 9); | |
816 | let e = u16x8::new(1, 3, 5, 7, 0, 2, 4, 6); | |
8faf50e0 | 817 | let r: u16x8 = ::mem::transmute(vpminq_u16(::mem::transmute(a), ::mem::transmute(b))); |
83c7162d XL |
818 | assert_eq!(r, e); |
819 | } | |
820 | ||
821 | #[simd_test(enable = "neon")] | |
822 | unsafe fn test_vpminq_u32() { | |
823 | let a = u32x4::new(1, 2, 3, 4); | |
824 | let b = u32x4::new(0, 3, 2, 5); | |
825 | let e = u32x4::new(1, 3, 0, 2); | |
8faf50e0 | 826 | let r: u32x4 = ::mem::transmute(vpminq_u32(::mem::transmute(a), ::mem::transmute(b))); |
83c7162d XL |
827 | assert_eq!(r, e); |
828 | } | |
829 | ||
830 | #[simd_test(enable = "neon")] | |
831 | unsafe fn test_vpmin_f32() { | |
832 | let a = f32x4::new(1., -2., 3., 4.); | |
833 | let b = f32x4::new(0., 3., 2., 5.); | |
834 | let e = f32x4::new(-2., 3., 0., 2.); | |
8faf50e0 | 835 | let r: f32x4 = ::mem::transmute(vpminq_f32(::mem::transmute(a), ::mem::transmute(b))); |
83c7162d XL |
836 | assert_eq!(r, e); |
837 | } | |
838 | ||
839 | #[simd_test(enable = "neon")] | |
840 | unsafe fn test_vpmin_f64() { | |
841 | let a = f64x2::new(1., -2.); | |
842 | let b = f64x2::new(0., 3.); | |
843 | let e = f64x2::new(-2., 0.); | |
8faf50e0 | 844 | let r: f64x2 = ::mem::transmute(vpminq_f64(::mem::transmute(a), ::mem::transmute(b))); |
83c7162d XL |
845 | assert_eq!(r, e); |
846 | } | |
847 | ||
848 | #[simd_test(enable = "neon")] | |
849 | unsafe fn test_vpmaxq_s8() { | |
850 | #[cfg_attr(rustfmt, skip)] | |
8faf50e0 | 851 | let a = i8x16::new(1, -2, 3, -4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8); |
83c7162d | 852 | #[cfg_attr(rustfmt, skip)] |
8faf50e0 | 853 | let b = i8x16::new(0, 3, 2, 5, 4, 7, 6, 9, 0, 3, 2, 5, 4, 7, 6, 9); |
83c7162d | 854 | #[cfg_attr(rustfmt, skip)] |
8faf50e0 XL |
855 | let e = i8x16::new(1, 3, 6, 8, 2, 4, 6, 8, 3, 5, 7, 9, 3, 5, 7, 9); |
856 | let r: i8x16 = ::mem::transmute(vpmaxq_s8(::mem::transmute(a), ::mem::transmute(b))); | |
83c7162d XL |
857 | assert_eq!(r, e); |
858 | } | |
859 | ||
860 | #[simd_test(enable = "neon")] | |
861 | unsafe fn test_vpmaxq_s16() { | |
862 | let a = i16x8::new(1, -2, 3, 4, 5, 6, 7, 8); | |
863 | let b = i16x8::new(0, 3, 2, 5, 4, 7, 6, 9); | |
864 | let e = i16x8::new(1, 4, 6, 8, 3, 5, 7, 9); | |
8faf50e0 | 865 | let r: i16x8 = ::mem::transmute(vpmaxq_s16(::mem::transmute(a), ::mem::transmute(b))); |
83c7162d XL |
866 | assert_eq!(r, e); |
867 | } | |
868 | ||
869 | #[simd_test(enable = "neon")] | |
870 | unsafe fn test_vpmaxq_s32() { | |
871 | let a = i32x4::new(1, -2, 3, 4); | |
872 | let b = i32x4::new(0, 3, 2, 5); | |
873 | let e = i32x4::new(1, 4, 3, 5); | |
8faf50e0 | 874 | let r: i32x4 = ::mem::transmute(vpmaxq_s32(::mem::transmute(a), ::mem::transmute(b))); |
83c7162d XL |
875 | assert_eq!(r, e); |
876 | } | |
877 | ||
878 | #[simd_test(enable = "neon")] | |
879 | unsafe fn test_vpmaxq_u8() { | |
880 | #[cfg_attr(rustfmt, skip)] | |
8faf50e0 | 881 | let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8); |
83c7162d | 882 | #[cfg_attr(rustfmt, skip)] |
8faf50e0 | 883 | let b = u8x16::new(0, 3, 2, 5, 4, 7, 6, 9, 0, 3, 2, 5, 4, 7, 6, 9); |
83c7162d | 884 | #[cfg_attr(rustfmt, skip)] |
8faf50e0 XL |
885 | let e = u8x16::new(2, 4, 6, 8, 2, 4, 6, 8, 3, 5, 7, 9, 3, 5, 7, 9); |
886 | let r: u8x16 = ::mem::transmute(vpmaxq_u8(::mem::transmute(a), ::mem::transmute(b))); | |
83c7162d XL |
887 | assert_eq!(r, e); |
888 | } | |
889 | ||
890 | #[simd_test(enable = "neon")] | |
891 | unsafe fn test_vpmaxq_u16() { | |
892 | let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); | |
893 | let b = u16x8::new(0, 3, 2, 5, 4, 7, 6, 9); | |
894 | let e = u16x8::new(2, 4, 6, 8, 3, 5, 7, 9); | |
8faf50e0 | 895 | let r: u16x8 = ::mem::transmute(vpmaxq_u16(::mem::transmute(a), ::mem::transmute(b))); |
83c7162d XL |
896 | assert_eq!(r, e); |
897 | } | |
898 | ||
899 | #[simd_test(enable = "neon")] | |
900 | unsafe fn test_vpmaxq_u32() { | |
901 | let a = u32x4::new(1, 2, 3, 4); | |
902 | let b = u32x4::new(0, 3, 2, 5); | |
903 | let e = u32x4::new(2, 4, 3, 5); | |
8faf50e0 | 904 | let r: u32x4 = ::mem::transmute(vpmaxq_u32(::mem::transmute(a), ::mem::transmute(b))); |
83c7162d XL |
905 | assert_eq!(r, e); |
906 | } | |
907 | ||
908 | #[simd_test(enable = "neon")] | |
909 | unsafe fn test_vpmax_f32() { | |
910 | let a = f32x4::new(1., -2., 3., 4.); | |
911 | let b = f32x4::new(0., 3., 2., 5.); | |
912 | let e = f32x4::new(1., 4., 3., 5.); | |
8faf50e0 | 913 | let r: f32x4 = ::mem::transmute(vpmaxq_f32(::mem::transmute(a), ::mem::transmute(b))); |
83c7162d XL |
914 | assert_eq!(r, e); |
915 | } | |
916 | ||
917 | #[simd_test(enable = "neon")] | |
918 | unsafe fn test_vpmax_f64() { | |
919 | let a = f64x2::new(1., -2.); | |
920 | let b = f64x2::new(0., 3.); | |
921 | let e = f64x2::new(1., 3.); | |
8faf50e0 | 922 | let r: f64x2 = ::mem::transmute(vpmaxq_f64(::mem::transmute(a), ::mem::transmute(b))); |
83c7162d XL |
923 | assert_eq!(r, e); |
924 | } | |
0531ce1d | 925 | } |