[rustc.git] / src / stdsimd / stdsimd / arch / detect / os / linux / cpuinfo.rs

//! Parses /proc/cpuinfo
#![cfg_attr(not(target_arch = "arm"), allow(dead_code))]

use prelude::v1::*;
use fs::File;
use io::{self, Read};

/// cpuinfo
pub struct CpuInfo {
    raw: String,
}

impl CpuInfo {
    /// Reads /proc/cpuinfo into CpuInfo.
    pub fn new() -> Result<Self, io::Error> {
        let mut file = File::open("/proc/cpuinfo")?;
        let mut cpui = Self { raw: String::new() };
        file.read_to_string(&mut cpui.raw)?;
        Ok(cpui)
    }
    /// Returns the value of the cpuinfo `field`.
    pub fn field(&self, field: &str) -> CpuInfoField {
        for l in self.raw.lines() {
            if l.trim().starts_with(field) {
                return CpuInfoField::new(l.split(": ").nth(1));
            }
        }
        CpuInfoField(None)
    }

    /// Returns the `raw` contents of `/proc/cpuinfo`
    #[cfg(test)]
    fn raw(&self) -> &String {
        &self.raw
    }

    #[cfg(test)]
    fn from_str(other: &str) -> Result<Self, ::std::io::Error> {
        Ok(Self {
            raw: String::from(other),
        })
    }
}

/// Field of cpuinfo
#[derive(Debug)]
pub struct CpuInfoField<'a>(Option<&'a str>);

impl<'a> PartialEq<&'a str> for CpuInfoField<'a> {
    fn eq(&self, other: &&'a str) -> bool {
        match self.0 {
            None => other.is_empty(),
            Some(f) => f == other.trim(),
        }
    }
}

impl<'a> CpuInfoField<'a> {
    pub fn new<'b>(v: Option<&'b str>) -> CpuInfoField<'b> {
        match v {
            None => CpuInfoField::<'b>(None),
            Some(f) => CpuInfoField::<'b>(Some(f.trim())),
        }
    }
    /// Does the field exist?
    #[cfg(test)]
    pub fn exists(&self) -> bool {
        self.0.is_some()
    }
    /// Does the field contain `other`?
    pub fn has(&self, other: &str) -> bool {
        match self.0 {
            None => other.is_empty(),
            Some(f) => {
                let other = other.trim();
                for v in f.split(' ') {
                    if v == other {
                        return true;
                    }
                }
                false
            }
        }
    }
}

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn raw_dump() {
        let cpuinfo = CpuInfo::new().unwrap();
        if cpuinfo.field("vendor_id") == "GenuineIntel" {
            assert!(cpuinfo.field("flags").exists());
            assert!(!cpuinfo.field("vendor33_id").exists());
            assert!(cpuinfo.field("flags").has("sse"));
            assert!(!cpuinfo.field("flags").has("avx314"));
        }
        println!("{}", cpuinfo.raw());
    }

    const CORE_DUO_T6500: &str = r"processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 23
model name      : Intel(R) Core(TM)2 Duo CPU     T6500  @ 2.10GHz
stepping        : 10
microcode       : 0xa0b
cpu MHz         : 1600.000
cache size      : 2048 KB
physical id     : 0
siblings        : 2
core id         : 0
cpu cores       : 2
apicid          : 0
initial apicid  : 0
fdiv_bug        : no
hlt_bug         : no
f00f_bug        : no
coma_bug        : no
fpu             : yes
fpu_exception   : yes
cpuid level     : 13
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm constant_tsc arch_perfmon pebs bts aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm sse4_1 xsave lahf_lm dtherm
bogomips        : 4190.43
clflush size    : 64
cache_alignment : 64
address sizes   : 36 bits physical, 48 bits virtual
power management:
";

    #[test]
    fn core_duo_t6500() {
        let cpuinfo = CpuInfo::from_str(CORE_DUO_T6500).unwrap();
        assert_eq!(cpuinfo.field("vendor_id"), "GenuineIntel");
        assert_eq!(cpuinfo.field("cpu family"), "6");
        assert_eq!(cpuinfo.field("model"), "23");
        assert_eq!(
            cpuinfo.field("model name"),
            "Intel(R) Core(TM)2 Duo CPU     T6500  @ 2.10GHz"
        );
        assert_eq!(
            cpuinfo.field("flags"),
            "fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm constant_tsc arch_perfmon pebs bts aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm sse4_1 xsave lahf_lm dtherm"
        );
        assert!(cpuinfo.field("flags").has("fpu"));
        assert!(cpuinfo.field("flags").has("dtherm"));
        assert!(cpuinfo.field("flags").has("sse2"));
        assert!(!cpuinfo.field("flags").has("avx"));
    }

    const ARM_CORTEX_A53: &str =
        r"Processor   : AArch64 Processor rev 3 (aarch64)
        processor   : 0
        processor   : 1
        processor   : 2
        processor   : 3
        processor   : 4
        processor   : 5
        processor   : 6
        processor   : 7
        Features    : fp asimd evtstrm aes pmull sha1 sha2 crc32
        CPU implementer : 0x41
        CPU architecture: AArch64
        CPU variant : 0x0
        CPU part    : 0xd03
        CPU revision    : 3

        Hardware    : HiKey Development Board
        ";

    #[test]
    fn arm_cortex_a53() {
        let cpuinfo = CpuInfo::from_str(ARM_CORTEX_A53).unwrap();
        assert_eq!(
            cpuinfo.field("Processor"),
            "AArch64 Processor rev 3 (aarch64)"
        );
        assert_eq!(
            cpuinfo.field("Features"),
            "fp asimd evtstrm aes pmull sha1 sha2 crc32"
        );
        assert!(cpuinfo.field("Features").has("pmull"));
        assert!(!cpuinfo.field("Features").has("neon"));
        assert!(cpuinfo.field("Features").has("asimd"));
    }

    const ARM_CORTEX_A57: &str = r"Processor	: Cortex A57 Processor rev 1 (aarch64)
processor	: 0
processor	: 1
processor	: 2
processor	: 3
Features	: fp asimd aes pmull sha1 sha2 crc32 wp half thumb fastmult vfp edsp neon vfpv3 tlsi vfpv4 idiva idivt
CPU implementer	: 0x41
CPU architecture: 8
CPU variant	: 0x1
CPU part	: 0xd07
CPU revision	: 1";

    #[test]
    fn arm_cortex_a57() {
        let cpuinfo = CpuInfo::from_str(ARM_CORTEX_A57).unwrap();
        assert_eq!(
            cpuinfo.field("Processor"),
            "Cortex A57 Processor rev 1 (aarch64)"
        );
        assert_eq!(
            cpuinfo.field("Features"),
            "fp asimd aes pmull sha1 sha2 crc32 wp half thumb fastmult vfp edsp neon vfpv3 tlsi vfpv4 idiva idivt"
        );
        assert!(cpuinfo.field("Features").has("pmull"));
        assert!(cpuinfo.field("Features").has("neon"));
        assert!(cpuinfo.field("Features").has("asimd"));
    }

    const POWER8E_POWERKVM: &str = r"processor       : 0
cpu             : POWER8E (raw), altivec supported
clock           : 3425.000000MHz
revision        : 2.1 (pvr 004b 0201)

processor       : 1
cpu             : POWER8E (raw), altivec supported
clock           : 3425.000000MHz
revision        : 2.1 (pvr 004b 0201)

processor       : 2
cpu             : POWER8E (raw), altivec supported
clock           : 3425.000000MHz
revision        : 2.1 (pvr 004b 0201)

processor       : 3
cpu             : POWER8E (raw), altivec supported
clock           : 3425.000000MHz
revision        : 2.1 (pvr 004b 0201)

timebase        : 512000000
platform        : pSeries
model           : IBM pSeries (emulated by qemu)
machine         : CHRP IBM pSeries (emulated by qemu)";

    #[test]
    fn power8_powerkvm() {
        let cpuinfo = CpuInfo::from_str(POWER8E_POWERKVM).unwrap();
        assert_eq!(cpuinfo.field("cpu"), "POWER8E (raw), altivec supported");

        assert!(cpuinfo.field("cpu").has("altivec"));
    }

    const POWER5P: &str = r"processor       : 0
cpu             : POWER5+ (gs)
clock           : 1900.098000MHz
revision        : 2.1 (pvr 003b 0201)

processor       : 1
cpu             : POWER5+ (gs)
clock           : 1900.098000MHz
revision        : 2.1 (pvr 003b 0201)

processor       : 2
cpu             : POWER5+ (gs)
clock           : 1900.098000MHz
revision        : 2.1 (pvr 003b 0201)

processor       : 3
cpu             : POWER5+ (gs)
clock           : 1900.098000MHz
revision        : 2.1 (pvr 003b 0201)

processor       : 4
cpu             : POWER5+ (gs)
clock           : 1900.098000MHz
revision        : 2.1 (pvr 003b 0201)

processor       : 5
cpu             : POWER5+ (gs)
clock           : 1900.098000MHz
revision        : 2.1 (pvr 003b 0201)

processor       : 6
cpu             : POWER5+ (gs)
clock           : 1900.098000MHz
revision        : 2.1 (pvr 003b 0201)

processor       : 7
cpu             : POWER5+ (gs)
clock           : 1900.098000MHz
revision        : 2.1 (pvr 003b 0201)

timebase        : 237331000
platform        : pSeries
machine         : CHRP IBM,9133-55A";

    #[test]
    fn power5p() {
        let cpuinfo = CpuInfo::from_str(POWER5P).unwrap();
        assert_eq!(cpuinfo.field("cpu"), "POWER5+ (gs)");

        assert!(!cpuinfo.field("cpu").has("altivec"));
    }
}
Commit	Line	Data
83c7162d XL	1	//! Parses /proc/cpuinfo
83c7162d XL	2	#![cfg_attr(not(target_arch = "arm"), allow(dead_code))]
0531ce1d XL	3
	4	use prelude::v1::*;
	5	use fs::File;
	6	use io::{self, Read};
	7
0531ce1d XL	8	/// cpuinfo
	9	pub struct CpuInfo {
	10	raw: String,
	11	}
	12
	13	impl CpuInfo {
	14	/// Reads /proc/cpuinfo into CpuInfo.
	15	pub fn new() -> Result<Self, io::Error> {
	16	let mut file = File::open("/proc/cpuinfo")?;
	17	let mut cpui = Self { raw: String::new() };
	18	file.read_to_string(&mut cpui.raw)?;
	19	Ok(cpui)
	20	}
	21	/// Returns the value of the cpuinfo `field`.
	22	pub fn field(&self, field: &str) -> CpuInfoField {
	23	for l in self.raw.lines() {
	24	if l.trim().starts_with(field) {
	25	return CpuInfoField::new(l.split(": ").nth(1));
	26	}
	27	}
	28	CpuInfoField(None)
	29	}
	30
	31	/// Returns the `raw` contents of `/proc/cpuinfo`
	32	#[cfg(test)]
	33	fn raw(&self) -> &String {
	34	&self.raw
	35	}
	36
	37	#[cfg(test)]
	38	fn from_str(other: &str) -> Result<Self, ::std::io::Error> {
	39	Ok(Self {
	40	raw: String::from(other),
	41	})
	42	}
	43	}
	44
	45	/// Field of cpuinfo
	46	#[derive(Debug)]
	47	pub struct CpuInfoField<'a>(Option<&'a str>);
	48
	49	impl<'a> PartialEq<&'a str> for CpuInfoField<'a> {
	50	fn eq(&self, other: &&'a str) -> bool {
	51	match self.0 {
	52	None => other.is_empty(),
	53	Some(f) => f == other.trim(),
	54	}
	55	}
	56	}
	57
	58	impl<'a> CpuInfoField<'a> {
	59	pub fn new<'b>(v: Option<&'b str>) -> CpuInfoField<'b> {
	60	match v {
	61	None => CpuInfoField::<'b>(None),
	62	Some(f) => CpuInfoField::<'b>(Some(f.trim())),
	63	}
	64	}
	65	/// Does the field exist?
	66	#[cfg(test)]
	67	pub fn exists(&self) -> bool {
	68	self.0.is_some()
	69	}
	70	/// Does the field contain `other`?
	71	pub fn has(&self, other: &str) -> bool {
72	match self.0 {
73	None => other.is_empty(),
74	Some(f) => {
75	let other = other.trim();
76	for v in f.split(' ') {
77	if v == other {
78	return true;
79	}
80	}
81	false
82	}
83	}
84	}
85	}
86
83c7162d	87	#[cfg(test)]
0531ce1d	88	mod tests {
0531ce1d XL	89	use super::*;
0531ce1d XL	90
0531ce1d XL	91	#[test]
	92	fn raw_dump() {
	93	let cpuinfo = CpuInfo::new().unwrap();
	94	if cpuinfo.field("vendor_id") == "GenuineIntel" {
	95	assert!(cpuinfo.field("flags").exists());
	96	assert!(!cpuinfo.field("vendor33_id").exists());
	97	assert!(cpuinfo.field("flags").has("sse"));
	98	assert!(!cpuinfo.field("flags").has("avx314"));
	99	}
	100	println!("{}", cpuinfo.raw());
	101	}
	102
	103	const CORE_DUO_T6500: &str = r"processor : 0
	104	vendor_id : GenuineIntel
	105	cpu family : 6
	106	model : 23
	107	model name : Intel(R) Core(TM)2 Duo CPU T6500 @ 2.10GHz
	108	stepping : 10
	109	microcode : 0xa0b
	110	cpu MHz : 1600.000
	111	cache size : 2048 KB
	112	physical id : 0
	113	siblings : 2
	114	core id : 0
	115	cpu cores : 2
	116	apicid : 0
	117	initial apicid : 0
	118	fdiv_bug : no
	119	hlt_bug : no
	120	f00f_bug : no
	121	coma_bug : no
	122	fpu : yes
	123	fpu_exception : yes
	124	cpuid level : 13
	125	wp : yes
	126	flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm constant_tsc arch_perfmon pebs bts aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm sse4_1 xsave lahf_lm dtherm
	127	bogomips : 4190.43
	128	clflush size : 64
	129	cache_alignment : 64
	130	address sizes : 36 bits physical, 48 bits virtual
	131	power management:
	132	";
	133
	134	#[test]
	135	fn core_duo_t6500() {
	136	let cpuinfo = CpuInfo::from_str(CORE_DUO_T6500).unwrap();
	137	assert_eq!(cpuinfo.field("vendor_id"), "GenuineIntel");
	138	assert_eq!(cpuinfo.field("cpu family"), "6");
	139	assert_eq!(cpuinfo.field("model"), "23");
	140	assert_eq!(
	141	cpuinfo.field("model name"),
	142	"Intel(R) Core(TM)2 Duo CPU T6500 @ 2.10GHz"
	143	);
	144	assert_eq!(
	145	cpuinfo.field("flags"),
	146	"fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm constant_tsc arch_perfmon pebs bts aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm sse4_1 xsave lahf_lm dtherm"
	147	);
	148	assert!(cpuinfo.field("flags").has("fpu"));
	149	assert!(cpuinfo.field("flags").has("dtherm"));
	150	assert!(cpuinfo.field("flags").has("sse2"));
	151	assert!(!cpuinfo.field("flags").has("avx"));
	152	}
	153
	154	const ARM_CORTEX_A53: &str =
155	r"Processor : AArch64 Processor rev 3 (aarch64)
156	processor : 0
157	processor : 1
158	processor : 2
159	processor : 3
160	processor : 4
161	processor : 5
162	processor : 6
163	processor : 7
164	Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
165	CPU implementer : 0x41
166	CPU architecture: AArch64
167	CPU variant : 0x0
168	CPU part : 0xd03
169	CPU revision : 3
170
171	Hardware : HiKey Development Board
172	";
173
174	#[test]
175	fn arm_cortex_a53() {
176	let cpuinfo = CpuInfo::from_str(ARM_CORTEX_A53).unwrap();
177	assert_eq!(
178	cpuinfo.field("Processor"),
179	"AArch64 Processor rev 3 (aarch64)"
180	);
181	assert_eq!(
182	cpuinfo.field("Features"),
183	"fp asimd evtstrm aes pmull sha1 sha2 crc32"
184	);
185	assert!(cpuinfo.field("Features").has("pmull"));
186	assert!(!cpuinfo.field("Features").has("neon"));
187	assert!(cpuinfo.field("Features").has("asimd"));
188	}
189
190	const ARM_CORTEX_A57: &str = r"Processor : Cortex A57 Processor rev 1 (aarch64)
191	processor : 0
192	processor : 1
193	processor : 2
194	processor : 3
195	Features : fp asimd aes pmull sha1 sha2 crc32 wp half thumb fastmult vfp edsp neon vfpv3 tlsi vfpv4 idiva idivt
196	CPU implementer : 0x41
197	CPU architecture: 8
198	CPU variant : 0x1
199	CPU part : 0xd07
200	CPU revision : 1";
201
202	#[test]
203	fn arm_cortex_a57() {
204	let cpuinfo = CpuInfo::from_str(ARM_CORTEX_A57).unwrap();
205	assert_eq!(
206	cpuinfo.field("Processor"),
207	"Cortex A57 Processor rev 1 (aarch64)"
208	);
209	assert_eq!(
210	cpuinfo.field("Features"),
211	"fp asimd aes pmull sha1 sha2 crc32 wp half thumb fastmult vfp edsp neon vfpv3 tlsi vfpv4 idiva idivt"
212	);
213	assert!(cpuinfo.field("Features").has("pmull"));
214	assert!(cpuinfo.field("Features").has("neon"));
215	assert!(cpuinfo.field("Features").has("asimd"));
216	}
217
218	const POWER8E_POWERKVM: &str = r"processor : 0
219	cpu : POWER8E (raw), altivec supported
220	clock : 3425.000000MHz
221	revision : 2.1 (pvr 004b 0201)
222
223	processor : 1
224	cpu : POWER8E (raw), altivec supported
225	clock : 3425.000000MHz
226	revision : 2.1 (pvr 004b 0201)
227
228	processor : 2
229	cpu : POWER8E (raw), altivec supported
230	clock : 3425.000000MHz
231	revision : 2.1 (pvr 004b 0201)
232
233	processor : 3
234	cpu : POWER8E (raw), altivec supported
235	clock : 3425.000000MHz
236	revision : 2.1 (pvr 004b 0201)
237
238	timebase : 512000000
239	platform : pSeries
240	model : IBM pSeries (emulated by qemu)
241	machine : CHRP IBM pSeries (emulated by qemu)";
242
243	#[test]
244	fn power8_powerkvm() {
245	let cpuinfo = CpuInfo::from_str(POWER8E_POWERKVM).unwrap();
246	assert_eq!(cpuinfo.field("cpu"), "POWER8E (raw), altivec supported");
247
248	assert!(cpuinfo.field("cpu").has("altivec"));
249	}
250
251	const POWER5P: &str = r"processor : 0
252	cpu : POWER5+ (gs)
253	clock : 1900.098000MHz
254	revision : 2.1 (pvr 003b 0201)
255
256	processor : 1
257	cpu : POWER5+ (gs)
258	clock : 1900.098000MHz
259	revision : 2.1 (pvr 003b 0201)
260
261	processor : 2
262	cpu : POWER5+ (gs)
263	clock : 1900.098000MHz
264	revision : 2.1 (pvr 003b 0201)
265
266	processor : 3
267	cpu : POWER5+ (gs)
268	clock : 1900.098000MHz
269	revision : 2.1 (pvr 003b 0201)
270
271	processor : 4
272	cpu : POWER5+ (gs)
273	clock : 1900.098000MHz
274	revision : 2.1 (pvr 003b 0201)
275
276	processor : 5
277	cpu : POWER5+ (gs)
278	clock : 1900.098000MHz
279	revision : 2.1 (pvr 003b 0201)
280
281	processor : 6
282	cpu : POWER5+ (gs)
283	clock : 1900.098000MHz
284	revision : 2.1 (pvr 003b 0201)
285
286	processor : 7
287	cpu : POWER5+ (gs)
288	clock : 1900.098000MHz
289	revision : 2.1 (pvr 003b 0201)
290
291	timebase : 237331000
292	platform : pSeries
293	machine : CHRP IBM,9133-55A";
294
295	#[test]
296	fn power5p() {
297	let cpuinfo = CpuInfo::from_str(POWER5P).unwrap();
298	assert_eq!(cpuinfo.field("cpu"), "POWER5+ (gs)");
299
300	assert!(!cpuinfo.field("cpu").has("altivec"));
301	}
302	}