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New upstream version 1.63.0+dfsg1
[rustc.git] / src / test / mir-opt / issue_73223.main.PreCodegen.32bit.diff
CommitLineData
3dfed10e
XL		 1- // MIR for `main` before PreCodegen
2+ // MIR for `main` after PreCodegen
3
4 fn main() -> () {
5 let mut _0: (); // return place in scope 0 at $DIR/issue-73223.rs:1:11: 1:11
1b1a35ee
XL		 6 let _1: i32; // in scope 0 at $DIR/issue-73223.rs:2:9: 2:14
7 let mut _2: std::option::Option<i32>; // in scope 0 at $DIR/issue-73223.rs:2:23: 2:30
8 let _3: i32; // in scope 0 at $DIR/issue-73223.rs:3:14: 3:15
923072b8
FG		 9 let mut _5: (&i32, &i32); // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
10 let mut _6: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d 11 let mut _7: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
923072b8 12 let mut _10: bool; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d 13 let mut _11: bool; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
923072b8
FG		 14 let mut _12: i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
15 let _14: !; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d
XL		 16 let mut _15: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
17 let _16: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
18 let mut _17: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
19 let _18: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
20 let mut _19: std::option::Option<std::fmt::Arguments>; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
3dfed10e 21 scope 1 {
1b1a35ee
XL		 22 debug split => _1; // in scope 1 at $DIR/issue-73223.rs:2:9: 2:14
23 let _4: std::option::Option<i32>; // in scope 1 at $DIR/issue-73223.rs:7:9: 7:14
3dfed10e 24 scope 3 {
1b1a35ee 25 debug _prev => _4; // in scope 3 at $DIR/issue-73223.rs:7:9: 7:14
923072b8 26 let _8: &i32; // in scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d 27 let _9: &i32; // in scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d 28 let mut _20: &i32; // in scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
3dfed10e 29 scope 4 {
923072b8
FG		 30 debug left_val => _8; // in scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
31 debug right_val => _9; // in scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
32 let _13: core::panicking::AssertKind; // in scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
3dfed10e 33 scope 5 {
923072b8 34 debug kind => _13; // in scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
3dfed10e
XL		 35 }
36 }
37 }
38 }
39 scope 2 {
1b1a35ee 40 debug v => _3; // in scope 2 at $DIR/issue-73223.rs:3:14: 3:15
3dfed10e 41 }
3dfed10e
XL		 42
43 bb0: {
1b1a35ee
XL		 44 StorageLive(_1); // scope 0 at $DIR/issue-73223.rs:2:9: 2:14
45 StorageLive(_2); // scope 0 at $DIR/issue-73223.rs:2:23: 2:30
04454e1e 46 Deinit(_2); // scope 0 at $DIR/issue-73223.rs:2:23: 2:30
1b1a35ee
XL		 47 ((_2 as Some).0: i32) = const 1_i32; // scope 0 at $DIR/issue-73223.rs:2:23: 2:30
48 discriminant(_2) = 1; // scope 0 at $DIR/issue-73223.rs:2:23: 2:30
49 StorageLive(_3); // scope 0 at $DIR/issue-73223.rs:3:14: 3:15
50 _3 = ((_2 as Some).0: i32); // scope 0 at $DIR/issue-73223.rs:3:14: 3:15
51 _1 = _3; // scope 2 at $DIR/issue-73223.rs:3:20: 3:21
52 StorageDead(_3); // scope 0 at $DIR/issue-73223.rs:3:20: 3:21
53 StorageDead(_2); // scope 0 at $DIR/issue-73223.rs:5:6: 5:7
6a06907d 54 StorageLive(_4); // scope 1 at $DIR/issue-73223.rs:7:9: 7:14
923072b8 55 StorageLive(_5); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d 56 StorageLive(_6); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
923072b8 57 _6 = &_1; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d 58 StorageLive(_7); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d 59 _20 = const main::promoted[0]; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
3dfed10e
XL		 60 // mir::Constant
61 // + span: $SRC_DIR/core/src/macros/mod.rs:LL:COL
5e7ed085 62 // + literal: Const { ty: &i32, val: Unevaluated(main, [], Some(promoted[0])) }
923072b8
FG		 63 _7 = _20; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
64 Deinit(_5); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
65 (_5.0: &i32) = move _6; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
66 (_5.1: &i32) = move _7; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d 67 StorageDead(_7); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
923072b8
FG		 68 StorageDead(_6); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
69 StorageLive(_8); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
70 _8 = (_5.0: &i32); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d 71 StorageLive(_9); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
923072b8
FG		 72 _9 = (_5.1: &i32); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
73 StorageLive(_10); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
3dfed10e 74 StorageLive(_11); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d 75 StorageLive(_12); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
923072b8
FG		 76 _12 = (*_8); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
77 _11 = Eq(move _12, const 1_i32); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d 78 StorageDead(_12); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
923072b8
FG		 79 _10 = Not(move _11); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
80 StorageDead(_11); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
81 switchInt(move _10) -> [false: bb2, otherwise: bb1]; // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
3dfed10e
XL		 82 }
83
84 bb1: {
923072b8
FG		 85 StorageLive(_13); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
86 StorageLive(_14); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d
XL		 87 StorageLive(_15); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
88 StorageLive(_16); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
923072b8 89 _16 = _8; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d
XL		 90 _15 = _16; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
91 StorageLive(_17); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
92 StorageLive(_18); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
923072b8 93 _18 = _9; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d
XL		 94 _17 = _18; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
95 StorageLive(_19); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
04454e1e 96 Deinit(_19); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d 97 discriminant(_19) = 0; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
923072b8 98 _14 = core::panicking::assert_failed::<i32, i32>(const core::panicking::AssertKind::Eq, move _15, move _17, move _19); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
3dfed10e
XL		 99 // mir::Constant
100 // + span: $SRC_DIR/core/src/macros/mod.rs:LL:COL
5e7ed085 101 // + literal: Const { ty: for<'r, 's, 't0> fn(core::panicking::AssertKind, &'r i32, &'s i32, Option<Arguments<'t0>>) -> ! {core::panicking::assert_failed::<i32, i32>}, val: Value(Scalar(<ZST>)) }
3dfed10e
XL		 102 // mir::Constant
103 // + span: $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d 104 // + literal: Const { ty: core::panicking::AssertKind, val: Value(Scalar(0x00)) }
3dfed10e
XL		 105 }
106
5869c6ff 107 bb2: {
923072b8 108 StorageDead(_10); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d 109 StorageDead(_9); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
923072b8
FG		 110 StorageDead(_8); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
111 StorageDead(_5); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d 112 StorageDead(_4); // scope 1 at $DIR/issue-73223.rs:9:1: 9:2
5869c6ff
XL		 113 StorageDead(_1); // scope 0 at $DIR/issue-73223.rs:9:1: 9:2
114 return; // scope 0 at $DIR/issue-73223.rs:9:2: 9:2
115 }
3dfed10e
XL		 116 }
117
backport for Debian buster