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New upstream version 1.61.0+dfsg1
[rustc.git] / src / test / mir-opt / issue_73223.main.PreCodegen.32bit.diff
CommitLineData
3dfed10e
XL		 1- // MIR for `main` before PreCodegen
2+ // MIR for `main` after PreCodegen
3
4 fn main() -> () {
5 let mut _0: (); // return place in scope 0 at $DIR/issue-73223.rs:1:11: 1:11
1b1a35ee
XL		 6 let _1: i32; // in scope 0 at $DIR/issue-73223.rs:2:9: 2:14
7 let mut _2: std::option::Option<i32>; // in scope 0 at $DIR/issue-73223.rs:2:23: 2:30
8 let _3: i32; // in scope 0 at $DIR/issue-73223.rs:3:14: 3:15
6a06907d
XL		 9 let mut _5: i32; // in scope 0 at $DIR/issue-73223.rs:7:22: 7:27
10 let mut _6: (&i32, &i32); // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
11 let mut _7: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
12 let mut _8: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
13 let mut _11: bool; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
14 let mut _12: bool; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
15 let mut _13: i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
16 let mut _15: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
17 let _16: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
18 let mut _17: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
19 let _18: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
20 let mut _19: std::option::Option<std::fmt::Arguments>; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
3dfed10e 21 scope 1 {
1b1a35ee
XL		 22 debug split => _1; // in scope 1 at $DIR/issue-73223.rs:2:9: 2:14
23 let _4: std::option::Option<i32>; // in scope 1 at $DIR/issue-73223.rs:7:9: 7:14
3dfed10e 24 scope 3 {
1b1a35ee 25 debug _prev => _4; // in scope 3 at $DIR/issue-73223.rs:7:9: 7:14
6a06907d
XL		 26 let _9: &i32; // in scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
27 let _10: &i32; // in scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
28 let mut _20: &i32; // in scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
3dfed10e 29 scope 4 {
6a06907d
XL		 30 debug left_val => _9; // in scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
31 debug right_val => _10; // in scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
32 let _14: core::panicking::AssertKind; // in scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
3dfed10e 33 scope 5 {
6a06907d 34 debug kind => _14; // in scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
3dfed10e
XL		 35 }
36 }
37 }
38 }
39 scope 2 {
1b1a35ee 40 debug v => _3; // in scope 2 at $DIR/issue-73223.rs:3:14: 3:15
3dfed10e 41 }
3dfed10e
XL		 42
43 bb0: {
1b1a35ee
XL		 44 StorageLive(_1); // scope 0 at $DIR/issue-73223.rs:2:9: 2:14
45 StorageLive(_2); // scope 0 at $DIR/issue-73223.rs:2:23: 2:30
46 ((_2 as Some).0: i32) = const 1_i32; // scope 0 at $DIR/issue-73223.rs:2:23: 2:30
47 discriminant(_2) = 1; // scope 0 at $DIR/issue-73223.rs:2:23: 2:30
48 StorageLive(_3); // scope 0 at $DIR/issue-73223.rs:3:14: 3:15
49 _3 = ((_2 as Some).0: i32); // scope 0 at $DIR/issue-73223.rs:3:14: 3:15
50 _1 = _3; // scope 2 at $DIR/issue-73223.rs:3:20: 3:21
51 StorageDead(_3); // scope 0 at $DIR/issue-73223.rs:3:20: 3:21
52 StorageDead(_2); // scope 0 at $DIR/issue-73223.rs:5:6: 5:7
6a06907d
XL		 53 StorageLive(_4); // scope 1 at $DIR/issue-73223.rs:7:9: 7:14
54 StorageLive(_5); // scope 1 at $DIR/issue-73223.rs:7:22: 7:27
55 _5 = _1; // scope 1 at $DIR/issue-73223.rs:7:22: 7:27
56 ((_4 as Some).0: i32) = move _5; // scope 1 at $DIR/issue-73223.rs:7:17: 7:28
1b1a35ee 57 discriminant(_4) = 1; // scope 1 at $DIR/issue-73223.rs:7:17: 7:28
6a06907d
XL		 58 StorageDead(_5); // scope 1 at $DIR/issue-73223.rs:7:27: 7:28
59 StorageLive(_6); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
60 StorageLive(_7); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
61 _7 = &_1; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
62 StorageLive(_8); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
63 _20 = const main::promoted[0]; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
3dfed10e
XL		 64 // mir::Constant
65 // + span: $SRC_DIR/core/src/macros/mod.rs:LL:COL
ee023bcb 66 // + literal: Const { ty: &i32, val: Unevaluated(main, [], Some(promoted[0])) }
6a06907d
XL		 67 _8 = _20; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
68 (_6.0: &i32) = move _7; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
69 (_6.1: &i32) = move _8; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
70 StorageDead(_8); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
71 StorageDead(_7); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
72 StorageLive(_9); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
73 _9 = (_6.0: &i32); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
74 StorageLive(_10); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
75 _10 = (_6.1: &i32); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
3dfed10e 76 StorageLive(_11); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d
XL		 77 StorageLive(_12); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
78 StorageLive(_13); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
79 _13 = (*_9); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
80 _12 = Eq(move _13, const 1_i32); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
81 StorageDead(_13); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
82 _11 = Not(move _12); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
83 StorageDead(_12); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
84 switchInt(move _11) -> [false: bb2, otherwise: bb1]; // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
3dfed10e
XL		 85 }
86
87 bb1: {
6a06907d
XL		 88 StorageLive(_14); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
89 discriminant(_14) = 0; // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
90 StorageLive(_15); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
91 StorageLive(_16); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
92 _16 = _9; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
93 _15 = _16; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
94 StorageLive(_17); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
95 StorageLive(_18); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
96 _18 = _10; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
97 _17 = _18; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
98 StorageLive(_19); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
99 discriminant(_19) = 0; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
100 core::panicking::assert_failed::<i32, i32>(const core::panicking::AssertKind::Eq, move _15, move _17, move _19); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
3dfed10e
XL		 101 // mir::Constant
102 // + span: $SRC_DIR/core/src/macros/mod.rs:LL:COL
ee023bcb 103 // + literal: Const { ty: for<'r, 's, 't0> fn(core::panicking::AssertKind, &'r i32, &'s i32, Option<Arguments<'t0>>) -> ! {core::panicking::assert_failed::<i32, i32>}, val: Value(Scalar(<ZST>)) }
3dfed10e
XL		 104 // mir::Constant
105 // + span: $SRC_DIR/core/src/macros/mod.rs:LL:COL
6a06907d 106 // + literal: Const { ty: core::panicking::AssertKind, val: Value(Scalar(0x00)) }
3dfed10e
XL		 107 }
108
5869c6ff 109 bb2: {
6a06907d
XL		 110 StorageDead(_11); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
111 StorageDead(_10); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
112 StorageDead(_9); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
113 StorageDead(_6); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
114 StorageDead(_4); // scope 1 at $DIR/issue-73223.rs:9:1: 9:2
5869c6ff
XL		 115 StorageDead(_1); // scope 0 at $DIR/issue-73223.rs:9:1: 9:2
116 return; // scope 0 at $DIR/issue-73223.rs:9:2: 9:2
117 }
3dfed10e
XL		 118 }
119
backport for Debian buster