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b7449926 XL |
1 | // run-pass |
2 | #![allow(non_camel_case_types)] | |
3 | ||
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4 | // ignore-emscripten FIXME(#45351) hits an LLVM assert |
5 | ||
5869c6ff | 6 | #![feature(repr_simd, platform_intrinsics)] |
e9174d1e SL |
7 | |
8 | #[repr(simd)] | |
9 | #[derive(Copy, Clone)] | |
10 | struct i32x4(pub i32, pub i32, pub i32, pub i32); | |
11 | ||
12 | #[repr(simd)] | |
13 | #[derive(Copy, Clone)] | |
fc512014 | 14 | struct U32<const N: usize>([u32; N]); |
e9174d1e SL |
15 | |
16 | #[repr(simd)] | |
17 | #[derive(Copy, Clone)] | |
18 | struct f32x4(pub f32, pub f32, pub f32, pub f32); | |
19 | ||
20 | macro_rules! all_eq { | |
21 | ($a: expr, $b: expr) => {{ | |
22 | let a = $a; | |
23 | let b = $b; | |
24 | assert!(a.0 == b.0 && a.1 == b.1 && a.2 == b.2 && a.3 == b.3); | |
25 | }} | |
26 | } | |
27 | ||
fc512014 XL |
28 | macro_rules! all_eq_ { |
29 | ($a: expr, $b: expr) => {{ | |
30 | let a = $a; | |
31 | let b = $b; | |
32 | assert!(a.0 == b.0); | |
33 | }} | |
34 | } | |
35 | ||
36 | ||
e9174d1e SL |
37 | extern "platform-intrinsic" { |
38 | fn simd_add<T>(x: T, y: T) -> T; | |
39 | fn simd_sub<T>(x: T, y: T) -> T; | |
40 | fn simd_mul<T>(x: T, y: T) -> T; | |
41 | fn simd_div<T>(x: T, y: T) -> T; | |
abe05a73 | 42 | fn simd_rem<T>(x: T, y: T) -> T; |
e9174d1e SL |
43 | fn simd_shl<T>(x: T, y: T) -> T; |
44 | fn simd_shr<T>(x: T, y: T) -> T; | |
45 | fn simd_and<T>(x: T, y: T) -> T; | |
46 | fn simd_or<T>(x: T, y: T) -> T; | |
47 | fn simd_xor<T>(x: T, y: T) -> T; | |
6a06907d XL |
48 | |
49 | fn simd_neg<T>(x: T) -> T; | |
e9174d1e SL |
50 | } |
51 | ||
52 | fn main() { | |
53 | let x1 = i32x4(1, 2, 3, 4); | |
fc512014 | 54 | let y1 = U32::<4>([1, 2, 3, 4]); |
e9174d1e SL |
55 | let z1 = f32x4(1.0, 2.0, 3.0, 4.0); |
56 | let x2 = i32x4(2, 3, 4, 5); | |
fc512014 | 57 | let y2 = U32::<4>([2, 3, 4, 5]); |
e9174d1e SL |
58 | let z2 = f32x4(2.0, 3.0, 4.0, 5.0); |
59 | ||
60 | unsafe { | |
61 | all_eq!(simd_add(x1, x2), i32x4(3, 5, 7, 9)); | |
62 | all_eq!(simd_add(x2, x1), i32x4(3, 5, 7, 9)); | |
fc512014 XL |
63 | all_eq_!(simd_add(y1, y2), U32::<4>([3, 5, 7, 9])); |
64 | all_eq_!(simd_add(y2, y1), U32::<4>([3, 5, 7, 9])); | |
e9174d1e SL |
65 | all_eq!(simd_add(z1, z2), f32x4(3.0, 5.0, 7.0, 9.0)); |
66 | all_eq!(simd_add(z2, z1), f32x4(3.0, 5.0, 7.0, 9.0)); | |
67 | ||
68 | all_eq!(simd_mul(x1, x2), i32x4(2, 6, 12, 20)); | |
69 | all_eq!(simd_mul(x2, x1), i32x4(2, 6, 12, 20)); | |
fc512014 XL |
70 | all_eq_!(simd_mul(y1, y2), U32::<4>([2, 6, 12, 20])); |
71 | all_eq_!(simd_mul(y2, y1), U32::<4>([2, 6, 12, 20])); | |
e9174d1e SL |
72 | all_eq!(simd_mul(z1, z2), f32x4(2.0, 6.0, 12.0, 20.0)); |
73 | all_eq!(simd_mul(z2, z1), f32x4(2.0, 6.0, 12.0, 20.0)); | |
74 | ||
75 | all_eq!(simd_sub(x2, x1), i32x4(1, 1, 1, 1)); | |
76 | all_eq!(simd_sub(x1, x2), i32x4(-1, -1, -1, -1)); | |
fc512014 XL |
77 | all_eq_!(simd_sub(y2, y1), U32::<4>([1, 1, 1, 1])); |
78 | all_eq_!(simd_sub(y1, y2), U32::<4>([!0, !0, !0, !0])); | |
e9174d1e SL |
79 | all_eq!(simd_sub(z2, z1), f32x4(1.0, 1.0, 1.0, 1.0)); |
80 | all_eq!(simd_sub(z1, z2), f32x4(-1.0, -1.0, -1.0, -1.0)); | |
81 | ||
abe05a73 XL |
82 | all_eq!(simd_div(x1, x1), i32x4(1, 1, 1, 1)); |
83 | all_eq!(simd_div(i32x4(2, 4, 6, 8), i32x4(2, 2, 2, 2)), x1); | |
fc512014 XL |
84 | all_eq_!(simd_div(y1, y1), U32::<4>([1, 1, 1, 1])); |
85 | all_eq_!(simd_div(U32::<4>([2, 4, 6, 8]), U32::<4>([2, 2, 2, 2])), y1); | |
abe05a73 | 86 | all_eq!(simd_div(z1, z1), f32x4(1.0, 1.0, 1.0, 1.0)); |
e9174d1e SL |
87 | all_eq!(simd_div(z1, z2), f32x4(1.0/2.0, 2.0/3.0, 3.0/4.0, 4.0/5.0)); |
88 | all_eq!(simd_div(z2, z1), f32x4(2.0/1.0, 3.0/2.0, 4.0/3.0, 5.0/4.0)); | |
89 | ||
abe05a73 XL |
90 | all_eq!(simd_rem(x1, x1), i32x4(0, 0, 0, 0)); |
91 | all_eq!(simd_rem(x2, x1), i32x4(0, 1, 1, 1)); | |
fc512014 XL |
92 | all_eq_!(simd_rem(y1, y1), U32::<4>([0, 0, 0, 0])); |
93 | all_eq_!(simd_rem(y2, y1), U32::<4>([0, 1, 1, 1])); | |
abe05a73 XL |
94 | all_eq!(simd_rem(z1, z1), f32x4(0.0, 0.0, 0.0, 0.0)); |
95 | all_eq!(simd_rem(z1, z2), z1); | |
96 | all_eq!(simd_rem(z2, z1), f32x4(0.0, 1.0, 1.0, 1.0)); | |
97 | ||
e9174d1e SL |
98 | all_eq!(simd_shl(x1, x2), i32x4(1 << 2, 2 << 3, 3 << 4, 4 << 5)); |
99 | all_eq!(simd_shl(x2, x1), i32x4(2 << 1, 3 << 2, 4 << 3, 5 << 4)); | |
fc512014 XL |
100 | all_eq_!(simd_shl(y1, y2), U32::<4>([1 << 2, 2 << 3, 3 << 4, 4 << 5])); |
101 | all_eq_!(simd_shl(y2, y1), U32::<4>([2 << 1, 3 << 2, 4 << 3, 5 << 4])); | |
e9174d1e SL |
102 | |
103 | // test right-shift by assuming left-shift is correct | |
104 | all_eq!(simd_shr(simd_shl(x1, x2), x2), x1); | |
105 | all_eq!(simd_shr(simd_shl(x2, x1), x1), x2); | |
fc512014 XL |
106 | all_eq_!(simd_shr(simd_shl(y1, y2), y2), y1); |
107 | all_eq_!(simd_shr(simd_shl(y2, y1), y1), y2); | |
e9174d1e SL |
108 | |
109 | // ensure we get logical vs. arithmetic shifts correct | |
110 | let (a, b, c, d) = (-12, -123, -1234, -12345); | |
111 | all_eq!(simd_shr(i32x4(a, b, c, d), x1), i32x4(a >> 1, b >> 2, c >> 3, d >> 4)); | |
fc512014 XL |
112 | all_eq_!(simd_shr(U32::<4>([a as u32, b as u32, c as u32, d as u32]), y1), |
113 | U32::<4>([(a as u32) >> 1, (b as u32) >> 2, (c as u32) >> 3, (d as u32) >> 4])); | |
e9174d1e SL |
114 | |
115 | all_eq!(simd_and(x1, x2), i32x4(0, 2, 0, 4)); | |
116 | all_eq!(simd_and(x2, x1), i32x4(0, 2, 0, 4)); | |
fc512014 XL |
117 | all_eq_!(simd_and(y1, y2), U32::<4>([0, 2, 0, 4])); |
118 | all_eq_!(simd_and(y2, y1), U32::<4>([0, 2, 0, 4])); | |
e9174d1e SL |
119 | |
120 | all_eq!(simd_or(x1, x2), i32x4(3, 3, 7, 5)); | |
121 | all_eq!(simd_or(x2, x1), i32x4(3, 3, 7, 5)); | |
fc512014 XL |
122 | all_eq_!(simd_or(y1, y2), U32::<4>([3, 3, 7, 5])); |
123 | all_eq_!(simd_or(y2, y1), U32::<4>([3, 3, 7, 5])); | |
e9174d1e SL |
124 | |
125 | all_eq!(simd_xor(x1, x2), i32x4(3, 1, 7, 1)); | |
126 | all_eq!(simd_xor(x2, x1), i32x4(3, 1, 7, 1)); | |
fc512014 XL |
127 | all_eq_!(simd_xor(y1, y2), U32::<4>([3, 1, 7, 1])); |
128 | all_eq_!(simd_xor(y2, y1), U32::<4>([3, 1, 7, 1])); | |
e9174d1e | 129 | |
6a06907d XL |
130 | all_eq!(simd_neg(x1), i32x4(-1, -2, -3, -4)); |
131 | all_eq!(simd_neg(x2), i32x4(-2, -3, -4, -5)); | |
132 | all_eq!(simd_neg(z1), f32x4(-1.0, -2.0, -3.0, -4.0)); | |
133 | all_eq!(simd_neg(z2), f32x4(-2.0, -3.0, -4.0, -5.0)); | |
134 | ||
e9174d1e SL |
135 | } |
136 | } |