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25ebd80f AF |
1 | /* |
2 | * QEMU Alpha CPU | |
3 | * | |
9444006f | 4 | * Copyright (c) 2007 Jocelyn Mayer |
25ebd80f AF |
5 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2.1 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see | |
19 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
20 | */ | |
21 | ||
e2e5e114 | 22 | #include "qemu/osdep.h" |
da34e65c | 23 | #include "qapi/error.h" |
0442428a | 24 | #include "qemu/qemu-print.h" |
3993c6bd | 25 | #include "cpu.h" |
63c91552 | 26 | #include "exec/exec-all.h" |
25ebd80f AF |
27 | |
28 | ||
f45748f1 AF |
29 | static void alpha_cpu_set_pc(CPUState *cs, vaddr value) |
30 | { | |
31 | AlphaCPU *cpu = ALPHA_CPU(cs); | |
32 | ||
33 | cpu->env.pc = value; | |
34 | } | |
35 | ||
e4fdf9df RH |
36 | static vaddr alpha_cpu_get_pc(CPUState *cs) |
37 | { | |
38 | AlphaCPU *cpu = ALPHA_CPU(cs); | |
39 | ||
40 | return cpu->env.pc; | |
41 | } | |
42 | ||
c0cd068f RH |
43 | static void alpha_restore_state_to_opc(CPUState *cs, |
44 | const TranslationBlock *tb, | |
45 | const uint64_t *data) | |
46 | { | |
47 | AlphaCPU *cpu = ALPHA_CPU(cs); | |
48 | ||
49 | cpu->env.pc = data[0]; | |
50 | } | |
e4fdf9df | 51 | |
8c2e1b00 AF |
52 | static bool alpha_cpu_has_work(CPUState *cs) |
53 | { | |
54 | /* Here we are checking to see if the CPU should wake up from HALT. | |
55 | We will have gotten into this state only for WTINT from PALmode. */ | |
56 | /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU | |
57 | asleep even if (some) interrupts have been asserted. For now, | |
58 | assume that if a CPU really wants to stay asleep, it will mask | |
59 | interrupts at the chipset level, which will prevent these bits | |
60 | from being set in the first place. */ | |
61 | return cs->interrupt_request & (CPU_INTERRUPT_HARD | |
62 | | CPU_INTERRUPT_TIMER | |
63 | | CPU_INTERRUPT_SMP | |
64 | | CPU_INTERRUPT_MCHK); | |
65 | } | |
66 | ||
0960be7c PC |
67 | static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) |
68 | { | |
69 | info->mach = bfd_mach_alpha_ev6; | |
70 | info->print_insn = print_insn_alpha; | |
71 | } | |
72 | ||
bd1b2828 | 73 | static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) |
0c28246f | 74 | { |
14a10fc3 | 75 | CPUState *cs = CPU(dev); |
bd1b2828 | 76 | AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev); |
ce5b1bbf LV |
77 | Error *local_err = NULL; |
78 | ||
79 | cpu_exec_realizefn(cs, &local_err); | |
80 | if (local_err != NULL) { | |
81 | error_propagate(errp, local_err); | |
82 | return; | |
83 | } | |
0c28246f | 84 | |
14a10fc3 AF |
85 | qemu_init_vcpu(cs); |
86 | ||
bd1b2828 | 87 | acc->parent_realize(dev, errp); |
0c28246f AF |
88 | } |
89 | ||
494342b3 AF |
90 | static void alpha_cpu_list_entry(gpointer data, gpointer user_data) |
91 | { | |
92 | ObjectClass *oc = data; | |
494342b3 | 93 | |
0442428a | 94 | qemu_printf(" %s\n", object_class_get_name(oc)); |
494342b3 AF |
95 | } |
96 | ||
0442428a | 97 | void alpha_cpu_list(void) |
494342b3 | 98 | { |
494342b3 AF |
99 | GSList *list; |
100 | ||
47c66009 | 101 | list = object_class_get_list_sorted(TYPE_ALPHA_CPU, false); |
0442428a MA |
102 | qemu_printf("Available CPUs:\n"); |
103 | g_slist_foreach(list, alpha_cpu_list_entry, NULL); | |
494342b3 AF |
104 | g_slist_free(list); |
105 | } | |
106 | ||
0c28246f | 107 | /* Models */ |
0c28246f AF |
108 | typedef struct AlphaCPUAlias { |
109 | const char *alias; | |
110 | const char *typename; | |
111 | } AlphaCPUAlias; | |
112 | ||
113 | static const AlphaCPUAlias alpha_cpu_aliases[] = { | |
73a25e83 IM |
114 | { "21064", ALPHA_CPU_TYPE_NAME("ev4") }, |
115 | { "21164", ALPHA_CPU_TYPE_NAME("ev5") }, | |
116 | { "21164a", ALPHA_CPU_TYPE_NAME("ev56") }, | |
117 | { "21164pc", ALPHA_CPU_TYPE_NAME("pca56") }, | |
118 | { "21264", ALPHA_CPU_TYPE_NAME("ev6") }, | |
119 | { "21264a", ALPHA_CPU_TYPE_NAME("ev67") }, | |
0c28246f AF |
120 | }; |
121 | ||
122 | static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model) | |
123 | { | |
8301ea44 | 124 | ObjectClass *oc; |
0c28246f AF |
125 | char *typename; |
126 | int i; | |
127 | ||
0c28246f | 128 | oc = object_class_by_name(cpu_model); |
a120c287 AF |
129 | if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL && |
130 | !object_class_is_abstract(oc)) { | |
0c28246f AF |
131 | return oc; |
132 | } | |
133 | ||
134 | for (i = 0; i < ARRAY_SIZE(alpha_cpu_aliases); i++) { | |
135 | if (strcmp(cpu_model, alpha_cpu_aliases[i].alias) == 0) { | |
136 | oc = object_class_by_name(alpha_cpu_aliases[i].typename); | |
a120c287 | 137 | assert(oc != NULL && !object_class_is_abstract(oc)); |
0c28246f AF |
138 | return oc; |
139 | } | |
140 | } | |
141 | ||
73a25e83 | 142 | typename = g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model); |
0c28246f AF |
143 | oc = object_class_by_name(typename); |
144 | g_free(typename); | |
a120c287 AF |
145 | if (oc != NULL && object_class_is_abstract(oc)) { |
146 | oc = NULL; | |
147 | } | |
0c28246f | 148 | |
82a3d1f8 IM |
149 | /* TODO: remove match everything nonsense */ |
150 | /* Default to ev67; no reason not to emulate insns by default. */ | |
151 | if (!oc) { | |
73a25e83 | 152 | oc = object_class_by_name(ALPHA_CPU_TYPE_NAME("ev67")); |
0c28246f | 153 | } |
bd1b2828 | 154 | |
82a3d1f8 | 155 | return oc; |
0c28246f AF |
156 | } |
157 | ||
158 | static void ev4_cpu_initfn(Object *obj) | |
159 | { | |
160 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
161 | CPUAlphaState *env = &cpu->env; | |
162 | ||
163 | env->implver = IMPLVER_2106x; | |
164 | } | |
165 | ||
0c28246f AF |
166 | static void ev5_cpu_initfn(Object *obj) |
167 | { | |
168 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
169 | CPUAlphaState *env = &cpu->env; | |
170 | ||
171 | env->implver = IMPLVER_21164; | |
172 | } | |
173 | ||
0c28246f AF |
174 | static void ev56_cpu_initfn(Object *obj) |
175 | { | |
176 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
177 | CPUAlphaState *env = &cpu->env; | |
178 | ||
179 | env->amask |= AMASK_BWX; | |
180 | } | |
181 | ||
0c28246f AF |
182 | static void pca56_cpu_initfn(Object *obj) |
183 | { | |
184 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
185 | CPUAlphaState *env = &cpu->env; | |
186 | ||
187 | env->amask |= AMASK_MVI; | |
188 | } | |
189 | ||
0c28246f AF |
190 | static void ev6_cpu_initfn(Object *obj) |
191 | { | |
192 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
193 | CPUAlphaState *env = &cpu->env; | |
194 | ||
195 | env->implver = IMPLVER_21264; | |
196 | env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP; | |
197 | } | |
198 | ||
0c28246f AF |
199 | static void ev67_cpu_initfn(Object *obj) |
200 | { | |
201 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
202 | CPUAlphaState *env = &cpu->env; | |
203 | ||
204 | env->amask |= AMASK_CIX | AMASK_PREFETCH; | |
205 | } | |
206 | ||
9444006f AF |
207 | static void alpha_cpu_initfn(Object *obj) |
208 | { | |
209 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
210 | CPUAlphaState *env = &cpu->env; | |
211 | ||
7506ed90 | 212 | cpu_set_cpustate_pointers(cpu); |
9444006f | 213 | |
bcd2625d | 214 | env->lock_addr = -1; |
9444006f | 215 | #if defined(CONFIG_USER_ONLY) |
bcd2625d | 216 | env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN; |
29eb5280 RH |
217 | cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD |
218 | | FPCR_UNFD | FPCR_INED | FPCR_DNOD | |
219 | | FPCR_DYN_NORMAL) << 32); | |
bcd2625d RH |
220 | #else |
221 | env->flags = ENV_FLAG_PAL_MODE | ENV_FLAG_FEN; | |
9444006f | 222 | #endif |
9444006f AF |
223 | } |
224 | ||
8b80bd28 PMD |
225 | #ifndef CONFIG_USER_ONLY |
226 | #include "hw/core/sysemu-cpu-ops.h" | |
227 | ||
228 | static const struct SysemuCPUOps alpha_sysemu_ops = { | |
08928c6d | 229 | .get_phys_page_debug = alpha_cpu_get_phys_page_debug, |
8b80bd28 PMD |
230 | }; |
231 | #endif | |
232 | ||
78271684 CF |
233 | #include "hw/core/tcg-cpu-ops.h" |
234 | ||
11906557 | 235 | static const struct TCGCPUOps alpha_tcg_ops = { |
78271684 | 236 | .initialize = alpha_translate_init, |
c0cd068f | 237 | .restore_state_to_opc = alpha_restore_state_to_opc, |
78271684 | 238 | |
90113883 RH |
239 | #ifdef CONFIG_USER_ONLY |
240 | .record_sigsegv = alpha_cpu_record_sigsegv, | |
e7424abc | 241 | .record_sigbus = alpha_cpu_record_sigbus, |
90113883 RH |
242 | #else |
243 | .tlb_fill = alpha_cpu_tlb_fill, | |
9354e694 | 244 | .cpu_exec_interrupt = alpha_cpu_exec_interrupt, |
78271684 CF |
245 | .do_interrupt = alpha_cpu_do_interrupt, |
246 | .do_transaction_failed = alpha_cpu_do_transaction_failed, | |
247 | .do_unaligned_access = alpha_cpu_do_unaligned_access, | |
248 | #endif /* !CONFIG_USER_ONLY */ | |
249 | }; | |
250 | ||
2b8c2754 AF |
251 | static void alpha_cpu_class_init(ObjectClass *oc, void *data) |
252 | { | |
bd1b2828 | 253 | DeviceClass *dc = DEVICE_CLASS(oc); |
2b8c2754 | 254 | CPUClass *cc = CPU_CLASS(oc); |
bd1b2828 AF |
255 | AlphaCPUClass *acc = ALPHA_CPU_CLASS(oc); |
256 | ||
bf853881 PMD |
257 | device_class_set_parent_realize(dc, alpha_cpu_realizefn, |
258 | &acc->parent_realize); | |
2b8c2754 AF |
259 | |
260 | cc->class_by_name = alpha_cpu_class_by_name; | |
8c2e1b00 | 261 | cc->has_work = alpha_cpu_has_work; |
878096ee | 262 | cc->dump_state = alpha_cpu_dump_state; |
f45748f1 | 263 | cc->set_pc = alpha_cpu_set_pc; |
e4fdf9df | 264 | cc->get_pc = alpha_cpu_get_pc; |
5b50e790 AF |
265 | cc->gdb_read_register = alpha_cpu_gdb_read_register; |
266 | cc->gdb_write_register = alpha_cpu_gdb_write_register; | |
e41c9452 | 267 | #ifndef CONFIG_USER_ONLY |
00b941e5 | 268 | dc->vmsd = &vmstate_alpha_cpu; |
8b80bd28 | 269 | cc->sysemu_ops = &alpha_sysemu_ops; |
00b941e5 | 270 | #endif |
0960be7c PC |
271 | cc->disas_set_info = alpha_cpu_disas_set_info; |
272 | ||
78271684 | 273 | cc->tcg_ops = &alpha_tcg_ops; |
a0e372f0 | 274 | cc->gdb_num_core_regs = 67; |
2b8c2754 AF |
275 | } |
276 | ||
73a25e83 IM |
277 | #define DEFINE_ALPHA_CPU_TYPE(base_type, cpu_model, initfn) \ |
278 | { \ | |
279 | .parent = base_type, \ | |
280 | .instance_init = initfn, \ | |
281 | .name = ALPHA_CPU_TYPE_NAME(cpu_model), \ | |
282 | } | |
283 | ||
284 | static const TypeInfo alpha_cpu_type_infos[] = { | |
285 | { | |
286 | .name = TYPE_ALPHA_CPU, | |
287 | .parent = TYPE_CPU, | |
288 | .instance_size = sizeof(AlphaCPU), | |
f669c992 | 289 | .instance_align = __alignof(AlphaCPU), |
73a25e83 IM |
290 | .instance_init = alpha_cpu_initfn, |
291 | .abstract = true, | |
292 | .class_size = sizeof(AlphaCPUClass), | |
293 | .class_init = alpha_cpu_class_init, | |
294 | }, | |
295 | DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev4", ev4_cpu_initfn), | |
296 | DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev5", ev5_cpu_initfn), | |
297 | DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev5"), "ev56", ev56_cpu_initfn), | |
298 | DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev56"), "pca56", | |
299 | pca56_cpu_initfn), | |
300 | DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev6", ev6_cpu_initfn), | |
301 | DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev6"), "ev67", ev67_cpu_initfn), | |
302 | DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev67"), "ev68", NULL), | |
25ebd80f AF |
303 | }; |
304 | ||
73a25e83 | 305 | DEFINE_TYPES(alpha_cpu_type_infos) |