]>
Commit | Line | Data |
---|---|---|
4c9649a9 JM |
1 | /* |
2 | * Alpha emulation cpu definitions for qemu. | |
5fafdf24 | 3 | * |
4c9649a9 JM |
4 | * Copyright (c) 2007 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
4c9649a9 JM |
18 | */ |
19 | ||
07f5a258 MA |
20 | #ifndef ALPHA_CPU_H |
21 | #define ALPHA_CPU_H | |
4c9649a9 | 22 | |
2c976297 | 23 | #include "qemu-common.h" |
1dc8e6b7 | 24 | #include "cpu-qom.h" |
74433bf0 | 25 | #include "exec/cpu-defs.h" |
4c9649a9 | 26 | |
d94f0a8e | 27 | #define ALIGNED_ONLY |
4c9649a9 | 28 | |
5ee4f3c2 RH |
29 | /* Alpha processors have a weak memory model */ |
30 | #define TCG_GUEST_DEFAULT_MO (0) | |
31 | ||
4c9649a9 JM |
32 | #define ICACHE_LINE_SIZE 32 |
33 | #define DCACHE_LINE_SIZE 32 | |
34 | ||
4c9649a9 JM |
35 | /* Alpha major type */ |
36 | enum { | |
37 | ALPHA_EV3 = 1, | |
38 | ALPHA_EV4 = 2, | |
39 | ALPHA_SIM = 3, | |
40 | ALPHA_LCA = 4, | |
41 | ALPHA_EV5 = 5, /* 21164 */ | |
42 | ALPHA_EV45 = 6, /* 21064A */ | |
43 | ALPHA_EV56 = 7, /* 21164A */ | |
44 | }; | |
45 | ||
46 | /* EV4 minor type */ | |
47 | enum { | |
48 | ALPHA_EV4_2 = 0, | |
49 | ALPHA_EV4_3 = 1, | |
50 | }; | |
51 | ||
52 | /* LCA minor type */ | |
53 | enum { | |
54 | ALPHA_LCA_1 = 1, /* 21066 */ | |
55 | ALPHA_LCA_2 = 2, /* 20166 */ | |
56 | ALPHA_LCA_3 = 3, /* 21068 */ | |
57 | ALPHA_LCA_4 = 4, /* 21068 */ | |
58 | ALPHA_LCA_5 = 5, /* 21066A */ | |
59 | ALPHA_LCA_6 = 6, /* 21068A */ | |
60 | }; | |
61 | ||
62 | /* EV5 minor type */ | |
63 | enum { | |
64 | ALPHA_EV5_1 = 1, /* Rev BA, CA */ | |
65 | ALPHA_EV5_2 = 2, /* Rev DA, EA */ | |
66 | ALPHA_EV5_3 = 3, /* Pass 3 */ | |
67 | ALPHA_EV5_4 = 4, /* Pass 3.2 */ | |
68 | ALPHA_EV5_5 = 5, /* Pass 4 */ | |
69 | }; | |
70 | ||
71 | /* EV45 minor type */ | |
72 | enum { | |
73 | ALPHA_EV45_1 = 1, /* Pass 1 */ | |
74 | ALPHA_EV45_2 = 2, /* Pass 1.1 */ | |
75 | ALPHA_EV45_3 = 3, /* Pass 2 */ | |
76 | }; | |
77 | ||
78 | /* EV56 minor type */ | |
79 | enum { | |
80 | ALPHA_EV56_1 = 1, /* Pass 1 */ | |
81 | ALPHA_EV56_2 = 2, /* Pass 2 */ | |
82 | }; | |
83 | ||
84 | enum { | |
85 | IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */ | |
86 | IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */ | |
87 | IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */ | |
88 | IMPLVER_21364 = 3, /* EV7 & EV79 */ | |
89 | }; | |
90 | ||
91 | enum { | |
92 | AMASK_BWX = 0x00000001, | |
93 | AMASK_FIX = 0x00000002, | |
94 | AMASK_CIX = 0x00000004, | |
95 | AMASK_MVI = 0x00000100, | |
96 | AMASK_TRAP = 0x00000200, | |
97 | AMASK_PREFETCH = 0x00001000, | |
98 | }; | |
99 | ||
100 | enum { | |
101 | VAX_ROUND_NORMAL = 0, | |
102 | VAX_ROUND_CHOPPED, | |
103 | }; | |
104 | ||
105 | enum { | |
106 | IEEE_ROUND_NORMAL = 0, | |
107 | IEEE_ROUND_DYNAMIC, | |
108 | IEEE_ROUND_PLUS, | |
109 | IEEE_ROUND_MINUS, | |
110 | IEEE_ROUND_CHOPPED, | |
111 | }; | |
112 | ||
113 | /* IEEE floating-point operations encoding */ | |
114 | /* Trap mode */ | |
115 | enum { | |
116 | FP_TRAP_I = 0x0, | |
117 | FP_TRAP_U = 0x1, | |
118 | FP_TRAP_S = 0x4, | |
119 | FP_TRAP_SU = 0x5, | |
120 | FP_TRAP_SUI = 0x7, | |
121 | }; | |
122 | ||
123 | /* Rounding mode */ | |
124 | enum { | |
125 | FP_ROUND_CHOPPED = 0x0, | |
126 | FP_ROUND_MINUS = 0x1, | |
127 | FP_ROUND_NORMAL = 0x2, | |
128 | FP_ROUND_DYNAMIC = 0x3, | |
129 | }; | |
130 | ||
f3d3aad4 RH |
131 | /* FPCR bits -- right-shifted 32 so we can use a uint32_t. */ |
132 | #define FPCR_SUM (1U << (63 - 32)) | |
133 | #define FPCR_INED (1U << (62 - 32)) | |
134 | #define FPCR_UNFD (1U << (61 - 32)) | |
135 | #define FPCR_UNDZ (1U << (60 - 32)) | |
136 | #define FPCR_DYN_SHIFT (58 - 32) | |
137 | #define FPCR_DYN_CHOPPED (0U << FPCR_DYN_SHIFT) | |
138 | #define FPCR_DYN_MINUS (1U << FPCR_DYN_SHIFT) | |
139 | #define FPCR_DYN_NORMAL (2U << FPCR_DYN_SHIFT) | |
140 | #define FPCR_DYN_PLUS (3U << FPCR_DYN_SHIFT) | |
141 | #define FPCR_DYN_MASK (3U << FPCR_DYN_SHIFT) | |
142 | #define FPCR_IOV (1U << (57 - 32)) | |
143 | #define FPCR_INE (1U << (56 - 32)) | |
144 | #define FPCR_UNF (1U << (55 - 32)) | |
145 | #define FPCR_OVF (1U << (54 - 32)) | |
146 | #define FPCR_DZE (1U << (53 - 32)) | |
147 | #define FPCR_INV (1U << (52 - 32)) | |
148 | #define FPCR_OVFD (1U << (51 - 32)) | |
149 | #define FPCR_DZED (1U << (50 - 32)) | |
150 | #define FPCR_INVD (1U << (49 - 32)) | |
151 | #define FPCR_DNZ (1U << (48 - 32)) | |
152 | #define FPCR_DNOD (1U << (47 - 32)) | |
153 | #define FPCR_STATUS_MASK (FPCR_IOV | FPCR_INE | FPCR_UNF \ | |
154 | | FPCR_OVF | FPCR_DZE | FPCR_INV) | |
ba0e276d RH |
155 | |
156 | /* The silly software trap enables implemented by the kernel emulation. | |
157 | These are more or less architecturally required, since the real hardware | |
158 | has read-as-zero bits in the FPCR when the features aren't implemented. | |
159 | For the purposes of QEMU, we pretend the FPCR can hold everything. */ | |
f3d3aad4 RH |
160 | #define SWCR_TRAP_ENABLE_INV (1U << 1) |
161 | #define SWCR_TRAP_ENABLE_DZE (1U << 2) | |
162 | #define SWCR_TRAP_ENABLE_OVF (1U << 3) | |
163 | #define SWCR_TRAP_ENABLE_UNF (1U << 4) | |
164 | #define SWCR_TRAP_ENABLE_INE (1U << 5) | |
165 | #define SWCR_TRAP_ENABLE_DNO (1U << 6) | |
166 | #define SWCR_TRAP_ENABLE_MASK ((1U << 7) - (1U << 1)) | |
167 | ||
168 | #define SWCR_MAP_DMZ (1U << 12) | |
169 | #define SWCR_MAP_UMZ (1U << 13) | |
170 | #define SWCR_MAP_MASK (SWCR_MAP_DMZ | SWCR_MAP_UMZ) | |
171 | ||
172 | #define SWCR_STATUS_INV (1U << 17) | |
173 | #define SWCR_STATUS_DZE (1U << 18) | |
174 | #define SWCR_STATUS_OVF (1U << 19) | |
175 | #define SWCR_STATUS_UNF (1U << 20) | |
176 | #define SWCR_STATUS_INE (1U << 21) | |
177 | #define SWCR_STATUS_DNO (1U << 22) | |
178 | #define SWCR_STATUS_MASK ((1U << 23) - (1U << 17)) | |
ba0e276d | 179 | |
21ba8564 RH |
180 | #define SWCR_STATUS_TO_EXCSUM_SHIFT 16 |
181 | ||
ba0e276d RH |
182 | #define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK) |
183 | ||
8417845e RH |
184 | /* MMU modes definitions */ |
185 | ||
6a73ecf5 | 186 | /* Alpha has 5 MMU modes: PALcode, Kernel, Executive, Supervisor, and User. |
8417845e RH |
187 | The Unix PALcode only exposes the kernel and user modes; presumably |
188 | executive and supervisor are used by VMS. | |
189 | ||
190 | PALcode itself uses physical mode for code and kernel mode for data; | |
191 | there are PALmode instructions that can access data via physical mode | |
192 | or via an os-installed "alternate mode", which is one of the 4 above. | |
193 | ||
6a73ecf5 RH |
194 | That said, we're only emulating Unix PALcode, and not attempting VMS, |
195 | so we don't need to implement Executive and Supervisor. QEMU's own | |
196 | PALcode cheats and usees the KSEG mapping for its code+data rather than | |
197 | physical addresses. */ | |
8417845e | 198 | |
8417845e RH |
199 | #define MMU_MODE0_SUFFIX _kernel |
200 | #define MMU_MODE1_SUFFIX _user | |
201 | #define MMU_KERNEL_IDX 0 | |
202 | #define MMU_USER_IDX 1 | |
6a73ecf5 | 203 | #define MMU_PHYS_IDX 2 |
8417845e RH |
204 | |
205 | typedef struct CPUAlphaState CPUAlphaState; | |
6ebbf390 | 206 | |
4c9649a9 JM |
207 | struct CPUAlphaState { |
208 | uint64_t ir[31]; | |
8443effb | 209 | float64 fir[31]; |
4c9649a9 | 210 | uint64_t pc; |
4c9649a9 | 211 | uint64_t unique; |
6910b8f6 | 212 | uint64_t lock_addr; |
6910b8f6 | 213 | uint64_t lock_value; |
f3d3aad4 RH |
214 | |
215 | /* The FPCR, and disassembled portions thereof. */ | |
216 | uint32_t fpcr; | |
21ba8564 RH |
217 | #ifdef CONFIG_USER_ONLY |
218 | uint32_t swcr; | |
219 | #endif | |
f3d3aad4 | 220 | uint32_t fpcr_exc_enable; |
8443effb | 221 | float_status fp_status; |
8443effb RH |
222 | uint8_t fpcr_dyn_round; |
223 | uint8_t fpcr_flush_to_zero; | |
8443effb | 224 | |
bcd2625d RH |
225 | /* Mask of PALmode, Processor State et al. Most of this gets copied |
226 | into the TranslatorBlock flags and controls code generation. */ | |
227 | uint32_t flags; | |
26b46094 | 228 | |
bcd2625d | 229 | /* The high 32-bits of the processor cycle counter. */ |
26b46094 | 230 | uint32_t pcc_ofs; |
129d8aa5 RH |
231 | |
232 | /* These pass data from the exception logic in the translator and | |
233 | helpers to the OS entry point. This is used for both system | |
234 | emulation and user-mode. */ | |
235 | uint64_t trap_arg0; | |
236 | uint64_t trap_arg1; | |
237 | uint64_t trap_arg2; | |
4c9649a9 | 238 | |
26b46094 RH |
239 | #if !defined(CONFIG_USER_ONLY) |
240 | /* The internal data required by our emulation of the Unix PALcode. */ | |
241 | uint64_t exc_addr; | |
242 | uint64_t palbr; | |
243 | uint64_t ptbr; | |
244 | uint64_t vptptr; | |
245 | uint64_t sysval; | |
246 | uint64_t usp; | |
247 | uint64_t shadow[8]; | |
248 | uint64_t scratch[24]; | |
249 | #endif | |
250 | ||
c781cf96 | 251 | /* This alarm doesn't exist in real hardware; we wish it did. */ |
c781cf96 RH |
252 | uint64_t alarm_expire; |
253 | ||
5cbdb3a3 | 254 | /* Those resources are used only in QEMU core */ |
4c9649a9 JM |
255 | CPU_COMMON |
256 | ||
4c9649a9 | 257 | int error_code; |
4c9649a9 JM |
258 | |
259 | uint32_t features; | |
260 | uint32_t amask; | |
261 | int implver; | |
4c9649a9 JM |
262 | }; |
263 | ||
1dc8e6b7 PB |
264 | /** |
265 | * AlphaCPU: | |
266 | * @env: #CPUAlphaState | |
267 | * | |
268 | * An Alpha CPU. | |
269 | */ | |
270 | struct AlphaCPU { | |
271 | /*< private >*/ | |
272 | CPUState parent_obj; | |
273 | /*< public >*/ | |
274 | ||
275 | CPUAlphaState env; | |
276 | ||
277 | /* This alarm doesn't exist in real hardware; we wish it did. */ | |
278 | QEMUTimer *alarm_timer; | |
279 | }; | |
280 | ||
281 | static inline AlphaCPU *alpha_env_get_cpu(CPUAlphaState *env) | |
282 | { | |
283 | return container_of(env, AlphaCPU, env); | |
284 | } | |
285 | ||
1dc8e6b7 PB |
286 | #define ENV_OFFSET offsetof(AlphaCPU, env) |
287 | ||
288 | #ifndef CONFIG_USER_ONLY | |
289 | extern const struct VMStateDescription vmstate_alpha_cpu; | |
290 | #endif | |
291 | ||
292 | void alpha_cpu_do_interrupt(CPUState *cpu); | |
293 | bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req); | |
90c84c56 | 294 | void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags); |
1dc8e6b7 PB |
295 | hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
296 | int alpha_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); | |
297 | int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | |
298 | void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, | |
b35399bb SS |
299 | MMUAccessType access_type, |
300 | int mmu_idx, uintptr_t retaddr); | |
1dc8e6b7 | 301 | |
494342b3 | 302 | #define cpu_list alpha_cpu_list |
9467d44c TS |
303 | #define cpu_signal_handler cpu_alpha_signal_handler |
304 | ||
4f7c64b3 | 305 | typedef CPUAlphaState CPUArchState; |
2161a612 | 306 | typedef AlphaCPU ArchCPU; |
4f7c64b3 | 307 | |
022c62cb | 308 | #include "exec/cpu-all.h" |
4c9649a9 JM |
309 | |
310 | enum { | |
311 | FEATURE_ASN = 0x00000001, | |
312 | FEATURE_SPS = 0x00000002, | |
313 | FEATURE_VIRBND = 0x00000004, | |
314 | FEATURE_TBCHK = 0x00000008, | |
315 | }; | |
316 | ||
317 | enum { | |
07b6c13b RH |
318 | EXCP_RESET, |
319 | EXCP_MCHK, | |
320 | EXCP_SMP_INTERRUPT, | |
321 | EXCP_CLK_INTERRUPT, | |
322 | EXCP_DEV_INTERRUPT, | |
323 | EXCP_MMFAULT, | |
324 | EXCP_UNALIGN, | |
325 | EXCP_OPCDEC, | |
326 | EXCP_ARITH, | |
327 | EXCP_FEN, | |
328 | EXCP_CALL_PAL, | |
4c9649a9 JM |
329 | }; |
330 | ||
6a80e088 RH |
331 | /* Alpha-specific interrupt pending bits. */ |
332 | #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0 | |
333 | #define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1 | |
334 | #define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2 | |
335 | ||
a3b9af16 RH |
336 | /* OSF/1 Page table bits. */ |
337 | enum { | |
338 | PTE_VALID = 0x0001, | |
339 | PTE_FOR = 0x0002, /* used for page protection (fault on read) */ | |
340 | PTE_FOW = 0x0004, /* used for page protection (fault on write) */ | |
341 | PTE_FOE = 0x0008, /* used for page protection (fault on exec) */ | |
342 | PTE_ASM = 0x0010, | |
343 | PTE_KRE = 0x0100, | |
344 | PTE_URE = 0x0200, | |
345 | PTE_KWE = 0x1000, | |
346 | PTE_UWE = 0x2000 | |
347 | }; | |
348 | ||
ea879fc7 RH |
349 | /* Hardware interrupt (entInt) constants. */ |
350 | enum { | |
351 | INT_K_IP, | |
352 | INT_K_CLK, | |
353 | INT_K_MCHK, | |
354 | INT_K_DEV, | |
355 | INT_K_PERF, | |
356 | }; | |
357 | ||
358 | /* Memory management (entMM) constants. */ | |
359 | enum { | |
360 | MM_K_TNV, | |
361 | MM_K_ACV, | |
362 | MM_K_FOR, | |
363 | MM_K_FOE, | |
364 | MM_K_FOW | |
365 | }; | |
366 | ||
367 | /* Arithmetic exception (entArith) constants. */ | |
368 | enum { | |
369 | EXC_M_SWC = 1, /* Software completion */ | |
370 | EXC_M_INV = 2, /* Invalid operation */ | |
371 | EXC_M_DZE = 4, /* Division by zero */ | |
372 | EXC_M_FOV = 8, /* Overflow */ | |
373 | EXC_M_UNF = 16, /* Underflow */ | |
374 | EXC_M_INE = 32, /* Inexact result */ | |
375 | EXC_M_IOV = 64 /* Integer Overflow */ | |
376 | }; | |
377 | ||
378 | /* Processor status constants. */ | |
bcd2625d RH |
379 | /* Low 3 bits are interrupt mask level. */ |
380 | #define PS_INT_MASK 7u | |
ea879fc7 | 381 | |
bcd2625d RH |
382 | /* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes; |
383 | The Unix PALcode only uses bit 4. */ | |
384 | #define PS_USER_MODE 8u | |
385 | ||
386 | /* CPUAlphaState->flags constants. These are layed out so that we | |
387 | can set or reset the pieces individually by assigning to the byte, | |
388 | or manipulated as a whole. */ | |
389 | ||
390 | #define ENV_FLAG_PAL_SHIFT 0 | |
391 | #define ENV_FLAG_PS_SHIFT 8 | |
392 | #define ENV_FLAG_RX_SHIFT 16 | |
393 | #define ENV_FLAG_FEN_SHIFT 24 | |
394 | ||
395 | #define ENV_FLAG_PAL_MODE (1u << ENV_FLAG_PAL_SHIFT) | |
396 | #define ENV_FLAG_PS_USER (PS_USER_MODE << ENV_FLAG_PS_SHIFT) | |
397 | #define ENV_FLAG_RX_FLAG (1u << ENV_FLAG_RX_SHIFT) | |
398 | #define ENV_FLAG_FEN (1u << ENV_FLAG_FEN_SHIFT) | |
399 | ||
400 | #define ENV_FLAG_TB_MASK \ | |
401 | (ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN) | |
ea879fc7 | 402 | |
97ed5ccd | 403 | static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) |
ea879fc7 | 404 | { |
bcd2625d RH |
405 | int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX; |
406 | if (env->flags & ENV_FLAG_PAL_MODE) { | |
407 | ret = MMU_KERNEL_IDX; | |
bba9bdce | 408 | } |
bcd2625d | 409 | return ret; |
ea879fc7 | 410 | } |
4c9649a9 | 411 | |
4c9649a9 JM |
412 | enum { |
413 | IR_V0 = 0, | |
414 | IR_T0 = 1, | |
415 | IR_T1 = 2, | |
416 | IR_T2 = 3, | |
417 | IR_T3 = 4, | |
418 | IR_T4 = 5, | |
419 | IR_T5 = 6, | |
420 | IR_T6 = 7, | |
421 | IR_T7 = 8, | |
422 | IR_S0 = 9, | |
423 | IR_S1 = 10, | |
424 | IR_S2 = 11, | |
425 | IR_S3 = 12, | |
426 | IR_S4 = 13, | |
427 | IR_S5 = 14, | |
428 | IR_S6 = 15, | |
a4b388ff | 429 | IR_FP = IR_S6, |
4c9649a9 JM |
430 | IR_A0 = 16, |
431 | IR_A1 = 17, | |
432 | IR_A2 = 18, | |
433 | IR_A3 = 19, | |
434 | IR_A4 = 20, | |
435 | IR_A5 = 21, | |
436 | IR_T8 = 22, | |
437 | IR_T9 = 23, | |
438 | IR_T10 = 24, | |
439 | IR_T11 = 25, | |
440 | IR_RA = 26, | |
441 | IR_T12 = 27, | |
a4b388ff | 442 | IR_PV = IR_T12, |
4c9649a9 JM |
443 | IR_AT = 28, |
444 | IR_GP = 29, | |
445 | IR_SP = 30, | |
446 | IR_ZERO = 31, | |
447 | }; | |
448 | ||
0c28246f AF |
449 | void alpha_translate_init(void); |
450 | ||
73a25e83 IM |
451 | #define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU |
452 | #define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX | |
0dacec87 | 453 | #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU |
73a25e83 | 454 | |
0442428a | 455 | void alpha_cpu_list(void); |
e96efcfc JM |
456 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
457 | signal handlers to inform the virtual CPU of exceptions. non zero | |
458 | is returned if the signal was handled by the virtual CPU. */ | |
5fafdf24 | 459 | int cpu_alpha_signal_handler(int host_signum, void *pinfo, |
e96efcfc | 460 | void *puc); |
e41c9452 RH |
461 | bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
462 | MMUAccessType access_type, int mmu_idx, | |
463 | bool probe, uintptr_t retaddr); | |
20503968 BS |
464 | void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int); |
465 | void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t); | |
95870356 | 466 | |
4d5712f1 AF |
467 | uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env); |
468 | void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val); | |
59124384 RH |
469 | uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg); |
470 | void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val); | |
5b450407 | 471 | #ifndef CONFIG_USER_ONLY |
6ad4d7ee PM |
472 | void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
473 | vaddr addr, unsigned size, | |
474 | MMUAccessType access_type, | |
475 | int mmu_idx, MemTxAttrs attrs, | |
476 | MemTxResult response, uintptr_t retaddr); | |
5b450407 | 477 | #endif |
4c9649a9 | 478 | |
4d5712f1 | 479 | static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc, |
89fee74a | 480 | target_ulong *cs_base, uint32_t *pflags) |
6b917547 AL |
481 | { |
482 | *pc = env->pc; | |
483 | *cs_base = 0; | |
bcd2625d | 484 | *pflags = env->flags & ENV_FLAG_TB_MASK; |
6b917547 AL |
485 | } |
486 | ||
21ba8564 RH |
487 | #ifdef CONFIG_USER_ONLY |
488 | /* Copied from linux ieee_swcr_to_fpcr. */ | |
489 | static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr) | |
490 | { | |
491 | uint64_t fpcr = 0; | |
492 | ||
493 | fpcr |= (swcr & SWCR_STATUS_MASK) << 35; | |
494 | fpcr |= (swcr & SWCR_MAP_DMZ) << 36; | |
495 | fpcr |= (~swcr & (SWCR_TRAP_ENABLE_INV | |
496 | | SWCR_TRAP_ENABLE_DZE | |
497 | | SWCR_TRAP_ENABLE_OVF)) << 48; | |
498 | fpcr |= (~swcr & (SWCR_TRAP_ENABLE_UNF | |
499 | | SWCR_TRAP_ENABLE_INE)) << 57; | |
500 | fpcr |= (swcr & SWCR_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0); | |
501 | fpcr |= (~swcr & SWCR_TRAP_ENABLE_DNO) << 41; | |
502 | ||
503 | return fpcr; | |
504 | } | |
505 | ||
506 | /* Copied from linux ieee_fpcr_to_swcr. */ | |
507 | static inline uint64_t alpha_ieee_fpcr_to_swcr(uint64_t fpcr) | |
508 | { | |
509 | uint64_t swcr = 0; | |
510 | ||
511 | swcr |= (fpcr >> 35) & SWCR_STATUS_MASK; | |
512 | swcr |= (fpcr >> 36) & SWCR_MAP_DMZ; | |
513 | swcr |= (~fpcr >> 48) & (SWCR_TRAP_ENABLE_INV | |
514 | | SWCR_TRAP_ENABLE_DZE | |
515 | | SWCR_TRAP_ENABLE_OVF); | |
516 | swcr |= (~fpcr >> 57) & (SWCR_TRAP_ENABLE_UNF | SWCR_TRAP_ENABLE_INE); | |
517 | swcr |= (fpcr >> 47) & SWCR_MAP_UMZ; | |
518 | swcr |= (~fpcr >> 41) & SWCR_TRAP_ENABLE_DNO; | |
519 | ||
520 | return swcr; | |
521 | } | |
522 | #endif /* CONFIG_USER_ONLY */ | |
523 | ||
07f5a258 | 524 | #endif /* ALPHA_CPU_H */ |