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dec9c2d4 AF |
1 | /* |
2 | * QEMU ARM CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
74c21bd0 | 21 | #include "qemu/osdep.h" |
181962fd | 22 | #include "target/arm/idau.h" |
0b8fa32f | 23 | #include "qemu/module.h" |
da34e65c | 24 | #include "qapi/error.h" |
f9f62e4c | 25 | #include "qapi/visitor.h" |
778c3a06 | 26 | #include "cpu.h" |
ccd38087 | 27 | #include "internals.h" |
63c91552 | 28 | #include "exec/exec-all.h" |
5de16430 | 29 | #include "hw/qdev-properties.h" |
3c30dd5a PM |
30 | #if !defined(CONFIG_USER_ONLY) |
31 | #include "hw/loader.h" | |
32 | #endif | |
9c17d615 | 33 | #include "sysemu/sysemu.h" |
14a48c1d | 34 | #include "sysemu/tcg.h" |
b3946626 | 35 | #include "sysemu/hw_accel.h" |
50a2c6e5 | 36 | #include "kvm_arm.h" |
110f6c70 | 37 | #include "disas/capstone.h" |
24f91e81 | 38 | #include "fpu/softfloat.h" |
dec9c2d4 | 39 | |
f45748f1 AF |
40 | static void arm_cpu_set_pc(CPUState *cs, vaddr value) |
41 | { | |
42 | ARMCPU *cpu = ARM_CPU(cs); | |
42f6ed91 JS |
43 | CPUARMState *env = &cpu->env; |
44 | ||
45 | if (is_a64(env)) { | |
46 | env->pc = value; | |
47 | env->thumb = 0; | |
48 | } else { | |
49 | env->regs[15] = value & ~1; | |
50 | env->thumb = value & 1; | |
51 | } | |
52 | } | |
f45748f1 | 53 | |
42f6ed91 JS |
54 | static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) |
55 | { | |
56 | ARMCPU *cpu = ARM_CPU(cs); | |
57 | CPUARMState *env = &cpu->env; | |
58 | ||
59 | /* | |
60 | * It's OK to look at env for the current mode here, because it's | |
61 | * never possible for an AArch64 TB to chain to an AArch32 TB. | |
62 | */ | |
63 | if (is_a64(env)) { | |
64 | env->pc = tb->pc; | |
65 | } else { | |
66 | env->regs[15] = tb->pc; | |
67 | } | |
f45748f1 AF |
68 | } |
69 | ||
8c2e1b00 AF |
70 | static bool arm_cpu_has_work(CPUState *cs) |
71 | { | |
543486db RH |
72 | ARMCPU *cpu = ARM_CPU(cs); |
73 | ||
062ba099 | 74 | return (cpu->power_state != PSCI_OFF) |
543486db | 75 | && cs->interrupt_request & |
136e67e9 EI |
76 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD |
77 | | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | |
78 | | CPU_INTERRUPT_EXITTB); | |
8c2e1b00 AF |
79 | } |
80 | ||
b5c53d1b AL |
81 | void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
82 | void *opaque) | |
83 | { | |
84 | ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); | |
85 | ||
86 | entry->hook = hook; | |
87 | entry->opaque = opaque; | |
88 | ||
89 | QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); | |
90 | } | |
91 | ||
08267487 | 92 | void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
bd7d00fc PM |
93 | void *opaque) |
94 | { | |
08267487 AL |
95 | ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); |
96 | ||
97 | entry->hook = hook; | |
98 | entry->opaque = opaque; | |
99 | ||
100 | QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); | |
bd7d00fc PM |
101 | } |
102 | ||
4b6a83fb PM |
103 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
104 | { | |
105 | /* Reset a single ARMCPRegInfo register */ | |
106 | ARMCPRegInfo *ri = value; | |
107 | ARMCPU *cpu = opaque; | |
108 | ||
b061a82b | 109 | if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { |
4b6a83fb PM |
110 | return; |
111 | } | |
112 | ||
113 | if (ri->resetfn) { | |
114 | ri->resetfn(&cpu->env, ri); | |
115 | return; | |
116 | } | |
117 | ||
118 | /* A zero offset is never possible as it would be regs[0] | |
119 | * so we use it to indicate that reset is being handled elsewhere. | |
120 | * This is basically only used for fields in non-core coprocessors | |
121 | * (like the pxa2xx ones). | |
122 | */ | |
123 | if (!ri->fieldoffset) { | |
124 | return; | |
125 | } | |
126 | ||
67ed771d | 127 | if (cpreg_field_is_64bit(ri)) { |
4b6a83fb PM |
128 | CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; |
129 | } else { | |
130 | CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; | |
131 | } | |
132 | } | |
133 | ||
49a66191 PM |
134 | static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) |
135 | { | |
136 | /* Purely an assertion check: we've already done reset once, | |
137 | * so now check that running the reset for the cpreg doesn't | |
138 | * change its value. This traps bugs where two different cpregs | |
139 | * both try to reset the same state field but to different values. | |
140 | */ | |
141 | ARMCPRegInfo *ri = value; | |
142 | ARMCPU *cpu = opaque; | |
143 | uint64_t oldvalue, newvalue; | |
144 | ||
145 | if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { | |
146 | return; | |
147 | } | |
148 | ||
149 | oldvalue = read_raw_cp_reg(&cpu->env, ri); | |
150 | cp_reg_reset(key, value, opaque); | |
151 | newvalue = read_raw_cp_reg(&cpu->env, ri); | |
152 | assert(oldvalue == newvalue); | |
153 | } | |
154 | ||
dec9c2d4 AF |
155 | /* CPUClass::reset() */ |
156 | static void arm_cpu_reset(CPUState *s) | |
157 | { | |
158 | ARMCPU *cpu = ARM_CPU(s); | |
159 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); | |
3c30dd5a | 160 | CPUARMState *env = &cpu->env; |
3c30dd5a | 161 | |
dec9c2d4 AF |
162 | acc->parent_reset(s); |
163 | ||
1f5c00cf AB |
164 | memset(env, 0, offsetof(CPUARMState, end_reset_fields)); |
165 | ||
4b6a83fb | 166 | g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
49a66191 PM |
167 | g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); |
168 | ||
3c30dd5a | 169 | env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
47576b94 RH |
170 | env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; |
171 | env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; | |
172 | env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; | |
3c30dd5a | 173 | |
062ba099 | 174 | cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; |
543486db RH |
175 | s->halted = cpu->start_powered_off; |
176 | ||
3c30dd5a PM |
177 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { |
178 | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; | |
179 | } | |
180 | ||
3926cc84 AG |
181 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
182 | /* 64 bit CPUs always start in 64 bit mode */ | |
183 | env->aarch64 = 1; | |
d356312f PM |
184 | #if defined(CONFIG_USER_ONLY) |
185 | env->pstate = PSTATE_MODE_EL0t; | |
14e5f106 | 186 | /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ |
137feaa9 | 187 | env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; |
276c6e81 RH |
188 | /* Enable all PAC keys. */ |
189 | env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | | |
190 | SCTLR_EnDA | SCTLR_EnDB); | |
1ae9cfbd RH |
191 | /* Enable all PAC instructions */ |
192 | env->cp15.hcr_el2 |= HCR_API; | |
193 | env->cp15.scr_el3 |= SCR_API; | |
8c6afa6a | 194 | /* and to the FP/Neon instructions */ |
7ebd5f2e | 195 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); |
802ac0e1 RH |
196 | /* and to the SVE instructions */ |
197 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); | |
198 | env->cp15.cptr_el[3] |= CPTR_EZ; | |
199 | /* with maximum vector length */ | |
adf92eab RH |
200 | env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; |
201 | env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; | |
202 | env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; | |
f6a148fe RH |
203 | /* |
204 | * Enable TBI0 and TBI1. While the real kernel only enables TBI0, | |
205 | * turning on both here will produce smaller code and otherwise | |
206 | * make no difference to the user-level emulation. | |
207 | */ | |
208 | env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); | |
d356312f | 209 | #else |
5097227c GB |
210 | /* Reset into the highest available EL */ |
211 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
212 | env->pstate = PSTATE_MODE_EL3h; | |
213 | } else if (arm_feature(env, ARM_FEATURE_EL2)) { | |
214 | env->pstate = PSTATE_MODE_EL2h; | |
215 | } else { | |
216 | env->pstate = PSTATE_MODE_EL1h; | |
217 | } | |
3933443e | 218 | env->pc = cpu->rvbar; |
8c6afa6a PM |
219 | #endif |
220 | } else { | |
221 | #if defined(CONFIG_USER_ONLY) | |
222 | /* Userspace expects access to cp10 and cp11 for FP/Neon */ | |
7ebd5f2e | 223 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); |
d356312f | 224 | #endif |
3926cc84 AG |
225 | } |
226 | ||
3c30dd5a PM |
227 | #if defined(CONFIG_USER_ONLY) |
228 | env->uncached_cpsr = ARM_CPU_MODE_USR; | |
229 | /* For user mode we must enable access to coprocessors */ | |
230 | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; | |
231 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
232 | env->cp15.c15_cpar = 3; | |
233 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
234 | env->cp15.c15_cpar = 1; | |
235 | } | |
236 | #else | |
060a65df PM |
237 | |
238 | /* | |
239 | * If the highest available EL is EL2, AArch32 will start in Hyp | |
240 | * mode; otherwise it starts in SVC. Note that if we start in | |
241 | * AArch64 then these values in the uncached_cpsr will be ignored. | |
242 | */ | |
243 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
244 | !arm_feature(env, ARM_FEATURE_EL3)) { | |
245 | env->uncached_cpsr = ARM_CPU_MODE_HYP; | |
246 | } else { | |
247 | env->uncached_cpsr = ARM_CPU_MODE_SVC; | |
248 | } | |
4cc35614 | 249 | env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; |
dc7abe4d | 250 | |
531c60a9 | 251 | if (arm_feature(env, ARM_FEATURE_M)) { |
6e3cf5df MG |
252 | uint32_t initial_msp; /* Loaded from 0x0 */ |
253 | uint32_t initial_pc; /* Loaded from 0x4 */ | |
3c30dd5a | 254 | uint8_t *rom; |
38e2a77c | 255 | uint32_t vecbase; |
6e3cf5df | 256 | |
1e577cc7 PM |
257 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
258 | env->v7m.secure = true; | |
3b2e9344 PM |
259 | } else { |
260 | /* This bit resets to 0 if security is supported, but 1 if | |
261 | * it is not. The bit is not present in v7M, but we set it | |
262 | * here so we can avoid having to make checks on it conditional | |
263 | * on ARM_FEATURE_V8 (we don't let the guest see the bit). | |
264 | */ | |
265 | env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; | |
1e577cc7 PM |
266 | } |
267 | ||
9d40cd8a | 268 | /* In v7M the reset value of this bit is IMPDEF, but ARM recommends |
2c4da50d | 269 | * that it resets to 1, so QEMU always does that rather than making |
9d40cd8a | 270 | * it dependent on CPU model. In v8M it is RES1. |
2c4da50d | 271 | */ |
9d40cd8a PM |
272 | env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; |
273 | env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; | |
274 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
275 | /* in v8M the NONBASETHRDENA bit [0] is RES1 */ | |
276 | env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; | |
277 | env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; | |
278 | } | |
22ab3460 JS |
279 | if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { |
280 | env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; | |
281 | env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; | |
282 | } | |
2c4da50d | 283 | |
d33abe82 PM |
284 | if (arm_feature(env, ARM_FEATURE_VFP)) { |
285 | env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; | |
286 | env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | | |
287 | R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; | |
288 | } | |
056f43df PM |
289 | /* Unlike A/R profile, M profile defines the reset LR value */ |
290 | env->regs[14] = 0xffffffff; | |
291 | ||
38e2a77c PM |
292 | env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; |
293 | ||
294 | /* Load the initial SP and PC from offset 0 and 4 in the vector table */ | |
295 | vecbase = env->v7m.vecbase[env->v7m.secure]; | |
0f0f8b61 | 296 | rom = rom_ptr(vecbase, 8); |
3c30dd5a | 297 | if (rom) { |
6e3cf5df MG |
298 | /* Address zero is covered by ROM which hasn't yet been |
299 | * copied into physical memory. | |
300 | */ | |
301 | initial_msp = ldl_p(rom); | |
302 | initial_pc = ldl_p(rom + 4); | |
303 | } else { | |
304 | /* Address zero not covered by a ROM blob, or the ROM blob | |
305 | * is in non-modifiable memory and this is a second reset after | |
306 | * it got copied into memory. In the latter case, rom_ptr | |
307 | * will return a NULL pointer and we should use ldl_phys instead. | |
308 | */ | |
38e2a77c PM |
309 | initial_msp = ldl_phys(s->as, vecbase); |
310 | initial_pc = ldl_phys(s->as, vecbase + 4); | |
3c30dd5a | 311 | } |
6e3cf5df MG |
312 | |
313 | env->regs[13] = initial_msp & 0xFFFFFFFC; | |
314 | env->regs[15] = initial_pc & ~1; | |
315 | env->thumb = initial_pc & 1; | |
3c30dd5a | 316 | } |
387f9806 | 317 | |
137feaa9 FA |
318 | /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently |
319 | * executing as AArch32 then check if highvecs are enabled and | |
320 | * adjust the PC accordingly. | |
321 | */ | |
322 | if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { | |
34bf7744 | 323 | env->regs[15] = 0xFFFF0000; |
387f9806 AP |
324 | } |
325 | ||
dc3c4c14 PM |
326 | /* M profile requires that reset clears the exclusive monitor; |
327 | * A profile does not, but clearing it makes more sense than having it | |
328 | * set with an exclusive access on address zero. | |
329 | */ | |
330 | arm_clear_exclusive(env); | |
331 | ||
3c30dd5a | 332 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; |
3c30dd5a | 333 | #endif |
69ceea64 | 334 | |
0e1a46bb | 335 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
69ceea64 | 336 | if (cpu->pmsav7_dregion > 0) { |
0e1a46bb | 337 | if (arm_feature(env, ARM_FEATURE_V8)) { |
62c58ee0 PM |
338 | memset(env->pmsav8.rbar[M_REG_NS], 0, |
339 | sizeof(*env->pmsav8.rbar[M_REG_NS]) | |
340 | * cpu->pmsav7_dregion); | |
341 | memset(env->pmsav8.rlar[M_REG_NS], 0, | |
342 | sizeof(*env->pmsav8.rlar[M_REG_NS]) | |
343 | * cpu->pmsav7_dregion); | |
344 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
345 | memset(env->pmsav8.rbar[M_REG_S], 0, | |
346 | sizeof(*env->pmsav8.rbar[M_REG_S]) | |
347 | * cpu->pmsav7_dregion); | |
348 | memset(env->pmsav8.rlar[M_REG_S], 0, | |
349 | sizeof(*env->pmsav8.rlar[M_REG_S]) | |
350 | * cpu->pmsav7_dregion); | |
351 | } | |
0e1a46bb PM |
352 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
353 | memset(env->pmsav7.drbar, 0, | |
354 | sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); | |
355 | memset(env->pmsav7.drsr, 0, | |
356 | sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); | |
357 | memset(env->pmsav7.dracr, 0, | |
358 | sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); | |
359 | } | |
69ceea64 | 360 | } |
1bc04a88 PM |
361 | env->pmsav7.rnr[M_REG_NS] = 0; |
362 | env->pmsav7.rnr[M_REG_S] = 0; | |
4125e6fe PM |
363 | env->pmsav8.mair0[M_REG_NS] = 0; |
364 | env->pmsav8.mair0[M_REG_S] = 0; | |
365 | env->pmsav8.mair1[M_REG_NS] = 0; | |
366 | env->pmsav8.mair1[M_REG_S] = 0; | |
69ceea64 PM |
367 | } |
368 | ||
9901c576 PM |
369 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
370 | if (cpu->sau_sregion > 0) { | |
371 | memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); | |
372 | memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); | |
373 | } | |
374 | env->sau.rnr = 0; | |
375 | /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what | |
376 | * the Cortex-M33 does. | |
377 | */ | |
378 | env->sau.ctrl = 0; | |
379 | } | |
380 | ||
3c30dd5a PM |
381 | set_flush_to_zero(1, &env->vfp.standard_fp_status); |
382 | set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); | |
383 | set_default_nan_mode(1, &env->vfp.standard_fp_status); | |
384 | set_float_detect_tininess(float_tininess_before_rounding, | |
385 | &env->vfp.fp_status); | |
386 | set_float_detect_tininess(float_tininess_before_rounding, | |
387 | &env->vfp.standard_fp_status); | |
bcc531f0 PM |
388 | set_float_detect_tininess(float_tininess_before_rounding, |
389 | &env->vfp.fp_status_f16); | |
50a2c6e5 PB |
390 | #ifndef CONFIG_USER_ONLY |
391 | if (kvm_enabled()) { | |
392 | kvm_arm_reset_vcpu(cpu); | |
393 | } | |
394 | #endif | |
9ee98ce8 | 395 | |
46747d15 | 396 | hw_breakpoint_update_all(cpu); |
9ee98ce8 | 397 | hw_watchpoint_update_all(cpu); |
dec9c2d4 AF |
398 | } |
399 | ||
e8925712 RH |
400 | bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
401 | { | |
402 | CPUClass *cc = CPU_GET_CLASS(cs); | |
012a906b GB |
403 | CPUARMState *env = cs->env_ptr; |
404 | uint32_t cur_el = arm_current_el(env); | |
405 | bool secure = arm_is_secure(env); | |
406 | uint32_t target_el; | |
407 | uint32_t excp_idx; | |
e8925712 RH |
408 | bool ret = false; |
409 | ||
012a906b GB |
410 | if (interrupt_request & CPU_INTERRUPT_FIQ) { |
411 | excp_idx = EXCP_FIQ; | |
412 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
413 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
414 | cs->exception_index = excp_idx; | |
415 | env->exception.target_el = target_el; | |
416 | cc->do_interrupt(cs); | |
417 | ret = true; | |
418 | } | |
e8925712 | 419 | } |
012a906b GB |
420 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
421 | excp_idx = EXCP_IRQ; | |
422 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
423 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
424 | cs->exception_index = excp_idx; | |
425 | env->exception.target_el = target_el; | |
426 | cc->do_interrupt(cs); | |
427 | ret = true; | |
428 | } | |
e8925712 | 429 | } |
012a906b GB |
430 | if (interrupt_request & CPU_INTERRUPT_VIRQ) { |
431 | excp_idx = EXCP_VIRQ; | |
432 | target_el = 1; | |
433 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
434 | cs->exception_index = excp_idx; | |
435 | env->exception.target_el = target_el; | |
436 | cc->do_interrupt(cs); | |
437 | ret = true; | |
438 | } | |
136e67e9 | 439 | } |
012a906b GB |
440 | if (interrupt_request & CPU_INTERRUPT_VFIQ) { |
441 | excp_idx = EXCP_VFIQ; | |
442 | target_el = 1; | |
443 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
444 | cs->exception_index = excp_idx; | |
445 | env->exception.target_el = target_el; | |
446 | cc->do_interrupt(cs); | |
447 | ret = true; | |
448 | } | |
136e67e9 | 449 | } |
e8925712 RH |
450 | |
451 | return ret; | |
452 | } | |
453 | ||
b5c633c5 PM |
454 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) |
455 | static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | |
456 | { | |
457 | CPUClass *cc = CPU_GET_CLASS(cs); | |
458 | ARMCPU *cpu = ARM_CPU(cs); | |
459 | CPUARMState *env = &cpu->env; | |
460 | bool ret = false; | |
461 | ||
f4e8e4ed | 462 | /* ARMv7-M interrupt masking works differently than -A or -R. |
7ecdaa4a PM |
463 | * There is no FIQ/IRQ distinction. Instead of I and F bits |
464 | * masking FIQ and IRQ interrupts, an exception is taken only | |
465 | * if it is higher priority than the current execution priority | |
466 | * (which depends on state like BASEPRI, FAULTMASK and the | |
467 | * currently active exception). | |
b5c633c5 PM |
468 | */ |
469 | if (interrupt_request & CPU_INTERRUPT_HARD | |
f4e8e4ed | 470 | && (armv7m_nvic_can_take_pending_exception(env->nvic))) { |
b5c633c5 PM |
471 | cs->exception_index = EXCP_IRQ; |
472 | cc->do_interrupt(cs); | |
473 | ret = true; | |
474 | } | |
475 | return ret; | |
476 | } | |
477 | #endif | |
478 | ||
89430fc6 PM |
479 | void arm_cpu_update_virq(ARMCPU *cpu) |
480 | { | |
481 | /* | |
482 | * Update the interrupt level for VIRQ, which is the logical OR of | |
483 | * the HCR_EL2.VI bit and the input line level from the GIC. | |
484 | */ | |
485 | CPUARMState *env = &cpu->env; | |
486 | CPUState *cs = CPU(cpu); | |
487 | ||
488 | bool new_state = (env->cp15.hcr_el2 & HCR_VI) || | |
489 | (env->irq_line_state & CPU_INTERRUPT_VIRQ); | |
490 | ||
491 | if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { | |
492 | if (new_state) { | |
493 | cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); | |
494 | } else { | |
495 | cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); | |
496 | } | |
497 | } | |
498 | } | |
499 | ||
500 | void arm_cpu_update_vfiq(ARMCPU *cpu) | |
501 | { | |
502 | /* | |
503 | * Update the interrupt level for VFIQ, which is the logical OR of | |
504 | * the HCR_EL2.VF bit and the input line level from the GIC. | |
505 | */ | |
506 | CPUARMState *env = &cpu->env; | |
507 | CPUState *cs = CPU(cpu); | |
508 | ||
509 | bool new_state = (env->cp15.hcr_el2 & HCR_VF) || | |
510 | (env->irq_line_state & CPU_INTERRUPT_VFIQ); | |
511 | ||
512 | if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { | |
513 | if (new_state) { | |
514 | cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); | |
515 | } else { | |
516 | cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); | |
517 | } | |
518 | } | |
519 | } | |
520 | ||
7c1840b6 PM |
521 | #ifndef CONFIG_USER_ONLY |
522 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | |
523 | { | |
524 | ARMCPU *cpu = opaque; | |
136e67e9 | 525 | CPUARMState *env = &cpu->env; |
7c1840b6 | 526 | CPUState *cs = CPU(cpu); |
136e67e9 EI |
527 | static const int mask[] = { |
528 | [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, | |
529 | [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, | |
530 | [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, | |
531 | [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ | |
532 | }; | |
7c1840b6 | 533 | |
ed89f078 PM |
534 | if (level) { |
535 | env->irq_line_state |= mask[irq]; | |
536 | } else { | |
537 | env->irq_line_state &= ~mask[irq]; | |
538 | } | |
539 | ||
7c1840b6 | 540 | switch (irq) { |
136e67e9 | 541 | case ARM_CPU_VIRQ: |
89430fc6 PM |
542 | assert(arm_feature(env, ARM_FEATURE_EL2)); |
543 | arm_cpu_update_virq(cpu); | |
544 | break; | |
136e67e9 | 545 | case ARM_CPU_VFIQ: |
f128bf29 | 546 | assert(arm_feature(env, ARM_FEATURE_EL2)); |
89430fc6 PM |
547 | arm_cpu_update_vfiq(cpu); |
548 | break; | |
136e67e9 | 549 | case ARM_CPU_IRQ: |
7c1840b6 PM |
550 | case ARM_CPU_FIQ: |
551 | if (level) { | |
136e67e9 | 552 | cpu_interrupt(cs, mask[irq]); |
7c1840b6 | 553 | } else { |
136e67e9 | 554 | cpu_reset_interrupt(cs, mask[irq]); |
7c1840b6 PM |
555 | } |
556 | break; | |
557 | default: | |
8f6fd322 | 558 | g_assert_not_reached(); |
7c1840b6 PM |
559 | } |
560 | } | |
561 | ||
562 | static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) | |
563 | { | |
564 | #ifdef CONFIG_KVM | |
565 | ARMCPU *cpu = opaque; | |
ed89f078 | 566 | CPUARMState *env = &cpu->env; |
7c1840b6 PM |
567 | CPUState *cs = CPU(cpu); |
568 | int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; | |
ed89f078 | 569 | uint32_t linestate_bit; |
7c1840b6 PM |
570 | |
571 | switch (irq) { | |
572 | case ARM_CPU_IRQ: | |
573 | kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; | |
ed89f078 | 574 | linestate_bit = CPU_INTERRUPT_HARD; |
7c1840b6 PM |
575 | break; |
576 | case ARM_CPU_FIQ: | |
577 | kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; | |
ed89f078 | 578 | linestate_bit = CPU_INTERRUPT_FIQ; |
7c1840b6 PM |
579 | break; |
580 | default: | |
8f6fd322 | 581 | g_assert_not_reached(); |
7c1840b6 | 582 | } |
ed89f078 PM |
583 | |
584 | if (level) { | |
585 | env->irq_line_state |= linestate_bit; | |
586 | } else { | |
587 | env->irq_line_state &= ~linestate_bit; | |
588 | } | |
589 | ||
7c1840b6 PM |
590 | kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; |
591 | kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); | |
592 | #endif | |
593 | } | |
84f2bed3 | 594 | |
ed50ff78 | 595 | static bool arm_cpu_virtio_is_big_endian(CPUState *cs) |
84f2bed3 PS |
596 | { |
597 | ARMCPU *cpu = ARM_CPU(cs); | |
598 | CPUARMState *env = &cpu->env; | |
84f2bed3 PS |
599 | |
600 | cpu_synchronize_state(cs); | |
ed50ff78 | 601 | return arm_cpu_data_is_big_endian(env); |
84f2bed3 PS |
602 | } |
603 | ||
7c1840b6 PM |
604 | #endif |
605 | ||
581be094 PM |
606 | static inline void set_feature(CPUARMState *env, int feature) |
607 | { | |
918f5dca | 608 | env->features |= 1ULL << feature; |
581be094 PM |
609 | } |
610 | ||
08828484 GB |
611 | static inline void unset_feature(CPUARMState *env, int feature) |
612 | { | |
613 | env->features &= ~(1ULL << feature); | |
614 | } | |
615 | ||
48440620 PC |
616 | static int |
617 | print_insn_thumb1(bfd_vma pc, disassemble_info *info) | |
618 | { | |
619 | return print_insn_arm(pc | 1, info); | |
620 | } | |
621 | ||
622 | static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) | |
623 | { | |
624 | ARMCPU *ac = ARM_CPU(cpu); | |
625 | CPUARMState *env = &ac->env; | |
7bcdbf51 | 626 | bool sctlr_b; |
48440620 PC |
627 | |
628 | if (is_a64(env)) { | |
629 | /* We might not be compiled with the A64 disassembler | |
630 | * because it needs a C++ compiler. Leave print_insn | |
631 | * unset in this case to use the caller default behaviour. | |
632 | */ | |
633 | #if defined(CONFIG_ARM_A64_DIS) | |
634 | info->print_insn = print_insn_arm_a64; | |
635 | #endif | |
110f6c70 | 636 | info->cap_arch = CS_ARCH_ARM64; |
15fa1a0a RH |
637 | info->cap_insn_unit = 4; |
638 | info->cap_insn_split = 4; | |
48440620 | 639 | } else { |
110f6c70 RH |
640 | int cap_mode; |
641 | if (env->thumb) { | |
642 | info->print_insn = print_insn_thumb1; | |
15fa1a0a RH |
643 | info->cap_insn_unit = 2; |
644 | info->cap_insn_split = 4; | |
110f6c70 RH |
645 | cap_mode = CS_MODE_THUMB; |
646 | } else { | |
647 | info->print_insn = print_insn_arm; | |
15fa1a0a RH |
648 | info->cap_insn_unit = 4; |
649 | info->cap_insn_split = 4; | |
110f6c70 RH |
650 | cap_mode = CS_MODE_ARM; |
651 | } | |
652 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
653 | cap_mode |= CS_MODE_V8; | |
654 | } | |
655 | if (arm_feature(env, ARM_FEATURE_M)) { | |
656 | cap_mode |= CS_MODE_MCLASS; | |
657 | } | |
658 | info->cap_arch = CS_ARCH_ARM; | |
659 | info->cap_mode = cap_mode; | |
48440620 | 660 | } |
7bcdbf51 RH |
661 | |
662 | sctlr_b = arm_sctlr_b(env); | |
663 | if (bswap_code(sctlr_b)) { | |
48440620 PC |
664 | #ifdef TARGET_WORDS_BIGENDIAN |
665 | info->endian = BFD_ENDIAN_LITTLE; | |
666 | #else | |
667 | info->endian = BFD_ENDIAN_BIG; | |
668 | #endif | |
669 | } | |
f7478a92 | 670 | info->flags &= ~INSN_ARM_BE32; |
7bcdbf51 RH |
671 | #ifndef CONFIG_USER_ONLY |
672 | if (sctlr_b) { | |
f7478a92 JB |
673 | info->flags |= INSN_ARM_BE32; |
674 | } | |
7bcdbf51 | 675 | #endif |
48440620 PC |
676 | } |
677 | ||
46de5913 IM |
678 | uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) |
679 | { | |
680 | uint32_t Aff1 = idx / clustersz; | |
681 | uint32_t Aff0 = idx % clustersz; | |
682 | return (Aff1 << ARM_AFF1_SHIFT) | Aff0; | |
683 | } | |
684 | ||
ac87e507 PM |
685 | static void cpreg_hashtable_data_destroy(gpointer data) |
686 | { | |
687 | /* | |
688 | * Destroy function for cpu->cp_regs hashtable data entries. | |
689 | * We must free the name string because it was g_strdup()ed in | |
690 | * add_cpreg_to_hashtable(). It's OK to cast away the 'const' | |
691 | * from r->name because we know we definitely allocated it. | |
692 | */ | |
693 | ARMCPRegInfo *r = data; | |
694 | ||
695 | g_free((void *)r->name); | |
696 | g_free(r); | |
697 | } | |
698 | ||
777dc784 PM |
699 | static void arm_cpu_initfn(Object *obj) |
700 | { | |
701 | ARMCPU *cpu = ARM_CPU(obj); | |
702 | ||
7506ed90 | 703 | cpu_set_cpustate_pointers(cpu); |
4b6a83fb | 704 | cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
ac87e507 | 705 | g_free, cpreg_hashtable_data_destroy); |
79614b78 | 706 | |
b5c53d1b | 707 | QLIST_INIT(&cpu->pre_el_change_hooks); |
08267487 AL |
708 | QLIST_INIT(&cpu->el_change_hooks); |
709 | ||
7c1840b6 PM |
710 | #ifndef CONFIG_USER_ONLY |
711 | /* Our inbound IRQ and FIQ lines */ | |
712 | if (kvm_enabled()) { | |
136e67e9 EI |
713 | /* VIRQ and VFIQ are unused with KVM but we add them to maintain |
714 | * the same interface as non-KVM CPUs. | |
715 | */ | |
716 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); | |
7c1840b6 | 717 | } else { |
136e67e9 | 718 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); |
7c1840b6 | 719 | } |
55d284af | 720 | |
55d284af PM |
721 | qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, |
722 | ARRAY_SIZE(cpu->gt_timer_outputs)); | |
aa1b3111 PM |
723 | |
724 | qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, | |
725 | "gicv3-maintenance-interrupt", 1); | |
07f48730 AJ |
726 | qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, |
727 | "pmu-interrupt", 1); | |
7c1840b6 PM |
728 | #endif |
729 | ||
54d3e3f5 PM |
730 | /* DTB consumers generally don't in fact care what the 'compatible' |
731 | * string is, so always provide some string and trust that a hypothetical | |
732 | * picky DTB consumer will also provide a helpful error message. | |
733 | */ | |
734 | cpu->dtb_compatible = "qemu,unknown"; | |
dd032e34 | 735 | cpu->psci_version = 1; /* By default assume PSCI v0.1 */ |
3541addc | 736 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; |
54d3e3f5 | 737 | |
98128601 RH |
738 | if (tcg_enabled()) { |
739 | cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ | |
79614b78 | 740 | } |
4b6a83fb PM |
741 | } |
742 | ||
07a5b0d2 | 743 | static Property arm_cpu_reset_cbar_property = |
f318cec6 | 744 | DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); |
07a5b0d2 | 745 | |
68e0a40a AP |
746 | static Property arm_cpu_reset_hivecs_property = |
747 | DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); | |
748 | ||
3933443e PM |
749 | static Property arm_cpu_rvbar_property = |
750 | DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); | |
751 | ||
c25bd18a PM |
752 | static Property arm_cpu_has_el2_property = |
753 | DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); | |
754 | ||
51942aee GB |
755 | static Property arm_cpu_has_el3_property = |
756 | DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); | |
757 | ||
3a062d57 JB |
758 | static Property arm_cpu_cfgend_property = |
759 | DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); | |
760 | ||
929e754d WH |
761 | /* use property name "pmu" to match other archs and virt tools */ |
762 | static Property arm_cpu_has_pmu_property = | |
763 | DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); | |
764 | ||
8f325f56 PC |
765 | static Property arm_cpu_has_mpu_property = |
766 | DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); | |
767 | ||
8d92e26b PM |
768 | /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, |
769 | * because the CPU initfn will have already set cpu->pmsav7_dregion to | |
770 | * the right value for that particular CPU type, and we don't want | |
771 | * to override that with an incorrect constant value. | |
772 | */ | |
3281af81 | 773 | static Property arm_cpu_pmsav7_dregion_property = |
8d92e26b PM |
774 | DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, |
775 | pmsav7_dregion, | |
776 | qdev_prop_uint32, uint32_t); | |
3281af81 | 777 | |
f9f62e4c PM |
778 | static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name, |
779 | void *opaque, Error **errp) | |
780 | { | |
781 | ARMCPU *cpu = ARM_CPU(obj); | |
782 | ||
783 | visit_type_uint32(v, name, &cpu->init_svtor, errp); | |
784 | } | |
785 | ||
786 | static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name, | |
787 | void *opaque, Error **errp) | |
788 | { | |
789 | ARMCPU *cpu = ARM_CPU(obj); | |
790 | ||
791 | visit_type_uint32(v, name, &cpu->init_svtor, errp); | |
792 | } | |
38e2a77c | 793 | |
51e5ef45 | 794 | void arm_cpu_post_init(Object *obj) |
07a5b0d2 PC |
795 | { |
796 | ARMCPU *cpu = ARM_CPU(obj); | |
07a5b0d2 | 797 | |
790a1150 PM |
798 | /* M profile implies PMSA. We have to do this here rather than |
799 | * in realize with the other feature-implication checks because | |
800 | * we look at the PMSA bit to see if we should add some properties. | |
801 | */ | |
802 | if (arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
803 | set_feature(&cpu->env, ARM_FEATURE_PMSA); | |
804 | } | |
805 | ||
f318cec6 PM |
806 | if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || |
807 | arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { | |
07a5b0d2 | 808 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, |
5433a0a8 | 809 | &error_abort); |
07a5b0d2 | 810 | } |
68e0a40a AP |
811 | |
812 | if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
813 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, | |
5433a0a8 | 814 | &error_abort); |
68e0a40a | 815 | } |
3933443e PM |
816 | |
817 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
818 | qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, | |
819 | &error_abort); | |
820 | } | |
51942aee GB |
821 | |
822 | if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { | |
823 | /* Add the has_el3 state CPU property only if EL3 is allowed. This will | |
824 | * prevent "has_el3" from existing on CPUs which cannot support EL3. | |
825 | */ | |
826 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, | |
827 | &error_abort); | |
9e273ef2 PM |
828 | |
829 | #ifndef CONFIG_USER_ONLY | |
830 | object_property_add_link(obj, "secure-memory", | |
831 | TYPE_MEMORY_REGION, | |
832 | (Object **)&cpu->secure_memory, | |
833 | qdev_prop_allow_set_link_before_realize, | |
265b578c | 834 | OBJ_PROP_LINK_STRONG, |
9e273ef2 PM |
835 | &error_abort); |
836 | #endif | |
51942aee | 837 | } |
8f325f56 | 838 | |
c25bd18a PM |
839 | if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { |
840 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, | |
841 | &error_abort); | |
842 | } | |
843 | ||
929e754d WH |
844 | if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { |
845 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, | |
846 | &error_abort); | |
847 | } | |
848 | ||
452a0955 | 849 | if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { |
8f325f56 PC |
850 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, |
851 | &error_abort); | |
3281af81 PC |
852 | if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { |
853 | qdev_property_add_static(DEVICE(obj), | |
854 | &arm_cpu_pmsav7_dregion_property, | |
855 | &error_abort); | |
856 | } | |
8f325f56 PC |
857 | } |
858 | ||
181962fd PM |
859 | if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { |
860 | object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, | |
861 | qdev_prop_allow_set_link_before_realize, | |
265b578c | 862 | OBJ_PROP_LINK_STRONG, |
181962fd | 863 | &error_abort); |
f9f62e4c PM |
864 | /* |
865 | * M profile: initial value of the Secure VTOR. We can't just use | |
866 | * a simple DEFINE_PROP_UINT32 for this because we want to permit | |
867 | * the property to be set after realize. | |
868 | */ | |
869 | object_property_add(obj, "init-svtor", "uint32", | |
870 | arm_get_init_svtor, arm_set_init_svtor, | |
871 | NULL, NULL, &error_abort); | |
181962fd PM |
872 | } |
873 | ||
3a062d57 JB |
874 | qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, |
875 | &error_abort); | |
07a5b0d2 PC |
876 | } |
877 | ||
4b6a83fb PM |
878 | static void arm_cpu_finalizefn(Object *obj) |
879 | { | |
880 | ARMCPU *cpu = ARM_CPU(obj); | |
08267487 AL |
881 | ARMELChangeHook *hook, *next; |
882 | ||
4b6a83fb | 883 | g_hash_table_destroy(cpu->cp_regs); |
08267487 | 884 | |
b5c53d1b AL |
885 | QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { |
886 | QLIST_REMOVE(hook, node); | |
887 | g_free(hook); | |
888 | } | |
08267487 AL |
889 | QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { |
890 | QLIST_REMOVE(hook, node); | |
891 | g_free(hook); | |
892 | } | |
4e7beb0c AL |
893 | #ifndef CONFIG_USER_ONLY |
894 | if (cpu->pmu_timer) { | |
895 | timer_del(cpu->pmu_timer); | |
896 | timer_deinit(cpu->pmu_timer); | |
897 | timer_free(cpu->pmu_timer); | |
898 | } | |
899 | #endif | |
777dc784 PM |
900 | } |
901 | ||
14969266 | 902 | static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
581be094 | 903 | { |
14a10fc3 | 904 | CPUState *cs = CPU(dev); |
14969266 AF |
905 | ARMCPU *cpu = ARM_CPU(dev); |
906 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); | |
581be094 | 907 | CPUARMState *env = &cpu->env; |
e97da98f | 908 | int pagebits; |
ce5b1bbf | 909 | Error *local_err = NULL; |
0f8d06f1 | 910 | bool no_aa32 = false; |
ce5b1bbf | 911 | |
c4487d76 PM |
912 | /* If we needed to query the host kernel for the CPU features |
913 | * then it's possible that might have failed in the initfn, but | |
914 | * this is the first point where we can report it. | |
915 | */ | |
916 | if (cpu->host_cpu_probe_failed) { | |
917 | if (!kvm_enabled()) { | |
918 | error_setg(errp, "The 'host' CPU type can only be used with KVM"); | |
919 | } else { | |
920 | error_setg(errp, "Failed to retrieve host CPU features"); | |
921 | } | |
922 | return; | |
923 | } | |
924 | ||
95f87565 PM |
925 | #ifndef CONFIG_USER_ONLY |
926 | /* The NVIC and M-profile CPU are two halves of a single piece of | |
927 | * hardware; trying to use one without the other is a command line | |
928 | * error and will result in segfaults if not caught here. | |
929 | */ | |
930 | if (arm_feature(env, ARM_FEATURE_M)) { | |
931 | if (!env->nvic) { | |
932 | error_setg(errp, "This board cannot be used with Cortex-M CPUs"); | |
933 | return; | |
934 | } | |
935 | } else { | |
936 | if (env->nvic) { | |
937 | error_setg(errp, "This board can only be used with Cortex-M CPUs"); | |
938 | return; | |
939 | } | |
940 | } | |
397cd31f PM |
941 | |
942 | cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, | |
943 | arm_gt_ptimer_cb, cpu); | |
944 | cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, | |
945 | arm_gt_vtimer_cb, cpu); | |
946 | cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, | |
947 | arm_gt_htimer_cb, cpu); | |
948 | cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, | |
949 | arm_gt_stimer_cb, cpu); | |
95f87565 PM |
950 | #endif |
951 | ||
ce5b1bbf LV |
952 | cpu_exec_realizefn(cs, &local_err); |
953 | if (local_err != NULL) { | |
954 | error_propagate(errp, local_err); | |
955 | return; | |
956 | } | |
14969266 | 957 | |
581be094 | 958 | /* Some features automatically imply others: */ |
81e69fb0 | 959 | if (arm_feature(env, ARM_FEATURE_V8)) { |
5256df88 RH |
960 | if (arm_feature(env, ARM_FEATURE_M)) { |
961 | set_feature(env, ARM_FEATURE_V7); | |
962 | } else { | |
963 | set_feature(env, ARM_FEATURE_V7VE); | |
964 | } | |
5110e683 | 965 | } |
0f8d06f1 RH |
966 | |
967 | /* | |
968 | * There exist AArch64 cpus without AArch32 support. When KVM | |
969 | * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. | |
970 | * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. | |
971 | */ | |
972 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
973 | no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); | |
974 | } | |
975 | ||
5110e683 AL |
976 | if (arm_feature(env, ARM_FEATURE_V7VE)) { |
977 | /* v7 Virtualization Extensions. In real hardware this implies | |
978 | * EL2 and also the presence of the Security Extensions. | |
979 | * For QEMU, for backwards-compatibility we implement some | |
980 | * CPUs or CPU configs which have no actual EL2 or EL3 but do | |
981 | * include the various other features that V7VE implies. | |
982 | * Presence of EL2 itself is ARM_FEATURE_EL2, and of the | |
983 | * Security Extensions is ARM_FEATURE_EL3. | |
984 | */ | |
0f8d06f1 | 985 | assert(no_aa32 || cpu_isar_feature(arm_div, cpu)); |
81e69fb0 | 986 | set_feature(env, ARM_FEATURE_LPAE); |
5110e683 | 987 | set_feature(env, ARM_FEATURE_V7); |
81e69fb0 | 988 | } |
581be094 PM |
989 | if (arm_feature(env, ARM_FEATURE_V7)) { |
990 | set_feature(env, ARM_FEATURE_VAPA); | |
991 | set_feature(env, ARM_FEATURE_THUMB2); | |
81bdde9d | 992 | set_feature(env, ARM_FEATURE_MPIDR); |
581be094 PM |
993 | if (!arm_feature(env, ARM_FEATURE_M)) { |
994 | set_feature(env, ARM_FEATURE_V6K); | |
995 | } else { | |
996 | set_feature(env, ARM_FEATURE_V6); | |
997 | } | |
91db4642 CLG |
998 | |
999 | /* Always define VBAR for V7 CPUs even if it doesn't exist in | |
1000 | * non-EL3 configs. This is needed by some legacy boards. | |
1001 | */ | |
1002 | set_feature(env, ARM_FEATURE_VBAR); | |
581be094 PM |
1003 | } |
1004 | if (arm_feature(env, ARM_FEATURE_V6K)) { | |
1005 | set_feature(env, ARM_FEATURE_V6); | |
1006 | set_feature(env, ARM_FEATURE_MVFR); | |
1007 | } | |
1008 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
1009 | set_feature(env, ARM_FEATURE_V5); | |
1010 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
0f8d06f1 | 1011 | assert(no_aa32 || cpu_isar_feature(jazelle, cpu)); |
581be094 PM |
1012 | set_feature(env, ARM_FEATURE_AUXCR); |
1013 | } | |
1014 | } | |
1015 | if (arm_feature(env, ARM_FEATURE_V5)) { | |
1016 | set_feature(env, ARM_FEATURE_V4T); | |
1017 | } | |
581be094 PM |
1018 | if (arm_feature(env, ARM_FEATURE_VFP4)) { |
1019 | set_feature(env, ARM_FEATURE_VFP3); | |
1020 | } | |
1021 | if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
1022 | set_feature(env, ARM_FEATURE_VFP); | |
1023 | } | |
de9b05b8 | 1024 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
bdcc150d | 1025 | set_feature(env, ARM_FEATURE_V7MP); |
de9b05b8 PM |
1026 | set_feature(env, ARM_FEATURE_PXN); |
1027 | } | |
f318cec6 PM |
1028 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { |
1029 | set_feature(env, ARM_FEATURE_CBAR); | |
1030 | } | |
62b44f05 AR |
1031 | if (arm_feature(env, ARM_FEATURE_THUMB2) && |
1032 | !arm_feature(env, ARM_FEATURE_M)) { | |
1033 | set_feature(env, ARM_FEATURE_THUMB_DSP); | |
1034 | } | |
2ceb98c0 | 1035 | |
ea7ac69d PM |
1036 | /* |
1037 | * We rely on no XScale CPU having VFP so we can use the same bits in the | |
1038 | * TB flags field for VECSTRIDE and XSCALE_CPAR. | |
1039 | */ | |
1040 | assert(!(arm_feature(env, ARM_FEATURE_VFP) && | |
1041 | arm_feature(env, ARM_FEATURE_XSCALE))); | |
1042 | ||
e97da98f PM |
1043 | if (arm_feature(env, ARM_FEATURE_V7) && |
1044 | !arm_feature(env, ARM_FEATURE_M) && | |
452a0955 | 1045 | !arm_feature(env, ARM_FEATURE_PMSA)) { |
e97da98f PM |
1046 | /* v7VMSA drops support for the old ARMv5 tiny pages, so we |
1047 | * can use 4K pages. | |
1048 | */ | |
1049 | pagebits = 12; | |
1050 | } else { | |
1051 | /* For CPUs which might have tiny 1K pages, or which have an | |
1052 | * MPU and might have small region sizes, stick with 1K pages. | |
1053 | */ | |
1054 | pagebits = 10; | |
1055 | } | |
1056 | if (!set_preferred_target_page_bits(pagebits)) { | |
1057 | /* This can only ever happen for hotplugging a CPU, or if | |
1058 | * the board code incorrectly creates a CPU which it has | |
1059 | * promised via minimum_page_size that it will not. | |
1060 | */ | |
1061 | error_setg(errp, "This CPU requires a smaller page size than the " | |
1062 | "system is using"); | |
1063 | return; | |
1064 | } | |
1065 | ||
ce5b1bbf LV |
1066 | /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. |
1067 | * We don't support setting cluster ID ([16..23]) (known as Aff2 | |
1068 | * in later ARM ARM versions), or any of the higher affinity level fields, | |
1069 | * so these bits always RAZ. | |
1070 | */ | |
1071 | if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { | |
46de5913 IM |
1072 | cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, |
1073 | ARM_DEFAULT_CPUS_PER_CLUSTER); | |
ce5b1bbf LV |
1074 | } |
1075 | ||
68e0a40a AP |
1076 | if (cpu->reset_hivecs) { |
1077 | cpu->reset_sctlr |= (1 << 13); | |
1078 | } | |
1079 | ||
3a062d57 JB |
1080 | if (cpu->cfgend) { |
1081 | if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { | |
1082 | cpu->reset_sctlr |= SCTLR_EE; | |
1083 | } else { | |
1084 | cpu->reset_sctlr |= SCTLR_B; | |
1085 | } | |
1086 | } | |
1087 | ||
51942aee GB |
1088 | if (!cpu->has_el3) { |
1089 | /* If the has_el3 CPU property is disabled then we need to disable the | |
1090 | * feature. | |
1091 | */ | |
1092 | unset_feature(env, ARM_FEATURE_EL3); | |
1093 | ||
1094 | /* Disable the security extension feature bits in the processor feature | |
3d5c84ff | 1095 | * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. |
51942aee GB |
1096 | */ |
1097 | cpu->id_pfr1 &= ~0xf0; | |
47576b94 | 1098 | cpu->isar.id_aa64pfr0 &= ~0xf000; |
51942aee GB |
1099 | } |
1100 | ||
c25bd18a PM |
1101 | if (!cpu->has_el2) { |
1102 | unset_feature(env, ARM_FEATURE_EL2); | |
1103 | } | |
1104 | ||
d6f02ce3 | 1105 | if (!cpu->has_pmu) { |
929e754d | 1106 | unset_feature(env, ARM_FEATURE_PMU); |
57a4a11b AL |
1107 | } |
1108 | if (arm_feature(env, ARM_FEATURE_PMU)) { | |
bf8d0969 | 1109 | pmu_init(cpu); |
57a4a11b AL |
1110 | |
1111 | if (!kvm_enabled()) { | |
1112 | arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); | |
1113 | arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); | |
1114 | } | |
4e7beb0c AL |
1115 | |
1116 | #ifndef CONFIG_USER_ONLY | |
1117 | cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, | |
1118 | cpu); | |
1119 | #endif | |
57a4a11b | 1120 | } else { |
2b3ffa92 | 1121 | cpu->id_aa64dfr0 &= ~0xf00; |
a46118fc | 1122 | cpu->id_dfr0 &= ~(0xf << 24); |
57a4a11b AL |
1123 | cpu->pmceid0 = 0; |
1124 | cpu->pmceid1 = 0; | |
929e754d WH |
1125 | } |
1126 | ||
3c2f7bb3 PM |
1127 | if (!arm_feature(env, ARM_FEATURE_EL2)) { |
1128 | /* Disable the hypervisor feature bits in the processor feature | |
1129 | * registers if we don't have EL2. These are id_pfr1[15:12] and | |
1130 | * id_aa64pfr0_el1[11:8]. | |
1131 | */ | |
47576b94 | 1132 | cpu->isar.id_aa64pfr0 &= ~0xf00; |
3c2f7bb3 PM |
1133 | cpu->id_pfr1 &= ~0xf000; |
1134 | } | |
1135 | ||
f50cd314 PM |
1136 | /* MPU can be configured out of a PMSA CPU either by setting has-mpu |
1137 | * to false or by setting pmsav7-dregion to 0. | |
1138 | */ | |
8f325f56 | 1139 | if (!cpu->has_mpu) { |
f50cd314 PM |
1140 | cpu->pmsav7_dregion = 0; |
1141 | } | |
1142 | if (cpu->pmsav7_dregion == 0) { | |
1143 | cpu->has_mpu = false; | |
8f325f56 PC |
1144 | } |
1145 | ||
452a0955 | 1146 | if (arm_feature(env, ARM_FEATURE_PMSA) && |
3281af81 PC |
1147 | arm_feature(env, ARM_FEATURE_V7)) { |
1148 | uint32_t nr = cpu->pmsav7_dregion; | |
1149 | ||
1150 | if (nr > 0xff) { | |
9af9e0fe | 1151 | error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); |
3281af81 PC |
1152 | return; |
1153 | } | |
6cb0b013 PC |
1154 | |
1155 | if (nr) { | |
0e1a46bb PM |
1156 | if (arm_feature(env, ARM_FEATURE_V8)) { |
1157 | /* PMSAv8 */ | |
62c58ee0 PM |
1158 | env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); |
1159 | env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); | |
1160 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
1161 | env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); | |
1162 | env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); | |
1163 | } | |
0e1a46bb PM |
1164 | } else { |
1165 | env->pmsav7.drbar = g_new0(uint32_t, nr); | |
1166 | env->pmsav7.drsr = g_new0(uint32_t, nr); | |
1167 | env->pmsav7.dracr = g_new0(uint32_t, nr); | |
1168 | } | |
6cb0b013 | 1169 | } |
3281af81 PC |
1170 | } |
1171 | ||
9901c576 PM |
1172 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
1173 | uint32_t nr = cpu->sau_sregion; | |
1174 | ||
1175 | if (nr > 0xff) { | |
1176 | error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); | |
1177 | return; | |
1178 | } | |
1179 | ||
1180 | if (nr) { | |
1181 | env->sau.rbar = g_new0(uint32_t, nr); | |
1182 | env->sau.rlar = g_new0(uint32_t, nr); | |
1183 | } | |
1184 | } | |
1185 | ||
91db4642 CLG |
1186 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
1187 | set_feature(env, ARM_FEATURE_VBAR); | |
1188 | } | |
1189 | ||
2ceb98c0 | 1190 | register_cp_regs_for_features(cpu); |
14969266 AF |
1191 | arm_cpu_register_gdb_regs_for_features(cpu); |
1192 | ||
721fae12 PM |
1193 | init_cpreg_list(cpu); |
1194 | ||
9e273ef2 | 1195 | #ifndef CONFIG_USER_ONLY |
1d2091bc | 1196 | if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
1d2091bc PM |
1197 | cs->num_ases = 2; |
1198 | ||
9e273ef2 PM |
1199 | if (!cpu->secure_memory) { |
1200 | cpu->secure_memory = cs->memory; | |
1201 | } | |
80ceb07a PX |
1202 | cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", |
1203 | cpu->secure_memory); | |
1d2091bc PM |
1204 | } else { |
1205 | cs->num_ases = 1; | |
9e273ef2 | 1206 | } |
80ceb07a | 1207 | cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); |
f9a69711 AF |
1208 | |
1209 | /* No core_count specified, default to smp_cpus. */ | |
1210 | if (cpu->core_count == -1) { | |
1211 | cpu->core_count = smp_cpus; | |
1212 | } | |
9e273ef2 PM |
1213 | #endif |
1214 | ||
14a10fc3 | 1215 | qemu_init_vcpu(cs); |
00d0f7cb | 1216 | cpu_reset(cs); |
14969266 AF |
1217 | |
1218 | acc->parent_realize(dev, errp); | |
581be094 PM |
1219 | } |
1220 | ||
5900d6b2 AF |
1221 | static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) |
1222 | { | |
1223 | ObjectClass *oc; | |
51492fd1 | 1224 | char *typename; |
fb8d6c24 | 1225 | char **cpuname; |
a0032cc5 | 1226 | const char *cpunamestr; |
5900d6b2 | 1227 | |
fb8d6c24 | 1228 | cpuname = g_strsplit(cpu_model, ",", 1); |
a0032cc5 PM |
1229 | cpunamestr = cpuname[0]; |
1230 | #ifdef CONFIG_USER_ONLY | |
1231 | /* For backwards compatibility usermode emulation allows "-cpu any", | |
1232 | * which has the same semantics as "-cpu max". | |
1233 | */ | |
1234 | if (!strcmp(cpunamestr, "any")) { | |
1235 | cpunamestr = "max"; | |
1236 | } | |
1237 | #endif | |
1238 | typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); | |
51492fd1 | 1239 | oc = object_class_by_name(typename); |
fb8d6c24 | 1240 | g_strfreev(cpuname); |
51492fd1 | 1241 | g_free(typename); |
245fb54d AF |
1242 | if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || |
1243 | object_class_is_abstract(oc)) { | |
5900d6b2 AF |
1244 | return NULL; |
1245 | } | |
1246 | return oc; | |
1247 | } | |
1248 | ||
15ee776b PM |
1249 | /* CPU models. These are not needed for the AArch64 linux-user build. */ |
1250 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | |
1251 | ||
777dc784 PM |
1252 | static void arm926_initfn(Object *obj) |
1253 | { | |
1254 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1255 | |
1256 | cpu->dtb_compatible = "arm,arm926"; | |
581be094 PM |
1257 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1258 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
1259 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
1260 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 1261 | cpu->midr = 0x41069265; |
325b3cef | 1262 | cpu->reset_fpsid = 0x41011090; |
64e1671f | 1263 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 1264 | cpu->reset_sctlr = 0x00090078; |
09cbd501 RH |
1265 | |
1266 | /* | |
1267 | * ARMv5 does not have the ID_ISAR registers, but we can still | |
1268 | * set the field to indicate Jazelle support within QEMU. | |
1269 | */ | |
1270 | cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); | |
777dc784 PM |
1271 | } |
1272 | ||
1273 | static void arm946_initfn(Object *obj) | |
1274 | { | |
1275 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1276 | |
1277 | cpu->dtb_compatible = "arm,arm946"; | |
581be094 | 1278 | set_feature(&cpu->env, ARM_FEATURE_V5); |
452a0955 | 1279 | set_feature(&cpu->env, ARM_FEATURE_PMSA); |
c4804214 | 1280 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1281 | cpu->midr = 0x41059461; |
64e1671f | 1282 | cpu->ctr = 0x0f004006; |
0ca7e01c | 1283 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1284 | } |
1285 | ||
1286 | static void arm1026_initfn(Object *obj) | |
1287 | { | |
1288 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1289 | |
1290 | cpu->dtb_compatible = "arm,arm1026"; | |
581be094 PM |
1291 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1292 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
1293 | set_feature(&cpu->env, ARM_FEATURE_AUXCR); | |
c4804214 PM |
1294 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
1295 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 1296 | cpu->midr = 0x4106a262; |
325b3cef | 1297 | cpu->reset_fpsid = 0x410110a0; |
64e1671f | 1298 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 1299 | cpu->reset_sctlr = 0x00090078; |
2771db27 | 1300 | cpu->reset_auxcr = 1; |
09cbd501 RH |
1301 | |
1302 | /* | |
1303 | * ARMv5 does not have the ID_ISAR registers, but we can still | |
1304 | * set the field to indicate Jazelle support within QEMU. | |
1305 | */ | |
1306 | cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); | |
1307 | ||
06d76f31 PM |
1308 | { |
1309 | /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ | |
1310 | ARMCPRegInfo ifar = { | |
1311 | .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1312 | .access = PL1_RW, | |
b848ce2b | 1313 | .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), |
06d76f31 PM |
1314 | .resetvalue = 0 |
1315 | }; | |
1316 | define_one_arm_cp_reg(cpu, &ifar); | |
1317 | } | |
777dc784 PM |
1318 | } |
1319 | ||
1320 | static void arm1136_r2_initfn(Object *obj) | |
1321 | { | |
1322 | ARMCPU *cpu = ARM_CPU(obj); | |
2e4d7e3e PM |
1323 | /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an |
1324 | * older core than plain "arm1136". In particular this does not | |
1325 | * have the v6K features. | |
1326 | * These ID register values are correct for 1136 but may be wrong | |
1327 | * for 1136_r2 (in particular r0p2 does not actually implement most | |
1328 | * of the ID registers). | |
1329 | */ | |
54d3e3f5 PM |
1330 | |
1331 | cpu->dtb_compatible = "arm,arm1136"; | |
581be094 PM |
1332 | set_feature(&cpu->env, ARM_FEATURE_V6); |
1333 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
1334 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
1335 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
1336 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 1337 | cpu->midr = 0x4107b362; |
325b3cef | 1338 | cpu->reset_fpsid = 0x410120b4; |
47576b94 RH |
1339 | cpu->isar.mvfr0 = 0x11111111; |
1340 | cpu->isar.mvfr1 = 0x00000000; | |
64e1671f | 1341 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 1342 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
1343 | cpu->id_pfr0 = 0x111; |
1344 | cpu->id_pfr1 = 0x1; | |
1345 | cpu->id_dfr0 = 0x2; | |
1346 | cpu->id_afr0 = 0x3; | |
1347 | cpu->id_mmfr0 = 0x01130003; | |
1348 | cpu->id_mmfr1 = 0x10030302; | |
1349 | cpu->id_mmfr2 = 0x01222110; | |
47576b94 RH |
1350 | cpu->isar.id_isar0 = 0x00140011; |
1351 | cpu->isar.id_isar1 = 0x12002111; | |
1352 | cpu->isar.id_isar2 = 0x11231111; | |
1353 | cpu->isar.id_isar3 = 0x01102131; | |
1354 | cpu->isar.id_isar4 = 0x141; | |
2771db27 | 1355 | cpu->reset_auxcr = 7; |
777dc784 PM |
1356 | } |
1357 | ||
1358 | static void arm1136_initfn(Object *obj) | |
1359 | { | |
1360 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1361 | |
1362 | cpu->dtb_compatible = "arm,arm1136"; | |
581be094 PM |
1363 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
1364 | set_feature(&cpu->env, ARM_FEATURE_V6); | |
1365 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
1366 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
1367 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
1368 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 1369 | cpu->midr = 0x4117b363; |
325b3cef | 1370 | cpu->reset_fpsid = 0x410120b4; |
47576b94 RH |
1371 | cpu->isar.mvfr0 = 0x11111111; |
1372 | cpu->isar.mvfr1 = 0x00000000; | |
64e1671f | 1373 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 1374 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
1375 | cpu->id_pfr0 = 0x111; |
1376 | cpu->id_pfr1 = 0x1; | |
1377 | cpu->id_dfr0 = 0x2; | |
1378 | cpu->id_afr0 = 0x3; | |
1379 | cpu->id_mmfr0 = 0x01130003; | |
1380 | cpu->id_mmfr1 = 0x10030302; | |
1381 | cpu->id_mmfr2 = 0x01222110; | |
47576b94 RH |
1382 | cpu->isar.id_isar0 = 0x00140011; |
1383 | cpu->isar.id_isar1 = 0x12002111; | |
1384 | cpu->isar.id_isar2 = 0x11231111; | |
1385 | cpu->isar.id_isar3 = 0x01102131; | |
1386 | cpu->isar.id_isar4 = 0x141; | |
2771db27 | 1387 | cpu->reset_auxcr = 7; |
777dc784 PM |
1388 | } |
1389 | ||
1390 | static void arm1176_initfn(Object *obj) | |
1391 | { | |
1392 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1393 | |
1394 | cpu->dtb_compatible = "arm,arm1176"; | |
581be094 PM |
1395 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
1396 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
1397 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
c4804214 PM |
1398 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
1399 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
1400 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
c0ccb02d | 1401 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
b2d06f96 | 1402 | cpu->midr = 0x410fb767; |
325b3cef | 1403 | cpu->reset_fpsid = 0x410120b5; |
47576b94 RH |
1404 | cpu->isar.mvfr0 = 0x11111111; |
1405 | cpu->isar.mvfr1 = 0x00000000; | |
64e1671f | 1406 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 1407 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
1408 | cpu->id_pfr0 = 0x111; |
1409 | cpu->id_pfr1 = 0x11; | |
1410 | cpu->id_dfr0 = 0x33; | |
1411 | cpu->id_afr0 = 0; | |
1412 | cpu->id_mmfr0 = 0x01130003; | |
1413 | cpu->id_mmfr1 = 0x10030302; | |
1414 | cpu->id_mmfr2 = 0x01222100; | |
47576b94 RH |
1415 | cpu->isar.id_isar0 = 0x0140011; |
1416 | cpu->isar.id_isar1 = 0x12002111; | |
1417 | cpu->isar.id_isar2 = 0x11231121; | |
1418 | cpu->isar.id_isar3 = 0x01102131; | |
1419 | cpu->isar.id_isar4 = 0x01141; | |
2771db27 | 1420 | cpu->reset_auxcr = 7; |
777dc784 PM |
1421 | } |
1422 | ||
1423 | static void arm11mpcore_initfn(Object *obj) | |
1424 | { | |
1425 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1426 | |
1427 | cpu->dtb_compatible = "arm,arm11mpcore"; | |
581be094 PM |
1428 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
1429 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
1430 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
81bdde9d | 1431 | set_feature(&cpu->env, ARM_FEATURE_MPIDR); |
c4804214 | 1432 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1433 | cpu->midr = 0x410fb022; |
325b3cef | 1434 | cpu->reset_fpsid = 0x410120b4; |
47576b94 RH |
1435 | cpu->isar.mvfr0 = 0x11111111; |
1436 | cpu->isar.mvfr1 = 0x00000000; | |
200bf596 | 1437 | cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ |
2e4d7e3e PM |
1438 | cpu->id_pfr0 = 0x111; |
1439 | cpu->id_pfr1 = 0x1; | |
1440 | cpu->id_dfr0 = 0; | |
1441 | cpu->id_afr0 = 0x2; | |
1442 | cpu->id_mmfr0 = 0x01100103; | |
1443 | cpu->id_mmfr1 = 0x10020302; | |
1444 | cpu->id_mmfr2 = 0x01222000; | |
47576b94 RH |
1445 | cpu->isar.id_isar0 = 0x00100011; |
1446 | cpu->isar.id_isar1 = 0x12002111; | |
1447 | cpu->isar.id_isar2 = 0x11221011; | |
1448 | cpu->isar.id_isar3 = 0x01102131; | |
1449 | cpu->isar.id_isar4 = 0x141; | |
2771db27 | 1450 | cpu->reset_auxcr = 1; |
777dc784 PM |
1451 | } |
1452 | ||
191776b9 SH |
1453 | static void cortex_m0_initfn(Object *obj) |
1454 | { | |
1455 | ARMCPU *cpu = ARM_CPU(obj); | |
1456 | set_feature(&cpu->env, ARM_FEATURE_V6); | |
1457 | set_feature(&cpu->env, ARM_FEATURE_M); | |
1458 | ||
1459 | cpu->midr = 0x410cc200; | |
1460 | } | |
1461 | ||
777dc784 PM |
1462 | static void cortex_m3_initfn(Object *obj) |
1463 | { | |
1464 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
1465 | set_feature(&cpu->env, ARM_FEATURE_V7); |
1466 | set_feature(&cpu->env, ARM_FEATURE_M); | |
cc2ae7c9 | 1467 | set_feature(&cpu->env, ARM_FEATURE_M_MAIN); |
b2d06f96 | 1468 | cpu->midr = 0x410fc231; |
8d92e26b | 1469 | cpu->pmsav7_dregion = 8; |
5a53e2c1 PM |
1470 | cpu->id_pfr0 = 0x00000030; |
1471 | cpu->id_pfr1 = 0x00000200; | |
1472 | cpu->id_dfr0 = 0x00100000; | |
1473 | cpu->id_afr0 = 0x00000000; | |
1474 | cpu->id_mmfr0 = 0x00000030; | |
1475 | cpu->id_mmfr1 = 0x00000000; | |
1476 | cpu->id_mmfr2 = 0x00000000; | |
1477 | cpu->id_mmfr3 = 0x00000000; | |
47576b94 RH |
1478 | cpu->isar.id_isar0 = 0x01141110; |
1479 | cpu->isar.id_isar1 = 0x02111000; | |
1480 | cpu->isar.id_isar2 = 0x21112231; | |
1481 | cpu->isar.id_isar3 = 0x01111110; | |
1482 | cpu->isar.id_isar4 = 0x01310102; | |
1483 | cpu->isar.id_isar5 = 0x00000000; | |
1484 | cpu->isar.id_isar6 = 0x00000000; | |
777dc784 PM |
1485 | } |
1486 | ||
ba890a9b AR |
1487 | static void cortex_m4_initfn(Object *obj) |
1488 | { | |
1489 | ARMCPU *cpu = ARM_CPU(obj); | |
1490 | ||
1491 | set_feature(&cpu->env, ARM_FEATURE_V7); | |
1492 | set_feature(&cpu->env, ARM_FEATURE_M); | |
cc2ae7c9 | 1493 | set_feature(&cpu->env, ARM_FEATURE_M_MAIN); |
ba890a9b | 1494 | set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); |
14fd0c31 | 1495 | set_feature(&cpu->env, ARM_FEATURE_VFP4); |
ba890a9b | 1496 | cpu->midr = 0x410fc240; /* r0p0 */ |
8d92e26b | 1497 | cpu->pmsav7_dregion = 8; |
14fd0c31 PM |
1498 | cpu->isar.mvfr0 = 0x10110021; |
1499 | cpu->isar.mvfr1 = 0x11000011; | |
1500 | cpu->isar.mvfr2 = 0x00000000; | |
5a53e2c1 PM |
1501 | cpu->id_pfr0 = 0x00000030; |
1502 | cpu->id_pfr1 = 0x00000200; | |
1503 | cpu->id_dfr0 = 0x00100000; | |
1504 | cpu->id_afr0 = 0x00000000; | |
1505 | cpu->id_mmfr0 = 0x00000030; | |
1506 | cpu->id_mmfr1 = 0x00000000; | |
1507 | cpu->id_mmfr2 = 0x00000000; | |
1508 | cpu->id_mmfr3 = 0x00000000; | |
47576b94 RH |
1509 | cpu->isar.id_isar0 = 0x01141110; |
1510 | cpu->isar.id_isar1 = 0x02111000; | |
1511 | cpu->isar.id_isar2 = 0x21112231; | |
1512 | cpu->isar.id_isar3 = 0x01111110; | |
1513 | cpu->isar.id_isar4 = 0x01310102; | |
1514 | cpu->isar.id_isar5 = 0x00000000; | |
1515 | cpu->isar.id_isar6 = 0x00000000; | |
ba890a9b | 1516 | } |
9901c576 | 1517 | |
c7b26382 PM |
1518 | static void cortex_m33_initfn(Object *obj) |
1519 | { | |
1520 | ARMCPU *cpu = ARM_CPU(obj); | |
1521 | ||
1522 | set_feature(&cpu->env, ARM_FEATURE_V8); | |
1523 | set_feature(&cpu->env, ARM_FEATURE_M); | |
cc2ae7c9 | 1524 | set_feature(&cpu->env, ARM_FEATURE_M_MAIN); |
c7b26382 PM |
1525 | set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); |
1526 | set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | |
14fd0c31 | 1527 | set_feature(&cpu->env, ARM_FEATURE_VFP4); |
c7b26382 PM |
1528 | cpu->midr = 0x410fd213; /* r0p3 */ |
1529 | cpu->pmsav7_dregion = 16; | |
1530 | cpu->sau_sregion = 8; | |
14fd0c31 PM |
1531 | cpu->isar.mvfr0 = 0x10110021; |
1532 | cpu->isar.mvfr1 = 0x11000011; | |
1533 | cpu->isar.mvfr2 = 0x00000040; | |
c7b26382 PM |
1534 | cpu->id_pfr0 = 0x00000030; |
1535 | cpu->id_pfr1 = 0x00000210; | |
1536 | cpu->id_dfr0 = 0x00200000; | |
1537 | cpu->id_afr0 = 0x00000000; | |
1538 | cpu->id_mmfr0 = 0x00101F40; | |
1539 | cpu->id_mmfr1 = 0x00000000; | |
1540 | cpu->id_mmfr2 = 0x01000000; | |
1541 | cpu->id_mmfr3 = 0x00000000; | |
47576b94 RH |
1542 | cpu->isar.id_isar0 = 0x01101110; |
1543 | cpu->isar.id_isar1 = 0x02212000; | |
1544 | cpu->isar.id_isar2 = 0x20232232; | |
1545 | cpu->isar.id_isar3 = 0x01111131; | |
1546 | cpu->isar.id_isar4 = 0x01310132; | |
1547 | cpu->isar.id_isar5 = 0x00000000; | |
1548 | cpu->isar.id_isar6 = 0x00000000; | |
c7b26382 PM |
1549 | cpu->clidr = 0x00000000; |
1550 | cpu->ctr = 0x8000c000; | |
1551 | } | |
1552 | ||
e6f010cc AF |
1553 | static void arm_v7m_class_init(ObjectClass *oc, void *data) |
1554 | { | |
51e5ef45 | 1555 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); |
e6f010cc AF |
1556 | CPUClass *cc = CPU_CLASS(oc); |
1557 | ||
51e5ef45 | 1558 | acc->info = data; |
b5c633c5 | 1559 | #ifndef CONFIG_USER_ONLY |
e6f010cc AF |
1560 | cc->do_interrupt = arm_v7m_cpu_do_interrupt; |
1561 | #endif | |
b5c633c5 PM |
1562 | |
1563 | cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; | |
e6f010cc AF |
1564 | } |
1565 | ||
d6a6b13e PC |
1566 | static const ARMCPRegInfo cortexr5_cp_reginfo[] = { |
1567 | /* Dummy the TCM region regs for the moment */ | |
1568 | { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
1569 | .access = PL1_RW, .type = ARM_CP_CONST }, | |
1570 | { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
1571 | .access = PL1_RW, .type = ARM_CP_CONST }, | |
95e9a242 LM |
1572 | { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, |
1573 | .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, | |
d6a6b13e PC |
1574 | REGINFO_SENTINEL |
1575 | }; | |
1576 | ||
1577 | static void cortex_r5_initfn(Object *obj) | |
1578 | { | |
1579 | ARMCPU *cpu = ARM_CPU(obj); | |
1580 | ||
1581 | set_feature(&cpu->env, ARM_FEATURE_V7); | |
d6a6b13e | 1582 | set_feature(&cpu->env, ARM_FEATURE_V7MP); |
452a0955 | 1583 | set_feature(&cpu->env, ARM_FEATURE_PMSA); |
d6a6b13e PC |
1584 | cpu->midr = 0x411fc153; /* r1p3 */ |
1585 | cpu->id_pfr0 = 0x0131; | |
1586 | cpu->id_pfr1 = 0x001; | |
1587 | cpu->id_dfr0 = 0x010400; | |
1588 | cpu->id_afr0 = 0x0; | |
1589 | cpu->id_mmfr0 = 0x0210030; | |
1590 | cpu->id_mmfr1 = 0x00000000; | |
1591 | cpu->id_mmfr2 = 0x01200000; | |
1592 | cpu->id_mmfr3 = 0x0211; | |
47576b94 RH |
1593 | cpu->isar.id_isar0 = 0x02101111; |
1594 | cpu->isar.id_isar1 = 0x13112111; | |
1595 | cpu->isar.id_isar2 = 0x21232141; | |
1596 | cpu->isar.id_isar3 = 0x01112131; | |
1597 | cpu->isar.id_isar4 = 0x0010142; | |
1598 | cpu->isar.id_isar5 = 0x0; | |
1599 | cpu->isar.id_isar6 = 0x0; | |
d6a6b13e | 1600 | cpu->mp_is_up = true; |
8d92e26b | 1601 | cpu->pmsav7_dregion = 16; |
d6a6b13e PC |
1602 | define_arm_cp_regs(cpu, cortexr5_cp_reginfo); |
1603 | } | |
1604 | ||
ebac5458 EI |
1605 | static void cortex_r5f_initfn(Object *obj) |
1606 | { | |
1607 | ARMCPU *cpu = ARM_CPU(obj); | |
1608 | ||
1609 | cortex_r5_initfn(obj); | |
1610 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
1611 | } | |
1612 | ||
34f90529 PM |
1613 | static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |
1614 | { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, | |
1615 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1616 | { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
1617 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1618 | REGINFO_SENTINEL | |
1619 | }; | |
1620 | ||
777dc784 PM |
1621 | static void cortex_a8_initfn(Object *obj) |
1622 | { | |
1623 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1624 | |
1625 | cpu->dtb_compatible = "arm,cortex-a8"; | |
581be094 PM |
1626 | set_feature(&cpu->env, ARM_FEATURE_V7); |
1627 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
1628 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
1629 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c4804214 | 1630 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
c0ccb02d | 1631 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
b2d06f96 | 1632 | cpu->midr = 0x410fc080; |
325b3cef | 1633 | cpu->reset_fpsid = 0x410330c0; |
47576b94 RH |
1634 | cpu->isar.mvfr0 = 0x11110222; |
1635 | cpu->isar.mvfr1 = 0x00011111; | |
64e1671f | 1636 | cpu->ctr = 0x82048004; |
0ca7e01c | 1637 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
1638 | cpu->id_pfr0 = 0x1031; |
1639 | cpu->id_pfr1 = 0x11; | |
1640 | cpu->id_dfr0 = 0x400; | |
1641 | cpu->id_afr0 = 0; | |
1642 | cpu->id_mmfr0 = 0x31100003; | |
1643 | cpu->id_mmfr1 = 0x20000000; | |
1644 | cpu->id_mmfr2 = 0x01202000; | |
1645 | cpu->id_mmfr3 = 0x11; | |
47576b94 RH |
1646 | cpu->isar.id_isar0 = 0x00101111; |
1647 | cpu->isar.id_isar1 = 0x12112111; | |
1648 | cpu->isar.id_isar2 = 0x21232031; | |
1649 | cpu->isar.id_isar3 = 0x11112131; | |
1650 | cpu->isar.id_isar4 = 0x00111142; | |
48eb3ae6 | 1651 | cpu->dbgdidr = 0x15141000; |
85df3786 PM |
1652 | cpu->clidr = (1 << 27) | (2 << 24) | 3; |
1653 | cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ | |
1654 | cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ | |
1655 | cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ | |
2771db27 | 1656 | cpu->reset_auxcr = 2; |
34f90529 | 1657 | define_arm_cp_regs(cpu, cortexa8_cp_reginfo); |
777dc784 PM |
1658 | } |
1659 | ||
1047b9d7 PM |
1660 | static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
1661 | /* power_control should be set to maximum latency. Again, | |
1662 | * default to 0 and set by private hook | |
1663 | */ | |
1664 | { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, | |
1665 | .access = PL1_RW, .resetvalue = 0, | |
1666 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, | |
1667 | { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1668 | .access = PL1_RW, .resetvalue = 0, | |
1669 | .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, | |
1670 | { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, | |
1671 | .access = PL1_RW, .resetvalue = 0, | |
1672 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, | |
1673 | { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
1674 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1675 | /* TLB lockdown control */ | |
1676 | { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, | |
1677 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
1678 | { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, | |
1679 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
1680 | { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, | |
1681 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1682 | { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, | |
1683 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1684 | { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, | |
1685 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1686 | REGINFO_SENTINEL | |
1687 | }; | |
1688 | ||
777dc784 PM |
1689 | static void cortex_a9_initfn(Object *obj) |
1690 | { | |
1691 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1692 | |
1693 | cpu->dtb_compatible = "arm,cortex-a9"; | |
581be094 PM |
1694 | set_feature(&cpu->env, ARM_FEATURE_V7); |
1695 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
581be094 PM |
1696 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
1697 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c0ccb02d | 1698 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
581be094 PM |
1699 | /* Note that A9 supports the MP extensions even for |
1700 | * A9UP and single-core A9MP (which are both different | |
1701 | * and valid configurations; we don't model A9UP). | |
1702 | */ | |
1703 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
d8ba780b | 1704 | set_feature(&cpu->env, ARM_FEATURE_CBAR); |
b2d06f96 | 1705 | cpu->midr = 0x410fc090; |
325b3cef | 1706 | cpu->reset_fpsid = 0x41033090; |
47576b94 RH |
1707 | cpu->isar.mvfr0 = 0x11110222; |
1708 | cpu->isar.mvfr1 = 0x01111111; | |
64e1671f | 1709 | cpu->ctr = 0x80038003; |
0ca7e01c | 1710 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
1711 | cpu->id_pfr0 = 0x1031; |
1712 | cpu->id_pfr1 = 0x11; | |
1713 | cpu->id_dfr0 = 0x000; | |
1714 | cpu->id_afr0 = 0; | |
1715 | cpu->id_mmfr0 = 0x00100103; | |
1716 | cpu->id_mmfr1 = 0x20000000; | |
1717 | cpu->id_mmfr2 = 0x01230000; | |
1718 | cpu->id_mmfr3 = 0x00002111; | |
47576b94 RH |
1719 | cpu->isar.id_isar0 = 0x00101111; |
1720 | cpu->isar.id_isar1 = 0x13112111; | |
1721 | cpu->isar.id_isar2 = 0x21232041; | |
1722 | cpu->isar.id_isar3 = 0x11112131; | |
1723 | cpu->isar.id_isar4 = 0x00111142; | |
48eb3ae6 | 1724 | cpu->dbgdidr = 0x35141000; |
85df3786 | 1725 | cpu->clidr = (1 << 27) | (1 << 24) | 3; |
f7838b52 PC |
1726 | cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ |
1727 | cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ | |
d8ba780b | 1728 | define_arm_cp_regs(cpu, cortexa9_cp_reginfo); |
777dc784 PM |
1729 | } |
1730 | ||
34f90529 | 1731 | #ifndef CONFIG_USER_ONLY |
c4241c7d | 1732 | static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
34f90529 PM |
1733 | { |
1734 | /* Linux wants the number of processors from here. | |
1735 | * Might as well set the interrupt-controller bit too. | |
1736 | */ | |
c4241c7d | 1737 | return ((smp_cpus - 1) << 24) | (1 << 23); |
34f90529 PM |
1738 | } |
1739 | #endif | |
1740 | ||
1741 | static const ARMCPRegInfo cortexa15_cp_reginfo[] = { | |
1742 | #ifndef CONFIG_USER_ONLY | |
1743 | { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
1744 | .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, | |
1745 | .writefn = arm_cp_write_ignore, }, | |
1746 | #endif | |
1747 | { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, | |
1748 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1749 | REGINFO_SENTINEL | |
1750 | }; | |
1751 | ||
dcf578ed AY |
1752 | static void cortex_a7_initfn(Object *obj) |
1753 | { | |
1754 | ARMCPU *cpu = ARM_CPU(obj); | |
1755 | ||
1756 | cpu->dtb_compatible = "arm,cortex-a7"; | |
5110e683 | 1757 | set_feature(&cpu->env, ARM_FEATURE_V7VE); |
dcf578ed AY |
1758 | set_feature(&cpu->env, ARM_FEATURE_VFP4); |
1759 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
1760 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
dcf578ed AY |
1761 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
1762 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | |
1763 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | |
436c0cbb | 1764 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
dcf578ed | 1765 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
a46118fc | 1766 | set_feature(&cpu->env, ARM_FEATURE_PMU); |
dcf578ed AY |
1767 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; |
1768 | cpu->midr = 0x410fc075; | |
1769 | cpu->reset_fpsid = 0x41023075; | |
47576b94 RH |
1770 | cpu->isar.mvfr0 = 0x10110222; |
1771 | cpu->isar.mvfr1 = 0x11111111; | |
dcf578ed AY |
1772 | cpu->ctr = 0x84448003; |
1773 | cpu->reset_sctlr = 0x00c50078; | |
1774 | cpu->id_pfr0 = 0x00001131; | |
1775 | cpu->id_pfr1 = 0x00011011; | |
1776 | cpu->id_dfr0 = 0x02010555; | |
dcf578ed AY |
1777 | cpu->id_afr0 = 0x00000000; |
1778 | cpu->id_mmfr0 = 0x10101105; | |
1779 | cpu->id_mmfr1 = 0x40000000; | |
1780 | cpu->id_mmfr2 = 0x01240000; | |
1781 | cpu->id_mmfr3 = 0x02102211; | |
37bdda89 RH |
1782 | /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but |
1783 | * table 4-41 gives 0x02101110, which includes the arm div insns. | |
1784 | */ | |
47576b94 RH |
1785 | cpu->isar.id_isar0 = 0x02101110; |
1786 | cpu->isar.id_isar1 = 0x13112111; | |
1787 | cpu->isar.id_isar2 = 0x21232041; | |
1788 | cpu->isar.id_isar3 = 0x11112131; | |
1789 | cpu->isar.id_isar4 = 0x10011142; | |
dcf578ed AY |
1790 | cpu->dbgdidr = 0x3515f005; |
1791 | cpu->clidr = 0x0a200023; | |
1792 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
1793 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
1794 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
1795 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ | |
1796 | } | |
1797 | ||
777dc784 PM |
1798 | static void cortex_a15_initfn(Object *obj) |
1799 | { | |
1800 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1801 | |
1802 | cpu->dtb_compatible = "arm,cortex-a15"; | |
5110e683 | 1803 | set_feature(&cpu->env, ARM_FEATURE_V7VE); |
581be094 | 1804 | set_feature(&cpu->env, ARM_FEATURE_VFP4); |
581be094 PM |
1805 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
1806 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
581be094 | 1807 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
c4804214 | 1808 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
c29f9a0a | 1809 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
436c0cbb | 1810 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
c0ccb02d | 1811 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
a46118fc | 1812 | set_feature(&cpu->env, ARM_FEATURE_PMU); |
3541addc | 1813 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; |
b2d06f96 | 1814 | cpu->midr = 0x412fc0f1; |
325b3cef | 1815 | cpu->reset_fpsid = 0x410430f0; |
47576b94 RH |
1816 | cpu->isar.mvfr0 = 0x10110222; |
1817 | cpu->isar.mvfr1 = 0x11111111; | |
64e1671f | 1818 | cpu->ctr = 0x8444c004; |
0ca7e01c | 1819 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
1820 | cpu->id_pfr0 = 0x00001131; |
1821 | cpu->id_pfr1 = 0x00011011; | |
1822 | cpu->id_dfr0 = 0x02010555; | |
1823 | cpu->id_afr0 = 0x00000000; | |
1824 | cpu->id_mmfr0 = 0x10201105; | |
1825 | cpu->id_mmfr1 = 0x20000000; | |
1826 | cpu->id_mmfr2 = 0x01240000; | |
1827 | cpu->id_mmfr3 = 0x02102211; | |
47576b94 RH |
1828 | cpu->isar.id_isar0 = 0x02101110; |
1829 | cpu->isar.id_isar1 = 0x13112111; | |
1830 | cpu->isar.id_isar2 = 0x21232041; | |
1831 | cpu->isar.id_isar3 = 0x11112131; | |
1832 | cpu->isar.id_isar4 = 0x10011142; | |
48eb3ae6 | 1833 | cpu->dbgdidr = 0x3515f021; |
85df3786 PM |
1834 | cpu->clidr = 0x0a200023; |
1835 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
1836 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
1837 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
34f90529 | 1838 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); |
777dc784 PM |
1839 | } |
1840 | ||
1841 | static void ti925t_initfn(Object *obj) | |
1842 | { | |
1843 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
1844 | set_feature(&cpu->env, ARM_FEATURE_V4T); |
1845 | set_feature(&cpu->env, ARM_FEATURE_OMAPCP); | |
777dc784 | 1846 | cpu->midr = ARM_CPUID_TI925T; |
64e1671f | 1847 | cpu->ctr = 0x5109149; |
0ca7e01c | 1848 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1849 | } |
1850 | ||
1851 | static void sa1100_initfn(Object *obj) | |
1852 | { | |
1853 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1854 | |
1855 | cpu->dtb_compatible = "intel,sa1100"; | |
581be094 | 1856 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 1857 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1858 | cpu->midr = 0x4401A11B; |
0ca7e01c | 1859 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1860 | } |
1861 | ||
1862 | static void sa1110_initfn(Object *obj) | |
1863 | { | |
1864 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 | 1865 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 1866 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1867 | cpu->midr = 0x6901B119; |
0ca7e01c | 1868 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1869 | } |
1870 | ||
1871 | static void pxa250_initfn(Object *obj) | |
1872 | { | |
1873 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1874 | |
1875 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1876 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1877 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1878 | cpu->midr = 0x69052100; |
64e1671f | 1879 | cpu->ctr = 0xd172172; |
0ca7e01c | 1880 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1881 | } |
1882 | ||
1883 | static void pxa255_initfn(Object *obj) | |
1884 | { | |
1885 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1886 | |
1887 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1888 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1889 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1890 | cpu->midr = 0x69052d00; |
64e1671f | 1891 | cpu->ctr = 0xd172172; |
0ca7e01c | 1892 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1893 | } |
1894 | ||
1895 | static void pxa260_initfn(Object *obj) | |
1896 | { | |
1897 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1898 | |
1899 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1900 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1901 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1902 | cpu->midr = 0x69052903; |
64e1671f | 1903 | cpu->ctr = 0xd172172; |
0ca7e01c | 1904 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1905 | } |
1906 | ||
1907 | static void pxa261_initfn(Object *obj) | |
1908 | { | |
1909 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1910 | |
1911 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1912 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1913 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1914 | cpu->midr = 0x69052d05; |
64e1671f | 1915 | cpu->ctr = 0xd172172; |
0ca7e01c | 1916 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1917 | } |
1918 | ||
1919 | static void pxa262_initfn(Object *obj) | |
1920 | { | |
1921 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1922 | |
1923 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1924 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1925 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1926 | cpu->midr = 0x69052d06; |
64e1671f | 1927 | cpu->ctr = 0xd172172; |
0ca7e01c | 1928 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1929 | } |
1930 | ||
1931 | static void pxa270a0_initfn(Object *obj) | |
1932 | { | |
1933 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1934 | |
1935 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1936 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1937 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1938 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1939 | cpu->midr = 0x69054110; |
64e1671f | 1940 | cpu->ctr = 0xd172172; |
0ca7e01c | 1941 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1942 | } |
1943 | ||
1944 | static void pxa270a1_initfn(Object *obj) | |
1945 | { | |
1946 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1947 | |
1948 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1949 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1950 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1951 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1952 | cpu->midr = 0x69054111; |
64e1671f | 1953 | cpu->ctr = 0xd172172; |
0ca7e01c | 1954 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1955 | } |
1956 | ||
1957 | static void pxa270b0_initfn(Object *obj) | |
1958 | { | |
1959 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1960 | |
1961 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1962 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1963 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1964 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1965 | cpu->midr = 0x69054112; |
64e1671f | 1966 | cpu->ctr = 0xd172172; |
0ca7e01c | 1967 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1968 | } |
1969 | ||
1970 | static void pxa270b1_initfn(Object *obj) | |
1971 | { | |
1972 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1973 | |
1974 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1975 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1976 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1977 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1978 | cpu->midr = 0x69054113; |
64e1671f | 1979 | cpu->ctr = 0xd172172; |
0ca7e01c | 1980 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1981 | } |
1982 | ||
1983 | static void pxa270c0_initfn(Object *obj) | |
1984 | { | |
1985 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1986 | |
1987 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1988 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1989 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1990 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1991 | cpu->midr = 0x69054114; |
64e1671f | 1992 | cpu->ctr = 0xd172172; |
0ca7e01c | 1993 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1994 | } |
1995 | ||
1996 | static void pxa270c5_initfn(Object *obj) | |
1997 | { | |
1998 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1999 | |
2000 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
2001 | set_feature(&cpu->env, ARM_FEATURE_V5); |
2002 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
2003 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 2004 | cpu->midr = 0x69054117; |
64e1671f | 2005 | cpu->ctr = 0xd172172; |
0ca7e01c | 2006 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
2007 | } |
2008 | ||
bab52d4b PM |
2009 | #ifndef TARGET_AARCH64 |
2010 | /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); | |
2011 | * otherwise, a CPU with as many features enabled as our emulation supports. | |
2012 | * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; | |
2013 | * this only needs to handle 32 bits. | |
2014 | */ | |
2015 | static void arm_max_initfn(Object *obj) | |
2016 | { | |
2017 | ARMCPU *cpu = ARM_CPU(obj); | |
2018 | ||
2019 | if (kvm_enabled()) { | |
2020 | kvm_arm_set_cpu_features_from_host(cpu); | |
2021 | } else { | |
2022 | cortex_a15_initfn(obj); | |
a0032cc5 PM |
2023 | #ifdef CONFIG_USER_ONLY |
2024 | /* We don't set these in system emulation mode for the moment, | |
962fcbf2 RH |
2025 | * since we don't correctly set (all of) the ID registers to |
2026 | * advertise them. | |
bab52d4b | 2027 | */ |
a0032cc5 | 2028 | set_feature(&cpu->env, ARM_FEATURE_V8); |
962fcbf2 RH |
2029 | { |
2030 | uint32_t t; | |
2031 | ||
2032 | t = cpu->isar.id_isar5; | |
2033 | t = FIELD_DP32(t, ID_ISAR5, AES, 2); | |
2034 | t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | |
2035 | t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | |
2036 | t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | |
2037 | t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | |
2038 | t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | |
2039 | cpu->isar.id_isar5 = t; | |
2040 | ||
2041 | t = cpu->isar.id_isar6; | |
6c1f6f27 | 2042 | t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); |
962fcbf2 | 2043 | t = FIELD_DP32(t, ID_ISAR6, DP, 1); |
991c0599 | 2044 | t = FIELD_DP32(t, ID_ISAR6, FHM, 1); |
9888bd1e | 2045 | t = FIELD_DP32(t, ID_ISAR6, SB, 1); |
cb570bd3 | 2046 | t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); |
962fcbf2 | 2047 | cpu->isar.id_isar6 = t; |
ab638a32 | 2048 | |
c8877d0f RH |
2049 | t = cpu->isar.mvfr2; |
2050 | t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | |
2051 | t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | |
2052 | cpu->isar.mvfr2 = t; | |
2053 | ||
ab638a32 RH |
2054 | t = cpu->id_mmfr4; |
2055 | t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | |
2056 | cpu->id_mmfr4 = t; | |
962fcbf2 | 2057 | } |
bab52d4b | 2058 | #endif |
a0032cc5 | 2059 | } |
777dc784 | 2060 | } |
f5f6d38b | 2061 | #endif |
777dc784 | 2062 | |
15ee776b PM |
2063 | #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ |
2064 | ||
51e5ef45 | 2065 | struct ARMCPUInfo { |
777dc784 PM |
2066 | const char *name; |
2067 | void (*initfn)(Object *obj); | |
e6f010cc | 2068 | void (*class_init)(ObjectClass *oc, void *data); |
51e5ef45 | 2069 | }; |
777dc784 PM |
2070 | |
2071 | static const ARMCPUInfo arm_cpus[] = { | |
15ee776b | 2072 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) |
777dc784 PM |
2073 | { .name = "arm926", .initfn = arm926_initfn }, |
2074 | { .name = "arm946", .initfn = arm946_initfn }, | |
2075 | { .name = "arm1026", .initfn = arm1026_initfn }, | |
2076 | /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an | |
2077 | * older core than plain "arm1136". In particular this does not | |
2078 | * have the v6K features. | |
2079 | */ | |
2080 | { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, | |
2081 | { .name = "arm1136", .initfn = arm1136_initfn }, | |
2082 | { .name = "arm1176", .initfn = arm1176_initfn }, | |
2083 | { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, | |
191776b9 SH |
2084 | { .name = "cortex-m0", .initfn = cortex_m0_initfn, |
2085 | .class_init = arm_v7m_class_init }, | |
e6f010cc AF |
2086 | { .name = "cortex-m3", .initfn = cortex_m3_initfn, |
2087 | .class_init = arm_v7m_class_init }, | |
ba890a9b AR |
2088 | { .name = "cortex-m4", .initfn = cortex_m4_initfn, |
2089 | .class_init = arm_v7m_class_init }, | |
c7b26382 PM |
2090 | { .name = "cortex-m33", .initfn = cortex_m33_initfn, |
2091 | .class_init = arm_v7m_class_init }, | |
d6a6b13e | 2092 | { .name = "cortex-r5", .initfn = cortex_r5_initfn }, |
ebac5458 | 2093 | { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, |
dcf578ed | 2094 | { .name = "cortex-a7", .initfn = cortex_a7_initfn }, |
777dc784 PM |
2095 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, |
2096 | { .name = "cortex-a9", .initfn = cortex_a9_initfn }, | |
2097 | { .name = "cortex-a15", .initfn = cortex_a15_initfn }, | |
2098 | { .name = "ti925t", .initfn = ti925t_initfn }, | |
2099 | { .name = "sa1100", .initfn = sa1100_initfn }, | |
2100 | { .name = "sa1110", .initfn = sa1110_initfn }, | |
2101 | { .name = "pxa250", .initfn = pxa250_initfn }, | |
2102 | { .name = "pxa255", .initfn = pxa255_initfn }, | |
2103 | { .name = "pxa260", .initfn = pxa260_initfn }, | |
2104 | { .name = "pxa261", .initfn = pxa261_initfn }, | |
2105 | { .name = "pxa262", .initfn = pxa262_initfn }, | |
2106 | /* "pxa270" is an alias for "pxa270-a0" */ | |
2107 | { .name = "pxa270", .initfn = pxa270a0_initfn }, | |
2108 | { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, | |
2109 | { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, | |
2110 | { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, | |
2111 | { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, | |
2112 | { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, | |
2113 | { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, | |
bab52d4b PM |
2114 | #ifndef TARGET_AARCH64 |
2115 | { .name = "max", .initfn = arm_max_initfn }, | |
2116 | #endif | |
f5f6d38b | 2117 | #ifdef CONFIG_USER_ONLY |
a0032cc5 | 2118 | { .name = "any", .initfn = arm_max_initfn }, |
f5f6d38b | 2119 | #endif |
15ee776b | 2120 | #endif |
83e6813a | 2121 | { .name = NULL } |
777dc784 PM |
2122 | }; |
2123 | ||
5de16430 PM |
2124 | static Property arm_cpu_properties[] = { |
2125 | DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), | |
98128601 | 2126 | DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), |
51a9b04b | 2127 | DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), |
ce5b1bbf LV |
2128 | DEFINE_PROP_UINT64("mp-affinity", ARMCPU, |
2129 | mp_affinity, ARM64_AFFINITY_INVALID), | |
15f8b142 | 2130 | DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), |
f9a69711 | 2131 | DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), |
5de16430 PM |
2132 | DEFINE_PROP_END_OF_LIST() |
2133 | }; | |
2134 | ||
b3820e6c DH |
2135 | static gchar *arm_gdb_arch_name(CPUState *cs) |
2136 | { | |
2137 | ARMCPU *cpu = ARM_CPU(cs); | |
2138 | CPUARMState *env = &cpu->env; | |
2139 | ||
2140 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
2141 | return g_strdup("iwmmxt"); | |
2142 | } | |
2143 | return g_strdup("arm"); | |
2144 | } | |
2145 | ||
dec9c2d4 AF |
2146 | static void arm_cpu_class_init(ObjectClass *oc, void *data) |
2147 | { | |
2148 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
2149 | CPUClass *cc = CPU_CLASS(acc); | |
14969266 AF |
2150 | DeviceClass *dc = DEVICE_CLASS(oc); |
2151 | ||
bf853881 PMD |
2152 | device_class_set_parent_realize(dc, arm_cpu_realizefn, |
2153 | &acc->parent_realize); | |
5de16430 | 2154 | dc->props = arm_cpu_properties; |
dec9c2d4 AF |
2155 | |
2156 | acc->parent_reset = cc->reset; | |
2157 | cc->reset = arm_cpu_reset; | |
5900d6b2 AF |
2158 | |
2159 | cc->class_by_name = arm_cpu_class_by_name; | |
8c2e1b00 | 2160 | cc->has_work = arm_cpu_has_work; |
e8925712 | 2161 | cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; |
878096ee | 2162 | cc->dump_state = arm_cpu_dump_state; |
f45748f1 | 2163 | cc->set_pc = arm_cpu_set_pc; |
42f6ed91 | 2164 | cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; |
5b50e790 AF |
2165 | cc->gdb_read_register = arm_cpu_gdb_read_register; |
2166 | cc->gdb_write_register = arm_cpu_gdb_write_register; | |
7350d553 | 2167 | #ifndef CONFIG_USER_ONLY |
0adf7d3c | 2168 | cc->do_interrupt = arm_cpu_do_interrupt; |
30901475 | 2169 | cc->do_unaligned_access = arm_cpu_do_unaligned_access; |
c79c0a31 | 2170 | cc->do_transaction_failed = arm_cpu_do_transaction_failed; |
0faea0c7 | 2171 | cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; |
017518c1 | 2172 | cc->asidx_from_attrs = arm_asidx_from_attrs; |
00b941e5 | 2173 | cc->vmsd = &vmstate_arm_cpu; |
ed50ff78 | 2174 | cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; |
da2b9140 AJ |
2175 | cc->write_elf64_note = arm_cpu_write_elf64_note; |
2176 | cc->write_elf32_note = arm_cpu_write_elf32_note; | |
00b941e5 | 2177 | #endif |
a0e372f0 | 2178 | cc->gdb_num_core_regs = 26; |
5b24c641 | 2179 | cc->gdb_core_xml_file = "arm-core.xml"; |
b3820e6c | 2180 | cc->gdb_arch_name = arm_gdb_arch_name; |
200bf5b7 | 2181 | cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; |
2472b6c0 | 2182 | cc->gdb_stop_before_watchpoint = true; |
3ff6fc91 | 2183 | cc->debug_excp_handler = arm_debug_excp_handler; |
3826121d | 2184 | cc->debug_check_watchpoint = arm_debug_check_watchpoint; |
40612000 JB |
2185 | #if !defined(CONFIG_USER_ONLY) |
2186 | cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; | |
2187 | #endif | |
48440620 PC |
2188 | |
2189 | cc->disas_set_info = arm_disas_set_info; | |
74d7fc7f | 2190 | #ifdef CONFIG_TCG |
55c3ceef | 2191 | cc->tcg_initialize = arm_translate_init; |
7350d553 | 2192 | cc->tlb_fill = arm_cpu_tlb_fill; |
74d7fc7f | 2193 | #endif |
dec9c2d4 AF |
2194 | } |
2195 | ||
86f0a186 PM |
2196 | #ifdef CONFIG_KVM |
2197 | static void arm_host_initfn(Object *obj) | |
2198 | { | |
2199 | ARMCPU *cpu = ARM_CPU(obj); | |
2200 | ||
2201 | kvm_arm_set_cpu_features_from_host(cpu); | |
51e5ef45 | 2202 | arm_cpu_post_init(obj); |
86f0a186 PM |
2203 | } |
2204 | ||
2205 | static const TypeInfo host_arm_cpu_type_info = { | |
2206 | .name = TYPE_ARM_HOST_CPU, | |
2207 | #ifdef TARGET_AARCH64 | |
2208 | .parent = TYPE_AARCH64_CPU, | |
2209 | #else | |
2210 | .parent = TYPE_ARM_CPU, | |
2211 | #endif | |
2212 | .instance_init = arm_host_initfn, | |
2213 | }; | |
2214 | ||
2215 | #endif | |
2216 | ||
51e5ef45 MAL |
2217 | static void arm_cpu_instance_init(Object *obj) |
2218 | { | |
2219 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); | |
2220 | ||
2221 | acc->info->initfn(obj); | |
2222 | arm_cpu_post_init(obj); | |
2223 | } | |
2224 | ||
2225 | static void cpu_register_class_init(ObjectClass *oc, void *data) | |
2226 | { | |
2227 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
2228 | ||
2229 | acc->info = data; | |
2230 | } | |
2231 | ||
777dc784 PM |
2232 | static void cpu_register(const ARMCPUInfo *info) |
2233 | { | |
2234 | TypeInfo type_info = { | |
777dc784 PM |
2235 | .parent = TYPE_ARM_CPU, |
2236 | .instance_size = sizeof(ARMCPU), | |
51e5ef45 | 2237 | .instance_init = arm_cpu_instance_init, |
777dc784 | 2238 | .class_size = sizeof(ARMCPUClass), |
51e5ef45 MAL |
2239 | .class_init = info->class_init ?: cpu_register_class_init, |
2240 | .class_data = (void *)info, | |
777dc784 PM |
2241 | }; |
2242 | ||
51492fd1 | 2243 | type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); |
918fd083 | 2244 | type_register(&type_info); |
51492fd1 | 2245 | g_free((void *)type_info.name); |
777dc784 PM |
2246 | } |
2247 | ||
dec9c2d4 AF |
2248 | static const TypeInfo arm_cpu_type_info = { |
2249 | .name = TYPE_ARM_CPU, | |
2250 | .parent = TYPE_CPU, | |
2251 | .instance_size = sizeof(ARMCPU), | |
777dc784 | 2252 | .instance_init = arm_cpu_initfn, |
4b6a83fb | 2253 | .instance_finalize = arm_cpu_finalizefn, |
777dc784 | 2254 | .abstract = true, |
dec9c2d4 AF |
2255 | .class_size = sizeof(ARMCPUClass), |
2256 | .class_init = arm_cpu_class_init, | |
2257 | }; | |
2258 | ||
181962fd PM |
2259 | static const TypeInfo idau_interface_type_info = { |
2260 | .name = TYPE_IDAU_INTERFACE, | |
2261 | .parent = TYPE_INTERFACE, | |
2262 | .class_size = sizeof(IDAUInterfaceClass), | |
2263 | }; | |
2264 | ||
dec9c2d4 AF |
2265 | static void arm_cpu_register_types(void) |
2266 | { | |
83e6813a | 2267 | const ARMCPUInfo *info = arm_cpus; |
777dc784 | 2268 | |
dec9c2d4 | 2269 | type_register_static(&arm_cpu_type_info); |
181962fd | 2270 | type_register_static(&idau_interface_type_info); |
83e6813a PM |
2271 | |
2272 | while (info->name) { | |
2273 | cpu_register(info); | |
2274 | info++; | |
777dc784 | 2275 | } |
86f0a186 PM |
2276 | |
2277 | #ifdef CONFIG_KVM | |
2278 | type_register_static(&host_arm_cpu_type_info); | |
2279 | #endif | |
dec9c2d4 AF |
2280 | } |
2281 | ||
2282 | type_init(arm_cpu_register_types) |