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Commit | Line | Data |
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dec9c2d4 AF |
1 | /* |
2 | * QEMU ARM CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
74c21bd0 | 21 | #include "qemu/osdep.h" |
929e754d | 22 | #include "qemu/error-report.h" |
da34e65c | 23 | #include "qapi/error.h" |
778c3a06 | 24 | #include "cpu.h" |
ccd38087 | 25 | #include "internals.h" |
dec9c2d4 | 26 | #include "qemu-common.h" |
63c91552 | 27 | #include "exec/exec-all.h" |
5de16430 | 28 | #include "hw/qdev-properties.h" |
3c30dd5a PM |
29 | #if !defined(CONFIG_USER_ONLY) |
30 | #include "hw/loader.h" | |
31 | #endif | |
7c1840b6 | 32 | #include "hw/arm/arm.h" |
9c17d615 | 33 | #include "sysemu/sysemu.h" |
7c1840b6 | 34 | #include "sysemu/kvm.h" |
50a2c6e5 | 35 | #include "kvm_arm.h" |
dec9c2d4 | 36 | |
f45748f1 AF |
37 | static void arm_cpu_set_pc(CPUState *cs, vaddr value) |
38 | { | |
39 | ARMCPU *cpu = ARM_CPU(cs); | |
40 | ||
41 | cpu->env.regs[15] = value; | |
42 | } | |
43 | ||
8c2e1b00 AF |
44 | static bool arm_cpu_has_work(CPUState *cs) |
45 | { | |
543486db RH |
46 | ARMCPU *cpu = ARM_CPU(cs); |
47 | ||
48 | return !cpu->powered_off | |
49 | && cs->interrupt_request & | |
136e67e9 EI |
50 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD |
51 | | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | |
52 | | CPU_INTERRUPT_EXITTB); | |
8c2e1b00 AF |
53 | } |
54 | ||
bd7d00fc PM |
55 | void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, |
56 | void *opaque) | |
57 | { | |
58 | /* We currently only support registering a single hook function */ | |
59 | assert(!cpu->el_change_hook); | |
60 | cpu->el_change_hook = hook; | |
61 | cpu->el_change_hook_opaque = opaque; | |
62 | } | |
63 | ||
4b6a83fb PM |
64 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
65 | { | |
66 | /* Reset a single ARMCPRegInfo register */ | |
67 | ARMCPRegInfo *ri = value; | |
68 | ARMCPU *cpu = opaque; | |
69 | ||
b061a82b | 70 | if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { |
4b6a83fb PM |
71 | return; |
72 | } | |
73 | ||
74 | if (ri->resetfn) { | |
75 | ri->resetfn(&cpu->env, ri); | |
76 | return; | |
77 | } | |
78 | ||
79 | /* A zero offset is never possible as it would be regs[0] | |
80 | * so we use it to indicate that reset is being handled elsewhere. | |
81 | * This is basically only used for fields in non-core coprocessors | |
82 | * (like the pxa2xx ones). | |
83 | */ | |
84 | if (!ri->fieldoffset) { | |
85 | return; | |
86 | } | |
87 | ||
67ed771d | 88 | if (cpreg_field_is_64bit(ri)) { |
4b6a83fb PM |
89 | CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; |
90 | } else { | |
91 | CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; | |
92 | } | |
93 | } | |
94 | ||
49a66191 PM |
95 | static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) |
96 | { | |
97 | /* Purely an assertion check: we've already done reset once, | |
98 | * so now check that running the reset for the cpreg doesn't | |
99 | * change its value. This traps bugs where two different cpregs | |
100 | * both try to reset the same state field but to different values. | |
101 | */ | |
102 | ARMCPRegInfo *ri = value; | |
103 | ARMCPU *cpu = opaque; | |
104 | uint64_t oldvalue, newvalue; | |
105 | ||
106 | if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { | |
107 | return; | |
108 | } | |
109 | ||
110 | oldvalue = read_raw_cp_reg(&cpu->env, ri); | |
111 | cp_reg_reset(key, value, opaque); | |
112 | newvalue = read_raw_cp_reg(&cpu->env, ri); | |
113 | assert(oldvalue == newvalue); | |
114 | } | |
115 | ||
dec9c2d4 AF |
116 | /* CPUClass::reset() */ |
117 | static void arm_cpu_reset(CPUState *s) | |
118 | { | |
119 | ARMCPU *cpu = ARM_CPU(s); | |
120 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); | |
3c30dd5a | 121 | CPUARMState *env = &cpu->env; |
3c30dd5a | 122 | |
dec9c2d4 AF |
123 | acc->parent_reset(s); |
124 | ||
f0c3c505 | 125 | memset(env, 0, offsetof(CPUARMState, features)); |
4b6a83fb | 126 | g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
49a66191 PM |
127 | g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); |
128 | ||
3c30dd5a PM |
129 | env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
130 | env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; | |
131 | env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; | |
a50c0f51 | 132 | env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; |
3c30dd5a | 133 | |
543486db RH |
134 | cpu->powered_off = cpu->start_powered_off; |
135 | s->halted = cpu->start_powered_off; | |
136 | ||
3c30dd5a PM |
137 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { |
138 | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; | |
139 | } | |
140 | ||
3926cc84 AG |
141 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
142 | /* 64 bit CPUs always start in 64 bit mode */ | |
143 | env->aarch64 = 1; | |
d356312f PM |
144 | #if defined(CONFIG_USER_ONLY) |
145 | env->pstate = PSTATE_MODE_EL0t; | |
14e5f106 | 146 | /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ |
137feaa9 | 147 | env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; |
8c6afa6a | 148 | /* and to the FP/Neon instructions */ |
7ebd5f2e | 149 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); |
d356312f | 150 | #else |
5097227c GB |
151 | /* Reset into the highest available EL */ |
152 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
153 | env->pstate = PSTATE_MODE_EL3h; | |
154 | } else if (arm_feature(env, ARM_FEATURE_EL2)) { | |
155 | env->pstate = PSTATE_MODE_EL2h; | |
156 | } else { | |
157 | env->pstate = PSTATE_MODE_EL1h; | |
158 | } | |
3933443e | 159 | env->pc = cpu->rvbar; |
8c6afa6a PM |
160 | #endif |
161 | } else { | |
162 | #if defined(CONFIG_USER_ONLY) | |
163 | /* Userspace expects access to cp10 and cp11 for FP/Neon */ | |
7ebd5f2e | 164 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); |
d356312f | 165 | #endif |
3926cc84 AG |
166 | } |
167 | ||
3c30dd5a PM |
168 | #if defined(CONFIG_USER_ONLY) |
169 | env->uncached_cpsr = ARM_CPU_MODE_USR; | |
170 | /* For user mode we must enable access to coprocessors */ | |
171 | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; | |
172 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
173 | env->cp15.c15_cpar = 3; | |
174 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
175 | env->cp15.c15_cpar = 1; | |
176 | } | |
177 | #else | |
178 | /* SVC mode with interrupts disabled. */ | |
4cc35614 PM |
179 | env->uncached_cpsr = ARM_CPU_MODE_SVC; |
180 | env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; | |
3c30dd5a | 181 | /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is |
6e3cf5df MG |
182 | * clear at reset. Initial SP and PC are loaded from ROM. |
183 | */ | |
3c30dd5a | 184 | if (IS_M(env)) { |
6e3cf5df MG |
185 | uint32_t initial_msp; /* Loaded from 0x0 */ |
186 | uint32_t initial_pc; /* Loaded from 0x4 */ | |
3c30dd5a | 187 | uint8_t *rom; |
6e3cf5df | 188 | |
4cc35614 | 189 | env->daif &= ~PSTATE_I; |
3c30dd5a PM |
190 | rom = rom_ptr(0); |
191 | if (rom) { | |
6e3cf5df MG |
192 | /* Address zero is covered by ROM which hasn't yet been |
193 | * copied into physical memory. | |
194 | */ | |
195 | initial_msp = ldl_p(rom); | |
196 | initial_pc = ldl_p(rom + 4); | |
197 | } else { | |
198 | /* Address zero not covered by a ROM blob, or the ROM blob | |
199 | * is in non-modifiable memory and this is a second reset after | |
200 | * it got copied into memory. In the latter case, rom_ptr | |
201 | * will return a NULL pointer and we should use ldl_phys instead. | |
202 | */ | |
203 | initial_msp = ldl_phys(s->as, 0); | |
204 | initial_pc = ldl_phys(s->as, 4); | |
3c30dd5a | 205 | } |
6e3cf5df MG |
206 | |
207 | env->regs[13] = initial_msp & 0xFFFFFFFC; | |
208 | env->regs[15] = initial_pc & ~1; | |
209 | env->thumb = initial_pc & 1; | |
3c30dd5a | 210 | } |
387f9806 | 211 | |
137feaa9 FA |
212 | /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently |
213 | * executing as AArch32 then check if highvecs are enabled and | |
214 | * adjust the PC accordingly. | |
215 | */ | |
216 | if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { | |
34bf7744 | 217 | env->regs[15] = 0xFFFF0000; |
387f9806 AP |
218 | } |
219 | ||
3c30dd5a | 220 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; |
3c30dd5a PM |
221 | #endif |
222 | set_flush_to_zero(1, &env->vfp.standard_fp_status); | |
223 | set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); | |
224 | set_default_nan_mode(1, &env->vfp.standard_fp_status); | |
225 | set_float_detect_tininess(float_tininess_before_rounding, | |
226 | &env->vfp.fp_status); | |
227 | set_float_detect_tininess(float_tininess_before_rounding, | |
228 | &env->vfp.standard_fp_status); | |
00c8cb0a | 229 | tlb_flush(s, 1); |
50a2c6e5 PB |
230 | |
231 | #ifndef CONFIG_USER_ONLY | |
232 | if (kvm_enabled()) { | |
233 | kvm_arm_reset_vcpu(cpu); | |
234 | } | |
235 | #endif | |
9ee98ce8 | 236 | |
46747d15 | 237 | hw_breakpoint_update_all(cpu); |
9ee98ce8 | 238 | hw_watchpoint_update_all(cpu); |
dec9c2d4 AF |
239 | } |
240 | ||
e8925712 RH |
241 | bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
242 | { | |
243 | CPUClass *cc = CPU_GET_CLASS(cs); | |
012a906b GB |
244 | CPUARMState *env = cs->env_ptr; |
245 | uint32_t cur_el = arm_current_el(env); | |
246 | bool secure = arm_is_secure(env); | |
247 | uint32_t target_el; | |
248 | uint32_t excp_idx; | |
e8925712 RH |
249 | bool ret = false; |
250 | ||
012a906b GB |
251 | if (interrupt_request & CPU_INTERRUPT_FIQ) { |
252 | excp_idx = EXCP_FIQ; | |
253 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
254 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
255 | cs->exception_index = excp_idx; | |
256 | env->exception.target_el = target_el; | |
257 | cc->do_interrupt(cs); | |
258 | ret = true; | |
259 | } | |
e8925712 | 260 | } |
012a906b GB |
261 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
262 | excp_idx = EXCP_IRQ; | |
263 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
264 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
265 | cs->exception_index = excp_idx; | |
266 | env->exception.target_el = target_el; | |
267 | cc->do_interrupt(cs); | |
268 | ret = true; | |
269 | } | |
e8925712 | 270 | } |
012a906b GB |
271 | if (interrupt_request & CPU_INTERRUPT_VIRQ) { |
272 | excp_idx = EXCP_VIRQ; | |
273 | target_el = 1; | |
274 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
275 | cs->exception_index = excp_idx; | |
276 | env->exception.target_el = target_el; | |
277 | cc->do_interrupt(cs); | |
278 | ret = true; | |
279 | } | |
136e67e9 | 280 | } |
012a906b GB |
281 | if (interrupt_request & CPU_INTERRUPT_VFIQ) { |
282 | excp_idx = EXCP_VFIQ; | |
283 | target_el = 1; | |
284 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
285 | cs->exception_index = excp_idx; | |
286 | env->exception.target_el = target_el; | |
287 | cc->do_interrupt(cs); | |
288 | ret = true; | |
289 | } | |
136e67e9 | 290 | } |
e8925712 RH |
291 | |
292 | return ret; | |
293 | } | |
294 | ||
b5c633c5 PM |
295 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) |
296 | static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | |
297 | { | |
298 | CPUClass *cc = CPU_GET_CLASS(cs); | |
299 | ARMCPU *cpu = ARM_CPU(cs); | |
300 | CPUARMState *env = &cpu->env; | |
301 | bool ret = false; | |
302 | ||
303 | ||
304 | if (interrupt_request & CPU_INTERRUPT_FIQ | |
305 | && !(env->daif & PSTATE_F)) { | |
306 | cs->exception_index = EXCP_FIQ; | |
307 | cc->do_interrupt(cs); | |
308 | ret = true; | |
309 | } | |
310 | /* ARMv7-M interrupt return works by loading a magic value | |
311 | * into the PC. On real hardware the load causes the | |
312 | * return to occur. The qemu implementation performs the | |
313 | * jump normally, then does the exception return when the | |
314 | * CPU tries to execute code at the magic address. | |
315 | * This will cause the magic PC value to be pushed to | |
316 | * the stack if an interrupt occurred at the wrong time. | |
317 | * We avoid this by disabling interrupts when | |
318 | * pc contains a magic address. | |
319 | */ | |
320 | if (interrupt_request & CPU_INTERRUPT_HARD | |
321 | && !(env->daif & PSTATE_I) | |
322 | && (env->regs[15] < 0xfffffff0)) { | |
323 | cs->exception_index = EXCP_IRQ; | |
324 | cc->do_interrupt(cs); | |
325 | ret = true; | |
326 | } | |
327 | return ret; | |
328 | } | |
329 | #endif | |
330 | ||
7c1840b6 PM |
331 | #ifndef CONFIG_USER_ONLY |
332 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | |
333 | { | |
334 | ARMCPU *cpu = opaque; | |
136e67e9 | 335 | CPUARMState *env = &cpu->env; |
7c1840b6 | 336 | CPUState *cs = CPU(cpu); |
136e67e9 EI |
337 | static const int mask[] = { |
338 | [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, | |
339 | [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, | |
340 | [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, | |
341 | [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ | |
342 | }; | |
7c1840b6 PM |
343 | |
344 | switch (irq) { | |
136e67e9 EI |
345 | case ARM_CPU_VIRQ: |
346 | case ARM_CPU_VFIQ: | |
f128bf29 | 347 | assert(arm_feature(env, ARM_FEATURE_EL2)); |
136e67e9 EI |
348 | /* fall through */ |
349 | case ARM_CPU_IRQ: | |
7c1840b6 PM |
350 | case ARM_CPU_FIQ: |
351 | if (level) { | |
136e67e9 | 352 | cpu_interrupt(cs, mask[irq]); |
7c1840b6 | 353 | } else { |
136e67e9 | 354 | cpu_reset_interrupt(cs, mask[irq]); |
7c1840b6 PM |
355 | } |
356 | break; | |
357 | default: | |
8f6fd322 | 358 | g_assert_not_reached(); |
7c1840b6 PM |
359 | } |
360 | } | |
361 | ||
362 | static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) | |
363 | { | |
364 | #ifdef CONFIG_KVM | |
365 | ARMCPU *cpu = opaque; | |
366 | CPUState *cs = CPU(cpu); | |
367 | int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; | |
368 | ||
369 | switch (irq) { | |
370 | case ARM_CPU_IRQ: | |
371 | kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; | |
372 | break; | |
373 | case ARM_CPU_FIQ: | |
374 | kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; | |
375 | break; | |
376 | default: | |
8f6fd322 | 377 | g_assert_not_reached(); |
7c1840b6 PM |
378 | } |
379 | kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; | |
380 | kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); | |
381 | #endif | |
382 | } | |
84f2bed3 | 383 | |
ed50ff78 | 384 | static bool arm_cpu_virtio_is_big_endian(CPUState *cs) |
84f2bed3 PS |
385 | { |
386 | ARMCPU *cpu = ARM_CPU(cs); | |
387 | CPUARMState *env = &cpu->env; | |
84f2bed3 PS |
388 | |
389 | cpu_synchronize_state(cs); | |
ed50ff78 | 390 | return arm_cpu_data_is_big_endian(env); |
84f2bed3 PS |
391 | } |
392 | ||
7c1840b6 PM |
393 | #endif |
394 | ||
581be094 PM |
395 | static inline void set_feature(CPUARMState *env, int feature) |
396 | { | |
918f5dca | 397 | env->features |= 1ULL << feature; |
581be094 PM |
398 | } |
399 | ||
08828484 GB |
400 | static inline void unset_feature(CPUARMState *env, int feature) |
401 | { | |
402 | env->features &= ~(1ULL << feature); | |
403 | } | |
404 | ||
48440620 PC |
405 | static int |
406 | print_insn_thumb1(bfd_vma pc, disassemble_info *info) | |
407 | { | |
408 | return print_insn_arm(pc | 1, info); | |
409 | } | |
410 | ||
411 | static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) | |
412 | { | |
413 | ARMCPU *ac = ARM_CPU(cpu); | |
414 | CPUARMState *env = &ac->env; | |
415 | ||
416 | if (is_a64(env)) { | |
417 | /* We might not be compiled with the A64 disassembler | |
418 | * because it needs a C++ compiler. Leave print_insn | |
419 | * unset in this case to use the caller default behaviour. | |
420 | */ | |
421 | #if defined(CONFIG_ARM_A64_DIS) | |
422 | info->print_insn = print_insn_arm_a64; | |
423 | #endif | |
424 | } else if (env->thumb) { | |
425 | info->print_insn = print_insn_thumb1; | |
426 | } else { | |
427 | info->print_insn = print_insn_arm; | |
428 | } | |
f9fd40eb | 429 | if (bswap_code(arm_sctlr_b(env))) { |
48440620 PC |
430 | #ifdef TARGET_WORDS_BIGENDIAN |
431 | info->endian = BFD_ENDIAN_LITTLE; | |
432 | #else | |
433 | info->endian = BFD_ENDIAN_BIG; | |
434 | #endif | |
435 | } | |
436 | } | |
437 | ||
777dc784 PM |
438 | static void arm_cpu_initfn(Object *obj) |
439 | { | |
c05efcb1 | 440 | CPUState *cs = CPU(obj); |
777dc784 | 441 | ARMCPU *cpu = ARM_CPU(obj); |
79614b78 | 442 | static bool inited; |
777dc784 | 443 | |
c05efcb1 | 444 | cs->env_ptr = &cpu->env; |
4b6a83fb PM |
445 | cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
446 | g_free, g_free); | |
79614b78 | 447 | |
7c1840b6 PM |
448 | #ifndef CONFIG_USER_ONLY |
449 | /* Our inbound IRQ and FIQ lines */ | |
450 | if (kvm_enabled()) { | |
136e67e9 EI |
451 | /* VIRQ and VFIQ are unused with KVM but we add them to maintain |
452 | * the same interface as non-KVM CPUs. | |
453 | */ | |
454 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); | |
7c1840b6 | 455 | } else { |
136e67e9 | 456 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); |
7c1840b6 | 457 | } |
55d284af | 458 | |
bc72ad67 | 459 | cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
55d284af | 460 | arm_gt_ptimer_cb, cpu); |
bc72ad67 | 461 | cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
55d284af | 462 | arm_gt_vtimer_cb, cpu); |
b0e66d95 EI |
463 | cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
464 | arm_gt_htimer_cb, cpu); | |
b4d3978c PM |
465 | cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
466 | arm_gt_stimer_cb, cpu); | |
55d284af PM |
467 | qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, |
468 | ARRAY_SIZE(cpu->gt_timer_outputs)); | |
7c1840b6 PM |
469 | #endif |
470 | ||
54d3e3f5 PM |
471 | /* DTB consumers generally don't in fact care what the 'compatible' |
472 | * string is, so always provide some string and trust that a hypothetical | |
473 | * picky DTB consumer will also provide a helpful error message. | |
474 | */ | |
475 | cpu->dtb_compatible = "qemu,unknown"; | |
dd032e34 | 476 | cpu->psci_version = 1; /* By default assume PSCI v0.1 */ |
3541addc | 477 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; |
54d3e3f5 | 478 | |
98128601 RH |
479 | if (tcg_enabled()) { |
480 | cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ | |
481 | if (!inited) { | |
482 | inited = true; | |
483 | arm_translate_init(); | |
484 | } | |
79614b78 | 485 | } |
4b6a83fb PM |
486 | } |
487 | ||
07a5b0d2 | 488 | static Property arm_cpu_reset_cbar_property = |
f318cec6 | 489 | DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); |
07a5b0d2 | 490 | |
68e0a40a AP |
491 | static Property arm_cpu_reset_hivecs_property = |
492 | DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); | |
493 | ||
3933443e PM |
494 | static Property arm_cpu_rvbar_property = |
495 | DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); | |
496 | ||
51942aee GB |
497 | static Property arm_cpu_has_el3_property = |
498 | DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); | |
499 | ||
929e754d WH |
500 | /* use property name "pmu" to match other archs and virt tools */ |
501 | static Property arm_cpu_has_pmu_property = | |
502 | DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); | |
503 | ||
8f325f56 PC |
504 | static Property arm_cpu_has_mpu_property = |
505 | DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); | |
506 | ||
3281af81 PC |
507 | static Property arm_cpu_pmsav7_dregion_property = |
508 | DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16); | |
509 | ||
07a5b0d2 PC |
510 | static void arm_cpu_post_init(Object *obj) |
511 | { | |
512 | ARMCPU *cpu = ARM_CPU(obj); | |
07a5b0d2 | 513 | |
f318cec6 PM |
514 | if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || |
515 | arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { | |
07a5b0d2 | 516 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, |
5433a0a8 | 517 | &error_abort); |
07a5b0d2 | 518 | } |
68e0a40a AP |
519 | |
520 | if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
521 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, | |
5433a0a8 | 522 | &error_abort); |
68e0a40a | 523 | } |
3933443e PM |
524 | |
525 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
526 | qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, | |
527 | &error_abort); | |
528 | } | |
51942aee GB |
529 | |
530 | if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { | |
531 | /* Add the has_el3 state CPU property only if EL3 is allowed. This will | |
532 | * prevent "has_el3" from existing on CPUs which cannot support EL3. | |
533 | */ | |
534 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, | |
535 | &error_abort); | |
9e273ef2 PM |
536 | |
537 | #ifndef CONFIG_USER_ONLY | |
538 | object_property_add_link(obj, "secure-memory", | |
539 | TYPE_MEMORY_REGION, | |
540 | (Object **)&cpu->secure_memory, | |
541 | qdev_prop_allow_set_link_before_realize, | |
542 | OBJ_PROP_LINK_UNREF_ON_RELEASE, | |
543 | &error_abort); | |
544 | #endif | |
51942aee | 545 | } |
8f325f56 | 546 | |
929e754d WH |
547 | if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { |
548 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, | |
549 | &error_abort); | |
550 | } | |
551 | ||
8f325f56 PC |
552 | if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) { |
553 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, | |
554 | &error_abort); | |
3281af81 PC |
555 | if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { |
556 | qdev_property_add_static(DEVICE(obj), | |
557 | &arm_cpu_pmsav7_dregion_property, | |
558 | &error_abort); | |
559 | } | |
8f325f56 PC |
560 | } |
561 | ||
07a5b0d2 PC |
562 | } |
563 | ||
4b6a83fb PM |
564 | static void arm_cpu_finalizefn(Object *obj) |
565 | { | |
566 | ARMCPU *cpu = ARM_CPU(obj); | |
567 | g_hash_table_destroy(cpu->cp_regs); | |
777dc784 PM |
568 | } |
569 | ||
14969266 | 570 | static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
581be094 | 571 | { |
14a10fc3 | 572 | CPUState *cs = CPU(dev); |
14969266 AF |
573 | ARMCPU *cpu = ARM_CPU(dev); |
574 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); | |
581be094 | 575 | CPUARMState *env = &cpu->env; |
e97da98f | 576 | int pagebits; |
ce5b1bbf LV |
577 | Error *local_err = NULL; |
578 | ||
579 | cpu_exec_realizefn(cs, &local_err); | |
580 | if (local_err != NULL) { | |
581 | error_propagate(errp, local_err); | |
582 | return; | |
583 | } | |
14969266 | 584 | |
581be094 | 585 | /* Some features automatically imply others: */ |
81e69fb0 MR |
586 | if (arm_feature(env, ARM_FEATURE_V8)) { |
587 | set_feature(env, ARM_FEATURE_V7); | |
588 | set_feature(env, ARM_FEATURE_ARM_DIV); | |
589 | set_feature(env, ARM_FEATURE_LPAE); | |
590 | } | |
581be094 PM |
591 | if (arm_feature(env, ARM_FEATURE_V7)) { |
592 | set_feature(env, ARM_FEATURE_VAPA); | |
593 | set_feature(env, ARM_FEATURE_THUMB2); | |
81bdde9d | 594 | set_feature(env, ARM_FEATURE_MPIDR); |
581be094 PM |
595 | if (!arm_feature(env, ARM_FEATURE_M)) { |
596 | set_feature(env, ARM_FEATURE_V6K); | |
597 | } else { | |
598 | set_feature(env, ARM_FEATURE_V6); | |
599 | } | |
600 | } | |
601 | if (arm_feature(env, ARM_FEATURE_V6K)) { | |
602 | set_feature(env, ARM_FEATURE_V6); | |
603 | set_feature(env, ARM_FEATURE_MVFR); | |
604 | } | |
605 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
606 | set_feature(env, ARM_FEATURE_V5); | |
607 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
608 | set_feature(env, ARM_FEATURE_AUXCR); | |
609 | } | |
610 | } | |
611 | if (arm_feature(env, ARM_FEATURE_V5)) { | |
612 | set_feature(env, ARM_FEATURE_V4T); | |
613 | } | |
614 | if (arm_feature(env, ARM_FEATURE_M)) { | |
615 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
616 | } | |
617 | if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { | |
618 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
619 | } | |
620 | if (arm_feature(env, ARM_FEATURE_VFP4)) { | |
621 | set_feature(env, ARM_FEATURE_VFP3); | |
da5141fc | 622 | set_feature(env, ARM_FEATURE_VFP_FP16); |
581be094 PM |
623 | } |
624 | if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
625 | set_feature(env, ARM_FEATURE_VFP); | |
626 | } | |
de9b05b8 | 627 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
bdcc150d | 628 | set_feature(env, ARM_FEATURE_V7MP); |
de9b05b8 PM |
629 | set_feature(env, ARM_FEATURE_PXN); |
630 | } | |
f318cec6 PM |
631 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { |
632 | set_feature(env, ARM_FEATURE_CBAR); | |
633 | } | |
62b44f05 AR |
634 | if (arm_feature(env, ARM_FEATURE_THUMB2) && |
635 | !arm_feature(env, ARM_FEATURE_M)) { | |
636 | set_feature(env, ARM_FEATURE_THUMB_DSP); | |
637 | } | |
2ceb98c0 | 638 | |
e97da98f PM |
639 | if (arm_feature(env, ARM_FEATURE_V7) && |
640 | !arm_feature(env, ARM_FEATURE_M) && | |
641 | !arm_feature(env, ARM_FEATURE_MPU)) { | |
642 | /* v7VMSA drops support for the old ARMv5 tiny pages, so we | |
643 | * can use 4K pages. | |
644 | */ | |
645 | pagebits = 12; | |
646 | } else { | |
647 | /* For CPUs which might have tiny 1K pages, or which have an | |
648 | * MPU and might have small region sizes, stick with 1K pages. | |
649 | */ | |
650 | pagebits = 10; | |
651 | } | |
652 | if (!set_preferred_target_page_bits(pagebits)) { | |
653 | /* This can only ever happen for hotplugging a CPU, or if | |
654 | * the board code incorrectly creates a CPU which it has | |
655 | * promised via minimum_page_size that it will not. | |
656 | */ | |
657 | error_setg(errp, "This CPU requires a smaller page size than the " | |
658 | "system is using"); | |
659 | return; | |
660 | } | |
661 | ||
ce5b1bbf LV |
662 | /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. |
663 | * We don't support setting cluster ID ([16..23]) (known as Aff2 | |
664 | * in later ARM ARM versions), or any of the higher affinity level fields, | |
665 | * so these bits always RAZ. | |
666 | */ | |
667 | if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { | |
668 | uint32_t Aff1 = cs->cpu_index / ARM_DEFAULT_CPUS_PER_CLUSTER; | |
669 | uint32_t Aff0 = cs->cpu_index % ARM_DEFAULT_CPUS_PER_CLUSTER; | |
670 | cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0; | |
671 | } | |
672 | ||
68e0a40a AP |
673 | if (cpu->reset_hivecs) { |
674 | cpu->reset_sctlr |= (1 << 13); | |
675 | } | |
676 | ||
51942aee GB |
677 | if (!cpu->has_el3) { |
678 | /* If the has_el3 CPU property is disabled then we need to disable the | |
679 | * feature. | |
680 | */ | |
681 | unset_feature(env, ARM_FEATURE_EL3); | |
682 | ||
683 | /* Disable the security extension feature bits in the processor feature | |
3d5c84ff | 684 | * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. |
51942aee GB |
685 | */ |
686 | cpu->id_pfr1 &= ~0xf0; | |
3d5c84ff | 687 | cpu->id_aa64pfr0 &= ~0xf000; |
51942aee GB |
688 | } |
689 | ||
929e754d WH |
690 | if (!cpu->has_pmu || !kvm_enabled()) { |
691 | cpu->has_pmu = false; | |
692 | unset_feature(env, ARM_FEATURE_PMU); | |
693 | } | |
694 | ||
3c2f7bb3 PM |
695 | if (!arm_feature(env, ARM_FEATURE_EL2)) { |
696 | /* Disable the hypervisor feature bits in the processor feature | |
697 | * registers if we don't have EL2. These are id_pfr1[15:12] and | |
698 | * id_aa64pfr0_el1[11:8]. | |
699 | */ | |
700 | cpu->id_aa64pfr0 &= ~0xf00; | |
701 | cpu->id_pfr1 &= ~0xf000; | |
702 | } | |
703 | ||
8f325f56 PC |
704 | if (!cpu->has_mpu) { |
705 | unset_feature(env, ARM_FEATURE_MPU); | |
706 | } | |
707 | ||
3281af81 PC |
708 | if (arm_feature(env, ARM_FEATURE_MPU) && |
709 | arm_feature(env, ARM_FEATURE_V7)) { | |
710 | uint32_t nr = cpu->pmsav7_dregion; | |
711 | ||
712 | if (nr > 0xff) { | |
9af9e0fe | 713 | error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); |
3281af81 PC |
714 | return; |
715 | } | |
6cb0b013 PC |
716 | |
717 | if (nr) { | |
718 | env->pmsav7.drbar = g_new0(uint32_t, nr); | |
719 | env->pmsav7.drsr = g_new0(uint32_t, nr); | |
720 | env->pmsav7.dracr = g_new0(uint32_t, nr); | |
721 | } | |
3281af81 PC |
722 | } |
723 | ||
2ceb98c0 | 724 | register_cp_regs_for_features(cpu); |
14969266 AF |
725 | arm_cpu_register_gdb_regs_for_features(cpu); |
726 | ||
721fae12 PM |
727 | init_cpreg_list(cpu); |
728 | ||
9e273ef2 PM |
729 | #ifndef CONFIG_USER_ONLY |
730 | if (cpu->has_el3) { | |
731 | cs->num_ases = 2; | |
732 | } else { | |
733 | cs->num_ases = 1; | |
734 | } | |
735 | ||
736 | if (cpu->has_el3) { | |
737 | AddressSpace *as; | |
738 | ||
739 | if (!cpu->secure_memory) { | |
740 | cpu->secure_memory = cs->memory; | |
741 | } | |
742 | as = address_space_init_shareable(cpu->secure_memory, | |
743 | "cpu-secure-memory"); | |
744 | cpu_address_space_init(cs, as, ARMASIdx_S); | |
745 | } | |
746 | cpu_address_space_init(cs, | |
747 | address_space_init_shareable(cs->memory, | |
748 | "cpu-memory"), | |
749 | ARMASIdx_NS); | |
750 | #endif | |
751 | ||
14a10fc3 | 752 | qemu_init_vcpu(cs); |
00d0f7cb | 753 | cpu_reset(cs); |
14969266 AF |
754 | |
755 | acc->parent_realize(dev, errp); | |
581be094 PM |
756 | } |
757 | ||
5900d6b2 AF |
758 | static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) |
759 | { | |
760 | ObjectClass *oc; | |
51492fd1 | 761 | char *typename; |
fb8d6c24 | 762 | char **cpuname; |
5900d6b2 AF |
763 | |
764 | if (!cpu_model) { | |
765 | return NULL; | |
766 | } | |
767 | ||
fb8d6c24 GB |
768 | cpuname = g_strsplit(cpu_model, ",", 1); |
769 | typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]); | |
51492fd1 | 770 | oc = object_class_by_name(typename); |
fb8d6c24 | 771 | g_strfreev(cpuname); |
51492fd1 | 772 | g_free(typename); |
245fb54d AF |
773 | if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || |
774 | object_class_is_abstract(oc)) { | |
5900d6b2 AF |
775 | return NULL; |
776 | } | |
777 | return oc; | |
778 | } | |
779 | ||
15ee776b PM |
780 | /* CPU models. These are not needed for the AArch64 linux-user build. */ |
781 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | |
782 | ||
777dc784 PM |
783 | static void arm926_initfn(Object *obj) |
784 | { | |
785 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
786 | |
787 | cpu->dtb_compatible = "arm,arm926"; | |
581be094 PM |
788 | set_feature(&cpu->env, ARM_FEATURE_V5); |
789 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
790 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
791 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 792 | cpu->midr = 0x41069265; |
325b3cef | 793 | cpu->reset_fpsid = 0x41011090; |
64e1671f | 794 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 795 | cpu->reset_sctlr = 0x00090078; |
777dc784 PM |
796 | } |
797 | ||
798 | static void arm946_initfn(Object *obj) | |
799 | { | |
800 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
801 | |
802 | cpu->dtb_compatible = "arm,arm946"; | |
581be094 PM |
803 | set_feature(&cpu->env, ARM_FEATURE_V5); |
804 | set_feature(&cpu->env, ARM_FEATURE_MPU); | |
c4804214 | 805 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 806 | cpu->midr = 0x41059461; |
64e1671f | 807 | cpu->ctr = 0x0f004006; |
0ca7e01c | 808 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
809 | } |
810 | ||
811 | static void arm1026_initfn(Object *obj) | |
812 | { | |
813 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
814 | |
815 | cpu->dtb_compatible = "arm,arm1026"; | |
581be094 PM |
816 | set_feature(&cpu->env, ARM_FEATURE_V5); |
817 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
818 | set_feature(&cpu->env, ARM_FEATURE_AUXCR); | |
c4804214 PM |
819 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
820 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 821 | cpu->midr = 0x4106a262; |
325b3cef | 822 | cpu->reset_fpsid = 0x410110a0; |
64e1671f | 823 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 824 | cpu->reset_sctlr = 0x00090078; |
2771db27 | 825 | cpu->reset_auxcr = 1; |
06d76f31 PM |
826 | { |
827 | /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ | |
828 | ARMCPRegInfo ifar = { | |
829 | .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
830 | .access = PL1_RW, | |
b848ce2b | 831 | .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), |
06d76f31 PM |
832 | .resetvalue = 0 |
833 | }; | |
834 | define_one_arm_cp_reg(cpu, &ifar); | |
835 | } | |
777dc784 PM |
836 | } |
837 | ||
838 | static void arm1136_r2_initfn(Object *obj) | |
839 | { | |
840 | ARMCPU *cpu = ARM_CPU(obj); | |
2e4d7e3e PM |
841 | /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an |
842 | * older core than plain "arm1136". In particular this does not | |
843 | * have the v6K features. | |
844 | * These ID register values are correct for 1136 but may be wrong | |
845 | * for 1136_r2 (in particular r0p2 does not actually implement most | |
846 | * of the ID registers). | |
847 | */ | |
54d3e3f5 PM |
848 | |
849 | cpu->dtb_compatible = "arm,arm1136"; | |
581be094 PM |
850 | set_feature(&cpu->env, ARM_FEATURE_V6); |
851 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
852 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
853 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
854 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 855 | cpu->midr = 0x4107b362; |
325b3cef | 856 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
857 | cpu->mvfr0 = 0x11111111; |
858 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 859 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 860 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
861 | cpu->id_pfr0 = 0x111; |
862 | cpu->id_pfr1 = 0x1; | |
863 | cpu->id_dfr0 = 0x2; | |
864 | cpu->id_afr0 = 0x3; | |
865 | cpu->id_mmfr0 = 0x01130003; | |
866 | cpu->id_mmfr1 = 0x10030302; | |
867 | cpu->id_mmfr2 = 0x01222110; | |
868 | cpu->id_isar0 = 0x00140011; | |
869 | cpu->id_isar1 = 0x12002111; | |
870 | cpu->id_isar2 = 0x11231111; | |
871 | cpu->id_isar3 = 0x01102131; | |
872 | cpu->id_isar4 = 0x141; | |
2771db27 | 873 | cpu->reset_auxcr = 7; |
777dc784 PM |
874 | } |
875 | ||
876 | static void arm1136_initfn(Object *obj) | |
877 | { | |
878 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
879 | |
880 | cpu->dtb_compatible = "arm,arm1136"; | |
581be094 PM |
881 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
882 | set_feature(&cpu->env, ARM_FEATURE_V6); | |
883 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
884 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
885 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
886 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 887 | cpu->midr = 0x4117b363; |
325b3cef | 888 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
889 | cpu->mvfr0 = 0x11111111; |
890 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 891 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 892 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
893 | cpu->id_pfr0 = 0x111; |
894 | cpu->id_pfr1 = 0x1; | |
895 | cpu->id_dfr0 = 0x2; | |
896 | cpu->id_afr0 = 0x3; | |
897 | cpu->id_mmfr0 = 0x01130003; | |
898 | cpu->id_mmfr1 = 0x10030302; | |
899 | cpu->id_mmfr2 = 0x01222110; | |
900 | cpu->id_isar0 = 0x00140011; | |
901 | cpu->id_isar1 = 0x12002111; | |
902 | cpu->id_isar2 = 0x11231111; | |
903 | cpu->id_isar3 = 0x01102131; | |
904 | cpu->id_isar4 = 0x141; | |
2771db27 | 905 | cpu->reset_auxcr = 7; |
777dc784 PM |
906 | } |
907 | ||
908 | static void arm1176_initfn(Object *obj) | |
909 | { | |
910 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
911 | |
912 | cpu->dtb_compatible = "arm,arm1176"; | |
581be094 PM |
913 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
914 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
915 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
c4804214 PM |
916 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
917 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
918 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
c0ccb02d | 919 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
b2d06f96 | 920 | cpu->midr = 0x410fb767; |
325b3cef | 921 | cpu->reset_fpsid = 0x410120b5; |
bd35c355 PM |
922 | cpu->mvfr0 = 0x11111111; |
923 | cpu->mvfr1 = 0x00000000; | |
64e1671f | 924 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 925 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
926 | cpu->id_pfr0 = 0x111; |
927 | cpu->id_pfr1 = 0x11; | |
928 | cpu->id_dfr0 = 0x33; | |
929 | cpu->id_afr0 = 0; | |
930 | cpu->id_mmfr0 = 0x01130003; | |
931 | cpu->id_mmfr1 = 0x10030302; | |
932 | cpu->id_mmfr2 = 0x01222100; | |
933 | cpu->id_isar0 = 0x0140011; | |
934 | cpu->id_isar1 = 0x12002111; | |
935 | cpu->id_isar2 = 0x11231121; | |
936 | cpu->id_isar3 = 0x01102131; | |
937 | cpu->id_isar4 = 0x01141; | |
2771db27 | 938 | cpu->reset_auxcr = 7; |
777dc784 PM |
939 | } |
940 | ||
941 | static void arm11mpcore_initfn(Object *obj) | |
942 | { | |
943 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
944 | |
945 | cpu->dtb_compatible = "arm,arm11mpcore"; | |
581be094 PM |
946 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
947 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
948 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
81bdde9d | 949 | set_feature(&cpu->env, ARM_FEATURE_MPIDR); |
c4804214 | 950 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 951 | cpu->midr = 0x410fb022; |
325b3cef | 952 | cpu->reset_fpsid = 0x410120b4; |
bd35c355 PM |
953 | cpu->mvfr0 = 0x11111111; |
954 | cpu->mvfr1 = 0x00000000; | |
200bf596 | 955 | cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ |
2e4d7e3e PM |
956 | cpu->id_pfr0 = 0x111; |
957 | cpu->id_pfr1 = 0x1; | |
958 | cpu->id_dfr0 = 0; | |
959 | cpu->id_afr0 = 0x2; | |
960 | cpu->id_mmfr0 = 0x01100103; | |
961 | cpu->id_mmfr1 = 0x10020302; | |
962 | cpu->id_mmfr2 = 0x01222000; | |
963 | cpu->id_isar0 = 0x00100011; | |
964 | cpu->id_isar1 = 0x12002111; | |
965 | cpu->id_isar2 = 0x11221011; | |
966 | cpu->id_isar3 = 0x01102131; | |
967 | cpu->id_isar4 = 0x141; | |
2771db27 | 968 | cpu->reset_auxcr = 1; |
777dc784 PM |
969 | } |
970 | ||
971 | static void cortex_m3_initfn(Object *obj) | |
972 | { | |
973 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
974 | set_feature(&cpu->env, ARM_FEATURE_V7); |
975 | set_feature(&cpu->env, ARM_FEATURE_M); | |
b2d06f96 | 976 | cpu->midr = 0x410fc231; |
777dc784 PM |
977 | } |
978 | ||
ba890a9b AR |
979 | static void cortex_m4_initfn(Object *obj) |
980 | { | |
981 | ARMCPU *cpu = ARM_CPU(obj); | |
982 | ||
983 | set_feature(&cpu->env, ARM_FEATURE_V7); | |
984 | set_feature(&cpu->env, ARM_FEATURE_M); | |
985 | set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | |
986 | cpu->midr = 0x410fc240; /* r0p0 */ | |
987 | } | |
e6f010cc AF |
988 | static void arm_v7m_class_init(ObjectClass *oc, void *data) |
989 | { | |
e6f010cc AF |
990 | CPUClass *cc = CPU_CLASS(oc); |
991 | ||
b5c633c5 | 992 | #ifndef CONFIG_USER_ONLY |
e6f010cc AF |
993 | cc->do_interrupt = arm_v7m_cpu_do_interrupt; |
994 | #endif | |
b5c633c5 PM |
995 | |
996 | cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; | |
e6f010cc AF |
997 | } |
998 | ||
d6a6b13e PC |
999 | static const ARMCPRegInfo cortexr5_cp_reginfo[] = { |
1000 | /* Dummy the TCM region regs for the moment */ | |
1001 | { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
1002 | .access = PL1_RW, .type = ARM_CP_CONST }, | |
1003 | { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
1004 | .access = PL1_RW, .type = ARM_CP_CONST }, | |
1005 | REGINFO_SENTINEL | |
1006 | }; | |
1007 | ||
1008 | static void cortex_r5_initfn(Object *obj) | |
1009 | { | |
1010 | ARMCPU *cpu = ARM_CPU(obj); | |
1011 | ||
1012 | set_feature(&cpu->env, ARM_FEATURE_V7); | |
1013 | set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); | |
1014 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
1015 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
1016 | set_feature(&cpu->env, ARM_FEATURE_MPU); | |
1017 | cpu->midr = 0x411fc153; /* r1p3 */ | |
1018 | cpu->id_pfr0 = 0x0131; | |
1019 | cpu->id_pfr1 = 0x001; | |
1020 | cpu->id_dfr0 = 0x010400; | |
1021 | cpu->id_afr0 = 0x0; | |
1022 | cpu->id_mmfr0 = 0x0210030; | |
1023 | cpu->id_mmfr1 = 0x00000000; | |
1024 | cpu->id_mmfr2 = 0x01200000; | |
1025 | cpu->id_mmfr3 = 0x0211; | |
1026 | cpu->id_isar0 = 0x2101111; | |
1027 | cpu->id_isar1 = 0x13112111; | |
1028 | cpu->id_isar2 = 0x21232141; | |
1029 | cpu->id_isar3 = 0x01112131; | |
1030 | cpu->id_isar4 = 0x0010142; | |
1031 | cpu->id_isar5 = 0x0; | |
1032 | cpu->mp_is_up = true; | |
1033 | define_arm_cp_regs(cpu, cortexr5_cp_reginfo); | |
1034 | } | |
1035 | ||
34f90529 PM |
1036 | static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |
1037 | { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, | |
1038 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1039 | { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
1040 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1041 | REGINFO_SENTINEL | |
1042 | }; | |
1043 | ||
777dc784 PM |
1044 | static void cortex_a8_initfn(Object *obj) |
1045 | { | |
1046 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1047 | |
1048 | cpu->dtb_compatible = "arm,cortex-a8"; | |
581be094 PM |
1049 | set_feature(&cpu->env, ARM_FEATURE_V7); |
1050 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
1051 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
1052 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c4804214 | 1053 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
c0ccb02d | 1054 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
b2d06f96 | 1055 | cpu->midr = 0x410fc080; |
325b3cef | 1056 | cpu->reset_fpsid = 0x410330c0; |
bd35c355 PM |
1057 | cpu->mvfr0 = 0x11110222; |
1058 | cpu->mvfr1 = 0x00011100; | |
64e1671f | 1059 | cpu->ctr = 0x82048004; |
0ca7e01c | 1060 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
1061 | cpu->id_pfr0 = 0x1031; |
1062 | cpu->id_pfr1 = 0x11; | |
1063 | cpu->id_dfr0 = 0x400; | |
1064 | cpu->id_afr0 = 0; | |
1065 | cpu->id_mmfr0 = 0x31100003; | |
1066 | cpu->id_mmfr1 = 0x20000000; | |
1067 | cpu->id_mmfr2 = 0x01202000; | |
1068 | cpu->id_mmfr3 = 0x11; | |
1069 | cpu->id_isar0 = 0x00101111; | |
1070 | cpu->id_isar1 = 0x12112111; | |
1071 | cpu->id_isar2 = 0x21232031; | |
1072 | cpu->id_isar3 = 0x11112131; | |
1073 | cpu->id_isar4 = 0x00111142; | |
48eb3ae6 | 1074 | cpu->dbgdidr = 0x15141000; |
85df3786 PM |
1075 | cpu->clidr = (1 << 27) | (2 << 24) | 3; |
1076 | cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ | |
1077 | cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ | |
1078 | cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ | |
2771db27 | 1079 | cpu->reset_auxcr = 2; |
34f90529 | 1080 | define_arm_cp_regs(cpu, cortexa8_cp_reginfo); |
777dc784 PM |
1081 | } |
1082 | ||
1047b9d7 PM |
1083 | static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
1084 | /* power_control should be set to maximum latency. Again, | |
1085 | * default to 0 and set by private hook | |
1086 | */ | |
1087 | { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, | |
1088 | .access = PL1_RW, .resetvalue = 0, | |
1089 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, | |
1090 | { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1091 | .access = PL1_RW, .resetvalue = 0, | |
1092 | .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, | |
1093 | { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, | |
1094 | .access = PL1_RW, .resetvalue = 0, | |
1095 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, | |
1096 | { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
1097 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1098 | /* TLB lockdown control */ | |
1099 | { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, | |
1100 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
1101 | { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, | |
1102 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
1103 | { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, | |
1104 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1105 | { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, | |
1106 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1107 | { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, | |
1108 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1109 | REGINFO_SENTINEL | |
1110 | }; | |
1111 | ||
777dc784 PM |
1112 | static void cortex_a9_initfn(Object *obj) |
1113 | { | |
1114 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1115 | |
1116 | cpu->dtb_compatible = "arm,cortex-a9"; | |
581be094 PM |
1117 | set_feature(&cpu->env, ARM_FEATURE_V7); |
1118 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
1119 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
1120 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
1121 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c0ccb02d | 1122 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
581be094 PM |
1123 | /* Note that A9 supports the MP extensions even for |
1124 | * A9UP and single-core A9MP (which are both different | |
1125 | * and valid configurations; we don't model A9UP). | |
1126 | */ | |
1127 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
d8ba780b | 1128 | set_feature(&cpu->env, ARM_FEATURE_CBAR); |
b2d06f96 | 1129 | cpu->midr = 0x410fc090; |
325b3cef | 1130 | cpu->reset_fpsid = 0x41033090; |
bd35c355 PM |
1131 | cpu->mvfr0 = 0x11110222; |
1132 | cpu->mvfr1 = 0x01111111; | |
64e1671f | 1133 | cpu->ctr = 0x80038003; |
0ca7e01c | 1134 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
1135 | cpu->id_pfr0 = 0x1031; |
1136 | cpu->id_pfr1 = 0x11; | |
1137 | cpu->id_dfr0 = 0x000; | |
1138 | cpu->id_afr0 = 0; | |
1139 | cpu->id_mmfr0 = 0x00100103; | |
1140 | cpu->id_mmfr1 = 0x20000000; | |
1141 | cpu->id_mmfr2 = 0x01230000; | |
1142 | cpu->id_mmfr3 = 0x00002111; | |
1143 | cpu->id_isar0 = 0x00101111; | |
1144 | cpu->id_isar1 = 0x13112111; | |
1145 | cpu->id_isar2 = 0x21232041; | |
1146 | cpu->id_isar3 = 0x11112131; | |
1147 | cpu->id_isar4 = 0x00111142; | |
48eb3ae6 | 1148 | cpu->dbgdidr = 0x35141000; |
85df3786 | 1149 | cpu->clidr = (1 << 27) | (1 << 24) | 3; |
f7838b52 PC |
1150 | cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ |
1151 | cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ | |
d8ba780b | 1152 | define_arm_cp_regs(cpu, cortexa9_cp_reginfo); |
777dc784 PM |
1153 | } |
1154 | ||
34f90529 | 1155 | #ifndef CONFIG_USER_ONLY |
c4241c7d | 1156 | static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
34f90529 PM |
1157 | { |
1158 | /* Linux wants the number of processors from here. | |
1159 | * Might as well set the interrupt-controller bit too. | |
1160 | */ | |
c4241c7d | 1161 | return ((smp_cpus - 1) << 24) | (1 << 23); |
34f90529 PM |
1162 | } |
1163 | #endif | |
1164 | ||
1165 | static const ARMCPRegInfo cortexa15_cp_reginfo[] = { | |
1166 | #ifndef CONFIG_USER_ONLY | |
1167 | { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
1168 | .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, | |
1169 | .writefn = arm_cp_write_ignore, }, | |
1170 | #endif | |
1171 | { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, | |
1172 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1173 | REGINFO_SENTINEL | |
1174 | }; | |
1175 | ||
dcf578ed AY |
1176 | static void cortex_a7_initfn(Object *obj) |
1177 | { | |
1178 | ARMCPU *cpu = ARM_CPU(obj); | |
1179 | ||
1180 | cpu->dtb_compatible = "arm,cortex-a7"; | |
1181 | set_feature(&cpu->env, ARM_FEATURE_V7); | |
1182 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
1183 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
1184 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
1185 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
1186 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | |
1187 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | |
1188 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | |
1189 | set_feature(&cpu->env, ARM_FEATURE_LPAE); | |
1190 | set_feature(&cpu->env, ARM_FEATURE_EL3); | |
1191 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; | |
1192 | cpu->midr = 0x410fc075; | |
1193 | cpu->reset_fpsid = 0x41023075; | |
1194 | cpu->mvfr0 = 0x10110222; | |
1195 | cpu->mvfr1 = 0x11111111; | |
1196 | cpu->ctr = 0x84448003; | |
1197 | cpu->reset_sctlr = 0x00c50078; | |
1198 | cpu->id_pfr0 = 0x00001131; | |
1199 | cpu->id_pfr1 = 0x00011011; | |
1200 | cpu->id_dfr0 = 0x02010555; | |
1201 | cpu->pmceid0 = 0x00000000; | |
1202 | cpu->pmceid1 = 0x00000000; | |
1203 | cpu->id_afr0 = 0x00000000; | |
1204 | cpu->id_mmfr0 = 0x10101105; | |
1205 | cpu->id_mmfr1 = 0x40000000; | |
1206 | cpu->id_mmfr2 = 0x01240000; | |
1207 | cpu->id_mmfr3 = 0x02102211; | |
1208 | cpu->id_isar0 = 0x01101110; | |
1209 | cpu->id_isar1 = 0x13112111; | |
1210 | cpu->id_isar2 = 0x21232041; | |
1211 | cpu->id_isar3 = 0x11112131; | |
1212 | cpu->id_isar4 = 0x10011142; | |
1213 | cpu->dbgdidr = 0x3515f005; | |
1214 | cpu->clidr = 0x0a200023; | |
1215 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
1216 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
1217 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
1218 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ | |
1219 | } | |
1220 | ||
777dc784 PM |
1221 | static void cortex_a15_initfn(Object *obj) |
1222 | { | |
1223 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1224 | |
1225 | cpu->dtb_compatible = "arm,cortex-a15"; | |
581be094 PM |
1226 | set_feature(&cpu->env, ARM_FEATURE_V7); |
1227 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
581be094 PM |
1228 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
1229 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
1230 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
581be094 | 1231 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
c4804214 | 1232 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
c29f9a0a | 1233 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
de9b05b8 | 1234 | set_feature(&cpu->env, ARM_FEATURE_LPAE); |
c0ccb02d | 1235 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
3541addc | 1236 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; |
b2d06f96 | 1237 | cpu->midr = 0x412fc0f1; |
325b3cef | 1238 | cpu->reset_fpsid = 0x410430f0; |
bd35c355 PM |
1239 | cpu->mvfr0 = 0x10110222; |
1240 | cpu->mvfr1 = 0x11111111; | |
64e1671f | 1241 | cpu->ctr = 0x8444c004; |
0ca7e01c | 1242 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
1243 | cpu->id_pfr0 = 0x00001131; |
1244 | cpu->id_pfr1 = 0x00011011; | |
1245 | cpu->id_dfr0 = 0x02010555; | |
4054bfa9 AF |
1246 | cpu->pmceid0 = 0x0000000; |
1247 | cpu->pmceid1 = 0x00000000; | |
2e4d7e3e PM |
1248 | cpu->id_afr0 = 0x00000000; |
1249 | cpu->id_mmfr0 = 0x10201105; | |
1250 | cpu->id_mmfr1 = 0x20000000; | |
1251 | cpu->id_mmfr2 = 0x01240000; | |
1252 | cpu->id_mmfr3 = 0x02102211; | |
1253 | cpu->id_isar0 = 0x02101110; | |
1254 | cpu->id_isar1 = 0x13112111; | |
1255 | cpu->id_isar2 = 0x21232041; | |
1256 | cpu->id_isar3 = 0x11112131; | |
1257 | cpu->id_isar4 = 0x10011142; | |
48eb3ae6 | 1258 | cpu->dbgdidr = 0x3515f021; |
85df3786 PM |
1259 | cpu->clidr = 0x0a200023; |
1260 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
1261 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
1262 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
34f90529 | 1263 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); |
777dc784 PM |
1264 | } |
1265 | ||
1266 | static void ti925t_initfn(Object *obj) | |
1267 | { | |
1268 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
1269 | set_feature(&cpu->env, ARM_FEATURE_V4T); |
1270 | set_feature(&cpu->env, ARM_FEATURE_OMAPCP); | |
777dc784 | 1271 | cpu->midr = ARM_CPUID_TI925T; |
64e1671f | 1272 | cpu->ctr = 0x5109149; |
0ca7e01c | 1273 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1274 | } |
1275 | ||
1276 | static void sa1100_initfn(Object *obj) | |
1277 | { | |
1278 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1279 | |
1280 | cpu->dtb_compatible = "intel,sa1100"; | |
581be094 | 1281 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 1282 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1283 | cpu->midr = 0x4401A11B; |
0ca7e01c | 1284 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1285 | } |
1286 | ||
1287 | static void sa1110_initfn(Object *obj) | |
1288 | { | |
1289 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 | 1290 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 1291 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1292 | cpu->midr = 0x6901B119; |
0ca7e01c | 1293 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1294 | } |
1295 | ||
1296 | static void pxa250_initfn(Object *obj) | |
1297 | { | |
1298 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1299 | |
1300 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1301 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1302 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1303 | cpu->midr = 0x69052100; |
64e1671f | 1304 | cpu->ctr = 0xd172172; |
0ca7e01c | 1305 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1306 | } |
1307 | ||
1308 | static void pxa255_initfn(Object *obj) | |
1309 | { | |
1310 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1311 | |
1312 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1313 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1314 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1315 | cpu->midr = 0x69052d00; |
64e1671f | 1316 | cpu->ctr = 0xd172172; |
0ca7e01c | 1317 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1318 | } |
1319 | ||
1320 | static void pxa260_initfn(Object *obj) | |
1321 | { | |
1322 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1323 | |
1324 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1325 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1326 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1327 | cpu->midr = 0x69052903; |
64e1671f | 1328 | cpu->ctr = 0xd172172; |
0ca7e01c | 1329 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1330 | } |
1331 | ||
1332 | static void pxa261_initfn(Object *obj) | |
1333 | { | |
1334 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1335 | |
1336 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1337 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1338 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1339 | cpu->midr = 0x69052d05; |
64e1671f | 1340 | cpu->ctr = 0xd172172; |
0ca7e01c | 1341 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1342 | } |
1343 | ||
1344 | static void pxa262_initfn(Object *obj) | |
1345 | { | |
1346 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1347 | |
1348 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1349 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1350 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1351 | cpu->midr = 0x69052d06; |
64e1671f | 1352 | cpu->ctr = 0xd172172; |
0ca7e01c | 1353 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1354 | } |
1355 | ||
1356 | static void pxa270a0_initfn(Object *obj) | |
1357 | { | |
1358 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1359 | |
1360 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1361 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1362 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1363 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1364 | cpu->midr = 0x69054110; |
64e1671f | 1365 | cpu->ctr = 0xd172172; |
0ca7e01c | 1366 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1367 | } |
1368 | ||
1369 | static void pxa270a1_initfn(Object *obj) | |
1370 | { | |
1371 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1372 | |
1373 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1374 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1375 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1376 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1377 | cpu->midr = 0x69054111; |
64e1671f | 1378 | cpu->ctr = 0xd172172; |
0ca7e01c | 1379 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1380 | } |
1381 | ||
1382 | static void pxa270b0_initfn(Object *obj) | |
1383 | { | |
1384 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1385 | |
1386 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1387 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1388 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1389 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1390 | cpu->midr = 0x69054112; |
64e1671f | 1391 | cpu->ctr = 0xd172172; |
0ca7e01c | 1392 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1393 | } |
1394 | ||
1395 | static void pxa270b1_initfn(Object *obj) | |
1396 | { | |
1397 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1398 | |
1399 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1400 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1401 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1402 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1403 | cpu->midr = 0x69054113; |
64e1671f | 1404 | cpu->ctr = 0xd172172; |
0ca7e01c | 1405 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1406 | } |
1407 | ||
1408 | static void pxa270c0_initfn(Object *obj) | |
1409 | { | |
1410 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1411 | |
1412 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1413 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1414 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1415 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1416 | cpu->midr = 0x69054114; |
64e1671f | 1417 | cpu->ctr = 0xd172172; |
0ca7e01c | 1418 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1419 | } |
1420 | ||
1421 | static void pxa270c5_initfn(Object *obj) | |
1422 | { | |
1423 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1424 | |
1425 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1426 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1427 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1428 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1429 | cpu->midr = 0x69054117; |
64e1671f | 1430 | cpu->ctr = 0xd172172; |
0ca7e01c | 1431 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1432 | } |
1433 | ||
f5f6d38b | 1434 | #ifdef CONFIG_USER_ONLY |
777dc784 PM |
1435 | static void arm_any_initfn(Object *obj) |
1436 | { | |
1437 | ARMCPU *cpu = ARM_CPU(obj); | |
81e69fb0 | 1438 | set_feature(&cpu->env, ARM_FEATURE_V8); |
581be094 | 1439 | set_feature(&cpu->env, ARM_FEATURE_VFP4); |
581be094 PM |
1440 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
1441 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
25f748e3 PM |
1442 | set_feature(&cpu->env, ARM_FEATURE_V8_AES); |
1443 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); | |
1444 | set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); | |
1445 | set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | |
eb0ecd5a | 1446 | set_feature(&cpu->env, ARM_FEATURE_CRC); |
b2d06f96 | 1447 | cpu->midr = 0xffffffff; |
777dc784 | 1448 | } |
f5f6d38b | 1449 | #endif |
777dc784 | 1450 | |
15ee776b PM |
1451 | #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ |
1452 | ||
777dc784 PM |
1453 | typedef struct ARMCPUInfo { |
1454 | const char *name; | |
1455 | void (*initfn)(Object *obj); | |
e6f010cc | 1456 | void (*class_init)(ObjectClass *oc, void *data); |
777dc784 PM |
1457 | } ARMCPUInfo; |
1458 | ||
1459 | static const ARMCPUInfo arm_cpus[] = { | |
15ee776b | 1460 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) |
777dc784 PM |
1461 | { .name = "arm926", .initfn = arm926_initfn }, |
1462 | { .name = "arm946", .initfn = arm946_initfn }, | |
1463 | { .name = "arm1026", .initfn = arm1026_initfn }, | |
1464 | /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an | |
1465 | * older core than plain "arm1136". In particular this does not | |
1466 | * have the v6K features. | |
1467 | */ | |
1468 | { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, | |
1469 | { .name = "arm1136", .initfn = arm1136_initfn }, | |
1470 | { .name = "arm1176", .initfn = arm1176_initfn }, | |
1471 | { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, | |
e6f010cc AF |
1472 | { .name = "cortex-m3", .initfn = cortex_m3_initfn, |
1473 | .class_init = arm_v7m_class_init }, | |
ba890a9b AR |
1474 | { .name = "cortex-m4", .initfn = cortex_m4_initfn, |
1475 | .class_init = arm_v7m_class_init }, | |
d6a6b13e | 1476 | { .name = "cortex-r5", .initfn = cortex_r5_initfn }, |
dcf578ed | 1477 | { .name = "cortex-a7", .initfn = cortex_a7_initfn }, |
777dc784 PM |
1478 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, |
1479 | { .name = "cortex-a9", .initfn = cortex_a9_initfn }, | |
1480 | { .name = "cortex-a15", .initfn = cortex_a15_initfn }, | |
1481 | { .name = "ti925t", .initfn = ti925t_initfn }, | |
1482 | { .name = "sa1100", .initfn = sa1100_initfn }, | |
1483 | { .name = "sa1110", .initfn = sa1110_initfn }, | |
1484 | { .name = "pxa250", .initfn = pxa250_initfn }, | |
1485 | { .name = "pxa255", .initfn = pxa255_initfn }, | |
1486 | { .name = "pxa260", .initfn = pxa260_initfn }, | |
1487 | { .name = "pxa261", .initfn = pxa261_initfn }, | |
1488 | { .name = "pxa262", .initfn = pxa262_initfn }, | |
1489 | /* "pxa270" is an alias for "pxa270-a0" */ | |
1490 | { .name = "pxa270", .initfn = pxa270a0_initfn }, | |
1491 | { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, | |
1492 | { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, | |
1493 | { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, | |
1494 | { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, | |
1495 | { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, | |
1496 | { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, | |
f5f6d38b | 1497 | #ifdef CONFIG_USER_ONLY |
777dc784 | 1498 | { .name = "any", .initfn = arm_any_initfn }, |
f5f6d38b | 1499 | #endif |
15ee776b | 1500 | #endif |
83e6813a | 1501 | { .name = NULL } |
777dc784 PM |
1502 | }; |
1503 | ||
5de16430 PM |
1504 | static Property arm_cpu_properties[] = { |
1505 | DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), | |
98128601 | 1506 | DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), |
51a9b04b | 1507 | DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), |
ce5b1bbf LV |
1508 | DEFINE_PROP_UINT64("mp-affinity", ARMCPU, |
1509 | mp_affinity, ARM64_AFFINITY_INVALID), | |
5de16430 PM |
1510 | DEFINE_PROP_END_OF_LIST() |
1511 | }; | |
1512 | ||
8c6084bf PM |
1513 | #ifdef CONFIG_USER_ONLY |
1514 | static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, | |
1515 | int mmu_idx) | |
1516 | { | |
1517 | ARMCPU *cpu = ARM_CPU(cs); | |
1518 | CPUARMState *env = &cpu->env; | |
1519 | ||
1520 | env->exception.vaddress = address; | |
1521 | if (rw == 2) { | |
1522 | cs->exception_index = EXCP_PREFETCH_ABORT; | |
1523 | } else { | |
1524 | cs->exception_index = EXCP_DATA_ABORT; | |
1525 | } | |
1526 | return 1; | |
1527 | } | |
1528 | #endif | |
1529 | ||
b3820e6c DH |
1530 | static gchar *arm_gdb_arch_name(CPUState *cs) |
1531 | { | |
1532 | ARMCPU *cpu = ARM_CPU(cs); | |
1533 | CPUARMState *env = &cpu->env; | |
1534 | ||
1535 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
1536 | return g_strdup("iwmmxt"); | |
1537 | } | |
1538 | return g_strdup("arm"); | |
1539 | } | |
1540 | ||
dec9c2d4 AF |
1541 | static void arm_cpu_class_init(ObjectClass *oc, void *data) |
1542 | { | |
1543 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
1544 | CPUClass *cc = CPU_CLASS(acc); | |
14969266 AF |
1545 | DeviceClass *dc = DEVICE_CLASS(oc); |
1546 | ||
1547 | acc->parent_realize = dc->realize; | |
1548 | dc->realize = arm_cpu_realizefn; | |
5de16430 | 1549 | dc->props = arm_cpu_properties; |
dec9c2d4 AF |
1550 | |
1551 | acc->parent_reset = cc->reset; | |
1552 | cc->reset = arm_cpu_reset; | |
5900d6b2 AF |
1553 | |
1554 | cc->class_by_name = arm_cpu_class_by_name; | |
8c2e1b00 | 1555 | cc->has_work = arm_cpu_has_work; |
e8925712 | 1556 | cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; |
878096ee | 1557 | cc->dump_state = arm_cpu_dump_state; |
f45748f1 | 1558 | cc->set_pc = arm_cpu_set_pc; |
5b50e790 AF |
1559 | cc->gdb_read_register = arm_cpu_gdb_read_register; |
1560 | cc->gdb_write_register = arm_cpu_gdb_write_register; | |
7510454e AF |
1561 | #ifdef CONFIG_USER_ONLY |
1562 | cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; | |
1563 | #else | |
0adf7d3c | 1564 | cc->do_interrupt = arm_cpu_do_interrupt; |
30901475 | 1565 | cc->do_unaligned_access = arm_cpu_do_unaligned_access; |
0faea0c7 | 1566 | cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; |
017518c1 | 1567 | cc->asidx_from_attrs = arm_asidx_from_attrs; |
00b941e5 | 1568 | cc->vmsd = &vmstate_arm_cpu; |
ed50ff78 | 1569 | cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; |
da2b9140 AJ |
1570 | cc->write_elf64_note = arm_cpu_write_elf64_note; |
1571 | cc->write_elf32_note = arm_cpu_write_elf32_note; | |
00b941e5 | 1572 | #endif |
a0e372f0 | 1573 | cc->gdb_num_core_regs = 26; |
5b24c641 | 1574 | cc->gdb_core_xml_file = "arm-core.xml"; |
b3820e6c | 1575 | cc->gdb_arch_name = arm_gdb_arch_name; |
2472b6c0 | 1576 | cc->gdb_stop_before_watchpoint = true; |
3ff6fc91 | 1577 | cc->debug_excp_handler = arm_debug_excp_handler; |
3826121d | 1578 | cc->debug_check_watchpoint = arm_debug_check_watchpoint; |
48440620 PC |
1579 | |
1580 | cc->disas_set_info = arm_disas_set_info; | |
dec9c2d4 AF |
1581 | } |
1582 | ||
777dc784 PM |
1583 | static void cpu_register(const ARMCPUInfo *info) |
1584 | { | |
1585 | TypeInfo type_info = { | |
777dc784 PM |
1586 | .parent = TYPE_ARM_CPU, |
1587 | .instance_size = sizeof(ARMCPU), | |
1588 | .instance_init = info->initfn, | |
1589 | .class_size = sizeof(ARMCPUClass), | |
e6f010cc | 1590 | .class_init = info->class_init, |
777dc784 PM |
1591 | }; |
1592 | ||
51492fd1 | 1593 | type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); |
918fd083 | 1594 | type_register(&type_info); |
51492fd1 | 1595 | g_free((void *)type_info.name); |
777dc784 PM |
1596 | } |
1597 | ||
dec9c2d4 AF |
1598 | static const TypeInfo arm_cpu_type_info = { |
1599 | .name = TYPE_ARM_CPU, | |
1600 | .parent = TYPE_CPU, | |
1601 | .instance_size = sizeof(ARMCPU), | |
777dc784 | 1602 | .instance_init = arm_cpu_initfn, |
07a5b0d2 | 1603 | .instance_post_init = arm_cpu_post_init, |
4b6a83fb | 1604 | .instance_finalize = arm_cpu_finalizefn, |
777dc784 | 1605 | .abstract = true, |
dec9c2d4 AF |
1606 | .class_size = sizeof(ARMCPUClass), |
1607 | .class_init = arm_cpu_class_init, | |
1608 | }; | |
1609 | ||
1610 | static void arm_cpu_register_types(void) | |
1611 | { | |
83e6813a | 1612 | const ARMCPUInfo *info = arm_cpus; |
777dc784 | 1613 | |
dec9c2d4 | 1614 | type_register_static(&arm_cpu_type_info); |
83e6813a PM |
1615 | |
1616 | while (info->name) { | |
1617 | cpu_register(info); | |
1618 | info++; | |
777dc784 | 1619 | } |
dec9c2d4 AF |
1620 | } |
1621 | ||
1622 | type_init(arm_cpu_register_types) |