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dec9c2d4 AF |
1 | /* |
2 | * QEMU ARM CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
74c21bd0 | 21 | #include "qemu/osdep.h" |
86480615 | 22 | #include "qemu/qemu-print.h" |
b8012ecf | 23 | #include "qemu/timer.h" |
8cc2246c | 24 | #include "qemu/log.h" |
ec5f7ca8 | 25 | #include "exec/page-vary.h" |
181962fd | 26 | #include "target/arm/idau.h" |
0b8fa32f | 27 | #include "qemu/module.h" |
da34e65c | 28 | #include "qapi/error.h" |
778c3a06 | 29 | #include "cpu.h" |
78271684 CF |
30 | #ifdef CONFIG_TCG |
31 | #include "hw/core/tcg-cpu-ops.h" | |
32 | #endif /* CONFIG_TCG */ | |
ccd38087 | 33 | #include "internals.h" |
63c91552 | 34 | #include "exec/exec-all.h" |
5de16430 | 35 | #include "hw/qdev-properties.h" |
3c30dd5a PM |
36 | #if !defined(CONFIG_USER_ONLY) |
37 | #include "hw/loader.h" | |
cc7d44c2 | 38 | #include "hw/boards.h" |
165876f2 | 39 | #ifdef CONFIG_TCG |
8f4e07c9 | 40 | #include "hw/intc/armv7m_nvic.h" |
165876f2 PMD |
41 | #endif /* CONFIG_TCG */ |
42 | #endif /* !CONFIG_USER_ONLY */ | |
14a48c1d | 43 | #include "sysemu/tcg.h" |
045e5064 | 44 | #include "sysemu/qtest.h" |
b3946626 | 45 | #include "sysemu/hw_accel.h" |
50a2c6e5 | 46 | #include "kvm_arm.h" |
110f6c70 | 47 | #include "disas/capstone.h" |
24f91e81 | 48 | #include "fpu/softfloat.h" |
cf7c6d10 | 49 | #include "cpregs.h" |
dec9c2d4 | 50 | |
f45748f1 AF |
51 | static void arm_cpu_set_pc(CPUState *cs, vaddr value) |
52 | { | |
53 | ARMCPU *cpu = ARM_CPU(cs); | |
42f6ed91 JS |
54 | CPUARMState *env = &cpu->env; |
55 | ||
56 | if (is_a64(env)) { | |
57 | env->pc = value; | |
063bbd80 | 58 | env->thumb = false; |
42f6ed91 JS |
59 | } else { |
60 | env->regs[15] = value & ~1; | |
61 | env->thumb = value & 1; | |
62 | } | |
63 | } | |
f45748f1 | 64 | |
e4fdf9df RH |
65 | static vaddr arm_cpu_get_pc(CPUState *cs) |
66 | { | |
67 | ARMCPU *cpu = ARM_CPU(cs); | |
68 | CPUARMState *env = &cpu->env; | |
69 | ||
70 | if (is_a64(env)) { | |
71 | return env->pc; | |
72 | } else { | |
73 | return env->regs[15]; | |
74 | } | |
75 | } | |
76 | ||
ec62595b | 77 | #ifdef CONFIG_TCG |
78271684 CF |
78 | void arm_cpu_synchronize_from_tb(CPUState *cs, |
79 | const TranslationBlock *tb) | |
42f6ed91 | 80 | { |
03a648c4 AJ |
81 | /* The program counter is always up to date with CF_PCREL. */ |
82 | if (!(tb_cflags(tb) & CF_PCREL)) { | |
abb80995 RH |
83 | CPUARMState *env = cs->env_ptr; |
84 | /* | |
85 | * It's OK to look at env for the current mode here, because it's | |
86 | * never possible for an AArch64 TB to chain to an AArch32 TB. | |
87 | */ | |
88 | if (is_a64(env)) { | |
f51a1dd7 | 89 | env->pc = tb->pc; |
abb80995 | 90 | } else { |
f51a1dd7 | 91 | env->regs[15] = tb->pc; |
abb80995 | 92 | } |
42f6ed91 | 93 | } |
f45748f1 | 94 | } |
56c6c98d | 95 | |
475e56b6 EE |
96 | void arm_restore_state_to_opc(CPUState *cs, |
97 | const TranslationBlock *tb, | |
98 | const uint64_t *data) | |
56c6c98d RH |
99 | { |
100 | CPUARMState *env = cs->env_ptr; | |
101 | ||
102 | if (is_a64(env)) { | |
03a648c4 | 103 | if (tb_cflags(tb) & CF_PCREL) { |
56c6c98d RH |
104 | env->pc = (env->pc & TARGET_PAGE_MASK) | data[0]; |
105 | } else { | |
106 | env->pc = data[0]; | |
107 | } | |
108 | env->condexec_bits = 0; | |
109 | env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; | |
110 | } else { | |
03a648c4 | 111 | if (tb_cflags(tb) & CF_PCREL) { |
56c6c98d RH |
112 | env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0]; |
113 | } else { | |
114 | env->regs[15] = data[0]; | |
115 | } | |
116 | env->condexec_bits = data[1]; | |
117 | env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT; | |
118 | } | |
119 | } | |
ec62595b | 120 | #endif /* CONFIG_TCG */ |
f45748f1 | 121 | |
8c2e1b00 AF |
122 | static bool arm_cpu_has_work(CPUState *cs) |
123 | { | |
543486db RH |
124 | ARMCPU *cpu = ARM_CPU(cs); |
125 | ||
062ba099 | 126 | return (cpu->power_state != PSCI_OFF) |
543486db | 127 | && cs->interrupt_request & |
136e67e9 | 128 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD |
3c29632f | 129 | | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR |
136e67e9 | 130 | | CPU_INTERRUPT_EXITTB); |
8c2e1b00 AF |
131 | } |
132 | ||
b5c53d1b AL |
133 | void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
134 | void *opaque) | |
135 | { | |
136 | ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); | |
137 | ||
138 | entry->hook = hook; | |
139 | entry->opaque = opaque; | |
140 | ||
141 | QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); | |
142 | } | |
143 | ||
08267487 | 144 | void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
bd7d00fc PM |
145 | void *opaque) |
146 | { | |
08267487 AL |
147 | ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); |
148 | ||
149 | entry->hook = hook; | |
150 | entry->opaque = opaque; | |
151 | ||
152 | QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); | |
bd7d00fc PM |
153 | } |
154 | ||
4b6a83fb PM |
155 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
156 | { | |
157 | /* Reset a single ARMCPRegInfo register */ | |
158 | ARMCPRegInfo *ri = value; | |
159 | ARMCPU *cpu = opaque; | |
160 | ||
87c3f0f2 | 161 | if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { |
4b6a83fb PM |
162 | return; |
163 | } | |
164 | ||
165 | if (ri->resetfn) { | |
166 | ri->resetfn(&cpu->env, ri); | |
167 | return; | |
168 | } | |
169 | ||
170 | /* A zero offset is never possible as it would be regs[0] | |
171 | * so we use it to indicate that reset is being handled elsewhere. | |
172 | * This is basically only used for fields in non-core coprocessors | |
173 | * (like the pxa2xx ones). | |
174 | */ | |
175 | if (!ri->fieldoffset) { | |
176 | return; | |
177 | } | |
178 | ||
67ed771d | 179 | if (cpreg_field_is_64bit(ri)) { |
4b6a83fb PM |
180 | CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; |
181 | } else { | |
182 | CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; | |
183 | } | |
184 | } | |
185 | ||
49a66191 PM |
186 | static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) |
187 | { | |
188 | /* Purely an assertion check: we've already done reset once, | |
189 | * so now check that running the reset for the cpreg doesn't | |
190 | * change its value. This traps bugs where two different cpregs | |
191 | * both try to reset the same state field but to different values. | |
192 | */ | |
193 | ARMCPRegInfo *ri = value; | |
194 | ARMCPU *cpu = opaque; | |
195 | uint64_t oldvalue, newvalue; | |
196 | ||
87c3f0f2 | 197 | if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { |
49a66191 PM |
198 | return; |
199 | } | |
200 | ||
201 | oldvalue = read_raw_cp_reg(&cpu->env, ri); | |
202 | cp_reg_reset(key, value, opaque); | |
203 | newvalue = read_raw_cp_reg(&cpu->env, ri); | |
204 | assert(oldvalue == newvalue); | |
205 | } | |
206 | ||
9130cade | 207 | static void arm_cpu_reset_hold(Object *obj) |
dec9c2d4 | 208 | { |
9130cade | 209 | CPUState *s = CPU(obj); |
dec9c2d4 AF |
210 | ARMCPU *cpu = ARM_CPU(s); |
211 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); | |
3c30dd5a | 212 | CPUARMState *env = &cpu->env; |
3c30dd5a | 213 | |
9130cade PM |
214 | if (acc->parent_phases.hold) { |
215 | acc->parent_phases.hold(obj); | |
216 | } | |
dec9c2d4 | 217 | |
1f5c00cf AB |
218 | memset(env, 0, offsetof(CPUARMState, end_reset_fields)); |
219 | ||
4b6a83fb | 220 | g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
49a66191 PM |
221 | g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); |
222 | ||
3c30dd5a | 223 | env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
47576b94 RH |
224 | env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; |
225 | env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; | |
226 | env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; | |
3c30dd5a | 227 | |
c1b70158 | 228 | cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; |
543486db | 229 | |
3c30dd5a PM |
230 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { |
231 | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; | |
232 | } | |
233 | ||
3926cc84 AG |
234 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
235 | /* 64 bit CPUs always start in 64 bit mode */ | |
53221552 | 236 | env->aarch64 = true; |
d356312f PM |
237 | #if defined(CONFIG_USER_ONLY) |
238 | env->pstate = PSTATE_MODE_EL0t; | |
14e5f106 | 239 | /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ |
137feaa9 | 240 | env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; |
276c6e81 RH |
241 | /* Enable all PAC keys. */ |
242 | env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | | |
243 | SCTLR_EnDA | SCTLR_EnDB); | |
cda86e2b RH |
244 | /* Trap on btype=3 for PACIxSP. */ |
245 | env->cp15.sctlr_el[1] |= SCTLR_BT0; | |
8c6afa6a | 246 | /* and to the FP/Neon instructions */ |
fab8ad39 RH |
247 | env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, |
248 | CPACR_EL1, FPEN, 3); | |
46303535 | 249 | /* and to the SVE instructions, with default vector length */ |
7b6a2198 | 250 | if (cpu_isar_feature(aa64_sve, cpu)) { |
46303535 RH |
251 | env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, |
252 | CPACR_EL1, ZEN, 3); | |
87252bde | 253 | env->vfp.zcr_el[1] = cpu->sve_default_vq - 1; |
7b6a2198 | 254 | } |
78011586 RH |
255 | /* and for SME instructions, with default vector length, and TPIDR2 */ |
256 | if (cpu_isar_feature(aa64_sme, cpu)) { | |
257 | env->cp15.sctlr_el[1] |= SCTLR_EnTP2; | |
258 | env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, | |
259 | CPACR_EL1, SMEN, 3); | |
260 | env->vfp.smcr_el[1] = cpu->sme_default_vq - 1; | |
261 | if (cpu_isar_feature(aa64_sme_fa64, cpu)) { | |
262 | env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1], | |
263 | SMCR, FA64, 1); | |
264 | } | |
265 | } | |
f6a148fe | 266 | /* |
691f1ffd | 267 | * Enable 48-bit address space (TODO: take reserved_va into account). |
16c84978 RH |
268 | * Enable TBI0 but not TBI1. |
269 | * Note that this must match useronly_clean_ptr. | |
f6a148fe | 270 | */ |
cb4a0a34 | 271 | env->cp15.tcr_el[1] = 5 | (1ULL << 37); |
e3232864 RH |
272 | |
273 | /* Enable MTE */ | |
274 | if (cpu_isar_feature(aa64_mte, cpu)) { | |
275 | /* Enable tag access, but leave TCF0 as No Effect (0). */ | |
276 | env->cp15.sctlr_el[1] |= SCTLR_ATA0; | |
277 | /* | |
278 | * Exclude all tags, so that tag 0 is always used. | |
279 | * This corresponds to Linux current->thread.gcr_incl = 0. | |
280 | * | |
281 | * Set RRND, so that helper_irg() will generate a seed later. | |
282 | * Here in cpu_reset(), the crypto subsystem has not yet been | |
283 | * initialized. | |
284 | */ | |
285 | env->cp15.gcr_el1 = 0x1ffff; | |
286 | } | |
7cb1e618 RH |
287 | /* |
288 | * Disable access to SCXTNUM_EL0 from CSV2_1p2. | |
289 | * This is not yet exposed from the Linux kernel in any way. | |
290 | */ | |
291 | env->cp15.sctlr_el[1] |= SCTLR_TSCXT; | |
d356312f | 292 | #else |
5097227c GB |
293 | /* Reset into the highest available EL */ |
294 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
295 | env->pstate = PSTATE_MODE_EL3h; | |
296 | } else if (arm_feature(env, ARM_FEATURE_EL2)) { | |
297 | env->pstate = PSTATE_MODE_EL2h; | |
298 | } else { | |
299 | env->pstate = PSTATE_MODE_EL1h; | |
300 | } | |
4a7319b7 EI |
301 | |
302 | /* Sample rvbar at reset. */ | |
303 | env->cp15.rvbar = cpu->rvbar_prop; | |
304 | env->pc = env->cp15.rvbar; | |
8c6afa6a PM |
305 | #endif |
306 | } else { | |
307 | #if defined(CONFIG_USER_ONLY) | |
308 | /* Userspace expects access to cp10 and cp11 for FP/Neon */ | |
fab8ad39 RH |
309 | env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, |
310 | CPACR, CP10, 3); | |
311 | env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, | |
312 | CPACR, CP11, 3); | |
d356312f | 313 | #endif |
910e4f24 TR |
314 | if (arm_feature(env, ARM_FEATURE_V8)) { |
315 | env->cp15.rvbar = cpu->rvbar_prop; | |
316 | env->regs[15] = cpu->rvbar_prop; | |
317 | } | |
3926cc84 AG |
318 | } |
319 | ||
3c30dd5a PM |
320 | #if defined(CONFIG_USER_ONLY) |
321 | env->uncached_cpsr = ARM_CPU_MODE_USR; | |
322 | /* For user mode we must enable access to coprocessors */ | |
323 | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; | |
324 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
325 | env->cp15.c15_cpar = 3; | |
326 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
327 | env->cp15.c15_cpar = 1; | |
328 | } | |
329 | #else | |
060a65df PM |
330 | |
331 | /* | |
332 | * If the highest available EL is EL2, AArch32 will start in Hyp | |
333 | * mode; otherwise it starts in SVC. Note that if we start in | |
334 | * AArch64 then these values in the uncached_cpsr will be ignored. | |
335 | */ | |
336 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
337 | !arm_feature(env, ARM_FEATURE_EL3)) { | |
338 | env->uncached_cpsr = ARM_CPU_MODE_HYP; | |
339 | } else { | |
340 | env->uncached_cpsr = ARM_CPU_MODE_SVC; | |
341 | } | |
4cc35614 | 342 | env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; |
1426f244 PM |
343 | |
344 | /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently | |
345 | * executing as AArch32 then check if highvecs are enabled and | |
346 | * adjust the PC accordingly. | |
347 | */ | |
348 | if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { | |
349 | env->regs[15] = 0xFFFF0000; | |
350 | } | |
351 | ||
352 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; | |
b62ceeaf | 353 | #endif |
dc7abe4d | 354 | |
531c60a9 | 355 | if (arm_feature(env, ARM_FEATURE_M)) { |
b62ceeaf | 356 | #ifndef CONFIG_USER_ONLY |
6e3cf5df MG |
357 | uint32_t initial_msp; /* Loaded from 0x0 */ |
358 | uint32_t initial_pc; /* Loaded from 0x4 */ | |
3c30dd5a | 359 | uint8_t *rom; |
38e2a77c | 360 | uint32_t vecbase; |
b62ceeaf | 361 | #endif |
6e3cf5df | 362 | |
8128c8e8 PM |
363 | if (cpu_isar_feature(aa32_lob, cpu)) { |
364 | /* | |
365 | * LTPSIZE is constant 4 if MVE not implemented, and resets | |
366 | * to an UNKNOWN value if MVE is implemented. We choose to | |
367 | * always reset to 4. | |
368 | */ | |
369 | env->v7m.ltpsize = 4; | |
99c7834f PM |
370 | /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ |
371 | env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; | |
372 | env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; | |
8128c8e8 PM |
373 | } |
374 | ||
1e577cc7 PM |
375 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
376 | env->v7m.secure = true; | |
3b2e9344 PM |
377 | } else { |
378 | /* This bit resets to 0 if security is supported, but 1 if | |
379 | * it is not. The bit is not present in v7M, but we set it | |
380 | * here so we can avoid having to make checks on it conditional | |
381 | * on ARM_FEATURE_V8 (we don't let the guest see the bit). | |
382 | */ | |
383 | env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; | |
02ac2f7f PM |
384 | /* |
385 | * Set NSACR to indicate "NS access permitted to everything"; | |
386 | * this avoids having to have all the tests of it being | |
387 | * conditional on ARM_FEATURE_M_SECURITY. Note also that from | |
388 | * v8.1M the guest-visible value of NSACR in a CPU without the | |
389 | * Security Extension is 0xcff. | |
390 | */ | |
391 | env->v7m.nsacr = 0xcff; | |
1e577cc7 PM |
392 | } |
393 | ||
9d40cd8a | 394 | /* In v7M the reset value of this bit is IMPDEF, but ARM recommends |
2c4da50d | 395 | * that it resets to 1, so QEMU always does that rather than making |
9d40cd8a | 396 | * it dependent on CPU model. In v8M it is RES1. |
2c4da50d | 397 | */ |
9d40cd8a PM |
398 | env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; |
399 | env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; | |
400 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
401 | /* in v8M the NONBASETHRDENA bit [0] is RES1 */ | |
402 | env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; | |
403 | env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; | |
404 | } | |
22ab3460 JS |
405 | if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { |
406 | env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; | |
407 | env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; | |
408 | } | |
2c4da50d | 409 | |
7fbc6a40 | 410 | if (cpu_isar_feature(aa32_vfp_simd, cpu)) { |
d33abe82 PM |
411 | env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; |
412 | env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | | |
413 | R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; | |
414 | } | |
b62ceeaf PM |
415 | |
416 | #ifndef CONFIG_USER_ONLY | |
056f43df PM |
417 | /* Unlike A/R profile, M profile defines the reset LR value */ |
418 | env->regs[14] = 0xffffffff; | |
419 | ||
38e2a77c | 420 | env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; |
7cda2149 | 421 | env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; |
38e2a77c PM |
422 | |
423 | /* Load the initial SP and PC from offset 0 and 4 in the vector table */ | |
424 | vecbase = env->v7m.vecbase[env->v7m.secure]; | |
75ce72b7 | 425 | rom = rom_ptr_for_as(s->as, vecbase, 8); |
3c30dd5a | 426 | if (rom) { |
6e3cf5df MG |
427 | /* Address zero is covered by ROM which hasn't yet been |
428 | * copied into physical memory. | |
429 | */ | |
430 | initial_msp = ldl_p(rom); | |
431 | initial_pc = ldl_p(rom + 4); | |
432 | } else { | |
433 | /* Address zero not covered by a ROM blob, or the ROM blob | |
434 | * is in non-modifiable memory and this is a second reset after | |
435 | * it got copied into memory. In the latter case, rom_ptr | |
436 | * will return a NULL pointer and we should use ldl_phys instead. | |
437 | */ | |
38e2a77c PM |
438 | initial_msp = ldl_phys(s->as, vecbase); |
439 | initial_pc = ldl_phys(s->as, vecbase + 4); | |
3c30dd5a | 440 | } |
6e3cf5df | 441 | |
8cc2246c PM |
442 | qemu_log_mask(CPU_LOG_INT, |
443 | "Loaded reset SP 0x%x PC 0x%x from vector table\n", | |
444 | initial_msp, initial_pc); | |
445 | ||
6e3cf5df MG |
446 | env->regs[13] = initial_msp & 0xFFFFFFFC; |
447 | env->regs[15] = initial_pc & ~1; | |
448 | env->thumb = initial_pc & 1; | |
b62ceeaf PM |
449 | #else |
450 | /* | |
451 | * For user mode we run non-secure and with access to the FPU. | |
452 | * The FPU context is active (ie does not need further setup) | |
453 | * and is owned by non-secure. | |
454 | */ | |
455 | env->v7m.secure = false; | |
456 | env->v7m.nsacr = 0xcff; | |
457 | env->v7m.cpacr[M_REG_NS] = 0xf0ffff; | |
458 | env->v7m.fpccr[M_REG_S] &= | |
459 | ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); | |
460 | env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; | |
461 | #endif | |
3c30dd5a | 462 | } |
387f9806 | 463 | |
dc3c4c14 PM |
464 | /* M profile requires that reset clears the exclusive monitor; |
465 | * A profile does not, but clearing it makes more sense than having it | |
466 | * set with an exclusive access on address zero. | |
467 | */ | |
468 | arm_clear_exclusive(env); | |
469 | ||
0e1a46bb | 470 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
69ceea64 | 471 | if (cpu->pmsav7_dregion > 0) { |
0e1a46bb | 472 | if (arm_feature(env, ARM_FEATURE_V8)) { |
62c58ee0 PM |
473 | memset(env->pmsav8.rbar[M_REG_NS], 0, |
474 | sizeof(*env->pmsav8.rbar[M_REG_NS]) | |
475 | * cpu->pmsav7_dregion); | |
476 | memset(env->pmsav8.rlar[M_REG_NS], 0, | |
477 | sizeof(*env->pmsav8.rlar[M_REG_NS]) | |
478 | * cpu->pmsav7_dregion); | |
479 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
480 | memset(env->pmsav8.rbar[M_REG_S], 0, | |
481 | sizeof(*env->pmsav8.rbar[M_REG_S]) | |
482 | * cpu->pmsav7_dregion); | |
483 | memset(env->pmsav8.rlar[M_REG_S], 0, | |
484 | sizeof(*env->pmsav8.rlar[M_REG_S]) | |
485 | * cpu->pmsav7_dregion); | |
486 | } | |
0e1a46bb PM |
487 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
488 | memset(env->pmsav7.drbar, 0, | |
489 | sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); | |
490 | memset(env->pmsav7.drsr, 0, | |
491 | sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); | |
492 | memset(env->pmsav7.dracr, 0, | |
493 | sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); | |
494 | } | |
69ceea64 | 495 | } |
761c4642 TR |
496 | |
497 | if (cpu->pmsav8r_hdregion > 0) { | |
498 | memset(env->pmsav8.hprbar, 0, | |
499 | sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion); | |
500 | memset(env->pmsav8.hprlar, 0, | |
501 | sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion); | |
502 | } | |
503 | ||
1bc04a88 PM |
504 | env->pmsav7.rnr[M_REG_NS] = 0; |
505 | env->pmsav7.rnr[M_REG_S] = 0; | |
4125e6fe PM |
506 | env->pmsav8.mair0[M_REG_NS] = 0; |
507 | env->pmsav8.mair0[M_REG_S] = 0; | |
508 | env->pmsav8.mair1[M_REG_NS] = 0; | |
509 | env->pmsav8.mair1[M_REG_S] = 0; | |
69ceea64 PM |
510 | } |
511 | ||
9901c576 PM |
512 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
513 | if (cpu->sau_sregion > 0) { | |
514 | memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); | |
515 | memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); | |
516 | } | |
517 | env->sau.rnr = 0; | |
518 | /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what | |
519 | * the Cortex-M33 does. | |
520 | */ | |
521 | env->sau.ctrl = 0; | |
522 | } | |
523 | ||
3c30dd5a PM |
524 | set_flush_to_zero(1, &env->vfp.standard_fp_status); |
525 | set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); | |
526 | set_default_nan_mode(1, &env->vfp.standard_fp_status); | |
aaae563b | 527 | set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); |
3c30dd5a PM |
528 | set_float_detect_tininess(float_tininess_before_rounding, |
529 | &env->vfp.fp_status); | |
530 | set_float_detect_tininess(float_tininess_before_rounding, | |
531 | &env->vfp.standard_fp_status); | |
bcc531f0 PM |
532 | set_float_detect_tininess(float_tininess_before_rounding, |
533 | &env->vfp.fp_status_f16); | |
aaae563b PM |
534 | set_float_detect_tininess(float_tininess_before_rounding, |
535 | &env->vfp.standard_fp_status_f16); | |
50a2c6e5 PB |
536 | #ifndef CONFIG_USER_ONLY |
537 | if (kvm_enabled()) { | |
538 | kvm_arm_reset_vcpu(cpu); | |
539 | } | |
540 | #endif | |
9ee98ce8 | 541 | |
fa05d1ab FR |
542 | if (tcg_enabled()) { |
543 | hw_breakpoint_update_all(cpu); | |
544 | hw_watchpoint_update_all(cpu); | |
2b77ad4d FR |
545 | |
546 | arm_rebuild_hflags(env); | |
fa05d1ab | 547 | } |
dec9c2d4 AF |
548 | } |
549 | ||
9e406eea | 550 | #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) |
083afd18 | 551 | |
310cedf3 | 552 | static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, |
be879556 RH |
553 | unsigned int target_el, |
554 | unsigned int cur_el, bool secure, | |
555 | uint64_t hcr_el2) | |
310cedf3 RH |
556 | { |
557 | CPUARMState *env = cs->env_ptr; | |
310cedf3 | 558 | bool pstate_unmasked; |
16e07f78 | 559 | bool unmasked = false; |
310cedf3 RH |
560 | |
561 | /* | |
562 | * Don't take exceptions if they target a lower EL. | |
563 | * This check should catch any exceptions that would not be taken | |
564 | * but left pending. | |
565 | */ | |
566 | if (cur_el > target_el) { | |
567 | return false; | |
568 | } | |
569 | ||
310cedf3 RH |
570 | switch (excp_idx) { |
571 | case EXCP_FIQ: | |
572 | pstate_unmasked = !(env->daif & PSTATE_F); | |
573 | break; | |
574 | ||
575 | case EXCP_IRQ: | |
576 | pstate_unmasked = !(env->daif & PSTATE_I); | |
577 | break; | |
578 | ||
579 | case EXCP_VFIQ: | |
cc974d5c RDC |
580 | if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { |
581 | /* VFIQs are only taken when hypervized. */ | |
310cedf3 RH |
582 | return false; |
583 | } | |
584 | return !(env->daif & PSTATE_F); | |
585 | case EXCP_VIRQ: | |
cc974d5c RDC |
586 | if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { |
587 | /* VIRQs are only taken when hypervized. */ | |
310cedf3 RH |
588 | return false; |
589 | } | |
590 | return !(env->daif & PSTATE_I); | |
3c29632f RH |
591 | case EXCP_VSERR: |
592 | if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { | |
593 | /* VIRQs are only taken when hypervized. */ | |
594 | return false; | |
595 | } | |
596 | return !(env->daif & PSTATE_A); | |
310cedf3 RH |
597 | default: |
598 | g_assert_not_reached(); | |
599 | } | |
600 | ||
601 | /* | |
602 | * Use the target EL, current execution state and SCR/HCR settings to | |
603 | * determine whether the corresponding CPSR bit is used to mask the | |
604 | * interrupt. | |
605 | */ | |
606 | if ((target_el > cur_el) && (target_el != 1)) { | |
607 | /* Exceptions targeting a higher EL may not be maskable */ | |
608 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
c939a7c7 AK |
609 | switch (target_el) { |
610 | case 2: | |
611 | /* | |
612 | * According to ARM DDI 0487H.a, an interrupt can be masked | |
613 | * when HCR_E2H and HCR_TGE are both set regardless of the | |
614 | * current Security state. Note that we need to revisit this | |
615 | * part again once we need to support NMI. | |
616 | */ | |
617 | if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { | |
618 | unmasked = true; | |
619 | } | |
620 | break; | |
621 | case 3: | |
622 | /* Interrupt cannot be masked when the target EL is 3 */ | |
16e07f78 | 623 | unmasked = true; |
c939a7c7 AK |
624 | break; |
625 | default: | |
626 | g_assert_not_reached(); | |
310cedf3 RH |
627 | } |
628 | } else { | |
629 | /* | |
630 | * The old 32-bit-only environment has a more complicated | |
631 | * masking setup. HCR and SCR bits not only affect interrupt | |
632 | * routing but also change the behaviour of masking. | |
633 | */ | |
634 | bool hcr, scr; | |
635 | ||
636 | switch (excp_idx) { | |
637 | case EXCP_FIQ: | |
638 | /* | |
639 | * If FIQs are routed to EL3 or EL2 then there are cases where | |
640 | * we override the CPSR.F in determining if the exception is | |
641 | * masked or not. If neither of these are set then we fall back | |
642 | * to the CPSR.F setting otherwise we further assess the state | |
643 | * below. | |
644 | */ | |
645 | hcr = hcr_el2 & HCR_FMO; | |
646 | scr = (env->cp15.scr_el3 & SCR_FIQ); | |
647 | ||
648 | /* | |
649 | * When EL3 is 32-bit, the SCR.FW bit controls whether the | |
650 | * CPSR.F bit masks FIQ interrupts when taken in non-secure | |
651 | * state. If SCR.FW is set then FIQs can be masked by CPSR.F | |
652 | * when non-secure but only when FIQs are only routed to EL3. | |
653 | */ | |
654 | scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); | |
655 | break; | |
656 | case EXCP_IRQ: | |
657 | /* | |
658 | * When EL3 execution state is 32-bit, if HCR.IMO is set then | |
659 | * we may override the CPSR.I masking when in non-secure state. | |
660 | * The SCR.IRQ setting has already been taken into consideration | |
661 | * when setting the target EL, so it does not have a further | |
662 | * affect here. | |
663 | */ | |
664 | hcr = hcr_el2 & HCR_IMO; | |
665 | scr = false; | |
666 | break; | |
667 | default: | |
668 | g_assert_not_reached(); | |
669 | } | |
670 | ||
671 | if ((scr || hcr) && !secure) { | |
16e07f78 | 672 | unmasked = true; |
310cedf3 RH |
673 | } |
674 | } | |
675 | } | |
676 | ||
677 | /* | |
678 | * The PSTATE bits only mask the interrupt if we have not overriden the | |
679 | * ability above. | |
680 | */ | |
681 | return unmasked || pstate_unmasked; | |
682 | } | |
683 | ||
083afd18 | 684 | static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
e8925712 RH |
685 | { |
686 | CPUClass *cc = CPU_GET_CLASS(cs); | |
012a906b GB |
687 | CPUARMState *env = cs->env_ptr; |
688 | uint32_t cur_el = arm_current_el(env); | |
689 | bool secure = arm_is_secure(env); | |
be879556 | 690 | uint64_t hcr_el2 = arm_hcr_el2_eff(env); |
012a906b GB |
691 | uint32_t target_el; |
692 | uint32_t excp_idx; | |
d63d0ec5 RH |
693 | |
694 | /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ | |
e8925712 | 695 | |
012a906b GB |
696 | if (interrupt_request & CPU_INTERRUPT_FIQ) { |
697 | excp_idx = EXCP_FIQ; | |
698 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
be879556 RH |
699 | if (arm_excp_unmasked(cs, excp_idx, target_el, |
700 | cur_el, secure, hcr_el2)) { | |
d63d0ec5 | 701 | goto found; |
012a906b | 702 | } |
e8925712 | 703 | } |
012a906b GB |
704 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
705 | excp_idx = EXCP_IRQ; | |
706 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
be879556 RH |
707 | if (arm_excp_unmasked(cs, excp_idx, target_el, |
708 | cur_el, secure, hcr_el2)) { | |
d63d0ec5 | 709 | goto found; |
012a906b | 710 | } |
e8925712 | 711 | } |
012a906b GB |
712 | if (interrupt_request & CPU_INTERRUPT_VIRQ) { |
713 | excp_idx = EXCP_VIRQ; | |
714 | target_el = 1; | |
be879556 RH |
715 | if (arm_excp_unmasked(cs, excp_idx, target_el, |
716 | cur_el, secure, hcr_el2)) { | |
d63d0ec5 | 717 | goto found; |
012a906b | 718 | } |
136e67e9 | 719 | } |
012a906b GB |
720 | if (interrupt_request & CPU_INTERRUPT_VFIQ) { |
721 | excp_idx = EXCP_VFIQ; | |
722 | target_el = 1; | |
be879556 RH |
723 | if (arm_excp_unmasked(cs, excp_idx, target_el, |
724 | cur_el, secure, hcr_el2)) { | |
d63d0ec5 | 725 | goto found; |
012a906b | 726 | } |
136e67e9 | 727 | } |
3c29632f RH |
728 | if (interrupt_request & CPU_INTERRUPT_VSERR) { |
729 | excp_idx = EXCP_VSERR; | |
730 | target_el = 1; | |
731 | if (arm_excp_unmasked(cs, excp_idx, target_el, | |
732 | cur_el, secure, hcr_el2)) { | |
733 | /* Taking a virtual abort clears HCR_EL2.VSE */ | |
734 | env->cp15.hcr_el2 &= ~HCR_VSE; | |
735 | cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); | |
736 | goto found; | |
737 | } | |
738 | } | |
d63d0ec5 | 739 | return false; |
e8925712 | 740 | |
d63d0ec5 RH |
741 | found: |
742 | cs->exception_index = excp_idx; | |
743 | env->exception.target_el = target_el; | |
78271684 | 744 | cc->tcg_ops->do_interrupt(cs); |
d63d0ec5 | 745 | return true; |
e8925712 | 746 | } |
9e406eea PMD |
747 | |
748 | #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ | |
e8925712 | 749 | |
89430fc6 PM |
750 | void arm_cpu_update_virq(ARMCPU *cpu) |
751 | { | |
752 | /* | |
753 | * Update the interrupt level for VIRQ, which is the logical OR of | |
754 | * the HCR_EL2.VI bit and the input line level from the GIC. | |
755 | */ | |
756 | CPUARMState *env = &cpu->env; | |
757 | CPUState *cs = CPU(cpu); | |
758 | ||
759 | bool new_state = (env->cp15.hcr_el2 & HCR_VI) || | |
760 | (env->irq_line_state & CPU_INTERRUPT_VIRQ); | |
761 | ||
762 | if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { | |
763 | if (new_state) { | |
764 | cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); | |
765 | } else { | |
766 | cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); | |
767 | } | |
768 | } | |
769 | } | |
770 | ||
771 | void arm_cpu_update_vfiq(ARMCPU *cpu) | |
772 | { | |
773 | /* | |
774 | * Update the interrupt level for VFIQ, which is the logical OR of | |
775 | * the HCR_EL2.VF bit and the input line level from the GIC. | |
776 | */ | |
777 | CPUARMState *env = &cpu->env; | |
778 | CPUState *cs = CPU(cpu); | |
779 | ||
780 | bool new_state = (env->cp15.hcr_el2 & HCR_VF) || | |
781 | (env->irq_line_state & CPU_INTERRUPT_VFIQ); | |
782 | ||
783 | if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { | |
784 | if (new_state) { | |
785 | cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); | |
786 | } else { | |
787 | cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); | |
788 | } | |
789 | } | |
790 | } | |
791 | ||
3c29632f RH |
792 | void arm_cpu_update_vserr(ARMCPU *cpu) |
793 | { | |
794 | /* | |
795 | * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. | |
796 | */ | |
797 | CPUARMState *env = &cpu->env; | |
798 | CPUState *cs = CPU(cpu); | |
799 | ||
800 | bool new_state = env->cp15.hcr_el2 & HCR_VSE; | |
801 | ||
802 | if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) { | |
803 | if (new_state) { | |
804 | cpu_interrupt(cs, CPU_INTERRUPT_VSERR); | |
805 | } else { | |
806 | cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); | |
807 | } | |
808 | } | |
809 | } | |
810 | ||
7c1840b6 PM |
811 | #ifndef CONFIG_USER_ONLY |
812 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | |
813 | { | |
814 | ARMCPU *cpu = opaque; | |
136e67e9 | 815 | CPUARMState *env = &cpu->env; |
7c1840b6 | 816 | CPUState *cs = CPU(cpu); |
136e67e9 EI |
817 | static const int mask[] = { |
818 | [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, | |
819 | [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, | |
820 | [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, | |
821 | [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ | |
822 | }; | |
7c1840b6 | 823 | |
9acd2d33 PM |
824 | if (!arm_feature(env, ARM_FEATURE_EL2) && |
825 | (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) { | |
826 | /* | |
827 | * The GIC might tell us about VIRQ and VFIQ state, but if we don't | |
828 | * have EL2 support we don't care. (Unless the guest is doing something | |
829 | * silly this will only be calls saying "level is still 0".) | |
830 | */ | |
831 | return; | |
832 | } | |
833 | ||
ed89f078 PM |
834 | if (level) { |
835 | env->irq_line_state |= mask[irq]; | |
836 | } else { | |
837 | env->irq_line_state &= ~mask[irq]; | |
838 | } | |
839 | ||
7c1840b6 | 840 | switch (irq) { |
136e67e9 | 841 | case ARM_CPU_VIRQ: |
89430fc6 PM |
842 | arm_cpu_update_virq(cpu); |
843 | break; | |
136e67e9 | 844 | case ARM_CPU_VFIQ: |
89430fc6 PM |
845 | arm_cpu_update_vfiq(cpu); |
846 | break; | |
136e67e9 | 847 | case ARM_CPU_IRQ: |
7c1840b6 PM |
848 | case ARM_CPU_FIQ: |
849 | if (level) { | |
136e67e9 | 850 | cpu_interrupt(cs, mask[irq]); |
7c1840b6 | 851 | } else { |
136e67e9 | 852 | cpu_reset_interrupt(cs, mask[irq]); |
7c1840b6 PM |
853 | } |
854 | break; | |
855 | default: | |
8f6fd322 | 856 | g_assert_not_reached(); |
7c1840b6 PM |
857 | } |
858 | } | |
859 | ||
860 | static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) | |
861 | { | |
862 | #ifdef CONFIG_KVM | |
863 | ARMCPU *cpu = opaque; | |
ed89f078 | 864 | CPUARMState *env = &cpu->env; |
7c1840b6 | 865 | CPUState *cs = CPU(cpu); |
ed89f078 | 866 | uint32_t linestate_bit; |
f6530926 | 867 | int irq_id; |
7c1840b6 PM |
868 | |
869 | switch (irq) { | |
870 | case ARM_CPU_IRQ: | |
f6530926 | 871 | irq_id = KVM_ARM_IRQ_CPU_IRQ; |
ed89f078 | 872 | linestate_bit = CPU_INTERRUPT_HARD; |
7c1840b6 PM |
873 | break; |
874 | case ARM_CPU_FIQ: | |
f6530926 | 875 | irq_id = KVM_ARM_IRQ_CPU_FIQ; |
ed89f078 | 876 | linestate_bit = CPU_INTERRUPT_FIQ; |
7c1840b6 PM |
877 | break; |
878 | default: | |
8f6fd322 | 879 | g_assert_not_reached(); |
7c1840b6 | 880 | } |
ed89f078 PM |
881 | |
882 | if (level) { | |
883 | env->irq_line_state |= linestate_bit; | |
884 | } else { | |
885 | env->irq_line_state &= ~linestate_bit; | |
886 | } | |
f6530926 | 887 | kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); |
7c1840b6 PM |
888 | #endif |
889 | } | |
84f2bed3 | 890 | |
ed50ff78 | 891 | static bool arm_cpu_virtio_is_big_endian(CPUState *cs) |
84f2bed3 PS |
892 | { |
893 | ARMCPU *cpu = ARM_CPU(cs); | |
894 | CPUARMState *env = &cpu->env; | |
84f2bed3 PS |
895 | |
896 | cpu_synchronize_state(cs); | |
ed50ff78 | 897 | return arm_cpu_data_is_big_endian(env); |
84f2bed3 PS |
898 | } |
899 | ||
7c1840b6 PM |
900 | #endif |
901 | ||
48440620 PC |
902 | static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) |
903 | { | |
904 | ARMCPU *ac = ARM_CPU(cpu); | |
905 | CPUARMState *env = &ac->env; | |
7bcdbf51 | 906 | bool sctlr_b; |
48440620 PC |
907 | |
908 | if (is_a64(env)) { | |
110f6c70 | 909 | info->cap_arch = CS_ARCH_ARM64; |
15fa1a0a RH |
910 | info->cap_insn_unit = 4; |
911 | info->cap_insn_split = 4; | |
48440620 | 912 | } else { |
110f6c70 RH |
913 | int cap_mode; |
914 | if (env->thumb) { | |
15fa1a0a RH |
915 | info->cap_insn_unit = 2; |
916 | info->cap_insn_split = 4; | |
110f6c70 RH |
917 | cap_mode = CS_MODE_THUMB; |
918 | } else { | |
15fa1a0a RH |
919 | info->cap_insn_unit = 4; |
920 | info->cap_insn_split = 4; | |
110f6c70 RH |
921 | cap_mode = CS_MODE_ARM; |
922 | } | |
923 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
924 | cap_mode |= CS_MODE_V8; | |
925 | } | |
926 | if (arm_feature(env, ARM_FEATURE_M)) { | |
927 | cap_mode |= CS_MODE_MCLASS; | |
928 | } | |
929 | info->cap_arch = CS_ARCH_ARM; | |
930 | info->cap_mode = cap_mode; | |
48440620 | 931 | } |
7bcdbf51 RH |
932 | |
933 | sctlr_b = arm_sctlr_b(env); | |
934 | if (bswap_code(sctlr_b)) { | |
ee3eb3a7 | 935 | #if TARGET_BIG_ENDIAN |
48440620 PC |
936 | info->endian = BFD_ENDIAN_LITTLE; |
937 | #else | |
938 | info->endian = BFD_ENDIAN_BIG; | |
939 | #endif | |
940 | } | |
f7478a92 | 941 | info->flags &= ~INSN_ARM_BE32; |
7bcdbf51 RH |
942 | #ifndef CONFIG_USER_ONLY |
943 | if (sctlr_b) { | |
f7478a92 JB |
944 | info->flags |= INSN_ARM_BE32; |
945 | } | |
7bcdbf51 | 946 | #endif |
48440620 PC |
947 | } |
948 | ||
86480615 PMD |
949 | #ifdef TARGET_AARCH64 |
950 | ||
951 | static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) | |
952 | { | |
953 | ARMCPU *cpu = ARM_CPU(cs); | |
954 | CPUARMState *env = &cpu->env; | |
955 | uint32_t psr = pstate_read(env); | |
956 | int i; | |
957 | int el = arm_current_el(env); | |
958 | const char *ns_status; | |
7a867dd5 | 959 | bool sve; |
86480615 PMD |
960 | |
961 | qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); | |
962 | for (i = 0; i < 32; i++) { | |
963 | if (i == 31) { | |
964 | qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); | |
965 | } else { | |
966 | qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], | |
967 | (i + 2) % 3 ? " " : "\n"); | |
968 | } | |
969 | } | |
970 | ||
971 | if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { | |
972 | ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; | |
973 | } else { | |
974 | ns_status = ""; | |
975 | } | |
976 | qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", | |
977 | psr, | |
978 | psr & PSTATE_N ? 'N' : '-', | |
979 | psr & PSTATE_Z ? 'Z' : '-', | |
980 | psr & PSTATE_C ? 'C' : '-', | |
981 | psr & PSTATE_V ? 'V' : '-', | |
982 | ns_status, | |
983 | el, | |
984 | psr & PSTATE_SP ? 'h' : 't'); | |
985 | ||
7a867dd5 RH |
986 | if (cpu_isar_feature(aa64_sme, cpu)) { |
987 | qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c", | |
988 | env->svcr, | |
989 | (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), | |
990 | (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); | |
991 | } | |
86480615 PMD |
992 | if (cpu_isar_feature(aa64_bti, cpu)) { |
993 | qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); | |
994 | } | |
995 | if (!(flags & CPU_DUMP_FPU)) { | |
996 | qemu_fprintf(f, "\n"); | |
997 | return; | |
998 | } | |
999 | if (fp_exception_el(env, el) != 0) { | |
1000 | qemu_fprintf(f, " FPU disabled\n"); | |
1001 | return; | |
1002 | } | |
1003 | qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", | |
1004 | vfp_get_fpcr(env), vfp_get_fpsr(env)); | |
1005 | ||
7a867dd5 RH |
1006 | if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) { |
1007 | sve = sme_exception_el(env, el) == 0; | |
1008 | } else if (cpu_isar_feature(aa64_sve, cpu)) { | |
1009 | sve = sve_exception_el(env, el) == 0; | |
1010 | } else { | |
1011 | sve = false; | |
1012 | } | |
1013 | ||
1014 | if (sve) { | |
5ef3cc56 | 1015 | int j, zcr_len = sve_vqm1_for_el(env, el); |
86480615 PMD |
1016 | |
1017 | for (i = 0; i <= FFR_PRED_NUM; i++) { | |
1018 | bool eol; | |
1019 | if (i == FFR_PRED_NUM) { | |
1020 | qemu_fprintf(f, "FFR="); | |
1021 | /* It's last, so end the line. */ | |
1022 | eol = true; | |
1023 | } else { | |
1024 | qemu_fprintf(f, "P%02d=", i); | |
1025 | switch (zcr_len) { | |
1026 | case 0: | |
1027 | eol = i % 8 == 7; | |
1028 | break; | |
1029 | case 1: | |
1030 | eol = i % 6 == 5; | |
1031 | break; | |
1032 | case 2: | |
1033 | case 3: | |
1034 | eol = i % 3 == 2; | |
1035 | break; | |
1036 | default: | |
1037 | /* More than one quadword per predicate. */ | |
1038 | eol = true; | |
1039 | break; | |
1040 | } | |
1041 | } | |
1042 | for (j = zcr_len / 4; j >= 0; j--) { | |
1043 | int digits; | |
1044 | if (j * 4 + 4 <= zcr_len + 1) { | |
1045 | digits = 16; | |
1046 | } else { | |
1047 | digits = (zcr_len % 4 + 1) * 4; | |
1048 | } | |
1049 | qemu_fprintf(f, "%0*" PRIx64 "%s", digits, | |
1050 | env->vfp.pregs[i].p[j], | |
1051 | j ? ":" : eol ? "\n" : " "); | |
1052 | } | |
1053 | } | |
1054 | ||
1055 | for (i = 0; i < 32; i++) { | |
1056 | if (zcr_len == 0) { | |
1057 | qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", | |
1058 | i, env->vfp.zregs[i].d[1], | |
1059 | env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); | |
1060 | } else if (zcr_len == 1) { | |
1061 | qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 | |
1062 | ":%016" PRIx64 ":%016" PRIx64 "\n", | |
1063 | i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], | |
1064 | env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); | |
1065 | } else { | |
1066 | for (j = zcr_len; j >= 0; j--) { | |
1067 | bool odd = (zcr_len - j) % 2 != 0; | |
1068 | if (j == zcr_len) { | |
1069 | qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); | |
1070 | } else if (!odd) { | |
1071 | if (j > 0) { | |
1072 | qemu_fprintf(f, " [%x-%x]=", j, j - 1); | |
1073 | } else { | |
1074 | qemu_fprintf(f, " [%x]=", j); | |
1075 | } | |
1076 | } | |
1077 | qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", | |
1078 | env->vfp.zregs[i].d[j * 2 + 1], | |
1079 | env->vfp.zregs[i].d[j * 2], | |
1080 | odd || j == 0 ? "\n" : ":"); | |
1081 | } | |
1082 | } | |
1083 | } | |
1084 | } else { | |
1085 | for (i = 0; i < 32; i++) { | |
1086 | uint64_t *q = aa64_vfp_qreg(env, i); | |
1087 | qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", | |
1088 | i, q[1], q[0], (i & 1 ? "\n" : " ")); | |
1089 | } | |
1090 | } | |
1091 | } | |
1092 | ||
1093 | #else | |
1094 | ||
1095 | static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) | |
1096 | { | |
1097 | g_assert_not_reached(); | |
1098 | } | |
1099 | ||
1100 | #endif | |
1101 | ||
1102 | static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) | |
1103 | { | |
1104 | ARMCPU *cpu = ARM_CPU(cs); | |
1105 | CPUARMState *env = &cpu->env; | |
1106 | int i; | |
1107 | ||
1108 | if (is_a64(env)) { | |
1109 | aarch64_cpu_dump_state(cs, f, flags); | |
1110 | return; | |
1111 | } | |
1112 | ||
1113 | for (i = 0; i < 16; i++) { | |
1114 | qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); | |
1115 | if ((i % 4) == 3) { | |
1116 | qemu_fprintf(f, "\n"); | |
1117 | } else { | |
1118 | qemu_fprintf(f, " "); | |
1119 | } | |
1120 | } | |
1121 | ||
1122 | if (arm_feature(env, ARM_FEATURE_M)) { | |
1123 | uint32_t xpsr = xpsr_read(env); | |
1124 | const char *mode; | |
1125 | const char *ns_status = ""; | |
1126 | ||
1127 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
1128 | ns_status = env->v7m.secure ? "S " : "NS "; | |
1129 | } | |
1130 | ||
1131 | if (xpsr & XPSR_EXCP) { | |
1132 | mode = "handler"; | |
1133 | } else { | |
1134 | if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { | |
1135 | mode = "unpriv-thread"; | |
1136 | } else { | |
1137 | mode = "priv-thread"; | |
1138 | } | |
1139 | } | |
1140 | ||
1141 | qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", | |
1142 | xpsr, | |
1143 | xpsr & XPSR_N ? 'N' : '-', | |
1144 | xpsr & XPSR_Z ? 'Z' : '-', | |
1145 | xpsr & XPSR_C ? 'C' : '-', | |
1146 | xpsr & XPSR_V ? 'V' : '-', | |
1147 | xpsr & XPSR_T ? 'T' : 'A', | |
1148 | ns_status, | |
1149 | mode); | |
1150 | } else { | |
1151 | uint32_t psr = cpsr_read(env); | |
1152 | const char *ns_status = ""; | |
1153 | ||
1154 | if (arm_feature(env, ARM_FEATURE_EL3) && | |
1155 | (psr & CPSR_M) != ARM_CPU_MODE_MON) { | |
1156 | ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; | |
1157 | } | |
1158 | ||
1159 | qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", | |
1160 | psr, | |
1161 | psr & CPSR_N ? 'N' : '-', | |
1162 | psr & CPSR_Z ? 'Z' : '-', | |
1163 | psr & CPSR_C ? 'C' : '-', | |
1164 | psr & CPSR_V ? 'V' : '-', | |
1165 | psr & CPSR_T ? 'T' : 'A', | |
1166 | ns_status, | |
1167 | aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); | |
1168 | } | |
1169 | ||
1170 | if (flags & CPU_DUMP_FPU) { | |
1171 | int numvfpregs = 0; | |
a6627f5f RH |
1172 | if (cpu_isar_feature(aa32_simd_r32, cpu)) { |
1173 | numvfpregs = 32; | |
7fbc6a40 | 1174 | } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { |
a6627f5f | 1175 | numvfpregs = 16; |
86480615 PMD |
1176 | } |
1177 | for (i = 0; i < numvfpregs; i++) { | |
1178 | uint64_t v = *aa32_vfp_dreg(env, i); | |
1179 | qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", | |
1180 | i * 2, (uint32_t)v, | |
1181 | i * 2 + 1, (uint32_t)(v >> 32), | |
1182 | i, v); | |
1183 | } | |
1184 | qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); | |
aa291908 PM |
1185 | if (cpu_isar_feature(aa32_mve, cpu)) { |
1186 | qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); | |
1187 | } | |
86480615 PMD |
1188 | } |
1189 | } | |
1190 | ||
46de5913 IM |
1191 | uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) |
1192 | { | |
1193 | uint32_t Aff1 = idx / clustersz; | |
1194 | uint32_t Aff0 = idx % clustersz; | |
1195 | return (Aff1 << ARM_AFF1_SHIFT) | Aff0; | |
1196 | } | |
1197 | ||
777dc784 PM |
1198 | static void arm_cpu_initfn(Object *obj) |
1199 | { | |
1200 | ARMCPU *cpu = ARM_CPU(obj); | |
1201 | ||
7506ed90 | 1202 | cpu_set_cpustate_pointers(cpu); |
5860362d | 1203 | cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal, |
c27f5d3a | 1204 | NULL, g_free); |
79614b78 | 1205 | |
b5c53d1b | 1206 | QLIST_INIT(&cpu->pre_el_change_hooks); |
08267487 AL |
1207 | QLIST_INIT(&cpu->el_change_hooks); |
1208 | ||
b3d52804 RH |
1209 | #ifdef CONFIG_USER_ONLY |
1210 | # ifdef TARGET_AARCH64 | |
1211 | /* | |
e74c0976 RH |
1212 | * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME. |
1213 | * These values were chosen to fit within the default signal frame. | |
1214 | * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length, | |
1215 | * and our corresponding cpu property. | |
b3d52804 RH |
1216 | */ |
1217 | cpu->sve_default_vq = 4; | |
e74c0976 | 1218 | cpu->sme_default_vq = 2; |
b3d52804 RH |
1219 | # endif |
1220 | #else | |
7c1840b6 PM |
1221 | /* Our inbound IRQ and FIQ lines */ |
1222 | if (kvm_enabled()) { | |
136e67e9 EI |
1223 | /* VIRQ and VFIQ are unused with KVM but we add them to maintain |
1224 | * the same interface as non-KVM CPUs. | |
1225 | */ | |
1226 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); | |
7c1840b6 | 1227 | } else { |
136e67e9 | 1228 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); |
7c1840b6 | 1229 | } |
55d284af | 1230 | |
55d284af PM |
1231 | qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, |
1232 | ARRAY_SIZE(cpu->gt_timer_outputs)); | |
aa1b3111 PM |
1233 | |
1234 | qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, | |
1235 | "gicv3-maintenance-interrupt", 1); | |
07f48730 AJ |
1236 | qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, |
1237 | "pmu-interrupt", 1); | |
7c1840b6 PM |
1238 | #endif |
1239 | ||
54d3e3f5 PM |
1240 | /* DTB consumers generally don't in fact care what the 'compatible' |
1241 | * string is, so always provide some string and trust that a hypothetical | |
1242 | * picky DTB consumer will also provide a helpful error message. | |
1243 | */ | |
1244 | cpu->dtb_compatible = "qemu,unknown"; | |
0dc71c70 | 1245 | cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ |
3541addc | 1246 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; |
54d3e3f5 | 1247 | |
2c9c0bf9 | 1248 | if (tcg_enabled() || hvf_enabled()) { |
0dc71c70 AO |
1249 | /* TCG and HVF implement PSCI 1.1 */ |
1250 | cpu->psci_version = QEMU_PSCI_VERSION_1_1; | |
79614b78 | 1251 | } |
4b6a83fb PM |
1252 | } |
1253 | ||
96eec6b2 AJ |
1254 | static Property arm_cpu_gt_cntfrq_property = |
1255 | DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, | |
1256 | NANOSECONDS_PER_SECOND / GTIMER_SCALE); | |
1257 | ||
07a5b0d2 | 1258 | static Property arm_cpu_reset_cbar_property = |
f318cec6 | 1259 | DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); |
07a5b0d2 | 1260 | |
68e0a40a AP |
1261 | static Property arm_cpu_reset_hivecs_property = |
1262 | DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); | |
1263 | ||
45ca3a14 | 1264 | #ifndef CONFIG_USER_ONLY |
c25bd18a PM |
1265 | static Property arm_cpu_has_el2_property = |
1266 | DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); | |
1267 | ||
51942aee GB |
1268 | static Property arm_cpu_has_el3_property = |
1269 | DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); | |
45ca3a14 | 1270 | #endif |
51942aee | 1271 | |
3a062d57 JB |
1272 | static Property arm_cpu_cfgend_property = |
1273 | DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); | |
1274 | ||
97a28b0e PM |
1275 | static Property arm_cpu_has_vfp_property = |
1276 | DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); | |
1277 | ||
1278 | static Property arm_cpu_has_neon_property = | |
1279 | DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); | |
1280 | ||
ea90db0a PM |
1281 | static Property arm_cpu_has_dsp_property = |
1282 | DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); | |
1283 | ||
8f325f56 PC |
1284 | static Property arm_cpu_has_mpu_property = |
1285 | DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); | |
1286 | ||
8d92e26b PM |
1287 | /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, |
1288 | * because the CPU initfn will have already set cpu->pmsav7_dregion to | |
1289 | * the right value for that particular CPU type, and we don't want | |
1290 | * to override that with an incorrect constant value. | |
1291 | */ | |
3281af81 | 1292 | static Property arm_cpu_pmsav7_dregion_property = |
8d92e26b PM |
1293 | DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, |
1294 | pmsav7_dregion, | |
1295 | qdev_prop_uint32, uint32_t); | |
3281af81 | 1296 | |
ae502508 AJ |
1297 | static bool arm_get_pmu(Object *obj, Error **errp) |
1298 | { | |
1299 | ARMCPU *cpu = ARM_CPU(obj); | |
1300 | ||
1301 | return cpu->has_pmu; | |
1302 | } | |
1303 | ||
1304 | static void arm_set_pmu(Object *obj, bool value, Error **errp) | |
1305 | { | |
1306 | ARMCPU *cpu = ARM_CPU(obj); | |
1307 | ||
1308 | if (value) { | |
7d20e681 | 1309 | if (kvm_enabled() && !kvm_arm_pmu_supported()) { |
ae502508 AJ |
1310 | error_setg(errp, "'pmu' feature not supported by KVM on this host"); |
1311 | return; | |
1312 | } | |
1313 | set_feature(&cpu->env, ARM_FEATURE_PMU); | |
1314 | } else { | |
1315 | unset_feature(&cpu->env, ARM_FEATURE_PMU); | |
1316 | } | |
1317 | cpu->has_pmu = value; | |
1318 | } | |
1319 | ||
7def8754 AJ |
1320 | unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) |
1321 | { | |
96eec6b2 AJ |
1322 | /* |
1323 | * The exact approach to calculating guest ticks is: | |
1324 | * | |
1325 | * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, | |
1326 | * NANOSECONDS_PER_SECOND); | |
1327 | * | |
1328 | * We don't do that. Rather we intentionally use integer division | |
1329 | * truncation below and in the caller for the conversion of host monotonic | |
1330 | * time to guest ticks to provide the exact inverse for the semantics of | |
1331 | * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so | |
1332 | * it loses precision when representing frequencies where | |
1333 | * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to | |
1334 | * provide an exact inverse leads to scheduling timers with negative | |
1335 | * periods, which in turn leads to sticky behaviour in the guest. | |
1336 | * | |
1337 | * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor | |
1338 | * cannot become zero. | |
1339 | */ | |
7def8754 AJ |
1340 | return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? |
1341 | NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; | |
1342 | } | |
1343 | ||
51e5ef45 | 1344 | void arm_cpu_post_init(Object *obj) |
07a5b0d2 PC |
1345 | { |
1346 | ARMCPU *cpu = ARM_CPU(obj); | |
07a5b0d2 | 1347 | |
790a1150 PM |
1348 | /* M profile implies PMSA. We have to do this here rather than |
1349 | * in realize with the other feature-implication checks because | |
1350 | * we look at the PMSA bit to see if we should add some properties. | |
1351 | */ | |
1352 | if (arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
1353 | set_feature(&cpu->env, ARM_FEATURE_PMSA); | |
1354 | } | |
1355 | ||
f318cec6 PM |
1356 | if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || |
1357 | arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { | |
94d912d1 | 1358 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); |
07a5b0d2 | 1359 | } |
68e0a40a AP |
1360 | |
1361 | if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
94d912d1 | 1362 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); |
68e0a40a | 1363 | } |
3933443e | 1364 | |
910e4f24 | 1365 | if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { |
4a7319b7 EI |
1366 | object_property_add_uint64_ptr(obj, "rvbar", |
1367 | &cpu->rvbar_prop, | |
1368 | OBJ_PROP_FLAG_READWRITE); | |
3933443e | 1369 | } |
51942aee | 1370 | |
45ca3a14 | 1371 | #ifndef CONFIG_USER_ONLY |
51942aee GB |
1372 | if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { |
1373 | /* Add the has_el3 state CPU property only if EL3 is allowed. This will | |
1374 | * prevent "has_el3" from existing on CPUs which cannot support EL3. | |
1375 | */ | |
94d912d1 | 1376 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); |
9e273ef2 | 1377 | |
9e273ef2 PM |
1378 | object_property_add_link(obj, "secure-memory", |
1379 | TYPE_MEMORY_REGION, | |
1380 | (Object **)&cpu->secure_memory, | |
1381 | qdev_prop_allow_set_link_before_realize, | |
d2623129 | 1382 | OBJ_PROP_LINK_STRONG); |
51942aee | 1383 | } |
8f325f56 | 1384 | |
c25bd18a | 1385 | if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { |
94d912d1 | 1386 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); |
c25bd18a | 1387 | } |
45ca3a14 | 1388 | #endif |
c25bd18a | 1389 | |
929e754d | 1390 | if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { |
ae502508 | 1391 | cpu->has_pmu = true; |
d2623129 | 1392 | object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); |
929e754d WH |
1393 | } |
1394 | ||
97a28b0e PM |
1395 | /* |
1396 | * Allow user to turn off VFP and Neon support, but only for TCG -- | |
1397 | * KVM does not currently allow us to lie to the guest about its | |
1398 | * ID/feature registers, so the guest always sees what the host has. | |
1399 | */ | |
7d63183f RH |
1400 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) |
1401 | ? cpu_isar_feature(aa64_fp_simd, cpu) | |
1402 | : cpu_isar_feature(aa32_vfp, cpu)) { | |
97a28b0e PM |
1403 | cpu->has_vfp = true; |
1404 | if (!kvm_enabled()) { | |
94d912d1 | 1405 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); |
97a28b0e PM |
1406 | } |
1407 | } | |
1408 | ||
1409 | if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { | |
1410 | cpu->has_neon = true; | |
1411 | if (!kvm_enabled()) { | |
94d912d1 | 1412 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); |
97a28b0e PM |
1413 | } |
1414 | } | |
1415 | ||
ea90db0a PM |
1416 | if (arm_feature(&cpu->env, ARM_FEATURE_M) && |
1417 | arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { | |
94d912d1 | 1418 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); |
ea90db0a PM |
1419 | } |
1420 | ||
452a0955 | 1421 | if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { |
94d912d1 | 1422 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); |
3281af81 PC |
1423 | if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { |
1424 | qdev_property_add_static(DEVICE(obj), | |
94d912d1 | 1425 | &arm_cpu_pmsav7_dregion_property); |
3281af81 | 1426 | } |
8f325f56 PC |
1427 | } |
1428 | ||
181962fd PM |
1429 | if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { |
1430 | object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, | |
1431 | qdev_prop_allow_set_link_before_realize, | |
d2623129 | 1432 | OBJ_PROP_LINK_STRONG); |
f9f62e4c PM |
1433 | /* |
1434 | * M profile: initial value of the Secure VTOR. We can't just use | |
1435 | * a simple DEFINE_PROP_UINT32 for this because we want to permit | |
1436 | * the property to be set after realize. | |
1437 | */ | |
64a7b8de FF |
1438 | object_property_add_uint32_ptr(obj, "init-svtor", |
1439 | &cpu->init_svtor, | |
d2623129 | 1440 | OBJ_PROP_FLAG_READWRITE); |
181962fd | 1441 | } |
7cda2149 PM |
1442 | if (arm_feature(&cpu->env, ARM_FEATURE_M)) { |
1443 | /* | |
1444 | * Initial value of the NS VTOR (for cores without the Security | |
1445 | * extension, this is the only VTOR) | |
1446 | */ | |
1447 | object_property_add_uint32_ptr(obj, "init-nsvtor", | |
1448 | &cpu->init_nsvtor, | |
1449 | OBJ_PROP_FLAG_READWRITE); | |
1450 | } | |
181962fd | 1451 | |
bddd892e PM |
1452 | /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ |
1453 | object_property_add_uint32_ptr(obj, "psci-conduit", | |
1454 | &cpu->psci_conduit, | |
1455 | OBJ_PROP_FLAG_READWRITE); | |
1456 | ||
94d912d1 | 1457 | qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); |
96eec6b2 AJ |
1458 | |
1459 | if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { | |
94d912d1 | 1460 | qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); |
96eec6b2 | 1461 | } |
9e6f8d8a | 1462 | |
1463 | if (kvm_enabled()) { | |
1464 | kvm_arm_add_vcpu_properties(obj); | |
1465 | } | |
8bce44a2 RH |
1466 | |
1467 | #ifndef CONFIG_USER_ONLY | |
1468 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && | |
1469 | cpu_isar_feature(aa64_mte, cpu)) { | |
1470 | object_property_add_link(obj, "tag-memory", | |
1471 | TYPE_MEMORY_REGION, | |
1472 | (Object **)&cpu->tag_memory, | |
1473 | qdev_prop_allow_set_link_before_realize, | |
1474 | OBJ_PROP_LINK_STRONG); | |
1475 | ||
1476 | if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { | |
1477 | object_property_add_link(obj, "secure-tag-memory", | |
1478 | TYPE_MEMORY_REGION, | |
1479 | (Object **)&cpu->secure_tag_memory, | |
1480 | qdev_prop_allow_set_link_before_realize, | |
1481 | OBJ_PROP_LINK_STRONG); | |
1482 | } | |
b320e21c | 1483 | cpu->has_mte = true; |
8bce44a2 RH |
1484 | } |
1485 | #endif | |
07a5b0d2 PC |
1486 | } |
1487 | ||
4b6a83fb PM |
1488 | static void arm_cpu_finalizefn(Object *obj) |
1489 | { | |
1490 | ARMCPU *cpu = ARM_CPU(obj); | |
08267487 AL |
1491 | ARMELChangeHook *hook, *next; |
1492 | ||
4b6a83fb | 1493 | g_hash_table_destroy(cpu->cp_regs); |
08267487 | 1494 | |
b5c53d1b AL |
1495 | QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { |
1496 | QLIST_REMOVE(hook, node); | |
1497 | g_free(hook); | |
1498 | } | |
08267487 AL |
1499 | QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { |
1500 | QLIST_REMOVE(hook, node); | |
1501 | g_free(hook); | |
1502 | } | |
4e7beb0c AL |
1503 | #ifndef CONFIG_USER_ONLY |
1504 | if (cpu->pmu_timer) { | |
4e7beb0c AL |
1505 | timer_free(cpu->pmu_timer); |
1506 | } | |
1507 | #endif | |
777dc784 PM |
1508 | } |
1509 | ||
0df9142d AJ |
1510 | void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) |
1511 | { | |
1512 | Error *local_err = NULL; | |
1513 | ||
07301161 | 1514 | #ifdef TARGET_AARCH64 |
0df9142d AJ |
1515 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { |
1516 | arm_cpu_sve_finalize(cpu, &local_err); | |
68970d1e AJ |
1517 | if (local_err != NULL) { |
1518 | error_propagate(errp, local_err); | |
1519 | return; | |
1520 | } | |
eb94284d | 1521 | |
e74c0976 RH |
1522 | arm_cpu_sme_finalize(cpu, &local_err); |
1523 | if (local_err != NULL) { | |
1524 | error_propagate(errp, local_err); | |
1525 | return; | |
1526 | } | |
1527 | ||
95ea96e8 MZ |
1528 | arm_cpu_pauth_finalize(cpu, &local_err); |
1529 | if (local_err != NULL) { | |
1530 | error_propagate(errp, local_err); | |
1531 | return; | |
eb94284d | 1532 | } |
69b2265d RH |
1533 | |
1534 | arm_cpu_lpa2_finalize(cpu, &local_err); | |
1535 | if (local_err != NULL) { | |
1536 | error_propagate(errp, local_err); | |
1537 | return; | |
1538 | } | |
68970d1e | 1539 | } |
07301161 | 1540 | #endif |
68970d1e AJ |
1541 | |
1542 | if (kvm_enabled()) { | |
1543 | kvm_arm_steal_time_finalize(cpu, &local_err); | |
0df9142d AJ |
1544 | if (local_err != NULL) { |
1545 | error_propagate(errp, local_err); | |
1546 | return; | |
1547 | } | |
1548 | } | |
1549 | } | |
1550 | ||
14969266 | 1551 | static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
581be094 | 1552 | { |
14a10fc3 | 1553 | CPUState *cs = CPU(dev); |
14969266 AF |
1554 | ARMCPU *cpu = ARM_CPU(dev); |
1555 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); | |
581be094 | 1556 | CPUARMState *env = &cpu->env; |
e97da98f | 1557 | int pagebits; |
ce5b1bbf | 1558 | Error *local_err = NULL; |
0f8d06f1 | 1559 | bool no_aa32 = false; |
ce5b1bbf | 1560 | |
e607ea39 AJ |
1561 | /* Use pc-relative instructions in system-mode */ |
1562 | #ifndef CONFIG_USER_ONLY | |
1563 | cs->tcg_cflags |= CF_PCREL; | |
1564 | #endif | |
1565 | ||
c4487d76 PM |
1566 | /* If we needed to query the host kernel for the CPU features |
1567 | * then it's possible that might have failed in the initfn, but | |
1568 | * this is the first point where we can report it. | |
1569 | */ | |
1570 | if (cpu->host_cpu_probe_failed) { | |
585df85e PM |
1571 | if (!kvm_enabled() && !hvf_enabled()) { |
1572 | error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); | |
c4487d76 PM |
1573 | } else { |
1574 | error_setg(errp, "Failed to retrieve host CPU features"); | |
1575 | } | |
1576 | return; | |
1577 | } | |
1578 | ||
95f87565 PM |
1579 | #ifndef CONFIG_USER_ONLY |
1580 | /* The NVIC and M-profile CPU are two halves of a single piece of | |
1581 | * hardware; trying to use one without the other is a command line | |
1582 | * error and will result in segfaults if not caught here. | |
1583 | */ | |
1584 | if (arm_feature(env, ARM_FEATURE_M)) { | |
1585 | if (!env->nvic) { | |
1586 | error_setg(errp, "This board cannot be used with Cortex-M CPUs"); | |
1587 | return; | |
1588 | } | |
1589 | } else { | |
1590 | if (env->nvic) { | |
1591 | error_setg(errp, "This board can only be used with Cortex-M CPUs"); | |
1592 | return; | |
1593 | } | |
1594 | } | |
397cd31f | 1595 | |
045e5064 | 1596 | if (!tcg_enabled() && !qtest_enabled()) { |
49e7f191 | 1597 | /* |
045e5064 AG |
1598 | * We assume that no accelerator except TCG (and the "not really an |
1599 | * accelerator" qtest) can handle these features, because Arm hardware | |
1600 | * virtualization can't virtualize them. | |
1601 | * | |
49e7f191 PM |
1602 | * Catch all the cases which might cause us to create more than one |
1603 | * address space for the CPU (otherwise we will assert() later in | |
1604 | * cpu_address_space_init()). | |
1605 | */ | |
1606 | if (arm_feature(env, ARM_FEATURE_M)) { | |
1607 | error_setg(errp, | |
045e5064 AG |
1608 | "Cannot enable %s when using an M-profile guest CPU", |
1609 | current_accel_name()); | |
49e7f191 PM |
1610 | return; |
1611 | } | |
1612 | if (cpu->has_el3) { | |
1613 | error_setg(errp, | |
045e5064 AG |
1614 | "Cannot enable %s when guest CPU has EL3 enabled", |
1615 | current_accel_name()); | |
49e7f191 PM |
1616 | return; |
1617 | } | |
1618 | if (cpu->tag_memory) { | |
1619 | error_setg(errp, | |
b320e21c | 1620 | "Cannot enable %s when guest CPUs has tag memory enabled", |
045e5064 | 1621 | current_accel_name()); |
49e7f191 PM |
1622 | return; |
1623 | } | |
1624 | } | |
1625 | ||
96eec6b2 AJ |
1626 | { |
1627 | uint64_t scale; | |
1628 | ||
1629 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { | |
1630 | if (!cpu->gt_cntfrq_hz) { | |
1631 | error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", | |
1632 | cpu->gt_cntfrq_hz); | |
1633 | return; | |
1634 | } | |
1635 | scale = gt_cntfrq_period_ns(cpu); | |
1636 | } else { | |
1637 | scale = GTIMER_SCALE; | |
1638 | } | |
1639 | ||
1640 | cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, | |
1641 | arm_gt_ptimer_cb, cpu); | |
1642 | cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, | |
1643 | arm_gt_vtimer_cb, cpu); | |
1644 | cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, | |
1645 | arm_gt_htimer_cb, cpu); | |
1646 | cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, | |
1647 | arm_gt_stimer_cb, cpu); | |
8c94b071 RH |
1648 | cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, |
1649 | arm_gt_hvtimer_cb, cpu); | |
96eec6b2 | 1650 | } |
95f87565 PM |
1651 | #endif |
1652 | ||
ce5b1bbf LV |
1653 | cpu_exec_realizefn(cs, &local_err); |
1654 | if (local_err != NULL) { | |
1655 | error_propagate(errp, local_err); | |
1656 | return; | |
1657 | } | |
14969266 | 1658 | |
0df9142d AJ |
1659 | arm_cpu_finalize_features(cpu, &local_err); |
1660 | if (local_err != NULL) { | |
1661 | error_propagate(errp, local_err); | |
1662 | return; | |
1663 | } | |
1664 | ||
97a28b0e PM |
1665 | if (arm_feature(env, ARM_FEATURE_AARCH64) && |
1666 | cpu->has_vfp != cpu->has_neon) { | |
1667 | /* | |
1668 | * This is an architectural requirement for AArch64; AArch32 is | |
1669 | * more flexible and permits VFP-no-Neon and Neon-no-VFP. | |
1670 | */ | |
1671 | error_setg(errp, | |
1672 | "AArch64 CPUs must have both VFP and Neon or neither"); | |
1673 | return; | |
1674 | } | |
1675 | ||
1676 | if (!cpu->has_vfp) { | |
1677 | uint64_t t; | |
1678 | uint32_t u; | |
1679 | ||
97a28b0e PM |
1680 | t = cpu->isar.id_aa64isar1; |
1681 | t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); | |
1682 | cpu->isar.id_aa64isar1 = t; | |
1683 | ||
1684 | t = cpu->isar.id_aa64pfr0; | |
1685 | t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); | |
1686 | cpu->isar.id_aa64pfr0 = t; | |
1687 | ||
1688 | u = cpu->isar.id_isar6; | |
1689 | u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); | |
3c93dfa4 | 1690 | u = FIELD_DP32(u, ID_ISAR6, BF16, 0); |
97a28b0e PM |
1691 | cpu->isar.id_isar6 = u; |
1692 | ||
1693 | u = cpu->isar.mvfr0; | |
1694 | u = FIELD_DP32(u, MVFR0, FPSP, 0); | |
1695 | u = FIELD_DP32(u, MVFR0, FPDP, 0); | |
97a28b0e PM |
1696 | u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); |
1697 | u = FIELD_DP32(u, MVFR0, FPSQRT, 0); | |
97a28b0e | 1698 | u = FIELD_DP32(u, MVFR0, FPROUND, 0); |
532a3af5 PM |
1699 | if (!arm_feature(env, ARM_FEATURE_M)) { |
1700 | u = FIELD_DP32(u, MVFR0, FPTRAP, 0); | |
1701 | u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); | |
1702 | } | |
97a28b0e PM |
1703 | cpu->isar.mvfr0 = u; |
1704 | ||
1705 | u = cpu->isar.mvfr1; | |
1706 | u = FIELD_DP32(u, MVFR1, FPFTZ, 0); | |
1707 | u = FIELD_DP32(u, MVFR1, FPDNAN, 0); | |
1708 | u = FIELD_DP32(u, MVFR1, FPHP, 0); | |
532a3af5 PM |
1709 | if (arm_feature(env, ARM_FEATURE_M)) { |
1710 | u = FIELD_DP32(u, MVFR1, FP16, 0); | |
1711 | } | |
97a28b0e PM |
1712 | cpu->isar.mvfr1 = u; |
1713 | ||
1714 | u = cpu->isar.mvfr2; | |
1715 | u = FIELD_DP32(u, MVFR2, FPMISC, 0); | |
1716 | cpu->isar.mvfr2 = u; | |
1717 | } | |
1718 | ||
1719 | if (!cpu->has_neon) { | |
1720 | uint64_t t; | |
1721 | uint32_t u; | |
1722 | ||
1723 | unset_feature(env, ARM_FEATURE_NEON); | |
1724 | ||
1725 | t = cpu->isar.id_aa64isar0; | |
eb851c11 DH |
1726 | t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); |
1727 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); | |
1728 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); | |
1729 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); | |
1730 | t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); | |
1731 | t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); | |
97a28b0e PM |
1732 | t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); |
1733 | cpu->isar.id_aa64isar0 = t; | |
1734 | ||
1735 | t = cpu->isar.id_aa64isar1; | |
1736 | t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); | |
3c93dfa4 | 1737 | t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); |
f8680aaa | 1738 | t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); |
97a28b0e PM |
1739 | cpu->isar.id_aa64isar1 = t; |
1740 | ||
1741 | t = cpu->isar.id_aa64pfr0; | |
1742 | t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); | |
1743 | cpu->isar.id_aa64pfr0 = t; | |
1744 | ||
1745 | u = cpu->isar.id_isar5; | |
eb851c11 DH |
1746 | u = FIELD_DP32(u, ID_ISAR5, AES, 0); |
1747 | u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); | |
1748 | u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); | |
97a28b0e PM |
1749 | u = FIELD_DP32(u, ID_ISAR5, RDM, 0); |
1750 | u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); | |
1751 | cpu->isar.id_isar5 = u; | |
1752 | ||
1753 | u = cpu->isar.id_isar6; | |
1754 | u = FIELD_DP32(u, ID_ISAR6, DP, 0); | |
1755 | u = FIELD_DP32(u, ID_ISAR6, FHM, 0); | |
3c93dfa4 | 1756 | u = FIELD_DP32(u, ID_ISAR6, BF16, 0); |
f8680aaa | 1757 | u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); |
97a28b0e PM |
1758 | cpu->isar.id_isar6 = u; |
1759 | ||
532a3af5 PM |
1760 | if (!arm_feature(env, ARM_FEATURE_M)) { |
1761 | u = cpu->isar.mvfr1; | |
1762 | u = FIELD_DP32(u, MVFR1, SIMDLS, 0); | |
1763 | u = FIELD_DP32(u, MVFR1, SIMDINT, 0); | |
1764 | u = FIELD_DP32(u, MVFR1, SIMDSP, 0); | |
1765 | u = FIELD_DP32(u, MVFR1, SIMDHP, 0); | |
1766 | cpu->isar.mvfr1 = u; | |
1767 | ||
1768 | u = cpu->isar.mvfr2; | |
1769 | u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); | |
1770 | cpu->isar.mvfr2 = u; | |
1771 | } | |
97a28b0e PM |
1772 | } |
1773 | ||
1774 | if (!cpu->has_neon && !cpu->has_vfp) { | |
1775 | uint64_t t; | |
1776 | uint32_t u; | |
1777 | ||
1778 | t = cpu->isar.id_aa64isar0; | |
1779 | t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); | |
1780 | cpu->isar.id_aa64isar0 = t; | |
1781 | ||
1782 | t = cpu->isar.id_aa64isar1; | |
1783 | t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); | |
1784 | cpu->isar.id_aa64isar1 = t; | |
1785 | ||
1786 | u = cpu->isar.mvfr0; | |
1787 | u = FIELD_DP32(u, MVFR0, SIMDREG, 0); | |
1788 | cpu->isar.mvfr0 = u; | |
c52881bb RH |
1789 | |
1790 | /* Despite the name, this field covers both VFP and Neon */ | |
1791 | u = cpu->isar.mvfr1; | |
1792 | u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); | |
1793 | cpu->isar.mvfr1 = u; | |
97a28b0e PM |
1794 | } |
1795 | ||
ea90db0a PM |
1796 | if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { |
1797 | uint32_t u; | |
1798 | ||
1799 | unset_feature(env, ARM_FEATURE_THUMB_DSP); | |
1800 | ||
1801 | u = cpu->isar.id_isar1; | |
1802 | u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); | |
1803 | cpu->isar.id_isar1 = u; | |
1804 | ||
1805 | u = cpu->isar.id_isar2; | |
1806 | u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); | |
1807 | u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); | |
1808 | cpu->isar.id_isar2 = u; | |
1809 | ||
1810 | u = cpu->isar.id_isar3; | |
1811 | u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); | |
1812 | u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); | |
1813 | cpu->isar.id_isar3 = u; | |
1814 | } | |
1815 | ||
581be094 | 1816 | /* Some features automatically imply others: */ |
81e69fb0 | 1817 | if (arm_feature(env, ARM_FEATURE_V8)) { |
5256df88 RH |
1818 | if (arm_feature(env, ARM_FEATURE_M)) { |
1819 | set_feature(env, ARM_FEATURE_V7); | |
1820 | } else { | |
1821 | set_feature(env, ARM_FEATURE_V7VE); | |
1822 | } | |
5110e683 | 1823 | } |
0f8d06f1 RH |
1824 | |
1825 | /* | |
1826 | * There exist AArch64 cpus without AArch32 support. When KVM | |
1827 | * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. | |
1828 | * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. | |
8f4821d7 PM |
1829 | * As a general principle, we also do not make ID register |
1830 | * consistency checks anywhere unless using TCG, because only | |
1831 | * for TCG would a consistency-check failure be a QEMU bug. | |
0f8d06f1 RH |
1832 | */ |
1833 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
1834 | no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); | |
1835 | } | |
1836 | ||
5110e683 AL |
1837 | if (arm_feature(env, ARM_FEATURE_V7VE)) { |
1838 | /* v7 Virtualization Extensions. In real hardware this implies | |
1839 | * EL2 and also the presence of the Security Extensions. | |
1840 | * For QEMU, for backwards-compatibility we implement some | |
1841 | * CPUs or CPU configs which have no actual EL2 or EL3 but do | |
1842 | * include the various other features that V7VE implies. | |
1843 | * Presence of EL2 itself is ARM_FEATURE_EL2, and of the | |
1844 | * Security Extensions is ARM_FEATURE_EL3. | |
1845 | */ | |
873b73c0 PM |
1846 | assert(!tcg_enabled() || no_aa32 || |
1847 | cpu_isar_feature(aa32_arm_div, cpu)); | |
81e69fb0 | 1848 | set_feature(env, ARM_FEATURE_LPAE); |
5110e683 | 1849 | set_feature(env, ARM_FEATURE_V7); |
81e69fb0 | 1850 | } |
581be094 PM |
1851 | if (arm_feature(env, ARM_FEATURE_V7)) { |
1852 | set_feature(env, ARM_FEATURE_VAPA); | |
1853 | set_feature(env, ARM_FEATURE_THUMB2); | |
81bdde9d | 1854 | set_feature(env, ARM_FEATURE_MPIDR); |
581be094 PM |
1855 | if (!arm_feature(env, ARM_FEATURE_M)) { |
1856 | set_feature(env, ARM_FEATURE_V6K); | |
1857 | } else { | |
1858 | set_feature(env, ARM_FEATURE_V6); | |
1859 | } | |
91db4642 CLG |
1860 | |
1861 | /* Always define VBAR for V7 CPUs even if it doesn't exist in | |
1862 | * non-EL3 configs. This is needed by some legacy boards. | |
1863 | */ | |
1864 | set_feature(env, ARM_FEATURE_VBAR); | |
581be094 PM |
1865 | } |
1866 | if (arm_feature(env, ARM_FEATURE_V6K)) { | |
1867 | set_feature(env, ARM_FEATURE_V6); | |
1868 | set_feature(env, ARM_FEATURE_MVFR); | |
1869 | } | |
1870 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
1871 | set_feature(env, ARM_FEATURE_V5); | |
1872 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
873b73c0 PM |
1873 | assert(!tcg_enabled() || no_aa32 || |
1874 | cpu_isar_feature(aa32_jazelle, cpu)); | |
581be094 PM |
1875 | set_feature(env, ARM_FEATURE_AUXCR); |
1876 | } | |
1877 | } | |
1878 | if (arm_feature(env, ARM_FEATURE_V5)) { | |
1879 | set_feature(env, ARM_FEATURE_V4T); | |
1880 | } | |
de9b05b8 | 1881 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
bdcc150d | 1882 | set_feature(env, ARM_FEATURE_V7MP); |
de9b05b8 | 1883 | } |
f318cec6 PM |
1884 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { |
1885 | set_feature(env, ARM_FEATURE_CBAR); | |
1886 | } | |
62b44f05 AR |
1887 | if (arm_feature(env, ARM_FEATURE_THUMB2) && |
1888 | !arm_feature(env, ARM_FEATURE_M)) { | |
1889 | set_feature(env, ARM_FEATURE_THUMB_DSP); | |
1890 | } | |
2ceb98c0 | 1891 | |
ea7ac69d PM |
1892 | /* |
1893 | * We rely on no XScale CPU having VFP so we can use the same bits in the | |
1894 | * TB flags field for VECSTRIDE and XSCALE_CPAR. | |
1895 | */ | |
7d63183f RH |
1896 | assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || |
1897 | !cpu_isar_feature(aa32_vfp_simd, cpu) || | |
1898 | !arm_feature(env, ARM_FEATURE_XSCALE)); | |
ea7ac69d | 1899 | |
e97da98f PM |
1900 | if (arm_feature(env, ARM_FEATURE_V7) && |
1901 | !arm_feature(env, ARM_FEATURE_M) && | |
452a0955 | 1902 | !arm_feature(env, ARM_FEATURE_PMSA)) { |
e97da98f PM |
1903 | /* v7VMSA drops support for the old ARMv5 tiny pages, so we |
1904 | * can use 4K pages. | |
1905 | */ | |
1906 | pagebits = 12; | |
1907 | } else { | |
1908 | /* For CPUs which might have tiny 1K pages, or which have an | |
1909 | * MPU and might have small region sizes, stick with 1K pages. | |
1910 | */ | |
1911 | pagebits = 10; | |
1912 | } | |
1913 | if (!set_preferred_target_page_bits(pagebits)) { | |
1914 | /* This can only ever happen for hotplugging a CPU, or if | |
1915 | * the board code incorrectly creates a CPU which it has | |
1916 | * promised via minimum_page_size that it will not. | |
1917 | */ | |
1918 | error_setg(errp, "This CPU requires a smaller page size than the " | |
1919 | "system is using"); | |
1920 | return; | |
1921 | } | |
1922 | ||
ce5b1bbf LV |
1923 | /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. |
1924 | * We don't support setting cluster ID ([16..23]) (known as Aff2 | |
1925 | * in later ARM ARM versions), or any of the higher affinity level fields, | |
1926 | * so these bits always RAZ. | |
1927 | */ | |
1928 | if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { | |
46de5913 IM |
1929 | cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, |
1930 | ARM_DEFAULT_CPUS_PER_CLUSTER); | |
ce5b1bbf LV |
1931 | } |
1932 | ||
68e0a40a AP |
1933 | if (cpu->reset_hivecs) { |
1934 | cpu->reset_sctlr |= (1 << 13); | |
1935 | } | |
1936 | ||
3a062d57 JB |
1937 | if (cpu->cfgend) { |
1938 | if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { | |
1939 | cpu->reset_sctlr |= SCTLR_EE; | |
1940 | } else { | |
1941 | cpu->reset_sctlr |= SCTLR_B; | |
1942 | } | |
1943 | } | |
1944 | ||
40188188 | 1945 | if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { |
51942aee GB |
1946 | /* If the has_el3 CPU property is disabled then we need to disable the |
1947 | * feature. | |
1948 | */ | |
1949 | unset_feature(env, ARM_FEATURE_EL3); | |
1950 | ||
b13c91c0 RH |
1951 | /* |
1952 | * Disable the security extension feature bits in the processor | |
1953 | * feature registers as well. | |
51942aee | 1954 | */ |
b13c91c0 | 1955 | cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); |
033a4f15 | 1956 | cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0); |
b13c91c0 RH |
1957 | cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, |
1958 | ID_AA64PFR0, EL3, 0); | |
51942aee GB |
1959 | } |
1960 | ||
c25bd18a PM |
1961 | if (!cpu->has_el2) { |
1962 | unset_feature(env, ARM_FEATURE_EL2); | |
1963 | } | |
1964 | ||
d6f02ce3 | 1965 | if (!cpu->has_pmu) { |
929e754d | 1966 | unset_feature(env, ARM_FEATURE_PMU); |
57a4a11b AL |
1967 | } |
1968 | if (arm_feature(env, ARM_FEATURE_PMU)) { | |
bf8d0969 | 1969 | pmu_init(cpu); |
57a4a11b AL |
1970 | |
1971 | if (!kvm_enabled()) { | |
1972 | arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); | |
1973 | arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); | |
1974 | } | |
4e7beb0c AL |
1975 | |
1976 | #ifndef CONFIG_USER_ONLY | |
1977 | cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, | |
1978 | cpu); | |
1979 | #endif | |
57a4a11b | 1980 | } else { |
2a609df8 PM |
1981 | cpu->isar.id_aa64dfr0 = |
1982 | FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); | |
a6179538 | 1983 | cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); |
57a4a11b AL |
1984 | cpu->pmceid0 = 0; |
1985 | cpu->pmceid1 = 0; | |
929e754d WH |
1986 | } |
1987 | ||
3c2f7bb3 | 1988 | if (!arm_feature(env, ARM_FEATURE_EL2)) { |
b13c91c0 RH |
1989 | /* |
1990 | * Disable the hypervisor feature bits in the processor feature | |
1991 | * registers if we don't have EL2. | |
3c2f7bb3 | 1992 | */ |
b13c91c0 RH |
1993 | cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, |
1994 | ID_AA64PFR0, EL2, 0); | |
1995 | cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, | |
1996 | ID_PFR1, VIRTUALIZATION, 0); | |
3c2f7bb3 PM |
1997 | } |
1998 | ||
6f4e1405 | 1999 | #ifndef CONFIG_USER_ONLY |
b320e21c | 2000 | if (!cpu->has_mte && cpu_isar_feature(aa64_mte, cpu)) { |
6f4e1405 | 2001 | /* |
b320e21c CH |
2002 | * Disable the MTE feature bits if we do not have the feature |
2003 | * setup by the machine. | |
6f4e1405 RH |
2004 | */ |
2005 | cpu->isar.id_aa64pfr1 = | |
2006 | FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); | |
2007 | } | |
2008 | #endif | |
2009 | ||
2daf518d PM |
2010 | if (tcg_enabled()) { |
2011 | /* | |
2012 | * Don't report the Statistical Profiling Extension in the ID | |
2013 | * registers, because TCG doesn't implement it yet (not even a | |
2014 | * minimal stub version) and guests will fall over when they | |
2015 | * try to access the non-existent system registers for it. | |
2016 | */ | |
2017 | cpu->isar.id_aa64dfr0 = | |
2018 | FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); | |
2019 | } | |
2020 | ||
f50cd314 PM |
2021 | /* MPU can be configured out of a PMSA CPU either by setting has-mpu |
2022 | * to false or by setting pmsav7-dregion to 0. | |
2023 | */ | |
761c4642 | 2024 | if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) { |
f50cd314 | 2025 | cpu->has_mpu = false; |
761c4642 TR |
2026 | cpu->pmsav7_dregion = 0; |
2027 | cpu->pmsav8r_hdregion = 0; | |
8f325f56 PC |
2028 | } |
2029 | ||
452a0955 | 2030 | if (arm_feature(env, ARM_FEATURE_PMSA) && |
3281af81 PC |
2031 | arm_feature(env, ARM_FEATURE_V7)) { |
2032 | uint32_t nr = cpu->pmsav7_dregion; | |
2033 | ||
2034 | if (nr > 0xff) { | |
9af9e0fe | 2035 | error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); |
3281af81 PC |
2036 | return; |
2037 | } | |
6cb0b013 PC |
2038 | |
2039 | if (nr) { | |
0e1a46bb PM |
2040 | if (arm_feature(env, ARM_FEATURE_V8)) { |
2041 | /* PMSAv8 */ | |
62c58ee0 PM |
2042 | env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); |
2043 | env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); | |
2044 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
2045 | env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); | |
2046 | env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); | |
2047 | } | |
0e1a46bb PM |
2048 | } else { |
2049 | env->pmsav7.drbar = g_new0(uint32_t, nr); | |
2050 | env->pmsav7.drsr = g_new0(uint32_t, nr); | |
2051 | env->pmsav7.dracr = g_new0(uint32_t, nr); | |
2052 | } | |
6cb0b013 | 2053 | } |
761c4642 TR |
2054 | |
2055 | if (cpu->pmsav8r_hdregion > 0xff) { | |
2056 | error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32, | |
2057 | cpu->pmsav8r_hdregion); | |
2058 | return; | |
2059 | } | |
2060 | ||
2061 | if (cpu->pmsav8r_hdregion) { | |
2062 | env->pmsav8.hprbar = g_new0(uint32_t, | |
2063 | cpu->pmsav8r_hdregion); | |
2064 | env->pmsav8.hprlar = g_new0(uint32_t, | |
2065 | cpu->pmsav8r_hdregion); | |
2066 | } | |
3281af81 PC |
2067 | } |
2068 | ||
9901c576 PM |
2069 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
2070 | uint32_t nr = cpu->sau_sregion; | |
2071 | ||
2072 | if (nr > 0xff) { | |
2073 | error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); | |
2074 | return; | |
2075 | } | |
2076 | ||
2077 | if (nr) { | |
2078 | env->sau.rbar = g_new0(uint32_t, nr); | |
2079 | env->sau.rlar = g_new0(uint32_t, nr); | |
2080 | } | |
2081 | } | |
2082 | ||
91db4642 CLG |
2083 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
2084 | set_feature(env, ARM_FEATURE_VBAR); | |
2085 | } | |
2086 | ||
2ceb98c0 | 2087 | register_cp_regs_for_features(cpu); |
14969266 AF |
2088 | arm_cpu_register_gdb_regs_for_features(cpu); |
2089 | ||
721fae12 PM |
2090 | init_cpreg_list(cpu); |
2091 | ||
9e273ef2 | 2092 | #ifndef CONFIG_USER_ONLY |
cc7d44c2 LX |
2093 | MachineState *ms = MACHINE(qdev_get_machine()); |
2094 | unsigned int smp_cpus = ms->smp.cpus; | |
8bce44a2 | 2095 | bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); |
cc7d44c2 | 2096 | |
8bce44a2 RH |
2097 | /* |
2098 | * We must set cs->num_ases to the final value before | |
2099 | * the first call to cpu_address_space_init. | |
2100 | */ | |
2101 | if (cpu->tag_memory != NULL) { | |
2102 | cs->num_ases = 3 + has_secure; | |
2103 | } else { | |
2104 | cs->num_ases = 1 + has_secure; | |
2105 | } | |
1d2091bc | 2106 | |
8bce44a2 | 2107 | if (has_secure) { |
9e273ef2 PM |
2108 | if (!cpu->secure_memory) { |
2109 | cpu->secure_memory = cs->memory; | |
2110 | } | |
80ceb07a PX |
2111 | cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", |
2112 | cpu->secure_memory); | |
9e273ef2 | 2113 | } |
8bce44a2 RH |
2114 | |
2115 | if (cpu->tag_memory != NULL) { | |
2116 | cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", | |
2117 | cpu->tag_memory); | |
2118 | if (has_secure) { | |
2119 | cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", | |
2120 | cpu->secure_tag_memory); | |
2121 | } | |
8bce44a2 RH |
2122 | } |
2123 | ||
80ceb07a | 2124 | cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); |
f9a69711 AF |
2125 | |
2126 | /* No core_count specified, default to smp_cpus. */ | |
2127 | if (cpu->core_count == -1) { | |
2128 | cpu->core_count = smp_cpus; | |
2129 | } | |
9e273ef2 PM |
2130 | #endif |
2131 | ||
a4157b80 RH |
2132 | if (tcg_enabled()) { |
2133 | int dcz_blocklen = 4 << cpu->dcz_blocksize; | |
2134 | ||
2135 | /* | |
2136 | * We only support DCZ blocklen that fits on one page. | |
2137 | * | |
2138 | * Architectually this is always true. However TARGET_PAGE_SIZE | |
2139 | * is variable and, for compatibility with -machine virt-2.7, | |
2140 | * is only 1KiB, as an artifact of legacy ARMv5 subpage support. | |
2141 | * But even then, while the largest architectural DCZ blocklen | |
2142 | * is 2KiB, no cpu actually uses such a large blocklen. | |
2143 | */ | |
2144 | assert(dcz_blocklen <= TARGET_PAGE_SIZE); | |
2145 | ||
2146 | /* | |
2147 | * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say | |
2148 | * both nibbles of each byte storing tag data may be written at once. | |
2149 | * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. | |
2150 | */ | |
2151 | if (cpu_isar_feature(aa64_mte, cpu)) { | |
2152 | assert(dcz_blocklen >= 2 * TAG_GRANULE); | |
2153 | } | |
2154 | } | |
2155 | ||
14a10fc3 | 2156 | qemu_init_vcpu(cs); |
00d0f7cb | 2157 | cpu_reset(cs); |
14969266 AF |
2158 | |
2159 | acc->parent_realize(dev, errp); | |
581be094 PM |
2160 | } |
2161 | ||
5900d6b2 AF |
2162 | static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) |
2163 | { | |
2164 | ObjectClass *oc; | |
51492fd1 | 2165 | char *typename; |
fb8d6c24 | 2166 | char **cpuname; |
a0032cc5 | 2167 | const char *cpunamestr; |
5900d6b2 | 2168 | |
fb8d6c24 | 2169 | cpuname = g_strsplit(cpu_model, ",", 1); |
a0032cc5 PM |
2170 | cpunamestr = cpuname[0]; |
2171 | #ifdef CONFIG_USER_ONLY | |
2172 | /* For backwards compatibility usermode emulation allows "-cpu any", | |
2173 | * which has the same semantics as "-cpu max". | |
2174 | */ | |
2175 | if (!strcmp(cpunamestr, "any")) { | |
2176 | cpunamestr = "max"; | |
2177 | } | |
2178 | #endif | |
2179 | typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); | |
51492fd1 | 2180 | oc = object_class_by_name(typename); |
fb8d6c24 | 2181 | g_strfreev(cpuname); |
51492fd1 | 2182 | g_free(typename); |
245fb54d AF |
2183 | if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || |
2184 | object_class_is_abstract(oc)) { | |
5900d6b2 AF |
2185 | return NULL; |
2186 | } | |
2187 | return oc; | |
2188 | } | |
2189 | ||
5de16430 | 2190 | static Property arm_cpu_properties[] = { |
e544f800 | 2191 | DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), |
ce5b1bbf LV |
2192 | DEFINE_PROP_UINT64("mp-affinity", ARMCPU, |
2193 | mp_affinity, ARM64_AFFINITY_INVALID), | |
15f8b142 | 2194 | DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), |
f9a69711 | 2195 | DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), |
5de16430 PM |
2196 | DEFINE_PROP_END_OF_LIST() |
2197 | }; | |
2198 | ||
b3820e6c DH |
2199 | static gchar *arm_gdb_arch_name(CPUState *cs) |
2200 | { | |
2201 | ARMCPU *cpu = ARM_CPU(cs); | |
2202 | CPUARMState *env = &cpu->env; | |
2203 | ||
2204 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
2205 | return g_strdup("iwmmxt"); | |
2206 | } | |
2207 | return g_strdup("arm"); | |
2208 | } | |
2209 | ||
8b80bd28 PMD |
2210 | #ifndef CONFIG_USER_ONLY |
2211 | #include "hw/core/sysemu-cpu-ops.h" | |
2212 | ||
2213 | static const struct SysemuCPUOps arm_sysemu_ops = { | |
08928c6d | 2214 | .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, |
faf39e82 | 2215 | .asidx_from_attrs = arm_asidx_from_attrs, |
715e3c1a PMD |
2216 | .write_elf32_note = arm_cpu_write_elf32_note, |
2217 | .write_elf64_note = arm_cpu_write_elf64_note, | |
da383e02 | 2218 | .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, |
feece4d0 | 2219 | .legacy_vmsd = &vmstate_arm_cpu, |
8b80bd28 PMD |
2220 | }; |
2221 | #endif | |
2222 | ||
78271684 | 2223 | #ifdef CONFIG_TCG |
11906557 | 2224 | static const struct TCGCPUOps arm_tcg_ops = { |
78271684 CF |
2225 | .initialize = arm_translate_init, |
2226 | .synchronize_from_tb = arm_cpu_synchronize_from_tb, | |
78271684 | 2227 | .debug_excp_handler = arm_debug_excp_handler, |
56c6c98d | 2228 | .restore_state_to_opc = arm_restore_state_to_opc, |
78271684 | 2229 | |
9b12b6b4 RH |
2230 | #ifdef CONFIG_USER_ONLY |
2231 | .record_sigsegv = arm_cpu_record_sigsegv, | |
39a099ca | 2232 | .record_sigbus = arm_cpu_record_sigbus, |
9b12b6b4 RH |
2233 | #else |
2234 | .tlb_fill = arm_cpu_tlb_fill, | |
083afd18 | 2235 | .cpu_exec_interrupt = arm_cpu_exec_interrupt, |
78271684 CF |
2236 | .do_interrupt = arm_cpu_do_interrupt, |
2237 | .do_transaction_failed = arm_cpu_do_transaction_failed, | |
2238 | .do_unaligned_access = arm_cpu_do_unaligned_access, | |
2239 | .adjust_watchpoint_address = arm_adjust_watchpoint_address, | |
2240 | .debug_check_watchpoint = arm_debug_check_watchpoint, | |
b00d86bc | 2241 | .debug_check_breakpoint = arm_debug_check_breakpoint, |
78271684 CF |
2242 | #endif /* !CONFIG_USER_ONLY */ |
2243 | }; | |
2244 | #endif /* CONFIG_TCG */ | |
2245 | ||
dec9c2d4 AF |
2246 | static void arm_cpu_class_init(ObjectClass *oc, void *data) |
2247 | { | |
2248 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
2249 | CPUClass *cc = CPU_CLASS(acc); | |
14969266 | 2250 | DeviceClass *dc = DEVICE_CLASS(oc); |
9130cade | 2251 | ResettableClass *rc = RESETTABLE_CLASS(oc); |
14969266 | 2252 | |
bf853881 PMD |
2253 | device_class_set_parent_realize(dc, arm_cpu_realizefn, |
2254 | &acc->parent_realize); | |
dec9c2d4 | 2255 | |
4f67d30b | 2256 | device_class_set_props(dc, arm_cpu_properties); |
9130cade PM |
2257 | |
2258 | resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, | |
2259 | &acc->parent_phases); | |
5900d6b2 AF |
2260 | |
2261 | cc->class_by_name = arm_cpu_class_by_name; | |
8c2e1b00 | 2262 | cc->has_work = arm_cpu_has_work; |
878096ee | 2263 | cc->dump_state = arm_cpu_dump_state; |
f45748f1 | 2264 | cc->set_pc = arm_cpu_set_pc; |
e4fdf9df | 2265 | cc->get_pc = arm_cpu_get_pc; |
5b50e790 AF |
2266 | cc->gdb_read_register = arm_cpu_gdb_read_register; |
2267 | cc->gdb_write_register = arm_cpu_gdb_write_register; | |
7350d553 | 2268 | #ifndef CONFIG_USER_ONLY |
8b80bd28 | 2269 | cc->sysemu_ops = &arm_sysemu_ops; |
00b941e5 | 2270 | #endif |
a0e372f0 | 2271 | cc->gdb_num_core_regs = 26; |
5b24c641 | 2272 | cc->gdb_core_xml_file = "arm-core.xml"; |
b3820e6c | 2273 | cc->gdb_arch_name = arm_gdb_arch_name; |
200bf5b7 | 2274 | cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; |
2472b6c0 | 2275 | cc->gdb_stop_before_watchpoint = true; |
48440620 | 2276 | cc->disas_set_info = arm_disas_set_info; |
78271684 | 2277 | |
74d7fc7f | 2278 | #ifdef CONFIG_TCG |
78271684 | 2279 | cc->tcg_ops = &arm_tcg_ops; |
cbc183d2 | 2280 | #endif /* CONFIG_TCG */ |
dec9c2d4 AF |
2281 | } |
2282 | ||
51e5ef45 MAL |
2283 | static void arm_cpu_instance_init(Object *obj) |
2284 | { | |
2285 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); | |
2286 | ||
2287 | acc->info->initfn(obj); | |
2288 | arm_cpu_post_init(obj); | |
2289 | } | |
2290 | ||
2291 | static void cpu_register_class_init(ObjectClass *oc, void *data) | |
2292 | { | |
2293 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
2294 | ||
2295 | acc->info = data; | |
2296 | } | |
2297 | ||
37bcf244 | 2298 | void arm_cpu_register(const ARMCPUInfo *info) |
777dc784 PM |
2299 | { |
2300 | TypeInfo type_info = { | |
777dc784 PM |
2301 | .parent = TYPE_ARM_CPU, |
2302 | .instance_size = sizeof(ARMCPU), | |
d03087bd | 2303 | .instance_align = __alignof__(ARMCPU), |
51e5ef45 | 2304 | .instance_init = arm_cpu_instance_init, |
777dc784 | 2305 | .class_size = sizeof(ARMCPUClass), |
51e5ef45 MAL |
2306 | .class_init = info->class_init ?: cpu_register_class_init, |
2307 | .class_data = (void *)info, | |
777dc784 PM |
2308 | }; |
2309 | ||
51492fd1 | 2310 | type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); |
918fd083 | 2311 | type_register(&type_info); |
51492fd1 | 2312 | g_free((void *)type_info.name); |
777dc784 PM |
2313 | } |
2314 | ||
dec9c2d4 AF |
2315 | static const TypeInfo arm_cpu_type_info = { |
2316 | .name = TYPE_ARM_CPU, | |
2317 | .parent = TYPE_CPU, | |
2318 | .instance_size = sizeof(ARMCPU), | |
d03087bd | 2319 | .instance_align = __alignof__(ARMCPU), |
777dc784 | 2320 | .instance_init = arm_cpu_initfn, |
4b6a83fb | 2321 | .instance_finalize = arm_cpu_finalizefn, |
777dc784 | 2322 | .abstract = true, |
dec9c2d4 AF |
2323 | .class_size = sizeof(ARMCPUClass), |
2324 | .class_init = arm_cpu_class_init, | |
2325 | }; | |
2326 | ||
2327 | static void arm_cpu_register_types(void) | |
2328 | { | |
2329 | type_register_static(&arm_cpu_type_info); | |
2330 | } | |
2331 | ||
2332 | type_init(arm_cpu_register_types) |