]>
Commit | Line | Data |
---|---|---|
dec9c2d4 AF |
1 | /* |
2 | * QEMU ARM CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
74c21bd0 | 21 | #include "qemu/osdep.h" |
86480615 | 22 | #include "qemu/qemu-print.h" |
b8012ecf | 23 | #include "qemu/timer.h" |
8cc2246c | 24 | #include "qemu/log.h" |
a8d25326 | 25 | #include "qemu-common.h" |
181962fd | 26 | #include "target/arm/idau.h" |
0b8fa32f | 27 | #include "qemu/module.h" |
da34e65c | 28 | #include "qapi/error.h" |
f9f62e4c | 29 | #include "qapi/visitor.h" |
778c3a06 | 30 | #include "cpu.h" |
78271684 CF |
31 | #ifdef CONFIG_TCG |
32 | #include "hw/core/tcg-cpu-ops.h" | |
33 | #endif /* CONFIG_TCG */ | |
ccd38087 | 34 | #include "internals.h" |
63c91552 | 35 | #include "exec/exec-all.h" |
5de16430 | 36 | #include "hw/qdev-properties.h" |
3c30dd5a PM |
37 | #if !defined(CONFIG_USER_ONLY) |
38 | #include "hw/loader.h" | |
cc7d44c2 | 39 | #include "hw/boards.h" |
3c30dd5a | 40 | #endif |
14a48c1d | 41 | #include "sysemu/tcg.h" |
b3946626 | 42 | #include "sysemu/hw_accel.h" |
50a2c6e5 | 43 | #include "kvm_arm.h" |
110f6c70 | 44 | #include "disas/capstone.h" |
24f91e81 | 45 | #include "fpu/softfloat.h" |
dec9c2d4 | 46 | |
f45748f1 AF |
47 | static void arm_cpu_set_pc(CPUState *cs, vaddr value) |
48 | { | |
49 | ARMCPU *cpu = ARM_CPU(cs); | |
42f6ed91 JS |
50 | CPUARMState *env = &cpu->env; |
51 | ||
52 | if (is_a64(env)) { | |
53 | env->pc = value; | |
54 | env->thumb = 0; | |
55 | } else { | |
56 | env->regs[15] = value & ~1; | |
57 | env->thumb = value & 1; | |
58 | } | |
59 | } | |
f45748f1 | 60 | |
ec62595b | 61 | #ifdef CONFIG_TCG |
78271684 CF |
62 | void arm_cpu_synchronize_from_tb(CPUState *cs, |
63 | const TranslationBlock *tb) | |
42f6ed91 JS |
64 | { |
65 | ARMCPU *cpu = ARM_CPU(cs); | |
66 | CPUARMState *env = &cpu->env; | |
67 | ||
68 | /* | |
69 | * It's OK to look at env for the current mode here, because it's | |
70 | * never possible for an AArch64 TB to chain to an AArch32 TB. | |
71 | */ | |
72 | if (is_a64(env)) { | |
73 | env->pc = tb->pc; | |
74 | } else { | |
75 | env->regs[15] = tb->pc; | |
76 | } | |
f45748f1 | 77 | } |
ec62595b | 78 | #endif /* CONFIG_TCG */ |
f45748f1 | 79 | |
8c2e1b00 AF |
80 | static bool arm_cpu_has_work(CPUState *cs) |
81 | { | |
543486db RH |
82 | ARMCPU *cpu = ARM_CPU(cs); |
83 | ||
062ba099 | 84 | return (cpu->power_state != PSCI_OFF) |
543486db | 85 | && cs->interrupt_request & |
136e67e9 EI |
86 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD |
87 | | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | |
88 | | CPU_INTERRUPT_EXITTB); | |
8c2e1b00 AF |
89 | } |
90 | ||
b5c53d1b AL |
91 | void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
92 | void *opaque) | |
93 | { | |
94 | ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); | |
95 | ||
96 | entry->hook = hook; | |
97 | entry->opaque = opaque; | |
98 | ||
99 | QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); | |
100 | } | |
101 | ||
08267487 | 102 | void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
bd7d00fc PM |
103 | void *opaque) |
104 | { | |
08267487 AL |
105 | ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); |
106 | ||
107 | entry->hook = hook; | |
108 | entry->opaque = opaque; | |
109 | ||
110 | QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); | |
bd7d00fc PM |
111 | } |
112 | ||
4b6a83fb PM |
113 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
114 | { | |
115 | /* Reset a single ARMCPRegInfo register */ | |
116 | ARMCPRegInfo *ri = value; | |
117 | ARMCPU *cpu = opaque; | |
118 | ||
b061a82b | 119 | if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { |
4b6a83fb PM |
120 | return; |
121 | } | |
122 | ||
123 | if (ri->resetfn) { | |
124 | ri->resetfn(&cpu->env, ri); | |
125 | return; | |
126 | } | |
127 | ||
128 | /* A zero offset is never possible as it would be regs[0] | |
129 | * so we use it to indicate that reset is being handled elsewhere. | |
130 | * This is basically only used for fields in non-core coprocessors | |
131 | * (like the pxa2xx ones). | |
132 | */ | |
133 | if (!ri->fieldoffset) { | |
134 | return; | |
135 | } | |
136 | ||
67ed771d | 137 | if (cpreg_field_is_64bit(ri)) { |
4b6a83fb PM |
138 | CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; |
139 | } else { | |
140 | CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; | |
141 | } | |
142 | } | |
143 | ||
49a66191 PM |
144 | static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) |
145 | { | |
146 | /* Purely an assertion check: we've already done reset once, | |
147 | * so now check that running the reset for the cpreg doesn't | |
148 | * change its value. This traps bugs where two different cpregs | |
149 | * both try to reset the same state field but to different values. | |
150 | */ | |
151 | ARMCPRegInfo *ri = value; | |
152 | ARMCPU *cpu = opaque; | |
153 | uint64_t oldvalue, newvalue; | |
154 | ||
155 | if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { | |
156 | return; | |
157 | } | |
158 | ||
159 | oldvalue = read_raw_cp_reg(&cpu->env, ri); | |
160 | cp_reg_reset(key, value, opaque); | |
161 | newvalue = read_raw_cp_reg(&cpu->env, ri); | |
162 | assert(oldvalue == newvalue); | |
163 | } | |
164 | ||
781c67ca | 165 | static void arm_cpu_reset(DeviceState *dev) |
dec9c2d4 | 166 | { |
781c67ca | 167 | CPUState *s = CPU(dev); |
dec9c2d4 AF |
168 | ARMCPU *cpu = ARM_CPU(s); |
169 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); | |
3c30dd5a | 170 | CPUARMState *env = &cpu->env; |
3c30dd5a | 171 | |
781c67ca | 172 | acc->parent_reset(dev); |
dec9c2d4 | 173 | |
1f5c00cf AB |
174 | memset(env, 0, offsetof(CPUARMState, end_reset_fields)); |
175 | ||
4b6a83fb | 176 | g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
49a66191 PM |
177 | g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); |
178 | ||
3c30dd5a | 179 | env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
47576b94 RH |
180 | env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; |
181 | env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; | |
182 | env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; | |
3c30dd5a | 183 | |
c1b70158 | 184 | cpu->power_state = s->start_powered_off ? PSCI_OFF : PSCI_ON; |
543486db | 185 | |
3c30dd5a PM |
186 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { |
187 | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; | |
188 | } | |
189 | ||
3926cc84 AG |
190 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
191 | /* 64 bit CPUs always start in 64 bit mode */ | |
192 | env->aarch64 = 1; | |
d356312f PM |
193 | #if defined(CONFIG_USER_ONLY) |
194 | env->pstate = PSTATE_MODE_EL0t; | |
14e5f106 | 195 | /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ |
137feaa9 | 196 | env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; |
276c6e81 RH |
197 | /* Enable all PAC keys. */ |
198 | env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | | |
199 | SCTLR_EnDA | SCTLR_EnDB); | |
8c6afa6a | 200 | /* and to the FP/Neon instructions */ |
7ebd5f2e | 201 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); |
802ac0e1 RH |
202 | /* and to the SVE instructions */ |
203 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); | |
7b6a2198 AB |
204 | /* with reasonable vector length */ |
205 | if (cpu_isar_feature(aa64_sve, cpu)) { | |
b3d52804 RH |
206 | env->vfp.zcr_el[1] = |
207 | aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); | |
7b6a2198 | 208 | } |
f6a148fe | 209 | /* |
691f1ffd | 210 | * Enable 48-bit address space (TODO: take reserved_va into account). |
16c84978 RH |
211 | * Enable TBI0 but not TBI1. |
212 | * Note that this must match useronly_clean_ptr. | |
f6a148fe | 213 | */ |
691f1ffd | 214 | env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37); |
e3232864 RH |
215 | |
216 | /* Enable MTE */ | |
217 | if (cpu_isar_feature(aa64_mte, cpu)) { | |
218 | /* Enable tag access, but leave TCF0 as No Effect (0). */ | |
219 | env->cp15.sctlr_el[1] |= SCTLR_ATA0; | |
220 | /* | |
221 | * Exclude all tags, so that tag 0 is always used. | |
222 | * This corresponds to Linux current->thread.gcr_incl = 0. | |
223 | * | |
224 | * Set RRND, so that helper_irg() will generate a seed later. | |
225 | * Here in cpu_reset(), the crypto subsystem has not yet been | |
226 | * initialized. | |
227 | */ | |
228 | env->cp15.gcr_el1 = 0x1ffff; | |
229 | } | |
d356312f | 230 | #else |
5097227c GB |
231 | /* Reset into the highest available EL */ |
232 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
233 | env->pstate = PSTATE_MODE_EL3h; | |
234 | } else if (arm_feature(env, ARM_FEATURE_EL2)) { | |
235 | env->pstate = PSTATE_MODE_EL2h; | |
236 | } else { | |
237 | env->pstate = PSTATE_MODE_EL1h; | |
238 | } | |
3933443e | 239 | env->pc = cpu->rvbar; |
8c6afa6a PM |
240 | #endif |
241 | } else { | |
242 | #if defined(CONFIG_USER_ONLY) | |
243 | /* Userspace expects access to cp10 and cp11 for FP/Neon */ | |
7ebd5f2e | 244 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); |
d356312f | 245 | #endif |
3926cc84 AG |
246 | } |
247 | ||
3c30dd5a PM |
248 | #if defined(CONFIG_USER_ONLY) |
249 | env->uncached_cpsr = ARM_CPU_MODE_USR; | |
250 | /* For user mode we must enable access to coprocessors */ | |
251 | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; | |
252 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
253 | env->cp15.c15_cpar = 3; | |
254 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
255 | env->cp15.c15_cpar = 1; | |
256 | } | |
257 | #else | |
060a65df PM |
258 | |
259 | /* | |
260 | * If the highest available EL is EL2, AArch32 will start in Hyp | |
261 | * mode; otherwise it starts in SVC. Note that if we start in | |
262 | * AArch64 then these values in the uncached_cpsr will be ignored. | |
263 | */ | |
264 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
265 | !arm_feature(env, ARM_FEATURE_EL3)) { | |
266 | env->uncached_cpsr = ARM_CPU_MODE_HYP; | |
267 | } else { | |
268 | env->uncached_cpsr = ARM_CPU_MODE_SVC; | |
269 | } | |
4cc35614 | 270 | env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; |
1426f244 PM |
271 | |
272 | /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently | |
273 | * executing as AArch32 then check if highvecs are enabled and | |
274 | * adjust the PC accordingly. | |
275 | */ | |
276 | if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { | |
277 | env->regs[15] = 0xFFFF0000; | |
278 | } | |
279 | ||
280 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; | |
b62ceeaf | 281 | #endif |
dc7abe4d | 282 | |
531c60a9 | 283 | if (arm_feature(env, ARM_FEATURE_M)) { |
b62ceeaf | 284 | #ifndef CONFIG_USER_ONLY |
6e3cf5df MG |
285 | uint32_t initial_msp; /* Loaded from 0x0 */ |
286 | uint32_t initial_pc; /* Loaded from 0x4 */ | |
3c30dd5a | 287 | uint8_t *rom; |
38e2a77c | 288 | uint32_t vecbase; |
b62ceeaf | 289 | #endif |
6e3cf5df | 290 | |
8128c8e8 PM |
291 | if (cpu_isar_feature(aa32_lob, cpu)) { |
292 | /* | |
293 | * LTPSIZE is constant 4 if MVE not implemented, and resets | |
294 | * to an UNKNOWN value if MVE is implemented. We choose to | |
295 | * always reset to 4. | |
296 | */ | |
297 | env->v7m.ltpsize = 4; | |
99c7834f PM |
298 | /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ |
299 | env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; | |
300 | env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; | |
8128c8e8 PM |
301 | } |
302 | ||
1e577cc7 PM |
303 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
304 | env->v7m.secure = true; | |
3b2e9344 PM |
305 | } else { |
306 | /* This bit resets to 0 if security is supported, but 1 if | |
307 | * it is not. The bit is not present in v7M, but we set it | |
308 | * here so we can avoid having to make checks on it conditional | |
309 | * on ARM_FEATURE_V8 (we don't let the guest see the bit). | |
310 | */ | |
311 | env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; | |
02ac2f7f PM |
312 | /* |
313 | * Set NSACR to indicate "NS access permitted to everything"; | |
314 | * this avoids having to have all the tests of it being | |
315 | * conditional on ARM_FEATURE_M_SECURITY. Note also that from | |
316 | * v8.1M the guest-visible value of NSACR in a CPU without the | |
317 | * Security Extension is 0xcff. | |
318 | */ | |
319 | env->v7m.nsacr = 0xcff; | |
1e577cc7 PM |
320 | } |
321 | ||
9d40cd8a | 322 | /* In v7M the reset value of this bit is IMPDEF, but ARM recommends |
2c4da50d | 323 | * that it resets to 1, so QEMU always does that rather than making |
9d40cd8a | 324 | * it dependent on CPU model. In v8M it is RES1. |
2c4da50d | 325 | */ |
9d40cd8a PM |
326 | env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; |
327 | env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; | |
328 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
329 | /* in v8M the NONBASETHRDENA bit [0] is RES1 */ | |
330 | env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; | |
331 | env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; | |
332 | } | |
22ab3460 JS |
333 | if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { |
334 | env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; | |
335 | env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; | |
336 | } | |
2c4da50d | 337 | |
7fbc6a40 | 338 | if (cpu_isar_feature(aa32_vfp_simd, cpu)) { |
d33abe82 PM |
339 | env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; |
340 | env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | | |
341 | R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; | |
342 | } | |
b62ceeaf PM |
343 | |
344 | #ifndef CONFIG_USER_ONLY | |
056f43df PM |
345 | /* Unlike A/R profile, M profile defines the reset LR value */ |
346 | env->regs[14] = 0xffffffff; | |
347 | ||
38e2a77c | 348 | env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; |
7cda2149 | 349 | env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; |
38e2a77c PM |
350 | |
351 | /* Load the initial SP and PC from offset 0 and 4 in the vector table */ | |
352 | vecbase = env->v7m.vecbase[env->v7m.secure]; | |
75ce72b7 | 353 | rom = rom_ptr_for_as(s->as, vecbase, 8); |
3c30dd5a | 354 | if (rom) { |
6e3cf5df MG |
355 | /* Address zero is covered by ROM which hasn't yet been |
356 | * copied into physical memory. | |
357 | */ | |
358 | initial_msp = ldl_p(rom); | |
359 | initial_pc = ldl_p(rom + 4); | |
360 | } else { | |
361 | /* Address zero not covered by a ROM blob, or the ROM blob | |
362 | * is in non-modifiable memory and this is a second reset after | |
363 | * it got copied into memory. In the latter case, rom_ptr | |
364 | * will return a NULL pointer and we should use ldl_phys instead. | |
365 | */ | |
38e2a77c PM |
366 | initial_msp = ldl_phys(s->as, vecbase); |
367 | initial_pc = ldl_phys(s->as, vecbase + 4); | |
3c30dd5a | 368 | } |
6e3cf5df | 369 | |
8cc2246c PM |
370 | qemu_log_mask(CPU_LOG_INT, |
371 | "Loaded reset SP 0x%x PC 0x%x from vector table\n", | |
372 | initial_msp, initial_pc); | |
373 | ||
6e3cf5df MG |
374 | env->regs[13] = initial_msp & 0xFFFFFFFC; |
375 | env->regs[15] = initial_pc & ~1; | |
376 | env->thumb = initial_pc & 1; | |
b62ceeaf PM |
377 | #else |
378 | /* | |
379 | * For user mode we run non-secure and with access to the FPU. | |
380 | * The FPU context is active (ie does not need further setup) | |
381 | * and is owned by non-secure. | |
382 | */ | |
383 | env->v7m.secure = false; | |
384 | env->v7m.nsacr = 0xcff; | |
385 | env->v7m.cpacr[M_REG_NS] = 0xf0ffff; | |
386 | env->v7m.fpccr[M_REG_S] &= | |
387 | ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK); | |
388 | env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; | |
389 | #endif | |
3c30dd5a | 390 | } |
387f9806 | 391 | |
dc3c4c14 PM |
392 | /* M profile requires that reset clears the exclusive monitor; |
393 | * A profile does not, but clearing it makes more sense than having it | |
394 | * set with an exclusive access on address zero. | |
395 | */ | |
396 | arm_clear_exclusive(env); | |
397 | ||
0e1a46bb | 398 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
69ceea64 | 399 | if (cpu->pmsav7_dregion > 0) { |
0e1a46bb | 400 | if (arm_feature(env, ARM_FEATURE_V8)) { |
62c58ee0 PM |
401 | memset(env->pmsav8.rbar[M_REG_NS], 0, |
402 | sizeof(*env->pmsav8.rbar[M_REG_NS]) | |
403 | * cpu->pmsav7_dregion); | |
404 | memset(env->pmsav8.rlar[M_REG_NS], 0, | |
405 | sizeof(*env->pmsav8.rlar[M_REG_NS]) | |
406 | * cpu->pmsav7_dregion); | |
407 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
408 | memset(env->pmsav8.rbar[M_REG_S], 0, | |
409 | sizeof(*env->pmsav8.rbar[M_REG_S]) | |
410 | * cpu->pmsav7_dregion); | |
411 | memset(env->pmsav8.rlar[M_REG_S], 0, | |
412 | sizeof(*env->pmsav8.rlar[M_REG_S]) | |
413 | * cpu->pmsav7_dregion); | |
414 | } | |
0e1a46bb PM |
415 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
416 | memset(env->pmsav7.drbar, 0, | |
417 | sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); | |
418 | memset(env->pmsav7.drsr, 0, | |
419 | sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); | |
420 | memset(env->pmsav7.dracr, 0, | |
421 | sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); | |
422 | } | |
69ceea64 | 423 | } |
1bc04a88 PM |
424 | env->pmsav7.rnr[M_REG_NS] = 0; |
425 | env->pmsav7.rnr[M_REG_S] = 0; | |
4125e6fe PM |
426 | env->pmsav8.mair0[M_REG_NS] = 0; |
427 | env->pmsav8.mair0[M_REG_S] = 0; | |
428 | env->pmsav8.mair1[M_REG_NS] = 0; | |
429 | env->pmsav8.mair1[M_REG_S] = 0; | |
69ceea64 PM |
430 | } |
431 | ||
9901c576 PM |
432 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
433 | if (cpu->sau_sregion > 0) { | |
434 | memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); | |
435 | memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); | |
436 | } | |
437 | env->sau.rnr = 0; | |
438 | /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what | |
439 | * the Cortex-M33 does. | |
440 | */ | |
441 | env->sau.ctrl = 0; | |
442 | } | |
443 | ||
3c30dd5a PM |
444 | set_flush_to_zero(1, &env->vfp.standard_fp_status); |
445 | set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); | |
446 | set_default_nan_mode(1, &env->vfp.standard_fp_status); | |
aaae563b | 447 | set_default_nan_mode(1, &env->vfp.standard_fp_status_f16); |
3c30dd5a PM |
448 | set_float_detect_tininess(float_tininess_before_rounding, |
449 | &env->vfp.fp_status); | |
450 | set_float_detect_tininess(float_tininess_before_rounding, | |
451 | &env->vfp.standard_fp_status); | |
bcc531f0 PM |
452 | set_float_detect_tininess(float_tininess_before_rounding, |
453 | &env->vfp.fp_status_f16); | |
aaae563b PM |
454 | set_float_detect_tininess(float_tininess_before_rounding, |
455 | &env->vfp.standard_fp_status_f16); | |
50a2c6e5 PB |
456 | #ifndef CONFIG_USER_ONLY |
457 | if (kvm_enabled()) { | |
458 | kvm_arm_reset_vcpu(cpu); | |
459 | } | |
460 | #endif | |
9ee98ce8 | 461 | |
46747d15 | 462 | hw_breakpoint_update_all(cpu); |
9ee98ce8 | 463 | hw_watchpoint_update_all(cpu); |
a8a79c7a | 464 | arm_rebuild_hflags(env); |
dec9c2d4 AF |
465 | } |
466 | ||
083afd18 PMD |
467 | #ifndef CONFIG_USER_ONLY |
468 | ||
310cedf3 | 469 | static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, |
be879556 RH |
470 | unsigned int target_el, |
471 | unsigned int cur_el, bool secure, | |
472 | uint64_t hcr_el2) | |
310cedf3 RH |
473 | { |
474 | CPUARMState *env = cs->env_ptr; | |
310cedf3 | 475 | bool pstate_unmasked; |
16e07f78 | 476 | bool unmasked = false; |
310cedf3 RH |
477 | |
478 | /* | |
479 | * Don't take exceptions if they target a lower EL. | |
480 | * This check should catch any exceptions that would not be taken | |
481 | * but left pending. | |
482 | */ | |
483 | if (cur_el > target_el) { | |
484 | return false; | |
485 | } | |
486 | ||
310cedf3 RH |
487 | switch (excp_idx) { |
488 | case EXCP_FIQ: | |
489 | pstate_unmasked = !(env->daif & PSTATE_F); | |
490 | break; | |
491 | ||
492 | case EXCP_IRQ: | |
493 | pstate_unmasked = !(env->daif & PSTATE_I); | |
494 | break; | |
495 | ||
496 | case EXCP_VFIQ: | |
cc974d5c RDC |
497 | if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { |
498 | /* VFIQs are only taken when hypervized. */ | |
310cedf3 RH |
499 | return false; |
500 | } | |
501 | return !(env->daif & PSTATE_F); | |
502 | case EXCP_VIRQ: | |
cc974d5c RDC |
503 | if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { |
504 | /* VIRQs are only taken when hypervized. */ | |
310cedf3 RH |
505 | return false; |
506 | } | |
507 | return !(env->daif & PSTATE_I); | |
508 | default: | |
509 | g_assert_not_reached(); | |
510 | } | |
511 | ||
512 | /* | |
513 | * Use the target EL, current execution state and SCR/HCR settings to | |
514 | * determine whether the corresponding CPSR bit is used to mask the | |
515 | * interrupt. | |
516 | */ | |
517 | if ((target_el > cur_el) && (target_el != 1)) { | |
518 | /* Exceptions targeting a higher EL may not be maskable */ | |
519 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
520 | /* | |
521 | * 64-bit masking rules are simple: exceptions to EL3 | |
522 | * can't be masked, and exceptions to EL2 can only be | |
523 | * masked from Secure state. The HCR and SCR settings | |
524 | * don't affect the masking logic, only the interrupt routing. | |
525 | */ | |
926c1b97 | 526 | if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) { |
16e07f78 | 527 | unmasked = true; |
310cedf3 RH |
528 | } |
529 | } else { | |
530 | /* | |
531 | * The old 32-bit-only environment has a more complicated | |
532 | * masking setup. HCR and SCR bits not only affect interrupt | |
533 | * routing but also change the behaviour of masking. | |
534 | */ | |
535 | bool hcr, scr; | |
536 | ||
537 | switch (excp_idx) { | |
538 | case EXCP_FIQ: | |
539 | /* | |
540 | * If FIQs are routed to EL3 or EL2 then there are cases where | |
541 | * we override the CPSR.F in determining if the exception is | |
542 | * masked or not. If neither of these are set then we fall back | |
543 | * to the CPSR.F setting otherwise we further assess the state | |
544 | * below. | |
545 | */ | |
546 | hcr = hcr_el2 & HCR_FMO; | |
547 | scr = (env->cp15.scr_el3 & SCR_FIQ); | |
548 | ||
549 | /* | |
550 | * When EL3 is 32-bit, the SCR.FW bit controls whether the | |
551 | * CPSR.F bit masks FIQ interrupts when taken in non-secure | |
552 | * state. If SCR.FW is set then FIQs can be masked by CPSR.F | |
553 | * when non-secure but only when FIQs are only routed to EL3. | |
554 | */ | |
555 | scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); | |
556 | break; | |
557 | case EXCP_IRQ: | |
558 | /* | |
559 | * When EL3 execution state is 32-bit, if HCR.IMO is set then | |
560 | * we may override the CPSR.I masking when in non-secure state. | |
561 | * The SCR.IRQ setting has already been taken into consideration | |
562 | * when setting the target EL, so it does not have a further | |
563 | * affect here. | |
564 | */ | |
565 | hcr = hcr_el2 & HCR_IMO; | |
566 | scr = false; | |
567 | break; | |
568 | default: | |
569 | g_assert_not_reached(); | |
570 | } | |
571 | ||
572 | if ((scr || hcr) && !secure) { | |
16e07f78 | 573 | unmasked = true; |
310cedf3 RH |
574 | } |
575 | } | |
576 | } | |
577 | ||
578 | /* | |
579 | * The PSTATE bits only mask the interrupt if we have not overriden the | |
580 | * ability above. | |
581 | */ | |
582 | return unmasked || pstate_unmasked; | |
583 | } | |
584 | ||
083afd18 | 585 | static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
e8925712 RH |
586 | { |
587 | CPUClass *cc = CPU_GET_CLASS(cs); | |
012a906b GB |
588 | CPUARMState *env = cs->env_ptr; |
589 | uint32_t cur_el = arm_current_el(env); | |
590 | bool secure = arm_is_secure(env); | |
be879556 | 591 | uint64_t hcr_el2 = arm_hcr_el2_eff(env); |
012a906b GB |
592 | uint32_t target_el; |
593 | uint32_t excp_idx; | |
d63d0ec5 RH |
594 | |
595 | /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ | |
e8925712 | 596 | |
012a906b GB |
597 | if (interrupt_request & CPU_INTERRUPT_FIQ) { |
598 | excp_idx = EXCP_FIQ; | |
599 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
be879556 RH |
600 | if (arm_excp_unmasked(cs, excp_idx, target_el, |
601 | cur_el, secure, hcr_el2)) { | |
d63d0ec5 | 602 | goto found; |
012a906b | 603 | } |
e8925712 | 604 | } |
012a906b GB |
605 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
606 | excp_idx = EXCP_IRQ; | |
607 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
be879556 RH |
608 | if (arm_excp_unmasked(cs, excp_idx, target_el, |
609 | cur_el, secure, hcr_el2)) { | |
d63d0ec5 | 610 | goto found; |
012a906b | 611 | } |
e8925712 | 612 | } |
012a906b GB |
613 | if (interrupt_request & CPU_INTERRUPT_VIRQ) { |
614 | excp_idx = EXCP_VIRQ; | |
615 | target_el = 1; | |
be879556 RH |
616 | if (arm_excp_unmasked(cs, excp_idx, target_el, |
617 | cur_el, secure, hcr_el2)) { | |
d63d0ec5 | 618 | goto found; |
012a906b | 619 | } |
136e67e9 | 620 | } |
012a906b GB |
621 | if (interrupt_request & CPU_INTERRUPT_VFIQ) { |
622 | excp_idx = EXCP_VFIQ; | |
623 | target_el = 1; | |
be879556 RH |
624 | if (arm_excp_unmasked(cs, excp_idx, target_el, |
625 | cur_el, secure, hcr_el2)) { | |
d63d0ec5 | 626 | goto found; |
012a906b | 627 | } |
136e67e9 | 628 | } |
d63d0ec5 | 629 | return false; |
e8925712 | 630 | |
d63d0ec5 RH |
631 | found: |
632 | cs->exception_index = excp_idx; | |
633 | env->exception.target_el = target_el; | |
78271684 | 634 | cc->tcg_ops->do_interrupt(cs); |
d63d0ec5 | 635 | return true; |
e8925712 | 636 | } |
083afd18 | 637 | #endif /* !CONFIG_USER_ONLY */ |
e8925712 | 638 | |
89430fc6 PM |
639 | void arm_cpu_update_virq(ARMCPU *cpu) |
640 | { | |
641 | /* | |
642 | * Update the interrupt level for VIRQ, which is the logical OR of | |
643 | * the HCR_EL2.VI bit and the input line level from the GIC. | |
644 | */ | |
645 | CPUARMState *env = &cpu->env; | |
646 | CPUState *cs = CPU(cpu); | |
647 | ||
648 | bool new_state = (env->cp15.hcr_el2 & HCR_VI) || | |
649 | (env->irq_line_state & CPU_INTERRUPT_VIRQ); | |
650 | ||
651 | if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { | |
652 | if (new_state) { | |
653 | cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); | |
654 | } else { | |
655 | cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); | |
656 | } | |
657 | } | |
658 | } | |
659 | ||
660 | void arm_cpu_update_vfiq(ARMCPU *cpu) | |
661 | { | |
662 | /* | |
663 | * Update the interrupt level for VFIQ, which is the logical OR of | |
664 | * the HCR_EL2.VF bit and the input line level from the GIC. | |
665 | */ | |
666 | CPUARMState *env = &cpu->env; | |
667 | CPUState *cs = CPU(cpu); | |
668 | ||
669 | bool new_state = (env->cp15.hcr_el2 & HCR_VF) || | |
670 | (env->irq_line_state & CPU_INTERRUPT_VFIQ); | |
671 | ||
672 | if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { | |
673 | if (new_state) { | |
674 | cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); | |
675 | } else { | |
676 | cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); | |
677 | } | |
678 | } | |
679 | } | |
680 | ||
7c1840b6 PM |
681 | #ifndef CONFIG_USER_ONLY |
682 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | |
683 | { | |
684 | ARMCPU *cpu = opaque; | |
136e67e9 | 685 | CPUARMState *env = &cpu->env; |
7c1840b6 | 686 | CPUState *cs = CPU(cpu); |
136e67e9 EI |
687 | static const int mask[] = { |
688 | [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, | |
689 | [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, | |
690 | [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, | |
691 | [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ | |
692 | }; | |
7c1840b6 | 693 | |
ed89f078 PM |
694 | if (level) { |
695 | env->irq_line_state |= mask[irq]; | |
696 | } else { | |
697 | env->irq_line_state &= ~mask[irq]; | |
698 | } | |
699 | ||
7c1840b6 | 700 | switch (irq) { |
136e67e9 | 701 | case ARM_CPU_VIRQ: |
89430fc6 PM |
702 | assert(arm_feature(env, ARM_FEATURE_EL2)); |
703 | arm_cpu_update_virq(cpu); | |
704 | break; | |
136e67e9 | 705 | case ARM_CPU_VFIQ: |
f128bf29 | 706 | assert(arm_feature(env, ARM_FEATURE_EL2)); |
89430fc6 PM |
707 | arm_cpu_update_vfiq(cpu); |
708 | break; | |
136e67e9 | 709 | case ARM_CPU_IRQ: |
7c1840b6 PM |
710 | case ARM_CPU_FIQ: |
711 | if (level) { | |
136e67e9 | 712 | cpu_interrupt(cs, mask[irq]); |
7c1840b6 | 713 | } else { |
136e67e9 | 714 | cpu_reset_interrupt(cs, mask[irq]); |
7c1840b6 PM |
715 | } |
716 | break; | |
717 | default: | |
8f6fd322 | 718 | g_assert_not_reached(); |
7c1840b6 PM |
719 | } |
720 | } | |
721 | ||
722 | static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) | |
723 | { | |
724 | #ifdef CONFIG_KVM | |
725 | ARMCPU *cpu = opaque; | |
ed89f078 | 726 | CPUARMState *env = &cpu->env; |
7c1840b6 | 727 | CPUState *cs = CPU(cpu); |
ed89f078 | 728 | uint32_t linestate_bit; |
f6530926 | 729 | int irq_id; |
7c1840b6 PM |
730 | |
731 | switch (irq) { | |
732 | case ARM_CPU_IRQ: | |
f6530926 | 733 | irq_id = KVM_ARM_IRQ_CPU_IRQ; |
ed89f078 | 734 | linestate_bit = CPU_INTERRUPT_HARD; |
7c1840b6 PM |
735 | break; |
736 | case ARM_CPU_FIQ: | |
f6530926 | 737 | irq_id = KVM_ARM_IRQ_CPU_FIQ; |
ed89f078 | 738 | linestate_bit = CPU_INTERRUPT_FIQ; |
7c1840b6 PM |
739 | break; |
740 | default: | |
8f6fd322 | 741 | g_assert_not_reached(); |
7c1840b6 | 742 | } |
ed89f078 PM |
743 | |
744 | if (level) { | |
745 | env->irq_line_state |= linestate_bit; | |
746 | } else { | |
747 | env->irq_line_state &= ~linestate_bit; | |
748 | } | |
f6530926 | 749 | kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); |
7c1840b6 PM |
750 | #endif |
751 | } | |
84f2bed3 | 752 | |
ed50ff78 | 753 | static bool arm_cpu_virtio_is_big_endian(CPUState *cs) |
84f2bed3 PS |
754 | { |
755 | ARMCPU *cpu = ARM_CPU(cs); | |
756 | CPUARMState *env = &cpu->env; | |
84f2bed3 PS |
757 | |
758 | cpu_synchronize_state(cs); | |
ed50ff78 | 759 | return arm_cpu_data_is_big_endian(env); |
84f2bed3 PS |
760 | } |
761 | ||
7c1840b6 PM |
762 | #endif |
763 | ||
48440620 PC |
764 | static int |
765 | print_insn_thumb1(bfd_vma pc, disassemble_info *info) | |
766 | { | |
767 | return print_insn_arm(pc | 1, info); | |
768 | } | |
769 | ||
770 | static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) | |
771 | { | |
772 | ARMCPU *ac = ARM_CPU(cpu); | |
773 | CPUARMState *env = &ac->env; | |
7bcdbf51 | 774 | bool sctlr_b; |
48440620 PC |
775 | |
776 | if (is_a64(env)) { | |
777 | /* We might not be compiled with the A64 disassembler | |
778 | * because it needs a C++ compiler. Leave print_insn | |
779 | * unset in this case to use the caller default behaviour. | |
780 | */ | |
781 | #if defined(CONFIG_ARM_A64_DIS) | |
782 | info->print_insn = print_insn_arm_a64; | |
783 | #endif | |
110f6c70 | 784 | info->cap_arch = CS_ARCH_ARM64; |
15fa1a0a RH |
785 | info->cap_insn_unit = 4; |
786 | info->cap_insn_split = 4; | |
48440620 | 787 | } else { |
110f6c70 RH |
788 | int cap_mode; |
789 | if (env->thumb) { | |
790 | info->print_insn = print_insn_thumb1; | |
15fa1a0a RH |
791 | info->cap_insn_unit = 2; |
792 | info->cap_insn_split = 4; | |
110f6c70 RH |
793 | cap_mode = CS_MODE_THUMB; |
794 | } else { | |
795 | info->print_insn = print_insn_arm; | |
15fa1a0a RH |
796 | info->cap_insn_unit = 4; |
797 | info->cap_insn_split = 4; | |
110f6c70 RH |
798 | cap_mode = CS_MODE_ARM; |
799 | } | |
800 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
801 | cap_mode |= CS_MODE_V8; | |
802 | } | |
803 | if (arm_feature(env, ARM_FEATURE_M)) { | |
804 | cap_mode |= CS_MODE_MCLASS; | |
805 | } | |
806 | info->cap_arch = CS_ARCH_ARM; | |
807 | info->cap_mode = cap_mode; | |
48440620 | 808 | } |
7bcdbf51 RH |
809 | |
810 | sctlr_b = arm_sctlr_b(env); | |
811 | if (bswap_code(sctlr_b)) { | |
48440620 PC |
812 | #ifdef TARGET_WORDS_BIGENDIAN |
813 | info->endian = BFD_ENDIAN_LITTLE; | |
814 | #else | |
815 | info->endian = BFD_ENDIAN_BIG; | |
816 | #endif | |
817 | } | |
f7478a92 | 818 | info->flags &= ~INSN_ARM_BE32; |
7bcdbf51 RH |
819 | #ifndef CONFIG_USER_ONLY |
820 | if (sctlr_b) { | |
f7478a92 JB |
821 | info->flags |= INSN_ARM_BE32; |
822 | } | |
7bcdbf51 | 823 | #endif |
48440620 PC |
824 | } |
825 | ||
86480615 PMD |
826 | #ifdef TARGET_AARCH64 |
827 | ||
828 | static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) | |
829 | { | |
830 | ARMCPU *cpu = ARM_CPU(cs); | |
831 | CPUARMState *env = &cpu->env; | |
832 | uint32_t psr = pstate_read(env); | |
833 | int i; | |
834 | int el = arm_current_el(env); | |
835 | const char *ns_status; | |
836 | ||
837 | qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); | |
838 | for (i = 0; i < 32; i++) { | |
839 | if (i == 31) { | |
840 | qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); | |
841 | } else { | |
842 | qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], | |
843 | (i + 2) % 3 ? " " : "\n"); | |
844 | } | |
845 | } | |
846 | ||
847 | if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { | |
848 | ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; | |
849 | } else { | |
850 | ns_status = ""; | |
851 | } | |
852 | qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", | |
853 | psr, | |
854 | psr & PSTATE_N ? 'N' : '-', | |
855 | psr & PSTATE_Z ? 'Z' : '-', | |
856 | psr & PSTATE_C ? 'C' : '-', | |
857 | psr & PSTATE_V ? 'V' : '-', | |
858 | ns_status, | |
859 | el, | |
860 | psr & PSTATE_SP ? 'h' : 't'); | |
861 | ||
862 | if (cpu_isar_feature(aa64_bti, cpu)) { | |
863 | qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); | |
864 | } | |
865 | if (!(flags & CPU_DUMP_FPU)) { | |
866 | qemu_fprintf(f, "\n"); | |
867 | return; | |
868 | } | |
869 | if (fp_exception_el(env, el) != 0) { | |
870 | qemu_fprintf(f, " FPU disabled\n"); | |
871 | return; | |
872 | } | |
873 | qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", | |
874 | vfp_get_fpcr(env), vfp_get_fpsr(env)); | |
875 | ||
876 | if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { | |
877 | int j, zcr_len = sve_zcr_len_for_el(env, el); | |
878 | ||
879 | for (i = 0; i <= FFR_PRED_NUM; i++) { | |
880 | bool eol; | |
881 | if (i == FFR_PRED_NUM) { | |
882 | qemu_fprintf(f, "FFR="); | |
883 | /* It's last, so end the line. */ | |
884 | eol = true; | |
885 | } else { | |
886 | qemu_fprintf(f, "P%02d=", i); | |
887 | switch (zcr_len) { | |
888 | case 0: | |
889 | eol = i % 8 == 7; | |
890 | break; | |
891 | case 1: | |
892 | eol = i % 6 == 5; | |
893 | break; | |
894 | case 2: | |
895 | case 3: | |
896 | eol = i % 3 == 2; | |
897 | break; | |
898 | default: | |
899 | /* More than one quadword per predicate. */ | |
900 | eol = true; | |
901 | break; | |
902 | } | |
903 | } | |
904 | for (j = zcr_len / 4; j >= 0; j--) { | |
905 | int digits; | |
906 | if (j * 4 + 4 <= zcr_len + 1) { | |
907 | digits = 16; | |
908 | } else { | |
909 | digits = (zcr_len % 4 + 1) * 4; | |
910 | } | |
911 | qemu_fprintf(f, "%0*" PRIx64 "%s", digits, | |
912 | env->vfp.pregs[i].p[j], | |
913 | j ? ":" : eol ? "\n" : " "); | |
914 | } | |
915 | } | |
916 | ||
917 | for (i = 0; i < 32; i++) { | |
918 | if (zcr_len == 0) { | |
919 | qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", | |
920 | i, env->vfp.zregs[i].d[1], | |
921 | env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); | |
922 | } else if (zcr_len == 1) { | |
923 | qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 | |
924 | ":%016" PRIx64 ":%016" PRIx64 "\n", | |
925 | i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], | |
926 | env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); | |
927 | } else { | |
928 | for (j = zcr_len; j >= 0; j--) { | |
929 | bool odd = (zcr_len - j) % 2 != 0; | |
930 | if (j == zcr_len) { | |
931 | qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); | |
932 | } else if (!odd) { | |
933 | if (j > 0) { | |
934 | qemu_fprintf(f, " [%x-%x]=", j, j - 1); | |
935 | } else { | |
936 | qemu_fprintf(f, " [%x]=", j); | |
937 | } | |
938 | } | |
939 | qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", | |
940 | env->vfp.zregs[i].d[j * 2 + 1], | |
941 | env->vfp.zregs[i].d[j * 2], | |
942 | odd || j == 0 ? "\n" : ":"); | |
943 | } | |
944 | } | |
945 | } | |
946 | } else { | |
947 | for (i = 0; i < 32; i++) { | |
948 | uint64_t *q = aa64_vfp_qreg(env, i); | |
949 | qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", | |
950 | i, q[1], q[0], (i & 1 ? "\n" : " ")); | |
951 | } | |
952 | } | |
953 | } | |
954 | ||
955 | #else | |
956 | ||
957 | static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) | |
958 | { | |
959 | g_assert_not_reached(); | |
960 | } | |
961 | ||
962 | #endif | |
963 | ||
964 | static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) | |
965 | { | |
966 | ARMCPU *cpu = ARM_CPU(cs); | |
967 | CPUARMState *env = &cpu->env; | |
968 | int i; | |
969 | ||
970 | if (is_a64(env)) { | |
971 | aarch64_cpu_dump_state(cs, f, flags); | |
972 | return; | |
973 | } | |
974 | ||
975 | for (i = 0; i < 16; i++) { | |
976 | qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); | |
977 | if ((i % 4) == 3) { | |
978 | qemu_fprintf(f, "\n"); | |
979 | } else { | |
980 | qemu_fprintf(f, " "); | |
981 | } | |
982 | } | |
983 | ||
984 | if (arm_feature(env, ARM_FEATURE_M)) { | |
985 | uint32_t xpsr = xpsr_read(env); | |
986 | const char *mode; | |
987 | const char *ns_status = ""; | |
988 | ||
989 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
990 | ns_status = env->v7m.secure ? "S " : "NS "; | |
991 | } | |
992 | ||
993 | if (xpsr & XPSR_EXCP) { | |
994 | mode = "handler"; | |
995 | } else { | |
996 | if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { | |
997 | mode = "unpriv-thread"; | |
998 | } else { | |
999 | mode = "priv-thread"; | |
1000 | } | |
1001 | } | |
1002 | ||
1003 | qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", | |
1004 | xpsr, | |
1005 | xpsr & XPSR_N ? 'N' : '-', | |
1006 | xpsr & XPSR_Z ? 'Z' : '-', | |
1007 | xpsr & XPSR_C ? 'C' : '-', | |
1008 | xpsr & XPSR_V ? 'V' : '-', | |
1009 | xpsr & XPSR_T ? 'T' : 'A', | |
1010 | ns_status, | |
1011 | mode); | |
1012 | } else { | |
1013 | uint32_t psr = cpsr_read(env); | |
1014 | const char *ns_status = ""; | |
1015 | ||
1016 | if (arm_feature(env, ARM_FEATURE_EL3) && | |
1017 | (psr & CPSR_M) != ARM_CPU_MODE_MON) { | |
1018 | ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; | |
1019 | } | |
1020 | ||
1021 | qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", | |
1022 | psr, | |
1023 | psr & CPSR_N ? 'N' : '-', | |
1024 | psr & CPSR_Z ? 'Z' : '-', | |
1025 | psr & CPSR_C ? 'C' : '-', | |
1026 | psr & CPSR_V ? 'V' : '-', | |
1027 | psr & CPSR_T ? 'T' : 'A', | |
1028 | ns_status, | |
1029 | aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); | |
1030 | } | |
1031 | ||
1032 | if (flags & CPU_DUMP_FPU) { | |
1033 | int numvfpregs = 0; | |
a6627f5f RH |
1034 | if (cpu_isar_feature(aa32_simd_r32, cpu)) { |
1035 | numvfpregs = 32; | |
7fbc6a40 | 1036 | } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { |
a6627f5f | 1037 | numvfpregs = 16; |
86480615 PMD |
1038 | } |
1039 | for (i = 0; i < numvfpregs; i++) { | |
1040 | uint64_t v = *aa32_vfp_dreg(env, i); | |
1041 | qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", | |
1042 | i * 2, (uint32_t)v, | |
1043 | i * 2 + 1, (uint32_t)(v >> 32), | |
1044 | i, v); | |
1045 | } | |
1046 | qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); | |
aa291908 PM |
1047 | if (cpu_isar_feature(aa32_mve, cpu)) { |
1048 | qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr); | |
1049 | } | |
86480615 PMD |
1050 | } |
1051 | } | |
1052 | ||
46de5913 IM |
1053 | uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) |
1054 | { | |
1055 | uint32_t Aff1 = idx / clustersz; | |
1056 | uint32_t Aff0 = idx % clustersz; | |
1057 | return (Aff1 << ARM_AFF1_SHIFT) | Aff0; | |
1058 | } | |
1059 | ||
ac87e507 PM |
1060 | static void cpreg_hashtable_data_destroy(gpointer data) |
1061 | { | |
1062 | /* | |
1063 | * Destroy function for cpu->cp_regs hashtable data entries. | |
1064 | * We must free the name string because it was g_strdup()ed in | |
1065 | * add_cpreg_to_hashtable(). It's OK to cast away the 'const' | |
1066 | * from r->name because we know we definitely allocated it. | |
1067 | */ | |
1068 | ARMCPRegInfo *r = data; | |
1069 | ||
1070 | g_free((void *)r->name); | |
1071 | g_free(r); | |
1072 | } | |
1073 | ||
777dc784 PM |
1074 | static void arm_cpu_initfn(Object *obj) |
1075 | { | |
1076 | ARMCPU *cpu = ARM_CPU(obj); | |
1077 | ||
7506ed90 | 1078 | cpu_set_cpustate_pointers(cpu); |
4b6a83fb | 1079 | cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
ac87e507 | 1080 | g_free, cpreg_hashtable_data_destroy); |
79614b78 | 1081 | |
b5c53d1b | 1082 | QLIST_INIT(&cpu->pre_el_change_hooks); |
08267487 AL |
1083 | QLIST_INIT(&cpu->el_change_hooks); |
1084 | ||
b3d52804 RH |
1085 | #ifdef CONFIG_USER_ONLY |
1086 | # ifdef TARGET_AARCH64 | |
1087 | /* | |
1088 | * The linux kernel defaults to 512-bit vectors, when sve is supported. | |
1089 | * See documentation for /proc/sys/abi/sve_default_vector_length, and | |
1090 | * our corresponding sve-default-vector-length cpu property. | |
1091 | */ | |
1092 | cpu->sve_default_vq = 4; | |
1093 | # endif | |
1094 | #else | |
7c1840b6 PM |
1095 | /* Our inbound IRQ and FIQ lines */ |
1096 | if (kvm_enabled()) { | |
136e67e9 EI |
1097 | /* VIRQ and VFIQ are unused with KVM but we add them to maintain |
1098 | * the same interface as non-KVM CPUs. | |
1099 | */ | |
1100 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); | |
7c1840b6 | 1101 | } else { |
136e67e9 | 1102 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); |
7c1840b6 | 1103 | } |
55d284af | 1104 | |
55d284af PM |
1105 | qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, |
1106 | ARRAY_SIZE(cpu->gt_timer_outputs)); | |
aa1b3111 PM |
1107 | |
1108 | qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, | |
1109 | "gicv3-maintenance-interrupt", 1); | |
07f48730 AJ |
1110 | qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, |
1111 | "pmu-interrupt", 1); | |
7c1840b6 PM |
1112 | #endif |
1113 | ||
54d3e3f5 PM |
1114 | /* DTB consumers generally don't in fact care what the 'compatible' |
1115 | * string is, so always provide some string and trust that a hypothetical | |
1116 | * picky DTB consumer will also provide a helpful error message. | |
1117 | */ | |
1118 | cpu->dtb_compatible = "qemu,unknown"; | |
0dc71c70 | 1119 | cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */ |
3541addc | 1120 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; |
54d3e3f5 | 1121 | |
2c9c0bf9 | 1122 | if (tcg_enabled() || hvf_enabled()) { |
0dc71c70 AO |
1123 | /* TCG and HVF implement PSCI 1.1 */ |
1124 | cpu->psci_version = QEMU_PSCI_VERSION_1_1; | |
79614b78 | 1125 | } |
4b6a83fb PM |
1126 | } |
1127 | ||
96eec6b2 AJ |
1128 | static Property arm_cpu_gt_cntfrq_property = |
1129 | DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, | |
1130 | NANOSECONDS_PER_SECOND / GTIMER_SCALE); | |
1131 | ||
07a5b0d2 | 1132 | static Property arm_cpu_reset_cbar_property = |
f318cec6 | 1133 | DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); |
07a5b0d2 | 1134 | |
68e0a40a AP |
1135 | static Property arm_cpu_reset_hivecs_property = |
1136 | DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); | |
1137 | ||
3933443e PM |
1138 | static Property arm_cpu_rvbar_property = |
1139 | DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); | |
1140 | ||
45ca3a14 | 1141 | #ifndef CONFIG_USER_ONLY |
c25bd18a PM |
1142 | static Property arm_cpu_has_el2_property = |
1143 | DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); | |
1144 | ||
51942aee GB |
1145 | static Property arm_cpu_has_el3_property = |
1146 | DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); | |
45ca3a14 | 1147 | #endif |
51942aee | 1148 | |
3a062d57 JB |
1149 | static Property arm_cpu_cfgend_property = |
1150 | DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); | |
1151 | ||
97a28b0e PM |
1152 | static Property arm_cpu_has_vfp_property = |
1153 | DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); | |
1154 | ||
1155 | static Property arm_cpu_has_neon_property = | |
1156 | DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); | |
1157 | ||
ea90db0a PM |
1158 | static Property arm_cpu_has_dsp_property = |
1159 | DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); | |
1160 | ||
8f325f56 PC |
1161 | static Property arm_cpu_has_mpu_property = |
1162 | DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); | |
1163 | ||
8d92e26b PM |
1164 | /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, |
1165 | * because the CPU initfn will have already set cpu->pmsav7_dregion to | |
1166 | * the right value for that particular CPU type, and we don't want | |
1167 | * to override that with an incorrect constant value. | |
1168 | */ | |
3281af81 | 1169 | static Property arm_cpu_pmsav7_dregion_property = |
8d92e26b PM |
1170 | DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, |
1171 | pmsav7_dregion, | |
1172 | qdev_prop_uint32, uint32_t); | |
3281af81 | 1173 | |
ae502508 AJ |
1174 | static bool arm_get_pmu(Object *obj, Error **errp) |
1175 | { | |
1176 | ARMCPU *cpu = ARM_CPU(obj); | |
1177 | ||
1178 | return cpu->has_pmu; | |
1179 | } | |
1180 | ||
1181 | static void arm_set_pmu(Object *obj, bool value, Error **errp) | |
1182 | { | |
1183 | ARMCPU *cpu = ARM_CPU(obj); | |
1184 | ||
1185 | if (value) { | |
7d20e681 | 1186 | if (kvm_enabled() && !kvm_arm_pmu_supported()) { |
ae502508 AJ |
1187 | error_setg(errp, "'pmu' feature not supported by KVM on this host"); |
1188 | return; | |
1189 | } | |
1190 | set_feature(&cpu->env, ARM_FEATURE_PMU); | |
1191 | } else { | |
1192 | unset_feature(&cpu->env, ARM_FEATURE_PMU); | |
1193 | } | |
1194 | cpu->has_pmu = value; | |
1195 | } | |
1196 | ||
7def8754 AJ |
1197 | unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) |
1198 | { | |
96eec6b2 AJ |
1199 | /* |
1200 | * The exact approach to calculating guest ticks is: | |
1201 | * | |
1202 | * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, | |
1203 | * NANOSECONDS_PER_SECOND); | |
1204 | * | |
1205 | * We don't do that. Rather we intentionally use integer division | |
1206 | * truncation below and in the caller for the conversion of host monotonic | |
1207 | * time to guest ticks to provide the exact inverse for the semantics of | |
1208 | * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so | |
1209 | * it loses precision when representing frequencies where | |
1210 | * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to | |
1211 | * provide an exact inverse leads to scheduling timers with negative | |
1212 | * periods, which in turn leads to sticky behaviour in the guest. | |
1213 | * | |
1214 | * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor | |
1215 | * cannot become zero. | |
1216 | */ | |
7def8754 AJ |
1217 | return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? |
1218 | NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; | |
1219 | } | |
1220 | ||
51e5ef45 | 1221 | void arm_cpu_post_init(Object *obj) |
07a5b0d2 PC |
1222 | { |
1223 | ARMCPU *cpu = ARM_CPU(obj); | |
07a5b0d2 | 1224 | |
790a1150 PM |
1225 | /* M profile implies PMSA. We have to do this here rather than |
1226 | * in realize with the other feature-implication checks because | |
1227 | * we look at the PMSA bit to see if we should add some properties. | |
1228 | */ | |
1229 | if (arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
1230 | set_feature(&cpu->env, ARM_FEATURE_PMSA); | |
1231 | } | |
1232 | ||
f318cec6 PM |
1233 | if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || |
1234 | arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { | |
94d912d1 | 1235 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); |
07a5b0d2 | 1236 | } |
68e0a40a AP |
1237 | |
1238 | if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
94d912d1 | 1239 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); |
68e0a40a | 1240 | } |
3933443e PM |
1241 | |
1242 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
94d912d1 | 1243 | qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); |
3933443e | 1244 | } |
51942aee | 1245 | |
45ca3a14 | 1246 | #ifndef CONFIG_USER_ONLY |
51942aee GB |
1247 | if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { |
1248 | /* Add the has_el3 state CPU property only if EL3 is allowed. This will | |
1249 | * prevent "has_el3" from existing on CPUs which cannot support EL3. | |
1250 | */ | |
94d912d1 | 1251 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); |
9e273ef2 | 1252 | |
9e273ef2 PM |
1253 | object_property_add_link(obj, "secure-memory", |
1254 | TYPE_MEMORY_REGION, | |
1255 | (Object **)&cpu->secure_memory, | |
1256 | qdev_prop_allow_set_link_before_realize, | |
d2623129 | 1257 | OBJ_PROP_LINK_STRONG); |
51942aee | 1258 | } |
8f325f56 | 1259 | |
c25bd18a | 1260 | if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { |
94d912d1 | 1261 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); |
c25bd18a | 1262 | } |
45ca3a14 | 1263 | #endif |
c25bd18a | 1264 | |
929e754d | 1265 | if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { |
ae502508 | 1266 | cpu->has_pmu = true; |
d2623129 | 1267 | object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); |
929e754d WH |
1268 | } |
1269 | ||
97a28b0e PM |
1270 | /* |
1271 | * Allow user to turn off VFP and Neon support, but only for TCG -- | |
1272 | * KVM does not currently allow us to lie to the guest about its | |
1273 | * ID/feature registers, so the guest always sees what the host has. | |
1274 | */ | |
7d63183f RH |
1275 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) |
1276 | ? cpu_isar_feature(aa64_fp_simd, cpu) | |
1277 | : cpu_isar_feature(aa32_vfp, cpu)) { | |
97a28b0e PM |
1278 | cpu->has_vfp = true; |
1279 | if (!kvm_enabled()) { | |
94d912d1 | 1280 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); |
97a28b0e PM |
1281 | } |
1282 | } | |
1283 | ||
1284 | if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { | |
1285 | cpu->has_neon = true; | |
1286 | if (!kvm_enabled()) { | |
94d912d1 | 1287 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); |
97a28b0e PM |
1288 | } |
1289 | } | |
1290 | ||
ea90db0a PM |
1291 | if (arm_feature(&cpu->env, ARM_FEATURE_M) && |
1292 | arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { | |
94d912d1 | 1293 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); |
ea90db0a PM |
1294 | } |
1295 | ||
452a0955 | 1296 | if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { |
94d912d1 | 1297 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); |
3281af81 PC |
1298 | if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { |
1299 | qdev_property_add_static(DEVICE(obj), | |
94d912d1 | 1300 | &arm_cpu_pmsav7_dregion_property); |
3281af81 | 1301 | } |
8f325f56 PC |
1302 | } |
1303 | ||
181962fd PM |
1304 | if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { |
1305 | object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, | |
1306 | qdev_prop_allow_set_link_before_realize, | |
d2623129 | 1307 | OBJ_PROP_LINK_STRONG); |
f9f62e4c PM |
1308 | /* |
1309 | * M profile: initial value of the Secure VTOR. We can't just use | |
1310 | * a simple DEFINE_PROP_UINT32 for this because we want to permit | |
1311 | * the property to be set after realize. | |
1312 | */ | |
64a7b8de FF |
1313 | object_property_add_uint32_ptr(obj, "init-svtor", |
1314 | &cpu->init_svtor, | |
d2623129 | 1315 | OBJ_PROP_FLAG_READWRITE); |
181962fd | 1316 | } |
7cda2149 PM |
1317 | if (arm_feature(&cpu->env, ARM_FEATURE_M)) { |
1318 | /* | |
1319 | * Initial value of the NS VTOR (for cores without the Security | |
1320 | * extension, this is the only VTOR) | |
1321 | */ | |
1322 | object_property_add_uint32_ptr(obj, "init-nsvtor", | |
1323 | &cpu->init_nsvtor, | |
1324 | OBJ_PROP_FLAG_READWRITE); | |
1325 | } | |
181962fd | 1326 | |
bddd892e PM |
1327 | /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */ |
1328 | object_property_add_uint32_ptr(obj, "psci-conduit", | |
1329 | &cpu->psci_conduit, | |
1330 | OBJ_PROP_FLAG_READWRITE); | |
1331 | ||
94d912d1 | 1332 | qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); |
96eec6b2 AJ |
1333 | |
1334 | if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { | |
94d912d1 | 1335 | qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); |
96eec6b2 | 1336 | } |
9e6f8d8a | 1337 | |
1338 | if (kvm_enabled()) { | |
1339 | kvm_arm_add_vcpu_properties(obj); | |
1340 | } | |
8bce44a2 RH |
1341 | |
1342 | #ifndef CONFIG_USER_ONLY | |
1343 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && | |
1344 | cpu_isar_feature(aa64_mte, cpu)) { | |
1345 | object_property_add_link(obj, "tag-memory", | |
1346 | TYPE_MEMORY_REGION, | |
1347 | (Object **)&cpu->tag_memory, | |
1348 | qdev_prop_allow_set_link_before_realize, | |
1349 | OBJ_PROP_LINK_STRONG); | |
1350 | ||
1351 | if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { | |
1352 | object_property_add_link(obj, "secure-tag-memory", | |
1353 | TYPE_MEMORY_REGION, | |
1354 | (Object **)&cpu->secure_tag_memory, | |
1355 | qdev_prop_allow_set_link_before_realize, | |
1356 | OBJ_PROP_LINK_STRONG); | |
1357 | } | |
1358 | } | |
1359 | #endif | |
07a5b0d2 PC |
1360 | } |
1361 | ||
4b6a83fb PM |
1362 | static void arm_cpu_finalizefn(Object *obj) |
1363 | { | |
1364 | ARMCPU *cpu = ARM_CPU(obj); | |
08267487 AL |
1365 | ARMELChangeHook *hook, *next; |
1366 | ||
4b6a83fb | 1367 | g_hash_table_destroy(cpu->cp_regs); |
08267487 | 1368 | |
b5c53d1b AL |
1369 | QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { |
1370 | QLIST_REMOVE(hook, node); | |
1371 | g_free(hook); | |
1372 | } | |
08267487 AL |
1373 | QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { |
1374 | QLIST_REMOVE(hook, node); | |
1375 | g_free(hook); | |
1376 | } | |
4e7beb0c AL |
1377 | #ifndef CONFIG_USER_ONLY |
1378 | if (cpu->pmu_timer) { | |
4e7beb0c AL |
1379 | timer_free(cpu->pmu_timer); |
1380 | } | |
1381 | #endif | |
777dc784 PM |
1382 | } |
1383 | ||
0df9142d AJ |
1384 | void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) |
1385 | { | |
1386 | Error *local_err = NULL; | |
1387 | ||
1388 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
1389 | arm_cpu_sve_finalize(cpu, &local_err); | |
68970d1e AJ |
1390 | if (local_err != NULL) { |
1391 | error_propagate(errp, local_err); | |
1392 | return; | |
1393 | } | |
eb94284d | 1394 | |
95ea96e8 MZ |
1395 | arm_cpu_pauth_finalize(cpu, &local_err); |
1396 | if (local_err != NULL) { | |
1397 | error_propagate(errp, local_err); | |
1398 | return; | |
eb94284d | 1399 | } |
69b2265d RH |
1400 | |
1401 | arm_cpu_lpa2_finalize(cpu, &local_err); | |
1402 | if (local_err != NULL) { | |
1403 | error_propagate(errp, local_err); | |
1404 | return; | |
1405 | } | |
68970d1e AJ |
1406 | } |
1407 | ||
1408 | if (kvm_enabled()) { | |
1409 | kvm_arm_steal_time_finalize(cpu, &local_err); | |
0df9142d AJ |
1410 | if (local_err != NULL) { |
1411 | error_propagate(errp, local_err); | |
1412 | return; | |
1413 | } | |
1414 | } | |
1415 | } | |
1416 | ||
14969266 | 1417 | static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
581be094 | 1418 | { |
14a10fc3 | 1419 | CPUState *cs = CPU(dev); |
14969266 AF |
1420 | ARMCPU *cpu = ARM_CPU(dev); |
1421 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); | |
581be094 | 1422 | CPUARMState *env = &cpu->env; |
e97da98f | 1423 | int pagebits; |
ce5b1bbf | 1424 | Error *local_err = NULL; |
0f8d06f1 | 1425 | bool no_aa32 = false; |
ce5b1bbf | 1426 | |
c4487d76 PM |
1427 | /* If we needed to query the host kernel for the CPU features |
1428 | * then it's possible that might have failed in the initfn, but | |
1429 | * this is the first point where we can report it. | |
1430 | */ | |
1431 | if (cpu->host_cpu_probe_failed) { | |
585df85e PM |
1432 | if (!kvm_enabled() && !hvf_enabled()) { |
1433 | error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF"); | |
c4487d76 PM |
1434 | } else { |
1435 | error_setg(errp, "Failed to retrieve host CPU features"); | |
1436 | } | |
1437 | return; | |
1438 | } | |
1439 | ||
95f87565 PM |
1440 | #ifndef CONFIG_USER_ONLY |
1441 | /* The NVIC and M-profile CPU are two halves of a single piece of | |
1442 | * hardware; trying to use one without the other is a command line | |
1443 | * error and will result in segfaults if not caught here. | |
1444 | */ | |
1445 | if (arm_feature(env, ARM_FEATURE_M)) { | |
1446 | if (!env->nvic) { | |
1447 | error_setg(errp, "This board cannot be used with Cortex-M CPUs"); | |
1448 | return; | |
1449 | } | |
1450 | } else { | |
1451 | if (env->nvic) { | |
1452 | error_setg(errp, "This board can only be used with Cortex-M CPUs"); | |
1453 | return; | |
1454 | } | |
1455 | } | |
397cd31f | 1456 | |
49e7f191 PM |
1457 | if (kvm_enabled()) { |
1458 | /* | |
1459 | * Catch all the cases which might cause us to create more than one | |
1460 | * address space for the CPU (otherwise we will assert() later in | |
1461 | * cpu_address_space_init()). | |
1462 | */ | |
1463 | if (arm_feature(env, ARM_FEATURE_M)) { | |
1464 | error_setg(errp, | |
1465 | "Cannot enable KVM when using an M-profile guest CPU"); | |
1466 | return; | |
1467 | } | |
1468 | if (cpu->has_el3) { | |
1469 | error_setg(errp, | |
1470 | "Cannot enable KVM when guest CPU has EL3 enabled"); | |
1471 | return; | |
1472 | } | |
1473 | if (cpu->tag_memory) { | |
1474 | error_setg(errp, | |
1475 | "Cannot enable KVM when guest CPUs has MTE enabled"); | |
1476 | return; | |
1477 | } | |
1478 | } | |
1479 | ||
96eec6b2 AJ |
1480 | { |
1481 | uint64_t scale; | |
1482 | ||
1483 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { | |
1484 | if (!cpu->gt_cntfrq_hz) { | |
1485 | error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", | |
1486 | cpu->gt_cntfrq_hz); | |
1487 | return; | |
1488 | } | |
1489 | scale = gt_cntfrq_period_ns(cpu); | |
1490 | } else { | |
1491 | scale = GTIMER_SCALE; | |
1492 | } | |
1493 | ||
1494 | cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, | |
1495 | arm_gt_ptimer_cb, cpu); | |
1496 | cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, | |
1497 | arm_gt_vtimer_cb, cpu); | |
1498 | cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, | |
1499 | arm_gt_htimer_cb, cpu); | |
1500 | cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, | |
1501 | arm_gt_stimer_cb, cpu); | |
8c94b071 RH |
1502 | cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, |
1503 | arm_gt_hvtimer_cb, cpu); | |
96eec6b2 | 1504 | } |
95f87565 PM |
1505 | #endif |
1506 | ||
ce5b1bbf LV |
1507 | cpu_exec_realizefn(cs, &local_err); |
1508 | if (local_err != NULL) { | |
1509 | error_propagate(errp, local_err); | |
1510 | return; | |
1511 | } | |
14969266 | 1512 | |
0df9142d AJ |
1513 | arm_cpu_finalize_features(cpu, &local_err); |
1514 | if (local_err != NULL) { | |
1515 | error_propagate(errp, local_err); | |
1516 | return; | |
1517 | } | |
1518 | ||
97a28b0e PM |
1519 | if (arm_feature(env, ARM_FEATURE_AARCH64) && |
1520 | cpu->has_vfp != cpu->has_neon) { | |
1521 | /* | |
1522 | * This is an architectural requirement for AArch64; AArch32 is | |
1523 | * more flexible and permits VFP-no-Neon and Neon-no-VFP. | |
1524 | */ | |
1525 | error_setg(errp, | |
1526 | "AArch64 CPUs must have both VFP and Neon or neither"); | |
1527 | return; | |
1528 | } | |
1529 | ||
1530 | if (!cpu->has_vfp) { | |
1531 | uint64_t t; | |
1532 | uint32_t u; | |
1533 | ||
97a28b0e PM |
1534 | t = cpu->isar.id_aa64isar1; |
1535 | t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); | |
1536 | cpu->isar.id_aa64isar1 = t; | |
1537 | ||
1538 | t = cpu->isar.id_aa64pfr0; | |
1539 | t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); | |
1540 | cpu->isar.id_aa64pfr0 = t; | |
1541 | ||
1542 | u = cpu->isar.id_isar6; | |
1543 | u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); | |
3c93dfa4 | 1544 | u = FIELD_DP32(u, ID_ISAR6, BF16, 0); |
97a28b0e PM |
1545 | cpu->isar.id_isar6 = u; |
1546 | ||
1547 | u = cpu->isar.mvfr0; | |
1548 | u = FIELD_DP32(u, MVFR0, FPSP, 0); | |
1549 | u = FIELD_DP32(u, MVFR0, FPDP, 0); | |
97a28b0e PM |
1550 | u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); |
1551 | u = FIELD_DP32(u, MVFR0, FPSQRT, 0); | |
97a28b0e | 1552 | u = FIELD_DP32(u, MVFR0, FPROUND, 0); |
532a3af5 PM |
1553 | if (!arm_feature(env, ARM_FEATURE_M)) { |
1554 | u = FIELD_DP32(u, MVFR0, FPTRAP, 0); | |
1555 | u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); | |
1556 | } | |
97a28b0e PM |
1557 | cpu->isar.mvfr0 = u; |
1558 | ||
1559 | u = cpu->isar.mvfr1; | |
1560 | u = FIELD_DP32(u, MVFR1, FPFTZ, 0); | |
1561 | u = FIELD_DP32(u, MVFR1, FPDNAN, 0); | |
1562 | u = FIELD_DP32(u, MVFR1, FPHP, 0); | |
532a3af5 PM |
1563 | if (arm_feature(env, ARM_FEATURE_M)) { |
1564 | u = FIELD_DP32(u, MVFR1, FP16, 0); | |
1565 | } | |
97a28b0e PM |
1566 | cpu->isar.mvfr1 = u; |
1567 | ||
1568 | u = cpu->isar.mvfr2; | |
1569 | u = FIELD_DP32(u, MVFR2, FPMISC, 0); | |
1570 | cpu->isar.mvfr2 = u; | |
1571 | } | |
1572 | ||
1573 | if (!cpu->has_neon) { | |
1574 | uint64_t t; | |
1575 | uint32_t u; | |
1576 | ||
1577 | unset_feature(env, ARM_FEATURE_NEON); | |
1578 | ||
1579 | t = cpu->isar.id_aa64isar0; | |
1580 | t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); | |
1581 | cpu->isar.id_aa64isar0 = t; | |
1582 | ||
1583 | t = cpu->isar.id_aa64isar1; | |
1584 | t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); | |
3c93dfa4 | 1585 | t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0); |
f8680aaa | 1586 | t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0); |
97a28b0e PM |
1587 | cpu->isar.id_aa64isar1 = t; |
1588 | ||
1589 | t = cpu->isar.id_aa64pfr0; | |
1590 | t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); | |
1591 | cpu->isar.id_aa64pfr0 = t; | |
1592 | ||
1593 | u = cpu->isar.id_isar5; | |
1594 | u = FIELD_DP32(u, ID_ISAR5, RDM, 0); | |
1595 | u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); | |
1596 | cpu->isar.id_isar5 = u; | |
1597 | ||
1598 | u = cpu->isar.id_isar6; | |
1599 | u = FIELD_DP32(u, ID_ISAR6, DP, 0); | |
1600 | u = FIELD_DP32(u, ID_ISAR6, FHM, 0); | |
3c93dfa4 | 1601 | u = FIELD_DP32(u, ID_ISAR6, BF16, 0); |
f8680aaa | 1602 | u = FIELD_DP32(u, ID_ISAR6, I8MM, 0); |
97a28b0e PM |
1603 | cpu->isar.id_isar6 = u; |
1604 | ||
532a3af5 PM |
1605 | if (!arm_feature(env, ARM_FEATURE_M)) { |
1606 | u = cpu->isar.mvfr1; | |
1607 | u = FIELD_DP32(u, MVFR1, SIMDLS, 0); | |
1608 | u = FIELD_DP32(u, MVFR1, SIMDINT, 0); | |
1609 | u = FIELD_DP32(u, MVFR1, SIMDSP, 0); | |
1610 | u = FIELD_DP32(u, MVFR1, SIMDHP, 0); | |
1611 | cpu->isar.mvfr1 = u; | |
1612 | ||
1613 | u = cpu->isar.mvfr2; | |
1614 | u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); | |
1615 | cpu->isar.mvfr2 = u; | |
1616 | } | |
97a28b0e PM |
1617 | } |
1618 | ||
1619 | if (!cpu->has_neon && !cpu->has_vfp) { | |
1620 | uint64_t t; | |
1621 | uint32_t u; | |
1622 | ||
1623 | t = cpu->isar.id_aa64isar0; | |
1624 | t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); | |
1625 | cpu->isar.id_aa64isar0 = t; | |
1626 | ||
1627 | t = cpu->isar.id_aa64isar1; | |
1628 | t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); | |
1629 | cpu->isar.id_aa64isar1 = t; | |
1630 | ||
1631 | u = cpu->isar.mvfr0; | |
1632 | u = FIELD_DP32(u, MVFR0, SIMDREG, 0); | |
1633 | cpu->isar.mvfr0 = u; | |
c52881bb RH |
1634 | |
1635 | /* Despite the name, this field covers both VFP and Neon */ | |
1636 | u = cpu->isar.mvfr1; | |
1637 | u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); | |
1638 | cpu->isar.mvfr1 = u; | |
97a28b0e PM |
1639 | } |
1640 | ||
ea90db0a PM |
1641 | if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { |
1642 | uint32_t u; | |
1643 | ||
1644 | unset_feature(env, ARM_FEATURE_THUMB_DSP); | |
1645 | ||
1646 | u = cpu->isar.id_isar1; | |
1647 | u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); | |
1648 | cpu->isar.id_isar1 = u; | |
1649 | ||
1650 | u = cpu->isar.id_isar2; | |
1651 | u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); | |
1652 | u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); | |
1653 | cpu->isar.id_isar2 = u; | |
1654 | ||
1655 | u = cpu->isar.id_isar3; | |
1656 | u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); | |
1657 | u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); | |
1658 | cpu->isar.id_isar3 = u; | |
1659 | } | |
1660 | ||
581be094 | 1661 | /* Some features automatically imply others: */ |
81e69fb0 | 1662 | if (arm_feature(env, ARM_FEATURE_V8)) { |
5256df88 RH |
1663 | if (arm_feature(env, ARM_FEATURE_M)) { |
1664 | set_feature(env, ARM_FEATURE_V7); | |
1665 | } else { | |
1666 | set_feature(env, ARM_FEATURE_V7VE); | |
1667 | } | |
5110e683 | 1668 | } |
0f8d06f1 RH |
1669 | |
1670 | /* | |
1671 | * There exist AArch64 cpus without AArch32 support. When KVM | |
1672 | * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. | |
1673 | * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. | |
8f4821d7 PM |
1674 | * As a general principle, we also do not make ID register |
1675 | * consistency checks anywhere unless using TCG, because only | |
1676 | * for TCG would a consistency-check failure be a QEMU bug. | |
0f8d06f1 RH |
1677 | */ |
1678 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
1679 | no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); | |
1680 | } | |
1681 | ||
5110e683 AL |
1682 | if (arm_feature(env, ARM_FEATURE_V7VE)) { |
1683 | /* v7 Virtualization Extensions. In real hardware this implies | |
1684 | * EL2 and also the presence of the Security Extensions. | |
1685 | * For QEMU, for backwards-compatibility we implement some | |
1686 | * CPUs or CPU configs which have no actual EL2 or EL3 but do | |
1687 | * include the various other features that V7VE implies. | |
1688 | * Presence of EL2 itself is ARM_FEATURE_EL2, and of the | |
1689 | * Security Extensions is ARM_FEATURE_EL3. | |
1690 | */ | |
873b73c0 PM |
1691 | assert(!tcg_enabled() || no_aa32 || |
1692 | cpu_isar_feature(aa32_arm_div, cpu)); | |
81e69fb0 | 1693 | set_feature(env, ARM_FEATURE_LPAE); |
5110e683 | 1694 | set_feature(env, ARM_FEATURE_V7); |
81e69fb0 | 1695 | } |
581be094 PM |
1696 | if (arm_feature(env, ARM_FEATURE_V7)) { |
1697 | set_feature(env, ARM_FEATURE_VAPA); | |
1698 | set_feature(env, ARM_FEATURE_THUMB2); | |
81bdde9d | 1699 | set_feature(env, ARM_FEATURE_MPIDR); |
581be094 PM |
1700 | if (!arm_feature(env, ARM_FEATURE_M)) { |
1701 | set_feature(env, ARM_FEATURE_V6K); | |
1702 | } else { | |
1703 | set_feature(env, ARM_FEATURE_V6); | |
1704 | } | |
91db4642 CLG |
1705 | |
1706 | /* Always define VBAR for V7 CPUs even if it doesn't exist in | |
1707 | * non-EL3 configs. This is needed by some legacy boards. | |
1708 | */ | |
1709 | set_feature(env, ARM_FEATURE_VBAR); | |
581be094 PM |
1710 | } |
1711 | if (arm_feature(env, ARM_FEATURE_V6K)) { | |
1712 | set_feature(env, ARM_FEATURE_V6); | |
1713 | set_feature(env, ARM_FEATURE_MVFR); | |
1714 | } | |
1715 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
1716 | set_feature(env, ARM_FEATURE_V5); | |
1717 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
873b73c0 PM |
1718 | assert(!tcg_enabled() || no_aa32 || |
1719 | cpu_isar_feature(aa32_jazelle, cpu)); | |
581be094 PM |
1720 | set_feature(env, ARM_FEATURE_AUXCR); |
1721 | } | |
1722 | } | |
1723 | if (arm_feature(env, ARM_FEATURE_V5)) { | |
1724 | set_feature(env, ARM_FEATURE_V4T); | |
1725 | } | |
de9b05b8 | 1726 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
bdcc150d | 1727 | set_feature(env, ARM_FEATURE_V7MP); |
de9b05b8 | 1728 | } |
f318cec6 PM |
1729 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { |
1730 | set_feature(env, ARM_FEATURE_CBAR); | |
1731 | } | |
62b44f05 AR |
1732 | if (arm_feature(env, ARM_FEATURE_THUMB2) && |
1733 | !arm_feature(env, ARM_FEATURE_M)) { | |
1734 | set_feature(env, ARM_FEATURE_THUMB_DSP); | |
1735 | } | |
2ceb98c0 | 1736 | |
ea7ac69d PM |
1737 | /* |
1738 | * We rely on no XScale CPU having VFP so we can use the same bits in the | |
1739 | * TB flags field for VECSTRIDE and XSCALE_CPAR. | |
1740 | */ | |
7d63183f RH |
1741 | assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || |
1742 | !cpu_isar_feature(aa32_vfp_simd, cpu) || | |
1743 | !arm_feature(env, ARM_FEATURE_XSCALE)); | |
ea7ac69d | 1744 | |
e97da98f PM |
1745 | if (arm_feature(env, ARM_FEATURE_V7) && |
1746 | !arm_feature(env, ARM_FEATURE_M) && | |
452a0955 | 1747 | !arm_feature(env, ARM_FEATURE_PMSA)) { |
e97da98f PM |
1748 | /* v7VMSA drops support for the old ARMv5 tiny pages, so we |
1749 | * can use 4K pages. | |
1750 | */ | |
1751 | pagebits = 12; | |
1752 | } else { | |
1753 | /* For CPUs which might have tiny 1K pages, or which have an | |
1754 | * MPU and might have small region sizes, stick with 1K pages. | |
1755 | */ | |
1756 | pagebits = 10; | |
1757 | } | |
1758 | if (!set_preferred_target_page_bits(pagebits)) { | |
1759 | /* This can only ever happen for hotplugging a CPU, or if | |
1760 | * the board code incorrectly creates a CPU which it has | |
1761 | * promised via minimum_page_size that it will not. | |
1762 | */ | |
1763 | error_setg(errp, "This CPU requires a smaller page size than the " | |
1764 | "system is using"); | |
1765 | return; | |
1766 | } | |
1767 | ||
ce5b1bbf LV |
1768 | /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. |
1769 | * We don't support setting cluster ID ([16..23]) (known as Aff2 | |
1770 | * in later ARM ARM versions), or any of the higher affinity level fields, | |
1771 | * so these bits always RAZ. | |
1772 | */ | |
1773 | if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { | |
46de5913 IM |
1774 | cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, |
1775 | ARM_DEFAULT_CPUS_PER_CLUSTER); | |
ce5b1bbf LV |
1776 | } |
1777 | ||
68e0a40a AP |
1778 | if (cpu->reset_hivecs) { |
1779 | cpu->reset_sctlr |= (1 << 13); | |
1780 | } | |
1781 | ||
3a062d57 JB |
1782 | if (cpu->cfgend) { |
1783 | if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { | |
1784 | cpu->reset_sctlr |= SCTLR_EE; | |
1785 | } else { | |
1786 | cpu->reset_sctlr |= SCTLR_B; | |
1787 | } | |
1788 | } | |
1789 | ||
40188188 | 1790 | if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { |
51942aee GB |
1791 | /* If the has_el3 CPU property is disabled then we need to disable the |
1792 | * feature. | |
1793 | */ | |
1794 | unset_feature(env, ARM_FEATURE_EL3); | |
1795 | ||
1796 | /* Disable the security extension feature bits in the processor feature | |
3d5c84ff | 1797 | * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. |
51942aee | 1798 | */ |
8a130a7b | 1799 | cpu->isar.id_pfr1 &= ~0xf0; |
47576b94 | 1800 | cpu->isar.id_aa64pfr0 &= ~0xf000; |
51942aee GB |
1801 | } |
1802 | ||
c25bd18a PM |
1803 | if (!cpu->has_el2) { |
1804 | unset_feature(env, ARM_FEATURE_EL2); | |
1805 | } | |
1806 | ||
d6f02ce3 | 1807 | if (!cpu->has_pmu) { |
929e754d | 1808 | unset_feature(env, ARM_FEATURE_PMU); |
57a4a11b AL |
1809 | } |
1810 | if (arm_feature(env, ARM_FEATURE_PMU)) { | |
bf8d0969 | 1811 | pmu_init(cpu); |
57a4a11b AL |
1812 | |
1813 | if (!kvm_enabled()) { | |
1814 | arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); | |
1815 | arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); | |
1816 | } | |
4e7beb0c AL |
1817 | |
1818 | #ifndef CONFIG_USER_ONLY | |
1819 | cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, | |
1820 | cpu); | |
1821 | #endif | |
57a4a11b | 1822 | } else { |
2a609df8 PM |
1823 | cpu->isar.id_aa64dfr0 = |
1824 | FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); | |
a6179538 | 1825 | cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); |
57a4a11b AL |
1826 | cpu->pmceid0 = 0; |
1827 | cpu->pmceid1 = 0; | |
929e754d WH |
1828 | } |
1829 | ||
3c2f7bb3 PM |
1830 | if (!arm_feature(env, ARM_FEATURE_EL2)) { |
1831 | /* Disable the hypervisor feature bits in the processor feature | |
1832 | * registers if we don't have EL2. These are id_pfr1[15:12] and | |
1833 | * id_aa64pfr0_el1[11:8]. | |
1834 | */ | |
47576b94 | 1835 | cpu->isar.id_aa64pfr0 &= ~0xf00; |
8a130a7b | 1836 | cpu->isar.id_pfr1 &= ~0xf000; |
3c2f7bb3 PM |
1837 | } |
1838 | ||
6f4e1405 RH |
1839 | #ifndef CONFIG_USER_ONLY |
1840 | if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { | |
1841 | /* | |
1842 | * Disable the MTE feature bits if we do not have tag-memory | |
1843 | * provided by the machine. | |
1844 | */ | |
1845 | cpu->isar.id_aa64pfr1 = | |
1846 | FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); | |
1847 | } | |
1848 | #endif | |
1849 | ||
f50cd314 PM |
1850 | /* MPU can be configured out of a PMSA CPU either by setting has-mpu |
1851 | * to false or by setting pmsav7-dregion to 0. | |
1852 | */ | |
8f325f56 | 1853 | if (!cpu->has_mpu) { |
f50cd314 PM |
1854 | cpu->pmsav7_dregion = 0; |
1855 | } | |
1856 | if (cpu->pmsav7_dregion == 0) { | |
1857 | cpu->has_mpu = false; | |
8f325f56 PC |
1858 | } |
1859 | ||
452a0955 | 1860 | if (arm_feature(env, ARM_FEATURE_PMSA) && |
3281af81 PC |
1861 | arm_feature(env, ARM_FEATURE_V7)) { |
1862 | uint32_t nr = cpu->pmsav7_dregion; | |
1863 | ||
1864 | if (nr > 0xff) { | |
9af9e0fe | 1865 | error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); |
3281af81 PC |
1866 | return; |
1867 | } | |
6cb0b013 PC |
1868 | |
1869 | if (nr) { | |
0e1a46bb PM |
1870 | if (arm_feature(env, ARM_FEATURE_V8)) { |
1871 | /* PMSAv8 */ | |
62c58ee0 PM |
1872 | env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); |
1873 | env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); | |
1874 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
1875 | env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); | |
1876 | env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); | |
1877 | } | |
0e1a46bb PM |
1878 | } else { |
1879 | env->pmsav7.drbar = g_new0(uint32_t, nr); | |
1880 | env->pmsav7.drsr = g_new0(uint32_t, nr); | |
1881 | env->pmsav7.dracr = g_new0(uint32_t, nr); | |
1882 | } | |
6cb0b013 | 1883 | } |
3281af81 PC |
1884 | } |
1885 | ||
9901c576 PM |
1886 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
1887 | uint32_t nr = cpu->sau_sregion; | |
1888 | ||
1889 | if (nr > 0xff) { | |
1890 | error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); | |
1891 | return; | |
1892 | } | |
1893 | ||
1894 | if (nr) { | |
1895 | env->sau.rbar = g_new0(uint32_t, nr); | |
1896 | env->sau.rlar = g_new0(uint32_t, nr); | |
1897 | } | |
1898 | } | |
1899 | ||
91db4642 CLG |
1900 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
1901 | set_feature(env, ARM_FEATURE_VBAR); | |
1902 | } | |
1903 | ||
2ceb98c0 | 1904 | register_cp_regs_for_features(cpu); |
14969266 AF |
1905 | arm_cpu_register_gdb_regs_for_features(cpu); |
1906 | ||
721fae12 PM |
1907 | init_cpreg_list(cpu); |
1908 | ||
9e273ef2 | 1909 | #ifndef CONFIG_USER_ONLY |
cc7d44c2 LX |
1910 | MachineState *ms = MACHINE(qdev_get_machine()); |
1911 | unsigned int smp_cpus = ms->smp.cpus; | |
8bce44a2 | 1912 | bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY); |
cc7d44c2 | 1913 | |
8bce44a2 RH |
1914 | /* |
1915 | * We must set cs->num_ases to the final value before | |
1916 | * the first call to cpu_address_space_init. | |
1917 | */ | |
1918 | if (cpu->tag_memory != NULL) { | |
1919 | cs->num_ases = 3 + has_secure; | |
1920 | } else { | |
1921 | cs->num_ases = 1 + has_secure; | |
1922 | } | |
1d2091bc | 1923 | |
8bce44a2 | 1924 | if (has_secure) { |
9e273ef2 PM |
1925 | if (!cpu->secure_memory) { |
1926 | cpu->secure_memory = cs->memory; | |
1927 | } | |
80ceb07a PX |
1928 | cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", |
1929 | cpu->secure_memory); | |
9e273ef2 | 1930 | } |
8bce44a2 RH |
1931 | |
1932 | if (cpu->tag_memory != NULL) { | |
1933 | cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory", | |
1934 | cpu->tag_memory); | |
1935 | if (has_secure) { | |
1936 | cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory", | |
1937 | cpu->secure_tag_memory); | |
1938 | } | |
8bce44a2 RH |
1939 | } |
1940 | ||
80ceb07a | 1941 | cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); |
f9a69711 AF |
1942 | |
1943 | /* No core_count specified, default to smp_cpus. */ | |
1944 | if (cpu->core_count == -1) { | |
1945 | cpu->core_count = smp_cpus; | |
1946 | } | |
9e273ef2 PM |
1947 | #endif |
1948 | ||
a4157b80 RH |
1949 | if (tcg_enabled()) { |
1950 | int dcz_blocklen = 4 << cpu->dcz_blocksize; | |
1951 | ||
1952 | /* | |
1953 | * We only support DCZ blocklen that fits on one page. | |
1954 | * | |
1955 | * Architectually this is always true. However TARGET_PAGE_SIZE | |
1956 | * is variable and, for compatibility with -machine virt-2.7, | |
1957 | * is only 1KiB, as an artifact of legacy ARMv5 subpage support. | |
1958 | * But even then, while the largest architectural DCZ blocklen | |
1959 | * is 2KiB, no cpu actually uses such a large blocklen. | |
1960 | */ | |
1961 | assert(dcz_blocklen <= TARGET_PAGE_SIZE); | |
1962 | ||
1963 | /* | |
1964 | * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say | |
1965 | * both nibbles of each byte storing tag data may be written at once. | |
1966 | * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. | |
1967 | */ | |
1968 | if (cpu_isar_feature(aa64_mte, cpu)) { | |
1969 | assert(dcz_blocklen >= 2 * TAG_GRANULE); | |
1970 | } | |
1971 | } | |
1972 | ||
14a10fc3 | 1973 | qemu_init_vcpu(cs); |
00d0f7cb | 1974 | cpu_reset(cs); |
14969266 AF |
1975 | |
1976 | acc->parent_realize(dev, errp); | |
581be094 PM |
1977 | } |
1978 | ||
5900d6b2 AF |
1979 | static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) |
1980 | { | |
1981 | ObjectClass *oc; | |
51492fd1 | 1982 | char *typename; |
fb8d6c24 | 1983 | char **cpuname; |
a0032cc5 | 1984 | const char *cpunamestr; |
5900d6b2 | 1985 | |
fb8d6c24 | 1986 | cpuname = g_strsplit(cpu_model, ",", 1); |
a0032cc5 PM |
1987 | cpunamestr = cpuname[0]; |
1988 | #ifdef CONFIG_USER_ONLY | |
1989 | /* For backwards compatibility usermode emulation allows "-cpu any", | |
1990 | * which has the same semantics as "-cpu max". | |
1991 | */ | |
1992 | if (!strcmp(cpunamestr, "any")) { | |
1993 | cpunamestr = "max"; | |
1994 | } | |
1995 | #endif | |
1996 | typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); | |
51492fd1 | 1997 | oc = object_class_by_name(typename); |
fb8d6c24 | 1998 | g_strfreev(cpuname); |
51492fd1 | 1999 | g_free(typename); |
245fb54d AF |
2000 | if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || |
2001 | object_class_is_abstract(oc)) { | |
5900d6b2 AF |
2002 | return NULL; |
2003 | } | |
2004 | return oc; | |
2005 | } | |
2006 | ||
5de16430 | 2007 | static Property arm_cpu_properties[] = { |
e544f800 | 2008 | DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), |
ce5b1bbf LV |
2009 | DEFINE_PROP_UINT64("mp-affinity", ARMCPU, |
2010 | mp_affinity, ARM64_AFFINITY_INVALID), | |
15f8b142 | 2011 | DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), |
f9a69711 | 2012 | DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), |
5de16430 PM |
2013 | DEFINE_PROP_END_OF_LIST() |
2014 | }; | |
2015 | ||
b3820e6c DH |
2016 | static gchar *arm_gdb_arch_name(CPUState *cs) |
2017 | { | |
2018 | ARMCPU *cpu = ARM_CPU(cs); | |
2019 | CPUARMState *env = &cpu->env; | |
2020 | ||
2021 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
2022 | return g_strdup("iwmmxt"); | |
2023 | } | |
2024 | return g_strdup("arm"); | |
2025 | } | |
2026 | ||
8b80bd28 PMD |
2027 | #ifndef CONFIG_USER_ONLY |
2028 | #include "hw/core/sysemu-cpu-ops.h" | |
2029 | ||
2030 | static const struct SysemuCPUOps arm_sysemu_ops = { | |
08928c6d | 2031 | .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug, |
faf39e82 | 2032 | .asidx_from_attrs = arm_asidx_from_attrs, |
715e3c1a PMD |
2033 | .write_elf32_note = arm_cpu_write_elf32_note, |
2034 | .write_elf64_note = arm_cpu_write_elf64_note, | |
da383e02 | 2035 | .virtio_is_big_endian = arm_cpu_virtio_is_big_endian, |
feece4d0 | 2036 | .legacy_vmsd = &vmstate_arm_cpu, |
8b80bd28 PMD |
2037 | }; |
2038 | #endif | |
2039 | ||
78271684 | 2040 | #ifdef CONFIG_TCG |
11906557 | 2041 | static const struct TCGCPUOps arm_tcg_ops = { |
78271684 CF |
2042 | .initialize = arm_translate_init, |
2043 | .synchronize_from_tb = arm_cpu_synchronize_from_tb, | |
78271684 CF |
2044 | .debug_excp_handler = arm_debug_excp_handler, |
2045 | ||
9b12b6b4 RH |
2046 | #ifdef CONFIG_USER_ONLY |
2047 | .record_sigsegv = arm_cpu_record_sigsegv, | |
39a099ca | 2048 | .record_sigbus = arm_cpu_record_sigbus, |
9b12b6b4 RH |
2049 | #else |
2050 | .tlb_fill = arm_cpu_tlb_fill, | |
083afd18 | 2051 | .cpu_exec_interrupt = arm_cpu_exec_interrupt, |
78271684 CF |
2052 | .do_interrupt = arm_cpu_do_interrupt, |
2053 | .do_transaction_failed = arm_cpu_do_transaction_failed, | |
2054 | .do_unaligned_access = arm_cpu_do_unaligned_access, | |
2055 | .adjust_watchpoint_address = arm_adjust_watchpoint_address, | |
2056 | .debug_check_watchpoint = arm_debug_check_watchpoint, | |
b00d86bc | 2057 | .debug_check_breakpoint = arm_debug_check_breakpoint, |
78271684 CF |
2058 | #endif /* !CONFIG_USER_ONLY */ |
2059 | }; | |
2060 | #endif /* CONFIG_TCG */ | |
2061 | ||
dec9c2d4 AF |
2062 | static void arm_cpu_class_init(ObjectClass *oc, void *data) |
2063 | { | |
2064 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
2065 | CPUClass *cc = CPU_CLASS(acc); | |
14969266 AF |
2066 | DeviceClass *dc = DEVICE_CLASS(oc); |
2067 | ||
bf853881 PMD |
2068 | device_class_set_parent_realize(dc, arm_cpu_realizefn, |
2069 | &acc->parent_realize); | |
dec9c2d4 | 2070 | |
4f67d30b | 2071 | device_class_set_props(dc, arm_cpu_properties); |
781c67ca | 2072 | device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); |
5900d6b2 AF |
2073 | |
2074 | cc->class_by_name = arm_cpu_class_by_name; | |
8c2e1b00 | 2075 | cc->has_work = arm_cpu_has_work; |
878096ee | 2076 | cc->dump_state = arm_cpu_dump_state; |
f45748f1 | 2077 | cc->set_pc = arm_cpu_set_pc; |
5b50e790 AF |
2078 | cc->gdb_read_register = arm_cpu_gdb_read_register; |
2079 | cc->gdb_write_register = arm_cpu_gdb_write_register; | |
7350d553 | 2080 | #ifndef CONFIG_USER_ONLY |
8b80bd28 | 2081 | cc->sysemu_ops = &arm_sysemu_ops; |
00b941e5 | 2082 | #endif |
a0e372f0 | 2083 | cc->gdb_num_core_regs = 26; |
5b24c641 | 2084 | cc->gdb_core_xml_file = "arm-core.xml"; |
b3820e6c | 2085 | cc->gdb_arch_name = arm_gdb_arch_name; |
200bf5b7 | 2086 | cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; |
2472b6c0 | 2087 | cc->gdb_stop_before_watchpoint = true; |
48440620 | 2088 | cc->disas_set_info = arm_disas_set_info; |
78271684 | 2089 | |
74d7fc7f | 2090 | #ifdef CONFIG_TCG |
78271684 | 2091 | cc->tcg_ops = &arm_tcg_ops; |
cbc183d2 | 2092 | #endif /* CONFIG_TCG */ |
dec9c2d4 AF |
2093 | } |
2094 | ||
51e5ef45 MAL |
2095 | static void arm_cpu_instance_init(Object *obj) |
2096 | { | |
2097 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); | |
2098 | ||
2099 | acc->info->initfn(obj); | |
2100 | arm_cpu_post_init(obj); | |
2101 | } | |
2102 | ||
2103 | static void cpu_register_class_init(ObjectClass *oc, void *data) | |
2104 | { | |
2105 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
2106 | ||
2107 | acc->info = data; | |
2108 | } | |
2109 | ||
37bcf244 | 2110 | void arm_cpu_register(const ARMCPUInfo *info) |
777dc784 PM |
2111 | { |
2112 | TypeInfo type_info = { | |
777dc784 PM |
2113 | .parent = TYPE_ARM_CPU, |
2114 | .instance_size = sizeof(ARMCPU), | |
d03087bd | 2115 | .instance_align = __alignof__(ARMCPU), |
51e5ef45 | 2116 | .instance_init = arm_cpu_instance_init, |
777dc784 | 2117 | .class_size = sizeof(ARMCPUClass), |
51e5ef45 MAL |
2118 | .class_init = info->class_init ?: cpu_register_class_init, |
2119 | .class_data = (void *)info, | |
777dc784 PM |
2120 | }; |
2121 | ||
51492fd1 | 2122 | type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); |
918fd083 | 2123 | type_register(&type_info); |
51492fd1 | 2124 | g_free((void *)type_info.name); |
777dc784 PM |
2125 | } |
2126 | ||
dec9c2d4 AF |
2127 | static const TypeInfo arm_cpu_type_info = { |
2128 | .name = TYPE_ARM_CPU, | |
2129 | .parent = TYPE_CPU, | |
2130 | .instance_size = sizeof(ARMCPU), | |
d03087bd | 2131 | .instance_align = __alignof__(ARMCPU), |
777dc784 | 2132 | .instance_init = arm_cpu_initfn, |
4b6a83fb | 2133 | .instance_finalize = arm_cpu_finalizefn, |
777dc784 | 2134 | .abstract = true, |
dec9c2d4 AF |
2135 | .class_size = sizeof(ARMCPUClass), |
2136 | .class_init = arm_cpu_class_init, | |
2137 | }; | |
2138 | ||
2139 | static void arm_cpu_register_types(void) | |
2140 | { | |
2141 | type_register_static(&arm_cpu_type_info); | |
2142 | } | |
2143 | ||
2144 | type_init(arm_cpu_register_types) |