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dec9c2d4 AF |
1 | /* |
2 | * QEMU ARM CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
74c21bd0 | 21 | #include "qemu/osdep.h" |
86480615 | 22 | #include "qemu/qemu-print.h" |
a8d25326 | 23 | #include "qemu-common.h" |
181962fd | 24 | #include "target/arm/idau.h" |
0b8fa32f | 25 | #include "qemu/module.h" |
da34e65c | 26 | #include "qapi/error.h" |
f9f62e4c | 27 | #include "qapi/visitor.h" |
778c3a06 | 28 | #include "cpu.h" |
ccd38087 | 29 | #include "internals.h" |
63c91552 | 30 | #include "exec/exec-all.h" |
5de16430 | 31 | #include "hw/qdev-properties.h" |
3c30dd5a PM |
32 | #if !defined(CONFIG_USER_ONLY) |
33 | #include "hw/loader.h" | |
cc7d44c2 | 34 | #include "hw/boards.h" |
3c30dd5a | 35 | #endif |
9c17d615 | 36 | #include "sysemu/sysemu.h" |
14a48c1d | 37 | #include "sysemu/tcg.h" |
b3946626 | 38 | #include "sysemu/hw_accel.h" |
50a2c6e5 | 39 | #include "kvm_arm.h" |
110f6c70 | 40 | #include "disas/capstone.h" |
24f91e81 | 41 | #include "fpu/softfloat.h" |
dec9c2d4 | 42 | |
f45748f1 AF |
43 | static void arm_cpu_set_pc(CPUState *cs, vaddr value) |
44 | { | |
45 | ARMCPU *cpu = ARM_CPU(cs); | |
42f6ed91 JS |
46 | CPUARMState *env = &cpu->env; |
47 | ||
48 | if (is_a64(env)) { | |
49 | env->pc = value; | |
50 | env->thumb = 0; | |
51 | } else { | |
52 | env->regs[15] = value & ~1; | |
53 | env->thumb = value & 1; | |
54 | } | |
55 | } | |
f45748f1 | 56 | |
42f6ed91 JS |
57 | static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) |
58 | { | |
59 | ARMCPU *cpu = ARM_CPU(cs); | |
60 | CPUARMState *env = &cpu->env; | |
61 | ||
62 | /* | |
63 | * It's OK to look at env for the current mode here, because it's | |
64 | * never possible for an AArch64 TB to chain to an AArch32 TB. | |
65 | */ | |
66 | if (is_a64(env)) { | |
67 | env->pc = tb->pc; | |
68 | } else { | |
69 | env->regs[15] = tb->pc; | |
70 | } | |
f45748f1 AF |
71 | } |
72 | ||
8c2e1b00 AF |
73 | static bool arm_cpu_has_work(CPUState *cs) |
74 | { | |
543486db RH |
75 | ARMCPU *cpu = ARM_CPU(cs); |
76 | ||
062ba099 | 77 | return (cpu->power_state != PSCI_OFF) |
543486db | 78 | && cs->interrupt_request & |
136e67e9 EI |
79 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD |
80 | | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | |
81 | | CPU_INTERRUPT_EXITTB); | |
8c2e1b00 AF |
82 | } |
83 | ||
b5c53d1b AL |
84 | void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
85 | void *opaque) | |
86 | { | |
87 | ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); | |
88 | ||
89 | entry->hook = hook; | |
90 | entry->opaque = opaque; | |
91 | ||
92 | QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); | |
93 | } | |
94 | ||
08267487 | 95 | void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
bd7d00fc PM |
96 | void *opaque) |
97 | { | |
08267487 AL |
98 | ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); |
99 | ||
100 | entry->hook = hook; | |
101 | entry->opaque = opaque; | |
102 | ||
103 | QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); | |
bd7d00fc PM |
104 | } |
105 | ||
4b6a83fb PM |
106 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
107 | { | |
108 | /* Reset a single ARMCPRegInfo register */ | |
109 | ARMCPRegInfo *ri = value; | |
110 | ARMCPU *cpu = opaque; | |
111 | ||
b061a82b | 112 | if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { |
4b6a83fb PM |
113 | return; |
114 | } | |
115 | ||
116 | if (ri->resetfn) { | |
117 | ri->resetfn(&cpu->env, ri); | |
118 | return; | |
119 | } | |
120 | ||
121 | /* A zero offset is never possible as it would be regs[0] | |
122 | * so we use it to indicate that reset is being handled elsewhere. | |
123 | * This is basically only used for fields in non-core coprocessors | |
124 | * (like the pxa2xx ones). | |
125 | */ | |
126 | if (!ri->fieldoffset) { | |
127 | return; | |
128 | } | |
129 | ||
67ed771d | 130 | if (cpreg_field_is_64bit(ri)) { |
4b6a83fb PM |
131 | CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; |
132 | } else { | |
133 | CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; | |
134 | } | |
135 | } | |
136 | ||
49a66191 PM |
137 | static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) |
138 | { | |
139 | /* Purely an assertion check: we've already done reset once, | |
140 | * so now check that running the reset for the cpreg doesn't | |
141 | * change its value. This traps bugs where two different cpregs | |
142 | * both try to reset the same state field but to different values. | |
143 | */ | |
144 | ARMCPRegInfo *ri = value; | |
145 | ARMCPU *cpu = opaque; | |
146 | uint64_t oldvalue, newvalue; | |
147 | ||
148 | if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { | |
149 | return; | |
150 | } | |
151 | ||
152 | oldvalue = read_raw_cp_reg(&cpu->env, ri); | |
153 | cp_reg_reset(key, value, opaque); | |
154 | newvalue = read_raw_cp_reg(&cpu->env, ri); | |
155 | assert(oldvalue == newvalue); | |
156 | } | |
157 | ||
781c67ca | 158 | static void arm_cpu_reset(DeviceState *dev) |
dec9c2d4 | 159 | { |
781c67ca | 160 | CPUState *s = CPU(dev); |
dec9c2d4 AF |
161 | ARMCPU *cpu = ARM_CPU(s); |
162 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); | |
3c30dd5a | 163 | CPUARMState *env = &cpu->env; |
3c30dd5a | 164 | |
781c67ca | 165 | acc->parent_reset(dev); |
dec9c2d4 | 166 | |
1f5c00cf AB |
167 | memset(env, 0, offsetof(CPUARMState, end_reset_fields)); |
168 | ||
4b6a83fb | 169 | g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
49a66191 PM |
170 | g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); |
171 | ||
3c30dd5a | 172 | env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
47576b94 RH |
173 | env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; |
174 | env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; | |
175 | env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; | |
3c30dd5a | 176 | |
062ba099 | 177 | cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; |
543486db RH |
178 | s->halted = cpu->start_powered_off; |
179 | ||
3c30dd5a PM |
180 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { |
181 | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; | |
182 | } | |
183 | ||
3926cc84 AG |
184 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
185 | /* 64 bit CPUs always start in 64 bit mode */ | |
186 | env->aarch64 = 1; | |
d356312f PM |
187 | #if defined(CONFIG_USER_ONLY) |
188 | env->pstate = PSTATE_MODE_EL0t; | |
14e5f106 | 189 | /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ |
137feaa9 | 190 | env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; |
276c6e81 RH |
191 | /* Enable all PAC keys. */ |
192 | env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB | | |
193 | SCTLR_EnDA | SCTLR_EnDB); | |
8c6afa6a | 194 | /* and to the FP/Neon instructions */ |
7ebd5f2e | 195 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); |
802ac0e1 RH |
196 | /* and to the SVE instructions */ |
197 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); | |
7b6a2198 AB |
198 | /* with reasonable vector length */ |
199 | if (cpu_isar_feature(aa64_sve, cpu)) { | |
200 | env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3); | |
201 | } | |
f6a148fe RH |
202 | /* |
203 | * Enable TBI0 and TBI1. While the real kernel only enables TBI0, | |
204 | * turning on both here will produce smaller code and otherwise | |
205 | * make no difference to the user-level emulation. | |
c4af8ba1 RH |
206 | * |
207 | * In sve_probe_page, we assume that this is set. | |
208 | * Do not modify this without other changes. | |
f6a148fe RH |
209 | */ |
210 | env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); | |
d356312f | 211 | #else |
5097227c GB |
212 | /* Reset into the highest available EL */ |
213 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
214 | env->pstate = PSTATE_MODE_EL3h; | |
215 | } else if (arm_feature(env, ARM_FEATURE_EL2)) { | |
216 | env->pstate = PSTATE_MODE_EL2h; | |
217 | } else { | |
218 | env->pstate = PSTATE_MODE_EL1h; | |
219 | } | |
3933443e | 220 | env->pc = cpu->rvbar; |
8c6afa6a PM |
221 | #endif |
222 | } else { | |
223 | #if defined(CONFIG_USER_ONLY) | |
224 | /* Userspace expects access to cp10 and cp11 for FP/Neon */ | |
7ebd5f2e | 225 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); |
d356312f | 226 | #endif |
3926cc84 AG |
227 | } |
228 | ||
3c30dd5a PM |
229 | #if defined(CONFIG_USER_ONLY) |
230 | env->uncached_cpsr = ARM_CPU_MODE_USR; | |
231 | /* For user mode we must enable access to coprocessors */ | |
232 | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; | |
233 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
234 | env->cp15.c15_cpar = 3; | |
235 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
236 | env->cp15.c15_cpar = 1; | |
237 | } | |
238 | #else | |
060a65df PM |
239 | |
240 | /* | |
241 | * If the highest available EL is EL2, AArch32 will start in Hyp | |
242 | * mode; otherwise it starts in SVC. Note that if we start in | |
243 | * AArch64 then these values in the uncached_cpsr will be ignored. | |
244 | */ | |
245 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
246 | !arm_feature(env, ARM_FEATURE_EL3)) { | |
247 | env->uncached_cpsr = ARM_CPU_MODE_HYP; | |
248 | } else { | |
249 | env->uncached_cpsr = ARM_CPU_MODE_SVC; | |
250 | } | |
4cc35614 | 251 | env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; |
dc7abe4d | 252 | |
531c60a9 | 253 | if (arm_feature(env, ARM_FEATURE_M)) { |
6e3cf5df MG |
254 | uint32_t initial_msp; /* Loaded from 0x0 */ |
255 | uint32_t initial_pc; /* Loaded from 0x4 */ | |
3c30dd5a | 256 | uint8_t *rom; |
38e2a77c | 257 | uint32_t vecbase; |
6e3cf5df | 258 | |
1e577cc7 PM |
259 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
260 | env->v7m.secure = true; | |
3b2e9344 PM |
261 | } else { |
262 | /* This bit resets to 0 if security is supported, but 1 if | |
263 | * it is not. The bit is not present in v7M, but we set it | |
264 | * here so we can avoid having to make checks on it conditional | |
265 | * on ARM_FEATURE_V8 (we don't let the guest see the bit). | |
266 | */ | |
267 | env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; | |
02ac2f7f PM |
268 | /* |
269 | * Set NSACR to indicate "NS access permitted to everything"; | |
270 | * this avoids having to have all the tests of it being | |
271 | * conditional on ARM_FEATURE_M_SECURITY. Note also that from | |
272 | * v8.1M the guest-visible value of NSACR in a CPU without the | |
273 | * Security Extension is 0xcff. | |
274 | */ | |
275 | env->v7m.nsacr = 0xcff; | |
1e577cc7 PM |
276 | } |
277 | ||
9d40cd8a | 278 | /* In v7M the reset value of this bit is IMPDEF, but ARM recommends |
2c4da50d | 279 | * that it resets to 1, so QEMU always does that rather than making |
9d40cd8a | 280 | * it dependent on CPU model. In v8M it is RES1. |
2c4da50d | 281 | */ |
9d40cd8a PM |
282 | env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; |
283 | env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; | |
284 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
285 | /* in v8M the NONBASETHRDENA bit [0] is RES1 */ | |
286 | env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; | |
287 | env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; | |
288 | } | |
22ab3460 JS |
289 | if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { |
290 | env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; | |
291 | env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; | |
292 | } | |
2c4da50d | 293 | |
7fbc6a40 | 294 | if (cpu_isar_feature(aa32_vfp_simd, cpu)) { |
d33abe82 PM |
295 | env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; |
296 | env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | | |
297 | R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; | |
298 | } | |
056f43df PM |
299 | /* Unlike A/R profile, M profile defines the reset LR value */ |
300 | env->regs[14] = 0xffffffff; | |
301 | ||
38e2a77c PM |
302 | env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; |
303 | ||
304 | /* Load the initial SP and PC from offset 0 and 4 in the vector table */ | |
305 | vecbase = env->v7m.vecbase[env->v7m.secure]; | |
0f0f8b61 | 306 | rom = rom_ptr(vecbase, 8); |
3c30dd5a | 307 | if (rom) { |
6e3cf5df MG |
308 | /* Address zero is covered by ROM which hasn't yet been |
309 | * copied into physical memory. | |
310 | */ | |
311 | initial_msp = ldl_p(rom); | |
312 | initial_pc = ldl_p(rom + 4); | |
313 | } else { | |
314 | /* Address zero not covered by a ROM blob, or the ROM blob | |
315 | * is in non-modifiable memory and this is a second reset after | |
316 | * it got copied into memory. In the latter case, rom_ptr | |
317 | * will return a NULL pointer and we should use ldl_phys instead. | |
318 | */ | |
38e2a77c PM |
319 | initial_msp = ldl_phys(s->as, vecbase); |
320 | initial_pc = ldl_phys(s->as, vecbase + 4); | |
3c30dd5a | 321 | } |
6e3cf5df MG |
322 | |
323 | env->regs[13] = initial_msp & 0xFFFFFFFC; | |
324 | env->regs[15] = initial_pc & ~1; | |
325 | env->thumb = initial_pc & 1; | |
3c30dd5a | 326 | } |
387f9806 | 327 | |
137feaa9 FA |
328 | /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently |
329 | * executing as AArch32 then check if highvecs are enabled and | |
330 | * adjust the PC accordingly. | |
331 | */ | |
332 | if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { | |
34bf7744 | 333 | env->regs[15] = 0xFFFF0000; |
387f9806 AP |
334 | } |
335 | ||
dc3c4c14 PM |
336 | /* M profile requires that reset clears the exclusive monitor; |
337 | * A profile does not, but clearing it makes more sense than having it | |
338 | * set with an exclusive access on address zero. | |
339 | */ | |
340 | arm_clear_exclusive(env); | |
341 | ||
3c30dd5a | 342 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; |
3c30dd5a | 343 | #endif |
69ceea64 | 344 | |
0e1a46bb | 345 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
69ceea64 | 346 | if (cpu->pmsav7_dregion > 0) { |
0e1a46bb | 347 | if (arm_feature(env, ARM_FEATURE_V8)) { |
62c58ee0 PM |
348 | memset(env->pmsav8.rbar[M_REG_NS], 0, |
349 | sizeof(*env->pmsav8.rbar[M_REG_NS]) | |
350 | * cpu->pmsav7_dregion); | |
351 | memset(env->pmsav8.rlar[M_REG_NS], 0, | |
352 | sizeof(*env->pmsav8.rlar[M_REG_NS]) | |
353 | * cpu->pmsav7_dregion); | |
354 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
355 | memset(env->pmsav8.rbar[M_REG_S], 0, | |
356 | sizeof(*env->pmsav8.rbar[M_REG_S]) | |
357 | * cpu->pmsav7_dregion); | |
358 | memset(env->pmsav8.rlar[M_REG_S], 0, | |
359 | sizeof(*env->pmsav8.rlar[M_REG_S]) | |
360 | * cpu->pmsav7_dregion); | |
361 | } | |
0e1a46bb PM |
362 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
363 | memset(env->pmsav7.drbar, 0, | |
364 | sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); | |
365 | memset(env->pmsav7.drsr, 0, | |
366 | sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); | |
367 | memset(env->pmsav7.dracr, 0, | |
368 | sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); | |
369 | } | |
69ceea64 | 370 | } |
1bc04a88 PM |
371 | env->pmsav7.rnr[M_REG_NS] = 0; |
372 | env->pmsav7.rnr[M_REG_S] = 0; | |
4125e6fe PM |
373 | env->pmsav8.mair0[M_REG_NS] = 0; |
374 | env->pmsav8.mair0[M_REG_S] = 0; | |
375 | env->pmsav8.mair1[M_REG_NS] = 0; | |
376 | env->pmsav8.mair1[M_REG_S] = 0; | |
69ceea64 PM |
377 | } |
378 | ||
9901c576 PM |
379 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
380 | if (cpu->sau_sregion > 0) { | |
381 | memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); | |
382 | memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); | |
383 | } | |
384 | env->sau.rnr = 0; | |
385 | /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what | |
386 | * the Cortex-M33 does. | |
387 | */ | |
388 | env->sau.ctrl = 0; | |
389 | } | |
390 | ||
3c30dd5a PM |
391 | set_flush_to_zero(1, &env->vfp.standard_fp_status); |
392 | set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); | |
393 | set_default_nan_mode(1, &env->vfp.standard_fp_status); | |
394 | set_float_detect_tininess(float_tininess_before_rounding, | |
395 | &env->vfp.fp_status); | |
396 | set_float_detect_tininess(float_tininess_before_rounding, | |
397 | &env->vfp.standard_fp_status); | |
bcc531f0 PM |
398 | set_float_detect_tininess(float_tininess_before_rounding, |
399 | &env->vfp.fp_status_f16); | |
50a2c6e5 PB |
400 | #ifndef CONFIG_USER_ONLY |
401 | if (kvm_enabled()) { | |
402 | kvm_arm_reset_vcpu(cpu); | |
403 | } | |
404 | #endif | |
9ee98ce8 | 405 | |
46747d15 | 406 | hw_breakpoint_update_all(cpu); |
9ee98ce8 | 407 | hw_watchpoint_update_all(cpu); |
a8a79c7a | 408 | arm_rebuild_hflags(env); |
dec9c2d4 AF |
409 | } |
410 | ||
310cedf3 | 411 | static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, |
be879556 RH |
412 | unsigned int target_el, |
413 | unsigned int cur_el, bool secure, | |
414 | uint64_t hcr_el2) | |
310cedf3 RH |
415 | { |
416 | CPUARMState *env = cs->env_ptr; | |
310cedf3 | 417 | bool pstate_unmasked; |
16e07f78 | 418 | bool unmasked = false; |
310cedf3 RH |
419 | |
420 | /* | |
421 | * Don't take exceptions if they target a lower EL. | |
422 | * This check should catch any exceptions that would not be taken | |
423 | * but left pending. | |
424 | */ | |
425 | if (cur_el > target_el) { | |
426 | return false; | |
427 | } | |
428 | ||
310cedf3 RH |
429 | switch (excp_idx) { |
430 | case EXCP_FIQ: | |
431 | pstate_unmasked = !(env->daif & PSTATE_F); | |
432 | break; | |
433 | ||
434 | case EXCP_IRQ: | |
435 | pstate_unmasked = !(env->daif & PSTATE_I); | |
436 | break; | |
437 | ||
438 | case EXCP_VFIQ: | |
439 | if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { | |
440 | /* VFIQs are only taken when hypervized and non-secure. */ | |
441 | return false; | |
442 | } | |
443 | return !(env->daif & PSTATE_F); | |
444 | case EXCP_VIRQ: | |
445 | if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { | |
446 | /* VIRQs are only taken when hypervized and non-secure. */ | |
447 | return false; | |
448 | } | |
449 | return !(env->daif & PSTATE_I); | |
450 | default: | |
451 | g_assert_not_reached(); | |
452 | } | |
453 | ||
454 | /* | |
455 | * Use the target EL, current execution state and SCR/HCR settings to | |
456 | * determine whether the corresponding CPSR bit is used to mask the | |
457 | * interrupt. | |
458 | */ | |
459 | if ((target_el > cur_el) && (target_el != 1)) { | |
460 | /* Exceptions targeting a higher EL may not be maskable */ | |
461 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
462 | /* | |
463 | * 64-bit masking rules are simple: exceptions to EL3 | |
464 | * can't be masked, and exceptions to EL2 can only be | |
465 | * masked from Secure state. The HCR and SCR settings | |
466 | * don't affect the masking logic, only the interrupt routing. | |
467 | */ | |
468 | if (target_el == 3 || !secure) { | |
16e07f78 | 469 | unmasked = true; |
310cedf3 RH |
470 | } |
471 | } else { | |
472 | /* | |
473 | * The old 32-bit-only environment has a more complicated | |
474 | * masking setup. HCR and SCR bits not only affect interrupt | |
475 | * routing but also change the behaviour of masking. | |
476 | */ | |
477 | bool hcr, scr; | |
478 | ||
479 | switch (excp_idx) { | |
480 | case EXCP_FIQ: | |
481 | /* | |
482 | * If FIQs are routed to EL3 or EL2 then there are cases where | |
483 | * we override the CPSR.F in determining if the exception is | |
484 | * masked or not. If neither of these are set then we fall back | |
485 | * to the CPSR.F setting otherwise we further assess the state | |
486 | * below. | |
487 | */ | |
488 | hcr = hcr_el2 & HCR_FMO; | |
489 | scr = (env->cp15.scr_el3 & SCR_FIQ); | |
490 | ||
491 | /* | |
492 | * When EL3 is 32-bit, the SCR.FW bit controls whether the | |
493 | * CPSR.F bit masks FIQ interrupts when taken in non-secure | |
494 | * state. If SCR.FW is set then FIQs can be masked by CPSR.F | |
495 | * when non-secure but only when FIQs are only routed to EL3. | |
496 | */ | |
497 | scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); | |
498 | break; | |
499 | case EXCP_IRQ: | |
500 | /* | |
501 | * When EL3 execution state is 32-bit, if HCR.IMO is set then | |
502 | * we may override the CPSR.I masking when in non-secure state. | |
503 | * The SCR.IRQ setting has already been taken into consideration | |
504 | * when setting the target EL, so it does not have a further | |
505 | * affect here. | |
506 | */ | |
507 | hcr = hcr_el2 & HCR_IMO; | |
508 | scr = false; | |
509 | break; | |
510 | default: | |
511 | g_assert_not_reached(); | |
512 | } | |
513 | ||
514 | if ((scr || hcr) && !secure) { | |
16e07f78 | 515 | unmasked = true; |
310cedf3 RH |
516 | } |
517 | } | |
518 | } | |
519 | ||
520 | /* | |
521 | * The PSTATE bits only mask the interrupt if we have not overriden the | |
522 | * ability above. | |
523 | */ | |
524 | return unmasked || pstate_unmasked; | |
525 | } | |
526 | ||
e8925712 RH |
527 | bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
528 | { | |
529 | CPUClass *cc = CPU_GET_CLASS(cs); | |
012a906b GB |
530 | CPUARMState *env = cs->env_ptr; |
531 | uint32_t cur_el = arm_current_el(env); | |
532 | bool secure = arm_is_secure(env); | |
be879556 | 533 | uint64_t hcr_el2 = arm_hcr_el2_eff(env); |
012a906b GB |
534 | uint32_t target_el; |
535 | uint32_t excp_idx; | |
d63d0ec5 RH |
536 | |
537 | /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ | |
e8925712 | 538 | |
012a906b GB |
539 | if (interrupt_request & CPU_INTERRUPT_FIQ) { |
540 | excp_idx = EXCP_FIQ; | |
541 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
be879556 RH |
542 | if (arm_excp_unmasked(cs, excp_idx, target_el, |
543 | cur_el, secure, hcr_el2)) { | |
d63d0ec5 | 544 | goto found; |
012a906b | 545 | } |
e8925712 | 546 | } |
012a906b GB |
547 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
548 | excp_idx = EXCP_IRQ; | |
549 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
be879556 RH |
550 | if (arm_excp_unmasked(cs, excp_idx, target_el, |
551 | cur_el, secure, hcr_el2)) { | |
d63d0ec5 | 552 | goto found; |
012a906b | 553 | } |
e8925712 | 554 | } |
012a906b GB |
555 | if (interrupt_request & CPU_INTERRUPT_VIRQ) { |
556 | excp_idx = EXCP_VIRQ; | |
557 | target_el = 1; | |
be879556 RH |
558 | if (arm_excp_unmasked(cs, excp_idx, target_el, |
559 | cur_el, secure, hcr_el2)) { | |
d63d0ec5 | 560 | goto found; |
012a906b | 561 | } |
136e67e9 | 562 | } |
012a906b GB |
563 | if (interrupt_request & CPU_INTERRUPT_VFIQ) { |
564 | excp_idx = EXCP_VFIQ; | |
565 | target_el = 1; | |
be879556 RH |
566 | if (arm_excp_unmasked(cs, excp_idx, target_el, |
567 | cur_el, secure, hcr_el2)) { | |
d63d0ec5 | 568 | goto found; |
012a906b | 569 | } |
136e67e9 | 570 | } |
d63d0ec5 | 571 | return false; |
e8925712 | 572 | |
d63d0ec5 RH |
573 | found: |
574 | cs->exception_index = excp_idx; | |
575 | env->exception.target_el = target_el; | |
576 | cc->do_interrupt(cs); | |
577 | return true; | |
e8925712 RH |
578 | } |
579 | ||
89430fc6 PM |
580 | void arm_cpu_update_virq(ARMCPU *cpu) |
581 | { | |
582 | /* | |
583 | * Update the interrupt level for VIRQ, which is the logical OR of | |
584 | * the HCR_EL2.VI bit and the input line level from the GIC. | |
585 | */ | |
586 | CPUARMState *env = &cpu->env; | |
587 | CPUState *cs = CPU(cpu); | |
588 | ||
589 | bool new_state = (env->cp15.hcr_el2 & HCR_VI) || | |
590 | (env->irq_line_state & CPU_INTERRUPT_VIRQ); | |
591 | ||
592 | if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { | |
593 | if (new_state) { | |
594 | cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); | |
595 | } else { | |
596 | cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); | |
597 | } | |
598 | } | |
599 | } | |
600 | ||
601 | void arm_cpu_update_vfiq(ARMCPU *cpu) | |
602 | { | |
603 | /* | |
604 | * Update the interrupt level for VFIQ, which is the logical OR of | |
605 | * the HCR_EL2.VF bit and the input line level from the GIC. | |
606 | */ | |
607 | CPUARMState *env = &cpu->env; | |
608 | CPUState *cs = CPU(cpu); | |
609 | ||
610 | bool new_state = (env->cp15.hcr_el2 & HCR_VF) || | |
611 | (env->irq_line_state & CPU_INTERRUPT_VFIQ); | |
612 | ||
613 | if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { | |
614 | if (new_state) { | |
615 | cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); | |
616 | } else { | |
617 | cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); | |
618 | } | |
619 | } | |
620 | } | |
621 | ||
7c1840b6 PM |
622 | #ifndef CONFIG_USER_ONLY |
623 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | |
624 | { | |
625 | ARMCPU *cpu = opaque; | |
136e67e9 | 626 | CPUARMState *env = &cpu->env; |
7c1840b6 | 627 | CPUState *cs = CPU(cpu); |
136e67e9 EI |
628 | static const int mask[] = { |
629 | [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, | |
630 | [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, | |
631 | [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, | |
632 | [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ | |
633 | }; | |
7c1840b6 | 634 | |
ed89f078 PM |
635 | if (level) { |
636 | env->irq_line_state |= mask[irq]; | |
637 | } else { | |
638 | env->irq_line_state &= ~mask[irq]; | |
639 | } | |
640 | ||
7c1840b6 | 641 | switch (irq) { |
136e67e9 | 642 | case ARM_CPU_VIRQ: |
89430fc6 PM |
643 | assert(arm_feature(env, ARM_FEATURE_EL2)); |
644 | arm_cpu_update_virq(cpu); | |
645 | break; | |
136e67e9 | 646 | case ARM_CPU_VFIQ: |
f128bf29 | 647 | assert(arm_feature(env, ARM_FEATURE_EL2)); |
89430fc6 PM |
648 | arm_cpu_update_vfiq(cpu); |
649 | break; | |
136e67e9 | 650 | case ARM_CPU_IRQ: |
7c1840b6 PM |
651 | case ARM_CPU_FIQ: |
652 | if (level) { | |
136e67e9 | 653 | cpu_interrupt(cs, mask[irq]); |
7c1840b6 | 654 | } else { |
136e67e9 | 655 | cpu_reset_interrupt(cs, mask[irq]); |
7c1840b6 PM |
656 | } |
657 | break; | |
658 | default: | |
8f6fd322 | 659 | g_assert_not_reached(); |
7c1840b6 PM |
660 | } |
661 | } | |
662 | ||
663 | static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) | |
664 | { | |
665 | #ifdef CONFIG_KVM | |
666 | ARMCPU *cpu = opaque; | |
ed89f078 | 667 | CPUARMState *env = &cpu->env; |
7c1840b6 | 668 | CPUState *cs = CPU(cpu); |
ed89f078 | 669 | uint32_t linestate_bit; |
f6530926 | 670 | int irq_id; |
7c1840b6 PM |
671 | |
672 | switch (irq) { | |
673 | case ARM_CPU_IRQ: | |
f6530926 | 674 | irq_id = KVM_ARM_IRQ_CPU_IRQ; |
ed89f078 | 675 | linestate_bit = CPU_INTERRUPT_HARD; |
7c1840b6 PM |
676 | break; |
677 | case ARM_CPU_FIQ: | |
f6530926 | 678 | irq_id = KVM_ARM_IRQ_CPU_FIQ; |
ed89f078 | 679 | linestate_bit = CPU_INTERRUPT_FIQ; |
7c1840b6 PM |
680 | break; |
681 | default: | |
8f6fd322 | 682 | g_assert_not_reached(); |
7c1840b6 | 683 | } |
ed89f078 PM |
684 | |
685 | if (level) { | |
686 | env->irq_line_state |= linestate_bit; | |
687 | } else { | |
688 | env->irq_line_state &= ~linestate_bit; | |
689 | } | |
f6530926 | 690 | kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); |
7c1840b6 PM |
691 | #endif |
692 | } | |
84f2bed3 | 693 | |
ed50ff78 | 694 | static bool arm_cpu_virtio_is_big_endian(CPUState *cs) |
84f2bed3 PS |
695 | { |
696 | ARMCPU *cpu = ARM_CPU(cs); | |
697 | CPUARMState *env = &cpu->env; | |
84f2bed3 PS |
698 | |
699 | cpu_synchronize_state(cs); | |
ed50ff78 | 700 | return arm_cpu_data_is_big_endian(env); |
84f2bed3 PS |
701 | } |
702 | ||
7c1840b6 PM |
703 | #endif |
704 | ||
48440620 PC |
705 | static int |
706 | print_insn_thumb1(bfd_vma pc, disassemble_info *info) | |
707 | { | |
708 | return print_insn_arm(pc | 1, info); | |
709 | } | |
710 | ||
711 | static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) | |
712 | { | |
713 | ARMCPU *ac = ARM_CPU(cpu); | |
714 | CPUARMState *env = &ac->env; | |
7bcdbf51 | 715 | bool sctlr_b; |
48440620 PC |
716 | |
717 | if (is_a64(env)) { | |
718 | /* We might not be compiled with the A64 disassembler | |
719 | * because it needs a C++ compiler. Leave print_insn | |
720 | * unset in this case to use the caller default behaviour. | |
721 | */ | |
722 | #if defined(CONFIG_ARM_A64_DIS) | |
723 | info->print_insn = print_insn_arm_a64; | |
724 | #endif | |
110f6c70 | 725 | info->cap_arch = CS_ARCH_ARM64; |
15fa1a0a RH |
726 | info->cap_insn_unit = 4; |
727 | info->cap_insn_split = 4; | |
48440620 | 728 | } else { |
110f6c70 RH |
729 | int cap_mode; |
730 | if (env->thumb) { | |
731 | info->print_insn = print_insn_thumb1; | |
15fa1a0a RH |
732 | info->cap_insn_unit = 2; |
733 | info->cap_insn_split = 4; | |
110f6c70 RH |
734 | cap_mode = CS_MODE_THUMB; |
735 | } else { | |
736 | info->print_insn = print_insn_arm; | |
15fa1a0a RH |
737 | info->cap_insn_unit = 4; |
738 | info->cap_insn_split = 4; | |
110f6c70 RH |
739 | cap_mode = CS_MODE_ARM; |
740 | } | |
741 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
742 | cap_mode |= CS_MODE_V8; | |
743 | } | |
744 | if (arm_feature(env, ARM_FEATURE_M)) { | |
745 | cap_mode |= CS_MODE_MCLASS; | |
746 | } | |
747 | info->cap_arch = CS_ARCH_ARM; | |
748 | info->cap_mode = cap_mode; | |
48440620 | 749 | } |
7bcdbf51 RH |
750 | |
751 | sctlr_b = arm_sctlr_b(env); | |
752 | if (bswap_code(sctlr_b)) { | |
48440620 PC |
753 | #ifdef TARGET_WORDS_BIGENDIAN |
754 | info->endian = BFD_ENDIAN_LITTLE; | |
755 | #else | |
756 | info->endian = BFD_ENDIAN_BIG; | |
757 | #endif | |
758 | } | |
f7478a92 | 759 | info->flags &= ~INSN_ARM_BE32; |
7bcdbf51 RH |
760 | #ifndef CONFIG_USER_ONLY |
761 | if (sctlr_b) { | |
f7478a92 JB |
762 | info->flags |= INSN_ARM_BE32; |
763 | } | |
7bcdbf51 | 764 | #endif |
48440620 PC |
765 | } |
766 | ||
86480615 PMD |
767 | #ifdef TARGET_AARCH64 |
768 | ||
769 | static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) | |
770 | { | |
771 | ARMCPU *cpu = ARM_CPU(cs); | |
772 | CPUARMState *env = &cpu->env; | |
773 | uint32_t psr = pstate_read(env); | |
774 | int i; | |
775 | int el = arm_current_el(env); | |
776 | const char *ns_status; | |
777 | ||
778 | qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); | |
779 | for (i = 0; i < 32; i++) { | |
780 | if (i == 31) { | |
781 | qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); | |
782 | } else { | |
783 | qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], | |
784 | (i + 2) % 3 ? " " : "\n"); | |
785 | } | |
786 | } | |
787 | ||
788 | if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { | |
789 | ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; | |
790 | } else { | |
791 | ns_status = ""; | |
792 | } | |
793 | qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", | |
794 | psr, | |
795 | psr & PSTATE_N ? 'N' : '-', | |
796 | psr & PSTATE_Z ? 'Z' : '-', | |
797 | psr & PSTATE_C ? 'C' : '-', | |
798 | psr & PSTATE_V ? 'V' : '-', | |
799 | ns_status, | |
800 | el, | |
801 | psr & PSTATE_SP ? 'h' : 't'); | |
802 | ||
803 | if (cpu_isar_feature(aa64_bti, cpu)) { | |
804 | qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); | |
805 | } | |
806 | if (!(flags & CPU_DUMP_FPU)) { | |
807 | qemu_fprintf(f, "\n"); | |
808 | return; | |
809 | } | |
810 | if (fp_exception_el(env, el) != 0) { | |
811 | qemu_fprintf(f, " FPU disabled\n"); | |
812 | return; | |
813 | } | |
814 | qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n", | |
815 | vfp_get_fpcr(env), vfp_get_fpsr(env)); | |
816 | ||
817 | if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { | |
818 | int j, zcr_len = sve_zcr_len_for_el(env, el); | |
819 | ||
820 | for (i = 0; i <= FFR_PRED_NUM; i++) { | |
821 | bool eol; | |
822 | if (i == FFR_PRED_NUM) { | |
823 | qemu_fprintf(f, "FFR="); | |
824 | /* It's last, so end the line. */ | |
825 | eol = true; | |
826 | } else { | |
827 | qemu_fprintf(f, "P%02d=", i); | |
828 | switch (zcr_len) { | |
829 | case 0: | |
830 | eol = i % 8 == 7; | |
831 | break; | |
832 | case 1: | |
833 | eol = i % 6 == 5; | |
834 | break; | |
835 | case 2: | |
836 | case 3: | |
837 | eol = i % 3 == 2; | |
838 | break; | |
839 | default: | |
840 | /* More than one quadword per predicate. */ | |
841 | eol = true; | |
842 | break; | |
843 | } | |
844 | } | |
845 | for (j = zcr_len / 4; j >= 0; j--) { | |
846 | int digits; | |
847 | if (j * 4 + 4 <= zcr_len + 1) { | |
848 | digits = 16; | |
849 | } else { | |
850 | digits = (zcr_len % 4 + 1) * 4; | |
851 | } | |
852 | qemu_fprintf(f, "%0*" PRIx64 "%s", digits, | |
853 | env->vfp.pregs[i].p[j], | |
854 | j ? ":" : eol ? "\n" : " "); | |
855 | } | |
856 | } | |
857 | ||
858 | for (i = 0; i < 32; i++) { | |
859 | if (zcr_len == 0) { | |
860 | qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", | |
861 | i, env->vfp.zregs[i].d[1], | |
862 | env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); | |
863 | } else if (zcr_len == 1) { | |
864 | qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 | |
865 | ":%016" PRIx64 ":%016" PRIx64 "\n", | |
866 | i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], | |
867 | env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); | |
868 | } else { | |
869 | for (j = zcr_len; j >= 0; j--) { | |
870 | bool odd = (zcr_len - j) % 2 != 0; | |
871 | if (j == zcr_len) { | |
872 | qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); | |
873 | } else if (!odd) { | |
874 | if (j > 0) { | |
875 | qemu_fprintf(f, " [%x-%x]=", j, j - 1); | |
876 | } else { | |
877 | qemu_fprintf(f, " [%x]=", j); | |
878 | } | |
879 | } | |
880 | qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", | |
881 | env->vfp.zregs[i].d[j * 2 + 1], | |
882 | env->vfp.zregs[i].d[j * 2], | |
883 | odd || j == 0 ? "\n" : ":"); | |
884 | } | |
885 | } | |
886 | } | |
887 | } else { | |
888 | for (i = 0; i < 32; i++) { | |
889 | uint64_t *q = aa64_vfp_qreg(env, i); | |
890 | qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", | |
891 | i, q[1], q[0], (i & 1 ? "\n" : " ")); | |
892 | } | |
893 | } | |
894 | } | |
895 | ||
896 | #else | |
897 | ||
898 | static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) | |
899 | { | |
900 | g_assert_not_reached(); | |
901 | } | |
902 | ||
903 | #endif | |
904 | ||
905 | static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) | |
906 | { | |
907 | ARMCPU *cpu = ARM_CPU(cs); | |
908 | CPUARMState *env = &cpu->env; | |
909 | int i; | |
910 | ||
911 | if (is_a64(env)) { | |
912 | aarch64_cpu_dump_state(cs, f, flags); | |
913 | return; | |
914 | } | |
915 | ||
916 | for (i = 0; i < 16; i++) { | |
917 | qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]); | |
918 | if ((i % 4) == 3) { | |
919 | qemu_fprintf(f, "\n"); | |
920 | } else { | |
921 | qemu_fprintf(f, " "); | |
922 | } | |
923 | } | |
924 | ||
925 | if (arm_feature(env, ARM_FEATURE_M)) { | |
926 | uint32_t xpsr = xpsr_read(env); | |
927 | const char *mode; | |
928 | const char *ns_status = ""; | |
929 | ||
930 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
931 | ns_status = env->v7m.secure ? "S " : "NS "; | |
932 | } | |
933 | ||
934 | if (xpsr & XPSR_EXCP) { | |
935 | mode = "handler"; | |
936 | } else { | |
937 | if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) { | |
938 | mode = "unpriv-thread"; | |
939 | } else { | |
940 | mode = "priv-thread"; | |
941 | } | |
942 | } | |
943 | ||
944 | qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", | |
945 | xpsr, | |
946 | xpsr & XPSR_N ? 'N' : '-', | |
947 | xpsr & XPSR_Z ? 'Z' : '-', | |
948 | xpsr & XPSR_C ? 'C' : '-', | |
949 | xpsr & XPSR_V ? 'V' : '-', | |
950 | xpsr & XPSR_T ? 'T' : 'A', | |
951 | ns_status, | |
952 | mode); | |
953 | } else { | |
954 | uint32_t psr = cpsr_read(env); | |
955 | const char *ns_status = ""; | |
956 | ||
957 | if (arm_feature(env, ARM_FEATURE_EL3) && | |
958 | (psr & CPSR_M) != ARM_CPU_MODE_MON) { | |
959 | ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; | |
960 | } | |
961 | ||
962 | qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", | |
963 | psr, | |
964 | psr & CPSR_N ? 'N' : '-', | |
965 | psr & CPSR_Z ? 'Z' : '-', | |
966 | psr & CPSR_C ? 'C' : '-', | |
967 | psr & CPSR_V ? 'V' : '-', | |
968 | psr & CPSR_T ? 'T' : 'A', | |
969 | ns_status, | |
970 | aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); | |
971 | } | |
972 | ||
973 | if (flags & CPU_DUMP_FPU) { | |
974 | int numvfpregs = 0; | |
a6627f5f RH |
975 | if (cpu_isar_feature(aa32_simd_r32, cpu)) { |
976 | numvfpregs = 32; | |
7fbc6a40 | 977 | } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { |
a6627f5f | 978 | numvfpregs = 16; |
86480615 PMD |
979 | } |
980 | for (i = 0; i < numvfpregs; i++) { | |
981 | uint64_t v = *aa32_vfp_dreg(env, i); | |
982 | qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", | |
983 | i * 2, (uint32_t)v, | |
984 | i * 2 + 1, (uint32_t)(v >> 32), | |
985 | i, v); | |
986 | } | |
987 | qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); | |
988 | } | |
989 | } | |
990 | ||
46de5913 IM |
991 | uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) |
992 | { | |
993 | uint32_t Aff1 = idx / clustersz; | |
994 | uint32_t Aff0 = idx % clustersz; | |
995 | return (Aff1 << ARM_AFF1_SHIFT) | Aff0; | |
996 | } | |
997 | ||
ac87e507 PM |
998 | static void cpreg_hashtable_data_destroy(gpointer data) |
999 | { | |
1000 | /* | |
1001 | * Destroy function for cpu->cp_regs hashtable data entries. | |
1002 | * We must free the name string because it was g_strdup()ed in | |
1003 | * add_cpreg_to_hashtable(). It's OK to cast away the 'const' | |
1004 | * from r->name because we know we definitely allocated it. | |
1005 | */ | |
1006 | ARMCPRegInfo *r = data; | |
1007 | ||
1008 | g_free((void *)r->name); | |
1009 | g_free(r); | |
1010 | } | |
1011 | ||
777dc784 PM |
1012 | static void arm_cpu_initfn(Object *obj) |
1013 | { | |
1014 | ARMCPU *cpu = ARM_CPU(obj); | |
1015 | ||
7506ed90 | 1016 | cpu_set_cpustate_pointers(cpu); |
4b6a83fb | 1017 | cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
ac87e507 | 1018 | g_free, cpreg_hashtable_data_destroy); |
79614b78 | 1019 | |
b5c53d1b | 1020 | QLIST_INIT(&cpu->pre_el_change_hooks); |
08267487 AL |
1021 | QLIST_INIT(&cpu->el_change_hooks); |
1022 | ||
7c1840b6 PM |
1023 | #ifndef CONFIG_USER_ONLY |
1024 | /* Our inbound IRQ and FIQ lines */ | |
1025 | if (kvm_enabled()) { | |
136e67e9 EI |
1026 | /* VIRQ and VFIQ are unused with KVM but we add them to maintain |
1027 | * the same interface as non-KVM CPUs. | |
1028 | */ | |
1029 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); | |
7c1840b6 | 1030 | } else { |
136e67e9 | 1031 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); |
7c1840b6 | 1032 | } |
55d284af | 1033 | |
55d284af PM |
1034 | qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, |
1035 | ARRAY_SIZE(cpu->gt_timer_outputs)); | |
aa1b3111 PM |
1036 | |
1037 | qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, | |
1038 | "gicv3-maintenance-interrupt", 1); | |
07f48730 AJ |
1039 | qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, |
1040 | "pmu-interrupt", 1); | |
7c1840b6 PM |
1041 | #endif |
1042 | ||
54d3e3f5 PM |
1043 | /* DTB consumers generally don't in fact care what the 'compatible' |
1044 | * string is, so always provide some string and trust that a hypothetical | |
1045 | * picky DTB consumer will also provide a helpful error message. | |
1046 | */ | |
1047 | cpu->dtb_compatible = "qemu,unknown"; | |
dd032e34 | 1048 | cpu->psci_version = 1; /* By default assume PSCI v0.1 */ |
3541addc | 1049 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; |
54d3e3f5 | 1050 | |
98128601 RH |
1051 | if (tcg_enabled()) { |
1052 | cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ | |
79614b78 | 1053 | } |
4b6a83fb PM |
1054 | } |
1055 | ||
96eec6b2 AJ |
1056 | static Property arm_cpu_gt_cntfrq_property = |
1057 | DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, | |
1058 | NANOSECONDS_PER_SECOND / GTIMER_SCALE); | |
1059 | ||
07a5b0d2 | 1060 | static Property arm_cpu_reset_cbar_property = |
f318cec6 | 1061 | DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); |
07a5b0d2 | 1062 | |
68e0a40a AP |
1063 | static Property arm_cpu_reset_hivecs_property = |
1064 | DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); | |
1065 | ||
3933443e PM |
1066 | static Property arm_cpu_rvbar_property = |
1067 | DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); | |
1068 | ||
45ca3a14 | 1069 | #ifndef CONFIG_USER_ONLY |
c25bd18a PM |
1070 | static Property arm_cpu_has_el2_property = |
1071 | DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); | |
1072 | ||
51942aee GB |
1073 | static Property arm_cpu_has_el3_property = |
1074 | DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); | |
45ca3a14 | 1075 | #endif |
51942aee | 1076 | |
3a062d57 JB |
1077 | static Property arm_cpu_cfgend_property = |
1078 | DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); | |
1079 | ||
97a28b0e PM |
1080 | static Property arm_cpu_has_vfp_property = |
1081 | DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); | |
1082 | ||
1083 | static Property arm_cpu_has_neon_property = | |
1084 | DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); | |
1085 | ||
ea90db0a PM |
1086 | static Property arm_cpu_has_dsp_property = |
1087 | DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true); | |
1088 | ||
8f325f56 PC |
1089 | static Property arm_cpu_has_mpu_property = |
1090 | DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); | |
1091 | ||
8d92e26b PM |
1092 | /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, |
1093 | * because the CPU initfn will have already set cpu->pmsav7_dregion to | |
1094 | * the right value for that particular CPU type, and we don't want | |
1095 | * to override that with an incorrect constant value. | |
1096 | */ | |
3281af81 | 1097 | static Property arm_cpu_pmsav7_dregion_property = |
8d92e26b PM |
1098 | DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, |
1099 | pmsav7_dregion, | |
1100 | qdev_prop_uint32, uint32_t); | |
3281af81 | 1101 | |
ae502508 AJ |
1102 | static bool arm_get_pmu(Object *obj, Error **errp) |
1103 | { | |
1104 | ARMCPU *cpu = ARM_CPU(obj); | |
1105 | ||
1106 | return cpu->has_pmu; | |
1107 | } | |
1108 | ||
1109 | static void arm_set_pmu(Object *obj, bool value, Error **errp) | |
1110 | { | |
1111 | ARMCPU *cpu = ARM_CPU(obj); | |
1112 | ||
1113 | if (value) { | |
7d20e681 | 1114 | if (kvm_enabled() && !kvm_arm_pmu_supported()) { |
ae502508 AJ |
1115 | error_setg(errp, "'pmu' feature not supported by KVM on this host"); |
1116 | return; | |
1117 | } | |
1118 | set_feature(&cpu->env, ARM_FEATURE_PMU); | |
1119 | } else { | |
1120 | unset_feature(&cpu->env, ARM_FEATURE_PMU); | |
1121 | } | |
1122 | cpu->has_pmu = value; | |
1123 | } | |
1124 | ||
7def8754 AJ |
1125 | unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) |
1126 | { | |
96eec6b2 AJ |
1127 | /* |
1128 | * The exact approach to calculating guest ticks is: | |
1129 | * | |
1130 | * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz, | |
1131 | * NANOSECONDS_PER_SECOND); | |
1132 | * | |
1133 | * We don't do that. Rather we intentionally use integer division | |
1134 | * truncation below and in the caller for the conversion of host monotonic | |
1135 | * time to guest ticks to provide the exact inverse for the semantics of | |
1136 | * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so | |
1137 | * it loses precision when representing frequencies where | |
1138 | * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to | |
1139 | * provide an exact inverse leads to scheduling timers with negative | |
1140 | * periods, which in turn leads to sticky behaviour in the guest. | |
1141 | * | |
1142 | * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor | |
1143 | * cannot become zero. | |
1144 | */ | |
7def8754 AJ |
1145 | return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ? |
1146 | NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; | |
1147 | } | |
1148 | ||
51e5ef45 | 1149 | void arm_cpu_post_init(Object *obj) |
07a5b0d2 PC |
1150 | { |
1151 | ARMCPU *cpu = ARM_CPU(obj); | |
07a5b0d2 | 1152 | |
790a1150 PM |
1153 | /* M profile implies PMSA. We have to do this here rather than |
1154 | * in realize with the other feature-implication checks because | |
1155 | * we look at the PMSA bit to see if we should add some properties. | |
1156 | */ | |
1157 | if (arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
1158 | set_feature(&cpu->env, ARM_FEATURE_PMSA); | |
1159 | } | |
1160 | ||
f318cec6 PM |
1161 | if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || |
1162 | arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { | |
94d912d1 | 1163 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); |
07a5b0d2 | 1164 | } |
68e0a40a AP |
1165 | |
1166 | if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
94d912d1 | 1167 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); |
68e0a40a | 1168 | } |
3933443e PM |
1169 | |
1170 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
94d912d1 | 1171 | qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); |
3933443e | 1172 | } |
51942aee | 1173 | |
45ca3a14 | 1174 | #ifndef CONFIG_USER_ONLY |
51942aee GB |
1175 | if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { |
1176 | /* Add the has_el3 state CPU property only if EL3 is allowed. This will | |
1177 | * prevent "has_el3" from existing on CPUs which cannot support EL3. | |
1178 | */ | |
94d912d1 | 1179 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); |
9e273ef2 | 1180 | |
9e273ef2 PM |
1181 | object_property_add_link(obj, "secure-memory", |
1182 | TYPE_MEMORY_REGION, | |
1183 | (Object **)&cpu->secure_memory, | |
1184 | qdev_prop_allow_set_link_before_realize, | |
d2623129 | 1185 | OBJ_PROP_LINK_STRONG); |
51942aee | 1186 | } |
8f325f56 | 1187 | |
c25bd18a | 1188 | if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { |
94d912d1 | 1189 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); |
c25bd18a | 1190 | } |
45ca3a14 | 1191 | #endif |
c25bd18a | 1192 | |
929e754d | 1193 | if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { |
ae502508 | 1194 | cpu->has_pmu = true; |
d2623129 | 1195 | object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); |
929e754d WH |
1196 | } |
1197 | ||
97a28b0e PM |
1198 | /* |
1199 | * Allow user to turn off VFP and Neon support, but only for TCG -- | |
1200 | * KVM does not currently allow us to lie to the guest about its | |
1201 | * ID/feature registers, so the guest always sees what the host has. | |
1202 | */ | |
7d63183f RH |
1203 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) |
1204 | ? cpu_isar_feature(aa64_fp_simd, cpu) | |
1205 | : cpu_isar_feature(aa32_vfp, cpu)) { | |
97a28b0e PM |
1206 | cpu->has_vfp = true; |
1207 | if (!kvm_enabled()) { | |
94d912d1 | 1208 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); |
97a28b0e PM |
1209 | } |
1210 | } | |
1211 | ||
1212 | if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { | |
1213 | cpu->has_neon = true; | |
1214 | if (!kvm_enabled()) { | |
94d912d1 | 1215 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); |
97a28b0e PM |
1216 | } |
1217 | } | |
1218 | ||
ea90db0a PM |
1219 | if (arm_feature(&cpu->env, ARM_FEATURE_M) && |
1220 | arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { | |
94d912d1 | 1221 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); |
ea90db0a PM |
1222 | } |
1223 | ||
452a0955 | 1224 | if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { |
94d912d1 | 1225 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); |
3281af81 PC |
1226 | if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { |
1227 | qdev_property_add_static(DEVICE(obj), | |
94d912d1 | 1228 | &arm_cpu_pmsav7_dregion_property); |
3281af81 | 1229 | } |
8f325f56 PC |
1230 | } |
1231 | ||
181962fd PM |
1232 | if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { |
1233 | object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, | |
1234 | qdev_prop_allow_set_link_before_realize, | |
d2623129 | 1235 | OBJ_PROP_LINK_STRONG); |
f9f62e4c PM |
1236 | /* |
1237 | * M profile: initial value of the Secure VTOR. We can't just use | |
1238 | * a simple DEFINE_PROP_UINT32 for this because we want to permit | |
1239 | * the property to be set after realize. | |
1240 | */ | |
64a7b8de FF |
1241 | object_property_add_uint32_ptr(obj, "init-svtor", |
1242 | &cpu->init_svtor, | |
d2623129 | 1243 | OBJ_PROP_FLAG_READWRITE); |
181962fd PM |
1244 | } |
1245 | ||
94d912d1 | 1246 | qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); |
96eec6b2 AJ |
1247 | |
1248 | if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { | |
94d912d1 | 1249 | qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); |
96eec6b2 | 1250 | } |
9e6f8d8a | 1251 | |
1252 | if (kvm_enabled()) { | |
1253 | kvm_arm_add_vcpu_properties(obj); | |
1254 | } | |
07a5b0d2 PC |
1255 | } |
1256 | ||
4b6a83fb PM |
1257 | static void arm_cpu_finalizefn(Object *obj) |
1258 | { | |
1259 | ARMCPU *cpu = ARM_CPU(obj); | |
08267487 AL |
1260 | ARMELChangeHook *hook, *next; |
1261 | ||
4b6a83fb | 1262 | g_hash_table_destroy(cpu->cp_regs); |
08267487 | 1263 | |
b5c53d1b AL |
1264 | QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { |
1265 | QLIST_REMOVE(hook, node); | |
1266 | g_free(hook); | |
1267 | } | |
08267487 AL |
1268 | QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { |
1269 | QLIST_REMOVE(hook, node); | |
1270 | g_free(hook); | |
1271 | } | |
4e7beb0c AL |
1272 | #ifndef CONFIG_USER_ONLY |
1273 | if (cpu->pmu_timer) { | |
1274 | timer_del(cpu->pmu_timer); | |
1275 | timer_deinit(cpu->pmu_timer); | |
1276 | timer_free(cpu->pmu_timer); | |
1277 | } | |
1278 | #endif | |
777dc784 PM |
1279 | } |
1280 | ||
0df9142d AJ |
1281 | void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) |
1282 | { | |
1283 | Error *local_err = NULL; | |
1284 | ||
1285 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
1286 | arm_cpu_sve_finalize(cpu, &local_err); | |
1287 | if (local_err != NULL) { | |
1288 | error_propagate(errp, local_err); | |
1289 | return; | |
1290 | } | |
1291 | } | |
1292 | } | |
1293 | ||
14969266 | 1294 | static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
581be094 | 1295 | { |
14a10fc3 | 1296 | CPUState *cs = CPU(dev); |
14969266 AF |
1297 | ARMCPU *cpu = ARM_CPU(dev); |
1298 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); | |
581be094 | 1299 | CPUARMState *env = &cpu->env; |
e97da98f | 1300 | int pagebits; |
ce5b1bbf | 1301 | Error *local_err = NULL; |
0f8d06f1 | 1302 | bool no_aa32 = false; |
ce5b1bbf | 1303 | |
c4487d76 PM |
1304 | /* If we needed to query the host kernel for the CPU features |
1305 | * then it's possible that might have failed in the initfn, but | |
1306 | * this is the first point where we can report it. | |
1307 | */ | |
1308 | if (cpu->host_cpu_probe_failed) { | |
1309 | if (!kvm_enabled()) { | |
1310 | error_setg(errp, "The 'host' CPU type can only be used with KVM"); | |
1311 | } else { | |
1312 | error_setg(errp, "Failed to retrieve host CPU features"); | |
1313 | } | |
1314 | return; | |
1315 | } | |
1316 | ||
95f87565 PM |
1317 | #ifndef CONFIG_USER_ONLY |
1318 | /* The NVIC and M-profile CPU are two halves of a single piece of | |
1319 | * hardware; trying to use one without the other is a command line | |
1320 | * error and will result in segfaults if not caught here. | |
1321 | */ | |
1322 | if (arm_feature(env, ARM_FEATURE_M)) { | |
1323 | if (!env->nvic) { | |
1324 | error_setg(errp, "This board cannot be used with Cortex-M CPUs"); | |
1325 | return; | |
1326 | } | |
1327 | } else { | |
1328 | if (env->nvic) { | |
1329 | error_setg(errp, "This board can only be used with Cortex-M CPUs"); | |
1330 | return; | |
1331 | } | |
1332 | } | |
397cd31f | 1333 | |
96eec6b2 AJ |
1334 | { |
1335 | uint64_t scale; | |
1336 | ||
1337 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { | |
1338 | if (!cpu->gt_cntfrq_hz) { | |
1339 | error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", | |
1340 | cpu->gt_cntfrq_hz); | |
1341 | return; | |
1342 | } | |
1343 | scale = gt_cntfrq_period_ns(cpu); | |
1344 | } else { | |
1345 | scale = GTIMER_SCALE; | |
1346 | } | |
1347 | ||
1348 | cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, | |
1349 | arm_gt_ptimer_cb, cpu); | |
1350 | cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, | |
1351 | arm_gt_vtimer_cb, cpu); | |
1352 | cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale, | |
1353 | arm_gt_htimer_cb, cpu); | |
1354 | cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale, | |
1355 | arm_gt_stimer_cb, cpu); | |
8c94b071 RH |
1356 | cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale, |
1357 | arm_gt_hvtimer_cb, cpu); | |
96eec6b2 | 1358 | } |
95f87565 PM |
1359 | #endif |
1360 | ||
ce5b1bbf LV |
1361 | cpu_exec_realizefn(cs, &local_err); |
1362 | if (local_err != NULL) { | |
1363 | error_propagate(errp, local_err); | |
1364 | return; | |
1365 | } | |
14969266 | 1366 | |
0df9142d AJ |
1367 | arm_cpu_finalize_features(cpu, &local_err); |
1368 | if (local_err != NULL) { | |
1369 | error_propagate(errp, local_err); | |
1370 | return; | |
1371 | } | |
1372 | ||
97a28b0e PM |
1373 | if (arm_feature(env, ARM_FEATURE_AARCH64) && |
1374 | cpu->has_vfp != cpu->has_neon) { | |
1375 | /* | |
1376 | * This is an architectural requirement for AArch64; AArch32 is | |
1377 | * more flexible and permits VFP-no-Neon and Neon-no-VFP. | |
1378 | */ | |
1379 | error_setg(errp, | |
1380 | "AArch64 CPUs must have both VFP and Neon or neither"); | |
1381 | return; | |
1382 | } | |
1383 | ||
1384 | if (!cpu->has_vfp) { | |
1385 | uint64_t t; | |
1386 | uint32_t u; | |
1387 | ||
97a28b0e PM |
1388 | t = cpu->isar.id_aa64isar1; |
1389 | t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); | |
1390 | cpu->isar.id_aa64isar1 = t; | |
1391 | ||
1392 | t = cpu->isar.id_aa64pfr0; | |
1393 | t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf); | |
1394 | cpu->isar.id_aa64pfr0 = t; | |
1395 | ||
1396 | u = cpu->isar.id_isar6; | |
1397 | u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0); | |
1398 | cpu->isar.id_isar6 = u; | |
1399 | ||
1400 | u = cpu->isar.mvfr0; | |
1401 | u = FIELD_DP32(u, MVFR0, FPSP, 0); | |
1402 | u = FIELD_DP32(u, MVFR0, FPDP, 0); | |
1403 | u = FIELD_DP32(u, MVFR0, FPTRAP, 0); | |
1404 | u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0); | |
1405 | u = FIELD_DP32(u, MVFR0, FPSQRT, 0); | |
1406 | u = FIELD_DP32(u, MVFR0, FPSHVEC, 0); | |
1407 | u = FIELD_DP32(u, MVFR0, FPROUND, 0); | |
1408 | cpu->isar.mvfr0 = u; | |
1409 | ||
1410 | u = cpu->isar.mvfr1; | |
1411 | u = FIELD_DP32(u, MVFR1, FPFTZ, 0); | |
1412 | u = FIELD_DP32(u, MVFR1, FPDNAN, 0); | |
1413 | u = FIELD_DP32(u, MVFR1, FPHP, 0); | |
1414 | cpu->isar.mvfr1 = u; | |
1415 | ||
1416 | u = cpu->isar.mvfr2; | |
1417 | u = FIELD_DP32(u, MVFR2, FPMISC, 0); | |
1418 | cpu->isar.mvfr2 = u; | |
1419 | } | |
1420 | ||
1421 | if (!cpu->has_neon) { | |
1422 | uint64_t t; | |
1423 | uint32_t u; | |
1424 | ||
1425 | unset_feature(env, ARM_FEATURE_NEON); | |
1426 | ||
1427 | t = cpu->isar.id_aa64isar0; | |
1428 | t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); | |
1429 | cpu->isar.id_aa64isar0 = t; | |
1430 | ||
1431 | t = cpu->isar.id_aa64isar1; | |
1432 | t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0); | |
1433 | cpu->isar.id_aa64isar1 = t; | |
1434 | ||
1435 | t = cpu->isar.id_aa64pfr0; | |
1436 | t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf); | |
1437 | cpu->isar.id_aa64pfr0 = t; | |
1438 | ||
1439 | u = cpu->isar.id_isar5; | |
1440 | u = FIELD_DP32(u, ID_ISAR5, RDM, 0); | |
1441 | u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); | |
1442 | cpu->isar.id_isar5 = u; | |
1443 | ||
1444 | u = cpu->isar.id_isar6; | |
1445 | u = FIELD_DP32(u, ID_ISAR6, DP, 0); | |
1446 | u = FIELD_DP32(u, ID_ISAR6, FHM, 0); | |
1447 | cpu->isar.id_isar6 = u; | |
1448 | ||
1449 | u = cpu->isar.mvfr1; | |
1450 | u = FIELD_DP32(u, MVFR1, SIMDLS, 0); | |
1451 | u = FIELD_DP32(u, MVFR1, SIMDINT, 0); | |
1452 | u = FIELD_DP32(u, MVFR1, SIMDSP, 0); | |
1453 | u = FIELD_DP32(u, MVFR1, SIMDHP, 0); | |
97a28b0e PM |
1454 | cpu->isar.mvfr1 = u; |
1455 | ||
1456 | u = cpu->isar.mvfr2; | |
1457 | u = FIELD_DP32(u, MVFR2, SIMDMISC, 0); | |
1458 | cpu->isar.mvfr2 = u; | |
1459 | } | |
1460 | ||
1461 | if (!cpu->has_neon && !cpu->has_vfp) { | |
1462 | uint64_t t; | |
1463 | uint32_t u; | |
1464 | ||
1465 | t = cpu->isar.id_aa64isar0; | |
1466 | t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0); | |
1467 | cpu->isar.id_aa64isar0 = t; | |
1468 | ||
1469 | t = cpu->isar.id_aa64isar1; | |
1470 | t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0); | |
1471 | cpu->isar.id_aa64isar1 = t; | |
1472 | ||
1473 | u = cpu->isar.mvfr0; | |
1474 | u = FIELD_DP32(u, MVFR0, SIMDREG, 0); | |
1475 | cpu->isar.mvfr0 = u; | |
c52881bb RH |
1476 | |
1477 | /* Despite the name, this field covers both VFP and Neon */ | |
1478 | u = cpu->isar.mvfr1; | |
1479 | u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); | |
1480 | cpu->isar.mvfr1 = u; | |
97a28b0e PM |
1481 | } |
1482 | ||
ea90db0a PM |
1483 | if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { |
1484 | uint32_t u; | |
1485 | ||
1486 | unset_feature(env, ARM_FEATURE_THUMB_DSP); | |
1487 | ||
1488 | u = cpu->isar.id_isar1; | |
1489 | u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1); | |
1490 | cpu->isar.id_isar1 = u; | |
1491 | ||
1492 | u = cpu->isar.id_isar2; | |
1493 | u = FIELD_DP32(u, ID_ISAR2, MULTU, 1); | |
1494 | u = FIELD_DP32(u, ID_ISAR2, MULTS, 1); | |
1495 | cpu->isar.id_isar2 = u; | |
1496 | ||
1497 | u = cpu->isar.id_isar3; | |
1498 | u = FIELD_DP32(u, ID_ISAR3, SIMD, 1); | |
1499 | u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0); | |
1500 | cpu->isar.id_isar3 = u; | |
1501 | } | |
1502 | ||
581be094 | 1503 | /* Some features automatically imply others: */ |
81e69fb0 | 1504 | if (arm_feature(env, ARM_FEATURE_V8)) { |
5256df88 RH |
1505 | if (arm_feature(env, ARM_FEATURE_M)) { |
1506 | set_feature(env, ARM_FEATURE_V7); | |
1507 | } else { | |
1508 | set_feature(env, ARM_FEATURE_V7VE); | |
1509 | } | |
5110e683 | 1510 | } |
0f8d06f1 RH |
1511 | |
1512 | /* | |
1513 | * There exist AArch64 cpus without AArch32 support. When KVM | |
1514 | * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. | |
1515 | * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. | |
8f4821d7 PM |
1516 | * As a general principle, we also do not make ID register |
1517 | * consistency checks anywhere unless using TCG, because only | |
1518 | * for TCG would a consistency-check failure be a QEMU bug. | |
0f8d06f1 RH |
1519 | */ |
1520 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
1521 | no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); | |
1522 | } | |
1523 | ||
5110e683 AL |
1524 | if (arm_feature(env, ARM_FEATURE_V7VE)) { |
1525 | /* v7 Virtualization Extensions. In real hardware this implies | |
1526 | * EL2 and also the presence of the Security Extensions. | |
1527 | * For QEMU, for backwards-compatibility we implement some | |
1528 | * CPUs or CPU configs which have no actual EL2 or EL3 but do | |
1529 | * include the various other features that V7VE implies. | |
1530 | * Presence of EL2 itself is ARM_FEATURE_EL2, and of the | |
1531 | * Security Extensions is ARM_FEATURE_EL3. | |
1532 | */ | |
873b73c0 PM |
1533 | assert(!tcg_enabled() || no_aa32 || |
1534 | cpu_isar_feature(aa32_arm_div, cpu)); | |
81e69fb0 | 1535 | set_feature(env, ARM_FEATURE_LPAE); |
5110e683 | 1536 | set_feature(env, ARM_FEATURE_V7); |
81e69fb0 | 1537 | } |
581be094 PM |
1538 | if (arm_feature(env, ARM_FEATURE_V7)) { |
1539 | set_feature(env, ARM_FEATURE_VAPA); | |
1540 | set_feature(env, ARM_FEATURE_THUMB2); | |
81bdde9d | 1541 | set_feature(env, ARM_FEATURE_MPIDR); |
581be094 PM |
1542 | if (!arm_feature(env, ARM_FEATURE_M)) { |
1543 | set_feature(env, ARM_FEATURE_V6K); | |
1544 | } else { | |
1545 | set_feature(env, ARM_FEATURE_V6); | |
1546 | } | |
91db4642 CLG |
1547 | |
1548 | /* Always define VBAR for V7 CPUs even if it doesn't exist in | |
1549 | * non-EL3 configs. This is needed by some legacy boards. | |
1550 | */ | |
1551 | set_feature(env, ARM_FEATURE_VBAR); | |
581be094 PM |
1552 | } |
1553 | if (arm_feature(env, ARM_FEATURE_V6K)) { | |
1554 | set_feature(env, ARM_FEATURE_V6); | |
1555 | set_feature(env, ARM_FEATURE_MVFR); | |
1556 | } | |
1557 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
1558 | set_feature(env, ARM_FEATURE_V5); | |
1559 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
873b73c0 PM |
1560 | assert(!tcg_enabled() || no_aa32 || |
1561 | cpu_isar_feature(aa32_jazelle, cpu)); | |
581be094 PM |
1562 | set_feature(env, ARM_FEATURE_AUXCR); |
1563 | } | |
1564 | } | |
1565 | if (arm_feature(env, ARM_FEATURE_V5)) { | |
1566 | set_feature(env, ARM_FEATURE_V4T); | |
1567 | } | |
de9b05b8 | 1568 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
bdcc150d | 1569 | set_feature(env, ARM_FEATURE_V7MP); |
de9b05b8 PM |
1570 | set_feature(env, ARM_FEATURE_PXN); |
1571 | } | |
f318cec6 PM |
1572 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { |
1573 | set_feature(env, ARM_FEATURE_CBAR); | |
1574 | } | |
62b44f05 AR |
1575 | if (arm_feature(env, ARM_FEATURE_THUMB2) && |
1576 | !arm_feature(env, ARM_FEATURE_M)) { | |
1577 | set_feature(env, ARM_FEATURE_THUMB_DSP); | |
1578 | } | |
2ceb98c0 | 1579 | |
ea7ac69d PM |
1580 | /* |
1581 | * We rely on no XScale CPU having VFP so we can use the same bits in the | |
1582 | * TB flags field for VECSTRIDE and XSCALE_CPAR. | |
1583 | */ | |
7d63183f RH |
1584 | assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || |
1585 | !cpu_isar_feature(aa32_vfp_simd, cpu) || | |
1586 | !arm_feature(env, ARM_FEATURE_XSCALE)); | |
ea7ac69d | 1587 | |
e97da98f PM |
1588 | if (arm_feature(env, ARM_FEATURE_V7) && |
1589 | !arm_feature(env, ARM_FEATURE_M) && | |
452a0955 | 1590 | !arm_feature(env, ARM_FEATURE_PMSA)) { |
e97da98f PM |
1591 | /* v7VMSA drops support for the old ARMv5 tiny pages, so we |
1592 | * can use 4K pages. | |
1593 | */ | |
1594 | pagebits = 12; | |
1595 | } else { | |
1596 | /* For CPUs which might have tiny 1K pages, or which have an | |
1597 | * MPU and might have small region sizes, stick with 1K pages. | |
1598 | */ | |
1599 | pagebits = 10; | |
1600 | } | |
1601 | if (!set_preferred_target_page_bits(pagebits)) { | |
1602 | /* This can only ever happen for hotplugging a CPU, or if | |
1603 | * the board code incorrectly creates a CPU which it has | |
1604 | * promised via minimum_page_size that it will not. | |
1605 | */ | |
1606 | error_setg(errp, "This CPU requires a smaller page size than the " | |
1607 | "system is using"); | |
1608 | return; | |
1609 | } | |
1610 | ||
ce5b1bbf LV |
1611 | /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. |
1612 | * We don't support setting cluster ID ([16..23]) (known as Aff2 | |
1613 | * in later ARM ARM versions), or any of the higher affinity level fields, | |
1614 | * so these bits always RAZ. | |
1615 | */ | |
1616 | if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { | |
46de5913 IM |
1617 | cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, |
1618 | ARM_DEFAULT_CPUS_PER_CLUSTER); | |
ce5b1bbf LV |
1619 | } |
1620 | ||
68e0a40a AP |
1621 | if (cpu->reset_hivecs) { |
1622 | cpu->reset_sctlr |= (1 << 13); | |
1623 | } | |
1624 | ||
3a062d57 JB |
1625 | if (cpu->cfgend) { |
1626 | if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { | |
1627 | cpu->reset_sctlr |= SCTLR_EE; | |
1628 | } else { | |
1629 | cpu->reset_sctlr |= SCTLR_B; | |
1630 | } | |
1631 | } | |
1632 | ||
51942aee GB |
1633 | if (!cpu->has_el3) { |
1634 | /* If the has_el3 CPU property is disabled then we need to disable the | |
1635 | * feature. | |
1636 | */ | |
1637 | unset_feature(env, ARM_FEATURE_EL3); | |
1638 | ||
1639 | /* Disable the security extension feature bits in the processor feature | |
3d5c84ff | 1640 | * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. |
51942aee GB |
1641 | */ |
1642 | cpu->id_pfr1 &= ~0xf0; | |
47576b94 | 1643 | cpu->isar.id_aa64pfr0 &= ~0xf000; |
51942aee GB |
1644 | } |
1645 | ||
c25bd18a PM |
1646 | if (!cpu->has_el2) { |
1647 | unset_feature(env, ARM_FEATURE_EL2); | |
1648 | } | |
1649 | ||
d6f02ce3 | 1650 | if (!cpu->has_pmu) { |
929e754d | 1651 | unset_feature(env, ARM_FEATURE_PMU); |
57a4a11b AL |
1652 | } |
1653 | if (arm_feature(env, ARM_FEATURE_PMU)) { | |
bf8d0969 | 1654 | pmu_init(cpu); |
57a4a11b AL |
1655 | |
1656 | if (!kvm_enabled()) { | |
1657 | arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); | |
1658 | arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); | |
1659 | } | |
4e7beb0c AL |
1660 | |
1661 | #ifndef CONFIG_USER_ONLY | |
1662 | cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb, | |
1663 | cpu); | |
1664 | #endif | |
57a4a11b | 1665 | } else { |
2a609df8 PM |
1666 | cpu->isar.id_aa64dfr0 = |
1667 | FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); | |
a6179538 | 1668 | cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0); |
57a4a11b AL |
1669 | cpu->pmceid0 = 0; |
1670 | cpu->pmceid1 = 0; | |
929e754d WH |
1671 | } |
1672 | ||
3c2f7bb3 PM |
1673 | if (!arm_feature(env, ARM_FEATURE_EL2)) { |
1674 | /* Disable the hypervisor feature bits in the processor feature | |
1675 | * registers if we don't have EL2. These are id_pfr1[15:12] and | |
1676 | * id_aa64pfr0_el1[11:8]. | |
1677 | */ | |
47576b94 | 1678 | cpu->isar.id_aa64pfr0 &= ~0xf00; |
3c2f7bb3 PM |
1679 | cpu->id_pfr1 &= ~0xf000; |
1680 | } | |
1681 | ||
f50cd314 PM |
1682 | /* MPU can be configured out of a PMSA CPU either by setting has-mpu |
1683 | * to false or by setting pmsav7-dregion to 0. | |
1684 | */ | |
8f325f56 | 1685 | if (!cpu->has_mpu) { |
f50cd314 PM |
1686 | cpu->pmsav7_dregion = 0; |
1687 | } | |
1688 | if (cpu->pmsav7_dregion == 0) { | |
1689 | cpu->has_mpu = false; | |
8f325f56 PC |
1690 | } |
1691 | ||
452a0955 | 1692 | if (arm_feature(env, ARM_FEATURE_PMSA) && |
3281af81 PC |
1693 | arm_feature(env, ARM_FEATURE_V7)) { |
1694 | uint32_t nr = cpu->pmsav7_dregion; | |
1695 | ||
1696 | if (nr > 0xff) { | |
9af9e0fe | 1697 | error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); |
3281af81 PC |
1698 | return; |
1699 | } | |
6cb0b013 PC |
1700 | |
1701 | if (nr) { | |
0e1a46bb PM |
1702 | if (arm_feature(env, ARM_FEATURE_V8)) { |
1703 | /* PMSAv8 */ | |
62c58ee0 PM |
1704 | env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); |
1705 | env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); | |
1706 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
1707 | env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); | |
1708 | env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); | |
1709 | } | |
0e1a46bb PM |
1710 | } else { |
1711 | env->pmsav7.drbar = g_new0(uint32_t, nr); | |
1712 | env->pmsav7.drsr = g_new0(uint32_t, nr); | |
1713 | env->pmsav7.dracr = g_new0(uint32_t, nr); | |
1714 | } | |
6cb0b013 | 1715 | } |
3281af81 PC |
1716 | } |
1717 | ||
9901c576 PM |
1718 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
1719 | uint32_t nr = cpu->sau_sregion; | |
1720 | ||
1721 | if (nr > 0xff) { | |
1722 | error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); | |
1723 | return; | |
1724 | } | |
1725 | ||
1726 | if (nr) { | |
1727 | env->sau.rbar = g_new0(uint32_t, nr); | |
1728 | env->sau.rlar = g_new0(uint32_t, nr); | |
1729 | } | |
1730 | } | |
1731 | ||
91db4642 CLG |
1732 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
1733 | set_feature(env, ARM_FEATURE_VBAR); | |
1734 | } | |
1735 | ||
2ceb98c0 | 1736 | register_cp_regs_for_features(cpu); |
14969266 AF |
1737 | arm_cpu_register_gdb_regs_for_features(cpu); |
1738 | ||
721fae12 PM |
1739 | init_cpreg_list(cpu); |
1740 | ||
9e273ef2 | 1741 | #ifndef CONFIG_USER_ONLY |
cc7d44c2 LX |
1742 | MachineState *ms = MACHINE(qdev_get_machine()); |
1743 | unsigned int smp_cpus = ms->smp.cpus; | |
1744 | ||
1d2091bc | 1745 | if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
1d2091bc PM |
1746 | cs->num_ases = 2; |
1747 | ||
9e273ef2 PM |
1748 | if (!cpu->secure_memory) { |
1749 | cpu->secure_memory = cs->memory; | |
1750 | } | |
80ceb07a PX |
1751 | cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", |
1752 | cpu->secure_memory); | |
1d2091bc PM |
1753 | } else { |
1754 | cs->num_ases = 1; | |
9e273ef2 | 1755 | } |
80ceb07a | 1756 | cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); |
f9a69711 AF |
1757 | |
1758 | /* No core_count specified, default to smp_cpus. */ | |
1759 | if (cpu->core_count == -1) { | |
1760 | cpu->core_count = smp_cpus; | |
1761 | } | |
9e273ef2 PM |
1762 | #endif |
1763 | ||
a4157b80 RH |
1764 | if (tcg_enabled()) { |
1765 | int dcz_blocklen = 4 << cpu->dcz_blocksize; | |
1766 | ||
1767 | /* | |
1768 | * We only support DCZ blocklen that fits on one page. | |
1769 | * | |
1770 | * Architectually this is always true. However TARGET_PAGE_SIZE | |
1771 | * is variable and, for compatibility with -machine virt-2.7, | |
1772 | * is only 1KiB, as an artifact of legacy ARMv5 subpage support. | |
1773 | * But even then, while the largest architectural DCZ blocklen | |
1774 | * is 2KiB, no cpu actually uses such a large blocklen. | |
1775 | */ | |
1776 | assert(dcz_blocklen <= TARGET_PAGE_SIZE); | |
1777 | ||
1778 | /* | |
1779 | * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say | |
1780 | * both nibbles of each byte storing tag data may be written at once. | |
1781 | * Since TAG_GRANULE is 16, this means that blocklen must be >= 32. | |
1782 | */ | |
1783 | if (cpu_isar_feature(aa64_mte, cpu)) { | |
1784 | assert(dcz_blocklen >= 2 * TAG_GRANULE); | |
1785 | } | |
1786 | } | |
1787 | ||
14a10fc3 | 1788 | qemu_init_vcpu(cs); |
00d0f7cb | 1789 | cpu_reset(cs); |
14969266 AF |
1790 | |
1791 | acc->parent_realize(dev, errp); | |
581be094 PM |
1792 | } |
1793 | ||
5900d6b2 AF |
1794 | static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) |
1795 | { | |
1796 | ObjectClass *oc; | |
51492fd1 | 1797 | char *typename; |
fb8d6c24 | 1798 | char **cpuname; |
a0032cc5 | 1799 | const char *cpunamestr; |
5900d6b2 | 1800 | |
fb8d6c24 | 1801 | cpuname = g_strsplit(cpu_model, ",", 1); |
a0032cc5 PM |
1802 | cpunamestr = cpuname[0]; |
1803 | #ifdef CONFIG_USER_ONLY | |
1804 | /* For backwards compatibility usermode emulation allows "-cpu any", | |
1805 | * which has the same semantics as "-cpu max". | |
1806 | */ | |
1807 | if (!strcmp(cpunamestr, "any")) { | |
1808 | cpunamestr = "max"; | |
1809 | } | |
1810 | #endif | |
1811 | typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); | |
51492fd1 | 1812 | oc = object_class_by_name(typename); |
fb8d6c24 | 1813 | g_strfreev(cpuname); |
51492fd1 | 1814 | g_free(typename); |
245fb54d AF |
1815 | if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || |
1816 | object_class_is_abstract(oc)) { | |
5900d6b2 AF |
1817 | return NULL; |
1818 | } | |
1819 | return oc; | |
1820 | } | |
1821 | ||
15ee776b PM |
1822 | /* CPU models. These are not needed for the AArch64 linux-user build. */ |
1823 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | |
1824 | ||
34f90529 PM |
1825 | static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |
1826 | { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, | |
1827 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1828 | { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
1829 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1830 | REGINFO_SENTINEL | |
1831 | }; | |
1832 | ||
777dc784 PM |
1833 | static void cortex_a8_initfn(Object *obj) |
1834 | { | |
1835 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1836 | |
1837 | cpu->dtb_compatible = "arm,cortex-a8"; | |
581be094 | 1838 | set_feature(&cpu->env, ARM_FEATURE_V7); |
581be094 PM |
1839 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
1840 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c4804214 | 1841 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
c0ccb02d | 1842 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
b2d06f96 | 1843 | cpu->midr = 0x410fc080; |
325b3cef | 1844 | cpu->reset_fpsid = 0x410330c0; |
47576b94 RH |
1845 | cpu->isar.mvfr0 = 0x11110222; |
1846 | cpu->isar.mvfr1 = 0x00011111; | |
64e1671f | 1847 | cpu->ctr = 0x82048004; |
0ca7e01c | 1848 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
1849 | cpu->id_pfr0 = 0x1031; |
1850 | cpu->id_pfr1 = 0x11; | |
a6179538 | 1851 | cpu->isar.id_dfr0 = 0x400; |
2e4d7e3e | 1852 | cpu->id_afr0 = 0; |
10054016 PM |
1853 | cpu->isar.id_mmfr0 = 0x31100003; |
1854 | cpu->isar.id_mmfr1 = 0x20000000; | |
1855 | cpu->isar.id_mmfr2 = 0x01202000; | |
1856 | cpu->isar.id_mmfr3 = 0x11; | |
47576b94 RH |
1857 | cpu->isar.id_isar0 = 0x00101111; |
1858 | cpu->isar.id_isar1 = 0x12112111; | |
1859 | cpu->isar.id_isar2 = 0x21232031; | |
1860 | cpu->isar.id_isar3 = 0x11112131; | |
1861 | cpu->isar.id_isar4 = 0x00111142; | |
4426d361 | 1862 | cpu->isar.dbgdidr = 0x15141000; |
85df3786 PM |
1863 | cpu->clidr = (1 << 27) | (2 << 24) | 3; |
1864 | cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ | |
1865 | cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ | |
1866 | cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ | |
2771db27 | 1867 | cpu->reset_auxcr = 2; |
34f90529 | 1868 | define_arm_cp_regs(cpu, cortexa8_cp_reginfo); |
777dc784 PM |
1869 | } |
1870 | ||
1047b9d7 PM |
1871 | static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
1872 | /* power_control should be set to maximum latency. Again, | |
1873 | * default to 0 and set by private hook | |
1874 | */ | |
1875 | { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, | |
1876 | .access = PL1_RW, .resetvalue = 0, | |
1877 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, | |
1878 | { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1879 | .access = PL1_RW, .resetvalue = 0, | |
1880 | .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, | |
1881 | { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, | |
1882 | .access = PL1_RW, .resetvalue = 0, | |
1883 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, | |
1884 | { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
1885 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1886 | /* TLB lockdown control */ | |
1887 | { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, | |
1888 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
1889 | { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, | |
1890 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
1891 | { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, | |
1892 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1893 | { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, | |
1894 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1895 | { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, | |
1896 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1897 | REGINFO_SENTINEL | |
1898 | }; | |
1899 | ||
777dc784 PM |
1900 | static void cortex_a9_initfn(Object *obj) |
1901 | { | |
1902 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1903 | |
1904 | cpu->dtb_compatible = "arm,cortex-a9"; | |
581be094 | 1905 | set_feature(&cpu->env, ARM_FEATURE_V7); |
581be094 PM |
1906 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
1907 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c0ccb02d | 1908 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
581be094 PM |
1909 | /* Note that A9 supports the MP extensions even for |
1910 | * A9UP and single-core A9MP (which are both different | |
1911 | * and valid configurations; we don't model A9UP). | |
1912 | */ | |
1913 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
d8ba780b | 1914 | set_feature(&cpu->env, ARM_FEATURE_CBAR); |
b2d06f96 | 1915 | cpu->midr = 0x410fc090; |
325b3cef | 1916 | cpu->reset_fpsid = 0x41033090; |
47576b94 RH |
1917 | cpu->isar.mvfr0 = 0x11110222; |
1918 | cpu->isar.mvfr1 = 0x01111111; | |
64e1671f | 1919 | cpu->ctr = 0x80038003; |
0ca7e01c | 1920 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
1921 | cpu->id_pfr0 = 0x1031; |
1922 | cpu->id_pfr1 = 0x11; | |
a6179538 | 1923 | cpu->isar.id_dfr0 = 0x000; |
2e4d7e3e | 1924 | cpu->id_afr0 = 0; |
10054016 PM |
1925 | cpu->isar.id_mmfr0 = 0x00100103; |
1926 | cpu->isar.id_mmfr1 = 0x20000000; | |
1927 | cpu->isar.id_mmfr2 = 0x01230000; | |
1928 | cpu->isar.id_mmfr3 = 0x00002111; | |
47576b94 RH |
1929 | cpu->isar.id_isar0 = 0x00101111; |
1930 | cpu->isar.id_isar1 = 0x13112111; | |
1931 | cpu->isar.id_isar2 = 0x21232041; | |
1932 | cpu->isar.id_isar3 = 0x11112131; | |
1933 | cpu->isar.id_isar4 = 0x00111142; | |
4426d361 | 1934 | cpu->isar.dbgdidr = 0x35141000; |
85df3786 | 1935 | cpu->clidr = (1 << 27) | (1 << 24) | 3; |
f7838b52 PC |
1936 | cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ |
1937 | cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ | |
d8ba780b | 1938 | define_arm_cp_regs(cpu, cortexa9_cp_reginfo); |
777dc784 PM |
1939 | } |
1940 | ||
34f90529 | 1941 | #ifndef CONFIG_USER_ONLY |
c4241c7d | 1942 | static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
34f90529 | 1943 | { |
cc7d44c2 LX |
1944 | MachineState *ms = MACHINE(qdev_get_machine()); |
1945 | ||
34f90529 PM |
1946 | /* Linux wants the number of processors from here. |
1947 | * Might as well set the interrupt-controller bit too. | |
1948 | */ | |
cc7d44c2 | 1949 | return ((ms->smp.cpus - 1) << 24) | (1 << 23); |
34f90529 PM |
1950 | } |
1951 | #endif | |
1952 | ||
1953 | static const ARMCPRegInfo cortexa15_cp_reginfo[] = { | |
1954 | #ifndef CONFIG_USER_ONLY | |
1955 | { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
1956 | .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, | |
1957 | .writefn = arm_cp_write_ignore, }, | |
1958 | #endif | |
1959 | { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, | |
1960 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1961 | REGINFO_SENTINEL | |
1962 | }; | |
1963 | ||
dcf578ed AY |
1964 | static void cortex_a7_initfn(Object *obj) |
1965 | { | |
1966 | ARMCPU *cpu = ARM_CPU(obj); | |
1967 | ||
1968 | cpu->dtb_compatible = "arm,cortex-a7"; | |
5110e683 | 1969 | set_feature(&cpu->env, ARM_FEATURE_V7VE); |
dcf578ed AY |
1970 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
1971 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
dcf578ed AY |
1972 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
1973 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | |
1974 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | |
436c0cbb | 1975 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
dcf578ed | 1976 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
a46118fc | 1977 | set_feature(&cpu->env, ARM_FEATURE_PMU); |
dcf578ed AY |
1978 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; |
1979 | cpu->midr = 0x410fc075; | |
1980 | cpu->reset_fpsid = 0x41023075; | |
47576b94 RH |
1981 | cpu->isar.mvfr0 = 0x10110222; |
1982 | cpu->isar.mvfr1 = 0x11111111; | |
dcf578ed AY |
1983 | cpu->ctr = 0x84448003; |
1984 | cpu->reset_sctlr = 0x00c50078; | |
1985 | cpu->id_pfr0 = 0x00001131; | |
1986 | cpu->id_pfr1 = 0x00011011; | |
a6179538 | 1987 | cpu->isar.id_dfr0 = 0x02010555; |
dcf578ed | 1988 | cpu->id_afr0 = 0x00000000; |
10054016 PM |
1989 | cpu->isar.id_mmfr0 = 0x10101105; |
1990 | cpu->isar.id_mmfr1 = 0x40000000; | |
1991 | cpu->isar.id_mmfr2 = 0x01240000; | |
1992 | cpu->isar.id_mmfr3 = 0x02102211; | |
37bdda89 RH |
1993 | /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but |
1994 | * table 4-41 gives 0x02101110, which includes the arm div insns. | |
1995 | */ | |
47576b94 RH |
1996 | cpu->isar.id_isar0 = 0x02101110; |
1997 | cpu->isar.id_isar1 = 0x13112111; | |
1998 | cpu->isar.id_isar2 = 0x21232041; | |
1999 | cpu->isar.id_isar3 = 0x11112131; | |
2000 | cpu->isar.id_isar4 = 0x10011142; | |
4426d361 | 2001 | cpu->isar.dbgdidr = 0x3515f005; |
dcf578ed AY |
2002 | cpu->clidr = 0x0a200023; |
2003 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
2004 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
2005 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
2006 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ | |
2007 | } | |
2008 | ||
777dc784 PM |
2009 | static void cortex_a15_initfn(Object *obj) |
2010 | { | |
2011 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
2012 | |
2013 | cpu->dtb_compatible = "arm,cortex-a15"; | |
5110e683 | 2014 | set_feature(&cpu->env, ARM_FEATURE_V7VE); |
581be094 PM |
2015 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
2016 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
581be094 | 2017 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
c4804214 | 2018 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
c29f9a0a | 2019 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
436c0cbb | 2020 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
c0ccb02d | 2021 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
a46118fc | 2022 | set_feature(&cpu->env, ARM_FEATURE_PMU); |
3541addc | 2023 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; |
b2d06f96 | 2024 | cpu->midr = 0x412fc0f1; |
325b3cef | 2025 | cpu->reset_fpsid = 0x410430f0; |
47576b94 RH |
2026 | cpu->isar.mvfr0 = 0x10110222; |
2027 | cpu->isar.mvfr1 = 0x11111111; | |
64e1671f | 2028 | cpu->ctr = 0x8444c004; |
0ca7e01c | 2029 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
2030 | cpu->id_pfr0 = 0x00001131; |
2031 | cpu->id_pfr1 = 0x00011011; | |
a6179538 | 2032 | cpu->isar.id_dfr0 = 0x02010555; |
2e4d7e3e | 2033 | cpu->id_afr0 = 0x00000000; |
10054016 PM |
2034 | cpu->isar.id_mmfr0 = 0x10201105; |
2035 | cpu->isar.id_mmfr1 = 0x20000000; | |
2036 | cpu->isar.id_mmfr2 = 0x01240000; | |
2037 | cpu->isar.id_mmfr3 = 0x02102211; | |
47576b94 RH |
2038 | cpu->isar.id_isar0 = 0x02101110; |
2039 | cpu->isar.id_isar1 = 0x13112111; | |
2040 | cpu->isar.id_isar2 = 0x21232041; | |
2041 | cpu->isar.id_isar3 = 0x11112131; | |
2042 | cpu->isar.id_isar4 = 0x10011142; | |
4426d361 | 2043 | cpu->isar.dbgdidr = 0x3515f021; |
85df3786 PM |
2044 | cpu->clidr = 0x0a200023; |
2045 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
2046 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
2047 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
34f90529 | 2048 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); |
777dc784 PM |
2049 | } |
2050 | ||
bab52d4b PM |
2051 | #ifndef TARGET_AARCH64 |
2052 | /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); | |
2053 | * otherwise, a CPU with as many features enabled as our emulation supports. | |
2054 | * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; | |
2055 | * this only needs to handle 32 bits. | |
2056 | */ | |
2057 | static void arm_max_initfn(Object *obj) | |
2058 | { | |
2059 | ARMCPU *cpu = ARM_CPU(obj); | |
2060 | ||
2061 | if (kvm_enabled()) { | |
2062 | kvm_arm_set_cpu_features_from_host(cpu); | |
2063 | } else { | |
2064 | cortex_a15_initfn(obj); | |
973751fd PM |
2065 | |
2066 | /* old-style VFP short-vector support */ | |
2067 | cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); | |
2068 | ||
a0032cc5 PM |
2069 | #ifdef CONFIG_USER_ONLY |
2070 | /* We don't set these in system emulation mode for the moment, | |
962fcbf2 RH |
2071 | * since we don't correctly set (all of) the ID registers to |
2072 | * advertise them. | |
bab52d4b | 2073 | */ |
a0032cc5 | 2074 | set_feature(&cpu->env, ARM_FEATURE_V8); |
962fcbf2 RH |
2075 | { |
2076 | uint32_t t; | |
2077 | ||
2078 | t = cpu->isar.id_isar5; | |
2079 | t = FIELD_DP32(t, ID_ISAR5, AES, 2); | |
2080 | t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | |
2081 | t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | |
2082 | t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | |
2083 | t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | |
2084 | t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | |
2085 | cpu->isar.id_isar5 = t; | |
2086 | ||
2087 | t = cpu->isar.id_isar6; | |
6c1f6f27 | 2088 | t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); |
962fcbf2 | 2089 | t = FIELD_DP32(t, ID_ISAR6, DP, 1); |
991c0599 | 2090 | t = FIELD_DP32(t, ID_ISAR6, FHM, 1); |
9888bd1e | 2091 | t = FIELD_DP32(t, ID_ISAR6, SB, 1); |
cb570bd3 | 2092 | t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); |
962fcbf2 | 2093 | cpu->isar.id_isar6 = t; |
ab638a32 | 2094 | |
45b1a243 AB |
2095 | t = cpu->isar.mvfr1; |
2096 | t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */ | |
2097 | cpu->isar.mvfr1 = t; | |
2098 | ||
c8877d0f RH |
2099 | t = cpu->isar.mvfr2; |
2100 | t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | |
2101 | t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | |
2102 | cpu->isar.mvfr2 = t; | |
2103 | ||
10054016 | 2104 | t = cpu->isar.id_mmfr3; |
e0fe7309 | 2105 | t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ |
10054016 | 2106 | cpu->isar.id_mmfr3 = t; |
e0fe7309 | 2107 | |
10054016 | 2108 | t = cpu->isar.id_mmfr4; |
ab638a32 | 2109 | t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ |
f6287c24 | 2110 | t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ |
41a4bf1f | 2111 | t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ |
ce3125be | 2112 | t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ |
10054016 | 2113 | cpu->isar.id_mmfr4 = t; |
962fcbf2 | 2114 | } |
bab52d4b | 2115 | #endif |
a0032cc5 | 2116 | } |
777dc784 | 2117 | } |
f5f6d38b | 2118 | #endif |
777dc784 | 2119 | |
15ee776b PM |
2120 | #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ |
2121 | ||
777dc784 | 2122 | static const ARMCPUInfo arm_cpus[] = { |
15ee776b | 2123 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) |
dcf578ed | 2124 | { .name = "cortex-a7", .initfn = cortex_a7_initfn }, |
777dc784 PM |
2125 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, |
2126 | { .name = "cortex-a9", .initfn = cortex_a9_initfn }, | |
2127 | { .name = "cortex-a15", .initfn = cortex_a15_initfn }, | |
bab52d4b PM |
2128 | #ifndef TARGET_AARCH64 |
2129 | { .name = "max", .initfn = arm_max_initfn }, | |
2130 | #endif | |
f5f6d38b | 2131 | #ifdef CONFIG_USER_ONLY |
a0032cc5 | 2132 | { .name = "any", .initfn = arm_max_initfn }, |
f5f6d38b | 2133 | #endif |
15ee776b | 2134 | #endif |
777dc784 PM |
2135 | }; |
2136 | ||
5de16430 PM |
2137 | static Property arm_cpu_properties[] = { |
2138 | DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), | |
98128601 | 2139 | DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), |
e544f800 | 2140 | DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), |
ce5b1bbf LV |
2141 | DEFINE_PROP_UINT64("mp-affinity", ARMCPU, |
2142 | mp_affinity, ARM64_AFFINITY_INVALID), | |
15f8b142 | 2143 | DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), |
f9a69711 | 2144 | DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), |
5de16430 PM |
2145 | DEFINE_PROP_END_OF_LIST() |
2146 | }; | |
2147 | ||
b3820e6c DH |
2148 | static gchar *arm_gdb_arch_name(CPUState *cs) |
2149 | { | |
2150 | ARMCPU *cpu = ARM_CPU(cs); | |
2151 | CPUARMState *env = &cpu->env; | |
2152 | ||
2153 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
2154 | return g_strdup("iwmmxt"); | |
2155 | } | |
2156 | return g_strdup("arm"); | |
2157 | } | |
2158 | ||
dec9c2d4 AF |
2159 | static void arm_cpu_class_init(ObjectClass *oc, void *data) |
2160 | { | |
2161 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
2162 | CPUClass *cc = CPU_CLASS(acc); | |
14969266 AF |
2163 | DeviceClass *dc = DEVICE_CLASS(oc); |
2164 | ||
bf853881 PMD |
2165 | device_class_set_parent_realize(dc, arm_cpu_realizefn, |
2166 | &acc->parent_realize); | |
dec9c2d4 | 2167 | |
4f67d30b | 2168 | device_class_set_props(dc, arm_cpu_properties); |
781c67ca | 2169 | device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); |
5900d6b2 AF |
2170 | |
2171 | cc->class_by_name = arm_cpu_class_by_name; | |
8c2e1b00 | 2172 | cc->has_work = arm_cpu_has_work; |
e8925712 | 2173 | cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; |
878096ee | 2174 | cc->dump_state = arm_cpu_dump_state; |
f45748f1 | 2175 | cc->set_pc = arm_cpu_set_pc; |
42f6ed91 | 2176 | cc->synchronize_from_tb = arm_cpu_synchronize_from_tb; |
5b50e790 AF |
2177 | cc->gdb_read_register = arm_cpu_gdb_read_register; |
2178 | cc->gdb_write_register = arm_cpu_gdb_write_register; | |
7350d553 | 2179 | #ifndef CONFIG_USER_ONLY |
0adf7d3c | 2180 | cc->do_interrupt = arm_cpu_do_interrupt; |
0faea0c7 | 2181 | cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; |
017518c1 | 2182 | cc->asidx_from_attrs = arm_asidx_from_attrs; |
00b941e5 | 2183 | cc->vmsd = &vmstate_arm_cpu; |
ed50ff78 | 2184 | cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; |
da2b9140 AJ |
2185 | cc->write_elf64_note = arm_cpu_write_elf64_note; |
2186 | cc->write_elf32_note = arm_cpu_write_elf32_note; | |
00b941e5 | 2187 | #endif |
a0e372f0 | 2188 | cc->gdb_num_core_regs = 26; |
5b24c641 | 2189 | cc->gdb_core_xml_file = "arm-core.xml"; |
b3820e6c | 2190 | cc->gdb_arch_name = arm_gdb_arch_name; |
200bf5b7 | 2191 | cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; |
2472b6c0 | 2192 | cc->gdb_stop_before_watchpoint = true; |
48440620 | 2193 | cc->disas_set_info = arm_disas_set_info; |
74d7fc7f | 2194 | #ifdef CONFIG_TCG |
55c3ceef | 2195 | cc->tcg_initialize = arm_translate_init; |
7350d553 | 2196 | cc->tlb_fill = arm_cpu_tlb_fill; |
9dd5cca4 PMD |
2197 | cc->debug_excp_handler = arm_debug_excp_handler; |
2198 | cc->debug_check_watchpoint = arm_debug_check_watchpoint; | |
e21b551c | 2199 | cc->do_unaligned_access = arm_cpu_do_unaligned_access; |
0d1762e9 | 2200 | #if !defined(CONFIG_USER_ONLY) |
e21b551c | 2201 | cc->do_transaction_failed = arm_cpu_do_transaction_failed; |
9dd5cca4 | 2202 | cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; |
e21b551c | 2203 | #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ |
74d7fc7f | 2204 | #endif |
dec9c2d4 AF |
2205 | } |
2206 | ||
86f0a186 PM |
2207 | #ifdef CONFIG_KVM |
2208 | static void arm_host_initfn(Object *obj) | |
2209 | { | |
2210 | ARMCPU *cpu = ARM_CPU(obj); | |
2211 | ||
2212 | kvm_arm_set_cpu_features_from_host(cpu); | |
87014c6b AJ |
2213 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { |
2214 | aarch64_add_sve_properties(obj); | |
2215 | } | |
51e5ef45 | 2216 | arm_cpu_post_init(obj); |
86f0a186 PM |
2217 | } |
2218 | ||
2219 | static const TypeInfo host_arm_cpu_type_info = { | |
2220 | .name = TYPE_ARM_HOST_CPU, | |
2221 | #ifdef TARGET_AARCH64 | |
2222 | .parent = TYPE_AARCH64_CPU, | |
2223 | #else | |
2224 | .parent = TYPE_ARM_CPU, | |
2225 | #endif | |
2226 | .instance_init = arm_host_initfn, | |
2227 | }; | |
2228 | ||
2229 | #endif | |
2230 | ||
51e5ef45 MAL |
2231 | static void arm_cpu_instance_init(Object *obj) |
2232 | { | |
2233 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); | |
2234 | ||
2235 | acc->info->initfn(obj); | |
2236 | arm_cpu_post_init(obj); | |
2237 | } | |
2238 | ||
2239 | static void cpu_register_class_init(ObjectClass *oc, void *data) | |
2240 | { | |
2241 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
2242 | ||
2243 | acc->info = data; | |
2244 | } | |
2245 | ||
37bcf244 | 2246 | void arm_cpu_register(const ARMCPUInfo *info) |
777dc784 PM |
2247 | { |
2248 | TypeInfo type_info = { | |
777dc784 PM |
2249 | .parent = TYPE_ARM_CPU, |
2250 | .instance_size = sizeof(ARMCPU), | |
51e5ef45 | 2251 | .instance_init = arm_cpu_instance_init, |
777dc784 | 2252 | .class_size = sizeof(ARMCPUClass), |
51e5ef45 MAL |
2253 | .class_init = info->class_init ?: cpu_register_class_init, |
2254 | .class_data = (void *)info, | |
777dc784 PM |
2255 | }; |
2256 | ||
51492fd1 | 2257 | type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); |
918fd083 | 2258 | type_register(&type_info); |
51492fd1 | 2259 | g_free((void *)type_info.name); |
777dc784 PM |
2260 | } |
2261 | ||
dec9c2d4 AF |
2262 | static const TypeInfo arm_cpu_type_info = { |
2263 | .name = TYPE_ARM_CPU, | |
2264 | .parent = TYPE_CPU, | |
2265 | .instance_size = sizeof(ARMCPU), | |
777dc784 | 2266 | .instance_init = arm_cpu_initfn, |
4b6a83fb | 2267 | .instance_finalize = arm_cpu_finalizefn, |
777dc784 | 2268 | .abstract = true, |
dec9c2d4 AF |
2269 | .class_size = sizeof(ARMCPUClass), |
2270 | .class_init = arm_cpu_class_init, | |
2271 | }; | |
2272 | ||
181962fd PM |
2273 | static const TypeInfo idau_interface_type_info = { |
2274 | .name = TYPE_IDAU_INTERFACE, | |
2275 | .parent = TYPE_INTERFACE, | |
2276 | .class_size = sizeof(IDAUInterfaceClass), | |
2277 | }; | |
2278 | ||
dec9c2d4 AF |
2279 | static void arm_cpu_register_types(void) |
2280 | { | |
92b6a659 | 2281 | const size_t cpu_count = ARRAY_SIZE(arm_cpus); |
777dc784 | 2282 | |
dec9c2d4 | 2283 | type_register_static(&arm_cpu_type_info); |
83e6813a | 2284 | |
86f0a186 PM |
2285 | #ifdef CONFIG_KVM |
2286 | type_register_static(&host_arm_cpu_type_info); | |
2287 | #endif | |
92b6a659 PMD |
2288 | |
2289 | if (cpu_count) { | |
2290 | size_t i; | |
2291 | ||
fcdf0a90 | 2292 | type_register_static(&idau_interface_type_info); |
92b6a659 PMD |
2293 | for (i = 0; i < cpu_count; ++i) { |
2294 | arm_cpu_register(&arm_cpus[i]); | |
2295 | } | |
2296 | } | |
dec9c2d4 AF |
2297 | } |
2298 | ||
2299 | type_init(arm_cpu_register_types) |