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dec9c2d4 AF |
1 | /* |
2 | * QEMU ARM CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
74c21bd0 | 21 | #include "qemu/osdep.h" |
181962fd | 22 | #include "target/arm/idau.h" |
929e754d | 23 | #include "qemu/error-report.h" |
da34e65c | 24 | #include "qapi/error.h" |
778c3a06 | 25 | #include "cpu.h" |
ccd38087 | 26 | #include "internals.h" |
dec9c2d4 | 27 | #include "qemu-common.h" |
63c91552 | 28 | #include "exec/exec-all.h" |
5de16430 | 29 | #include "hw/qdev-properties.h" |
3c30dd5a PM |
30 | #if !defined(CONFIG_USER_ONLY) |
31 | #include "hw/loader.h" | |
32 | #endif | |
7c1840b6 | 33 | #include "hw/arm/arm.h" |
9c17d615 | 34 | #include "sysemu/sysemu.h" |
b3946626 | 35 | #include "sysemu/hw_accel.h" |
50a2c6e5 | 36 | #include "kvm_arm.h" |
110f6c70 | 37 | #include "disas/capstone.h" |
24f91e81 | 38 | #include "fpu/softfloat.h" |
dec9c2d4 | 39 | |
f45748f1 AF |
40 | static void arm_cpu_set_pc(CPUState *cs, vaddr value) |
41 | { | |
42 | ARMCPU *cpu = ARM_CPU(cs); | |
43 | ||
44 | cpu->env.regs[15] = value; | |
45 | } | |
46 | ||
8c2e1b00 AF |
47 | static bool arm_cpu_has_work(CPUState *cs) |
48 | { | |
543486db RH |
49 | ARMCPU *cpu = ARM_CPU(cs); |
50 | ||
062ba099 | 51 | return (cpu->power_state != PSCI_OFF) |
543486db | 52 | && cs->interrupt_request & |
136e67e9 EI |
53 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD |
54 | | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | |
55 | | CPU_INTERRUPT_EXITTB); | |
8c2e1b00 AF |
56 | } |
57 | ||
b5c53d1b AL |
58 | void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
59 | void *opaque) | |
60 | { | |
61 | ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); | |
62 | ||
63 | entry->hook = hook; | |
64 | entry->opaque = opaque; | |
65 | ||
66 | QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node); | |
67 | } | |
68 | ||
08267487 | 69 | void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
bd7d00fc PM |
70 | void *opaque) |
71 | { | |
08267487 AL |
72 | ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1); |
73 | ||
74 | entry->hook = hook; | |
75 | entry->opaque = opaque; | |
76 | ||
77 | QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); | |
bd7d00fc PM |
78 | } |
79 | ||
4b6a83fb PM |
80 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
81 | { | |
82 | /* Reset a single ARMCPRegInfo register */ | |
83 | ARMCPRegInfo *ri = value; | |
84 | ARMCPU *cpu = opaque; | |
85 | ||
b061a82b | 86 | if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { |
4b6a83fb PM |
87 | return; |
88 | } | |
89 | ||
90 | if (ri->resetfn) { | |
91 | ri->resetfn(&cpu->env, ri); | |
92 | return; | |
93 | } | |
94 | ||
95 | /* A zero offset is never possible as it would be regs[0] | |
96 | * so we use it to indicate that reset is being handled elsewhere. | |
97 | * This is basically only used for fields in non-core coprocessors | |
98 | * (like the pxa2xx ones). | |
99 | */ | |
100 | if (!ri->fieldoffset) { | |
101 | return; | |
102 | } | |
103 | ||
67ed771d | 104 | if (cpreg_field_is_64bit(ri)) { |
4b6a83fb PM |
105 | CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; |
106 | } else { | |
107 | CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; | |
108 | } | |
109 | } | |
110 | ||
49a66191 PM |
111 | static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) |
112 | { | |
113 | /* Purely an assertion check: we've already done reset once, | |
114 | * so now check that running the reset for the cpreg doesn't | |
115 | * change its value. This traps bugs where two different cpregs | |
116 | * both try to reset the same state field but to different values. | |
117 | */ | |
118 | ARMCPRegInfo *ri = value; | |
119 | ARMCPU *cpu = opaque; | |
120 | uint64_t oldvalue, newvalue; | |
121 | ||
122 | if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { | |
123 | return; | |
124 | } | |
125 | ||
126 | oldvalue = read_raw_cp_reg(&cpu->env, ri); | |
127 | cp_reg_reset(key, value, opaque); | |
128 | newvalue = read_raw_cp_reg(&cpu->env, ri); | |
129 | assert(oldvalue == newvalue); | |
130 | } | |
131 | ||
dec9c2d4 AF |
132 | /* CPUClass::reset() */ |
133 | static void arm_cpu_reset(CPUState *s) | |
134 | { | |
135 | ARMCPU *cpu = ARM_CPU(s); | |
136 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); | |
3c30dd5a | 137 | CPUARMState *env = &cpu->env; |
3c30dd5a | 138 | |
dec9c2d4 AF |
139 | acc->parent_reset(s); |
140 | ||
1f5c00cf AB |
141 | memset(env, 0, offsetof(CPUARMState, end_reset_fields)); |
142 | ||
4b6a83fb | 143 | g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
49a66191 PM |
144 | g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu); |
145 | ||
3c30dd5a | 146 | env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
47576b94 RH |
147 | env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0; |
148 | env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1; | |
149 | env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2; | |
3c30dd5a | 150 | |
062ba099 | 151 | cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON; |
543486db RH |
152 | s->halted = cpu->start_powered_off; |
153 | ||
3c30dd5a PM |
154 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { |
155 | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; | |
156 | } | |
157 | ||
3926cc84 AG |
158 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
159 | /* 64 bit CPUs always start in 64 bit mode */ | |
160 | env->aarch64 = 1; | |
d356312f PM |
161 | #if defined(CONFIG_USER_ONLY) |
162 | env->pstate = PSTATE_MODE_EL0t; | |
14e5f106 | 163 | /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ |
137feaa9 | 164 | env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; |
1ae9cfbd RH |
165 | /* Enable all PAC instructions */ |
166 | env->cp15.hcr_el2 |= HCR_API; | |
167 | env->cp15.scr_el3 |= SCR_API; | |
8c6afa6a | 168 | /* and to the FP/Neon instructions */ |
7ebd5f2e | 169 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3); |
802ac0e1 RH |
170 | /* and to the SVE instructions */ |
171 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); | |
172 | env->cp15.cptr_el[3] |= CPTR_EZ; | |
173 | /* with maximum vector length */ | |
adf92eab RH |
174 | env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; |
175 | env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; | |
176 | env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; | |
d356312f | 177 | #else |
5097227c GB |
178 | /* Reset into the highest available EL */ |
179 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
180 | env->pstate = PSTATE_MODE_EL3h; | |
181 | } else if (arm_feature(env, ARM_FEATURE_EL2)) { | |
182 | env->pstate = PSTATE_MODE_EL2h; | |
183 | } else { | |
184 | env->pstate = PSTATE_MODE_EL1h; | |
185 | } | |
3933443e | 186 | env->pc = cpu->rvbar; |
8c6afa6a PM |
187 | #endif |
188 | } else { | |
189 | #if defined(CONFIG_USER_ONLY) | |
190 | /* Userspace expects access to cp10 and cp11 for FP/Neon */ | |
7ebd5f2e | 191 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); |
d356312f | 192 | #endif |
3926cc84 AG |
193 | } |
194 | ||
3c30dd5a PM |
195 | #if defined(CONFIG_USER_ONLY) |
196 | env->uncached_cpsr = ARM_CPU_MODE_USR; | |
197 | /* For user mode we must enable access to coprocessors */ | |
198 | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; | |
199 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
200 | env->cp15.c15_cpar = 3; | |
201 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
202 | env->cp15.c15_cpar = 1; | |
203 | } | |
204 | #else | |
060a65df PM |
205 | |
206 | /* | |
207 | * If the highest available EL is EL2, AArch32 will start in Hyp | |
208 | * mode; otherwise it starts in SVC. Note that if we start in | |
209 | * AArch64 then these values in the uncached_cpsr will be ignored. | |
210 | */ | |
211 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
212 | !arm_feature(env, ARM_FEATURE_EL3)) { | |
213 | env->uncached_cpsr = ARM_CPU_MODE_HYP; | |
214 | } else { | |
215 | env->uncached_cpsr = ARM_CPU_MODE_SVC; | |
216 | } | |
4cc35614 | 217 | env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; |
dc7abe4d | 218 | |
531c60a9 | 219 | if (arm_feature(env, ARM_FEATURE_M)) { |
6e3cf5df MG |
220 | uint32_t initial_msp; /* Loaded from 0x0 */ |
221 | uint32_t initial_pc; /* Loaded from 0x4 */ | |
3c30dd5a | 222 | uint8_t *rom; |
38e2a77c | 223 | uint32_t vecbase; |
6e3cf5df | 224 | |
1e577cc7 PM |
225 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
226 | env->v7m.secure = true; | |
3b2e9344 PM |
227 | } else { |
228 | /* This bit resets to 0 if security is supported, but 1 if | |
229 | * it is not. The bit is not present in v7M, but we set it | |
230 | * here so we can avoid having to make checks on it conditional | |
231 | * on ARM_FEATURE_V8 (we don't let the guest see the bit). | |
232 | */ | |
233 | env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; | |
1e577cc7 PM |
234 | } |
235 | ||
9d40cd8a | 236 | /* In v7M the reset value of this bit is IMPDEF, but ARM recommends |
2c4da50d | 237 | * that it resets to 1, so QEMU always does that rather than making |
9d40cd8a | 238 | * it dependent on CPU model. In v8M it is RES1. |
2c4da50d | 239 | */ |
9d40cd8a PM |
240 | env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; |
241 | env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; | |
242 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
243 | /* in v8M the NONBASETHRDENA bit [0] is RES1 */ | |
244 | env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; | |
245 | env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; | |
246 | } | |
22ab3460 JS |
247 | if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { |
248 | env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK; | |
249 | env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; | |
250 | } | |
2c4da50d | 251 | |
056f43df PM |
252 | /* Unlike A/R profile, M profile defines the reset LR value */ |
253 | env->regs[14] = 0xffffffff; | |
254 | ||
38e2a77c PM |
255 | env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; |
256 | ||
257 | /* Load the initial SP and PC from offset 0 and 4 in the vector table */ | |
258 | vecbase = env->v7m.vecbase[env->v7m.secure]; | |
0f0f8b61 | 259 | rom = rom_ptr(vecbase, 8); |
3c30dd5a | 260 | if (rom) { |
6e3cf5df MG |
261 | /* Address zero is covered by ROM which hasn't yet been |
262 | * copied into physical memory. | |
263 | */ | |
264 | initial_msp = ldl_p(rom); | |
265 | initial_pc = ldl_p(rom + 4); | |
266 | } else { | |
267 | /* Address zero not covered by a ROM blob, or the ROM blob | |
268 | * is in non-modifiable memory and this is a second reset after | |
269 | * it got copied into memory. In the latter case, rom_ptr | |
270 | * will return a NULL pointer and we should use ldl_phys instead. | |
271 | */ | |
38e2a77c PM |
272 | initial_msp = ldl_phys(s->as, vecbase); |
273 | initial_pc = ldl_phys(s->as, vecbase + 4); | |
3c30dd5a | 274 | } |
6e3cf5df MG |
275 | |
276 | env->regs[13] = initial_msp & 0xFFFFFFFC; | |
277 | env->regs[15] = initial_pc & ~1; | |
278 | env->thumb = initial_pc & 1; | |
3c30dd5a | 279 | } |
387f9806 | 280 | |
137feaa9 FA |
281 | /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently |
282 | * executing as AArch32 then check if highvecs are enabled and | |
283 | * adjust the PC accordingly. | |
284 | */ | |
285 | if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { | |
34bf7744 | 286 | env->regs[15] = 0xFFFF0000; |
387f9806 AP |
287 | } |
288 | ||
dc3c4c14 PM |
289 | /* M profile requires that reset clears the exclusive monitor; |
290 | * A profile does not, but clearing it makes more sense than having it | |
291 | * set with an exclusive access on address zero. | |
292 | */ | |
293 | arm_clear_exclusive(env); | |
294 | ||
3c30dd5a | 295 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; |
3c30dd5a | 296 | #endif |
69ceea64 | 297 | |
0e1a46bb | 298 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
69ceea64 | 299 | if (cpu->pmsav7_dregion > 0) { |
0e1a46bb | 300 | if (arm_feature(env, ARM_FEATURE_V8)) { |
62c58ee0 PM |
301 | memset(env->pmsav8.rbar[M_REG_NS], 0, |
302 | sizeof(*env->pmsav8.rbar[M_REG_NS]) | |
303 | * cpu->pmsav7_dregion); | |
304 | memset(env->pmsav8.rlar[M_REG_NS], 0, | |
305 | sizeof(*env->pmsav8.rlar[M_REG_NS]) | |
306 | * cpu->pmsav7_dregion); | |
307 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
308 | memset(env->pmsav8.rbar[M_REG_S], 0, | |
309 | sizeof(*env->pmsav8.rbar[M_REG_S]) | |
310 | * cpu->pmsav7_dregion); | |
311 | memset(env->pmsav8.rlar[M_REG_S], 0, | |
312 | sizeof(*env->pmsav8.rlar[M_REG_S]) | |
313 | * cpu->pmsav7_dregion); | |
314 | } | |
0e1a46bb PM |
315 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
316 | memset(env->pmsav7.drbar, 0, | |
317 | sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); | |
318 | memset(env->pmsav7.drsr, 0, | |
319 | sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); | |
320 | memset(env->pmsav7.dracr, 0, | |
321 | sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); | |
322 | } | |
69ceea64 | 323 | } |
1bc04a88 PM |
324 | env->pmsav7.rnr[M_REG_NS] = 0; |
325 | env->pmsav7.rnr[M_REG_S] = 0; | |
4125e6fe PM |
326 | env->pmsav8.mair0[M_REG_NS] = 0; |
327 | env->pmsav8.mair0[M_REG_S] = 0; | |
328 | env->pmsav8.mair1[M_REG_NS] = 0; | |
329 | env->pmsav8.mair1[M_REG_S] = 0; | |
69ceea64 PM |
330 | } |
331 | ||
9901c576 PM |
332 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
333 | if (cpu->sau_sregion > 0) { | |
334 | memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion); | |
335 | memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion); | |
336 | } | |
337 | env->sau.rnr = 0; | |
338 | /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what | |
339 | * the Cortex-M33 does. | |
340 | */ | |
341 | env->sau.ctrl = 0; | |
342 | } | |
343 | ||
3c30dd5a PM |
344 | set_flush_to_zero(1, &env->vfp.standard_fp_status); |
345 | set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); | |
346 | set_default_nan_mode(1, &env->vfp.standard_fp_status); | |
347 | set_float_detect_tininess(float_tininess_before_rounding, | |
348 | &env->vfp.fp_status); | |
349 | set_float_detect_tininess(float_tininess_before_rounding, | |
350 | &env->vfp.standard_fp_status); | |
bcc531f0 PM |
351 | set_float_detect_tininess(float_tininess_before_rounding, |
352 | &env->vfp.fp_status_f16); | |
50a2c6e5 PB |
353 | #ifndef CONFIG_USER_ONLY |
354 | if (kvm_enabled()) { | |
355 | kvm_arm_reset_vcpu(cpu); | |
356 | } | |
357 | #endif | |
9ee98ce8 | 358 | |
46747d15 | 359 | hw_breakpoint_update_all(cpu); |
9ee98ce8 | 360 | hw_watchpoint_update_all(cpu); |
dec9c2d4 AF |
361 | } |
362 | ||
e8925712 RH |
363 | bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
364 | { | |
365 | CPUClass *cc = CPU_GET_CLASS(cs); | |
012a906b GB |
366 | CPUARMState *env = cs->env_ptr; |
367 | uint32_t cur_el = arm_current_el(env); | |
368 | bool secure = arm_is_secure(env); | |
369 | uint32_t target_el; | |
370 | uint32_t excp_idx; | |
e8925712 RH |
371 | bool ret = false; |
372 | ||
012a906b GB |
373 | if (interrupt_request & CPU_INTERRUPT_FIQ) { |
374 | excp_idx = EXCP_FIQ; | |
375 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
376 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
377 | cs->exception_index = excp_idx; | |
378 | env->exception.target_el = target_el; | |
379 | cc->do_interrupt(cs); | |
380 | ret = true; | |
381 | } | |
e8925712 | 382 | } |
012a906b GB |
383 | if (interrupt_request & CPU_INTERRUPT_HARD) { |
384 | excp_idx = EXCP_IRQ; | |
385 | target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure); | |
386 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
387 | cs->exception_index = excp_idx; | |
388 | env->exception.target_el = target_el; | |
389 | cc->do_interrupt(cs); | |
390 | ret = true; | |
391 | } | |
e8925712 | 392 | } |
012a906b GB |
393 | if (interrupt_request & CPU_INTERRUPT_VIRQ) { |
394 | excp_idx = EXCP_VIRQ; | |
395 | target_el = 1; | |
396 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
397 | cs->exception_index = excp_idx; | |
398 | env->exception.target_el = target_el; | |
399 | cc->do_interrupt(cs); | |
400 | ret = true; | |
401 | } | |
136e67e9 | 402 | } |
012a906b GB |
403 | if (interrupt_request & CPU_INTERRUPT_VFIQ) { |
404 | excp_idx = EXCP_VFIQ; | |
405 | target_el = 1; | |
406 | if (arm_excp_unmasked(cs, excp_idx, target_el)) { | |
407 | cs->exception_index = excp_idx; | |
408 | env->exception.target_el = target_el; | |
409 | cc->do_interrupt(cs); | |
410 | ret = true; | |
411 | } | |
136e67e9 | 412 | } |
e8925712 RH |
413 | |
414 | return ret; | |
415 | } | |
416 | ||
b5c633c5 PM |
417 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) |
418 | static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | |
419 | { | |
420 | CPUClass *cc = CPU_GET_CLASS(cs); | |
421 | ARMCPU *cpu = ARM_CPU(cs); | |
422 | CPUARMState *env = &cpu->env; | |
423 | bool ret = false; | |
424 | ||
f4e8e4ed | 425 | /* ARMv7-M interrupt masking works differently than -A or -R. |
7ecdaa4a PM |
426 | * There is no FIQ/IRQ distinction. Instead of I and F bits |
427 | * masking FIQ and IRQ interrupts, an exception is taken only | |
428 | * if it is higher priority than the current execution priority | |
429 | * (which depends on state like BASEPRI, FAULTMASK and the | |
430 | * currently active exception). | |
b5c633c5 PM |
431 | */ |
432 | if (interrupt_request & CPU_INTERRUPT_HARD | |
f4e8e4ed | 433 | && (armv7m_nvic_can_take_pending_exception(env->nvic))) { |
b5c633c5 PM |
434 | cs->exception_index = EXCP_IRQ; |
435 | cc->do_interrupt(cs); | |
436 | ret = true; | |
437 | } | |
438 | return ret; | |
439 | } | |
440 | #endif | |
441 | ||
89430fc6 PM |
442 | void arm_cpu_update_virq(ARMCPU *cpu) |
443 | { | |
444 | /* | |
445 | * Update the interrupt level for VIRQ, which is the logical OR of | |
446 | * the HCR_EL2.VI bit and the input line level from the GIC. | |
447 | */ | |
448 | CPUARMState *env = &cpu->env; | |
449 | CPUState *cs = CPU(cpu); | |
450 | ||
451 | bool new_state = (env->cp15.hcr_el2 & HCR_VI) || | |
452 | (env->irq_line_state & CPU_INTERRUPT_VIRQ); | |
453 | ||
454 | if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) { | |
455 | if (new_state) { | |
456 | cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); | |
457 | } else { | |
458 | cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); | |
459 | } | |
460 | } | |
461 | } | |
462 | ||
463 | void arm_cpu_update_vfiq(ARMCPU *cpu) | |
464 | { | |
465 | /* | |
466 | * Update the interrupt level for VFIQ, which is the logical OR of | |
467 | * the HCR_EL2.VF bit and the input line level from the GIC. | |
468 | */ | |
469 | CPUARMState *env = &cpu->env; | |
470 | CPUState *cs = CPU(cpu); | |
471 | ||
472 | bool new_state = (env->cp15.hcr_el2 & HCR_VF) || | |
473 | (env->irq_line_state & CPU_INTERRUPT_VFIQ); | |
474 | ||
475 | if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) { | |
476 | if (new_state) { | |
477 | cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); | |
478 | } else { | |
479 | cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ); | |
480 | } | |
481 | } | |
482 | } | |
483 | ||
7c1840b6 PM |
484 | #ifndef CONFIG_USER_ONLY |
485 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | |
486 | { | |
487 | ARMCPU *cpu = opaque; | |
136e67e9 | 488 | CPUARMState *env = &cpu->env; |
7c1840b6 | 489 | CPUState *cs = CPU(cpu); |
136e67e9 EI |
490 | static const int mask[] = { |
491 | [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD, | |
492 | [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ, | |
493 | [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ, | |
494 | [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ | |
495 | }; | |
7c1840b6 | 496 | |
ed89f078 PM |
497 | if (level) { |
498 | env->irq_line_state |= mask[irq]; | |
499 | } else { | |
500 | env->irq_line_state &= ~mask[irq]; | |
501 | } | |
502 | ||
7c1840b6 | 503 | switch (irq) { |
136e67e9 | 504 | case ARM_CPU_VIRQ: |
89430fc6 PM |
505 | assert(arm_feature(env, ARM_FEATURE_EL2)); |
506 | arm_cpu_update_virq(cpu); | |
507 | break; | |
136e67e9 | 508 | case ARM_CPU_VFIQ: |
f128bf29 | 509 | assert(arm_feature(env, ARM_FEATURE_EL2)); |
89430fc6 PM |
510 | arm_cpu_update_vfiq(cpu); |
511 | break; | |
136e67e9 | 512 | case ARM_CPU_IRQ: |
7c1840b6 PM |
513 | case ARM_CPU_FIQ: |
514 | if (level) { | |
136e67e9 | 515 | cpu_interrupt(cs, mask[irq]); |
7c1840b6 | 516 | } else { |
136e67e9 | 517 | cpu_reset_interrupt(cs, mask[irq]); |
7c1840b6 PM |
518 | } |
519 | break; | |
520 | default: | |
8f6fd322 | 521 | g_assert_not_reached(); |
7c1840b6 PM |
522 | } |
523 | } | |
524 | ||
525 | static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) | |
526 | { | |
527 | #ifdef CONFIG_KVM | |
528 | ARMCPU *cpu = opaque; | |
ed89f078 | 529 | CPUARMState *env = &cpu->env; |
7c1840b6 PM |
530 | CPUState *cs = CPU(cpu); |
531 | int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; | |
ed89f078 | 532 | uint32_t linestate_bit; |
7c1840b6 PM |
533 | |
534 | switch (irq) { | |
535 | case ARM_CPU_IRQ: | |
536 | kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; | |
ed89f078 | 537 | linestate_bit = CPU_INTERRUPT_HARD; |
7c1840b6 PM |
538 | break; |
539 | case ARM_CPU_FIQ: | |
540 | kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; | |
ed89f078 | 541 | linestate_bit = CPU_INTERRUPT_FIQ; |
7c1840b6 PM |
542 | break; |
543 | default: | |
8f6fd322 | 544 | g_assert_not_reached(); |
7c1840b6 | 545 | } |
ed89f078 PM |
546 | |
547 | if (level) { | |
548 | env->irq_line_state |= linestate_bit; | |
549 | } else { | |
550 | env->irq_line_state &= ~linestate_bit; | |
551 | } | |
552 | ||
7c1840b6 PM |
553 | kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; |
554 | kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); | |
555 | #endif | |
556 | } | |
84f2bed3 | 557 | |
ed50ff78 | 558 | static bool arm_cpu_virtio_is_big_endian(CPUState *cs) |
84f2bed3 PS |
559 | { |
560 | ARMCPU *cpu = ARM_CPU(cs); | |
561 | CPUARMState *env = &cpu->env; | |
84f2bed3 PS |
562 | |
563 | cpu_synchronize_state(cs); | |
ed50ff78 | 564 | return arm_cpu_data_is_big_endian(env); |
84f2bed3 PS |
565 | } |
566 | ||
7c1840b6 PM |
567 | #endif |
568 | ||
581be094 PM |
569 | static inline void set_feature(CPUARMState *env, int feature) |
570 | { | |
918f5dca | 571 | env->features |= 1ULL << feature; |
581be094 PM |
572 | } |
573 | ||
08828484 GB |
574 | static inline void unset_feature(CPUARMState *env, int feature) |
575 | { | |
576 | env->features &= ~(1ULL << feature); | |
577 | } | |
578 | ||
48440620 PC |
579 | static int |
580 | print_insn_thumb1(bfd_vma pc, disassemble_info *info) | |
581 | { | |
582 | return print_insn_arm(pc | 1, info); | |
583 | } | |
584 | ||
585 | static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) | |
586 | { | |
587 | ARMCPU *ac = ARM_CPU(cpu); | |
588 | CPUARMState *env = &ac->env; | |
7bcdbf51 | 589 | bool sctlr_b; |
48440620 PC |
590 | |
591 | if (is_a64(env)) { | |
592 | /* We might not be compiled with the A64 disassembler | |
593 | * because it needs a C++ compiler. Leave print_insn | |
594 | * unset in this case to use the caller default behaviour. | |
595 | */ | |
596 | #if defined(CONFIG_ARM_A64_DIS) | |
597 | info->print_insn = print_insn_arm_a64; | |
598 | #endif | |
110f6c70 | 599 | info->cap_arch = CS_ARCH_ARM64; |
15fa1a0a RH |
600 | info->cap_insn_unit = 4; |
601 | info->cap_insn_split = 4; | |
48440620 | 602 | } else { |
110f6c70 RH |
603 | int cap_mode; |
604 | if (env->thumb) { | |
605 | info->print_insn = print_insn_thumb1; | |
15fa1a0a RH |
606 | info->cap_insn_unit = 2; |
607 | info->cap_insn_split = 4; | |
110f6c70 RH |
608 | cap_mode = CS_MODE_THUMB; |
609 | } else { | |
610 | info->print_insn = print_insn_arm; | |
15fa1a0a RH |
611 | info->cap_insn_unit = 4; |
612 | info->cap_insn_split = 4; | |
110f6c70 RH |
613 | cap_mode = CS_MODE_ARM; |
614 | } | |
615 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
616 | cap_mode |= CS_MODE_V8; | |
617 | } | |
618 | if (arm_feature(env, ARM_FEATURE_M)) { | |
619 | cap_mode |= CS_MODE_MCLASS; | |
620 | } | |
621 | info->cap_arch = CS_ARCH_ARM; | |
622 | info->cap_mode = cap_mode; | |
48440620 | 623 | } |
7bcdbf51 RH |
624 | |
625 | sctlr_b = arm_sctlr_b(env); | |
626 | if (bswap_code(sctlr_b)) { | |
48440620 PC |
627 | #ifdef TARGET_WORDS_BIGENDIAN |
628 | info->endian = BFD_ENDIAN_LITTLE; | |
629 | #else | |
630 | info->endian = BFD_ENDIAN_BIG; | |
631 | #endif | |
632 | } | |
f7478a92 | 633 | info->flags &= ~INSN_ARM_BE32; |
7bcdbf51 RH |
634 | #ifndef CONFIG_USER_ONLY |
635 | if (sctlr_b) { | |
f7478a92 JB |
636 | info->flags |= INSN_ARM_BE32; |
637 | } | |
7bcdbf51 | 638 | #endif |
48440620 PC |
639 | } |
640 | ||
46de5913 IM |
641 | uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) |
642 | { | |
643 | uint32_t Aff1 = idx / clustersz; | |
644 | uint32_t Aff0 = idx % clustersz; | |
645 | return (Aff1 << ARM_AFF1_SHIFT) | Aff0; | |
646 | } | |
647 | ||
ac87e507 PM |
648 | static void cpreg_hashtable_data_destroy(gpointer data) |
649 | { | |
650 | /* | |
651 | * Destroy function for cpu->cp_regs hashtable data entries. | |
652 | * We must free the name string because it was g_strdup()ed in | |
653 | * add_cpreg_to_hashtable(). It's OK to cast away the 'const' | |
654 | * from r->name because we know we definitely allocated it. | |
655 | */ | |
656 | ARMCPRegInfo *r = data; | |
657 | ||
658 | g_free((void *)r->name); | |
659 | g_free(r); | |
660 | } | |
661 | ||
777dc784 PM |
662 | static void arm_cpu_initfn(Object *obj) |
663 | { | |
c05efcb1 | 664 | CPUState *cs = CPU(obj); |
777dc784 PM |
665 | ARMCPU *cpu = ARM_CPU(obj); |
666 | ||
c05efcb1 | 667 | cs->env_ptr = &cpu->env; |
4b6a83fb | 668 | cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
ac87e507 | 669 | g_free, cpreg_hashtable_data_destroy); |
79614b78 | 670 | |
b5c53d1b | 671 | QLIST_INIT(&cpu->pre_el_change_hooks); |
08267487 AL |
672 | QLIST_INIT(&cpu->el_change_hooks); |
673 | ||
7c1840b6 PM |
674 | #ifndef CONFIG_USER_ONLY |
675 | /* Our inbound IRQ and FIQ lines */ | |
676 | if (kvm_enabled()) { | |
136e67e9 EI |
677 | /* VIRQ and VFIQ are unused with KVM but we add them to maintain |
678 | * the same interface as non-KVM CPUs. | |
679 | */ | |
680 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); | |
7c1840b6 | 681 | } else { |
136e67e9 | 682 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); |
7c1840b6 | 683 | } |
55d284af | 684 | |
55d284af PM |
685 | qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, |
686 | ARRAY_SIZE(cpu->gt_timer_outputs)); | |
aa1b3111 PM |
687 | |
688 | qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt, | |
689 | "gicv3-maintenance-interrupt", 1); | |
07f48730 AJ |
690 | qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt, |
691 | "pmu-interrupt", 1); | |
7c1840b6 PM |
692 | #endif |
693 | ||
54d3e3f5 PM |
694 | /* DTB consumers generally don't in fact care what the 'compatible' |
695 | * string is, so always provide some string and trust that a hypothetical | |
696 | * picky DTB consumer will also provide a helpful error message. | |
697 | */ | |
698 | cpu->dtb_compatible = "qemu,unknown"; | |
dd032e34 | 699 | cpu->psci_version = 1; /* By default assume PSCI v0.1 */ |
3541addc | 700 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; |
54d3e3f5 | 701 | |
98128601 RH |
702 | if (tcg_enabled()) { |
703 | cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ | |
79614b78 | 704 | } |
4b6a83fb PM |
705 | } |
706 | ||
07a5b0d2 | 707 | static Property arm_cpu_reset_cbar_property = |
f318cec6 | 708 | DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); |
07a5b0d2 | 709 | |
68e0a40a AP |
710 | static Property arm_cpu_reset_hivecs_property = |
711 | DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); | |
712 | ||
3933443e PM |
713 | static Property arm_cpu_rvbar_property = |
714 | DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); | |
715 | ||
c25bd18a PM |
716 | static Property arm_cpu_has_el2_property = |
717 | DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); | |
718 | ||
51942aee GB |
719 | static Property arm_cpu_has_el3_property = |
720 | DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); | |
721 | ||
3a062d57 JB |
722 | static Property arm_cpu_cfgend_property = |
723 | DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); | |
724 | ||
929e754d WH |
725 | /* use property name "pmu" to match other archs and virt tools */ |
726 | static Property arm_cpu_has_pmu_property = | |
727 | DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); | |
728 | ||
8f325f56 PC |
729 | static Property arm_cpu_has_mpu_property = |
730 | DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); | |
731 | ||
8d92e26b PM |
732 | /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, |
733 | * because the CPU initfn will have already set cpu->pmsav7_dregion to | |
734 | * the right value for that particular CPU type, and we don't want | |
735 | * to override that with an incorrect constant value. | |
736 | */ | |
3281af81 | 737 | static Property arm_cpu_pmsav7_dregion_property = |
8d92e26b PM |
738 | DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, |
739 | pmsav7_dregion, | |
740 | qdev_prop_uint32, uint32_t); | |
3281af81 | 741 | |
38e2a77c PM |
742 | /* M profile: initial value of the Secure VTOR */ |
743 | static Property arm_cpu_initsvtor_property = | |
744 | DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0); | |
745 | ||
51e5ef45 | 746 | void arm_cpu_post_init(Object *obj) |
07a5b0d2 PC |
747 | { |
748 | ARMCPU *cpu = ARM_CPU(obj); | |
07a5b0d2 | 749 | |
790a1150 PM |
750 | /* M profile implies PMSA. We have to do this here rather than |
751 | * in realize with the other feature-implication checks because | |
752 | * we look at the PMSA bit to see if we should add some properties. | |
753 | */ | |
754 | if (arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
755 | set_feature(&cpu->env, ARM_FEATURE_PMSA); | |
756 | } | |
757 | ||
f318cec6 PM |
758 | if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || |
759 | arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { | |
07a5b0d2 | 760 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, |
5433a0a8 | 761 | &error_abort); |
07a5b0d2 | 762 | } |
68e0a40a AP |
763 | |
764 | if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
765 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, | |
5433a0a8 | 766 | &error_abort); |
68e0a40a | 767 | } |
3933443e PM |
768 | |
769 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
770 | qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, | |
771 | &error_abort); | |
772 | } | |
51942aee GB |
773 | |
774 | if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { | |
775 | /* Add the has_el3 state CPU property only if EL3 is allowed. This will | |
776 | * prevent "has_el3" from existing on CPUs which cannot support EL3. | |
777 | */ | |
778 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, | |
779 | &error_abort); | |
9e273ef2 PM |
780 | |
781 | #ifndef CONFIG_USER_ONLY | |
782 | object_property_add_link(obj, "secure-memory", | |
783 | TYPE_MEMORY_REGION, | |
784 | (Object **)&cpu->secure_memory, | |
785 | qdev_prop_allow_set_link_before_realize, | |
265b578c | 786 | OBJ_PROP_LINK_STRONG, |
9e273ef2 PM |
787 | &error_abort); |
788 | #endif | |
51942aee | 789 | } |
8f325f56 | 790 | |
c25bd18a PM |
791 | if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { |
792 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, | |
793 | &error_abort); | |
794 | } | |
795 | ||
929e754d WH |
796 | if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { |
797 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property, | |
798 | &error_abort); | |
799 | } | |
800 | ||
452a0955 | 801 | if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { |
8f325f56 PC |
802 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, |
803 | &error_abort); | |
3281af81 PC |
804 | if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { |
805 | qdev_property_add_static(DEVICE(obj), | |
806 | &arm_cpu_pmsav7_dregion_property, | |
807 | &error_abort); | |
808 | } | |
8f325f56 PC |
809 | } |
810 | ||
181962fd PM |
811 | if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) { |
812 | object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau, | |
813 | qdev_prop_allow_set_link_before_realize, | |
265b578c | 814 | OBJ_PROP_LINK_STRONG, |
181962fd | 815 | &error_abort); |
38e2a77c PM |
816 | qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property, |
817 | &error_abort); | |
181962fd PM |
818 | } |
819 | ||
3a062d57 JB |
820 | qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, |
821 | &error_abort); | |
07a5b0d2 PC |
822 | } |
823 | ||
4b6a83fb PM |
824 | static void arm_cpu_finalizefn(Object *obj) |
825 | { | |
826 | ARMCPU *cpu = ARM_CPU(obj); | |
08267487 AL |
827 | ARMELChangeHook *hook, *next; |
828 | ||
4b6a83fb | 829 | g_hash_table_destroy(cpu->cp_regs); |
08267487 | 830 | |
b5c53d1b AL |
831 | QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { |
832 | QLIST_REMOVE(hook, node); | |
833 | g_free(hook); | |
834 | } | |
08267487 AL |
835 | QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { |
836 | QLIST_REMOVE(hook, node); | |
837 | g_free(hook); | |
838 | } | |
777dc784 PM |
839 | } |
840 | ||
14969266 | 841 | static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
581be094 | 842 | { |
14a10fc3 | 843 | CPUState *cs = CPU(dev); |
14969266 AF |
844 | ARMCPU *cpu = ARM_CPU(dev); |
845 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); | |
581be094 | 846 | CPUARMState *env = &cpu->env; |
e97da98f | 847 | int pagebits; |
ce5b1bbf | 848 | Error *local_err = NULL; |
0f8d06f1 | 849 | bool no_aa32 = false; |
ce5b1bbf | 850 | |
c4487d76 PM |
851 | /* If we needed to query the host kernel for the CPU features |
852 | * then it's possible that might have failed in the initfn, but | |
853 | * this is the first point where we can report it. | |
854 | */ | |
855 | if (cpu->host_cpu_probe_failed) { | |
856 | if (!kvm_enabled()) { | |
857 | error_setg(errp, "The 'host' CPU type can only be used with KVM"); | |
858 | } else { | |
859 | error_setg(errp, "Failed to retrieve host CPU features"); | |
860 | } | |
861 | return; | |
862 | } | |
863 | ||
95f87565 PM |
864 | #ifndef CONFIG_USER_ONLY |
865 | /* The NVIC and M-profile CPU are two halves of a single piece of | |
866 | * hardware; trying to use one without the other is a command line | |
867 | * error and will result in segfaults if not caught here. | |
868 | */ | |
869 | if (arm_feature(env, ARM_FEATURE_M)) { | |
870 | if (!env->nvic) { | |
871 | error_setg(errp, "This board cannot be used with Cortex-M CPUs"); | |
872 | return; | |
873 | } | |
874 | } else { | |
875 | if (env->nvic) { | |
876 | error_setg(errp, "This board can only be used with Cortex-M CPUs"); | |
877 | return; | |
878 | } | |
879 | } | |
397cd31f PM |
880 | |
881 | cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, | |
882 | arm_gt_ptimer_cb, cpu); | |
883 | cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, | |
884 | arm_gt_vtimer_cb, cpu); | |
885 | cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, | |
886 | arm_gt_htimer_cb, cpu); | |
887 | cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, | |
888 | arm_gt_stimer_cb, cpu); | |
95f87565 PM |
889 | #endif |
890 | ||
ce5b1bbf LV |
891 | cpu_exec_realizefn(cs, &local_err); |
892 | if (local_err != NULL) { | |
893 | error_propagate(errp, local_err); | |
894 | return; | |
895 | } | |
14969266 | 896 | |
581be094 | 897 | /* Some features automatically imply others: */ |
81e69fb0 | 898 | if (arm_feature(env, ARM_FEATURE_V8)) { |
5256df88 RH |
899 | if (arm_feature(env, ARM_FEATURE_M)) { |
900 | set_feature(env, ARM_FEATURE_V7); | |
901 | } else { | |
902 | set_feature(env, ARM_FEATURE_V7VE); | |
903 | } | |
5110e683 | 904 | } |
0f8d06f1 RH |
905 | |
906 | /* | |
907 | * There exist AArch64 cpus without AArch32 support. When KVM | |
908 | * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. | |
909 | * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. | |
910 | */ | |
911 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
912 | no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); | |
913 | } | |
914 | ||
5110e683 AL |
915 | if (arm_feature(env, ARM_FEATURE_V7VE)) { |
916 | /* v7 Virtualization Extensions. In real hardware this implies | |
917 | * EL2 and also the presence of the Security Extensions. | |
918 | * For QEMU, for backwards-compatibility we implement some | |
919 | * CPUs or CPU configs which have no actual EL2 or EL3 but do | |
920 | * include the various other features that V7VE implies. | |
921 | * Presence of EL2 itself is ARM_FEATURE_EL2, and of the | |
922 | * Security Extensions is ARM_FEATURE_EL3. | |
923 | */ | |
0f8d06f1 | 924 | assert(no_aa32 || cpu_isar_feature(arm_div, cpu)); |
81e69fb0 | 925 | set_feature(env, ARM_FEATURE_LPAE); |
5110e683 | 926 | set_feature(env, ARM_FEATURE_V7); |
81e69fb0 | 927 | } |
581be094 PM |
928 | if (arm_feature(env, ARM_FEATURE_V7)) { |
929 | set_feature(env, ARM_FEATURE_VAPA); | |
930 | set_feature(env, ARM_FEATURE_THUMB2); | |
81bdde9d | 931 | set_feature(env, ARM_FEATURE_MPIDR); |
581be094 PM |
932 | if (!arm_feature(env, ARM_FEATURE_M)) { |
933 | set_feature(env, ARM_FEATURE_V6K); | |
934 | } else { | |
935 | set_feature(env, ARM_FEATURE_V6); | |
936 | } | |
91db4642 CLG |
937 | |
938 | /* Always define VBAR for V7 CPUs even if it doesn't exist in | |
939 | * non-EL3 configs. This is needed by some legacy boards. | |
940 | */ | |
941 | set_feature(env, ARM_FEATURE_VBAR); | |
581be094 PM |
942 | } |
943 | if (arm_feature(env, ARM_FEATURE_V6K)) { | |
944 | set_feature(env, ARM_FEATURE_V6); | |
945 | set_feature(env, ARM_FEATURE_MVFR); | |
946 | } | |
947 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
948 | set_feature(env, ARM_FEATURE_V5); | |
949 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
0f8d06f1 | 950 | assert(no_aa32 || cpu_isar_feature(jazelle, cpu)); |
581be094 PM |
951 | set_feature(env, ARM_FEATURE_AUXCR); |
952 | } | |
953 | } | |
954 | if (arm_feature(env, ARM_FEATURE_V5)) { | |
955 | set_feature(env, ARM_FEATURE_V4T); | |
956 | } | |
581be094 PM |
957 | if (arm_feature(env, ARM_FEATURE_VFP4)) { |
958 | set_feature(env, ARM_FEATURE_VFP3); | |
da5141fc | 959 | set_feature(env, ARM_FEATURE_VFP_FP16); |
581be094 PM |
960 | } |
961 | if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
962 | set_feature(env, ARM_FEATURE_VFP); | |
963 | } | |
de9b05b8 | 964 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
bdcc150d | 965 | set_feature(env, ARM_FEATURE_V7MP); |
de9b05b8 PM |
966 | set_feature(env, ARM_FEATURE_PXN); |
967 | } | |
f318cec6 PM |
968 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { |
969 | set_feature(env, ARM_FEATURE_CBAR); | |
970 | } | |
62b44f05 AR |
971 | if (arm_feature(env, ARM_FEATURE_THUMB2) && |
972 | !arm_feature(env, ARM_FEATURE_M)) { | |
973 | set_feature(env, ARM_FEATURE_THUMB_DSP); | |
974 | } | |
2ceb98c0 | 975 | |
e97da98f PM |
976 | if (arm_feature(env, ARM_FEATURE_V7) && |
977 | !arm_feature(env, ARM_FEATURE_M) && | |
452a0955 | 978 | !arm_feature(env, ARM_FEATURE_PMSA)) { |
e97da98f PM |
979 | /* v7VMSA drops support for the old ARMv5 tiny pages, so we |
980 | * can use 4K pages. | |
981 | */ | |
982 | pagebits = 12; | |
983 | } else { | |
984 | /* For CPUs which might have tiny 1K pages, or which have an | |
985 | * MPU and might have small region sizes, stick with 1K pages. | |
986 | */ | |
987 | pagebits = 10; | |
988 | } | |
989 | if (!set_preferred_target_page_bits(pagebits)) { | |
990 | /* This can only ever happen for hotplugging a CPU, or if | |
991 | * the board code incorrectly creates a CPU which it has | |
992 | * promised via minimum_page_size that it will not. | |
993 | */ | |
994 | error_setg(errp, "This CPU requires a smaller page size than the " | |
995 | "system is using"); | |
996 | return; | |
997 | } | |
998 | ||
ce5b1bbf LV |
999 | /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it. |
1000 | * We don't support setting cluster ID ([16..23]) (known as Aff2 | |
1001 | * in later ARM ARM versions), or any of the higher affinity level fields, | |
1002 | * so these bits always RAZ. | |
1003 | */ | |
1004 | if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { | |
46de5913 IM |
1005 | cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, |
1006 | ARM_DEFAULT_CPUS_PER_CLUSTER); | |
ce5b1bbf LV |
1007 | } |
1008 | ||
68e0a40a AP |
1009 | if (cpu->reset_hivecs) { |
1010 | cpu->reset_sctlr |= (1 << 13); | |
1011 | } | |
1012 | ||
3a062d57 JB |
1013 | if (cpu->cfgend) { |
1014 | if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { | |
1015 | cpu->reset_sctlr |= SCTLR_EE; | |
1016 | } else { | |
1017 | cpu->reset_sctlr |= SCTLR_B; | |
1018 | } | |
1019 | } | |
1020 | ||
51942aee GB |
1021 | if (!cpu->has_el3) { |
1022 | /* If the has_el3 CPU property is disabled then we need to disable the | |
1023 | * feature. | |
1024 | */ | |
1025 | unset_feature(env, ARM_FEATURE_EL3); | |
1026 | ||
1027 | /* Disable the security extension feature bits in the processor feature | |
3d5c84ff | 1028 | * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. |
51942aee GB |
1029 | */ |
1030 | cpu->id_pfr1 &= ~0xf0; | |
47576b94 | 1031 | cpu->isar.id_aa64pfr0 &= ~0xf000; |
51942aee GB |
1032 | } |
1033 | ||
c25bd18a PM |
1034 | if (!cpu->has_el2) { |
1035 | unset_feature(env, ARM_FEATURE_EL2); | |
1036 | } | |
1037 | ||
d6f02ce3 | 1038 | if (!cpu->has_pmu) { |
929e754d | 1039 | unset_feature(env, ARM_FEATURE_PMU); |
2b3ffa92 | 1040 | cpu->id_aa64dfr0 &= ~0xf00; |
033614c4 AL |
1041 | } else if (!kvm_enabled()) { |
1042 | arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); | |
1043 | arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); | |
929e754d WH |
1044 | } |
1045 | ||
3c2f7bb3 PM |
1046 | if (!arm_feature(env, ARM_FEATURE_EL2)) { |
1047 | /* Disable the hypervisor feature bits in the processor feature | |
1048 | * registers if we don't have EL2. These are id_pfr1[15:12] and | |
1049 | * id_aa64pfr0_el1[11:8]. | |
1050 | */ | |
47576b94 | 1051 | cpu->isar.id_aa64pfr0 &= ~0xf00; |
3c2f7bb3 PM |
1052 | cpu->id_pfr1 &= ~0xf000; |
1053 | } | |
1054 | ||
f50cd314 PM |
1055 | /* MPU can be configured out of a PMSA CPU either by setting has-mpu |
1056 | * to false or by setting pmsav7-dregion to 0. | |
1057 | */ | |
8f325f56 | 1058 | if (!cpu->has_mpu) { |
f50cd314 PM |
1059 | cpu->pmsav7_dregion = 0; |
1060 | } | |
1061 | if (cpu->pmsav7_dregion == 0) { | |
1062 | cpu->has_mpu = false; | |
8f325f56 PC |
1063 | } |
1064 | ||
452a0955 | 1065 | if (arm_feature(env, ARM_FEATURE_PMSA) && |
3281af81 PC |
1066 | arm_feature(env, ARM_FEATURE_V7)) { |
1067 | uint32_t nr = cpu->pmsav7_dregion; | |
1068 | ||
1069 | if (nr > 0xff) { | |
9af9e0fe | 1070 | error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr); |
3281af81 PC |
1071 | return; |
1072 | } | |
6cb0b013 PC |
1073 | |
1074 | if (nr) { | |
0e1a46bb PM |
1075 | if (arm_feature(env, ARM_FEATURE_V8)) { |
1076 | /* PMSAv8 */ | |
62c58ee0 PM |
1077 | env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr); |
1078 | env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr); | |
1079 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
1080 | env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr); | |
1081 | env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr); | |
1082 | } | |
0e1a46bb PM |
1083 | } else { |
1084 | env->pmsav7.drbar = g_new0(uint32_t, nr); | |
1085 | env->pmsav7.drsr = g_new0(uint32_t, nr); | |
1086 | env->pmsav7.dracr = g_new0(uint32_t, nr); | |
1087 | } | |
6cb0b013 | 1088 | } |
3281af81 PC |
1089 | } |
1090 | ||
9901c576 PM |
1091 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
1092 | uint32_t nr = cpu->sau_sregion; | |
1093 | ||
1094 | if (nr > 0xff) { | |
1095 | error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr); | |
1096 | return; | |
1097 | } | |
1098 | ||
1099 | if (nr) { | |
1100 | env->sau.rbar = g_new0(uint32_t, nr); | |
1101 | env->sau.rlar = g_new0(uint32_t, nr); | |
1102 | } | |
1103 | } | |
1104 | ||
91db4642 CLG |
1105 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
1106 | set_feature(env, ARM_FEATURE_VBAR); | |
1107 | } | |
1108 | ||
2ceb98c0 | 1109 | register_cp_regs_for_features(cpu); |
14969266 AF |
1110 | arm_cpu_register_gdb_regs_for_features(cpu); |
1111 | ||
721fae12 PM |
1112 | init_cpreg_list(cpu); |
1113 | ||
9e273ef2 | 1114 | #ifndef CONFIG_USER_ONLY |
1d2091bc | 1115 | if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
1d2091bc PM |
1116 | cs->num_ases = 2; |
1117 | ||
9e273ef2 PM |
1118 | if (!cpu->secure_memory) { |
1119 | cpu->secure_memory = cs->memory; | |
1120 | } | |
80ceb07a PX |
1121 | cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory", |
1122 | cpu->secure_memory); | |
1d2091bc PM |
1123 | } else { |
1124 | cs->num_ases = 1; | |
9e273ef2 | 1125 | } |
80ceb07a | 1126 | cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory); |
f9a69711 AF |
1127 | |
1128 | /* No core_count specified, default to smp_cpus. */ | |
1129 | if (cpu->core_count == -1) { | |
1130 | cpu->core_count = smp_cpus; | |
1131 | } | |
9e273ef2 PM |
1132 | #endif |
1133 | ||
14a10fc3 | 1134 | qemu_init_vcpu(cs); |
00d0f7cb | 1135 | cpu_reset(cs); |
14969266 AF |
1136 | |
1137 | acc->parent_realize(dev, errp); | |
581be094 PM |
1138 | } |
1139 | ||
5900d6b2 AF |
1140 | static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) |
1141 | { | |
1142 | ObjectClass *oc; | |
51492fd1 | 1143 | char *typename; |
fb8d6c24 | 1144 | char **cpuname; |
a0032cc5 | 1145 | const char *cpunamestr; |
5900d6b2 | 1146 | |
fb8d6c24 | 1147 | cpuname = g_strsplit(cpu_model, ",", 1); |
a0032cc5 PM |
1148 | cpunamestr = cpuname[0]; |
1149 | #ifdef CONFIG_USER_ONLY | |
1150 | /* For backwards compatibility usermode emulation allows "-cpu any", | |
1151 | * which has the same semantics as "-cpu max". | |
1152 | */ | |
1153 | if (!strcmp(cpunamestr, "any")) { | |
1154 | cpunamestr = "max"; | |
1155 | } | |
1156 | #endif | |
1157 | typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); | |
51492fd1 | 1158 | oc = object_class_by_name(typename); |
fb8d6c24 | 1159 | g_strfreev(cpuname); |
51492fd1 | 1160 | g_free(typename); |
245fb54d AF |
1161 | if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || |
1162 | object_class_is_abstract(oc)) { | |
5900d6b2 AF |
1163 | return NULL; |
1164 | } | |
1165 | return oc; | |
1166 | } | |
1167 | ||
15ee776b PM |
1168 | /* CPU models. These are not needed for the AArch64 linux-user build. */ |
1169 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | |
1170 | ||
777dc784 PM |
1171 | static void arm926_initfn(Object *obj) |
1172 | { | |
1173 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1174 | |
1175 | cpu->dtb_compatible = "arm,arm926"; | |
581be094 PM |
1176 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1177 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
1178 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
1179 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 1180 | cpu->midr = 0x41069265; |
325b3cef | 1181 | cpu->reset_fpsid = 0x41011090; |
64e1671f | 1182 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 1183 | cpu->reset_sctlr = 0x00090078; |
09cbd501 RH |
1184 | |
1185 | /* | |
1186 | * ARMv5 does not have the ID_ISAR registers, but we can still | |
1187 | * set the field to indicate Jazelle support within QEMU. | |
1188 | */ | |
1189 | cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); | |
777dc784 PM |
1190 | } |
1191 | ||
1192 | static void arm946_initfn(Object *obj) | |
1193 | { | |
1194 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1195 | |
1196 | cpu->dtb_compatible = "arm,arm946"; | |
581be094 | 1197 | set_feature(&cpu->env, ARM_FEATURE_V5); |
452a0955 | 1198 | set_feature(&cpu->env, ARM_FEATURE_PMSA); |
c4804214 | 1199 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1200 | cpu->midr = 0x41059461; |
64e1671f | 1201 | cpu->ctr = 0x0f004006; |
0ca7e01c | 1202 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1203 | } |
1204 | ||
1205 | static void arm1026_initfn(Object *obj) | |
1206 | { | |
1207 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1208 | |
1209 | cpu->dtb_compatible = "arm,arm1026"; | |
581be094 PM |
1210 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1211 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
1212 | set_feature(&cpu->env, ARM_FEATURE_AUXCR); | |
c4804214 PM |
1213 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
1214 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
b2d06f96 | 1215 | cpu->midr = 0x4106a262; |
325b3cef | 1216 | cpu->reset_fpsid = 0x410110a0; |
64e1671f | 1217 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 1218 | cpu->reset_sctlr = 0x00090078; |
2771db27 | 1219 | cpu->reset_auxcr = 1; |
09cbd501 RH |
1220 | |
1221 | /* | |
1222 | * ARMv5 does not have the ID_ISAR registers, but we can still | |
1223 | * set the field to indicate Jazelle support within QEMU. | |
1224 | */ | |
1225 | cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); | |
1226 | ||
06d76f31 PM |
1227 | { |
1228 | /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ | |
1229 | ARMCPRegInfo ifar = { | |
1230 | .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1231 | .access = PL1_RW, | |
b848ce2b | 1232 | .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), |
06d76f31 PM |
1233 | .resetvalue = 0 |
1234 | }; | |
1235 | define_one_arm_cp_reg(cpu, &ifar); | |
1236 | } | |
777dc784 PM |
1237 | } |
1238 | ||
1239 | static void arm1136_r2_initfn(Object *obj) | |
1240 | { | |
1241 | ARMCPU *cpu = ARM_CPU(obj); | |
2e4d7e3e PM |
1242 | /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an |
1243 | * older core than plain "arm1136". In particular this does not | |
1244 | * have the v6K features. | |
1245 | * These ID register values are correct for 1136 but may be wrong | |
1246 | * for 1136_r2 (in particular r0p2 does not actually implement most | |
1247 | * of the ID registers). | |
1248 | */ | |
54d3e3f5 PM |
1249 | |
1250 | cpu->dtb_compatible = "arm,arm1136"; | |
581be094 PM |
1251 | set_feature(&cpu->env, ARM_FEATURE_V6); |
1252 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
1253 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
1254 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
1255 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 1256 | cpu->midr = 0x4107b362; |
325b3cef | 1257 | cpu->reset_fpsid = 0x410120b4; |
47576b94 RH |
1258 | cpu->isar.mvfr0 = 0x11111111; |
1259 | cpu->isar.mvfr1 = 0x00000000; | |
64e1671f | 1260 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 1261 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
1262 | cpu->id_pfr0 = 0x111; |
1263 | cpu->id_pfr1 = 0x1; | |
1264 | cpu->id_dfr0 = 0x2; | |
1265 | cpu->id_afr0 = 0x3; | |
1266 | cpu->id_mmfr0 = 0x01130003; | |
1267 | cpu->id_mmfr1 = 0x10030302; | |
1268 | cpu->id_mmfr2 = 0x01222110; | |
47576b94 RH |
1269 | cpu->isar.id_isar0 = 0x00140011; |
1270 | cpu->isar.id_isar1 = 0x12002111; | |
1271 | cpu->isar.id_isar2 = 0x11231111; | |
1272 | cpu->isar.id_isar3 = 0x01102131; | |
1273 | cpu->isar.id_isar4 = 0x141; | |
2771db27 | 1274 | cpu->reset_auxcr = 7; |
777dc784 PM |
1275 | } |
1276 | ||
1277 | static void arm1136_initfn(Object *obj) | |
1278 | { | |
1279 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1280 | |
1281 | cpu->dtb_compatible = "arm,arm1136"; | |
581be094 PM |
1282 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
1283 | set_feature(&cpu->env, ARM_FEATURE_V6); | |
1284 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
c4804214 PM |
1285 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
1286 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
1287 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
b2d06f96 | 1288 | cpu->midr = 0x4117b363; |
325b3cef | 1289 | cpu->reset_fpsid = 0x410120b4; |
47576b94 RH |
1290 | cpu->isar.mvfr0 = 0x11111111; |
1291 | cpu->isar.mvfr1 = 0x00000000; | |
64e1671f | 1292 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 1293 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
1294 | cpu->id_pfr0 = 0x111; |
1295 | cpu->id_pfr1 = 0x1; | |
1296 | cpu->id_dfr0 = 0x2; | |
1297 | cpu->id_afr0 = 0x3; | |
1298 | cpu->id_mmfr0 = 0x01130003; | |
1299 | cpu->id_mmfr1 = 0x10030302; | |
1300 | cpu->id_mmfr2 = 0x01222110; | |
47576b94 RH |
1301 | cpu->isar.id_isar0 = 0x00140011; |
1302 | cpu->isar.id_isar1 = 0x12002111; | |
1303 | cpu->isar.id_isar2 = 0x11231111; | |
1304 | cpu->isar.id_isar3 = 0x01102131; | |
1305 | cpu->isar.id_isar4 = 0x141; | |
2771db27 | 1306 | cpu->reset_auxcr = 7; |
777dc784 PM |
1307 | } |
1308 | ||
1309 | static void arm1176_initfn(Object *obj) | |
1310 | { | |
1311 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1312 | |
1313 | cpu->dtb_compatible = "arm,arm1176"; | |
581be094 PM |
1314 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
1315 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
1316 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
c4804214 PM |
1317 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
1318 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
1319 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
c0ccb02d | 1320 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
b2d06f96 | 1321 | cpu->midr = 0x410fb767; |
325b3cef | 1322 | cpu->reset_fpsid = 0x410120b5; |
47576b94 RH |
1323 | cpu->isar.mvfr0 = 0x11111111; |
1324 | cpu->isar.mvfr1 = 0x00000000; | |
64e1671f | 1325 | cpu->ctr = 0x1dd20d2; |
0ca7e01c | 1326 | cpu->reset_sctlr = 0x00050078; |
2e4d7e3e PM |
1327 | cpu->id_pfr0 = 0x111; |
1328 | cpu->id_pfr1 = 0x11; | |
1329 | cpu->id_dfr0 = 0x33; | |
1330 | cpu->id_afr0 = 0; | |
1331 | cpu->id_mmfr0 = 0x01130003; | |
1332 | cpu->id_mmfr1 = 0x10030302; | |
1333 | cpu->id_mmfr2 = 0x01222100; | |
47576b94 RH |
1334 | cpu->isar.id_isar0 = 0x0140011; |
1335 | cpu->isar.id_isar1 = 0x12002111; | |
1336 | cpu->isar.id_isar2 = 0x11231121; | |
1337 | cpu->isar.id_isar3 = 0x01102131; | |
1338 | cpu->isar.id_isar4 = 0x01141; | |
2771db27 | 1339 | cpu->reset_auxcr = 7; |
777dc784 PM |
1340 | } |
1341 | ||
1342 | static void arm11mpcore_initfn(Object *obj) | |
1343 | { | |
1344 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1345 | |
1346 | cpu->dtb_compatible = "arm,arm11mpcore"; | |
581be094 PM |
1347 | set_feature(&cpu->env, ARM_FEATURE_V6K); |
1348 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
1349 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
81bdde9d | 1350 | set_feature(&cpu->env, ARM_FEATURE_MPIDR); |
c4804214 | 1351 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1352 | cpu->midr = 0x410fb022; |
325b3cef | 1353 | cpu->reset_fpsid = 0x410120b4; |
47576b94 RH |
1354 | cpu->isar.mvfr0 = 0x11111111; |
1355 | cpu->isar.mvfr1 = 0x00000000; | |
200bf596 | 1356 | cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ |
2e4d7e3e PM |
1357 | cpu->id_pfr0 = 0x111; |
1358 | cpu->id_pfr1 = 0x1; | |
1359 | cpu->id_dfr0 = 0; | |
1360 | cpu->id_afr0 = 0x2; | |
1361 | cpu->id_mmfr0 = 0x01100103; | |
1362 | cpu->id_mmfr1 = 0x10020302; | |
1363 | cpu->id_mmfr2 = 0x01222000; | |
47576b94 RH |
1364 | cpu->isar.id_isar0 = 0x00100011; |
1365 | cpu->isar.id_isar1 = 0x12002111; | |
1366 | cpu->isar.id_isar2 = 0x11221011; | |
1367 | cpu->isar.id_isar3 = 0x01102131; | |
1368 | cpu->isar.id_isar4 = 0x141; | |
2771db27 | 1369 | cpu->reset_auxcr = 1; |
777dc784 PM |
1370 | } |
1371 | ||
191776b9 SH |
1372 | static void cortex_m0_initfn(Object *obj) |
1373 | { | |
1374 | ARMCPU *cpu = ARM_CPU(obj); | |
1375 | set_feature(&cpu->env, ARM_FEATURE_V6); | |
1376 | set_feature(&cpu->env, ARM_FEATURE_M); | |
1377 | ||
1378 | cpu->midr = 0x410cc200; | |
1379 | } | |
1380 | ||
777dc784 PM |
1381 | static void cortex_m3_initfn(Object *obj) |
1382 | { | |
1383 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
1384 | set_feature(&cpu->env, ARM_FEATURE_V7); |
1385 | set_feature(&cpu->env, ARM_FEATURE_M); | |
cc2ae7c9 | 1386 | set_feature(&cpu->env, ARM_FEATURE_M_MAIN); |
b2d06f96 | 1387 | cpu->midr = 0x410fc231; |
8d92e26b | 1388 | cpu->pmsav7_dregion = 8; |
5a53e2c1 PM |
1389 | cpu->id_pfr0 = 0x00000030; |
1390 | cpu->id_pfr1 = 0x00000200; | |
1391 | cpu->id_dfr0 = 0x00100000; | |
1392 | cpu->id_afr0 = 0x00000000; | |
1393 | cpu->id_mmfr0 = 0x00000030; | |
1394 | cpu->id_mmfr1 = 0x00000000; | |
1395 | cpu->id_mmfr2 = 0x00000000; | |
1396 | cpu->id_mmfr3 = 0x00000000; | |
47576b94 RH |
1397 | cpu->isar.id_isar0 = 0x01141110; |
1398 | cpu->isar.id_isar1 = 0x02111000; | |
1399 | cpu->isar.id_isar2 = 0x21112231; | |
1400 | cpu->isar.id_isar3 = 0x01111110; | |
1401 | cpu->isar.id_isar4 = 0x01310102; | |
1402 | cpu->isar.id_isar5 = 0x00000000; | |
1403 | cpu->isar.id_isar6 = 0x00000000; | |
777dc784 PM |
1404 | } |
1405 | ||
ba890a9b AR |
1406 | static void cortex_m4_initfn(Object *obj) |
1407 | { | |
1408 | ARMCPU *cpu = ARM_CPU(obj); | |
1409 | ||
1410 | set_feature(&cpu->env, ARM_FEATURE_V7); | |
1411 | set_feature(&cpu->env, ARM_FEATURE_M); | |
cc2ae7c9 | 1412 | set_feature(&cpu->env, ARM_FEATURE_M_MAIN); |
ba890a9b AR |
1413 | set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); |
1414 | cpu->midr = 0x410fc240; /* r0p0 */ | |
8d92e26b | 1415 | cpu->pmsav7_dregion = 8; |
5a53e2c1 PM |
1416 | cpu->id_pfr0 = 0x00000030; |
1417 | cpu->id_pfr1 = 0x00000200; | |
1418 | cpu->id_dfr0 = 0x00100000; | |
1419 | cpu->id_afr0 = 0x00000000; | |
1420 | cpu->id_mmfr0 = 0x00000030; | |
1421 | cpu->id_mmfr1 = 0x00000000; | |
1422 | cpu->id_mmfr2 = 0x00000000; | |
1423 | cpu->id_mmfr3 = 0x00000000; | |
47576b94 RH |
1424 | cpu->isar.id_isar0 = 0x01141110; |
1425 | cpu->isar.id_isar1 = 0x02111000; | |
1426 | cpu->isar.id_isar2 = 0x21112231; | |
1427 | cpu->isar.id_isar3 = 0x01111110; | |
1428 | cpu->isar.id_isar4 = 0x01310102; | |
1429 | cpu->isar.id_isar5 = 0x00000000; | |
1430 | cpu->isar.id_isar6 = 0x00000000; | |
ba890a9b | 1431 | } |
9901c576 | 1432 | |
c7b26382 PM |
1433 | static void cortex_m33_initfn(Object *obj) |
1434 | { | |
1435 | ARMCPU *cpu = ARM_CPU(obj); | |
1436 | ||
1437 | set_feature(&cpu->env, ARM_FEATURE_V8); | |
1438 | set_feature(&cpu->env, ARM_FEATURE_M); | |
cc2ae7c9 | 1439 | set_feature(&cpu->env, ARM_FEATURE_M_MAIN); |
c7b26382 PM |
1440 | set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); |
1441 | set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | |
1442 | cpu->midr = 0x410fd213; /* r0p3 */ | |
1443 | cpu->pmsav7_dregion = 16; | |
1444 | cpu->sau_sregion = 8; | |
1445 | cpu->id_pfr0 = 0x00000030; | |
1446 | cpu->id_pfr1 = 0x00000210; | |
1447 | cpu->id_dfr0 = 0x00200000; | |
1448 | cpu->id_afr0 = 0x00000000; | |
1449 | cpu->id_mmfr0 = 0x00101F40; | |
1450 | cpu->id_mmfr1 = 0x00000000; | |
1451 | cpu->id_mmfr2 = 0x01000000; | |
1452 | cpu->id_mmfr3 = 0x00000000; | |
47576b94 RH |
1453 | cpu->isar.id_isar0 = 0x01101110; |
1454 | cpu->isar.id_isar1 = 0x02212000; | |
1455 | cpu->isar.id_isar2 = 0x20232232; | |
1456 | cpu->isar.id_isar3 = 0x01111131; | |
1457 | cpu->isar.id_isar4 = 0x01310132; | |
1458 | cpu->isar.id_isar5 = 0x00000000; | |
1459 | cpu->isar.id_isar6 = 0x00000000; | |
c7b26382 PM |
1460 | cpu->clidr = 0x00000000; |
1461 | cpu->ctr = 0x8000c000; | |
1462 | } | |
1463 | ||
e6f010cc AF |
1464 | static void arm_v7m_class_init(ObjectClass *oc, void *data) |
1465 | { | |
51e5ef45 | 1466 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); |
e6f010cc AF |
1467 | CPUClass *cc = CPU_CLASS(oc); |
1468 | ||
51e5ef45 | 1469 | acc->info = data; |
b5c633c5 | 1470 | #ifndef CONFIG_USER_ONLY |
e6f010cc AF |
1471 | cc->do_interrupt = arm_v7m_cpu_do_interrupt; |
1472 | #endif | |
b5c633c5 PM |
1473 | |
1474 | cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt; | |
e6f010cc AF |
1475 | } |
1476 | ||
d6a6b13e PC |
1477 | static const ARMCPRegInfo cortexr5_cp_reginfo[] = { |
1478 | /* Dummy the TCM region regs for the moment */ | |
1479 | { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
1480 | .access = PL1_RW, .type = ARM_CP_CONST }, | |
1481 | { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
1482 | .access = PL1_RW, .type = ARM_CP_CONST }, | |
95e9a242 LM |
1483 | { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, |
1484 | .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, | |
d6a6b13e PC |
1485 | REGINFO_SENTINEL |
1486 | }; | |
1487 | ||
1488 | static void cortex_r5_initfn(Object *obj) | |
1489 | { | |
1490 | ARMCPU *cpu = ARM_CPU(obj); | |
1491 | ||
1492 | set_feature(&cpu->env, ARM_FEATURE_V7); | |
d6a6b13e | 1493 | set_feature(&cpu->env, ARM_FEATURE_V7MP); |
452a0955 | 1494 | set_feature(&cpu->env, ARM_FEATURE_PMSA); |
d6a6b13e PC |
1495 | cpu->midr = 0x411fc153; /* r1p3 */ |
1496 | cpu->id_pfr0 = 0x0131; | |
1497 | cpu->id_pfr1 = 0x001; | |
1498 | cpu->id_dfr0 = 0x010400; | |
1499 | cpu->id_afr0 = 0x0; | |
1500 | cpu->id_mmfr0 = 0x0210030; | |
1501 | cpu->id_mmfr1 = 0x00000000; | |
1502 | cpu->id_mmfr2 = 0x01200000; | |
1503 | cpu->id_mmfr3 = 0x0211; | |
47576b94 RH |
1504 | cpu->isar.id_isar0 = 0x02101111; |
1505 | cpu->isar.id_isar1 = 0x13112111; | |
1506 | cpu->isar.id_isar2 = 0x21232141; | |
1507 | cpu->isar.id_isar3 = 0x01112131; | |
1508 | cpu->isar.id_isar4 = 0x0010142; | |
1509 | cpu->isar.id_isar5 = 0x0; | |
1510 | cpu->isar.id_isar6 = 0x0; | |
d6a6b13e | 1511 | cpu->mp_is_up = true; |
8d92e26b | 1512 | cpu->pmsav7_dregion = 16; |
d6a6b13e PC |
1513 | define_arm_cp_regs(cpu, cortexr5_cp_reginfo); |
1514 | } | |
1515 | ||
ebac5458 EI |
1516 | static void cortex_r5f_initfn(Object *obj) |
1517 | { | |
1518 | ARMCPU *cpu = ARM_CPU(obj); | |
1519 | ||
1520 | cortex_r5_initfn(obj); | |
1521 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
1522 | } | |
1523 | ||
34f90529 PM |
1524 | static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |
1525 | { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, | |
1526 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1527 | { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
1528 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1529 | REGINFO_SENTINEL | |
1530 | }; | |
1531 | ||
777dc784 PM |
1532 | static void cortex_a8_initfn(Object *obj) |
1533 | { | |
1534 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1535 | |
1536 | cpu->dtb_compatible = "arm,cortex-a8"; | |
581be094 PM |
1537 | set_feature(&cpu->env, ARM_FEATURE_V7); |
1538 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
1539 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
1540 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c4804214 | 1541 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
c0ccb02d | 1542 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
b2d06f96 | 1543 | cpu->midr = 0x410fc080; |
325b3cef | 1544 | cpu->reset_fpsid = 0x410330c0; |
47576b94 RH |
1545 | cpu->isar.mvfr0 = 0x11110222; |
1546 | cpu->isar.mvfr1 = 0x00011111; | |
64e1671f | 1547 | cpu->ctr = 0x82048004; |
0ca7e01c | 1548 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
1549 | cpu->id_pfr0 = 0x1031; |
1550 | cpu->id_pfr1 = 0x11; | |
1551 | cpu->id_dfr0 = 0x400; | |
1552 | cpu->id_afr0 = 0; | |
1553 | cpu->id_mmfr0 = 0x31100003; | |
1554 | cpu->id_mmfr1 = 0x20000000; | |
1555 | cpu->id_mmfr2 = 0x01202000; | |
1556 | cpu->id_mmfr3 = 0x11; | |
47576b94 RH |
1557 | cpu->isar.id_isar0 = 0x00101111; |
1558 | cpu->isar.id_isar1 = 0x12112111; | |
1559 | cpu->isar.id_isar2 = 0x21232031; | |
1560 | cpu->isar.id_isar3 = 0x11112131; | |
1561 | cpu->isar.id_isar4 = 0x00111142; | |
48eb3ae6 | 1562 | cpu->dbgdidr = 0x15141000; |
85df3786 PM |
1563 | cpu->clidr = (1 << 27) | (2 << 24) | 3; |
1564 | cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ | |
1565 | cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ | |
1566 | cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ | |
2771db27 | 1567 | cpu->reset_auxcr = 2; |
34f90529 | 1568 | define_arm_cp_regs(cpu, cortexa8_cp_reginfo); |
777dc784 PM |
1569 | } |
1570 | ||
1047b9d7 PM |
1571 | static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
1572 | /* power_control should be set to maximum latency. Again, | |
1573 | * default to 0 and set by private hook | |
1574 | */ | |
1575 | { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, | |
1576 | .access = PL1_RW, .resetvalue = 0, | |
1577 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, | |
1578 | { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1579 | .access = PL1_RW, .resetvalue = 0, | |
1580 | .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, | |
1581 | { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, | |
1582 | .access = PL1_RW, .resetvalue = 0, | |
1583 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, | |
1584 | { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
1585 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1586 | /* TLB lockdown control */ | |
1587 | { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, | |
1588 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
1589 | { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, | |
1590 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
1591 | { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, | |
1592 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1593 | { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, | |
1594 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1595 | { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, | |
1596 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
1597 | REGINFO_SENTINEL | |
1598 | }; | |
1599 | ||
777dc784 PM |
1600 | static void cortex_a9_initfn(Object *obj) |
1601 | { | |
1602 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1603 | |
1604 | cpu->dtb_compatible = "arm,cortex-a9"; | |
581be094 PM |
1605 | set_feature(&cpu->env, ARM_FEATURE_V7); |
1606 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
1607 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
1608 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
1609 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
c0ccb02d | 1610 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
581be094 PM |
1611 | /* Note that A9 supports the MP extensions even for |
1612 | * A9UP and single-core A9MP (which are both different | |
1613 | * and valid configurations; we don't model A9UP). | |
1614 | */ | |
1615 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
d8ba780b | 1616 | set_feature(&cpu->env, ARM_FEATURE_CBAR); |
b2d06f96 | 1617 | cpu->midr = 0x410fc090; |
325b3cef | 1618 | cpu->reset_fpsid = 0x41033090; |
47576b94 RH |
1619 | cpu->isar.mvfr0 = 0x11110222; |
1620 | cpu->isar.mvfr1 = 0x01111111; | |
64e1671f | 1621 | cpu->ctr = 0x80038003; |
0ca7e01c | 1622 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
1623 | cpu->id_pfr0 = 0x1031; |
1624 | cpu->id_pfr1 = 0x11; | |
1625 | cpu->id_dfr0 = 0x000; | |
1626 | cpu->id_afr0 = 0; | |
1627 | cpu->id_mmfr0 = 0x00100103; | |
1628 | cpu->id_mmfr1 = 0x20000000; | |
1629 | cpu->id_mmfr2 = 0x01230000; | |
1630 | cpu->id_mmfr3 = 0x00002111; | |
47576b94 RH |
1631 | cpu->isar.id_isar0 = 0x00101111; |
1632 | cpu->isar.id_isar1 = 0x13112111; | |
1633 | cpu->isar.id_isar2 = 0x21232041; | |
1634 | cpu->isar.id_isar3 = 0x11112131; | |
1635 | cpu->isar.id_isar4 = 0x00111142; | |
48eb3ae6 | 1636 | cpu->dbgdidr = 0x35141000; |
85df3786 | 1637 | cpu->clidr = (1 << 27) | (1 << 24) | 3; |
f7838b52 PC |
1638 | cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ |
1639 | cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ | |
d8ba780b | 1640 | define_arm_cp_regs(cpu, cortexa9_cp_reginfo); |
777dc784 PM |
1641 | } |
1642 | ||
34f90529 | 1643 | #ifndef CONFIG_USER_ONLY |
c4241c7d | 1644 | static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
34f90529 PM |
1645 | { |
1646 | /* Linux wants the number of processors from here. | |
1647 | * Might as well set the interrupt-controller bit too. | |
1648 | */ | |
c4241c7d | 1649 | return ((smp_cpus - 1) << 24) | (1 << 23); |
34f90529 PM |
1650 | } |
1651 | #endif | |
1652 | ||
1653 | static const ARMCPRegInfo cortexa15_cp_reginfo[] = { | |
1654 | #ifndef CONFIG_USER_ONLY | |
1655 | { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
1656 | .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, | |
1657 | .writefn = arm_cp_write_ignore, }, | |
1658 | #endif | |
1659 | { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, | |
1660 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1661 | REGINFO_SENTINEL | |
1662 | }; | |
1663 | ||
dcf578ed AY |
1664 | static void cortex_a7_initfn(Object *obj) |
1665 | { | |
1666 | ARMCPU *cpu = ARM_CPU(obj); | |
1667 | ||
1668 | cpu->dtb_compatible = "arm,cortex-a7"; | |
5110e683 | 1669 | set_feature(&cpu->env, ARM_FEATURE_V7VE); |
dcf578ed AY |
1670 | set_feature(&cpu->env, ARM_FEATURE_VFP4); |
1671 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
1672 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
dcf578ed AY |
1673 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
1674 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | |
1675 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | |
436c0cbb | 1676 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
dcf578ed AY |
1677 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
1678 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; | |
1679 | cpu->midr = 0x410fc075; | |
1680 | cpu->reset_fpsid = 0x41023075; | |
47576b94 RH |
1681 | cpu->isar.mvfr0 = 0x10110222; |
1682 | cpu->isar.mvfr1 = 0x11111111; | |
dcf578ed AY |
1683 | cpu->ctr = 0x84448003; |
1684 | cpu->reset_sctlr = 0x00c50078; | |
1685 | cpu->id_pfr0 = 0x00001131; | |
1686 | cpu->id_pfr1 = 0x00011011; | |
1687 | cpu->id_dfr0 = 0x02010555; | |
1688 | cpu->pmceid0 = 0x00000000; | |
1689 | cpu->pmceid1 = 0x00000000; | |
1690 | cpu->id_afr0 = 0x00000000; | |
1691 | cpu->id_mmfr0 = 0x10101105; | |
1692 | cpu->id_mmfr1 = 0x40000000; | |
1693 | cpu->id_mmfr2 = 0x01240000; | |
1694 | cpu->id_mmfr3 = 0x02102211; | |
37bdda89 RH |
1695 | /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but |
1696 | * table 4-41 gives 0x02101110, which includes the arm div insns. | |
1697 | */ | |
47576b94 RH |
1698 | cpu->isar.id_isar0 = 0x02101110; |
1699 | cpu->isar.id_isar1 = 0x13112111; | |
1700 | cpu->isar.id_isar2 = 0x21232041; | |
1701 | cpu->isar.id_isar3 = 0x11112131; | |
1702 | cpu->isar.id_isar4 = 0x10011142; | |
dcf578ed AY |
1703 | cpu->dbgdidr = 0x3515f005; |
1704 | cpu->clidr = 0x0a200023; | |
1705 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
1706 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
1707 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
1708 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ | |
1709 | } | |
1710 | ||
777dc784 PM |
1711 | static void cortex_a15_initfn(Object *obj) |
1712 | { | |
1713 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1714 | |
1715 | cpu->dtb_compatible = "arm,cortex-a15"; | |
5110e683 | 1716 | set_feature(&cpu->env, ARM_FEATURE_V7VE); |
581be094 | 1717 | set_feature(&cpu->env, ARM_FEATURE_VFP4); |
581be094 PM |
1718 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
1719 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
581be094 | 1720 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
c4804214 | 1721 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
c29f9a0a | 1722 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
436c0cbb | 1723 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
c0ccb02d | 1724 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
3541addc | 1725 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; |
b2d06f96 | 1726 | cpu->midr = 0x412fc0f1; |
325b3cef | 1727 | cpu->reset_fpsid = 0x410430f0; |
47576b94 RH |
1728 | cpu->isar.mvfr0 = 0x10110222; |
1729 | cpu->isar.mvfr1 = 0x11111111; | |
64e1671f | 1730 | cpu->ctr = 0x8444c004; |
0ca7e01c | 1731 | cpu->reset_sctlr = 0x00c50078; |
2e4d7e3e PM |
1732 | cpu->id_pfr0 = 0x00001131; |
1733 | cpu->id_pfr1 = 0x00011011; | |
1734 | cpu->id_dfr0 = 0x02010555; | |
4054bfa9 AF |
1735 | cpu->pmceid0 = 0x0000000; |
1736 | cpu->pmceid1 = 0x00000000; | |
2e4d7e3e PM |
1737 | cpu->id_afr0 = 0x00000000; |
1738 | cpu->id_mmfr0 = 0x10201105; | |
1739 | cpu->id_mmfr1 = 0x20000000; | |
1740 | cpu->id_mmfr2 = 0x01240000; | |
1741 | cpu->id_mmfr3 = 0x02102211; | |
47576b94 RH |
1742 | cpu->isar.id_isar0 = 0x02101110; |
1743 | cpu->isar.id_isar1 = 0x13112111; | |
1744 | cpu->isar.id_isar2 = 0x21232041; | |
1745 | cpu->isar.id_isar3 = 0x11112131; | |
1746 | cpu->isar.id_isar4 = 0x10011142; | |
48eb3ae6 | 1747 | cpu->dbgdidr = 0x3515f021; |
85df3786 PM |
1748 | cpu->clidr = 0x0a200023; |
1749 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
1750 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
1751 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
34f90529 | 1752 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); |
777dc784 PM |
1753 | } |
1754 | ||
1755 | static void ti925t_initfn(Object *obj) | |
1756 | { | |
1757 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 PM |
1758 | set_feature(&cpu->env, ARM_FEATURE_V4T); |
1759 | set_feature(&cpu->env, ARM_FEATURE_OMAPCP); | |
777dc784 | 1760 | cpu->midr = ARM_CPUID_TI925T; |
64e1671f | 1761 | cpu->ctr = 0x5109149; |
0ca7e01c | 1762 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1763 | } |
1764 | ||
1765 | static void sa1100_initfn(Object *obj) | |
1766 | { | |
1767 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1768 | |
1769 | cpu->dtb_compatible = "intel,sa1100"; | |
581be094 | 1770 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 1771 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1772 | cpu->midr = 0x4401A11B; |
0ca7e01c | 1773 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1774 | } |
1775 | ||
1776 | static void sa1110_initfn(Object *obj) | |
1777 | { | |
1778 | ARMCPU *cpu = ARM_CPU(obj); | |
581be094 | 1779 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
c4804214 | 1780 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
b2d06f96 | 1781 | cpu->midr = 0x6901B119; |
0ca7e01c | 1782 | cpu->reset_sctlr = 0x00000070; |
777dc784 PM |
1783 | } |
1784 | ||
1785 | static void pxa250_initfn(Object *obj) | |
1786 | { | |
1787 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1788 | |
1789 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1790 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1791 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1792 | cpu->midr = 0x69052100; |
64e1671f | 1793 | cpu->ctr = 0xd172172; |
0ca7e01c | 1794 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1795 | } |
1796 | ||
1797 | static void pxa255_initfn(Object *obj) | |
1798 | { | |
1799 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1800 | |
1801 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1802 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1803 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1804 | cpu->midr = 0x69052d00; |
64e1671f | 1805 | cpu->ctr = 0xd172172; |
0ca7e01c | 1806 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1807 | } |
1808 | ||
1809 | static void pxa260_initfn(Object *obj) | |
1810 | { | |
1811 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1812 | |
1813 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1814 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1815 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1816 | cpu->midr = 0x69052903; |
64e1671f | 1817 | cpu->ctr = 0xd172172; |
0ca7e01c | 1818 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1819 | } |
1820 | ||
1821 | static void pxa261_initfn(Object *obj) | |
1822 | { | |
1823 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1824 | |
1825 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1826 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1827 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1828 | cpu->midr = 0x69052d05; |
64e1671f | 1829 | cpu->ctr = 0xd172172; |
0ca7e01c | 1830 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1831 | } |
1832 | ||
1833 | static void pxa262_initfn(Object *obj) | |
1834 | { | |
1835 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1836 | |
1837 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1838 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1839 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
b2d06f96 | 1840 | cpu->midr = 0x69052d06; |
64e1671f | 1841 | cpu->ctr = 0xd172172; |
0ca7e01c | 1842 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1843 | } |
1844 | ||
1845 | static void pxa270a0_initfn(Object *obj) | |
1846 | { | |
1847 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1848 | |
1849 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1850 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1851 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1852 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1853 | cpu->midr = 0x69054110; |
64e1671f | 1854 | cpu->ctr = 0xd172172; |
0ca7e01c | 1855 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1856 | } |
1857 | ||
1858 | static void pxa270a1_initfn(Object *obj) | |
1859 | { | |
1860 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1861 | |
1862 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1863 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1864 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1865 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1866 | cpu->midr = 0x69054111; |
64e1671f | 1867 | cpu->ctr = 0xd172172; |
0ca7e01c | 1868 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1869 | } |
1870 | ||
1871 | static void pxa270b0_initfn(Object *obj) | |
1872 | { | |
1873 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1874 | |
1875 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1876 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1877 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1878 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1879 | cpu->midr = 0x69054112; |
64e1671f | 1880 | cpu->ctr = 0xd172172; |
0ca7e01c | 1881 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1882 | } |
1883 | ||
1884 | static void pxa270b1_initfn(Object *obj) | |
1885 | { | |
1886 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1887 | |
1888 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1889 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1890 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1891 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1892 | cpu->midr = 0x69054113; |
64e1671f | 1893 | cpu->ctr = 0xd172172; |
0ca7e01c | 1894 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1895 | } |
1896 | ||
1897 | static void pxa270c0_initfn(Object *obj) | |
1898 | { | |
1899 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1900 | |
1901 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1902 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1903 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1904 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1905 | cpu->midr = 0x69054114; |
64e1671f | 1906 | cpu->ctr = 0xd172172; |
0ca7e01c | 1907 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1908 | } |
1909 | ||
1910 | static void pxa270c5_initfn(Object *obj) | |
1911 | { | |
1912 | ARMCPU *cpu = ARM_CPU(obj); | |
54d3e3f5 PM |
1913 | |
1914 | cpu->dtb_compatible = "marvell,xscale"; | |
581be094 PM |
1915 | set_feature(&cpu->env, ARM_FEATURE_V5); |
1916 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
1917 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
b2d06f96 | 1918 | cpu->midr = 0x69054117; |
64e1671f | 1919 | cpu->ctr = 0xd172172; |
0ca7e01c | 1920 | cpu->reset_sctlr = 0x00000078; |
777dc784 PM |
1921 | } |
1922 | ||
bab52d4b PM |
1923 | #ifndef TARGET_AARCH64 |
1924 | /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); | |
1925 | * otherwise, a CPU with as many features enabled as our emulation supports. | |
1926 | * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; | |
1927 | * this only needs to handle 32 bits. | |
1928 | */ | |
1929 | static void arm_max_initfn(Object *obj) | |
1930 | { | |
1931 | ARMCPU *cpu = ARM_CPU(obj); | |
1932 | ||
1933 | if (kvm_enabled()) { | |
1934 | kvm_arm_set_cpu_features_from_host(cpu); | |
1935 | } else { | |
1936 | cortex_a15_initfn(obj); | |
a0032cc5 PM |
1937 | #ifdef CONFIG_USER_ONLY |
1938 | /* We don't set these in system emulation mode for the moment, | |
962fcbf2 RH |
1939 | * since we don't correctly set (all of) the ID registers to |
1940 | * advertise them. | |
bab52d4b | 1941 | */ |
a0032cc5 | 1942 | set_feature(&cpu->env, ARM_FEATURE_V8); |
962fcbf2 RH |
1943 | { |
1944 | uint32_t t; | |
1945 | ||
1946 | t = cpu->isar.id_isar5; | |
1947 | t = FIELD_DP32(t, ID_ISAR5, AES, 2); | |
1948 | t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); | |
1949 | t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); | |
1950 | t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); | |
1951 | t = FIELD_DP32(t, ID_ISAR5, RDM, 1); | |
1952 | t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); | |
1953 | cpu->isar.id_isar5 = t; | |
1954 | ||
1955 | t = cpu->isar.id_isar6; | |
1956 | t = FIELD_DP32(t, ID_ISAR6, DP, 1); | |
1957 | cpu->isar.id_isar6 = t; | |
ab638a32 RH |
1958 | |
1959 | t = cpu->id_mmfr4; | |
1960 | t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | |
1961 | cpu->id_mmfr4 = t; | |
962fcbf2 | 1962 | } |
bab52d4b | 1963 | #endif |
a0032cc5 | 1964 | } |
777dc784 | 1965 | } |
f5f6d38b | 1966 | #endif |
777dc784 | 1967 | |
15ee776b PM |
1968 | #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ |
1969 | ||
51e5ef45 | 1970 | struct ARMCPUInfo { |
777dc784 PM |
1971 | const char *name; |
1972 | void (*initfn)(Object *obj); | |
e6f010cc | 1973 | void (*class_init)(ObjectClass *oc, void *data); |
51e5ef45 | 1974 | }; |
777dc784 PM |
1975 | |
1976 | static const ARMCPUInfo arm_cpus[] = { | |
15ee776b | 1977 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) |
777dc784 PM |
1978 | { .name = "arm926", .initfn = arm926_initfn }, |
1979 | { .name = "arm946", .initfn = arm946_initfn }, | |
1980 | { .name = "arm1026", .initfn = arm1026_initfn }, | |
1981 | /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an | |
1982 | * older core than plain "arm1136". In particular this does not | |
1983 | * have the v6K features. | |
1984 | */ | |
1985 | { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, | |
1986 | { .name = "arm1136", .initfn = arm1136_initfn }, | |
1987 | { .name = "arm1176", .initfn = arm1176_initfn }, | |
1988 | { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, | |
191776b9 SH |
1989 | { .name = "cortex-m0", .initfn = cortex_m0_initfn, |
1990 | .class_init = arm_v7m_class_init }, | |
e6f010cc AF |
1991 | { .name = "cortex-m3", .initfn = cortex_m3_initfn, |
1992 | .class_init = arm_v7m_class_init }, | |
ba890a9b AR |
1993 | { .name = "cortex-m4", .initfn = cortex_m4_initfn, |
1994 | .class_init = arm_v7m_class_init }, | |
c7b26382 PM |
1995 | { .name = "cortex-m33", .initfn = cortex_m33_initfn, |
1996 | .class_init = arm_v7m_class_init }, | |
d6a6b13e | 1997 | { .name = "cortex-r5", .initfn = cortex_r5_initfn }, |
ebac5458 | 1998 | { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, |
dcf578ed | 1999 | { .name = "cortex-a7", .initfn = cortex_a7_initfn }, |
777dc784 PM |
2000 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, |
2001 | { .name = "cortex-a9", .initfn = cortex_a9_initfn }, | |
2002 | { .name = "cortex-a15", .initfn = cortex_a15_initfn }, | |
2003 | { .name = "ti925t", .initfn = ti925t_initfn }, | |
2004 | { .name = "sa1100", .initfn = sa1100_initfn }, | |
2005 | { .name = "sa1110", .initfn = sa1110_initfn }, | |
2006 | { .name = "pxa250", .initfn = pxa250_initfn }, | |
2007 | { .name = "pxa255", .initfn = pxa255_initfn }, | |
2008 | { .name = "pxa260", .initfn = pxa260_initfn }, | |
2009 | { .name = "pxa261", .initfn = pxa261_initfn }, | |
2010 | { .name = "pxa262", .initfn = pxa262_initfn }, | |
2011 | /* "pxa270" is an alias for "pxa270-a0" */ | |
2012 | { .name = "pxa270", .initfn = pxa270a0_initfn }, | |
2013 | { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, | |
2014 | { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, | |
2015 | { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, | |
2016 | { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, | |
2017 | { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, | |
2018 | { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, | |
bab52d4b PM |
2019 | #ifndef TARGET_AARCH64 |
2020 | { .name = "max", .initfn = arm_max_initfn }, | |
2021 | #endif | |
f5f6d38b | 2022 | #ifdef CONFIG_USER_ONLY |
a0032cc5 | 2023 | { .name = "any", .initfn = arm_max_initfn }, |
f5f6d38b | 2024 | #endif |
15ee776b | 2025 | #endif |
83e6813a | 2026 | { .name = NULL } |
777dc784 PM |
2027 | }; |
2028 | ||
5de16430 PM |
2029 | static Property arm_cpu_properties[] = { |
2030 | DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), | |
98128601 | 2031 | DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), |
51a9b04b | 2032 | DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), |
ce5b1bbf LV |
2033 | DEFINE_PROP_UINT64("mp-affinity", ARMCPU, |
2034 | mp_affinity, ARM64_AFFINITY_INVALID), | |
15f8b142 | 2035 | DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), |
f9a69711 | 2036 | DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), |
5de16430 PM |
2037 | DEFINE_PROP_END_OF_LIST() |
2038 | }; | |
2039 | ||
8c6084bf | 2040 | #ifdef CONFIG_USER_ONLY |
98670d47 LV |
2041 | static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, |
2042 | int rw, int mmu_idx) | |
8c6084bf PM |
2043 | { |
2044 | ARMCPU *cpu = ARM_CPU(cs); | |
2045 | CPUARMState *env = &cpu->env; | |
2046 | ||
2047 | env->exception.vaddress = address; | |
2048 | if (rw == 2) { | |
2049 | cs->exception_index = EXCP_PREFETCH_ABORT; | |
2050 | } else { | |
2051 | cs->exception_index = EXCP_DATA_ABORT; | |
2052 | } | |
2053 | return 1; | |
2054 | } | |
2055 | #endif | |
2056 | ||
b3820e6c DH |
2057 | static gchar *arm_gdb_arch_name(CPUState *cs) |
2058 | { | |
2059 | ARMCPU *cpu = ARM_CPU(cs); | |
2060 | CPUARMState *env = &cpu->env; | |
2061 | ||
2062 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
2063 | return g_strdup("iwmmxt"); | |
2064 | } | |
2065 | return g_strdup("arm"); | |
2066 | } | |
2067 | ||
dec9c2d4 AF |
2068 | static void arm_cpu_class_init(ObjectClass *oc, void *data) |
2069 | { | |
2070 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
2071 | CPUClass *cc = CPU_CLASS(acc); | |
14969266 AF |
2072 | DeviceClass *dc = DEVICE_CLASS(oc); |
2073 | ||
bf853881 PMD |
2074 | device_class_set_parent_realize(dc, arm_cpu_realizefn, |
2075 | &acc->parent_realize); | |
5de16430 | 2076 | dc->props = arm_cpu_properties; |
dec9c2d4 AF |
2077 | |
2078 | acc->parent_reset = cc->reset; | |
2079 | cc->reset = arm_cpu_reset; | |
5900d6b2 AF |
2080 | |
2081 | cc->class_by_name = arm_cpu_class_by_name; | |
8c2e1b00 | 2082 | cc->has_work = arm_cpu_has_work; |
e8925712 | 2083 | cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; |
878096ee | 2084 | cc->dump_state = arm_cpu_dump_state; |
f45748f1 | 2085 | cc->set_pc = arm_cpu_set_pc; |
5b50e790 AF |
2086 | cc->gdb_read_register = arm_cpu_gdb_read_register; |
2087 | cc->gdb_write_register = arm_cpu_gdb_write_register; | |
7510454e AF |
2088 | #ifdef CONFIG_USER_ONLY |
2089 | cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; | |
2090 | #else | |
0adf7d3c | 2091 | cc->do_interrupt = arm_cpu_do_interrupt; |
30901475 | 2092 | cc->do_unaligned_access = arm_cpu_do_unaligned_access; |
c79c0a31 | 2093 | cc->do_transaction_failed = arm_cpu_do_transaction_failed; |
0faea0c7 | 2094 | cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; |
017518c1 | 2095 | cc->asidx_from_attrs = arm_asidx_from_attrs; |
00b941e5 | 2096 | cc->vmsd = &vmstate_arm_cpu; |
ed50ff78 | 2097 | cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; |
da2b9140 AJ |
2098 | cc->write_elf64_note = arm_cpu_write_elf64_note; |
2099 | cc->write_elf32_note = arm_cpu_write_elf32_note; | |
00b941e5 | 2100 | #endif |
a0e372f0 | 2101 | cc->gdb_num_core_regs = 26; |
5b24c641 | 2102 | cc->gdb_core_xml_file = "arm-core.xml"; |
b3820e6c | 2103 | cc->gdb_arch_name = arm_gdb_arch_name; |
200bf5b7 | 2104 | cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml; |
2472b6c0 | 2105 | cc->gdb_stop_before_watchpoint = true; |
3ff6fc91 | 2106 | cc->debug_excp_handler = arm_debug_excp_handler; |
3826121d | 2107 | cc->debug_check_watchpoint = arm_debug_check_watchpoint; |
40612000 JB |
2108 | #if !defined(CONFIG_USER_ONLY) |
2109 | cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; | |
2110 | #endif | |
48440620 PC |
2111 | |
2112 | cc->disas_set_info = arm_disas_set_info; | |
74d7fc7f | 2113 | #ifdef CONFIG_TCG |
55c3ceef | 2114 | cc->tcg_initialize = arm_translate_init; |
74d7fc7f | 2115 | #endif |
dec9c2d4 AF |
2116 | } |
2117 | ||
86f0a186 PM |
2118 | #ifdef CONFIG_KVM |
2119 | static void arm_host_initfn(Object *obj) | |
2120 | { | |
2121 | ARMCPU *cpu = ARM_CPU(obj); | |
2122 | ||
2123 | kvm_arm_set_cpu_features_from_host(cpu); | |
51e5ef45 | 2124 | arm_cpu_post_init(obj); |
86f0a186 PM |
2125 | } |
2126 | ||
2127 | static const TypeInfo host_arm_cpu_type_info = { | |
2128 | .name = TYPE_ARM_HOST_CPU, | |
2129 | #ifdef TARGET_AARCH64 | |
2130 | .parent = TYPE_AARCH64_CPU, | |
2131 | #else | |
2132 | .parent = TYPE_ARM_CPU, | |
2133 | #endif | |
2134 | .instance_init = arm_host_initfn, | |
2135 | }; | |
2136 | ||
2137 | #endif | |
2138 | ||
51e5ef45 MAL |
2139 | static void arm_cpu_instance_init(Object *obj) |
2140 | { | |
2141 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); | |
2142 | ||
2143 | acc->info->initfn(obj); | |
2144 | arm_cpu_post_init(obj); | |
2145 | } | |
2146 | ||
2147 | static void cpu_register_class_init(ObjectClass *oc, void *data) | |
2148 | { | |
2149 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
2150 | ||
2151 | acc->info = data; | |
2152 | } | |
2153 | ||
777dc784 PM |
2154 | static void cpu_register(const ARMCPUInfo *info) |
2155 | { | |
2156 | TypeInfo type_info = { | |
777dc784 PM |
2157 | .parent = TYPE_ARM_CPU, |
2158 | .instance_size = sizeof(ARMCPU), | |
51e5ef45 | 2159 | .instance_init = arm_cpu_instance_init, |
777dc784 | 2160 | .class_size = sizeof(ARMCPUClass), |
51e5ef45 MAL |
2161 | .class_init = info->class_init ?: cpu_register_class_init, |
2162 | .class_data = (void *)info, | |
777dc784 PM |
2163 | }; |
2164 | ||
51492fd1 | 2165 | type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); |
918fd083 | 2166 | type_register(&type_info); |
51492fd1 | 2167 | g_free((void *)type_info.name); |
777dc784 PM |
2168 | } |
2169 | ||
dec9c2d4 AF |
2170 | static const TypeInfo arm_cpu_type_info = { |
2171 | .name = TYPE_ARM_CPU, | |
2172 | .parent = TYPE_CPU, | |
2173 | .instance_size = sizeof(ARMCPU), | |
777dc784 | 2174 | .instance_init = arm_cpu_initfn, |
4b6a83fb | 2175 | .instance_finalize = arm_cpu_finalizefn, |
777dc784 | 2176 | .abstract = true, |
dec9c2d4 AF |
2177 | .class_size = sizeof(ARMCPUClass), |
2178 | .class_init = arm_cpu_class_init, | |
2179 | }; | |
2180 | ||
181962fd PM |
2181 | static const TypeInfo idau_interface_type_info = { |
2182 | .name = TYPE_IDAU_INTERFACE, | |
2183 | .parent = TYPE_INTERFACE, | |
2184 | .class_size = sizeof(IDAUInterfaceClass), | |
2185 | }; | |
2186 | ||
dec9c2d4 AF |
2187 | static void arm_cpu_register_types(void) |
2188 | { | |
83e6813a | 2189 | const ARMCPUInfo *info = arm_cpus; |
777dc784 | 2190 | |
dec9c2d4 | 2191 | type_register_static(&arm_cpu_type_info); |
181962fd | 2192 | type_register_static(&idau_interface_type_info); |
83e6813a PM |
2193 | |
2194 | while (info->name) { | |
2195 | cpu_register(info); | |
2196 | info++; | |
777dc784 | 2197 | } |
86f0a186 PM |
2198 | |
2199 | #ifdef CONFIG_KVM | |
2200 | type_register_static(&host_arm_cpu_type_info); | |
2201 | #endif | |
dec9c2d4 AF |
2202 | } |
2203 | ||
2204 | type_init(arm_cpu_register_types) |