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target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field
[mirror_qemu.git] / target / arm / cpu.c
CommitLineData
dec9c2d4
AF		 1/*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
74c21bd0 21#include "qemu/osdep.h"
86480615 22#include "qemu/qemu-print.h"
a8d25326 23#include "qemu-common.h"
181962fd 24#include "target/arm/idau.h"
0b8fa32f 25#include "qemu/module.h"
da34e65c 26#include "qapi/error.h"
f9f62e4c 27#include "qapi/visitor.h"
778c3a06 28#include "cpu.h"
ccd38087 29#include "internals.h"
63c91552 30#include "exec/exec-all.h"
5de16430 31#include "hw/qdev-properties.h"
3c30dd5a
PM		 32#if !defined(CONFIG_USER_ONLY)
33#include "hw/loader.h"
cc7d44c2 34#include "hw/boards.h"
3c30dd5a 35#endif
9c17d615 36#include "sysemu/sysemu.h"
14a48c1d 37#include "sysemu/tcg.h"
b3946626 38#include "sysemu/hw_accel.h"
50a2c6e5 39#include "kvm_arm.h"
110f6c70 40#include "disas/capstone.h"
24f91e81 41#include "fpu/softfloat.h"
dec9c2d4 42
f45748f1
AF		 43static void arm_cpu_set_pc(CPUState *cs, vaddr value)
44{
45 ARMCPU *cpu = ARM_CPU(cs);
42f6ed91
JS		 46 CPUARMState *env = &cpu->env;
47
48 if (is_a64(env)) {
49 env->pc = value;
50 env->thumb = 0;
51 } else {
52 env->regs[15] = value & ~1;
53 env->thumb = value & 1;
54 }
55}
f45748f1 56
42f6ed91
JS		 57static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
58{
59 ARMCPU *cpu = ARM_CPU(cs);
60 CPUARMState *env = &cpu->env;
61
62 /*
63 * It's OK to look at env for the current mode here, because it's
64 * never possible for an AArch64 TB to chain to an AArch32 TB.
65 */
66 if (is_a64(env)) {
67 env->pc = tb->pc;
68 } else {
69 env->regs[15] = tb->pc;
70 }
f45748f1
AF		 71}
72
8c2e1b00
AF		 73static bool arm_cpu_has_work(CPUState *cs)
74{
543486db
RH		 75 ARMCPU *cpu = ARM_CPU(cs);
76
062ba099 77 return (cpu->power_state != PSCI_OFF)
543486db 78 && cs->interrupt_request &
136e67e9
EI		 79 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
80 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
81 | CPU_INTERRUPT_EXITTB);
8c2e1b00
AF		 82}
83
b5c53d1b
AL		 84void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
85 void *opaque)
86{
87 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
88
89 entry->hook = hook;
90 entry->opaque = opaque;
91
92 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
93}
94
08267487 95void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
bd7d00fc
PM		 96 void *opaque)
97{
08267487
AL		 98 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
99
100 entry->hook = hook;
101 entry->opaque = opaque;
102
103 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
bd7d00fc
PM		 104}
105
4b6a83fb
PM		 106static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
107{
108 /* Reset a single ARMCPRegInfo register */
109 ARMCPRegInfo *ri = value;
110 ARMCPU *cpu = opaque;
111
b061a82b 112 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
4b6a83fb
PM		 113 return;
114 }
115
116 if (ri->resetfn) {
117 ri->resetfn(&cpu->env, ri);
118 return;
119 }
120
121 /* A zero offset is never possible as it would be regs[0]
122 * so we use it to indicate that reset is being handled elsewhere.
123 * This is basically only used for fields in non-core coprocessors
124 * (like the pxa2xx ones).
125 */
126 if (!ri->fieldoffset) {
127 return;
128 }
129
67ed771d 130 if (cpreg_field_is_64bit(ri)) {
4b6a83fb
PM		 131 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
132 } else {
133 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
134 }
135}
136
49a66191
PM		 137static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
138{
139 /* Purely an assertion check: we've already done reset once,
140 * so now check that running the reset for the cpreg doesn't
141 * change its value. This traps bugs where two different cpregs
142 * both try to reset the same state field but to different values.
143 */
144 ARMCPRegInfo *ri = value;
145 ARMCPU *cpu = opaque;
146 uint64_t oldvalue, newvalue;
147
148 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
149 return;
150 }
151
152 oldvalue = read_raw_cp_reg(&cpu->env, ri);
153 cp_reg_reset(key, value, opaque);
154 newvalue = read_raw_cp_reg(&cpu->env, ri);
155 assert(oldvalue == newvalue);
156}
157
dec9c2d4
AF		 158/* CPUClass::reset() */
159static void arm_cpu_reset(CPUState *s)
160{
161 ARMCPU *cpu = ARM_CPU(s);
162 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
3c30dd5a 163 CPUARMState *env = &cpu->env;
3c30dd5a 164
dec9c2d4
AF		 165 acc->parent_reset(s);
166
1f5c00cf
AB		 167 memset(env, 0, offsetof(CPUARMState, end_reset_fields));
168
4b6a83fb 169 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
49a66191
PM		 170 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
171
3c30dd5a 172 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
47576b94
RH		 173 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
174 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
175 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
3c30dd5a 176
062ba099 177 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON;
543486db
RH		 178 s->halted = cpu->start_powered_off;
179
3c30dd5a
PM		 180 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
181 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
182 }
183
3926cc84
AG		 184 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
185 /* 64 bit CPUs always start in 64 bit mode */
186 env->aarch64 = 1;
d356312f
PM		 187#if defined(CONFIG_USER_ONLY)
188 env->pstate = PSTATE_MODE_EL0t;
14e5f106 189 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
137feaa9 190 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
276c6e81
RH		 191 /* Enable all PAC keys. */
192 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
193 SCTLR_EnDA | SCTLR_EnDB);
1ae9cfbd
RH		 194 /* Enable all PAC instructions */
195 env->cp15.hcr_el2 |= HCR_API;
196 env->cp15.scr_el3 |= SCR_API;
8c6afa6a 197 /* and to the FP/Neon instructions */
7ebd5f2e 198 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
802ac0e1
RH		 199 /* and to the SVE instructions */
200 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
201 env->cp15.cptr_el[3] |= CPTR_EZ;
202 /* with maximum vector length */
73234775
AJ		 203 env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ?
204 cpu->sve_max_vq - 1 : 0;
adf92eab
RH		 205 env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
206 env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
f6a148fe
RH		 207 /*
208 * Enable TBI0 and TBI1. While the real kernel only enables TBI0,
209 * turning on both here will produce smaller code and otherwise
210 * make no difference to the user-level emulation.
211 */
212 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37);
d356312f 213#else
5097227c
GB		 214 /* Reset into the highest available EL */
215 if (arm_feature(env, ARM_FEATURE_EL3)) {
216 env->pstate = PSTATE_MODE_EL3h;
217 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
218 env->pstate = PSTATE_MODE_EL2h;
219 } else {
220 env->pstate = PSTATE_MODE_EL1h;
221 }
3933443e 222 env->pc = cpu->rvbar;
8c6afa6a
PM		 223#endif
224 } else {
225#if defined(CONFIG_USER_ONLY)
226 /* Userspace expects access to cp10 and cp11 for FP/Neon */
7ebd5f2e 227 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
d356312f 228#endif
3926cc84
AG		 229 }
230
3c30dd5a
PM		 231#if defined(CONFIG_USER_ONLY)
232 env->uncached_cpsr = ARM_CPU_MODE_USR;
233 /* For user mode we must enable access to coprocessors */
234 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
235 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
236 env->cp15.c15_cpar = 3;
237 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
238 env->cp15.c15_cpar = 1;
239 }
240#else
060a65df
PM		 241
242 /*
243 * If the highest available EL is EL2, AArch32 will start in Hyp
244 * mode; otherwise it starts in SVC. Note that if we start in
245 * AArch64 then these values in the uncached_cpsr will be ignored.
246 */
247 if (arm_feature(env, ARM_FEATURE_EL2) &&
248 !arm_feature(env, ARM_FEATURE_EL3)) {
249 env->uncached_cpsr = ARM_CPU_MODE_HYP;
250 } else {
251 env->uncached_cpsr = ARM_CPU_MODE_SVC;
252 }
4cc35614 253 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
dc7abe4d 254
531c60a9 255 if (arm_feature(env, ARM_FEATURE_M)) {
6e3cf5df
MG		 256 uint32_t initial_msp; /* Loaded from 0x0 */
257 uint32_t initial_pc; /* Loaded from 0x4 */
3c30dd5a 258 uint8_t *rom;
38e2a77c 259 uint32_t vecbase;
6e3cf5df 260
1e577cc7
PM		 261 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
262 env->v7m.secure = true;
3b2e9344
PM		 263 } else {
264 /* This bit resets to 0 if security is supported, but 1 if
265 * it is not. The bit is not present in v7M, but we set it
266 * here so we can avoid having to make checks on it conditional
267 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
268 */
269 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
02ac2f7f
PM		 270 /*
271 * Set NSACR to indicate "NS access permitted to everything";
272 * this avoids having to have all the tests of it being
273 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
274 * v8.1M the guest-visible value of NSACR in a CPU without the
275 * Security Extension is 0xcff.
276 */
277 env->v7m.nsacr = 0xcff;
1e577cc7
PM		 278 }
279
9d40cd8a 280 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
2c4da50d 281 * that it resets to 1, so QEMU always does that rather than making
9d40cd8a 282 * it dependent on CPU model. In v8M it is RES1.
2c4da50d 283 */
9d40cd8a
PM		 284 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
285 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
286 if (arm_feature(env, ARM_FEATURE_V8)) {
287 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
288 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
289 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
290 }
22ab3460
JS		 291 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
292 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
293 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
294 }
2c4da50d 295
d33abe82
PM		 296 if (arm_feature(env, ARM_FEATURE_VFP)) {
297 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
298 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
299 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
300 }
056f43df
PM		 301 /* Unlike A/R profile, M profile defines the reset LR value */
302 env->regs[14] = 0xffffffff;
303
38e2a77c
PM		 304 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
305
306 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
307 vecbase = env->v7m.vecbase[env->v7m.secure];
0f0f8b61 308 rom = rom_ptr(vecbase, 8);
3c30dd5a 309 if (rom) {
6e3cf5df
MG		 310 /* Address zero is covered by ROM which hasn't yet been
311 * copied into physical memory.
312 */
313 initial_msp = ldl_p(rom);
314 initial_pc = ldl_p(rom + 4);
315 } else {
316 /* Address zero not covered by a ROM blob, or the ROM blob
317 * is in non-modifiable memory and this is a second reset after
318 * it got copied into memory. In the latter case, rom_ptr
319 * will return a NULL pointer and we should use ldl_phys instead.
320 */
38e2a77c
PM		 321 initial_msp = ldl_phys(s->as, vecbase);
322 initial_pc = ldl_phys(s->as, vecbase + 4);
3c30dd5a 323 }
6e3cf5df
MG		 324
325 env->regs[13] = initial_msp & 0xFFFFFFFC;
326 env->regs[15] = initial_pc & ~1;
327 env->thumb = initial_pc & 1;
3c30dd5a 328 }
387f9806 329
137feaa9
FA		 330 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
331 * executing as AArch32 then check if highvecs are enabled and
332 * adjust the PC accordingly.
333 */
334 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
34bf7744 335 env->regs[15] = 0xFFFF0000;
387f9806
AP		 336 }
337
dc3c4c14
PM		 338 /* M profile requires that reset clears the exclusive monitor;
339 * A profile does not, but clearing it makes more sense than having it
340 * set with an exclusive access on address zero.
341 */
342 arm_clear_exclusive(env);
343
3c30dd5a 344 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
3c30dd5a 345#endif
69ceea64 346
0e1a46bb 347 if (arm_feature(env, ARM_FEATURE_PMSA)) {
69ceea64 348 if (cpu->pmsav7_dregion > 0) {
0e1a46bb 349 if (arm_feature(env, ARM_FEATURE_V8)) {
62c58ee0
PM		 350 memset(env->pmsav8.rbar[M_REG_NS], 0,
351 sizeof(*env->pmsav8.rbar[M_REG_NS])
352 * cpu->pmsav7_dregion);
353 memset(env->pmsav8.rlar[M_REG_NS], 0,
354 sizeof(*env->pmsav8.rlar[M_REG_NS])
355 * cpu->pmsav7_dregion);
356 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
357 memset(env->pmsav8.rbar[M_REG_S], 0,
358 sizeof(*env->pmsav8.rbar[M_REG_S])
359 * cpu->pmsav7_dregion);
360 memset(env->pmsav8.rlar[M_REG_S], 0,
361 sizeof(*env->pmsav8.rlar[M_REG_S])
362 * cpu->pmsav7_dregion);
363 }
0e1a46bb
PM		 364 } else if (arm_feature(env, ARM_FEATURE_V7)) {
365 memset(env->pmsav7.drbar, 0,
366 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
367 memset(env->pmsav7.drsr, 0,
368 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
369 memset(env->pmsav7.dracr, 0,
370 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
371 }
69ceea64 372 }
1bc04a88
PM		 373 env->pmsav7.rnr[M_REG_NS] = 0;
374 env->pmsav7.rnr[M_REG_S] = 0;
4125e6fe
PM		 375 env->pmsav8.mair0[M_REG_NS] = 0;
376 env->pmsav8.mair0[M_REG_S] = 0;
377 env->pmsav8.mair1[M_REG_NS] = 0;
378 env->pmsav8.mair1[M_REG_S] = 0;
69ceea64
PM		 379 }
380
9901c576
PM		 381 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
382 if (cpu->sau_sregion > 0) {
383 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
384 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
385 }
386 env->sau.rnr = 0;
387 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
388 * the Cortex-M33 does.
389 */
390 env->sau.ctrl = 0;
391 }
392
3c30dd5a
PM		 393 set_flush_to_zero(1, &env->vfp.standard_fp_status);
394 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
395 set_default_nan_mode(1, &env->vfp.standard_fp_status);
396 set_float_detect_tininess(float_tininess_before_rounding,
397 &env->vfp.fp_status);
398 set_float_detect_tininess(float_tininess_before_rounding,
399 &env->vfp.standard_fp_status);
bcc531f0
PM		 400 set_float_detect_tininess(float_tininess_before_rounding,
401 &env->vfp.fp_status_f16);
50a2c6e5
PB		 402#ifndef CONFIG_USER_ONLY
403 if (kvm_enabled()) {
404 kvm_arm_reset_vcpu(cpu);
405 }
406#endif
9ee98ce8 407
46747d15 408 hw_breakpoint_update_all(cpu);
9ee98ce8 409 hw_watchpoint_update_all(cpu);
a8a79c7a 410 arm_rebuild_hflags(env);
dec9c2d4
AF		 411}
412
310cedf3 413static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
be879556
RH		 414 unsigned int target_el,
415 unsigned int cur_el, bool secure,
416 uint64_t hcr_el2)
310cedf3
RH		 417{
418 CPUARMState *env = cs->env_ptr;
310cedf3 419 bool pstate_unmasked;
16e07f78 420 bool unmasked = false;
310cedf3
RH		 421
422 /*
423 * Don't take exceptions if they target a lower EL.
424 * This check should catch any exceptions that would not be taken
425 * but left pending.
426 */
427 if (cur_el > target_el) {
428 return false;
429 }
430
310cedf3
RH		 431 switch (excp_idx) {
432 case EXCP_FIQ:
433 pstate_unmasked = !(env->daif & PSTATE_F);
434 break;
435
436 case EXCP_IRQ:
437 pstate_unmasked = !(env->daif & PSTATE_I);
438 break;
439
440 case EXCP_VFIQ:
441 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
442 /* VFIQs are only taken when hypervized and non-secure. */
443 return false;
444 }
445 return !(env->daif & PSTATE_F);
446 case EXCP_VIRQ:
447 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
448 /* VIRQs are only taken when hypervized and non-secure. */
449 return false;
450 }
451 return !(env->daif & PSTATE_I);
452 default:
453 g_assert_not_reached();
454 }
455
456 /*
457 * Use the target EL, current execution state and SCR/HCR settings to
458 * determine whether the corresponding CPSR bit is used to mask the
459 * interrupt.
460 */
461 if ((target_el > cur_el) && (target_el != 1)) {
462 /* Exceptions targeting a higher EL may not be maskable */
463 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
464 /*
465 * 64-bit masking rules are simple: exceptions to EL3
466 * can't be masked, and exceptions to EL2 can only be
467 * masked from Secure state. The HCR and SCR settings
468 * don't affect the masking logic, only the interrupt routing.
469 */
470 if (target_el == 3 || !secure) {
16e07f78 471 unmasked = true;
310cedf3
RH		 472 }
473 } else {
474 /*
475 * The old 32-bit-only environment has a more complicated
476 * masking setup. HCR and SCR bits not only affect interrupt
477 * routing but also change the behaviour of masking.
478 */
479 bool hcr, scr;
480
481 switch (excp_idx) {
482 case EXCP_FIQ:
483 /*
484 * If FIQs are routed to EL3 or EL2 then there are cases where
485 * we override the CPSR.F in determining if the exception is
486 * masked or not. If neither of these are set then we fall back
487 * to the CPSR.F setting otherwise we further assess the state
488 * below.
489 */
490 hcr = hcr_el2 & HCR_FMO;
491 scr = (env->cp15.scr_el3 & SCR_FIQ);
492
493 /*
494 * When EL3 is 32-bit, the SCR.FW bit controls whether the
495 * CPSR.F bit masks FIQ interrupts when taken in non-secure
496 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
497 * when non-secure but only when FIQs are only routed to EL3.
498 */
499 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
500 break;
501 case EXCP_IRQ:
502 /*
503 * When EL3 execution state is 32-bit, if HCR.IMO is set then
504 * we may override the CPSR.I masking when in non-secure state.
505 * The SCR.IRQ setting has already been taken into consideration
506 * when setting the target EL, so it does not have a further
507 * affect here.
508 */
509 hcr = hcr_el2 & HCR_IMO;
510 scr = false;
511 break;
512 default:
513 g_assert_not_reached();
514 }
515
516 if ((scr || hcr) && !secure) {
16e07f78 517 unmasked = true;
310cedf3
RH		 518 }
519 }
520 }
521
522 /*
523 * The PSTATE bits only mask the interrupt if we have not overriden the
524 * ability above.
525 */
526 return unmasked || pstate_unmasked;
527}
528
e8925712
RH		 529bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
530{
531 CPUClass *cc = CPU_GET_CLASS(cs);
012a906b
GB		 532 CPUARMState *env = cs->env_ptr;
533 uint32_t cur_el = arm_current_el(env);
534 bool secure = arm_is_secure(env);
be879556 535 uint64_t hcr_el2 = arm_hcr_el2_eff(env);
012a906b
GB		 536 uint32_t target_el;
537 uint32_t excp_idx;
d63d0ec5
RH		 538
539 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
e8925712 540
012a906b
GB		 541 if (interrupt_request & CPU_INTERRUPT_FIQ) {
542 excp_idx = EXCP_FIQ;
543 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
be879556
RH		 544 if (arm_excp_unmasked(cs, excp_idx, target_el,
545 cur_el, secure, hcr_el2)) {
d63d0ec5 546 goto found;
012a906b 547 }
e8925712 548 }
012a906b
GB		 549 if (interrupt_request & CPU_INTERRUPT_HARD) {
550 excp_idx = EXCP_IRQ;
551 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
be879556
RH		 552 if (arm_excp_unmasked(cs, excp_idx, target_el,
553 cur_el, secure, hcr_el2)) {
d63d0ec5 554 goto found;
012a906b 555 }
e8925712 556 }
012a906b
GB		 557 if (interrupt_request & CPU_INTERRUPT_VIRQ) {
558 excp_idx = EXCP_VIRQ;
559 target_el = 1;
be879556
RH		 560 if (arm_excp_unmasked(cs, excp_idx, target_el,
561 cur_el, secure, hcr_el2)) {
d63d0ec5 562 goto found;
012a906b 563 }
136e67e9 564 }
012a906b
GB		 565 if (interrupt_request & CPU_INTERRUPT_VFIQ) {
566 excp_idx = EXCP_VFIQ;
567 target_el = 1;
be879556
RH		 568 if (arm_excp_unmasked(cs, excp_idx, target_el,
569 cur_el, secure, hcr_el2)) {
d63d0ec5 570 goto found;
012a906b 571 }
136e67e9 572 }
d63d0ec5 573 return false;
e8925712 574
d63d0ec5
RH		 575 found:
576 cs->exception_index = excp_idx;
577 env->exception.target_el = target_el;
578 cc->do_interrupt(cs);
579 return true;
e8925712
RH		 580}
581
b5c633c5
PM		 582#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
583static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
584{
585 CPUClass *cc = CPU_GET_CLASS(cs);
586 ARMCPU *cpu = ARM_CPU(cs);
587 CPUARMState *env = &cpu->env;
588 bool ret = false;
589
f4e8e4ed 590 /* ARMv7-M interrupt masking works differently than -A or -R.
7ecdaa4a
PM		 591 * There is no FIQ/IRQ distinction. Instead of I and F bits
592 * masking FIQ and IRQ interrupts, an exception is taken only
593 * if it is higher priority than the current execution priority
594 * (which depends on state like BASEPRI, FAULTMASK and the
595 * currently active exception).
b5c633c5
PM		 596 */
597 if (interrupt_request & CPU_INTERRUPT_HARD
f4e8e4ed 598 && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
b5c633c5
PM		 599 cs->exception_index = EXCP_IRQ;
600 cc->do_interrupt(cs);
601 ret = true;
602 }
603 return ret;
604}
605#endif
606
89430fc6
PM		 607void arm_cpu_update_virq(ARMCPU *cpu)
608{
609 /*
610 * Update the interrupt level for VIRQ, which is the logical OR of
611 * the HCR_EL2.VI bit and the input line level from the GIC.
612 */
613 CPUARMState *env = &cpu->env;
614 CPUState *cs = CPU(cpu);
615
616 bool new_state = (env->cp15.hcr_el2 & HCR_VI) ||
617 (env->irq_line_state & CPU_INTERRUPT_VIRQ);
618
619 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) {
620 if (new_state) {
621 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ);
622 } else {
623 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ);
624 }
625 }
626}
627
628void arm_cpu_update_vfiq(ARMCPU *cpu)
629{
630 /*
631 * Update the interrupt level for VFIQ, which is the logical OR of
632 * the HCR_EL2.VF bit and the input line level from the GIC.
633 */
634 CPUARMState *env = &cpu->env;
635 CPUState *cs = CPU(cpu);
636
637 bool new_state = (env->cp15.hcr_el2 & HCR_VF) ||
638 (env->irq_line_state & CPU_INTERRUPT_VFIQ);
639
640 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) {
641 if (new_state) {
642 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ);
643 } else {
644 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ);
645 }
646 }
647}
648
7c1840b6
PM		 649#ifndef CONFIG_USER_ONLY
650static void arm_cpu_set_irq(void *opaque, int irq, int level)
651{
652 ARMCPU *cpu = opaque;
136e67e9 653 CPUARMState *env = &cpu->env;
7c1840b6 654 CPUState *cs = CPU(cpu);
136e67e9
EI		 655 static const int mask[] = {
656 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
657 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
658 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
659 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
660 };
7c1840b6 661
ed89f078
PM		 662 if (level) {
663 env->irq_line_state |= mask[irq];
664 } else {
665 env->irq_line_state &= ~mask[irq];
666 }
667
7c1840b6 668 switch (irq) {
136e67e9 669 case ARM_CPU_VIRQ:
89430fc6
PM		 670 assert(arm_feature(env, ARM_FEATURE_EL2));
671 arm_cpu_update_virq(cpu);
672 break;
136e67e9 673 case ARM_CPU_VFIQ:
f128bf29 674 assert(arm_feature(env, ARM_FEATURE_EL2));
89430fc6
PM		 675 arm_cpu_update_vfiq(cpu);
676 break;
136e67e9 677 case ARM_CPU_IRQ:
7c1840b6
PM		 678 case ARM_CPU_FIQ:
679 if (level) {
136e67e9 680 cpu_interrupt(cs, mask[irq]);
7c1840b6 681 } else {
136e67e9 682 cpu_reset_interrupt(cs, mask[irq]);
7c1840b6
PM		 683 }
684 break;
685 default:
8f6fd322 686 g_assert_not_reached();
7c1840b6
PM		 687 }
688}
689
690static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
691{
692#ifdef CONFIG_KVM
693 ARMCPU *cpu = opaque;
ed89f078 694 CPUARMState *env = &cpu->env;
7c1840b6 695 CPUState *cs = CPU(cpu);
ed89f078 696 uint32_t linestate_bit;
f6530926 697 int irq_id;
7c1840b6
PM		 698
699 switch (irq) {
700 case ARM_CPU_IRQ:
f6530926 701 irq_id = KVM_ARM_IRQ_CPU_IRQ;
ed89f078 702 linestate_bit = CPU_INTERRUPT_HARD;
7c1840b6
PM		 703 break;
704 case ARM_CPU_FIQ:
f6530926 705 irq_id = KVM_ARM_IRQ_CPU_FIQ;
ed89f078 706 linestate_bit = CPU_INTERRUPT_FIQ;
7c1840b6
PM		 707 break;
708 default:
8f6fd322 709 g_assert_not_reached();
7c1840b6 710 }
ed89f078
PM		 711
712 if (level) {
713 env->irq_line_state |= linestate_bit;
714 } else {
715 env->irq_line_state &= ~linestate_bit;
716 }
f6530926 717 kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level);
7c1840b6
PM		 718#endif
719}
84f2bed3 720
ed50ff78 721static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
84f2bed3
PS		 722{
723 ARMCPU *cpu = ARM_CPU(cs);
724 CPUARMState *env = &cpu->env;
84f2bed3
PS		 725
726 cpu_synchronize_state(cs);
ed50ff78 727 return arm_cpu_data_is_big_endian(env);
84f2bed3
PS		 728}
729
7c1840b6
PM		 730#endif
731
581be094
PM		 732static inline void set_feature(CPUARMState *env, int feature)
733{
918f5dca 734 env->features |= 1ULL << feature;
581be094
PM		 735}
736
08828484
GB		 737static inline void unset_feature(CPUARMState *env, int feature)
738{
739 env->features &= ~(1ULL << feature);
740}
741
48440620
PC		 742static int
743print_insn_thumb1(bfd_vma pc, disassemble_info *info)
744{
745 return print_insn_arm(pc | 1, info);
746}
747
748static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
749{
750 ARMCPU *ac = ARM_CPU(cpu);
751 CPUARMState *env = &ac->env;
7bcdbf51 752 bool sctlr_b;
48440620
PC		 753
754 if (is_a64(env)) {
755 /* We might not be compiled with the A64 disassembler
756 * because it needs a C++ compiler. Leave print_insn
757 * unset in this case to use the caller default behaviour.
758 */
759#if defined(CONFIG_ARM_A64_DIS)
760 info->print_insn = print_insn_arm_a64;
761#endif
110f6c70 762 info->cap_arch = CS_ARCH_ARM64;
15fa1a0a
RH		 763 info->cap_insn_unit = 4;
764 info->cap_insn_split = 4;
48440620 765 } else {
110f6c70
RH		 766 int cap_mode;
767 if (env->thumb) {
768 info->print_insn = print_insn_thumb1;
15fa1a0a
RH		 769 info->cap_insn_unit = 2;
770 info->cap_insn_split = 4;
110f6c70
RH		 771 cap_mode = CS_MODE_THUMB;
772 } else {
773 info->print_insn = print_insn_arm;
15fa1a0a
RH		 774 info->cap_insn_unit = 4;
775 info->cap_insn_split = 4;
110f6c70
RH		 776 cap_mode = CS_MODE_ARM;
777 }
778 if (arm_feature(env, ARM_FEATURE_V8)) {
779 cap_mode |= CS_MODE_V8;
780 }
781 if (arm_feature(env, ARM_FEATURE_M)) {
782 cap_mode |= CS_MODE_MCLASS;
783 }
784 info->cap_arch = CS_ARCH_ARM;
785 info->cap_mode = cap_mode;
48440620 786 }
7bcdbf51
RH		 787
788 sctlr_b = arm_sctlr_b(env);
789 if (bswap_code(sctlr_b)) {
48440620
PC		 790#ifdef TARGET_WORDS_BIGENDIAN
791 info->endian = BFD_ENDIAN_LITTLE;
792#else
793 info->endian = BFD_ENDIAN_BIG;
794#endif
795 }
f7478a92 796 info->flags &= ~INSN_ARM_BE32;
7bcdbf51
RH		 797#ifndef CONFIG_USER_ONLY
798 if (sctlr_b) {
f7478a92
JB		 799 info->flags |= INSN_ARM_BE32;
800 }
7bcdbf51 801#endif
48440620
PC		 802}
803
86480615
PMD		 804#ifdef TARGET_AARCH64
805
806static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
807{
808 ARMCPU *cpu = ARM_CPU(cs);
809 CPUARMState *env = &cpu->env;
810 uint32_t psr = pstate_read(env);
811 int i;
812 int el = arm_current_el(env);
813 const char *ns_status;
814
815 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
816 for (i = 0; i < 32; i++) {
817 if (i == 31) {
818 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
819 } else {
820 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
821 (i + 2) % 3 ? " " : "\n");
822 }
823 }
824
825 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
826 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
827 } else {
828 ns_status = "";
829 }
830 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
831 psr,
832 psr & PSTATE_N ? 'N' : '-',
833 psr & PSTATE_Z ? 'Z' : '-',
834 psr & PSTATE_C ? 'C' : '-',
835 psr & PSTATE_V ? 'V' : '-',
836 ns_status,
837 el,
838 psr & PSTATE_SP ? 'h' : 't');
839
840 if (cpu_isar_feature(aa64_bti, cpu)) {
841 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
842 }
843 if (!(flags & CPU_DUMP_FPU)) {
844 qemu_fprintf(f, "\n");
845 return;
846 }
847 if (fp_exception_el(env, el) != 0) {
848 qemu_fprintf(f, " FPU disabled\n");
849 return;
850 }
851 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
852 vfp_get_fpcr(env), vfp_get_fpsr(env));
853
854 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
855 int j, zcr_len = sve_zcr_len_for_el(env, el);
856
857 for (i = 0; i <= FFR_PRED_NUM; i++) {
858 bool eol;
859 if (i == FFR_PRED_NUM) {
860 qemu_fprintf(f, "FFR=");
861 /* It's last, so end the line. */
862 eol = true;
863 } else {
864 qemu_fprintf(f, "P%02d=", i);
865 switch (zcr_len) {
866 case 0:
867 eol = i % 8 == 7;
868 break;
869 case 1:
870 eol = i % 6 == 5;
871 break;
872 case 2:
873 case 3:
874 eol = i % 3 == 2;
875 break;
876 default:
877 /* More than one quadword per predicate. */
878 eol = true;
879 break;
880 }
881 }
882 for (j = zcr_len / 4; j >= 0; j--) {
883 int digits;
884 if (j * 4 + 4 <= zcr_len + 1) {
885 digits = 16;
886 } else {
887 digits = (zcr_len % 4 + 1) * 4;
888 }
889 qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
890 env->vfp.pregs[i].p[j],
891 j ? ":" : eol ? "\n" : " ");
892 }
893 }
894
895 for (i = 0; i < 32; i++) {
896 if (zcr_len == 0) {
897 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
898 i, env->vfp.zregs[i].d[1],
899 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
900 } else if (zcr_len == 1) {
901 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
902 ":%016" PRIx64 ":%016" PRIx64 "\n",
903 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
904 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
905 } else {
906 for (j = zcr_len; j >= 0; j--) {
907 bool odd = (zcr_len - j) % 2 != 0;
908 if (j == zcr_len) {
909 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
910 } else if (!odd) {
911 if (j > 0) {
912 qemu_fprintf(f, " [%x-%x]=", j, j - 1);
913 } else {
914 qemu_fprintf(f, " [%x]=", j);
915 }
916 }
917 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
918 env->vfp.zregs[i].d[j * 2 + 1],
919 env->vfp.zregs[i].d[j * 2],
920 odd || j == 0 ? "\n" : ":");
921 }
922 }
923 }
924 } else {
925 for (i = 0; i < 32; i++) {
926 uint64_t *q = aa64_vfp_qreg(env, i);
927 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
928 i, q[1], q[0], (i & 1 ? "\n" : " "));
929 }
930 }
931}
932
933#else
934
935static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
936{
937 g_assert_not_reached();
938}
939
940#endif
941
942static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
943{
944 ARMCPU *cpu = ARM_CPU(cs);
945 CPUARMState *env = &cpu->env;
946 int i;
947
948 if (is_a64(env)) {
949 aarch64_cpu_dump_state(cs, f, flags);
950 return;
951 }
952
953 for (i = 0; i < 16; i++) {
954 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
955 if ((i % 4) == 3) {
956 qemu_fprintf(f, "\n");
957 } else {
958 qemu_fprintf(f, " ");
959 }
960 }
961
962 if (arm_feature(env, ARM_FEATURE_M)) {
963 uint32_t xpsr = xpsr_read(env);
964 const char *mode;
965 const char *ns_status = "";
966
967 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
968 ns_status = env->v7m.secure ? "S " : "NS ";
969 }
970
971 if (xpsr & XPSR_EXCP) {
972 mode = "handler";
973 } else {
974 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
975 mode = "unpriv-thread";
976 } else {
977 mode = "priv-thread";
978 }
979 }
980
981 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
982 xpsr,
983 xpsr & XPSR_N ? 'N' : '-',
984 xpsr & XPSR_Z ? 'Z' : '-',
985 xpsr & XPSR_C ? 'C' : '-',
986 xpsr & XPSR_V ? 'V' : '-',
987 xpsr & XPSR_T ? 'T' : 'A',
988 ns_status,
989 mode);
990 } else {
991 uint32_t psr = cpsr_read(env);
992 const char *ns_status = "";
993
994 if (arm_feature(env, ARM_FEATURE_EL3) &&
995 (psr & CPSR_M) != ARM_CPU_MODE_MON) {
996 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
997 }
998
999 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
1000 psr,
1001 psr & CPSR_N ? 'N' : '-',
1002 psr & CPSR_Z ? 'Z' : '-',
1003 psr & CPSR_C ? 'C' : '-',
1004 psr & CPSR_V ? 'V' : '-',
1005 psr & CPSR_T ? 'T' : 'A',
1006 ns_status,
1007 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
1008 }
1009
1010 if (flags & CPU_DUMP_FPU) {
1011 int numvfpregs = 0;
1012 if (arm_feature(env, ARM_FEATURE_VFP)) {
1013 numvfpregs += 16;
1014 }
1015 if (arm_feature(env, ARM_FEATURE_VFP3)) {
1016 numvfpregs += 16;
1017 }
1018 for (i = 0; i < numvfpregs; i++) {
1019 uint64_t v = *aa32_vfp_dreg(env, i);
1020 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
1021 i * 2, (uint32_t)v,
1022 i * 2 + 1, (uint32_t)(v >> 32),
1023 i, v);
1024 }
1025 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
1026 }
1027}
1028
46de5913
IM		 1029uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
1030{
1031 uint32_t Aff1 = idx / clustersz;
1032 uint32_t Aff0 = idx % clustersz;
1033 return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
1034}
1035
ac87e507
PM		 1036static void cpreg_hashtable_data_destroy(gpointer data)
1037{
1038 /*
1039 * Destroy function for cpu->cp_regs hashtable data entries.
1040 * We must free the name string because it was g_strdup()ed in
1041 * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
1042 * from r->name because we know we definitely allocated it.
1043 */
1044 ARMCPRegInfo *r = data;
1045
1046 g_free((void *)r->name);
1047 g_free(r);
1048}
1049
777dc784
PM		 1050static void arm_cpu_initfn(Object *obj)
1051{
1052 ARMCPU *cpu = ARM_CPU(obj);
1053
7506ed90 1054 cpu_set_cpustate_pointers(cpu);
4b6a83fb 1055 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
ac87e507 1056 g_free, cpreg_hashtable_data_destroy);
79614b78 1057
b5c53d1b 1058 QLIST_INIT(&cpu->pre_el_change_hooks);
08267487
AL		 1059 QLIST_INIT(&cpu->el_change_hooks);
1060
7c1840b6
PM		 1061#ifndef CONFIG_USER_ONLY
1062 /* Our inbound IRQ and FIQ lines */
1063 if (kvm_enabled()) {
136e67e9
EI		 1064 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
1065 * the same interface as non-KVM CPUs.
1066 */
1067 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
7c1840b6 1068 } else {
136e67e9 1069 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
7c1840b6 1070 }
55d284af 1071
55d284af
PM		 1072 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
1073 ARRAY_SIZE(cpu->gt_timer_outputs));
aa1b3111
PM		 1074
1075 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
1076 "gicv3-maintenance-interrupt", 1);
07f48730
AJ		 1077 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
1078 "pmu-interrupt", 1);
7c1840b6
PM		 1079#endif
1080
54d3e3f5
PM		 1081 /* DTB consumers generally don't in fact care what the 'compatible'
1082 * string is, so always provide some string and trust that a hypothetical
1083 * picky DTB consumer will also provide a helpful error message.
1084 */
1085 cpu->dtb_compatible = "qemu,unknown";
dd032e34 1086 cpu->psci_version = 1; /* By default assume PSCI v0.1 */
3541addc 1087 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
54d3e3f5 1088
98128601
RH		 1089 if (tcg_enabled()) {
1090 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
79614b78 1091 }
4b6a83fb
PM		 1092}
1093
96eec6b2
AJ		 1094static Property arm_cpu_gt_cntfrq_property =
1095 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz,
1096 NANOSECONDS_PER_SECOND / GTIMER_SCALE);
1097
07a5b0d2 1098static Property arm_cpu_reset_cbar_property =
f318cec6 1099 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
07a5b0d2 1100
68e0a40a
AP		 1101static Property arm_cpu_reset_hivecs_property =
1102 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
1103
3933443e
PM		 1104static Property arm_cpu_rvbar_property =
1105 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
1106
c25bd18a
PM		 1107static Property arm_cpu_has_el2_property =
1108 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
1109
51942aee
GB		 1110static Property arm_cpu_has_el3_property =
1111 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
1112
3a062d57
JB		 1113static Property arm_cpu_cfgend_property =
1114 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
1115
97a28b0e
PM		 1116static Property arm_cpu_has_vfp_property =
1117 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
1118
1119static Property arm_cpu_has_neon_property =
1120 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
1121
ea90db0a
PM		 1122static Property arm_cpu_has_dsp_property =
1123 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true);
1124
8f325f56
PC		 1125static Property arm_cpu_has_mpu_property =
1126 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
1127
8d92e26b
PM		 1128/* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1129 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1130 * the right value for that particular CPU type, and we don't want
1131 * to override that with an incorrect constant value.
1132 */
3281af81 1133static Property arm_cpu_pmsav7_dregion_property =
8d92e26b
PM		 1134 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
1135 pmsav7_dregion,
1136 qdev_prop_uint32, uint32_t);
3281af81 1137
ae502508
AJ		 1138static bool arm_get_pmu(Object *obj, Error **errp)
1139{
1140 ARMCPU *cpu = ARM_CPU(obj);
1141
1142 return cpu->has_pmu;
1143}
1144
1145static void arm_set_pmu(Object *obj, bool value, Error **errp)
1146{
1147 ARMCPU *cpu = ARM_CPU(obj);
1148
1149 if (value) {
1150 if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu))) {
1151 error_setg(errp, "'pmu' feature not supported by KVM on this host");
1152 return;
1153 }
1154 set_feature(&cpu->env, ARM_FEATURE_PMU);
1155 } else {
1156 unset_feature(&cpu->env, ARM_FEATURE_PMU);
1157 }
1158 cpu->has_pmu = value;
1159}
1160
f9f62e4c
PM		 1161static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name,
1162 void *opaque, Error **errp)
1163{
1164 ARMCPU *cpu = ARM_CPU(obj);
1165
1166 visit_type_uint32(v, name, &cpu->init_svtor, errp);
1167}
1168
1169static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name,
1170 void *opaque, Error **errp)
1171{
1172 ARMCPU *cpu = ARM_CPU(obj);
1173
1174 visit_type_uint32(v, name, &cpu->init_svtor, errp);
1175}
38e2a77c 1176
7def8754
AJ		 1177unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
1178{
96eec6b2
AJ		 1179 /*
1180 * The exact approach to calculating guest ticks is:
1181 *
1182 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1183 * NANOSECONDS_PER_SECOND);
1184 *
1185 * We don't do that. Rather we intentionally use integer division
1186 * truncation below and in the caller for the conversion of host monotonic
1187 * time to guest ticks to provide the exact inverse for the semantics of
1188 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1189 * it loses precision when representing frequencies where
1190 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1191 * provide an exact inverse leads to scheduling timers with negative
1192 * periods, which in turn leads to sticky behaviour in the guest.
1193 *
1194 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1195 * cannot become zero.
1196 */
7def8754
AJ		 1197 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ?
1198 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
1199}
1200
51e5ef45 1201void arm_cpu_post_init(Object *obj)
07a5b0d2
PC		 1202{
1203 ARMCPU *cpu = ARM_CPU(obj);
07a5b0d2 1204
790a1150
PM		 1205 /* M profile implies PMSA. We have to do this here rather than
1206 * in realize with the other feature-implication checks because
1207 * we look at the PMSA bit to see if we should add some properties.
1208 */
1209 if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
1210 set_feature(&cpu->env, ARM_FEATURE_PMSA);
1211 }
97a28b0e
PM		 1212 /* Similarly for the VFP feature bits */
1213 if (arm_feature(&cpu->env, ARM_FEATURE_VFP4)) {
1214 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1215 }
1216 if (arm_feature(&cpu->env, ARM_FEATURE_VFP3)) {
1217 set_feature(&cpu->env, ARM_FEATURE_VFP);
1218 }
790a1150 1219
f318cec6
PM		 1220 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
1221 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
94d912d1 1222 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property);
07a5b0d2 1223 }
68e0a40a
AP		 1224
1225 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
94d912d1 1226 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
68e0a40a 1227 }
3933443e
PM		 1228
1229 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
94d912d1 1230 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property);
3933443e 1231 }
51942aee
GB		 1232
1233 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1234 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1235 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1236 */
94d912d1 1237 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property);
9e273ef2
PM		 1238
1239#ifndef CONFIG_USER_ONLY
1240 object_property_add_link(obj, "secure-memory",
1241 TYPE_MEMORY_REGION,
1242 (Object **)&cpu->secure_memory,
1243 qdev_prop_allow_set_link_before_realize,
265b578c 1244 OBJ_PROP_LINK_STRONG,
9e273ef2
PM		 1245 &error_abort);
1246#endif
51942aee 1247 }
8f325f56 1248
c25bd18a 1249 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
94d912d1 1250 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property);
c25bd18a
PM		 1251 }
1252
929e754d 1253 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
ae502508
AJ		 1254 cpu->has_pmu = true;
1255 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu,
929e754d
WH		 1256 &error_abort);
1257 }
1258
97a28b0e
PM		 1259 /*
1260 * Allow user to turn off VFP and Neon support, but only for TCG --
1261 * KVM does not currently allow us to lie to the guest about its
1262 * ID/feature registers, so the guest always sees what the host has.
1263 */
1264 if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1265 cpu->has_vfp = true;
1266 if (!kvm_enabled()) {
94d912d1 1267 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property);
97a28b0e
PM		 1268 }
1269 }
1270
1271 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
1272 cpu->has_neon = true;
1273 if (!kvm_enabled()) {
94d912d1 1274 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property);
97a28b0e
PM		 1275 }
1276 }
1277
ea90db0a
PM		 1278 if (arm_feature(&cpu->env, ARM_FEATURE_M) &&
1279 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) {
94d912d1 1280 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property);
ea90db0a
PM		 1281 }
1282
452a0955 1283 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
94d912d1 1284 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property);
3281af81
PC		 1285 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1286 qdev_property_add_static(DEVICE(obj),
94d912d1 1287 &arm_cpu_pmsav7_dregion_property);
3281af81 1288 }
8f325f56
PC		 1289 }
1290
181962fd
PM		 1291 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
1292 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
1293 qdev_prop_allow_set_link_before_realize,
265b578c 1294 OBJ_PROP_LINK_STRONG,
181962fd 1295 &error_abort);
f9f62e4c
PM		 1296 /*
1297 * M profile: initial value of the Secure VTOR. We can't just use
1298 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1299 * the property to be set after realize.
1300 */
1301 object_property_add(obj, "init-svtor", "uint32",
1302 arm_get_init_svtor, arm_set_init_svtor,
1303 NULL, NULL, &error_abort);
181962fd
PM		 1304 }
1305
94d912d1 1306 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property);
96eec6b2
AJ		 1307
1308 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) {
94d912d1 1309 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property);
96eec6b2 1310 }
07a5b0d2
PC		 1311}
1312
4b6a83fb
PM		 1313static void arm_cpu_finalizefn(Object *obj)
1314{
1315 ARMCPU *cpu = ARM_CPU(obj);
08267487
AL		 1316 ARMELChangeHook *hook, *next;
1317
4b6a83fb 1318 g_hash_table_destroy(cpu->cp_regs);
08267487 1319
b5c53d1b
AL		 1320 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
1321 QLIST_REMOVE(hook, node);
1322 g_free(hook);
1323 }
08267487
AL		 1324 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
1325 QLIST_REMOVE(hook, node);
1326 g_free(hook);
1327 }
4e7beb0c
AL		 1328#ifndef CONFIG_USER_ONLY
1329 if (cpu->pmu_timer) {
1330 timer_del(cpu->pmu_timer);
1331 timer_deinit(cpu->pmu_timer);
1332 timer_free(cpu->pmu_timer);
1333 }
1334#endif
777dc784
PM		 1335}
1336
0df9142d
AJ		 1337void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
1338{
1339 Error *local_err = NULL;
1340
1341 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1342 arm_cpu_sve_finalize(cpu, &local_err);
1343 if (local_err != NULL) {
1344 error_propagate(errp, local_err);
1345 return;
1346 }
1347 }
1348}
1349
14969266 1350static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
581be094 1351{
14a10fc3 1352 CPUState *cs = CPU(dev);
14969266
AF		 1353 ARMCPU *cpu = ARM_CPU(dev);
1354 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
581be094 1355 CPUARMState *env = &cpu->env;
e97da98f 1356 int pagebits;
ce5b1bbf 1357 Error *local_err = NULL;
0f8d06f1 1358 bool no_aa32 = false;
ce5b1bbf 1359
c4487d76
PM		 1360 /* If we needed to query the host kernel for the CPU features
1361 * then it's possible that might have failed in the initfn, but
1362 * this is the first point where we can report it.
1363 */
1364 if (cpu->host_cpu_probe_failed) {
1365 if (!kvm_enabled()) {
1366 error_setg(errp, "The 'host' CPU type can only be used with KVM");
1367 } else {
1368 error_setg(errp, "Failed to retrieve host CPU features");
1369 }
1370 return;
1371 }
1372
95f87565
PM		 1373#ifndef CONFIG_USER_ONLY
1374 /* The NVIC and M-profile CPU are two halves of a single piece of
1375 * hardware; trying to use one without the other is a command line
1376 * error and will result in segfaults if not caught here.
1377 */
1378 if (arm_feature(env, ARM_FEATURE_M)) {
1379 if (!env->nvic) {
1380 error_setg(errp, "This board cannot be used with Cortex-M CPUs");
1381 return;
1382 }
1383 } else {
1384 if (env->nvic) {
1385 error_setg(errp, "This board can only be used with Cortex-M CPUs");
1386 return;
1387 }
1388 }
397cd31f 1389
96eec6b2
AJ		 1390 {
1391 uint64_t scale;
1392
1393 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
1394 if (!cpu->gt_cntfrq_hz) {
1395 error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz",
1396 cpu->gt_cntfrq_hz);
1397 return;
1398 }
1399 scale = gt_cntfrq_period_ns(cpu);
1400 } else {
1401 scale = GTIMER_SCALE;
1402 }
1403
1404 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1405 arm_gt_ptimer_cb, cpu);
1406 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1407 arm_gt_vtimer_cb, cpu);
1408 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1409 arm_gt_htimer_cb, cpu);
1410 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1411 arm_gt_stimer_cb, cpu);
8c94b071
RH		 1412 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
1413 arm_gt_hvtimer_cb, cpu);
96eec6b2 1414 }
95f87565
PM		 1415#endif
1416
ce5b1bbf
LV		 1417 cpu_exec_realizefn(cs, &local_err);
1418 if (local_err != NULL) {
1419 error_propagate(errp, local_err);
1420 return;
1421 }
14969266 1422
0df9142d
AJ		 1423 arm_cpu_finalize_features(cpu, &local_err);
1424 if (local_err != NULL) {
1425 error_propagate(errp, local_err);
1426 return;
1427 }
1428
97a28b0e
PM		 1429 if (arm_feature(env, ARM_FEATURE_AARCH64) &&
1430 cpu->has_vfp != cpu->has_neon) {
1431 /*
1432 * This is an architectural requirement for AArch64; AArch32 is
1433 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1434 */
1435 error_setg(errp,
1436 "AArch64 CPUs must have both VFP and Neon or neither");
1437 return;
1438 }
1439
1440 if (!cpu->has_vfp) {
1441 uint64_t t;
1442 uint32_t u;
1443
1444 unset_feature(env, ARM_FEATURE_VFP);
1445 unset_feature(env, ARM_FEATURE_VFP3);
1446 unset_feature(env, ARM_FEATURE_VFP4);
1447
1448 t = cpu->isar.id_aa64isar1;
1449 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
1450 cpu->isar.id_aa64isar1 = t;
1451
1452 t = cpu->isar.id_aa64pfr0;
1453 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
1454 cpu->isar.id_aa64pfr0 = t;
1455
1456 u = cpu->isar.id_isar6;
1457 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
1458 cpu->isar.id_isar6 = u;
1459
1460 u = cpu->isar.mvfr0;
1461 u = FIELD_DP32(u, MVFR0, FPSP, 0);
1462 u = FIELD_DP32(u, MVFR0, FPDP, 0);
1463 u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
1464 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0);
1465 u = FIELD_DP32(u, MVFR0, FPSQRT, 0);
1466 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
1467 u = FIELD_DP32(u, MVFR0, FPROUND, 0);
1468 cpu->isar.mvfr0 = u;
1469
1470 u = cpu->isar.mvfr1;
1471 u = FIELD_DP32(u, MVFR1, FPFTZ, 0);
1472 u = FIELD_DP32(u, MVFR1, FPDNAN, 0);
1473 u = FIELD_DP32(u, MVFR1, FPHP, 0);
1474 cpu->isar.mvfr1 = u;
1475
1476 u = cpu->isar.mvfr2;
1477 u = FIELD_DP32(u, MVFR2, FPMISC, 0);
1478 cpu->isar.mvfr2 = u;
1479 }
1480
1481 if (!cpu->has_neon) {
1482 uint64_t t;
1483 uint32_t u;
1484
1485 unset_feature(env, ARM_FEATURE_NEON);
1486
1487 t = cpu->isar.id_aa64isar0;
1488 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
1489 cpu->isar.id_aa64isar0 = t;
1490
1491 t = cpu->isar.id_aa64isar1;
1492 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
1493 cpu->isar.id_aa64isar1 = t;
1494
1495 t = cpu->isar.id_aa64pfr0;
1496 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
1497 cpu->isar.id_aa64pfr0 = t;
1498
1499 u = cpu->isar.id_isar5;
1500 u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
1501 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
1502 cpu->isar.id_isar5 = u;
1503
1504 u = cpu->isar.id_isar6;
1505 u = FIELD_DP32(u, ID_ISAR6, DP, 0);
1506 u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
1507 cpu->isar.id_isar6 = u;
1508
1509 u = cpu->isar.mvfr1;
1510 u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
1511 u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
1512 u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
1513 u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
1514 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
1515 cpu->isar.mvfr1 = u;
1516
1517 u = cpu->isar.mvfr2;
1518 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
1519 cpu->isar.mvfr2 = u;
1520 }
1521
1522 if (!cpu->has_neon && !cpu->has_vfp) {
1523 uint64_t t;
1524 uint32_t u;
1525
1526 t = cpu->isar.id_aa64isar0;
1527 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0);
1528 cpu->isar.id_aa64isar0 = t;
1529
1530 t = cpu->isar.id_aa64isar1;
1531 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0);
1532 cpu->isar.id_aa64isar1 = t;
1533
1534 u = cpu->isar.mvfr0;
1535 u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
1536 cpu->isar.mvfr0 = u;
1537 }
1538
ea90db0a
PM		 1539 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) {
1540 uint32_t u;
1541
1542 unset_feature(env, ARM_FEATURE_THUMB_DSP);
1543
1544 u = cpu->isar.id_isar1;
1545 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1);
1546 cpu->isar.id_isar1 = u;
1547
1548 u = cpu->isar.id_isar2;
1549 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1);
1550 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1);
1551 cpu->isar.id_isar2 = u;
1552
1553 u = cpu->isar.id_isar3;
1554 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1);
1555 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0);
1556 cpu->isar.id_isar3 = u;
1557 }
1558
581be094 1559 /* Some features automatically imply others: */
81e69fb0 1560 if (arm_feature(env, ARM_FEATURE_V8)) {
5256df88
RH		 1561 if (arm_feature(env, ARM_FEATURE_M)) {
1562 set_feature(env, ARM_FEATURE_V7);
1563 } else {
1564 set_feature(env, ARM_FEATURE_V7VE);
1565 }
5110e683 1566 }
0f8d06f1
RH		 1567
1568 /*
1569 * There exist AArch64 cpus without AArch32 support. When KVM
1570 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1571 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
8f4821d7
PM		 1572 * As a general principle, we also do not make ID register
1573 * consistency checks anywhere unless using TCG, because only
1574 * for TCG would a consistency-check failure be a QEMU bug.
0f8d06f1
RH		 1575 */
1576 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1577 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
1578 }
1579
5110e683
AL		 1580 if (arm_feature(env, ARM_FEATURE_V7VE)) {
1581 /* v7 Virtualization Extensions. In real hardware this implies
1582 * EL2 and also the presence of the Security Extensions.
1583 * For QEMU, for backwards-compatibility we implement some
1584 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1585 * include the various other features that V7VE implies.
1586 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1587 * Security Extensions is ARM_FEATURE_EL3.
1588 */
873b73c0
PM		 1589 assert(!tcg_enabled() || no_aa32 ||
1590 cpu_isar_feature(aa32_arm_div, cpu));
81e69fb0 1591 set_feature(env, ARM_FEATURE_LPAE);
5110e683 1592 set_feature(env, ARM_FEATURE_V7);
81e69fb0 1593 }
581be094
PM		 1594 if (arm_feature(env, ARM_FEATURE_V7)) {
1595 set_feature(env, ARM_FEATURE_VAPA);
1596 set_feature(env, ARM_FEATURE_THUMB2);
81bdde9d 1597 set_feature(env, ARM_FEATURE_MPIDR);
581be094
PM		 1598 if (!arm_feature(env, ARM_FEATURE_M)) {
1599 set_feature(env, ARM_FEATURE_V6K);
1600 } else {
1601 set_feature(env, ARM_FEATURE_V6);
1602 }
91db4642
CLG		 1603
1604 /* Always define VBAR for V7 CPUs even if it doesn't exist in
1605 * non-EL3 configs. This is needed by some legacy boards.
1606 */
1607 set_feature(env, ARM_FEATURE_VBAR);
581be094
PM		 1608 }
1609 if (arm_feature(env, ARM_FEATURE_V6K)) {
1610 set_feature(env, ARM_FEATURE_V6);
1611 set_feature(env, ARM_FEATURE_MVFR);
1612 }
1613 if (arm_feature(env, ARM_FEATURE_V6)) {
1614 set_feature(env, ARM_FEATURE_V5);
1615 if (!arm_feature(env, ARM_FEATURE_M)) {
873b73c0
PM		 1616 assert(!tcg_enabled() || no_aa32 ||
1617 cpu_isar_feature(aa32_jazelle, cpu));
581be094
PM		 1618 set_feature(env, ARM_FEATURE_AUXCR);
1619 }
1620 }
1621 if (arm_feature(env, ARM_FEATURE_V5)) {
1622 set_feature(env, ARM_FEATURE_V4T);
1623 }
de9b05b8 1624 if (arm_feature(env, ARM_FEATURE_LPAE)) {
bdcc150d 1625 set_feature(env, ARM_FEATURE_V7MP);
de9b05b8
PM		 1626 set_feature(env, ARM_FEATURE_PXN);
1627 }
f318cec6
PM		 1628 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
1629 set_feature(env, ARM_FEATURE_CBAR);
1630 }
62b44f05
AR		 1631 if (arm_feature(env, ARM_FEATURE_THUMB2) &&
1632 !arm_feature(env, ARM_FEATURE_M)) {
1633 set_feature(env, ARM_FEATURE_THUMB_DSP);
1634 }
2ceb98c0 1635
ea7ac69d
PM		 1636 /*
1637 * We rely on no XScale CPU having VFP so we can use the same bits in the
1638 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1639 */
1640 assert(!(arm_feature(env, ARM_FEATURE_VFP) &&
1641 arm_feature(env, ARM_FEATURE_XSCALE)));
1642
e97da98f
PM		 1643 if (arm_feature(env, ARM_FEATURE_V7) &&
1644 !arm_feature(env, ARM_FEATURE_M) &&
452a0955 1645 !arm_feature(env, ARM_FEATURE_PMSA)) {
e97da98f
PM		 1646 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1647 * can use 4K pages.
1648 */
1649 pagebits = 12;
1650 } else {
1651 /* For CPUs which might have tiny 1K pages, or which have an
1652 * MPU and might have small region sizes, stick with 1K pages.
1653 */
1654 pagebits = 10;
1655 }
1656 if (!set_preferred_target_page_bits(pagebits)) {
1657 /* This can only ever happen for hotplugging a CPU, or if
1658 * the board code incorrectly creates a CPU which it has
1659 * promised via minimum_page_size that it will not.
1660 */
1661 error_setg(errp, "This CPU requires a smaller page size than the "
1662 "system is using");
1663 return;
1664 }
1665
ce5b1bbf
LV		 1666 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1667 * We don't support setting cluster ID ([16..23]) (known as Aff2
1668 * in later ARM ARM versions), or any of the higher affinity level fields,
1669 * so these bits always RAZ.
1670 */
1671 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
46de5913
IM		 1672 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index,
1673 ARM_DEFAULT_CPUS_PER_CLUSTER);
ce5b1bbf
LV		 1674 }
1675
68e0a40a
AP		 1676 if (cpu->reset_hivecs) {
1677 cpu->reset_sctlr |= (1 << 13);
1678 }
1679
3a062d57
JB		 1680 if (cpu->cfgend) {
1681 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1682 cpu->reset_sctlr |= SCTLR_EE;
1683 } else {
1684 cpu->reset_sctlr |= SCTLR_B;
1685 }
1686 }
1687
51942aee
GB		 1688 if (!cpu->has_el3) {
1689 /* If the has_el3 CPU property is disabled then we need to disable the
1690 * feature.
1691 */
1692 unset_feature(env, ARM_FEATURE_EL3);
1693
1694 /* Disable the security extension feature bits in the processor feature
3d5c84ff 1695 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
51942aee
GB		 1696 */
1697 cpu->id_pfr1 &= ~0xf0;
47576b94 1698 cpu->isar.id_aa64pfr0 &= ~0xf000;
51942aee
GB		 1699 }
1700
c25bd18a
PM		 1701 if (!cpu->has_el2) {
1702 unset_feature(env, ARM_FEATURE_EL2);
1703 }
1704
d6f02ce3 1705 if (!cpu->has_pmu) {
929e754d 1706 unset_feature(env, ARM_FEATURE_PMU);
57a4a11b
AL		 1707 }
1708 if (arm_feature(env, ARM_FEATURE_PMU)) {
bf8d0969 1709 pmu_init(cpu);
57a4a11b
AL		 1710
1711 if (!kvm_enabled()) {
1712 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
1713 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
1714 }
4e7beb0c
AL		 1715
1716#ifndef CONFIG_USER_ONLY
1717 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
1718 cpu);
1719#endif
57a4a11b 1720 } else {
ceb2744b 1721 cpu->id_aa64dfr0 = FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
d52c061e 1722 cpu->id_dfr0 = FIELD_DP32(cpu->id_dfr0, ID_DFR0, PERFMON, 0);
57a4a11b
AL		 1723 cpu->pmceid0 = 0;
1724 cpu->pmceid1 = 0;
929e754d
WH		 1725 }
1726
3c2f7bb3
PM		 1727 if (!arm_feature(env, ARM_FEATURE_EL2)) {
1728 /* Disable the hypervisor feature bits in the processor feature
1729 * registers if we don't have EL2. These are id_pfr1[15:12] and
1730 * id_aa64pfr0_el1[11:8].
1731 */
47576b94 1732 cpu->isar.id_aa64pfr0 &= ~0xf00;
3c2f7bb3
PM		 1733 cpu->id_pfr1 &= ~0xf000;
1734 }
1735
f50cd314
PM		 1736 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1737 * to false or by setting pmsav7-dregion to 0.
1738 */
8f325f56 1739 if (!cpu->has_mpu) {
f50cd314
PM		 1740 cpu->pmsav7_dregion = 0;
1741 }
1742 if (cpu->pmsav7_dregion == 0) {
1743 cpu->has_mpu = false;
8f325f56
PC		 1744 }
1745
452a0955 1746 if (arm_feature(env, ARM_FEATURE_PMSA) &&
3281af81
PC		 1747 arm_feature(env, ARM_FEATURE_V7)) {
1748 uint32_t nr = cpu->pmsav7_dregion;
1749
1750 if (nr > 0xff) {
9af9e0fe 1751 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
3281af81
PC		 1752 return;
1753 }
6cb0b013
PC		 1754
1755 if (nr) {
0e1a46bb
PM		 1756 if (arm_feature(env, ARM_FEATURE_V8)) {
1757 /* PMSAv8 */
62c58ee0
PM		 1758 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
1759 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
1760 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1761 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
1762 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
1763 }
0e1a46bb
PM		 1764 } else {
1765 env->pmsav7.drbar = g_new0(uint32_t, nr);
1766 env->pmsav7.drsr = g_new0(uint32_t, nr);
1767 env->pmsav7.dracr = g_new0(uint32_t, nr);
1768 }
6cb0b013 1769 }
3281af81
PC		 1770 }
1771
9901c576
PM		 1772 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1773 uint32_t nr = cpu->sau_sregion;
1774
1775 if (nr > 0xff) {
1776 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
1777 return;
1778 }
1779
1780 if (nr) {
1781 env->sau.rbar = g_new0(uint32_t, nr);
1782 env->sau.rlar = g_new0(uint32_t, nr);
1783 }
1784 }
1785
91db4642
CLG		 1786 if (arm_feature(env, ARM_FEATURE_EL3)) {
1787 set_feature(env, ARM_FEATURE_VBAR);
1788 }
1789
2ceb98c0 1790 register_cp_regs_for_features(cpu);
14969266
AF		 1791 arm_cpu_register_gdb_regs_for_features(cpu);
1792
721fae12
PM		 1793 init_cpreg_list(cpu);
1794
9e273ef2 1795#ifndef CONFIG_USER_ONLY
cc7d44c2
LX		 1796 MachineState *ms = MACHINE(qdev_get_machine());
1797 unsigned int smp_cpus = ms->smp.cpus;
1798
1d2091bc 1799 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1d2091bc
PM		 1800 cs->num_ases = 2;
1801
9e273ef2
PM		 1802 if (!cpu->secure_memory) {
1803 cpu->secure_memory = cs->memory;
1804 }
80ceb07a
PX		 1805 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
1806 cpu->secure_memory);
1d2091bc
PM		 1807 } else {
1808 cs->num_ases = 1;
9e273ef2 1809 }
80ceb07a 1810 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
f9a69711
AF		 1811
1812 /* No core_count specified, default to smp_cpus. */
1813 if (cpu->core_count == -1) {
1814 cpu->core_count = smp_cpus;
1815 }
9e273ef2
PM		 1816#endif
1817
14a10fc3 1818 qemu_init_vcpu(cs);
00d0f7cb 1819 cpu_reset(cs);
14969266
AF		 1820
1821 acc->parent_realize(dev, errp);
581be094
PM		 1822}
1823
5900d6b2
AF		 1824static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
1825{
1826 ObjectClass *oc;
51492fd1 1827 char *typename;
fb8d6c24 1828 char **cpuname;
a0032cc5 1829 const char *cpunamestr;
5900d6b2 1830
fb8d6c24 1831 cpuname = g_strsplit(cpu_model, ",", 1);
a0032cc5
PM		 1832 cpunamestr = cpuname[0];
1833#ifdef CONFIG_USER_ONLY
1834 /* For backwards compatibility usermode emulation allows "-cpu any",
1835 * which has the same semantics as "-cpu max".
1836 */
1837 if (!strcmp(cpunamestr, "any")) {
1838 cpunamestr = "max";
1839 }
1840#endif
1841 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
51492fd1 1842 oc = object_class_by_name(typename);
fb8d6c24 1843 g_strfreev(cpuname);
51492fd1 1844 g_free(typename);
245fb54d
AF		 1845 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
1846 object_class_is_abstract(oc)) {
5900d6b2
AF		 1847 return NULL;
1848 }
1849 return oc;
1850}
1851
15ee776b
PM		 1852/* CPU models. These are not needed for the AArch64 linux-user build. */
1853#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1854
777dc784
PM		 1855static void arm926_initfn(Object *obj)
1856{
1857 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 1858
1859 cpu->dtb_compatible = "arm,arm926";
581be094
PM		 1860 set_feature(&cpu->env, ARM_FEATURE_V5);
1861 set_feature(&cpu->env, ARM_FEATURE_VFP);
c4804214
PM		 1862 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1863 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
b2d06f96 1864 cpu->midr = 0x41069265;
325b3cef 1865 cpu->reset_fpsid = 0x41011090;
64e1671f 1866 cpu->ctr = 0x1dd20d2;
0ca7e01c 1867 cpu->reset_sctlr = 0x00090078;
09cbd501
RH		 1868
1869 /*
1870 * ARMv5 does not have the ID_ISAR registers, but we can still
1871 * set the field to indicate Jazelle support within QEMU.
1872 */
1873 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
cb7cef8b
PM		 1874 /*
1875 * Similarly, we need to set MVFR0 fields to enable double precision
1876 * and short vector support even though ARMv5 doesn't have this register.
1877 */
1878 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
1879 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
777dc784
PM		 1880}
1881
1882static void arm946_initfn(Object *obj)
1883{
1884 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 1885
1886 cpu->dtb_compatible = "arm,arm946";
581be094 1887 set_feature(&cpu->env, ARM_FEATURE_V5);
452a0955 1888 set_feature(&cpu->env, ARM_FEATURE_PMSA);
c4804214 1889 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
b2d06f96 1890 cpu->midr = 0x41059461;
64e1671f 1891 cpu->ctr = 0x0f004006;
0ca7e01c 1892 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 1893}
1894
1895static void arm1026_initfn(Object *obj)
1896{
1897 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 1898
1899 cpu->dtb_compatible = "arm,arm1026";
581be094
PM		 1900 set_feature(&cpu->env, ARM_FEATURE_V5);
1901 set_feature(&cpu->env, ARM_FEATURE_VFP);
1902 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
c4804214
PM		 1903 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1904 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
b2d06f96 1905 cpu->midr = 0x4106a262;
325b3cef 1906 cpu->reset_fpsid = 0x410110a0;
64e1671f 1907 cpu->ctr = 0x1dd20d2;
0ca7e01c 1908 cpu->reset_sctlr = 0x00090078;
2771db27 1909 cpu->reset_auxcr = 1;
09cbd501
RH		 1910
1911 /*
1912 * ARMv5 does not have the ID_ISAR registers, but we can still
1913 * set the field to indicate Jazelle support within QEMU.
1914 */
1915 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
cb7cef8b
PM		 1916 /*
1917 * Similarly, we need to set MVFR0 fields to enable double precision
1918 * and short vector support even though ARMv5 doesn't have this register.
1919 */
1920 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
1921 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
09cbd501 1922
06d76f31
PM		 1923 {
1924 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
1925 ARMCPRegInfo ifar = {
1926 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
1927 .access = PL1_RW,
b848ce2b 1928 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
06d76f31
PM		 1929 .resetvalue = 0
1930 };
1931 define_one_arm_cp_reg(cpu, &ifar);
1932 }
777dc784
PM		 1933}
1934
1935static void arm1136_r2_initfn(Object *obj)
1936{
1937 ARMCPU *cpu = ARM_CPU(obj);
2e4d7e3e
PM		 1938 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1939 * older core than plain "arm1136". In particular this does not
1940 * have the v6K features.
1941 * These ID register values are correct for 1136 but may be wrong
1942 * for 1136_r2 (in particular r0p2 does not actually implement most
1943 * of the ID registers).
1944 */
54d3e3f5
PM		 1945
1946 cpu->dtb_compatible = "arm,arm1136";
581be094
PM		 1947 set_feature(&cpu->env, ARM_FEATURE_V6);
1948 set_feature(&cpu->env, ARM_FEATURE_VFP);
c4804214
PM		 1949 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1950 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1951 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
b2d06f96 1952 cpu->midr = 0x4107b362;
325b3cef 1953 cpu->reset_fpsid = 0x410120b4;
47576b94
RH		 1954 cpu->isar.mvfr0 = 0x11111111;
1955 cpu->isar.mvfr1 = 0x00000000;
64e1671f 1956 cpu->ctr = 0x1dd20d2;
0ca7e01c 1957 cpu->reset_sctlr = 0x00050078;
2e4d7e3e
PM		 1958 cpu->id_pfr0 = 0x111;
1959 cpu->id_pfr1 = 0x1;
1960 cpu->id_dfr0 = 0x2;
1961 cpu->id_afr0 = 0x3;
1962 cpu->id_mmfr0 = 0x01130003;
1963 cpu->id_mmfr1 = 0x10030302;
1964 cpu->id_mmfr2 = 0x01222110;
47576b94
RH		 1965 cpu->isar.id_isar0 = 0x00140011;
1966 cpu->isar.id_isar1 = 0x12002111;
1967 cpu->isar.id_isar2 = 0x11231111;
1968 cpu->isar.id_isar3 = 0x01102131;
1969 cpu->isar.id_isar4 = 0x141;
2771db27 1970 cpu->reset_auxcr = 7;
777dc784
PM		 1971}
1972
1973static void arm1136_initfn(Object *obj)
1974{
1975 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 1976
1977 cpu->dtb_compatible = "arm,arm1136";
581be094
PM		 1978 set_feature(&cpu->env, ARM_FEATURE_V6K);
1979 set_feature(&cpu->env, ARM_FEATURE_V6);
1980 set_feature(&cpu->env, ARM_FEATURE_VFP);
c4804214
PM		 1981 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1982 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1983 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
b2d06f96 1984 cpu->midr = 0x4117b363;
325b3cef 1985 cpu->reset_fpsid = 0x410120b4;
47576b94
RH		 1986 cpu->isar.mvfr0 = 0x11111111;
1987 cpu->isar.mvfr1 = 0x00000000;
64e1671f 1988 cpu->ctr = 0x1dd20d2;
0ca7e01c 1989 cpu->reset_sctlr = 0x00050078;
2e4d7e3e
PM		 1990 cpu->id_pfr0 = 0x111;
1991 cpu->id_pfr1 = 0x1;
1992 cpu->id_dfr0 = 0x2;
1993 cpu->id_afr0 = 0x3;
1994 cpu->id_mmfr0 = 0x01130003;
1995 cpu->id_mmfr1 = 0x10030302;
1996 cpu->id_mmfr2 = 0x01222110;
47576b94
RH		 1997 cpu->isar.id_isar0 = 0x00140011;
1998 cpu->isar.id_isar1 = 0x12002111;
1999 cpu->isar.id_isar2 = 0x11231111;
2000 cpu->isar.id_isar3 = 0x01102131;
2001 cpu->isar.id_isar4 = 0x141;
2771db27 2002 cpu->reset_auxcr = 7;
777dc784
PM		 2003}
2004
2005static void arm1176_initfn(Object *obj)
2006{
2007 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2008
2009 cpu->dtb_compatible = "arm,arm1176";
581be094
PM		 2010 set_feature(&cpu->env, ARM_FEATURE_V6K);
2011 set_feature(&cpu->env, ARM_FEATURE_VFP);
2012 set_feature(&cpu->env, ARM_FEATURE_VAPA);
c4804214
PM		 2013 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2014 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
2015 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
c0ccb02d 2016 set_feature(&cpu->env, ARM_FEATURE_EL3);
b2d06f96 2017 cpu->midr = 0x410fb767;
325b3cef 2018 cpu->reset_fpsid = 0x410120b5;
47576b94
RH		 2019 cpu->isar.mvfr0 = 0x11111111;
2020 cpu->isar.mvfr1 = 0x00000000;
64e1671f 2021 cpu->ctr = 0x1dd20d2;
0ca7e01c 2022 cpu->reset_sctlr = 0x00050078;
2e4d7e3e
PM		 2023 cpu->id_pfr0 = 0x111;
2024 cpu->id_pfr1 = 0x11;
2025 cpu->id_dfr0 = 0x33;
2026 cpu->id_afr0 = 0;
2027 cpu->id_mmfr0 = 0x01130003;
2028 cpu->id_mmfr1 = 0x10030302;
2029 cpu->id_mmfr2 = 0x01222100;
47576b94
RH		 2030 cpu->isar.id_isar0 = 0x0140011;
2031 cpu->isar.id_isar1 = 0x12002111;
2032 cpu->isar.id_isar2 = 0x11231121;
2033 cpu->isar.id_isar3 = 0x01102131;
2034 cpu->isar.id_isar4 = 0x01141;
2771db27 2035 cpu->reset_auxcr = 7;
777dc784
PM		 2036}
2037
2038static void arm11mpcore_initfn(Object *obj)
2039{
2040 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2041
2042 cpu->dtb_compatible = "arm,arm11mpcore";
581be094
PM		 2043 set_feature(&cpu->env, ARM_FEATURE_V6K);
2044 set_feature(&cpu->env, ARM_FEATURE_VFP);
2045 set_feature(&cpu->env, ARM_FEATURE_VAPA);
81bdde9d 2046 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
c4804214 2047 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
b2d06f96 2048 cpu->midr = 0x410fb022;
325b3cef 2049 cpu->reset_fpsid = 0x410120b4;
47576b94
RH		 2050 cpu->isar.mvfr0 = 0x11111111;
2051 cpu->isar.mvfr1 = 0x00000000;
200bf596 2052 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
2e4d7e3e
PM		 2053 cpu->id_pfr0 = 0x111;
2054 cpu->id_pfr1 = 0x1;
2055 cpu->id_dfr0 = 0;
2056 cpu->id_afr0 = 0x2;
2057 cpu->id_mmfr0 = 0x01100103;
2058 cpu->id_mmfr1 = 0x10020302;
2059 cpu->id_mmfr2 = 0x01222000;
47576b94
RH		 2060 cpu->isar.id_isar0 = 0x00100011;
2061 cpu->isar.id_isar1 = 0x12002111;
2062 cpu->isar.id_isar2 = 0x11221011;
2063 cpu->isar.id_isar3 = 0x01102131;
2064 cpu->isar.id_isar4 = 0x141;
2771db27 2065 cpu->reset_auxcr = 1;
777dc784
PM		 2066}
2067
191776b9
SH		 2068static void cortex_m0_initfn(Object *obj)
2069{
2070 ARMCPU *cpu = ARM_CPU(obj);
2071 set_feature(&cpu->env, ARM_FEATURE_V6);
2072 set_feature(&cpu->env, ARM_FEATURE_M);
2073
2074 cpu->midr = 0x410cc200;
2075}
2076
777dc784
PM		 2077static void cortex_m3_initfn(Object *obj)
2078{
2079 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 2080 set_feature(&cpu->env, ARM_FEATURE_V7);
2081 set_feature(&cpu->env, ARM_FEATURE_M);
cc2ae7c9 2082 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
b2d06f96 2083 cpu->midr = 0x410fc231;
8d92e26b 2084 cpu->pmsav7_dregion = 8;
5a53e2c1
PM		 2085 cpu->id_pfr0 = 0x00000030;
2086 cpu->id_pfr1 = 0x00000200;
2087 cpu->id_dfr0 = 0x00100000;
2088 cpu->id_afr0 = 0x00000000;
2089 cpu->id_mmfr0 = 0x00000030;
2090 cpu->id_mmfr1 = 0x00000000;
2091 cpu->id_mmfr2 = 0x00000000;
2092 cpu->id_mmfr3 = 0x00000000;
47576b94
RH		 2093 cpu->isar.id_isar0 = 0x01141110;
2094 cpu->isar.id_isar1 = 0x02111000;
2095 cpu->isar.id_isar2 = 0x21112231;
2096 cpu->isar.id_isar3 = 0x01111110;
2097 cpu->isar.id_isar4 = 0x01310102;
2098 cpu->isar.id_isar5 = 0x00000000;
2099 cpu->isar.id_isar6 = 0x00000000;
777dc784
PM		 2100}
2101
ba890a9b
AR		 2102static void cortex_m4_initfn(Object *obj)
2103{
2104 ARMCPU *cpu = ARM_CPU(obj);
2105
2106 set_feature(&cpu->env, ARM_FEATURE_V7);
2107 set_feature(&cpu->env, ARM_FEATURE_M);
cc2ae7c9 2108 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
ba890a9b 2109 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
14fd0c31 2110 set_feature(&cpu->env, ARM_FEATURE_VFP4);
ba890a9b 2111 cpu->midr = 0x410fc240; /* r0p0 */
8d92e26b 2112 cpu->pmsav7_dregion = 8;
14fd0c31
PM		 2113 cpu->isar.mvfr0 = 0x10110021;
2114 cpu->isar.mvfr1 = 0x11000011;
2115 cpu->isar.mvfr2 = 0x00000000;
5a53e2c1
PM		 2116 cpu->id_pfr0 = 0x00000030;
2117 cpu->id_pfr1 = 0x00000200;
2118 cpu->id_dfr0 = 0x00100000;
2119 cpu->id_afr0 = 0x00000000;
2120 cpu->id_mmfr0 = 0x00000030;
2121 cpu->id_mmfr1 = 0x00000000;
2122 cpu->id_mmfr2 = 0x00000000;
2123 cpu->id_mmfr3 = 0x00000000;
47576b94
RH		 2124 cpu->isar.id_isar0 = 0x01141110;
2125 cpu->isar.id_isar1 = 0x02111000;
2126 cpu->isar.id_isar2 = 0x21112231;
2127 cpu->isar.id_isar3 = 0x01111110;
2128 cpu->isar.id_isar4 = 0x01310102;
2129 cpu->isar.id_isar5 = 0x00000000;
2130 cpu->isar.id_isar6 = 0x00000000;
ba890a9b 2131}
9901c576 2132
cf7beda5
CL		 2133static void cortex_m7_initfn(Object *obj)
2134{
2135 ARMCPU *cpu = ARM_CPU(obj);
2136
2137 set_feature(&cpu->env, ARM_FEATURE_V7);
2138 set_feature(&cpu->env, ARM_FEATURE_M);
2139 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
2140 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
2141 set_feature(&cpu->env, ARM_FEATURE_VFP4);
2142 cpu->midr = 0x411fc272; /* r1p2 */
2143 cpu->pmsav7_dregion = 8;
2144 cpu->isar.mvfr0 = 0x10110221;
2145 cpu->isar.mvfr1 = 0x12000011;
2146 cpu->isar.mvfr2 = 0x00000040;
2147 cpu->id_pfr0 = 0x00000030;
2148 cpu->id_pfr1 = 0x00000200;
2149 cpu->id_dfr0 = 0x00100000;
2150 cpu->id_afr0 = 0x00000000;
2151 cpu->id_mmfr0 = 0x00100030;
2152 cpu->id_mmfr1 = 0x00000000;
2153 cpu->id_mmfr2 = 0x01000000;
2154 cpu->id_mmfr3 = 0x00000000;
2155 cpu->isar.id_isar0 = 0x01101110;
2156 cpu->isar.id_isar1 = 0x02112000;
2157 cpu->isar.id_isar2 = 0x20232231;
2158 cpu->isar.id_isar3 = 0x01111131;
2159 cpu->isar.id_isar4 = 0x01310132;
2160 cpu->isar.id_isar5 = 0x00000000;
2161 cpu->isar.id_isar6 = 0x00000000;
2162}
2163
c7b26382
PM		 2164static void cortex_m33_initfn(Object *obj)
2165{
2166 ARMCPU *cpu = ARM_CPU(obj);
2167
2168 set_feature(&cpu->env, ARM_FEATURE_V8);
2169 set_feature(&cpu->env, ARM_FEATURE_M);
cc2ae7c9 2170 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
c7b26382
PM		 2171 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
2172 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
14fd0c31 2173 set_feature(&cpu->env, ARM_FEATURE_VFP4);
c7b26382
PM		 2174 cpu->midr = 0x410fd213; /* r0p3 */
2175 cpu->pmsav7_dregion = 16;
2176 cpu->sau_sregion = 8;
14fd0c31
PM		 2177 cpu->isar.mvfr0 = 0x10110021;
2178 cpu->isar.mvfr1 = 0x11000011;
2179 cpu->isar.mvfr2 = 0x00000040;
c7b26382
PM		 2180 cpu->id_pfr0 = 0x00000030;
2181 cpu->id_pfr1 = 0x00000210;
2182 cpu->id_dfr0 = 0x00200000;
2183 cpu->id_afr0 = 0x00000000;
2184 cpu->id_mmfr0 = 0x00101F40;
2185 cpu->id_mmfr1 = 0x00000000;
2186 cpu->id_mmfr2 = 0x01000000;
2187 cpu->id_mmfr3 = 0x00000000;
47576b94
RH		 2188 cpu->isar.id_isar0 = 0x01101110;
2189 cpu->isar.id_isar1 = 0x02212000;
2190 cpu->isar.id_isar2 = 0x20232232;
2191 cpu->isar.id_isar3 = 0x01111131;
2192 cpu->isar.id_isar4 = 0x01310132;
2193 cpu->isar.id_isar5 = 0x00000000;
2194 cpu->isar.id_isar6 = 0x00000000;
c7b26382
PM		 2195 cpu->clidr = 0x00000000;
2196 cpu->ctr = 0x8000c000;
2197}
2198
e6f010cc
AF		 2199static void arm_v7m_class_init(ObjectClass *oc, void *data)
2200{
51e5ef45 2201 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
e6f010cc
AF		 2202 CPUClass *cc = CPU_CLASS(oc);
2203
51e5ef45 2204 acc->info = data;
b5c633c5 2205#ifndef CONFIG_USER_ONLY
e6f010cc
AF		 2206 cc->do_interrupt = arm_v7m_cpu_do_interrupt;
2207#endif
b5c633c5
PM		 2208
2209 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
e6f010cc
AF		 2210}
2211
d6a6b13e
PC		 2212static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
2213 /* Dummy the TCM region regs for the moment */
2214 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
2215 .access = PL1_RW, .type = ARM_CP_CONST },
2216 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
2217 .access = PL1_RW, .type = ARM_CP_CONST },
95e9a242
LM		 2218 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
2219 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
d6a6b13e
PC		 2220 REGINFO_SENTINEL
2221};
2222
2223static void cortex_r5_initfn(Object *obj)
2224{
2225 ARMCPU *cpu = ARM_CPU(obj);
2226
2227 set_feature(&cpu->env, ARM_FEATURE_V7);
d6a6b13e 2228 set_feature(&cpu->env, ARM_FEATURE_V7MP);
452a0955 2229 set_feature(&cpu->env, ARM_FEATURE_PMSA);
90f67158 2230 set_feature(&cpu->env, ARM_FEATURE_PMU);
d6a6b13e
PC		 2231 cpu->midr = 0x411fc153; /* r1p3 */
2232 cpu->id_pfr0 = 0x0131;
2233 cpu->id_pfr1 = 0x001;
2234 cpu->id_dfr0 = 0x010400;
2235 cpu->id_afr0 = 0x0;
2236 cpu->id_mmfr0 = 0x0210030;
2237 cpu->id_mmfr1 = 0x00000000;
2238 cpu->id_mmfr2 = 0x01200000;
2239 cpu->id_mmfr3 = 0x0211;
47576b94
RH		 2240 cpu->isar.id_isar0 = 0x02101111;
2241 cpu->isar.id_isar1 = 0x13112111;
2242 cpu->isar.id_isar2 = 0x21232141;
2243 cpu->isar.id_isar3 = 0x01112131;
2244 cpu->isar.id_isar4 = 0x0010142;
2245 cpu->isar.id_isar5 = 0x0;
2246 cpu->isar.id_isar6 = 0x0;
d6a6b13e 2247 cpu->mp_is_up = true;
8d92e26b 2248 cpu->pmsav7_dregion = 16;
d6a6b13e
PC		 2249 define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
2250}
2251
ebac5458
EI		 2252static void cortex_r5f_initfn(Object *obj)
2253{
2254 ARMCPU *cpu = ARM_CPU(obj);
2255
2256 cortex_r5_initfn(obj);
2257 set_feature(&cpu->env, ARM_FEATURE_VFP3);
3de79d33
PM		 2258 cpu->isar.mvfr0 = 0x10110221;
2259 cpu->isar.mvfr1 = 0x00000011;
ebac5458
EI		 2260}
2261
34f90529
PM		 2262static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
2263 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
2264 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2265 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
2266 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2267 REGINFO_SENTINEL
2268};
2269
777dc784
PM		 2270static void cortex_a8_initfn(Object *obj)
2271{
2272 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2273
2274 cpu->dtb_compatible = "arm,cortex-a8";
581be094
PM		 2275 set_feature(&cpu->env, ARM_FEATURE_V7);
2276 set_feature(&cpu->env, ARM_FEATURE_VFP3);
2277 set_feature(&cpu->env, ARM_FEATURE_NEON);
2278 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
c4804214 2279 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
c0ccb02d 2280 set_feature(&cpu->env, ARM_FEATURE_EL3);
b2d06f96 2281 cpu->midr = 0x410fc080;
325b3cef 2282 cpu->reset_fpsid = 0x410330c0;
47576b94
RH		 2283 cpu->isar.mvfr0 = 0x11110222;
2284 cpu->isar.mvfr1 = 0x00011111;
64e1671f 2285 cpu->ctr = 0x82048004;
0ca7e01c 2286 cpu->reset_sctlr = 0x00c50078;
2e4d7e3e
PM		 2287 cpu->id_pfr0 = 0x1031;
2288 cpu->id_pfr1 = 0x11;
2289 cpu->id_dfr0 = 0x400;
2290 cpu->id_afr0 = 0;
2291 cpu->id_mmfr0 = 0x31100003;
2292 cpu->id_mmfr1 = 0x20000000;
2293 cpu->id_mmfr2 = 0x01202000;
2294 cpu->id_mmfr3 = 0x11;
47576b94
RH		 2295 cpu->isar.id_isar0 = 0x00101111;
2296 cpu->isar.id_isar1 = 0x12112111;
2297 cpu->isar.id_isar2 = 0x21232031;
2298 cpu->isar.id_isar3 = 0x11112131;
2299 cpu->isar.id_isar4 = 0x00111142;
48eb3ae6 2300 cpu->dbgdidr = 0x15141000;
85df3786
PM		 2301 cpu->clidr = (1 << 27) | (2 << 24) | 3;
2302 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
2303 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
2304 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
2771db27 2305 cpu->reset_auxcr = 2;
34f90529 2306 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
777dc784
PM		 2307}
2308
1047b9d7
PM		 2309static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
2310 /* power_control should be set to maximum latency. Again,
2311 * default to 0 and set by private hook
2312 */
2313 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
2314 .access = PL1_RW, .resetvalue = 0,
2315 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
2316 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
2317 .access = PL1_RW, .resetvalue = 0,
2318 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
2319 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
2320 .access = PL1_RW, .resetvalue = 0,
2321 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
2322 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
2323 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2324 /* TLB lockdown control */
2325 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
2326 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
2327 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
2328 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
2329 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
2330 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2331 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
2332 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2333 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
2334 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2335 REGINFO_SENTINEL
2336};
2337
777dc784
PM		 2338static void cortex_a9_initfn(Object *obj)
2339{
2340 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2341
2342 cpu->dtb_compatible = "arm,cortex-a9";
581be094
PM		 2343 set_feature(&cpu->env, ARM_FEATURE_V7);
2344 set_feature(&cpu->env, ARM_FEATURE_VFP3);
581be094
PM		 2345 set_feature(&cpu->env, ARM_FEATURE_NEON);
2346 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
c0ccb02d 2347 set_feature(&cpu->env, ARM_FEATURE_EL3);
581be094
PM		 2348 /* Note that A9 supports the MP extensions even for
2349 * A9UP and single-core A9MP (which are both different
2350 * and valid configurations; we don't model A9UP).
2351 */
2352 set_feature(&cpu->env, ARM_FEATURE_V7MP);
d8ba780b 2353 set_feature(&cpu->env, ARM_FEATURE_CBAR);
b2d06f96 2354 cpu->midr = 0x410fc090;
325b3cef 2355 cpu->reset_fpsid = 0x41033090;
47576b94
RH		 2356 cpu->isar.mvfr0 = 0x11110222;
2357 cpu->isar.mvfr1 = 0x01111111;
64e1671f 2358 cpu->ctr = 0x80038003;
0ca7e01c 2359 cpu->reset_sctlr = 0x00c50078;
2e4d7e3e
PM		 2360 cpu->id_pfr0 = 0x1031;
2361 cpu->id_pfr1 = 0x11;
2362 cpu->id_dfr0 = 0x000;
2363 cpu->id_afr0 = 0;
2364 cpu->id_mmfr0 = 0x00100103;
2365 cpu->id_mmfr1 = 0x20000000;
2366 cpu->id_mmfr2 = 0x01230000;
2367 cpu->id_mmfr3 = 0x00002111;
47576b94
RH		 2368 cpu->isar.id_isar0 = 0x00101111;
2369 cpu->isar.id_isar1 = 0x13112111;
2370 cpu->isar.id_isar2 = 0x21232041;
2371 cpu->isar.id_isar3 = 0x11112131;
2372 cpu->isar.id_isar4 = 0x00111142;
48eb3ae6 2373 cpu->dbgdidr = 0x35141000;
85df3786 2374 cpu->clidr = (1 << 27) | (1 << 24) | 3;
f7838b52
PC		 2375 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
2376 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
d8ba780b 2377 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
777dc784
PM		 2378}
2379
34f90529 2380#ifndef CONFIG_USER_ONLY
c4241c7d 2381static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
34f90529 2382{
cc7d44c2
LX		 2383 MachineState *ms = MACHINE(qdev_get_machine());
2384
34f90529
PM		 2385 /* Linux wants the number of processors from here.
2386 * Might as well set the interrupt-controller bit too.
2387 */
cc7d44c2 2388 return ((ms->smp.cpus - 1) << 24) | (1 << 23);
34f90529
PM		 2389}
2390#endif
2391
2392static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
2393#ifndef CONFIG_USER_ONLY
2394 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
2395 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
2396 .writefn = arm_cp_write_ignore, },
2397#endif
2398 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
2399 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2400 REGINFO_SENTINEL
2401};
2402
dcf578ed
AY		 2403static void cortex_a7_initfn(Object *obj)
2404{
2405 ARMCPU *cpu = ARM_CPU(obj);
2406
2407 cpu->dtb_compatible = "arm,cortex-a7";
5110e683 2408 set_feature(&cpu->env, ARM_FEATURE_V7VE);
dcf578ed
AY		 2409 set_feature(&cpu->env, ARM_FEATURE_VFP4);
2410 set_feature(&cpu->env, ARM_FEATURE_NEON);
2411 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
dcf578ed
AY		 2412 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
2413 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2414 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
436c0cbb 2415 set_feature(&cpu->env, ARM_FEATURE_EL2);
dcf578ed 2416 set_feature(&cpu->env, ARM_FEATURE_EL3);
a46118fc 2417 set_feature(&cpu->env, ARM_FEATURE_PMU);
dcf578ed
AY		 2418 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
2419 cpu->midr = 0x410fc075;
2420 cpu->reset_fpsid = 0x41023075;
47576b94
RH		 2421 cpu->isar.mvfr0 = 0x10110222;
2422 cpu->isar.mvfr1 = 0x11111111;
dcf578ed
AY		 2423 cpu->ctr = 0x84448003;
2424 cpu->reset_sctlr = 0x00c50078;
2425 cpu->id_pfr0 = 0x00001131;
2426 cpu->id_pfr1 = 0x00011011;
2427 cpu->id_dfr0 = 0x02010555;
dcf578ed
AY		 2428 cpu->id_afr0 = 0x00000000;
2429 cpu->id_mmfr0 = 0x10101105;
2430 cpu->id_mmfr1 = 0x40000000;
2431 cpu->id_mmfr2 = 0x01240000;
2432 cpu->id_mmfr3 = 0x02102211;
37bdda89
RH		 2433 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
2434 * table 4-41 gives 0x02101110, which includes the arm div insns.
2435 */
47576b94
RH		 2436 cpu->isar.id_isar0 = 0x02101110;
2437 cpu->isar.id_isar1 = 0x13112111;
2438 cpu->isar.id_isar2 = 0x21232041;
2439 cpu->isar.id_isar3 = 0x11112131;
2440 cpu->isar.id_isar4 = 0x10011142;
dcf578ed
AY		 2441 cpu->dbgdidr = 0x3515f005;
2442 cpu->clidr = 0x0a200023;
2443 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
2444 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
2445 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
2446 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
2447}
2448
777dc784
PM		 2449static void cortex_a15_initfn(Object *obj)
2450{
2451 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2452
2453 cpu->dtb_compatible = "arm,cortex-a15";
5110e683 2454 set_feature(&cpu->env, ARM_FEATURE_V7VE);
581be094 2455 set_feature(&cpu->env, ARM_FEATURE_VFP4);
581be094
PM		 2456 set_feature(&cpu->env, ARM_FEATURE_NEON);
2457 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
581be094 2458 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
c4804214 2459 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
c29f9a0a 2460 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
436c0cbb 2461 set_feature(&cpu->env, ARM_FEATURE_EL2);
c0ccb02d 2462 set_feature(&cpu->env, ARM_FEATURE_EL3);
a46118fc 2463 set_feature(&cpu->env, ARM_FEATURE_PMU);
3541addc 2464 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
b2d06f96 2465 cpu->midr = 0x412fc0f1;
325b3cef 2466 cpu->reset_fpsid = 0x410430f0;
47576b94
RH		 2467 cpu->isar.mvfr0 = 0x10110222;
2468 cpu->isar.mvfr1 = 0x11111111;
64e1671f 2469 cpu->ctr = 0x8444c004;
0ca7e01c 2470 cpu->reset_sctlr = 0x00c50078;
2e4d7e3e
PM		 2471 cpu->id_pfr0 = 0x00001131;
2472 cpu->id_pfr1 = 0x00011011;
2473 cpu->id_dfr0 = 0x02010555;
2474 cpu->id_afr0 = 0x00000000;
2475 cpu->id_mmfr0 = 0x10201105;
2476 cpu->id_mmfr1 = 0x20000000;
2477 cpu->id_mmfr2 = 0x01240000;
2478 cpu->id_mmfr3 = 0x02102211;
47576b94
RH		 2479 cpu->isar.id_isar0 = 0x02101110;
2480 cpu->isar.id_isar1 = 0x13112111;
2481 cpu->isar.id_isar2 = 0x21232041;
2482 cpu->isar.id_isar3 = 0x11112131;
2483 cpu->isar.id_isar4 = 0x10011142;
48eb3ae6 2484 cpu->dbgdidr = 0x3515f021;
85df3786
PM		 2485 cpu->clidr = 0x0a200023;
2486 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
2487 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
2488 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
34f90529 2489 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
777dc784
PM		 2490}
2491
2492static void ti925t_initfn(Object *obj)
2493{
2494 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 2495 set_feature(&cpu->env, ARM_FEATURE_V4T);
2496 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
777dc784 2497 cpu->midr = ARM_CPUID_TI925T;
64e1671f 2498 cpu->ctr = 0x5109149;
0ca7e01c 2499 cpu->reset_sctlr = 0x00000070;
777dc784
PM		 2500}
2501
2502static void sa1100_initfn(Object *obj)
2503{
2504 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2505
2506 cpu->dtb_compatible = "intel,sa1100";
581be094 2507 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
c4804214 2508 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
b2d06f96 2509 cpu->midr = 0x4401A11B;
0ca7e01c 2510 cpu->reset_sctlr = 0x00000070;
777dc784
PM		 2511}
2512
2513static void sa1110_initfn(Object *obj)
2514{
2515 ARMCPU *cpu = ARM_CPU(obj);
581be094 2516 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
c4804214 2517 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
b2d06f96 2518 cpu->midr = 0x6901B119;
0ca7e01c 2519 cpu->reset_sctlr = 0x00000070;
777dc784
PM		 2520}
2521
2522static void pxa250_initfn(Object *obj)
2523{
2524 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2525
2526 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2527 set_feature(&cpu->env, ARM_FEATURE_V5);
2528 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 2529 cpu->midr = 0x69052100;
64e1671f 2530 cpu->ctr = 0xd172172;
0ca7e01c 2531 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2532}
2533
2534static void pxa255_initfn(Object *obj)
2535{
2536 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2537
2538 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2539 set_feature(&cpu->env, ARM_FEATURE_V5);
2540 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 2541 cpu->midr = 0x69052d00;
64e1671f 2542 cpu->ctr = 0xd172172;
0ca7e01c 2543 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2544}
2545
2546static void pxa260_initfn(Object *obj)
2547{
2548 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2549
2550 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2551 set_feature(&cpu->env, ARM_FEATURE_V5);
2552 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 2553 cpu->midr = 0x69052903;
64e1671f 2554 cpu->ctr = 0xd172172;
0ca7e01c 2555 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2556}
2557
2558static void pxa261_initfn(Object *obj)
2559{
2560 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2561
2562 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2563 set_feature(&cpu->env, ARM_FEATURE_V5);
2564 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 2565 cpu->midr = 0x69052d05;
64e1671f 2566 cpu->ctr = 0xd172172;
0ca7e01c 2567 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2568}
2569
2570static void pxa262_initfn(Object *obj)
2571{
2572 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2573
2574 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2575 set_feature(&cpu->env, ARM_FEATURE_V5);
2576 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 2577 cpu->midr = 0x69052d06;
64e1671f 2578 cpu->ctr = 0xd172172;
0ca7e01c 2579 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2580}
2581
2582static void pxa270a0_initfn(Object *obj)
2583{
2584 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2585
2586 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2587 set_feature(&cpu->env, ARM_FEATURE_V5);
2588 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2589 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 2590 cpu->midr = 0x69054110;
64e1671f 2591 cpu->ctr = 0xd172172;
0ca7e01c 2592 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2593}
2594
2595static void pxa270a1_initfn(Object *obj)
2596{
2597 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2598
2599 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2600 set_feature(&cpu->env, ARM_FEATURE_V5);
2601 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2602 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 2603 cpu->midr = 0x69054111;
64e1671f 2604 cpu->ctr = 0xd172172;
0ca7e01c 2605 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2606}
2607
2608static void pxa270b0_initfn(Object *obj)
2609{
2610 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2611
2612 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2613 set_feature(&cpu->env, ARM_FEATURE_V5);
2614 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2615 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 2616 cpu->midr = 0x69054112;
64e1671f 2617 cpu->ctr = 0xd172172;
0ca7e01c 2618 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2619}
2620
2621static void pxa270b1_initfn(Object *obj)
2622{
2623 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2624
2625 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2626 set_feature(&cpu->env, ARM_FEATURE_V5);
2627 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2628 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 2629 cpu->midr = 0x69054113;
64e1671f 2630 cpu->ctr = 0xd172172;
0ca7e01c 2631 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2632}
2633
2634static void pxa270c0_initfn(Object *obj)
2635{
2636 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2637
2638 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2639 set_feature(&cpu->env, ARM_FEATURE_V5);
2640 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2641 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 2642 cpu->midr = 0x69054114;
64e1671f 2643 cpu->ctr = 0xd172172;
0ca7e01c 2644 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2645}
2646
2647static void pxa270c5_initfn(Object *obj)
2648{
2649 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2650
2651 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2652 set_feature(&cpu->env, ARM_FEATURE_V5);
2653 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2654 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 2655 cpu->midr = 0x69054117;
64e1671f 2656 cpu->ctr = 0xd172172;
0ca7e01c 2657 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2658}
2659
bab52d4b
PM		 2660#ifndef TARGET_AARCH64
2661/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
2662 * otherwise, a CPU with as many features enabled as our emulation supports.
2663 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
2664 * this only needs to handle 32 bits.
2665 */
2666static void arm_max_initfn(Object *obj)
2667{
2668 ARMCPU *cpu = ARM_CPU(obj);
2669
2670 if (kvm_enabled()) {
2671 kvm_arm_set_cpu_features_from_host(cpu);
dea101a1 2672 kvm_arm_add_vcpu_properties(obj);
bab52d4b
PM		 2673 } else {
2674 cortex_a15_initfn(obj);
973751fd
PM		 2675
2676 /* old-style VFP short-vector support */
2677 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
2678
a0032cc5
PM		 2679#ifdef CONFIG_USER_ONLY
2680 /* We don't set these in system emulation mode for the moment,
962fcbf2
RH		 2681 * since we don't correctly set (all of) the ID registers to
2682 * advertise them.
bab52d4b 2683 */
a0032cc5 2684 set_feature(&cpu->env, ARM_FEATURE_V8);
962fcbf2
RH		 2685 {
2686 uint32_t t;
2687
2688 t = cpu->isar.id_isar5;
2689 t = FIELD_DP32(t, ID_ISAR5, AES, 2);
2690 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
2691 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
2692 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
2693 t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
2694 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
2695 cpu->isar.id_isar5 = t;
2696
2697 t = cpu->isar.id_isar6;
6c1f6f27 2698 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
962fcbf2 2699 t = FIELD_DP32(t, ID_ISAR6, DP, 1);
991c0599 2700 t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
9888bd1e 2701 t = FIELD_DP32(t, ID_ISAR6, SB, 1);
cb570bd3 2702 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
962fcbf2 2703 cpu->isar.id_isar6 = t;
ab638a32 2704
45b1a243
AB		 2705 t = cpu->isar.mvfr1;
2706 t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */
2707 cpu->isar.mvfr1 = t;
2708
c8877d0f
RH		 2709 t = cpu->isar.mvfr2;
2710 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
2711 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
2712 cpu->isar.mvfr2 = t;
2713
e0fe7309
RH		 2714 t = cpu->id_mmfr3;
2715 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
2716 cpu->id_mmfr3 = t;
2717
ab638a32
RH		 2718 t = cpu->id_mmfr4;
2719 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
2720 cpu->id_mmfr4 = t;
962fcbf2 2721 }
bab52d4b 2722#endif
a0032cc5 2723 }
777dc784 2724}
f5f6d38b 2725#endif
777dc784 2726
15ee776b
PM		 2727#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
2728
51e5ef45 2729struct ARMCPUInfo {
777dc784
PM		 2730 const char *name;
2731 void (*initfn)(Object *obj);
e6f010cc 2732 void (*class_init)(ObjectClass *oc, void *data);
51e5ef45 2733};
777dc784
PM		 2734
2735static const ARMCPUInfo arm_cpus[] = {
15ee776b 2736#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
777dc784
PM		 2737 { .name = "arm926", .initfn = arm926_initfn },
2738 { .name = "arm946", .initfn = arm946_initfn },
2739 { .name = "arm1026", .initfn = arm1026_initfn },
2740 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
2741 * older core than plain "arm1136". In particular this does not
2742 * have the v6K features.
2743 */
2744 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
2745 { .name = "arm1136", .initfn = arm1136_initfn },
2746 { .name = "arm1176", .initfn = arm1176_initfn },
2747 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
191776b9
SH		 2748 { .name = "cortex-m0", .initfn = cortex_m0_initfn,
2749 .class_init = arm_v7m_class_init },
e6f010cc
AF		 2750 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
2751 .class_init = arm_v7m_class_init },
ba890a9b
AR		 2752 { .name = "cortex-m4", .initfn = cortex_m4_initfn,
2753 .class_init = arm_v7m_class_init },
cf7beda5
CL		 2754 { .name = "cortex-m7", .initfn = cortex_m7_initfn,
2755 .class_init = arm_v7m_class_init },
c7b26382
PM		 2756 { .name = "cortex-m33", .initfn = cortex_m33_initfn,
2757 .class_init = arm_v7m_class_init },
d6a6b13e 2758 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
ebac5458 2759 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
dcf578ed 2760 { .name = "cortex-a7", .initfn = cortex_a7_initfn },
777dc784
PM		 2761 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
2762 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
2763 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
2764 { .name = "ti925t", .initfn = ti925t_initfn },
2765 { .name = "sa1100", .initfn = sa1100_initfn },
2766 { .name = "sa1110", .initfn = sa1110_initfn },
2767 { .name = "pxa250", .initfn = pxa250_initfn },
2768 { .name = "pxa255", .initfn = pxa255_initfn },
2769 { .name = "pxa260", .initfn = pxa260_initfn },
2770 { .name = "pxa261", .initfn = pxa261_initfn },
2771 { .name = "pxa262", .initfn = pxa262_initfn },
2772 /* "pxa270" is an alias for "pxa270-a0" */
2773 { .name = "pxa270", .initfn = pxa270a0_initfn },
2774 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
2775 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
2776 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
2777 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
2778 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
2779 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
bab52d4b
PM		 2780#ifndef TARGET_AARCH64
2781 { .name = "max", .initfn = arm_max_initfn },
2782#endif
f5f6d38b 2783#ifdef CONFIG_USER_ONLY
a0032cc5 2784 { .name = "any", .initfn = arm_max_initfn },
f5f6d38b 2785#endif
15ee776b 2786#endif
83e6813a 2787 { .name = NULL }
777dc784
PM		 2788};
2789
5de16430
PM		 2790static Property arm_cpu_properties[] = {
2791 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
98128601 2792 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
51a9b04b 2793 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
ce5b1bbf
LV		 2794 DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
2795 mp_affinity, ARM64_AFFINITY_INVALID),
15f8b142 2796 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
f9a69711 2797 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
5de16430
PM		 2798 DEFINE_PROP_END_OF_LIST()
2799};
2800
b3820e6c
DH		 2801static gchar *arm_gdb_arch_name(CPUState *cs)
2802{
2803 ARMCPU *cpu = ARM_CPU(cs);
2804 CPUARMState *env = &cpu->env;
2805
2806 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
2807 return g_strdup("iwmmxt");
2808 }
2809 return g_strdup("arm");
2810}
2811
dec9c2d4
AF		 2812static void arm_cpu_class_init(ObjectClass *oc, void *data)
2813{
2814 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2815 CPUClass *cc = CPU_CLASS(acc);
14969266
AF		 2816 DeviceClass *dc = DEVICE_CLASS(oc);
2817
bf853881
PMD		 2818 device_class_set_parent_realize(dc, arm_cpu_realizefn,
2819 &acc->parent_realize);
dec9c2d4 2820
4f67d30b 2821 device_class_set_props(dc, arm_cpu_properties);
bc9888f7 2822 cpu_class_set_parent_reset(cc, arm_cpu_reset, &acc->parent_reset);
5900d6b2
AF		 2823
2824 cc->class_by_name = arm_cpu_class_by_name;
8c2e1b00 2825 cc->has_work = arm_cpu_has_work;
e8925712 2826 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
878096ee 2827 cc->dump_state = arm_cpu_dump_state;
f45748f1 2828 cc->set_pc = arm_cpu_set_pc;
42f6ed91 2829 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb;
5b50e790
AF		 2830 cc->gdb_read_register = arm_cpu_gdb_read_register;
2831 cc->gdb_write_register = arm_cpu_gdb_write_register;
7350d553 2832#ifndef CONFIG_USER_ONLY
0adf7d3c 2833 cc->do_interrupt = arm_cpu_do_interrupt;
0faea0c7 2834 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
017518c1 2835 cc->asidx_from_attrs = arm_asidx_from_attrs;
00b941e5 2836 cc->vmsd = &vmstate_arm_cpu;
ed50ff78 2837 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
da2b9140
AJ		 2838 cc->write_elf64_note = arm_cpu_write_elf64_note;
2839 cc->write_elf32_note = arm_cpu_write_elf32_note;
00b941e5 2840#endif
a0e372f0 2841 cc->gdb_num_core_regs = 26;
5b24c641 2842 cc->gdb_core_xml_file = "arm-core.xml";
b3820e6c 2843 cc->gdb_arch_name = arm_gdb_arch_name;
200bf5b7 2844 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
2472b6c0 2845 cc->gdb_stop_before_watchpoint = true;
48440620 2846 cc->disas_set_info = arm_disas_set_info;
74d7fc7f 2847#ifdef CONFIG_TCG
55c3ceef 2848 cc->tcg_initialize = arm_translate_init;
7350d553 2849 cc->tlb_fill = arm_cpu_tlb_fill;
9dd5cca4
PMD		 2850 cc->debug_excp_handler = arm_debug_excp_handler;
2851 cc->debug_check_watchpoint = arm_debug_check_watchpoint;
e21b551c
PMD		 2852#if !defined(CONFIG_USER_ONLY)
2853 cc->do_unaligned_access = arm_cpu_do_unaligned_access;
2854 cc->do_transaction_failed = arm_cpu_do_transaction_failed;
9dd5cca4 2855 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
e21b551c 2856#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
74d7fc7f 2857#endif
dec9c2d4
AF		 2858}
2859
86f0a186
PM		 2860#ifdef CONFIG_KVM
2861static void arm_host_initfn(Object *obj)
2862{
2863 ARMCPU *cpu = ARM_CPU(obj);
2864
2865 kvm_arm_set_cpu_features_from_host(cpu);
87014c6b
AJ		 2866 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
2867 aarch64_add_sve_properties(obj);
2868 }
dea101a1 2869 kvm_arm_add_vcpu_properties(obj);
51e5ef45 2870 arm_cpu_post_init(obj);
86f0a186
PM		 2871}
2872
2873static const TypeInfo host_arm_cpu_type_info = {
2874 .name = TYPE_ARM_HOST_CPU,
2875#ifdef TARGET_AARCH64
2876 .parent = TYPE_AARCH64_CPU,
2877#else
2878 .parent = TYPE_ARM_CPU,
2879#endif
2880 .instance_init = arm_host_initfn,
2881};
2882
2883#endif
2884
51e5ef45
MAL		 2885static void arm_cpu_instance_init(Object *obj)
2886{
2887 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
2888
2889 acc->info->initfn(obj);
2890 arm_cpu_post_init(obj);
2891}
2892
2893static void cpu_register_class_init(ObjectClass *oc, void *data)
2894{
2895 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2896
2897 acc->info = data;
2898}
2899
777dc784
PM		 2900static void cpu_register(const ARMCPUInfo *info)
2901{
2902 TypeInfo type_info = {
777dc784
PM		 2903 .parent = TYPE_ARM_CPU,
2904 .instance_size = sizeof(ARMCPU),
51e5ef45 2905 .instance_init = arm_cpu_instance_init,
777dc784 2906 .class_size = sizeof(ARMCPUClass),
51e5ef45
MAL		 2907 .class_init = info->class_init ?: cpu_register_class_init,
2908 .class_data = (void *)info,
777dc784
PM		 2909 };
2910
51492fd1 2911 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
918fd083 2912 type_register(&type_info);
51492fd1 2913 g_free((void *)type_info.name);
777dc784
PM		 2914}
2915
dec9c2d4
AF		 2916static const TypeInfo arm_cpu_type_info = {
2917 .name = TYPE_ARM_CPU,
2918 .parent = TYPE_CPU,
2919 .instance_size = sizeof(ARMCPU),
777dc784 2920 .instance_init = arm_cpu_initfn,
4b6a83fb 2921 .instance_finalize = arm_cpu_finalizefn,
777dc784 2922 .abstract = true,
dec9c2d4
AF		 2923 .class_size = sizeof(ARMCPUClass),
2924 .class_init = arm_cpu_class_init,
2925};
2926
181962fd
PM		 2927static const TypeInfo idau_interface_type_info = {
2928 .name = TYPE_IDAU_INTERFACE,
2929 .parent = TYPE_INTERFACE,
2930 .class_size = sizeof(IDAUInterfaceClass),
2931};
2932
dec9c2d4
AF		 2933static void arm_cpu_register_types(void)
2934{
83e6813a 2935 const ARMCPUInfo *info = arm_cpus;
777dc784 2936
dec9c2d4 2937 type_register_static(&arm_cpu_type_info);
181962fd 2938 type_register_static(&idau_interface_type_info);
83e6813a
PM		 2939
2940 while (info->name) {
2941 cpu_register(info);
2942 info++;
777dc784 2943 }
86f0a186
PM		 2944
2945#ifdef CONFIG_KVM
2946 type_register_static(&host_arm_cpu_type_info);
2947#endif
dec9c2d4
AF		 2948}
2949
2950type_init(arm_cpu_register_types)
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