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[mirror_qemu.git] / target / arm / cpu.c
CommitLineData
dec9c2d4
AF		 1/*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
74c21bd0 21#include "qemu/osdep.h"
86480615 22#include "qemu/qemu-print.h"
a8d25326 23#include "qemu-common.h"
181962fd 24#include "target/arm/idau.h"
0b8fa32f 25#include "qemu/module.h"
da34e65c 26#include "qapi/error.h"
f9f62e4c 27#include "qapi/visitor.h"
778c3a06 28#include "cpu.h"
ccd38087 29#include "internals.h"
63c91552 30#include "exec/exec-all.h"
5de16430 31#include "hw/qdev-properties.h"
3c30dd5a
PM		 32#if !defined(CONFIG_USER_ONLY)
33#include "hw/loader.h"
cc7d44c2 34#include "hw/boards.h"
3c30dd5a 35#endif
9c17d615 36#include "sysemu/sysemu.h"
14a48c1d 37#include "sysemu/tcg.h"
b3946626 38#include "sysemu/hw_accel.h"
50a2c6e5 39#include "kvm_arm.h"
110f6c70 40#include "disas/capstone.h"
24f91e81 41#include "fpu/softfloat.h"
dec9c2d4 42
f45748f1
AF		 43static void arm_cpu_set_pc(CPUState *cs, vaddr value)
44{
45 ARMCPU *cpu = ARM_CPU(cs);
42f6ed91
JS		 46 CPUARMState *env = &cpu->env;
47
48 if (is_a64(env)) {
49 env->pc = value;
50 env->thumb = 0;
51 } else {
52 env->regs[15] = value & ~1;
53 env->thumb = value & 1;
54 }
55}
f45748f1 56
42f6ed91
JS		 57static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
58{
59 ARMCPU *cpu = ARM_CPU(cs);
60 CPUARMState *env = &cpu->env;
61
62 /*
63 * It's OK to look at env for the current mode here, because it's
64 * never possible for an AArch64 TB to chain to an AArch32 TB.
65 */
66 if (is_a64(env)) {
67 env->pc = tb->pc;
68 } else {
69 env->regs[15] = tb->pc;
70 }
f45748f1
AF		 71}
72
8c2e1b00
AF		 73static bool arm_cpu_has_work(CPUState *cs)
74{
543486db
RH		 75 ARMCPU *cpu = ARM_CPU(cs);
76
062ba099 77 return (cpu->power_state != PSCI_OFF)
543486db 78 && cs->interrupt_request &
136e67e9
EI		 79 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
80 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
81 | CPU_INTERRUPT_EXITTB);
8c2e1b00
AF		 82}
83
b5c53d1b
AL		 84void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
85 void *opaque)
86{
87 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
88
89 entry->hook = hook;
90 entry->opaque = opaque;
91
92 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
93}
94
08267487 95void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
bd7d00fc
PM		 96 void *opaque)
97{
08267487
AL		 98 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
99
100 entry->hook = hook;
101 entry->opaque = opaque;
102
103 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
bd7d00fc
PM		 104}
105
4b6a83fb
PM		 106static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
107{
108 /* Reset a single ARMCPRegInfo register */
109 ARMCPRegInfo *ri = value;
110 ARMCPU *cpu = opaque;
111
b061a82b 112 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
4b6a83fb
PM		 113 return;
114 }
115
116 if (ri->resetfn) {
117 ri->resetfn(&cpu->env, ri);
118 return;
119 }
120
121 /* A zero offset is never possible as it would be regs[0]
122 * so we use it to indicate that reset is being handled elsewhere.
123 * This is basically only used for fields in non-core coprocessors
124 * (like the pxa2xx ones).
125 */
126 if (!ri->fieldoffset) {
127 return;
128 }
129
67ed771d 130 if (cpreg_field_is_64bit(ri)) {
4b6a83fb
PM		 131 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
132 } else {
133 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
134 }
135}
136
49a66191
PM		 137static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
138{
139 /* Purely an assertion check: we've already done reset once,
140 * so now check that running the reset for the cpreg doesn't
141 * change its value. This traps bugs where two different cpregs
142 * both try to reset the same state field but to different values.
143 */
144 ARMCPRegInfo *ri = value;
145 ARMCPU *cpu = opaque;
146 uint64_t oldvalue, newvalue;
147
148 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
149 return;
150 }
151
152 oldvalue = read_raw_cp_reg(&cpu->env, ri);
153 cp_reg_reset(key, value, opaque);
154 newvalue = read_raw_cp_reg(&cpu->env, ri);
155 assert(oldvalue == newvalue);
156}
157
dec9c2d4
AF		 158/* CPUClass::reset() */
159static void arm_cpu_reset(CPUState *s)
160{
161 ARMCPU *cpu = ARM_CPU(s);
162 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
3c30dd5a 163 CPUARMState *env = &cpu->env;
3c30dd5a 164
dec9c2d4
AF		 165 acc->parent_reset(s);
166
1f5c00cf
AB		 167 memset(env, 0, offsetof(CPUARMState, end_reset_fields));
168
4b6a83fb 169 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
49a66191
PM		 170 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
171
3c30dd5a 172 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
47576b94
RH		 173 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
174 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
175 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
3c30dd5a 176
062ba099 177 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON;
543486db
RH		 178 s->halted = cpu->start_powered_off;
179
3c30dd5a
PM		 180 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
181 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
182 }
183
3926cc84
AG		 184 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
185 /* 64 bit CPUs always start in 64 bit mode */
186 env->aarch64 = 1;
d356312f
PM		 187#if defined(CONFIG_USER_ONLY)
188 env->pstate = PSTATE_MODE_EL0t;
14e5f106 189 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
137feaa9 190 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
276c6e81
RH		 191 /* Enable all PAC keys. */
192 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
193 SCTLR_EnDA | SCTLR_EnDB);
1ae9cfbd
RH		 194 /* Enable all PAC instructions */
195 env->cp15.hcr_el2 |= HCR_API;
196 env->cp15.scr_el3 |= SCR_API;
8c6afa6a 197 /* and to the FP/Neon instructions */
7ebd5f2e 198 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
802ac0e1
RH		 199 /* and to the SVE instructions */
200 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
201 env->cp15.cptr_el[3] |= CPTR_EZ;
202 /* with maximum vector length */
adf92eab
RH		 203 env->vfp.zcr_el[1] = cpu->sve_max_vq - 1;
204 env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
205 env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
f6a148fe
RH		 206 /*
207 * Enable TBI0 and TBI1. While the real kernel only enables TBI0,
208 * turning on both here will produce smaller code and otherwise
209 * make no difference to the user-level emulation.
210 */
211 env->cp15.tcr_el[1].raw_tcr = (3ULL << 37);
d356312f 212#else
5097227c
GB		 213 /* Reset into the highest available EL */
214 if (arm_feature(env, ARM_FEATURE_EL3)) {
215 env->pstate = PSTATE_MODE_EL3h;
216 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
217 env->pstate = PSTATE_MODE_EL2h;
218 } else {
219 env->pstate = PSTATE_MODE_EL1h;
220 }
3933443e 221 env->pc = cpu->rvbar;
8c6afa6a
PM		 222#endif
223 } else {
224#if defined(CONFIG_USER_ONLY)
225 /* Userspace expects access to cp10 and cp11 for FP/Neon */
7ebd5f2e 226 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
d356312f 227#endif
3926cc84
AG		 228 }
229
3c30dd5a
PM		 230#if defined(CONFIG_USER_ONLY)
231 env->uncached_cpsr = ARM_CPU_MODE_USR;
232 /* For user mode we must enable access to coprocessors */
233 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
234 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
235 env->cp15.c15_cpar = 3;
236 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
237 env->cp15.c15_cpar = 1;
238 }
239#else
060a65df
PM		 240
241 /*
242 * If the highest available EL is EL2, AArch32 will start in Hyp
243 * mode; otherwise it starts in SVC. Note that if we start in
244 * AArch64 then these values in the uncached_cpsr will be ignored.
245 */
246 if (arm_feature(env, ARM_FEATURE_EL2) &&
247 !arm_feature(env, ARM_FEATURE_EL3)) {
248 env->uncached_cpsr = ARM_CPU_MODE_HYP;
249 } else {
250 env->uncached_cpsr = ARM_CPU_MODE_SVC;
251 }
4cc35614 252 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
dc7abe4d 253
531c60a9 254 if (arm_feature(env, ARM_FEATURE_M)) {
6e3cf5df
MG		 255 uint32_t initial_msp; /* Loaded from 0x0 */
256 uint32_t initial_pc; /* Loaded from 0x4 */
3c30dd5a 257 uint8_t *rom;
38e2a77c 258 uint32_t vecbase;
6e3cf5df 259
1e577cc7
PM		 260 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
261 env->v7m.secure = true;
3b2e9344
PM		 262 } else {
263 /* This bit resets to 0 if security is supported, but 1 if
264 * it is not. The bit is not present in v7M, but we set it
265 * here so we can avoid having to make checks on it conditional
266 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
267 */
268 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
02ac2f7f
PM		 269 /*
270 * Set NSACR to indicate "NS access permitted to everything";
271 * this avoids having to have all the tests of it being
272 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
273 * v8.1M the guest-visible value of NSACR in a CPU without the
274 * Security Extension is 0xcff.
275 */
276 env->v7m.nsacr = 0xcff;
1e577cc7
PM		 277 }
278
9d40cd8a 279 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
2c4da50d 280 * that it resets to 1, so QEMU always does that rather than making
9d40cd8a 281 * it dependent on CPU model. In v8M it is RES1.
2c4da50d 282 */
9d40cd8a
PM		 283 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
284 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
285 if (arm_feature(env, ARM_FEATURE_V8)) {
286 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
287 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
288 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
289 }
22ab3460
JS		 290 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
291 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
292 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
293 }
2c4da50d 294
d33abe82
PM		 295 if (arm_feature(env, ARM_FEATURE_VFP)) {
296 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
297 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
298 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
299 }
056f43df
PM		 300 /* Unlike A/R profile, M profile defines the reset LR value */
301 env->regs[14] = 0xffffffff;
302
38e2a77c
PM		 303 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
304
305 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
306 vecbase = env->v7m.vecbase[env->v7m.secure];
0f0f8b61 307 rom = rom_ptr(vecbase, 8);
3c30dd5a 308 if (rom) {
6e3cf5df
MG		 309 /* Address zero is covered by ROM which hasn't yet been
310 * copied into physical memory.
311 */
312 initial_msp = ldl_p(rom);
313 initial_pc = ldl_p(rom + 4);
314 } else {
315 /* Address zero not covered by a ROM blob, or the ROM blob
316 * is in non-modifiable memory and this is a second reset after
317 * it got copied into memory. In the latter case, rom_ptr
318 * will return a NULL pointer and we should use ldl_phys instead.
319 */
38e2a77c
PM		 320 initial_msp = ldl_phys(s->as, vecbase);
321 initial_pc = ldl_phys(s->as, vecbase + 4);
3c30dd5a 322 }
6e3cf5df
MG		 323
324 env->regs[13] = initial_msp & 0xFFFFFFFC;
325 env->regs[15] = initial_pc & ~1;
326 env->thumb = initial_pc & 1;
3c30dd5a 327 }
387f9806 328
137feaa9
FA		 329 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
330 * executing as AArch32 then check if highvecs are enabled and
331 * adjust the PC accordingly.
332 */
333 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
34bf7744 334 env->regs[15] = 0xFFFF0000;
387f9806
AP		 335 }
336
dc3c4c14
PM		 337 /* M profile requires that reset clears the exclusive monitor;
338 * A profile does not, but clearing it makes more sense than having it
339 * set with an exclusive access on address zero.
340 */
341 arm_clear_exclusive(env);
342
3c30dd5a 343 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
3c30dd5a 344#endif
69ceea64 345
0e1a46bb 346 if (arm_feature(env, ARM_FEATURE_PMSA)) {
69ceea64 347 if (cpu->pmsav7_dregion > 0) {
0e1a46bb 348 if (arm_feature(env, ARM_FEATURE_V8)) {
62c58ee0
PM		 349 memset(env->pmsav8.rbar[M_REG_NS], 0,
350 sizeof(*env->pmsav8.rbar[M_REG_NS])
351 * cpu->pmsav7_dregion);
352 memset(env->pmsav8.rlar[M_REG_NS], 0,
353 sizeof(*env->pmsav8.rlar[M_REG_NS])
354 * cpu->pmsav7_dregion);
355 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
356 memset(env->pmsav8.rbar[M_REG_S], 0,
357 sizeof(*env->pmsav8.rbar[M_REG_S])
358 * cpu->pmsav7_dregion);
359 memset(env->pmsav8.rlar[M_REG_S], 0,
360 sizeof(*env->pmsav8.rlar[M_REG_S])
361 * cpu->pmsav7_dregion);
362 }
0e1a46bb
PM		 363 } else if (arm_feature(env, ARM_FEATURE_V7)) {
364 memset(env->pmsav7.drbar, 0,
365 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
366 memset(env->pmsav7.drsr, 0,
367 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
368 memset(env->pmsav7.dracr, 0,
369 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
370 }
69ceea64 371 }
1bc04a88
PM		 372 env->pmsav7.rnr[M_REG_NS] = 0;
373 env->pmsav7.rnr[M_REG_S] = 0;
4125e6fe
PM		 374 env->pmsav8.mair0[M_REG_NS] = 0;
375 env->pmsav8.mair0[M_REG_S] = 0;
376 env->pmsav8.mair1[M_REG_NS] = 0;
377 env->pmsav8.mair1[M_REG_S] = 0;
69ceea64
PM		 378 }
379
9901c576
PM		 380 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
381 if (cpu->sau_sregion > 0) {
382 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
383 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
384 }
385 env->sau.rnr = 0;
386 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
387 * the Cortex-M33 does.
388 */
389 env->sau.ctrl = 0;
390 }
391
3c30dd5a
PM		 392 set_flush_to_zero(1, &env->vfp.standard_fp_status);
393 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
394 set_default_nan_mode(1, &env->vfp.standard_fp_status);
395 set_float_detect_tininess(float_tininess_before_rounding,
396 &env->vfp.fp_status);
397 set_float_detect_tininess(float_tininess_before_rounding,
398 &env->vfp.standard_fp_status);
bcc531f0
PM		 399 set_float_detect_tininess(float_tininess_before_rounding,
400 &env->vfp.fp_status_f16);
50a2c6e5
PB		 401#ifndef CONFIG_USER_ONLY
402 if (kvm_enabled()) {
403 kvm_arm_reset_vcpu(cpu);
404 }
405#endif
9ee98ce8 406
46747d15 407 hw_breakpoint_update_all(cpu);
9ee98ce8 408 hw_watchpoint_update_all(cpu);
dec9c2d4
AF		 409}
410
e8925712
RH		 411bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
412{
413 CPUClass *cc = CPU_GET_CLASS(cs);
012a906b
GB		 414 CPUARMState *env = cs->env_ptr;
415 uint32_t cur_el = arm_current_el(env);
416 bool secure = arm_is_secure(env);
417 uint32_t target_el;
418 uint32_t excp_idx;
e8925712
RH		 419 bool ret = false;
420
012a906b
GB		 421 if (interrupt_request & CPU_INTERRUPT_FIQ) {
422 excp_idx = EXCP_FIQ;
423 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
424 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
425 cs->exception_index = excp_idx;
426 env->exception.target_el = target_el;
427 cc->do_interrupt(cs);
428 ret = true;
429 }
e8925712 430 }
012a906b
GB		 431 if (interrupt_request & CPU_INTERRUPT_HARD) {
432 excp_idx = EXCP_IRQ;
433 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
434 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
435 cs->exception_index = excp_idx;
436 env->exception.target_el = target_el;
437 cc->do_interrupt(cs);
438 ret = true;
439 }
e8925712 440 }
012a906b
GB		 441 if (interrupt_request & CPU_INTERRUPT_VIRQ) {
442 excp_idx = EXCP_VIRQ;
443 target_el = 1;
444 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
445 cs->exception_index = excp_idx;
446 env->exception.target_el = target_el;
447 cc->do_interrupt(cs);
448 ret = true;
449 }
136e67e9 450 }
012a906b
GB		 451 if (interrupt_request & CPU_INTERRUPT_VFIQ) {
452 excp_idx = EXCP_VFIQ;
453 target_el = 1;
454 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
455 cs->exception_index = excp_idx;
456 env->exception.target_el = target_el;
457 cc->do_interrupt(cs);
458 ret = true;
459 }
136e67e9 460 }
e8925712
RH		 461
462 return ret;
463}
464
b5c633c5
PM		 465#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
466static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
467{
468 CPUClass *cc = CPU_GET_CLASS(cs);
469 ARMCPU *cpu = ARM_CPU(cs);
470 CPUARMState *env = &cpu->env;
471 bool ret = false;
472
f4e8e4ed 473 /* ARMv7-M interrupt masking works differently than -A or -R.
7ecdaa4a
PM		 474 * There is no FIQ/IRQ distinction. Instead of I and F bits
475 * masking FIQ and IRQ interrupts, an exception is taken only
476 * if it is higher priority than the current execution priority
477 * (which depends on state like BASEPRI, FAULTMASK and the
478 * currently active exception).
b5c633c5
PM		 479 */
480 if (interrupt_request & CPU_INTERRUPT_HARD
f4e8e4ed 481 && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
b5c633c5
PM		 482 cs->exception_index = EXCP_IRQ;
483 cc->do_interrupt(cs);
484 ret = true;
485 }
486 return ret;
487}
488#endif
489
89430fc6
PM		 490void arm_cpu_update_virq(ARMCPU *cpu)
491{
492 /*
493 * Update the interrupt level for VIRQ, which is the logical OR of
494 * the HCR_EL2.VI bit and the input line level from the GIC.
495 */
496 CPUARMState *env = &cpu->env;
497 CPUState *cs = CPU(cpu);
498
499 bool new_state = (env->cp15.hcr_el2 & HCR_VI) ||
500 (env->irq_line_state & CPU_INTERRUPT_VIRQ);
501
502 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) {
503 if (new_state) {
504 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ);
505 } else {
506 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ);
507 }
508 }
509}
510
511void arm_cpu_update_vfiq(ARMCPU *cpu)
512{
513 /*
514 * Update the interrupt level for VFIQ, which is the logical OR of
515 * the HCR_EL2.VF bit and the input line level from the GIC.
516 */
517 CPUARMState *env = &cpu->env;
518 CPUState *cs = CPU(cpu);
519
520 bool new_state = (env->cp15.hcr_el2 & HCR_VF) ||
521 (env->irq_line_state & CPU_INTERRUPT_VFIQ);
522
523 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) {
524 if (new_state) {
525 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ);
526 } else {
527 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ);
528 }
529 }
530}
531
7c1840b6
PM		 532#ifndef CONFIG_USER_ONLY
533static void arm_cpu_set_irq(void *opaque, int irq, int level)
534{
535 ARMCPU *cpu = opaque;
136e67e9 536 CPUARMState *env = &cpu->env;
7c1840b6 537 CPUState *cs = CPU(cpu);
136e67e9
EI		 538 static const int mask[] = {
539 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
540 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
541 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
542 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
543 };
7c1840b6 544
ed89f078
PM		 545 if (level) {
546 env->irq_line_state |= mask[irq];
547 } else {
548 env->irq_line_state &= ~mask[irq];
549 }
550
7c1840b6 551 switch (irq) {
136e67e9 552 case ARM_CPU_VIRQ:
89430fc6
PM		 553 assert(arm_feature(env, ARM_FEATURE_EL2));
554 arm_cpu_update_virq(cpu);
555 break;
136e67e9 556 case ARM_CPU_VFIQ:
f128bf29 557 assert(arm_feature(env, ARM_FEATURE_EL2));
89430fc6
PM		 558 arm_cpu_update_vfiq(cpu);
559 break;
136e67e9 560 case ARM_CPU_IRQ:
7c1840b6
PM		 561 case ARM_CPU_FIQ:
562 if (level) {
136e67e9 563 cpu_interrupt(cs, mask[irq]);
7c1840b6 564 } else {
136e67e9 565 cpu_reset_interrupt(cs, mask[irq]);
7c1840b6
PM		 566 }
567 break;
568 default:
8f6fd322 569 g_assert_not_reached();
7c1840b6
PM		 570 }
571}
572
573static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
574{
575#ifdef CONFIG_KVM
576 ARMCPU *cpu = opaque;
ed89f078 577 CPUARMState *env = &cpu->env;
7c1840b6
PM		 578 CPUState *cs = CPU(cpu);
579 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
ed89f078 580 uint32_t linestate_bit;
7c1840b6
PM		 581
582 switch (irq) {
583 case ARM_CPU_IRQ:
584 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
ed89f078 585 linestate_bit = CPU_INTERRUPT_HARD;
7c1840b6
PM		 586 break;
587 case ARM_CPU_FIQ:
588 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
ed89f078 589 linestate_bit = CPU_INTERRUPT_FIQ;
7c1840b6
PM		 590 break;
591 default:
8f6fd322 592 g_assert_not_reached();
7c1840b6 593 }
ed89f078
PM		 594
595 if (level) {
596 env->irq_line_state |= linestate_bit;
597 } else {
598 env->irq_line_state &= ~linestate_bit;
599 }
600
7c1840b6
PM		 601 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
602 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
603#endif
604}
84f2bed3 605
ed50ff78 606static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
84f2bed3
PS		 607{
608 ARMCPU *cpu = ARM_CPU(cs);
609 CPUARMState *env = &cpu->env;
84f2bed3
PS		 610
611 cpu_synchronize_state(cs);
ed50ff78 612 return arm_cpu_data_is_big_endian(env);
84f2bed3
PS		 613}
614
7c1840b6
PM		 615#endif
616
581be094
PM		 617static inline void set_feature(CPUARMState *env, int feature)
618{
918f5dca 619 env->features |= 1ULL << feature;
581be094
PM		 620}
621
08828484
GB		 622static inline void unset_feature(CPUARMState *env, int feature)
623{
624 env->features &= ~(1ULL << feature);
625}
626
48440620
PC		 627static int
628print_insn_thumb1(bfd_vma pc, disassemble_info *info)
629{
630 return print_insn_arm(pc | 1, info);
631}
632
633static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
634{
635 ARMCPU *ac = ARM_CPU(cpu);
636 CPUARMState *env = &ac->env;
7bcdbf51 637 bool sctlr_b;
48440620
PC		 638
639 if (is_a64(env)) {
640 /* We might not be compiled with the A64 disassembler
641 * because it needs a C++ compiler. Leave print_insn
642 * unset in this case to use the caller default behaviour.
643 */
644#if defined(CONFIG_ARM_A64_DIS)
645 info->print_insn = print_insn_arm_a64;
646#endif
110f6c70 647 info->cap_arch = CS_ARCH_ARM64;
15fa1a0a
RH		 648 info->cap_insn_unit = 4;
649 info->cap_insn_split = 4;
48440620 650 } else {
110f6c70
RH		 651 int cap_mode;
652 if (env->thumb) {
653 info->print_insn = print_insn_thumb1;
15fa1a0a
RH		 654 info->cap_insn_unit = 2;
655 info->cap_insn_split = 4;
110f6c70
RH		 656 cap_mode = CS_MODE_THUMB;
657 } else {
658 info->print_insn = print_insn_arm;
15fa1a0a
RH		 659 info->cap_insn_unit = 4;
660 info->cap_insn_split = 4;
110f6c70
RH		 661 cap_mode = CS_MODE_ARM;
662 }
663 if (arm_feature(env, ARM_FEATURE_V8)) {
664 cap_mode |= CS_MODE_V8;
665 }
666 if (arm_feature(env, ARM_FEATURE_M)) {
667 cap_mode |= CS_MODE_MCLASS;
668 }
669 info->cap_arch = CS_ARCH_ARM;
670 info->cap_mode = cap_mode;
48440620 671 }
7bcdbf51
RH		 672
673 sctlr_b = arm_sctlr_b(env);
674 if (bswap_code(sctlr_b)) {
48440620
PC		 675#ifdef TARGET_WORDS_BIGENDIAN
676 info->endian = BFD_ENDIAN_LITTLE;
677#else
678 info->endian = BFD_ENDIAN_BIG;
679#endif
680 }
f7478a92 681 info->flags &= ~INSN_ARM_BE32;
7bcdbf51
RH		 682#ifndef CONFIG_USER_ONLY
683 if (sctlr_b) {
f7478a92
JB		 684 info->flags |= INSN_ARM_BE32;
685 }
7bcdbf51 686#endif
48440620
PC		 687}
688
86480615
PMD		 689#ifdef TARGET_AARCH64
690
691static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
692{
693 ARMCPU *cpu = ARM_CPU(cs);
694 CPUARMState *env = &cpu->env;
695 uint32_t psr = pstate_read(env);
696 int i;
697 int el = arm_current_el(env);
698 const char *ns_status;
699
700 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
701 for (i = 0; i < 32; i++) {
702 if (i == 31) {
703 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
704 } else {
705 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
706 (i + 2) % 3 ? " " : "\n");
707 }
708 }
709
710 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
711 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
712 } else {
713 ns_status = "";
714 }
715 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
716 psr,
717 psr & PSTATE_N ? 'N' : '-',
718 psr & PSTATE_Z ? 'Z' : '-',
719 psr & PSTATE_C ? 'C' : '-',
720 psr & PSTATE_V ? 'V' : '-',
721 ns_status,
722 el,
723 psr & PSTATE_SP ? 'h' : 't');
724
725 if (cpu_isar_feature(aa64_bti, cpu)) {
726 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
727 }
728 if (!(flags & CPU_DUMP_FPU)) {
729 qemu_fprintf(f, "\n");
730 return;
731 }
732 if (fp_exception_el(env, el) != 0) {
733 qemu_fprintf(f, " FPU disabled\n");
734 return;
735 }
736 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
737 vfp_get_fpcr(env), vfp_get_fpsr(env));
738
739 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
740 int j, zcr_len = sve_zcr_len_for_el(env, el);
741
742 for (i = 0; i <= FFR_PRED_NUM; i++) {
743 bool eol;
744 if (i == FFR_PRED_NUM) {
745 qemu_fprintf(f, "FFR=");
746 /* It's last, so end the line. */
747 eol = true;
748 } else {
749 qemu_fprintf(f, "P%02d=", i);
750 switch (zcr_len) {
751 case 0:
752 eol = i % 8 == 7;
753 break;
754 case 1:
755 eol = i % 6 == 5;
756 break;
757 case 2:
758 case 3:
759 eol = i % 3 == 2;
760 break;
761 default:
762 /* More than one quadword per predicate. */
763 eol = true;
764 break;
765 }
766 }
767 for (j = zcr_len / 4; j >= 0; j--) {
768 int digits;
769 if (j * 4 + 4 <= zcr_len + 1) {
770 digits = 16;
771 } else {
772 digits = (zcr_len % 4 + 1) * 4;
773 }
774 qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
775 env->vfp.pregs[i].p[j],
776 j ? ":" : eol ? "\n" : " ");
777 }
778 }
779
780 for (i = 0; i < 32; i++) {
781 if (zcr_len == 0) {
782 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
783 i, env->vfp.zregs[i].d[1],
784 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
785 } else if (zcr_len == 1) {
786 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
787 ":%016" PRIx64 ":%016" PRIx64 "\n",
788 i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
789 env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
790 } else {
791 for (j = zcr_len; j >= 0; j--) {
792 bool odd = (zcr_len - j) % 2 != 0;
793 if (j == zcr_len) {
794 qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
795 } else if (!odd) {
796 if (j > 0) {
797 qemu_fprintf(f, " [%x-%x]=", j, j - 1);
798 } else {
799 qemu_fprintf(f, " [%x]=", j);
800 }
801 }
802 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
803 env->vfp.zregs[i].d[j * 2 + 1],
804 env->vfp.zregs[i].d[j * 2],
805 odd || j == 0 ? "\n" : ":");
806 }
807 }
808 }
809 } else {
810 for (i = 0; i < 32; i++) {
811 uint64_t *q = aa64_vfp_qreg(env, i);
812 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
813 i, q[1], q[0], (i & 1 ? "\n" : " "));
814 }
815 }
816}
817
818#else
819
820static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
821{
822 g_assert_not_reached();
823}
824
825#endif
826
827static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
828{
829 ARMCPU *cpu = ARM_CPU(cs);
830 CPUARMState *env = &cpu->env;
831 int i;
832
833 if (is_a64(env)) {
834 aarch64_cpu_dump_state(cs, f, flags);
835 return;
836 }
837
838 for (i = 0; i < 16; i++) {
839 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
840 if ((i % 4) == 3) {
841 qemu_fprintf(f, "\n");
842 } else {
843 qemu_fprintf(f, " ");
844 }
845 }
846
847 if (arm_feature(env, ARM_FEATURE_M)) {
848 uint32_t xpsr = xpsr_read(env);
849 const char *mode;
850 const char *ns_status = "";
851
852 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
853 ns_status = env->v7m.secure ? "S " : "NS ";
854 }
855
856 if (xpsr & XPSR_EXCP) {
857 mode = "handler";
858 } else {
859 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
860 mode = "unpriv-thread";
861 } else {
862 mode = "priv-thread";
863 }
864 }
865
866 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
867 xpsr,
868 xpsr & XPSR_N ? 'N' : '-',
869 xpsr & XPSR_Z ? 'Z' : '-',
870 xpsr & XPSR_C ? 'C' : '-',
871 xpsr & XPSR_V ? 'V' : '-',
872 xpsr & XPSR_T ? 'T' : 'A',
873 ns_status,
874 mode);
875 } else {
876 uint32_t psr = cpsr_read(env);
877 const char *ns_status = "";
878
879 if (arm_feature(env, ARM_FEATURE_EL3) &&
880 (psr & CPSR_M) != ARM_CPU_MODE_MON) {
881 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
882 }
883
884 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
885 psr,
886 psr & CPSR_N ? 'N' : '-',
887 psr & CPSR_Z ? 'Z' : '-',
888 psr & CPSR_C ? 'C' : '-',
889 psr & CPSR_V ? 'V' : '-',
890 psr & CPSR_T ? 'T' : 'A',
891 ns_status,
892 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
893 }
894
895 if (flags & CPU_DUMP_FPU) {
896 int numvfpregs = 0;
897 if (arm_feature(env, ARM_FEATURE_VFP)) {
898 numvfpregs += 16;
899 }
900 if (arm_feature(env, ARM_FEATURE_VFP3)) {
901 numvfpregs += 16;
902 }
903 for (i = 0; i < numvfpregs; i++) {
904 uint64_t v = *aa32_vfp_dreg(env, i);
905 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
906 i * 2, (uint32_t)v,
907 i * 2 + 1, (uint32_t)(v >> 32),
908 i, v);
909 }
910 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
911 }
912}
913
46de5913
IM		 914uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
915{
916 uint32_t Aff1 = idx / clustersz;
917 uint32_t Aff0 = idx % clustersz;
918 return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
919}
920
ac87e507
PM		 921static void cpreg_hashtable_data_destroy(gpointer data)
922{
923 /*
924 * Destroy function for cpu->cp_regs hashtable data entries.
925 * We must free the name string because it was g_strdup()ed in
926 * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
927 * from r->name because we know we definitely allocated it.
928 */
929 ARMCPRegInfo *r = data;
930
931 g_free((void *)r->name);
932 g_free(r);
933}
934
777dc784
PM		 935static void arm_cpu_initfn(Object *obj)
936{
937 ARMCPU *cpu = ARM_CPU(obj);
938
7506ed90 939 cpu_set_cpustate_pointers(cpu);
4b6a83fb 940 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
ac87e507 941 g_free, cpreg_hashtable_data_destroy);
79614b78 942
b5c53d1b 943 QLIST_INIT(&cpu->pre_el_change_hooks);
08267487
AL		 944 QLIST_INIT(&cpu->el_change_hooks);
945
7c1840b6
PM		 946#ifndef CONFIG_USER_ONLY
947 /* Our inbound IRQ and FIQ lines */
948 if (kvm_enabled()) {
136e67e9
EI		 949 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
950 * the same interface as non-KVM CPUs.
951 */
952 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
7c1840b6 953 } else {
136e67e9 954 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
7c1840b6 955 }
55d284af 956
55d284af
PM		 957 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
958 ARRAY_SIZE(cpu->gt_timer_outputs));
aa1b3111
PM		 959
960 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
961 "gicv3-maintenance-interrupt", 1);
07f48730
AJ		 962 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
963 "pmu-interrupt", 1);
7c1840b6
PM		 964#endif
965
54d3e3f5
PM		 966 /* DTB consumers generally don't in fact care what the 'compatible'
967 * string is, so always provide some string and trust that a hypothetical
968 * picky DTB consumer will also provide a helpful error message.
969 */
970 cpu->dtb_compatible = "qemu,unknown";
dd032e34 971 cpu->psci_version = 1; /* By default assume PSCI v0.1 */
3541addc 972 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
54d3e3f5 973
98128601
RH		 974 if (tcg_enabled()) {
975 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
79614b78 976 }
4b6a83fb
PM		 977}
978
07a5b0d2 979static Property arm_cpu_reset_cbar_property =
f318cec6 980 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
07a5b0d2 981
68e0a40a
AP		 982static Property arm_cpu_reset_hivecs_property =
983 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
984
3933443e
PM		 985static Property arm_cpu_rvbar_property =
986 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
987
c25bd18a
PM		 988static Property arm_cpu_has_el2_property =
989 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
990
51942aee
GB		 991static Property arm_cpu_has_el3_property =
992 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
993
3a062d57
JB		 994static Property arm_cpu_cfgend_property =
995 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
996
97a28b0e
PM		 997static Property arm_cpu_has_vfp_property =
998 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
999
1000static Property arm_cpu_has_neon_property =
1001 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
1002
ea90db0a
PM		 1003static Property arm_cpu_has_dsp_property =
1004 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true);
1005
8f325f56
PC		 1006static Property arm_cpu_has_mpu_property =
1007 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
1008
8d92e26b
PM		 1009/* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1010 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1011 * the right value for that particular CPU type, and we don't want
1012 * to override that with an incorrect constant value.
1013 */
3281af81 1014static Property arm_cpu_pmsav7_dregion_property =
8d92e26b
PM		 1015 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
1016 pmsav7_dregion,
1017 qdev_prop_uint32, uint32_t);
3281af81 1018
ae502508
AJ		 1019static bool arm_get_pmu(Object *obj, Error **errp)
1020{
1021 ARMCPU *cpu = ARM_CPU(obj);
1022
1023 return cpu->has_pmu;
1024}
1025
1026static void arm_set_pmu(Object *obj, bool value, Error **errp)
1027{
1028 ARMCPU *cpu = ARM_CPU(obj);
1029
1030 if (value) {
1031 if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu))) {
1032 error_setg(errp, "'pmu' feature not supported by KVM on this host");
1033 return;
1034 }
1035 set_feature(&cpu->env, ARM_FEATURE_PMU);
1036 } else {
1037 unset_feature(&cpu->env, ARM_FEATURE_PMU);
1038 }
1039 cpu->has_pmu = value;
1040}
1041
f9f62e4c
PM		 1042static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name,
1043 void *opaque, Error **errp)
1044{
1045 ARMCPU *cpu = ARM_CPU(obj);
1046
1047 visit_type_uint32(v, name, &cpu->init_svtor, errp);
1048}
1049
1050static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name,
1051 void *opaque, Error **errp)
1052{
1053 ARMCPU *cpu = ARM_CPU(obj);
1054
1055 visit_type_uint32(v, name, &cpu->init_svtor, errp);
1056}
38e2a77c 1057
51e5ef45 1058void arm_cpu_post_init(Object *obj)
07a5b0d2
PC		 1059{
1060 ARMCPU *cpu = ARM_CPU(obj);
07a5b0d2 1061
790a1150
PM		 1062 /* M profile implies PMSA. We have to do this here rather than
1063 * in realize with the other feature-implication checks because
1064 * we look at the PMSA bit to see if we should add some properties.
1065 */
1066 if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
1067 set_feature(&cpu->env, ARM_FEATURE_PMSA);
1068 }
97a28b0e
PM		 1069 /* Similarly for the VFP feature bits */
1070 if (arm_feature(&cpu->env, ARM_FEATURE_VFP4)) {
1071 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1072 }
1073 if (arm_feature(&cpu->env, ARM_FEATURE_VFP3)) {
1074 set_feature(&cpu->env, ARM_FEATURE_VFP);
1075 }
790a1150 1076
f318cec6
PM		 1077 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
1078 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
07a5b0d2 1079 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
5433a0a8 1080 &error_abort);
07a5b0d2 1081 }
68e0a40a
AP		 1082
1083 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
1084 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
5433a0a8 1085 &error_abort);
68e0a40a 1086 }
3933443e
PM		 1087
1088 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1089 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
1090 &error_abort);
1091 }
51942aee
GB		 1092
1093 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1094 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1095 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1096 */
1097 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
1098 &error_abort);
9e273ef2
PM		 1099
1100#ifndef CONFIG_USER_ONLY
1101 object_property_add_link(obj, "secure-memory",
1102 TYPE_MEMORY_REGION,
1103 (Object **)&cpu->secure_memory,
1104 qdev_prop_allow_set_link_before_realize,
265b578c 1105 OBJ_PROP_LINK_STRONG,
9e273ef2
PM		 1106 &error_abort);
1107#endif
51942aee 1108 }
8f325f56 1109
c25bd18a
PM		 1110 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
1111 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property,
1112 &error_abort);
1113 }
1114
929e754d 1115 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
ae502508
AJ		 1116 cpu->has_pmu = true;
1117 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu,
929e754d
WH		 1118 &error_abort);
1119 }
1120
97a28b0e
PM		 1121 /*
1122 * Allow user to turn off VFP and Neon support, but only for TCG --
1123 * KVM does not currently allow us to lie to the guest about its
1124 * ID/feature registers, so the guest always sees what the host has.
1125 */
1126 if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
1127 cpu->has_vfp = true;
1128 if (!kvm_enabled()) {
1129 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property,
1130 &error_abort);
1131 }
1132 }
1133
1134 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
1135 cpu->has_neon = true;
1136 if (!kvm_enabled()) {
1137 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property,
1138 &error_abort);
1139 }
1140 }
1141
ea90db0a
PM		 1142 if (arm_feature(&cpu->env, ARM_FEATURE_M) &&
1143 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) {
1144 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property,
1145 &error_abort);
1146 }
1147
452a0955 1148 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
8f325f56
PC		 1149 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
1150 &error_abort);
3281af81
PC		 1151 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1152 qdev_property_add_static(DEVICE(obj),
1153 &arm_cpu_pmsav7_dregion_property,
1154 &error_abort);
1155 }
8f325f56
PC		 1156 }
1157
181962fd
PM		 1158 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
1159 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
1160 qdev_prop_allow_set_link_before_realize,
265b578c 1161 OBJ_PROP_LINK_STRONG,
181962fd 1162 &error_abort);
f9f62e4c
PM		 1163 /*
1164 * M profile: initial value of the Secure VTOR. We can't just use
1165 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1166 * the property to be set after realize.
1167 */
1168 object_property_add(obj, "init-svtor", "uint32",
1169 arm_get_init_svtor, arm_set_init_svtor,
1170 NULL, NULL, &error_abort);
181962fd
PM		 1171 }
1172
3a062d57
JB		 1173 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
1174 &error_abort);
07a5b0d2
PC		 1175}
1176
4b6a83fb
PM		 1177static void arm_cpu_finalizefn(Object *obj)
1178{
1179 ARMCPU *cpu = ARM_CPU(obj);
08267487
AL		 1180 ARMELChangeHook *hook, *next;
1181
4b6a83fb 1182 g_hash_table_destroy(cpu->cp_regs);
08267487 1183
b5c53d1b
AL		 1184 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
1185 QLIST_REMOVE(hook, node);
1186 g_free(hook);
1187 }
08267487
AL		 1188 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
1189 QLIST_REMOVE(hook, node);
1190 g_free(hook);
1191 }
4e7beb0c
AL		 1192#ifndef CONFIG_USER_ONLY
1193 if (cpu->pmu_timer) {
1194 timer_del(cpu->pmu_timer);
1195 timer_deinit(cpu->pmu_timer);
1196 timer_free(cpu->pmu_timer);
1197 }
1198#endif
777dc784
PM		 1199}
1200
14969266 1201static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
581be094 1202{
14a10fc3 1203 CPUState *cs = CPU(dev);
14969266
AF		 1204 ARMCPU *cpu = ARM_CPU(dev);
1205 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
581be094 1206 CPUARMState *env = &cpu->env;
e97da98f 1207 int pagebits;
ce5b1bbf 1208 Error *local_err = NULL;
0f8d06f1 1209 bool no_aa32 = false;
ce5b1bbf 1210
c4487d76
PM		 1211 /* If we needed to query the host kernel for the CPU features
1212 * then it's possible that might have failed in the initfn, but
1213 * this is the first point where we can report it.
1214 */
1215 if (cpu->host_cpu_probe_failed) {
1216 if (!kvm_enabled()) {
1217 error_setg(errp, "The 'host' CPU type can only be used with KVM");
1218 } else {
1219 error_setg(errp, "Failed to retrieve host CPU features");
1220 }
1221 return;
1222 }
1223
95f87565
PM		 1224#ifndef CONFIG_USER_ONLY
1225 /* The NVIC and M-profile CPU are two halves of a single piece of
1226 * hardware; trying to use one without the other is a command line
1227 * error and will result in segfaults if not caught here.
1228 */
1229 if (arm_feature(env, ARM_FEATURE_M)) {
1230 if (!env->nvic) {
1231 error_setg(errp, "This board cannot be used with Cortex-M CPUs");
1232 return;
1233 }
1234 } else {
1235 if (env->nvic) {
1236 error_setg(errp, "This board can only be used with Cortex-M CPUs");
1237 return;
1238 }
1239 }
397cd31f
PM		 1240
1241 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
1242 arm_gt_ptimer_cb, cpu);
1243 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
1244 arm_gt_vtimer_cb, cpu);
1245 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
1246 arm_gt_htimer_cb, cpu);
1247 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
1248 arm_gt_stimer_cb, cpu);
95f87565
PM		 1249#endif
1250
ce5b1bbf
LV		 1251 cpu_exec_realizefn(cs, &local_err);
1252 if (local_err != NULL) {
1253 error_propagate(errp, local_err);
1254 return;
1255 }
14969266 1256
97a28b0e
PM		 1257 if (arm_feature(env, ARM_FEATURE_AARCH64) &&
1258 cpu->has_vfp != cpu->has_neon) {
1259 /*
1260 * This is an architectural requirement for AArch64; AArch32 is
1261 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1262 */
1263 error_setg(errp,
1264 "AArch64 CPUs must have both VFP and Neon or neither");
1265 return;
1266 }
1267
1268 if (!cpu->has_vfp) {
1269 uint64_t t;
1270 uint32_t u;
1271
1272 unset_feature(env, ARM_FEATURE_VFP);
1273 unset_feature(env, ARM_FEATURE_VFP3);
1274 unset_feature(env, ARM_FEATURE_VFP4);
1275
1276 t = cpu->isar.id_aa64isar1;
1277 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
1278 cpu->isar.id_aa64isar1 = t;
1279
1280 t = cpu->isar.id_aa64pfr0;
1281 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
1282 cpu->isar.id_aa64pfr0 = t;
1283
1284 u = cpu->isar.id_isar6;
1285 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
1286 cpu->isar.id_isar6 = u;
1287
1288 u = cpu->isar.mvfr0;
1289 u = FIELD_DP32(u, MVFR0, FPSP, 0);
1290 u = FIELD_DP32(u, MVFR0, FPDP, 0);
1291 u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
1292 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0);
1293 u = FIELD_DP32(u, MVFR0, FPSQRT, 0);
1294 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
1295 u = FIELD_DP32(u, MVFR0, FPROUND, 0);
1296 cpu->isar.mvfr0 = u;
1297
1298 u = cpu->isar.mvfr1;
1299 u = FIELD_DP32(u, MVFR1, FPFTZ, 0);
1300 u = FIELD_DP32(u, MVFR1, FPDNAN, 0);
1301 u = FIELD_DP32(u, MVFR1, FPHP, 0);
1302 cpu->isar.mvfr1 = u;
1303
1304 u = cpu->isar.mvfr2;
1305 u = FIELD_DP32(u, MVFR2, FPMISC, 0);
1306 cpu->isar.mvfr2 = u;
1307 }
1308
1309 if (!cpu->has_neon) {
1310 uint64_t t;
1311 uint32_t u;
1312
1313 unset_feature(env, ARM_FEATURE_NEON);
1314
1315 t = cpu->isar.id_aa64isar0;
1316 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
1317 cpu->isar.id_aa64isar0 = t;
1318
1319 t = cpu->isar.id_aa64isar1;
1320 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
1321 cpu->isar.id_aa64isar1 = t;
1322
1323 t = cpu->isar.id_aa64pfr0;
1324 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
1325 cpu->isar.id_aa64pfr0 = t;
1326
1327 u = cpu->isar.id_isar5;
1328 u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
1329 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
1330 cpu->isar.id_isar5 = u;
1331
1332 u = cpu->isar.id_isar6;
1333 u = FIELD_DP32(u, ID_ISAR6, DP, 0);
1334 u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
1335 cpu->isar.id_isar6 = u;
1336
1337 u = cpu->isar.mvfr1;
1338 u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
1339 u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
1340 u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
1341 u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
1342 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
1343 cpu->isar.mvfr1 = u;
1344
1345 u = cpu->isar.mvfr2;
1346 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
1347 cpu->isar.mvfr2 = u;
1348 }
1349
1350 if (!cpu->has_neon && !cpu->has_vfp) {
1351 uint64_t t;
1352 uint32_t u;
1353
1354 t = cpu->isar.id_aa64isar0;
1355 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0);
1356 cpu->isar.id_aa64isar0 = t;
1357
1358 t = cpu->isar.id_aa64isar1;
1359 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0);
1360 cpu->isar.id_aa64isar1 = t;
1361
1362 u = cpu->isar.mvfr0;
1363 u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
1364 cpu->isar.mvfr0 = u;
1365 }
1366
ea90db0a
PM		 1367 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) {
1368 uint32_t u;
1369
1370 unset_feature(env, ARM_FEATURE_THUMB_DSP);
1371
1372 u = cpu->isar.id_isar1;
1373 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1);
1374 cpu->isar.id_isar1 = u;
1375
1376 u = cpu->isar.id_isar2;
1377 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1);
1378 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1);
1379 cpu->isar.id_isar2 = u;
1380
1381 u = cpu->isar.id_isar3;
1382 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1);
1383 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0);
1384 cpu->isar.id_isar3 = u;
1385 }
1386
581be094 1387 /* Some features automatically imply others: */
81e69fb0 1388 if (arm_feature(env, ARM_FEATURE_V8)) {
5256df88
RH		 1389 if (arm_feature(env, ARM_FEATURE_M)) {
1390 set_feature(env, ARM_FEATURE_V7);
1391 } else {
1392 set_feature(env, ARM_FEATURE_V7VE);
1393 }
5110e683 1394 }
0f8d06f1
RH		 1395
1396 /*
1397 * There exist AArch64 cpus without AArch32 support. When KVM
1398 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1399 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
8f4821d7
PM		 1400 * As a general principle, we also do not make ID register
1401 * consistency checks anywhere unless using TCG, because only
1402 * for TCG would a consistency-check failure be a QEMU bug.
0f8d06f1
RH		 1403 */
1404 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1405 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
1406 }
1407
5110e683
AL		 1408 if (arm_feature(env, ARM_FEATURE_V7VE)) {
1409 /* v7 Virtualization Extensions. In real hardware this implies
1410 * EL2 and also the presence of the Security Extensions.
1411 * For QEMU, for backwards-compatibility we implement some
1412 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1413 * include the various other features that V7VE implies.
1414 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1415 * Security Extensions is ARM_FEATURE_EL3.
1416 */
8f4821d7 1417 assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu));
81e69fb0 1418 set_feature(env, ARM_FEATURE_LPAE);
5110e683 1419 set_feature(env, ARM_FEATURE_V7);
81e69fb0 1420 }
581be094
PM		 1421 if (arm_feature(env, ARM_FEATURE_V7)) {
1422 set_feature(env, ARM_FEATURE_VAPA);
1423 set_feature(env, ARM_FEATURE_THUMB2);
81bdde9d 1424 set_feature(env, ARM_FEATURE_MPIDR);
581be094
PM		 1425 if (!arm_feature(env, ARM_FEATURE_M)) {
1426 set_feature(env, ARM_FEATURE_V6K);
1427 } else {
1428 set_feature(env, ARM_FEATURE_V6);
1429 }
91db4642
CLG		 1430
1431 /* Always define VBAR for V7 CPUs even if it doesn't exist in
1432 * non-EL3 configs. This is needed by some legacy boards.
1433 */
1434 set_feature(env, ARM_FEATURE_VBAR);
581be094
PM		 1435 }
1436 if (arm_feature(env, ARM_FEATURE_V6K)) {
1437 set_feature(env, ARM_FEATURE_V6);
1438 set_feature(env, ARM_FEATURE_MVFR);
1439 }
1440 if (arm_feature(env, ARM_FEATURE_V6)) {
1441 set_feature(env, ARM_FEATURE_V5);
1442 if (!arm_feature(env, ARM_FEATURE_M)) {
8f4821d7 1443 assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle, cpu));
581be094
PM		 1444 set_feature(env, ARM_FEATURE_AUXCR);
1445 }
1446 }
1447 if (arm_feature(env, ARM_FEATURE_V5)) {
1448 set_feature(env, ARM_FEATURE_V4T);
1449 }
de9b05b8 1450 if (arm_feature(env, ARM_FEATURE_LPAE)) {
bdcc150d 1451 set_feature(env, ARM_FEATURE_V7MP);
de9b05b8
PM		 1452 set_feature(env, ARM_FEATURE_PXN);
1453 }
f318cec6
PM		 1454 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
1455 set_feature(env, ARM_FEATURE_CBAR);
1456 }
62b44f05
AR		 1457 if (arm_feature(env, ARM_FEATURE_THUMB2) &&
1458 !arm_feature(env, ARM_FEATURE_M)) {
1459 set_feature(env, ARM_FEATURE_THUMB_DSP);
1460 }
2ceb98c0 1461
ea7ac69d
PM		 1462 /*
1463 * We rely on no XScale CPU having VFP so we can use the same bits in the
1464 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1465 */
1466 assert(!(arm_feature(env, ARM_FEATURE_VFP) &&
1467 arm_feature(env, ARM_FEATURE_XSCALE)));
1468
e97da98f
PM		 1469 if (arm_feature(env, ARM_FEATURE_V7) &&
1470 !arm_feature(env, ARM_FEATURE_M) &&
452a0955 1471 !arm_feature(env, ARM_FEATURE_PMSA)) {
e97da98f
PM		 1472 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1473 * can use 4K pages.
1474 */
1475 pagebits = 12;
1476 } else {
1477 /* For CPUs which might have tiny 1K pages, or which have an
1478 * MPU and might have small region sizes, stick with 1K pages.
1479 */
1480 pagebits = 10;
1481 }
1482 if (!set_preferred_target_page_bits(pagebits)) {
1483 /* This can only ever happen for hotplugging a CPU, or if
1484 * the board code incorrectly creates a CPU which it has
1485 * promised via minimum_page_size that it will not.
1486 */
1487 error_setg(errp, "This CPU requires a smaller page size than the "
1488 "system is using");
1489 return;
1490 }
1491
ce5b1bbf
LV		 1492 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1493 * We don't support setting cluster ID ([16..23]) (known as Aff2
1494 * in later ARM ARM versions), or any of the higher affinity level fields,
1495 * so these bits always RAZ.
1496 */
1497 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
46de5913
IM		 1498 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index,
1499 ARM_DEFAULT_CPUS_PER_CLUSTER);
ce5b1bbf
LV		 1500 }
1501
68e0a40a
AP		 1502 if (cpu->reset_hivecs) {
1503 cpu->reset_sctlr |= (1 << 13);
1504 }
1505
3a062d57
JB		 1506 if (cpu->cfgend) {
1507 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1508 cpu->reset_sctlr |= SCTLR_EE;
1509 } else {
1510 cpu->reset_sctlr |= SCTLR_B;
1511 }
1512 }
1513
51942aee
GB		 1514 if (!cpu->has_el3) {
1515 /* If the has_el3 CPU property is disabled then we need to disable the
1516 * feature.
1517 */
1518 unset_feature(env, ARM_FEATURE_EL3);
1519
1520 /* Disable the security extension feature bits in the processor feature
3d5c84ff 1521 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
51942aee
GB		 1522 */
1523 cpu->id_pfr1 &= ~0xf0;
47576b94 1524 cpu->isar.id_aa64pfr0 &= ~0xf000;
51942aee
GB		 1525 }
1526
c25bd18a
PM		 1527 if (!cpu->has_el2) {
1528 unset_feature(env, ARM_FEATURE_EL2);
1529 }
1530
d6f02ce3 1531 if (!cpu->has_pmu) {
929e754d 1532 unset_feature(env, ARM_FEATURE_PMU);
57a4a11b
AL		 1533 }
1534 if (arm_feature(env, ARM_FEATURE_PMU)) {
bf8d0969 1535 pmu_init(cpu);
57a4a11b
AL		 1536
1537 if (!kvm_enabled()) {
1538 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
1539 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
1540 }
4e7beb0c
AL		 1541
1542#ifndef CONFIG_USER_ONLY
1543 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
1544 cpu);
1545#endif
57a4a11b 1546 } else {
2b3ffa92 1547 cpu->id_aa64dfr0 &= ~0xf00;
a46118fc 1548 cpu->id_dfr0 &= ~(0xf << 24);
57a4a11b
AL		 1549 cpu->pmceid0 = 0;
1550 cpu->pmceid1 = 0;
929e754d
WH		 1551 }
1552
3c2f7bb3
PM		 1553 if (!arm_feature(env, ARM_FEATURE_EL2)) {
1554 /* Disable the hypervisor feature bits in the processor feature
1555 * registers if we don't have EL2. These are id_pfr1[15:12] and
1556 * id_aa64pfr0_el1[11:8].
1557 */
47576b94 1558 cpu->isar.id_aa64pfr0 &= ~0xf00;
3c2f7bb3
PM		 1559 cpu->id_pfr1 &= ~0xf000;
1560 }
1561
f50cd314
PM		 1562 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1563 * to false or by setting pmsav7-dregion to 0.
1564 */
8f325f56 1565 if (!cpu->has_mpu) {
f50cd314
PM		 1566 cpu->pmsav7_dregion = 0;
1567 }
1568 if (cpu->pmsav7_dregion == 0) {
1569 cpu->has_mpu = false;
8f325f56
PC		 1570 }
1571
452a0955 1572 if (arm_feature(env, ARM_FEATURE_PMSA) &&
3281af81
PC		 1573 arm_feature(env, ARM_FEATURE_V7)) {
1574 uint32_t nr = cpu->pmsav7_dregion;
1575
1576 if (nr > 0xff) {
9af9e0fe 1577 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
3281af81
PC		 1578 return;
1579 }
6cb0b013
PC		 1580
1581 if (nr) {
0e1a46bb
PM		 1582 if (arm_feature(env, ARM_FEATURE_V8)) {
1583 /* PMSAv8 */
62c58ee0
PM		 1584 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
1585 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
1586 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1587 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
1588 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
1589 }
0e1a46bb
PM		 1590 } else {
1591 env->pmsav7.drbar = g_new0(uint32_t, nr);
1592 env->pmsav7.drsr = g_new0(uint32_t, nr);
1593 env->pmsav7.dracr = g_new0(uint32_t, nr);
1594 }
6cb0b013 1595 }
3281af81
PC		 1596 }
1597
9901c576
PM		 1598 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1599 uint32_t nr = cpu->sau_sregion;
1600
1601 if (nr > 0xff) {
1602 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
1603 return;
1604 }
1605
1606 if (nr) {
1607 env->sau.rbar = g_new0(uint32_t, nr);
1608 env->sau.rlar = g_new0(uint32_t, nr);
1609 }
1610 }
1611
91db4642
CLG		 1612 if (arm_feature(env, ARM_FEATURE_EL3)) {
1613 set_feature(env, ARM_FEATURE_VBAR);
1614 }
1615
2ceb98c0 1616 register_cp_regs_for_features(cpu);
14969266
AF		 1617 arm_cpu_register_gdb_regs_for_features(cpu);
1618
721fae12
PM		 1619 init_cpreg_list(cpu);
1620
9e273ef2 1621#ifndef CONFIG_USER_ONLY
cc7d44c2
LX		 1622 MachineState *ms = MACHINE(qdev_get_machine());
1623 unsigned int smp_cpus = ms->smp.cpus;
1624
1d2091bc 1625 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1d2091bc
PM		 1626 cs->num_ases = 2;
1627
9e273ef2
PM		 1628 if (!cpu->secure_memory) {
1629 cpu->secure_memory = cs->memory;
1630 }
80ceb07a
PX		 1631 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
1632 cpu->secure_memory);
1d2091bc
PM		 1633 } else {
1634 cs->num_ases = 1;
9e273ef2 1635 }
80ceb07a 1636 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
f9a69711
AF		 1637
1638 /* No core_count specified, default to smp_cpus. */
1639 if (cpu->core_count == -1) {
1640 cpu->core_count = smp_cpus;
1641 }
9e273ef2
PM		 1642#endif
1643
14a10fc3 1644 qemu_init_vcpu(cs);
00d0f7cb 1645 cpu_reset(cs);
14969266
AF		 1646
1647 acc->parent_realize(dev, errp);
581be094
PM		 1648}
1649
5900d6b2
AF		 1650static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
1651{
1652 ObjectClass *oc;
51492fd1 1653 char *typename;
fb8d6c24 1654 char **cpuname;
a0032cc5 1655 const char *cpunamestr;
5900d6b2 1656
fb8d6c24 1657 cpuname = g_strsplit(cpu_model, ",", 1);
a0032cc5
PM		 1658 cpunamestr = cpuname[0];
1659#ifdef CONFIG_USER_ONLY
1660 /* For backwards compatibility usermode emulation allows "-cpu any",
1661 * which has the same semantics as "-cpu max".
1662 */
1663 if (!strcmp(cpunamestr, "any")) {
1664 cpunamestr = "max";
1665 }
1666#endif
1667 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
51492fd1 1668 oc = object_class_by_name(typename);
fb8d6c24 1669 g_strfreev(cpuname);
51492fd1 1670 g_free(typename);
245fb54d
AF		 1671 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
1672 object_class_is_abstract(oc)) {
5900d6b2
AF		 1673 return NULL;
1674 }
1675 return oc;
1676}
1677
15ee776b
PM		 1678/* CPU models. These are not needed for the AArch64 linux-user build. */
1679#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1680
777dc784
PM		 1681static void arm926_initfn(Object *obj)
1682{
1683 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 1684
1685 cpu->dtb_compatible = "arm,arm926";
581be094
PM		 1686 set_feature(&cpu->env, ARM_FEATURE_V5);
1687 set_feature(&cpu->env, ARM_FEATURE_VFP);
c4804214
PM		 1688 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1689 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
b2d06f96 1690 cpu->midr = 0x41069265;
325b3cef 1691 cpu->reset_fpsid = 0x41011090;
64e1671f 1692 cpu->ctr = 0x1dd20d2;
0ca7e01c 1693 cpu->reset_sctlr = 0x00090078;
09cbd501
RH		 1694
1695 /*
1696 * ARMv5 does not have the ID_ISAR registers, but we can still
1697 * set the field to indicate Jazelle support within QEMU.
1698 */
1699 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
cb7cef8b
PM		 1700 /*
1701 * Similarly, we need to set MVFR0 fields to enable double precision
1702 * and short vector support even though ARMv5 doesn't have this register.
1703 */
1704 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
1705 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
777dc784
PM		 1706}
1707
1708static void arm946_initfn(Object *obj)
1709{
1710 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 1711
1712 cpu->dtb_compatible = "arm,arm946";
581be094 1713 set_feature(&cpu->env, ARM_FEATURE_V5);
452a0955 1714 set_feature(&cpu->env, ARM_FEATURE_PMSA);
c4804214 1715 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
b2d06f96 1716 cpu->midr = 0x41059461;
64e1671f 1717 cpu->ctr = 0x0f004006;
0ca7e01c 1718 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 1719}
1720
1721static void arm1026_initfn(Object *obj)
1722{
1723 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 1724
1725 cpu->dtb_compatible = "arm,arm1026";
581be094
PM		 1726 set_feature(&cpu->env, ARM_FEATURE_V5);
1727 set_feature(&cpu->env, ARM_FEATURE_VFP);
1728 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
c4804214
PM		 1729 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1730 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
b2d06f96 1731 cpu->midr = 0x4106a262;
325b3cef 1732 cpu->reset_fpsid = 0x410110a0;
64e1671f 1733 cpu->ctr = 0x1dd20d2;
0ca7e01c 1734 cpu->reset_sctlr = 0x00090078;
2771db27 1735 cpu->reset_auxcr = 1;
09cbd501
RH		 1736
1737 /*
1738 * ARMv5 does not have the ID_ISAR registers, but we can still
1739 * set the field to indicate Jazelle support within QEMU.
1740 */
1741 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
cb7cef8b
PM		 1742 /*
1743 * Similarly, we need to set MVFR0 fields to enable double precision
1744 * and short vector support even though ARMv5 doesn't have this register.
1745 */
1746 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
1747 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
09cbd501 1748
06d76f31
PM		 1749 {
1750 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
1751 ARMCPRegInfo ifar = {
1752 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
1753 .access = PL1_RW,
b848ce2b 1754 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
06d76f31
PM		 1755 .resetvalue = 0
1756 };
1757 define_one_arm_cp_reg(cpu, &ifar);
1758 }
777dc784
PM		 1759}
1760
1761static void arm1136_r2_initfn(Object *obj)
1762{
1763 ARMCPU *cpu = ARM_CPU(obj);
2e4d7e3e
PM		 1764 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1765 * older core than plain "arm1136". In particular this does not
1766 * have the v6K features.
1767 * These ID register values are correct for 1136 but may be wrong
1768 * for 1136_r2 (in particular r0p2 does not actually implement most
1769 * of the ID registers).
1770 */
54d3e3f5
PM		 1771
1772 cpu->dtb_compatible = "arm,arm1136";
581be094
PM		 1773 set_feature(&cpu->env, ARM_FEATURE_V6);
1774 set_feature(&cpu->env, ARM_FEATURE_VFP);
c4804214
PM		 1775 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1776 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1777 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
b2d06f96 1778 cpu->midr = 0x4107b362;
325b3cef 1779 cpu->reset_fpsid = 0x410120b4;
47576b94
RH		 1780 cpu->isar.mvfr0 = 0x11111111;
1781 cpu->isar.mvfr1 = 0x00000000;
64e1671f 1782 cpu->ctr = 0x1dd20d2;
0ca7e01c 1783 cpu->reset_sctlr = 0x00050078;
2e4d7e3e
PM		 1784 cpu->id_pfr0 = 0x111;
1785 cpu->id_pfr1 = 0x1;
1786 cpu->id_dfr0 = 0x2;
1787 cpu->id_afr0 = 0x3;
1788 cpu->id_mmfr0 = 0x01130003;
1789 cpu->id_mmfr1 = 0x10030302;
1790 cpu->id_mmfr2 = 0x01222110;
47576b94
RH		 1791 cpu->isar.id_isar0 = 0x00140011;
1792 cpu->isar.id_isar1 = 0x12002111;
1793 cpu->isar.id_isar2 = 0x11231111;
1794 cpu->isar.id_isar3 = 0x01102131;
1795 cpu->isar.id_isar4 = 0x141;
2771db27 1796 cpu->reset_auxcr = 7;
777dc784
PM		 1797}
1798
1799static void arm1136_initfn(Object *obj)
1800{
1801 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 1802
1803 cpu->dtb_compatible = "arm,arm1136";
581be094
PM		 1804 set_feature(&cpu->env, ARM_FEATURE_V6K);
1805 set_feature(&cpu->env, ARM_FEATURE_V6);
1806 set_feature(&cpu->env, ARM_FEATURE_VFP);
c4804214
PM		 1807 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1808 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1809 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
b2d06f96 1810 cpu->midr = 0x4117b363;
325b3cef 1811 cpu->reset_fpsid = 0x410120b4;
47576b94
RH		 1812 cpu->isar.mvfr0 = 0x11111111;
1813 cpu->isar.mvfr1 = 0x00000000;
64e1671f 1814 cpu->ctr = 0x1dd20d2;
0ca7e01c 1815 cpu->reset_sctlr = 0x00050078;
2e4d7e3e
PM		 1816 cpu->id_pfr0 = 0x111;
1817 cpu->id_pfr1 = 0x1;
1818 cpu->id_dfr0 = 0x2;
1819 cpu->id_afr0 = 0x3;
1820 cpu->id_mmfr0 = 0x01130003;
1821 cpu->id_mmfr1 = 0x10030302;
1822 cpu->id_mmfr2 = 0x01222110;
47576b94
RH		 1823 cpu->isar.id_isar0 = 0x00140011;
1824 cpu->isar.id_isar1 = 0x12002111;
1825 cpu->isar.id_isar2 = 0x11231111;
1826 cpu->isar.id_isar3 = 0x01102131;
1827 cpu->isar.id_isar4 = 0x141;
2771db27 1828 cpu->reset_auxcr = 7;
777dc784
PM		 1829}
1830
1831static void arm1176_initfn(Object *obj)
1832{
1833 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 1834
1835 cpu->dtb_compatible = "arm,arm1176";
581be094
PM		 1836 set_feature(&cpu->env, ARM_FEATURE_V6K);
1837 set_feature(&cpu->env, ARM_FEATURE_VFP);
1838 set_feature(&cpu->env, ARM_FEATURE_VAPA);
c4804214
PM		 1839 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1840 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1841 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
c0ccb02d 1842 set_feature(&cpu->env, ARM_FEATURE_EL3);
b2d06f96 1843 cpu->midr = 0x410fb767;
325b3cef 1844 cpu->reset_fpsid = 0x410120b5;
47576b94
RH		 1845 cpu->isar.mvfr0 = 0x11111111;
1846 cpu->isar.mvfr1 = 0x00000000;
64e1671f 1847 cpu->ctr = 0x1dd20d2;
0ca7e01c 1848 cpu->reset_sctlr = 0x00050078;
2e4d7e3e
PM		 1849 cpu->id_pfr0 = 0x111;
1850 cpu->id_pfr1 = 0x11;
1851 cpu->id_dfr0 = 0x33;
1852 cpu->id_afr0 = 0;
1853 cpu->id_mmfr0 = 0x01130003;
1854 cpu->id_mmfr1 = 0x10030302;
1855 cpu->id_mmfr2 = 0x01222100;
47576b94
RH		 1856 cpu->isar.id_isar0 = 0x0140011;
1857 cpu->isar.id_isar1 = 0x12002111;
1858 cpu->isar.id_isar2 = 0x11231121;
1859 cpu->isar.id_isar3 = 0x01102131;
1860 cpu->isar.id_isar4 = 0x01141;
2771db27 1861 cpu->reset_auxcr = 7;
777dc784
PM		 1862}
1863
1864static void arm11mpcore_initfn(Object *obj)
1865{
1866 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 1867
1868 cpu->dtb_compatible = "arm,arm11mpcore";
581be094
PM		 1869 set_feature(&cpu->env, ARM_FEATURE_V6K);
1870 set_feature(&cpu->env, ARM_FEATURE_VFP);
1871 set_feature(&cpu->env, ARM_FEATURE_VAPA);
81bdde9d 1872 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
c4804214 1873 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
b2d06f96 1874 cpu->midr = 0x410fb022;
325b3cef 1875 cpu->reset_fpsid = 0x410120b4;
47576b94
RH		 1876 cpu->isar.mvfr0 = 0x11111111;
1877 cpu->isar.mvfr1 = 0x00000000;
200bf596 1878 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
2e4d7e3e
PM		 1879 cpu->id_pfr0 = 0x111;
1880 cpu->id_pfr1 = 0x1;
1881 cpu->id_dfr0 = 0;
1882 cpu->id_afr0 = 0x2;
1883 cpu->id_mmfr0 = 0x01100103;
1884 cpu->id_mmfr1 = 0x10020302;
1885 cpu->id_mmfr2 = 0x01222000;
47576b94
RH		 1886 cpu->isar.id_isar0 = 0x00100011;
1887 cpu->isar.id_isar1 = 0x12002111;
1888 cpu->isar.id_isar2 = 0x11221011;
1889 cpu->isar.id_isar3 = 0x01102131;
1890 cpu->isar.id_isar4 = 0x141;
2771db27 1891 cpu->reset_auxcr = 1;
777dc784
PM		 1892}
1893
191776b9
SH		 1894static void cortex_m0_initfn(Object *obj)
1895{
1896 ARMCPU *cpu = ARM_CPU(obj);
1897 set_feature(&cpu->env, ARM_FEATURE_V6);
1898 set_feature(&cpu->env, ARM_FEATURE_M);
1899
1900 cpu->midr = 0x410cc200;
1901}
1902
777dc784
PM		 1903static void cortex_m3_initfn(Object *obj)
1904{
1905 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 1906 set_feature(&cpu->env, ARM_FEATURE_V7);
1907 set_feature(&cpu->env, ARM_FEATURE_M);
cc2ae7c9 1908 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
b2d06f96 1909 cpu->midr = 0x410fc231;
8d92e26b 1910 cpu->pmsav7_dregion = 8;
5a53e2c1
PM		 1911 cpu->id_pfr0 = 0x00000030;
1912 cpu->id_pfr1 = 0x00000200;
1913 cpu->id_dfr0 = 0x00100000;
1914 cpu->id_afr0 = 0x00000000;
1915 cpu->id_mmfr0 = 0x00000030;
1916 cpu->id_mmfr1 = 0x00000000;
1917 cpu->id_mmfr2 = 0x00000000;
1918 cpu->id_mmfr3 = 0x00000000;
47576b94
RH		 1919 cpu->isar.id_isar0 = 0x01141110;
1920 cpu->isar.id_isar1 = 0x02111000;
1921 cpu->isar.id_isar2 = 0x21112231;
1922 cpu->isar.id_isar3 = 0x01111110;
1923 cpu->isar.id_isar4 = 0x01310102;
1924 cpu->isar.id_isar5 = 0x00000000;
1925 cpu->isar.id_isar6 = 0x00000000;
777dc784
PM		 1926}
1927
ba890a9b
AR		 1928static void cortex_m4_initfn(Object *obj)
1929{
1930 ARMCPU *cpu = ARM_CPU(obj);
1931
1932 set_feature(&cpu->env, ARM_FEATURE_V7);
1933 set_feature(&cpu->env, ARM_FEATURE_M);
cc2ae7c9 1934 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
ba890a9b 1935 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
14fd0c31 1936 set_feature(&cpu->env, ARM_FEATURE_VFP4);
ba890a9b 1937 cpu->midr = 0x410fc240; /* r0p0 */
8d92e26b 1938 cpu->pmsav7_dregion = 8;
14fd0c31
PM		 1939 cpu->isar.mvfr0 = 0x10110021;
1940 cpu->isar.mvfr1 = 0x11000011;
1941 cpu->isar.mvfr2 = 0x00000000;
5a53e2c1
PM		 1942 cpu->id_pfr0 = 0x00000030;
1943 cpu->id_pfr1 = 0x00000200;
1944 cpu->id_dfr0 = 0x00100000;
1945 cpu->id_afr0 = 0x00000000;
1946 cpu->id_mmfr0 = 0x00000030;
1947 cpu->id_mmfr1 = 0x00000000;
1948 cpu->id_mmfr2 = 0x00000000;
1949 cpu->id_mmfr3 = 0x00000000;
47576b94
RH		 1950 cpu->isar.id_isar0 = 0x01141110;
1951 cpu->isar.id_isar1 = 0x02111000;
1952 cpu->isar.id_isar2 = 0x21112231;
1953 cpu->isar.id_isar3 = 0x01111110;
1954 cpu->isar.id_isar4 = 0x01310102;
1955 cpu->isar.id_isar5 = 0x00000000;
1956 cpu->isar.id_isar6 = 0x00000000;
ba890a9b 1957}
9901c576 1958
c7b26382
PM		 1959static void cortex_m33_initfn(Object *obj)
1960{
1961 ARMCPU *cpu = ARM_CPU(obj);
1962
1963 set_feature(&cpu->env, ARM_FEATURE_V8);
1964 set_feature(&cpu->env, ARM_FEATURE_M);
cc2ae7c9 1965 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
c7b26382
PM		 1966 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
1967 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
14fd0c31 1968 set_feature(&cpu->env, ARM_FEATURE_VFP4);
c7b26382
PM		 1969 cpu->midr = 0x410fd213; /* r0p3 */
1970 cpu->pmsav7_dregion = 16;
1971 cpu->sau_sregion = 8;
14fd0c31
PM		 1972 cpu->isar.mvfr0 = 0x10110021;
1973 cpu->isar.mvfr1 = 0x11000011;
1974 cpu->isar.mvfr2 = 0x00000040;
c7b26382
PM		 1975 cpu->id_pfr0 = 0x00000030;
1976 cpu->id_pfr1 = 0x00000210;
1977 cpu->id_dfr0 = 0x00200000;
1978 cpu->id_afr0 = 0x00000000;
1979 cpu->id_mmfr0 = 0x00101F40;
1980 cpu->id_mmfr1 = 0x00000000;
1981 cpu->id_mmfr2 = 0x01000000;
1982 cpu->id_mmfr3 = 0x00000000;
47576b94
RH		 1983 cpu->isar.id_isar0 = 0x01101110;
1984 cpu->isar.id_isar1 = 0x02212000;
1985 cpu->isar.id_isar2 = 0x20232232;
1986 cpu->isar.id_isar3 = 0x01111131;
1987 cpu->isar.id_isar4 = 0x01310132;
1988 cpu->isar.id_isar5 = 0x00000000;
1989 cpu->isar.id_isar6 = 0x00000000;
c7b26382
PM		 1990 cpu->clidr = 0x00000000;
1991 cpu->ctr = 0x8000c000;
1992}
1993
e6f010cc
AF		 1994static void arm_v7m_class_init(ObjectClass *oc, void *data)
1995{
51e5ef45 1996 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
e6f010cc
AF		 1997 CPUClass *cc = CPU_CLASS(oc);
1998
51e5ef45 1999 acc->info = data;
b5c633c5 2000#ifndef CONFIG_USER_ONLY
e6f010cc
AF		 2001 cc->do_interrupt = arm_v7m_cpu_do_interrupt;
2002#endif
b5c633c5
PM		 2003
2004 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
e6f010cc
AF		 2005}
2006
d6a6b13e
PC		 2007static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
2008 /* Dummy the TCM region regs for the moment */
2009 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
2010 .access = PL1_RW, .type = ARM_CP_CONST },
2011 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
2012 .access = PL1_RW, .type = ARM_CP_CONST },
95e9a242
LM		 2013 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
2014 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
d6a6b13e
PC		 2015 REGINFO_SENTINEL
2016};
2017
2018static void cortex_r5_initfn(Object *obj)
2019{
2020 ARMCPU *cpu = ARM_CPU(obj);
2021
2022 set_feature(&cpu->env, ARM_FEATURE_V7);
d6a6b13e 2023 set_feature(&cpu->env, ARM_FEATURE_V7MP);
452a0955 2024 set_feature(&cpu->env, ARM_FEATURE_PMSA);
d6a6b13e
PC		 2025 cpu->midr = 0x411fc153; /* r1p3 */
2026 cpu->id_pfr0 = 0x0131;
2027 cpu->id_pfr1 = 0x001;
2028 cpu->id_dfr0 = 0x010400;
2029 cpu->id_afr0 = 0x0;
2030 cpu->id_mmfr0 = 0x0210030;
2031 cpu->id_mmfr1 = 0x00000000;
2032 cpu->id_mmfr2 = 0x01200000;
2033 cpu->id_mmfr3 = 0x0211;
47576b94
RH		 2034 cpu->isar.id_isar0 = 0x02101111;
2035 cpu->isar.id_isar1 = 0x13112111;
2036 cpu->isar.id_isar2 = 0x21232141;
2037 cpu->isar.id_isar3 = 0x01112131;
2038 cpu->isar.id_isar4 = 0x0010142;
2039 cpu->isar.id_isar5 = 0x0;
2040 cpu->isar.id_isar6 = 0x0;
d6a6b13e 2041 cpu->mp_is_up = true;
8d92e26b 2042 cpu->pmsav7_dregion = 16;
d6a6b13e
PC		 2043 define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
2044}
2045
ebac5458
EI		 2046static void cortex_r5f_initfn(Object *obj)
2047{
2048 ARMCPU *cpu = ARM_CPU(obj);
2049
2050 cortex_r5_initfn(obj);
2051 set_feature(&cpu->env, ARM_FEATURE_VFP3);
3de79d33
PM		 2052 cpu->isar.mvfr0 = 0x10110221;
2053 cpu->isar.mvfr1 = 0x00000011;
ebac5458
EI		 2054}
2055
34f90529
PM		 2056static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
2057 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
2058 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2059 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
2060 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2061 REGINFO_SENTINEL
2062};
2063
777dc784
PM		 2064static void cortex_a8_initfn(Object *obj)
2065{
2066 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2067
2068 cpu->dtb_compatible = "arm,cortex-a8";
581be094
PM		 2069 set_feature(&cpu->env, ARM_FEATURE_V7);
2070 set_feature(&cpu->env, ARM_FEATURE_VFP3);
2071 set_feature(&cpu->env, ARM_FEATURE_NEON);
2072 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
c4804214 2073 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
c0ccb02d 2074 set_feature(&cpu->env, ARM_FEATURE_EL3);
b2d06f96 2075 cpu->midr = 0x410fc080;
325b3cef 2076 cpu->reset_fpsid = 0x410330c0;
47576b94
RH		 2077 cpu->isar.mvfr0 = 0x11110222;
2078 cpu->isar.mvfr1 = 0x00011111;
64e1671f 2079 cpu->ctr = 0x82048004;
0ca7e01c 2080 cpu->reset_sctlr = 0x00c50078;
2e4d7e3e
PM		 2081 cpu->id_pfr0 = 0x1031;
2082 cpu->id_pfr1 = 0x11;
2083 cpu->id_dfr0 = 0x400;
2084 cpu->id_afr0 = 0;
2085 cpu->id_mmfr0 = 0x31100003;
2086 cpu->id_mmfr1 = 0x20000000;
2087 cpu->id_mmfr2 = 0x01202000;
2088 cpu->id_mmfr3 = 0x11;
47576b94
RH		 2089 cpu->isar.id_isar0 = 0x00101111;
2090 cpu->isar.id_isar1 = 0x12112111;
2091 cpu->isar.id_isar2 = 0x21232031;
2092 cpu->isar.id_isar3 = 0x11112131;
2093 cpu->isar.id_isar4 = 0x00111142;
48eb3ae6 2094 cpu->dbgdidr = 0x15141000;
85df3786
PM		 2095 cpu->clidr = (1 << 27) | (2 << 24) | 3;
2096 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
2097 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
2098 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
2771db27 2099 cpu->reset_auxcr = 2;
34f90529 2100 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
777dc784
PM		 2101}
2102
1047b9d7
PM		 2103static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
2104 /* power_control should be set to maximum latency. Again,
2105 * default to 0 and set by private hook
2106 */
2107 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
2108 .access = PL1_RW, .resetvalue = 0,
2109 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
2110 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
2111 .access = PL1_RW, .resetvalue = 0,
2112 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
2113 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
2114 .access = PL1_RW, .resetvalue = 0,
2115 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
2116 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
2117 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2118 /* TLB lockdown control */
2119 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
2120 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
2121 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
2122 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
2123 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
2124 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2125 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
2126 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2127 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
2128 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
2129 REGINFO_SENTINEL
2130};
2131
777dc784
PM		 2132static void cortex_a9_initfn(Object *obj)
2133{
2134 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2135
2136 cpu->dtb_compatible = "arm,cortex-a9";
581be094
PM		 2137 set_feature(&cpu->env, ARM_FEATURE_V7);
2138 set_feature(&cpu->env, ARM_FEATURE_VFP3);
581be094
PM		 2139 set_feature(&cpu->env, ARM_FEATURE_NEON);
2140 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
c0ccb02d 2141 set_feature(&cpu->env, ARM_FEATURE_EL3);
581be094
PM		 2142 /* Note that A9 supports the MP extensions even for
2143 * A9UP and single-core A9MP (which are both different
2144 * and valid configurations; we don't model A9UP).
2145 */
2146 set_feature(&cpu->env, ARM_FEATURE_V7MP);
d8ba780b 2147 set_feature(&cpu->env, ARM_FEATURE_CBAR);
b2d06f96 2148 cpu->midr = 0x410fc090;
325b3cef 2149 cpu->reset_fpsid = 0x41033090;
47576b94
RH		 2150 cpu->isar.mvfr0 = 0x11110222;
2151 cpu->isar.mvfr1 = 0x01111111;
64e1671f 2152 cpu->ctr = 0x80038003;
0ca7e01c 2153 cpu->reset_sctlr = 0x00c50078;
2e4d7e3e
PM		 2154 cpu->id_pfr0 = 0x1031;
2155 cpu->id_pfr1 = 0x11;
2156 cpu->id_dfr0 = 0x000;
2157 cpu->id_afr0 = 0;
2158 cpu->id_mmfr0 = 0x00100103;
2159 cpu->id_mmfr1 = 0x20000000;
2160 cpu->id_mmfr2 = 0x01230000;
2161 cpu->id_mmfr3 = 0x00002111;
47576b94
RH		 2162 cpu->isar.id_isar0 = 0x00101111;
2163 cpu->isar.id_isar1 = 0x13112111;
2164 cpu->isar.id_isar2 = 0x21232041;
2165 cpu->isar.id_isar3 = 0x11112131;
2166 cpu->isar.id_isar4 = 0x00111142;
48eb3ae6 2167 cpu->dbgdidr = 0x35141000;
85df3786 2168 cpu->clidr = (1 << 27) | (1 << 24) | 3;
f7838b52
PC		 2169 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
2170 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
d8ba780b 2171 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
777dc784
PM		 2172}
2173
34f90529 2174#ifndef CONFIG_USER_ONLY
c4241c7d 2175static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
34f90529 2176{
cc7d44c2
LX		 2177 MachineState *ms = MACHINE(qdev_get_machine());
2178
34f90529
PM		 2179 /* Linux wants the number of processors from here.
2180 * Might as well set the interrupt-controller bit too.
2181 */
cc7d44c2 2182 return ((ms->smp.cpus - 1) << 24) | (1 << 23);
34f90529
PM		 2183}
2184#endif
2185
2186static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
2187#ifndef CONFIG_USER_ONLY
2188 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
2189 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
2190 .writefn = arm_cp_write_ignore, },
2191#endif
2192 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
2193 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2194 REGINFO_SENTINEL
2195};
2196
dcf578ed
AY		 2197static void cortex_a7_initfn(Object *obj)
2198{
2199 ARMCPU *cpu = ARM_CPU(obj);
2200
2201 cpu->dtb_compatible = "arm,cortex-a7";
5110e683 2202 set_feature(&cpu->env, ARM_FEATURE_V7VE);
dcf578ed
AY		 2203 set_feature(&cpu->env, ARM_FEATURE_VFP4);
2204 set_feature(&cpu->env, ARM_FEATURE_NEON);
2205 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
dcf578ed
AY		 2206 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
2207 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
2208 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
436c0cbb 2209 set_feature(&cpu->env, ARM_FEATURE_EL2);
dcf578ed 2210 set_feature(&cpu->env, ARM_FEATURE_EL3);
a46118fc 2211 set_feature(&cpu->env, ARM_FEATURE_PMU);
dcf578ed
AY		 2212 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
2213 cpu->midr = 0x410fc075;
2214 cpu->reset_fpsid = 0x41023075;
47576b94
RH		 2215 cpu->isar.mvfr0 = 0x10110222;
2216 cpu->isar.mvfr1 = 0x11111111;
dcf578ed
AY		 2217 cpu->ctr = 0x84448003;
2218 cpu->reset_sctlr = 0x00c50078;
2219 cpu->id_pfr0 = 0x00001131;
2220 cpu->id_pfr1 = 0x00011011;
2221 cpu->id_dfr0 = 0x02010555;
dcf578ed
AY		 2222 cpu->id_afr0 = 0x00000000;
2223 cpu->id_mmfr0 = 0x10101105;
2224 cpu->id_mmfr1 = 0x40000000;
2225 cpu->id_mmfr2 = 0x01240000;
2226 cpu->id_mmfr3 = 0x02102211;
37bdda89
RH		 2227 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
2228 * table 4-41 gives 0x02101110, which includes the arm div insns.
2229 */
47576b94
RH		 2230 cpu->isar.id_isar0 = 0x02101110;
2231 cpu->isar.id_isar1 = 0x13112111;
2232 cpu->isar.id_isar2 = 0x21232041;
2233 cpu->isar.id_isar3 = 0x11112131;
2234 cpu->isar.id_isar4 = 0x10011142;
dcf578ed
AY		 2235 cpu->dbgdidr = 0x3515f005;
2236 cpu->clidr = 0x0a200023;
2237 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
2238 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
2239 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
2240 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
2241}
2242
777dc784
PM		 2243static void cortex_a15_initfn(Object *obj)
2244{
2245 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2246
2247 cpu->dtb_compatible = "arm,cortex-a15";
5110e683 2248 set_feature(&cpu->env, ARM_FEATURE_V7VE);
581be094 2249 set_feature(&cpu->env, ARM_FEATURE_VFP4);
581be094
PM		 2250 set_feature(&cpu->env, ARM_FEATURE_NEON);
2251 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
581be094 2252 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
c4804214 2253 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
c29f9a0a 2254 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
436c0cbb 2255 set_feature(&cpu->env, ARM_FEATURE_EL2);
c0ccb02d 2256 set_feature(&cpu->env, ARM_FEATURE_EL3);
a46118fc 2257 set_feature(&cpu->env, ARM_FEATURE_PMU);
3541addc 2258 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
b2d06f96 2259 cpu->midr = 0x412fc0f1;
325b3cef 2260 cpu->reset_fpsid = 0x410430f0;
47576b94
RH		 2261 cpu->isar.mvfr0 = 0x10110222;
2262 cpu->isar.mvfr1 = 0x11111111;
64e1671f 2263 cpu->ctr = 0x8444c004;
0ca7e01c 2264 cpu->reset_sctlr = 0x00c50078;
2e4d7e3e
PM		 2265 cpu->id_pfr0 = 0x00001131;
2266 cpu->id_pfr1 = 0x00011011;
2267 cpu->id_dfr0 = 0x02010555;
2268 cpu->id_afr0 = 0x00000000;
2269 cpu->id_mmfr0 = 0x10201105;
2270 cpu->id_mmfr1 = 0x20000000;
2271 cpu->id_mmfr2 = 0x01240000;
2272 cpu->id_mmfr3 = 0x02102211;
47576b94
RH		 2273 cpu->isar.id_isar0 = 0x02101110;
2274 cpu->isar.id_isar1 = 0x13112111;
2275 cpu->isar.id_isar2 = 0x21232041;
2276 cpu->isar.id_isar3 = 0x11112131;
2277 cpu->isar.id_isar4 = 0x10011142;
48eb3ae6 2278 cpu->dbgdidr = 0x3515f021;
85df3786
PM		 2279 cpu->clidr = 0x0a200023;
2280 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
2281 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
2282 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
34f90529 2283 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
777dc784
PM		 2284}
2285
2286static void ti925t_initfn(Object *obj)
2287{
2288 ARMCPU *cpu = ARM_CPU(obj);
581be094
PM		 2289 set_feature(&cpu->env, ARM_FEATURE_V4T);
2290 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
777dc784 2291 cpu->midr = ARM_CPUID_TI925T;
64e1671f 2292 cpu->ctr = 0x5109149;
0ca7e01c 2293 cpu->reset_sctlr = 0x00000070;
777dc784
PM		 2294}
2295
2296static void sa1100_initfn(Object *obj)
2297{
2298 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2299
2300 cpu->dtb_compatible = "intel,sa1100";
581be094 2301 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
c4804214 2302 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
b2d06f96 2303 cpu->midr = 0x4401A11B;
0ca7e01c 2304 cpu->reset_sctlr = 0x00000070;
777dc784
PM		 2305}
2306
2307static void sa1110_initfn(Object *obj)
2308{
2309 ARMCPU *cpu = ARM_CPU(obj);
581be094 2310 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
c4804214 2311 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
b2d06f96 2312 cpu->midr = 0x6901B119;
0ca7e01c 2313 cpu->reset_sctlr = 0x00000070;
777dc784
PM		 2314}
2315
2316static void pxa250_initfn(Object *obj)
2317{
2318 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2319
2320 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2321 set_feature(&cpu->env, ARM_FEATURE_V5);
2322 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 2323 cpu->midr = 0x69052100;
64e1671f 2324 cpu->ctr = 0xd172172;
0ca7e01c 2325 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2326}
2327
2328static void pxa255_initfn(Object *obj)
2329{
2330 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2331
2332 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2333 set_feature(&cpu->env, ARM_FEATURE_V5);
2334 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 2335 cpu->midr = 0x69052d00;
64e1671f 2336 cpu->ctr = 0xd172172;
0ca7e01c 2337 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2338}
2339
2340static void pxa260_initfn(Object *obj)
2341{
2342 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2343
2344 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2345 set_feature(&cpu->env, ARM_FEATURE_V5);
2346 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 2347 cpu->midr = 0x69052903;
64e1671f 2348 cpu->ctr = 0xd172172;
0ca7e01c 2349 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2350}
2351
2352static void pxa261_initfn(Object *obj)
2353{
2354 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2355
2356 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2357 set_feature(&cpu->env, ARM_FEATURE_V5);
2358 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 2359 cpu->midr = 0x69052d05;
64e1671f 2360 cpu->ctr = 0xd172172;
0ca7e01c 2361 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2362}
2363
2364static void pxa262_initfn(Object *obj)
2365{
2366 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2367
2368 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2369 set_feature(&cpu->env, ARM_FEATURE_V5);
2370 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
b2d06f96 2371 cpu->midr = 0x69052d06;
64e1671f 2372 cpu->ctr = 0xd172172;
0ca7e01c 2373 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2374}
2375
2376static void pxa270a0_initfn(Object *obj)
2377{
2378 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2379
2380 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2381 set_feature(&cpu->env, ARM_FEATURE_V5);
2382 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2383 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 2384 cpu->midr = 0x69054110;
64e1671f 2385 cpu->ctr = 0xd172172;
0ca7e01c 2386 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2387}
2388
2389static void pxa270a1_initfn(Object *obj)
2390{
2391 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2392
2393 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2394 set_feature(&cpu->env, ARM_FEATURE_V5);
2395 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2396 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 2397 cpu->midr = 0x69054111;
64e1671f 2398 cpu->ctr = 0xd172172;
0ca7e01c 2399 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2400}
2401
2402static void pxa270b0_initfn(Object *obj)
2403{
2404 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2405
2406 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2407 set_feature(&cpu->env, ARM_FEATURE_V5);
2408 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2409 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 2410 cpu->midr = 0x69054112;
64e1671f 2411 cpu->ctr = 0xd172172;
0ca7e01c 2412 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2413}
2414
2415static void pxa270b1_initfn(Object *obj)
2416{
2417 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2418
2419 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2420 set_feature(&cpu->env, ARM_FEATURE_V5);
2421 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2422 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 2423 cpu->midr = 0x69054113;
64e1671f 2424 cpu->ctr = 0xd172172;
0ca7e01c 2425 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2426}
2427
2428static void pxa270c0_initfn(Object *obj)
2429{
2430 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2431
2432 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2433 set_feature(&cpu->env, ARM_FEATURE_V5);
2434 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2435 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 2436 cpu->midr = 0x69054114;
64e1671f 2437 cpu->ctr = 0xd172172;
0ca7e01c 2438 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2439}
2440
2441static void pxa270c5_initfn(Object *obj)
2442{
2443 ARMCPU *cpu = ARM_CPU(obj);
54d3e3f5
PM		 2444
2445 cpu->dtb_compatible = "marvell,xscale";
581be094
PM		 2446 set_feature(&cpu->env, ARM_FEATURE_V5);
2447 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
2448 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
b2d06f96 2449 cpu->midr = 0x69054117;
64e1671f 2450 cpu->ctr = 0xd172172;
0ca7e01c 2451 cpu->reset_sctlr = 0x00000078;
777dc784
PM		 2452}
2453
bab52d4b
PM		 2454#ifndef TARGET_AARCH64
2455/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
2456 * otherwise, a CPU with as many features enabled as our emulation supports.
2457 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
2458 * this only needs to handle 32 bits.
2459 */
2460static void arm_max_initfn(Object *obj)
2461{
2462 ARMCPU *cpu = ARM_CPU(obj);
2463
2464 if (kvm_enabled()) {
2465 kvm_arm_set_cpu_features_from_host(cpu);
2466 } else {
2467 cortex_a15_initfn(obj);
973751fd
PM		 2468
2469 /* old-style VFP short-vector support */
2470 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
2471
a0032cc5
PM		 2472#ifdef CONFIG_USER_ONLY
2473 /* We don't set these in system emulation mode for the moment,
962fcbf2
RH		 2474 * since we don't correctly set (all of) the ID registers to
2475 * advertise them.
bab52d4b 2476 */
a0032cc5 2477 set_feature(&cpu->env, ARM_FEATURE_V8);
962fcbf2
RH		 2478 {
2479 uint32_t t;
2480
2481 t = cpu->isar.id_isar5;
2482 t = FIELD_DP32(t, ID_ISAR5, AES, 2);
2483 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
2484 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
2485 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
2486 t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
2487 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
2488 cpu->isar.id_isar5 = t;
2489
2490 t = cpu->isar.id_isar6;
6c1f6f27 2491 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
962fcbf2 2492 t = FIELD_DP32(t, ID_ISAR6, DP, 1);
991c0599 2493 t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
9888bd1e 2494 t = FIELD_DP32(t, ID_ISAR6, SB, 1);
cb570bd3 2495 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
962fcbf2 2496 cpu->isar.id_isar6 = t;
ab638a32 2497
45b1a243
AB		 2498 t = cpu->isar.mvfr1;
2499 t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */
2500 cpu->isar.mvfr1 = t;
2501
c8877d0f
RH		 2502 t = cpu->isar.mvfr2;
2503 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
2504 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
2505 cpu->isar.mvfr2 = t;
2506
ab638a32
RH		 2507 t = cpu->id_mmfr4;
2508 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
2509 cpu->id_mmfr4 = t;
962fcbf2 2510 }
bab52d4b 2511#endif
a0032cc5 2512 }
777dc784 2513}
f5f6d38b 2514#endif
777dc784 2515
15ee776b
PM		 2516#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
2517
51e5ef45 2518struct ARMCPUInfo {
777dc784
PM		 2519 const char *name;
2520 void (*initfn)(Object *obj);
e6f010cc 2521 void (*class_init)(ObjectClass *oc, void *data);
51e5ef45 2522};
777dc784
PM		 2523
2524static const ARMCPUInfo arm_cpus[] = {
15ee776b 2525#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
777dc784
PM		 2526 { .name = "arm926", .initfn = arm926_initfn },
2527 { .name = "arm946", .initfn = arm946_initfn },
2528 { .name = "arm1026", .initfn = arm1026_initfn },
2529 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
2530 * older core than plain "arm1136". In particular this does not
2531 * have the v6K features.
2532 */
2533 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
2534 { .name = "arm1136", .initfn = arm1136_initfn },
2535 { .name = "arm1176", .initfn = arm1176_initfn },
2536 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
191776b9
SH		 2537 { .name = "cortex-m0", .initfn = cortex_m0_initfn,
2538 .class_init = arm_v7m_class_init },
e6f010cc
AF		 2539 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
2540 .class_init = arm_v7m_class_init },
ba890a9b
AR		 2541 { .name = "cortex-m4", .initfn = cortex_m4_initfn,
2542 .class_init = arm_v7m_class_init },
c7b26382
PM		 2543 { .name = "cortex-m33", .initfn = cortex_m33_initfn,
2544 .class_init = arm_v7m_class_init },
d6a6b13e 2545 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
ebac5458 2546 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
dcf578ed 2547 { .name = "cortex-a7", .initfn = cortex_a7_initfn },
777dc784
PM		 2548 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
2549 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
2550 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
2551 { .name = "ti925t", .initfn = ti925t_initfn },
2552 { .name = "sa1100", .initfn = sa1100_initfn },
2553 { .name = "sa1110", .initfn = sa1110_initfn },
2554 { .name = "pxa250", .initfn = pxa250_initfn },
2555 { .name = "pxa255", .initfn = pxa255_initfn },
2556 { .name = "pxa260", .initfn = pxa260_initfn },
2557 { .name = "pxa261", .initfn = pxa261_initfn },
2558 { .name = "pxa262", .initfn = pxa262_initfn },
2559 /* "pxa270" is an alias for "pxa270-a0" */
2560 { .name = "pxa270", .initfn = pxa270a0_initfn },
2561 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
2562 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
2563 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
2564 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
2565 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
2566 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
bab52d4b
PM		 2567#ifndef TARGET_AARCH64
2568 { .name = "max", .initfn = arm_max_initfn },
2569#endif
f5f6d38b 2570#ifdef CONFIG_USER_ONLY
a0032cc5 2571 { .name = "any", .initfn = arm_max_initfn },
f5f6d38b 2572#endif
15ee776b 2573#endif
83e6813a 2574 { .name = NULL }
777dc784
PM		 2575};
2576
5de16430
PM		 2577static Property arm_cpu_properties[] = {
2578 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
98128601 2579 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
51a9b04b 2580 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
ce5b1bbf
LV		 2581 DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
2582 mp_affinity, ARM64_AFFINITY_INVALID),
15f8b142 2583 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
f9a69711 2584 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
5de16430
PM		 2585 DEFINE_PROP_END_OF_LIST()
2586};
2587
b3820e6c
DH		 2588static gchar *arm_gdb_arch_name(CPUState *cs)
2589{
2590 ARMCPU *cpu = ARM_CPU(cs);
2591 CPUARMState *env = &cpu->env;
2592
2593 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
2594 return g_strdup("iwmmxt");
2595 }
2596 return g_strdup("arm");
2597}
2598
dec9c2d4
AF		 2599static void arm_cpu_class_init(ObjectClass *oc, void *data)
2600{
2601 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2602 CPUClass *cc = CPU_CLASS(acc);
14969266
AF		 2603 DeviceClass *dc = DEVICE_CLASS(oc);
2604
bf853881
PMD		 2605 device_class_set_parent_realize(dc, arm_cpu_realizefn,
2606 &acc->parent_realize);
5de16430 2607 dc->props = arm_cpu_properties;
dec9c2d4
AF		 2608
2609 acc->parent_reset = cc->reset;
2610 cc->reset = arm_cpu_reset;
5900d6b2
AF		 2611
2612 cc->class_by_name = arm_cpu_class_by_name;
8c2e1b00 2613 cc->has_work = arm_cpu_has_work;
e8925712 2614 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
878096ee 2615 cc->dump_state = arm_cpu_dump_state;
f45748f1 2616 cc->set_pc = arm_cpu_set_pc;
42f6ed91 2617 cc->synchronize_from_tb = arm_cpu_synchronize_from_tb;
5b50e790
AF		 2618 cc->gdb_read_register = arm_cpu_gdb_read_register;
2619 cc->gdb_write_register = arm_cpu_gdb_write_register;
7350d553 2620#ifndef CONFIG_USER_ONLY
0adf7d3c 2621 cc->do_interrupt = arm_cpu_do_interrupt;
0faea0c7 2622 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
017518c1 2623 cc->asidx_from_attrs = arm_asidx_from_attrs;
00b941e5 2624 cc->vmsd = &vmstate_arm_cpu;
ed50ff78 2625 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
da2b9140
AJ		 2626 cc->write_elf64_note = arm_cpu_write_elf64_note;
2627 cc->write_elf32_note = arm_cpu_write_elf32_note;
00b941e5 2628#endif
a0e372f0 2629 cc->gdb_num_core_regs = 26;
5b24c641 2630 cc->gdb_core_xml_file = "arm-core.xml";
b3820e6c 2631 cc->gdb_arch_name = arm_gdb_arch_name;
200bf5b7 2632 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
2472b6c0 2633 cc->gdb_stop_before_watchpoint = true;
48440620 2634 cc->disas_set_info = arm_disas_set_info;
74d7fc7f 2635#ifdef CONFIG_TCG
55c3ceef 2636 cc->tcg_initialize = arm_translate_init;
7350d553 2637 cc->tlb_fill = arm_cpu_tlb_fill;
9dd5cca4
PMD		 2638 cc->debug_excp_handler = arm_debug_excp_handler;
2639 cc->debug_check_watchpoint = arm_debug_check_watchpoint;
e21b551c
PMD		 2640#if !defined(CONFIG_USER_ONLY)
2641 cc->do_unaligned_access = arm_cpu_do_unaligned_access;
2642 cc->do_transaction_failed = arm_cpu_do_transaction_failed;
9dd5cca4 2643 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
e21b551c 2644#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
74d7fc7f 2645#endif
dec9c2d4
AF		 2646}
2647
86f0a186
PM		 2648#ifdef CONFIG_KVM
2649static void arm_host_initfn(Object *obj)
2650{
2651 ARMCPU *cpu = ARM_CPU(obj);
2652
2653 kvm_arm_set_cpu_features_from_host(cpu);
51e5ef45 2654 arm_cpu_post_init(obj);
86f0a186
PM		 2655}
2656
2657static const TypeInfo host_arm_cpu_type_info = {
2658 .name = TYPE_ARM_HOST_CPU,
2659#ifdef TARGET_AARCH64
2660 .parent = TYPE_AARCH64_CPU,
2661#else
2662 .parent = TYPE_ARM_CPU,
2663#endif
2664 .instance_init = arm_host_initfn,
2665};
2666
2667#endif
2668
51e5ef45
MAL		 2669static void arm_cpu_instance_init(Object *obj)
2670{
2671 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
2672
2673 acc->info->initfn(obj);
2674 arm_cpu_post_init(obj);
2675}
2676
2677static void cpu_register_class_init(ObjectClass *oc, void *data)
2678{
2679 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2680
2681 acc->info = data;
2682}
2683
777dc784
PM		 2684static void cpu_register(const ARMCPUInfo *info)
2685{
2686 TypeInfo type_info = {
777dc784
PM		 2687 .parent = TYPE_ARM_CPU,
2688 .instance_size = sizeof(ARMCPU),
51e5ef45 2689 .instance_init = arm_cpu_instance_init,
777dc784 2690 .class_size = sizeof(ARMCPUClass),
51e5ef45
MAL		 2691 .class_init = info->class_init ?: cpu_register_class_init,
2692 .class_data = (void *)info,
777dc784
PM		 2693 };
2694
51492fd1 2695 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
918fd083 2696 type_register(&type_info);
51492fd1 2697 g_free((void *)type_info.name);
777dc784
PM		 2698}
2699
dec9c2d4
AF		 2700static const TypeInfo arm_cpu_type_info = {
2701 .name = TYPE_ARM_CPU,
2702 .parent = TYPE_CPU,
2703 .instance_size = sizeof(ARMCPU),
777dc784 2704 .instance_init = arm_cpu_initfn,
4b6a83fb 2705 .instance_finalize = arm_cpu_finalizefn,
777dc784 2706 .abstract = true,
dec9c2d4
AF		 2707 .class_size = sizeof(ARMCPUClass),
2708 .class_init = arm_cpu_class_init,
2709};
2710
181962fd
PM		 2711static const TypeInfo idau_interface_type_info = {
2712 .name = TYPE_IDAU_INTERFACE,
2713 .parent = TYPE_INTERFACE,
2714 .class_size = sizeof(IDAUInterfaceClass),
2715};
2716
dec9c2d4
AF		 2717static void arm_cpu_register_types(void)
2718{
83e6813a 2719 const ARMCPUInfo *info = arm_cpus;
777dc784 2720
dec9c2d4 2721 type_register_static(&arm_cpu_type_info);
181962fd 2722 type_register_static(&idau_interface_type_info);
83e6813a
PM		 2723
2724 while (info->name) {
2725 cpu_register(info);
2726 info++;
777dc784 2727 }
86f0a186
PM		 2728
2729#ifdef CONFIG_KVM
2730 type_register_static(&host_arm_cpu_type_info);
2731#endif
dec9c2d4
AF		 2732}
2733
2734type_init(arm_cpu_register_types)
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