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2c0262af FB |
1 | /* |
2 | * ARM virtual CPU header | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af | 18 | */ |
2c0262af | 19 | |
07f5a258 MA |
20 | #ifndef ARM_CPU_H |
21 | #define ARM_CPU_H | |
3cf1e035 | 22 | |
72b0cd35 | 23 | #include "kvm-consts.h" |
2c4da50d | 24 | #include "hw/registerfields.h" |
72b0cd35 | 25 | |
3926cc84 AG |
26 | #if defined(TARGET_AARCH64) |
27 | /* AArch64 definitions */ | |
28 | # define TARGET_LONG_BITS 64 | |
3926cc84 AG |
29 | #else |
30 | # define TARGET_LONG_BITS 32 | |
3926cc84 | 31 | #endif |
9042c0e2 | 32 | |
ca759f9e AB |
33 | /* ARM processors have a weak memory model */ |
34 | #define TCG_GUEST_DEFAULT_MO (0) | |
35 | ||
9349b4f9 | 36 | #define CPUArchState struct CPUARMState |
c2764719 | 37 | |
9a78eead | 38 | #include "qemu-common.h" |
74e75564 | 39 | #include "cpu-qom.h" |
022c62cb | 40 | #include "exec/cpu-defs.h" |
2c0262af | 41 | |
6b4c305c | 42 | #include "fpu/softfloat.h" |
53cd6637 | 43 | |
b8a9e8f1 FB |
44 | #define EXCP_UDEF 1 /* undefined instruction */ |
45 | #define EXCP_SWI 2 /* software interrupt */ | |
46 | #define EXCP_PREFETCH_ABORT 3 | |
47 | #define EXCP_DATA_ABORT 4 | |
b5ff1b31 FB |
48 | #define EXCP_IRQ 5 |
49 | #define EXCP_FIQ 6 | |
06c949e6 | 50 | #define EXCP_BKPT 7 |
9ee6e8bb | 51 | #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ |
fbb4a2e3 | 52 | #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ |
35979d71 | 53 | #define EXCP_HVC 11 /* HyperVisor Call */ |
607d98b8 | 54 | #define EXCP_HYP_TRAP 12 |
e0d6e6a5 | 55 | #define EXCP_SMC 13 /* Secure Monitor Call */ |
136e67e9 EI |
56 | #define EXCP_VIRQ 14 |
57 | #define EXCP_VFIQ 15 | |
19a6e31c | 58 | #define EXCP_SEMIHOST 16 /* semihosting call */ |
7517748e | 59 | #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ |
e13886e3 | 60 | #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ |
2c4a7cc5 | 61 | /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ |
9ee6e8bb PB |
62 | |
63 | #define ARMV7M_EXCP_RESET 1 | |
64 | #define ARMV7M_EXCP_NMI 2 | |
65 | #define ARMV7M_EXCP_HARD 3 | |
66 | #define ARMV7M_EXCP_MEM 4 | |
67 | #define ARMV7M_EXCP_BUS 5 | |
68 | #define ARMV7M_EXCP_USAGE 6 | |
69 | #define ARMV7M_EXCP_SVC 11 | |
70 | #define ARMV7M_EXCP_DEBUG 12 | |
71 | #define ARMV7M_EXCP_PENDSV 14 | |
72 | #define ARMV7M_EXCP_SYSTICK 15 | |
2c0262af | 73 | |
403946c0 RH |
74 | /* ARM-specific interrupt pending bits. */ |
75 | #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 | |
136e67e9 EI |
76 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 |
77 | #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 | |
403946c0 | 78 | |
e4fe830b PM |
79 | /* The usual mapping for an AArch64 system register to its AArch32 |
80 | * counterpart is for the 32 bit world to have access to the lower | |
81 | * half only (with writes leaving the upper half untouched). It's | |
82 | * therefore useful to be able to pass TCG the offset of the least | |
83 | * significant half of a uint64_t struct member. | |
84 | */ | |
85 | #ifdef HOST_WORDS_BIGENDIAN | |
5cd8a118 | 86 | #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) |
b0fe2427 | 87 | #define offsetofhigh32(S, M) offsetof(S, M) |
e4fe830b PM |
88 | #else |
89 | #define offsetoflow32(S, M) offsetof(S, M) | |
b0fe2427 | 90 | #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) |
e4fe830b PM |
91 | #endif |
92 | ||
136e67e9 | 93 | /* Meanings of the ARMCPU object's four inbound GPIO lines */ |
7c1840b6 PM |
94 | #define ARM_CPU_IRQ 0 |
95 | #define ARM_CPU_FIQ 1 | |
136e67e9 EI |
96 | #define ARM_CPU_VIRQ 2 |
97 | #define ARM_CPU_VFIQ 3 | |
403946c0 | 98 | |
c1e37810 | 99 | #define NB_MMU_MODES 7 |
aaa1f954 EI |
100 | /* ARM-specific extra insn start words: |
101 | * 1: Conditional execution bits | |
102 | * 2: Partial exception syndrome for data aborts | |
103 | */ | |
104 | #define TARGET_INSN_START_EXTRA_WORDS 2 | |
105 | ||
106 | /* The 2nd extra word holding syndrome info for data aborts does not use | |
107 | * the upper 6 bits nor the lower 14 bits. We mask and shift it down to | |
108 | * help the sleb128 encoder do a better job. | |
109 | * When restoring the CPU state, we shift it back up. | |
110 | */ | |
111 | #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) | |
112 | #define ARM_INSN_START_WORD2_SHIFT 14 | |
6ebbf390 | 113 | |
b7bcbe95 FB |
114 | /* We currently assume float and double are IEEE single and double |
115 | precision respectively. | |
116 | Doing runtime conversions is tricky because VFP registers may contain | |
117 | integer values (eg. as the result of a FTOSI instruction). | |
8e96005d FB |
118 | s<2n> maps to the least significant half of d<n> |
119 | s<2n+1> maps to the most significant half of d<n> | |
120 | */ | |
b7bcbe95 | 121 | |
55d284af PM |
122 | /* CPU state for each instance of a generic timer (in cp15 c14) */ |
123 | typedef struct ARMGenericTimer { | |
124 | uint64_t cval; /* Timer CompareValue register */ | |
a7adc4b7 | 125 | uint64_t ctl; /* Timer Control register */ |
55d284af PM |
126 | } ARMGenericTimer; |
127 | ||
128 | #define GTIMER_PHYS 0 | |
129 | #define GTIMER_VIRT 1 | |
b0e66d95 | 130 | #define GTIMER_HYP 2 |
b4d3978c PM |
131 | #define GTIMER_SEC 3 |
132 | #define NUM_GTIMERS 4 | |
55d284af | 133 | |
11f136ee FA |
134 | typedef struct { |
135 | uint64_t raw_tcr; | |
136 | uint32_t mask; | |
137 | uint32_t base_mask; | |
138 | } TCR; | |
139 | ||
2c0262af | 140 | typedef struct CPUARMState { |
b5ff1b31 | 141 | /* Regs for current mode. */ |
2c0262af | 142 | uint32_t regs[16]; |
3926cc84 AG |
143 | |
144 | /* 32/64 switch only happens when taking and returning from | |
145 | * exceptions so the overlap semantics are taken care of then | |
146 | * instead of having a complicated union. | |
147 | */ | |
148 | /* Regs for A64 mode. */ | |
149 | uint64_t xregs[32]; | |
150 | uint64_t pc; | |
d356312f PM |
151 | /* PSTATE isn't an architectural register for ARMv8. However, it is |
152 | * convenient for us to assemble the underlying state into a 32 bit format | |
153 | * identical to the architectural format used for the SPSR. (This is also | |
154 | * what the Linux kernel's 'pstate' field in signal handlers and KVM's | |
155 | * 'pstate' register are.) Of the PSTATE bits: | |
156 | * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same | |
157 | * semantics as for AArch32, as described in the comments on each field) | |
158 | * nRW (also known as M[4]) is kept, inverted, in env->aarch64 | |
4cc35614 | 159 | * DAIF (exception masks) are kept in env->daif |
d356312f | 160 | * all other bits are stored in their correct places in env->pstate |
3926cc84 AG |
161 | */ |
162 | uint32_t pstate; | |
163 | uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ | |
164 | ||
b90372ad | 165 | /* Frequently accessed CPSR bits are stored separately for efficiency. |
d37aca66 | 166 | This contains all the other bits. Use cpsr_{read,write} to access |
b5ff1b31 FB |
167 | the whole CPSR. */ |
168 | uint32_t uncached_cpsr; | |
169 | uint32_t spsr; | |
170 | ||
171 | /* Banked registers. */ | |
28c9457d | 172 | uint64_t banked_spsr[8]; |
0b7d409d FA |
173 | uint32_t banked_r13[8]; |
174 | uint32_t banked_r14[8]; | |
3b46e624 | 175 | |
b5ff1b31 FB |
176 | /* These hold r8-r12. */ |
177 | uint32_t usr_regs[5]; | |
178 | uint32_t fiq_regs[5]; | |
3b46e624 | 179 | |
2c0262af FB |
180 | /* cpsr flag cache for faster execution */ |
181 | uint32_t CF; /* 0 or 1 */ | |
182 | uint32_t VF; /* V is the bit 31. All other bits are undefined */ | |
6fbe23d5 PB |
183 | uint32_t NF; /* N is bit 31. All other bits are undefined. */ |
184 | uint32_t ZF; /* Z set if zero. */ | |
99c475ab | 185 | uint32_t QF; /* 0 or 1 */ |
9ee6e8bb | 186 | uint32_t GE; /* cpsr[19:16] */ |
b26eefb6 | 187 | uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ |
9ee6e8bb | 188 | uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ |
b6af0975 | 189 | uint64_t daif; /* exception masks, in the bits they are in PSTATE */ |
2c0262af | 190 | |
1b174238 | 191 | uint64_t elr_el[4]; /* AArch64 exception link regs */ |
73fb3b76 | 192 | uint64_t sp_el[4]; /* AArch64 banked stack pointers */ |
a0618a19 | 193 | |
b5ff1b31 FB |
194 | /* System control coprocessor (cp15) */ |
195 | struct { | |
40f137e1 | 196 | uint32_t c0_cpuid; |
b85a1fd6 FA |
197 | union { /* Cache size selection */ |
198 | struct { | |
199 | uint64_t _unused_csselr0; | |
200 | uint64_t csselr_ns; | |
201 | uint64_t _unused_csselr1; | |
202 | uint64_t csselr_s; | |
203 | }; | |
204 | uint64_t csselr_el[4]; | |
205 | }; | |
137feaa9 FA |
206 | union { /* System control register. */ |
207 | struct { | |
208 | uint64_t _unused_sctlr; | |
209 | uint64_t sctlr_ns; | |
210 | uint64_t hsctlr; | |
211 | uint64_t sctlr_s; | |
212 | }; | |
213 | uint64_t sctlr_el[4]; | |
214 | }; | |
7ebd5f2e | 215 | uint64_t cpacr_el1; /* Architectural feature access control register */ |
c6f19164 | 216 | uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ |
610c3c8a | 217 | uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ |
144634ae | 218 | uint64_t sder; /* Secure debug enable register. */ |
77022576 | 219 | uint32_t nsacr; /* Non-secure access control register. */ |
7dd8c9af FA |
220 | union { /* MMU translation table base 0. */ |
221 | struct { | |
222 | uint64_t _unused_ttbr0_0; | |
223 | uint64_t ttbr0_ns; | |
224 | uint64_t _unused_ttbr0_1; | |
225 | uint64_t ttbr0_s; | |
226 | }; | |
227 | uint64_t ttbr0_el[4]; | |
228 | }; | |
229 | union { /* MMU translation table base 1. */ | |
230 | struct { | |
231 | uint64_t _unused_ttbr1_0; | |
232 | uint64_t ttbr1_ns; | |
233 | uint64_t _unused_ttbr1_1; | |
234 | uint64_t ttbr1_s; | |
235 | }; | |
236 | uint64_t ttbr1_el[4]; | |
237 | }; | |
b698e9cf | 238 | uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ |
11f136ee FA |
239 | /* MMU translation table base control. */ |
240 | TCR tcr_el[4]; | |
68e9c2fe | 241 | TCR vtcr_el2; /* Virtualization Translation Control. */ |
67cc32eb VL |
242 | uint32_t c2_data; /* MPU data cacheable bits. */ |
243 | uint32_t c2_insn; /* MPU instruction cacheable bits. */ | |
0c17d68c FA |
244 | union { /* MMU domain access control register |
245 | * MPU write buffer control. | |
246 | */ | |
247 | struct { | |
248 | uint64_t dacr_ns; | |
249 | uint64_t dacr_s; | |
250 | }; | |
251 | struct { | |
252 | uint64_t dacr32_el2; | |
253 | }; | |
254 | }; | |
7e09797c PM |
255 | uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ |
256 | uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ | |
f149e3e8 | 257 | uint64_t hcr_el2; /* Hypervisor configuration register */ |
64e0e2de | 258 | uint64_t scr_el3; /* Secure configuration register. */ |
88ca1c2d FA |
259 | union { /* Fault status registers. */ |
260 | struct { | |
261 | uint64_t ifsr_ns; | |
262 | uint64_t ifsr_s; | |
263 | }; | |
264 | struct { | |
265 | uint64_t ifsr32_el2; | |
266 | }; | |
267 | }; | |
4a7e2d73 FA |
268 | union { |
269 | struct { | |
270 | uint64_t _unused_dfsr; | |
271 | uint64_t dfsr_ns; | |
272 | uint64_t hsr; | |
273 | uint64_t dfsr_s; | |
274 | }; | |
275 | uint64_t esr_el[4]; | |
276 | }; | |
ce819861 | 277 | uint32_t c6_region[8]; /* MPU base/size registers. */ |
b848ce2b FA |
278 | union { /* Fault address registers. */ |
279 | struct { | |
280 | uint64_t _unused_far0; | |
281 | #ifdef HOST_WORDS_BIGENDIAN | |
282 | uint32_t ifar_ns; | |
283 | uint32_t dfar_ns; | |
284 | uint32_t ifar_s; | |
285 | uint32_t dfar_s; | |
286 | #else | |
287 | uint32_t dfar_ns; | |
288 | uint32_t ifar_ns; | |
289 | uint32_t dfar_s; | |
290 | uint32_t ifar_s; | |
291 | #endif | |
292 | uint64_t _unused_far3; | |
293 | }; | |
294 | uint64_t far_el[4]; | |
295 | }; | |
59e05530 | 296 | uint64_t hpfar_el2; |
2a5a9abd | 297 | uint64_t hstr_el2; |
01c097f7 FA |
298 | union { /* Translation result. */ |
299 | struct { | |
300 | uint64_t _unused_par_0; | |
301 | uint64_t par_ns; | |
302 | uint64_t _unused_par_1; | |
303 | uint64_t par_s; | |
304 | }; | |
305 | uint64_t par_el[4]; | |
306 | }; | |
6cb0b013 PC |
307 | |
308 | uint32_t c6_rgnr; | |
309 | ||
b5ff1b31 FB |
310 | uint32_t c9_insn; /* Cache lockdown registers. */ |
311 | uint32_t c9_data; | |
8521466b AF |
312 | uint64_t c9_pmcr; /* performance monitor control register */ |
313 | uint64_t c9_pmcnten; /* perf monitor counter enables */ | |
74594c9d | 314 | uint32_t c9_pmovsr; /* perf monitor overflow status */ |
74594c9d | 315 | uint32_t c9_pmuserenr; /* perf monitor user enable */ |
6b040780 | 316 | uint64_t c9_pmselr; /* perf monitor counter selection register */ |
e6ec5457 | 317 | uint64_t c9_pminten; /* perf monitor interrupt enables */ |
be693c87 GB |
318 | union { /* Memory attribute redirection */ |
319 | struct { | |
320 | #ifdef HOST_WORDS_BIGENDIAN | |
321 | uint64_t _unused_mair_0; | |
322 | uint32_t mair1_ns; | |
323 | uint32_t mair0_ns; | |
324 | uint64_t _unused_mair_1; | |
325 | uint32_t mair1_s; | |
326 | uint32_t mair0_s; | |
327 | #else | |
328 | uint64_t _unused_mair_0; | |
329 | uint32_t mair0_ns; | |
330 | uint32_t mair1_ns; | |
331 | uint64_t _unused_mair_1; | |
332 | uint32_t mair0_s; | |
333 | uint32_t mair1_s; | |
334 | #endif | |
335 | }; | |
336 | uint64_t mair_el[4]; | |
337 | }; | |
fb6c91ba GB |
338 | union { /* vector base address register */ |
339 | struct { | |
340 | uint64_t _unused_vbar; | |
341 | uint64_t vbar_ns; | |
342 | uint64_t hvbar; | |
343 | uint64_t vbar_s; | |
344 | }; | |
345 | uint64_t vbar_el[4]; | |
346 | }; | |
e89e51a1 | 347 | uint32_t mvbar; /* (monitor) vector base address register */ |
54bf36ed FA |
348 | struct { /* FCSE PID. */ |
349 | uint32_t fcseidr_ns; | |
350 | uint32_t fcseidr_s; | |
351 | }; | |
352 | union { /* Context ID. */ | |
353 | struct { | |
354 | uint64_t _unused_contextidr_0; | |
355 | uint64_t contextidr_ns; | |
356 | uint64_t _unused_contextidr_1; | |
357 | uint64_t contextidr_s; | |
358 | }; | |
359 | uint64_t contextidr_el[4]; | |
360 | }; | |
361 | union { /* User RW Thread register. */ | |
362 | struct { | |
363 | uint64_t tpidrurw_ns; | |
364 | uint64_t tpidrprw_ns; | |
365 | uint64_t htpidr; | |
366 | uint64_t _tpidr_el3; | |
367 | }; | |
368 | uint64_t tpidr_el[4]; | |
369 | }; | |
370 | /* The secure banks of these registers don't map anywhere */ | |
371 | uint64_t tpidrurw_s; | |
372 | uint64_t tpidrprw_s; | |
373 | uint64_t tpidruro_s; | |
374 | ||
375 | union { /* User RO Thread register. */ | |
376 | uint64_t tpidruro_ns; | |
377 | uint64_t tpidrro_el[1]; | |
378 | }; | |
a7adc4b7 PM |
379 | uint64_t c14_cntfrq; /* Counter Frequency register */ |
380 | uint64_t c14_cntkctl; /* Timer Control register */ | |
0b6440af | 381 | uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ |
edac4d8a | 382 | uint64_t cntvoff_el2; /* Counter Virtual Offset register */ |
55d284af | 383 | ARMGenericTimer c14_timer[NUM_GTIMERS]; |
c1713132 | 384 | uint32_t c15_cpar; /* XScale Coprocessor Access Register */ |
c3d2689d AZ |
385 | uint32_t c15_ticonfig; /* TI925T configuration byte. */ |
386 | uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ | |
387 | uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ | |
388 | uint32_t c15_threadid; /* TI debugger thread-ID. */ | |
7da362d0 ML |
389 | uint32_t c15_config_base_address; /* SCU base address. */ |
390 | uint32_t c15_diagnostic; /* diagnostic register */ | |
391 | uint32_t c15_power_diagnostic; | |
392 | uint32_t c15_power_control; /* power control */ | |
0b45451e PM |
393 | uint64_t dbgbvr[16]; /* breakpoint value registers */ |
394 | uint64_t dbgbcr[16]; /* breakpoint control registers */ | |
395 | uint64_t dbgwvr[16]; /* watchpoint value registers */ | |
396 | uint64_t dbgwcr[16]; /* watchpoint control registers */ | |
3a298203 | 397 | uint64_t mdscr_el1; |
1424ca8d | 398 | uint64_t oslsr_el1; /* OS Lock Status */ |
14cc7b54 | 399 | uint64_t mdcr_el2; |
5513c3ab | 400 | uint64_t mdcr_el3; |
7c2cb42b AF |
401 | /* If the counter is enabled, this stores the last time the counter |
402 | * was reset. Otherwise it stores the counter value | |
403 | */ | |
c92c0687 | 404 | uint64_t c15_ccnt; |
8521466b | 405 | uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ |
731de9e6 | 406 | uint64_t vpidr_el2; /* Virtualization Processor ID Register */ |
f0d574d6 | 407 | uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ |
b5ff1b31 | 408 | } cp15; |
40f137e1 | 409 | |
9ee6e8bb PB |
410 | struct { |
411 | uint32_t other_sp; | |
412 | uint32_t vecbase; | |
413 | uint32_t basepri; | |
414 | uint32_t control; | |
2c4da50d PM |
415 | uint32_t ccr; /* Configuration and Control */ |
416 | uint32_t cfsr; /* Configurable Fault Status */ | |
417 | uint32_t hfsr; /* HardFault Status */ | |
418 | uint32_t dfsr; /* Debug Fault Status Register */ | |
419 | uint32_t mmfar; /* MemManage Fault Address */ | |
420 | uint32_t bfar; /* BusFault Address */ | |
29c483a5 | 421 | unsigned mpu_ctrl; /* MPU_CTRL (some bits kept in sctlr_el[1]) */ |
9ee6e8bb | 422 | int exception; |
9ee6e8bb PB |
423 | } v7m; |
424 | ||
abf1172f PM |
425 | /* Information associated with an exception about to be taken: |
426 | * code which raises an exception must set cs->exception_index and | |
427 | * the relevant parts of this structure; the cpu_do_interrupt function | |
428 | * will then set the guest-visible registers as part of the exception | |
429 | * entry process. | |
430 | */ | |
431 | struct { | |
432 | uint32_t syndrome; /* AArch64 format syndrome register */ | |
433 | uint32_t fsr; /* AArch32 format fault status register info */ | |
434 | uint64_t vaddress; /* virtual addr associated with exception, if any */ | |
73710361 | 435 | uint32_t target_el; /* EL the exception should be targeted for */ |
abf1172f PM |
436 | /* If we implement EL2 we will also need to store information |
437 | * about the intermediate physical address for stage 2 faults. | |
438 | */ | |
439 | } exception; | |
440 | ||
fe1479c3 PB |
441 | /* Thumb-2 EE state. */ |
442 | uint32_t teecr; | |
443 | uint32_t teehbr; | |
444 | ||
b7bcbe95 FB |
445 | /* VFP coprocessor state. */ |
446 | struct { | |
3926cc84 AG |
447 | /* VFP/Neon register state. Note that the mapping between S, D and Q |
448 | * views of the register bank differs between AArch64 and AArch32: | |
449 | * In AArch32: | |
450 | * Qn = regs[2n+1]:regs[2n] | |
451 | * Dn = regs[n] | |
452 | * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n | |
453 | * (and regs[32] to regs[63] are inaccessible) | |
454 | * In AArch64: | |
455 | * Qn = regs[2n+1]:regs[2n] | |
456 | * Dn = regs[2n] | |
457 | * Sn = regs[2n] bits 31..0 | |
458 | * This corresponds to the architecturally defined mapping between | |
459 | * the two execution states, and means we do not need to explicitly | |
460 | * map these registers when changing states. | |
461 | */ | |
462 | float64 regs[64]; | |
b7bcbe95 | 463 | |
40f137e1 | 464 | uint32_t xregs[16]; |
b7bcbe95 FB |
465 | /* We store these fpcsr fields separately for convenience. */ |
466 | int vec_len; | |
467 | int vec_stride; | |
468 | ||
9ee6e8bb PB |
469 | /* scratch space when Tn are not sufficient. */ |
470 | uint32_t scratch[8]; | |
3b46e624 | 471 | |
3a492f3a PM |
472 | /* fp_status is the "normal" fp status. standard_fp_status retains |
473 | * values corresponding to the ARM "Standard FPSCR Value", ie | |
474 | * default-NaN, flush-to-zero, round-to-nearest and is used by | |
475 | * any operations (generally Neon) which the architecture defines | |
476 | * as controlled by the standard FPSCR value rather than the FPSCR. | |
477 | * | |
478 | * To avoid having to transfer exception bits around, we simply | |
479 | * say that the FPSCR cumulative exception flags are the logical | |
480 | * OR of the flags in the two fp statuses. This relies on the | |
481 | * only thing which needs to read the exception flags being | |
482 | * an explicit FPSCR read. | |
483 | */ | |
53cd6637 | 484 | float_status fp_status; |
3a492f3a | 485 | float_status standard_fp_status; |
b7bcbe95 | 486 | } vfp; |
03d05e2d PM |
487 | uint64_t exclusive_addr; |
488 | uint64_t exclusive_val; | |
489 | uint64_t exclusive_high; | |
b7bcbe95 | 490 | |
18c9b560 AZ |
491 | /* iwMMXt coprocessor state. */ |
492 | struct { | |
493 | uint64_t regs[16]; | |
494 | uint64_t val; | |
495 | ||
496 | uint32_t cregs[16]; | |
497 | } iwmmxt; | |
498 | ||
ce4defa0 PB |
499 | #if defined(CONFIG_USER_ONLY) |
500 | /* For usermode syscall translation. */ | |
501 | int eabi; | |
502 | #endif | |
503 | ||
46747d15 | 504 | struct CPUBreakpoint *cpu_breakpoint[16]; |
9ee98ce8 PM |
505 | struct CPUWatchpoint *cpu_watchpoint[16]; |
506 | ||
1f5c00cf AB |
507 | /* Fields up to this point are cleared by a CPU reset */ |
508 | struct {} end_reset_fields; | |
509 | ||
a316d335 FB |
510 | CPU_COMMON |
511 | ||
1f5c00cf | 512 | /* Fields after CPU_COMMON are preserved across CPU reset. */ |
9ba8c3f4 | 513 | |
581be094 | 514 | /* Internal CPU feature flags. */ |
918f5dca | 515 | uint64_t features; |
581be094 | 516 | |
6cb0b013 PC |
517 | /* PMSAv7 MPU */ |
518 | struct { | |
519 | uint32_t *drbar; | |
520 | uint32_t *drsr; | |
521 | uint32_t *dracr; | |
522 | } pmsav7; | |
523 | ||
983fe826 | 524 | void *nvic; |
462a8bc6 | 525 | const struct arm_boot_info *boot_info; |
d3a3e529 VK |
526 | /* Store GICv3CPUState to access from this struct */ |
527 | void *gicv3state; | |
2c0262af FB |
528 | } CPUARMState; |
529 | ||
bd7d00fc PM |
530 | /** |
531 | * ARMELChangeHook: | |
532 | * type of a function which can be registered via arm_register_el_change_hook() | |
533 | * to get callbacks when the CPU changes its exception level or mode. | |
534 | */ | |
535 | typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque); | |
536 | ||
062ba099 AB |
537 | |
538 | /* These values map onto the return values for | |
539 | * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ | |
540 | typedef enum ARMPSCIState { | |
d5affb0d AJ |
541 | PSCI_ON = 0, |
542 | PSCI_OFF = 1, | |
062ba099 AB |
543 | PSCI_ON_PENDING = 2 |
544 | } ARMPSCIState; | |
545 | ||
74e75564 PB |
546 | /** |
547 | * ARMCPU: | |
548 | * @env: #CPUARMState | |
549 | * | |
550 | * An ARM CPU core. | |
551 | */ | |
552 | struct ARMCPU { | |
553 | /*< private >*/ | |
554 | CPUState parent_obj; | |
555 | /*< public >*/ | |
556 | ||
557 | CPUARMState env; | |
558 | ||
559 | /* Coprocessor information */ | |
560 | GHashTable *cp_regs; | |
561 | /* For marshalling (mostly coprocessor) register state between the | |
562 | * kernel and QEMU (for KVM) and between two QEMUs (for migration), | |
563 | * we use these arrays. | |
564 | */ | |
565 | /* List of register indexes managed via these arrays; (full KVM style | |
566 | * 64 bit indexes, not CPRegInfo 32 bit indexes) | |
567 | */ | |
568 | uint64_t *cpreg_indexes; | |
569 | /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ | |
570 | uint64_t *cpreg_values; | |
571 | /* Length of the indexes, values, reset_values arrays */ | |
572 | int32_t cpreg_array_len; | |
573 | /* These are used only for migration: incoming data arrives in | |
574 | * these fields and is sanity checked in post_load before copying | |
575 | * to the working data structures above. | |
576 | */ | |
577 | uint64_t *cpreg_vmstate_indexes; | |
578 | uint64_t *cpreg_vmstate_values; | |
579 | int32_t cpreg_vmstate_array_len; | |
580 | ||
581 | /* Timers used by the generic (architected) timer */ | |
582 | QEMUTimer *gt_timer[NUM_GTIMERS]; | |
583 | /* GPIO outputs for generic timer */ | |
584 | qemu_irq gt_timer_outputs[NUM_GTIMERS]; | |
aa1b3111 PM |
585 | /* GPIO output for GICv3 maintenance interrupt signal */ |
586 | qemu_irq gicv3_maintenance_interrupt; | |
74e75564 PB |
587 | |
588 | /* MemoryRegion to use for secure physical accesses */ | |
589 | MemoryRegion *secure_memory; | |
590 | ||
591 | /* 'compatible' string for this CPU for Linux device trees */ | |
592 | const char *dtb_compatible; | |
593 | ||
594 | /* PSCI version for this CPU | |
595 | * Bits[31:16] = Major Version | |
596 | * Bits[15:0] = Minor Version | |
597 | */ | |
598 | uint32_t psci_version; | |
599 | ||
600 | /* Should CPU start in PSCI powered-off state? */ | |
601 | bool start_powered_off; | |
062ba099 AB |
602 | |
603 | /* Current power state, access guarded by BQL */ | |
604 | ARMPSCIState power_state; | |
605 | ||
c25bd18a PM |
606 | /* CPU has virtualization extension */ |
607 | bool has_el2; | |
74e75564 PB |
608 | /* CPU has security extension */ |
609 | bool has_el3; | |
5c0a3819 SZ |
610 | /* CPU has PMU (Performance Monitor Unit) */ |
611 | bool has_pmu; | |
74e75564 PB |
612 | |
613 | /* CPU has memory protection unit */ | |
614 | bool has_mpu; | |
615 | /* PMSAv7 MPU number of supported regions */ | |
616 | uint32_t pmsav7_dregion; | |
617 | ||
618 | /* PSCI conduit used to invoke PSCI methods | |
619 | * 0 - disabled, 1 - smc, 2 - hvc | |
620 | */ | |
621 | uint32_t psci_conduit; | |
622 | ||
623 | /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or | |
624 | * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. | |
625 | */ | |
626 | uint32_t kvm_target; | |
627 | ||
628 | /* KVM init features for this CPU */ | |
629 | uint32_t kvm_init_features[7]; | |
630 | ||
631 | /* Uniprocessor system with MP extensions */ | |
632 | bool mp_is_up; | |
633 | ||
634 | /* The instance init functions for implementation-specific subclasses | |
635 | * set these fields to specify the implementation-dependent values of | |
636 | * various constant registers and reset values of non-constant | |
637 | * registers. | |
638 | * Some of these might become QOM properties eventually. | |
639 | * Field names match the official register names as defined in the | |
640 | * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix | |
641 | * is used for reset values of non-constant registers; no reset_ | |
642 | * prefix means a constant register. | |
643 | */ | |
644 | uint32_t midr; | |
645 | uint32_t revidr; | |
646 | uint32_t reset_fpsid; | |
647 | uint32_t mvfr0; | |
648 | uint32_t mvfr1; | |
649 | uint32_t mvfr2; | |
650 | uint32_t ctr; | |
651 | uint32_t reset_sctlr; | |
652 | uint32_t id_pfr0; | |
653 | uint32_t id_pfr1; | |
654 | uint32_t id_dfr0; | |
655 | uint32_t pmceid0; | |
656 | uint32_t pmceid1; | |
657 | uint32_t id_afr0; | |
658 | uint32_t id_mmfr0; | |
659 | uint32_t id_mmfr1; | |
660 | uint32_t id_mmfr2; | |
661 | uint32_t id_mmfr3; | |
662 | uint32_t id_mmfr4; | |
663 | uint32_t id_isar0; | |
664 | uint32_t id_isar1; | |
665 | uint32_t id_isar2; | |
666 | uint32_t id_isar3; | |
667 | uint32_t id_isar4; | |
668 | uint32_t id_isar5; | |
669 | uint64_t id_aa64pfr0; | |
670 | uint64_t id_aa64pfr1; | |
671 | uint64_t id_aa64dfr0; | |
672 | uint64_t id_aa64dfr1; | |
673 | uint64_t id_aa64afr0; | |
674 | uint64_t id_aa64afr1; | |
675 | uint64_t id_aa64isar0; | |
676 | uint64_t id_aa64isar1; | |
677 | uint64_t id_aa64mmfr0; | |
678 | uint64_t id_aa64mmfr1; | |
679 | uint32_t dbgdidr; | |
680 | uint32_t clidr; | |
681 | uint64_t mp_affinity; /* MP ID without feature bits */ | |
682 | /* The elements of this array are the CCSIDR values for each cache, | |
683 | * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. | |
684 | */ | |
685 | uint32_t ccsidr[16]; | |
686 | uint64_t reset_cbar; | |
687 | uint32_t reset_auxcr; | |
688 | bool reset_hivecs; | |
689 | /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ | |
690 | uint32_t dcz_blocksize; | |
691 | uint64_t rvbar; | |
bd7d00fc | 692 | |
e45868a3 PM |
693 | /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ |
694 | int gic_num_lrs; /* number of list registers */ | |
695 | int gic_vpribits; /* number of virtual priority bits */ | |
696 | int gic_vprebits; /* number of virtual preemption bits */ | |
697 | ||
3a062d57 JB |
698 | /* Whether the cfgend input is high (i.e. this CPU should reset into |
699 | * big-endian mode). This setting isn't used directly: instead it modifies | |
700 | * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the | |
701 | * architecture version. | |
702 | */ | |
703 | bool cfgend; | |
704 | ||
bd7d00fc PM |
705 | ARMELChangeHook *el_change_hook; |
706 | void *el_change_hook_opaque; | |
74e75564 PB |
707 | }; |
708 | ||
709 | static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) | |
710 | { | |
711 | return container_of(env, ARMCPU, env); | |
712 | } | |
713 | ||
46de5913 IM |
714 | uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); |
715 | ||
74e75564 PB |
716 | #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) |
717 | ||
718 | #define ENV_OFFSET offsetof(ARMCPU, env) | |
719 | ||
720 | #ifndef CONFIG_USER_ONLY | |
721 | extern const struct VMStateDescription vmstate_arm_cpu; | |
722 | #endif | |
723 | ||
724 | void arm_cpu_do_interrupt(CPUState *cpu); | |
725 | void arm_v7m_cpu_do_interrupt(CPUState *cpu); | |
726 | bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); | |
727 | ||
728 | void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, | |
729 | int flags); | |
730 | ||
731 | hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, | |
732 | MemTxAttrs *attrs); | |
733 | ||
734 | int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); | |
735 | int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | |
736 | ||
737 | int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, | |
738 | int cpuid, void *opaque); | |
739 | int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, | |
740 | int cpuid, void *opaque); | |
741 | ||
742 | #ifdef TARGET_AARCH64 | |
743 | int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); | |
744 | int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | |
745 | #endif | |
778c3a06 AF |
746 | |
747 | ARMCPU *cpu_arm_init(const char *cpu_model); | |
faacc041 | 748 | target_ulong do_arm_semihosting(CPUARMState *env); |
ce02049d GB |
749 | void aarch64_sync_32_to_64(CPUARMState *env); |
750 | void aarch64_sync_64_to_32(CPUARMState *env); | |
b5ff1b31 | 751 | |
3926cc84 AG |
752 | static inline bool is_a64(CPUARMState *env) |
753 | { | |
754 | return env->aarch64; | |
755 | } | |
756 | ||
2c0262af FB |
757 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
758 | signal handlers to inform the virtual CPU of exceptions. non zero | |
759 | is returned if the signal was handled by the virtual CPU. */ | |
5fafdf24 | 760 | int cpu_arm_signal_handler(int host_signum, void *pinfo, |
2c0262af FB |
761 | void *puc); |
762 | ||
ec7b4ce4 AF |
763 | /** |
764 | * pmccntr_sync | |
765 | * @env: CPUARMState | |
766 | * | |
767 | * Synchronises the counter in the PMCCNTR. This must always be called twice, | |
768 | * once before any action that might affect the timer and again afterwards. | |
769 | * The function is used to swap the state of the register if required. | |
770 | * This only happens when not in user mode (!CONFIG_USER_ONLY) | |
771 | */ | |
772 | void pmccntr_sync(CPUARMState *env); | |
773 | ||
76e3e1bc PM |
774 | /* SCTLR bit meanings. Several bits have been reused in newer |
775 | * versions of the architecture; in that case we define constants | |
776 | * for both old and new bit meanings. Code which tests against those | |
777 | * bits should probably check or otherwise arrange that the CPU | |
778 | * is the architectural version it expects. | |
779 | */ | |
780 | #define SCTLR_M (1U << 0) | |
781 | #define SCTLR_A (1U << 1) | |
782 | #define SCTLR_C (1U << 2) | |
783 | #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ | |
784 | #define SCTLR_SA (1U << 3) | |
785 | #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ | |
786 | #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ | |
787 | #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ | |
788 | #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ | |
789 | #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ | |
790 | #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ | |
791 | #define SCTLR_ITD (1U << 7) /* v8 onward */ | |
792 | #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ | |
793 | #define SCTLR_SED (1U << 8) /* v8 onward */ | |
794 | #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ | |
795 | #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ | |
796 | #define SCTLR_F (1U << 10) /* up to v6 */ | |
797 | #define SCTLR_SW (1U << 10) /* v7 onward */ | |
798 | #define SCTLR_Z (1U << 11) | |
799 | #define SCTLR_I (1U << 12) | |
800 | #define SCTLR_V (1U << 13) | |
801 | #define SCTLR_RR (1U << 14) /* up to v7 */ | |
802 | #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ | |
803 | #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ | |
804 | #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ | |
805 | #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ | |
806 | #define SCTLR_nTWI (1U << 16) /* v8 onward */ | |
807 | #define SCTLR_HA (1U << 17) | |
f6bda88f | 808 | #define SCTLR_BR (1U << 17) /* PMSA only */ |
76e3e1bc PM |
809 | #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ |
810 | #define SCTLR_nTWE (1U << 18) /* v8 onward */ | |
811 | #define SCTLR_WXN (1U << 19) | |
812 | #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ | |
813 | #define SCTLR_UWXN (1U << 20) /* v7 onward */ | |
814 | #define SCTLR_FI (1U << 21) | |
815 | #define SCTLR_U (1U << 22) | |
816 | #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ | |
817 | #define SCTLR_VE (1U << 24) /* up to v7 */ | |
818 | #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ | |
819 | #define SCTLR_EE (1U << 25) | |
820 | #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ | |
821 | #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ | |
822 | #define SCTLR_NMFI (1U << 27) | |
823 | #define SCTLR_TRE (1U << 28) | |
824 | #define SCTLR_AFE (1U << 29) | |
825 | #define SCTLR_TE (1U << 30) | |
826 | ||
c6f19164 GB |
827 | #define CPTR_TCPAC (1U << 31) |
828 | #define CPTR_TTA (1U << 20) | |
829 | #define CPTR_TFP (1U << 10) | |
830 | ||
187f678d PM |
831 | #define MDCR_EPMAD (1U << 21) |
832 | #define MDCR_EDAD (1U << 20) | |
833 | #define MDCR_SPME (1U << 17) | |
834 | #define MDCR_SDD (1U << 16) | |
a8d64e73 | 835 | #define MDCR_SPD (3U << 14) |
187f678d PM |
836 | #define MDCR_TDRA (1U << 11) |
837 | #define MDCR_TDOSA (1U << 10) | |
838 | #define MDCR_TDA (1U << 9) | |
839 | #define MDCR_TDE (1U << 8) | |
840 | #define MDCR_HPME (1U << 7) | |
841 | #define MDCR_TPM (1U << 6) | |
842 | #define MDCR_TPMCR (1U << 5) | |
843 | ||
a8d64e73 PM |
844 | /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ |
845 | #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) | |
846 | ||
78dbbbe4 PM |
847 | #define CPSR_M (0x1fU) |
848 | #define CPSR_T (1U << 5) | |
849 | #define CPSR_F (1U << 6) | |
850 | #define CPSR_I (1U << 7) | |
851 | #define CPSR_A (1U << 8) | |
852 | #define CPSR_E (1U << 9) | |
853 | #define CPSR_IT_2_7 (0xfc00U) | |
854 | #define CPSR_GE (0xfU << 16) | |
4051e12c PM |
855 | #define CPSR_IL (1U << 20) |
856 | /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in | |
857 | * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use | |
858 | * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, | |
859 | * where it is live state but not accessible to the AArch32 code. | |
860 | */ | |
861 | #define CPSR_RESERVED (0x7U << 21) | |
78dbbbe4 PM |
862 | #define CPSR_J (1U << 24) |
863 | #define CPSR_IT_0_1 (3U << 25) | |
864 | #define CPSR_Q (1U << 27) | |
865 | #define CPSR_V (1U << 28) | |
866 | #define CPSR_C (1U << 29) | |
867 | #define CPSR_Z (1U << 30) | |
868 | #define CPSR_N (1U << 31) | |
9ee6e8bb | 869 | #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) |
4cc35614 | 870 | #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) |
9ee6e8bb PB |
871 | |
872 | #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) | |
4cc35614 PM |
873 | #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ |
874 | | CPSR_NZCV) | |
9ee6e8bb PB |
875 | /* Bits writable in user mode. */ |
876 | #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) | |
877 | /* Execution state bits. MRS read as zero, MSR writes ignored. */ | |
4051e12c PM |
878 | #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) |
879 | /* Mask of bits which may be set by exception return copying them from SPSR */ | |
880 | #define CPSR_ERET_MASK (~CPSR_RESERVED) | |
b5ff1b31 | 881 | |
e389be16 FA |
882 | #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ |
883 | #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ | |
884 | #define TTBCR_PD0 (1U << 4) | |
885 | #define TTBCR_PD1 (1U << 5) | |
886 | #define TTBCR_EPD0 (1U << 7) | |
887 | #define TTBCR_IRGN0 (3U << 8) | |
888 | #define TTBCR_ORGN0 (3U << 10) | |
889 | #define TTBCR_SH0 (3U << 12) | |
890 | #define TTBCR_T1SZ (3U << 16) | |
891 | #define TTBCR_A1 (1U << 22) | |
892 | #define TTBCR_EPD1 (1U << 23) | |
893 | #define TTBCR_IRGN1 (3U << 24) | |
894 | #define TTBCR_ORGN1 (3U << 26) | |
895 | #define TTBCR_SH1 (1U << 28) | |
896 | #define TTBCR_EAE (1U << 31) | |
897 | ||
d356312f PM |
898 | /* Bit definitions for ARMv8 SPSR (PSTATE) format. |
899 | * Only these are valid when in AArch64 mode; in | |
900 | * AArch32 mode SPSRs are basically CPSR-format. | |
901 | */ | |
f502cfc2 | 902 | #define PSTATE_SP (1U) |
d356312f PM |
903 | #define PSTATE_M (0xFU) |
904 | #define PSTATE_nRW (1U << 4) | |
905 | #define PSTATE_F (1U << 6) | |
906 | #define PSTATE_I (1U << 7) | |
907 | #define PSTATE_A (1U << 8) | |
908 | #define PSTATE_D (1U << 9) | |
909 | #define PSTATE_IL (1U << 20) | |
910 | #define PSTATE_SS (1U << 21) | |
911 | #define PSTATE_V (1U << 28) | |
912 | #define PSTATE_C (1U << 29) | |
913 | #define PSTATE_Z (1U << 30) | |
914 | #define PSTATE_N (1U << 31) | |
915 | #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) | |
4cc35614 PM |
916 | #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) |
917 | #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) | |
d356312f PM |
918 | /* Mode values for AArch64 */ |
919 | #define PSTATE_MODE_EL3h 13 | |
920 | #define PSTATE_MODE_EL3t 12 | |
921 | #define PSTATE_MODE_EL2h 9 | |
922 | #define PSTATE_MODE_EL2t 8 | |
923 | #define PSTATE_MODE_EL1h 5 | |
924 | #define PSTATE_MODE_EL1t 4 | |
925 | #define PSTATE_MODE_EL0t 0 | |
926 | ||
9e729b57 EI |
927 | /* Map EL and handler into a PSTATE_MODE. */ |
928 | static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) | |
929 | { | |
930 | return (el << 2) | handler; | |
931 | } | |
932 | ||
d356312f PM |
933 | /* Return the current PSTATE value. For the moment we don't support 32<->64 bit |
934 | * interprocessing, so we don't attempt to sync with the cpsr state used by | |
935 | * the 32 bit decoder. | |
936 | */ | |
937 | static inline uint32_t pstate_read(CPUARMState *env) | |
938 | { | |
939 | int ZF; | |
940 | ||
941 | ZF = (env->ZF == 0); | |
942 | return (env->NF & 0x80000000) | (ZF << 30) | |
943 | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | |
4cc35614 | 944 | | env->pstate | env->daif; |
d356312f PM |
945 | } |
946 | ||
947 | static inline void pstate_write(CPUARMState *env, uint32_t val) | |
948 | { | |
949 | env->ZF = (~val) & PSTATE_Z; | |
950 | env->NF = val; | |
951 | env->CF = (val >> 29) & 1; | |
952 | env->VF = (val << 3) & 0x80000000; | |
4cc35614 | 953 | env->daif = val & PSTATE_DAIF; |
d356312f PM |
954 | env->pstate = val & ~CACHED_PSTATE_BITS; |
955 | } | |
956 | ||
b5ff1b31 | 957 | /* Return the current CPSR value. */ |
2f4a40e5 | 958 | uint32_t cpsr_read(CPUARMState *env); |
50866ba5 PM |
959 | |
960 | typedef enum CPSRWriteType { | |
961 | CPSRWriteByInstr = 0, /* from guest MSR or CPS */ | |
962 | CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ | |
963 | CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ | |
964 | CPSRWriteByGDBStub = 3, /* from the GDB stub */ | |
965 | } CPSRWriteType; | |
966 | ||
967 | /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ | |
968 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, | |
969 | CPSRWriteType write_type); | |
9ee6e8bb PB |
970 | |
971 | /* Return the current xPSR value. */ | |
972 | static inline uint32_t xpsr_read(CPUARMState *env) | |
973 | { | |
974 | int ZF; | |
6fbe23d5 PB |
975 | ZF = (env->ZF == 0); |
976 | return (env->NF & 0x80000000) | (ZF << 30) | |
9ee6e8bb PB |
977 | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
978 | | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) | |
979 | | ((env->condexec_bits & 0xfc) << 8) | |
980 | | env->v7m.exception; | |
b5ff1b31 FB |
981 | } |
982 | ||
9ee6e8bb PB |
983 | /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ |
984 | static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | |
985 | { | |
9ee6e8bb | 986 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
987 | env->ZF = (~val) & CPSR_Z; |
988 | env->NF = val; | |
9ee6e8bb PB |
989 | env->CF = (val >> 29) & 1; |
990 | env->VF = (val << 3) & 0x80000000; | |
991 | } | |
992 | if (mask & CPSR_Q) | |
993 | env->QF = ((val & CPSR_Q) != 0); | |
994 | if (mask & (1 << 24)) | |
995 | env->thumb = ((val & (1 << 24)) != 0); | |
996 | if (mask & CPSR_IT_0_1) { | |
997 | env->condexec_bits &= ~3; | |
998 | env->condexec_bits |= (val >> 25) & 3; | |
999 | } | |
1000 | if (mask & CPSR_IT_2_7) { | |
1001 | env->condexec_bits &= 3; | |
1002 | env->condexec_bits |= (val >> 8) & 0xfc; | |
1003 | } | |
1004 | if (mask & 0x1ff) { | |
1005 | env->v7m.exception = val & 0x1ff; | |
1006 | } | |
1007 | } | |
1008 | ||
f149e3e8 EI |
1009 | #define HCR_VM (1ULL << 0) |
1010 | #define HCR_SWIO (1ULL << 1) | |
1011 | #define HCR_PTW (1ULL << 2) | |
1012 | #define HCR_FMO (1ULL << 3) | |
1013 | #define HCR_IMO (1ULL << 4) | |
1014 | #define HCR_AMO (1ULL << 5) | |
1015 | #define HCR_VF (1ULL << 6) | |
1016 | #define HCR_VI (1ULL << 7) | |
1017 | #define HCR_VSE (1ULL << 8) | |
1018 | #define HCR_FB (1ULL << 9) | |
1019 | #define HCR_BSU_MASK (3ULL << 10) | |
1020 | #define HCR_DC (1ULL << 12) | |
1021 | #define HCR_TWI (1ULL << 13) | |
1022 | #define HCR_TWE (1ULL << 14) | |
1023 | #define HCR_TID0 (1ULL << 15) | |
1024 | #define HCR_TID1 (1ULL << 16) | |
1025 | #define HCR_TID2 (1ULL << 17) | |
1026 | #define HCR_TID3 (1ULL << 18) | |
1027 | #define HCR_TSC (1ULL << 19) | |
1028 | #define HCR_TIDCP (1ULL << 20) | |
1029 | #define HCR_TACR (1ULL << 21) | |
1030 | #define HCR_TSW (1ULL << 22) | |
1031 | #define HCR_TPC (1ULL << 23) | |
1032 | #define HCR_TPU (1ULL << 24) | |
1033 | #define HCR_TTLB (1ULL << 25) | |
1034 | #define HCR_TVM (1ULL << 26) | |
1035 | #define HCR_TGE (1ULL << 27) | |
1036 | #define HCR_TDZ (1ULL << 28) | |
1037 | #define HCR_HCD (1ULL << 29) | |
1038 | #define HCR_TRVM (1ULL << 30) | |
1039 | #define HCR_RW (1ULL << 31) | |
1040 | #define HCR_CD (1ULL << 32) | |
1041 | #define HCR_ID (1ULL << 33) | |
1042 | #define HCR_MASK ((1ULL << 34) - 1) | |
1043 | ||
64e0e2de EI |
1044 | #define SCR_NS (1U << 0) |
1045 | #define SCR_IRQ (1U << 1) | |
1046 | #define SCR_FIQ (1U << 2) | |
1047 | #define SCR_EA (1U << 3) | |
1048 | #define SCR_FW (1U << 4) | |
1049 | #define SCR_AW (1U << 5) | |
1050 | #define SCR_NET (1U << 6) | |
1051 | #define SCR_SMD (1U << 7) | |
1052 | #define SCR_HCE (1U << 8) | |
1053 | #define SCR_SIF (1U << 9) | |
1054 | #define SCR_RW (1U << 10) | |
1055 | #define SCR_ST (1U << 11) | |
1056 | #define SCR_TWI (1U << 12) | |
1057 | #define SCR_TWE (1U << 13) | |
1058 | #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) | |
1059 | #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) | |
1060 | ||
01653295 PM |
1061 | /* Return the current FPSCR value. */ |
1062 | uint32_t vfp_get_fpscr(CPUARMState *env); | |
1063 | void vfp_set_fpscr(CPUARMState *env, uint32_t val); | |
1064 | ||
f903fa22 PM |
1065 | /* For A64 the FPSCR is split into two logically distinct registers, |
1066 | * FPCR and FPSR. However since they still use non-overlapping bits | |
1067 | * we store the underlying state in fpscr and just mask on read/write. | |
1068 | */ | |
1069 | #define FPSR_MASK 0xf800009f | |
1070 | #define FPCR_MASK 0x07f79f00 | |
1071 | static inline uint32_t vfp_get_fpsr(CPUARMState *env) | |
1072 | { | |
1073 | return vfp_get_fpscr(env) & FPSR_MASK; | |
1074 | } | |
1075 | ||
1076 | static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) | |
1077 | { | |
1078 | uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); | |
1079 | vfp_set_fpscr(env, new_fpscr); | |
1080 | } | |
1081 | ||
1082 | static inline uint32_t vfp_get_fpcr(CPUARMState *env) | |
1083 | { | |
1084 | return vfp_get_fpscr(env) & FPCR_MASK; | |
1085 | } | |
1086 | ||
1087 | static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) | |
1088 | { | |
1089 | uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); | |
1090 | vfp_set_fpscr(env, new_fpscr); | |
1091 | } | |
1092 | ||
b5ff1b31 FB |
1093 | enum arm_cpu_mode { |
1094 | ARM_CPU_MODE_USR = 0x10, | |
1095 | ARM_CPU_MODE_FIQ = 0x11, | |
1096 | ARM_CPU_MODE_IRQ = 0x12, | |
1097 | ARM_CPU_MODE_SVC = 0x13, | |
28c9457d | 1098 | ARM_CPU_MODE_MON = 0x16, |
b5ff1b31 | 1099 | ARM_CPU_MODE_ABT = 0x17, |
28c9457d | 1100 | ARM_CPU_MODE_HYP = 0x1a, |
b5ff1b31 FB |
1101 | ARM_CPU_MODE_UND = 0x1b, |
1102 | ARM_CPU_MODE_SYS = 0x1f | |
1103 | }; | |
1104 | ||
40f137e1 PB |
1105 | /* VFP system registers. */ |
1106 | #define ARM_VFP_FPSID 0 | |
1107 | #define ARM_VFP_FPSCR 1 | |
a50c0f51 | 1108 | #define ARM_VFP_MVFR2 5 |
9ee6e8bb PB |
1109 | #define ARM_VFP_MVFR1 6 |
1110 | #define ARM_VFP_MVFR0 7 | |
40f137e1 PB |
1111 | #define ARM_VFP_FPEXC 8 |
1112 | #define ARM_VFP_FPINST 9 | |
1113 | #define ARM_VFP_FPINST2 10 | |
1114 | ||
18c9b560 AZ |
1115 | /* iwMMXt coprocessor control registers. */ |
1116 | #define ARM_IWMMXT_wCID 0 | |
1117 | #define ARM_IWMMXT_wCon 1 | |
1118 | #define ARM_IWMMXT_wCSSF 2 | |
1119 | #define ARM_IWMMXT_wCASF 3 | |
1120 | #define ARM_IWMMXT_wCGR0 8 | |
1121 | #define ARM_IWMMXT_wCGR1 9 | |
1122 | #define ARM_IWMMXT_wCGR2 10 | |
1123 | #define ARM_IWMMXT_wCGR3 11 | |
1124 | ||
2c4da50d PM |
1125 | /* V7M CCR bits */ |
1126 | FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) | |
1127 | FIELD(V7M_CCR, USERSETMPEND, 1, 1) | |
1128 | FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) | |
1129 | FIELD(V7M_CCR, DIV_0_TRP, 4, 1) | |
1130 | FIELD(V7M_CCR, BFHFNMIGN, 8, 1) | |
1131 | FIELD(V7M_CCR, STKALIGN, 9, 1) | |
1132 | FIELD(V7M_CCR, DC, 16, 1) | |
1133 | FIELD(V7M_CCR, IC, 17, 1) | |
1134 | ||
1135 | /* V7M CFSR bits for MMFSR */ | |
1136 | FIELD(V7M_CFSR, IACCVIOL, 0, 1) | |
1137 | FIELD(V7M_CFSR, DACCVIOL, 1, 1) | |
1138 | FIELD(V7M_CFSR, MUNSTKERR, 3, 1) | |
1139 | FIELD(V7M_CFSR, MSTKERR, 4, 1) | |
1140 | FIELD(V7M_CFSR, MLSPERR, 5, 1) | |
1141 | FIELD(V7M_CFSR, MMARVALID, 7, 1) | |
1142 | ||
1143 | /* V7M CFSR bits for BFSR */ | |
1144 | FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) | |
1145 | FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) | |
1146 | FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) | |
1147 | FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) | |
1148 | FIELD(V7M_CFSR, STKERR, 8 + 4, 1) | |
1149 | FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) | |
1150 | FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) | |
1151 | ||
1152 | /* V7M CFSR bits for UFSR */ | |
1153 | FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) | |
1154 | FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) | |
1155 | FIELD(V7M_CFSR, INVPC, 16 + 2, 1) | |
1156 | FIELD(V7M_CFSR, NOCP, 16 + 3, 1) | |
1157 | FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) | |
1158 | FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) | |
1159 | ||
1160 | /* V7M HFSR bits */ | |
1161 | FIELD(V7M_HFSR, VECTTBL, 1, 1) | |
1162 | FIELD(V7M_HFSR, FORCED, 30, 1) | |
1163 | FIELD(V7M_HFSR, DEBUGEVT, 31, 1) | |
1164 | ||
1165 | /* V7M DFSR bits */ | |
1166 | FIELD(V7M_DFSR, HALTED, 0, 1) | |
1167 | FIELD(V7M_DFSR, BKPT, 1, 1) | |
1168 | FIELD(V7M_DFSR, DWTTRAP, 2, 1) | |
1169 | FIELD(V7M_DFSR, VCATCH, 3, 1) | |
1170 | FIELD(V7M_DFSR, EXTERNAL, 4, 1) | |
1171 | ||
29c483a5 MD |
1172 | /* v7M MPU_CTRL bits */ |
1173 | FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) | |
1174 | FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) | |
1175 | FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) | |
1176 | ||
ce854d7c BC |
1177 | /* If adding a feature bit which corresponds to a Linux ELF |
1178 | * HWCAP bit, remember to update the feature-bit-to-hwcap | |
1179 | * mapping in linux-user/elfload.c:get_elf_hwcap(). | |
1180 | */ | |
40f137e1 PB |
1181 | enum arm_features { |
1182 | ARM_FEATURE_VFP, | |
c1713132 AZ |
1183 | ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ |
1184 | ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ | |
ce819861 | 1185 | ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ |
9ee6e8bb PB |
1186 | ARM_FEATURE_V6, |
1187 | ARM_FEATURE_V6K, | |
1188 | ARM_FEATURE_V7, | |
1189 | ARM_FEATURE_THUMB2, | |
452a0955 | 1190 | ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ |
9ee6e8bb | 1191 | ARM_FEATURE_VFP3, |
60011498 | 1192 | ARM_FEATURE_VFP_FP16, |
9ee6e8bb | 1193 | ARM_FEATURE_NEON, |
47789990 | 1194 | ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ |
9ee6e8bb | 1195 | ARM_FEATURE_M, /* Microcontroller profile. */ |
fe1479c3 | 1196 | ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ |
e1bbf446 | 1197 | ARM_FEATURE_THUMB2EE, |
be5e7a76 DES |
1198 | ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ |
1199 | ARM_FEATURE_V4T, | |
1200 | ARM_FEATURE_V5, | |
5bc95aa2 | 1201 | ARM_FEATURE_STRONGARM, |
906879a9 | 1202 | ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ |
b8b8ea05 | 1203 | ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ |
da97f52c | 1204 | ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ |
0383ac00 | 1205 | ARM_FEATURE_GENERIC_TIMER, |
06ed5d66 | 1206 | ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ |
1047b9d7 | 1207 | ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ |
c4804214 PM |
1208 | ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ |
1209 | ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ | |
1210 | ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ | |
81bdde9d | 1211 | ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ |
de9b05b8 PM |
1212 | ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ |
1213 | ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ | |
81e69fb0 | 1214 | ARM_FEATURE_V8, |
3926cc84 | 1215 | ARM_FEATURE_AARCH64, /* supports 64 bit mode */ |
9d935509 | 1216 | ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ |
d8ba780b | 1217 | ARM_FEATURE_CBAR, /* has cp15 CBAR */ |
eb0ecd5a | 1218 | ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ |
f318cec6 | 1219 | ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ |
cca7c2f5 | 1220 | ARM_FEATURE_EL2, /* has EL2 Virtualization support */ |
1fe8141e | 1221 | ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ |
f1ecb913 AB |
1222 | ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */ |
1223 | ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ | |
4e624eda | 1224 | ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */ |
62b44f05 | 1225 | ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ |
929e754d | 1226 | ARM_FEATURE_PMU, /* has PMU support */ |
91db4642 | 1227 | ARM_FEATURE_VBAR, /* has cp15 VBAR */ |
40f137e1 PB |
1228 | }; |
1229 | ||
1230 | static inline int arm_feature(CPUARMState *env, int feature) | |
1231 | { | |
918f5dca | 1232 | return (env->features & (1ULL << feature)) != 0; |
40f137e1 PB |
1233 | } |
1234 | ||
19e0fefa FA |
1235 | #if !defined(CONFIG_USER_ONLY) |
1236 | /* Return true if exception levels below EL3 are in secure state, | |
1237 | * or would be following an exception return to that level. | |
1238 | * Unlike arm_is_secure() (which is always a question about the | |
1239 | * _current_ state of the CPU) this doesn't care about the current | |
1240 | * EL or mode. | |
1241 | */ | |
1242 | static inline bool arm_is_secure_below_el3(CPUARMState *env) | |
1243 | { | |
1244 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
1245 | return !(env->cp15.scr_el3 & SCR_NS); | |
1246 | } else { | |
6b7f0b61 | 1247 | /* If EL3 is not supported then the secure state is implementation |
19e0fefa FA |
1248 | * defined, in which case QEMU defaults to non-secure. |
1249 | */ | |
1250 | return false; | |
1251 | } | |
1252 | } | |
1253 | ||
71205876 PM |
1254 | /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ |
1255 | static inline bool arm_is_el3_or_mon(CPUARMState *env) | |
19e0fefa FA |
1256 | { |
1257 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
1258 | if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { | |
1259 | /* CPU currently in AArch64 state and EL3 */ | |
1260 | return true; | |
1261 | } else if (!is_a64(env) && | |
1262 | (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
1263 | /* CPU currently in AArch32 state and monitor mode */ | |
1264 | return true; | |
1265 | } | |
1266 | } | |
71205876 PM |
1267 | return false; |
1268 | } | |
1269 | ||
1270 | /* Return true if the processor is in secure state */ | |
1271 | static inline bool arm_is_secure(CPUARMState *env) | |
1272 | { | |
1273 | if (arm_is_el3_or_mon(env)) { | |
1274 | return true; | |
1275 | } | |
19e0fefa FA |
1276 | return arm_is_secure_below_el3(env); |
1277 | } | |
1278 | ||
1279 | #else | |
1280 | static inline bool arm_is_secure_below_el3(CPUARMState *env) | |
1281 | { | |
1282 | return false; | |
1283 | } | |
1284 | ||
1285 | static inline bool arm_is_secure(CPUARMState *env) | |
1286 | { | |
1287 | return false; | |
1288 | } | |
1289 | #endif | |
1290 | ||
1f79ee32 PM |
1291 | /* Return true if the specified exception level is running in AArch64 state. */ |
1292 | static inline bool arm_el_is_aa64(CPUARMState *env, int el) | |
1293 | { | |
446c81ab PM |
1294 | /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, |
1295 | * and if we're not in EL0 then the state of EL0 isn't well defined.) | |
1f79ee32 | 1296 | */ |
446c81ab PM |
1297 | assert(el >= 1 && el <= 3); |
1298 | bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); | |
592125f8 | 1299 | |
446c81ab PM |
1300 | /* The highest exception level is always at the maximum supported |
1301 | * register width, and then lower levels have a register width controlled | |
1302 | * by bits in the SCR or HCR registers. | |
1f79ee32 | 1303 | */ |
446c81ab PM |
1304 | if (el == 3) { |
1305 | return aa64; | |
1306 | } | |
1307 | ||
1308 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
1309 | aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); | |
1310 | } | |
1311 | ||
1312 | if (el == 2) { | |
1313 | return aa64; | |
1314 | } | |
1315 | ||
1316 | if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) { | |
1317 | aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); | |
1318 | } | |
1319 | ||
1320 | return aa64; | |
1f79ee32 PM |
1321 | } |
1322 | ||
3f342b9e SF |
1323 | /* Function for determing whether guest cp register reads and writes should |
1324 | * access the secure or non-secure bank of a cp register. When EL3 is | |
1325 | * operating in AArch32 state, the NS-bit determines whether the secure | |
1326 | * instance of a cp register should be used. When EL3 is AArch64 (or if | |
1327 | * it doesn't exist at all) then there is no register banking, and all | |
1328 | * accesses are to the non-secure version. | |
1329 | */ | |
1330 | static inline bool access_secure_reg(CPUARMState *env) | |
1331 | { | |
1332 | bool ret = (arm_feature(env, ARM_FEATURE_EL3) && | |
1333 | !arm_el_is_aa64(env, 3) && | |
1334 | !(env->cp15.scr_el3 & SCR_NS)); | |
1335 | ||
1336 | return ret; | |
1337 | } | |
1338 | ||
ea30a4b8 FA |
1339 | /* Macros for accessing a specified CP register bank */ |
1340 | #define A32_BANKED_REG_GET(_env, _regname, _secure) \ | |
1341 | ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) | |
1342 | ||
1343 | #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ | |
1344 | do { \ | |
1345 | if (_secure) { \ | |
1346 | (_env)->cp15._regname##_s = (_val); \ | |
1347 | } else { \ | |
1348 | (_env)->cp15._regname##_ns = (_val); \ | |
1349 | } \ | |
1350 | } while (0) | |
1351 | ||
1352 | /* Macros for automatically accessing a specific CP register bank depending on | |
1353 | * the current secure state of the system. These macros are not intended for | |
1354 | * supporting instruction translation reads/writes as these are dependent | |
1355 | * solely on the SCR.NS bit and not the mode. | |
1356 | */ | |
1357 | #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ | |
1358 | A32_BANKED_REG_GET((_env), _regname, \ | |
2cde031f | 1359 | (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) |
ea30a4b8 FA |
1360 | |
1361 | #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ | |
1362 | A32_BANKED_REG_SET((_env), _regname, \ | |
2cde031f | 1363 | (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ |
ea30a4b8 FA |
1364 | (_val)) |
1365 | ||
9a78eead | 1366 | void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); |
012a906b GB |
1367 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
1368 | uint32_t cur_el, bool secure); | |
40f137e1 | 1369 | |
9ee6e8bb | 1370 | /* Interface between CPU and Interrupt controller. */ |
7ecdaa4a PM |
1371 | #ifndef CONFIG_USER_ONLY |
1372 | bool armv7m_nvic_can_take_pending_exception(void *opaque); | |
1373 | #else | |
1374 | static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) | |
1375 | { | |
1376 | return true; | |
1377 | } | |
1378 | #endif | |
9ee6e8bb | 1379 | void armv7m_nvic_set_pending(void *opaque, int irq); |
a5d82355 | 1380 | void armv7m_nvic_acknowledge_irq(void *opaque); |
aa488fe3 PM |
1381 | /** |
1382 | * armv7m_nvic_complete_irq: complete specified interrupt or exception | |
1383 | * @opaque: the NVIC | |
1384 | * @irq: the exception number to complete | |
1385 | * | |
1386 | * Returns: -1 if the irq was not active | |
1387 | * 1 if completing this irq brought us back to base (no active irqs) | |
1388 | * 0 if there is still an irq active after this one was completed | |
1389 | * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | |
1390 | */ | |
1391 | int armv7m_nvic_complete_irq(void *opaque, int irq); | |
9ee6e8bb | 1392 | |
4b6a83fb PM |
1393 | /* Interface for defining coprocessor registers. |
1394 | * Registers are defined in tables of arm_cp_reginfo structs | |
1395 | * which are passed to define_arm_cp_regs(). | |
1396 | */ | |
1397 | ||
1398 | /* When looking up a coprocessor register we look for it | |
1399 | * via an integer which encodes all of: | |
1400 | * coprocessor number | |
1401 | * Crn, Crm, opc1, opc2 fields | |
1402 | * 32 or 64 bit register (ie is it accessed via MRC/MCR | |
1403 | * or via MRRC/MCRR?) | |
51a79b03 | 1404 | * non-secure/secure bank (AArch32 only) |
4b6a83fb PM |
1405 | * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. |
1406 | * (In this case crn and opc2 should be zero.) | |
f5a0a5a5 PM |
1407 | * For AArch64, there is no 32/64 bit size distinction; |
1408 | * instead all registers have a 2 bit op0, 3 bit op1 and op2, | |
1409 | * and 4 bit CRn and CRm. The encoding patterns are chosen | |
1410 | * to be easy to convert to and from the KVM encodings, and also | |
1411 | * so that the hashtable can contain both AArch32 and AArch64 | |
1412 | * registers (to allow for interprocessing where we might run | |
1413 | * 32 bit code on a 64 bit core). | |
4b6a83fb | 1414 | */ |
f5a0a5a5 PM |
1415 | /* This bit is private to our hashtable cpreg; in KVM register |
1416 | * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 | |
1417 | * in the upper bits of the 64 bit ID. | |
1418 | */ | |
1419 | #define CP_REG_AA64_SHIFT 28 | |
1420 | #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) | |
1421 | ||
51a79b03 PM |
1422 | /* To enable banking of coprocessor registers depending on ns-bit we |
1423 | * add a bit to distinguish between secure and non-secure cpregs in the | |
1424 | * hashtable. | |
1425 | */ | |
1426 | #define CP_REG_NS_SHIFT 29 | |
1427 | #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) | |
1428 | ||
1429 | #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ | |
1430 | ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ | |
1431 | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) | |
4b6a83fb | 1432 | |
f5a0a5a5 PM |
1433 | #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ |
1434 | (CP_REG_AA64_MASK | \ | |
1435 | ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ | |
1436 | ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ | |
1437 | ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ | |
1438 | ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ | |
1439 | ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ | |
1440 | ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) | |
1441 | ||
721fae12 PM |
1442 | /* Convert a full 64 bit KVM register ID to the truncated 32 bit |
1443 | * version used as a key for the coprocessor register hashtable | |
1444 | */ | |
1445 | static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) | |
1446 | { | |
1447 | uint32_t cpregid = kvmid; | |
f5a0a5a5 PM |
1448 | if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { |
1449 | cpregid |= CP_REG_AA64_MASK; | |
51a79b03 PM |
1450 | } else { |
1451 | if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { | |
1452 | cpregid |= (1 << 15); | |
1453 | } | |
1454 | ||
1455 | /* KVM is always non-secure so add the NS flag on AArch32 register | |
1456 | * entries. | |
1457 | */ | |
1458 | cpregid |= 1 << CP_REG_NS_SHIFT; | |
721fae12 PM |
1459 | } |
1460 | return cpregid; | |
1461 | } | |
1462 | ||
1463 | /* Convert a truncated 32 bit hashtable key into the full | |
1464 | * 64 bit KVM register ID. | |
1465 | */ | |
1466 | static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | |
1467 | { | |
f5a0a5a5 PM |
1468 | uint64_t kvmid; |
1469 | ||
1470 | if (cpregid & CP_REG_AA64_MASK) { | |
1471 | kvmid = cpregid & ~CP_REG_AA64_MASK; | |
1472 | kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; | |
721fae12 | 1473 | } else { |
f5a0a5a5 PM |
1474 | kvmid = cpregid & ~(1 << 15); |
1475 | if (cpregid & (1 << 15)) { | |
1476 | kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; | |
1477 | } else { | |
1478 | kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; | |
1479 | } | |
721fae12 PM |
1480 | } |
1481 | return kvmid; | |
1482 | } | |
1483 | ||
4b6a83fb PM |
1484 | /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a |
1485 | * special-behaviour cp reg and bits [15..8] indicate what behaviour | |
1486 | * it has. Otherwise it is a simple cp reg, where CONST indicates that | |
1487 | * TCG can assume the value to be constant (ie load at translate time) | |
1488 | * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END | |
1489 | * indicates that the TB should not be ended after a write to this register | |
1490 | * (the default is that the TB ends after cp writes). OVERRIDE permits | |
1491 | * a register definition to override a previous definition for the | |
1492 | * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the | |
1493 | * old must have the OVERRIDE bit set. | |
7a0e58fa PM |
1494 | * ALIAS indicates that this register is an alias view of some underlying |
1495 | * state which is also visible via another register, and that the other | |
b061a82b SF |
1496 | * register is handling migration and reset; registers marked ALIAS will not be |
1497 | * migrated but may have their state set by syncing of register state from KVM. | |
7a0e58fa PM |
1498 | * NO_RAW indicates that this register has no underlying state and does not |
1499 | * support raw access for state saving/loading; it will not be used for either | |
1500 | * migration or KVM state synchronization. (Typically this is for "registers" | |
1501 | * which are actually used as instructions for cache maintenance and so on.) | |
2452731c PM |
1502 | * IO indicates that this register does I/O and therefore its accesses |
1503 | * need to be surrounded by gen_io_start()/gen_io_end(). In particular, | |
1504 | * registers which implement clocks or timers require this. | |
4b6a83fb PM |
1505 | */ |
1506 | #define ARM_CP_SPECIAL 1 | |
1507 | #define ARM_CP_CONST 2 | |
1508 | #define ARM_CP_64BIT 4 | |
1509 | #define ARM_CP_SUPPRESS_TB_END 8 | |
1510 | #define ARM_CP_OVERRIDE 16 | |
7a0e58fa | 1511 | #define ARM_CP_ALIAS 32 |
2452731c | 1512 | #define ARM_CP_IO 64 |
7a0e58fa | 1513 | #define ARM_CP_NO_RAW 128 |
4b6a83fb PM |
1514 | #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) |
1515 | #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) | |
b0d2b7d0 | 1516 | #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8)) |
0eef9d98 | 1517 | #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8)) |
aca3f40b PM |
1518 | #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8)) |
1519 | #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA | |
4b6a83fb PM |
1520 | /* Used only as a terminator for ARMCPRegInfo lists */ |
1521 | #define ARM_CP_SENTINEL 0xffff | |
1522 | /* Mask of only the flag bits in a type field */ | |
7a0e58fa | 1523 | #define ARM_CP_FLAG_MASK 0xff |
4b6a83fb | 1524 | |
f5a0a5a5 PM |
1525 | /* Valid values for ARMCPRegInfo state field, indicating which of |
1526 | * the AArch32 and AArch64 execution states this register is visible in. | |
1527 | * If the reginfo doesn't explicitly specify then it is AArch32 only. | |
1528 | * If the reginfo is declared to be visible in both states then a second | |
1529 | * reginfo is synthesised for the AArch32 view of the AArch64 register, | |
1530 | * such that the AArch32 view is the lower 32 bits of the AArch64 one. | |
1531 | * Note that we rely on the values of these enums as we iterate through | |
1532 | * the various states in some places. | |
1533 | */ | |
1534 | enum { | |
1535 | ARM_CP_STATE_AA32 = 0, | |
1536 | ARM_CP_STATE_AA64 = 1, | |
1537 | ARM_CP_STATE_BOTH = 2, | |
1538 | }; | |
1539 | ||
c3e30260 FA |
1540 | /* ARM CP register secure state flags. These flags identify security state |
1541 | * attributes for a given CP register entry. | |
1542 | * The existence of both or neither secure and non-secure flags indicates that | |
1543 | * the register has both a secure and non-secure hash entry. A single one of | |
1544 | * these flags causes the register to only be hashed for the specified | |
1545 | * security state. | |
1546 | * Although definitions may have any combination of the S/NS bits, each | |
1547 | * registered entry will only have one to identify whether the entry is secure | |
1548 | * or non-secure. | |
1549 | */ | |
1550 | enum { | |
1551 | ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ | |
1552 | ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ | |
1553 | }; | |
1554 | ||
4b6a83fb PM |
1555 | /* Return true if cptype is a valid type field. This is used to try to |
1556 | * catch errors where the sentinel has been accidentally left off the end | |
1557 | * of a list of registers. | |
1558 | */ | |
1559 | static inline bool cptype_valid(int cptype) | |
1560 | { | |
1561 | return ((cptype & ~ARM_CP_FLAG_MASK) == 0) | |
1562 | || ((cptype & ARM_CP_SPECIAL) && | |
34affeef | 1563 | ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); |
4b6a83fb PM |
1564 | } |
1565 | ||
1566 | /* Access rights: | |
1567 | * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM | |
1568 | * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and | |
1569 | * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 | |
1570 | * (ie any of the privileged modes in Secure state, or Monitor mode). | |
1571 | * If a register is accessible in one privilege level it's always accessible | |
1572 | * in higher privilege levels too. Since "Secure PL1" also follows this rule | |
1573 | * (ie anything visible in PL2 is visible in S-PL1, some things are only | |
1574 | * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the | |
1575 | * terminology a little and call this PL3. | |
f5a0a5a5 PM |
1576 | * In AArch64 things are somewhat simpler as the PLx bits line up exactly |
1577 | * with the ELx exception levels. | |
4b6a83fb PM |
1578 | * |
1579 | * If access permissions for a register are more complex than can be | |
1580 | * described with these bits, then use a laxer set of restrictions, and | |
1581 | * do the more restrictive/complex check inside a helper function. | |
1582 | */ | |
1583 | #define PL3_R 0x80 | |
1584 | #define PL3_W 0x40 | |
1585 | #define PL2_R (0x20 | PL3_R) | |
1586 | #define PL2_W (0x10 | PL3_W) | |
1587 | #define PL1_R (0x08 | PL2_R) | |
1588 | #define PL1_W (0x04 | PL2_W) | |
1589 | #define PL0_R (0x02 | PL1_R) | |
1590 | #define PL0_W (0x01 | PL1_W) | |
1591 | ||
1592 | #define PL3_RW (PL3_R | PL3_W) | |
1593 | #define PL2_RW (PL2_R | PL2_W) | |
1594 | #define PL1_RW (PL1_R | PL1_W) | |
1595 | #define PL0_RW (PL0_R | PL0_W) | |
1596 | ||
75502672 PM |
1597 | /* Return the highest implemented Exception Level */ |
1598 | static inline int arm_highest_el(CPUARMState *env) | |
1599 | { | |
1600 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
1601 | return 3; | |
1602 | } | |
1603 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
1604 | return 2; | |
1605 | } | |
1606 | return 1; | |
1607 | } | |
1608 | ||
dcbff19b GB |
1609 | /* Return the current Exception Level (as per ARMv8; note that this differs |
1610 | * from the ARMv7 Privilege Level). | |
1611 | */ | |
1612 | static inline int arm_current_el(CPUARMState *env) | |
4b6a83fb | 1613 | { |
6d54ed3c PM |
1614 | if (arm_feature(env, ARM_FEATURE_M)) { |
1615 | return !((env->v7m.exception == 0) && (env->v7m.control & 1)); | |
1616 | } | |
1617 | ||
592125f8 | 1618 | if (is_a64(env)) { |
f5a0a5a5 PM |
1619 | return extract32(env->pstate, 2, 2); |
1620 | } | |
1621 | ||
592125f8 FA |
1622 | switch (env->uncached_cpsr & 0x1f) { |
1623 | case ARM_CPU_MODE_USR: | |
4b6a83fb | 1624 | return 0; |
592125f8 FA |
1625 | case ARM_CPU_MODE_HYP: |
1626 | return 2; | |
1627 | case ARM_CPU_MODE_MON: | |
1628 | return 3; | |
1629 | default: | |
1630 | if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { | |
1631 | /* If EL3 is 32-bit then all secure privileged modes run in | |
1632 | * EL3 | |
1633 | */ | |
1634 | return 3; | |
1635 | } | |
1636 | ||
1637 | return 1; | |
4b6a83fb | 1638 | } |
4b6a83fb PM |
1639 | } |
1640 | ||
1641 | typedef struct ARMCPRegInfo ARMCPRegInfo; | |
1642 | ||
f59df3f2 PM |
1643 | typedef enum CPAccessResult { |
1644 | /* Access is permitted */ | |
1645 | CP_ACCESS_OK = 0, | |
1646 | /* Access fails due to a configurable trap or enable which would | |
1647 | * result in a categorized exception syndrome giving information about | |
1648 | * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, | |
38836a2c PM |
1649 | * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or |
1650 | * PL1 if in EL0, otherwise to the current EL). | |
f59df3f2 PM |
1651 | */ |
1652 | CP_ACCESS_TRAP = 1, | |
1653 | /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). | |
1654 | * Note that this is not a catch-all case -- the set of cases which may | |
1655 | * result in this failure is specifically defined by the architecture. | |
1656 | */ | |
1657 | CP_ACCESS_TRAP_UNCATEGORIZED = 2, | |
38836a2c PM |
1658 | /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ |
1659 | CP_ACCESS_TRAP_EL2 = 3, | |
1660 | CP_ACCESS_TRAP_EL3 = 4, | |
e7615726 PM |
1661 | /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ |
1662 | CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, | |
1663 | CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, | |
f2cae609 PM |
1664 | /* Access fails and results in an exception syndrome for an FP access, |
1665 | * trapped directly to EL2 or EL3 | |
1666 | */ | |
1667 | CP_ACCESS_TRAP_FP_EL2 = 7, | |
1668 | CP_ACCESS_TRAP_FP_EL3 = 8, | |
f59df3f2 PM |
1669 | } CPAccessResult; |
1670 | ||
c4241c7d PM |
1671 | /* Access functions for coprocessor registers. These cannot fail and |
1672 | * may not raise exceptions. | |
1673 | */ | |
1674 | typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); | |
1675 | typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, | |
1676 | uint64_t value); | |
f59df3f2 | 1677 | /* Access permission check functions for coprocessor registers. */ |
3f208fd7 PM |
1678 | typedef CPAccessResult CPAccessFn(CPUARMState *env, |
1679 | const ARMCPRegInfo *opaque, | |
1680 | bool isread); | |
4b6a83fb PM |
1681 | /* Hook function for register reset */ |
1682 | typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); | |
1683 | ||
1684 | #define CP_ANY 0xff | |
1685 | ||
1686 | /* Definition of an ARM coprocessor register */ | |
1687 | struct ARMCPRegInfo { | |
1688 | /* Name of register (useful mainly for debugging, need not be unique) */ | |
1689 | const char *name; | |
1690 | /* Location of register: coprocessor number and (crn,crm,opc1,opc2) | |
1691 | * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a | |
1692 | * 'wildcard' field -- any value of that field in the MRC/MCR insn | |
1693 | * will be decoded to this register. The register read and write | |
1694 | * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 | |
1695 | * used by the program, so it is possible to register a wildcard and | |
1696 | * then behave differently on read/write if necessary. | |
1697 | * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 | |
1698 | * must both be zero. | |
f5a0a5a5 PM |
1699 | * For AArch64-visible registers, opc0 is also used. |
1700 | * Since there are no "coprocessors" in AArch64, cp is purely used as a | |
1701 | * way to distinguish (for KVM's benefit) guest-visible system registers | |
1702 | * from demuxed ones provided to preserve the "no side effects on | |
1703 | * KVM register read/write from QEMU" semantics. cp==0x13 is guest | |
1704 | * visible (to match KVM's encoding); cp==0 will be converted to | |
1705 | * cp==0x13 when the ARMCPRegInfo is registered, for convenience. | |
4b6a83fb PM |
1706 | */ |
1707 | uint8_t cp; | |
1708 | uint8_t crn; | |
1709 | uint8_t crm; | |
f5a0a5a5 | 1710 | uint8_t opc0; |
4b6a83fb PM |
1711 | uint8_t opc1; |
1712 | uint8_t opc2; | |
f5a0a5a5 PM |
1713 | /* Execution state in which this register is visible: ARM_CP_STATE_* */ |
1714 | int state; | |
4b6a83fb PM |
1715 | /* Register type: ARM_CP_* bits/values */ |
1716 | int type; | |
1717 | /* Access rights: PL*_[RW] */ | |
1718 | int access; | |
c3e30260 FA |
1719 | /* Security state: ARM_CP_SECSTATE_* bits/values */ |
1720 | int secure; | |
4b6a83fb PM |
1721 | /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when |
1722 | * this register was defined: can be used to hand data through to the | |
1723 | * register read/write functions, since they are passed the ARMCPRegInfo*. | |
1724 | */ | |
1725 | void *opaque; | |
1726 | /* Value of this register, if it is ARM_CP_CONST. Otherwise, if | |
1727 | * fieldoffset is non-zero, the reset value of the register. | |
1728 | */ | |
1729 | uint64_t resetvalue; | |
c3e30260 FA |
1730 | /* Offset of the field in CPUARMState for this register. |
1731 | * | |
1732 | * This is not needed if either: | |
4b6a83fb PM |
1733 | * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs |
1734 | * 2. both readfn and writefn are specified | |
1735 | */ | |
1736 | ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ | |
c3e30260 FA |
1737 | |
1738 | /* Offsets of the secure and non-secure fields in CPUARMState for the | |
1739 | * register if it is banked. These fields are only used during the static | |
1740 | * registration of a register. During hashing the bank associated | |
1741 | * with a given security state is copied to fieldoffset which is used from | |
1742 | * there on out. | |
1743 | * | |
1744 | * It is expected that register definitions use either fieldoffset or | |
1745 | * bank_fieldoffsets in the definition but not both. It is also expected | |
1746 | * that both bank offsets are set when defining a banked register. This | |
1747 | * use indicates that a register is banked. | |
1748 | */ | |
1749 | ptrdiff_t bank_fieldoffsets[2]; | |
1750 | ||
f59df3f2 PM |
1751 | /* Function for making any access checks for this register in addition to |
1752 | * those specified by the 'access' permissions bits. If NULL, no extra | |
1753 | * checks required. The access check is performed at runtime, not at | |
1754 | * translate time. | |
1755 | */ | |
1756 | CPAccessFn *accessfn; | |
4b6a83fb PM |
1757 | /* Function for handling reads of this register. If NULL, then reads |
1758 | * will be done by loading from the offset into CPUARMState specified | |
1759 | * by fieldoffset. | |
1760 | */ | |
1761 | CPReadFn *readfn; | |
1762 | /* Function for handling writes of this register. If NULL, then writes | |
1763 | * will be done by writing to the offset into CPUARMState specified | |
1764 | * by fieldoffset. | |
1765 | */ | |
1766 | CPWriteFn *writefn; | |
7023ec7e PM |
1767 | /* Function for doing a "raw" read; used when we need to copy |
1768 | * coprocessor state to the kernel for KVM or out for | |
1769 | * migration. This only needs to be provided if there is also a | |
c4241c7d | 1770 | * readfn and it has side effects (for instance clear-on-read bits). |
7023ec7e PM |
1771 | */ |
1772 | CPReadFn *raw_readfn; | |
1773 | /* Function for doing a "raw" write; used when we need to copy KVM | |
1774 | * kernel coprocessor state into userspace, or for inbound | |
1775 | * migration. This only needs to be provided if there is also a | |
c4241c7d PM |
1776 | * writefn and it masks out "unwritable" bits or has write-one-to-clear |
1777 | * or similar behaviour. | |
7023ec7e PM |
1778 | */ |
1779 | CPWriteFn *raw_writefn; | |
4b6a83fb PM |
1780 | /* Function for resetting the register. If NULL, then reset will be done |
1781 | * by writing resetvalue to the field specified in fieldoffset. If | |
1782 | * fieldoffset is 0 then no reset will be done. | |
1783 | */ | |
1784 | CPResetFn *resetfn; | |
1785 | }; | |
1786 | ||
1787 | /* Macros which are lvalues for the field in CPUARMState for the | |
1788 | * ARMCPRegInfo *ri. | |
1789 | */ | |
1790 | #define CPREG_FIELD32(env, ri) \ | |
1791 | (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) | |
1792 | #define CPREG_FIELD64(env, ri) \ | |
1793 | (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) | |
1794 | ||
1795 | #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } | |
1796 | ||
1797 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
1798 | const ARMCPRegInfo *regs, void *opaque); | |
1799 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | |
1800 | const ARMCPRegInfo *regs, void *opaque); | |
1801 | static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) | |
1802 | { | |
1803 | define_arm_cp_regs_with_opaque(cpu, regs, 0); | |
1804 | } | |
1805 | static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) | |
1806 | { | |
1807 | define_one_arm_cp_reg_with_opaque(cpu, regs, 0); | |
1808 | } | |
60322b39 | 1809 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); |
4b6a83fb PM |
1810 | |
1811 | /* CPWriteFn that can be used to implement writes-ignored behaviour */ | |
c4241c7d PM |
1812 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
1813 | uint64_t value); | |
4b6a83fb | 1814 | /* CPReadFn that can be used for read-as-zero behaviour */ |
c4241c7d | 1815 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); |
4b6a83fb | 1816 | |
f5a0a5a5 PM |
1817 | /* CPResetFn that does nothing, for use if no reset is required even |
1818 | * if fieldoffset is non zero. | |
1819 | */ | |
1820 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); | |
1821 | ||
67ed771d PM |
1822 | /* Return true if this reginfo struct's field in the cpu state struct |
1823 | * is 64 bits wide. | |
1824 | */ | |
1825 | static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) | |
1826 | { | |
1827 | return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); | |
1828 | } | |
1829 | ||
dcbff19b | 1830 | static inline bool cp_access_ok(int current_el, |
4b6a83fb PM |
1831 | const ARMCPRegInfo *ri, int isread) |
1832 | { | |
dcbff19b | 1833 | return (ri->access >> ((current_el * 2) + isread)) & 1; |
4b6a83fb PM |
1834 | } |
1835 | ||
49a66191 PM |
1836 | /* Raw read of a coprocessor register (as needed for migration, etc) */ |
1837 | uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); | |
1838 | ||
721fae12 PM |
1839 | /** |
1840 | * write_list_to_cpustate | |
1841 | * @cpu: ARMCPU | |
1842 | * | |
1843 | * For each register listed in the ARMCPU cpreg_indexes list, write | |
1844 | * its value from the cpreg_values list into the ARMCPUState structure. | |
1845 | * This updates TCG's working data structures from KVM data or | |
1846 | * from incoming migration state. | |
1847 | * | |
1848 | * Returns: true if all register values were updated correctly, | |
1849 | * false if some register was unknown or could not be written. | |
1850 | * Note that we do not stop early on failure -- we will attempt | |
1851 | * writing all registers in the list. | |
1852 | */ | |
1853 | bool write_list_to_cpustate(ARMCPU *cpu); | |
1854 | ||
1855 | /** | |
1856 | * write_cpustate_to_list: | |
1857 | * @cpu: ARMCPU | |
1858 | * | |
1859 | * For each register listed in the ARMCPU cpreg_indexes list, write | |
1860 | * its value from the ARMCPUState structure into the cpreg_values list. | |
1861 | * This is used to copy info from TCG's working data structures into | |
1862 | * KVM or for outbound migration. | |
1863 | * | |
1864 | * Returns: true if all register values were read correctly, | |
1865 | * false if some register was unknown or could not be read. | |
1866 | * Note that we do not stop early on failure -- we will attempt | |
1867 | * reading all registers in the list. | |
1868 | */ | |
1869 | bool write_cpustate_to_list(ARMCPU *cpu); | |
1870 | ||
9ee6e8bb PB |
1871 | #define ARM_CPUID_TI915T 0x54029152 |
1872 | #define ARM_CPUID_TI925T 0x54029252 | |
40f137e1 | 1873 | |
b5ff1b31 | 1874 | #if defined(CONFIG_USER_ONLY) |
2c0262af | 1875 | #define TARGET_PAGE_BITS 12 |
b5ff1b31 | 1876 | #else |
e97da98f PM |
1877 | /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6 |
1878 | * have to support 1K tiny pages. | |
1879 | */ | |
1880 | #define TARGET_PAGE_BITS_VARY | |
1881 | #define TARGET_PAGE_BITS_MIN 10 | |
b5ff1b31 | 1882 | #endif |
9467d44c | 1883 | |
3926cc84 AG |
1884 | #if defined(TARGET_AARCH64) |
1885 | # define TARGET_PHYS_ADDR_SPACE_BITS 48 | |
1886 | # define TARGET_VIRT_ADDR_SPACE_BITS 64 | |
1887 | #else | |
1888 | # define TARGET_PHYS_ADDR_SPACE_BITS 40 | |
1889 | # define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
1890 | #endif | |
52705890 | 1891 | |
012a906b GB |
1892 | static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, |
1893 | unsigned int target_el) | |
043b7f8d EI |
1894 | { |
1895 | CPUARMState *env = cs->env_ptr; | |
dcbff19b | 1896 | unsigned int cur_el = arm_current_el(env); |
57e3a0c7 | 1897 | bool secure = arm_is_secure(env); |
57e3a0c7 GB |
1898 | bool pstate_unmasked; |
1899 | int8_t unmasked = 0; | |
1900 | ||
1901 | /* Don't take exceptions if they target a lower EL. | |
1902 | * This check should catch any exceptions that would not be taken but left | |
1903 | * pending. | |
1904 | */ | |
dfafd090 EI |
1905 | if (cur_el > target_el) { |
1906 | return false; | |
1907 | } | |
043b7f8d EI |
1908 | |
1909 | switch (excp_idx) { | |
1910 | case EXCP_FIQ: | |
57e3a0c7 GB |
1911 | pstate_unmasked = !(env->daif & PSTATE_F); |
1912 | break; | |
1913 | ||
043b7f8d | 1914 | case EXCP_IRQ: |
57e3a0c7 GB |
1915 | pstate_unmasked = !(env->daif & PSTATE_I); |
1916 | break; | |
1917 | ||
136e67e9 | 1918 | case EXCP_VFIQ: |
9fae24f5 | 1919 | if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) { |
136e67e9 EI |
1920 | /* VFIQs are only taken when hypervized and non-secure. */ |
1921 | return false; | |
1922 | } | |
1923 | return !(env->daif & PSTATE_F); | |
1924 | case EXCP_VIRQ: | |
9fae24f5 | 1925 | if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) { |
136e67e9 EI |
1926 | /* VIRQs are only taken when hypervized and non-secure. */ |
1927 | return false; | |
1928 | } | |
b5c633c5 | 1929 | return !(env->daif & PSTATE_I); |
043b7f8d EI |
1930 | default: |
1931 | g_assert_not_reached(); | |
1932 | } | |
57e3a0c7 GB |
1933 | |
1934 | /* Use the target EL, current execution state and SCR/HCR settings to | |
1935 | * determine whether the corresponding CPSR bit is used to mask the | |
1936 | * interrupt. | |
1937 | */ | |
1938 | if ((target_el > cur_el) && (target_el != 1)) { | |
7cd6de3b PM |
1939 | /* Exceptions targeting a higher EL may not be maskable */ |
1940 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
1941 | /* 64-bit masking rules are simple: exceptions to EL3 | |
1942 | * can't be masked, and exceptions to EL2 can only be | |
1943 | * masked from Secure state. The HCR and SCR settings | |
1944 | * don't affect the masking logic, only the interrupt routing. | |
1945 | */ | |
1946 | if (target_el == 3 || !secure) { | |
1947 | unmasked = 1; | |
1948 | } | |
1949 | } else { | |
1950 | /* The old 32-bit-only environment has a more complicated | |
1951 | * masking setup. HCR and SCR bits not only affect interrupt | |
1952 | * routing but also change the behaviour of masking. | |
1953 | */ | |
1954 | bool hcr, scr; | |
1955 | ||
1956 | switch (excp_idx) { | |
1957 | case EXCP_FIQ: | |
1958 | /* If FIQs are routed to EL3 or EL2 then there are cases where | |
1959 | * we override the CPSR.F in determining if the exception is | |
1960 | * masked or not. If neither of these are set then we fall back | |
1961 | * to the CPSR.F setting otherwise we further assess the state | |
1962 | * below. | |
1963 | */ | |
1964 | hcr = (env->cp15.hcr_el2 & HCR_FMO); | |
1965 | scr = (env->cp15.scr_el3 & SCR_FIQ); | |
1966 | ||
1967 | /* When EL3 is 32-bit, the SCR.FW bit controls whether the | |
1968 | * CPSR.F bit masks FIQ interrupts when taken in non-secure | |
1969 | * state. If SCR.FW is set then FIQs can be masked by CPSR.F | |
1970 | * when non-secure but only when FIQs are only routed to EL3. | |
1971 | */ | |
1972 | scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); | |
1973 | break; | |
1974 | case EXCP_IRQ: | |
1975 | /* When EL3 execution state is 32-bit, if HCR.IMO is set then | |
1976 | * we may override the CPSR.I masking when in non-secure state. | |
1977 | * The SCR.IRQ setting has already been taken into consideration | |
1978 | * when setting the target EL, so it does not have a further | |
1979 | * affect here. | |
1980 | */ | |
1981 | hcr = (env->cp15.hcr_el2 & HCR_IMO); | |
1982 | scr = false; | |
1983 | break; | |
1984 | default: | |
1985 | g_assert_not_reached(); | |
1986 | } | |
1987 | ||
1988 | if ((scr || hcr) && !secure) { | |
1989 | unmasked = 1; | |
1990 | } | |
57e3a0c7 GB |
1991 | } |
1992 | } | |
1993 | ||
1994 | /* The PSTATE bits only mask the interrupt if we have not overriden the | |
1995 | * ability above. | |
1996 | */ | |
1997 | return unmasked || pstate_unmasked; | |
043b7f8d EI |
1998 | } |
1999 | ||
2994fd96 | 2000 | #define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model)) |
ad37ad5b | 2001 | |
9467d44c | 2002 | #define cpu_signal_handler cpu_arm_signal_handler |
c732abe2 | 2003 | #define cpu_list arm_cpu_list |
9467d44c | 2004 | |
c1e37810 PM |
2005 | /* ARM has the following "translation regimes" (as the ARM ARM calls them): |
2006 | * | |
2007 | * If EL3 is 64-bit: | |
2008 | * + NonSecure EL1 & 0 stage 1 | |
2009 | * + NonSecure EL1 & 0 stage 2 | |
2010 | * + NonSecure EL2 | |
2011 | * + Secure EL1 & EL0 | |
2012 | * + Secure EL3 | |
2013 | * If EL3 is 32-bit: | |
2014 | * + NonSecure PL1 & 0 stage 1 | |
2015 | * + NonSecure PL1 & 0 stage 2 | |
2016 | * + NonSecure PL2 | |
2017 | * + Secure PL0 & PL1 | |
2018 | * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) | |
2019 | * | |
2020 | * For QEMU, an mmu_idx is not quite the same as a translation regime because: | |
2021 | * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they | |
2022 | * may differ in access permissions even if the VA->PA map is the same | |
2023 | * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 | |
2024 | * translation, which means that we have one mmu_idx that deals with two | |
2025 | * concatenated translation regimes [this sort of combined s1+2 TLB is | |
2026 | * architecturally permitted] | |
2027 | * 3. we don't need to allocate an mmu_idx to translations that we won't be | |
2028 | * handling via the TLB. The only way to do a stage 1 translation without | |
2029 | * the immediate stage 2 translation is via the ATS or AT system insns, | |
2030 | * which can be slow-pathed and always do a page table walk. | |
2031 | * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" | |
2032 | * translation regimes, because they map reasonably well to each other | |
2033 | * and they can't both be active at the same time. | |
2034 | * This gives us the following list of mmu_idx values: | |
2035 | * | |
2036 | * NS EL0 (aka NS PL0) stage 1+2 | |
2037 | * NS EL1 (aka NS PL1) stage 1+2 | |
2038 | * NS EL2 (aka NS PL2) | |
2039 | * S EL3 (aka S PL1) | |
2040 | * S EL0 (aka S PL0) | |
2041 | * S EL1 (not used if EL3 is 32 bit) | |
2042 | * NS EL0+1 stage 2 | |
2043 | * | |
2044 | * (The last of these is an mmu_idx because we want to be able to use the TLB | |
2045 | * for the accesses done as part of a stage 1 page table walk, rather than | |
2046 | * having to walk the stage 2 page table over and over.) | |
2047 | * | |
8bd5c820 PM |
2048 | * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code |
2049 | * are not quite the same -- different CPU types (most notably M profile | |
2050 | * vs A/R profile) would like to use MMU indexes with different semantics, | |
2051 | * but since we don't ever need to use all of those in a single CPU we | |
2052 | * can avoid setting NB_MMU_MODES to more than 8. The lower bits of | |
2053 | * ARMMMUIdx are the core TLB mmu index, and the higher bits are always | |
2054 | * the same for any particular CPU. | |
2055 | * Variables of type ARMMUIdx are always full values, and the core | |
2056 | * index values are in variables of type 'int'. | |
2057 | * | |
c1e37810 PM |
2058 | * Our enumeration includes at the end some entries which are not "true" |
2059 | * mmu_idx values in that they don't have corresponding TLBs and are only | |
2060 | * valid for doing slow path page table walks. | |
2061 | * | |
2062 | * The constant names here are patterned after the general style of the names | |
2063 | * of the AT/ATS operations. | |
2064 | * The values used are carefully arranged to make mmu_idx => EL lookup easy. | |
2065 | */ | |
e7b921c2 | 2066 | #define ARM_MMU_IDX_A 0x10 /* A profile */ |
8bd5c820 | 2067 | #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ |
e7b921c2 | 2068 | #define ARM_MMU_IDX_M 0x40 /* M profile */ |
8bd5c820 PM |
2069 | |
2070 | #define ARM_MMU_IDX_TYPE_MASK (~0x7) | |
2071 | #define ARM_MMU_IDX_COREIDX_MASK 0x7 | |
2072 | ||
c1e37810 | 2073 | typedef enum ARMMMUIdx { |
8bd5c820 PM |
2074 | ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A, |
2075 | ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A, | |
2076 | ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, | |
2077 | ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, | |
2078 | ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, | |
2079 | ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, | |
2080 | ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A, | |
e7b921c2 PM |
2081 | ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, |
2082 | ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, | |
c1e37810 PM |
2083 | /* Indexes below here don't have TLBs and are used only for AT system |
2084 | * instructions or for the first stage of an S12 page table walk. | |
2085 | */ | |
8bd5c820 PM |
2086 | ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, |
2087 | ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, | |
c1e37810 PM |
2088 | } ARMMMUIdx; |
2089 | ||
8bd5c820 PM |
2090 | /* Bit macros for the core-mmu-index values for each index, |
2091 | * for use when calling tlb_flush_by_mmuidx() and friends. | |
2092 | */ | |
2093 | typedef enum ARMMMUIdxBit { | |
2094 | ARMMMUIdxBit_S12NSE0 = 1 << 0, | |
2095 | ARMMMUIdxBit_S12NSE1 = 1 << 1, | |
2096 | ARMMMUIdxBit_S1E2 = 1 << 2, | |
2097 | ARMMMUIdxBit_S1E3 = 1 << 3, | |
2098 | ARMMMUIdxBit_S1SE0 = 1 << 4, | |
2099 | ARMMMUIdxBit_S1SE1 = 1 << 5, | |
2100 | ARMMMUIdxBit_S2NS = 1 << 6, | |
e7b921c2 PM |
2101 | ARMMMUIdxBit_MUser = 1 << 0, |
2102 | ARMMMUIdxBit_MPriv = 1 << 1, | |
8bd5c820 PM |
2103 | } ARMMMUIdxBit; |
2104 | ||
f79fbf39 | 2105 | #define MMU_USER_IDX 0 |
c1e37810 | 2106 | |
8bd5c820 PM |
2107 | static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) |
2108 | { | |
2109 | return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; | |
2110 | } | |
2111 | ||
2112 | static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) | |
2113 | { | |
e7b921c2 PM |
2114 | if (arm_feature(env, ARM_FEATURE_M)) { |
2115 | return mmu_idx | ARM_MMU_IDX_M; | |
2116 | } else { | |
2117 | return mmu_idx | ARM_MMU_IDX_A; | |
2118 | } | |
8bd5c820 PM |
2119 | } |
2120 | ||
c1e37810 PM |
2121 | /* Return the exception level we're running at if this is our mmu_idx */ |
2122 | static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) | |
6ebbf390 | 2123 | { |
8bd5c820 PM |
2124 | switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) { |
2125 | case ARM_MMU_IDX_A: | |
2126 | return mmu_idx & 3; | |
e7b921c2 PM |
2127 | case ARM_MMU_IDX_M: |
2128 | return mmu_idx & 1; | |
8bd5c820 PM |
2129 | default: |
2130 | g_assert_not_reached(); | |
2131 | } | |
c1e37810 PM |
2132 | } |
2133 | ||
2134 | /* Determine the current mmu_idx to use for normal loads/stores */ | |
97ed5ccd | 2135 | static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) |
c1e37810 PM |
2136 | { |
2137 | int el = arm_current_el(env); | |
2138 | ||
e7b921c2 PM |
2139 | if (arm_feature(env, ARM_FEATURE_M)) { |
2140 | ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv; | |
2141 | ||
2142 | return arm_to_core_mmu_idx(mmu_idx); | |
2143 | } | |
2144 | ||
c1e37810 | 2145 | if (el < 2 && arm_is_secure_below_el3(env)) { |
8bd5c820 | 2146 | return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el); |
c1e37810 PM |
2147 | } |
2148 | return el; | |
6ebbf390 JM |
2149 | } |
2150 | ||
9e273ef2 PM |
2151 | /* Indexes used when registering address spaces with cpu_address_space_init */ |
2152 | typedef enum ARMASIdx { | |
2153 | ARMASIdx_NS = 0, | |
2154 | ARMASIdx_S = 1, | |
2155 | } ARMASIdx; | |
2156 | ||
533e93f1 | 2157 | /* Return the Exception Level targeted by debug exceptions. */ |
3a298203 PM |
2158 | static inline int arm_debug_target_el(CPUARMState *env) |
2159 | { | |
81669b8b SF |
2160 | bool secure = arm_is_secure(env); |
2161 | bool route_to_el2 = false; | |
2162 | ||
2163 | if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { | |
2164 | route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || | |
2165 | env->cp15.mdcr_el2 & (1 << 8); | |
2166 | } | |
2167 | ||
2168 | if (route_to_el2) { | |
2169 | return 2; | |
2170 | } else if (arm_feature(env, ARM_FEATURE_EL3) && | |
2171 | !arm_el_is_aa64(env, 3) && secure) { | |
2172 | return 3; | |
2173 | } else { | |
2174 | return 1; | |
2175 | } | |
3a298203 PM |
2176 | } |
2177 | ||
2178 | static inline bool aa64_generate_debug_exceptions(CPUARMState *env) | |
2179 | { | |
533e93f1 PM |
2180 | if (arm_is_secure(env)) { |
2181 | /* MDCR_EL3.SDD disables debug events from Secure state */ | |
2182 | if (extract32(env->cp15.mdcr_el3, 16, 1) != 0 | |
2183 | || arm_current_el(env) == 3) { | |
2184 | return false; | |
2185 | } | |
2186 | } | |
2187 | ||
dcbff19b | 2188 | if (arm_current_el(env) == arm_debug_target_el(env)) { |
3a298203 PM |
2189 | if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0) |
2190 | || (env->daif & PSTATE_D)) { | |
2191 | return false; | |
2192 | } | |
2193 | } | |
2194 | return true; | |
2195 | } | |
2196 | ||
2197 | static inline bool aa32_generate_debug_exceptions(CPUARMState *env) | |
2198 | { | |
533e93f1 PM |
2199 | int el = arm_current_el(env); |
2200 | ||
2201 | if (el == 0 && arm_el_is_aa64(env, 1)) { | |
3a298203 PM |
2202 | return aa64_generate_debug_exceptions(env); |
2203 | } | |
533e93f1 PM |
2204 | |
2205 | if (arm_is_secure(env)) { | |
2206 | int spd; | |
2207 | ||
2208 | if (el == 0 && (env->cp15.sder & 1)) { | |
2209 | /* SDER.SUIDEN means debug exceptions from Secure EL0 | |
2210 | * are always enabled. Otherwise they are controlled by | |
2211 | * SDCR.SPD like those from other Secure ELs. | |
2212 | */ | |
2213 | return true; | |
2214 | } | |
2215 | ||
2216 | spd = extract32(env->cp15.mdcr_el3, 14, 2); | |
2217 | switch (spd) { | |
2218 | case 1: | |
2219 | /* SPD == 0b01 is reserved, but behaves as 0b00. */ | |
2220 | case 0: | |
2221 | /* For 0b00 we return true if external secure invasive debug | |
2222 | * is enabled. On real hardware this is controlled by external | |
2223 | * signals to the core. QEMU always permits debug, and behaves | |
2224 | * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. | |
2225 | */ | |
2226 | return true; | |
2227 | case 2: | |
2228 | return false; | |
2229 | case 3: | |
2230 | return true; | |
2231 | } | |
2232 | } | |
2233 | ||
2234 | return el != 2; | |
3a298203 PM |
2235 | } |
2236 | ||
2237 | /* Return true if debugging exceptions are currently enabled. | |
2238 | * This corresponds to what in ARM ARM pseudocode would be | |
2239 | * if UsingAArch32() then | |
2240 | * return AArch32.GenerateDebugExceptions() | |
2241 | * else | |
2242 | * return AArch64.GenerateDebugExceptions() | |
2243 | * We choose to push the if() down into this function for clarity, | |
2244 | * since the pseudocode has it at all callsites except for the one in | |
2245 | * CheckSoftwareStep(), where it is elided because both branches would | |
2246 | * always return the same value. | |
2247 | * | |
2248 | * Parts of the pseudocode relating to EL2 and EL3 are omitted because we | |
2249 | * don't yet implement those exception levels or their associated trap bits. | |
2250 | */ | |
2251 | static inline bool arm_generate_debug_exceptions(CPUARMState *env) | |
2252 | { | |
2253 | if (env->aarch64) { | |
2254 | return aa64_generate_debug_exceptions(env); | |
2255 | } else { | |
2256 | return aa32_generate_debug_exceptions(env); | |
2257 | } | |
2258 | } | |
2259 | ||
2260 | /* Is single-stepping active? (Note that the "is EL_D AArch64?" check | |
2261 | * implicitly means this always returns false in pre-v8 CPUs.) | |
2262 | */ | |
2263 | static inline bool arm_singlestep_active(CPUARMState *env) | |
2264 | { | |
2265 | return extract32(env->cp15.mdscr_el1, 0, 1) | |
2266 | && arm_el_is_aa64(env, arm_debug_target_el(env)) | |
2267 | && arm_generate_debug_exceptions(env); | |
2268 | } | |
2269 | ||
f9fd40eb PB |
2270 | static inline bool arm_sctlr_b(CPUARMState *env) |
2271 | { | |
2272 | return | |
2273 | /* We need not implement SCTLR.ITD in user-mode emulation, so | |
2274 | * let linux-user ignore the fact that it conflicts with SCTLR_B. | |
2275 | * This lets people run BE32 binaries with "-cpu any". | |
2276 | */ | |
2277 | #ifndef CONFIG_USER_ONLY | |
2278 | !arm_feature(env, ARM_FEATURE_V7) && | |
2279 | #endif | |
2280 | (env->cp15.sctlr_el[1] & SCTLR_B) != 0; | |
2281 | } | |
2282 | ||
ed50ff78 PC |
2283 | /* Return true if the processor is in big-endian mode. */ |
2284 | static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) | |
2285 | { | |
2286 | int cur_el; | |
2287 | ||
2288 | /* In 32bit endianness is determined by looking at CPSR's E bit */ | |
2289 | if (!is_a64(env)) { | |
b2e62d9a PC |
2290 | return |
2291 | #ifdef CONFIG_USER_ONLY | |
2292 | /* In system mode, BE32 is modelled in line with the | |
2293 | * architecture (as word-invariant big-endianness), where loads | |
2294 | * and stores are done little endian but from addresses which | |
2295 | * are adjusted by XORing with the appropriate constant. So the | |
2296 | * endianness to use for the raw data access is not affected by | |
2297 | * SCTLR.B. | |
2298 | * In user mode, however, we model BE32 as byte-invariant | |
2299 | * big-endianness (because user-only code cannot tell the | |
2300 | * difference), and so we need to use a data access endianness | |
2301 | * that depends on SCTLR.B. | |
2302 | */ | |
2303 | arm_sctlr_b(env) || | |
2304 | #endif | |
2305 | ((env->uncached_cpsr & CPSR_E) ? 1 : 0); | |
ed50ff78 PC |
2306 | } |
2307 | ||
2308 | cur_el = arm_current_el(env); | |
2309 | ||
2310 | if (cur_el == 0) { | |
2311 | return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; | |
2312 | } | |
2313 | ||
2314 | return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; | |
2315 | } | |
2316 | ||
022c62cb | 2317 | #include "exec/cpu-all.h" |
622ed360 | 2318 | |
3926cc84 AG |
2319 | /* Bit usage in the TB flags field: bit 31 indicates whether we are |
2320 | * in 32 or 64 bit mode. The meaning of the other bits depends on that. | |
c1e37810 PM |
2321 | * We put flags which are shared between 32 and 64 bit mode at the top |
2322 | * of the word, and flags which apply to only one mode at the bottom. | |
3926cc84 AG |
2323 | */ |
2324 | #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 | |
2325 | #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) | |
c1e37810 PM |
2326 | #define ARM_TBFLAG_MMUIDX_SHIFT 28 |
2327 | #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT) | |
3cf6a0fc PM |
2328 | #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27 |
2329 | #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT) | |
2330 | #define ARM_TBFLAG_PSTATE_SS_SHIFT 26 | |
2331 | #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT) | |
9dbbc748 GB |
2332 | /* Target EL if we take a floating-point-disabled exception */ |
2333 | #define ARM_TBFLAG_FPEXC_EL_SHIFT 24 | |
2334 | #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT) | |
3926cc84 AG |
2335 | |
2336 | /* Bit usage when in AArch32 state: */ | |
a1705768 PM |
2337 | #define ARM_TBFLAG_THUMB_SHIFT 0 |
2338 | #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) | |
2339 | #define ARM_TBFLAG_VECLEN_SHIFT 1 | |
2340 | #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) | |
2341 | #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 | |
2342 | #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) | |
a1705768 PM |
2343 | #define ARM_TBFLAG_VFPEN_SHIFT 7 |
2344 | #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) | |
2345 | #define ARM_TBFLAG_CONDEXEC_SHIFT 8 | |
2346 | #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) | |
f9fd40eb PB |
2347 | #define ARM_TBFLAG_SCTLR_B_SHIFT 16 |
2348 | #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT) | |
c0f4af17 PM |
2349 | /* We store the bottom two bits of the CPAR as TB flags and handle |
2350 | * checks on the other bits at runtime | |
2351 | */ | |
647f767b | 2352 | #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 |
c0f4af17 | 2353 | #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) |
3f342b9e SF |
2354 | /* Indicates whether cp register reads and writes by guest code should access |
2355 | * the secure or nonsecure bank of banked registers; note that this is not | |
2356 | * the same thing as the current security state of the processor! | |
2357 | */ | |
647f767b | 2358 | #define ARM_TBFLAG_NS_SHIFT 19 |
3f342b9e | 2359 | #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) |
91cca2cd PC |
2360 | #define ARM_TBFLAG_BE_DATA_SHIFT 20 |
2361 | #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT) | |
064c379c PM |
2362 | /* For M profile only, Handler (ie not Thread) mode */ |
2363 | #define ARM_TBFLAG_HANDLER_SHIFT 21 | |
2364 | #define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT) | |
3926cc84 | 2365 | |
86fb3fa4 TH |
2366 | /* Bit usage when in AArch64 state */ |
2367 | #define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */ | |
2368 | #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT) | |
2369 | #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */ | |
2370 | #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT) | |
a1705768 PM |
2371 | |
2372 | /* some convenience accessor macros */ | |
3926cc84 AG |
2373 | #define ARM_TBFLAG_AARCH64_STATE(F) \ |
2374 | (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) | |
c1e37810 PM |
2375 | #define ARM_TBFLAG_MMUIDX(F) \ |
2376 | (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT) | |
3cf6a0fc PM |
2377 | #define ARM_TBFLAG_SS_ACTIVE(F) \ |
2378 | (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT) | |
2379 | #define ARM_TBFLAG_PSTATE_SS(F) \ | |
2380 | (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT) | |
9dbbc748 GB |
2381 | #define ARM_TBFLAG_FPEXC_EL(F) \ |
2382 | (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT) | |
a1705768 PM |
2383 | #define ARM_TBFLAG_THUMB(F) \ |
2384 | (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) | |
2385 | #define ARM_TBFLAG_VECLEN(F) \ | |
2386 | (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) | |
2387 | #define ARM_TBFLAG_VECSTRIDE(F) \ | |
2388 | (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) | |
a1705768 PM |
2389 | #define ARM_TBFLAG_VFPEN(F) \ |
2390 | (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) | |
2391 | #define ARM_TBFLAG_CONDEXEC(F) \ | |
2392 | (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) | |
f9fd40eb PB |
2393 | #define ARM_TBFLAG_SCTLR_B(F) \ |
2394 | (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT) | |
c0f4af17 PM |
2395 | #define ARM_TBFLAG_XSCALE_CPAR(F) \ |
2396 | (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT) | |
3f342b9e SF |
2397 | #define ARM_TBFLAG_NS(F) \ |
2398 | (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) | |
91cca2cd PC |
2399 | #define ARM_TBFLAG_BE_DATA(F) \ |
2400 | (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT) | |
064c379c PM |
2401 | #define ARM_TBFLAG_HANDLER(F) \ |
2402 | (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT) | |
86fb3fa4 TH |
2403 | #define ARM_TBFLAG_TBI0(F) \ |
2404 | (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT) | |
2405 | #define ARM_TBFLAG_TBI1(F) \ | |
2406 | (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT) | |
a1705768 | 2407 | |
f9fd40eb PB |
2408 | static inline bool bswap_code(bool sctlr_b) |
2409 | { | |
2410 | #ifdef CONFIG_USER_ONLY | |
2411 | /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. | |
2412 | * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 | |
2413 | * would also end up as a mixed-endian mode with BE code, LE data. | |
2414 | */ | |
2415 | return | |
2416 | #ifdef TARGET_WORDS_BIGENDIAN | |
2417 | 1 ^ | |
2418 | #endif | |
2419 | sctlr_b; | |
2420 | #else | |
e334bd31 PB |
2421 | /* All code access in ARM is little endian, and there are no loaders |
2422 | * doing swaps that need to be reversed | |
f9fd40eb PB |
2423 | */ |
2424 | return 0; | |
2425 | #endif | |
2426 | } | |
2427 | ||
9dbbc748 GB |
2428 | /* Return the exception level to which FP-disabled exceptions should |
2429 | * be taken, or 0 if FP is enabled. | |
2430 | */ | |
2431 | static inline int fp_exception_el(CPUARMState *env) | |
6b917547 | 2432 | { |
ed1f13d6 | 2433 | int fpen; |
9dbbc748 | 2434 | int cur_el = arm_current_el(env); |
ed1f13d6 | 2435 | |
9dbbc748 GB |
2436 | /* CPACR and the CPTR registers don't exist before v6, so FP is |
2437 | * always accessible | |
2438 | */ | |
2439 | if (!arm_feature(env, ARM_FEATURE_V6)) { | |
2440 | return 0; | |
2441 | } | |
2442 | ||
2443 | /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: | |
2444 | * 0, 2 : trap EL0 and EL1/PL1 accesses | |
2445 | * 1 : trap only EL0 accesses | |
2446 | * 3 : trap no accesses | |
2447 | */ | |
2448 | fpen = extract32(env->cp15.cpacr_el1, 20, 2); | |
2449 | switch (fpen) { | |
2450 | case 0: | |
2451 | case 2: | |
2452 | if (cur_el == 0 || cur_el == 1) { | |
2453 | /* Trap to PL1, which might be EL1 or EL3 */ | |
2454 | if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { | |
2455 | return 3; | |
2456 | } | |
2457 | return 1; | |
2458 | } | |
2459 | if (cur_el == 3 && !is_a64(env)) { | |
2460 | /* Secure PL1 running at EL3 */ | |
2461 | return 3; | |
2462 | } | |
2463 | break; | |
2464 | case 1: | |
2465 | if (cur_el == 0) { | |
2466 | return 1; | |
2467 | } | |
2468 | break; | |
2469 | case 3: | |
2470 | break; | |
2471 | } | |
2472 | ||
2473 | /* For the CPTR registers we don't need to guard with an ARM_FEATURE | |
2474 | * check because zero bits in the registers mean "don't trap". | |
2475 | */ | |
2476 | ||
2477 | /* CPTR_EL2 : present in v7VE or v8 */ | |
2478 | if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1) | |
2479 | && !arm_is_secure_below_el3(env)) { | |
2480 | /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ | |
2481 | return 2; | |
2482 | } | |
2483 | ||
2484 | /* CPTR_EL3 : present in v8 */ | |
2485 | if (extract32(env->cp15.cptr_el[3], 10, 1)) { | |
2486 | /* Trap all FP ops to EL3 */ | |
2487 | return 3; | |
ed1f13d6 | 2488 | } |
8c6afa6a | 2489 | |
9dbbc748 GB |
2490 | return 0; |
2491 | } | |
2492 | ||
c3ae85fc PB |
2493 | #ifdef CONFIG_USER_ONLY |
2494 | static inline bool arm_cpu_bswap_data(CPUARMState *env) | |
2495 | { | |
2496 | return | |
2497 | #ifdef TARGET_WORDS_BIGENDIAN | |
2498 | 1 ^ | |
2499 | #endif | |
2500 | arm_cpu_data_is_big_endian(env); | |
2501 | } | |
2502 | #endif | |
2503 | ||
86fb3fa4 TH |
2504 | #ifndef CONFIG_USER_ONLY |
2505 | /** | |
2506 | * arm_regime_tbi0: | |
2507 | * @env: CPUARMState | |
2508 | * @mmu_idx: MMU index indicating required translation regime | |
2509 | * | |
2510 | * Extracts the TBI0 value from the appropriate TCR for the current EL | |
2511 | * | |
2512 | * Returns: the TBI0 value. | |
2513 | */ | |
2514 | uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx); | |
2515 | ||
2516 | /** | |
2517 | * arm_regime_tbi1: | |
2518 | * @env: CPUARMState | |
2519 | * @mmu_idx: MMU index indicating required translation regime | |
2520 | * | |
2521 | * Extracts the TBI1 value from the appropriate TCR for the current EL | |
2522 | * | |
2523 | * Returns: the TBI1 value. | |
2524 | */ | |
2525 | uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx); | |
2526 | #else | |
2527 | /* We can't handle tagged addresses properly in user-only mode */ | |
2528 | static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) | |
2529 | { | |
2530 | return 0; | |
2531 | } | |
2532 | ||
2533 | static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) | |
2534 | { | |
2535 | return 0; | |
2536 | } | |
2537 | #endif | |
2538 | ||
9dbbc748 | 2539 | static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, |
89fee74a | 2540 | target_ulong *cs_base, uint32_t *flags) |
9dbbc748 | 2541 | { |
8bd5c820 | 2542 | ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); |
3926cc84 AG |
2543 | if (is_a64(env)) { |
2544 | *pc = env->pc; | |
c1e37810 | 2545 | *flags = ARM_TBFLAG_AARCH64_STATE_MASK; |
86fb3fa4 TH |
2546 | /* Get control bits for tagged addresses */ |
2547 | *flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); | |
2548 | *flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); | |
05ed9a99 | 2549 | } else { |
3926cc84 AG |
2550 | *pc = env->regs[15]; |
2551 | *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) | |
2552 | | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) | |
2553 | | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) | |
2554 | | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) | |
f9fd40eb | 2555 | | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); |
3f342b9e SF |
2556 | if (!(access_secure_reg(env))) { |
2557 | *flags |= ARM_TBFLAG_NS_MASK; | |
2558 | } | |
2c7ffc41 PM |
2559 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) |
2560 | || arm_el_is_aa64(env, 1)) { | |
3926cc84 AG |
2561 | *flags |= ARM_TBFLAG_VFPEN_MASK; |
2562 | } | |
c0f4af17 PM |
2563 | *flags |= (extract32(env->cp15.c15_cpar, 0, 2) |
2564 | << ARM_TBFLAG_XSCALE_CPAR_SHIFT); | |
a1705768 | 2565 | } |
3926cc84 | 2566 | |
8bd5c820 | 2567 | *flags |= (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); |
86fb3fa4 | 2568 | |
3cf6a0fc PM |
2569 | /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine |
2570 | * states defined in the ARM ARM for software singlestep: | |
2571 | * SS_ACTIVE PSTATE.SS State | |
2572 | * 0 x Inactive (the TB flag for SS is always 0) | |
2573 | * 1 0 Active-pending | |
2574 | * 1 1 Active-not-pending | |
2575 | */ | |
2576 | if (arm_singlestep_active(env)) { | |
2577 | *flags |= ARM_TBFLAG_SS_ACTIVE_MASK; | |
2578 | if (is_a64(env)) { | |
2579 | if (env->pstate & PSTATE_SS) { | |
2580 | *flags |= ARM_TBFLAG_PSTATE_SS_MASK; | |
2581 | } | |
2582 | } else { | |
2583 | if (env->uncached_cpsr & PSTATE_SS) { | |
2584 | *flags |= ARM_TBFLAG_PSTATE_SS_MASK; | |
2585 | } | |
2586 | } | |
2587 | } | |
91cca2cd PC |
2588 | if (arm_cpu_data_is_big_endian(env)) { |
2589 | *flags |= ARM_TBFLAG_BE_DATA_MASK; | |
2590 | } | |
9dbbc748 | 2591 | *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; |
c1e37810 | 2592 | |
064c379c PM |
2593 | if (env->v7m.exception != 0) { |
2594 | *flags |= ARM_TBFLAG_HANDLER_MASK; | |
2595 | } | |
2596 | ||
3926cc84 | 2597 | *cs_base = 0; |
6b917547 AL |
2598 | } |
2599 | ||
98128601 RH |
2600 | enum { |
2601 | QEMU_PSCI_CONDUIT_DISABLED = 0, | |
2602 | QEMU_PSCI_CONDUIT_SMC = 1, | |
2603 | QEMU_PSCI_CONDUIT_HVC = 2, | |
2604 | }; | |
2605 | ||
017518c1 PM |
2606 | #ifndef CONFIG_USER_ONLY |
2607 | /* Return the address space index to use for a memory access */ | |
2608 | static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) | |
2609 | { | |
2610 | return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; | |
2611 | } | |
5ce4ff65 PM |
2612 | |
2613 | /* Return the AddressSpace to use for a memory access | |
2614 | * (which depends on whether the access is S or NS, and whether | |
2615 | * the board gave us a separate AddressSpace for S accesses). | |
2616 | */ | |
2617 | static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) | |
2618 | { | |
2619 | return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); | |
2620 | } | |
017518c1 PM |
2621 | #endif |
2622 | ||
bd7d00fc PM |
2623 | /** |
2624 | * arm_register_el_change_hook: | |
2625 | * Register a hook function which will be called back whenever this | |
2626 | * CPU changes exception level or mode. The hook function will be | |
2627 | * passed a pointer to the ARMCPU and the opaque data pointer passed | |
2628 | * to this function when the hook was registered. | |
2629 | * | |
2630 | * Note that we currently only support registering a single hook function, | |
2631 | * and will assert if this function is called twice. | |
2632 | * This facility is intended for the use of the GICv3 emulation. | |
2633 | */ | |
2634 | void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook, | |
2635 | void *opaque); | |
2636 | ||
2637 | /** | |
2638 | * arm_get_el_change_hook_opaque: | |
2639 | * Return the opaque data that will be used by the el_change_hook | |
2640 | * for this CPU. | |
2641 | */ | |
2642 | static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu) | |
2643 | { | |
2644 | return cpu->el_change_hook_opaque; | |
2645 | } | |
2646 | ||
2c0262af | 2647 | #endif |