]>
Commit | Line | Data |
---|---|---|
2c0262af FB |
1 | /* |
2 | * ARM virtual CPU header | |
5fafdf24 | 3 | * |
2c0262af FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
50f57e09 | 9 | * version 2.1 of the License, or (at your option) any later version. |
2c0262af FB |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
2c0262af | 18 | */ |
2c0262af | 19 | |
07f5a258 MA |
20 | #ifndef ARM_CPU_H |
21 | #define ARM_CPU_H | |
3cf1e035 | 22 | |
72b0cd35 | 23 | #include "kvm-consts.h" |
2c4da50d | 24 | #include "hw/registerfields.h" |
74433bf0 RH |
25 | #include "cpu-qom.h" |
26 | #include "exec/cpu-defs.h" | |
68970d1e | 27 | #include "qapi/qapi-types-common.h" |
9042c0e2 | 28 | |
ca759f9e AB |
29 | /* ARM processors have a weak memory model */ |
30 | #define TCG_GUEST_DEFAULT_MO (0) | |
31 | ||
e24fd076 DG |
32 | #ifdef TARGET_AARCH64 |
33 | #define KVM_HAVE_MCE_INJECTION 1 | |
34 | #endif | |
35 | ||
b8a9e8f1 FB |
36 | #define EXCP_UDEF 1 /* undefined instruction */ |
37 | #define EXCP_SWI 2 /* software interrupt */ | |
38 | #define EXCP_PREFETCH_ABORT 3 | |
39 | #define EXCP_DATA_ABORT 4 | |
b5ff1b31 FB |
40 | #define EXCP_IRQ 5 |
41 | #define EXCP_FIQ 6 | |
06c949e6 | 42 | #define EXCP_BKPT 7 |
9ee6e8bb | 43 | #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ |
fbb4a2e3 | 44 | #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ |
35979d71 | 45 | #define EXCP_HVC 11 /* HyperVisor Call */ |
607d98b8 | 46 | #define EXCP_HYP_TRAP 12 |
e0d6e6a5 | 47 | #define EXCP_SMC 13 /* Secure Monitor Call */ |
136e67e9 EI |
48 | #define EXCP_VIRQ 14 |
49 | #define EXCP_VFIQ 15 | |
19a6e31c | 50 | #define EXCP_SEMIHOST 16 /* semihosting call */ |
7517748e | 51 | #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ |
e13886e3 | 52 | #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ |
86f026de | 53 | #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ |
e33cf0f8 | 54 | #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ |
019076b0 PM |
55 | #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ |
56 | #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ | |
2c4a7cc5 | 57 | /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ |
9ee6e8bb PB |
58 | |
59 | #define ARMV7M_EXCP_RESET 1 | |
60 | #define ARMV7M_EXCP_NMI 2 | |
61 | #define ARMV7M_EXCP_HARD 3 | |
62 | #define ARMV7M_EXCP_MEM 4 | |
63 | #define ARMV7M_EXCP_BUS 5 | |
64 | #define ARMV7M_EXCP_USAGE 6 | |
1e577cc7 | 65 | #define ARMV7M_EXCP_SECURE 7 |
9ee6e8bb PB |
66 | #define ARMV7M_EXCP_SVC 11 |
67 | #define ARMV7M_EXCP_DEBUG 12 | |
68 | #define ARMV7M_EXCP_PENDSV 14 | |
69 | #define ARMV7M_EXCP_SYSTICK 15 | |
2c0262af | 70 | |
acf94941 PM |
71 | /* For M profile, some registers are banked secure vs non-secure; |
72 | * these are represented as a 2-element array where the first element | |
73 | * is the non-secure copy and the second is the secure copy. | |
74 | * When the CPU does not have implement the security extension then | |
75 | * only the first element is used. | |
76 | * This means that the copy for the current security state can be | |
77 | * accessed via env->registerfield[env->v7m.secure] (whether the security | |
78 | * extension is implemented or not). | |
79 | */ | |
4a16724f PM |
80 | enum { |
81 | M_REG_NS = 0, | |
82 | M_REG_S = 1, | |
83 | M_REG_NUM_BANKS = 2, | |
84 | }; | |
acf94941 | 85 | |
403946c0 RH |
86 | /* ARM-specific interrupt pending bits. */ |
87 | #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 | |
136e67e9 EI |
88 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 |
89 | #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 | |
403946c0 | 90 | |
e4fe830b PM |
91 | /* The usual mapping for an AArch64 system register to its AArch32 |
92 | * counterpart is for the 32 bit world to have access to the lower | |
93 | * half only (with writes leaving the upper half untouched). It's | |
94 | * therefore useful to be able to pass TCG the offset of the least | |
95 | * significant half of a uint64_t struct member. | |
96 | */ | |
97 | #ifdef HOST_WORDS_BIGENDIAN | |
5cd8a118 | 98 | #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t)) |
b0fe2427 | 99 | #define offsetofhigh32(S, M) offsetof(S, M) |
e4fe830b PM |
100 | #else |
101 | #define offsetoflow32(S, M) offsetof(S, M) | |
b0fe2427 | 102 | #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) |
e4fe830b PM |
103 | #endif |
104 | ||
136e67e9 | 105 | /* Meanings of the ARMCPU object's four inbound GPIO lines */ |
7c1840b6 PM |
106 | #define ARM_CPU_IRQ 0 |
107 | #define ARM_CPU_FIQ 1 | |
136e67e9 EI |
108 | #define ARM_CPU_VIRQ 2 |
109 | #define ARM_CPU_VFIQ 3 | |
403946c0 | 110 | |
aaa1f954 EI |
111 | /* ARM-specific extra insn start words: |
112 | * 1: Conditional execution bits | |
113 | * 2: Partial exception syndrome for data aborts | |
114 | */ | |
115 | #define TARGET_INSN_START_EXTRA_WORDS 2 | |
116 | ||
117 | /* The 2nd extra word holding syndrome info for data aborts does not use | |
118 | * the upper 6 bits nor the lower 14 bits. We mask and shift it down to | |
119 | * help the sleb128 encoder do a better job. | |
120 | * When restoring the CPU state, we shift it back up. | |
121 | */ | |
122 | #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) | |
123 | #define ARM_INSN_START_WORD2_SHIFT 14 | |
6ebbf390 | 124 | |
b7bcbe95 FB |
125 | /* We currently assume float and double are IEEE single and double |
126 | precision respectively. | |
127 | Doing runtime conversions is tricky because VFP registers may contain | |
128 | integer values (eg. as the result of a FTOSI instruction). | |
8e96005d FB |
129 | s<2n> maps to the least significant half of d<n> |
130 | s<2n+1> maps to the most significant half of d<n> | |
131 | */ | |
b7bcbe95 | 132 | |
200bf5b7 AB |
133 | /** |
134 | * DynamicGDBXMLInfo: | |
135 | * @desc: Contains the XML descriptions. | |
448d4d14 AB |
136 | * @num: Number of the registers in this XML seen by GDB. |
137 | * @data: A union with data specific to the set of registers | |
138 | * @cpregs_keys: Array that contains the corresponding Key of | |
139 | * a given cpreg with the same order of the cpreg | |
140 | * in the XML description. | |
200bf5b7 AB |
141 | */ |
142 | typedef struct DynamicGDBXMLInfo { | |
143 | char *desc; | |
448d4d14 AB |
144 | int num; |
145 | union { | |
146 | struct { | |
147 | uint32_t *keys; | |
148 | } cpregs; | |
149 | } data; | |
200bf5b7 AB |
150 | } DynamicGDBXMLInfo; |
151 | ||
55d284af PM |
152 | /* CPU state for each instance of a generic timer (in cp15 c14) */ |
153 | typedef struct ARMGenericTimer { | |
154 | uint64_t cval; /* Timer CompareValue register */ | |
a7adc4b7 | 155 | uint64_t ctl; /* Timer Control register */ |
55d284af PM |
156 | } ARMGenericTimer; |
157 | ||
8c94b071 RH |
158 | #define GTIMER_PHYS 0 |
159 | #define GTIMER_VIRT 1 | |
160 | #define GTIMER_HYP 2 | |
161 | #define GTIMER_SEC 3 | |
162 | #define GTIMER_HYPVIRT 4 | |
163 | #define NUM_GTIMERS 5 | |
55d284af | 164 | |
11f136ee FA |
165 | typedef struct { |
166 | uint64_t raw_tcr; | |
167 | uint32_t mask; | |
168 | uint32_t base_mask; | |
169 | } TCR; | |
170 | ||
c39c2b90 RH |
171 | /* Define a maximum sized vector register. |
172 | * For 32-bit, this is a 128-bit NEON/AdvSIMD register. | |
173 | * For 64-bit, this is a 2048-bit SVE register. | |
174 | * | |
175 | * Note that the mapping between S, D, and Q views of the register bank | |
176 | * differs between AArch64 and AArch32. | |
177 | * In AArch32: | |
178 | * Qn = regs[n].d[1]:regs[n].d[0] | |
179 | * Dn = regs[n / 2].d[n & 1] | |
180 | * Sn = regs[n / 4].d[n % 4 / 2], | |
181 | * bits 31..0 for even n, and bits 63..32 for odd n | |
182 | * (and regs[16] to regs[31] are inaccessible) | |
183 | * In AArch64: | |
184 | * Zn = regs[n].d[*] | |
185 | * Qn = regs[n].d[1]:regs[n].d[0] | |
186 | * Dn = regs[n].d[0] | |
187 | * Sn = regs[n].d[0] bits 31..0 | |
d0e69ea8 | 188 | * Hn = regs[n].d[0] bits 15..0 |
c39c2b90 RH |
189 | * |
190 | * This corresponds to the architecturally defined mapping between | |
191 | * the two execution states, and means we do not need to explicitly | |
192 | * map these registers when changing states. | |
193 | * | |
194 | * Align the data for use with TCG host vector operations. | |
195 | */ | |
196 | ||
197 | #ifdef TARGET_AARCH64 | |
198 | # define ARM_MAX_VQ 16 | |
0df9142d | 199 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); |
eb94284d | 200 | void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); |
c39c2b90 RH |
201 | #else |
202 | # define ARM_MAX_VQ 1 | |
0df9142d | 203 | static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } |
eb94284d | 204 | static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } |
c39c2b90 RH |
205 | #endif |
206 | ||
207 | typedef struct ARMVectorReg { | |
208 | uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); | |
209 | } ARMVectorReg; | |
210 | ||
3c7d3086 | 211 | #ifdef TARGET_AARCH64 |
991ad91b | 212 | /* In AArch32 mode, predicate registers do not exist at all. */ |
3c7d3086 | 213 | typedef struct ARMPredicateReg { |
46417784 | 214 | uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); |
3c7d3086 | 215 | } ARMPredicateReg; |
991ad91b RH |
216 | |
217 | /* In AArch32 mode, PAC keys do not exist at all. */ | |
218 | typedef struct ARMPACKey { | |
219 | uint64_t lo, hi; | |
220 | } ARMPACKey; | |
3c7d3086 RH |
221 | #endif |
222 | ||
c39c2b90 | 223 | |
2c0262af | 224 | typedef struct CPUARMState { |
b5ff1b31 | 225 | /* Regs for current mode. */ |
2c0262af | 226 | uint32_t regs[16]; |
3926cc84 AG |
227 | |
228 | /* 32/64 switch only happens when taking and returning from | |
229 | * exceptions so the overlap semantics are taken care of then | |
230 | * instead of having a complicated union. | |
231 | */ | |
232 | /* Regs for A64 mode. */ | |
233 | uint64_t xregs[32]; | |
234 | uint64_t pc; | |
d356312f PM |
235 | /* PSTATE isn't an architectural register for ARMv8. However, it is |
236 | * convenient for us to assemble the underlying state into a 32 bit format | |
237 | * identical to the architectural format used for the SPSR. (This is also | |
238 | * what the Linux kernel's 'pstate' field in signal handlers and KVM's | |
239 | * 'pstate' register are.) Of the PSTATE bits: | |
240 | * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same | |
241 | * semantics as for AArch32, as described in the comments on each field) | |
242 | * nRW (also known as M[4]) is kept, inverted, in env->aarch64 | |
4cc35614 | 243 | * DAIF (exception masks) are kept in env->daif |
f6e52eaa | 244 | * BTYPE is kept in env->btype |
d356312f | 245 | * all other bits are stored in their correct places in env->pstate |
3926cc84 AG |
246 | */ |
247 | uint32_t pstate; | |
248 | uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ | |
249 | ||
fdd1b228 RH |
250 | /* Cached TBFLAGS state. See below for which bits are included. */ |
251 | uint32_t hflags; | |
252 | ||
b90372ad | 253 | /* Frequently accessed CPSR bits are stored separately for efficiency. |
d37aca66 | 254 | This contains all the other bits. Use cpsr_{read,write} to access |
b5ff1b31 FB |
255 | the whole CPSR. */ |
256 | uint32_t uncached_cpsr; | |
257 | uint32_t spsr; | |
258 | ||
259 | /* Banked registers. */ | |
28c9457d | 260 | uint64_t banked_spsr[8]; |
0b7d409d FA |
261 | uint32_t banked_r13[8]; |
262 | uint32_t banked_r14[8]; | |
3b46e624 | 263 | |
b5ff1b31 FB |
264 | /* These hold r8-r12. */ |
265 | uint32_t usr_regs[5]; | |
266 | uint32_t fiq_regs[5]; | |
3b46e624 | 267 | |
2c0262af FB |
268 | /* cpsr flag cache for faster execution */ |
269 | uint32_t CF; /* 0 or 1 */ | |
270 | uint32_t VF; /* V is the bit 31. All other bits are undefined */ | |
6fbe23d5 PB |
271 | uint32_t NF; /* N is bit 31. All other bits are undefined. */ |
272 | uint32_t ZF; /* Z set if zero. */ | |
99c475ab | 273 | uint32_t QF; /* 0 or 1 */ |
9ee6e8bb | 274 | uint32_t GE; /* cpsr[19:16] */ |
b26eefb6 | 275 | uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ |
9ee6e8bb | 276 | uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ |
f6e52eaa | 277 | uint32_t btype; /* BTI branch type. spsr[11:10]. */ |
b6af0975 | 278 | uint64_t daif; /* exception masks, in the bits they are in PSTATE */ |
2c0262af | 279 | |
1b174238 | 280 | uint64_t elr_el[4]; /* AArch64 exception link regs */ |
73fb3b76 | 281 | uint64_t sp_el[4]; /* AArch64 banked stack pointers */ |
a0618a19 | 282 | |
b5ff1b31 FB |
283 | /* System control coprocessor (cp15) */ |
284 | struct { | |
40f137e1 | 285 | uint32_t c0_cpuid; |
b85a1fd6 FA |
286 | union { /* Cache size selection */ |
287 | struct { | |
288 | uint64_t _unused_csselr0; | |
289 | uint64_t csselr_ns; | |
290 | uint64_t _unused_csselr1; | |
291 | uint64_t csselr_s; | |
292 | }; | |
293 | uint64_t csselr_el[4]; | |
294 | }; | |
137feaa9 FA |
295 | union { /* System control register. */ |
296 | struct { | |
297 | uint64_t _unused_sctlr; | |
298 | uint64_t sctlr_ns; | |
299 | uint64_t hsctlr; | |
300 | uint64_t sctlr_s; | |
301 | }; | |
302 | uint64_t sctlr_el[4]; | |
303 | }; | |
7ebd5f2e | 304 | uint64_t cpacr_el1; /* Architectural feature access control register */ |
c6f19164 | 305 | uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ |
610c3c8a | 306 | uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ |
144634ae | 307 | uint64_t sder; /* Secure debug enable register. */ |
77022576 | 308 | uint32_t nsacr; /* Non-secure access control register. */ |
7dd8c9af FA |
309 | union { /* MMU translation table base 0. */ |
310 | struct { | |
311 | uint64_t _unused_ttbr0_0; | |
312 | uint64_t ttbr0_ns; | |
313 | uint64_t _unused_ttbr0_1; | |
314 | uint64_t ttbr0_s; | |
315 | }; | |
316 | uint64_t ttbr0_el[4]; | |
317 | }; | |
318 | union { /* MMU translation table base 1. */ | |
319 | struct { | |
320 | uint64_t _unused_ttbr1_0; | |
321 | uint64_t ttbr1_ns; | |
322 | uint64_t _unused_ttbr1_1; | |
323 | uint64_t ttbr1_s; | |
324 | }; | |
325 | uint64_t ttbr1_el[4]; | |
326 | }; | |
b698e9cf | 327 | uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ |
11f136ee FA |
328 | /* MMU translation table base control. */ |
329 | TCR tcr_el[4]; | |
68e9c2fe | 330 | TCR vtcr_el2; /* Virtualization Translation Control. */ |
67cc32eb VL |
331 | uint32_t c2_data; /* MPU data cacheable bits. */ |
332 | uint32_t c2_insn; /* MPU instruction cacheable bits. */ | |
0c17d68c FA |
333 | union { /* MMU domain access control register |
334 | * MPU write buffer control. | |
335 | */ | |
336 | struct { | |
337 | uint64_t dacr_ns; | |
338 | uint64_t dacr_s; | |
339 | }; | |
340 | struct { | |
341 | uint64_t dacr32_el2; | |
342 | }; | |
343 | }; | |
7e09797c PM |
344 | uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ |
345 | uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ | |
f149e3e8 | 346 | uint64_t hcr_el2; /* Hypervisor configuration register */ |
64e0e2de | 347 | uint64_t scr_el3; /* Secure configuration register. */ |
88ca1c2d FA |
348 | union { /* Fault status registers. */ |
349 | struct { | |
350 | uint64_t ifsr_ns; | |
351 | uint64_t ifsr_s; | |
352 | }; | |
353 | struct { | |
354 | uint64_t ifsr32_el2; | |
355 | }; | |
356 | }; | |
4a7e2d73 FA |
357 | union { |
358 | struct { | |
359 | uint64_t _unused_dfsr; | |
360 | uint64_t dfsr_ns; | |
361 | uint64_t hsr; | |
362 | uint64_t dfsr_s; | |
363 | }; | |
364 | uint64_t esr_el[4]; | |
365 | }; | |
ce819861 | 366 | uint32_t c6_region[8]; /* MPU base/size registers. */ |
b848ce2b FA |
367 | union { /* Fault address registers. */ |
368 | struct { | |
369 | uint64_t _unused_far0; | |
370 | #ifdef HOST_WORDS_BIGENDIAN | |
371 | uint32_t ifar_ns; | |
372 | uint32_t dfar_ns; | |
373 | uint32_t ifar_s; | |
374 | uint32_t dfar_s; | |
375 | #else | |
376 | uint32_t dfar_ns; | |
377 | uint32_t ifar_ns; | |
378 | uint32_t dfar_s; | |
379 | uint32_t ifar_s; | |
380 | #endif | |
381 | uint64_t _unused_far3; | |
382 | }; | |
383 | uint64_t far_el[4]; | |
384 | }; | |
59e05530 | 385 | uint64_t hpfar_el2; |
2a5a9abd | 386 | uint64_t hstr_el2; |
01c097f7 FA |
387 | union { /* Translation result. */ |
388 | struct { | |
389 | uint64_t _unused_par_0; | |
390 | uint64_t par_ns; | |
391 | uint64_t _unused_par_1; | |
392 | uint64_t par_s; | |
393 | }; | |
394 | uint64_t par_el[4]; | |
395 | }; | |
6cb0b013 | 396 | |
b5ff1b31 FB |
397 | uint32_t c9_insn; /* Cache lockdown registers. */ |
398 | uint32_t c9_data; | |
8521466b AF |
399 | uint64_t c9_pmcr; /* performance monitor control register */ |
400 | uint64_t c9_pmcnten; /* perf monitor counter enables */ | |
e4e91a21 AL |
401 | uint64_t c9_pmovsr; /* perf monitor overflow status */ |
402 | uint64_t c9_pmuserenr; /* perf monitor user enable */ | |
6b040780 | 403 | uint64_t c9_pmselr; /* perf monitor counter selection register */ |
e6ec5457 | 404 | uint64_t c9_pminten; /* perf monitor interrupt enables */ |
be693c87 GB |
405 | union { /* Memory attribute redirection */ |
406 | struct { | |
407 | #ifdef HOST_WORDS_BIGENDIAN | |
408 | uint64_t _unused_mair_0; | |
409 | uint32_t mair1_ns; | |
410 | uint32_t mair0_ns; | |
411 | uint64_t _unused_mair_1; | |
412 | uint32_t mair1_s; | |
413 | uint32_t mair0_s; | |
414 | #else | |
415 | uint64_t _unused_mair_0; | |
416 | uint32_t mair0_ns; | |
417 | uint32_t mair1_ns; | |
418 | uint64_t _unused_mair_1; | |
419 | uint32_t mair0_s; | |
420 | uint32_t mair1_s; | |
421 | #endif | |
422 | }; | |
423 | uint64_t mair_el[4]; | |
424 | }; | |
fb6c91ba GB |
425 | union { /* vector base address register */ |
426 | struct { | |
427 | uint64_t _unused_vbar; | |
428 | uint64_t vbar_ns; | |
429 | uint64_t hvbar; | |
430 | uint64_t vbar_s; | |
431 | }; | |
432 | uint64_t vbar_el[4]; | |
433 | }; | |
e89e51a1 | 434 | uint32_t mvbar; /* (monitor) vector base address register */ |
54bf36ed FA |
435 | struct { /* FCSE PID. */ |
436 | uint32_t fcseidr_ns; | |
437 | uint32_t fcseidr_s; | |
438 | }; | |
439 | union { /* Context ID. */ | |
440 | struct { | |
441 | uint64_t _unused_contextidr_0; | |
442 | uint64_t contextidr_ns; | |
443 | uint64_t _unused_contextidr_1; | |
444 | uint64_t contextidr_s; | |
445 | }; | |
446 | uint64_t contextidr_el[4]; | |
447 | }; | |
448 | union { /* User RW Thread register. */ | |
449 | struct { | |
450 | uint64_t tpidrurw_ns; | |
451 | uint64_t tpidrprw_ns; | |
452 | uint64_t htpidr; | |
453 | uint64_t _tpidr_el3; | |
454 | }; | |
455 | uint64_t tpidr_el[4]; | |
456 | }; | |
457 | /* The secure banks of these registers don't map anywhere */ | |
458 | uint64_t tpidrurw_s; | |
459 | uint64_t tpidrprw_s; | |
460 | uint64_t tpidruro_s; | |
461 | ||
462 | union { /* User RO Thread register. */ | |
463 | uint64_t tpidruro_ns; | |
464 | uint64_t tpidrro_el[1]; | |
465 | }; | |
a7adc4b7 PM |
466 | uint64_t c14_cntfrq; /* Counter Frequency register */ |
467 | uint64_t c14_cntkctl; /* Timer Control register */ | |
0b6440af | 468 | uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ |
edac4d8a | 469 | uint64_t cntvoff_el2; /* Counter Virtual Offset register */ |
55d284af | 470 | ARMGenericTimer c14_timer[NUM_GTIMERS]; |
c1713132 | 471 | uint32_t c15_cpar; /* XScale Coprocessor Access Register */ |
c3d2689d AZ |
472 | uint32_t c15_ticonfig; /* TI925T configuration byte. */ |
473 | uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ | |
474 | uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ | |
475 | uint32_t c15_threadid; /* TI debugger thread-ID. */ | |
7da362d0 ML |
476 | uint32_t c15_config_base_address; /* SCU base address. */ |
477 | uint32_t c15_diagnostic; /* diagnostic register */ | |
478 | uint32_t c15_power_diagnostic; | |
479 | uint32_t c15_power_control; /* power control */ | |
0b45451e PM |
480 | uint64_t dbgbvr[16]; /* breakpoint value registers */ |
481 | uint64_t dbgbcr[16]; /* breakpoint control registers */ | |
482 | uint64_t dbgwvr[16]; /* watchpoint value registers */ | |
483 | uint64_t dbgwcr[16]; /* watchpoint control registers */ | |
3a298203 | 484 | uint64_t mdscr_el1; |
1424ca8d | 485 | uint64_t oslsr_el1; /* OS Lock Status */ |
14cc7b54 | 486 | uint64_t mdcr_el2; |
5513c3ab | 487 | uint64_t mdcr_el3; |
5d05b9d4 AL |
488 | /* Stores the architectural value of the counter *the last time it was |
489 | * updated* by pmccntr_op_start. Accesses should always be surrounded | |
490 | * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest | |
491 | * architecturally-correct value is being read/set. | |
7c2cb42b | 492 | */ |
c92c0687 | 493 | uint64_t c15_ccnt; |
5d05b9d4 AL |
494 | /* Stores the delta between the architectural value and the underlying |
495 | * cycle count during normal operation. It is used to update c15_ccnt | |
496 | * to be the correct architectural value before accesses. During | |
497 | * accesses, c15_ccnt_delta contains the underlying count being used | |
498 | * for the access, after which it reverts to the delta value in | |
499 | * pmccntr_op_finish. | |
500 | */ | |
501 | uint64_t c15_ccnt_delta; | |
5ecdd3e4 AL |
502 | uint64_t c14_pmevcntr[31]; |
503 | uint64_t c14_pmevcntr_delta[31]; | |
504 | uint64_t c14_pmevtyper[31]; | |
8521466b | 505 | uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ |
731de9e6 | 506 | uint64_t vpidr_el2; /* Virtualization Processor ID Register */ |
f0d574d6 | 507 | uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ |
4b779ceb RH |
508 | uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ |
509 | uint64_t gcr_el1; | |
510 | uint64_t rgsr_el1; | |
b5ff1b31 | 511 | } cp15; |
40f137e1 | 512 | |
9ee6e8bb | 513 | struct { |
fb602cb7 PM |
514 | /* M profile has up to 4 stack pointers: |
515 | * a Main Stack Pointer and a Process Stack Pointer for each | |
516 | * of the Secure and Non-Secure states. (If the CPU doesn't support | |
517 | * the security extension then it has only two SPs.) | |
518 | * In QEMU we always store the currently active SP in regs[13], | |
519 | * and the non-active SP for the current security state in | |
520 | * v7m.other_sp. The stack pointers for the inactive security state | |
521 | * are stored in other_ss_msp and other_ss_psp. | |
522 | * switch_v7m_security_state() is responsible for rearranging them | |
523 | * when we change security state. | |
524 | */ | |
9ee6e8bb | 525 | uint32_t other_sp; |
fb602cb7 PM |
526 | uint32_t other_ss_msp; |
527 | uint32_t other_ss_psp; | |
4a16724f PM |
528 | uint32_t vecbase[M_REG_NUM_BANKS]; |
529 | uint32_t basepri[M_REG_NUM_BANKS]; | |
530 | uint32_t control[M_REG_NUM_BANKS]; | |
531 | uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ | |
532 | uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ | |
2c4da50d PM |
533 | uint32_t hfsr; /* HardFault Status */ |
534 | uint32_t dfsr; /* Debug Fault Status Register */ | |
bed079da | 535 | uint32_t sfsr; /* Secure Fault Status Register */ |
4a16724f | 536 | uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ |
2c4da50d | 537 | uint32_t bfar; /* BusFault Address */ |
bed079da | 538 | uint32_t sfar; /* Secure Fault Address Register */ |
4a16724f | 539 | unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ |
9ee6e8bb | 540 | int exception; |
4a16724f PM |
541 | uint32_t primask[M_REG_NUM_BANKS]; |
542 | uint32_t faultmask[M_REG_NUM_BANKS]; | |
3b2e9344 | 543 | uint32_t aircr; /* only holds r/w state if security extn implemented */ |
1e577cc7 | 544 | uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ |
43bbce7f | 545 | uint32_t csselr[M_REG_NUM_BANKS]; |
24ac0fb1 | 546 | uint32_t scr[M_REG_NUM_BANKS]; |
57bb3156 PM |
547 | uint32_t msplim[M_REG_NUM_BANKS]; |
548 | uint32_t psplim[M_REG_NUM_BANKS]; | |
d33abe82 PM |
549 | uint32_t fpcar[M_REG_NUM_BANKS]; |
550 | uint32_t fpccr[M_REG_NUM_BANKS]; | |
551 | uint32_t fpdscr[M_REG_NUM_BANKS]; | |
552 | uint32_t cpacr[M_REG_NUM_BANKS]; | |
553 | uint32_t nsacr; | |
8128c8e8 | 554 | int ltpsize; |
9ee6e8bb PB |
555 | } v7m; |
556 | ||
abf1172f PM |
557 | /* Information associated with an exception about to be taken: |
558 | * code which raises an exception must set cs->exception_index and | |
559 | * the relevant parts of this structure; the cpu_do_interrupt function | |
560 | * will then set the guest-visible registers as part of the exception | |
561 | * entry process. | |
562 | */ | |
563 | struct { | |
564 | uint32_t syndrome; /* AArch64 format syndrome register */ | |
565 | uint32_t fsr; /* AArch32 format fault status register info */ | |
566 | uint64_t vaddress; /* virtual addr associated with exception, if any */ | |
73710361 | 567 | uint32_t target_el; /* EL the exception should be targeted for */ |
abf1172f PM |
568 | /* If we implement EL2 we will also need to store information |
569 | * about the intermediate physical address for stage 2 faults. | |
570 | */ | |
571 | } exception; | |
572 | ||
202ccb6b DG |
573 | /* Information associated with an SError */ |
574 | struct { | |
575 | uint8_t pending; | |
576 | uint8_t has_esr; | |
577 | uint64_t esr; | |
578 | } serror; | |
579 | ||
1711bfa5 BM |
580 | uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ |
581 | ||
ed89f078 PM |
582 | /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ |
583 | uint32_t irq_line_state; | |
584 | ||
fe1479c3 PB |
585 | /* Thumb-2 EE state. */ |
586 | uint32_t teecr; | |
587 | uint32_t teehbr; | |
588 | ||
b7bcbe95 FB |
589 | /* VFP coprocessor state. */ |
590 | struct { | |
c39c2b90 | 591 | ARMVectorReg zregs[32]; |
b7bcbe95 | 592 | |
3c7d3086 RH |
593 | #ifdef TARGET_AARCH64 |
594 | /* Store FFR as pregs[16] to make it easier to treat as any other. */ | |
028e2a7b | 595 | #define FFR_PRED_NUM 16 |
3c7d3086 | 596 | ARMPredicateReg pregs[17]; |
516e246a RH |
597 | /* Scratch space for aa64 sve predicate temporary. */ |
598 | ARMPredicateReg preg_tmp; | |
3c7d3086 RH |
599 | #endif |
600 | ||
b7bcbe95 | 601 | /* We store these fpcsr fields separately for convenience. */ |
a4d58462 | 602 | uint32_t qc[4] QEMU_ALIGNED(16); |
b7bcbe95 FB |
603 | int vec_len; |
604 | int vec_stride; | |
605 | ||
a4d58462 RH |
606 | uint32_t xregs[16]; |
607 | ||
516e246a | 608 | /* Scratch space for aa32 neon expansion. */ |
9ee6e8bb | 609 | uint32_t scratch[8]; |
3b46e624 | 610 | |
d81ce0ef AB |
611 | /* There are a number of distinct float control structures: |
612 | * | |
613 | * fp_status: is the "normal" fp status. | |
614 | * fp_status_fp16: used for half-precision calculations | |
615 | * standard_fp_status : the ARM "Standard FPSCR Value" | |
aaae563b PM |
616 | * standard_fp_status_fp16 : used for half-precision |
617 | * calculations with the ARM "Standard FPSCR Value" | |
d81ce0ef AB |
618 | * |
619 | * Half-precision operations are governed by a separate | |
620 | * flush-to-zero control bit in FPSCR:FZ16. We pass a separate | |
621 | * status structure to control this. | |
622 | * | |
623 | * The "Standard FPSCR", ie default-NaN, flush-to-zero, | |
624 | * round-to-nearest and is used by any operations (generally | |
625 | * Neon) which the architecture defines as controlled by the | |
626 | * standard FPSCR value rather than the FPSCR. | |
3a492f3a | 627 | * |
aaae563b PM |
628 | * The "standard FPSCR but for fp16 ops" is needed because |
629 | * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than | |
630 | * using a fixed value for it. | |
631 | * | |
3a492f3a PM |
632 | * To avoid having to transfer exception bits around, we simply |
633 | * say that the FPSCR cumulative exception flags are the logical | |
aaae563b | 634 | * OR of the flags in the four fp statuses. This relies on the |
3a492f3a PM |
635 | * only thing which needs to read the exception flags being |
636 | * an explicit FPSCR read. | |
637 | */ | |
53cd6637 | 638 | float_status fp_status; |
d81ce0ef | 639 | float_status fp_status_f16; |
3a492f3a | 640 | float_status standard_fp_status; |
aaae563b | 641 | float_status standard_fp_status_f16; |
5be5e8ed RH |
642 | |
643 | /* ZCR_EL[1-3] */ | |
644 | uint64_t zcr_el[4]; | |
b7bcbe95 | 645 | } vfp; |
03d05e2d PM |
646 | uint64_t exclusive_addr; |
647 | uint64_t exclusive_val; | |
648 | uint64_t exclusive_high; | |
b7bcbe95 | 649 | |
18c9b560 AZ |
650 | /* iwMMXt coprocessor state. */ |
651 | struct { | |
652 | uint64_t regs[16]; | |
653 | uint64_t val; | |
654 | ||
655 | uint32_t cregs[16]; | |
656 | } iwmmxt; | |
657 | ||
991ad91b | 658 | #ifdef TARGET_AARCH64 |
108b3ba8 RH |
659 | struct { |
660 | ARMPACKey apia; | |
661 | ARMPACKey apib; | |
662 | ARMPACKey apda; | |
663 | ARMPACKey apdb; | |
664 | ARMPACKey apga; | |
665 | } keys; | |
991ad91b RH |
666 | #endif |
667 | ||
ce4defa0 PB |
668 | #if defined(CONFIG_USER_ONLY) |
669 | /* For usermode syscall translation. */ | |
670 | int eabi; | |
671 | #endif | |
672 | ||
46747d15 | 673 | struct CPUBreakpoint *cpu_breakpoint[16]; |
9ee98ce8 PM |
674 | struct CPUWatchpoint *cpu_watchpoint[16]; |
675 | ||
1f5c00cf AB |
676 | /* Fields up to this point are cleared by a CPU reset */ |
677 | struct {} end_reset_fields; | |
678 | ||
e8b5fae5 | 679 | /* Fields after this point are preserved across CPU reset. */ |
9ba8c3f4 | 680 | |
581be094 | 681 | /* Internal CPU feature flags. */ |
918f5dca | 682 | uint64_t features; |
581be094 | 683 | |
6cb0b013 PC |
684 | /* PMSAv7 MPU */ |
685 | struct { | |
686 | uint32_t *drbar; | |
687 | uint32_t *drsr; | |
688 | uint32_t *dracr; | |
4a16724f | 689 | uint32_t rnr[M_REG_NUM_BANKS]; |
6cb0b013 PC |
690 | } pmsav7; |
691 | ||
0e1a46bb PM |
692 | /* PMSAv8 MPU */ |
693 | struct { | |
694 | /* The PMSAv8 implementation also shares some PMSAv7 config | |
695 | * and state: | |
696 | * pmsav7.rnr (region number register) | |
697 | * pmsav7_dregion (number of configured regions) | |
698 | */ | |
4a16724f PM |
699 | uint32_t *rbar[M_REG_NUM_BANKS]; |
700 | uint32_t *rlar[M_REG_NUM_BANKS]; | |
701 | uint32_t mair0[M_REG_NUM_BANKS]; | |
702 | uint32_t mair1[M_REG_NUM_BANKS]; | |
0e1a46bb PM |
703 | } pmsav8; |
704 | ||
9901c576 PM |
705 | /* v8M SAU */ |
706 | struct { | |
707 | uint32_t *rbar; | |
708 | uint32_t *rlar; | |
709 | uint32_t rnr; | |
710 | uint32_t ctrl; | |
711 | } sau; | |
712 | ||
983fe826 | 713 | void *nvic; |
462a8bc6 | 714 | const struct arm_boot_info *boot_info; |
d3a3e529 VK |
715 | /* Store GICv3CPUState to access from this struct */ |
716 | void *gicv3state; | |
2c0262af FB |
717 | } CPUARMState; |
718 | ||
5fda9504 TH |
719 | static inline void set_feature(CPUARMState *env, int feature) |
720 | { | |
721 | env->features |= 1ULL << feature; | |
722 | } | |
723 | ||
724 | static inline void unset_feature(CPUARMState *env, int feature) | |
725 | { | |
726 | env->features &= ~(1ULL << feature); | |
727 | } | |
728 | ||
bd7d00fc | 729 | /** |
08267487 | 730 | * ARMELChangeHookFn: |
bd7d00fc PM |
731 | * type of a function which can be registered via arm_register_el_change_hook() |
732 | * to get callbacks when the CPU changes its exception level or mode. | |
733 | */ | |
08267487 AL |
734 | typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque); |
735 | typedef struct ARMELChangeHook ARMELChangeHook; | |
736 | struct ARMELChangeHook { | |
737 | ARMELChangeHookFn *hook; | |
738 | void *opaque; | |
739 | QLIST_ENTRY(ARMELChangeHook) node; | |
740 | }; | |
062ba099 AB |
741 | |
742 | /* These values map onto the return values for | |
743 | * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ | |
744 | typedef enum ARMPSCIState { | |
d5affb0d AJ |
745 | PSCI_ON = 0, |
746 | PSCI_OFF = 1, | |
062ba099 AB |
747 | PSCI_ON_PENDING = 2 |
748 | } ARMPSCIState; | |
749 | ||
962fcbf2 RH |
750 | typedef struct ARMISARegisters ARMISARegisters; |
751 | ||
74e75564 PB |
752 | /** |
753 | * ARMCPU: | |
754 | * @env: #CPUARMState | |
755 | * | |
756 | * An ARM CPU core. | |
757 | */ | |
758 | struct ARMCPU { | |
759 | /*< private >*/ | |
760 | CPUState parent_obj; | |
761 | /*< public >*/ | |
762 | ||
5b146dc7 | 763 | CPUNegativeOffsetState neg; |
74e75564 PB |
764 | CPUARMState env; |
765 | ||
766 | /* Coprocessor information */ | |
767 | GHashTable *cp_regs; | |
768 | /* For marshalling (mostly coprocessor) register state between the | |
769 | * kernel and QEMU (for KVM) and between two QEMUs (for migration), | |
770 | * we use these arrays. | |
771 | */ | |
772 | /* List of register indexes managed via these arrays; (full KVM style | |
773 | * 64 bit indexes, not CPRegInfo 32 bit indexes) | |
774 | */ | |
775 | uint64_t *cpreg_indexes; | |
776 | /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */ | |
777 | uint64_t *cpreg_values; | |
778 | /* Length of the indexes, values, reset_values arrays */ | |
779 | int32_t cpreg_array_len; | |
780 | /* These are used only for migration: incoming data arrives in | |
781 | * these fields and is sanity checked in post_load before copying | |
782 | * to the working data structures above. | |
783 | */ | |
784 | uint64_t *cpreg_vmstate_indexes; | |
785 | uint64_t *cpreg_vmstate_values; | |
786 | int32_t cpreg_vmstate_array_len; | |
787 | ||
448d4d14 | 788 | DynamicGDBXMLInfo dyn_sysreg_xml; |
d12379c5 | 789 | DynamicGDBXMLInfo dyn_svereg_xml; |
200bf5b7 | 790 | |
74e75564 PB |
791 | /* Timers used by the generic (architected) timer */ |
792 | QEMUTimer *gt_timer[NUM_GTIMERS]; | |
4e7beb0c AL |
793 | /* |
794 | * Timer used by the PMU. Its state is restored after migration by | |
795 | * pmu_op_finish() - it does not need other handling during migration | |
796 | */ | |
797 | QEMUTimer *pmu_timer; | |
74e75564 PB |
798 | /* GPIO outputs for generic timer */ |
799 | qemu_irq gt_timer_outputs[NUM_GTIMERS]; | |
aa1b3111 PM |
800 | /* GPIO output for GICv3 maintenance interrupt signal */ |
801 | qemu_irq gicv3_maintenance_interrupt; | |
07f48730 AJ |
802 | /* GPIO output for the PMU interrupt */ |
803 | qemu_irq pmu_interrupt; | |
74e75564 PB |
804 | |
805 | /* MemoryRegion to use for secure physical accesses */ | |
806 | MemoryRegion *secure_memory; | |
807 | ||
8bce44a2 RH |
808 | /* MemoryRegion to use for allocation tag accesses */ |
809 | MemoryRegion *tag_memory; | |
810 | MemoryRegion *secure_tag_memory; | |
811 | ||
181962fd PM |
812 | /* For v8M, pointer to the IDAU interface provided by board/SoC */ |
813 | Object *idau; | |
814 | ||
74e75564 PB |
815 | /* 'compatible' string for this CPU for Linux device trees */ |
816 | const char *dtb_compatible; | |
817 | ||
818 | /* PSCI version for this CPU | |
819 | * Bits[31:16] = Major Version | |
820 | * Bits[15:0] = Minor Version | |
821 | */ | |
822 | uint32_t psci_version; | |
823 | ||
062ba099 AB |
824 | /* Current power state, access guarded by BQL */ |
825 | ARMPSCIState power_state; | |
826 | ||
c25bd18a PM |
827 | /* CPU has virtualization extension */ |
828 | bool has_el2; | |
74e75564 PB |
829 | /* CPU has security extension */ |
830 | bool has_el3; | |
5c0a3819 SZ |
831 | /* CPU has PMU (Performance Monitor Unit) */ |
832 | bool has_pmu; | |
97a28b0e PM |
833 | /* CPU has VFP */ |
834 | bool has_vfp; | |
835 | /* CPU has Neon */ | |
836 | bool has_neon; | |
ea90db0a PM |
837 | /* CPU has M-profile DSP extension */ |
838 | bool has_dsp; | |
74e75564 PB |
839 | |
840 | /* CPU has memory protection unit */ | |
841 | bool has_mpu; | |
842 | /* PMSAv7 MPU number of supported regions */ | |
843 | uint32_t pmsav7_dregion; | |
9901c576 PM |
844 | /* v8M SAU number of supported regions */ |
845 | uint32_t sau_sregion; | |
74e75564 PB |
846 | |
847 | /* PSCI conduit used to invoke PSCI methods | |
848 | * 0 - disabled, 1 - smc, 2 - hvc | |
849 | */ | |
850 | uint32_t psci_conduit; | |
851 | ||
38e2a77c PM |
852 | /* For v8M, initial value of the Secure VTOR */ |
853 | uint32_t init_svtor; | |
854 | ||
74e75564 PB |
855 | /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or |
856 | * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. | |
857 | */ | |
858 | uint32_t kvm_target; | |
859 | ||
860 | /* KVM init features for this CPU */ | |
861 | uint32_t kvm_init_features[7]; | |
862 | ||
e5ac4200 AJ |
863 | /* KVM CPU state */ |
864 | ||
865 | /* KVM virtual time adjustment */ | |
866 | bool kvm_adjvtime; | |
867 | bool kvm_vtime_dirty; | |
868 | uint64_t kvm_vtime; | |
869 | ||
68970d1e AJ |
870 | /* KVM steal time */ |
871 | OnOffAuto kvm_steal_time; | |
872 | ||
74e75564 PB |
873 | /* Uniprocessor system with MP extensions */ |
874 | bool mp_is_up; | |
875 | ||
c4487d76 PM |
876 | /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init |
877 | * and the probe failed (so we need to report the error in realize) | |
878 | */ | |
879 | bool host_cpu_probe_failed; | |
880 | ||
f9a69711 AF |
881 | /* Specify the number of cores in this CPU cluster. Used for the L2CTLR |
882 | * register. | |
883 | */ | |
884 | int32_t core_count; | |
885 | ||
74e75564 PB |
886 | /* The instance init functions for implementation-specific subclasses |
887 | * set these fields to specify the implementation-dependent values of | |
888 | * various constant registers and reset values of non-constant | |
889 | * registers. | |
890 | * Some of these might become QOM properties eventually. | |
891 | * Field names match the official register names as defined in the | |
892 | * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix | |
893 | * is used for reset values of non-constant registers; no reset_ | |
894 | * prefix means a constant register. | |
47576b94 RH |
895 | * Some of these registers are split out into a substructure that |
896 | * is shared with the translators to control the ISA. | |
1548a7b2 PM |
897 | * |
898 | * Note that if you add an ID register to the ARMISARegisters struct | |
899 | * you need to also update the 32-bit and 64-bit versions of the | |
900 | * kvm_arm_get_host_cpu_features() function to correctly populate the | |
901 | * field by reading the value from the KVM vCPU. | |
74e75564 | 902 | */ |
47576b94 RH |
903 | struct ARMISARegisters { |
904 | uint32_t id_isar0; | |
905 | uint32_t id_isar1; | |
906 | uint32_t id_isar2; | |
907 | uint32_t id_isar3; | |
908 | uint32_t id_isar4; | |
909 | uint32_t id_isar5; | |
910 | uint32_t id_isar6; | |
10054016 PM |
911 | uint32_t id_mmfr0; |
912 | uint32_t id_mmfr1; | |
913 | uint32_t id_mmfr2; | |
914 | uint32_t id_mmfr3; | |
915 | uint32_t id_mmfr4; | |
8a130a7b PM |
916 | uint32_t id_pfr0; |
917 | uint32_t id_pfr1; | |
47576b94 RH |
918 | uint32_t mvfr0; |
919 | uint32_t mvfr1; | |
920 | uint32_t mvfr2; | |
a6179538 | 921 | uint32_t id_dfr0; |
4426d361 | 922 | uint32_t dbgdidr; |
47576b94 RH |
923 | uint64_t id_aa64isar0; |
924 | uint64_t id_aa64isar1; | |
925 | uint64_t id_aa64pfr0; | |
926 | uint64_t id_aa64pfr1; | |
3dc91ddb PM |
927 | uint64_t id_aa64mmfr0; |
928 | uint64_t id_aa64mmfr1; | |
64761e10 | 929 | uint64_t id_aa64mmfr2; |
2a609df8 PM |
930 | uint64_t id_aa64dfr0; |
931 | uint64_t id_aa64dfr1; | |
47576b94 | 932 | } isar; |
e544f800 | 933 | uint64_t midr; |
74e75564 PB |
934 | uint32_t revidr; |
935 | uint32_t reset_fpsid; | |
a5fd319a | 936 | uint64_t ctr; |
74e75564 | 937 | uint32_t reset_sctlr; |
cad86737 AL |
938 | uint64_t pmceid0; |
939 | uint64_t pmceid1; | |
74e75564 | 940 | uint32_t id_afr0; |
74e75564 PB |
941 | uint64_t id_aa64afr0; |
942 | uint64_t id_aa64afr1; | |
f6450bcb | 943 | uint64_t clidr; |
74e75564 PB |
944 | uint64_t mp_affinity; /* MP ID without feature bits */ |
945 | /* The elements of this array are the CCSIDR values for each cache, | |
946 | * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. | |
947 | */ | |
957e6155 | 948 | uint64_t ccsidr[16]; |
74e75564 PB |
949 | uint64_t reset_cbar; |
950 | uint32_t reset_auxcr; | |
951 | bool reset_hivecs; | |
eb94284d RH |
952 | |
953 | /* | |
954 | * Intermediate values used during property parsing. | |
955 | * Once finalized, the values should be read from ID_AA64ISAR1. | |
956 | */ | |
957 | bool prop_pauth; | |
958 | bool prop_pauth_impdef; | |
959 | ||
74e75564 PB |
960 | /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ |
961 | uint32_t dcz_blocksize; | |
962 | uint64_t rvbar; | |
bd7d00fc | 963 | |
e45868a3 PM |
964 | /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ |
965 | int gic_num_lrs; /* number of list registers */ | |
966 | int gic_vpribits; /* number of virtual priority bits */ | |
967 | int gic_vprebits; /* number of virtual preemption bits */ | |
968 | ||
3a062d57 JB |
969 | /* Whether the cfgend input is high (i.e. this CPU should reset into |
970 | * big-endian mode). This setting isn't used directly: instead it modifies | |
971 | * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the | |
972 | * architecture version. | |
973 | */ | |
974 | bool cfgend; | |
975 | ||
b5c53d1b | 976 | QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; |
08267487 | 977 | QLIST_HEAD(, ARMELChangeHook) el_change_hooks; |
15f8b142 IM |
978 | |
979 | int32_t node_id; /* NUMA node this CPU belongs to */ | |
5d721b78 AG |
980 | |
981 | /* Used to synchronize KVM and QEMU in-kernel device levels */ | |
982 | uint8_t device_irq_level; | |
adf92eab RH |
983 | |
984 | /* Used to set the maximum vector length the cpu will support. */ | |
985 | uint32_t sve_max_vq; | |
0df9142d AJ |
986 | |
987 | /* | |
988 | * In sve_vq_map each set bit is a supported vector length of | |
989 | * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector | |
990 | * length in quadwords. | |
991 | * | |
992 | * While processing properties during initialization, corresponding | |
993 | * sve_vq_init bits are set for bits in sve_vq_map that have been | |
994 | * set by properties. | |
995 | */ | |
996 | DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); | |
997 | DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); | |
7def8754 AJ |
998 | |
999 | /* Generic timer counter frequency, in Hz */ | |
1000 | uint64_t gt_cntfrq_hz; | |
74e75564 PB |
1001 | }; |
1002 | ||
7def8754 AJ |
1003 | unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); |
1004 | ||
51e5ef45 MAL |
1005 | void arm_cpu_post_init(Object *obj); |
1006 | ||
46de5913 IM |
1007 | uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); |
1008 | ||
74e75564 | 1009 | #ifndef CONFIG_USER_ONLY |
8a9358cc | 1010 | extern const VMStateDescription vmstate_arm_cpu; |
74e75564 PB |
1011 | #endif |
1012 | ||
1013 | void arm_cpu_do_interrupt(CPUState *cpu); | |
1014 | void arm_v7m_cpu_do_interrupt(CPUState *cpu); | |
1015 | bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); | |
1016 | ||
74e75564 PB |
1017 | hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, |
1018 | MemTxAttrs *attrs); | |
1019 | ||
a010bdbe | 1020 | int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
74e75564 PB |
1021 | int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
1022 | ||
d12379c5 AB |
1023 | /* |
1024 | * Helpers to dynamically generates XML descriptions of the sysregs | |
1025 | * and SVE registers. Returns the number of registers in each set. | |
200bf5b7 | 1026 | */ |
32d6e32a | 1027 | int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); |
d12379c5 | 1028 | int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); |
200bf5b7 AB |
1029 | |
1030 | /* Returns the dynamically generated XML for the gdb stub. | |
1031 | * Returns a pointer to the XML contents for the specified XML file or NULL | |
1032 | * if the XML name doesn't match the predefined one. | |
1033 | */ | |
1034 | const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); | |
1035 | ||
74e75564 PB |
1036 | int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, |
1037 | int cpuid, void *opaque); | |
1038 | int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, | |
1039 | int cpuid, void *opaque); | |
1040 | ||
1041 | #ifdef TARGET_AARCH64 | |
a010bdbe | 1042 | int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
74e75564 | 1043 | int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
85fc7167 | 1044 | void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); |
9a05f7b6 RH |
1045 | void aarch64_sve_change_el(CPUARMState *env, int old_el, |
1046 | int new_el, bool el0_a64); | |
87014c6b | 1047 | void aarch64_add_sve_properties(Object *obj); |
538baab2 AJ |
1048 | |
1049 | /* | |
1050 | * SVE registers are encoded in KVM's memory in an endianness-invariant format. | |
1051 | * The byte at offset i from the start of the in-memory representation contains | |
1052 | * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the | |
1053 | * lowest offsets are stored in the lowest memory addresses, then that nearly | |
1054 | * matches QEMU's representation, which is to use an array of host-endian | |
1055 | * uint64_t's, where the lower offsets are at the lower indices. To complete | |
1056 | * the translation we just need to byte swap the uint64_t's on big-endian hosts. | |
1057 | */ | |
1058 | static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) | |
1059 | { | |
1060 | #ifdef HOST_WORDS_BIGENDIAN | |
1061 | int i; | |
1062 | ||
1063 | for (i = 0; i < nr; ++i) { | |
1064 | dst[i] = bswap64(src[i]); | |
1065 | } | |
1066 | ||
1067 | return dst; | |
1068 | #else | |
1069 | return src; | |
1070 | #endif | |
1071 | } | |
1072 | ||
0ab5953b RH |
1073 | #else |
1074 | static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } | |
9a05f7b6 RH |
1075 | static inline void aarch64_sve_change_el(CPUARMState *env, int o, |
1076 | int n, bool a) | |
1077 | { } | |
87014c6b | 1078 | static inline void aarch64_add_sve_properties(Object *obj) { } |
74e75564 | 1079 | #endif |
778c3a06 | 1080 | |
ce02049d GB |
1081 | void aarch64_sync_32_to_64(CPUARMState *env); |
1082 | void aarch64_sync_64_to_32(CPUARMState *env); | |
b5ff1b31 | 1083 | |
ced31551 RH |
1084 | int fp_exception_el(CPUARMState *env, int cur_el); |
1085 | int sve_exception_el(CPUARMState *env, int cur_el); | |
1086 | uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); | |
1087 | ||
3926cc84 AG |
1088 | static inline bool is_a64(CPUARMState *env) |
1089 | { | |
1090 | return env->aarch64; | |
1091 | } | |
1092 | ||
2c0262af FB |
1093 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
1094 | signal handlers to inform the virtual CPU of exceptions. non zero | |
1095 | is returned if the signal was handled by the virtual CPU. */ | |
5fafdf24 | 1096 | int cpu_arm_signal_handler(int host_signum, void *pinfo, |
2c0262af FB |
1097 | void *puc); |
1098 | ||
5d05b9d4 AL |
1099 | /** |
1100 | * pmu_op_start/finish | |
ec7b4ce4 AF |
1101 | * @env: CPUARMState |
1102 | * | |
5d05b9d4 AL |
1103 | * Convert all PMU counters between their delta form (the typical mode when |
1104 | * they are enabled) and the guest-visible values. These two calls must | |
1105 | * surround any action which might affect the counters. | |
ec7b4ce4 | 1106 | */ |
5d05b9d4 AL |
1107 | void pmu_op_start(CPUARMState *env); |
1108 | void pmu_op_finish(CPUARMState *env); | |
ec7b4ce4 | 1109 | |
4e7beb0c AL |
1110 | /* |
1111 | * Called when a PMU counter is due to overflow | |
1112 | */ | |
1113 | void arm_pmu_timer_cb(void *opaque); | |
1114 | ||
033614c4 AL |
1115 | /** |
1116 | * Functions to register as EL change hooks for PMU mode filtering | |
1117 | */ | |
1118 | void pmu_pre_el_change(ARMCPU *cpu, void *ignored); | |
1119 | void pmu_post_el_change(ARMCPU *cpu, void *ignored); | |
1120 | ||
57a4a11b | 1121 | /* |
bf8d0969 AL |
1122 | * pmu_init |
1123 | * @cpu: ARMCPU | |
57a4a11b | 1124 | * |
bf8d0969 AL |
1125 | * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state |
1126 | * for the current configuration | |
57a4a11b | 1127 | */ |
bf8d0969 | 1128 | void pmu_init(ARMCPU *cpu); |
57a4a11b | 1129 | |
76e3e1bc PM |
1130 | /* SCTLR bit meanings. Several bits have been reused in newer |
1131 | * versions of the architecture; in that case we define constants | |
1132 | * for both old and new bit meanings. Code which tests against those | |
1133 | * bits should probably check or otherwise arrange that the CPU | |
1134 | * is the architectural version it expects. | |
1135 | */ | |
1136 | #define SCTLR_M (1U << 0) | |
1137 | #define SCTLR_A (1U << 1) | |
1138 | #define SCTLR_C (1U << 2) | |
1139 | #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */ | |
b2af69d0 RH |
1140 | #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */ |
1141 | #define SCTLR_SA (1U << 3) /* AArch64 only */ | |
76e3e1bc | 1142 | #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */ |
b2af69d0 | 1143 | #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */ |
76e3e1bc PM |
1144 | #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */ |
1145 | #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */ | |
1146 | #define SCTLR_CP15BEN (1U << 5) /* v7 onward */ | |
1147 | #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */ | |
b2af69d0 | 1148 | #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */ |
76e3e1bc PM |
1149 | #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */ |
1150 | #define SCTLR_ITD (1U << 7) /* v8 onward */ | |
1151 | #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */ | |
1152 | #define SCTLR_SED (1U << 8) /* v8 onward */ | |
1153 | #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ | |
1154 | #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ | |
1155 | #define SCTLR_F (1U << 10) /* up to v6 */ | |
cb570bd3 RH |
1156 | #define SCTLR_SW (1U << 10) /* v7 */ |
1157 | #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ | |
b2af69d0 RH |
1158 | #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ |
1159 | #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ | |
76e3e1bc | 1160 | #define SCTLR_I (1U << 12) |
b2af69d0 RH |
1161 | #define SCTLR_V (1U << 13) /* AArch32 only */ |
1162 | #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */ | |
76e3e1bc PM |
1163 | #define SCTLR_RR (1U << 14) /* up to v7 */ |
1164 | #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */ | |
1165 | #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */ | |
1166 | #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */ | |
1167 | #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */ | |
1168 | #define SCTLR_nTWI (1U << 16) /* v8 onward */ | |
b2af69d0 | 1169 | #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */ |
f6bda88f | 1170 | #define SCTLR_BR (1U << 17) /* PMSA only */ |
76e3e1bc PM |
1171 | #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */ |
1172 | #define SCTLR_nTWE (1U << 18) /* v8 onward */ | |
1173 | #define SCTLR_WXN (1U << 19) | |
1174 | #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ | |
b2af69d0 RH |
1175 | #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ |
1176 | #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ | |
1177 | #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ | |
1178 | #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ | |
1179 | #define SCTLR_EIS (1U << 22) /* v8.5-ExS */ | |
76e3e1bc | 1180 | #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */ |
b2af69d0 | 1181 | #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */ |
76e3e1bc PM |
1182 | #define SCTLR_VE (1U << 24) /* up to v7 */ |
1183 | #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */ | |
1184 | #define SCTLR_EE (1U << 25) | |
1185 | #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */ | |
1186 | #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */ | |
b2af69d0 RH |
1187 | #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */ |
1188 | #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */ | |
1189 | #define SCTLR_TRE (1U << 28) /* AArch32 only */ | |
1190 | #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */ | |
1191 | #define SCTLR_AFE (1U << 29) /* AArch32 only */ | |
1192 | #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */ | |
1193 | #define SCTLR_TE (1U << 30) /* AArch32 only */ | |
1194 | #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ | |
1195 | #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ | |
1196 | #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ | |
1197 | #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ | |
1198 | #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ | |
1199 | #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */ | |
1200 | #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */ | |
1201 | #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ | |
1202 | #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ | |
1203 | #define SCTLR_DSSBS (1ULL << 44) /* v8.5 */ | |
76e3e1bc | 1204 | |
c6f19164 GB |
1205 | #define CPTR_TCPAC (1U << 31) |
1206 | #define CPTR_TTA (1U << 20) | |
1207 | #define CPTR_TFP (1U << 10) | |
5be5e8ed RH |
1208 | #define CPTR_TZ (1U << 8) /* CPTR_EL2 */ |
1209 | #define CPTR_EZ (1U << 8) /* CPTR_EL3 */ | |
c6f19164 | 1210 | |
187f678d PM |
1211 | #define MDCR_EPMAD (1U << 21) |
1212 | #define MDCR_EDAD (1U << 20) | |
033614c4 AL |
1213 | #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ |
1214 | #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ | |
187f678d | 1215 | #define MDCR_SDD (1U << 16) |
a8d64e73 | 1216 | #define MDCR_SPD (3U << 14) |
187f678d PM |
1217 | #define MDCR_TDRA (1U << 11) |
1218 | #define MDCR_TDOSA (1U << 10) | |
1219 | #define MDCR_TDA (1U << 9) | |
1220 | #define MDCR_TDE (1U << 8) | |
1221 | #define MDCR_HPME (1U << 7) | |
1222 | #define MDCR_TPM (1U << 6) | |
1223 | #define MDCR_TPMCR (1U << 5) | |
033614c4 | 1224 | #define MDCR_HPMN (0x1fU) |
187f678d | 1225 | |
a8d64e73 PM |
1226 | /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ |
1227 | #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) | |
1228 | ||
78dbbbe4 PM |
1229 | #define CPSR_M (0x1fU) |
1230 | #define CPSR_T (1U << 5) | |
1231 | #define CPSR_F (1U << 6) | |
1232 | #define CPSR_I (1U << 7) | |
1233 | #define CPSR_A (1U << 8) | |
1234 | #define CPSR_E (1U << 9) | |
1235 | #define CPSR_IT_2_7 (0xfc00U) | |
1236 | #define CPSR_GE (0xfU << 16) | |
4051e12c | 1237 | #define CPSR_IL (1U << 20) |
220f508f | 1238 | #define CPSR_PAN (1U << 22) |
78dbbbe4 PM |
1239 | #define CPSR_J (1U << 24) |
1240 | #define CPSR_IT_0_1 (3U << 25) | |
1241 | #define CPSR_Q (1U << 27) | |
1242 | #define CPSR_V (1U << 28) | |
1243 | #define CPSR_C (1U << 29) | |
1244 | #define CPSR_Z (1U << 30) | |
1245 | #define CPSR_N (1U << 31) | |
9ee6e8bb | 1246 | #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) |
4cc35614 | 1247 | #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) |
9ee6e8bb PB |
1248 | |
1249 | #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) | |
4cc35614 PM |
1250 | #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ |
1251 | | CPSR_NZCV) | |
9ee6e8bb | 1252 | /* Bits writable in user mode. */ |
268b1b3d | 1253 | #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E) |
9ee6e8bb | 1254 | /* Execution state bits. MRS read as zero, MSR writes ignored. */ |
4051e12c | 1255 | #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) |
b5ff1b31 | 1256 | |
987ab45e PM |
1257 | /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ |
1258 | #define XPSR_EXCP 0x1ffU | |
1259 | #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */ | |
1260 | #define XPSR_IT_2_7 CPSR_IT_2_7 | |
1261 | #define XPSR_GE CPSR_GE | |
1262 | #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */ | |
1263 | #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */ | |
1264 | #define XPSR_IT_0_1 CPSR_IT_0_1 | |
1265 | #define XPSR_Q CPSR_Q | |
1266 | #define XPSR_V CPSR_V | |
1267 | #define XPSR_C CPSR_C | |
1268 | #define XPSR_Z CPSR_Z | |
1269 | #define XPSR_N CPSR_N | |
1270 | #define XPSR_NZCV CPSR_NZCV | |
1271 | #define XPSR_IT CPSR_IT | |
1272 | ||
e389be16 FA |
1273 | #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */ |
1274 | #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */ | |
1275 | #define TTBCR_PD0 (1U << 4) | |
1276 | #define TTBCR_PD1 (1U << 5) | |
1277 | #define TTBCR_EPD0 (1U << 7) | |
1278 | #define TTBCR_IRGN0 (3U << 8) | |
1279 | #define TTBCR_ORGN0 (3U << 10) | |
1280 | #define TTBCR_SH0 (3U << 12) | |
1281 | #define TTBCR_T1SZ (3U << 16) | |
1282 | #define TTBCR_A1 (1U << 22) | |
1283 | #define TTBCR_EPD1 (1U << 23) | |
1284 | #define TTBCR_IRGN1 (3U << 24) | |
1285 | #define TTBCR_ORGN1 (3U << 26) | |
1286 | #define TTBCR_SH1 (1U << 28) | |
1287 | #define TTBCR_EAE (1U << 31) | |
1288 | ||
d356312f PM |
1289 | /* Bit definitions for ARMv8 SPSR (PSTATE) format. |
1290 | * Only these are valid when in AArch64 mode; in | |
1291 | * AArch32 mode SPSRs are basically CPSR-format. | |
1292 | */ | |
f502cfc2 | 1293 | #define PSTATE_SP (1U) |
d356312f PM |
1294 | #define PSTATE_M (0xFU) |
1295 | #define PSTATE_nRW (1U << 4) | |
1296 | #define PSTATE_F (1U << 6) | |
1297 | #define PSTATE_I (1U << 7) | |
1298 | #define PSTATE_A (1U << 8) | |
1299 | #define PSTATE_D (1U << 9) | |
f6e52eaa | 1300 | #define PSTATE_BTYPE (3U << 10) |
d356312f PM |
1301 | #define PSTATE_IL (1U << 20) |
1302 | #define PSTATE_SS (1U << 21) | |
220f508f | 1303 | #define PSTATE_PAN (1U << 22) |
9eeb7a1c | 1304 | #define PSTATE_UAO (1U << 23) |
4b779ceb | 1305 | #define PSTATE_TCO (1U << 25) |
d356312f PM |
1306 | #define PSTATE_V (1U << 28) |
1307 | #define PSTATE_C (1U << 29) | |
1308 | #define PSTATE_Z (1U << 30) | |
1309 | #define PSTATE_N (1U << 31) | |
1310 | #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) | |
4cc35614 | 1311 | #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) |
f6e52eaa | 1312 | #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) |
d356312f PM |
1313 | /* Mode values for AArch64 */ |
1314 | #define PSTATE_MODE_EL3h 13 | |
1315 | #define PSTATE_MODE_EL3t 12 | |
1316 | #define PSTATE_MODE_EL2h 9 | |
1317 | #define PSTATE_MODE_EL2t 8 | |
1318 | #define PSTATE_MODE_EL1h 5 | |
1319 | #define PSTATE_MODE_EL1t 4 | |
1320 | #define PSTATE_MODE_EL0t 0 | |
1321 | ||
de2db7ec PM |
1322 | /* Write a new value to v7m.exception, thus transitioning into or out |
1323 | * of Handler mode; this may result in a change of active stack pointer. | |
1324 | */ | |
1325 | void write_v7m_exception(CPUARMState *env, uint32_t new_exc); | |
1326 | ||
9e729b57 EI |
1327 | /* Map EL and handler into a PSTATE_MODE. */ |
1328 | static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler) | |
1329 | { | |
1330 | return (el << 2) | handler; | |
1331 | } | |
1332 | ||
d356312f PM |
1333 | /* Return the current PSTATE value. For the moment we don't support 32<->64 bit |
1334 | * interprocessing, so we don't attempt to sync with the cpsr state used by | |
1335 | * the 32 bit decoder. | |
1336 | */ | |
1337 | static inline uint32_t pstate_read(CPUARMState *env) | |
1338 | { | |
1339 | int ZF; | |
1340 | ||
1341 | ZF = (env->ZF == 0); | |
1342 | return (env->NF & 0x80000000) | (ZF << 30) | |
1343 | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | |
f6e52eaa | 1344 | | env->pstate | env->daif | (env->btype << 10); |
d356312f PM |
1345 | } |
1346 | ||
1347 | static inline void pstate_write(CPUARMState *env, uint32_t val) | |
1348 | { | |
1349 | env->ZF = (~val) & PSTATE_Z; | |
1350 | env->NF = val; | |
1351 | env->CF = (val >> 29) & 1; | |
1352 | env->VF = (val << 3) & 0x80000000; | |
4cc35614 | 1353 | env->daif = val & PSTATE_DAIF; |
f6e52eaa | 1354 | env->btype = (val >> 10) & 3; |
d356312f PM |
1355 | env->pstate = val & ~CACHED_PSTATE_BITS; |
1356 | } | |
1357 | ||
b5ff1b31 | 1358 | /* Return the current CPSR value. */ |
2f4a40e5 | 1359 | uint32_t cpsr_read(CPUARMState *env); |
50866ba5 PM |
1360 | |
1361 | typedef enum CPSRWriteType { | |
1362 | CPSRWriteByInstr = 0, /* from guest MSR or CPS */ | |
1363 | CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ | |
1364 | CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ | |
1365 | CPSRWriteByGDBStub = 3, /* from the GDB stub */ | |
1366 | } CPSRWriteType; | |
1367 | ||
1368 | /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ | |
1369 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, | |
1370 | CPSRWriteType write_type); | |
9ee6e8bb PB |
1371 | |
1372 | /* Return the current xPSR value. */ | |
1373 | static inline uint32_t xpsr_read(CPUARMState *env) | |
1374 | { | |
1375 | int ZF; | |
6fbe23d5 PB |
1376 | ZF = (env->ZF == 0); |
1377 | return (env->NF & 0x80000000) | (ZF << 30) | |
9ee6e8bb PB |
1378 | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
1379 | | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) | |
1380 | | ((env->condexec_bits & 0xfc) << 8) | |
f1e2598c | 1381 | | (env->GE << 16) |
9ee6e8bb | 1382 | | env->v7m.exception; |
b5ff1b31 FB |
1383 | } |
1384 | ||
9ee6e8bb PB |
1385 | /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ |
1386 | static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) | |
1387 | { | |
987ab45e PM |
1388 | if (mask & XPSR_NZCV) { |
1389 | env->ZF = (~val) & XPSR_Z; | |
6fbe23d5 | 1390 | env->NF = val; |
9ee6e8bb PB |
1391 | env->CF = (val >> 29) & 1; |
1392 | env->VF = (val << 3) & 0x80000000; | |
1393 | } | |
987ab45e PM |
1394 | if (mask & XPSR_Q) { |
1395 | env->QF = ((val & XPSR_Q) != 0); | |
1396 | } | |
f1e2598c PM |
1397 | if (mask & XPSR_GE) { |
1398 | env->GE = (val & XPSR_GE) >> 16; | |
1399 | } | |
04c9c81b | 1400 | #ifndef CONFIG_USER_ONLY |
987ab45e PM |
1401 | if (mask & XPSR_T) { |
1402 | env->thumb = ((val & XPSR_T) != 0); | |
1403 | } | |
1404 | if (mask & XPSR_IT_0_1) { | |
9ee6e8bb PB |
1405 | env->condexec_bits &= ~3; |
1406 | env->condexec_bits |= (val >> 25) & 3; | |
1407 | } | |
987ab45e | 1408 | if (mask & XPSR_IT_2_7) { |
9ee6e8bb PB |
1409 | env->condexec_bits &= 3; |
1410 | env->condexec_bits |= (val >> 8) & 0xfc; | |
1411 | } | |
987ab45e | 1412 | if (mask & XPSR_EXCP) { |
de2db7ec PM |
1413 | /* Note that this only happens on exception exit */ |
1414 | write_v7m_exception(env, val & XPSR_EXCP); | |
9ee6e8bb | 1415 | } |
04c9c81b | 1416 | #endif |
9ee6e8bb PB |
1417 | } |
1418 | ||
f149e3e8 EI |
1419 | #define HCR_VM (1ULL << 0) |
1420 | #define HCR_SWIO (1ULL << 1) | |
1421 | #define HCR_PTW (1ULL << 2) | |
1422 | #define HCR_FMO (1ULL << 3) | |
1423 | #define HCR_IMO (1ULL << 4) | |
1424 | #define HCR_AMO (1ULL << 5) | |
1425 | #define HCR_VF (1ULL << 6) | |
1426 | #define HCR_VI (1ULL << 7) | |
1427 | #define HCR_VSE (1ULL << 8) | |
1428 | #define HCR_FB (1ULL << 9) | |
1429 | #define HCR_BSU_MASK (3ULL << 10) | |
1430 | #define HCR_DC (1ULL << 12) | |
1431 | #define HCR_TWI (1ULL << 13) | |
1432 | #define HCR_TWE (1ULL << 14) | |
1433 | #define HCR_TID0 (1ULL << 15) | |
1434 | #define HCR_TID1 (1ULL << 16) | |
1435 | #define HCR_TID2 (1ULL << 17) | |
1436 | #define HCR_TID3 (1ULL << 18) | |
1437 | #define HCR_TSC (1ULL << 19) | |
1438 | #define HCR_TIDCP (1ULL << 20) | |
1439 | #define HCR_TACR (1ULL << 21) | |
1440 | #define HCR_TSW (1ULL << 22) | |
099bf53b | 1441 | #define HCR_TPCP (1ULL << 23) |
f149e3e8 EI |
1442 | #define HCR_TPU (1ULL << 24) |
1443 | #define HCR_TTLB (1ULL << 25) | |
1444 | #define HCR_TVM (1ULL << 26) | |
1445 | #define HCR_TGE (1ULL << 27) | |
1446 | #define HCR_TDZ (1ULL << 28) | |
1447 | #define HCR_HCD (1ULL << 29) | |
1448 | #define HCR_TRVM (1ULL << 30) | |
1449 | #define HCR_RW (1ULL << 31) | |
1450 | #define HCR_CD (1ULL << 32) | |
1451 | #define HCR_ID (1ULL << 33) | |
ac656b16 | 1452 | #define HCR_E2H (1ULL << 34) |
099bf53b RH |
1453 | #define HCR_TLOR (1ULL << 35) |
1454 | #define HCR_TERR (1ULL << 36) | |
1455 | #define HCR_TEA (1ULL << 37) | |
1456 | #define HCR_MIOCNCE (1ULL << 38) | |
e0a38bb3 | 1457 | /* RES0 bit 39 */ |
099bf53b RH |
1458 | #define HCR_APK (1ULL << 40) |
1459 | #define HCR_API (1ULL << 41) | |
1460 | #define HCR_NV (1ULL << 42) | |
1461 | #define HCR_NV1 (1ULL << 43) | |
1462 | #define HCR_AT (1ULL << 44) | |
1463 | #define HCR_NV2 (1ULL << 45) | |
1464 | #define HCR_FWB (1ULL << 46) | |
1465 | #define HCR_FIEN (1ULL << 47) | |
e0a38bb3 | 1466 | /* RES0 bit 48 */ |
099bf53b RH |
1467 | #define HCR_TID4 (1ULL << 49) |
1468 | #define HCR_TICAB (1ULL << 50) | |
e0a38bb3 | 1469 | #define HCR_AMVOFFEN (1ULL << 51) |
099bf53b | 1470 | #define HCR_TOCU (1ULL << 52) |
e0a38bb3 | 1471 | #define HCR_ENSCXT (1ULL << 53) |
099bf53b RH |
1472 | #define HCR_TTLBIS (1ULL << 54) |
1473 | #define HCR_TTLBOS (1ULL << 55) | |
1474 | #define HCR_ATA (1ULL << 56) | |
1475 | #define HCR_DCT (1ULL << 57) | |
e0a38bb3 RH |
1476 | #define HCR_TID5 (1ULL << 58) |
1477 | #define HCR_TWEDEN (1ULL << 59) | |
1478 | #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) | |
099bf53b | 1479 | |
64e0e2de EI |
1480 | #define SCR_NS (1U << 0) |
1481 | #define SCR_IRQ (1U << 1) | |
1482 | #define SCR_FIQ (1U << 2) | |
1483 | #define SCR_EA (1U << 3) | |
1484 | #define SCR_FW (1U << 4) | |
1485 | #define SCR_AW (1U << 5) | |
1486 | #define SCR_NET (1U << 6) | |
1487 | #define SCR_SMD (1U << 7) | |
1488 | #define SCR_HCE (1U << 8) | |
1489 | #define SCR_SIF (1U << 9) | |
1490 | #define SCR_RW (1U << 10) | |
1491 | #define SCR_ST (1U << 11) | |
1492 | #define SCR_TWI (1U << 12) | |
1493 | #define SCR_TWE (1U << 13) | |
99f8f86d RH |
1494 | #define SCR_TLOR (1U << 14) |
1495 | #define SCR_TERR (1U << 15) | |
1496 | #define SCR_APK (1U << 16) | |
1497 | #define SCR_API (1U << 17) | |
1498 | #define SCR_EEL2 (1U << 18) | |
1499 | #define SCR_EASE (1U << 19) | |
1500 | #define SCR_NMEA (1U << 20) | |
1501 | #define SCR_FIEN (1U << 21) | |
1502 | #define SCR_ENSCXT (1U << 25) | |
1503 | #define SCR_ATA (1U << 26) | |
64e0e2de | 1504 | |
01653295 PM |
1505 | /* Return the current FPSCR value. */ |
1506 | uint32_t vfp_get_fpscr(CPUARMState *env); | |
1507 | void vfp_set_fpscr(CPUARMState *env, uint32_t val); | |
1508 | ||
d81ce0ef AB |
1509 | /* FPCR, Floating Point Control Register |
1510 | * FPSR, Floating Poiht Status Register | |
1511 | * | |
1512 | * For A64 the FPSCR is split into two logically distinct registers, | |
f903fa22 PM |
1513 | * FPCR and FPSR. However since they still use non-overlapping bits |
1514 | * we store the underlying state in fpscr and just mask on read/write. | |
1515 | */ | |
1516 | #define FPSR_MASK 0xf800009f | |
0b62159b | 1517 | #define FPCR_MASK 0x07ff9f00 |
d81ce0ef | 1518 | |
a15945d9 PM |
1519 | #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ |
1520 | #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ | |
1521 | #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ | |
1522 | #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ | |
1523 | #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ | |
1524 | #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ | |
d81ce0ef | 1525 | #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ |
99c7834f | 1526 | #define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ |
d81ce0ef AB |
1527 | #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ |
1528 | #define FPCR_DN (1 << 25) /* Default NaN enable bit */ | |
99c7834f | 1529 | #define FPCR_AHP (1 << 26) /* Alternative half-precision */ |
a4d58462 | 1530 | #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ |
9542c30b PM |
1531 | #define FPCR_V (1 << 28) /* FP overflow flag */ |
1532 | #define FPCR_C (1 << 29) /* FP carry flag */ | |
1533 | #define FPCR_Z (1 << 30) /* FP zero flag */ | |
1534 | #define FPCR_N (1 << 31) /* FP negative flag */ | |
1535 | ||
99c7834f PM |
1536 | #define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ |
1537 | #define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) | |
1538 | ||
9542c30b PM |
1539 | #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) |
1540 | #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) | |
d81ce0ef | 1541 | |
f903fa22 PM |
1542 | static inline uint32_t vfp_get_fpsr(CPUARMState *env) |
1543 | { | |
1544 | return vfp_get_fpscr(env) & FPSR_MASK; | |
1545 | } | |
1546 | ||
1547 | static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val) | |
1548 | { | |
1549 | uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK); | |
1550 | vfp_set_fpscr(env, new_fpscr); | |
1551 | } | |
1552 | ||
1553 | static inline uint32_t vfp_get_fpcr(CPUARMState *env) | |
1554 | { | |
1555 | return vfp_get_fpscr(env) & FPCR_MASK; | |
1556 | } | |
1557 | ||
1558 | static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val) | |
1559 | { | |
1560 | uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK); | |
1561 | vfp_set_fpscr(env, new_fpscr); | |
1562 | } | |
1563 | ||
b5ff1b31 FB |
1564 | enum arm_cpu_mode { |
1565 | ARM_CPU_MODE_USR = 0x10, | |
1566 | ARM_CPU_MODE_FIQ = 0x11, | |
1567 | ARM_CPU_MODE_IRQ = 0x12, | |
1568 | ARM_CPU_MODE_SVC = 0x13, | |
28c9457d | 1569 | ARM_CPU_MODE_MON = 0x16, |
b5ff1b31 | 1570 | ARM_CPU_MODE_ABT = 0x17, |
28c9457d | 1571 | ARM_CPU_MODE_HYP = 0x1a, |
b5ff1b31 FB |
1572 | ARM_CPU_MODE_UND = 0x1b, |
1573 | ARM_CPU_MODE_SYS = 0x1f | |
1574 | }; | |
1575 | ||
40f137e1 PB |
1576 | /* VFP system registers. */ |
1577 | #define ARM_VFP_FPSID 0 | |
1578 | #define ARM_VFP_FPSCR 1 | |
a50c0f51 | 1579 | #define ARM_VFP_MVFR2 5 |
9ee6e8bb PB |
1580 | #define ARM_VFP_MVFR1 6 |
1581 | #define ARM_VFP_MVFR0 7 | |
40f137e1 PB |
1582 | #define ARM_VFP_FPEXC 8 |
1583 | #define ARM_VFP_FPINST 9 | |
1584 | #define ARM_VFP_FPINST2 10 | |
9542c30b PM |
1585 | /* These ones are M-profile only */ |
1586 | #define ARM_VFP_FPSCR_NZCVQC 2 | |
1587 | #define ARM_VFP_VPR 12 | |
1588 | #define ARM_VFP_P0 13 | |
1589 | #define ARM_VFP_FPCXT_NS 14 | |
1590 | #define ARM_VFP_FPCXT_S 15 | |
40f137e1 | 1591 | |
32a290b8 PM |
1592 | /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ |
1593 | #define QEMU_VFP_FPSCR_NZCV 0xffff | |
1594 | ||
18c9b560 | 1595 | /* iwMMXt coprocessor control registers. */ |
6e0fafe2 PM |
1596 | #define ARM_IWMMXT_wCID 0 |
1597 | #define ARM_IWMMXT_wCon 1 | |
1598 | #define ARM_IWMMXT_wCSSF 2 | |
1599 | #define ARM_IWMMXT_wCASF 3 | |
1600 | #define ARM_IWMMXT_wCGR0 8 | |
1601 | #define ARM_IWMMXT_wCGR1 9 | |
1602 | #define ARM_IWMMXT_wCGR2 10 | |
1603 | #define ARM_IWMMXT_wCGR3 11 | |
18c9b560 | 1604 | |
2c4da50d PM |
1605 | /* V7M CCR bits */ |
1606 | FIELD(V7M_CCR, NONBASETHRDENA, 0, 1) | |
1607 | FIELD(V7M_CCR, USERSETMPEND, 1, 1) | |
1608 | FIELD(V7M_CCR, UNALIGN_TRP, 3, 1) | |
1609 | FIELD(V7M_CCR, DIV_0_TRP, 4, 1) | |
1610 | FIELD(V7M_CCR, BFHFNMIGN, 8, 1) | |
1611 | FIELD(V7M_CCR, STKALIGN, 9, 1) | |
4730fb85 | 1612 | FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) |
2c4da50d PM |
1613 | FIELD(V7M_CCR, DC, 16, 1) |
1614 | FIELD(V7M_CCR, IC, 17, 1) | |
4730fb85 | 1615 | FIELD(V7M_CCR, BP, 18, 1) |
0e83f905 PM |
1616 | FIELD(V7M_CCR, LOB, 19, 1) |
1617 | FIELD(V7M_CCR, TRD, 20, 1) | |
2c4da50d | 1618 | |
24ac0fb1 PM |
1619 | /* V7M SCR bits */ |
1620 | FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) | |
1621 | FIELD(V7M_SCR, SLEEPDEEP, 2, 1) | |
1622 | FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) | |
1623 | FIELD(V7M_SCR, SEVONPEND, 4, 1) | |
1624 | ||
3b2e9344 PM |
1625 | /* V7M AIRCR bits */ |
1626 | FIELD(V7M_AIRCR, VECTRESET, 0, 1) | |
1627 | FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1) | |
1628 | FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1) | |
1629 | FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1) | |
1630 | FIELD(V7M_AIRCR, PRIGROUP, 8, 3) | |
1631 | FIELD(V7M_AIRCR, BFHFNMINS, 13, 1) | |
1632 | FIELD(V7M_AIRCR, PRIS, 14, 1) | |
1633 | FIELD(V7M_AIRCR, ENDIANNESS, 15, 1) | |
1634 | FIELD(V7M_AIRCR, VECTKEY, 16, 16) | |
1635 | ||
2c4da50d PM |
1636 | /* V7M CFSR bits for MMFSR */ |
1637 | FIELD(V7M_CFSR, IACCVIOL, 0, 1) | |
1638 | FIELD(V7M_CFSR, DACCVIOL, 1, 1) | |
1639 | FIELD(V7M_CFSR, MUNSTKERR, 3, 1) | |
1640 | FIELD(V7M_CFSR, MSTKERR, 4, 1) | |
1641 | FIELD(V7M_CFSR, MLSPERR, 5, 1) | |
1642 | FIELD(V7M_CFSR, MMARVALID, 7, 1) | |
1643 | ||
1644 | /* V7M CFSR bits for BFSR */ | |
1645 | FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1) | |
1646 | FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1) | |
1647 | FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1) | |
1648 | FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1) | |
1649 | FIELD(V7M_CFSR, STKERR, 8 + 4, 1) | |
1650 | FIELD(V7M_CFSR, LSPERR, 8 + 5, 1) | |
1651 | FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1) | |
1652 | ||
1653 | /* V7M CFSR bits for UFSR */ | |
1654 | FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1) | |
1655 | FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1) | |
1656 | FIELD(V7M_CFSR, INVPC, 16 + 2, 1) | |
1657 | FIELD(V7M_CFSR, NOCP, 16 + 3, 1) | |
86f026de | 1658 | FIELD(V7M_CFSR, STKOF, 16 + 4, 1) |
2c4da50d PM |
1659 | FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) |
1660 | FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) | |
1661 | ||
334e8dad PM |
1662 | /* V7M CFSR bit masks covering all of the subregister bits */ |
1663 | FIELD(V7M_CFSR, MMFSR, 0, 8) | |
1664 | FIELD(V7M_CFSR, BFSR, 8, 8) | |
1665 | FIELD(V7M_CFSR, UFSR, 16, 16) | |
1666 | ||
2c4da50d PM |
1667 | /* V7M HFSR bits */ |
1668 | FIELD(V7M_HFSR, VECTTBL, 1, 1) | |
1669 | FIELD(V7M_HFSR, FORCED, 30, 1) | |
1670 | FIELD(V7M_HFSR, DEBUGEVT, 31, 1) | |
1671 | ||
1672 | /* V7M DFSR bits */ | |
1673 | FIELD(V7M_DFSR, HALTED, 0, 1) | |
1674 | FIELD(V7M_DFSR, BKPT, 1, 1) | |
1675 | FIELD(V7M_DFSR, DWTTRAP, 2, 1) | |
1676 | FIELD(V7M_DFSR, VCATCH, 3, 1) | |
1677 | FIELD(V7M_DFSR, EXTERNAL, 4, 1) | |
1678 | ||
bed079da PM |
1679 | /* V7M SFSR bits */ |
1680 | FIELD(V7M_SFSR, INVEP, 0, 1) | |
1681 | FIELD(V7M_SFSR, INVIS, 1, 1) | |
1682 | FIELD(V7M_SFSR, INVER, 2, 1) | |
1683 | FIELD(V7M_SFSR, AUVIOL, 3, 1) | |
1684 | FIELD(V7M_SFSR, INVTRAN, 4, 1) | |
1685 | FIELD(V7M_SFSR, LSPERR, 5, 1) | |
1686 | FIELD(V7M_SFSR, SFARVALID, 6, 1) | |
1687 | FIELD(V7M_SFSR, LSERR, 7, 1) | |
1688 | ||
29c483a5 MD |
1689 | /* v7M MPU_CTRL bits */ |
1690 | FIELD(V7M_MPU_CTRL, ENABLE, 0, 1) | |
1691 | FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1) | |
1692 | FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1) | |
1693 | ||
43bbce7f PM |
1694 | /* v7M CLIDR bits */ |
1695 | FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21) | |
1696 | FIELD(V7M_CLIDR, LOUIS, 21, 3) | |
1697 | FIELD(V7M_CLIDR, LOC, 24, 3) | |
1698 | FIELD(V7M_CLIDR, LOUU, 27, 3) | |
1699 | FIELD(V7M_CLIDR, ICB, 30, 2) | |
1700 | ||
1701 | FIELD(V7M_CSSELR, IND, 0, 1) | |
1702 | FIELD(V7M_CSSELR, LEVEL, 1, 3) | |
1703 | /* We use the combination of InD and Level to index into cpu->ccsidr[]; | |
1704 | * define a mask for this and check that it doesn't permit running off | |
1705 | * the end of the array. | |
1706 | */ | |
1707 | FIELD(V7M_CSSELR, INDEX, 0, 4) | |
d33abe82 PM |
1708 | |
1709 | /* v7M FPCCR bits */ | |
1710 | FIELD(V7M_FPCCR, LSPACT, 0, 1) | |
1711 | FIELD(V7M_FPCCR, USER, 1, 1) | |
1712 | FIELD(V7M_FPCCR, S, 2, 1) | |
1713 | FIELD(V7M_FPCCR, THREAD, 3, 1) | |
1714 | FIELD(V7M_FPCCR, HFRDY, 4, 1) | |
1715 | FIELD(V7M_FPCCR, MMRDY, 5, 1) | |
1716 | FIELD(V7M_FPCCR, BFRDY, 6, 1) | |
1717 | FIELD(V7M_FPCCR, SFRDY, 7, 1) | |
1718 | FIELD(V7M_FPCCR, MONRDY, 8, 1) | |
1719 | FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) | |
1720 | FIELD(V7M_FPCCR, UFRDY, 10, 1) | |
1721 | FIELD(V7M_FPCCR, RES0, 11, 15) | |
1722 | FIELD(V7M_FPCCR, TS, 26, 1) | |
1723 | FIELD(V7M_FPCCR, CLRONRETS, 27, 1) | |
1724 | FIELD(V7M_FPCCR, CLRONRET, 28, 1) | |
1725 | FIELD(V7M_FPCCR, LSPENS, 29, 1) | |
1726 | FIELD(V7M_FPCCR, LSPEN, 30, 1) | |
1727 | FIELD(V7M_FPCCR, ASPEN, 31, 1) | |
1728 | /* These bits are banked. Others are non-banked and live in the M_REG_S bank */ | |
1729 | #define R_V7M_FPCCR_BANKED_MASK \ | |
1730 | (R_V7M_FPCCR_LSPACT_MASK | \ | |
1731 | R_V7M_FPCCR_USER_MASK | \ | |
1732 | R_V7M_FPCCR_THREAD_MASK | \ | |
1733 | R_V7M_FPCCR_MMRDY_MASK | \ | |
1734 | R_V7M_FPCCR_SPLIMVIOL_MASK | \ | |
1735 | R_V7M_FPCCR_UFRDY_MASK | \ | |
1736 | R_V7M_FPCCR_ASPEN_MASK) | |
43bbce7f | 1737 | |
a62e62af RH |
1738 | /* |
1739 | * System register ID fields. | |
1740 | */ | |
2a14526a LL |
1741 | FIELD(CLIDR_EL1, CTYPE1, 0, 3) |
1742 | FIELD(CLIDR_EL1, CTYPE2, 3, 3) | |
1743 | FIELD(CLIDR_EL1, CTYPE3, 6, 3) | |
1744 | FIELD(CLIDR_EL1, CTYPE4, 9, 3) | |
1745 | FIELD(CLIDR_EL1, CTYPE5, 12, 3) | |
1746 | FIELD(CLIDR_EL1, CTYPE6, 15, 3) | |
1747 | FIELD(CLIDR_EL1, CTYPE7, 18, 3) | |
1748 | FIELD(CLIDR_EL1, LOUIS, 21, 3) | |
1749 | FIELD(CLIDR_EL1, LOC, 24, 3) | |
1750 | FIELD(CLIDR_EL1, LOUU, 27, 3) | |
1751 | FIELD(CLIDR_EL1, ICB, 30, 3) | |
1752 | ||
1753 | /* When FEAT_CCIDX is implemented */ | |
1754 | FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3) | |
1755 | FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21) | |
1756 | FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24) | |
1757 | ||
1758 | /* When FEAT_CCIDX is not implemented */ | |
1759 | FIELD(CCSIDR_EL1, LINESIZE, 0, 3) | |
1760 | FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10) | |
1761 | FIELD(CCSIDR_EL1, NUMSETS, 13, 15) | |
1762 | ||
1763 | FIELD(CTR_EL0, IMINLINE, 0, 4) | |
1764 | FIELD(CTR_EL0, L1IP, 14, 2) | |
1765 | FIELD(CTR_EL0, DMINLINE, 16, 4) | |
1766 | FIELD(CTR_EL0, ERG, 20, 4) | |
1767 | FIELD(CTR_EL0, CWG, 24, 4) | |
1768 | FIELD(CTR_EL0, IDC, 28, 1) | |
1769 | FIELD(CTR_EL0, DIC, 29, 1) | |
1770 | FIELD(CTR_EL0, TMINLINE, 32, 6) | |
1771 | ||
2bd5f41c AB |
1772 | FIELD(MIDR_EL1, REVISION, 0, 4) |
1773 | FIELD(MIDR_EL1, PARTNUM, 4, 12) | |
1774 | FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) | |
1775 | FIELD(MIDR_EL1, VARIANT, 20, 4) | |
1776 | FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) | |
1777 | ||
a62e62af RH |
1778 | FIELD(ID_ISAR0, SWAP, 0, 4) |
1779 | FIELD(ID_ISAR0, BITCOUNT, 4, 4) | |
1780 | FIELD(ID_ISAR0, BITFIELD, 8, 4) | |
1781 | FIELD(ID_ISAR0, CMPBRANCH, 12, 4) | |
1782 | FIELD(ID_ISAR0, COPROC, 16, 4) | |
1783 | FIELD(ID_ISAR0, DEBUG, 20, 4) | |
1784 | FIELD(ID_ISAR0, DIVIDE, 24, 4) | |
1785 | ||
1786 | FIELD(ID_ISAR1, ENDIAN, 0, 4) | |
1787 | FIELD(ID_ISAR1, EXCEPT, 4, 4) | |
1788 | FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) | |
1789 | FIELD(ID_ISAR1, EXTEND, 12, 4) | |
1790 | FIELD(ID_ISAR1, IFTHEN, 16, 4) | |
1791 | FIELD(ID_ISAR1, IMMEDIATE, 20, 4) | |
1792 | FIELD(ID_ISAR1, INTERWORK, 24, 4) | |
1793 | FIELD(ID_ISAR1, JAZELLE, 28, 4) | |
1794 | ||
1795 | FIELD(ID_ISAR2, LOADSTORE, 0, 4) | |
1796 | FIELD(ID_ISAR2, MEMHINT, 4, 4) | |
1797 | FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) | |
1798 | FIELD(ID_ISAR2, MULT, 12, 4) | |
1799 | FIELD(ID_ISAR2, MULTS, 16, 4) | |
1800 | FIELD(ID_ISAR2, MULTU, 20, 4) | |
1801 | FIELD(ID_ISAR2, PSR_AR, 24, 4) | |
1802 | FIELD(ID_ISAR2, REVERSAL, 28, 4) | |
1803 | ||
1804 | FIELD(ID_ISAR3, SATURATE, 0, 4) | |
1805 | FIELD(ID_ISAR3, SIMD, 4, 4) | |
1806 | FIELD(ID_ISAR3, SVC, 8, 4) | |
1807 | FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) | |
1808 | FIELD(ID_ISAR3, TABBRANCH, 16, 4) | |
1809 | FIELD(ID_ISAR3, T32COPY, 20, 4) | |
1810 | FIELD(ID_ISAR3, TRUENOP, 24, 4) | |
1811 | FIELD(ID_ISAR3, T32EE, 28, 4) | |
1812 | ||
1813 | FIELD(ID_ISAR4, UNPRIV, 0, 4) | |
1814 | FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) | |
1815 | FIELD(ID_ISAR4, WRITEBACK, 8, 4) | |
1816 | FIELD(ID_ISAR4, SMC, 12, 4) | |
1817 | FIELD(ID_ISAR4, BARRIER, 16, 4) | |
1818 | FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) | |
1819 | FIELD(ID_ISAR4, PSR_M, 24, 4) | |
1820 | FIELD(ID_ISAR4, SWP_FRAC, 28, 4) | |
1821 | ||
1822 | FIELD(ID_ISAR5, SEVL, 0, 4) | |
1823 | FIELD(ID_ISAR5, AES, 4, 4) | |
1824 | FIELD(ID_ISAR5, SHA1, 8, 4) | |
1825 | FIELD(ID_ISAR5, SHA2, 12, 4) | |
1826 | FIELD(ID_ISAR5, CRC32, 16, 4) | |
1827 | FIELD(ID_ISAR5, RDM, 24, 4) | |
1828 | FIELD(ID_ISAR5, VCMA, 28, 4) | |
1829 | ||
1830 | FIELD(ID_ISAR6, JSCVT, 0, 4) | |
1831 | FIELD(ID_ISAR6, DP, 4, 4) | |
1832 | FIELD(ID_ISAR6, FHM, 8, 4) | |
1833 | FIELD(ID_ISAR6, SB, 12, 4) | |
1834 | FIELD(ID_ISAR6, SPECRES, 16, 4) | |
bd78b6be LL |
1835 | FIELD(ID_ISAR6, BF16, 20, 4) |
1836 | FIELD(ID_ISAR6, I8MM, 24, 4) | |
a62e62af | 1837 | |
0ae0326b PM |
1838 | FIELD(ID_MMFR0, VMSA, 0, 4) |
1839 | FIELD(ID_MMFR0, PMSA, 4, 4) | |
1840 | FIELD(ID_MMFR0, OUTERSHR, 8, 4) | |
1841 | FIELD(ID_MMFR0, SHARELVL, 12, 4) | |
1842 | FIELD(ID_MMFR0, TCM, 16, 4) | |
1843 | FIELD(ID_MMFR0, AUXREG, 20, 4) | |
1844 | FIELD(ID_MMFR0, FCSE, 24, 4) | |
1845 | FIELD(ID_MMFR0, INNERSHR, 28, 4) | |
1846 | ||
bd78b6be LL |
1847 | FIELD(ID_MMFR1, L1HVDVA, 0, 4) |
1848 | FIELD(ID_MMFR1, L1UNIVA, 4, 4) | |
1849 | FIELD(ID_MMFR1, L1HVDSW, 8, 4) | |
1850 | FIELD(ID_MMFR1, L1UNISW, 12, 4) | |
1851 | FIELD(ID_MMFR1, L1HVD, 16, 4) | |
1852 | FIELD(ID_MMFR1, L1UNI, 20, 4) | |
1853 | FIELD(ID_MMFR1, L1TSTCLN, 24, 4) | |
1854 | FIELD(ID_MMFR1, BPRED, 28, 4) | |
1855 | ||
1856 | FIELD(ID_MMFR2, L1HVDFG, 0, 4) | |
1857 | FIELD(ID_MMFR2, L1HVDBG, 4, 4) | |
1858 | FIELD(ID_MMFR2, L1HVDRNG, 8, 4) | |
1859 | FIELD(ID_MMFR2, HVDTLB, 12, 4) | |
1860 | FIELD(ID_MMFR2, UNITLB, 16, 4) | |
1861 | FIELD(ID_MMFR2, MEMBARR, 20, 4) | |
1862 | FIELD(ID_MMFR2, WFISTALL, 24, 4) | |
1863 | FIELD(ID_MMFR2, HWACCFLG, 28, 4) | |
1864 | ||
3d6ad6bb RH |
1865 | FIELD(ID_MMFR3, CMAINTVA, 0, 4) |
1866 | FIELD(ID_MMFR3, CMAINTSW, 4, 4) | |
1867 | FIELD(ID_MMFR3, BPMAINT, 8, 4) | |
1868 | FIELD(ID_MMFR3, MAINTBCST, 12, 4) | |
1869 | FIELD(ID_MMFR3, PAN, 16, 4) | |
1870 | FIELD(ID_MMFR3, COHWALK, 20, 4) | |
1871 | FIELD(ID_MMFR3, CMEMSZ, 24, 4) | |
1872 | FIELD(ID_MMFR3, SUPERSEC, 28, 4) | |
1873 | ||
ab638a32 RH |
1874 | FIELD(ID_MMFR4, SPECSEI, 0, 4) |
1875 | FIELD(ID_MMFR4, AC2, 4, 4) | |
1876 | FIELD(ID_MMFR4, XNX, 8, 4) | |
1877 | FIELD(ID_MMFR4, CNP, 12, 4) | |
1878 | FIELD(ID_MMFR4, HPDS, 16, 4) | |
1879 | FIELD(ID_MMFR4, LSM, 20, 4) | |
1880 | FIELD(ID_MMFR4, CCIDX, 24, 4) | |
1881 | FIELD(ID_MMFR4, EVT, 28, 4) | |
1882 | ||
bd78b6be LL |
1883 | FIELD(ID_MMFR5, ETS, 0, 4) |
1884 | ||
46f4976f PM |
1885 | FIELD(ID_PFR0, STATE0, 0, 4) |
1886 | FIELD(ID_PFR0, STATE1, 4, 4) | |
1887 | FIELD(ID_PFR0, STATE2, 8, 4) | |
1888 | FIELD(ID_PFR0, STATE3, 12, 4) | |
1889 | FIELD(ID_PFR0, CSV2, 16, 4) | |
1890 | FIELD(ID_PFR0, AMU, 20, 4) | |
1891 | FIELD(ID_PFR0, DIT, 24, 4) | |
1892 | FIELD(ID_PFR0, RAS, 28, 4) | |
1893 | ||
dfc523a8 PM |
1894 | FIELD(ID_PFR1, PROGMOD, 0, 4) |
1895 | FIELD(ID_PFR1, SECURITY, 4, 4) | |
1896 | FIELD(ID_PFR1, MPROGMOD, 8, 4) | |
1897 | FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) | |
1898 | FIELD(ID_PFR1, GENTIMER, 16, 4) | |
1899 | FIELD(ID_PFR1, SEC_FRAC, 20, 4) | |
1900 | FIELD(ID_PFR1, VIRT_FRAC, 24, 4) | |
1901 | FIELD(ID_PFR1, GIC, 28, 4) | |
1902 | ||
bd78b6be LL |
1903 | FIELD(ID_PFR2, CSV3, 0, 4) |
1904 | FIELD(ID_PFR2, SSBS, 4, 4) | |
1905 | FIELD(ID_PFR2, RAS_FRAC, 8, 4) | |
1906 | ||
a62e62af RH |
1907 | FIELD(ID_AA64ISAR0, AES, 4, 4) |
1908 | FIELD(ID_AA64ISAR0, SHA1, 8, 4) | |
1909 | FIELD(ID_AA64ISAR0, SHA2, 12, 4) | |
1910 | FIELD(ID_AA64ISAR0, CRC32, 16, 4) | |
1911 | FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) | |
1912 | FIELD(ID_AA64ISAR0, RDM, 28, 4) | |
1913 | FIELD(ID_AA64ISAR0, SHA3, 32, 4) | |
1914 | FIELD(ID_AA64ISAR0, SM3, 36, 4) | |
1915 | FIELD(ID_AA64ISAR0, SM4, 40, 4) | |
1916 | FIELD(ID_AA64ISAR0, DP, 44, 4) | |
1917 | FIELD(ID_AA64ISAR0, FHM, 48, 4) | |
1918 | FIELD(ID_AA64ISAR0, TS, 52, 4) | |
1919 | FIELD(ID_AA64ISAR0, TLB, 56, 4) | |
1920 | FIELD(ID_AA64ISAR0, RNDR, 60, 4) | |
1921 | ||
1922 | FIELD(ID_AA64ISAR1, DPB, 0, 4) | |
1923 | FIELD(ID_AA64ISAR1, APA, 4, 4) | |
1924 | FIELD(ID_AA64ISAR1, API, 8, 4) | |
1925 | FIELD(ID_AA64ISAR1, JSCVT, 12, 4) | |
1926 | FIELD(ID_AA64ISAR1, FCMA, 16, 4) | |
1927 | FIELD(ID_AA64ISAR1, LRCPC, 20, 4) | |
1928 | FIELD(ID_AA64ISAR1, GPA, 24, 4) | |
1929 | FIELD(ID_AA64ISAR1, GPI, 28, 4) | |
1930 | FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) | |
1931 | FIELD(ID_AA64ISAR1, SB, 36, 4) | |
1932 | FIELD(ID_AA64ISAR1, SPECRES, 40, 4) | |
00a92832 LL |
1933 | FIELD(ID_AA64ISAR1, BF16, 44, 4) |
1934 | FIELD(ID_AA64ISAR1, DGH, 48, 4) | |
1935 | FIELD(ID_AA64ISAR1, I8MM, 52, 4) | |
a62e62af | 1936 | |
cd208a1c RH |
1937 | FIELD(ID_AA64PFR0, EL0, 0, 4) |
1938 | FIELD(ID_AA64PFR0, EL1, 4, 4) | |
1939 | FIELD(ID_AA64PFR0, EL2, 8, 4) | |
1940 | FIELD(ID_AA64PFR0, EL3, 12, 4) | |
1941 | FIELD(ID_AA64PFR0, FP, 16, 4) | |
1942 | FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) | |
1943 | FIELD(ID_AA64PFR0, GIC, 24, 4) | |
1944 | FIELD(ID_AA64PFR0, RAS, 28, 4) | |
1945 | FIELD(ID_AA64PFR0, SVE, 32, 4) | |
00a92832 LL |
1946 | FIELD(ID_AA64PFR0, SEL2, 36, 4) |
1947 | FIELD(ID_AA64PFR0, MPAM, 40, 4) | |
1948 | FIELD(ID_AA64PFR0, AMU, 44, 4) | |
1949 | FIELD(ID_AA64PFR0, DIT, 48, 4) | |
1950 | FIELD(ID_AA64PFR0, CSV2, 56, 4) | |
1951 | FIELD(ID_AA64PFR0, CSV3, 60, 4) | |
cd208a1c | 1952 | |
be53b6f4 | 1953 | FIELD(ID_AA64PFR1, BT, 0, 4) |
9a286bcd | 1954 | FIELD(ID_AA64PFR1, SSBS, 4, 4) |
be53b6f4 RH |
1955 | FIELD(ID_AA64PFR1, MTE, 8, 4) |
1956 | FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) | |
00a92832 | 1957 | FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) |
be53b6f4 | 1958 | |
3dc91ddb PM |
1959 | FIELD(ID_AA64MMFR0, PARANGE, 0, 4) |
1960 | FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) | |
1961 | FIELD(ID_AA64MMFR0, BIGEND, 8, 4) | |
1962 | FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) | |
1963 | FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) | |
1964 | FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) | |
1965 | FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) | |
1966 | FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) | |
1967 | FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) | |
1968 | FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) | |
1969 | FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) | |
1970 | FIELD(ID_AA64MMFR0, EXS, 44, 4) | |
00a92832 LL |
1971 | FIELD(ID_AA64MMFR0, FGT, 56, 4) |
1972 | FIELD(ID_AA64MMFR0, ECV, 60, 4) | |
3dc91ddb PM |
1973 | |
1974 | FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) | |
1975 | FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) | |
1976 | FIELD(ID_AA64MMFR1, VH, 8, 4) | |
1977 | FIELD(ID_AA64MMFR1, HPDS, 12, 4) | |
1978 | FIELD(ID_AA64MMFR1, LO, 16, 4) | |
1979 | FIELD(ID_AA64MMFR1, PAN, 20, 4) | |
1980 | FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) | |
1981 | FIELD(ID_AA64MMFR1, XNX, 28, 4) | |
00a92832 LL |
1982 | FIELD(ID_AA64MMFR1, TWED, 32, 4) |
1983 | FIELD(ID_AA64MMFR1, ETS, 36, 4) | |
3dc91ddb | 1984 | |
64761e10 RH |
1985 | FIELD(ID_AA64MMFR2, CNP, 0, 4) |
1986 | FIELD(ID_AA64MMFR2, UAO, 4, 4) | |
1987 | FIELD(ID_AA64MMFR2, LSM, 8, 4) | |
1988 | FIELD(ID_AA64MMFR2, IESB, 12, 4) | |
1989 | FIELD(ID_AA64MMFR2, VARANGE, 16, 4) | |
1990 | FIELD(ID_AA64MMFR2, CCIDX, 20, 4) | |
1991 | FIELD(ID_AA64MMFR2, NV, 24, 4) | |
1992 | FIELD(ID_AA64MMFR2, ST, 28, 4) | |
1993 | FIELD(ID_AA64MMFR2, AT, 32, 4) | |
1994 | FIELD(ID_AA64MMFR2, IDS, 36, 4) | |
1995 | FIELD(ID_AA64MMFR2, FWB, 40, 4) | |
1996 | FIELD(ID_AA64MMFR2, TTL, 48, 4) | |
1997 | FIELD(ID_AA64MMFR2, BBM, 52, 4) | |
1998 | FIELD(ID_AA64MMFR2, EVT, 56, 4) | |
1999 | FIELD(ID_AA64MMFR2, E0PD, 60, 4) | |
2000 | ||
ceb2744b PM |
2001 | FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) |
2002 | FIELD(ID_AA64DFR0, TRACEVER, 4, 4) | |
2003 | FIELD(ID_AA64DFR0, PMUVER, 8, 4) | |
2004 | FIELD(ID_AA64DFR0, BRPS, 12, 4) | |
2005 | FIELD(ID_AA64DFR0, WRPS, 20, 4) | |
2006 | FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) | |
2007 | FIELD(ID_AA64DFR0, PMSVER, 32, 4) | |
2008 | FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) | |
2009 | FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) | |
00a92832 | 2010 | FIELD(ID_AA64DFR0, MTPMU, 48, 4) |
ceb2744b | 2011 | |
beceb99c AL |
2012 | FIELD(ID_DFR0, COPDBG, 0, 4) |
2013 | FIELD(ID_DFR0, COPSDBG, 4, 4) | |
2014 | FIELD(ID_DFR0, MMAPDBG, 8, 4) | |
2015 | FIELD(ID_DFR0, COPTRC, 12, 4) | |
2016 | FIELD(ID_DFR0, MMAPTRC, 16, 4) | |
2017 | FIELD(ID_DFR0, MPROFDBG, 20, 4) | |
2018 | FIELD(ID_DFR0, PERFMON, 24, 4) | |
2019 | FIELD(ID_DFR0, TRACEFILT, 28, 4) | |
2020 | ||
bd78b6be LL |
2021 | FIELD(ID_DFR1, MTPMU, 0, 4) |
2022 | ||
88ce6c6e PM |
2023 | FIELD(DBGDIDR, SE_IMP, 12, 1) |
2024 | FIELD(DBGDIDR, NSUHD_IMP, 14, 1) | |
2025 | FIELD(DBGDIDR, VERSION, 16, 4) | |
2026 | FIELD(DBGDIDR, CTX_CMPS, 20, 4) | |
2027 | FIELD(DBGDIDR, BRPS, 24, 4) | |
2028 | FIELD(DBGDIDR, WRPS, 28, 4) | |
2029 | ||
602f6e42 PM |
2030 | FIELD(MVFR0, SIMDREG, 0, 4) |
2031 | FIELD(MVFR0, FPSP, 4, 4) | |
2032 | FIELD(MVFR0, FPDP, 8, 4) | |
2033 | FIELD(MVFR0, FPTRAP, 12, 4) | |
2034 | FIELD(MVFR0, FPDIVIDE, 16, 4) | |
2035 | FIELD(MVFR0, FPSQRT, 20, 4) | |
2036 | FIELD(MVFR0, FPSHVEC, 24, 4) | |
2037 | FIELD(MVFR0, FPROUND, 28, 4) | |
2038 | ||
2039 | FIELD(MVFR1, FPFTZ, 0, 4) | |
2040 | FIELD(MVFR1, FPDNAN, 4, 4) | |
dfc523a8 PM |
2041 | FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ |
2042 | FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ | |
2043 | FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ | |
2044 | FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ | |
2045 | FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ | |
2046 | FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ | |
602f6e42 PM |
2047 | FIELD(MVFR1, FPHP, 24, 4) |
2048 | FIELD(MVFR1, SIMDFMAC, 28, 4) | |
2049 | ||
2050 | FIELD(MVFR2, SIMDMISC, 0, 4) | |
2051 | FIELD(MVFR2, FPMISC, 4, 4) | |
2052 | ||
43bbce7f PM |
2053 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); |
2054 | ||
ce854d7c BC |
2055 | /* If adding a feature bit which corresponds to a Linux ELF |
2056 | * HWCAP bit, remember to update the feature-bit-to-hwcap | |
2057 | * mapping in linux-user/elfload.c:get_elf_hwcap(). | |
2058 | */ | |
40f137e1 | 2059 | enum arm_features { |
c1713132 AZ |
2060 | ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ |
2061 | ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ | |
ce819861 | 2062 | ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ |
9ee6e8bb PB |
2063 | ARM_FEATURE_V6, |
2064 | ARM_FEATURE_V6K, | |
2065 | ARM_FEATURE_V7, | |
2066 | ARM_FEATURE_THUMB2, | |
452a0955 | 2067 | ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ |
9ee6e8bb | 2068 | ARM_FEATURE_NEON, |
9ee6e8bb | 2069 | ARM_FEATURE_M, /* Microcontroller profile. */ |
fe1479c3 | 2070 | ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ |
e1bbf446 | 2071 | ARM_FEATURE_THUMB2EE, |
be5e7a76 | 2072 | ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ |
5110e683 | 2073 | ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ |
be5e7a76 DES |
2074 | ARM_FEATURE_V4T, |
2075 | ARM_FEATURE_V5, | |
5bc95aa2 | 2076 | ARM_FEATURE_STRONGARM, |
906879a9 | 2077 | ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ |
0383ac00 | 2078 | ARM_FEATURE_GENERIC_TIMER, |
06ed5d66 | 2079 | ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ |
1047b9d7 | 2080 | ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ |
c4804214 PM |
2081 | ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ |
2082 | ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ | |
2083 | ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ | |
81bdde9d | 2084 | ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ |
de9b05b8 | 2085 | ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ |
81e69fb0 | 2086 | ARM_FEATURE_V8, |
3926cc84 | 2087 | ARM_FEATURE_AARCH64, /* supports 64 bit mode */ |
d8ba780b | 2088 | ARM_FEATURE_CBAR, /* has cp15 CBAR */ |
f318cec6 | 2089 | ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ |
cca7c2f5 | 2090 | ARM_FEATURE_EL2, /* has EL2 Virtualization support */ |
1fe8141e | 2091 | ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ |
62b44f05 | 2092 | ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ |
929e754d | 2093 | ARM_FEATURE_PMU, /* has PMU support */ |
91db4642 | 2094 | ARM_FEATURE_VBAR, /* has cp15 VBAR */ |
1e577cc7 | 2095 | ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ |
cc2ae7c9 | 2096 | ARM_FEATURE_M_MAIN, /* M profile Main Extension */ |
5d2555a1 | 2097 | ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ |
40f137e1 PB |
2098 | }; |
2099 | ||
2100 | static inline int arm_feature(CPUARMState *env, int feature) | |
2101 | { | |
918f5dca | 2102 | return (env->features & (1ULL << feature)) != 0; |
40f137e1 PB |
2103 | } |
2104 | ||
0df9142d AJ |
2105 | void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); |
2106 | ||
19e0fefa FA |
2107 | #if !defined(CONFIG_USER_ONLY) |
2108 | /* Return true if exception levels below EL3 are in secure state, | |
2109 | * or would be following an exception return to that level. | |
2110 | * Unlike arm_is_secure() (which is always a question about the | |
2111 | * _current_ state of the CPU) this doesn't care about the current | |
2112 | * EL or mode. | |
2113 | */ | |
2114 | static inline bool arm_is_secure_below_el3(CPUARMState *env) | |
2115 | { | |
2116 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
2117 | return !(env->cp15.scr_el3 & SCR_NS); | |
2118 | } else { | |
6b7f0b61 | 2119 | /* If EL3 is not supported then the secure state is implementation |
19e0fefa FA |
2120 | * defined, in which case QEMU defaults to non-secure. |
2121 | */ | |
2122 | return false; | |
2123 | } | |
2124 | } | |
2125 | ||
71205876 PM |
2126 | /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ |
2127 | static inline bool arm_is_el3_or_mon(CPUARMState *env) | |
19e0fefa FA |
2128 | { |
2129 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
2130 | if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { | |
2131 | /* CPU currently in AArch64 state and EL3 */ | |
2132 | return true; | |
2133 | } else if (!is_a64(env) && | |
2134 | (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
2135 | /* CPU currently in AArch32 state and monitor mode */ | |
2136 | return true; | |
2137 | } | |
2138 | } | |
71205876 PM |
2139 | return false; |
2140 | } | |
2141 | ||
2142 | /* Return true if the processor is in secure state */ | |
2143 | static inline bool arm_is_secure(CPUARMState *env) | |
2144 | { | |
2145 | if (arm_is_el3_or_mon(env)) { | |
2146 | return true; | |
2147 | } | |
19e0fefa FA |
2148 | return arm_is_secure_below_el3(env); |
2149 | } | |
2150 | ||
f3ee5160 RDC |
2151 | /* |
2152 | * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. | |
2153 | * This corresponds to the pseudocode EL2Enabled() | |
2154 | */ | |
2155 | static inline bool arm_is_el2_enabled(CPUARMState *env) | |
2156 | { | |
2157 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
2158 | return !arm_is_secure_below_el3(env); | |
2159 | } | |
2160 | return false; | |
2161 | } | |
2162 | ||
19e0fefa FA |
2163 | #else |
2164 | static inline bool arm_is_secure_below_el3(CPUARMState *env) | |
2165 | { | |
2166 | return false; | |
2167 | } | |
2168 | ||
2169 | static inline bool arm_is_secure(CPUARMState *env) | |
2170 | { | |
2171 | return false; | |
2172 | } | |
f3ee5160 RDC |
2173 | |
2174 | static inline bool arm_is_el2_enabled(CPUARMState *env) | |
2175 | { | |
2176 | return false; | |
2177 | } | |
19e0fefa FA |
2178 | #endif |
2179 | ||
f7778444 RH |
2180 | /** |
2181 | * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. | |
2182 | * E.g. when in secure state, fields in HCR_EL2 are suppressed, | |
2183 | * "for all purposes other than a direct read or write access of HCR_EL2." | |
2184 | * Not included here is HCR_RW. | |
2185 | */ | |
2186 | uint64_t arm_hcr_el2_eff(CPUARMState *env); | |
2187 | ||
1f79ee32 PM |
2188 | /* Return true if the specified exception level is running in AArch64 state. */ |
2189 | static inline bool arm_el_is_aa64(CPUARMState *env, int el) | |
2190 | { | |
446c81ab PM |
2191 | /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want, |
2192 | * and if we're not in EL0 then the state of EL0 isn't well defined.) | |
1f79ee32 | 2193 | */ |
446c81ab PM |
2194 | assert(el >= 1 && el <= 3); |
2195 | bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64); | |
592125f8 | 2196 | |
446c81ab PM |
2197 | /* The highest exception level is always at the maximum supported |
2198 | * register width, and then lower levels have a register width controlled | |
2199 | * by bits in the SCR or HCR registers. | |
1f79ee32 | 2200 | */ |
446c81ab PM |
2201 | if (el == 3) { |
2202 | return aa64; | |
2203 | } | |
2204 | ||
2205 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
2206 | aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW); | |
2207 | } | |
2208 | ||
2209 | if (el == 2) { | |
2210 | return aa64; | |
2211 | } | |
2212 | ||
e6ef0169 | 2213 | if (arm_is_el2_enabled(env)) { |
446c81ab PM |
2214 | aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW); |
2215 | } | |
2216 | ||
2217 | return aa64; | |
1f79ee32 PM |
2218 | } |
2219 | ||
3f342b9e SF |
2220 | /* Function for determing whether guest cp register reads and writes should |
2221 | * access the secure or non-secure bank of a cp register. When EL3 is | |
2222 | * operating in AArch32 state, the NS-bit determines whether the secure | |
2223 | * instance of a cp register should be used. When EL3 is AArch64 (or if | |
2224 | * it doesn't exist at all) then there is no register banking, and all | |
2225 | * accesses are to the non-secure version. | |
2226 | */ | |
2227 | static inline bool access_secure_reg(CPUARMState *env) | |
2228 | { | |
2229 | bool ret = (arm_feature(env, ARM_FEATURE_EL3) && | |
2230 | !arm_el_is_aa64(env, 3) && | |
2231 | !(env->cp15.scr_el3 & SCR_NS)); | |
2232 | ||
2233 | return ret; | |
2234 | } | |
2235 | ||
ea30a4b8 FA |
2236 | /* Macros for accessing a specified CP register bank */ |
2237 | #define A32_BANKED_REG_GET(_env, _regname, _secure) \ | |
2238 | ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) | |
2239 | ||
2240 | #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ | |
2241 | do { \ | |
2242 | if (_secure) { \ | |
2243 | (_env)->cp15._regname##_s = (_val); \ | |
2244 | } else { \ | |
2245 | (_env)->cp15._regname##_ns = (_val); \ | |
2246 | } \ | |
2247 | } while (0) | |
2248 | ||
2249 | /* Macros for automatically accessing a specific CP register bank depending on | |
2250 | * the current secure state of the system. These macros are not intended for | |
2251 | * supporting instruction translation reads/writes as these are dependent | |
2252 | * solely on the SCR.NS bit and not the mode. | |
2253 | */ | |
2254 | #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ | |
2255 | A32_BANKED_REG_GET((_env), _regname, \ | |
2cde031f | 2256 | (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3))) |
ea30a4b8 FA |
2257 | |
2258 | #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ | |
2259 | A32_BANKED_REG_SET((_env), _regname, \ | |
2cde031f | 2260 | (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \ |
ea30a4b8 FA |
2261 | (_val)) |
2262 | ||
0442428a | 2263 | void arm_cpu_list(void); |
012a906b GB |
2264 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
2265 | uint32_t cur_el, bool secure); | |
40f137e1 | 2266 | |
9ee6e8bb | 2267 | /* Interface between CPU and Interrupt controller. */ |
7ecdaa4a PM |
2268 | #ifndef CONFIG_USER_ONLY |
2269 | bool armv7m_nvic_can_take_pending_exception(void *opaque); | |
2270 | #else | |
2271 | static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) | |
2272 | { | |
2273 | return true; | |
2274 | } | |
2275 | #endif | |
2fb50a33 PM |
2276 | /** |
2277 | * armv7m_nvic_set_pending: mark the specified exception as pending | |
2278 | * @opaque: the NVIC | |
2279 | * @irq: the exception number to mark pending | |
2280 | * @secure: false for non-banked exceptions or for the nonsecure | |
2281 | * version of a banked exception, true for the secure version of a banked | |
2282 | * exception. | |
2283 | * | |
2284 | * Marks the specified exception as pending. Note that we will assert() | |
2285 | * if @secure is true and @irq does not specify one of the fixed set | |
2286 | * of architecturally banked exceptions. | |
2287 | */ | |
2288 | void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); | |
5ede82b8 PM |
2289 | /** |
2290 | * armv7m_nvic_set_pending_derived: mark this derived exception as pending | |
2291 | * @opaque: the NVIC | |
2292 | * @irq: the exception number to mark pending | |
2293 | * @secure: false for non-banked exceptions or for the nonsecure | |
2294 | * version of a banked exception, true for the secure version of a banked | |
2295 | * exception. | |
2296 | * | |
2297 | * Similar to armv7m_nvic_set_pending(), but specifically for derived | |
2298 | * exceptions (exceptions generated in the course of trying to take | |
2299 | * a different exception). | |
2300 | */ | |
2301 | void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); | |
a99ba8ab PM |
2302 | /** |
2303 | * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | |
2304 | * @opaque: the NVIC | |
2305 | * @irq: the exception number to mark pending | |
2306 | * @secure: false for non-banked exceptions or for the nonsecure | |
2307 | * version of a banked exception, true for the secure version of a banked | |
2308 | * exception. | |
2309 | * | |
2310 | * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | |
2311 | * generated in the course of lazy stacking of FP registers. | |
2312 | */ | |
2313 | void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); | |
6c948518 PM |
2314 | /** |
2315 | * armv7m_nvic_get_pending_irq_info: return highest priority pending | |
2316 | * exception, and whether it targets Secure state | |
2317 | * @opaque: the NVIC | |
2318 | * @pirq: set to pending exception number | |
2319 | * @ptargets_secure: set to whether pending exception targets Secure | |
2320 | * | |
2321 | * This function writes the number of the highest priority pending | |
2322 | * exception (the one which would be made active by | |
2323 | * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure | |
2324 | * to true if the current highest priority pending exception should | |
2325 | * be taken to Secure state, false for NS. | |
2326 | */ | |
2327 | void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, | |
2328 | bool *ptargets_secure); | |
5cb18069 PM |
2329 | /** |
2330 | * armv7m_nvic_acknowledge_irq: make highest priority pending exception active | |
2331 | * @opaque: the NVIC | |
2332 | * | |
2333 | * Move the current highest priority pending exception from the pending | |
2334 | * state to the active state, and update v7m.exception to indicate that | |
2335 | * it is the exception currently being handled. | |
5cb18069 | 2336 | */ |
6c948518 | 2337 | void armv7m_nvic_acknowledge_irq(void *opaque); |
aa488fe3 PM |
2338 | /** |
2339 | * armv7m_nvic_complete_irq: complete specified interrupt or exception | |
2340 | * @opaque: the NVIC | |
2341 | * @irq: the exception number to complete | |
5cb18069 | 2342 | * @secure: true if this exception was secure |
aa488fe3 PM |
2343 | * |
2344 | * Returns: -1 if the irq was not active | |
2345 | * 1 if completing this irq brought us back to base (no active irqs) | |
2346 | * 0 if there is still an irq active after this one was completed | |
2347 | * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | |
2348 | */ | |
5cb18069 | 2349 | int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); |
b593c2b8 PM |
2350 | /** |
2351 | * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | |
2352 | * @opaque: the NVIC | |
2353 | * @irq: the exception number to mark pending | |
2354 | * @secure: false for non-banked exceptions or for the nonsecure | |
2355 | * version of a banked exception, true for the secure version of a banked | |
2356 | * exception. | |
2357 | * | |
2358 | * Return whether an exception is "ready", i.e. whether the exception is | |
2359 | * enabled and is configured at a priority which would allow it to | |
2360 | * interrupt the current execution priority. This controls whether the | |
2361 | * RDY bit for it in the FPCCR is set. | |
2362 | */ | |
2363 | bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); | |
42a6686b PM |
2364 | /** |
2365 | * armv7m_nvic_raw_execution_priority: return the raw execution priority | |
2366 | * @opaque: the NVIC | |
2367 | * | |
2368 | * Returns: the raw execution priority as defined by the v8M architecture. | |
2369 | * This is the execution priority minus the effects of AIRCR.PRIS, | |
2370 | * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | |
2371 | * (v8M ARM ARM I_PKLD.) | |
2372 | */ | |
2373 | int armv7m_nvic_raw_execution_priority(void *opaque); | |
5d479199 PM |
2374 | /** |
2375 | * armv7m_nvic_neg_prio_requested: return true if the requested execution | |
2376 | * priority is negative for the specified security state. | |
2377 | * @opaque: the NVIC | |
2378 | * @secure: the security state to test | |
2379 | * This corresponds to the pseudocode IsReqExecPriNeg(). | |
2380 | */ | |
2381 | #ifndef CONFIG_USER_ONLY | |
2382 | bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); | |
2383 | #else | |
2384 | static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | |
2385 | { | |
2386 | return false; | |
2387 | } | |
2388 | #endif | |
9ee6e8bb | 2389 | |
4b6a83fb PM |
2390 | /* Interface for defining coprocessor registers. |
2391 | * Registers are defined in tables of arm_cp_reginfo structs | |
2392 | * which are passed to define_arm_cp_regs(). | |
2393 | */ | |
2394 | ||
2395 | /* When looking up a coprocessor register we look for it | |
2396 | * via an integer which encodes all of: | |
2397 | * coprocessor number | |
2398 | * Crn, Crm, opc1, opc2 fields | |
2399 | * 32 or 64 bit register (ie is it accessed via MRC/MCR | |
2400 | * or via MRRC/MCRR?) | |
51a79b03 | 2401 | * non-secure/secure bank (AArch32 only) |
4b6a83fb PM |
2402 | * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. |
2403 | * (In this case crn and opc2 should be zero.) | |
f5a0a5a5 PM |
2404 | * For AArch64, there is no 32/64 bit size distinction; |
2405 | * instead all registers have a 2 bit op0, 3 bit op1 and op2, | |
2406 | * and 4 bit CRn and CRm. The encoding patterns are chosen | |
2407 | * to be easy to convert to and from the KVM encodings, and also | |
2408 | * so that the hashtable can contain both AArch32 and AArch64 | |
2409 | * registers (to allow for interprocessing where we might run | |
2410 | * 32 bit code on a 64 bit core). | |
4b6a83fb | 2411 | */ |
f5a0a5a5 PM |
2412 | /* This bit is private to our hashtable cpreg; in KVM register |
2413 | * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 | |
2414 | * in the upper bits of the 64 bit ID. | |
2415 | */ | |
2416 | #define CP_REG_AA64_SHIFT 28 | |
2417 | #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) | |
2418 | ||
51a79b03 PM |
2419 | /* To enable banking of coprocessor registers depending on ns-bit we |
2420 | * add a bit to distinguish between secure and non-secure cpregs in the | |
2421 | * hashtable. | |
2422 | */ | |
2423 | #define CP_REG_NS_SHIFT 29 | |
2424 | #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) | |
2425 | ||
2426 | #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ | |
2427 | ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ | |
2428 | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) | |
4b6a83fb | 2429 | |
f5a0a5a5 PM |
2430 | #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ |
2431 | (CP_REG_AA64_MASK | \ | |
2432 | ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ | |
2433 | ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ | |
2434 | ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ | |
2435 | ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ | |
2436 | ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ | |
2437 | ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) | |
2438 | ||
721fae12 PM |
2439 | /* Convert a full 64 bit KVM register ID to the truncated 32 bit |
2440 | * version used as a key for the coprocessor register hashtable | |
2441 | */ | |
2442 | static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) | |
2443 | { | |
2444 | uint32_t cpregid = kvmid; | |
f5a0a5a5 PM |
2445 | if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { |
2446 | cpregid |= CP_REG_AA64_MASK; | |
51a79b03 PM |
2447 | } else { |
2448 | if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { | |
2449 | cpregid |= (1 << 15); | |
2450 | } | |
2451 | ||
2452 | /* KVM is always non-secure so add the NS flag on AArch32 register | |
2453 | * entries. | |
2454 | */ | |
2455 | cpregid |= 1 << CP_REG_NS_SHIFT; | |
721fae12 PM |
2456 | } |
2457 | return cpregid; | |
2458 | } | |
2459 | ||
2460 | /* Convert a truncated 32 bit hashtable key into the full | |
2461 | * 64 bit KVM register ID. | |
2462 | */ | |
2463 | static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | |
2464 | { | |
f5a0a5a5 PM |
2465 | uint64_t kvmid; |
2466 | ||
2467 | if (cpregid & CP_REG_AA64_MASK) { | |
2468 | kvmid = cpregid & ~CP_REG_AA64_MASK; | |
2469 | kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; | |
721fae12 | 2470 | } else { |
f5a0a5a5 PM |
2471 | kvmid = cpregid & ~(1 << 15); |
2472 | if (cpregid & (1 << 15)) { | |
2473 | kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; | |
2474 | } else { | |
2475 | kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; | |
2476 | } | |
721fae12 PM |
2477 | } |
2478 | return kvmid; | |
2479 | } | |
2480 | ||
4b6a83fb | 2481 | /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a |
fe03d45f | 2482 | * special-behaviour cp reg and bits [11..8] indicate what behaviour |
4b6a83fb PM |
2483 | * it has. Otherwise it is a simple cp reg, where CONST indicates that |
2484 | * TCG can assume the value to be constant (ie load at translate time) | |
2485 | * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END | |
2486 | * indicates that the TB should not be ended after a write to this register | |
2487 | * (the default is that the TB ends after cp writes). OVERRIDE permits | |
2488 | * a register definition to override a previous definition for the | |
2489 | * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the | |
2490 | * old must have the OVERRIDE bit set. | |
7a0e58fa PM |
2491 | * ALIAS indicates that this register is an alias view of some underlying |
2492 | * state which is also visible via another register, and that the other | |
b061a82b SF |
2493 | * register is handling migration and reset; registers marked ALIAS will not be |
2494 | * migrated but may have their state set by syncing of register state from KVM. | |
7a0e58fa PM |
2495 | * NO_RAW indicates that this register has no underlying state and does not |
2496 | * support raw access for state saving/loading; it will not be used for either | |
2497 | * migration or KVM state synchronization. (Typically this is for "registers" | |
2498 | * which are actually used as instructions for cache maintenance and so on.) | |
2452731c | 2499 | * IO indicates that this register does I/O and therefore its accesses |
55c812b7 | 2500 | * need to be marked with gen_io_start() and also end the TB. In particular, |
2452731c | 2501 | * registers which implement clocks or timers require this. |
37ff584c PM |
2502 | * RAISES_EXC is for when the read or write hook might raise an exception; |
2503 | * the generated code will synchronize the CPU state before calling the hook | |
2504 | * so that it is safe for the hook to call raise_exception(). | |
f80741d1 AB |
2505 | * NEWEL is for writes to registers that might change the exception |
2506 | * level - typically on older ARM chips. For those cases we need to | |
2507 | * re-read the new el when recomputing the translation flags. | |
4b6a83fb | 2508 | */ |
fe03d45f RH |
2509 | #define ARM_CP_SPECIAL 0x0001 |
2510 | #define ARM_CP_CONST 0x0002 | |
2511 | #define ARM_CP_64BIT 0x0004 | |
2512 | #define ARM_CP_SUPPRESS_TB_END 0x0008 | |
2513 | #define ARM_CP_OVERRIDE 0x0010 | |
2514 | #define ARM_CP_ALIAS 0x0020 | |
2515 | #define ARM_CP_IO 0x0040 | |
2516 | #define ARM_CP_NO_RAW 0x0080 | |
2517 | #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) | |
2518 | #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) | |
2519 | #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) | |
2520 | #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) | |
2521 | #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) | |
eb821168 RH |
2522 | #define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) |
2523 | #define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) | |
2524 | #define ARM_LAST_SPECIAL ARM_CP_DC_GZVA | |
fe03d45f | 2525 | #define ARM_CP_FPU 0x1000 |
490aa7f1 | 2526 | #define ARM_CP_SVE 0x2000 |
1f163787 | 2527 | #define ARM_CP_NO_GDB 0x4000 |
37ff584c | 2528 | #define ARM_CP_RAISES_EXC 0x8000 |
f80741d1 | 2529 | #define ARM_CP_NEWEL 0x10000 |
4b6a83fb | 2530 | /* Used only as a terminator for ARMCPRegInfo lists */ |
f80741d1 | 2531 | #define ARM_CP_SENTINEL 0xfffff |
4b6a83fb | 2532 | /* Mask of only the flag bits in a type field */ |
f80741d1 | 2533 | #define ARM_CP_FLAG_MASK 0x1f0ff |
4b6a83fb | 2534 | |
f5a0a5a5 PM |
2535 | /* Valid values for ARMCPRegInfo state field, indicating which of |
2536 | * the AArch32 and AArch64 execution states this register is visible in. | |
2537 | * If the reginfo doesn't explicitly specify then it is AArch32 only. | |
2538 | * If the reginfo is declared to be visible in both states then a second | |
2539 | * reginfo is synthesised for the AArch32 view of the AArch64 register, | |
2540 | * such that the AArch32 view is the lower 32 bits of the AArch64 one. | |
2541 | * Note that we rely on the values of these enums as we iterate through | |
2542 | * the various states in some places. | |
2543 | */ | |
2544 | enum { | |
2545 | ARM_CP_STATE_AA32 = 0, | |
2546 | ARM_CP_STATE_AA64 = 1, | |
2547 | ARM_CP_STATE_BOTH = 2, | |
2548 | }; | |
2549 | ||
c3e30260 FA |
2550 | /* ARM CP register secure state flags. These flags identify security state |
2551 | * attributes for a given CP register entry. | |
2552 | * The existence of both or neither secure and non-secure flags indicates that | |
2553 | * the register has both a secure and non-secure hash entry. A single one of | |
2554 | * these flags causes the register to only be hashed for the specified | |
2555 | * security state. | |
2556 | * Although definitions may have any combination of the S/NS bits, each | |
2557 | * registered entry will only have one to identify whether the entry is secure | |
2558 | * or non-secure. | |
2559 | */ | |
2560 | enum { | |
2561 | ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ | |
2562 | ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ | |
2563 | }; | |
2564 | ||
4b6a83fb PM |
2565 | /* Return true if cptype is a valid type field. This is used to try to |
2566 | * catch errors where the sentinel has been accidentally left off the end | |
2567 | * of a list of registers. | |
2568 | */ | |
2569 | static inline bool cptype_valid(int cptype) | |
2570 | { | |
2571 | return ((cptype & ~ARM_CP_FLAG_MASK) == 0) | |
2572 | || ((cptype & ARM_CP_SPECIAL) && | |
34affeef | 2573 | ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); |
4b6a83fb PM |
2574 | } |
2575 | ||
2576 | /* Access rights: | |
2577 | * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM | |
2578 | * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and | |
2579 | * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 | |
2580 | * (ie any of the privileged modes in Secure state, or Monitor mode). | |
2581 | * If a register is accessible in one privilege level it's always accessible | |
2582 | * in higher privilege levels too. Since "Secure PL1" also follows this rule | |
2583 | * (ie anything visible in PL2 is visible in S-PL1, some things are only | |
2584 | * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the | |
2585 | * terminology a little and call this PL3. | |
f5a0a5a5 PM |
2586 | * In AArch64 things are somewhat simpler as the PLx bits line up exactly |
2587 | * with the ELx exception levels. | |
4b6a83fb PM |
2588 | * |
2589 | * If access permissions for a register are more complex than can be | |
2590 | * described with these bits, then use a laxer set of restrictions, and | |
2591 | * do the more restrictive/complex check inside a helper function. | |
2592 | */ | |
2593 | #define PL3_R 0x80 | |
2594 | #define PL3_W 0x40 | |
2595 | #define PL2_R (0x20 | PL3_R) | |
2596 | #define PL2_W (0x10 | PL3_W) | |
2597 | #define PL1_R (0x08 | PL2_R) | |
2598 | #define PL1_W (0x04 | PL2_W) | |
2599 | #define PL0_R (0x02 | PL1_R) | |
2600 | #define PL0_W (0x01 | PL1_W) | |
2601 | ||
b5bd7440 AB |
2602 | /* |
2603 | * For user-mode some registers are accessible to EL0 via a kernel | |
2604 | * trap-and-emulate ABI. In this case we define the read permissions | |
2605 | * as actually being PL0_R. However some bits of any given register | |
2606 | * may still be masked. | |
2607 | */ | |
2608 | #ifdef CONFIG_USER_ONLY | |
2609 | #define PL0U_R PL0_R | |
2610 | #else | |
2611 | #define PL0U_R PL1_R | |
2612 | #endif | |
2613 | ||
4b6a83fb PM |
2614 | #define PL3_RW (PL3_R | PL3_W) |
2615 | #define PL2_RW (PL2_R | PL2_W) | |
2616 | #define PL1_RW (PL1_R | PL1_W) | |
2617 | #define PL0_RW (PL0_R | PL0_W) | |
2618 | ||
75502672 PM |
2619 | /* Return the highest implemented Exception Level */ |
2620 | static inline int arm_highest_el(CPUARMState *env) | |
2621 | { | |
2622 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
2623 | return 3; | |
2624 | } | |
2625 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
2626 | return 2; | |
2627 | } | |
2628 | return 1; | |
2629 | } | |
2630 | ||
15b3f556 PM |
2631 | /* Return true if a v7M CPU is in Handler mode */ |
2632 | static inline bool arm_v7m_is_handler_mode(CPUARMState *env) | |
2633 | { | |
2634 | return env->v7m.exception != 0; | |
2635 | } | |
2636 | ||
dcbff19b GB |
2637 | /* Return the current Exception Level (as per ARMv8; note that this differs |
2638 | * from the ARMv7 Privilege Level). | |
2639 | */ | |
2640 | static inline int arm_current_el(CPUARMState *env) | |
4b6a83fb | 2641 | { |
6d54ed3c | 2642 | if (arm_feature(env, ARM_FEATURE_M)) { |
8bfc26ea PM |
2643 | return arm_v7m_is_handler_mode(env) || |
2644 | !(env->v7m.control[env->v7m.secure] & 1); | |
6d54ed3c PM |
2645 | } |
2646 | ||
592125f8 | 2647 | if (is_a64(env)) { |
f5a0a5a5 PM |
2648 | return extract32(env->pstate, 2, 2); |
2649 | } | |
2650 | ||
592125f8 FA |
2651 | switch (env->uncached_cpsr & 0x1f) { |
2652 | case ARM_CPU_MODE_USR: | |
4b6a83fb | 2653 | return 0; |
592125f8 FA |
2654 | case ARM_CPU_MODE_HYP: |
2655 | return 2; | |
2656 | case ARM_CPU_MODE_MON: | |
2657 | return 3; | |
2658 | default: | |
2659 | if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { | |
2660 | /* If EL3 is 32-bit then all secure privileged modes run in | |
2661 | * EL3 | |
2662 | */ | |
2663 | return 3; | |
2664 | } | |
2665 | ||
2666 | return 1; | |
4b6a83fb | 2667 | } |
4b6a83fb PM |
2668 | } |
2669 | ||
2670 | typedef struct ARMCPRegInfo ARMCPRegInfo; | |
2671 | ||
f59df3f2 PM |
2672 | typedef enum CPAccessResult { |
2673 | /* Access is permitted */ | |
2674 | CP_ACCESS_OK = 0, | |
2675 | /* Access fails due to a configurable trap or enable which would | |
2676 | * result in a categorized exception syndrome giving information about | |
2677 | * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, | |
38836a2c PM |
2678 | * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or |
2679 | * PL1 if in EL0, otherwise to the current EL). | |
f59df3f2 PM |
2680 | */ |
2681 | CP_ACCESS_TRAP = 1, | |
2682 | /* Access fails and results in an exception syndrome 0x0 ("uncategorized"). | |
2683 | * Note that this is not a catch-all case -- the set of cases which may | |
2684 | * result in this failure is specifically defined by the architecture. | |
2685 | */ | |
2686 | CP_ACCESS_TRAP_UNCATEGORIZED = 2, | |
38836a2c PM |
2687 | /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ |
2688 | CP_ACCESS_TRAP_EL2 = 3, | |
2689 | CP_ACCESS_TRAP_EL3 = 4, | |
e7615726 PM |
2690 | /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ |
2691 | CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, | |
2692 | CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, | |
f2cae609 PM |
2693 | /* Access fails and results in an exception syndrome for an FP access, |
2694 | * trapped directly to EL2 or EL3 | |
2695 | */ | |
2696 | CP_ACCESS_TRAP_FP_EL2 = 7, | |
2697 | CP_ACCESS_TRAP_FP_EL3 = 8, | |
f59df3f2 PM |
2698 | } CPAccessResult; |
2699 | ||
c4241c7d PM |
2700 | /* Access functions for coprocessor registers. These cannot fail and |
2701 | * may not raise exceptions. | |
2702 | */ | |
2703 | typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); | |
2704 | typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, | |
2705 | uint64_t value); | |
f59df3f2 | 2706 | /* Access permission check functions for coprocessor registers. */ |
3f208fd7 PM |
2707 | typedef CPAccessResult CPAccessFn(CPUARMState *env, |
2708 | const ARMCPRegInfo *opaque, | |
2709 | bool isread); | |
4b6a83fb PM |
2710 | /* Hook function for register reset */ |
2711 | typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); | |
2712 | ||
2713 | #define CP_ANY 0xff | |
2714 | ||
2715 | /* Definition of an ARM coprocessor register */ | |
2716 | struct ARMCPRegInfo { | |
2717 | /* Name of register (useful mainly for debugging, need not be unique) */ | |
2718 | const char *name; | |
2719 | /* Location of register: coprocessor number and (crn,crm,opc1,opc2) | |
2720 | * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a | |
2721 | * 'wildcard' field -- any value of that field in the MRC/MCR insn | |
2722 | * will be decoded to this register. The register read and write | |
2723 | * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 | |
2724 | * used by the program, so it is possible to register a wildcard and | |
2725 | * then behave differently on read/write if necessary. | |
2726 | * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 | |
2727 | * must both be zero. | |
f5a0a5a5 PM |
2728 | * For AArch64-visible registers, opc0 is also used. |
2729 | * Since there are no "coprocessors" in AArch64, cp is purely used as a | |
2730 | * way to distinguish (for KVM's benefit) guest-visible system registers | |
2731 | * from demuxed ones provided to preserve the "no side effects on | |
2732 | * KVM register read/write from QEMU" semantics. cp==0x13 is guest | |
2733 | * visible (to match KVM's encoding); cp==0 will be converted to | |
2734 | * cp==0x13 when the ARMCPRegInfo is registered, for convenience. | |
4b6a83fb PM |
2735 | */ |
2736 | uint8_t cp; | |
2737 | uint8_t crn; | |
2738 | uint8_t crm; | |
f5a0a5a5 | 2739 | uint8_t opc0; |
4b6a83fb PM |
2740 | uint8_t opc1; |
2741 | uint8_t opc2; | |
f5a0a5a5 PM |
2742 | /* Execution state in which this register is visible: ARM_CP_STATE_* */ |
2743 | int state; | |
4b6a83fb PM |
2744 | /* Register type: ARM_CP_* bits/values */ |
2745 | int type; | |
2746 | /* Access rights: PL*_[RW] */ | |
2747 | int access; | |
c3e30260 FA |
2748 | /* Security state: ARM_CP_SECSTATE_* bits/values */ |
2749 | int secure; | |
4b6a83fb PM |
2750 | /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when |
2751 | * this register was defined: can be used to hand data through to the | |
2752 | * register read/write functions, since they are passed the ARMCPRegInfo*. | |
2753 | */ | |
2754 | void *opaque; | |
2755 | /* Value of this register, if it is ARM_CP_CONST. Otherwise, if | |
2756 | * fieldoffset is non-zero, the reset value of the register. | |
2757 | */ | |
2758 | uint64_t resetvalue; | |
c3e30260 FA |
2759 | /* Offset of the field in CPUARMState for this register. |
2760 | * | |
2761 | * This is not needed if either: | |
4b6a83fb PM |
2762 | * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs |
2763 | * 2. both readfn and writefn are specified | |
2764 | */ | |
2765 | ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ | |
c3e30260 FA |
2766 | |
2767 | /* Offsets of the secure and non-secure fields in CPUARMState for the | |
2768 | * register if it is banked. These fields are only used during the static | |
2769 | * registration of a register. During hashing the bank associated | |
2770 | * with a given security state is copied to fieldoffset which is used from | |
2771 | * there on out. | |
2772 | * | |
2773 | * It is expected that register definitions use either fieldoffset or | |
2774 | * bank_fieldoffsets in the definition but not both. It is also expected | |
2775 | * that both bank offsets are set when defining a banked register. This | |
2776 | * use indicates that a register is banked. | |
2777 | */ | |
2778 | ptrdiff_t bank_fieldoffsets[2]; | |
2779 | ||
f59df3f2 PM |
2780 | /* Function for making any access checks for this register in addition to |
2781 | * those specified by the 'access' permissions bits. If NULL, no extra | |
2782 | * checks required. The access check is performed at runtime, not at | |
2783 | * translate time. | |
2784 | */ | |
2785 | CPAccessFn *accessfn; | |
4b6a83fb PM |
2786 | /* Function for handling reads of this register. If NULL, then reads |
2787 | * will be done by loading from the offset into CPUARMState specified | |
2788 | * by fieldoffset. | |
2789 | */ | |
2790 | CPReadFn *readfn; | |
2791 | /* Function for handling writes of this register. If NULL, then writes | |
2792 | * will be done by writing to the offset into CPUARMState specified | |
2793 | * by fieldoffset. | |
2794 | */ | |
2795 | CPWriteFn *writefn; | |
7023ec7e PM |
2796 | /* Function for doing a "raw" read; used when we need to copy |
2797 | * coprocessor state to the kernel for KVM or out for | |
2798 | * migration. This only needs to be provided if there is also a | |
c4241c7d | 2799 | * readfn and it has side effects (for instance clear-on-read bits). |
7023ec7e PM |
2800 | */ |
2801 | CPReadFn *raw_readfn; | |
2802 | /* Function for doing a "raw" write; used when we need to copy KVM | |
2803 | * kernel coprocessor state into userspace, or for inbound | |
2804 | * migration. This only needs to be provided if there is also a | |
c4241c7d PM |
2805 | * writefn and it masks out "unwritable" bits or has write-one-to-clear |
2806 | * or similar behaviour. | |
7023ec7e PM |
2807 | */ |
2808 | CPWriteFn *raw_writefn; | |
4b6a83fb PM |
2809 | /* Function for resetting the register. If NULL, then reset will be done |
2810 | * by writing resetvalue to the field specified in fieldoffset. If | |
2811 | * fieldoffset is 0 then no reset will be done. | |
2812 | */ | |
2813 | CPResetFn *resetfn; | |
e2cce18f RH |
2814 | |
2815 | /* | |
2816 | * "Original" writefn and readfn. | |
2817 | * For ARMv8.1-VHE register aliases, we overwrite the read/write | |
2818 | * accessor functions of various EL1/EL0 to perform the runtime | |
2819 | * check for which sysreg should actually be modified, and then | |
2820 | * forwards the operation. Before overwriting the accessors, | |
2821 | * the original function is copied here, so that accesses that | |
2822 | * really do go to the EL1/EL0 version proceed normally. | |
2823 | * (The corresponding EL2 register is linked via opaque.) | |
2824 | */ | |
2825 | CPReadFn *orig_readfn; | |
2826 | CPWriteFn *orig_writefn; | |
4b6a83fb PM |
2827 | }; |
2828 | ||
2829 | /* Macros which are lvalues for the field in CPUARMState for the | |
2830 | * ARMCPRegInfo *ri. | |
2831 | */ | |
2832 | #define CPREG_FIELD32(env, ri) \ | |
2833 | (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) | |
2834 | #define CPREG_FIELD64(env, ri) \ | |
2835 | (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) | |
2836 | ||
2837 | #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL } | |
2838 | ||
2839 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
2840 | const ARMCPRegInfo *regs, void *opaque); | |
2841 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, | |
2842 | const ARMCPRegInfo *regs, void *opaque); | |
2843 | static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) | |
2844 | { | |
2845 | define_arm_cp_regs_with_opaque(cpu, regs, 0); | |
2846 | } | |
2847 | static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) | |
2848 | { | |
2849 | define_one_arm_cp_reg_with_opaque(cpu, regs, 0); | |
2850 | } | |
60322b39 | 2851 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); |
4b6a83fb | 2852 | |
6c5c0fec AB |
2853 | /* |
2854 | * Definition of an ARM co-processor register as viewed from | |
2855 | * userspace. This is used for presenting sanitised versions of | |
2856 | * registers to userspace when emulating the Linux AArch64 CPU | |
2857 | * ID/feature ABI (advertised as HWCAP_CPUID). | |
2858 | */ | |
2859 | typedef struct ARMCPRegUserSpaceInfo { | |
2860 | /* Name of register */ | |
2861 | const char *name; | |
2862 | ||
d040242e AB |
2863 | /* Is the name actually a glob pattern */ |
2864 | bool is_glob; | |
2865 | ||
6c5c0fec AB |
2866 | /* Only some bits are exported to user space */ |
2867 | uint64_t exported_bits; | |
2868 | ||
2869 | /* Fixed bits are applied after the mask */ | |
2870 | uint64_t fixed_bits; | |
2871 | } ARMCPRegUserSpaceInfo; | |
2872 | ||
2873 | #define REGUSERINFO_SENTINEL { .name = NULL } | |
2874 | ||
2875 | void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); | |
2876 | ||
4b6a83fb | 2877 | /* CPWriteFn that can be used to implement writes-ignored behaviour */ |
c4241c7d PM |
2878 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
2879 | uint64_t value); | |
4b6a83fb | 2880 | /* CPReadFn that can be used for read-as-zero behaviour */ |
c4241c7d | 2881 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); |
4b6a83fb | 2882 | |
f5a0a5a5 PM |
2883 | /* CPResetFn that does nothing, for use if no reset is required even |
2884 | * if fieldoffset is non zero. | |
2885 | */ | |
2886 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); | |
2887 | ||
67ed771d PM |
2888 | /* Return true if this reginfo struct's field in the cpu state struct |
2889 | * is 64 bits wide. | |
2890 | */ | |
2891 | static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) | |
2892 | { | |
2893 | return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT); | |
2894 | } | |
2895 | ||
dcbff19b | 2896 | static inline bool cp_access_ok(int current_el, |
4b6a83fb PM |
2897 | const ARMCPRegInfo *ri, int isread) |
2898 | { | |
dcbff19b | 2899 | return (ri->access >> ((current_el * 2) + isread)) & 1; |
4b6a83fb PM |
2900 | } |
2901 | ||
49a66191 PM |
2902 | /* Raw read of a coprocessor register (as needed for migration, etc) */ |
2903 | uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); | |
2904 | ||
721fae12 PM |
2905 | /** |
2906 | * write_list_to_cpustate | |
2907 | * @cpu: ARMCPU | |
2908 | * | |
2909 | * For each register listed in the ARMCPU cpreg_indexes list, write | |
2910 | * its value from the cpreg_values list into the ARMCPUState structure. | |
2911 | * This updates TCG's working data structures from KVM data or | |
2912 | * from incoming migration state. | |
2913 | * | |
2914 | * Returns: true if all register values were updated correctly, | |
2915 | * false if some register was unknown or could not be written. | |
2916 | * Note that we do not stop early on failure -- we will attempt | |
2917 | * writing all registers in the list. | |
2918 | */ | |
2919 | bool write_list_to_cpustate(ARMCPU *cpu); | |
2920 | ||
2921 | /** | |
2922 | * write_cpustate_to_list: | |
2923 | * @cpu: ARMCPU | |
b698e4ee | 2924 | * @kvm_sync: true if this is for syncing back to KVM |
721fae12 PM |
2925 | * |
2926 | * For each register listed in the ARMCPU cpreg_indexes list, write | |
2927 | * its value from the ARMCPUState structure into the cpreg_values list. | |
2928 | * This is used to copy info from TCG's working data structures into | |
2929 | * KVM or for outbound migration. | |
2930 | * | |
b698e4ee PM |
2931 | * @kvm_sync is true if we are doing this in order to sync the |
2932 | * register state back to KVM. In this case we will only update | |
2933 | * values in the list if the previous list->cpustate sync actually | |
2934 | * successfully wrote the CPU state. Otherwise we will keep the value | |
2935 | * that is in the list. | |
2936 | * | |
721fae12 PM |
2937 | * Returns: true if all register values were read correctly, |
2938 | * false if some register was unknown or could not be read. | |
2939 | * Note that we do not stop early on failure -- we will attempt | |
2940 | * reading all registers in the list. | |
2941 | */ | |
b698e4ee | 2942 | bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); |
721fae12 | 2943 | |
9ee6e8bb PB |
2944 | #define ARM_CPUID_TI915T 0x54029152 |
2945 | #define ARM_CPUID_TI925T 0x54029252 | |
40f137e1 | 2946 | |
ba1ba5cc IM |
2947 | #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU |
2948 | #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) | |
0dacec87 | 2949 | #define CPU_RESOLVING_TYPE TYPE_ARM_CPU |
ba1ba5cc | 2950 | |
9467d44c | 2951 | #define cpu_signal_handler cpu_arm_signal_handler |
c732abe2 | 2952 | #define cpu_list arm_cpu_list |
9467d44c | 2953 | |
c1e37810 PM |
2954 | /* ARM has the following "translation regimes" (as the ARM ARM calls them): |
2955 | * | |
2956 | * If EL3 is 64-bit: | |
2957 | * + NonSecure EL1 & 0 stage 1 | |
2958 | * + NonSecure EL1 & 0 stage 2 | |
2959 | * + NonSecure EL2 | |
b9f6033c RH |
2960 | * + NonSecure EL2 & 0 (ARMv8.1-VHE) |
2961 | * + Secure EL1 & 0 | |
c1e37810 PM |
2962 | * + Secure EL3 |
2963 | * If EL3 is 32-bit: | |
2964 | * + NonSecure PL1 & 0 stage 1 | |
2965 | * + NonSecure PL1 & 0 stage 2 | |
2966 | * + NonSecure PL2 | |
b9f6033c RH |
2967 | * + Secure PL0 |
2968 | * + Secure PL1 | |
c1e37810 PM |
2969 | * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) |
2970 | * | |
2971 | * For QEMU, an mmu_idx is not quite the same as a translation regime because: | |
b9f6033c RH |
2972 | * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes, |
2973 | * because they may differ in access permissions even if the VA->PA map is | |
2974 | * the same | |
c1e37810 PM |
2975 | * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2 |
2976 | * translation, which means that we have one mmu_idx that deals with two | |
2977 | * concatenated translation regimes [this sort of combined s1+2 TLB is | |
2978 | * architecturally permitted] | |
2979 | * 3. we don't need to allocate an mmu_idx to translations that we won't be | |
2980 | * handling via the TLB. The only way to do a stage 1 translation without | |
2981 | * the immediate stage 2 translation is via the ATS or AT system insns, | |
2982 | * which can be slow-pathed and always do a page table walk. | |
bf05340c PM |
2983 | * The only use of stage 2 translations is either as part of an s1+2 |
2984 | * lookup or when loading the descriptors during a stage 1 page table walk, | |
2985 | * and in both those cases we don't use the TLB. | |
c1e37810 PM |
2986 | * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" |
2987 | * translation regimes, because they map reasonably well to each other | |
2988 | * and they can't both be active at the same time. | |
b9f6033c RH |
2989 | * 5. we want to be able to use the TLB for accesses done as part of a |
2990 | * stage1 page table walk, rather than having to walk the stage2 page | |
2991 | * table over and over. | |
452ef8cb RH |
2992 | * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access |
2993 | * Never (PAN) bit within PSTATE. | |
c1e37810 | 2994 | * |
b9f6033c RH |
2995 | * This gives us the following list of cases: |
2996 | * | |
2997 | * NS EL0 EL1&0 stage 1+2 (aka NS PL0) | |
2998 | * NS EL1 EL1&0 stage 1+2 (aka NS PL1) | |
452ef8cb | 2999 | * NS EL1 EL1&0 stage 1+2 +PAN |
b9f6033c | 3000 | * NS EL0 EL2&0 |
bf05340c | 3001 | * NS EL2 EL2&0 |
452ef8cb | 3002 | * NS EL2 EL2&0 +PAN |
c1e37810 | 3003 | * NS EL2 (aka NS PL2) |
b9f6033c RH |
3004 | * S EL0 EL1&0 (aka S PL0) |
3005 | * S EL1 EL1&0 (not used if EL3 is 32 bit) | |
452ef8cb | 3006 | * S EL1 EL1&0 +PAN |
c1e37810 | 3007 | * S EL3 (aka S PL1) |
c1e37810 | 3008 | * |
bf05340c | 3009 | * for a total of 11 different mmu_idx. |
c1e37810 | 3010 | * |
3bef7012 PM |
3011 | * R profile CPUs have an MPU, but can use the same set of MMU indexes |
3012 | * as A profile. They only need to distinguish NS EL0 and NS EL1 (and | |
3013 | * NS EL2 if we ever model a Cortex-R52). | |
3014 | * | |
3015 | * M profile CPUs are rather different as they do not have a true MMU. | |
3016 | * They have the following different MMU indexes: | |
3017 | * User | |
3018 | * Privileged | |
62593718 PM |
3019 | * User, execution priority negative (ie the MPU HFNMIENA bit may apply) |
3020 | * Privileged, execution priority negative (ditto) | |
66787c78 PM |
3021 | * If the CPU supports the v8M Security Extension then there are also: |
3022 | * Secure User | |
3023 | * Secure Privileged | |
62593718 PM |
3024 | * Secure User, execution priority negative |
3025 | * Secure Privileged, execution priority negative | |
3bef7012 | 3026 | * |
8bd5c820 PM |
3027 | * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code |
3028 | * are not quite the same -- different CPU types (most notably M profile | |
3029 | * vs A/R profile) would like to use MMU indexes with different semantics, | |
3030 | * but since we don't ever need to use all of those in a single CPU we | |
bf05340c PM |
3031 | * can avoid having to set NB_MMU_MODES to "total number of A profile MMU |
3032 | * modes + total number of M profile MMU modes". The lower bits of | |
8bd5c820 PM |
3033 | * ARMMMUIdx are the core TLB mmu index, and the higher bits are always |
3034 | * the same for any particular CPU. | |
3035 | * Variables of type ARMMUIdx are always full values, and the core | |
3036 | * index values are in variables of type 'int'. | |
3037 | * | |
c1e37810 PM |
3038 | * Our enumeration includes at the end some entries which are not "true" |
3039 | * mmu_idx values in that they don't have corresponding TLBs and are only | |
3040 | * valid for doing slow path page table walks. | |
3041 | * | |
3042 | * The constant names here are patterned after the general style of the names | |
3043 | * of the AT/ATS operations. | |
3044 | * The values used are carefully arranged to make mmu_idx => EL lookup easy. | |
62593718 PM |
3045 | * For M profile we arrange them to have a bit for priv, a bit for negpri |
3046 | * and a bit for secure. | |
c1e37810 | 3047 | */ |
b9f6033c RH |
3048 | #define ARM_MMU_IDX_A 0x10 /* A profile */ |
3049 | #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ | |
3050 | #define ARM_MMU_IDX_M 0x40 /* M profile */ | |
8bd5c820 | 3051 | |
b9f6033c RH |
3052 | /* Meanings of the bits for M profile mmu idx values */ |
3053 | #define ARM_MMU_IDX_M_PRIV 0x1 | |
62593718 | 3054 | #define ARM_MMU_IDX_M_NEGPRI 0x2 |
b9f6033c | 3055 | #define ARM_MMU_IDX_M_S 0x4 /* Secure */ |
62593718 | 3056 | |
b9f6033c RH |
3057 | #define ARM_MMU_IDX_TYPE_MASK \ |
3058 | (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) | |
3059 | #define ARM_MMU_IDX_COREIDX_MASK 0xf | |
8bd5c820 | 3060 | |
c1e37810 | 3061 | typedef enum ARMMMUIdx { |
b9f6033c RH |
3062 | /* |
3063 | * A-profile. | |
3064 | */ | |
452ef8cb RH |
3065 | ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, |
3066 | ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, | |
b9f6033c | 3067 | |
452ef8cb RH |
3068 | ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, |
3069 | ARMMMUIdx_E10_1_PAN = 3 | ARM_MMU_IDX_A, | |
b9f6033c | 3070 | |
452ef8cb RH |
3071 | ARMMMUIdx_E2 = 4 | ARM_MMU_IDX_A, |
3072 | ARMMMUIdx_E20_2 = 5 | ARM_MMU_IDX_A, | |
3073 | ARMMMUIdx_E20_2_PAN = 6 | ARM_MMU_IDX_A, | |
b9f6033c | 3074 | |
452ef8cb RH |
3075 | ARMMMUIdx_SE10_0 = 7 | ARM_MMU_IDX_A, |
3076 | ARMMMUIdx_SE10_1 = 8 | ARM_MMU_IDX_A, | |
3077 | ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A, | |
3078 | ARMMMUIdx_SE3 = 10 | ARM_MMU_IDX_A, | |
b9f6033c | 3079 | |
b9f6033c RH |
3080 | /* |
3081 | * These are not allocated TLBs and are used only for AT system | |
3082 | * instructions or for the first stage of an S12 page table walk. | |
3083 | */ | |
3084 | ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, | |
3085 | ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, | |
452ef8cb | 3086 | ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, |
bf05340c PM |
3087 | /* |
3088 | * Not allocated a TLB: used only for second stage of an S12 page | |
3089 | * table walk, or for descriptor loads during first stage of an S1 | |
3090 | * page table walk. Note that if we ever want to have a TLB for this | |
3091 | * then various TLB flush insns which currently are no-ops or flush | |
3092 | * only stage 1 MMU indexes will need to change to flush stage 2. | |
3093 | */ | |
3094 | ARMMMUIdx_Stage2 = 3 | ARM_MMU_IDX_NOTLB, | |
b9f6033c RH |
3095 | |
3096 | /* | |
3097 | * M-profile. | |
3098 | */ | |
25568316 RH |
3099 | ARMMMUIdx_MUser = ARM_MMU_IDX_M, |
3100 | ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, | |
3101 | ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, | |
3102 | ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, | |
3103 | ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, | |
3104 | ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, | |
3105 | ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, | |
3106 | ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, | |
c1e37810 PM |
3107 | } ARMMMUIdx; |
3108 | ||
5f09a6df RH |
3109 | /* |
3110 | * Bit macros for the core-mmu-index values for each index, | |
8bd5c820 PM |
3111 | * for use when calling tlb_flush_by_mmuidx() and friends. |
3112 | */ | |
5f09a6df RH |
3113 | #define TO_CORE_BIT(NAME) \ |
3114 | ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK) | |
3115 | ||
8bd5c820 | 3116 | typedef enum ARMMMUIdxBit { |
5f09a6df | 3117 | TO_CORE_BIT(E10_0), |
b9f6033c | 3118 | TO_CORE_BIT(E20_0), |
5f09a6df | 3119 | TO_CORE_BIT(E10_1), |
452ef8cb | 3120 | TO_CORE_BIT(E10_1_PAN), |
5f09a6df | 3121 | TO_CORE_BIT(E2), |
b9f6033c | 3122 | TO_CORE_BIT(E20_2), |
452ef8cb | 3123 | TO_CORE_BIT(E20_2_PAN), |
5f09a6df RH |
3124 | TO_CORE_BIT(SE10_0), |
3125 | TO_CORE_BIT(SE10_1), | |
452ef8cb | 3126 | TO_CORE_BIT(SE10_1_PAN), |
5f09a6df | 3127 | TO_CORE_BIT(SE3), |
5f09a6df RH |
3128 | |
3129 | TO_CORE_BIT(MUser), | |
3130 | TO_CORE_BIT(MPriv), | |
3131 | TO_CORE_BIT(MUserNegPri), | |
3132 | TO_CORE_BIT(MPrivNegPri), | |
3133 | TO_CORE_BIT(MSUser), | |
3134 | TO_CORE_BIT(MSPriv), | |
3135 | TO_CORE_BIT(MSUserNegPri), | |
3136 | TO_CORE_BIT(MSPrivNegPri), | |
8bd5c820 PM |
3137 | } ARMMMUIdxBit; |
3138 | ||
5f09a6df RH |
3139 | #undef TO_CORE_BIT |
3140 | ||
f79fbf39 | 3141 | #define MMU_USER_IDX 0 |
c1e37810 | 3142 | |
9e273ef2 PM |
3143 | /* Indexes used when registering address spaces with cpu_address_space_init */ |
3144 | typedef enum ARMASIdx { | |
3145 | ARMASIdx_NS = 0, | |
3146 | ARMASIdx_S = 1, | |
8bce44a2 RH |
3147 | ARMASIdx_TagNS = 2, |
3148 | ARMASIdx_TagS = 3, | |
9e273ef2 PM |
3149 | } ARMASIdx; |
3150 | ||
533e93f1 | 3151 | /* Return the Exception Level targeted by debug exceptions. */ |
3a298203 PM |
3152 | static inline int arm_debug_target_el(CPUARMState *env) |
3153 | { | |
81669b8b SF |
3154 | bool secure = arm_is_secure(env); |
3155 | bool route_to_el2 = false; | |
3156 | ||
e6ef0169 | 3157 | if (arm_is_el2_enabled(env)) { |
81669b8b | 3158 | route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || |
b281ba42 | 3159 | env->cp15.mdcr_el2 & MDCR_TDE; |
81669b8b SF |
3160 | } |
3161 | ||
3162 | if (route_to_el2) { | |
3163 | return 2; | |
3164 | } else if (arm_feature(env, ARM_FEATURE_EL3) && | |
3165 | !arm_el_is_aa64(env, 3) && secure) { | |
3166 | return 3; | |
3167 | } else { | |
3168 | return 1; | |
3169 | } | |
3a298203 PM |
3170 | } |
3171 | ||
43bbce7f PM |
3172 | static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) |
3173 | { | |
3174 | /* If all the CLIDR.Ctypem bits are 0 there are no caches, and | |
3175 | * CSSELR is RAZ/WI. | |
3176 | */ | |
3177 | return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; | |
3178 | } | |
3179 | ||
22af9025 | 3180 | /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ |
3a298203 PM |
3181 | static inline bool aa64_generate_debug_exceptions(CPUARMState *env) |
3182 | { | |
22af9025 AB |
3183 | int cur_el = arm_current_el(env); |
3184 | int debug_el; | |
3185 | ||
3186 | if (cur_el == 3) { | |
3187 | return false; | |
533e93f1 PM |
3188 | } |
3189 | ||
22af9025 AB |
3190 | /* MDCR_EL3.SDD disables debug events from Secure state */ |
3191 | if (arm_is_secure_below_el3(env) | |
3192 | && extract32(env->cp15.mdcr_el3, 16, 1)) { | |
3193 | return false; | |
3a298203 | 3194 | } |
22af9025 AB |
3195 | |
3196 | /* | |
3197 | * Same EL to same EL debug exceptions need MDSCR_KDE enabled | |
3198 | * while not masking the (D)ebug bit in DAIF. | |
3199 | */ | |
3200 | debug_el = arm_debug_target_el(env); | |
3201 | ||
3202 | if (cur_el == debug_el) { | |
3203 | return extract32(env->cp15.mdscr_el1, 13, 1) | |
3204 | && !(env->daif & PSTATE_D); | |
3205 | } | |
3206 | ||
3207 | /* Otherwise the debug target needs to be a higher EL */ | |
3208 | return debug_el > cur_el; | |
3a298203 PM |
3209 | } |
3210 | ||
3211 | static inline bool aa32_generate_debug_exceptions(CPUARMState *env) | |
3212 | { | |
533e93f1 PM |
3213 | int el = arm_current_el(env); |
3214 | ||
3215 | if (el == 0 && arm_el_is_aa64(env, 1)) { | |
3a298203 PM |
3216 | return aa64_generate_debug_exceptions(env); |
3217 | } | |
533e93f1 PM |
3218 | |
3219 | if (arm_is_secure(env)) { | |
3220 | int spd; | |
3221 | ||
3222 | if (el == 0 && (env->cp15.sder & 1)) { | |
3223 | /* SDER.SUIDEN means debug exceptions from Secure EL0 | |
3224 | * are always enabled. Otherwise they are controlled by | |
3225 | * SDCR.SPD like those from other Secure ELs. | |
3226 | */ | |
3227 | return true; | |
3228 | } | |
3229 | ||
3230 | spd = extract32(env->cp15.mdcr_el3, 14, 2); | |
3231 | switch (spd) { | |
3232 | case 1: | |
3233 | /* SPD == 0b01 is reserved, but behaves as 0b00. */ | |
3234 | case 0: | |
3235 | /* For 0b00 we return true if external secure invasive debug | |
3236 | * is enabled. On real hardware this is controlled by external | |
3237 | * signals to the core. QEMU always permits debug, and behaves | |
3238 | * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. | |
3239 | */ | |
3240 | return true; | |
3241 | case 2: | |
3242 | return false; | |
3243 | case 3: | |
3244 | return true; | |
3245 | } | |
3246 | } | |
3247 | ||
3248 | return el != 2; | |
3a298203 PM |
3249 | } |
3250 | ||
3251 | /* Return true if debugging exceptions are currently enabled. | |
3252 | * This corresponds to what in ARM ARM pseudocode would be | |
3253 | * if UsingAArch32() then | |
3254 | * return AArch32.GenerateDebugExceptions() | |
3255 | * else | |
3256 | * return AArch64.GenerateDebugExceptions() | |
3257 | * We choose to push the if() down into this function for clarity, | |
3258 | * since the pseudocode has it at all callsites except for the one in | |
3259 | * CheckSoftwareStep(), where it is elided because both branches would | |
3260 | * always return the same value. | |
3a298203 PM |
3261 | */ |
3262 | static inline bool arm_generate_debug_exceptions(CPUARMState *env) | |
3263 | { | |
3264 | if (env->aarch64) { | |
3265 | return aa64_generate_debug_exceptions(env); | |
3266 | } else { | |
3267 | return aa32_generate_debug_exceptions(env); | |
3268 | } | |
3269 | } | |
3270 | ||
3271 | /* Is single-stepping active? (Note that the "is EL_D AArch64?" check | |
3272 | * implicitly means this always returns false in pre-v8 CPUs.) | |
3273 | */ | |
3274 | static inline bool arm_singlestep_active(CPUARMState *env) | |
3275 | { | |
3276 | return extract32(env->cp15.mdscr_el1, 0, 1) | |
3277 | && arm_el_is_aa64(env, arm_debug_target_el(env)) | |
3278 | && arm_generate_debug_exceptions(env); | |
3279 | } | |
3280 | ||
f9fd40eb PB |
3281 | static inline bool arm_sctlr_b(CPUARMState *env) |
3282 | { | |
3283 | return | |
3284 | /* We need not implement SCTLR.ITD in user-mode emulation, so | |
3285 | * let linux-user ignore the fact that it conflicts with SCTLR_B. | |
3286 | * This lets people run BE32 binaries with "-cpu any". | |
3287 | */ | |
3288 | #ifndef CONFIG_USER_ONLY | |
3289 | !arm_feature(env, ARM_FEATURE_V7) && | |
3290 | #endif | |
3291 | (env->cp15.sctlr_el[1] & SCTLR_B) != 0; | |
3292 | } | |
3293 | ||
aaec1432 | 3294 | uint64_t arm_sctlr(CPUARMState *env, int el); |
64e40755 | 3295 | |
8061a649 RH |
3296 | static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env, |
3297 | bool sctlr_b) | |
3298 | { | |
3299 | #ifdef CONFIG_USER_ONLY | |
3300 | /* | |
3301 | * In system mode, BE32 is modelled in line with the | |
3302 | * architecture (as word-invariant big-endianness), where loads | |
3303 | * and stores are done little endian but from addresses which | |
3304 | * are adjusted by XORing with the appropriate constant. So the | |
3305 | * endianness to use for the raw data access is not affected by | |
3306 | * SCTLR.B. | |
3307 | * In user mode, however, we model BE32 as byte-invariant | |
3308 | * big-endianness (because user-only code cannot tell the | |
3309 | * difference), and so we need to use a data access endianness | |
3310 | * that depends on SCTLR.B. | |
3311 | */ | |
3312 | if (sctlr_b) { | |
3313 | return true; | |
3314 | } | |
3315 | #endif | |
3316 | /* In 32bit endianness is determined by looking at CPSR's E bit */ | |
3317 | return env->uncached_cpsr & CPSR_E; | |
3318 | } | |
3319 | ||
3320 | static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr) | |
3321 | { | |
3322 | return sctlr & (el ? SCTLR_EE : SCTLR_E0E); | |
3323 | } | |
64e40755 | 3324 | |
ed50ff78 PC |
3325 | /* Return true if the processor is in big-endian mode. */ |
3326 | static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) | |
3327 | { | |
ed50ff78 | 3328 | if (!is_a64(env)) { |
8061a649 | 3329 | return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env)); |
64e40755 RH |
3330 | } else { |
3331 | int cur_el = arm_current_el(env); | |
3332 | uint64_t sctlr = arm_sctlr(env, cur_el); | |
8061a649 | 3333 | return arm_cpu_data_is_big_endian_a64(cur_el, sctlr); |
ed50ff78 | 3334 | } |
ed50ff78 PC |
3335 | } |
3336 | ||
4f7c64b3 | 3337 | typedef CPUARMState CPUArchState; |
2161a612 | 3338 | typedef ARMCPU ArchCPU; |
4f7c64b3 | 3339 | |
022c62cb | 3340 | #include "exec/cpu-all.h" |
622ed360 | 3341 | |
fdd1b228 RH |
3342 | /* |
3343 | * Bit usage in the TB flags field: bit 31 indicates whether we are | |
3926cc84 | 3344 | * in 32 or 64 bit mode. The meaning of the other bits depends on that. |
c1e37810 PM |
3345 | * We put flags which are shared between 32 and 64 bit mode at the top |
3346 | * of the word, and flags which apply to only one mode at the bottom. | |
fdd1b228 | 3347 | * |
506f1498 | 3348 | * 31 20 18 14 9 0 |
79cabf1f RH |
3349 | * +--------------+-----+-----+----------+--------------+ |
3350 | * | | | TBFLAG_A32 | | | |
3351 | * | | +-----+----------+ TBFLAG_AM32 | | |
3352 | * | TBFLAG_ANY | |TBFLAG_M32| | | |
81ae05fa RH |
3353 | * | +-----------+----------+--------------| |
3354 | * | | TBFLAG_A64 | | |
3355 | * +--------------+-------------------------------------+ | |
3356 | * 31 20 0 | |
79cabf1f | 3357 | * |
fdd1b228 | 3358 | * Unless otherwise noted, these bits are cached in env->hflags. |
3926cc84 | 3359 | */ |
aad821ac | 3360 | FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) |
506f1498 RH |
3361 | FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1) |
3362 | FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1) /* Not cached. */ | |
3363 | FIELD(TBFLAG_ANY, BE_DATA, 28, 1) | |
3364 | FIELD(TBFLAG_ANY, MMUIDX, 24, 4) | |
9dbbc748 | 3365 | /* Target EL if we take a floating-point-disabled exception */ |
506f1498 | 3366 | FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2) |
79cabf1f | 3367 | /* For A-profile only, target EL for debug exceptions. */ |
506f1498 | 3368 | FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2) |
79cabf1f | 3369 | |
8bd587c1 | 3370 | /* |
79cabf1f | 3371 | * Bit usage when in AArch32 state, both A- and M-profile. |
8bd587c1 | 3372 | */ |
79cabf1f RH |
3373 | FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */ |
3374 | FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */ | |
3926cc84 | 3375 | |
79cabf1f RH |
3376 | /* |
3377 | * Bit usage when in AArch32 state, for A-profile only. | |
3378 | */ | |
3379 | FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */ | |
3380 | FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */ | |
ea7ac69d PM |
3381 | /* |
3382 | * We store the bottom two bits of the CPAR as TB flags and handle | |
3383 | * checks on the other bits at runtime. This shares the same bits as | |
3384 | * VECSTRIDE, which is OK as no XScale CPU has VFP. | |
fdd1b228 | 3385 | * Not cached, because VECLEN+VECSTRIDE are not cached. |
ea7ac69d | 3386 | */ |
79cabf1f RH |
3387 | FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2) |
3388 | FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */ | |
3389 | FIELD(TBFLAG_A32, SCTLR_B, 15, 1) | |
3390 | FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1) | |
7fbb535f PM |
3391 | /* |
3392 | * Indicates whether cp register reads and writes by guest code should access | |
3393 | * the secure or nonsecure bank of banked registers; note that this is not | |
3394 | * the same thing as the current security state of the processor! | |
3395 | */ | |
79cabf1f RH |
3396 | FIELD(TBFLAG_A32, NS, 17, 1) |
3397 | ||
3398 | /* | |
3399 | * Bit usage when in AArch32 state, for M-profile only. | |
3400 | */ | |
3401 | /* Handler (ie not Thread) mode */ | |
3402 | FIELD(TBFLAG_M32, HANDLER, 9, 1) | |
3403 | /* Whether we should generate stack-limit checks */ | |
3404 | FIELD(TBFLAG_M32, STACKCHECK, 10, 1) | |
3405 | /* Set if FPCCR.LSPACT is set */ | |
3406 | FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */ | |
3407 | /* Set if we must create a new FP context */ | |
3408 | FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */ | |
3409 | /* Set if FPCCR.S does not match current security state */ | |
3410 | FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */ | |
3411 | ||
3412 | /* | |
3413 | * Bit usage when in AArch64 state | |
3414 | */ | |
476a4692 | 3415 | FIELD(TBFLAG_A64, TBII, 0, 2) |
aad821ac RH |
3416 | FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) |
3417 | FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) | |
0816ef1b | 3418 | FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) |
08f1434a | 3419 | FIELD(TBFLAG_A64, BT, 9, 1) |
fdd1b228 | 3420 | FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ |
4a9ee99d | 3421 | FIELD(TBFLAG_A64, TBID, 12, 2) |
cc28fc30 | 3422 | FIELD(TBFLAG_A64, UNPRIV, 14, 1) |
81ae05fa RH |
3423 | FIELD(TBFLAG_A64, ATA, 15, 1) |
3424 | FIELD(TBFLAG_A64, TCMA, 16, 2) | |
3425 | FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1) | |
3426 | FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1) | |
a1705768 | 3427 | |
fb901c90 RH |
3428 | /** |
3429 | * cpu_mmu_index: | |
3430 | * @env: The cpu environment | |
3431 | * @ifetch: True for code access, false for data access. | |
3432 | * | |
3433 | * Return the core mmu index for the current translation regime. | |
3434 | * This function is used by generic TCG code paths. | |
3435 | */ | |
3436 | static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) | |
3437 | { | |
3438 | return FIELD_EX32(env->hflags, TBFLAG_ANY, MMUIDX); | |
3439 | } | |
3440 | ||
f9fd40eb PB |
3441 | static inline bool bswap_code(bool sctlr_b) |
3442 | { | |
3443 | #ifdef CONFIG_USER_ONLY | |
3444 | /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian. | |
3445 | * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0 | |
3446 | * would also end up as a mixed-endian mode with BE code, LE data. | |
3447 | */ | |
3448 | return | |
3449 | #ifdef TARGET_WORDS_BIGENDIAN | |
3450 | 1 ^ | |
3451 | #endif | |
3452 | sctlr_b; | |
3453 | #else | |
e334bd31 PB |
3454 | /* All code access in ARM is little endian, and there are no loaders |
3455 | * doing swaps that need to be reversed | |
f9fd40eb PB |
3456 | */ |
3457 | return 0; | |
3458 | #endif | |
3459 | } | |
3460 | ||
c3ae85fc PB |
3461 | #ifdef CONFIG_USER_ONLY |
3462 | static inline bool arm_cpu_bswap_data(CPUARMState *env) | |
3463 | { | |
3464 | return | |
3465 | #ifdef TARGET_WORDS_BIGENDIAN | |
3466 | 1 ^ | |
3467 | #endif | |
3468 | arm_cpu_data_is_big_endian(env); | |
3469 | } | |
3470 | #endif | |
3471 | ||
a9e01311 RH |
3472 | void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, |
3473 | target_ulong *cs_base, uint32_t *flags); | |
6b917547 | 3474 | |
98128601 RH |
3475 | enum { |
3476 | QEMU_PSCI_CONDUIT_DISABLED = 0, | |
3477 | QEMU_PSCI_CONDUIT_SMC = 1, | |
3478 | QEMU_PSCI_CONDUIT_HVC = 2, | |
3479 | }; | |
3480 | ||
017518c1 PM |
3481 | #ifndef CONFIG_USER_ONLY |
3482 | /* Return the address space index to use for a memory access */ | |
3483 | static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) | |
3484 | { | |
3485 | return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; | |
3486 | } | |
5ce4ff65 PM |
3487 | |
3488 | /* Return the AddressSpace to use for a memory access | |
3489 | * (which depends on whether the access is S or NS, and whether | |
3490 | * the board gave us a separate AddressSpace for S accesses). | |
3491 | */ | |
3492 | static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) | |
3493 | { | |
3494 | return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); | |
3495 | } | |
017518c1 PM |
3496 | #endif |
3497 | ||
bd7d00fc | 3498 | /** |
b5c53d1b AL |
3499 | * arm_register_pre_el_change_hook: |
3500 | * Register a hook function which will be called immediately before this | |
bd7d00fc PM |
3501 | * CPU changes exception level or mode. The hook function will be |
3502 | * passed a pointer to the ARMCPU and the opaque data pointer passed | |
3503 | * to this function when the hook was registered. | |
b5c53d1b AL |
3504 | * |
3505 | * Note that if a pre-change hook is called, any registered post-change hooks | |
3506 | * are guaranteed to subsequently be called. | |
bd7d00fc | 3507 | */ |
b5c53d1b | 3508 | void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, |
bd7d00fc | 3509 | void *opaque); |
b5c53d1b AL |
3510 | /** |
3511 | * arm_register_el_change_hook: | |
3512 | * Register a hook function which will be called immediately after this | |
3513 | * CPU changes exception level or mode. The hook function will be | |
3514 | * passed a pointer to the ARMCPU and the opaque data pointer passed | |
3515 | * to this function when the hook was registered. | |
3516 | * | |
3517 | * Note that any registered hooks registered here are guaranteed to be called | |
3518 | * if pre-change hooks have been. | |
3519 | */ | |
3520 | void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void | |
3521 | *opaque); | |
bd7d00fc | 3522 | |
3d74e2e9 RH |
3523 | /** |
3524 | * arm_rebuild_hflags: | |
3525 | * Rebuild the cached TBFLAGS for arbitrary changed processor state. | |
3526 | */ | |
3527 | void arm_rebuild_hflags(CPUARMState *env); | |
3528 | ||
9a2b5256 RH |
3529 | /** |
3530 | * aa32_vfp_dreg: | |
3531 | * Return a pointer to the Dn register within env in 32-bit mode. | |
3532 | */ | |
3533 | static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) | |
3534 | { | |
c39c2b90 | 3535 | return &env->vfp.zregs[regno >> 1].d[regno & 1]; |
9a2b5256 RH |
3536 | } |
3537 | ||
3538 | /** | |
3539 | * aa32_vfp_qreg: | |
3540 | * Return a pointer to the Qn register within env in 32-bit mode. | |
3541 | */ | |
3542 | static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) | |
3543 | { | |
c39c2b90 | 3544 | return &env->vfp.zregs[regno].d[0]; |
9a2b5256 RH |
3545 | } |
3546 | ||
3547 | /** | |
3548 | * aa64_vfp_qreg: | |
3549 | * Return a pointer to the Qn register within env in 64-bit mode. | |
3550 | */ | |
3551 | static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) | |
3552 | { | |
c39c2b90 | 3553 | return &env->vfp.zregs[regno].d[0]; |
9a2b5256 RH |
3554 | } |
3555 | ||
028e2a7b RH |
3556 | /* Shared between translate-sve.c and sve_helper.c. */ |
3557 | extern const uint64_t pred_esz_masks[4]; | |
3558 | ||
149d3b31 RH |
3559 | /* Helper for the macros below, validating the argument type. */ |
3560 | static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) | |
3561 | { | |
3562 | return x; | |
3563 | } | |
3564 | ||
3565 | /* | |
3566 | * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB. | |
3567 | * Using these should be a bit more self-documenting than using the | |
3568 | * generic target bits directly. | |
3569 | */ | |
3570 | #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) | |
206adacf | 3571 | #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) |
149d3b31 | 3572 | |
be5d6f48 RH |
3573 | /* |
3574 | * AArch64 usage of the PAGE_TARGET_* bits for linux-user. | |
3575 | */ | |
3576 | #define PAGE_BTI PAGE_TARGET_1 | |
3577 | ||
873b73c0 PM |
3578 | /* |
3579 | * Naming convention for isar_feature functions: | |
3580 | * Functions which test 32-bit ID registers should have _aa32_ in | |
3581 | * their name. Functions which test 64-bit ID registers should have | |
6e61f839 PM |
3582 | * _aa64_ in their name. These must only be used in code where we |
3583 | * know for certain that the CPU has AArch32 or AArch64 respectively | |
3584 | * or where the correct answer for a CPU which doesn't implement that | |
3585 | * CPU state is "false" (eg when generating A32 or A64 code, if adding | |
3586 | * system registers that are specific to that CPU state, for "should | |
3587 | * we let this system register bit be set" tests where the 32-bit | |
3588 | * flavour of the register doesn't have the bit, and so on). | |
3589 | * Functions which simply ask "does this feature exist at all" have | |
3590 | * _any_ in their name, and always return the logical OR of the _aa64_ | |
3591 | * and the _aa32_ function. | |
873b73c0 PM |
3592 | */ |
3593 | ||
962fcbf2 RH |
3594 | /* |
3595 | * 32-bit feature tests via id registers. | |
3596 | */ | |
873b73c0 | 3597 | static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) |
7e0cf8b4 RH |
3598 | { |
3599 | return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; | |
3600 | } | |
3601 | ||
873b73c0 | 3602 | static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) |
7e0cf8b4 RH |
3603 | { |
3604 | return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; | |
3605 | } | |
05903f03 PM |
3606 | |
3607 | static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) | |
3608 | { | |
3609 | /* (M-profile) low-overhead loops and branch future */ | |
3610 | return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; | |
3611 | } | |
7e0cf8b4 | 3612 | |
873b73c0 | 3613 | static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) |
09cbd501 RH |
3614 | { |
3615 | return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; | |
3616 | } | |
3617 | ||
962fcbf2 RH |
3618 | static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) |
3619 | { | |
3620 | return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; | |
3621 | } | |
3622 | ||
3623 | static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) | |
3624 | { | |
3625 | return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; | |
3626 | } | |
3627 | ||
3628 | static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) | |
3629 | { | |
3630 | return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; | |
3631 | } | |
3632 | ||
3633 | static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) | |
3634 | { | |
3635 | return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; | |
3636 | } | |
3637 | ||
3638 | static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) | |
3639 | { | |
3640 | return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; | |
3641 | } | |
3642 | ||
3643 | static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) | |
3644 | { | |
3645 | return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; | |
3646 | } | |
3647 | ||
3648 | static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) | |
3649 | { | |
3650 | return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; | |
3651 | } | |
3652 | ||
6c1f6f27 RH |
3653 | static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) |
3654 | { | |
3655 | return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; | |
3656 | } | |
3657 | ||
962fcbf2 RH |
3658 | static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) |
3659 | { | |
3660 | return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; | |
3661 | } | |
3662 | ||
87732318 RH |
3663 | static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) |
3664 | { | |
3665 | return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; | |
3666 | } | |
3667 | ||
9888bd1e RH |
3668 | static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) |
3669 | { | |
3670 | return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; | |
3671 | } | |
3672 | ||
cb570bd3 RH |
3673 | static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) |
3674 | { | |
3675 | return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; | |
3676 | } | |
3677 | ||
46f4976f PM |
3678 | static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) |
3679 | { | |
3680 | return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; | |
3681 | } | |
3682 | ||
dfc523a8 PM |
3683 | static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) |
3684 | { | |
3685 | return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; | |
3686 | } | |
3687 | ||
83ff3d6a PM |
3688 | static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) |
3689 | { | |
3690 | /* | |
3691 | * Return true if M-profile state handling insns | |
3692 | * (VSCCLRM, CLRM, FPCTX access insns) are implemented | |
3693 | */ | |
3694 | return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; | |
3695 | } | |
3696 | ||
5763190f RH |
3697 | static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) |
3698 | { | |
dfc523a8 PM |
3699 | /* Sadly this is encoded differently for A-profile and M-profile */ |
3700 | if (isar_feature_aa32_mprofile(id)) { | |
3701 | return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; | |
3702 | } else { | |
3703 | return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; | |
3704 | } | |
5763190f RH |
3705 | } |
3706 | ||
7fbc6a40 RH |
3707 | static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) |
3708 | { | |
3709 | /* | |
3710 | * Return true if either VFP or SIMD is implemented. | |
3711 | * In this case, a minimum of VFP w/ D0-D15. | |
3712 | */ | |
3713 | return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; | |
3714 | } | |
3715 | ||
0e13ba78 | 3716 | static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) |
b3ff4b87 PM |
3717 | { |
3718 | /* Return true if D16-D31 are implemented */ | |
b3a816f6 | 3719 | return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; |
b3ff4b87 PM |
3720 | } |
3721 | ||
266bd25c PM |
3722 | static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) |
3723 | { | |
b3a816f6 | 3724 | return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; |
266bd25c PM |
3725 | } |
3726 | ||
f67957e1 RH |
3727 | static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) |
3728 | { | |
3729 | /* Return true if CPU supports single precision floating point, VFPv2 */ | |
3730 | return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; | |
3731 | } | |
3732 | ||
3733 | static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) | |
3734 | { | |
3735 | /* Return true if CPU supports single precision floating point, VFPv3 */ | |
3736 | return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; | |
3737 | } | |
3738 | ||
c4ff8735 | 3739 | static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) |
1120827f | 3740 | { |
c4ff8735 | 3741 | /* Return true if CPU supports double precision floating point, VFPv2 */ |
b3a816f6 | 3742 | return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; |
1120827f PM |
3743 | } |
3744 | ||
f67957e1 RH |
3745 | static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) |
3746 | { | |
3747 | /* Return true if CPU supports double precision floating point, VFPv3 */ | |
3748 | return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; | |
3749 | } | |
3750 | ||
7d63183f RH |
3751 | static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) |
3752 | { | |
3753 | return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); | |
3754 | } | |
3755 | ||
602f6e42 PM |
3756 | /* |
3757 | * We always set the FP and SIMD FP16 fields to indicate identical | |
3758 | * levels of support (assuming SIMD is implemented at all), so | |
3759 | * we only need one set of accessors. | |
3760 | */ | |
3761 | static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) | |
3762 | { | |
b3a816f6 | 3763 | return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; |
602f6e42 PM |
3764 | } |
3765 | ||
3766 | static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) | |
3767 | { | |
b3a816f6 | 3768 | return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; |
602f6e42 PM |
3769 | } |
3770 | ||
c52881bb RH |
3771 | /* |
3772 | * Note that this ID register field covers both VFP and Neon FMAC, | |
3773 | * so should usually be tested in combination with some other | |
3774 | * check that confirms the presence of whichever of VFP or Neon is | |
3775 | * relevant, to avoid accidentally enabling a Neon feature on | |
3776 | * a VFP-no-Neon core or vice-versa. | |
3777 | */ | |
3778 | static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) | |
3779 | { | |
3780 | return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; | |
3781 | } | |
3782 | ||
c0c760af PM |
3783 | static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) |
3784 | { | |
b3a816f6 | 3785 | return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; |
c0c760af PM |
3786 | } |
3787 | ||
3788 | static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) | |
3789 | { | |
b3a816f6 | 3790 | return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; |
c0c760af PM |
3791 | } |
3792 | ||
3793 | static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) | |
3794 | { | |
b3a816f6 | 3795 | return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; |
c0c760af PM |
3796 | } |
3797 | ||
3798 | static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) | |
3799 | { | |
b3a816f6 | 3800 | return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; |
c0c760af PM |
3801 | } |
3802 | ||
0ae0326b PM |
3803 | static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) |
3804 | { | |
3805 | return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; | |
3806 | } | |
3807 | ||
3d6ad6bb RH |
3808 | static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) |
3809 | { | |
10054016 | 3810 | return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; |
3d6ad6bb RH |
3811 | } |
3812 | ||
3813 | static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) | |
3814 | { | |
10054016 | 3815 | return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; |
3d6ad6bb RH |
3816 | } |
3817 | ||
a6179538 PM |
3818 | static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) |
3819 | { | |
3820 | /* 0xf means "non-standard IMPDEF PMU" */ | |
3821 | return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && | |
3822 | FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; | |
3823 | } | |
3824 | ||
15dd1ebd PM |
3825 | static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) |
3826 | { | |
3827 | /* 0xf means "non-standard IMPDEF PMU" */ | |
3828 | return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && | |
3829 | FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; | |
3830 | } | |
3831 | ||
4036b7d1 PM |
3832 | static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) |
3833 | { | |
3834 | return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; | |
3835 | } | |
3836 | ||
f6287c24 PM |
3837 | static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) |
3838 | { | |
3839 | return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; | |
3840 | } | |
3841 | ||
957e6155 PM |
3842 | static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) |
3843 | { | |
3844 | return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; | |
3845 | } | |
3846 | ||
ce3125be PM |
3847 | static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) |
3848 | { | |
3849 | return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; | |
3850 | } | |
3851 | ||
962fcbf2 RH |
3852 | /* |
3853 | * 64-bit feature tests via id registers. | |
3854 | */ | |
3855 | static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) | |
3856 | { | |
3857 | return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; | |
3858 | } | |
3859 | ||
3860 | static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) | |
3861 | { | |
3862 | return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; | |
3863 | } | |
3864 | ||
3865 | static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) | |
3866 | { | |
3867 | return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; | |
3868 | } | |
3869 | ||
3870 | static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) | |
3871 | { | |
3872 | return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; | |
3873 | } | |
3874 | ||
3875 | static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) | |
3876 | { | |
3877 | return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; | |
3878 | } | |
3879 | ||
3880 | static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) | |
3881 | { | |
3882 | return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; | |
3883 | } | |
3884 | ||
3885 | static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) | |
3886 | { | |
3887 | return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; | |
3888 | } | |
3889 | ||
3890 | static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) | |
3891 | { | |
3892 | return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; | |
3893 | } | |
3894 | ||
3895 | static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) | |
3896 | { | |
3897 | return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; | |
3898 | } | |
3899 | ||
3900 | static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) | |
3901 | { | |
3902 | return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; | |
3903 | } | |
3904 | ||
3905 | static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) | |
3906 | { | |
3907 | return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; | |
3908 | } | |
3909 | ||
3910 | static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) | |
3911 | { | |
3912 | return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; | |
3913 | } | |
3914 | ||
0caa5af8 RH |
3915 | static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) |
3916 | { | |
3917 | return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; | |
3918 | } | |
3919 | ||
b89d9c98 RH |
3920 | static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) |
3921 | { | |
3922 | return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; | |
3923 | } | |
3924 | ||
5ef84f11 RH |
3925 | static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) |
3926 | { | |
3927 | return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; | |
3928 | } | |
3929 | ||
de390645 RH |
3930 | static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) |
3931 | { | |
3932 | return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; | |
3933 | } | |
3934 | ||
6c1f6f27 RH |
3935 | static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) |
3936 | { | |
3937 | return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; | |
3938 | } | |
3939 | ||
962fcbf2 RH |
3940 | static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) |
3941 | { | |
3942 | return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; | |
3943 | } | |
3944 | ||
991ad91b RH |
3945 | static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) |
3946 | { | |
3947 | /* | |
283fc52a RH |
3948 | * Return true if any form of pauth is enabled, as this |
3949 | * predicate controls migration of the 128-bit keys. | |
991ad91b RH |
3950 | */ |
3951 | return (id->id_aa64isar1 & | |
3952 | (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | | |
3953 | FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | | |
3954 | FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | | |
3955 | FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; | |
3956 | } | |
3957 | ||
283fc52a RH |
3958 | static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) |
3959 | { | |
3960 | /* | |
3961 | * Return true if pauth is enabled with the architected QARMA algorithm. | |
3962 | * QEMU will always set APA+GPA to the same value. | |
3963 | */ | |
3964 | return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; | |
3965 | } | |
3966 | ||
9888bd1e RH |
3967 | static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) |
3968 | { | |
3969 | return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; | |
3970 | } | |
3971 | ||
cb570bd3 RH |
3972 | static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) |
3973 | { | |
3974 | return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; | |
3975 | } | |
3976 | ||
6bea2563 RH |
3977 | static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) |
3978 | { | |
3979 | return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; | |
3980 | } | |
3981 | ||
0d57b499 BM |
3982 | static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) |
3983 | { | |
3984 | return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; | |
3985 | } | |
3986 | ||
3987 | static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) | |
3988 | { | |
3989 | return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; | |
3990 | } | |
3991 | ||
7d63183f RH |
3992 | static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) |
3993 | { | |
3994 | /* We always set the AdvSIMD and FP fields identically. */ | |
3995 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; | |
3996 | } | |
3997 | ||
5763190f RH |
3998 | static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) |
3999 | { | |
4000 | /* We always set the AdvSIMD and FP fields identically wrt FP16. */ | |
4001 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; | |
4002 | } | |
4003 | ||
0f8d06f1 RH |
4004 | static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) |
4005 | { | |
4006 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; | |
4007 | } | |
4008 | ||
cd208a1c RH |
4009 | static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) |
4010 | { | |
4011 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; | |
4012 | } | |
4013 | ||
8fc2ea21 RH |
4014 | static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) |
4015 | { | |
4016 | return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; | |
4017 | } | |
4018 | ||
2d7137c1 RH |
4019 | static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) |
4020 | { | |
4021 | return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; | |
4022 | } | |
4023 | ||
3d6ad6bb RH |
4024 | static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) |
4025 | { | |
4026 | return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; | |
4027 | } | |
4028 | ||
4029 | static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) | |
4030 | { | |
4031 | return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; | |
4032 | } | |
4033 | ||
9eeb7a1c RH |
4034 | static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) |
4035 | { | |
4036 | return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; | |
4037 | } | |
4038 | ||
c36c65ea RDC |
4039 | static inline bool isar_feature_aa64_st(const ARMISARegisters *id) |
4040 | { | |
4041 | return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; | |
4042 | } | |
4043 | ||
be53b6f4 RH |
4044 | static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) |
4045 | { | |
4046 | return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; | |
4047 | } | |
4048 | ||
c7fd0baa RH |
4049 | static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) |
4050 | { | |
4051 | return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; | |
4052 | } | |
4053 | ||
4054 | static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) | |
4055 | { | |
4056 | return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; | |
4057 | } | |
4058 | ||
2a609df8 PM |
4059 | static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) |
4060 | { | |
4061 | return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && | |
4062 | FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; | |
4063 | } | |
4064 | ||
15dd1ebd PM |
4065 | static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) |
4066 | { | |
54117b90 PM |
4067 | return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && |
4068 | FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; | |
15dd1ebd PM |
4069 | } |
4070 | ||
2677cf9f PM |
4071 | static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) |
4072 | { | |
4073 | return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; | |
4074 | } | |
4075 | ||
a1229109 PM |
4076 | static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) |
4077 | { | |
4078 | return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; | |
4079 | } | |
4080 | ||
957e6155 PM |
4081 | static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) |
4082 | { | |
4083 | return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; | |
4084 | } | |
4085 | ||
ce3125be PM |
4086 | static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) |
4087 | { | |
4088 | return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; | |
4089 | } | |
4090 | ||
6e61f839 PM |
4091 | /* |
4092 | * Feature tests for "does this exist in either 32-bit or 64-bit?" | |
4093 | */ | |
4094 | static inline bool isar_feature_any_fp16(const ARMISARegisters *id) | |
4095 | { | |
4096 | return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); | |
4097 | } | |
4098 | ||
22e57073 PM |
4099 | static inline bool isar_feature_any_predinv(const ARMISARegisters *id) |
4100 | { | |
4101 | return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); | |
4102 | } | |
4103 | ||
2a609df8 PM |
4104 | static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) |
4105 | { | |
4106 | return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); | |
4107 | } | |
4108 | ||
15dd1ebd PM |
4109 | static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) |
4110 | { | |
4111 | return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); | |
4112 | } | |
4113 | ||
957e6155 PM |
4114 | static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) |
4115 | { | |
4116 | return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); | |
4117 | } | |
4118 | ||
ce3125be PM |
4119 | static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) |
4120 | { | |
4121 | return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); | |
4122 | } | |
4123 | ||
962fcbf2 RH |
4124 | /* |
4125 | * Forward to the above feature tests given an ARMCPU pointer. | |
4126 | */ | |
4127 | #define cpu_isar_feature(name, cpu) \ | |
4128 | ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) | |
4129 | ||
2c0262af | 4130 | #endif |