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d14d42f1 PM |
1 | /* |
2 | * QEMU AArch64 CPU | |
3 | * | |
4 | * Copyright (c) 2013 Linaro Ltd | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
74c21bd0 | 21 | #include "qemu/osdep.h" |
da34e65c | 22 | #include "qapi/error.h" |
d14d42f1 PM |
23 | #include "cpu.h" |
24 | #include "qemu-common.h" | |
25 | #if !defined(CONFIG_USER_ONLY) | |
26 | #include "hw/loader.h" | |
27 | #endif | |
28 | #include "hw/arm/arm.h" | |
29 | #include "sysemu/sysemu.h" | |
30 | #include "sysemu/kvm.h" | |
bab52d4b | 31 | #include "kvm_arm.h" |
adf92eab | 32 | #include "qapi/visitor.h" |
d14d42f1 PM |
33 | |
34 | static inline void set_feature(CPUARMState *env, int feature) | |
35 | { | |
36 | env->features |= 1ULL << feature; | |
37 | } | |
38 | ||
fb8d6c24 GB |
39 | static inline void unset_feature(CPUARMState *env, int feature) |
40 | { | |
41 | env->features &= ~(1ULL << feature); | |
42 | } | |
43 | ||
377a44ec | 44 | #ifndef CONFIG_USER_ONLY |
ee804264 | 45 | static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
377a44ec | 46 | { |
f9a69711 AF |
47 | ARMCPU *cpu = arm_env_get_cpu(env); |
48 | ||
49 | /* Number of cores is in [25:24]; otherwise we RAZ */ | |
50 | return (cpu->core_count - 1) << 24; | |
377a44ec PM |
51 | } |
52 | #endif | |
53 | ||
f11b452b | 54 | static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { |
377a44ec PM |
55 | #ifndef CONFIG_USER_ONLY |
56 | { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, | |
57 | .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, | |
ee804264 | 58 | .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, |
377a44ec PM |
59 | .writefn = arm_cp_write_ignore }, |
60 | { .name = "L2CTLR", | |
61 | .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, | |
ee804264 | 62 | .access = PL1_RW, .readfn = a57_a53_l2ctlr_read, |
377a44ec PM |
63 | .writefn = arm_cp_write_ignore }, |
64 | #endif | |
65 | { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, | |
66 | .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, | |
67 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
68 | { .name = "L2ECTLR", | |
69 | .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, | |
70 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
71 | { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, | |
72 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, | |
73 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
74 | { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, | |
75 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, | |
76 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
77 | { .name = "CPUACTLR", | |
78 | .cp = 15, .opc1 = 0, .crm = 15, | |
79 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | |
80 | { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, | |
81 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, | |
82 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
83 | { .name = "CPUECTLR", | |
84 | .cp = 15, .opc1 = 1, .crm = 15, | |
85 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | |
86 | { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, | |
87 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, | |
88 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
89 | { .name = "CPUMERRSR", | |
90 | .cp = 15, .opc1 = 2, .crm = 15, | |
91 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | |
92 | { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, | |
93 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, | |
94 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
95 | { .name = "L2MERRSR", | |
96 | .cp = 15, .opc1 = 3, .crm = 15, | |
97 | .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | |
98 | REGINFO_SENTINEL | |
99 | }; | |
100 | ||
cb1fa941 PM |
101 | static void aarch64_a57_initfn(Object *obj) |
102 | { | |
103 | ARMCPU *cpu = ARM_CPU(obj); | |
104 | ||
0458b7b5 | 105 | cpu->dtb_compatible = "arm,cortex-a57"; |
cb1fa941 PM |
106 | set_feature(&cpu->env, ARM_FEATURE_V8); |
107 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
cb1fa941 PM |
108 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
109 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | |
110 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
f318cec6 | 111 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
c25bd18a | 112 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
3ad901bc | 113 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
929e754d | 114 | set_feature(&cpu->env, ARM_FEATURE_PMU); |
cb1fa941 PM |
115 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; |
116 | cpu->midr = 0x411fd070; | |
13b72b2b | 117 | cpu->revidr = 0x00000000; |
cb1fa941 | 118 | cpu->reset_fpsid = 0x41034070; |
47576b94 RH |
119 | cpu->isar.mvfr0 = 0x10110222; |
120 | cpu->isar.mvfr1 = 0x12111111; | |
121 | cpu->isar.mvfr2 = 0x00000043; | |
cb1fa941 PM |
122 | cpu->ctr = 0x8444c004; |
123 | cpu->reset_sctlr = 0x00c50838; | |
124 | cpu->id_pfr0 = 0x00000131; | |
125 | cpu->id_pfr1 = 0x00011011; | |
126 | cpu->id_dfr0 = 0x03010066; | |
127 | cpu->id_afr0 = 0x00000000; | |
128 | cpu->id_mmfr0 = 0x10101105; | |
129 | cpu->id_mmfr1 = 0x40000000; | |
130 | cpu->id_mmfr2 = 0x01260000; | |
131 | cpu->id_mmfr3 = 0x02102211; | |
47576b94 RH |
132 | cpu->isar.id_isar0 = 0x02101110; |
133 | cpu->isar.id_isar1 = 0x13112111; | |
134 | cpu->isar.id_isar2 = 0x21232042; | |
135 | cpu->isar.id_isar3 = 0x01112131; | |
136 | cpu->isar.id_isar4 = 0x00011142; | |
137 | cpu->isar.id_isar5 = 0x00011121; | |
138 | cpu->isar.id_isar6 = 0; | |
139 | cpu->isar.id_aa64pfr0 = 0x00002222; | |
cb1fa941 | 140 | cpu->id_aa64dfr0 = 0x10305106; |
47576b94 | 141 | cpu->isar.id_aa64isar0 = 0x00011120; |
3dc91ddb | 142 | cpu->isar.id_aa64mmfr0 = 0x00001124; |
48eb3ae6 | 143 | cpu->dbgdidr = 0x3516d000; |
cb1fa941 PM |
144 | cpu->clidr = 0x0a200023; |
145 | cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ | |
146 | cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ | |
147 | cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ | |
148 | cpu->dcz_blocksize = 4; /* 64 bytes */ | |
e45868a3 PM |
149 | cpu->gic_num_lrs = 4; |
150 | cpu->gic_vpribits = 5; | |
151 | cpu->gic_vprebits = 5; | |
f11b452b | 152 | define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); |
cb1fa941 PM |
153 | } |
154 | ||
e3531026 PC |
155 | static void aarch64_a53_initfn(Object *obj) |
156 | { | |
157 | ARMCPU *cpu = ARM_CPU(obj); | |
158 | ||
159 | cpu->dtb_compatible = "arm,cortex-a53"; | |
160 | set_feature(&cpu->env, ARM_FEATURE_V8); | |
161 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
162 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
163 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | |
164 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
165 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | |
c25bd18a | 166 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
3ad901bc | 167 | set_feature(&cpu->env, ARM_FEATURE_EL3); |
929e754d | 168 | set_feature(&cpu->env, ARM_FEATURE_PMU); |
7525465e | 169 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; |
e3531026 | 170 | cpu->midr = 0x410fd034; |
13b72b2b | 171 | cpu->revidr = 0x00000000; |
e3531026 | 172 | cpu->reset_fpsid = 0x41034070; |
47576b94 RH |
173 | cpu->isar.mvfr0 = 0x10110222; |
174 | cpu->isar.mvfr1 = 0x12111111; | |
175 | cpu->isar.mvfr2 = 0x00000043; | |
e3531026 PC |
176 | cpu->ctr = 0x84448004; /* L1Ip = VIPT */ |
177 | cpu->reset_sctlr = 0x00c50838; | |
178 | cpu->id_pfr0 = 0x00000131; | |
179 | cpu->id_pfr1 = 0x00011011; | |
180 | cpu->id_dfr0 = 0x03010066; | |
181 | cpu->id_afr0 = 0x00000000; | |
182 | cpu->id_mmfr0 = 0x10101105; | |
183 | cpu->id_mmfr1 = 0x40000000; | |
184 | cpu->id_mmfr2 = 0x01260000; | |
185 | cpu->id_mmfr3 = 0x02102211; | |
47576b94 RH |
186 | cpu->isar.id_isar0 = 0x02101110; |
187 | cpu->isar.id_isar1 = 0x13112111; | |
188 | cpu->isar.id_isar2 = 0x21232042; | |
189 | cpu->isar.id_isar3 = 0x01112131; | |
190 | cpu->isar.id_isar4 = 0x00011142; | |
191 | cpu->isar.id_isar5 = 0x00011121; | |
192 | cpu->isar.id_isar6 = 0; | |
193 | cpu->isar.id_aa64pfr0 = 0x00002222; | |
e3531026 | 194 | cpu->id_aa64dfr0 = 0x10305106; |
47576b94 | 195 | cpu->isar.id_aa64isar0 = 0x00011120; |
3dc91ddb | 196 | cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ |
e3531026 PC |
197 | cpu->dbgdidr = 0x3516d000; |
198 | cpu->clidr = 0x0a200023; | |
199 | cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ | |
200 | cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ | |
201 | cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ | |
202 | cpu->dcz_blocksize = 4; /* 64 bytes */ | |
e45868a3 PM |
203 | cpu->gic_num_lrs = 4; |
204 | cpu->gic_vpribits = 5; | |
205 | cpu->gic_vprebits = 5; | |
f11b452b EI |
206 | define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); |
207 | } | |
208 | ||
209 | static void aarch64_a72_initfn(Object *obj) | |
210 | { | |
211 | ARMCPU *cpu = ARM_CPU(obj); | |
212 | ||
213 | cpu->dtb_compatible = "arm,cortex-a72"; | |
214 | set_feature(&cpu->env, ARM_FEATURE_V8); | |
215 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
216 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
217 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | |
218 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
219 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | |
f11b452b EI |
220 | set_feature(&cpu->env, ARM_FEATURE_EL2); |
221 | set_feature(&cpu->env, ARM_FEATURE_EL3); | |
222 | set_feature(&cpu->env, ARM_FEATURE_PMU); | |
223 | cpu->midr = 0x410fd083; | |
224 | cpu->revidr = 0x00000000; | |
225 | cpu->reset_fpsid = 0x41034080; | |
47576b94 RH |
226 | cpu->isar.mvfr0 = 0x10110222; |
227 | cpu->isar.mvfr1 = 0x12111111; | |
228 | cpu->isar.mvfr2 = 0x00000043; | |
f11b452b EI |
229 | cpu->ctr = 0x8444c004; |
230 | cpu->reset_sctlr = 0x00c50838; | |
231 | cpu->id_pfr0 = 0x00000131; | |
232 | cpu->id_pfr1 = 0x00011011; | |
233 | cpu->id_dfr0 = 0x03010066; | |
234 | cpu->id_afr0 = 0x00000000; | |
235 | cpu->id_mmfr0 = 0x10201105; | |
236 | cpu->id_mmfr1 = 0x40000000; | |
237 | cpu->id_mmfr2 = 0x01260000; | |
238 | cpu->id_mmfr3 = 0x02102211; | |
47576b94 RH |
239 | cpu->isar.id_isar0 = 0x02101110; |
240 | cpu->isar.id_isar1 = 0x13112111; | |
241 | cpu->isar.id_isar2 = 0x21232042; | |
242 | cpu->isar.id_isar3 = 0x01112131; | |
243 | cpu->isar.id_isar4 = 0x00011142; | |
244 | cpu->isar.id_isar5 = 0x00011121; | |
245 | cpu->isar.id_aa64pfr0 = 0x00002222; | |
f11b452b | 246 | cpu->id_aa64dfr0 = 0x10305106; |
47576b94 | 247 | cpu->isar.id_aa64isar0 = 0x00011120; |
3dc91ddb | 248 | cpu->isar.id_aa64mmfr0 = 0x00001124; |
f11b452b EI |
249 | cpu->dbgdidr = 0x3516d000; |
250 | cpu->clidr = 0x0a200023; | |
251 | cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ | |
252 | cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ | |
253 | cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ | |
254 | cpu->dcz_blocksize = 4; /* 64 bytes */ | |
255 | cpu->gic_num_lrs = 4; | |
256 | cpu->gic_vpribits = 5; | |
257 | cpu->gic_vprebits = 5; | |
258 | define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | |
e3531026 PC |
259 | } |
260 | ||
adf92eab RH |
261 | static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, |
262 | void *opaque, Error **errp) | |
263 | { | |
264 | ARMCPU *cpu = ARM_CPU(obj); | |
265 | visit_type_uint32(v, name, &cpu->sve_max_vq, errp); | |
266 | } | |
267 | ||
268 | static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name, | |
269 | void *opaque, Error **errp) | |
270 | { | |
271 | ARMCPU *cpu = ARM_CPU(obj); | |
272 | Error *err = NULL; | |
273 | ||
274 | visit_type_uint32(v, name, &cpu->sve_max_vq, &err); | |
275 | ||
276 | if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) { | |
277 | error_setg(&err, "unsupported SVE vector length"); | |
278 | error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n", | |
279 | ARM_MAX_VQ); | |
280 | } | |
281 | error_propagate(errp, err); | |
282 | } | |
283 | ||
bab52d4b PM |
284 | /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); |
285 | * otherwise, a CPU with as many features enabled as our emulation supports. | |
286 | * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; | |
287 | * this only needs to handle 64 bits. | |
288 | */ | |
289 | static void aarch64_max_initfn(Object *obj) | |
290 | { | |
291 | ARMCPU *cpu = ARM_CPU(obj); | |
292 | ||
293 | if (kvm_enabled()) { | |
294 | kvm_arm_set_cpu_features_from_host(cpu); | |
295 | } else { | |
962fcbf2 RH |
296 | uint64_t t; |
297 | uint32_t u; | |
bab52d4b | 298 | aarch64_a57_initfn(obj); |
962fcbf2 RH |
299 | |
300 | t = cpu->isar.id_aa64isar0; | |
301 | t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ | |
302 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); | |
303 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ | |
304 | t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); | |
305 | t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); | |
306 | t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); | |
307 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); | |
308 | t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); | |
309 | t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); | |
310 | t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); | |
991c0599 | 311 | t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); |
b89d9c98 | 312 | t = FIELD_DP64(t, ID_AA64ISAR0, TS, 1); |
962fcbf2 RH |
313 | cpu->isar.id_aa64isar0 = t; |
314 | ||
315 | t = cpu->isar.id_aa64isar1; | |
6c1f6f27 | 316 | t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); |
962fcbf2 | 317 | t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); |
1ce32e47 RH |
318 | t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */ |
319 | t = FIELD_DP64(t, ID_AA64ISAR1, API, 0); | |
320 | t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); | |
321 | t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); | |
9888bd1e | 322 | t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); |
cb570bd3 | 323 | t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); |
962fcbf2 RH |
324 | cpu->isar.id_aa64isar1 = t; |
325 | ||
cd208a1c RH |
326 | t = cpu->isar.id_aa64pfr0; |
327 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | |
5763190f RH |
328 | t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); |
329 | t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); | |
cd208a1c RH |
330 | cpu->isar.id_aa64pfr0 = t; |
331 | ||
a15daafa RH |
332 | t = cpu->isar.id_aa64pfr1; |
333 | t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); | |
334 | cpu->isar.id_aa64pfr1 = t; | |
335 | ||
037c13c5 RH |
336 | t = cpu->isar.id_aa64mmfr1; |
337 | t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ | |
2d7137c1 | 338 | t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); |
037c13c5 RH |
339 | cpu->isar.id_aa64mmfr1 = t; |
340 | ||
962fcbf2 RH |
341 | /* Replicate the same data to the 32-bit id registers. */ |
342 | u = cpu->isar.id_isar5; | |
343 | u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ | |
344 | u = FIELD_DP32(u, ID_ISAR5, SHA1, 1); | |
345 | u = FIELD_DP32(u, ID_ISAR5, SHA2, 1); | |
346 | u = FIELD_DP32(u, ID_ISAR5, CRC32, 1); | |
347 | u = FIELD_DP32(u, ID_ISAR5, RDM, 1); | |
348 | u = FIELD_DP32(u, ID_ISAR5, VCMA, 1); | |
349 | cpu->isar.id_isar5 = u; | |
350 | ||
351 | u = cpu->isar.id_isar6; | |
6c1f6f27 | 352 | u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1); |
962fcbf2 | 353 | u = FIELD_DP32(u, ID_ISAR6, DP, 1); |
991c0599 | 354 | u = FIELD_DP32(u, ID_ISAR6, FHM, 1); |
9888bd1e | 355 | u = FIELD_DP32(u, ID_ISAR6, SB, 1); |
cb570bd3 | 356 | u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); |
962fcbf2 RH |
357 | cpu->isar.id_isar6 = u; |
358 | ||
5763190f RH |
359 | /* |
360 | * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet, | |
361 | * so do not set MVFR1.FPHP. Strictly speaking this is not legal, | |
362 | * but it is also not legal to enable SVE without support for FP16, | |
363 | * and enabling SVE in system mode is more useful in the short term. | |
a0032cc5 | 364 | */ |
5763190f RH |
365 | |
366 | #ifdef CONFIG_USER_ONLY | |
a0032cc5 PM |
367 | /* For usermode -cpu max we can use a larger and more efficient DCZ |
368 | * blocksize since we don't have to follow what the hardware does. | |
bab52d4b | 369 | */ |
a0032cc5 PM |
370 | cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ |
371 | cpu->dcz_blocksize = 7; /* 512 bytes */ | |
372 | #endif | |
adf92eab RH |
373 | |
374 | cpu->sve_max_vq = ARM_MAX_VQ; | |
375 | object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq, | |
376 | cpu_max_set_sve_vq, NULL, NULL, &error_fatal); | |
bab52d4b PM |
377 | } |
378 | } | |
379 | ||
51e5ef45 | 380 | struct ARMCPUInfo { |
d14d42f1 PM |
381 | const char *name; |
382 | void (*initfn)(Object *obj); | |
383 | void (*class_init)(ObjectClass *oc, void *data); | |
51e5ef45 | 384 | }; |
d14d42f1 PM |
385 | |
386 | static const ARMCPUInfo aarch64_cpus[] = { | |
cb1fa941 | 387 | { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, |
e3531026 | 388 | { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, |
f11b452b | 389 | { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, |
bab52d4b | 390 | { .name = "max", .initfn = aarch64_max_initfn }, |
83e6813a | 391 | { .name = NULL } |
d14d42f1 PM |
392 | }; |
393 | ||
fb8d6c24 GB |
394 | static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) |
395 | { | |
396 | ARMCPU *cpu = ARM_CPU(obj); | |
397 | ||
398 | return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
399 | } | |
400 | ||
401 | static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) | |
402 | { | |
403 | ARMCPU *cpu = ARM_CPU(obj); | |
404 | ||
405 | /* At this time, this property is only allowed if KVM is enabled. This | |
406 | * restriction allows us to avoid fixing up functionality that assumes a | |
407 | * uniform execution state like do_interrupt. | |
408 | */ | |
409 | if (!kvm_enabled()) { | |
410 | error_setg(errp, "'aarch64' feature cannot be disabled " | |
411 | "unless KVM is enabled"); | |
412 | return; | |
413 | } | |
414 | ||
415 | if (value == false) { | |
416 | unset_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
417 | } else { | |
418 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
419 | } | |
420 | } | |
421 | ||
d14d42f1 PM |
422 | static void aarch64_cpu_initfn(Object *obj) |
423 | { | |
fb8d6c24 GB |
424 | object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, |
425 | aarch64_cpu_set_aarch64, NULL); | |
426 | object_property_set_description(obj, "aarch64", | |
427 | "Set on/off to enable/disable aarch64 " | |
428 | "execution state ", | |
429 | NULL); | |
d14d42f1 PM |
430 | } |
431 | ||
432 | static void aarch64_cpu_finalizefn(Object *obj) | |
433 | { | |
434 | } | |
435 | ||
b3820e6c DH |
436 | static gchar *aarch64_gdb_arch_name(CPUState *cs) |
437 | { | |
438 | return g_strdup("aarch64"); | |
439 | } | |
440 | ||
d14d42f1 PM |
441 | static void aarch64_cpu_class_init(ObjectClass *oc, void *data) |
442 | { | |
14ade10f AG |
443 | CPUClass *cc = CPU_CLASS(oc); |
444 | ||
e8925712 | 445 | cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; |
96c04212 AG |
446 | cc->gdb_read_register = aarch64_cpu_gdb_read_register; |
447 | cc->gdb_write_register = aarch64_cpu_gdb_write_register; | |
448 | cc->gdb_num_core_regs = 34; | |
449 | cc->gdb_core_xml_file = "aarch64-core.xml"; | |
b3820e6c | 450 | cc->gdb_arch_name = aarch64_gdb_arch_name; |
d14d42f1 PM |
451 | } |
452 | ||
51e5ef45 MAL |
453 | static void aarch64_cpu_instance_init(Object *obj) |
454 | { | |
455 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj); | |
456 | ||
457 | acc->info->initfn(obj); | |
458 | arm_cpu_post_init(obj); | |
459 | } | |
460 | ||
461 | static void cpu_register_class_init(ObjectClass *oc, void *data) | |
462 | { | |
463 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
464 | ||
465 | acc->info = data; | |
466 | } | |
467 | ||
d14d42f1 PM |
468 | static void aarch64_cpu_register(const ARMCPUInfo *info) |
469 | { | |
470 | TypeInfo type_info = { | |
471 | .parent = TYPE_AARCH64_CPU, | |
472 | .instance_size = sizeof(ARMCPU), | |
51e5ef45 | 473 | .instance_init = aarch64_cpu_instance_init, |
d14d42f1 | 474 | .class_size = sizeof(ARMCPUClass), |
51e5ef45 MAL |
475 | .class_init = info->class_init ?: cpu_register_class_init, |
476 | .class_data = (void *)info, | |
d14d42f1 PM |
477 | }; |
478 | ||
479 | type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); | |
480 | type_register(&type_info); | |
481 | g_free((void *)type_info.name); | |
482 | } | |
483 | ||
484 | static const TypeInfo aarch64_cpu_type_info = { | |
485 | .name = TYPE_AARCH64_CPU, | |
486 | .parent = TYPE_ARM_CPU, | |
487 | .instance_size = sizeof(ARMCPU), | |
488 | .instance_init = aarch64_cpu_initfn, | |
489 | .instance_finalize = aarch64_cpu_finalizefn, | |
490 | .abstract = true, | |
491 | .class_size = sizeof(AArch64CPUClass), | |
492 | .class_init = aarch64_cpu_class_init, | |
493 | }; | |
494 | ||
495 | static void aarch64_cpu_register_types(void) | |
496 | { | |
83e6813a | 497 | const ARMCPUInfo *info = aarch64_cpus; |
d14d42f1 PM |
498 | |
499 | type_register_static(&aarch64_cpu_type_info); | |
83e6813a PM |
500 | |
501 | while (info->name) { | |
502 | aarch64_cpu_register(info); | |
503 | info++; | |
d14d42f1 PM |
504 | } |
505 | } | |
506 | ||
507 | type_init(aarch64_cpu_register_types) |