]> git.proxmox.com Git - mirror_qemu.git/blame - target/arm/cpu_tcg.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'pull-target-arm-20220509' of https://git.linaro.org/people/pmaydell/qemu...
[mirror_qemu.git] / target / arm / cpu_tcg.c
CommitLineData
2465b07c
PMD		 1/*
2 * QEMU ARM TCG CPUs.
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This code is licensed under the GNU GPL v2 or later.
7 *
8 * SPDX-License-Identifier: GPL-2.0-or-later
9 */
10
11#include "qemu/osdep.h"
12#include "cpu.h"
78271684
CF		 13#ifdef CONFIG_TCG
14#include "hw/core/tcg-cpu-ops.h"
15#endif /* CONFIG_TCG */
2465b07c 16#include "internals.h"
6e937ba7 17#include "target/arm/idau.h"
80485d88
PMD		 18#if !defined(CONFIG_USER_ONLY)
19#include "hw/boards.h"
20#endif
cf7c6d10 21#include "cpregs.h"
2465b07c 22
b6f8b358
RH		 23
24/* Share AArch32 -cpu max features with AArch64. */
25void aa32_max_features(ARMCPU *cpu)
26{
27 uint32_t t;
28
29 /* Add additional features supported by QEMU */
30 t = cpu->isar.id_isar5;
ef696cfb
RH		 31 t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
32 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
33 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
b6f8b358 34 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
ef696cfb
RH		 35 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
36 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
b6f8b358
RH		 37 cpu->isar.id_isar5 = t;
38
39 t = cpu->isar.id_isar6;
ef696cfb
RH		 40 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
41 t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
42 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
43 t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
44 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
45 t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
46 t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
b6f8b358
RH		 47 cpu->isar.id_isar6 = t;
48
49 t = cpu->isar.mvfr1;
ef696cfb
RH		 50 t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
51 t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
b6f8b358
RH		 52 cpu->isar.mvfr1 = t;
53
54 t = cpu->isar.mvfr2;
ef696cfb
RH		 55 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
56 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
b6f8b358
RH		 57 cpu->isar.mvfr2 = t;
58
59 t = cpu->isar.id_mmfr3;
ef696cfb 60 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
b6f8b358
RH		 61 cpu->isar.id_mmfr3 = t;
62
63 t = cpu->isar.id_mmfr4;
ef696cfb
RH		 64 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */
65 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
66 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
67 t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX*/
b6f8b358
RH		 68 cpu->isar.id_mmfr4 = t;
69
70 t = cpu->isar.id_pfr0;
74b17e16 71 t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
ef696cfb 72 t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
e95c74c5 73 t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
b6f8b358
RH		 74 cpu->isar.id_pfr0 = t;
75
76 t = cpu->isar.id_pfr2;
3082b86b 77 t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
ef696cfb 78 t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
b6f8b358
RH		 79 cpu->isar.id_pfr2 = t;
80
81 t = cpu->isar.id_dfr0;
8fc756b6
RH		 82 t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */
83 t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */
ef696cfb 84 t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */
b6f8b358
RH		 85 cpu->isar.id_dfr0 = t;
86}
87
7c1aaf98
RH		 88#ifndef CONFIG_USER_ONLY
89static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
90{
91 ARMCPU *cpu = env_archcpu(env);
92
93 /* Number of cores is in [25:24]; otherwise we RAZ */
94 return (cpu->core_count - 1) << 24;
95}
96
97static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
98 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
99 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
100 .access = PL1_RW, .readfn = l2ctlr_read,
101 .writefn = arm_cp_write_ignore },
102 { .name = "L2CTLR",
103 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
104 .access = PL1_RW, .readfn = l2ctlr_read,
105 .writefn = arm_cp_write_ignore },
106 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
107 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
108 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
109 { .name = "L2ECTLR",
110 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
111 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
112 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
113 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
114 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
115 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
116 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
117 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
118 { .name = "CPUACTLR",
119 .cp = 15, .opc1 = 0, .crm = 15,
120 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
121 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
122 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
123 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
124 { .name = "CPUECTLR",
125 .cp = 15, .opc1 = 1, .crm = 15,
126 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
127 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
128 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
129 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
130 { .name = "CPUMERRSR",
131 .cp = 15, .opc1 = 2, .crm = 15,
132 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
133 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
134 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
135 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
136 { .name = "L2MERRSR",
137 .cp = 15, .opc1 = 3, .crm = 15,
138 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
139};
140
141void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
142{
143 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
144}
145#endif /* !CONFIG_USER_ONLY */
146
2465b07c
PMD		 147/* CPU models. These are not needed for the AArch64 linux-user build. */
148#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
149
083afd18 150#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
2465b07c
PMD		 151static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
152{
153 CPUClass *cc = CPU_GET_CLASS(cs);
154 ARMCPU *cpu = ARM_CPU(cs);
155 CPUARMState *env = &cpu->env;
156 bool ret = false;
157
158 /*
159 * ARMv7-M interrupt masking works differently than -A or -R.
160 * There is no FIQ/IRQ distinction. Instead of I and F bits
161 * masking FIQ and IRQ interrupts, an exception is taken only
162 * if it is higher priority than the current execution priority
163 * (which depends on state like BASEPRI, FAULTMASK and the
164 * currently active exception).
165 */
166 if (interrupt_request & CPU_INTERRUPT_HARD
167 && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
168 cs->exception_index = EXCP_IRQ;
78271684 169 cc->tcg_ops->do_interrupt(cs);
2465b07c
PMD		 170 ret = true;
171 }
172 return ret;
173}
083afd18 174#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
2465b07c
PMD		 175
176static void arm926_initfn(Object *obj)
177{
178 ARMCPU *cpu = ARM_CPU(obj);
179
180 cpu->dtb_compatible = "arm,arm926";
181 set_feature(&cpu->env, ARM_FEATURE_V5);
182 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
183 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
184 cpu->midr = 0x41069265;
185 cpu->reset_fpsid = 0x41011090;
186 cpu->ctr = 0x1dd20d2;
187 cpu->reset_sctlr = 0x00090078;
188
189 /*
190 * ARMv5 does not have the ID_ISAR registers, but we can still
191 * set the field to indicate Jazelle support within QEMU.
192 */
193 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
194 /*
195 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
196 * support even though ARMv5 doesn't have this register.
197 */
198 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
199 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
200 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
201}
202
203static void arm946_initfn(Object *obj)
204{
205 ARMCPU *cpu = ARM_CPU(obj);
206
207 cpu->dtb_compatible = "arm,arm946";
208 set_feature(&cpu->env, ARM_FEATURE_V5);
209 set_feature(&cpu->env, ARM_FEATURE_PMSA);
210 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
211 cpu->midr = 0x41059461;
212 cpu->ctr = 0x0f004006;
213 cpu->reset_sctlr = 0x00000078;
214}
215
216static void arm1026_initfn(Object *obj)
217{
218 ARMCPU *cpu = ARM_CPU(obj);
219
220 cpu->dtb_compatible = "arm,arm1026";
221 set_feature(&cpu->env, ARM_FEATURE_V5);
222 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
223 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
224 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
225 cpu->midr = 0x4106a262;
226 cpu->reset_fpsid = 0x410110a0;
227 cpu->ctr = 0x1dd20d2;
228 cpu->reset_sctlr = 0x00090078;
229 cpu->reset_auxcr = 1;
230
231 /*
232 * ARMv5 does not have the ID_ISAR registers, but we can still
233 * set the field to indicate Jazelle support within QEMU.
234 */
235 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
236 /*
237 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
238 * support even though ARMv5 doesn't have this register.
239 */
240 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
241 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
242 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
243
244 {
245 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
246 ARMCPRegInfo ifar = {
247 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
248 .access = PL1_RW,
249 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
250 .resetvalue = 0
251 };
252 define_one_arm_cp_reg(cpu, &ifar);
253 }
254}
255
256static void arm1136_r2_initfn(Object *obj)
257{
258 ARMCPU *cpu = ARM_CPU(obj);
259 /*
260 * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
261 * older core than plain "arm1136". In particular this does not
262 * have the v6K features.
263 * These ID register values are correct for 1136 but may be wrong
264 * for 1136_r2 (in particular r0p2 does not actually implement most
265 * of the ID registers).
266 */
267
268 cpu->dtb_compatible = "arm,arm1136";
269 set_feature(&cpu->env, ARM_FEATURE_V6);
270 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
271 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
272 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
273 cpu->midr = 0x4107b362;
274 cpu->reset_fpsid = 0x410120b4;
275 cpu->isar.mvfr0 = 0x11111111;
276 cpu->isar.mvfr1 = 0x00000000;
277 cpu->ctr = 0x1dd20d2;
278 cpu->reset_sctlr = 0x00050078;
8a130a7b
PM		 279 cpu->isar.id_pfr0 = 0x111;
280 cpu->isar.id_pfr1 = 0x1;
2465b07c
PMD		 281 cpu->isar.id_dfr0 = 0x2;
282 cpu->id_afr0 = 0x3;
283 cpu->isar.id_mmfr0 = 0x01130003;
284 cpu->isar.id_mmfr1 = 0x10030302;
285 cpu->isar.id_mmfr2 = 0x01222110;
286 cpu->isar.id_isar0 = 0x00140011;
287 cpu->isar.id_isar1 = 0x12002111;
288 cpu->isar.id_isar2 = 0x11231111;
289 cpu->isar.id_isar3 = 0x01102131;
290 cpu->isar.id_isar4 = 0x141;
291 cpu->reset_auxcr = 7;
292}
293
294static void arm1136_initfn(Object *obj)
295{
296 ARMCPU *cpu = ARM_CPU(obj);
297
298 cpu->dtb_compatible = "arm,arm1136";
299 set_feature(&cpu->env, ARM_FEATURE_V6K);
300 set_feature(&cpu->env, ARM_FEATURE_V6);
301 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
302 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
303 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
304 cpu->midr = 0x4117b363;
305 cpu->reset_fpsid = 0x410120b4;
306 cpu->isar.mvfr0 = 0x11111111;
307 cpu->isar.mvfr1 = 0x00000000;
308 cpu->ctr = 0x1dd20d2;
309 cpu->reset_sctlr = 0x00050078;
8a130a7b
PM		 310 cpu->isar.id_pfr0 = 0x111;
311 cpu->isar.id_pfr1 = 0x1;
2465b07c
PMD		 312 cpu->isar.id_dfr0 = 0x2;
313 cpu->id_afr0 = 0x3;
314 cpu->isar.id_mmfr0 = 0x01130003;
315 cpu->isar.id_mmfr1 = 0x10030302;
316 cpu->isar.id_mmfr2 = 0x01222110;
317 cpu->isar.id_isar0 = 0x00140011;
318 cpu->isar.id_isar1 = 0x12002111;
319 cpu->isar.id_isar2 = 0x11231111;
320 cpu->isar.id_isar3 = 0x01102131;
321 cpu->isar.id_isar4 = 0x141;
322 cpu->reset_auxcr = 7;
323}
324
325static void arm1176_initfn(Object *obj)
326{
327 ARMCPU *cpu = ARM_CPU(obj);
328
329 cpu->dtb_compatible = "arm,arm1176";
330 set_feature(&cpu->env, ARM_FEATURE_V6K);
331 set_feature(&cpu->env, ARM_FEATURE_VAPA);
332 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
333 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
334 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
335 set_feature(&cpu->env, ARM_FEATURE_EL3);
336 cpu->midr = 0x410fb767;
337 cpu->reset_fpsid = 0x410120b5;
338 cpu->isar.mvfr0 = 0x11111111;
339 cpu->isar.mvfr1 = 0x00000000;
340 cpu->ctr = 0x1dd20d2;
341 cpu->reset_sctlr = 0x00050078;
8a130a7b
PM		 342 cpu->isar.id_pfr0 = 0x111;
343 cpu->isar.id_pfr1 = 0x11;
2465b07c
PMD		 344 cpu->isar.id_dfr0 = 0x33;
345 cpu->id_afr0 = 0;
346 cpu->isar.id_mmfr0 = 0x01130003;
347 cpu->isar.id_mmfr1 = 0x10030302;
348 cpu->isar.id_mmfr2 = 0x01222100;
349 cpu->isar.id_isar0 = 0x0140011;
350 cpu->isar.id_isar1 = 0x12002111;
351 cpu->isar.id_isar2 = 0x11231121;
352 cpu->isar.id_isar3 = 0x01102131;
353 cpu->isar.id_isar4 = 0x01141;
354 cpu->reset_auxcr = 7;
355}
356
357static void arm11mpcore_initfn(Object *obj)
358{
359 ARMCPU *cpu = ARM_CPU(obj);
360
361 cpu->dtb_compatible = "arm,arm11mpcore";
362 set_feature(&cpu->env, ARM_FEATURE_V6K);
363 set_feature(&cpu->env, ARM_FEATURE_VAPA);
364 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
365 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
366 cpu->midr = 0x410fb022;
367 cpu->reset_fpsid = 0x410120b4;
368 cpu->isar.mvfr0 = 0x11111111;
369 cpu->isar.mvfr1 = 0x00000000;
370 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
8a130a7b
PM		 371 cpu->isar.id_pfr0 = 0x111;
372 cpu->isar.id_pfr1 = 0x1;
2465b07c
PMD		 373 cpu->isar.id_dfr0 = 0;
374 cpu->id_afr0 = 0x2;
375 cpu->isar.id_mmfr0 = 0x01100103;
376 cpu->isar.id_mmfr1 = 0x10020302;
377 cpu->isar.id_mmfr2 = 0x01222000;
378 cpu->isar.id_isar0 = 0x00100011;
379 cpu->isar.id_isar1 = 0x12002111;
380 cpu->isar.id_isar2 = 0x11221011;
381 cpu->isar.id_isar3 = 0x01102131;
382 cpu->isar.id_isar4 = 0x141;
383 cpu->reset_auxcr = 1;
384}
385
80485d88
PMD		 386static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
387 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
388 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
389 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
390 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
80485d88
PMD		 391};
392
393static void cortex_a8_initfn(Object *obj)
394{
395 ARMCPU *cpu = ARM_CPU(obj);
396
397 cpu->dtb_compatible = "arm,cortex-a8";
398 set_feature(&cpu->env, ARM_FEATURE_V7);
399 set_feature(&cpu->env, ARM_FEATURE_NEON);
400 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
401 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
402 set_feature(&cpu->env, ARM_FEATURE_EL3);
403 cpu->midr = 0x410fc080;
404 cpu->reset_fpsid = 0x410330c0;
405 cpu->isar.mvfr0 = 0x11110222;
406 cpu->isar.mvfr1 = 0x00011111;
407 cpu->ctr = 0x82048004;
408 cpu->reset_sctlr = 0x00c50078;
409 cpu->isar.id_pfr0 = 0x1031;
410 cpu->isar.id_pfr1 = 0x11;
411 cpu->isar.id_dfr0 = 0x400;
412 cpu->id_afr0 = 0;
413 cpu->isar.id_mmfr0 = 0x31100003;
414 cpu->isar.id_mmfr1 = 0x20000000;
415 cpu->isar.id_mmfr2 = 0x01202000;
416 cpu->isar.id_mmfr3 = 0x11;
417 cpu->isar.id_isar0 = 0x00101111;
418 cpu->isar.id_isar1 = 0x12112111;
419 cpu->isar.id_isar2 = 0x21232031;
420 cpu->isar.id_isar3 = 0x11112131;
421 cpu->isar.id_isar4 = 0x00111142;
422 cpu->isar.dbgdidr = 0x15141000;
423 cpu->clidr = (1 << 27) | (2 << 24) | 3;
424 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
425 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
426 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
427 cpu->reset_auxcr = 2;
428 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
429}
430
431static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
432 /*
433 * power_control should be set to maximum latency. Again,
434 * default to 0 and set by private hook
435 */
436 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
437 .access = PL1_RW, .resetvalue = 0,
438 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
439 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
440 .access = PL1_RW, .resetvalue = 0,
441 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
442 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
443 .access = PL1_RW, .resetvalue = 0,
444 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
445 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
446 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
447 /* TLB lockdown control */
448 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
449 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
450 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
451 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
452 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
453 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
454 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
455 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
456 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
457 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
80485d88
PMD		 458};
459
460static void cortex_a9_initfn(Object *obj)
461{
462 ARMCPU *cpu = ARM_CPU(obj);
463
464 cpu->dtb_compatible = "arm,cortex-a9";
465 set_feature(&cpu->env, ARM_FEATURE_V7);
466 set_feature(&cpu->env, ARM_FEATURE_NEON);
467 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
468 set_feature(&cpu->env, ARM_FEATURE_EL3);
469 /*
470 * Note that A9 supports the MP extensions even for
471 * A9UP and single-core A9MP (which are both different
472 * and valid configurations; we don't model A9UP).
473 */
474 set_feature(&cpu->env, ARM_FEATURE_V7MP);
475 set_feature(&cpu->env, ARM_FEATURE_CBAR);
476 cpu->midr = 0x410fc090;
477 cpu->reset_fpsid = 0x41033090;
478 cpu->isar.mvfr0 = 0x11110222;
479 cpu->isar.mvfr1 = 0x01111111;
480 cpu->ctr = 0x80038003;
481 cpu->reset_sctlr = 0x00c50078;
482 cpu->isar.id_pfr0 = 0x1031;
483 cpu->isar.id_pfr1 = 0x11;
484 cpu->isar.id_dfr0 = 0x000;
485 cpu->id_afr0 = 0;
486 cpu->isar.id_mmfr0 = 0x00100103;
487 cpu->isar.id_mmfr1 = 0x20000000;
488 cpu->isar.id_mmfr2 = 0x01230000;
489 cpu->isar.id_mmfr3 = 0x00002111;
490 cpu->isar.id_isar0 = 0x00101111;
491 cpu->isar.id_isar1 = 0x13112111;
492 cpu->isar.id_isar2 = 0x21232041;
493 cpu->isar.id_isar3 = 0x11112131;
494 cpu->isar.id_isar4 = 0x00111142;
495 cpu->isar.dbgdidr = 0x35141000;
496 cpu->clidr = (1 << 27) | (1 << 24) | 3;
497 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
498 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
499 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
500}
501
502#ifndef CONFIG_USER_ONLY
503static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
504{
505 MachineState *ms = MACHINE(qdev_get_machine());
506
507 /*
508 * Linux wants the number of processors from here.
509 * Might as well set the interrupt-controller bit too.
510 */
511 return ((ms->smp.cpus - 1) << 24) | (1 << 23);
512}
513#endif
514
515static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
516#ifndef CONFIG_USER_ONLY
517 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
518 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
519 .writefn = arm_cp_write_ignore, },
520#endif
521 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
522 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
80485d88
PMD		 523};
524
525static void cortex_a7_initfn(Object *obj)
526{
527 ARMCPU *cpu = ARM_CPU(obj);
528
529 cpu->dtb_compatible = "arm,cortex-a7";
530 set_feature(&cpu->env, ARM_FEATURE_V7VE);
531 set_feature(&cpu->env, ARM_FEATURE_NEON);
532 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
533 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
534 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
535 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
536 set_feature(&cpu->env, ARM_FEATURE_EL2);
537 set_feature(&cpu->env, ARM_FEATURE_EL3);
538 set_feature(&cpu->env, ARM_FEATURE_PMU);
539 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
540 cpu->midr = 0x410fc075;
541 cpu->reset_fpsid = 0x41023075;
542 cpu->isar.mvfr0 = 0x10110222;
543 cpu->isar.mvfr1 = 0x11111111;
544 cpu->ctr = 0x84448003;
545 cpu->reset_sctlr = 0x00c50078;
546 cpu->isar.id_pfr0 = 0x00001131;
547 cpu->isar.id_pfr1 = 0x00011011;
548 cpu->isar.id_dfr0 = 0x02010555;
549 cpu->id_afr0 = 0x00000000;
550 cpu->isar.id_mmfr0 = 0x10101105;
551 cpu->isar.id_mmfr1 = 0x40000000;
552 cpu->isar.id_mmfr2 = 0x01240000;
553 cpu->isar.id_mmfr3 = 0x02102211;
554 /*
555 * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
556 * table 4-41 gives 0x02101110, which includes the arm div insns.
557 */
558 cpu->isar.id_isar0 = 0x02101110;
559 cpu->isar.id_isar1 = 0x13112111;
560 cpu->isar.id_isar2 = 0x21232041;
561 cpu->isar.id_isar3 = 0x11112131;
562 cpu->isar.id_isar4 = 0x10011142;
563 cpu->isar.dbgdidr = 0x3515f005;
564 cpu->clidr = 0x0a200023;
565 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
566 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
567 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
568 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
569}
570
571static void cortex_a15_initfn(Object *obj)
572{
573 ARMCPU *cpu = ARM_CPU(obj);
574
575 cpu->dtb_compatible = "arm,cortex-a15";
576 set_feature(&cpu->env, ARM_FEATURE_V7VE);
577 set_feature(&cpu->env, ARM_FEATURE_NEON);
578 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
579 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
580 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
581 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
582 set_feature(&cpu->env, ARM_FEATURE_EL2);
583 set_feature(&cpu->env, ARM_FEATURE_EL3);
584 set_feature(&cpu->env, ARM_FEATURE_PMU);
585 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
586 cpu->midr = 0x412fc0f1;
587 cpu->reset_fpsid = 0x410430f0;
588 cpu->isar.mvfr0 = 0x10110222;
589 cpu->isar.mvfr1 = 0x11111111;
590 cpu->ctr = 0x8444c004;
591 cpu->reset_sctlr = 0x00c50078;
592 cpu->isar.id_pfr0 = 0x00001131;
593 cpu->isar.id_pfr1 = 0x00011011;
594 cpu->isar.id_dfr0 = 0x02010555;
595 cpu->id_afr0 = 0x00000000;
596 cpu->isar.id_mmfr0 = 0x10201105;
597 cpu->isar.id_mmfr1 = 0x20000000;
598 cpu->isar.id_mmfr2 = 0x01240000;
599 cpu->isar.id_mmfr3 = 0x02102211;
600 cpu->isar.id_isar0 = 0x02101110;
601 cpu->isar.id_isar1 = 0x13112111;
602 cpu->isar.id_isar2 = 0x21232041;
603 cpu->isar.id_isar3 = 0x11112131;
604 cpu->isar.id_isar4 = 0x10011142;
605 cpu->isar.dbgdidr = 0x3515f021;
606 cpu->clidr = 0x0a200023;
607 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
608 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
609 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
610 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
611}
612
2465b07c
PMD		 613static void cortex_m0_initfn(Object *obj)
614{
615 ARMCPU *cpu = ARM_CPU(obj);
616 set_feature(&cpu->env, ARM_FEATURE_V6);
617 set_feature(&cpu->env, ARM_FEATURE_M);
618
619 cpu->midr = 0x410cc200;
51cb228a
PM		 620
621 /*
622 * These ID register values are not guest visible, because
623 * we do not implement the Main Extension. They must be set
624 * to values corresponding to the Cortex-M0's implemented
625 * features, because QEMU generally controls its emulation
626 * by looking at ID register fields. We use the same values as
627 * for the M3.
628 */
629 cpu->isar.id_pfr0 = 0x00000030;
630 cpu->isar.id_pfr1 = 0x00000200;
631 cpu->isar.id_dfr0 = 0x00100000;
632 cpu->id_afr0 = 0x00000000;
633 cpu->isar.id_mmfr0 = 0x00000030;
634 cpu->isar.id_mmfr1 = 0x00000000;
635 cpu->isar.id_mmfr2 = 0x00000000;
636 cpu->isar.id_mmfr3 = 0x00000000;
637 cpu->isar.id_isar0 = 0x01141110;
638 cpu->isar.id_isar1 = 0x02111000;
639 cpu->isar.id_isar2 = 0x21112231;
640 cpu->isar.id_isar3 = 0x01111110;
641 cpu->isar.id_isar4 = 0x01310102;
642 cpu->isar.id_isar5 = 0x00000000;
643 cpu->isar.id_isar6 = 0x00000000;
2465b07c
PMD		 644}
645
646static void cortex_m3_initfn(Object *obj)
647{
648 ARMCPU *cpu = ARM_CPU(obj);
649 set_feature(&cpu->env, ARM_FEATURE_V7);
650 set_feature(&cpu->env, ARM_FEATURE_M);
651 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
652 cpu->midr = 0x410fc231;
653 cpu->pmsav7_dregion = 8;
8a130a7b
PM		 654 cpu->isar.id_pfr0 = 0x00000030;
655 cpu->isar.id_pfr1 = 0x00000200;
2465b07c
PMD		 656 cpu->isar.id_dfr0 = 0x00100000;
657 cpu->id_afr0 = 0x00000000;
658 cpu->isar.id_mmfr0 = 0x00000030;
659 cpu->isar.id_mmfr1 = 0x00000000;
660 cpu->isar.id_mmfr2 = 0x00000000;
661 cpu->isar.id_mmfr3 = 0x00000000;
662 cpu->isar.id_isar0 = 0x01141110;
663 cpu->isar.id_isar1 = 0x02111000;
664 cpu->isar.id_isar2 = 0x21112231;
665 cpu->isar.id_isar3 = 0x01111110;
666 cpu->isar.id_isar4 = 0x01310102;
667 cpu->isar.id_isar5 = 0x00000000;
668 cpu->isar.id_isar6 = 0x00000000;
669}
670
671static void cortex_m4_initfn(Object *obj)
672{
673 ARMCPU *cpu = ARM_CPU(obj);
674
675 set_feature(&cpu->env, ARM_FEATURE_V7);
676 set_feature(&cpu->env, ARM_FEATURE_M);
677 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
678 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
679 cpu->midr = 0x410fc240; /* r0p0 */
680 cpu->pmsav7_dregion = 8;
681 cpu->isar.mvfr0 = 0x10110021;
682 cpu->isar.mvfr1 = 0x11000011;
683 cpu->isar.mvfr2 = 0x00000000;
8a130a7b
PM		 684 cpu->isar.id_pfr0 = 0x00000030;
685 cpu->isar.id_pfr1 = 0x00000200;
2465b07c
PMD		 686 cpu->isar.id_dfr0 = 0x00100000;
687 cpu->id_afr0 = 0x00000000;
688 cpu->isar.id_mmfr0 = 0x00000030;
689 cpu->isar.id_mmfr1 = 0x00000000;
690 cpu->isar.id_mmfr2 = 0x00000000;
691 cpu->isar.id_mmfr3 = 0x00000000;
692 cpu->isar.id_isar0 = 0x01141110;
693 cpu->isar.id_isar1 = 0x02111000;
694 cpu->isar.id_isar2 = 0x21112231;
695 cpu->isar.id_isar3 = 0x01111110;
696 cpu->isar.id_isar4 = 0x01310102;
697 cpu->isar.id_isar5 = 0x00000000;
698 cpu->isar.id_isar6 = 0x00000000;
699}
700
701static void cortex_m7_initfn(Object *obj)
702{
703 ARMCPU *cpu = ARM_CPU(obj);
704
705 set_feature(&cpu->env, ARM_FEATURE_V7);
706 set_feature(&cpu->env, ARM_FEATURE_M);
707 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
708 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
709 cpu->midr = 0x411fc272; /* r1p2 */
710 cpu->pmsav7_dregion = 8;
711 cpu->isar.mvfr0 = 0x10110221;
712 cpu->isar.mvfr1 = 0x12000011;
713 cpu->isar.mvfr2 = 0x00000040;
8a130a7b
PM		 714 cpu->isar.id_pfr0 = 0x00000030;
715 cpu->isar.id_pfr1 = 0x00000200;
2465b07c
PMD		 716 cpu->isar.id_dfr0 = 0x00100000;
717 cpu->id_afr0 = 0x00000000;
718 cpu->isar.id_mmfr0 = 0x00100030;
719 cpu->isar.id_mmfr1 = 0x00000000;
720 cpu->isar.id_mmfr2 = 0x01000000;
721 cpu->isar.id_mmfr3 = 0x00000000;
722 cpu->isar.id_isar0 = 0x01101110;
723 cpu->isar.id_isar1 = 0x02112000;
724 cpu->isar.id_isar2 = 0x20232231;
725 cpu->isar.id_isar3 = 0x01111131;
726 cpu->isar.id_isar4 = 0x01310132;
727 cpu->isar.id_isar5 = 0x00000000;
728 cpu->isar.id_isar6 = 0x00000000;
729}
730
731static void cortex_m33_initfn(Object *obj)
732{
733 ARMCPU *cpu = ARM_CPU(obj);
734
735 set_feature(&cpu->env, ARM_FEATURE_V8);
736 set_feature(&cpu->env, ARM_FEATURE_M);
737 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
738 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
739 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
740 cpu->midr = 0x410fd213; /* r0p3 */
741 cpu->pmsav7_dregion = 16;
742 cpu->sau_sregion = 8;
743 cpu->isar.mvfr0 = 0x10110021;
744 cpu->isar.mvfr1 = 0x11000011;
745 cpu->isar.mvfr2 = 0x00000040;
8a130a7b
PM		 746 cpu->isar.id_pfr0 = 0x00000030;
747 cpu->isar.id_pfr1 = 0x00000210;
2465b07c
PMD		 748 cpu->isar.id_dfr0 = 0x00200000;
749 cpu->id_afr0 = 0x00000000;
750 cpu->isar.id_mmfr0 = 0x00101F40;
751 cpu->isar.id_mmfr1 = 0x00000000;
752 cpu->isar.id_mmfr2 = 0x01000000;
753 cpu->isar.id_mmfr3 = 0x00000000;
754 cpu->isar.id_isar0 = 0x01101110;
755 cpu->isar.id_isar1 = 0x02212000;
756 cpu->isar.id_isar2 = 0x20232232;
757 cpu->isar.id_isar3 = 0x01111131;
758 cpu->isar.id_isar4 = 0x01310132;
759 cpu->isar.id_isar5 = 0x00000000;
760 cpu->isar.id_isar6 = 0x00000000;
761 cpu->clidr = 0x00000000;
762 cpu->ctr = 0x8000c000;
763}
764
590e05d6
PM		 765static void cortex_m55_initfn(Object *obj)
766{
767 ARMCPU *cpu = ARM_CPU(obj);
768
769 set_feature(&cpu->env, ARM_FEATURE_V8);
770 set_feature(&cpu->env, ARM_FEATURE_V8_1M);
771 set_feature(&cpu->env, ARM_FEATURE_M);
772 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
773 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
774 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
775 cpu->midr = 0x410fd221; /* r0p1 */
776 cpu->revidr = 0;
777 cpu->pmsav7_dregion = 16;
778 cpu->sau_sregion = 8;
d4cc1c21 779 /* These are the MVFR* values for the FPU + full MVE configuration */
590e05d6 780 cpu->isar.mvfr0 = 0x10110221;
d4cc1c21 781 cpu->isar.mvfr1 = 0x12100211;
590e05d6
PM		 782 cpu->isar.mvfr2 = 0x00000040;
783 cpu->isar.id_pfr0 = 0x20000030;
784 cpu->isar.id_pfr1 = 0x00000230;
785 cpu->isar.id_dfr0 = 0x10200000;
786 cpu->id_afr0 = 0x00000000;
787 cpu->isar.id_mmfr0 = 0x00111040;
788 cpu->isar.id_mmfr1 = 0x00000000;
789 cpu->isar.id_mmfr2 = 0x01000000;
790 cpu->isar.id_mmfr3 = 0x00000011;
791 cpu->isar.id_isar0 = 0x01103110;
792 cpu->isar.id_isar1 = 0x02212000;
793 cpu->isar.id_isar2 = 0x20232232;
794 cpu->isar.id_isar3 = 0x01111131;
795 cpu->isar.id_isar4 = 0x01310132;
796 cpu->isar.id_isar5 = 0x00000000;
797 cpu->isar.id_isar6 = 0x00000000;
798 cpu->clidr = 0x00000000; /* caches not implemented */
799 cpu->ctr = 0x8303c003;
800}
801
2465b07c
PMD		 802static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
803 /* Dummy the TCM region regs for the moment */
804 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
805 .access = PL1_RW, .type = ARM_CP_CONST },
806 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
807 .access = PL1_RW, .type = ARM_CP_CONST },
808 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
809 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
2465b07c
PMD		 810};
811
812static void cortex_r5_initfn(Object *obj)
813{
814 ARMCPU *cpu = ARM_CPU(obj);
815
816 set_feature(&cpu->env, ARM_FEATURE_V7);
817 set_feature(&cpu->env, ARM_FEATURE_V7MP);
818 set_feature(&cpu->env, ARM_FEATURE_PMSA);
819 set_feature(&cpu->env, ARM_FEATURE_PMU);
820 cpu->midr = 0x411fc153; /* r1p3 */
8a130a7b
PM		 821 cpu->isar.id_pfr0 = 0x0131;
822 cpu->isar.id_pfr1 = 0x001;
2465b07c
PMD		 823 cpu->isar.id_dfr0 = 0x010400;
824 cpu->id_afr0 = 0x0;
825 cpu->isar.id_mmfr0 = 0x0210030;
826 cpu->isar.id_mmfr1 = 0x00000000;
827 cpu->isar.id_mmfr2 = 0x01200000;
828 cpu->isar.id_mmfr3 = 0x0211;
829 cpu->isar.id_isar0 = 0x02101111;
830 cpu->isar.id_isar1 = 0x13112111;
831 cpu->isar.id_isar2 = 0x21232141;
832 cpu->isar.id_isar3 = 0x01112131;
833 cpu->isar.id_isar4 = 0x0010142;
834 cpu->isar.id_isar5 = 0x0;
835 cpu->isar.id_isar6 = 0x0;
836 cpu->mp_is_up = true;
837 cpu->pmsav7_dregion = 16;
838 define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
839}
840
841static void cortex_r5f_initfn(Object *obj)
842{
843 ARMCPU *cpu = ARM_CPU(obj);
844
845 cortex_r5_initfn(obj);
846 cpu->isar.mvfr0 = 0x10110221;
847 cpu->isar.mvfr1 = 0x00000011;
848}
849
850static void ti925t_initfn(Object *obj)
851{
852 ARMCPU *cpu = ARM_CPU(obj);
853 set_feature(&cpu->env, ARM_FEATURE_V4T);
854 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
855 cpu->midr = ARM_CPUID_TI925T;
856 cpu->ctr = 0x5109149;
857 cpu->reset_sctlr = 0x00000070;
858}
859
860static void sa1100_initfn(Object *obj)
861{
862 ARMCPU *cpu = ARM_CPU(obj);
863
864 cpu->dtb_compatible = "intel,sa1100";
865 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
866 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
867 cpu->midr = 0x4401A11B;
868 cpu->reset_sctlr = 0x00000070;
869}
870
871static void sa1110_initfn(Object *obj)
872{
873 ARMCPU *cpu = ARM_CPU(obj);
874 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
875 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
876 cpu->midr = 0x6901B119;
877 cpu->reset_sctlr = 0x00000070;
878}
879
880static void pxa250_initfn(Object *obj)
881{
882 ARMCPU *cpu = ARM_CPU(obj);
883
884 cpu->dtb_compatible = "marvell,xscale";
885 set_feature(&cpu->env, ARM_FEATURE_V5);
886 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
887 cpu->midr = 0x69052100;
888 cpu->ctr = 0xd172172;
889 cpu->reset_sctlr = 0x00000078;
890}
891
892static void pxa255_initfn(Object *obj)
893{
894 ARMCPU *cpu = ARM_CPU(obj);
895
896 cpu->dtb_compatible = "marvell,xscale";
897 set_feature(&cpu->env, ARM_FEATURE_V5);
898 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
899 cpu->midr = 0x69052d00;
900 cpu->ctr = 0xd172172;
901 cpu->reset_sctlr = 0x00000078;
902}
903
904static void pxa260_initfn(Object *obj)
905{
906 ARMCPU *cpu = ARM_CPU(obj);
907
908 cpu->dtb_compatible = "marvell,xscale";
909 set_feature(&cpu->env, ARM_FEATURE_V5);
910 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
911 cpu->midr = 0x69052903;
912 cpu->ctr = 0xd172172;
913 cpu->reset_sctlr = 0x00000078;
914}
915
916static void pxa261_initfn(Object *obj)
917{
918 ARMCPU *cpu = ARM_CPU(obj);
919
920 cpu->dtb_compatible = "marvell,xscale";
921 set_feature(&cpu->env, ARM_FEATURE_V5);
922 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
923 cpu->midr = 0x69052d05;
924 cpu->ctr = 0xd172172;
925 cpu->reset_sctlr = 0x00000078;
926}
927
928static void pxa262_initfn(Object *obj)
929{
930 ARMCPU *cpu = ARM_CPU(obj);
931
932 cpu->dtb_compatible = "marvell,xscale";
933 set_feature(&cpu->env, ARM_FEATURE_V5);
934 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
935 cpu->midr = 0x69052d06;
936 cpu->ctr = 0xd172172;
937 cpu->reset_sctlr = 0x00000078;
938}
939
940static void pxa270a0_initfn(Object *obj)
941{
942 ARMCPU *cpu = ARM_CPU(obj);
943
944 cpu->dtb_compatible = "marvell,xscale";
945 set_feature(&cpu->env, ARM_FEATURE_V5);
946 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
947 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
948 cpu->midr = 0x69054110;
949 cpu->ctr = 0xd172172;
950 cpu->reset_sctlr = 0x00000078;
951}
952
953static void pxa270a1_initfn(Object *obj)
954{
955 ARMCPU *cpu = ARM_CPU(obj);
956
957 cpu->dtb_compatible = "marvell,xscale";
958 set_feature(&cpu->env, ARM_FEATURE_V5);
959 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
960 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
961 cpu->midr = 0x69054111;
962 cpu->ctr = 0xd172172;
963 cpu->reset_sctlr = 0x00000078;
964}
965
966static void pxa270b0_initfn(Object *obj)
967{
968 ARMCPU *cpu = ARM_CPU(obj);
969
970 cpu->dtb_compatible = "marvell,xscale";
971 set_feature(&cpu->env, ARM_FEATURE_V5);
972 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
973 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
974 cpu->midr = 0x69054112;
975 cpu->ctr = 0xd172172;
976 cpu->reset_sctlr = 0x00000078;
977}
978
979static void pxa270b1_initfn(Object *obj)
980{
981 ARMCPU *cpu = ARM_CPU(obj);
982
983 cpu->dtb_compatible = "marvell,xscale";
984 set_feature(&cpu->env, ARM_FEATURE_V5);
985 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
986 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
987 cpu->midr = 0x69054113;
988 cpu->ctr = 0xd172172;
989 cpu->reset_sctlr = 0x00000078;
990}
991
992static void pxa270c0_initfn(Object *obj)
993{
994 ARMCPU *cpu = ARM_CPU(obj);
995
996 cpu->dtb_compatible = "marvell,xscale";
997 set_feature(&cpu->env, ARM_FEATURE_V5);
998 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
999 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1000 cpu->midr = 0x69054114;
1001 cpu->ctr = 0xd172172;
1002 cpu->reset_sctlr = 0x00000078;
1003}
1004
1005static void pxa270c5_initfn(Object *obj)
1006{
1007 ARMCPU *cpu = ARM_CPU(obj);
1008
1009 cpu->dtb_compatible = "marvell,xscale";
1010 set_feature(&cpu->env, ARM_FEATURE_V5);
1011 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1012 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1013 cpu->midr = 0x69054117;
1014 cpu->ctr = 0xd172172;
1015 cpu->reset_sctlr = 0x00000078;
1016}
1017
78271684 1018#ifdef CONFIG_TCG
11906557 1019static const struct TCGCPUOps arm_v7m_tcg_ops = {
78271684
CF		 1020 .initialize = arm_translate_init,
1021 .synchronize_from_tb = arm_cpu_synchronize_from_tb,
78271684
CF		 1022 .debug_excp_handler = arm_debug_excp_handler,
1023
9b12b6b4
RH		 1024#ifdef CONFIG_USER_ONLY
1025 .record_sigsegv = arm_cpu_record_sigsegv,
39a099ca 1026 .record_sigbus = arm_cpu_record_sigbus,
9b12b6b4
RH		 1027#else
1028 .tlb_fill = arm_cpu_tlb_fill,
083afd18 1029 .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
78271684
CF		 1030 .do_interrupt = arm_v7m_cpu_do_interrupt,
1031 .do_transaction_failed = arm_cpu_do_transaction_failed,
1032 .do_unaligned_access = arm_cpu_do_unaligned_access,
1033 .adjust_watchpoint_address = arm_adjust_watchpoint_address,
1034 .debug_check_watchpoint = arm_debug_check_watchpoint,
b00d86bc 1035 .debug_check_breakpoint = arm_debug_check_breakpoint,
78271684
CF		 1036#endif /* !CONFIG_USER_ONLY */
1037};
1038#endif /* CONFIG_TCG */
1039
2465b07c
PMD		 1040static void arm_v7m_class_init(ObjectClass *oc, void *data)
1041{
1042 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1043 CPUClass *cc = CPU_CLASS(oc);
1044
1045 acc->info = data;
48c1a3e3 1046#ifdef CONFIG_TCG
78271684 1047 cc->tcg_ops = &arm_v7m_tcg_ops;
48c1a3e3
EH		 1048#endif /* CONFIG_TCG */
1049
c888f7e0 1050 cc->gdb_core_xml_file = "arm-m-profile.xml";
2465b07c
PMD		 1051}
1052
80485d88
PMD		 1053#ifndef TARGET_AARCH64
1054/*
1055 * -cpu max: a CPU with as many features enabled as our emulation supports.
1056 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
1057 * this only needs to handle 32 bits, and need not care about KVM.
1058 */
1059static void arm_max_initfn(Object *obj)
1060{
1061 ARMCPU *cpu = ARM_CPU(obj);
1062
7e834daf
RH		 1063 /* aarch64_a57_initfn, advertising none of the aarch64 features */
1064 cpu->dtb_compatible = "arm,cortex-a57";
1065 set_feature(&cpu->env, ARM_FEATURE_V8);
1066 set_feature(&cpu->env, ARM_FEATURE_NEON);
1067 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1068 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1069 set_feature(&cpu->env, ARM_FEATURE_EL2);
1070 set_feature(&cpu->env, ARM_FEATURE_EL3);
1071 set_feature(&cpu->env, ARM_FEATURE_PMU);
1072 cpu->midr = 0x411fd070;
1073 cpu->revidr = 0x00000000;
1074 cpu->reset_fpsid = 0x41034070;
1075 cpu->isar.mvfr0 = 0x10110222;
1076 cpu->isar.mvfr1 = 0x12111111;
1077 cpu->isar.mvfr2 = 0x00000043;
1078 cpu->ctr = 0x8444c004;
1079 cpu->reset_sctlr = 0x00c50838;
1080 cpu->isar.id_pfr0 = 0x00000131;
1081 cpu->isar.id_pfr1 = 0x00011011;
1082 cpu->isar.id_dfr0 = 0x03010066;
1083 cpu->id_afr0 = 0x00000000;
1084 cpu->isar.id_mmfr0 = 0x10101105;
1085 cpu->isar.id_mmfr1 = 0x40000000;
1086 cpu->isar.id_mmfr2 = 0x01260000;
1087 cpu->isar.id_mmfr3 = 0x02102211;
1088 cpu->isar.id_isar0 = 0x02101110;
1089 cpu->isar.id_isar1 = 0x13112111;
1090 cpu->isar.id_isar2 = 0x21232042;
1091 cpu->isar.id_isar3 = 0x01112131;
1092 cpu->isar.id_isar4 = 0x00011142;
1093 cpu->isar.id_isar5 = 0x00011121;
1094 cpu->isar.id_isar6 = 0;
1095 cpu->isar.dbgdidr = 0x3516d000;
1096 cpu->clidr = 0x0a200023;
1097 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
1098 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
1099 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
1100 define_cortex_a72_a57_a53_cp_reginfo(cpu);
1101
b6f8b358 1102 aa32_max_features(cpu);
e14cc941 1103
80485d88
PMD		 1104#ifdef CONFIG_USER_ONLY
1105 /*
7e834daf
RH		 1106 * Break with true ARMv8 and add back old-style VFP short-vector support.
1107 * Only do this for user-mode, where -cpu max is the default, so that
1108 * older v6 and v7 programs are more likely to work without adjustment.
80485d88 1109 */
7e834daf
RH		 1110 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
1111#endif
80485d88
PMD		 1112}
1113#endif /* !TARGET_AARCH64 */
1114
2465b07c
PMD		 1115static const ARMCPUInfo arm_tcg_cpus[] = {
1116 { .name = "arm926", .initfn = arm926_initfn },
1117 { .name = "arm946", .initfn = arm946_initfn },
1118 { .name = "arm1026", .initfn = arm1026_initfn },
1119 /*
1120 * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1121 * older core than plain "arm1136". In particular this does not
1122 * have the v6K features.
1123 */
1124 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1125 { .name = "arm1136", .initfn = arm1136_initfn },
1126 { .name = "arm1176", .initfn = arm1176_initfn },
1127 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
80485d88
PMD		 1128 { .name = "cortex-a7", .initfn = cortex_a7_initfn },
1129 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
1130 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
1131 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
2465b07c
PMD		 1132 { .name = "cortex-m0", .initfn = cortex_m0_initfn,
1133 .class_init = arm_v7m_class_init },
1134 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
1135 .class_init = arm_v7m_class_init },
1136 { .name = "cortex-m4", .initfn = cortex_m4_initfn,
1137 .class_init = arm_v7m_class_init },
1138 { .name = "cortex-m7", .initfn = cortex_m7_initfn,
1139 .class_init = arm_v7m_class_init },
1140 { .name = "cortex-m33", .initfn = cortex_m33_initfn,
1141 .class_init = arm_v7m_class_init },
590e05d6
PM		 1142 { .name = "cortex-m55", .initfn = cortex_m55_initfn,
1143 .class_init = arm_v7m_class_init },
2465b07c
PMD		 1144 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
1145 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
1146 { .name = "ti925t", .initfn = ti925t_initfn },
1147 { .name = "sa1100", .initfn = sa1100_initfn },
1148 { .name = "sa1110", .initfn = sa1110_initfn },
1149 { .name = "pxa250", .initfn = pxa250_initfn },
1150 { .name = "pxa255", .initfn = pxa255_initfn },
1151 { .name = "pxa260", .initfn = pxa260_initfn },
1152 { .name = "pxa261", .initfn = pxa261_initfn },
1153 { .name = "pxa262", .initfn = pxa262_initfn },
1154 /* "pxa270" is an alias for "pxa270-a0" */
1155 { .name = "pxa270", .initfn = pxa270a0_initfn },
1156 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1157 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1158 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1159 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1160 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1161 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
80485d88
PMD		 1162#ifndef TARGET_AARCH64
1163 { .name = "max", .initfn = arm_max_initfn },
1164#endif
1165#ifdef CONFIG_USER_ONLY
1166 { .name = "any", .initfn = arm_max_initfn },
1167#endif
2465b07c
PMD		 1168};
1169
6e937ba7
PMD		 1170static const TypeInfo idau_interface_type_info = {
1171 .name = TYPE_IDAU_INTERFACE,
1172 .parent = TYPE_INTERFACE,
1173 .class_size = sizeof(IDAUInterfaceClass),
1174};
1175
2465b07c
PMD		 1176static void arm_tcg_cpu_register_types(void)
1177{
1178 size_t i;
1179
6e937ba7 1180 type_register_static(&idau_interface_type_info);
2465b07c
PMD		 1181 for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
1182 arm_cpu_register(&arm_tcg_cpus[i]);
1183 }
1184}
1185
1186type_init(arm_tcg_cpu_register_types)
1187
1188#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
QEMU mirror