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Commit | Line | Data |
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ed3baad1 PMD |
1 | /* |
2 | * ARM generic helpers. | |
3 | * | |
4 | * This code is licensed under the GNU GPL v2 or later. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0-or-later | |
7 | */ | |
db725815 | 8 | |
74c21bd0 | 9 | #include "qemu/osdep.h" |
63159601 | 10 | #include "qemu/units.h" |
cd617484 | 11 | #include "qemu/log.h" |
181962fd | 12 | #include "target/arm/idau.h" |
194cbc49 | 13 | #include "trace.h" |
b5ff1b31 | 14 | #include "cpu.h" |
ccd38087 | 15 | #include "internals.h" |
2ef6175a | 16 | #include "exec/helper-proto.h" |
1de7afc9 | 17 | #include "qemu/host-utils.h" |
db725815 | 18 | #include "qemu/main-loop.h" |
b8012ecf | 19 | #include "qemu/timer.h" |
1de7afc9 | 20 | #include "qemu/bitops.h" |
eb0ecd5a | 21 | #include "qemu/crc32c.h" |
0442428a | 22 | #include "qemu/qemu-print.h" |
63c91552 | 23 | #include "exec/exec-all.h" |
eb0ecd5a | 24 | #include <zlib.h> /* For crc32 */ |
64552b6b | 25 | #include "hw/irq.h" |
6b5fe137 | 26 | #include "semihosting/semihost.h" |
b2e23725 | 27 | #include "sysemu/cpus.h" |
740b1759 | 28 | #include "sysemu/cpu-timers.h" |
f3a9b694 | 29 | #include "sysemu/kvm.h" |
9d2b5a58 | 30 | #include "qemu/range.h" |
7f7b4e7a | 31 | #include "qapi/qapi-commands-machine-target.h" |
de390645 RH |
32 | #include "qapi/error.h" |
33 | #include "qemu/guest-random.h" | |
91f78c58 PMD |
34 | #ifdef CONFIG_TCG |
35 | #include "arm_ldst.h" | |
7aab5a8c | 36 | #include "exec/cpu_ldst.h" |
6b5fe137 | 37 | #include "semihosting/common-semi.h" |
91f78c58 | 38 | #endif |
cf7c6d10 | 39 | #include "cpregs.h" |
0b03bdfc | 40 | |
352c98e5 | 41 | #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ |
21c2dd77 | 42 | #define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */ |
352c98e5 | 43 | |
4a501606 | 44 | #ifndef CONFIG_USER_ONLY |
7c2cb42b | 45 | |
98e87797 | 46 | static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, |
03ae85f8 | 47 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
ff7de2fc | 48 | bool s1_is_el0, |
37785977 | 49 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, |
da909b2c | 50 | target_ulong *page_size_ptr, |
7e98e21c RH |
51 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) |
52 | __attribute__((nonnull)); | |
4a501606 PM |
53 | #endif |
54 | ||
affdb64d | 55 | static void switch_mode(CPUARMState *env, int mode); |
ea04dce7 | 56 | static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); |
affdb64d | 57 | |
c4241c7d | 58 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) |
d4e6df63 | 59 | { |
375421cc | 60 | assert(ri->fieldoffset); |
67ed771d | 61 | if (cpreg_field_is_64bit(ri)) { |
c4241c7d | 62 | return CPREG_FIELD64(env, ri); |
22d9e1a9 | 63 | } else { |
c4241c7d | 64 | return CPREG_FIELD32(env, ri); |
22d9e1a9 | 65 | } |
d4e6df63 PM |
66 | } |
67 | ||
c4241c7d PM |
68 | static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
69 | uint64_t value) | |
d4e6df63 | 70 | { |
375421cc | 71 | assert(ri->fieldoffset); |
67ed771d | 72 | if (cpreg_field_is_64bit(ri)) { |
22d9e1a9 PM |
73 | CPREG_FIELD64(env, ri) = value; |
74 | } else { | |
75 | CPREG_FIELD32(env, ri) = value; | |
76 | } | |
d4e6df63 PM |
77 | } |
78 | ||
11f136ee FA |
79 | static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) |
80 | { | |
81 | return (char *)env + ri->fieldoffset; | |
82 | } | |
83 | ||
49a66191 | 84 | uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) |
721fae12 | 85 | { |
59a1c327 | 86 | /* Raw read of a coprocessor register (as needed for migration, etc). */ |
721fae12 | 87 | if (ri->type & ARM_CP_CONST) { |
59a1c327 | 88 | return ri->resetvalue; |
721fae12 | 89 | } else if (ri->raw_readfn) { |
59a1c327 | 90 | return ri->raw_readfn(env, ri); |
721fae12 | 91 | } else if (ri->readfn) { |
59a1c327 | 92 | return ri->readfn(env, ri); |
721fae12 | 93 | } else { |
59a1c327 | 94 | return raw_read(env, ri); |
721fae12 | 95 | } |
721fae12 PM |
96 | } |
97 | ||
59a1c327 | 98 | static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, |
7900e9f1 | 99 | uint64_t v) |
721fae12 PM |
100 | { |
101 | /* Raw write of a coprocessor register (as needed for migration, etc). | |
721fae12 PM |
102 | * Note that constant registers are treated as write-ignored; the |
103 | * caller should check for success by whether a readback gives the | |
104 | * value written. | |
105 | */ | |
106 | if (ri->type & ARM_CP_CONST) { | |
59a1c327 | 107 | return; |
721fae12 | 108 | } else if (ri->raw_writefn) { |
c4241c7d | 109 | ri->raw_writefn(env, ri, v); |
721fae12 | 110 | } else if (ri->writefn) { |
c4241c7d | 111 | ri->writefn(env, ri, v); |
721fae12 | 112 | } else { |
afb2530f | 113 | raw_write(env, ri, v); |
721fae12 | 114 | } |
721fae12 PM |
115 | } |
116 | ||
375421cc PM |
117 | static bool raw_accessors_invalid(const ARMCPRegInfo *ri) |
118 | { | |
119 | /* Return true if the regdef would cause an assertion if you called | |
120 | * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a | |
121 | * program bug for it not to have the NO_RAW flag). | |
122 | * NB that returning false here doesn't necessarily mean that calling | |
123 | * read/write_raw_cp_reg() is safe, because we can't distinguish "has | |
124 | * read/write access functions which are safe for raw use" from "has | |
125 | * read/write access functions which have side effects but has forgotten | |
126 | * to provide raw access functions". | |
127 | * The tests here line up with the conditions in read/write_raw_cp_reg() | |
128 | * and assertions in raw_read()/raw_write(). | |
129 | */ | |
130 | if ((ri->type & ARM_CP_CONST) || | |
131 | ri->fieldoffset || | |
132 | ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { | |
133 | return false; | |
134 | } | |
135 | return true; | |
136 | } | |
137 | ||
b698e4ee | 138 | bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync) |
721fae12 PM |
139 | { |
140 | /* Write the coprocessor state from cpu->env to the (index,value) list. */ | |
141 | int i; | |
142 | bool ok = true; | |
143 | ||
144 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
145 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
146 | const ARMCPRegInfo *ri; | |
b698e4ee | 147 | uint64_t newval; |
59a1c327 | 148 | |
60322b39 | 149 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
150 | if (!ri) { |
151 | ok = false; | |
152 | continue; | |
153 | } | |
7a0e58fa | 154 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
155 | continue; |
156 | } | |
b698e4ee PM |
157 | |
158 | newval = read_raw_cp_reg(&cpu->env, ri); | |
159 | if (kvm_sync) { | |
160 | /* | |
161 | * Only sync if the previous list->cpustate sync succeeded. | |
162 | * Rather than tracking the success/failure state for every | |
163 | * item in the list, we just recheck "does the raw write we must | |
164 | * have made in write_list_to_cpustate() read back OK" here. | |
165 | */ | |
166 | uint64_t oldval = cpu->cpreg_values[i]; | |
167 | ||
168 | if (oldval == newval) { | |
169 | continue; | |
170 | } | |
171 | ||
172 | write_raw_cp_reg(&cpu->env, ri, oldval); | |
173 | if (read_raw_cp_reg(&cpu->env, ri) != oldval) { | |
174 | continue; | |
175 | } | |
176 | ||
177 | write_raw_cp_reg(&cpu->env, ri, newval); | |
178 | } | |
179 | cpu->cpreg_values[i] = newval; | |
721fae12 PM |
180 | } |
181 | return ok; | |
182 | } | |
183 | ||
184 | bool write_list_to_cpustate(ARMCPU *cpu) | |
185 | { | |
186 | int i; | |
187 | bool ok = true; | |
188 | ||
189 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
190 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
191 | uint64_t v = cpu->cpreg_values[i]; | |
721fae12 PM |
192 | const ARMCPRegInfo *ri; |
193 | ||
60322b39 | 194 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
195 | if (!ri) { |
196 | ok = false; | |
197 | continue; | |
198 | } | |
7a0e58fa | 199 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
200 | continue; |
201 | } | |
202 | /* Write value and confirm it reads back as written | |
203 | * (to catch read-only registers and partially read-only | |
204 | * registers where the incoming migration value doesn't match) | |
205 | */ | |
59a1c327 PM |
206 | write_raw_cp_reg(&cpu->env, ri, v); |
207 | if (read_raw_cp_reg(&cpu->env, ri) != v) { | |
721fae12 PM |
208 | ok = false; |
209 | } | |
210 | } | |
211 | return ok; | |
212 | } | |
213 | ||
214 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | |
215 | { | |
216 | ARMCPU *cpu = opaque; | |
217 | uint64_t regidx; | |
218 | const ARMCPRegInfo *ri; | |
219 | ||
220 | regidx = *(uint32_t *)key; | |
60322b39 | 221 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 | 222 | |
7a0e58fa | 223 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
224 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); |
225 | /* The value array need not be initialized at this point */ | |
226 | cpu->cpreg_array_len++; | |
227 | } | |
228 | } | |
229 | ||
230 | static void count_cpreg(gpointer key, gpointer opaque) | |
231 | { | |
232 | ARMCPU *cpu = opaque; | |
233 | uint64_t regidx; | |
234 | const ARMCPRegInfo *ri; | |
235 | ||
236 | regidx = *(uint32_t *)key; | |
60322b39 | 237 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 | 238 | |
7a0e58fa | 239 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
240 | cpu->cpreg_array_len++; |
241 | } | |
242 | } | |
243 | ||
244 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | |
245 | { | |
cbf239b7 AR |
246 | uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); |
247 | uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); | |
721fae12 | 248 | |
cbf239b7 AR |
249 | if (aidx > bidx) { |
250 | return 1; | |
251 | } | |
252 | if (aidx < bidx) { | |
253 | return -1; | |
254 | } | |
255 | return 0; | |
721fae12 PM |
256 | } |
257 | ||
258 | void init_cpreg_list(ARMCPU *cpu) | |
259 | { | |
260 | /* Initialise the cpreg_tuples[] array based on the cp_regs hash. | |
261 | * Note that we require cpreg_tuples[] to be sorted by key ID. | |
262 | */ | |
57b6d95e | 263 | GList *keys; |
721fae12 PM |
264 | int arraylen; |
265 | ||
57b6d95e | 266 | keys = g_hash_table_get_keys(cpu->cp_regs); |
721fae12 PM |
267 | keys = g_list_sort(keys, cpreg_key_compare); |
268 | ||
269 | cpu->cpreg_array_len = 0; | |
270 | ||
271 | g_list_foreach(keys, count_cpreg, cpu); | |
272 | ||
273 | arraylen = cpu->cpreg_array_len; | |
274 | cpu->cpreg_indexes = g_new(uint64_t, arraylen); | |
275 | cpu->cpreg_values = g_new(uint64_t, arraylen); | |
276 | cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); | |
277 | cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); | |
278 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; | |
279 | cpu->cpreg_array_len = 0; | |
280 | ||
281 | g_list_foreach(keys, add_cpreg_to_list, cpu); | |
282 | ||
283 | assert(cpu->cpreg_array_len == arraylen); | |
284 | ||
285 | g_list_free(keys); | |
286 | } | |
287 | ||
68e9c2fe | 288 | /* |
93dd1e61 | 289 | * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0. |
68e9c2fe EI |
290 | */ |
291 | static CPAccessResult access_el3_aa32ns(CPUARMState *env, | |
3f208fd7 PM |
292 | const ARMCPRegInfo *ri, |
293 | bool isread) | |
68e9c2fe | 294 | { |
93dd1e61 EI |
295 | if (!is_a64(env) && arm_current_el(env) == 3 && |
296 | arm_is_secure_below_el3(env)) { | |
68e9c2fe EI |
297 | return CP_ACCESS_TRAP_UNCATEGORIZED; |
298 | } | |
299 | return CP_ACCESS_OK; | |
300 | } | |
301 | ||
5513c3ab PM |
302 | /* Some secure-only AArch32 registers trap to EL3 if used from |
303 | * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). | |
304 | * Note that an access from Secure EL1 can only happen if EL3 is AArch64. | |
305 | * We assume that the .access field is set to PL1_RW. | |
306 | */ | |
307 | static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, | |
3f208fd7 PM |
308 | const ARMCPRegInfo *ri, |
309 | bool isread) | |
5513c3ab PM |
310 | { |
311 | if (arm_current_el(env) == 3) { | |
312 | return CP_ACCESS_OK; | |
313 | } | |
314 | if (arm_is_secure_below_el3(env)) { | |
926c1b97 RDC |
315 | if (env->cp15.scr_el3 & SCR_EEL2) { |
316 | return CP_ACCESS_TRAP_EL2; | |
317 | } | |
5513c3ab PM |
318 | return CP_ACCESS_TRAP_EL3; |
319 | } | |
320 | /* This will be EL1 NS and EL2 NS, which just UNDEF */ | |
321 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
322 | } | |
323 | ||
59dd089c RDC |
324 | static uint64_t arm_mdcr_el2_eff(CPUARMState *env) |
325 | { | |
326 | return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0; | |
327 | } | |
328 | ||
187f678d PM |
329 | /* Check for traps to "powerdown debug" registers, which are controlled |
330 | * by MDCR.TDOSA | |
331 | */ | |
332 | static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, | |
333 | bool isread) | |
334 | { | |
335 | int el = arm_current_el(env); | |
59dd089c RDC |
336 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
337 | bool mdcr_el2_tdosa = (mdcr_el2 & MDCR_TDOSA) || (mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 338 | (arm_hcr_el2_eff(env) & HCR_TGE); |
187f678d | 339 | |
59dd089c | 340 | if (el < 2 && mdcr_el2_tdosa) { |
187f678d PM |
341 | return CP_ACCESS_TRAP_EL2; |
342 | } | |
343 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { | |
344 | return CP_ACCESS_TRAP_EL3; | |
345 | } | |
346 | return CP_ACCESS_OK; | |
347 | } | |
348 | ||
91b0a238 PM |
349 | /* Check for traps to "debug ROM" registers, which are controlled |
350 | * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. | |
351 | */ | |
352 | static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, | |
353 | bool isread) | |
354 | { | |
355 | int el = arm_current_el(env); | |
59dd089c RDC |
356 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
357 | bool mdcr_el2_tdra = (mdcr_el2 & MDCR_TDRA) || (mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 358 | (arm_hcr_el2_eff(env) & HCR_TGE); |
91b0a238 | 359 | |
59dd089c | 360 | if (el < 2 && mdcr_el2_tdra) { |
91b0a238 PM |
361 | return CP_ACCESS_TRAP_EL2; |
362 | } | |
363 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
364 | return CP_ACCESS_TRAP_EL3; | |
365 | } | |
366 | return CP_ACCESS_OK; | |
367 | } | |
368 | ||
d6c8cf81 PM |
369 | /* Check for traps to general debug registers, which are controlled |
370 | * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. | |
371 | */ | |
372 | static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, | |
373 | bool isread) | |
374 | { | |
375 | int el = arm_current_el(env); | |
59dd089c RDC |
376 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
377 | bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 378 | (arm_hcr_el2_eff(env) & HCR_TGE); |
d6c8cf81 | 379 | |
59dd089c | 380 | if (el < 2 && mdcr_el2_tda) { |
d6c8cf81 PM |
381 | return CP_ACCESS_TRAP_EL2; |
382 | } | |
383 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
384 | return CP_ACCESS_TRAP_EL3; | |
385 | } | |
386 | return CP_ACCESS_OK; | |
387 | } | |
388 | ||
1fce1ba9 PM |
389 | /* Check for traps to performance monitor registers, which are controlled |
390 | * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. | |
391 | */ | |
392 | static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, | |
393 | bool isread) | |
394 | { | |
395 | int el = arm_current_el(env); | |
59dd089c | 396 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
1fce1ba9 | 397 | |
59dd089c | 398 | if (el < 2 && (mdcr_el2 & MDCR_TPM)) { |
1fce1ba9 PM |
399 | return CP_ACCESS_TRAP_EL2; |
400 | } | |
401 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
402 | return CP_ACCESS_TRAP_EL3; | |
403 | } | |
404 | return CP_ACCESS_OK; | |
405 | } | |
406 | ||
84929218 RH |
407 | /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ |
408 | static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, | |
409 | bool isread) | |
410 | { | |
411 | if (arm_current_el(env) == 1) { | |
412 | uint64_t trap = isread ? HCR_TRVM : HCR_TVM; | |
413 | if (arm_hcr_el2_eff(env) & trap) { | |
414 | return CP_ACCESS_TRAP_EL2; | |
415 | } | |
416 | } | |
417 | return CP_ACCESS_OK; | |
418 | } | |
419 | ||
1803d271 RH |
420 | /* Check for traps from EL1 due to HCR_EL2.TSW. */ |
421 | static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri, | |
422 | bool isread) | |
423 | { | |
424 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) { | |
425 | return CP_ACCESS_TRAP_EL2; | |
426 | } | |
427 | return CP_ACCESS_OK; | |
428 | } | |
429 | ||
99602377 RH |
430 | /* Check for traps from EL1 due to HCR_EL2.TACR. */ |
431 | static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri, | |
432 | bool isread) | |
433 | { | |
434 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TACR)) { | |
435 | return CP_ACCESS_TRAP_EL2; | |
436 | } | |
437 | return CP_ACCESS_OK; | |
438 | } | |
439 | ||
30881b73 RH |
440 | /* Check for traps from EL1 due to HCR_EL2.TTLB. */ |
441 | static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri, | |
442 | bool isread) | |
443 | { | |
444 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TTLB)) { | |
445 | return CP_ACCESS_TRAP_EL2; | |
446 | } | |
447 | return CP_ACCESS_OK; | |
448 | } | |
449 | ||
c4241c7d | 450 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
c983fe6c | 451 | { |
2fc0cc0e | 452 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 453 | |
8d5c773e | 454 | raw_write(env, ri, value); |
d10eb08f | 455 | tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ |
c983fe6c PM |
456 | } |
457 | ||
c4241c7d | 458 | static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
08de207b | 459 | { |
2fc0cc0e | 460 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 461 | |
8d5c773e | 462 | if (raw_read(env, ri) != value) { |
08de207b PM |
463 | /* Unlike real hardware the qemu TLB uses virtual addresses, |
464 | * not modified virtual addresses, so this causes a TLB flush. | |
465 | */ | |
d10eb08f | 466 | tlb_flush(CPU(cpu)); |
8d5c773e | 467 | raw_write(env, ri, value); |
08de207b | 468 | } |
08de207b | 469 | } |
c4241c7d PM |
470 | |
471 | static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
472 | uint64_t value) | |
08de207b | 473 | { |
2fc0cc0e | 474 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 475 | |
452a0955 | 476 | if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) |
014406b5 | 477 | && !extended_addresses_enabled(env)) { |
08de207b PM |
478 | /* For VMSA (when not using the LPAE long descriptor page table |
479 | * format) this register includes the ASID, so do a TLB flush. | |
480 | * For PMSA it is purely a process ID and no action is needed. | |
481 | */ | |
d10eb08f | 482 | tlb_flush(CPU(cpu)); |
08de207b | 483 | } |
8d5c773e | 484 | raw_write(env, ri, value); |
08de207b PM |
485 | } |
486 | ||
b4ab8ce9 PM |
487 | /* IS variants of TLB operations must affect all cores */ |
488 | static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
489 | uint64_t value) | |
490 | { | |
29a0af61 | 491 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
492 | |
493 | tlb_flush_all_cpus_synced(cs); | |
494 | } | |
495 | ||
496 | static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
497 | uint64_t value) | |
498 | { | |
29a0af61 | 499 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
500 | |
501 | tlb_flush_all_cpus_synced(cs); | |
502 | } | |
503 | ||
504 | static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
505 | uint64_t value) | |
506 | { | |
29a0af61 | 507 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
508 | |
509 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
510 | } | |
511 | ||
512 | static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
513 | uint64_t value) | |
514 | { | |
29a0af61 | 515 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
516 | |
517 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
518 | } | |
519 | ||
520 | /* | |
521 | * Non-IS variants of TLB operations are upgraded to | |
373e7ffd | 522 | * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to |
b4ab8ce9 PM |
523 | * force broadcast of these operations. |
524 | */ | |
525 | static bool tlb_force_broadcast(CPUARMState *env) | |
526 | { | |
373e7ffd | 527 | return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB); |
b4ab8ce9 PM |
528 | } |
529 | ||
c4241c7d PM |
530 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
531 | uint64_t value) | |
d929823f PM |
532 | { |
533 | /* Invalidate all (TLBIALL) */ | |
527db2be | 534 | CPUState *cs = env_cpu(env); |
00c8cb0a | 535 | |
b4ab8ce9 | 536 | if (tlb_force_broadcast(env)) { |
527db2be RH |
537 | tlb_flush_all_cpus_synced(cs); |
538 | } else { | |
539 | tlb_flush(cs); | |
b4ab8ce9 | 540 | } |
d929823f PM |
541 | } |
542 | ||
c4241c7d PM |
543 | static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
544 | uint64_t value) | |
d929823f PM |
545 | { |
546 | /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ | |
527db2be | 547 | CPUState *cs = env_cpu(env); |
31b030d4 | 548 | |
527db2be | 549 | value &= TARGET_PAGE_MASK; |
b4ab8ce9 | 550 | if (tlb_force_broadcast(env)) { |
527db2be RH |
551 | tlb_flush_page_all_cpus_synced(cs, value); |
552 | } else { | |
553 | tlb_flush_page(cs, value); | |
b4ab8ce9 | 554 | } |
d929823f PM |
555 | } |
556 | ||
c4241c7d PM |
557 | static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
558 | uint64_t value) | |
d929823f PM |
559 | { |
560 | /* Invalidate by ASID (TLBIASID) */ | |
527db2be | 561 | CPUState *cs = env_cpu(env); |
00c8cb0a | 562 | |
b4ab8ce9 | 563 | if (tlb_force_broadcast(env)) { |
527db2be RH |
564 | tlb_flush_all_cpus_synced(cs); |
565 | } else { | |
566 | tlb_flush(cs); | |
b4ab8ce9 | 567 | } |
d929823f PM |
568 | } |
569 | ||
c4241c7d PM |
570 | static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
571 | uint64_t value) | |
d929823f PM |
572 | { |
573 | /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ | |
527db2be | 574 | CPUState *cs = env_cpu(env); |
31b030d4 | 575 | |
527db2be | 576 | value &= TARGET_PAGE_MASK; |
b4ab8ce9 | 577 | if (tlb_force_broadcast(env)) { |
527db2be RH |
578 | tlb_flush_page_all_cpus_synced(cs, value); |
579 | } else { | |
580 | tlb_flush_page(cs, value); | |
b4ab8ce9 | 581 | } |
fa439fc5 PM |
582 | } |
583 | ||
541ef8c2 SS |
584 | static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, |
585 | uint64_t value) | |
586 | { | |
29a0af61 | 587 | CPUState *cs = env_cpu(env); |
541ef8c2 | 588 | |
0336cbf8 | 589 | tlb_flush_by_mmuidx(cs, |
01b98b68 | 590 | ARMMMUIdxBit_E10_1 | |
452ef8cb | 591 | ARMMMUIdxBit_E10_1_PAN | |
bf05340c | 592 | ARMMMUIdxBit_E10_0); |
541ef8c2 SS |
593 | } |
594 | ||
595 | static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
596 | uint64_t value) | |
597 | { | |
29a0af61 | 598 | CPUState *cs = env_cpu(env); |
541ef8c2 | 599 | |
a67cf277 | 600 | tlb_flush_by_mmuidx_all_cpus_synced(cs, |
01b98b68 | 601 | ARMMMUIdxBit_E10_1 | |
452ef8cb | 602 | ARMMMUIdxBit_E10_1_PAN | |
bf05340c | 603 | ARMMMUIdxBit_E10_0); |
541ef8c2 SS |
604 | } |
605 | ||
541ef8c2 SS |
606 | |
607 | static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
608 | uint64_t value) | |
609 | { | |
29a0af61 | 610 | CPUState *cs = env_cpu(env); |
541ef8c2 | 611 | |
e013b741 | 612 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); |
541ef8c2 SS |
613 | } |
614 | ||
615 | static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
616 | uint64_t value) | |
617 | { | |
29a0af61 | 618 | CPUState *cs = env_cpu(env); |
541ef8c2 | 619 | |
e013b741 | 620 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); |
541ef8c2 SS |
621 | } |
622 | ||
623 | static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
624 | uint64_t value) | |
625 | { | |
29a0af61 | 626 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
627 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
628 | ||
e013b741 | 629 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); |
541ef8c2 SS |
630 | } |
631 | ||
632 | static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
633 | uint64_t value) | |
634 | { | |
29a0af61 | 635 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
636 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
637 | ||
a67cf277 | 638 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
e013b741 | 639 | ARMMMUIdxBit_E2); |
541ef8c2 SS |
640 | } |
641 | ||
e9aa6c21 | 642 | static const ARMCPRegInfo cp_reginfo[] = { |
54bf36ed FA |
643 | /* Define the secure and non-secure FCSE identifier CP registers |
644 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
645 | * the secure register to be properly reset and migrated. There is also no | |
646 | * v8 EL1 version of the register so the non-secure instance stands alone. | |
647 | */ | |
9c513e78 | 648 | { .name = "FCSEIDR", |
54bf36ed FA |
649 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
650 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, | |
651 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), | |
652 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, | |
9c513e78 | 653 | { .name = "FCSEIDR_S", |
54bf36ed FA |
654 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
655 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
656 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), | |
d4e6df63 | 657 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, |
54bf36ed FA |
658 | /* Define the secure and non-secure context identifier CP registers |
659 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
660 | * the secure register to be properly reset and migrated. In the | |
661 | * non-secure case, the 32-bit register will have reset and migration | |
662 | * disabled during registration as it is handled by the 64-bit instance. | |
663 | */ | |
664 | { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
014406b5 | 665 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
84929218 RH |
666 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
667 | .secure = ARM_CP_SECSTATE_NS, | |
54bf36ed FA |
668 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), |
669 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, | |
9c513e78 | 670 | { .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32, |
54bf36ed | 671 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
84929218 RH |
672 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
673 | .secure = ARM_CP_SECSTATE_S, | |
54bf36ed | 674 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), |
d4e6df63 | 675 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, |
9449fdf6 PM |
676 | }; |
677 | ||
678 | static const ARMCPRegInfo not_v8_cp_reginfo[] = { | |
679 | /* NB: Some of these registers exist in v8 but with more precise | |
680 | * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). | |
681 | */ | |
682 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
683 | { .name = "DACR", |
684 | .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, | |
84929218 | 685 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
0c17d68c FA |
686 | .writefn = dacr_write, .raw_writefn = raw_write, |
687 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
688 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a903c449 EI |
689 | /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. |
690 | * For v6 and v5, these mappings are overly broad. | |
4fdd17dd | 691 | */ |
a903c449 EI |
692 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0, |
693 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
694 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1, | |
695 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
696 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4, | |
697 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
698 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8, | |
4fdd17dd | 699 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, |
c4804214 PM |
700 | /* Cache maintenance ops; some of this space may be overridden later. */ |
701 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | |
702 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | |
703 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | |
e9aa6c21 PM |
704 | }; |
705 | ||
7d57f408 PM |
706 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
707 | /* Not all pre-v6 cores implemented this WFI, so this is slightly | |
708 | * over-broad. | |
709 | */ | |
710 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | |
711 | .access = PL1_W, .type = ARM_CP_WFI }, | |
7d57f408 PM |
712 | }; |
713 | ||
714 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | |
715 | /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which | |
716 | * is UNPREDICTABLE; we choose to NOP as most implementations do). | |
717 | */ | |
718 | { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
719 | .access = PL1_W, .type = ARM_CP_WFI }, | |
34f90529 PM |
720 | /* L1 cache lockdown. Not architectural in v6 and earlier but in practice |
721 | * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and | |
722 | * OMAPCP will override this space. | |
723 | */ | |
724 | { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, | |
725 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), | |
726 | .resetvalue = 0 }, | |
727 | { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, | |
728 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), | |
729 | .resetvalue = 0 }, | |
776d4e5c PM |
730 | /* v6 doesn't have the cache ID registers but Linux reads them anyway */ |
731 | { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, | |
7a0e58fa | 732 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 733 | .resetvalue = 0 }, |
50300698 PM |
734 | /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; |
735 | * implementing it as RAZ means the "debug architecture version" bits | |
736 | * will read as a reserved value, which should cause Linux to not try | |
737 | * to use the debug hardware. | |
738 | */ | |
739 | { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
740 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
995939a6 PM |
741 | /* MMU TLB control. Note that the wildcarding means we cover not just |
742 | * the unified TLB ops but also the dside/iside/inner-shareable variants. | |
743 | */ | |
744 | { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, | |
745 | .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, | |
7a0e58fa | 746 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
747 | { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, |
748 | .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, | |
7a0e58fa | 749 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
750 | { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, |
751 | .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, | |
7a0e58fa | 752 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
753 | { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, |
754 | .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, | |
7a0e58fa | 755 | .type = ARM_CP_NO_RAW }, |
a903c449 EI |
756 | { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2, |
757 | .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, | |
758 | { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, | |
759 | .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, | |
7d57f408 PM |
760 | }; |
761 | ||
c4241c7d PM |
762 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
763 | uint64_t value) | |
2771db27 | 764 | { |
f0aff255 FA |
765 | uint32_t mask = 0; |
766 | ||
767 | /* In ARMv8 most bits of CPACR_EL1 are RES0. */ | |
768 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
769 | /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. | |
770 | * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. | |
771 | * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. | |
772 | */ | |
7fbc6a40 | 773 | if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { |
f0aff255 FA |
774 | /* VFP coprocessor: cp10 & cp11 [23:20] */ |
775 | mask |= (1 << 31) | (1 << 30) | (0xf << 20); | |
776 | ||
777 | if (!arm_feature(env, ARM_FEATURE_NEON)) { | |
778 | /* ASEDIS [31] bit is RAO/WI */ | |
779 | value |= (1 << 31); | |
780 | } | |
781 | ||
782 | /* VFPv3 and upwards with NEON implement 32 double precision | |
783 | * registers (D0-D31). | |
784 | */ | |
a6627f5f | 785 | if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { |
f0aff255 FA |
786 | /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ |
787 | value |= (1 << 30); | |
788 | } | |
789 | } | |
790 | value &= mask; | |
2771db27 | 791 | } |
fc1120a7 PM |
792 | |
793 | /* | |
794 | * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 | |
795 | * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. | |
796 | */ | |
797 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
798 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
799 | value &= ~(0xf << 20); | |
800 | value |= env->cp15.cpacr_el1 & (0xf << 20); | |
801 | } | |
802 | ||
7ebd5f2e | 803 | env->cp15.cpacr_el1 = value; |
2771db27 PM |
804 | } |
805 | ||
fc1120a7 PM |
806 | static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
807 | { | |
808 | /* | |
809 | * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 | |
810 | * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. | |
811 | */ | |
812 | uint64_t value = env->cp15.cpacr_el1; | |
813 | ||
814 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
815 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
816 | value &= ~(0xf << 20); | |
817 | } | |
818 | return value; | |
819 | } | |
820 | ||
821 | ||
5deac39c PM |
822 | static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
823 | { | |
824 | /* Call cpacr_write() so that we reset with the correct RAO bits set | |
825 | * for our CPU features. | |
826 | */ | |
827 | cpacr_write(env, ri, 0); | |
828 | } | |
829 | ||
3f208fd7 PM |
830 | static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
831 | bool isread) | |
c6f19164 GB |
832 | { |
833 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
834 | /* Check if CPACR accesses are to be trapped to EL2 */ | |
e6ef0169 RDC |
835 | if (arm_current_el(env) == 1 && arm_is_el2_enabled(env) && |
836 | (env->cp15.cptr_el[2] & CPTR_TCPAC)) { | |
c6f19164 GB |
837 | return CP_ACCESS_TRAP_EL2; |
838 | /* Check if CPACR accesses are to be trapped to EL3 */ | |
839 | } else if (arm_current_el(env) < 3 && | |
840 | (env->cp15.cptr_el[3] & CPTR_TCPAC)) { | |
841 | return CP_ACCESS_TRAP_EL3; | |
842 | } | |
843 | } | |
844 | ||
845 | return CP_ACCESS_OK; | |
846 | } | |
847 | ||
3f208fd7 PM |
848 | static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
849 | bool isread) | |
c6f19164 GB |
850 | { |
851 | /* Check if CPTR accesses are set to trap to EL3 */ | |
852 | if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) { | |
853 | return CP_ACCESS_TRAP_EL3; | |
854 | } | |
855 | ||
856 | return CP_ACCESS_OK; | |
857 | } | |
858 | ||
7d57f408 PM |
859 | static const ARMCPRegInfo v6_cp_reginfo[] = { |
860 | /* prefetch by MVA in v6, NOP in v7 */ | |
861 | { .name = "MVA_prefetch", | |
862 | .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, | |
863 | .access = PL1_W, .type = ARM_CP_NOP }, | |
6df99dec SS |
864 | /* We need to break the TB after ISB to execute self-modifying code |
865 | * correctly and also to take any pending interrupts immediately. | |
866 | * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. | |
867 | */ | |
7d57f408 | 868 | { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, |
6df99dec | 869 | .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, |
091fd17c | 870 | { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
7d57f408 | 871 | .access = PL0_W, .type = ARM_CP_NOP }, |
091fd17c | 872 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
7d57f408 | 873 | .access = PL0_W, .type = ARM_CP_NOP }, |
06d76f31 | 874 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
84929218 | 875 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
b848ce2b FA |
876 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), |
877 | offsetof(CPUARMState, cp15.ifar_ns) }, | |
06d76f31 PM |
878 | .resetvalue = 0, }, |
879 | /* Watchpoint Fault Address Register : should actually only be present | |
880 | * for 1136, 1176, 11MPCore. | |
881 | */ | |
882 | { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
883 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, | |
34222fb8 | 884 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, |
c6f19164 | 885 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, |
7ebd5f2e | 886 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), |
fc1120a7 | 887 | .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read }, |
7d57f408 PM |
888 | }; |
889 | ||
57a4a11b AL |
890 | typedef struct pm_event { |
891 | uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ | |
892 | /* If the event is supported on this CPU (used to generate PMCEID[01]) */ | |
893 | bool (*supported)(CPUARMState *); | |
894 | /* | |
895 | * Retrieve the current count of the underlying event. The programmed | |
896 | * counters hold a difference from the return value from this function | |
897 | */ | |
898 | uint64_t (*get_count)(CPUARMState *); | |
4e7beb0c AL |
899 | /* |
900 | * Return how many nanoseconds it will take (at a minimum) for count events | |
901 | * to occur. A negative value indicates the counter will never overflow, or | |
902 | * that the counter has otherwise arranged for the overflow bit to be set | |
903 | * and the PMU interrupt to be raised on overflow. | |
904 | */ | |
905 | int64_t (*ns_per_count)(uint64_t); | |
57a4a11b AL |
906 | } pm_event; |
907 | ||
b2e23725 AL |
908 | static bool event_always_supported(CPUARMState *env) |
909 | { | |
910 | return true; | |
911 | } | |
912 | ||
0d4bfd7d AL |
913 | static uint64_t swinc_get_count(CPUARMState *env) |
914 | { | |
915 | /* | |
916 | * SW_INCR events are written directly to the pmevcntr's by writes to | |
917 | * PMSWINC, so there is no underlying count maintained by the PMU itself | |
918 | */ | |
919 | return 0; | |
920 | } | |
921 | ||
4e7beb0c AL |
922 | static int64_t swinc_ns_per(uint64_t ignored) |
923 | { | |
924 | return -1; | |
925 | } | |
926 | ||
b2e23725 AL |
927 | /* |
928 | * Return the underlying cycle count for the PMU cycle counters. If we're in | |
929 | * usermode, simply return 0. | |
930 | */ | |
931 | static uint64_t cycles_get_count(CPUARMState *env) | |
932 | { | |
933 | #ifndef CONFIG_USER_ONLY | |
934 | return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
935 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); | |
936 | #else | |
937 | return cpu_get_host_ticks(); | |
938 | #endif | |
939 | } | |
940 | ||
941 | #ifndef CONFIG_USER_ONLY | |
4e7beb0c AL |
942 | static int64_t cycles_ns_per(uint64_t cycles) |
943 | { | |
944 | return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles; | |
945 | } | |
946 | ||
b2e23725 AL |
947 | static bool instructions_supported(CPUARMState *env) |
948 | { | |
740b1759 | 949 | return icount_enabled() == 1; /* Precise instruction counting */ |
b2e23725 AL |
950 | } |
951 | ||
952 | static uint64_t instructions_get_count(CPUARMState *env) | |
953 | { | |
8191d368 | 954 | return (uint64_t)icount_get_raw(); |
b2e23725 | 955 | } |
4e7beb0c AL |
956 | |
957 | static int64_t instructions_ns_per(uint64_t icount) | |
958 | { | |
8191d368 | 959 | return icount_to_ns((int64_t)icount); |
4e7beb0c | 960 | } |
b2e23725 AL |
961 | #endif |
962 | ||
0727f63b PM |
963 | static bool pmu_8_1_events_supported(CPUARMState *env) |
964 | { | |
965 | /* For events which are supported in any v8.1 PMU */ | |
966 | return cpu_isar_feature(any_pmu_8_1, env_archcpu(env)); | |
967 | } | |
968 | ||
15dd1ebd PM |
969 | static bool pmu_8_4_events_supported(CPUARMState *env) |
970 | { | |
971 | /* For events which are supported in any v8.1 PMU */ | |
972 | return cpu_isar_feature(any_pmu_8_4, env_archcpu(env)); | |
973 | } | |
974 | ||
0727f63b PM |
975 | static uint64_t zero_event_get_count(CPUARMState *env) |
976 | { | |
977 | /* For events which on QEMU never fire, so their count is always zero */ | |
978 | return 0; | |
979 | } | |
980 | ||
981 | static int64_t zero_event_ns_per(uint64_t cycles) | |
982 | { | |
983 | /* An event which never fires can never overflow */ | |
984 | return -1; | |
985 | } | |
986 | ||
57a4a11b | 987 | static const pm_event pm_events[] = { |
0d4bfd7d AL |
988 | { .number = 0x000, /* SW_INCR */ |
989 | .supported = event_always_supported, | |
990 | .get_count = swinc_get_count, | |
4e7beb0c | 991 | .ns_per_count = swinc_ns_per, |
0d4bfd7d | 992 | }, |
b2e23725 AL |
993 | #ifndef CONFIG_USER_ONLY |
994 | { .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */ | |
995 | .supported = instructions_supported, | |
996 | .get_count = instructions_get_count, | |
4e7beb0c | 997 | .ns_per_count = instructions_ns_per, |
b2e23725 AL |
998 | }, |
999 | { .number = 0x011, /* CPU_CYCLES, Cycle */ | |
1000 | .supported = event_always_supported, | |
1001 | .get_count = cycles_get_count, | |
4e7beb0c | 1002 | .ns_per_count = cycles_ns_per, |
0727f63b | 1003 | }, |
b2e23725 | 1004 | #endif |
0727f63b PM |
1005 | { .number = 0x023, /* STALL_FRONTEND */ |
1006 | .supported = pmu_8_1_events_supported, | |
1007 | .get_count = zero_event_get_count, | |
1008 | .ns_per_count = zero_event_ns_per, | |
1009 | }, | |
1010 | { .number = 0x024, /* STALL_BACKEND */ | |
1011 | .supported = pmu_8_1_events_supported, | |
1012 | .get_count = zero_event_get_count, | |
1013 | .ns_per_count = zero_event_ns_per, | |
1014 | }, | |
15dd1ebd PM |
1015 | { .number = 0x03c, /* STALL */ |
1016 | .supported = pmu_8_4_events_supported, | |
1017 | .get_count = zero_event_get_count, | |
1018 | .ns_per_count = zero_event_ns_per, | |
1019 | }, | |
57a4a11b AL |
1020 | }; |
1021 | ||
1022 | /* | |
1023 | * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of | |
1024 | * events (i.e. the statistical profiling extension), this implementation | |
1025 | * should first be updated to something sparse instead of the current | |
1026 | * supported_event_map[] array. | |
1027 | */ | |
15dd1ebd | 1028 | #define MAX_EVENT_ID 0x3c |
57a4a11b AL |
1029 | #define UNSUPPORTED_EVENT UINT16_MAX |
1030 | static uint16_t supported_event_map[MAX_EVENT_ID + 1]; | |
1031 | ||
1032 | /* | |
bf8d0969 AL |
1033 | * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map |
1034 | * of ARM event numbers to indices in our pm_events array. | |
57a4a11b AL |
1035 | * |
1036 | * Note: Events in the 0x40XX range are not currently supported. | |
1037 | */ | |
bf8d0969 | 1038 | void pmu_init(ARMCPU *cpu) |
57a4a11b | 1039 | { |
57a4a11b AL |
1040 | unsigned int i; |
1041 | ||
bf8d0969 AL |
1042 | /* |
1043 | * Empty supported_event_map and cpu->pmceid[01] before adding supported | |
1044 | * events to them | |
1045 | */ | |
57a4a11b AL |
1046 | for (i = 0; i < ARRAY_SIZE(supported_event_map); i++) { |
1047 | supported_event_map[i] = UNSUPPORTED_EVENT; | |
1048 | } | |
bf8d0969 AL |
1049 | cpu->pmceid0 = 0; |
1050 | cpu->pmceid1 = 0; | |
57a4a11b AL |
1051 | |
1052 | for (i = 0; i < ARRAY_SIZE(pm_events); i++) { | |
1053 | const pm_event *cnt = &pm_events[i]; | |
1054 | assert(cnt->number <= MAX_EVENT_ID); | |
1055 | /* We do not currently support events in the 0x40xx range */ | |
1056 | assert(cnt->number <= 0x3f); | |
1057 | ||
bf8d0969 | 1058 | if (cnt->supported(&cpu->env)) { |
57a4a11b | 1059 | supported_event_map[cnt->number] = i; |
67da43d6 | 1060 | uint64_t event_mask = 1ULL << (cnt->number & 0x1f); |
bf8d0969 AL |
1061 | if (cnt->number & 0x20) { |
1062 | cpu->pmceid1 |= event_mask; | |
1063 | } else { | |
1064 | cpu->pmceid0 |= event_mask; | |
1065 | } | |
57a4a11b AL |
1066 | } |
1067 | } | |
57a4a11b AL |
1068 | } |
1069 | ||
5ecdd3e4 AL |
1070 | /* |
1071 | * Check at runtime whether a PMU event is supported for the current machine | |
1072 | */ | |
1073 | static bool event_supported(uint16_t number) | |
1074 | { | |
1075 | if (number > MAX_EVENT_ID) { | |
1076 | return false; | |
1077 | } | |
1078 | return supported_event_map[number] != UNSUPPORTED_EVENT; | |
1079 | } | |
1080 | ||
3f208fd7 PM |
1081 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1082 | bool isread) | |
200ac0ef | 1083 | { |
3b163b01 | 1084 | /* Performance monitor registers user accessibility is controlled |
1fce1ba9 PM |
1085 | * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable |
1086 | * trapping to EL2 or EL3 for other accesses. | |
200ac0ef | 1087 | */ |
1fce1ba9 | 1088 | int el = arm_current_el(env); |
59dd089c | 1089 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
1fce1ba9 | 1090 | |
6ecd0b6b | 1091 | if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { |
fcd25206 | 1092 | return CP_ACCESS_TRAP; |
200ac0ef | 1093 | } |
59dd089c | 1094 | if (el < 2 && (mdcr_el2 & MDCR_TPM)) { |
1fce1ba9 PM |
1095 | return CP_ACCESS_TRAP_EL2; |
1096 | } | |
1097 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
1098 | return CP_ACCESS_TRAP_EL3; | |
1099 | } | |
1100 | ||
fcd25206 | 1101 | return CP_ACCESS_OK; |
200ac0ef PM |
1102 | } |
1103 | ||
6ecd0b6b AB |
1104 | static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, |
1105 | const ARMCPRegInfo *ri, | |
1106 | bool isread) | |
1107 | { | |
1108 | /* ER: event counter read trap control */ | |
1109 | if (arm_feature(env, ARM_FEATURE_V8) | |
1110 | && arm_current_el(env) == 0 | |
1111 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 | |
1112 | && isread) { | |
1113 | return CP_ACCESS_OK; | |
1114 | } | |
1115 | ||
1116 | return pmreg_access(env, ri, isread); | |
1117 | } | |
1118 | ||
1119 | static CPAccessResult pmreg_access_swinc(CPUARMState *env, | |
1120 | const ARMCPRegInfo *ri, | |
1121 | bool isread) | |
1122 | { | |
1123 | /* SW: software increment write trap control */ | |
1124 | if (arm_feature(env, ARM_FEATURE_V8) | |
1125 | && arm_current_el(env) == 0 | |
1126 | && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 | |
1127 | && !isread) { | |
1128 | return CP_ACCESS_OK; | |
1129 | } | |
1130 | ||
1131 | return pmreg_access(env, ri, isread); | |
1132 | } | |
1133 | ||
6ecd0b6b AB |
1134 | static CPAccessResult pmreg_access_selr(CPUARMState *env, |
1135 | const ARMCPRegInfo *ri, | |
1136 | bool isread) | |
1137 | { | |
1138 | /* ER: event counter read trap control */ | |
1139 | if (arm_feature(env, ARM_FEATURE_V8) | |
1140 | && arm_current_el(env) == 0 | |
1141 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { | |
1142 | return CP_ACCESS_OK; | |
1143 | } | |
1144 | ||
1145 | return pmreg_access(env, ri, isread); | |
1146 | } | |
1147 | ||
1148 | static CPAccessResult pmreg_access_ccntr(CPUARMState *env, | |
1149 | const ARMCPRegInfo *ri, | |
1150 | bool isread) | |
1151 | { | |
1152 | /* CR: cycle counter read trap control */ | |
1153 | if (arm_feature(env, ARM_FEATURE_V8) | |
1154 | && arm_current_el(env) == 0 | |
1155 | && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 | |
1156 | && isread) { | |
1157 | return CP_ACCESS_OK; | |
1158 | } | |
1159 | ||
1160 | return pmreg_access(env, ri, isread); | |
1161 | } | |
1162 | ||
033614c4 AL |
1163 | /* Returns true if the counter (pass 31 for PMCCNTR) should count events using |
1164 | * the current EL, security state, and register configuration. | |
1165 | */ | |
1166 | static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) | |
87124fde | 1167 | { |
033614c4 AL |
1168 | uint64_t filter; |
1169 | bool e, p, u, nsk, nsu, nsh, m; | |
1170 | bool enabled, prohibited, filtered; | |
1171 | bool secure = arm_is_secure(env); | |
1172 | int el = arm_current_el(env); | |
59dd089c RDC |
1173 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
1174 | uint8_t hpmn = mdcr_el2 & MDCR_HPMN; | |
87124fde | 1175 | |
cbbb3041 AJ |
1176 | if (!arm_feature(env, ARM_FEATURE_PMU)) { |
1177 | return false; | |
1178 | } | |
1179 | ||
033614c4 AL |
1180 | if (!arm_feature(env, ARM_FEATURE_EL2) || |
1181 | (counter < hpmn || counter == 31)) { | |
1182 | e = env->cp15.c9_pmcr & PMCRE; | |
1183 | } else { | |
59dd089c | 1184 | e = mdcr_el2 & MDCR_HPME; |
87124fde | 1185 | } |
033614c4 | 1186 | enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); |
87124fde | 1187 | |
033614c4 AL |
1188 | if (!secure) { |
1189 | if (el == 2 && (counter < hpmn || counter == 31)) { | |
59dd089c | 1190 | prohibited = mdcr_el2 & MDCR_HPMD; |
033614c4 AL |
1191 | } else { |
1192 | prohibited = false; | |
1193 | } | |
1194 | } else { | |
1195 | prohibited = arm_feature(env, ARM_FEATURE_EL3) && | |
db1f3afb | 1196 | !(env->cp15.mdcr_el3 & MDCR_SPME); |
033614c4 AL |
1197 | } |
1198 | ||
1199 | if (prohibited && counter == 31) { | |
1200 | prohibited = env->cp15.c9_pmcr & PMCRDP; | |
1201 | } | |
1202 | ||
5ecdd3e4 AL |
1203 | if (counter == 31) { |
1204 | filter = env->cp15.pmccfiltr_el0; | |
1205 | } else { | |
1206 | filter = env->cp15.c14_pmevtyper[counter]; | |
1207 | } | |
033614c4 AL |
1208 | |
1209 | p = filter & PMXEVTYPER_P; | |
1210 | u = filter & PMXEVTYPER_U; | |
1211 | nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); | |
1212 | nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); | |
1213 | nsh = arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); | |
1214 | m = arm_el_is_aa64(env, 1) && | |
1215 | arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); | |
1216 | ||
1217 | if (el == 0) { | |
1218 | filtered = secure ? u : u != nsu; | |
1219 | } else if (el == 1) { | |
1220 | filtered = secure ? p : p != nsk; | |
1221 | } else if (el == 2) { | |
1222 | filtered = !nsh; | |
1223 | } else { /* EL3 */ | |
1224 | filtered = m != p; | |
1225 | } | |
1226 | ||
5ecdd3e4 AL |
1227 | if (counter != 31) { |
1228 | /* | |
1229 | * If not checking PMCCNTR, ensure the counter is setup to an event we | |
1230 | * support | |
1231 | */ | |
1232 | uint16_t event = filter & PMXEVTYPER_EVTCOUNT; | |
1233 | if (!event_supported(event)) { | |
1234 | return false; | |
1235 | } | |
1236 | } | |
1237 | ||
033614c4 | 1238 | return enabled && !prohibited && !filtered; |
87124fde | 1239 | } |
033614c4 | 1240 | |
f4efb4b2 AL |
1241 | static void pmu_update_irq(CPUARMState *env) |
1242 | { | |
2fc0cc0e | 1243 | ARMCPU *cpu = env_archcpu(env); |
f4efb4b2 AL |
1244 | qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && |
1245 | (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); | |
1246 | } | |
1247 | ||
5d05b9d4 AL |
1248 | /* |
1249 | * Ensure c15_ccnt is the guest-visible count so that operations such as | |
1250 | * enabling/disabling the counter or filtering, modifying the count itself, | |
1251 | * etc. can be done logically. This is essentially a no-op if the counter is | |
1252 | * not enabled at the time of the call. | |
1253 | */ | |
f2b2f53f | 1254 | static void pmccntr_op_start(CPUARMState *env) |
ec7b4ce4 | 1255 | { |
b2e23725 | 1256 | uint64_t cycles = cycles_get_count(env); |
ec7b4ce4 | 1257 | |
033614c4 | 1258 | if (pmu_counter_enabled(env, 31)) { |
5d05b9d4 AL |
1259 | uint64_t eff_cycles = cycles; |
1260 | if (env->cp15.c9_pmcr & PMCRD) { | |
1261 | /* Increment once every 64 processor clock cycles */ | |
1262 | eff_cycles /= 64; | |
1263 | } | |
1264 | ||
f4efb4b2 AL |
1265 | uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta; |
1266 | ||
1267 | uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \ | |
1268 | 1ull << 63 : 1ull << 31; | |
1269 | if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { | |
1270 | env->cp15.c9_pmovsr |= (1 << 31); | |
1271 | pmu_update_irq(env); | |
1272 | } | |
1273 | ||
1274 | env->cp15.c15_ccnt = new_pmccntr; | |
ec7b4ce4 | 1275 | } |
5d05b9d4 AL |
1276 | env->cp15.c15_ccnt_delta = cycles; |
1277 | } | |
ec7b4ce4 | 1278 | |
5d05b9d4 AL |
1279 | /* |
1280 | * If PMCCNTR is enabled, recalculate the delta between the clock and the | |
1281 | * guest-visible count. A call to pmccntr_op_finish should follow every call to | |
1282 | * pmccntr_op_start. | |
1283 | */ | |
f2b2f53f | 1284 | static void pmccntr_op_finish(CPUARMState *env) |
5d05b9d4 | 1285 | { |
033614c4 | 1286 | if (pmu_counter_enabled(env, 31)) { |
4e7beb0c AL |
1287 | #ifndef CONFIG_USER_ONLY |
1288 | /* Calculate when the counter will next overflow */ | |
1289 | uint64_t remaining_cycles = -env->cp15.c15_ccnt; | |
1290 | if (!(env->cp15.c9_pmcr & PMCRLC)) { | |
1291 | remaining_cycles = (uint32_t)remaining_cycles; | |
1292 | } | |
1293 | int64_t overflow_in = cycles_ns_per(remaining_cycles); | |
1294 | ||
1295 | if (overflow_in > 0) { | |
1296 | int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
1297 | overflow_in; | |
2fc0cc0e | 1298 | ARMCPU *cpu = env_archcpu(env); |
4e7beb0c AL |
1299 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); |
1300 | } | |
1301 | #endif | |
5d05b9d4 | 1302 | |
4e7beb0c | 1303 | uint64_t prev_cycles = env->cp15.c15_ccnt_delta; |
5d05b9d4 AL |
1304 | if (env->cp15.c9_pmcr & PMCRD) { |
1305 | /* Increment once every 64 processor clock cycles */ | |
1306 | prev_cycles /= 64; | |
1307 | } | |
5d05b9d4 | 1308 | env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt; |
ec7b4ce4 AF |
1309 | } |
1310 | } | |
1311 | ||
5ecdd3e4 AL |
1312 | static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) |
1313 | { | |
1314 | ||
1315 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; | |
1316 | uint64_t count = 0; | |
1317 | if (event_supported(event)) { | |
1318 | uint16_t event_idx = supported_event_map[event]; | |
1319 | count = pm_events[event_idx].get_count(env); | |
1320 | } | |
1321 | ||
1322 | if (pmu_counter_enabled(env, counter)) { | |
f4efb4b2 AL |
1323 | uint32_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter]; |
1324 | ||
1325 | if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & INT32_MIN) { | |
1326 | env->cp15.c9_pmovsr |= (1 << counter); | |
1327 | pmu_update_irq(env); | |
1328 | } | |
1329 | env->cp15.c14_pmevcntr[counter] = new_pmevcntr; | |
5ecdd3e4 AL |
1330 | } |
1331 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1332 | } | |
1333 | ||
1334 | static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) | |
1335 | { | |
1336 | if (pmu_counter_enabled(env, counter)) { | |
4e7beb0c AL |
1337 | #ifndef CONFIG_USER_ONLY |
1338 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; | |
1339 | uint16_t event_idx = supported_event_map[event]; | |
1340 | uint64_t delta = UINT32_MAX - | |
1341 | (uint32_t)env->cp15.c14_pmevcntr[counter] + 1; | |
1342 | int64_t overflow_in = pm_events[event_idx].ns_per_count(delta); | |
1343 | ||
1344 | if (overflow_in > 0) { | |
1345 | int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
1346 | overflow_in; | |
2fc0cc0e | 1347 | ARMCPU *cpu = env_archcpu(env); |
4e7beb0c AL |
1348 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); |
1349 | } | |
1350 | #endif | |
1351 | ||
5ecdd3e4 AL |
1352 | env->cp15.c14_pmevcntr_delta[counter] -= |
1353 | env->cp15.c14_pmevcntr[counter]; | |
1354 | } | |
1355 | } | |
1356 | ||
5d05b9d4 AL |
1357 | void pmu_op_start(CPUARMState *env) |
1358 | { | |
5ecdd3e4 | 1359 | unsigned int i; |
5d05b9d4 | 1360 | pmccntr_op_start(env); |
5ecdd3e4 AL |
1361 | for (i = 0; i < pmu_num_counters(env); i++) { |
1362 | pmevcntr_op_start(env, i); | |
1363 | } | |
5d05b9d4 AL |
1364 | } |
1365 | ||
1366 | void pmu_op_finish(CPUARMState *env) | |
1367 | { | |
5ecdd3e4 | 1368 | unsigned int i; |
5d05b9d4 | 1369 | pmccntr_op_finish(env); |
5ecdd3e4 AL |
1370 | for (i = 0; i < pmu_num_counters(env); i++) { |
1371 | pmevcntr_op_finish(env, i); | |
1372 | } | |
5d05b9d4 AL |
1373 | } |
1374 | ||
033614c4 AL |
1375 | void pmu_pre_el_change(ARMCPU *cpu, void *ignored) |
1376 | { | |
1377 | pmu_op_start(&cpu->env); | |
1378 | } | |
1379 | ||
1380 | void pmu_post_el_change(ARMCPU *cpu, void *ignored) | |
1381 | { | |
1382 | pmu_op_finish(&cpu->env); | |
1383 | } | |
1384 | ||
4e7beb0c AL |
1385 | void arm_pmu_timer_cb(void *opaque) |
1386 | { | |
1387 | ARMCPU *cpu = opaque; | |
1388 | ||
1389 | /* | |
1390 | * Update all the counter values based on the current underlying counts, | |
1391 | * triggering interrupts to be raised, if necessary. pmu_op_finish() also | |
1392 | * has the effect of setting the cpu->pmu_timer to the next earliest time a | |
1393 | * counter may expire. | |
1394 | */ | |
1395 | pmu_op_start(&cpu->env); | |
1396 | pmu_op_finish(&cpu->env); | |
1397 | } | |
1398 | ||
c4241c7d PM |
1399 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1400 | uint64_t value) | |
200ac0ef | 1401 | { |
5d05b9d4 | 1402 | pmu_op_start(env); |
7c2cb42b AF |
1403 | |
1404 | if (value & PMCRC) { | |
1405 | /* The counter has been reset */ | |
1406 | env->cp15.c15_ccnt = 0; | |
1407 | } | |
1408 | ||
5ecdd3e4 AL |
1409 | if (value & PMCRP) { |
1410 | unsigned int i; | |
1411 | for (i = 0; i < pmu_num_counters(env); i++) { | |
1412 | env->cp15.c14_pmevcntr[i] = 0; | |
1413 | } | |
1414 | } | |
1415 | ||
62d96ff4 PM |
1416 | env->cp15.c9_pmcr &= ~PMCR_WRITEABLE_MASK; |
1417 | env->cp15.c9_pmcr |= (value & PMCR_WRITEABLE_MASK); | |
7c2cb42b | 1418 | |
5d05b9d4 | 1419 | pmu_op_finish(env); |
7c2cb42b AF |
1420 | } |
1421 | ||
0d4bfd7d AL |
1422 | static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1423 | uint64_t value) | |
1424 | { | |
1425 | unsigned int i; | |
1426 | for (i = 0; i < pmu_num_counters(env); i++) { | |
1427 | /* Increment a counter's count iff: */ | |
1428 | if ((value & (1 << i)) && /* counter's bit is set */ | |
1429 | /* counter is enabled and not filtered */ | |
1430 | pmu_counter_enabled(env, i) && | |
1431 | /* counter is SW_INCR */ | |
1432 | (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { | |
1433 | pmevcntr_op_start(env, i); | |
f4efb4b2 AL |
1434 | |
1435 | /* | |
1436 | * Detect if this write causes an overflow since we can't predict | |
1437 | * PMSWINC overflows like we can for other events | |
1438 | */ | |
1439 | uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; | |
1440 | ||
1441 | if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { | |
1442 | env->cp15.c9_pmovsr |= (1 << i); | |
1443 | pmu_update_irq(env); | |
1444 | } | |
1445 | ||
1446 | env->cp15.c14_pmevcntr[i] = new_pmswinc; | |
1447 | ||
0d4bfd7d AL |
1448 | pmevcntr_op_finish(env, i); |
1449 | } | |
1450 | } | |
1451 | } | |
1452 | ||
7c2cb42b AF |
1453 | static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1454 | { | |
5d05b9d4 AL |
1455 | uint64_t ret; |
1456 | pmccntr_op_start(env); | |
1457 | ret = env->cp15.c15_ccnt; | |
1458 | pmccntr_op_finish(env); | |
1459 | return ret; | |
7c2cb42b AF |
1460 | } |
1461 | ||
6b040780 WH |
1462 | static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1463 | uint64_t value) | |
1464 | { | |
1465 | /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and | |
1466 | * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the | |
1467 | * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are | |
1468 | * accessed. | |
1469 | */ | |
1470 | env->cp15.c9_pmselr = value & 0x1f; | |
1471 | } | |
1472 | ||
7c2cb42b AF |
1473 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1474 | uint64_t value) | |
1475 | { | |
5d05b9d4 AL |
1476 | pmccntr_op_start(env); |
1477 | env->cp15.c15_ccnt = value; | |
1478 | pmccntr_op_finish(env); | |
200ac0ef | 1479 | } |
421c7ebd PC |
1480 | |
1481 | static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1482 | uint64_t value) | |
1483 | { | |
1484 | uint64_t cur_val = pmccntr_read(env, NULL); | |
1485 | ||
1486 | pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); | |
1487 | } | |
1488 | ||
0614601c AF |
1489 | static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1490 | uint64_t value) | |
1491 | { | |
5d05b9d4 | 1492 | pmccntr_op_start(env); |
4b8afa1f AL |
1493 | env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0; |
1494 | pmccntr_op_finish(env); | |
1495 | } | |
1496 | ||
1497 | static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1498 | uint64_t value) | |
1499 | { | |
1500 | pmccntr_op_start(env); | |
1501 | /* M is not accessible from AArch32 */ | |
1502 | env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | | |
1503 | (value & PMCCFILTR); | |
5d05b9d4 | 1504 | pmccntr_op_finish(env); |
0614601c AF |
1505 | } |
1506 | ||
4b8afa1f AL |
1507 | static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri) |
1508 | { | |
1509 | /* M is not visible in AArch32 */ | |
1510 | return env->cp15.pmccfiltr_el0 & PMCCFILTR; | |
1511 | } | |
1512 | ||
c4241c7d | 1513 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1514 | uint64_t value) |
1515 | { | |
7ece99b1 | 1516 | value &= pmu_counter_mask(env); |
200ac0ef | 1517 | env->cp15.c9_pmcnten |= value; |
200ac0ef PM |
1518 | } |
1519 | ||
c4241c7d PM |
1520 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1521 | uint64_t value) | |
200ac0ef | 1522 | { |
7ece99b1 | 1523 | value &= pmu_counter_mask(env); |
200ac0ef | 1524 | env->cp15.c9_pmcnten &= ~value; |
200ac0ef PM |
1525 | } |
1526 | ||
c4241c7d PM |
1527 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1528 | uint64_t value) | |
200ac0ef | 1529 | { |
599b71e2 | 1530 | value &= pmu_counter_mask(env); |
200ac0ef | 1531 | env->cp15.c9_pmovsr &= ~value; |
f4efb4b2 | 1532 | pmu_update_irq(env); |
200ac0ef PM |
1533 | } |
1534 | ||
327dd510 AL |
1535 | static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1536 | uint64_t value) | |
1537 | { | |
1538 | value &= pmu_counter_mask(env); | |
1539 | env->cp15.c9_pmovsr |= value; | |
f4efb4b2 | 1540 | pmu_update_irq(env); |
327dd510 AL |
1541 | } |
1542 | ||
5ecdd3e4 AL |
1543 | static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1544 | uint64_t value, const uint8_t counter) | |
200ac0ef | 1545 | { |
5ecdd3e4 AL |
1546 | if (counter == 31) { |
1547 | pmccfiltr_write(env, ri, value); | |
1548 | } else if (counter < pmu_num_counters(env)) { | |
1549 | pmevcntr_op_start(env, counter); | |
1550 | ||
1551 | /* | |
1552 | * If this counter's event type is changing, store the current | |
1553 | * underlying count for the new type in c14_pmevcntr_delta[counter] so | |
1554 | * pmevcntr_op_finish has the correct baseline when it converts back to | |
1555 | * a delta. | |
1556 | */ | |
1557 | uint16_t old_event = env->cp15.c14_pmevtyper[counter] & | |
1558 | PMXEVTYPER_EVTCOUNT; | |
1559 | uint16_t new_event = value & PMXEVTYPER_EVTCOUNT; | |
1560 | if (old_event != new_event) { | |
1561 | uint64_t count = 0; | |
1562 | if (event_supported(new_event)) { | |
1563 | uint16_t event_idx = supported_event_map[new_event]; | |
1564 | count = pm_events[event_idx].get_count(env); | |
1565 | } | |
1566 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1567 | } | |
1568 | ||
1569 | env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK; | |
1570 | pmevcntr_op_finish(env, counter); | |
1571 | } | |
fdb86656 WH |
1572 | /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when |
1573 | * PMSELR value is equal to or greater than the number of implemented | |
1574 | * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. | |
1575 | */ | |
5ecdd3e4 AL |
1576 | } |
1577 | ||
1578 | static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1579 | const uint8_t counter) | |
1580 | { | |
1581 | if (counter == 31) { | |
1582 | return env->cp15.pmccfiltr_el0; | |
1583 | } else if (counter < pmu_num_counters(env)) { | |
1584 | return env->cp15.c14_pmevtyper[counter]; | |
1585 | } else { | |
1586 | /* | |
1587 | * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER | |
1588 | * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). | |
1589 | */ | |
1590 | return 0; | |
1591 | } | |
1592 | } | |
1593 | ||
1594 | static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, | |
1595 | uint64_t value) | |
1596 | { | |
1597 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1598 | pmevtyper_write(env, ri, value, counter); | |
1599 | } | |
1600 | ||
1601 | static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1602 | uint64_t value) | |
1603 | { | |
1604 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1605 | env->cp15.c14_pmevtyper[counter] = value; | |
1606 | ||
1607 | /* | |
1608 | * pmevtyper_rawwrite is called between a pair of pmu_op_start and | |
1609 | * pmu_op_finish calls when loading saved state for a migration. Because | |
1610 | * we're potentially updating the type of event here, the value written to | |
1611 | * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a | |
1612 | * different counter type. Therefore, we need to set this value to the | |
1613 | * current count for the counter type we're writing so that pmu_op_finish | |
1614 | * has the correct count for its calculation. | |
1615 | */ | |
1616 | uint16_t event = value & PMXEVTYPER_EVTCOUNT; | |
1617 | if (event_supported(event)) { | |
1618 | uint16_t event_idx = supported_event_map[event]; | |
1619 | env->cp15.c14_pmevcntr_delta[counter] = | |
1620 | pm_events[event_idx].get_count(env); | |
fdb86656 WH |
1621 | } |
1622 | } | |
1623 | ||
5ecdd3e4 AL |
1624 | static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) |
1625 | { | |
1626 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1627 | return pmevtyper_read(env, ri, counter); | |
1628 | } | |
1629 | ||
1630 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1631 | uint64_t value) | |
1632 | { | |
1633 | pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1634 | } | |
1635 | ||
fdb86656 WH |
1636 | static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1637 | { | |
5ecdd3e4 AL |
1638 | return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); |
1639 | } | |
1640 | ||
1641 | static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1642 | uint64_t value, uint8_t counter) | |
1643 | { | |
1644 | if (counter < pmu_num_counters(env)) { | |
1645 | pmevcntr_op_start(env, counter); | |
1646 | env->cp15.c14_pmevcntr[counter] = value; | |
1647 | pmevcntr_op_finish(env, counter); | |
1648 | } | |
1649 | /* | |
1650 | * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR | |
1651 | * are CONSTRAINED UNPREDICTABLE. | |
fdb86656 | 1652 | */ |
5ecdd3e4 AL |
1653 | } |
1654 | ||
1655 | static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1656 | uint8_t counter) | |
1657 | { | |
1658 | if (counter < pmu_num_counters(env)) { | |
1659 | uint64_t ret; | |
1660 | pmevcntr_op_start(env, counter); | |
1661 | ret = env->cp15.c14_pmevcntr[counter]; | |
1662 | pmevcntr_op_finish(env, counter); | |
1663 | return ret; | |
fdb86656 | 1664 | } else { |
5ecdd3e4 AL |
1665 | /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR |
1666 | * are CONSTRAINED UNPREDICTABLE. */ | |
fdb86656 WH |
1667 | return 0; |
1668 | } | |
200ac0ef PM |
1669 | } |
1670 | ||
5ecdd3e4 AL |
1671 | static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, |
1672 | uint64_t value) | |
1673 | { | |
1674 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1675 | pmevcntr_write(env, ri, value, counter); | |
1676 | } | |
1677 | ||
1678 | static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) | |
1679 | { | |
1680 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1681 | return pmevcntr_read(env, ri, counter); | |
1682 | } | |
1683 | ||
1684 | static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1685 | uint64_t value) | |
1686 | { | |
1687 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1688 | assert(counter < pmu_num_counters(env)); | |
1689 | env->cp15.c14_pmevcntr[counter] = value; | |
1690 | pmevcntr_write(env, ri, value, counter); | |
1691 | } | |
1692 | ||
1693 | static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri) | |
1694 | { | |
1695 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1696 | assert(counter < pmu_num_counters(env)); | |
1697 | return env->cp15.c14_pmevcntr[counter]; | |
1698 | } | |
1699 | ||
1700 | static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1701 | uint64_t value) | |
1702 | { | |
1703 | pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1704 | } | |
1705 | ||
1706 | static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1707 | { | |
1708 | return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); | |
1709 | } | |
1710 | ||
c4241c7d | 1711 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1712 | uint64_t value) |
1713 | { | |
6ecd0b6b AB |
1714 | if (arm_feature(env, ARM_FEATURE_V8)) { |
1715 | env->cp15.c9_pmuserenr = value & 0xf; | |
1716 | } else { | |
1717 | env->cp15.c9_pmuserenr = value & 1; | |
1718 | } | |
200ac0ef PM |
1719 | } |
1720 | ||
c4241c7d PM |
1721 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1722 | uint64_t value) | |
200ac0ef PM |
1723 | { |
1724 | /* We have no event counters so only the C bit can be changed */ | |
7ece99b1 | 1725 | value &= pmu_counter_mask(env); |
200ac0ef | 1726 | env->cp15.c9_pminten |= value; |
f4efb4b2 | 1727 | pmu_update_irq(env); |
200ac0ef PM |
1728 | } |
1729 | ||
c4241c7d PM |
1730 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1731 | uint64_t value) | |
200ac0ef | 1732 | { |
7ece99b1 | 1733 | value &= pmu_counter_mask(env); |
200ac0ef | 1734 | env->cp15.c9_pminten &= ~value; |
f4efb4b2 | 1735 | pmu_update_irq(env); |
200ac0ef PM |
1736 | } |
1737 | ||
c4241c7d PM |
1738 | static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1739 | uint64_t value) | |
8641136c | 1740 | { |
a505d7fe PM |
1741 | /* Note that even though the AArch64 view of this register has bits |
1742 | * [10:0] all RES0 we can only mask the bottom 5, to comply with the | |
1743 | * architectural requirements for bits which are RES0 only in some | |
1744 | * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 | |
1745 | * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) | |
1746 | */ | |
855ea66d | 1747 | raw_write(env, ri, value & ~0x1FULL); |
8641136c NR |
1748 | } |
1749 | ||
64e0e2de EI |
1750 | static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
1751 | { | |
ea22747c RH |
1752 | /* Begin with base v8.0 state. */ |
1753 | uint32_t valid_mask = 0x3fff; | |
2fc0cc0e | 1754 | ARMCPU *cpu = env_archcpu(env); |
ea22747c | 1755 | |
252e8c69 | 1756 | if (ri->state == ARM_CP_STATE_AA64) { |
10d0ef3e MN |
1757 | if (arm_feature(env, ARM_FEATURE_AARCH64) && |
1758 | !cpu_isar_feature(aa64_aa32_el1, cpu)) { | |
1759 | value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ | |
1760 | } | |
ea22747c | 1761 | valid_mask &= ~SCR_NET; |
252e8c69 RH |
1762 | |
1763 | if (cpu_isar_feature(aa64_lor, cpu)) { | |
1764 | valid_mask |= SCR_TLOR; | |
1765 | } | |
1766 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
1767 | valid_mask |= SCR_API | SCR_APK; | |
1768 | } | |
926c1b97 RDC |
1769 | if (cpu_isar_feature(aa64_sel2, cpu)) { |
1770 | valid_mask |= SCR_EEL2; | |
1771 | } | |
8ddb300b RH |
1772 | if (cpu_isar_feature(aa64_mte, cpu)) { |
1773 | valid_mask |= SCR_ATA; | |
1774 | } | |
ea22747c RH |
1775 | } else { |
1776 | valid_mask &= ~(SCR_RW | SCR_ST); | |
1777 | } | |
64e0e2de EI |
1778 | |
1779 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | |
1780 | valid_mask &= ~SCR_HCE; | |
1781 | ||
1782 | /* On ARMv7, SMD (or SCD as it is called in v7) is only | |
1783 | * supported if EL2 exists. The bit is UNK/SBZP when | |
1784 | * EL2 is unavailable. In QEMU ARMv7, we force it to always zero | |
1785 | * when EL2 is unavailable. | |
4eb27640 | 1786 | * On ARMv8, this bit is always available. |
64e0e2de | 1787 | */ |
4eb27640 GB |
1788 | if (arm_feature(env, ARM_FEATURE_V7) && |
1789 | !arm_feature(env, ARM_FEATURE_V8)) { | |
64e0e2de EI |
1790 | valid_mask &= ~SCR_SMD; |
1791 | } | |
1792 | } | |
1793 | ||
1794 | /* Clear all-context RES0 bits. */ | |
1795 | value &= valid_mask; | |
1796 | raw_write(env, ri, value); | |
1797 | } | |
1798 | ||
10d0ef3e MN |
1799 | static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1800 | { | |
1801 | /* | |
1802 | * scr_write will set the RES1 bits on an AArch64-only CPU. | |
1803 | * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise. | |
1804 | */ | |
1805 | scr_write(env, ri, 0); | |
1806 | } | |
1807 | ||
630fcd4d MZ |
1808 | static CPAccessResult access_aa64_tid2(CPUARMState *env, |
1809 | const ARMCPRegInfo *ri, | |
1810 | bool isread) | |
1811 | { | |
1812 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) { | |
1813 | return CP_ACCESS_TRAP_EL2; | |
1814 | } | |
1815 | ||
1816 | return CP_ACCESS_OK; | |
1817 | } | |
1818 | ||
c4241c7d | 1819 | static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
776d4e5c | 1820 | { |
2fc0cc0e | 1821 | ARMCPU *cpu = env_archcpu(env); |
b85a1fd6 FA |
1822 | |
1823 | /* Acquire the CSSELR index from the bank corresponding to the CCSIDR | |
1824 | * bank | |
1825 | */ | |
1826 | uint32_t index = A32_BANKED_REG_GET(env, csselr, | |
1827 | ri->secure & ARM_CP_SECSTATE_S); | |
1828 | ||
1829 | return cpu->ccsidr[index]; | |
776d4e5c PM |
1830 | } |
1831 | ||
c4241c7d PM |
1832 | static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1833 | uint64_t value) | |
776d4e5c | 1834 | { |
8d5c773e | 1835 | raw_write(env, ri, value & 0xf); |
776d4e5c PM |
1836 | } |
1837 | ||
1090b9c6 PM |
1838 | static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1839 | { | |
29a0af61 | 1840 | CPUState *cs = env_cpu(env); |
cc974d5c RDC |
1841 | bool el1 = arm_current_el(env) == 1; |
1842 | uint64_t hcr_el2 = el1 ? arm_hcr_el2_eff(env) : 0; | |
1090b9c6 PM |
1843 | uint64_t ret = 0; |
1844 | ||
cc974d5c | 1845 | if (hcr_el2 & HCR_IMO) { |
636540e9 PM |
1846 | if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { |
1847 | ret |= CPSR_I; | |
1848 | } | |
1849 | } else { | |
1850 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { | |
1851 | ret |= CPSR_I; | |
1852 | } | |
1090b9c6 | 1853 | } |
636540e9 | 1854 | |
cc974d5c | 1855 | if (hcr_el2 & HCR_FMO) { |
636540e9 PM |
1856 | if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { |
1857 | ret |= CPSR_F; | |
1858 | } | |
1859 | } else { | |
1860 | if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { | |
1861 | ret |= CPSR_F; | |
1862 | } | |
1090b9c6 | 1863 | } |
636540e9 | 1864 | |
1090b9c6 PM |
1865 | /* External aborts are not possible in QEMU so A bit is always clear */ |
1866 | return ret; | |
1867 | } | |
1868 | ||
93fbc983 MZ |
1869 | static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInfo *ri, |
1870 | bool isread) | |
1871 | { | |
1872 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID1)) { | |
1873 | return CP_ACCESS_TRAP_EL2; | |
1874 | } | |
1875 | ||
1876 | return CP_ACCESS_OK; | |
1877 | } | |
1878 | ||
1879 | static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInfo *ri, | |
1880 | bool isread) | |
1881 | { | |
1882 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
1883 | return access_aa64_tid1(env, ri, isread); | |
1884 | } | |
1885 | ||
1886 | return CP_ACCESS_OK; | |
1887 | } | |
1888 | ||
e9aa6c21 | 1889 | static const ARMCPRegInfo v7_cp_reginfo[] = { |
7d57f408 PM |
1890 | /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ |
1891 | { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
1892 | .access = PL1_W, .type = ARM_CP_NOP }, | |
200ac0ef PM |
1893 | /* Performance monitors are implementation defined in v7, |
1894 | * but with an ARM recommended set of registers, which we | |
ac689a2e | 1895 | * follow. |
200ac0ef PM |
1896 | * |
1897 | * Performance registers fall into three categories: | |
1898 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) | |
1899 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) | |
1900 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) | |
1901 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW | |
1902 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. | |
1903 | */ | |
1904 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 1905 | .access = PL0_RW, .type = ARM_CP_ALIAS, |
8521466b | 1906 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), |
fcd25206 PM |
1907 | .writefn = pmcntenset_write, |
1908 | .accessfn = pmreg_access, | |
1909 | .raw_writefn = raw_write }, | |
8521466b AF |
1910 | { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, |
1911 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, | |
1912 | .access = PL0_RW, .accessfn = pmreg_access, | |
1913 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, | |
1914 | .writefn = pmcntenset_write, .raw_writefn = raw_write }, | |
200ac0ef | 1915 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
8521466b AF |
1916 | .access = PL0_RW, |
1917 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
1918 | .accessfn = pmreg_access, |
1919 | .writefn = pmcntenclr_write, | |
7a0e58fa | 1920 | .type = ARM_CP_ALIAS }, |
8521466b AF |
1921 | { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, |
1922 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, | |
1923 | .access = PL0_RW, .accessfn = pmreg_access, | |
7a0e58fa | 1924 | .type = ARM_CP_ALIAS, |
8521466b AF |
1925 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), |
1926 | .writefn = pmcntenclr_write }, | |
200ac0ef | 1927 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
f4efb4b2 | 1928 | .access = PL0_RW, .type = ARM_CP_IO, |
e4e91a21 | 1929 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
fcd25206 PM |
1930 | .accessfn = pmreg_access, |
1931 | .writefn = pmovsr_write, | |
1932 | .raw_writefn = raw_write }, | |
978364f1 AF |
1933 | { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, |
1934 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, | |
1935 | .access = PL0_RW, .accessfn = pmreg_access, | |
f4efb4b2 | 1936 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
978364f1 AF |
1937 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
1938 | .writefn = pmovsr_write, | |
1939 | .raw_writefn = raw_write }, | |
200ac0ef | 1940 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
f4efb4b2 AL |
1941 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
1942 | .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
0d4bfd7d AL |
1943 | .writefn = pmswinc_write }, |
1944 | { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64, | |
1945 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4, | |
f4efb4b2 AL |
1946 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
1947 | .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
0d4bfd7d | 1948 | .writefn = pmswinc_write }, |
6b040780 WH |
1949 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, |
1950 | .access = PL0_RW, .type = ARM_CP_ALIAS, | |
1951 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), | |
6ecd0b6b | 1952 | .accessfn = pmreg_access_selr, .writefn = pmselr_write, |
6b040780 WH |
1953 | .raw_writefn = raw_write}, |
1954 | { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, | |
1955 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, | |
6ecd0b6b | 1956 | .access = PL0_RW, .accessfn = pmreg_access_selr, |
6b040780 WH |
1957 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), |
1958 | .writefn = pmselr_write, .raw_writefn = raw_write, }, | |
200ac0ef | 1959 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
169c8938 | 1960 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO, |
421c7ebd | 1961 | .readfn = pmccntr_read, .writefn = pmccntr_write32, |
6ecd0b6b | 1962 | .accessfn = pmreg_access_ccntr }, |
8521466b AF |
1963 | { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, |
1964 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, | |
6ecd0b6b | 1965 | .access = PL0_RW, .accessfn = pmreg_access_ccntr, |
8521466b | 1966 | .type = ARM_CP_IO, |
980ebe87 AL |
1967 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt), |
1968 | .readfn = pmccntr_read, .writefn = pmccntr_write, | |
1969 | .raw_readfn = raw_read, .raw_writefn = raw_write, }, | |
4b8afa1f AL |
1970 | { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7, |
1971 | .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32, | |
1972 | .access = PL0_RW, .accessfn = pmreg_access, | |
1973 | .type = ARM_CP_ALIAS | ARM_CP_IO, | |
1974 | .resetvalue = 0, }, | |
8521466b AF |
1975 | { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, |
1976 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, | |
980ebe87 | 1977 | .writefn = pmccfiltr_write, .raw_writefn = raw_write, |
8521466b AF |
1978 | .access = PL0_RW, .accessfn = pmreg_access, |
1979 | .type = ARM_CP_IO, | |
1980 | .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), | |
1981 | .resetvalue = 0, }, | |
200ac0ef | 1982 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
5ecdd3e4 AL |
1983 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
1984 | .accessfn = pmreg_access, | |
fdb86656 WH |
1985 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
1986 | { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, | |
1987 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, | |
5ecdd3e4 AL |
1988 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
1989 | .accessfn = pmreg_access, | |
fdb86656 | 1990 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
200ac0ef | 1991 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
5ecdd3e4 AL |
1992 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
1993 | .accessfn = pmreg_access_xevcntr, | |
1994 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, | |
1995 | { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64, | |
1996 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2, | |
1997 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
1998 | .accessfn = pmreg_access_xevcntr, | |
1999 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, | |
200ac0ef | 2000 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
1fce1ba9 | 2001 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, |
e4e91a21 | 2002 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr), |
200ac0ef | 2003 | .resetvalue = 0, |
d4e6df63 | 2004 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
8a83ffc2 AF |
2005 | { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, |
2006 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, | |
1fce1ba9 | 2007 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, |
8a83ffc2 AF |
2008 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), |
2009 | .resetvalue = 0, | |
2010 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, | |
200ac0ef | 2011 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
1fce1ba9 | 2012 | .access = PL1_RW, .accessfn = access_tpm, |
b7d793ad | 2013 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
e6ec5457 | 2014 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), |
200ac0ef | 2015 | .resetvalue = 0, |
d4e6df63 | 2016 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
e6ec5457 WH |
2017 | { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, |
2018 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, | |
2019 | .access = PL1_RW, .accessfn = access_tpm, | |
2020 | .type = ARM_CP_IO, | |
2021 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
2022 | .writefn = pmintenset_write, .raw_writefn = raw_write, | |
2023 | .resetvalue = 0x0 }, | |
200ac0ef | 2024 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
fc5f6856 | 2025 | .access = PL1_RW, .accessfn = access_tpm, |
887c0f15 | 2026 | .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, |
200ac0ef | 2027 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
b061a82b | 2028 | .writefn = pmintenclr_write, }, |
978364f1 AF |
2029 | { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, |
2030 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, | |
fc5f6856 | 2031 | .access = PL1_RW, .accessfn = access_tpm, |
887c0f15 | 2032 | .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, |
978364f1 AF |
2033 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
2034 | .writefn = pmintenclr_write }, | |
7da845b0 PM |
2035 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, |
2036 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | |
630fcd4d MZ |
2037 | .access = PL1_R, |
2038 | .accessfn = access_aa64_tid2, | |
2039 | .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, | |
7da845b0 PM |
2040 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, |
2041 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | |
630fcd4d MZ |
2042 | .access = PL1_RW, |
2043 | .accessfn = access_aa64_tid2, | |
2044 | .writefn = csselr_write, .resetvalue = 0, | |
b85a1fd6 FA |
2045 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), |
2046 | offsetof(CPUARMState, cp15.csselr_ns) } }, | |
776d4e5c PM |
2047 | /* Auxiliary ID register: this actually has an IMPDEF value but for now |
2048 | * just RAZ for all cores: | |
2049 | */ | |
0ff644a7 PM |
2050 | { .name = "AIDR", .state = ARM_CP_STATE_BOTH, |
2051 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, | |
93fbc983 MZ |
2052 | .access = PL1_R, .type = ARM_CP_CONST, |
2053 | .accessfn = access_aa64_tid1, | |
2054 | .resetvalue = 0 }, | |
f32cdad5 PM |
2055 | /* Auxiliary fault status registers: these also are IMPDEF, and we |
2056 | * choose to RAZ/WI for all cores. | |
2057 | */ | |
2058 | { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, | |
2059 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, | |
84929218 RH |
2060 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
2061 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
f32cdad5 PM |
2062 | { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, |
2063 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, | |
84929218 RH |
2064 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
2065 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b0fe2427 PM |
2066 | /* MAIR can just read-as-written because we don't implement caches |
2067 | * and so don't need to care about memory attributes. | |
2068 | */ | |
2069 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | |
2070 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | |
84929218 RH |
2071 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
2072 | .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), | |
b0fe2427 | 2073 | .resetvalue = 0 }, |
4cfb8ad8 PM |
2074 | { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, |
2075 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, | |
2076 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), | |
2077 | .resetvalue = 0 }, | |
b0fe2427 PM |
2078 | /* For non-long-descriptor page tables these are PRRR and NMRR; |
2079 | * regardless they still act as reads-as-written for QEMU. | |
b0fe2427 | 2080 | */ |
1281f8e3 | 2081 | /* MAIR0/1 are defined separately from their 64-bit counterpart which |
be693c87 GB |
2082 | * allows them to assign the correct fieldoffset based on the endianness |
2083 | * handled in the field definitions. | |
2084 | */ | |
a903c449 | 2085 | { .name = "MAIR0", .state = ARM_CP_STATE_AA32, |
84929218 RH |
2086 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, |
2087 | .access = PL1_RW, .accessfn = access_tvm_trvm, | |
be693c87 GB |
2088 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), |
2089 | offsetof(CPUARMState, cp15.mair0_ns) }, | |
b0fe2427 | 2090 | .resetfn = arm_cp_reset_ignore }, |
a903c449 | 2091 | { .name = "MAIR1", .state = ARM_CP_STATE_AA32, |
84929218 RH |
2092 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, |
2093 | .access = PL1_RW, .accessfn = access_tvm_trvm, | |
be693c87 GB |
2094 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), |
2095 | offsetof(CPUARMState, cp15.mair1_ns) }, | |
b0fe2427 | 2096 | .resetfn = arm_cp_reset_ignore }, |
1090b9c6 PM |
2097 | { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, |
2098 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, | |
7a0e58fa | 2099 | .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, |
995939a6 PM |
2100 | /* 32 bit ITLB invalidates */ |
2101 | { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, | |
30881b73 RH |
2102 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2103 | .writefn = tlbiall_write }, | |
995939a6 | 2104 | { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, |
30881b73 RH |
2105 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2106 | .writefn = tlbimva_write }, | |
995939a6 | 2107 | { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, |
30881b73 RH |
2108 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2109 | .writefn = tlbiasid_write }, | |
995939a6 PM |
2110 | /* 32 bit DTLB invalidates */ |
2111 | { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, | |
30881b73 RH |
2112 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2113 | .writefn = tlbiall_write }, | |
995939a6 | 2114 | { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, |
30881b73 RH |
2115 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2116 | .writefn = tlbimva_write }, | |
995939a6 | 2117 | { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, |
30881b73 RH |
2118 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2119 | .writefn = tlbiasid_write }, | |
995939a6 PM |
2120 | /* 32 bit TLB invalidates */ |
2121 | { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | |
30881b73 RH |
2122 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2123 | .writefn = tlbiall_write }, | |
995939a6 | 2124 | { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
30881b73 RH |
2125 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2126 | .writefn = tlbimva_write }, | |
995939a6 | 2127 | { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
30881b73 RH |
2128 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2129 | .writefn = tlbiasid_write }, | |
995939a6 | 2130 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
30881b73 RH |
2131 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2132 | .writefn = tlbimvaa_write }, | |
995939a6 PM |
2133 | }; |
2134 | ||
2135 | static const ARMCPRegInfo v7mp_cp_reginfo[] = { | |
2136 | /* 32 bit TLB invalidates, Inner Shareable */ | |
2137 | { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | |
30881b73 RH |
2138 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2139 | .writefn = tlbiall_is_write }, | |
995939a6 | 2140 | { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
30881b73 RH |
2141 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2142 | .writefn = tlbimva_is_write }, | |
995939a6 | 2143 | { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
30881b73 | 2144 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
fa439fc5 | 2145 | .writefn = tlbiasid_is_write }, |
995939a6 | 2146 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
30881b73 | 2147 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
fa439fc5 | 2148 | .writefn = tlbimvaa_is_write }, |
e9aa6c21 PM |
2149 | }; |
2150 | ||
327dd510 AL |
2151 | static const ARMCPRegInfo pmovsset_cp_reginfo[] = { |
2152 | /* PMOVSSET is not implemented in v7 before v7ve */ | |
2153 | { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3, | |
2154 | .access = PL0_RW, .accessfn = pmreg_access, | |
f4efb4b2 | 2155 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
327dd510 AL |
2156 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
2157 | .writefn = pmovsset_write, | |
2158 | .raw_writefn = raw_write }, | |
2159 | { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64, | |
2160 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3, | |
2161 | .access = PL0_RW, .accessfn = pmreg_access, | |
f4efb4b2 | 2162 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
327dd510 AL |
2163 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
2164 | .writefn = pmovsset_write, | |
2165 | .raw_writefn = raw_write }, | |
327dd510 AL |
2166 | }; |
2167 | ||
c4241c7d PM |
2168 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2169 | uint64_t value) | |
c326b979 PM |
2170 | { |
2171 | value &= 1; | |
2172 | env->teecr = value; | |
c326b979 PM |
2173 | } |
2174 | ||
cc7613bf PM |
2175 | static CPAccessResult teecr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2176 | bool isread) | |
2177 | { | |
2178 | /* | |
2179 | * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE | |
2180 | * at all, so we don't need to check whether we're v8A. | |
2181 | */ | |
2182 | if (arm_current_el(env) < 2 && !arm_is_secure_below_el3(env) && | |
2183 | (env->cp15.hstr_el2 & HSTR_TTEE)) { | |
2184 | return CP_ACCESS_TRAP_EL2; | |
2185 | } | |
2186 | return CP_ACCESS_OK; | |
2187 | } | |
2188 | ||
3f208fd7 PM |
2189 | static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2190 | bool isread) | |
c326b979 | 2191 | { |
dcbff19b | 2192 | if (arm_current_el(env) == 0 && (env->teecr & 1)) { |
92611c00 | 2193 | return CP_ACCESS_TRAP; |
c326b979 | 2194 | } |
cc7613bf | 2195 | return teecr_access(env, ri, isread); |
c326b979 PM |
2196 | } |
2197 | ||
2198 | static const ARMCPRegInfo t2ee_cp_reginfo[] = { | |
2199 | { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, | |
2200 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), | |
2201 | .resetvalue = 0, | |
cc7613bf | 2202 | .writefn = teecr_write, .accessfn = teecr_access }, |
c326b979 PM |
2203 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, |
2204 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | |
92611c00 | 2205 | .accessfn = teehbr_access, .resetvalue = 0 }, |
c326b979 PM |
2206 | }; |
2207 | ||
4d31c596 | 2208 | static const ARMCPRegInfo v6k_cp_reginfo[] = { |
e4fe830b PM |
2209 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, |
2210 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | |
2211 | .access = PL0_RW, | |
54bf36ed | 2212 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, |
4d31c596 PM |
2213 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
2214 | .access = PL0_RW, | |
54bf36ed FA |
2215 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), |
2216 | offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, | |
e4fe830b PM |
2217 | .resetfn = arm_cp_reset_ignore }, |
2218 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | |
2219 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | |
2220 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
2221 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), |
2222 | .resetvalue = 0}, | |
4d31c596 PM |
2223 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
2224 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
2225 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), |
2226 | offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, | |
e4fe830b | 2227 | .resetfn = arm_cp_reset_ignore }, |
54bf36ed | 2228 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, |
e4fe830b | 2229 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, |
4d31c596 | 2230 | .access = PL1_RW, |
54bf36ed FA |
2231 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, |
2232 | { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, | |
2233 | .access = PL1_RW, | |
2234 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), | |
2235 | offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, | |
2236 | .resetvalue = 0 }, | |
4d31c596 PM |
2237 | }; |
2238 | ||
55d284af PM |
2239 | #ifndef CONFIG_USER_ONLY |
2240 | ||
3f208fd7 PM |
2241 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2242 | bool isread) | |
00108f2d | 2243 | { |
75502672 PM |
2244 | /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. |
2245 | * Writable only at the highest implemented exception level. | |
2246 | */ | |
2247 | int el = arm_current_el(env); | |
5bc84371 RH |
2248 | uint64_t hcr; |
2249 | uint32_t cntkctl; | |
75502672 PM |
2250 | |
2251 | switch (el) { | |
2252 | case 0: | |
5bc84371 RH |
2253 | hcr = arm_hcr_el2_eff(env); |
2254 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2255 | cntkctl = env->cp15.cnthctl_el2; | |
2256 | } else { | |
2257 | cntkctl = env->cp15.c14_cntkctl; | |
2258 | } | |
2259 | if (!extract32(cntkctl, 0, 2)) { | |
75502672 PM |
2260 | return CP_ACCESS_TRAP; |
2261 | } | |
2262 | break; | |
2263 | case 1: | |
2264 | if (!isread && ri->state == ARM_CP_STATE_AA32 && | |
2265 | arm_is_secure_below_el3(env)) { | |
2266 | /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ | |
2267 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2268 | } | |
2269 | break; | |
2270 | case 2: | |
2271 | case 3: | |
2272 | break; | |
00108f2d | 2273 | } |
75502672 PM |
2274 | |
2275 | if (!isread && el < arm_highest_el(env)) { | |
2276 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2277 | } | |
2278 | ||
00108f2d PM |
2279 | return CP_ACCESS_OK; |
2280 | } | |
2281 | ||
3f208fd7 PM |
2282 | static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, |
2283 | bool isread) | |
00108f2d | 2284 | { |
0b6440af | 2285 | unsigned int cur_el = arm_current_el(env); |
e6ef0169 | 2286 | bool has_el2 = arm_is_el2_enabled(env); |
5bc84371 | 2287 | uint64_t hcr = arm_hcr_el2_eff(env); |
0b6440af | 2288 | |
5bc84371 RH |
2289 | switch (cur_el) { |
2290 | case 0: | |
2291 | /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */ | |
2292 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2293 | return (extract32(env->cp15.cnthctl_el2, timeridx, 1) | |
2294 | ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); | |
2295 | } | |
0b6440af | 2296 | |
5bc84371 RH |
2297 | /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */ |
2298 | if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) { | |
2299 | return CP_ACCESS_TRAP; | |
2300 | } | |
2301 | ||
2302 | /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */ | |
2303 | if (hcr & HCR_E2H) { | |
2304 | if (timeridx == GTIMER_PHYS && | |
2305 | !extract32(env->cp15.cnthctl_el2, 10, 1)) { | |
2306 | return CP_ACCESS_TRAP_EL2; | |
2307 | } | |
2308 | } else { | |
2309 | /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */ | |
e6ef0169 | 2310 | if (has_el2 && timeridx == GTIMER_PHYS && |
5bc84371 RH |
2311 | !extract32(env->cp15.cnthctl_el2, 1, 1)) { |
2312 | return CP_ACCESS_TRAP_EL2; | |
2313 | } | |
2314 | } | |
2315 | break; | |
2316 | ||
2317 | case 1: | |
2318 | /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */ | |
e6ef0169 | 2319 | if (has_el2 && timeridx == GTIMER_PHYS && |
5bc84371 RH |
2320 | (hcr & HCR_E2H |
2321 | ? !extract32(env->cp15.cnthctl_el2, 10, 1) | |
2322 | : !extract32(env->cp15.cnthctl_el2, 0, 1))) { | |
2323 | return CP_ACCESS_TRAP_EL2; | |
2324 | } | |
2325 | break; | |
0b6440af | 2326 | } |
00108f2d PM |
2327 | return CP_ACCESS_OK; |
2328 | } | |
2329 | ||
3f208fd7 PM |
2330 | static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, |
2331 | bool isread) | |
00108f2d | 2332 | { |
0b6440af | 2333 | unsigned int cur_el = arm_current_el(env); |
e6ef0169 | 2334 | bool has_el2 = arm_is_el2_enabled(env); |
5bc84371 | 2335 | uint64_t hcr = arm_hcr_el2_eff(env); |
0b6440af | 2336 | |
5bc84371 RH |
2337 | switch (cur_el) { |
2338 | case 0: | |
2339 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2340 | /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */ | |
2341 | return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1) | |
2342 | ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); | |
2343 | } | |
0b6440af | 2344 | |
5bc84371 RH |
2345 | /* |
2346 | * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from | |
2347 | * EL0 if EL0[PV]TEN is zero. | |
2348 | */ | |
2349 | if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { | |
2350 | return CP_ACCESS_TRAP; | |
2351 | } | |
2352 | /* fall through */ | |
2353 | ||
2354 | case 1: | |
e6ef0169 | 2355 | if (has_el2 && timeridx == GTIMER_PHYS) { |
5bc84371 RH |
2356 | if (hcr & HCR_E2H) { |
2357 | /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */ | |
2358 | if (!extract32(env->cp15.cnthctl_el2, 11, 1)) { | |
2359 | return CP_ACCESS_TRAP_EL2; | |
2360 | } | |
2361 | } else { | |
2362 | /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */ | |
2363 | if (!extract32(env->cp15.cnthctl_el2, 1, 1)) { | |
2364 | return CP_ACCESS_TRAP_EL2; | |
2365 | } | |
2366 | } | |
2367 | } | |
2368 | break; | |
0b6440af | 2369 | } |
00108f2d PM |
2370 | return CP_ACCESS_OK; |
2371 | } | |
2372 | ||
2373 | static CPAccessResult gt_pct_access(CPUARMState *env, | |
3f208fd7 PM |
2374 | const ARMCPRegInfo *ri, |
2375 | bool isread) | |
00108f2d | 2376 | { |
3f208fd7 | 2377 | return gt_counter_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2378 | } |
2379 | ||
2380 | static CPAccessResult gt_vct_access(CPUARMState *env, | |
3f208fd7 PM |
2381 | const ARMCPRegInfo *ri, |
2382 | bool isread) | |
00108f2d | 2383 | { |
3f208fd7 | 2384 | return gt_counter_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2385 | } |
2386 | ||
3f208fd7 PM |
2387 | static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2388 | bool isread) | |
00108f2d | 2389 | { |
3f208fd7 | 2390 | return gt_timer_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2391 | } |
2392 | ||
3f208fd7 PM |
2393 | static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2394 | bool isread) | |
00108f2d | 2395 | { |
3f208fd7 | 2396 | return gt_timer_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2397 | } |
2398 | ||
b4d3978c | 2399 | static CPAccessResult gt_stimer_access(CPUARMState *env, |
3f208fd7 PM |
2400 | const ARMCPRegInfo *ri, |
2401 | bool isread) | |
b4d3978c PM |
2402 | { |
2403 | /* The AArch64 register view of the secure physical timer is | |
2404 | * always accessible from EL3, and configurably accessible from | |
2405 | * Secure EL1. | |
2406 | */ | |
2407 | switch (arm_current_el(env)) { | |
2408 | case 1: | |
2409 | if (!arm_is_secure(env)) { | |
2410 | return CP_ACCESS_TRAP; | |
2411 | } | |
2412 | if (!(env->cp15.scr_el3 & SCR_ST)) { | |
2413 | return CP_ACCESS_TRAP_EL3; | |
2414 | } | |
2415 | return CP_ACCESS_OK; | |
2416 | case 0: | |
2417 | case 2: | |
2418 | return CP_ACCESS_TRAP; | |
2419 | case 3: | |
2420 | return CP_ACCESS_OK; | |
2421 | default: | |
2422 | g_assert_not_reached(); | |
2423 | } | |
2424 | } | |
2425 | ||
55d284af PM |
2426 | static uint64_t gt_get_countervalue(CPUARMState *env) |
2427 | { | |
7def8754 AJ |
2428 | ARMCPU *cpu = env_archcpu(env); |
2429 | ||
2430 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu); | |
55d284af PM |
2431 | } |
2432 | ||
2433 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) | |
2434 | { | |
2435 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; | |
2436 | ||
2437 | if (gt->ctl & 1) { | |
2438 | /* Timer enabled: calculate and set current ISTATUS, irq, and | |
2439 | * reset timer to when ISTATUS next has to change | |
2440 | */ | |
edac4d8a EI |
2441 | uint64_t offset = timeridx == GTIMER_VIRT ? |
2442 | cpu->env.cp15.cntvoff_el2 : 0; | |
55d284af PM |
2443 | uint64_t count = gt_get_countervalue(&cpu->env); |
2444 | /* Note that this must be unsigned 64 bit arithmetic: */ | |
edac4d8a | 2445 | int istatus = count - offset >= gt->cval; |
55d284af | 2446 | uint64_t nexttick; |
194cbc49 | 2447 | int irqstate; |
55d284af PM |
2448 | |
2449 | gt->ctl = deposit32(gt->ctl, 2, 1, istatus); | |
194cbc49 PM |
2450 | |
2451 | irqstate = (istatus && !(gt->ctl & 2)); | |
2452 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
2453 | ||
55d284af PM |
2454 | if (istatus) { |
2455 | /* Next transition is when count rolls back over to zero */ | |
2456 | nexttick = UINT64_MAX; | |
2457 | } else { | |
2458 | /* Next transition is when we hit cval */ | |
edac4d8a | 2459 | nexttick = gt->cval + offset; |
55d284af PM |
2460 | } |
2461 | /* Note that the desired next expiry time might be beyond the | |
2462 | * signed-64-bit range of a QEMUTimer -- in this case we just | |
2463 | * set the timer for as far in the future as possible. When the | |
2464 | * timer expires we will reset the timer for any remaining period. | |
2465 | */ | |
7def8754 | 2466 | if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { |
4a0245b6 AJ |
2467 | timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX); |
2468 | } else { | |
2469 | timer_mod(cpu->gt_timer[timeridx], nexttick); | |
55d284af | 2470 | } |
194cbc49 | 2471 | trace_arm_gt_recalc(timeridx, irqstate, nexttick); |
55d284af PM |
2472 | } else { |
2473 | /* Timer disabled: ISTATUS and timer output always clear */ | |
2474 | gt->ctl &= ~4; | |
2475 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); | |
bc72ad67 | 2476 | timer_del(cpu->gt_timer[timeridx]); |
194cbc49 | 2477 | trace_arm_gt_recalc_disabled(timeridx); |
55d284af PM |
2478 | } |
2479 | } | |
2480 | ||
0e3eca4c EI |
2481 | static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, |
2482 | int timeridx) | |
55d284af | 2483 | { |
2fc0cc0e | 2484 | ARMCPU *cpu = env_archcpu(env); |
55d284af | 2485 | |
bc72ad67 | 2486 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
2487 | } |
2488 | ||
c4241c7d | 2489 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
55d284af | 2490 | { |
c4241c7d | 2491 | return gt_get_countervalue(env); |
55d284af PM |
2492 | } |
2493 | ||
53d1f856 RH |
2494 | static uint64_t gt_virt_cnt_offset(CPUARMState *env) |
2495 | { | |
2496 | uint64_t hcr; | |
2497 | ||
2498 | switch (arm_current_el(env)) { | |
2499 | case 2: | |
2500 | hcr = arm_hcr_el2_eff(env); | |
2501 | if (hcr & HCR_E2H) { | |
2502 | return 0; | |
2503 | } | |
2504 | break; | |
2505 | case 0: | |
2506 | hcr = arm_hcr_el2_eff(env); | |
2507 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2508 | return 0; | |
2509 | } | |
2510 | break; | |
2511 | } | |
2512 | ||
2513 | return env->cp15.cntvoff_el2; | |
2514 | } | |
2515 | ||
edac4d8a EI |
2516 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2517 | { | |
53d1f856 | 2518 | return gt_get_countervalue(env) - gt_virt_cnt_offset(env); |
edac4d8a EI |
2519 | } |
2520 | ||
c4241c7d | 2521 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2522 | int timeridx, |
c4241c7d | 2523 | uint64_t value) |
55d284af | 2524 | { |
194cbc49 | 2525 | trace_arm_gt_cval_write(timeridx, value); |
55d284af | 2526 | env->cp15.c14_timer[timeridx].cval = value; |
2fc0cc0e | 2527 | gt_recalc_timer(env_archcpu(env), timeridx); |
55d284af | 2528 | } |
c4241c7d | 2529 | |
0e3eca4c EI |
2530 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, |
2531 | int timeridx) | |
55d284af | 2532 | { |
53d1f856 RH |
2533 | uint64_t offset = 0; |
2534 | ||
2535 | switch (timeridx) { | |
2536 | case GTIMER_VIRT: | |
8c94b071 | 2537 | case GTIMER_HYPVIRT: |
53d1f856 RH |
2538 | offset = gt_virt_cnt_offset(env); |
2539 | break; | |
2540 | } | |
55d284af | 2541 | |
c4241c7d | 2542 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - |
edac4d8a | 2543 | (gt_get_countervalue(env) - offset)); |
55d284af PM |
2544 | } |
2545 | ||
c4241c7d | 2546 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2547 | int timeridx, |
c4241c7d | 2548 | uint64_t value) |
55d284af | 2549 | { |
53d1f856 RH |
2550 | uint64_t offset = 0; |
2551 | ||
2552 | switch (timeridx) { | |
2553 | case GTIMER_VIRT: | |
8c94b071 | 2554 | case GTIMER_HYPVIRT: |
53d1f856 RH |
2555 | offset = gt_virt_cnt_offset(env); |
2556 | break; | |
2557 | } | |
55d284af | 2558 | |
194cbc49 | 2559 | trace_arm_gt_tval_write(timeridx, value); |
edac4d8a | 2560 | env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + |
18084b2f | 2561 | sextract64(value, 0, 32); |
2fc0cc0e | 2562 | gt_recalc_timer(env_archcpu(env), timeridx); |
55d284af PM |
2563 | } |
2564 | ||
c4241c7d | 2565 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2566 | int timeridx, |
c4241c7d | 2567 | uint64_t value) |
55d284af | 2568 | { |
2fc0cc0e | 2569 | ARMCPU *cpu = env_archcpu(env); |
55d284af PM |
2570 | uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; |
2571 | ||
194cbc49 | 2572 | trace_arm_gt_ctl_write(timeridx, value); |
d3afacc7 | 2573 | env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); |
55d284af PM |
2574 | if ((oldval ^ value) & 1) { |
2575 | /* Enable toggled */ | |
2576 | gt_recalc_timer(cpu, timeridx); | |
d3afacc7 | 2577 | } else if ((oldval ^ value) & 2) { |
55d284af PM |
2578 | /* IMASK toggled: don't need to recalculate, |
2579 | * just set the interrupt line based on ISTATUS | |
2580 | */ | |
194cbc49 PM |
2581 | int irqstate = (oldval & 4) && !(value & 2); |
2582 | ||
2583 | trace_arm_gt_imask_toggle(timeridx, irqstate); | |
2584 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
55d284af | 2585 | } |
55d284af PM |
2586 | } |
2587 | ||
0e3eca4c EI |
2588 | static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2589 | { | |
2590 | gt_timer_reset(env, ri, GTIMER_PHYS); | |
2591 | } | |
2592 | ||
2593 | static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2594 | uint64_t value) | |
2595 | { | |
2596 | gt_cval_write(env, ri, GTIMER_PHYS, value); | |
2597 | } | |
2598 | ||
2599 | static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2600 | { | |
2601 | return gt_tval_read(env, ri, GTIMER_PHYS); | |
2602 | } | |
2603 | ||
2604 | static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2605 | uint64_t value) | |
2606 | { | |
2607 | gt_tval_write(env, ri, GTIMER_PHYS, value); | |
2608 | } | |
2609 | ||
2610 | static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2611 | uint64_t value) | |
2612 | { | |
2613 | gt_ctl_write(env, ri, GTIMER_PHYS, value); | |
2614 | } | |
2615 | ||
bb5972e4 RH |
2616 | static int gt_phys_redir_timeridx(CPUARMState *env) |
2617 | { | |
2618 | switch (arm_mmu_idx(env)) { | |
2619 | case ARMMMUIdx_E20_0: | |
2620 | case ARMMMUIdx_E20_2: | |
452ef8cb | 2621 | case ARMMMUIdx_E20_2_PAN: |
b6ad6062 RDC |
2622 | case ARMMMUIdx_SE20_0: |
2623 | case ARMMMUIdx_SE20_2: | |
2624 | case ARMMMUIdx_SE20_2_PAN: | |
bb5972e4 RH |
2625 | return GTIMER_HYP; |
2626 | default: | |
2627 | return GTIMER_PHYS; | |
2628 | } | |
2629 | } | |
2630 | ||
2631 | static int gt_virt_redir_timeridx(CPUARMState *env) | |
2632 | { | |
2633 | switch (arm_mmu_idx(env)) { | |
2634 | case ARMMMUIdx_E20_0: | |
2635 | case ARMMMUIdx_E20_2: | |
452ef8cb | 2636 | case ARMMMUIdx_E20_2_PAN: |
b6ad6062 RDC |
2637 | case ARMMMUIdx_SE20_0: |
2638 | case ARMMMUIdx_SE20_2: | |
2639 | case ARMMMUIdx_SE20_2_PAN: | |
bb5972e4 RH |
2640 | return GTIMER_HYPVIRT; |
2641 | default: | |
2642 | return GTIMER_VIRT; | |
2643 | } | |
2644 | } | |
2645 | ||
2646 | static uint64_t gt_phys_redir_cval_read(CPUARMState *env, | |
2647 | const ARMCPRegInfo *ri) | |
2648 | { | |
2649 | int timeridx = gt_phys_redir_timeridx(env); | |
2650 | return env->cp15.c14_timer[timeridx].cval; | |
2651 | } | |
2652 | ||
2653 | static void gt_phys_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2654 | uint64_t value) | |
2655 | { | |
2656 | int timeridx = gt_phys_redir_timeridx(env); | |
2657 | gt_cval_write(env, ri, timeridx, value); | |
2658 | } | |
2659 | ||
2660 | static uint64_t gt_phys_redir_tval_read(CPUARMState *env, | |
2661 | const ARMCPRegInfo *ri) | |
2662 | { | |
2663 | int timeridx = gt_phys_redir_timeridx(env); | |
2664 | return gt_tval_read(env, ri, timeridx); | |
2665 | } | |
2666 | ||
2667 | static void gt_phys_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2668 | uint64_t value) | |
2669 | { | |
2670 | int timeridx = gt_phys_redir_timeridx(env); | |
2671 | gt_tval_write(env, ri, timeridx, value); | |
2672 | } | |
2673 | ||
2674 | static uint64_t gt_phys_redir_ctl_read(CPUARMState *env, | |
2675 | const ARMCPRegInfo *ri) | |
2676 | { | |
2677 | int timeridx = gt_phys_redir_timeridx(env); | |
2678 | return env->cp15.c14_timer[timeridx].ctl; | |
2679 | } | |
2680 | ||
2681 | static void gt_phys_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2682 | uint64_t value) | |
2683 | { | |
2684 | int timeridx = gt_phys_redir_timeridx(env); | |
2685 | gt_ctl_write(env, ri, timeridx, value); | |
2686 | } | |
2687 | ||
0e3eca4c EI |
2688 | static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2689 | { | |
2690 | gt_timer_reset(env, ri, GTIMER_VIRT); | |
2691 | } | |
2692 | ||
2693 | static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2694 | uint64_t value) | |
2695 | { | |
2696 | gt_cval_write(env, ri, GTIMER_VIRT, value); | |
2697 | } | |
2698 | ||
2699 | static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2700 | { | |
2701 | return gt_tval_read(env, ri, GTIMER_VIRT); | |
2702 | } | |
2703 | ||
2704 | static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2705 | uint64_t value) | |
2706 | { | |
2707 | gt_tval_write(env, ri, GTIMER_VIRT, value); | |
2708 | } | |
2709 | ||
2710 | static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2711 | uint64_t value) | |
2712 | { | |
2713 | gt_ctl_write(env, ri, GTIMER_VIRT, value); | |
2714 | } | |
2715 | ||
edac4d8a EI |
2716 | static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2717 | uint64_t value) | |
2718 | { | |
2fc0cc0e | 2719 | ARMCPU *cpu = env_archcpu(env); |
edac4d8a | 2720 | |
194cbc49 | 2721 | trace_arm_gt_cntvoff_write(value); |
edac4d8a EI |
2722 | raw_write(env, ri, value); |
2723 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
2724 | } | |
2725 | ||
bb5972e4 RH |
2726 | static uint64_t gt_virt_redir_cval_read(CPUARMState *env, |
2727 | const ARMCPRegInfo *ri) | |
2728 | { | |
2729 | int timeridx = gt_virt_redir_timeridx(env); | |
2730 | return env->cp15.c14_timer[timeridx].cval; | |
2731 | } | |
2732 | ||
2733 | static void gt_virt_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2734 | uint64_t value) | |
2735 | { | |
2736 | int timeridx = gt_virt_redir_timeridx(env); | |
2737 | gt_cval_write(env, ri, timeridx, value); | |
2738 | } | |
2739 | ||
2740 | static uint64_t gt_virt_redir_tval_read(CPUARMState *env, | |
2741 | const ARMCPRegInfo *ri) | |
2742 | { | |
2743 | int timeridx = gt_virt_redir_timeridx(env); | |
2744 | return gt_tval_read(env, ri, timeridx); | |
2745 | } | |
2746 | ||
2747 | static void gt_virt_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2748 | uint64_t value) | |
2749 | { | |
2750 | int timeridx = gt_virt_redir_timeridx(env); | |
2751 | gt_tval_write(env, ri, timeridx, value); | |
2752 | } | |
2753 | ||
2754 | static uint64_t gt_virt_redir_ctl_read(CPUARMState *env, | |
2755 | const ARMCPRegInfo *ri) | |
2756 | { | |
2757 | int timeridx = gt_virt_redir_timeridx(env); | |
2758 | return env->cp15.c14_timer[timeridx].ctl; | |
2759 | } | |
2760 | ||
2761 | static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2762 | uint64_t value) | |
2763 | { | |
2764 | int timeridx = gt_virt_redir_timeridx(env); | |
2765 | gt_ctl_write(env, ri, timeridx, value); | |
2766 | } | |
2767 | ||
b0e66d95 EI |
2768 | static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2769 | { | |
2770 | gt_timer_reset(env, ri, GTIMER_HYP); | |
2771 | } | |
2772 | ||
2773 | static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2774 | uint64_t value) | |
2775 | { | |
2776 | gt_cval_write(env, ri, GTIMER_HYP, value); | |
2777 | } | |
2778 | ||
2779 | static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2780 | { | |
2781 | return gt_tval_read(env, ri, GTIMER_HYP); | |
2782 | } | |
2783 | ||
2784 | static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2785 | uint64_t value) | |
2786 | { | |
2787 | gt_tval_write(env, ri, GTIMER_HYP, value); | |
2788 | } | |
2789 | ||
2790 | static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2791 | uint64_t value) | |
2792 | { | |
2793 | gt_ctl_write(env, ri, GTIMER_HYP, value); | |
2794 | } | |
2795 | ||
b4d3978c PM |
2796 | static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2797 | { | |
2798 | gt_timer_reset(env, ri, GTIMER_SEC); | |
2799 | } | |
2800 | ||
2801 | static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2802 | uint64_t value) | |
2803 | { | |
2804 | gt_cval_write(env, ri, GTIMER_SEC, value); | |
2805 | } | |
2806 | ||
2807 | static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2808 | { | |
2809 | return gt_tval_read(env, ri, GTIMER_SEC); | |
2810 | } | |
2811 | ||
2812 | static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2813 | uint64_t value) | |
2814 | { | |
2815 | gt_tval_write(env, ri, GTIMER_SEC, value); | |
2816 | } | |
2817 | ||
2818 | static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2819 | uint64_t value) | |
2820 | { | |
2821 | gt_ctl_write(env, ri, GTIMER_SEC, value); | |
2822 | } | |
2823 | ||
8c94b071 RH |
2824 | static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2825 | { | |
2826 | gt_timer_reset(env, ri, GTIMER_HYPVIRT); | |
2827 | } | |
2828 | ||
2829 | static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2830 | uint64_t value) | |
2831 | { | |
2832 | gt_cval_write(env, ri, GTIMER_HYPVIRT, value); | |
2833 | } | |
2834 | ||
2835 | static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2836 | { | |
2837 | return gt_tval_read(env, ri, GTIMER_HYPVIRT); | |
2838 | } | |
2839 | ||
2840 | static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2841 | uint64_t value) | |
2842 | { | |
2843 | gt_tval_write(env, ri, GTIMER_HYPVIRT, value); | |
2844 | } | |
2845 | ||
2846 | static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2847 | uint64_t value) | |
2848 | { | |
2849 | gt_ctl_write(env, ri, GTIMER_HYPVIRT, value); | |
2850 | } | |
2851 | ||
55d284af PM |
2852 | void arm_gt_ptimer_cb(void *opaque) |
2853 | { | |
2854 | ARMCPU *cpu = opaque; | |
2855 | ||
2856 | gt_recalc_timer(cpu, GTIMER_PHYS); | |
2857 | } | |
2858 | ||
2859 | void arm_gt_vtimer_cb(void *opaque) | |
2860 | { | |
2861 | ARMCPU *cpu = opaque; | |
2862 | ||
2863 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
2864 | } | |
2865 | ||
b0e66d95 EI |
2866 | void arm_gt_htimer_cb(void *opaque) |
2867 | { | |
2868 | ARMCPU *cpu = opaque; | |
2869 | ||
2870 | gt_recalc_timer(cpu, GTIMER_HYP); | |
2871 | } | |
2872 | ||
b4d3978c PM |
2873 | void arm_gt_stimer_cb(void *opaque) |
2874 | { | |
2875 | ARMCPU *cpu = opaque; | |
2876 | ||
2877 | gt_recalc_timer(cpu, GTIMER_SEC); | |
2878 | } | |
2879 | ||
8c94b071 RH |
2880 | void arm_gt_hvtimer_cb(void *opaque) |
2881 | { | |
2882 | ARMCPU *cpu = opaque; | |
2883 | ||
2884 | gt_recalc_timer(cpu, GTIMER_HYPVIRT); | |
2885 | } | |
2886 | ||
96eec6b2 AJ |
2887 | static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque) |
2888 | { | |
2889 | ARMCPU *cpu = env_archcpu(env); | |
2890 | ||
2891 | cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz; | |
2892 | } | |
2893 | ||
55d284af PM |
2894 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
2895 | /* Note that CNTFRQ is purely reads-as-written for the benefit | |
2896 | * of software; writing it doesn't actually change the timer frequency. | |
2897 | * Our reset value matches the fixed frequency we implement the timer at. | |
2898 | */ | |
2899 | { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 2900 | .type = ARM_CP_ALIAS, |
a7adc4b7 PM |
2901 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, |
2902 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), | |
a7adc4b7 PM |
2903 | }, |
2904 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, | |
2905 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
2906 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
55d284af | 2907 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), |
96eec6b2 | 2908 | .resetfn = arm_gt_cntfrq_reset, |
55d284af PM |
2909 | }, |
2910 | /* overall control: mostly access permissions */ | |
a7adc4b7 PM |
2911 | { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, |
2912 | .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, | |
55d284af PM |
2913 | .access = PL1_RW, |
2914 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), | |
2915 | .resetvalue = 0, | |
2916 | }, | |
2917 | /* per-timer control */ | |
2918 | { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
9ff9dd3c | 2919 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 2920 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
a7adc4b7 PM |
2921 | .accessfn = gt_ptimer_access, |
2922 | .fieldoffset = offsetoflow32(CPUARMState, | |
2923 | cp15.c14_timer[GTIMER_PHYS].ctl), | |
bb5972e4 RH |
2924 | .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read, |
2925 | .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write, | |
a7adc4b7 | 2926 | }, |
9c513e78 | 2927 | { .name = "CNTP_CTL_S", |
9ff9dd3c PM |
2928 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, |
2929 | .secure = ARM_CP_SECSTATE_S, | |
daf1dc5f | 2930 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
9ff9dd3c PM |
2931 | .accessfn = gt_ptimer_access, |
2932 | .fieldoffset = offsetoflow32(CPUARMState, | |
2933 | cp15.c14_timer[GTIMER_SEC].ctl), | |
2934 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
2935 | }, | |
a7adc4b7 PM |
2936 | { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, |
2937 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, | |
daf1dc5f | 2938 | .type = ARM_CP_IO, .access = PL0_RW, |
a7adc4b7 | 2939 | .accessfn = gt_ptimer_access, |
55d284af PM |
2940 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), |
2941 | .resetvalue = 0, | |
bb5972e4 RH |
2942 | .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read, |
2943 | .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write, | |
55d284af PM |
2944 | }, |
2945 | { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, | |
daf1dc5f | 2946 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
a7adc4b7 PM |
2947 | .accessfn = gt_vtimer_access, |
2948 | .fieldoffset = offsetoflow32(CPUARMState, | |
2949 | cp15.c14_timer[GTIMER_VIRT].ctl), | |
bb5972e4 RH |
2950 | .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read, |
2951 | .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write, | |
a7adc4b7 PM |
2952 | }, |
2953 | { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
2954 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, | |
daf1dc5f | 2955 | .type = ARM_CP_IO, .access = PL0_RW, |
a7adc4b7 | 2956 | .accessfn = gt_vtimer_access, |
55d284af PM |
2957 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), |
2958 | .resetvalue = 0, | |
bb5972e4 RH |
2959 | .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read, |
2960 | .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write, | |
55d284af PM |
2961 | }, |
2962 | /* TimerValue views: a 32 bit downcounting view of the underlying state */ | |
2963 | { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
9ff9dd3c | 2964 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 2965 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
00108f2d | 2966 | .accessfn = gt_ptimer_access, |
bb5972e4 | 2967 | .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write, |
55d284af | 2968 | }, |
9c513e78 | 2969 | { .name = "CNTP_TVAL_S", |
9ff9dd3c PM |
2970 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, |
2971 | .secure = ARM_CP_SECSTATE_S, | |
daf1dc5f | 2972 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
9ff9dd3c PM |
2973 | .accessfn = gt_ptimer_access, |
2974 | .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, | |
2975 | }, | |
a7adc4b7 PM |
2976 | { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
2977 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, | |
daf1dc5f | 2978 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
0e3eca4c | 2979 | .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, |
bb5972e4 | 2980 | .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write, |
a7adc4b7 | 2981 | }, |
55d284af | 2982 | { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, |
daf1dc5f | 2983 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
00108f2d | 2984 | .accessfn = gt_vtimer_access, |
bb5972e4 | 2985 | .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write, |
55d284af | 2986 | }, |
a7adc4b7 PM |
2987 | { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
2988 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, | |
daf1dc5f | 2989 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
0e3eca4c | 2990 | .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, |
bb5972e4 | 2991 | .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write, |
a7adc4b7 | 2992 | }, |
55d284af PM |
2993 | /* The counter itself */ |
2994 | { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, | |
7a0e58fa | 2995 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 2996 | .accessfn = gt_pct_access, |
a7adc4b7 PM |
2997 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
2998 | }, | |
2999 | { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, | |
3000 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, | |
7a0e58fa | 3001 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 3002 | .accessfn = gt_pct_access, .readfn = gt_cnt_read, |
55d284af PM |
3003 | }, |
3004 | { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, | |
7a0e58fa | 3005 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 3006 | .accessfn = gt_vct_access, |
edac4d8a | 3007 | .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, |
a7adc4b7 PM |
3008 | }, |
3009 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
3010 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
7a0e58fa | 3011 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 3012 | .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, |
55d284af PM |
3013 | }, |
3014 | /* Comparison value, indicating when the timer goes off */ | |
3015 | { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, | |
9ff9dd3c | 3016 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 3017 | .access = PL0_RW, |
7a0e58fa | 3018 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 3019 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), |
b061a82b | 3020 | .accessfn = gt_ptimer_access, |
bb5972e4 RH |
3021 | .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read, |
3022 | .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write, | |
a7adc4b7 | 3023 | }, |
9c513e78 | 3024 | { .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2, |
9ff9dd3c | 3025 | .secure = ARM_CP_SECSTATE_S, |
daf1dc5f | 3026 | .access = PL0_RW, |
9ff9dd3c PM |
3027 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
3028 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
3029 | .accessfn = gt_ptimer_access, | |
3030 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
3031 | }, | |
a7adc4b7 PM |
3032 | { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, |
3033 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, | |
daf1dc5f | 3034 | .access = PL0_RW, |
a7adc4b7 PM |
3035 | .type = ARM_CP_IO, |
3036 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
12cde08a | 3037 | .resetvalue = 0, .accessfn = gt_ptimer_access, |
bb5972e4 RH |
3038 | .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read, |
3039 | .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write, | |
55d284af PM |
3040 | }, |
3041 | { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, | |
daf1dc5f | 3042 | .access = PL0_RW, |
7a0e58fa | 3043 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 3044 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), |
b061a82b | 3045 | .accessfn = gt_vtimer_access, |
bb5972e4 RH |
3046 | .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read, |
3047 | .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write, | |
a7adc4b7 PM |
3048 | }, |
3049 | { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
3050 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, | |
daf1dc5f | 3051 | .access = PL0_RW, |
a7adc4b7 PM |
3052 | .type = ARM_CP_IO, |
3053 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
3054 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
bb5972e4 RH |
3055 | .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read, |
3056 | .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write, | |
55d284af | 3057 | }, |
b4d3978c PM |
3058 | /* Secure timer -- this is actually restricted to only EL3 |
3059 | * and configurably Secure-EL1 via the accessfn. | |
3060 | */ | |
3061 | { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, | |
3062 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, | |
3063 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, | |
3064 | .accessfn = gt_stimer_access, | |
3065 | .readfn = gt_sec_tval_read, | |
3066 | .writefn = gt_sec_tval_write, | |
3067 | .resetfn = gt_sec_timer_reset, | |
3068 | }, | |
3069 | { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64, | |
3070 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1, | |
3071 | .type = ARM_CP_IO, .access = PL1_RW, | |
3072 | .accessfn = gt_stimer_access, | |
3073 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), | |
3074 | .resetvalue = 0, | |
3075 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
3076 | }, | |
3077 | { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, | |
3078 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, | |
3079 | .type = ARM_CP_IO, .access = PL1_RW, | |
3080 | .accessfn = gt_stimer_access, | |
3081 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
3082 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
3083 | }, | |
55d284af PM |
3084 | }; |
3085 | ||
bb5972e4 RH |
3086 | static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3087 | bool isread) | |
3088 | { | |
3089 | if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { | |
3090 | return CP_ACCESS_TRAP; | |
3091 | } | |
3092 | return CP_ACCESS_OK; | |
3093 | } | |
3094 | ||
55d284af | 3095 | #else |
26c4a83b AB |
3096 | |
3097 | /* In user-mode most of the generic timer registers are inaccessible | |
3098 | * however modern kernels (4.12+) allow access to cntvct_el0 | |
55d284af | 3099 | */ |
26c4a83b AB |
3100 | |
3101 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3102 | { | |
7def8754 AJ |
3103 | ARMCPU *cpu = env_archcpu(env); |
3104 | ||
26c4a83b AB |
3105 | /* Currently we have no support for QEMUTimer in linux-user so we |
3106 | * can't call gt_get_countervalue(env), instead we directly | |
3107 | * call the lower level functions. | |
3108 | */ | |
7def8754 | 3109 | return cpu_get_clock() / gt_cntfrq_period_ns(cpu); |
26c4a83b AB |
3110 | } |
3111 | ||
6cc7a3ae | 3112 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
26c4a83b AB |
3113 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, |
3114 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
3115 | .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */, | |
3116 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), | |
3117 | .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE, | |
3118 | }, | |
3119 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
3120 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
3121 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
3122 | .readfn = gt_virt_cnt_read, | |
3123 | }, | |
6cc7a3ae PM |
3124 | }; |
3125 | ||
55d284af PM |
3126 | #endif |
3127 | ||
c4241c7d | 3128 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 3129 | { |
891a2fe7 | 3130 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8d5c773e | 3131 | raw_write(env, ri, value); |
891a2fe7 | 3132 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8d5c773e | 3133 | raw_write(env, ri, value & 0xfffff6ff); |
4a501606 | 3134 | } else { |
8d5c773e | 3135 | raw_write(env, ri, value & 0xfffff1ff); |
4a501606 | 3136 | } |
4a501606 PM |
3137 | } |
3138 | ||
3139 | #ifndef CONFIG_USER_ONLY | |
3140 | /* get_phys_addr() isn't present for user-mode-only targets */ | |
702a9357 | 3141 | |
3f208fd7 PM |
3142 | static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3143 | bool isread) | |
92611c00 PM |
3144 | { |
3145 | if (ri->opc2 & 4) { | |
926c1b97 | 3146 | /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in |
87562e4f PM |
3147 | * Secure EL1 (which can only happen if EL3 is AArch64). |
3148 | * They are simply UNDEF if executed from NS EL1. | |
3149 | * They function normally from EL2 or EL3. | |
92611c00 | 3150 | */ |
87562e4f PM |
3151 | if (arm_current_el(env) == 1) { |
3152 | if (arm_is_secure_below_el3(env)) { | |
926c1b97 RDC |
3153 | if (env->cp15.scr_el3 & SCR_EEL2) { |
3154 | return CP_ACCESS_TRAP_UNCATEGORIZED_EL2; | |
3155 | } | |
87562e4f PM |
3156 | return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; |
3157 | } | |
3158 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
3159 | } | |
92611c00 PM |
3160 | } |
3161 | return CP_ACCESS_OK; | |
3162 | } | |
3163 | ||
9fb005b0 | 3164 | #ifdef CONFIG_TCG |
060e8a48 | 3165 | static uint64_t do_ats_write(CPUARMState *env, uint64_t value, |
03ae85f8 | 3166 | MMUAccessType access_type, ARMMMUIdx mmu_idx) |
4a501606 | 3167 | { |
a8170e5e | 3168 | hwaddr phys_addr; |
4a501606 PM |
3169 | target_ulong page_size; |
3170 | int prot; | |
b7cc4e82 | 3171 | bool ret; |
01c097f7 | 3172 | uint64_t par64; |
1313e2d7 | 3173 | bool format64 = false; |
8bf5b6a9 | 3174 | MemTxAttrs attrs = {}; |
e14b5a23 | 3175 | ARMMMUFaultInfo fi = {}; |
5b2d261d | 3176 | ARMCacheAttrs cacheattrs = {}; |
4a501606 | 3177 | |
5b2d261d | 3178 | ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, |
bc52bfeb | 3179 | &prot, &page_size, &fi, &cacheattrs); |
1313e2d7 | 3180 | |
0710b2fa PM |
3181 | if (ret) { |
3182 | /* | |
3183 | * Some kinds of translation fault must cause exceptions rather | |
3184 | * than being reported in the PAR. | |
3185 | */ | |
3186 | int current_el = arm_current_el(env); | |
3187 | int target_el; | |
3188 | uint32_t syn, fsr, fsc; | |
3189 | bool take_exc = false; | |
3190 | ||
b1a10c86 | 3191 | if (fi.s1ptw && current_el == 1 |
fee7aa46 | 3192 | && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { |
0710b2fa PM |
3193 | /* |
3194 | * Synchronous stage 2 fault on an access made as part of the | |
3195 | * translation table walk for AT S1E0* or AT S1E1* insn | |
3196 | * executed from NS EL1. If this is a synchronous external abort | |
3197 | * and SCR_EL3.EA == 1, then we take a synchronous external abort | |
3198 | * to EL3. Otherwise the fault is taken as an exception to EL2, | |
3199 | * and HPFAR_EL2 holds the faulting IPA. | |
3200 | */ | |
3201 | if (fi.type == ARMFault_SyncExternalOnWalk && | |
3202 | (env->cp15.scr_el3 & SCR_EA)) { | |
3203 | target_el = 3; | |
3204 | } else { | |
3205 | env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; | |
9861248f RDC |
3206 | if (arm_is_secure_below_el3(env) && fi.s1ns) { |
3207 | env->cp15.hpfar_el2 |= HPFAR_NS; | |
3208 | } | |
0710b2fa PM |
3209 | target_el = 2; |
3210 | } | |
3211 | take_exc = true; | |
3212 | } else if (fi.type == ARMFault_SyncExternalOnWalk) { | |
3213 | /* | |
3214 | * Synchronous external aborts during a translation table walk | |
3215 | * are taken as Data Abort exceptions. | |
3216 | */ | |
3217 | if (fi.stage2) { | |
3218 | if (current_el == 3) { | |
3219 | target_el = 3; | |
3220 | } else { | |
3221 | target_el = 2; | |
3222 | } | |
3223 | } else { | |
3224 | target_el = exception_target_el(env); | |
3225 | } | |
3226 | take_exc = true; | |
3227 | } | |
3228 | ||
3229 | if (take_exc) { | |
3230 | /* Construct FSR and FSC using same logic as arm_deliver_fault() */ | |
3231 | if (target_el == 2 || arm_el_is_aa64(env, target_el) || | |
3232 | arm_s1_regime_using_lpae_format(env, mmu_idx)) { | |
3233 | fsr = arm_fi_to_lfsc(&fi); | |
3234 | fsc = extract32(fsr, 0, 6); | |
3235 | } else { | |
3236 | fsr = arm_fi_to_sfsc(&fi); | |
3237 | fsc = 0x3f; | |
3238 | } | |
3239 | /* | |
3240 | * Report exception with ESR indicating a fault due to a | |
3241 | * translation table walk for a cache maintenance instruction. | |
3242 | */ | |
e24fd076 | 3243 | syn = syn_data_abort_no_iss(current_el == target_el, 0, |
0710b2fa PM |
3244 | fi.ea, 1, fi.s1ptw, 1, fsc); |
3245 | env->exception.vaddress = value; | |
3246 | env->exception.fsr = fsr; | |
3247 | raise_exception(env, EXCP_DATA_ABORT, syn, target_el); | |
3248 | } | |
3249 | } | |
3250 | ||
1313e2d7 EI |
3251 | if (is_a64(env)) { |
3252 | format64 = true; | |
3253 | } else if (arm_feature(env, ARM_FEATURE_LPAE)) { | |
3254 | /* | |
3255 | * ATS1Cxx: | |
3256 | * * TTBCR.EAE determines whether the result is returned using the | |
3257 | * 32-bit or the 64-bit PAR format | |
3258 | * * Instructions executed in Hyp mode always use the 64bit format | |
3259 | * | |
3260 | * ATS1S2NSOxx uses the 64bit format if any of the following is true: | |
3261 | * * The Non-secure TTBCR.EAE bit is set to 1 | |
3262 | * * The implementation includes EL2, and the value of HCR.VM is 1 | |
3263 | * | |
9d1bab33 PM |
3264 | * (Note that HCR.DC makes HCR.VM behave as if it is 1.) |
3265 | * | |
23463e0e | 3266 | * ATS1Hx always uses the 64bit format. |
1313e2d7 EI |
3267 | */ |
3268 | format64 = arm_s1_regime_using_lpae_format(env, mmu_idx); | |
3269 | ||
3270 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
452ef8cb RH |
3271 | if (mmu_idx == ARMMMUIdx_E10_0 || |
3272 | mmu_idx == ARMMMUIdx_E10_1 || | |
3273 | mmu_idx == ARMMMUIdx_E10_1_PAN) { | |
9d1bab33 | 3274 | format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC); |
1313e2d7 EI |
3275 | } else { |
3276 | format64 |= arm_current_el(env) == 2; | |
3277 | } | |
3278 | } | |
3279 | } | |
3280 | ||
3281 | if (format64) { | |
5efe9ed4 | 3282 | /* Create a 64-bit PAR */ |
01c097f7 | 3283 | par64 = (1 << 11); /* LPAE bit always set */ |
b7cc4e82 | 3284 | if (!ret) { |
702a9357 | 3285 | par64 |= phys_addr & ~0xfffULL; |
8bf5b6a9 PM |
3286 | if (!attrs.secure) { |
3287 | par64 |= (1 << 9); /* NS */ | |
3288 | } | |
5b2d261d AB |
3289 | par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */ |
3290 | par64 |= cacheattrs.shareability << 7; /* SH */ | |
4a501606 | 3291 | } else { |
5efe9ed4 PM |
3292 | uint32_t fsr = arm_fi_to_lfsc(&fi); |
3293 | ||
702a9357 | 3294 | par64 |= 1; /* F */ |
b7cc4e82 | 3295 | par64 |= (fsr & 0x3f) << 1; /* FS */ |
0f7b791b PM |
3296 | if (fi.stage2) { |
3297 | par64 |= (1 << 9); /* S */ | |
3298 | } | |
3299 | if (fi.s1ptw) { | |
3300 | par64 |= (1 << 8); /* PTW */ | |
3301 | } | |
4a501606 PM |
3302 | } |
3303 | } else { | |
b7cc4e82 | 3304 | /* fsr is a DFSR/IFSR value for the short descriptor |
702a9357 PM |
3305 | * translation table format (with WnR always clear). |
3306 | * Convert it to a 32-bit PAR. | |
3307 | */ | |
b7cc4e82 | 3308 | if (!ret) { |
702a9357 PM |
3309 | /* We do not set any attribute bits in the PAR */ |
3310 | if (page_size == (1 << 24) | |
3311 | && arm_feature(env, ARM_FEATURE_V7)) { | |
01c097f7 | 3312 | par64 = (phys_addr & 0xff000000) | (1 << 1); |
702a9357 | 3313 | } else { |
01c097f7 | 3314 | par64 = phys_addr & 0xfffff000; |
702a9357 | 3315 | } |
8bf5b6a9 PM |
3316 | if (!attrs.secure) { |
3317 | par64 |= (1 << 9); /* NS */ | |
3318 | } | |
702a9357 | 3319 | } else { |
5efe9ed4 PM |
3320 | uint32_t fsr = arm_fi_to_sfsc(&fi); |
3321 | ||
b7cc4e82 PC |
3322 | par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | |
3323 | ((fsr & 0xf) << 1) | 1; | |
702a9357 | 3324 | } |
4a501606 | 3325 | } |
060e8a48 PM |
3326 | return par64; |
3327 | } | |
9fb005b0 | 3328 | #endif /* CONFIG_TCG */ |
060e8a48 PM |
3329 | |
3330 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | |
3331 | { | |
9fb005b0 | 3332 | #ifdef CONFIG_TCG |
03ae85f8 | 3333 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
060e8a48 | 3334 | uint64_t par64; |
d3649702 PM |
3335 | ARMMMUIdx mmu_idx; |
3336 | int el = arm_current_el(env); | |
3337 | bool secure = arm_is_secure_below_el3(env); | |
060e8a48 | 3338 | |
d3649702 PM |
3339 | switch (ri->opc2 & 6) { |
3340 | case 0: | |
04b07d29 | 3341 | /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */ |
d3649702 PM |
3342 | switch (el) { |
3343 | case 3: | |
127b2b08 | 3344 | mmu_idx = ARMMMUIdx_SE3; |
d3649702 PM |
3345 | break; |
3346 | case 2: | |
b6ad6062 | 3347 | g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ |
04b07d29 | 3348 | /* fall through */ |
d3649702 | 3349 | case 1: |
04b07d29 | 3350 | if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) { |
b1a10c86 | 3351 | mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN |
04b07d29 RH |
3352 | : ARMMMUIdx_Stage1_E1_PAN); |
3353 | } else { | |
b1a10c86 | 3354 | mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1; |
04b07d29 | 3355 | } |
d3649702 PM |
3356 | break; |
3357 | default: | |
3358 | g_assert_not_reached(); | |
3359 | } | |
3360 | break; | |
3361 | case 2: | |
3362 | /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ | |
3363 | switch (el) { | |
3364 | case 3: | |
fba37aed | 3365 | mmu_idx = ARMMMUIdx_SE10_0; |
d3649702 PM |
3366 | break; |
3367 | case 2: | |
b1a10c86 | 3368 | g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ |
2859d7b5 | 3369 | mmu_idx = ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3370 | break; |
3371 | case 1: | |
b1a10c86 | 3372 | mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3373 | break; |
3374 | default: | |
3375 | g_assert_not_reached(); | |
3376 | } | |
3377 | break; | |
3378 | case 4: | |
3379 | /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ | |
01b98b68 | 3380 | mmu_idx = ARMMMUIdx_E10_1; |
d3649702 PM |
3381 | break; |
3382 | case 6: | |
3383 | /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ | |
01b98b68 | 3384 | mmu_idx = ARMMMUIdx_E10_0; |
d3649702 PM |
3385 | break; |
3386 | default: | |
3387 | g_assert_not_reached(); | |
3388 | } | |
3389 | ||
3390 | par64 = do_ats_write(env, value, access_type, mmu_idx); | |
01c097f7 FA |
3391 | |
3392 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
9fb005b0 PMD |
3393 | #else |
3394 | /* Handled by hardware accelerator. */ | |
3395 | g_assert_not_reached(); | |
3396 | #endif /* CONFIG_TCG */ | |
4a501606 | 3397 | } |
060e8a48 | 3398 | |
14db7fe0 PM |
3399 | static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3400 | uint64_t value) | |
3401 | { | |
9fb005b0 | 3402 | #ifdef CONFIG_TCG |
03ae85f8 | 3403 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
14db7fe0 PM |
3404 | uint64_t par64; |
3405 | ||
e013b741 | 3406 | par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2); |
14db7fe0 PM |
3407 | |
3408 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
9fb005b0 PMD |
3409 | #else |
3410 | /* Handled by hardware accelerator. */ | |
3411 | g_assert_not_reached(); | |
3412 | #endif /* CONFIG_TCG */ | |
14db7fe0 PM |
3413 | } |
3414 | ||
3f208fd7 PM |
3415 | static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3416 | bool isread) | |
2a47df95 | 3417 | { |
926c1b97 RDC |
3418 | if (arm_current_el(env) == 3 && |
3419 | !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) { | |
2a47df95 PM |
3420 | return CP_ACCESS_TRAP; |
3421 | } | |
3422 | return CP_ACCESS_OK; | |
3423 | } | |
3424 | ||
060e8a48 PM |
3425 | static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, |
3426 | uint64_t value) | |
3427 | { | |
9fb005b0 | 3428 | #ifdef CONFIG_TCG |
03ae85f8 | 3429 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
d3649702 PM |
3430 | ARMMMUIdx mmu_idx; |
3431 | int secure = arm_is_secure_below_el3(env); | |
3432 | ||
3433 | switch (ri->opc2 & 6) { | |
3434 | case 0: | |
3435 | switch (ri->opc1) { | |
04b07d29 RH |
3436 | case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ |
3437 | if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) { | |
b1a10c86 | 3438 | mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN |
04b07d29 RH |
3439 | : ARMMMUIdx_Stage1_E1_PAN); |
3440 | } else { | |
b1a10c86 | 3441 | mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1; |
04b07d29 | 3442 | } |
d3649702 PM |
3443 | break; |
3444 | case 4: /* AT S1E2R, AT S1E2W */ | |
b6ad6062 | 3445 | mmu_idx = secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2; |
d3649702 PM |
3446 | break; |
3447 | case 6: /* AT S1E3R, AT S1E3W */ | |
127b2b08 | 3448 | mmu_idx = ARMMMUIdx_SE3; |
d3649702 PM |
3449 | break; |
3450 | default: | |
3451 | g_assert_not_reached(); | |
3452 | } | |
3453 | break; | |
3454 | case 2: /* AT S1E0R, AT S1E0W */ | |
b1a10c86 | 3455 | mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3456 | break; |
3457 | case 4: /* AT S12E1R, AT S12E1W */ | |
fba37aed | 3458 | mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1; |
d3649702 PM |
3459 | break; |
3460 | case 6: /* AT S12E0R, AT S12E0W */ | |
fba37aed | 3461 | mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0; |
d3649702 PM |
3462 | break; |
3463 | default: | |
3464 | g_assert_not_reached(); | |
3465 | } | |
060e8a48 | 3466 | |
d3649702 | 3467 | env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); |
9fb005b0 PMD |
3468 | #else |
3469 | /* Handled by hardware accelerator. */ | |
3470 | g_assert_not_reached(); | |
3471 | #endif /* CONFIG_TCG */ | |
060e8a48 | 3472 | } |
4a501606 PM |
3473 | #endif |
3474 | ||
3475 | static const ARMCPRegInfo vapa_cp_reginfo[] = { | |
3476 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, | |
3477 | .access = PL1_RW, .resetvalue = 0, | |
01c097f7 FA |
3478 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), |
3479 | offsetoflow32(CPUARMState, cp15.par_ns) }, | |
4a501606 PM |
3480 | .writefn = par_write }, |
3481 | #ifndef CONFIG_USER_ONLY | |
87562e4f | 3482 | /* This underdecoding is safe because the reginfo is NO_RAW. */ |
4a501606 | 3483 | { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, |
92611c00 | 3484 | .access = PL1_W, .accessfn = ats_access, |
0710b2fa | 3485 | .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
4a501606 | 3486 | #endif |
4a501606 PM |
3487 | }; |
3488 | ||
18032bec PM |
3489 | /* Return basic MPU access permission bits. */ |
3490 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
3491 | { | |
3492 | uint32_t ret; | |
3493 | uint32_t mask; | |
3494 | int i; | |
3495 | ret = 0; | |
3496 | mask = 3; | |
3497 | for (i = 0; i < 16; i += 2) { | |
3498 | ret |= (val >> i) & mask; | |
3499 | mask <<= 2; | |
3500 | } | |
3501 | return ret; | |
3502 | } | |
3503 | ||
3504 | /* Pad basic MPU access permission bits to extended format. */ | |
3505 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
3506 | { | |
3507 | uint32_t ret; | |
3508 | uint32_t mask; | |
3509 | int i; | |
3510 | ret = 0; | |
3511 | mask = 3; | |
3512 | for (i = 0; i < 16; i += 2) { | |
3513 | ret |= (val & mask) << i; | |
3514 | mask <<= 2; | |
3515 | } | |
3516 | return ret; | |
3517 | } | |
3518 | ||
c4241c7d PM |
3519 | static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3520 | uint64_t value) | |
18032bec | 3521 | { |
7e09797c | 3522 | env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3523 | } |
3524 | ||
c4241c7d | 3525 | static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3526 | { |
7e09797c | 3527 | return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); |
18032bec PM |
3528 | } |
3529 | ||
c4241c7d PM |
3530 | static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3531 | uint64_t value) | |
18032bec | 3532 | { |
7e09797c | 3533 | env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3534 | } |
3535 | ||
c4241c7d | 3536 | static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3537 | { |
7e09797c | 3538 | return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); |
18032bec PM |
3539 | } |
3540 | ||
6cb0b013 PC |
3541 | static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) |
3542 | { | |
3543 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); | |
3544 | ||
3545 | if (!u32p) { | |
3546 | return 0; | |
3547 | } | |
3548 | ||
1bc04a88 | 3549 | u32p += env->pmsav7.rnr[M_REG_NS]; |
6cb0b013 PC |
3550 | return *u32p; |
3551 | } | |
3552 | ||
3553 | static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3554 | uint64_t value) | |
3555 | { | |
2fc0cc0e | 3556 | ARMCPU *cpu = env_archcpu(env); |
6cb0b013 PC |
3557 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); |
3558 | ||
3559 | if (!u32p) { | |
3560 | return; | |
3561 | } | |
3562 | ||
1bc04a88 | 3563 | u32p += env->pmsav7.rnr[M_REG_NS]; |
d10eb08f | 3564 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ |
6cb0b013 PC |
3565 | *u32p = value; |
3566 | } | |
3567 | ||
6cb0b013 PC |
3568 | static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3569 | uint64_t value) | |
3570 | { | |
2fc0cc0e | 3571 | ARMCPU *cpu = env_archcpu(env); |
6cb0b013 PC |
3572 | uint32_t nrgs = cpu->pmsav7_dregion; |
3573 | ||
3574 | if (value >= nrgs) { | |
3575 | qemu_log_mask(LOG_GUEST_ERROR, | |
3576 | "PMSAv7 RGNR write >= # supported regions, %" PRIu32 | |
3577 | " > %" PRIu32 "\n", (uint32_t)value, nrgs); | |
3578 | return; | |
3579 | } | |
3580 | ||
3581 | raw_write(env, ri, value); | |
3582 | } | |
3583 | ||
3584 | static const ARMCPRegInfo pmsav7_cp_reginfo[] = { | |
69ceea64 PM |
3585 | /* Reset for all these registers is handled in arm_cpu_reset(), |
3586 | * because the PMSAv7 is also used by M-profile CPUs, which do | |
3587 | * not register cpregs but still need the state to be reset. | |
3588 | */ | |
6cb0b013 PC |
3589 | { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, |
3590 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3591 | .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), | |
69ceea64 PM |
3592 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3593 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3594 | { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, |
3595 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3596 | .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), | |
69ceea64 PM |
3597 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3598 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3599 | { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, |
3600 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3601 | .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), | |
69ceea64 PM |
3602 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3603 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3604 | { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, |
3605 | .access = PL1_RW, | |
1bc04a88 | 3606 | .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), |
69ceea64 PM |
3607 | .writefn = pmsav7_rgnr_write, |
3608 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3609 | }; |
3610 | ||
18032bec PM |
3611 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { |
3612 | { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 3613 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 3614 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
18032bec PM |
3615 | .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, |
3616 | { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 3617 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 3618 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
18032bec PM |
3619 | .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, |
3620 | { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, | |
3621 | .access = PL1_RW, | |
7e09797c PM |
3622 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
3623 | .resetvalue = 0, }, | |
18032bec PM |
3624 | { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, |
3625 | .access = PL1_RW, | |
7e09797c PM |
3626 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
3627 | .resetvalue = 0, }, | |
ecce5c3c PM |
3628 | { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
3629 | .access = PL1_RW, | |
3630 | .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, | |
3631 | { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
3632 | .access = PL1_RW, | |
3633 | .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, | |
06d76f31 | 3634 | /* Protection region base and size registers */ |
e508a92b PM |
3635 | { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, |
3636 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3637 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, | |
3638 | { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, | |
3639 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3640 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, | |
3641 | { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, | |
3642 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3643 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, | |
3644 | { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, | |
3645 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3646 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, | |
3647 | { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, | |
3648 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3649 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, | |
3650 | { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, | |
3651 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3652 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, | |
3653 | { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, | |
3654 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3655 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, | |
3656 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | |
3657 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3658 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | |
18032bec PM |
3659 | }; |
3660 | ||
c4241c7d PM |
3661 | static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3662 | uint64_t value) | |
ecce5c3c | 3663 | { |
11f136ee | 3664 | TCR *tcr = raw_ptr(env, ri); |
2ebcebe2 PM |
3665 | int maskshift = extract32(value, 0, 3); |
3666 | ||
e389be16 FA |
3667 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
3668 | if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { | |
3669 | /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when | |
3670 | * using Long-desciptor translation table format */ | |
3671 | value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); | |
3672 | } else if (arm_feature(env, ARM_FEATURE_EL3)) { | |
3673 | /* In an implementation that includes the Security Extensions | |
3674 | * TTBCR has additional fields PD0 [4] and PD1 [5] for | |
3675 | * Short-descriptor translation table format. | |
3676 | */ | |
3677 | value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; | |
3678 | } else { | |
3679 | value &= TTBCR_N; | |
3680 | } | |
e42c4db3 | 3681 | } |
e389be16 | 3682 | |
b6af0975 | 3683 | /* Update the masks corresponding to the TCR bank being written |
11f136ee | 3684 | * Note that we always calculate mask and base_mask, but |
e42c4db3 | 3685 | * they are only used for short-descriptor tables (ie if EAE is 0); |
11f136ee FA |
3686 | * for long-descriptor tables the TCR fields are used differently |
3687 | * and the mask and base_mask values are meaningless. | |
e42c4db3 | 3688 | */ |
11f136ee FA |
3689 | tcr->raw_tcr = value; |
3690 | tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift); | |
3691 | tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift); | |
ecce5c3c PM |
3692 | } |
3693 | ||
c4241c7d PM |
3694 | static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3695 | uint64_t value) | |
d4e6df63 | 3696 | { |
2fc0cc0e | 3697 | ARMCPU *cpu = env_archcpu(env); |
ab638a32 | 3698 | TCR *tcr = raw_ptr(env, ri); |
00c8cb0a | 3699 | |
d4e6df63 PM |
3700 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
3701 | /* With LPAE the TTBCR could result in a change of ASID | |
3702 | * via the TTBCR.A1 bit, so do a TLB flush. | |
3703 | */ | |
d10eb08f | 3704 | tlb_flush(CPU(cpu)); |
d4e6df63 | 3705 | } |
ab638a32 RH |
3706 | /* Preserve the high half of TCR_EL1, set via TTBCR2. */ |
3707 | value = deposit64(tcr->raw_tcr, 0, 32, value); | |
c4241c7d | 3708 | vmsa_ttbcr_raw_write(env, ri, value); |
d4e6df63 PM |
3709 | } |
3710 | ||
ecce5c3c PM |
3711 | static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
3712 | { | |
11f136ee FA |
3713 | TCR *tcr = raw_ptr(env, ri); |
3714 | ||
3715 | /* Reset both the TCR as well as the masks corresponding to the bank of | |
3716 | * the TCR being reset. | |
3717 | */ | |
3718 | tcr->raw_tcr = 0; | |
3719 | tcr->mask = 0; | |
3720 | tcr->base_mask = 0xffffc000u; | |
ecce5c3c PM |
3721 | } |
3722 | ||
d06dc933 | 3723 | static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, |
cb2e37df PM |
3724 | uint64_t value) |
3725 | { | |
2fc0cc0e | 3726 | ARMCPU *cpu = env_archcpu(env); |
11f136ee | 3727 | TCR *tcr = raw_ptr(env, ri); |
00c8cb0a | 3728 | |
cb2e37df | 3729 | /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ |
d10eb08f | 3730 | tlb_flush(CPU(cpu)); |
11f136ee | 3731 | tcr->raw_tcr = value; |
cb2e37df PM |
3732 | } |
3733 | ||
327ed10f PM |
3734 | static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3735 | uint64_t value) | |
3736 | { | |
93f379b0 RH |
3737 | /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ |
3738 | if (cpreg_field_is_64bit(ri) && | |
3739 | extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { | |
2fc0cc0e | 3740 | ARMCPU *cpu = env_archcpu(env); |
d10eb08f | 3741 | tlb_flush(CPU(cpu)); |
327ed10f PM |
3742 | } |
3743 | raw_write(env, ri, value); | |
3744 | } | |
3745 | ||
ed30da8e RH |
3746 | static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3747 | uint64_t value) | |
3748 | { | |
d06dc933 RH |
3749 | /* |
3750 | * If we are running with E2&0 regime, then an ASID is active. | |
3751 | * Flush if that might be changing. Note we're not checking | |
3752 | * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that | |
3753 | * holds the active ASID, only checking the field that might. | |
3754 | */ | |
3755 | if (extract64(raw_read(env, ri) ^ value, 48, 16) && | |
3756 | (arm_hcr_el2_eff(env) & HCR_E2H)) { | |
b6ad6062 RDC |
3757 | uint16_t mask = ARMMMUIdxBit_E20_2 | |
3758 | ARMMMUIdxBit_E20_2_PAN | | |
3759 | ARMMMUIdxBit_E20_0; | |
3760 | ||
3761 | if (arm_is_secure_below_el3(env)) { | |
3762 | mask >>= ARM_MMU_IDX_A_NS; | |
3763 | } | |
3764 | ||
3765 | tlb_flush_by_mmuidx(env_cpu(env), mask); | |
d06dc933 | 3766 | } |
ed30da8e RH |
3767 | raw_write(env, ri, value); |
3768 | } | |
3769 | ||
b698e9cf EI |
3770 | static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3771 | uint64_t value) | |
3772 | { | |
2fc0cc0e | 3773 | ARMCPU *cpu = env_archcpu(env); |
b698e9cf EI |
3774 | CPUState *cs = CPU(cpu); |
3775 | ||
97fa9350 RH |
3776 | /* |
3777 | * A change in VMID to the stage2 page table (Stage2) invalidates | |
3778 | * the combined stage 1&2 tlbs (EL10_1 and EL10_0). | |
3779 | */ | |
b698e9cf | 3780 | if (raw_read(env, ri) != value) { |
c4f060e8 RDC |
3781 | uint16_t mask = ARMMMUIdxBit_E10_1 | |
3782 | ARMMMUIdxBit_E10_1_PAN | | |
3783 | ARMMMUIdxBit_E10_0; | |
3784 | ||
3785 | if (arm_is_secure_below_el3(env)) { | |
3786 | mask >>= ARM_MMU_IDX_A_NS; | |
3787 | } | |
3788 | ||
3789 | tlb_flush_by_mmuidx(cs, mask); | |
b698e9cf EI |
3790 | raw_write(env, ri, value); |
3791 | } | |
3792 | } | |
3793 | ||
8e5d75c9 | 3794 | static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { |
18032bec | 3795 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, |
84929218 | 3796 | .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS, |
4a7e2d73 | 3797 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), |
b061a82b | 3798 | offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, |
18032bec | 3799 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, |
84929218 | 3800 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
88ca1c2d FA |
3801 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), |
3802 | offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, | |
8e5d75c9 | 3803 | { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, |
84929218 | 3804 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
8e5d75c9 PC |
3805 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), |
3806 | offsetof(CPUARMState, cp15.dfar_ns) } }, | |
3807 | { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, | |
3808 | .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, | |
84929218 RH |
3809 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3810 | .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), | |
8e5d75c9 | 3811 | .resetvalue = 0, }, |
8e5d75c9 PC |
3812 | }; |
3813 | ||
3814 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { | |
6cd8a264 RH |
3815 | { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, |
3816 | .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, | |
84929218 | 3817 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
d81c519c | 3818 | .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, |
327ed10f | 3819 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af | 3820 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, |
84929218 RH |
3821 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3822 | .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
7dd8c9af FA |
3823 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
3824 | offsetof(CPUARMState, cp15.ttbr0_ns) } }, | |
327ed10f | 3825 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af | 3826 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, |
84929218 RH |
3827 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3828 | .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
7dd8c9af FA |
3829 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
3830 | offsetof(CPUARMState, cp15.ttbr1_ns) } }, | |
cb2e37df PM |
3831 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, |
3832 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | |
84929218 RH |
3833 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3834 | .writefn = vmsa_tcr_el12_write, | |
cb2e37df | 3835 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, |
11f136ee | 3836 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, |
cb2e37df | 3837 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
84929218 RH |
3838 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3839 | .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, | |
b061a82b | 3840 | .raw_writefn = vmsa_ttbcr_raw_write, |
d102058e RH |
3841 | /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */ |
3842 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]), | |
3843 | offsetof(CPUARMState, cp15.tcr_el[1])} }, | |
18032bec PM |
3844 | }; |
3845 | ||
ab638a32 RH |
3846 | /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing |
3847 | * qemu tlbs nor adjusting cached masks. | |
3848 | */ | |
3849 | static const ARMCPRegInfo ttbcr2_reginfo = { | |
3850 | .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3, | |
84929218 RH |
3851 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3852 | .type = ARM_CP_ALIAS, | |
d102058e RH |
3853 | .bank_fieldoffsets = { |
3854 | offsetofhigh32(CPUARMState, cp15.tcr_el[3].raw_tcr), | |
3855 | offsetofhigh32(CPUARMState, cp15.tcr_el[1].raw_tcr), | |
3856 | }, | |
ab638a32 RH |
3857 | }; |
3858 | ||
c4241c7d PM |
3859 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3860 | uint64_t value) | |
1047b9d7 PM |
3861 | { |
3862 | env->cp15.c15_ticonfig = value & 0xe7; | |
3863 | /* The OS_TYPE bit in this register changes the reported CPUID! */ | |
3864 | env->cp15.c0_cpuid = (value & (1 << 5)) ? | |
3865 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1047b9d7 PM |
3866 | } |
3867 | ||
c4241c7d PM |
3868 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3869 | uint64_t value) | |
1047b9d7 PM |
3870 | { |
3871 | env->cp15.c15_threadid = value & 0xffff; | |
1047b9d7 PM |
3872 | } |
3873 | ||
c4241c7d PM |
3874 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3875 | uint64_t value) | |
1047b9d7 PM |
3876 | { |
3877 | /* Wait-for-interrupt (deprecated) */ | |
2fc0cc0e | 3878 | cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); |
1047b9d7 PM |
3879 | } |
3880 | ||
c4241c7d PM |
3881 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3882 | uint64_t value) | |
c4804214 PM |
3883 | { |
3884 | /* On OMAP there are registers indicating the max/min index of dcache lines | |
3885 | * containing a dirty line; cache flush operations have to reset these. | |
3886 | */ | |
3887 | env->cp15.c15_i_max = 0x000; | |
3888 | env->cp15.c15_i_min = 0xff0; | |
c4804214 PM |
3889 | } |
3890 | ||
18032bec PM |
3891 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
3892 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, | |
3893 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, | |
d81c519c | 3894 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 3895 | .resetvalue = 0, }, |
1047b9d7 PM |
3896 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
3897 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
3898 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
3899 | .access = PL1_RW, | |
3900 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, | |
3901 | .writefn = omap_ticonfig_write }, | |
3902 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, | |
3903 | .access = PL1_RW, | |
3904 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, | |
3905 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, | |
3906 | .access = PL1_RW, .resetvalue = 0xff0, | |
3907 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, | |
3908 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, | |
3909 | .access = PL1_RW, | |
3910 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, | |
3911 | .writefn = omap_threadid_write }, | |
3912 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, | |
3913 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
7a0e58fa | 3914 | .type = ARM_CP_NO_RAW, |
1047b9d7 PM |
3915 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
3916 | /* TODO: Peripheral port remap register: | |
3917 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller | |
3918 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), | |
3919 | * when MMU is off. | |
3920 | */ | |
c4804214 | 3921 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
d4e6df63 | 3922 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
7a0e58fa | 3923 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, |
c4804214 | 3924 | .writefn = omap_cachemaint_write }, |
34f90529 PM |
3925 | { .name = "C9", .cp = 15, .crn = 9, |
3926 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | |
3927 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | |
1047b9d7 PM |
3928 | }; |
3929 | ||
c4241c7d PM |
3930 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3931 | uint64_t value) | |
1047b9d7 | 3932 | { |
c0f4af17 | 3933 | env->cp15.c15_cpar = value & 0x3fff; |
1047b9d7 PM |
3934 | } |
3935 | ||
3936 | static const ARMCPRegInfo xscale_cp_reginfo[] = { | |
3937 | { .name = "XSCALE_CPAR", | |
3938 | .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
3939 | .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, | |
3940 | .writefn = xscale_cpar_write, }, | |
2771db27 PM |
3941 | { .name = "XSCALE_AUXCR", |
3942 | .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, | |
3943 | .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), | |
3944 | .resetvalue = 0, }, | |
3b771579 PM |
3945 | /* XScale specific cache-lockdown: since we have no cache we NOP these |
3946 | * and hope the guest does not really rely on cache behaviour. | |
3947 | */ | |
3948 | { .name = "XSCALE_LOCK_ICACHE_LINE", | |
3949 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
3950 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3951 | { .name = "XSCALE_UNLOCK_ICACHE", | |
3952 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
3953 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3954 | { .name = "XSCALE_DCACHE_LOCK", | |
3955 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, | |
3956 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
3957 | { .name = "XSCALE_UNLOCK_DCACHE", | |
3958 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, | |
3959 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1047b9d7 PM |
3960 | }; |
3961 | ||
3962 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | |
3963 | /* RAZ/WI the whole crn=15 space, when we don't have a more specific | |
3964 | * implementation of this implementation-defined space. | |
3965 | * Ideally this should eventually disappear in favour of actually | |
3966 | * implementing the correct behaviour for all cores. | |
3967 | */ | |
3968 | { .name = "C15_IMPDEF", .cp = 15, .crn = 15, | |
3969 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
3671cd87 | 3970 | .access = PL1_RW, |
7a0e58fa | 3971 | .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, |
d4e6df63 | 3972 | .resetvalue = 0 }, |
18032bec PM |
3973 | }; |
3974 | ||
c4804214 PM |
3975 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
3976 | /* Cache status: RAZ because we have no cache so it's always clean */ | |
3977 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | |
7a0e58fa | 3978 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 3979 | .resetvalue = 0 }, |
c4804214 PM |
3980 | }; |
3981 | ||
3982 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | |
3983 | /* We never have a a block transfer operation in progress */ | |
3984 | { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, | |
7a0e58fa | 3985 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 3986 | .resetvalue = 0 }, |
30b05bba PM |
3987 | /* The cache ops themselves: these all NOP for QEMU */ |
3988 | { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, | |
3989 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3990 | { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, | |
3991 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3992 | { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, | |
3993 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3994 | { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, | |
3995 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3996 | { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, | |
3997 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3998 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, | |
3999 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
c4804214 PM |
4000 | }; |
4001 | ||
4002 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | |
4003 | /* The cache test-and-clean instructions always return (1 << 30) | |
4004 | * to indicate that there are no dirty cache lines. | |
4005 | */ | |
4006 | { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, | |
7a0e58fa | 4007 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4008 | .resetvalue = (1 << 30) }, |
c4804214 | 4009 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
7a0e58fa | 4010 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4011 | .resetvalue = (1 << 30) }, |
c4804214 PM |
4012 | }; |
4013 | ||
34f90529 PM |
4014 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
4015 | /* Ignore ReadBuffer accesses */ | |
4016 | { .name = "C9_READBUFFER", .cp = 15, .crn = 9, | |
4017 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
d4e6df63 | 4018 | .access = PL1_RW, .resetvalue = 0, |
7a0e58fa | 4019 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, |
34f90529 PM |
4020 | }; |
4021 | ||
731de9e6 EI |
4022 | static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4023 | { | |
731de9e6 | 4024 | unsigned int cur_el = arm_current_el(env); |
731de9e6 | 4025 | |
e6ef0169 | 4026 | if (arm_is_el2_enabled(env) && cur_el == 1) { |
731de9e6 EI |
4027 | return env->cp15.vpidr_el2; |
4028 | } | |
4029 | return raw_read(env, ri); | |
4030 | } | |
4031 | ||
06a7e647 | 4032 | static uint64_t mpidr_read_val(CPUARMState *env) |
81bdde9d | 4033 | { |
2fc0cc0e | 4034 | ARMCPU *cpu = env_archcpu(env); |
eb5e1d3c PF |
4035 | uint64_t mpidr = cpu->mp_affinity; |
4036 | ||
81bdde9d | 4037 | if (arm_feature(env, ARM_FEATURE_V7MP)) { |
78dbbbe4 | 4038 | mpidr |= (1U << 31); |
81bdde9d PM |
4039 | /* Cores which are uniprocessor (non-coherent) |
4040 | * but still implement the MP extensions set | |
a8e81b31 | 4041 | * bit 30. (For instance, Cortex-R5). |
81bdde9d | 4042 | */ |
a8e81b31 PC |
4043 | if (cpu->mp_is_up) { |
4044 | mpidr |= (1u << 30); | |
4045 | } | |
81bdde9d | 4046 | } |
c4241c7d | 4047 | return mpidr; |
81bdde9d PM |
4048 | } |
4049 | ||
06a7e647 EI |
4050 | static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4051 | { | |
f0d574d6 | 4052 | unsigned int cur_el = arm_current_el(env); |
f0d574d6 | 4053 | |
e6ef0169 | 4054 | if (arm_is_el2_enabled(env) && cur_el == 1) { |
f0d574d6 EI |
4055 | return env->cp15.vmpidr_el2; |
4056 | } | |
06a7e647 EI |
4057 | return mpidr_read_val(env); |
4058 | } | |
4059 | ||
7ac681cf | 4060 | static const ARMCPRegInfo lpae_cp_reginfo[] = { |
a903c449 | 4061 | /* NOP AMAIR0/1 */ |
b0fe2427 PM |
4062 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, |
4063 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | |
84929218 RH |
4064 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4065 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b0fe2427 | 4066 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ |
7ac681cf | 4067 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
84929218 RH |
4068 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4069 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
891a2fe7 | 4070 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
01c097f7 FA |
4071 | .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, |
4072 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), | |
4073 | offsetof(CPUARMState, cp15.par_ns)} }, | |
891a2fe7 | 4074 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, |
84929218 RH |
4075 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4076 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
7dd8c9af FA |
4077 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
4078 | offsetof(CPUARMState, cp15.ttbr0_ns) }, | |
b061a82b | 4079 | .writefn = vmsa_ttbr_write, }, |
891a2fe7 | 4080 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
84929218 RH |
4081 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4082 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
7dd8c9af FA |
4083 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
4084 | offsetof(CPUARMState, cp15.ttbr1_ns) }, | |
b061a82b | 4085 | .writefn = vmsa_ttbr_write, }, |
7ac681cf PM |
4086 | }; |
4087 | ||
c4241c7d | 4088 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 4089 | { |
c4241c7d | 4090 | return vfp_get_fpcr(env); |
b0d2b7d0 PM |
4091 | } |
4092 | ||
c4241c7d PM |
4093 | static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4094 | uint64_t value) | |
b0d2b7d0 PM |
4095 | { |
4096 | vfp_set_fpcr(env, value); | |
b0d2b7d0 PM |
4097 | } |
4098 | ||
c4241c7d | 4099 | static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 4100 | { |
c4241c7d | 4101 | return vfp_get_fpsr(env); |
b0d2b7d0 PM |
4102 | } |
4103 | ||
c4241c7d PM |
4104 | static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4105 | uint64_t value) | |
b0d2b7d0 PM |
4106 | { |
4107 | vfp_set_fpsr(env, value); | |
b0d2b7d0 PM |
4108 | } |
4109 | ||
3f208fd7 PM |
4110 | static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4111 | bool isread) | |
c2b820fe | 4112 | { |
aaec1432 | 4113 | if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { |
c2b820fe PM |
4114 | return CP_ACCESS_TRAP; |
4115 | } | |
4116 | return CP_ACCESS_OK; | |
4117 | } | |
4118 | ||
4119 | static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4120 | uint64_t value) | |
4121 | { | |
4122 | env->daif = value & PSTATE_DAIF; | |
4123 | } | |
4124 | ||
220f508f RH |
4125 | static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4126 | { | |
4127 | return env->pstate & PSTATE_PAN; | |
4128 | } | |
4129 | ||
4130 | static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4131 | uint64_t value) | |
4132 | { | |
4133 | env->pstate = (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN); | |
4134 | } | |
4135 | ||
4136 | static const ARMCPRegInfo pan_reginfo = { | |
4137 | .name = "PAN", .state = ARM_CP_STATE_AA64, | |
4138 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 3, | |
4139 | .type = ARM_CP_NO_RAW, .access = PL1_RW, | |
4140 | .readfn = aa64_pan_read, .writefn = aa64_pan_write | |
4141 | }; | |
4142 | ||
9eeb7a1c RH |
4143 | static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4144 | { | |
4145 | return env->pstate & PSTATE_UAO; | |
4146 | } | |
4147 | ||
4148 | static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4149 | uint64_t value) | |
4150 | { | |
4151 | env->pstate = (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO); | |
4152 | } | |
4153 | ||
4154 | static const ARMCPRegInfo uao_reginfo = { | |
4155 | .name = "UAO", .state = ARM_CP_STATE_AA64, | |
4156 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4, | |
4157 | .type = ARM_CP_NO_RAW, .access = PL1_RW, | |
4158 | .readfn = aa64_uao_read, .writefn = aa64_uao_write | |
4159 | }; | |
4160 | ||
dc8b1853 RC |
4161 | static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4162 | { | |
4163 | return env->pstate & PSTATE_DIT; | |
4164 | } | |
4165 | ||
4166 | static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4167 | uint64_t value) | |
4168 | { | |
4169 | env->pstate = (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT); | |
4170 | } | |
4171 | ||
4172 | static const ARMCPRegInfo dit_reginfo = { | |
4173 | .name = "DIT", .state = ARM_CP_STATE_AA64, | |
4174 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 5, | |
4175 | .type = ARM_CP_NO_RAW, .access = PL0_RW, | |
4176 | .readfn = aa64_dit_read, .writefn = aa64_dit_write | |
4177 | }; | |
4178 | ||
f2f68a78 RC |
4179 | static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4180 | { | |
4181 | return env->pstate & PSTATE_SSBS; | |
4182 | } | |
4183 | ||
4184 | static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4185 | uint64_t value) | |
4186 | { | |
4187 | env->pstate = (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS); | |
4188 | } | |
4189 | ||
4190 | static const ARMCPRegInfo ssbs_reginfo = { | |
4191 | .name = "SSBS", .state = ARM_CP_STATE_AA64, | |
4192 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 6, | |
4193 | .type = ARM_CP_NO_RAW, .access = PL0_RW, | |
4194 | .readfn = aa64_ssbs_read, .writefn = aa64_ssbs_write | |
4195 | }; | |
4196 | ||
38262d8a RH |
4197 | static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, |
4198 | const ARMCPRegInfo *ri, | |
4199 | bool isread) | |
8af35c37 | 4200 | { |
38262d8a RH |
4201 | /* Cache invalidate/clean to Point of Coherency or Persistence... */ |
4202 | switch (arm_current_el(env)) { | |
4203 | case 0: | |
4204 | /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ | |
4205 | if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { | |
4206 | return CP_ACCESS_TRAP; | |
4207 | } | |
4208 | /* fall through */ | |
4209 | case 1: | |
4210 | /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */ | |
4211 | if (arm_hcr_el2_eff(env) & HCR_TPCP) { | |
4212 | return CP_ACCESS_TRAP_EL2; | |
4213 | } | |
4214 | break; | |
8af35c37 PM |
4215 | } |
4216 | return CP_ACCESS_OK; | |
4217 | } | |
4218 | ||
38262d8a | 4219 | static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, |
1bed4d2e RH |
4220 | const ARMCPRegInfo *ri, |
4221 | bool isread) | |
4222 | { | |
38262d8a | 4223 | /* Cache invalidate/clean to Point of Unification... */ |
1bed4d2e RH |
4224 | switch (arm_current_el(env)) { |
4225 | case 0: | |
4226 | /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ | |
4227 | if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { | |
4228 | return CP_ACCESS_TRAP; | |
4229 | } | |
4230 | /* fall through */ | |
4231 | case 1: | |
38262d8a RH |
4232 | /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */ |
4233 | if (arm_hcr_el2_eff(env) & HCR_TPU) { | |
1bed4d2e RH |
4234 | return CP_ACCESS_TRAP_EL2; |
4235 | } | |
4236 | break; | |
4237 | } | |
4238 | return CP_ACCESS_OK; | |
4239 | } | |
4240 | ||
dbb1fb27 AB |
4241 | /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions |
4242 | * Page D4-1736 (DDI0487A.b) | |
4243 | */ | |
4244 | ||
b7e0730d RH |
4245 | static int vae1_tlbmask(CPUARMState *env) |
4246 | { | |
e04a5752 | 4247 | uint64_t hcr = arm_hcr_el2_eff(env); |
bc944d3a | 4248 | uint16_t mask; |
e04a5752 RDC |
4249 | |
4250 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
bc944d3a RDC |
4251 | mask = ARMMMUIdxBit_E20_2 | |
4252 | ARMMMUIdxBit_E20_2_PAN | | |
4253 | ARMMMUIdxBit_E20_0; | |
b7e0730d | 4254 | } else { |
bc944d3a | 4255 | mask = ARMMMUIdxBit_E10_1 | |
452ef8cb RH |
4256 | ARMMMUIdxBit_E10_1_PAN | |
4257 | ARMMMUIdxBit_E10_0; | |
b7e0730d | 4258 | } |
bc944d3a RDC |
4259 | |
4260 | if (arm_is_secure_below_el3(env)) { | |
4261 | mask >>= ARM_MMU_IDX_A_NS; | |
4262 | } | |
4263 | ||
4264 | return mask; | |
b7e0730d RH |
4265 | } |
4266 | ||
ea04dce7 RH |
4267 | /* Return 56 if TBI is enabled, 64 otherwise. */ |
4268 | static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, | |
4269 | uint64_t addr) | |
4270 | { | |
4271 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | |
4272 | int tbi = aa64_va_parameter_tbi(tcr, mmu_idx); | |
4273 | int select = extract64(addr, 55, 1); | |
4274 | ||
4275 | return (tbi >> select) & 1 ? 56 : 64; | |
4276 | } | |
4277 | ||
4278 | static int vae1_tlbbits(CPUARMState *env, uint64_t addr) | |
4279 | { | |
b6ad6062 | 4280 | uint64_t hcr = arm_hcr_el2_eff(env); |
ea04dce7 RH |
4281 | ARMMMUIdx mmu_idx; |
4282 | ||
4283 | /* Only the regime of the mmu_idx below is significant. */ | |
b6ad6062 | 4284 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { |
ea04dce7 RH |
4285 | mmu_idx = ARMMMUIdx_E20_0; |
4286 | } else { | |
4287 | mmu_idx = ARMMMUIdx_E10_0; | |
4288 | } | |
b6ad6062 RDC |
4289 | |
4290 | if (arm_is_secure_below_el3(env)) { | |
4291 | mmu_idx &= ~ARM_MMU_IDX_A_NS; | |
4292 | } | |
4293 | ||
ea04dce7 RH |
4294 | return tlbbits_for_regime(env, mmu_idx, addr); |
4295 | } | |
4296 | ||
fd3ed969 PM |
4297 | static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4298 | uint64_t value) | |
168aa23b | 4299 | { |
29a0af61 | 4300 | CPUState *cs = env_cpu(env); |
b7e0730d | 4301 | int mask = vae1_tlbmask(env); |
dbb1fb27 | 4302 | |
b7e0730d | 4303 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
168aa23b PM |
4304 | } |
4305 | ||
b4ab8ce9 PM |
4306 | static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4307 | uint64_t value) | |
4308 | { | |
29a0af61 | 4309 | CPUState *cs = env_cpu(env); |
b7e0730d | 4310 | int mask = vae1_tlbmask(env); |
b4ab8ce9 PM |
4311 | |
4312 | if (tlb_force_broadcast(env)) { | |
527db2be RH |
4313 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
4314 | } else { | |
4315 | tlb_flush_by_mmuidx(cs, mask); | |
b4ab8ce9 | 4316 | } |
b4ab8ce9 PM |
4317 | } |
4318 | ||
90c19cdf | 4319 | static int alle1_tlbmask(CPUARMState *env) |
168aa23b | 4320 | { |
90c19cdf RH |
4321 | /* |
4322 | * Note that the 'ALL' scope must invalidate both stage 1 and | |
fd3ed969 PM |
4323 | * stage 2 translations, whereas most other scopes only invalidate |
4324 | * stage 1 translations. | |
4325 | */ | |
fd3ed969 | 4326 | if (arm_is_secure_below_el3(env)) { |
452ef8cb RH |
4327 | return ARMMMUIdxBit_SE10_1 | |
4328 | ARMMMUIdxBit_SE10_1_PAN | | |
4329 | ARMMMUIdxBit_SE10_0; | |
fd3ed969 | 4330 | } else { |
452ef8cb RH |
4331 | return ARMMMUIdxBit_E10_1 | |
4332 | ARMMMUIdxBit_E10_1_PAN | | |
4333 | ARMMMUIdxBit_E10_0; | |
fd3ed969 | 4334 | } |
168aa23b PM |
4335 | } |
4336 | ||
85d0dc9f RH |
4337 | static int e2_tlbmask(CPUARMState *env) |
4338 | { | |
b6ad6062 RDC |
4339 | if (arm_is_secure_below_el3(env)) { |
4340 | return ARMMMUIdxBit_SE20_0 | | |
4341 | ARMMMUIdxBit_SE20_2 | | |
4342 | ARMMMUIdxBit_SE20_2_PAN | | |
4343 | ARMMMUIdxBit_SE2; | |
4344 | } else { | |
4345 | return ARMMMUIdxBit_E20_0 | | |
4346 | ARMMMUIdxBit_E20_2 | | |
4347 | ARMMMUIdxBit_E20_2_PAN | | |
4348 | ARMMMUIdxBit_E2; | |
4349 | } | |
85d0dc9f RH |
4350 | } |
4351 | ||
90c19cdf RH |
4352 | static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4353 | uint64_t value) | |
4354 | { | |
4355 | CPUState *cs = env_cpu(env); | |
4356 | int mask = alle1_tlbmask(env); | |
4357 | ||
4358 | tlb_flush_by_mmuidx(cs, mask); | |
4359 | } | |
4360 | ||
fd3ed969 | 4361 | static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
fa439fc5 PM |
4362 | uint64_t value) |
4363 | { | |
85d0dc9f RH |
4364 | CPUState *cs = env_cpu(env); |
4365 | int mask = e2_tlbmask(env); | |
fd3ed969 | 4366 | |
85d0dc9f | 4367 | tlb_flush_by_mmuidx(cs, mask); |
fd3ed969 PM |
4368 | } |
4369 | ||
43efaa33 PM |
4370 | static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4371 | uint64_t value) | |
4372 | { | |
2fc0cc0e | 4373 | ARMCPU *cpu = env_archcpu(env); |
43efaa33 PM |
4374 | CPUState *cs = CPU(cpu); |
4375 | ||
127b2b08 | 4376 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3); |
43efaa33 PM |
4377 | } |
4378 | ||
fd3ed969 PM |
4379 | static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4380 | uint64_t value) | |
4381 | { | |
29a0af61 | 4382 | CPUState *cs = env_cpu(env); |
90c19cdf RH |
4383 | int mask = alle1_tlbmask(env); |
4384 | ||
4385 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); | |
fa439fc5 PM |
4386 | } |
4387 | ||
2bfb9d75 PM |
4388 | static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4389 | uint64_t value) | |
4390 | { | |
29a0af61 | 4391 | CPUState *cs = env_cpu(env); |
85d0dc9f | 4392 | int mask = e2_tlbmask(env); |
2bfb9d75 | 4393 | |
85d0dc9f | 4394 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
2bfb9d75 PM |
4395 | } |
4396 | ||
43efaa33 PM |
4397 | static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4398 | uint64_t value) | |
4399 | { | |
29a0af61 | 4400 | CPUState *cs = env_cpu(env); |
43efaa33 | 4401 | |
127b2b08 | 4402 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3); |
43efaa33 PM |
4403 | } |
4404 | ||
fd3ed969 PM |
4405 | static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4406 | uint64_t value) | |
fa439fc5 | 4407 | { |
fd3ed969 PM |
4408 | /* Invalidate by VA, EL2 |
4409 | * Currently handles both VAE2 and VALE2, since we don't support | |
4410 | * flush-last-level-only. | |
4411 | */ | |
85d0dc9f RH |
4412 | CPUState *cs = env_cpu(env); |
4413 | int mask = e2_tlbmask(env); | |
fd3ed969 PM |
4414 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
4415 | ||
85d0dc9f | 4416 | tlb_flush_page_by_mmuidx(cs, pageaddr, mask); |
fd3ed969 PM |
4417 | } |
4418 | ||
43efaa33 PM |
4419 | static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4420 | uint64_t value) | |
4421 | { | |
4422 | /* Invalidate by VA, EL3 | |
4423 | * Currently handles both VAE3 and VALE3, since we don't support | |
4424 | * flush-last-level-only. | |
4425 | */ | |
2fc0cc0e | 4426 | ARMCPU *cpu = env_archcpu(env); |
43efaa33 PM |
4427 | CPUState *cs = CPU(cpu); |
4428 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
4429 | ||
127b2b08 | 4430 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3); |
43efaa33 PM |
4431 | } |
4432 | ||
fd3ed969 PM |
4433 | static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4434 | uint64_t value) | |
4435 | { | |
90c19cdf RH |
4436 | CPUState *cs = env_cpu(env); |
4437 | int mask = vae1_tlbmask(env); | |
fa439fc5 | 4438 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ea04dce7 | 4439 | int bits = vae1_tlbbits(env, pageaddr); |
fa439fc5 | 4440 | |
ea04dce7 | 4441 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); |
fa439fc5 PM |
4442 | } |
4443 | ||
b4ab8ce9 PM |
4444 | static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4445 | uint64_t value) | |
4446 | { | |
4447 | /* Invalidate by VA, EL1&0 (AArch64 version). | |
4448 | * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, | |
4449 | * since we don't support flush-for-specific-ASID-only or | |
4450 | * flush-last-level-only. | |
4451 | */ | |
90c19cdf RH |
4452 | CPUState *cs = env_cpu(env); |
4453 | int mask = vae1_tlbmask(env); | |
b4ab8ce9 | 4454 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ea04dce7 | 4455 | int bits = vae1_tlbbits(env, pageaddr); |
b4ab8ce9 PM |
4456 | |
4457 | if (tlb_force_broadcast(env)) { | |
ea04dce7 | 4458 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); |
527db2be | 4459 | } else { |
ea04dce7 | 4460 | tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits); |
b4ab8ce9 | 4461 | } |
b4ab8ce9 PM |
4462 | } |
4463 | ||
fd3ed969 PM |
4464 | static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4465 | uint64_t value) | |
fa439fc5 | 4466 | { |
29a0af61 | 4467 | CPUState *cs = env_cpu(env); |
fd3ed969 | 4468 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
b6ad6062 RDC |
4469 | bool secure = arm_is_secure_below_el3(env); |
4470 | int mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; | |
eb849d8f | 4471 | int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2, |
b6ad6062 | 4472 | pageaddr); |
fa439fc5 | 4473 | |
b6ad6062 | 4474 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); |
fa439fc5 PM |
4475 | } |
4476 | ||
43efaa33 PM |
4477 | static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4478 | uint64_t value) | |
4479 | { | |
29a0af61 | 4480 | CPUState *cs = env_cpu(env); |
43efaa33 | 4481 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ea04dce7 | 4482 | int bits = tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr); |
43efaa33 | 4483 | |
ea04dce7 RH |
4484 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, |
4485 | ARMMMUIdxBit_SE3, bits); | |
43efaa33 PM |
4486 | } |
4487 | ||
84940ed8 | 4488 | #ifdef TARGET_AARCH64 |
ab1cdb47 RH |
4489 | typedef struct { |
4490 | uint64_t base; | |
84940ed8 | 4491 | uint64_t length; |
ab1cdb47 RH |
4492 | } TLBIRange; |
4493 | ||
4494 | static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, | |
4495 | uint64_t value) | |
4496 | { | |
4497 | unsigned int page_size_granule, page_shift, num, scale, exponent; | |
3974ff93 RH |
4498 | /* Extract one bit to represent the va selector in use. */ |
4499 | uint64_t select = sextract64(value, 36, 1); | |
4500 | ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true); | |
ab1cdb47 | 4501 | TLBIRange ret = { }; |
84940ed8 | 4502 | |
84940ed8 RC |
4503 | page_size_granule = extract64(value, 46, 2); |
4504 | ||
3974ff93 RH |
4505 | /* The granule encoded in value must match the granule in use. */ |
4506 | if (page_size_granule != (param.using64k ? 3 : param.using16k ? 2 : 1)) { | |
4507 | qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\n", | |
84940ed8 | 4508 | page_size_granule); |
ab1cdb47 | 4509 | return ret; |
84940ed8 RC |
4510 | } |
4511 | ||
52a9f609 | 4512 | page_shift = (page_size_granule - 1) * 2 + 12; |
ab1cdb47 RH |
4513 | num = extract64(value, 39, 5); |
4514 | scale = extract64(value, 44, 2); | |
84940ed8 | 4515 | exponent = (5 * scale) + 1; |
84940ed8 | 4516 | |
ab1cdb47 | 4517 | ret.length = (num + 1) << (exponent + page_shift); |
84940ed8 | 4518 | |
3974ff93 | 4519 | if (param.select) { |
d976de21 | 4520 | ret.base = sextract64(value, 0, 37); |
84940ed8 | 4521 | } else { |
d976de21 | 4522 | ret.base = extract64(value, 0, 37); |
84940ed8 | 4523 | } |
ef56c242 RH |
4524 | if (param.ds) { |
4525 | /* | |
4526 | * With DS=1, BaseADDR is always shifted 16 so that it is able | |
4527 | * to address all 52 va bits. The input address is perforce | |
4528 | * aligned on a 64k boundary regardless of translation granule. | |
4529 | */ | |
4530 | page_shift = 16; | |
4531 | } | |
d976de21 | 4532 | ret.base <<= page_shift; |
84940ed8 | 4533 | |
ab1cdb47 | 4534 | return ret; |
84940ed8 RC |
4535 | } |
4536 | ||
4537 | static void do_rvae_write(CPUARMState *env, uint64_t value, | |
4538 | int idxmap, bool synced) | |
4539 | { | |
4540 | ARMMMUIdx one_idx = ARM_MMU_IDX_A | ctz32(idxmap); | |
ab1cdb47 | 4541 | TLBIRange range; |
84940ed8 RC |
4542 | int bits; |
4543 | ||
ab1cdb47 RH |
4544 | range = tlbi_aa64_get_range(env, one_idx, value); |
4545 | bits = tlbbits_for_regime(env, one_idx, range.base); | |
84940ed8 RC |
4546 | |
4547 | if (synced) { | |
4548 | tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env), | |
ab1cdb47 RH |
4549 | range.base, |
4550 | range.length, | |
84940ed8 RC |
4551 | idxmap, |
4552 | bits); | |
4553 | } else { | |
ab1cdb47 RH |
4554 | tlb_flush_range_by_mmuidx(env_cpu(env), range.base, |
4555 | range.length, idxmap, bits); | |
84940ed8 RC |
4556 | } |
4557 | } | |
4558 | ||
4559 | static void tlbi_aa64_rvae1_write(CPUARMState *env, | |
4560 | const ARMCPRegInfo *ri, | |
4561 | uint64_t value) | |
4562 | { | |
4563 | /* | |
4564 | * Invalidate by VA range, EL1&0. | |
4565 | * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1, | |
4566 | * since we don't support flush-for-specific-ASID-only or | |
4567 | * flush-last-level-only. | |
4568 | */ | |
4569 | ||
4570 | do_rvae_write(env, value, vae1_tlbmask(env), | |
4571 | tlb_force_broadcast(env)); | |
4572 | } | |
4573 | ||
4574 | static void tlbi_aa64_rvae1is_write(CPUARMState *env, | |
4575 | const ARMCPRegInfo *ri, | |
4576 | uint64_t value) | |
4577 | { | |
4578 | /* | |
4579 | * Invalidate by VA range, Inner/Outer Shareable EL1&0. | |
4580 | * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS, | |
4581 | * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support | |
4582 | * flush-for-specific-ASID-only, flush-last-level-only or inner/outer | |
4583 | * shareable specific flushes. | |
4584 | */ | |
4585 | ||
4586 | do_rvae_write(env, value, vae1_tlbmask(env), true); | |
4587 | } | |
4588 | ||
4589 | static int vae2_tlbmask(CPUARMState *env) | |
4590 | { | |
4591 | return (arm_is_secure_below_el3(env) | |
4592 | ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2); | |
4593 | } | |
4594 | ||
4595 | static void tlbi_aa64_rvae2_write(CPUARMState *env, | |
4596 | const ARMCPRegInfo *ri, | |
4597 | uint64_t value) | |
4598 | { | |
4599 | /* | |
4600 | * Invalidate by VA range, EL2. | |
4601 | * Currently handles all of RVAE2 and RVALE2, | |
4602 | * since we don't support flush-for-specific-ASID-only or | |
4603 | * flush-last-level-only. | |
4604 | */ | |
4605 | ||
4606 | do_rvae_write(env, value, vae2_tlbmask(env), | |
4607 | tlb_force_broadcast(env)); | |
4608 | ||
4609 | ||
4610 | } | |
4611 | ||
4612 | static void tlbi_aa64_rvae2is_write(CPUARMState *env, | |
4613 | const ARMCPRegInfo *ri, | |
4614 | uint64_t value) | |
4615 | { | |
4616 | /* | |
4617 | * Invalidate by VA range, Inner/Outer Shareable, EL2. | |
4618 | * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS, | |
4619 | * since we don't support flush-for-specific-ASID-only, | |
4620 | * flush-last-level-only or inner/outer shareable specific flushes. | |
4621 | */ | |
4622 | ||
4623 | do_rvae_write(env, value, vae2_tlbmask(env), true); | |
4624 | ||
4625 | } | |
4626 | ||
4627 | static void tlbi_aa64_rvae3_write(CPUARMState *env, | |
4628 | const ARMCPRegInfo *ri, | |
4629 | uint64_t value) | |
4630 | { | |
4631 | /* | |
4632 | * Invalidate by VA range, EL3. | |
4633 | * Currently handles all of RVAE3 and RVALE3, | |
4634 | * since we don't support flush-for-specific-ASID-only or | |
4635 | * flush-last-level-only. | |
4636 | */ | |
4637 | ||
4638 | do_rvae_write(env, value, ARMMMUIdxBit_SE3, | |
4639 | tlb_force_broadcast(env)); | |
4640 | } | |
4641 | ||
4642 | static void tlbi_aa64_rvae3is_write(CPUARMState *env, | |
4643 | const ARMCPRegInfo *ri, | |
4644 | uint64_t value) | |
4645 | { | |
4646 | /* | |
4647 | * Invalidate by VA range, EL3, Inner/Outer Shareable. | |
4648 | * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS, | |
4649 | * since we don't support flush-for-specific-ASID-only, | |
4650 | * flush-last-level-only or inner/outer specific flushes. | |
4651 | */ | |
4652 | ||
4653 | do_rvae_write(env, value, ARMMMUIdxBit_SE3, true); | |
4654 | } | |
4655 | #endif | |
4656 | ||
3f208fd7 PM |
4657 | static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4658 | bool isread) | |
aca3f40b | 4659 | { |
4351cb72 RH |
4660 | int cur_el = arm_current_el(env); |
4661 | ||
4662 | if (cur_el < 2) { | |
4663 | uint64_t hcr = arm_hcr_el2_eff(env); | |
4664 | ||
4665 | if (cur_el == 0) { | |
4666 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
4667 | if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) { | |
4668 | return CP_ACCESS_TRAP_EL2; | |
4669 | } | |
4670 | } else { | |
4671 | if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) { | |
4672 | return CP_ACCESS_TRAP; | |
4673 | } | |
4674 | if (hcr & HCR_TDZ) { | |
4675 | return CP_ACCESS_TRAP_EL2; | |
4676 | } | |
4677 | } | |
4678 | } else if (hcr & HCR_TDZ) { | |
4679 | return CP_ACCESS_TRAP_EL2; | |
4680 | } | |
aca3f40b PM |
4681 | } |
4682 | return CP_ACCESS_OK; | |
4683 | } | |
4684 | ||
4685 | static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
4686 | { | |
2fc0cc0e | 4687 | ARMCPU *cpu = env_archcpu(env); |
aca3f40b PM |
4688 | int dzp_bit = 1 << 4; |
4689 | ||
4690 | /* DZP indicates whether DC ZVA access is allowed */ | |
3f208fd7 | 4691 | if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) { |
aca3f40b PM |
4692 | dzp_bit = 0; |
4693 | } | |
4694 | return cpu->dcz_blocksize | dzp_bit; | |
4695 | } | |
4696 | ||
3f208fd7 PM |
4697 | static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4698 | bool isread) | |
f502cfc2 | 4699 | { |
cdcf1405 | 4700 | if (!(env->pstate & PSTATE_SP)) { |
f502cfc2 PM |
4701 | /* Access to SP_EL0 is undefined if it's being used as |
4702 | * the stack pointer. | |
4703 | */ | |
4704 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
4705 | } | |
4706 | return CP_ACCESS_OK; | |
4707 | } | |
4708 | ||
4709 | static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
4710 | { | |
4711 | return env->pstate & PSTATE_SP; | |
4712 | } | |
4713 | ||
4714 | static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
4715 | { | |
4716 | update_spsel(env, val); | |
4717 | } | |
4718 | ||
137feaa9 FA |
4719 | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4720 | uint64_t value) | |
4721 | { | |
2fc0cc0e | 4722 | ARMCPU *cpu = env_archcpu(env); |
137feaa9 | 4723 | |
f00faf13 RH |
4724 | if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { |
4725 | /* M bit is RAZ/WI for PMSA with no MPU implemented */ | |
4726 | value &= ~SCTLR_M; | |
4727 | } | |
4728 | ||
4729 | /* ??? Lots of these bits are not implemented. */ | |
4730 | ||
4731 | if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) { | |
4732 | if (ri->opc1 == 6) { /* SCTLR_EL3 */ | |
4733 | value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); | |
4734 | } else { | |
4735 | value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | | |
4736 | SCTLR_ATA0 | SCTLR_ATA); | |
4737 | } | |
4738 | } | |
4739 | ||
137feaa9 FA |
4740 | if (raw_read(env, ri) == value) { |
4741 | /* Skip the TLB flush if nothing actually changed; Linux likes | |
4742 | * to do a lot of pointless SCTLR writes. | |
4743 | */ | |
4744 | return; | |
4745 | } | |
4746 | ||
4747 | raw_write(env, ri, value); | |
f00faf13 | 4748 | |
137feaa9 | 4749 | /* This may enable/disable the MMU, so do a TLB flush. */ |
d10eb08f | 4750 | tlb_flush(CPU(cpu)); |
2e5dcf36 RH |
4751 | |
4752 | if (ri->type & ARM_CP_SUPPRESS_TB_END) { | |
4753 | /* | |
4754 | * Normally we would always end the TB on an SCTLR write; see the | |
4755 | * comment in ARMCPRegInfo sctlr initialization below for why Xscale | |
4756 | * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild | |
4757 | * of hflags from the translator, so do it here. | |
4758 | */ | |
4759 | arm_rebuild_hflags(env); | |
4760 | } | |
137feaa9 FA |
4761 | } |
4762 | ||
a8d64e73 PM |
4763 | static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4764 | uint64_t value) | |
4765 | { | |
4766 | env->cp15.mdcr_el3 = value & SDCR_VALID_MASK; | |
4767 | } | |
4768 | ||
b0d2b7d0 PM |
4769 | static const ARMCPRegInfo v8_cp_reginfo[] = { |
4770 | /* Minimal set of EL0-visible registers. This will need to be expanded | |
4771 | * significantly for system emulation of AArch64 CPUs. | |
4772 | */ | |
4773 | { .name = "NZCV", .state = ARM_CP_STATE_AA64, | |
4774 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, | |
4775 | .access = PL0_RW, .type = ARM_CP_NZCV }, | |
c2b820fe PM |
4776 | { .name = "DAIF", .state = ARM_CP_STATE_AA64, |
4777 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, | |
7a0e58fa | 4778 | .type = ARM_CP_NO_RAW, |
c2b820fe PM |
4779 | .access = PL0_RW, .accessfn = aa64_daif_access, |
4780 | .fieldoffset = offsetof(CPUARMState, daif), | |
4781 | .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, | |
b0d2b7d0 PM |
4782 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, |
4783 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | |
b916c9c3 | 4784 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 4785 | .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, |
b0d2b7d0 PM |
4786 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, |
4787 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | |
b916c9c3 | 4788 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 4789 | .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, |
b0d2b7d0 PM |
4790 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, |
4791 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | |
7a0e58fa | 4792 | .access = PL0_R, .type = ARM_CP_NO_RAW, |
aca3f40b PM |
4793 | .readfn = aa64_dczid_read }, |
4794 | { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, | |
4795 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, | |
4796 | .access = PL0_W, .type = ARM_CP_DC_ZVA, | |
4797 | #ifndef CONFIG_USER_ONLY | |
4798 | /* Avoid overhead of an access check that always passes in user-mode */ | |
4799 | .accessfn = aa64_zva_access, | |
4800 | #endif | |
4801 | }, | |
0eef9d98 PM |
4802 | { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, |
4803 | .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, | |
4804 | .access = PL1_R, .type = ARM_CP_CURRENTEL }, | |
8af35c37 PM |
4805 | /* Cache ops: all NOPs since we don't emulate caches */ |
4806 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, | |
4807 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
38262d8a RH |
4808 | .access = PL1_W, .type = ARM_CP_NOP, |
4809 | .accessfn = aa64_cacheop_pou_access }, | |
8af35c37 PM |
4810 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, |
4811 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
38262d8a RH |
4812 | .access = PL1_W, .type = ARM_CP_NOP, |
4813 | .accessfn = aa64_cacheop_pou_access }, | |
8af35c37 PM |
4814 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, |
4815 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | |
4816 | .access = PL0_W, .type = ARM_CP_NOP, | |
38262d8a | 4817 | .accessfn = aa64_cacheop_pou_access }, |
8af35c37 PM |
4818 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, |
4819 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
1bed4d2e RH |
4820 | .access = PL1_W, .accessfn = aa64_cacheop_poc_access, |
4821 | .type = ARM_CP_NOP }, | |
8af35c37 PM |
4822 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, |
4823 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
1803d271 | 4824 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
8af35c37 PM |
4825 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, |
4826 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | |
4827 | .access = PL0_W, .type = ARM_CP_NOP, | |
1bed4d2e | 4828 | .accessfn = aa64_cacheop_poc_access }, |
8af35c37 PM |
4829 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, |
4830 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
1803d271 | 4831 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
8af35c37 PM |
4832 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, |
4833 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | |
4834 | .access = PL0_W, .type = ARM_CP_NOP, | |
38262d8a | 4835 | .accessfn = aa64_cacheop_pou_access }, |
8af35c37 PM |
4836 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, |
4837 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | |
4838 | .access = PL0_W, .type = ARM_CP_NOP, | |
1bed4d2e | 4839 | .accessfn = aa64_cacheop_poc_access }, |
8af35c37 PM |
4840 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, |
4841 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
1803d271 | 4842 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
168aa23b PM |
4843 | /* TLBI operations */ |
4844 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 4845 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, |
30881b73 | 4846 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4847 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 4848 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4849 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
30881b73 | 4850 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4851 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4852 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4853 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
30881b73 | 4854 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4855 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 4856 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4857 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
30881b73 | 4858 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4859 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4860 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4861 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
30881b73 | 4862 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4863 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4864 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4865 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
30881b73 | 4866 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4867 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4868 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4869 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, |
30881b73 | 4870 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4871 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 4872 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4873 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
30881b73 | 4874 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4875 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4876 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4877 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
30881b73 | 4878 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4879 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 4880 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4881 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
30881b73 | 4882 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4883 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4884 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4885 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
30881b73 | 4886 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4887 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4888 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4889 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
30881b73 | 4890 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4891 | .writefn = tlbi_aa64_vae1_write }, |
cea66e91 PM |
4892 | { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, |
4893 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
bf05340c | 4894 | .access = PL2_W, .type = ARM_CP_NOP }, |
cea66e91 PM |
4895 | { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, |
4896 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
bf05340c | 4897 | .access = PL2_W, .type = ARM_CP_NOP }, |
83ddf975 PM |
4898 | { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, |
4899 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
4900 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 4901 | .writefn = tlbi_aa64_alle1is_write }, |
43efaa33 PM |
4902 | { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, |
4903 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, | |
4904 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4905 | .writefn = tlbi_aa64_alle1is_write }, | |
cea66e91 PM |
4906 | { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, |
4907 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
bf05340c | 4908 | .access = PL2_W, .type = ARM_CP_NOP }, |
cea66e91 PM |
4909 | { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, |
4910 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
bf05340c | 4911 | .access = PL2_W, .type = ARM_CP_NOP }, |
83ddf975 PM |
4912 | { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, |
4913 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
4914 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 4915 | .writefn = tlbi_aa64_alle1_write }, |
43efaa33 PM |
4916 | { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, |
4917 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, | |
4918 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4919 | .writefn = tlbi_aa64_alle1is_write }, | |
19525524 PM |
4920 | #ifndef CONFIG_USER_ONLY |
4921 | /* 64 bit address translation operations */ | |
4922 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
4923 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, | |
0710b2fa PM |
4924 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4925 | .writefn = ats_write64 }, | |
19525524 PM |
4926 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, |
4927 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, | |
0710b2fa PM |
4928 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4929 | .writefn = ats_write64 }, | |
19525524 PM |
4930 | { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, |
4931 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, | |
0710b2fa PM |
4932 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4933 | .writefn = ats_write64 }, | |
19525524 PM |
4934 | { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, |
4935 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, | |
0710b2fa PM |
4936 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4937 | .writefn = ats_write64 }, | |
2a47df95 | 4938 | { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4939 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, |
0710b2fa PM |
4940 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4941 | .writefn = ats_write64 }, | |
2a47df95 | 4942 | { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4943 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, |
0710b2fa PM |
4944 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4945 | .writefn = ats_write64 }, | |
2a47df95 | 4946 | { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4947 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, |
0710b2fa PM |
4948 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4949 | .writefn = ats_write64 }, | |
2a47df95 | 4950 | { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4951 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, |
0710b2fa PM |
4952 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4953 | .writefn = ats_write64 }, | |
2a47df95 PM |
4954 | /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ |
4955 | { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, | |
4956 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, | |
0710b2fa PM |
4957 | .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4958 | .writefn = ats_write64 }, | |
2a47df95 PM |
4959 | { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, |
4960 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, | |
0710b2fa PM |
4961 | .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4962 | .writefn = ats_write64 }, | |
c96fc9b5 EI |
4963 | { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, |
4964 | .type = ARM_CP_ALIAS, | |
4965 | .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, | |
4966 | .access = PL1_RW, .resetvalue = 0, | |
4967 | .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), | |
4968 | .writefn = par_write }, | |
19525524 | 4969 | #endif |
995939a6 | 4970 | /* TLB invalidate last level of translation table walk */ |
9449fdf6 | 4971 | { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
30881b73 RH |
4972 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
4973 | .writefn = tlbimva_is_write }, | |
9449fdf6 | 4974 | { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
30881b73 | 4975 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
fa439fc5 | 4976 | .writefn = tlbimvaa_is_write }, |
9449fdf6 | 4977 | { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
30881b73 RH |
4978 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
4979 | .writefn = tlbimva_write }, | |
9449fdf6 | 4980 | { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
30881b73 RH |
4981 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
4982 | .writefn = tlbimvaa_write }, | |
541ef8c2 SS |
4983 | { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, |
4984 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4985 | .writefn = tlbimva_hyp_write }, | |
4986 | { .name = "TLBIMVALHIS", | |
4987 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
4988 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4989 | .writefn = tlbimva_hyp_is_write }, | |
4990 | { .name = "TLBIIPAS2", | |
4991 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
bf05340c | 4992 | .type = ARM_CP_NOP, .access = PL2_W }, |
541ef8c2 SS |
4993 | { .name = "TLBIIPAS2IS", |
4994 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
bf05340c | 4995 | .type = ARM_CP_NOP, .access = PL2_W }, |
541ef8c2 SS |
4996 | { .name = "TLBIIPAS2L", |
4997 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
bf05340c | 4998 | .type = ARM_CP_NOP, .access = PL2_W }, |
541ef8c2 SS |
4999 | { .name = "TLBIIPAS2LIS", |
5000 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
bf05340c | 5001 | .type = ARM_CP_NOP, .access = PL2_W }, |
9449fdf6 PM |
5002 | /* 32 bit cache operations */ |
5003 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
38262d8a | 5004 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, |
9449fdf6 PM |
5005 | { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, |
5006 | .type = ARM_CP_NOP, .access = PL1_W }, | |
5007 | { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
38262d8a | 5008 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, |
9449fdf6 | 5009 | { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, |
38262d8a | 5010 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, |
9449fdf6 PM |
5011 | { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, |
5012 | .type = ARM_CP_NOP, .access = PL1_W }, | |
5013 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | |
5014 | .type = ARM_CP_NOP, .access = PL1_W }, | |
5015 | { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
1bed4d2e | 5016 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 5017 | { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, |
1803d271 | 5018 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 5019 | { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, |
1bed4d2e | 5020 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 5021 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, |
1803d271 | 5022 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 5023 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, |
38262d8a | 5024 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, |
9449fdf6 | 5025 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, |
1bed4d2e | 5026 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 5027 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, |
1803d271 | 5028 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 5029 | /* MMU Domain access control / MPU write buffer control */ |
0c17d68c | 5030 | { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, |
84929218 | 5031 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
0c17d68c FA |
5032 | .writefn = dacr_write, .raw_writefn = raw_write, |
5033 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
5034 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a0618a19 | 5035 | { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5036 | .type = ARM_CP_ALIAS, |
a0618a19 | 5037 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, |
6947f059 EI |
5038 | .access = PL1_RW, |
5039 | .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, | |
a65f1de9 | 5040 | { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5041 | .type = ARM_CP_ALIAS, |
a65f1de9 | 5042 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
5043 | .access = PL1_RW, |
5044 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, | |
f502cfc2 PM |
5045 | /* We rely on the access checks not allowing the guest to write to the |
5046 | * state field when SPSel indicates that it's being used as the stack | |
5047 | * pointer. | |
5048 | */ | |
5049 | { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, | |
5050 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, | |
5051 | .access = PL1_RW, .accessfn = sp_el0_access, | |
7a0e58fa | 5052 | .type = ARM_CP_ALIAS, |
f502cfc2 | 5053 | .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, |
884b4dee GB |
5054 | { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, |
5055 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 5056 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
884b4dee | 5057 | .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, |
f502cfc2 PM |
5058 | { .name = "SPSel", .state = ARM_CP_STATE_AA64, |
5059 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, | |
7a0e58fa | 5060 | .type = ARM_CP_NO_RAW, |
f502cfc2 | 5061 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, |
03fbf20f PM |
5062 | { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, |
5063 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, | |
a4c88675 RH |
5064 | .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU, |
5065 | .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, | |
6a43e0b6 PM |
5066 | { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, |
5067 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, | |
5068 | .access = PL2_RW, .resetvalue = 0, | |
5069 | .writefn = dacr_write, .raw_writefn = raw_write, | |
5070 | .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, | |
5071 | { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, | |
5072 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, | |
5073 | .access = PL2_RW, .resetvalue = 0, | |
5074 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, | |
5075 | { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, | |
5076 | .type = ARM_CP_ALIAS, | |
5077 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, | |
5078 | .access = PL2_RW, | |
5079 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, | |
5080 | { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, | |
5081 | .type = ARM_CP_ALIAS, | |
5082 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, | |
5083 | .access = PL2_RW, | |
5084 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, | |
5085 | { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, | |
5086 | .type = ARM_CP_ALIAS, | |
5087 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, | |
5088 | .access = PL2_RW, | |
5089 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, | |
5090 | { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, | |
5091 | .type = ARM_CP_ALIAS, | |
5092 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, | |
5093 | .access = PL2_RW, | |
5094 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, | |
a8d64e73 PM |
5095 | { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, |
5096 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, | |
5097 | .resetvalue = 0, | |
5098 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) }, | |
5099 | { .name = "SDCR", .type = ARM_CP_ALIAS, | |
5100 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1, | |
5101 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, | |
5102 | .writefn = sdcr_write, | |
5103 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, | |
b0d2b7d0 PM |
5104 | }; |
5105 | ||
d42e3c26 | 5106 | /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ |
4771cd01 | 5107 | static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { |
d79e0c06 | 5108 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, |
d42e3c26 EI |
5109 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, |
5110 | .access = PL2_RW, | |
5111 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | |
ce4afed8 | 5112 | { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH, |
f149e3e8 EI |
5113 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
5114 | .access = PL2_RW, | |
ce4afed8 | 5115 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
831a2fca PM |
5116 | { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, |
5117 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, | |
5118 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
68e78e33 PM |
5119 | { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, |
5120 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, | |
5121 | .access = PL2_RW, | |
5122 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
c6f19164 GB |
5123 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
5124 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
5125 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
95f949ac EI |
5126 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
5127 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
5128 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5129 | .resetvalue = 0 }, | |
5130 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
b5ede85b | 5131 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, |
95f949ac | 5132 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
2179ef95 PM |
5133 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
5134 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
5135 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5136 | .resetvalue = 0 }, | |
55b53c71 | 5137 | { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, |
b5ede85b | 5138 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, |
2179ef95 PM |
5139 | .access = PL2_RW, .type = ARM_CP_CONST, |
5140 | .resetvalue = 0 }, | |
37cd6c24 PM |
5141 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
5142 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
5143 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5144 | .resetvalue = 0 }, | |
5145 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
5146 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
5147 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5148 | .resetvalue = 0 }, | |
06ec4c8c EI |
5149 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
5150 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
5151 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
68e9c2fe EI |
5152 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH, |
5153 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
93dd1e61 | 5154 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
68e9c2fe | 5155 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
b698e9cf EI |
5156 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
5157 | .cp = 15, .opc1 = 6, .crm = 2, | |
5158 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
5159 | .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | |
5160 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
5161 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
5162 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b9cb5323 EI |
5163 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
5164 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
5165 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
ff05f37b EI |
5166 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
5167 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
5168 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
a57633c0 EI |
5169 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
5170 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
5171 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5172 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
5173 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
5174 | .resetvalue = 0 }, | |
0b6440af EI |
5175 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
5176 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
5177 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
edac4d8a EI |
5178 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
5179 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
5180 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5181 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
5182 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
5183 | .resetvalue = 0 }, | |
b0e66d95 EI |
5184 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
5185 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
5186 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5187 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
5188 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
5189 | .resetvalue = 0 }, | |
5190 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
5191 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
5192 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5193 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
5194 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
5195 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
14cc7b54 SF |
5196 | { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, |
5197 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | |
d6c8cf81 PM |
5198 | .access = PL2_RW, .accessfn = access_tda, |
5199 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
59e05530 EI |
5200 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, |
5201 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
93dd1e61 | 5202 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
59e05530 | 5203 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
2a5a9abd AF |
5204 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
5205 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
5206 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
cba517c3 PM |
5207 | { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, |
5208 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, | |
5209 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5210 | { .name = "HIFAR", .state = ARM_CP_STATE_AA32, | |
5211 | .type = ARM_CP_CONST, | |
5212 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | |
5213 | .access = PL2_RW, .resetvalue = 0 }, | |
d42e3c26 EI |
5214 | }; |
5215 | ||
ce4afed8 PM |
5216 | /* Ditto, but for registers which exist in ARMv8 but not v7 */ |
5217 | static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { | |
5218 | { .name = "HCR2", .state = ARM_CP_STATE_AA32, | |
5219 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, | |
5220 | .access = PL2_RW, | |
5221 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
ce4afed8 PM |
5222 | }; |
5223 | ||
d1fb4da2 | 5224 | static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) |
f149e3e8 | 5225 | { |
2fc0cc0e | 5226 | ARMCPU *cpu = env_archcpu(env); |
d1fb4da2 RH |
5227 | |
5228 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
5229 | valid_mask |= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */ | |
5230 | } else { | |
5231 | valid_mask |= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */ | |
5232 | } | |
f149e3e8 EI |
5233 | |
5234 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
5235 | valid_mask &= ~HCR_HCD; | |
77077a83 JK |
5236 | } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { |
5237 | /* Architecturally HCR.TSC is RES0 if EL3 is not implemented. | |
5238 | * However, if we're using the SMC PSCI conduit then QEMU is | |
5239 | * effectively acting like EL3 firmware and so the guest at | |
5240 | * EL2 should retain the ability to prevent EL1 from being | |
5241 | * able to make SMC calls into the ersatz firmware, so in | |
5242 | * that case HCR.TSC should be read/write. | |
5243 | */ | |
f149e3e8 EI |
5244 | valid_mask &= ~HCR_TSC; |
5245 | } | |
d1fb4da2 RH |
5246 | |
5247 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
5248 | if (cpu_isar_feature(aa64_vh, cpu)) { | |
5249 | valid_mask |= HCR_E2H; | |
5250 | } | |
5251 | if (cpu_isar_feature(aa64_lor, cpu)) { | |
5252 | valid_mask |= HCR_TLOR; | |
5253 | } | |
5254 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
5255 | valid_mask |= HCR_API | HCR_APK; | |
5256 | } | |
8ddb300b RH |
5257 | if (cpu_isar_feature(aa64_mte, cpu)) { |
5258 | valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5; | |
5259 | } | |
ef682cdb | 5260 | } |
f149e3e8 EI |
5261 | |
5262 | /* Clear RES0 bits. */ | |
5263 | value &= valid_mask; | |
5264 | ||
8ddb300b RH |
5265 | /* |
5266 | * These bits change the MMU setup: | |
f149e3e8 EI |
5267 | * HCR_VM enables stage 2 translation |
5268 | * HCR_PTW forbids certain page-table setups | |
8ddb300b RH |
5269 | * HCR_DC disables stage1 and enables stage2 translation |
5270 | * HCR_DCT enables tagging on (disabled) stage1 translation | |
f149e3e8 | 5271 | */ |
8ddb300b | 5272 | if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT)) { |
d10eb08f | 5273 | tlb_flush(CPU(cpu)); |
f149e3e8 | 5274 | } |
ce4afed8 | 5275 | env->cp15.hcr_el2 = value; |
89430fc6 PM |
5276 | |
5277 | /* | |
5278 | * Updates to VI and VF require us to update the status of | |
5279 | * virtual interrupts, which are the logical OR of these bits | |
5280 | * and the state of the input lines from the GIC. (This requires | |
5281 | * that we have the iothread lock, which is done by marking the | |
5282 | * reginfo structs as ARM_CP_IO.) | |
5283 | * Note that if a write to HCR pends a VIRQ or VFIQ it is never | |
5284 | * possible for it to be taken immediately, because VIRQ and | |
5285 | * VFIQ are masked unless running at EL0 or EL1, and HCR | |
5286 | * can only be written at EL2. | |
5287 | */ | |
5288 | g_assert(qemu_mutex_iothread_locked()); | |
5289 | arm_cpu_update_virq(cpu); | |
5290 | arm_cpu_update_vfiq(cpu); | |
ce4afed8 PM |
5291 | } |
5292 | ||
d1fb4da2 RH |
5293 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
5294 | { | |
5295 | do_hcr_write(env, value, 0); | |
5296 | } | |
5297 | ||
ce4afed8 PM |
5298 | static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, |
5299 | uint64_t value) | |
5300 | { | |
5301 | /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */ | |
5302 | value = deposit64(env->cp15.hcr_el2, 32, 32, value); | |
d1fb4da2 | 5303 | do_hcr_write(env, value, MAKE_64BIT_MASK(0, 32)); |
ce4afed8 PM |
5304 | } |
5305 | ||
5306 | static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, | |
5307 | uint64_t value) | |
5308 | { | |
5309 | /* Handle HCR write, i.e. write to low half of HCR_EL2 */ | |
5310 | value = deposit64(env->cp15.hcr_el2, 0, 32, value); | |
d1fb4da2 | 5311 | do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32)); |
f149e3e8 EI |
5312 | } |
5313 | ||
f7778444 RH |
5314 | /* |
5315 | * Return the effective value of HCR_EL2. | |
5316 | * Bits that are not included here: | |
5317 | * RW (read from SCR_EL3.RW as needed) | |
5318 | */ | |
5319 | uint64_t arm_hcr_el2_eff(CPUARMState *env) | |
5320 | { | |
5321 | uint64_t ret = env->cp15.hcr_el2; | |
5322 | ||
e6ef0169 | 5323 | if (!arm_is_el2_enabled(env)) { |
f7778444 RH |
5324 | /* |
5325 | * "This register has no effect if EL2 is not enabled in the | |
5326 | * current Security state". This is ARMv8.4-SecEL2 speak for | |
5327 | * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1). | |
5328 | * | |
5329 | * Prior to that, the language was "In an implementation that | |
5330 | * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves | |
5331 | * as if this field is 0 for all purposes other than a direct | |
5332 | * read or write access of HCR_EL2". With lots of enumeration | |
5333 | * on a per-field basis. In current QEMU, this is condition | |
5334 | * is arm_is_secure_below_el3. | |
5335 | * | |
5336 | * Since the v8.4 language applies to the entire register, and | |
5337 | * appears to be backward compatible, use that. | |
5338 | */ | |
4990e1d3 RH |
5339 | return 0; |
5340 | } | |
5341 | ||
5342 | /* | |
5343 | * For a cpu that supports both aarch64 and aarch32, we can set bits | |
5344 | * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32. | |
5345 | * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32. | |
5346 | */ | |
5347 | if (!arm_el_is_aa64(env, 2)) { | |
5348 | uint64_t aa32_valid; | |
5349 | ||
5350 | /* | |
5351 | * These bits are up-to-date as of ARMv8.6. | |
5352 | * For HCR, it's easiest to list just the 2 bits that are invalid. | |
5353 | * For HCR2, list those that are valid. | |
5354 | */ | |
5355 | aa32_valid = MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ); | |
5356 | aa32_valid |= (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNCE | | |
5357 | HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS); | |
5358 | ret &= aa32_valid; | |
5359 | } | |
5360 | ||
5361 | if (ret & HCR_TGE) { | |
5362 | /* These bits are up-to-date as of ARMv8.6. */ | |
f7778444 RH |
5363 | if (ret & HCR_E2H) { |
5364 | ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | | |
5365 | HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | | |
5366 | HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | | |
4990e1d3 RH |
5367 | HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE | |
5368 | HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT | | |
5369 | HCR_TTLBIS | HCR_TTLBOS | HCR_TID5); | |
f7778444 RH |
5370 | } else { |
5371 | ret |= HCR_FMO | HCR_IMO | HCR_AMO; | |
5372 | } | |
5373 | ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | | |
5374 | HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | | |
5375 | HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | | |
5376 | HCR_TLOR); | |
5377 | } | |
5378 | ||
5379 | return ret; | |
5380 | } | |
5381 | ||
fc1120a7 PM |
5382 | static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5383 | uint64_t value) | |
5384 | { | |
5385 | /* | |
5386 | * For A-profile AArch32 EL3, if NSACR.CP10 | |
5387 | * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. | |
5388 | */ | |
5389 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
5390 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
5391 | value &= ~(0x3 << 10); | |
5392 | value |= env->cp15.cptr_el[2] & (0x3 << 10); | |
5393 | } | |
5394 | env->cp15.cptr_el[2] = value; | |
5395 | } | |
5396 | ||
5397 | static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5398 | { | |
5399 | /* | |
5400 | * For A-profile AArch32 EL3, if NSACR.CP10 | |
5401 | * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. | |
5402 | */ | |
5403 | uint64_t value = env->cp15.cptr_el[2]; | |
5404 | ||
5405 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
5406 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
5407 | value |= 0x3 << 10; | |
5408 | } | |
5409 | return value; | |
5410 | } | |
5411 | ||
4771cd01 | 5412 | static const ARMCPRegInfo el2_cp_reginfo[] = { |
f149e3e8 | 5413 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
89430fc6 | 5414 | .type = ARM_CP_IO, |
f149e3e8 EI |
5415 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
5416 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
c624ea0f | 5417 | .writefn = hcr_write }, |
ce4afed8 | 5418 | { .name = "HCR", .state = ARM_CP_STATE_AA32, |
89430fc6 | 5419 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
5420 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
5421 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
c624ea0f | 5422 | .writefn = hcr_writelow }, |
831a2fca PM |
5423 | { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, |
5424 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, | |
5425 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3b685ba7 | 5426 | { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5427 | .type = ARM_CP_ALIAS, |
3b685ba7 EI |
5428 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, |
5429 | .access = PL2_RW, | |
5430 | .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, | |
68e78e33 | 5431 | { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, |
f2c30f42 EI |
5432 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, |
5433 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, | |
cba517c3 | 5434 | { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, |
63b60551 EI |
5435 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, |
5436 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, | |
cba517c3 PM |
5437 | { .name = "HIFAR", .state = ARM_CP_STATE_AA32, |
5438 | .type = ARM_CP_ALIAS, | |
5439 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | |
5440 | .access = PL2_RW, | |
5441 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) }, | |
3b685ba7 | 5442 | { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5443 | .type = ARM_CP_ALIAS, |
3b685ba7 | 5444 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
5445 | .access = PL2_RW, |
5446 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, | |
d79e0c06 | 5447 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, |
d42e3c26 EI |
5448 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, |
5449 | .access = PL2_RW, .writefn = vbar_write, | |
5450 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), | |
5451 | .resetvalue = 0 }, | |
884b4dee GB |
5452 | { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, |
5453 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 5454 | .access = PL3_RW, .type = ARM_CP_ALIAS, |
884b4dee | 5455 | .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, |
c6f19164 GB |
5456 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
5457 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
5458 | .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, | |
fc1120a7 PM |
5459 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]), |
5460 | .readfn = cptr_el2_read, .writefn = cptr_el2_write }, | |
95f949ac EI |
5461 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
5462 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
5463 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), | |
5464 | .resetvalue = 0 }, | |
5465 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
b5ede85b | 5466 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, |
95f949ac EI |
5467 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
5468 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, | |
2179ef95 PM |
5469 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
5470 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
5471 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5472 | .resetvalue = 0 }, | |
5473 | /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ | |
55b53c71 | 5474 | { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, |
b5ede85b | 5475 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, |
2179ef95 PM |
5476 | .access = PL2_RW, .type = ARM_CP_CONST, |
5477 | .resetvalue = 0 }, | |
37cd6c24 PM |
5478 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
5479 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
5480 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5481 | .resetvalue = 0 }, | |
5482 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
5483 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
5484 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5485 | .resetvalue = 0 }, | |
06ec4c8c EI |
5486 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
5487 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
d06dc933 RH |
5488 | .access = PL2_RW, .writefn = vmsa_tcr_el12_write, |
5489 | /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */ | |
06ec4c8c | 5490 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, |
68e9c2fe EI |
5491 | { .name = "VTCR", .state = ARM_CP_STATE_AA32, |
5492 | .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 | 5493 | .type = ARM_CP_ALIAS, |
68e9c2fe EI |
5494 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
5495 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, | |
5496 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, | |
5497 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 PM |
5498 | .access = PL2_RW, |
5499 | /* no .writefn needed as this can't cause an ASID change; | |
5500 | * no .raw_writefn or .resetfn needed as we never use mask/base_mask | |
5501 | */ | |
68e9c2fe | 5502 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, |
b698e9cf EI |
5503 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
5504 | .cp = 15, .opc1 = 6, .crm = 2, | |
5505 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
5506 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
5507 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), | |
5508 | .writefn = vttbr_write }, | |
5509 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
5510 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
5511 | .access = PL2_RW, .writefn = vttbr_write, | |
5512 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, | |
b9cb5323 EI |
5513 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
5514 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
5515 | .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, | |
5516 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, | |
ff05f37b EI |
5517 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
5518 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
5519 | .access = PL2_RW, .resetvalue = 0, | |
5520 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, | |
a57633c0 EI |
5521 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
5522 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
ed30da8e | 5523 | .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write, |
a57633c0 EI |
5524 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
5525 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
5526 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
a57633c0 | 5527 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
541ef8c2 SS |
5528 | { .name = "TLBIALLNSNH", |
5529 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
5530 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5531 | .writefn = tlbiall_nsnh_write }, | |
5532 | { .name = "TLBIALLNSNHIS", | |
5533 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
5534 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5535 | .writefn = tlbiall_nsnh_is_write }, | |
5536 | { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
5537 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5538 | .writefn = tlbiall_hyp_write }, | |
5539 | { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
5540 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5541 | .writefn = tlbiall_hyp_is_write }, | |
5542 | { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
5543 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5544 | .writefn = tlbimva_hyp_write }, | |
5545 | { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
5546 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5547 | .writefn = tlbimva_hyp_is_write }, | |
51da9014 EI |
5548 | { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, |
5549 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
5550 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 5551 | .writefn = tlbi_aa64_alle2_write }, |
8742d49d EI |
5552 | { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, |
5553 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
5554 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 5555 | .writefn = tlbi_aa64_vae2_write }, |
2bfb9d75 PM |
5556 | { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, |
5557 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, | |
5558 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
5559 | .writefn = tlbi_aa64_vae2_write }, | |
5560 | { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, | |
5561 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
5562 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
5563 | .writefn = tlbi_aa64_alle2is_write }, | |
8742d49d EI |
5564 | { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, |
5565 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
5566 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 5567 | .writefn = tlbi_aa64_vae2is_write }, |
2bfb9d75 PM |
5568 | { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, |
5569 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
5570 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
5571 | .writefn = tlbi_aa64_vae2is_write }, | |
edac4d8a | 5572 | #ifndef CONFIG_USER_ONLY |
2a47df95 PM |
5573 | /* Unlike the other EL2-related AT operations, these must |
5574 | * UNDEF from EL3 if EL2 is not implemented, which is why we | |
5575 | * define them here rather than with the rest of the AT ops. | |
5576 | */ | |
5577 | { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, | |
5578 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
5579 | .access = PL2_W, .accessfn = at_s1e2_access, | |
0710b2fa | 5580 | .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, |
2a47df95 PM |
5581 | { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, |
5582 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | |
5583 | .access = PL2_W, .accessfn = at_s1e2_access, | |
0710b2fa | 5584 | .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, |
14db7fe0 PM |
5585 | /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE |
5586 | * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 | |
5587 | * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose | |
5588 | * to behave as if SCR.NS was 1. | |
5589 | */ | |
5590 | { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
5591 | .access = PL2_W, | |
0710b2fa | 5592 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
14db7fe0 PM |
5593 | { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, |
5594 | .access = PL2_W, | |
0710b2fa | 5595 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
0b6440af EI |
5596 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
5597 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
5598 | /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the | |
5599 | * reset values as IMPDEF. We choose to reset to 3 to comply with | |
5600 | * both ARMv7 and ARMv8. | |
5601 | */ | |
5602 | .access = PL2_RW, .resetvalue = 3, | |
5603 | .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, | |
edac4d8a EI |
5604 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
5605 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
5606 | .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, | |
5607 | .writefn = gt_cntvoff_write, | |
5608 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
5609 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
5610 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, | |
5611 | .writefn = gt_cntvoff_write, | |
5612 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
b0e66d95 EI |
5613 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
5614 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
5615 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
5616 | .type = ARM_CP_IO, .access = PL2_RW, | |
5617 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
5618 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
5619 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
5620 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO, | |
5621 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
5622 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
5623 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
d44ec156 | 5624 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, |
b0e66d95 EI |
5625 | .resetfn = gt_hyp_timer_reset, |
5626 | .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, | |
5627 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
5628 | .type = ARM_CP_IO, | |
5629 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
5630 | .access = PL2_RW, | |
5631 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), | |
5632 | .resetvalue = 0, | |
5633 | .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, | |
edac4d8a | 5634 | #endif |
21c2dd77 PM |
5635 | /* The only field of MDCR_EL2 that has a defined architectural reset value |
5636 | * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N. | |
5637 | */ | |
5638 | { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, | |
5639 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | |
5640 | .access = PL2_RW, .resetvalue = PMCR_NUM_COUNTERS, | |
5641 | .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), }, | |
59e05530 EI |
5642 | { .name = "HPFAR", .state = ARM_CP_STATE_AA32, |
5643 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
5644 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
5645 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
5646 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, | |
5647 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
5648 | .access = PL2_RW, | |
5649 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
2a5a9abd AF |
5650 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
5651 | .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
5652 | .access = PL2_RW, | |
5653 | .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, | |
3b685ba7 EI |
5654 | }; |
5655 | ||
ce4afed8 PM |
5656 | static const ARMCPRegInfo el2_v8_cp_reginfo[] = { |
5657 | { .name = "HCR2", .state = ARM_CP_STATE_AA32, | |
89430fc6 | 5658 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
5659 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, |
5660 | .access = PL2_RW, | |
5661 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2), | |
5662 | .writefn = hcr_writehigh }, | |
ce4afed8 PM |
5663 | }; |
5664 | ||
e9152ee9 RDC |
5665 | static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5666 | bool isread) | |
5667 | { | |
5668 | if (arm_current_el(env) == 3 || arm_is_secure_below_el3(env)) { | |
5669 | return CP_ACCESS_OK; | |
5670 | } | |
5671 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
5672 | } | |
5673 | ||
5674 | static const ARMCPRegInfo el2_sec_cp_reginfo[] = { | |
5675 | { .name = "VSTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
5676 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 0, | |
5677 | .access = PL2_RW, .accessfn = sel2_access, | |
5678 | .fieldoffset = offsetof(CPUARMState, cp15.vsttbr_el2) }, | |
5679 | { .name = "VSTCR_EL2", .state = ARM_CP_STATE_AA64, | |
5680 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2, | |
5681 | .access = PL2_RW, .accessfn = sel2_access, | |
5682 | .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) }, | |
e9152ee9 RDC |
5683 | }; |
5684 | ||
2f027fc5 PM |
5685 | static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5686 | bool isread) | |
5687 | { | |
5688 | /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. | |
926c1b97 | 5689 | * At Secure EL1 it traps to EL3 or EL2. |
2f027fc5 PM |
5690 | */ |
5691 | if (arm_current_el(env) == 3) { | |
5692 | return CP_ACCESS_OK; | |
5693 | } | |
5694 | if (arm_is_secure_below_el3(env)) { | |
926c1b97 RDC |
5695 | if (env->cp15.scr_el3 & SCR_EEL2) { |
5696 | return CP_ACCESS_TRAP_EL2; | |
5697 | } | |
2f027fc5 PM |
5698 | return CP_ACCESS_TRAP_EL3; |
5699 | } | |
5700 | /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ | |
5701 | if (isread) { | |
5702 | return CP_ACCESS_OK; | |
5703 | } | |
5704 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
5705 | } | |
5706 | ||
60fb1a87 GB |
5707 | static const ARMCPRegInfo el3_cp_reginfo[] = { |
5708 | { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, | |
5709 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, | |
5710 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), | |
10d0ef3e | 5711 | .resetfn = scr_reset, .writefn = scr_write }, |
f80741d1 | 5712 | { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL, |
60fb1a87 | 5713 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, |
efe4a274 PM |
5714 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
5715 | .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), | |
b061a82b | 5716 | .writefn = scr_write }, |
60fb1a87 GB |
5717 | { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, |
5718 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, | |
5719 | .access = PL3_RW, .resetvalue = 0, | |
5720 | .fieldoffset = offsetof(CPUARMState, cp15.sder) }, | |
5721 | { .name = "SDER", | |
5722 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, | |
5723 | .access = PL3_RW, .resetvalue = 0, | |
5724 | .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, | |
60fb1a87 | 5725 | { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, |
efe4a274 PM |
5726 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
5727 | .writefn = vbar_write, .resetvalue = 0, | |
60fb1a87 | 5728 | .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, |
7dd8c9af FA |
5729 | { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, |
5730 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, | |
f478847f | 5731 | .access = PL3_RW, .resetvalue = 0, |
7dd8c9af | 5732 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, |
11f136ee FA |
5733 | { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, |
5734 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, | |
6459b94c PM |
5735 | .access = PL3_RW, |
5736 | /* no .writefn needed as this can't cause an ASID change; | |
811595a2 PM |
5737 | * we must provide a .raw_writefn and .resetfn because we handle |
5738 | * reset and migration for the AArch32 TTBCR(S), which might be | |
5739 | * using mask and base_mask. | |
6459b94c | 5740 | */ |
811595a2 | 5741 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, |
11f136ee | 5742 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, |
81547d66 | 5743 | { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5744 | .type = ARM_CP_ALIAS, |
81547d66 EI |
5745 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, |
5746 | .access = PL3_RW, | |
5747 | .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, | |
f2c30f42 | 5748 | { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, |
f2c30f42 EI |
5749 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, |
5750 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, | |
63b60551 EI |
5751 | { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, |
5752 | .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, | |
5753 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, | |
81547d66 | 5754 | { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5755 | .type = ARM_CP_ALIAS, |
81547d66 | 5756 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
5757 | .access = PL3_RW, |
5758 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) }, | |
a1ba125c EI |
5759 | { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, |
5760 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, | |
5761 | .access = PL3_RW, .writefn = vbar_write, | |
5762 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), | |
5763 | .resetvalue = 0 }, | |
c6f19164 GB |
5764 | { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, |
5765 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, | |
5766 | .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, | |
5767 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, | |
4cfb8ad8 PM |
5768 | { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, |
5769 | .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, | |
5770 | .access = PL3_RW, .resetvalue = 0, | |
5771 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, | |
2179ef95 PM |
5772 | { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64, |
5773 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, | |
5774 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5775 | .resetvalue = 0 }, | |
37cd6c24 PM |
5776 | { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, |
5777 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, | |
5778 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5779 | .resetvalue = 0 }, | |
5780 | { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, | |
5781 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, | |
5782 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5783 | .resetvalue = 0 }, | |
43efaa33 PM |
5784 | { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, |
5785 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, | |
5786 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5787 | .writefn = tlbi_aa64_alle3is_write }, | |
5788 | { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, | |
5789 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, | |
5790 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5791 | .writefn = tlbi_aa64_vae3is_write }, | |
5792 | { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, | |
5793 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, | |
5794 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5795 | .writefn = tlbi_aa64_vae3is_write }, | |
5796 | { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, | |
5797 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, | |
5798 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5799 | .writefn = tlbi_aa64_alle3_write }, | |
5800 | { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, | |
5801 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, | |
5802 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5803 | .writefn = tlbi_aa64_vae3_write }, | |
5804 | { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, | |
5805 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, | |
5806 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5807 | .writefn = tlbi_aa64_vae3_write }, | |
0f1a3b24 FA |
5808 | }; |
5809 | ||
e2cce18f RH |
5810 | #ifndef CONFIG_USER_ONLY |
5811 | /* Test if system register redirection is to occur in the current state. */ | |
5812 | static bool redirect_for_e2h(CPUARMState *env) | |
5813 | { | |
5814 | return arm_current_el(env) == 2 && (arm_hcr_el2_eff(env) & HCR_E2H); | |
5815 | } | |
5816 | ||
5817 | static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5818 | { | |
5819 | CPReadFn *readfn; | |
5820 | ||
5821 | if (redirect_for_e2h(env)) { | |
5822 | /* Switch to the saved EL2 version of the register. */ | |
5823 | ri = ri->opaque; | |
5824 | readfn = ri->readfn; | |
5825 | } else { | |
5826 | readfn = ri->orig_readfn; | |
5827 | } | |
5828 | if (readfn == NULL) { | |
5829 | readfn = raw_read; | |
5830 | } | |
5831 | return readfn(env, ri); | |
5832 | } | |
5833 | ||
5834 | static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5835 | uint64_t value) | |
5836 | { | |
5837 | CPWriteFn *writefn; | |
5838 | ||
5839 | if (redirect_for_e2h(env)) { | |
5840 | /* Switch to the saved EL2 version of the register. */ | |
5841 | ri = ri->opaque; | |
5842 | writefn = ri->writefn; | |
5843 | } else { | |
5844 | writefn = ri->orig_writefn; | |
5845 | } | |
5846 | if (writefn == NULL) { | |
5847 | writefn = raw_write; | |
5848 | } | |
5849 | writefn(env, ri, value); | |
5850 | } | |
5851 | ||
5852 | static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) | |
5853 | { | |
5854 | struct E2HAlias { | |
5855 | uint32_t src_key, dst_key, new_key; | |
5856 | const char *src_name, *dst_name, *new_name; | |
5857 | bool (*feature)(const ARMISARegisters *id); | |
5858 | }; | |
5859 | ||
5860 | #define K(op0, op1, crn, crm, op2) \ | |
5861 | ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) | |
5862 | ||
5863 | static const struct E2HAlias aliases[] = { | |
5864 | { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), | |
5865 | "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, | |
5866 | { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), | |
5867 | "CPACR", "CPTR_EL2", "CPACR_EL12" }, | |
5868 | { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), | |
5869 | "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, | |
5870 | { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), | |
5871 | "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, | |
5872 | { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), | |
5873 | "TCR_EL1", "TCR_EL2", "TCR_EL12" }, | |
5874 | { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), | |
5875 | "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, | |
5876 | { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), | |
5877 | "ELR_EL1", "ELR_EL2", "ELR_EL12" }, | |
5878 | { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0), | |
5879 | "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" }, | |
5880 | { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1), | |
5881 | "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" }, | |
5882 | { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0), | |
5883 | "ESR_EL1", "ESR_EL2", "ESR_EL12" }, | |
5884 | { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0), | |
5885 | "FAR_EL1", "FAR_EL2", "FAR_EL12" }, | |
5886 | { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), | |
5887 | "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, | |
5888 | { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), | |
5889 | "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" }, | |
5890 | { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), | |
5891 | "VBAR", "VBAR_EL2", "VBAR_EL12" }, | |
5892 | { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), | |
5893 | "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, | |
5894 | { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), | |
5895 | "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" }, | |
5896 | ||
5897 | /* | |
5898 | * Note that redirection of ZCR is mentioned in the description | |
5899 | * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but | |
5900 | * not in the summary table. | |
5901 | */ | |
5902 | { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), | |
5903 | "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, | |
5904 | ||
4b779ceb RH |
5905 | { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), |
5906 | "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, | |
5907 | ||
e2cce18f RH |
5908 | /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ |
5909 | /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ | |
5910 | }; | |
5911 | #undef K | |
5912 | ||
5913 | size_t i; | |
5914 | ||
5915 | for (i = 0; i < ARRAY_SIZE(aliases); i++) { | |
5916 | const struct E2HAlias *a = &aliases[i]; | |
5917 | ARMCPRegInfo *src_reg, *dst_reg; | |
5918 | ||
5919 | if (a->feature && !a->feature(&cpu->isar)) { | |
5920 | continue; | |
5921 | } | |
5922 | ||
5923 | src_reg = g_hash_table_lookup(cpu->cp_regs, &a->src_key); | |
5924 | dst_reg = g_hash_table_lookup(cpu->cp_regs, &a->dst_key); | |
5925 | g_assert(src_reg != NULL); | |
5926 | g_assert(dst_reg != NULL); | |
5927 | ||
5928 | /* Cross-compare names to detect typos in the keys. */ | |
5929 | g_assert(strcmp(src_reg->name, a->src_name) == 0); | |
5930 | g_assert(strcmp(dst_reg->name, a->dst_name) == 0); | |
5931 | ||
5932 | /* None of the core system registers use opaque; we will. */ | |
5933 | g_assert(src_reg->opaque == NULL); | |
5934 | ||
5935 | /* Create alias before redirection so we dup the right data. */ | |
5936 | if (a->new_key) { | |
5937 | ARMCPRegInfo *new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo)); | |
5938 | uint32_t *new_key = g_memdup(&a->new_key, sizeof(uint32_t)); | |
5939 | bool ok; | |
5940 | ||
5941 | new_reg->name = a->new_name; | |
5942 | new_reg->type |= ARM_CP_ALIAS; | |
5943 | /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ | |
5944 | new_reg->access &= PL2_RW | PL3_RW; | |
5945 | ||
5946 | ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg); | |
5947 | g_assert(ok); | |
5948 | } | |
5949 | ||
5950 | src_reg->opaque = dst_reg; | |
5951 | src_reg->orig_readfn = src_reg->readfn ?: raw_read; | |
5952 | src_reg->orig_writefn = src_reg->writefn ?: raw_write; | |
5953 | if (!src_reg->raw_readfn) { | |
5954 | src_reg->raw_readfn = raw_read; | |
5955 | } | |
5956 | if (!src_reg->raw_writefn) { | |
5957 | src_reg->raw_writefn = raw_write; | |
5958 | } | |
5959 | src_reg->readfn = el2_e2h_read; | |
5960 | src_reg->writefn = el2_e2h_write; | |
5961 | } | |
5962 | } | |
5963 | #endif | |
5964 | ||
3f208fd7 PM |
5965 | static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5966 | bool isread) | |
7da845b0 | 5967 | { |
97475a89 RH |
5968 | int cur_el = arm_current_el(env); |
5969 | ||
5970 | if (cur_el < 2) { | |
5971 | uint64_t hcr = arm_hcr_el2_eff(env); | |
5972 | ||
5973 | if (cur_el == 0) { | |
5974 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
5975 | if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) { | |
5976 | return CP_ACCESS_TRAP_EL2; | |
5977 | } | |
5978 | } else { | |
5979 | if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) { | |
5980 | return CP_ACCESS_TRAP; | |
5981 | } | |
5982 | if (hcr & HCR_TID2) { | |
5983 | return CP_ACCESS_TRAP_EL2; | |
5984 | } | |
5985 | } | |
5986 | } else if (hcr & HCR_TID2) { | |
5987 | return CP_ACCESS_TRAP_EL2; | |
5988 | } | |
7da845b0 | 5989 | } |
630fcd4d MZ |
5990 | |
5991 | if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) { | |
5992 | return CP_ACCESS_TRAP_EL2; | |
5993 | } | |
5994 | ||
7da845b0 PM |
5995 | return CP_ACCESS_OK; |
5996 | } | |
5997 | ||
1424ca8d DM |
5998 | static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5999 | uint64_t value) | |
6000 | { | |
6001 | /* Writes to OSLAR_EL1 may update the OS lock status, which can be | |
6002 | * read via a bit in OSLSR_EL1. | |
6003 | */ | |
6004 | int oslock; | |
6005 | ||
6006 | if (ri->state == ARM_CP_STATE_AA32) { | |
6007 | oslock = (value == 0xC5ACCE55); | |
6008 | } else { | |
6009 | oslock = value & 1; | |
6010 | } | |
6011 | ||
6012 | env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); | |
6013 | } | |
6014 | ||
50300698 | 6015 | static const ARMCPRegInfo debug_cp_reginfo[] = { |
50300698 | 6016 | /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped |
10aae104 PM |
6017 | * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; |
6018 | * unlike DBGDRAR it is never accessible from EL0. | |
6019 | * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 | |
6020 | * accessor. | |
50300698 PM |
6021 | */ |
6022 | { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
91b0a238 PM |
6023 | .access = PL0_R, .accessfn = access_tdra, |
6024 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
10aae104 PM |
6025 | { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, |
6026 | .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, | |
91b0a238 PM |
6027 | .access = PL1_R, .accessfn = access_tdra, |
6028 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
50300698 | 6029 | { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
91b0a238 PM |
6030 | .access = PL0_R, .accessfn = access_tdra, |
6031 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
17a9eb53 | 6032 | /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ |
10aae104 PM |
6033 | { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, |
6034 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
d6c8cf81 | 6035 | .access = PL1_RW, .accessfn = access_tda, |
0e5e8935 PM |
6036 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), |
6037 | .resetvalue = 0 }, | |
49a6f3bf NH |
6038 | /* |
6039 | * MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external | |
6040 | * Debug Communication Channel is not implemented. | |
6041 | */ | |
6042 | { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64, | |
6043 | .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0, | |
6044 | .access = PL0_R, .accessfn = access_tda, | |
6045 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6046 | /* | |
6047 | * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as | |
6048 | * it is unlikely a guest will care. | |
5e8b12ff PM |
6049 | * We don't implement the configurable EL0 access. |
6050 | */ | |
49a6f3bf NH |
6051 | { .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32, |
6052 | .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
7a0e58fa | 6053 | .type = ARM_CP_ALIAS, |
d6c8cf81 | 6054 | .access = PL1_R, .accessfn = access_tda, |
b061a82b | 6055 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, |
10aae104 PM |
6056 | { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, |
6057 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, | |
1424ca8d | 6058 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
187f678d | 6059 | .accessfn = access_tdosa, |
1424ca8d DM |
6060 | .writefn = oslar_write }, |
6061 | { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, | |
6062 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, | |
6063 | .access = PL1_R, .resetvalue = 10, | |
187f678d | 6064 | .accessfn = access_tdosa, |
1424ca8d | 6065 | .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, |
5e8b12ff PM |
6066 | /* Dummy OSDLR_EL1: 32-bit Linux will read this */ |
6067 | { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, | |
6068 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, | |
187f678d PM |
6069 | .access = PL1_RW, .accessfn = access_tdosa, |
6070 | .type = ARM_CP_NOP }, | |
5e8b12ff PM |
6071 | /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't |
6072 | * implement vector catch debug events yet. | |
6073 | */ | |
6074 | { .name = "DBGVCR", | |
6075 | .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
d6c8cf81 PM |
6076 | .access = PL1_RW, .accessfn = access_tda, |
6077 | .type = ARM_CP_NOP }, | |
4d2ec4da PM |
6078 | /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor |
6079 | * to save and restore a 32-bit guest's DBGVCR) | |
6080 | */ | |
6081 | { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, | |
6082 | .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, | |
6083 | .access = PL2_RW, .accessfn = access_tda, | |
6084 | .type = ARM_CP_NOP }, | |
5dbdc434 PM |
6085 | /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications |
6086 | * Channel but Linux may try to access this register. The 32-bit | |
6087 | * alias is DBGDCCINT. | |
6088 | */ | |
6089 | { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, | |
6090 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
6091 | .access = PL1_RW, .accessfn = access_tda, | |
6092 | .type = ARM_CP_NOP }, | |
50300698 PM |
6093 | }; |
6094 | ||
6095 | static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | |
6096 | /* 64 bit access versions of the (dummy) debug registers */ | |
6097 | { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, | |
6098 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
6099 | { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | |
6100 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
50300698 PM |
6101 | }; |
6102 | ||
60eed086 RH |
6103 | /* Return the exception level to which exceptions should be taken |
6104 | * via SVEAccessTrap. If an exception should be routed through | |
6105 | * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should | |
6106 | * take care of raising that exception. | |
6107 | * C.f. the ARM pseudocode function CheckSVEEnabled. | |
5be5e8ed | 6108 | */ |
ced31551 | 6109 | int sve_exception_el(CPUARMState *env, int el) |
5be5e8ed RH |
6110 | { |
6111 | #ifndef CONFIG_USER_ONLY | |
c2ddb7cf RH |
6112 | uint64_t hcr_el2 = arm_hcr_el2_eff(env); |
6113 | ||
6114 | if (el <= 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { | |
7701cee5 RH |
6115 | /* Check CPACR.ZEN. */ |
6116 | switch (extract32(env->cp15.cpacr_el1, 16, 2)) { | |
6117 | case 1: | |
6118 | if (el != 0) { | |
6119 | break; | |
6120 | } | |
6121 | /* fall through */ | |
6122 | case 0: | |
6123 | case 2: | |
60eed086 | 6124 | /* route_to_el2 */ |
c2ddb7cf | 6125 | return hcr_el2 & HCR_TGE ? 2 : 1; |
5be5e8ed | 6126 | } |
5be5e8ed | 6127 | |
60eed086 | 6128 | /* Check CPACR.FPEN. */ |
7701cee5 RH |
6129 | switch (extract32(env->cp15.cpacr_el1, 20, 2)) { |
6130 | case 1: | |
6131 | if (el != 0) { | |
6132 | break; | |
6133 | } | |
6134 | /* fall through */ | |
6135 | case 0: | |
6136 | case 2: | |
60eed086 | 6137 | return 0; |
5be5e8ed | 6138 | } |
5be5e8ed RH |
6139 | } |
6140 | ||
d5a6fa2d RH |
6141 | /* |
6142 | * CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). | |
60eed086 | 6143 | */ |
d5a6fa2d RH |
6144 | if (el <= 2) { |
6145 | if (hcr_el2 & HCR_E2H) { | |
6146 | /* Check CPTR_EL2.ZEN. */ | |
6147 | switch (extract32(env->cp15.cptr_el[2], 16, 2)) { | |
6148 | case 1: | |
6149 | if (el != 0 || !(hcr_el2 & HCR_TGE)) { | |
6150 | break; | |
6151 | } | |
6152 | /* fall through */ | |
6153 | case 0: | |
6154 | case 2: | |
6155 | return 2; | |
6156 | } | |
6157 | ||
6158 | /* Check CPTR_EL2.FPEN. */ | |
6159 | switch (extract32(env->cp15.cptr_el[2], 20, 2)) { | |
6160 | case 1: | |
6161 | if (el == 2 || !(hcr_el2 & HCR_TGE)) { | |
6162 | break; | |
6163 | } | |
6164 | /* fall through */ | |
6165 | case 0: | |
6166 | case 2: | |
6167 | return 0; | |
6168 | } | |
6169 | } else if (arm_is_el2_enabled(env)) { | |
6170 | if (env->cp15.cptr_el[2] & CPTR_TZ) { | |
6171 | return 2; | |
6172 | } | |
6173 | if (env->cp15.cptr_el[2] & CPTR_TFP) { | |
6174 | return 0; | |
6175 | } | |
60eed086 | 6176 | } |
5be5e8ed RH |
6177 | } |
6178 | ||
60eed086 RH |
6179 | /* CPTR_EL3. Since EZ is negative we must check for EL3. */ |
6180 | if (arm_feature(env, ARM_FEATURE_EL3) | |
6181 | && !(env->cp15.cptr_el[3] & CPTR_EZ)) { | |
5be5e8ed RH |
6182 | return 3; |
6183 | } | |
6184 | #endif | |
6185 | return 0; | |
6186 | } | |
6187 | ||
ce440581 | 6188 | uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) |
0df9142d | 6189 | { |
6e553f2a | 6190 | uint32_t end_len; |
0df9142d | 6191 | |
dc0bc8e7 RH |
6192 | start_len = MIN(start_len, ARM_MAX_VQ - 1); |
6193 | end_len = start_len; | |
6194 | ||
6e553f2a RH |
6195 | if (!test_bit(start_len, cpu->sve_vq_map)) { |
6196 | end_len = find_last_bit(cpu->sve_vq_map, start_len); | |
6197 | assert(end_len < start_len); | |
6198 | } | |
6199 | return end_len; | |
0df9142d AJ |
6200 | } |
6201 | ||
0ab5953b RH |
6202 | /* |
6203 | * Given that SVE is enabled, return the vector length for EL. | |
6204 | */ | |
ced31551 | 6205 | uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) |
0ab5953b | 6206 | { |
2fc0cc0e | 6207 | ARMCPU *cpu = env_archcpu(env); |
0ab5953b RH |
6208 | uint32_t zcr_len = cpu->sve_max_vq - 1; |
6209 | ||
63888fa7 RH |
6210 | if (el <= 1 && |
6211 | (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { | |
0ab5953b RH |
6212 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); |
6213 | } | |
6a02a732 | 6214 | if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) { |
0ab5953b RH |
6215 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); |
6216 | } | |
6a02a732 | 6217 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0ab5953b RH |
6218 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); |
6219 | } | |
0df9142d | 6220 | |
ce440581 | 6221 | return aarch64_sve_zcr_get_valid_len(cpu, zcr_len); |
0ab5953b RH |
6222 | } |
6223 | ||
5be5e8ed RH |
6224 | static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
6225 | uint64_t value) | |
6226 | { | |
0ab5953b RH |
6227 | int cur_el = arm_current_el(env); |
6228 | int old_len = sve_zcr_len_for_el(env, cur_el); | |
6229 | int new_len; | |
6230 | ||
5be5e8ed | 6231 | /* Bits other than [3:0] are RAZ/WI. */ |
7b351d98 | 6232 | QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16); |
5be5e8ed | 6233 | raw_write(env, ri, value & 0xf); |
0ab5953b RH |
6234 | |
6235 | /* | |
6236 | * Because we arrived here, we know both FP and SVE are enabled; | |
6237 | * otherwise we would have trapped access to the ZCR_ELn register. | |
6238 | */ | |
6239 | new_len = sve_zcr_len_for_el(env, cur_el); | |
6240 | if (new_len < old_len) { | |
6241 | aarch64_sve_narrow_vq(env, new_len + 1); | |
6242 | } | |
5be5e8ed RH |
6243 | } |
6244 | ||
6245 | static const ARMCPRegInfo zcr_el1_reginfo = { | |
6246 | .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | |
6247 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 6248 | .access = PL1_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
6249 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), |
6250 | .writefn = zcr_write, .raw_writefn = raw_write | |
6251 | }; | |
6252 | ||
6253 | static const ARMCPRegInfo zcr_el2_reginfo = { | |
6254 | .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | |
6255 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 6256 | .access = PL2_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
6257 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), |
6258 | .writefn = zcr_write, .raw_writefn = raw_write | |
6259 | }; | |
6260 | ||
6261 | static const ARMCPRegInfo zcr_no_el2_reginfo = { | |
6262 | .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | |
6263 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 6264 | .access = PL2_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
6265 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore |
6266 | }; | |
6267 | ||
6268 | static const ARMCPRegInfo zcr_el3_reginfo = { | |
6269 | .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | |
6270 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 6271 | .access = PL3_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
6272 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), |
6273 | .writefn = zcr_write, .raw_writefn = raw_write | |
6274 | }; | |
6275 | ||
9ee98ce8 PM |
6276 | void hw_watchpoint_update(ARMCPU *cpu, int n) |
6277 | { | |
6278 | CPUARMState *env = &cpu->env; | |
6279 | vaddr len = 0; | |
6280 | vaddr wvr = env->cp15.dbgwvr[n]; | |
6281 | uint64_t wcr = env->cp15.dbgwcr[n]; | |
6282 | int mask; | |
6283 | int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; | |
6284 | ||
6285 | if (env->cpu_watchpoint[n]) { | |
6286 | cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); | |
6287 | env->cpu_watchpoint[n] = NULL; | |
6288 | } | |
6289 | ||
8b7a5bbe | 6290 | if (!FIELD_EX64(wcr, DBGWCR, E)) { |
9ee98ce8 PM |
6291 | /* E bit clear : watchpoint disabled */ |
6292 | return; | |
6293 | } | |
6294 | ||
8b7a5bbe | 6295 | switch (FIELD_EX64(wcr, DBGWCR, LSC)) { |
9ee98ce8 PM |
6296 | case 0: |
6297 | /* LSC 00 is reserved and must behave as if the wp is disabled */ | |
6298 | return; | |
6299 | case 1: | |
6300 | flags |= BP_MEM_READ; | |
6301 | break; | |
6302 | case 2: | |
6303 | flags |= BP_MEM_WRITE; | |
6304 | break; | |
6305 | case 3: | |
6306 | flags |= BP_MEM_ACCESS; | |
6307 | break; | |
6308 | } | |
6309 | ||
6310 | /* Attempts to use both MASK and BAS fields simultaneously are | |
6311 | * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, | |
6312 | * thus generating a watchpoint for every byte in the masked region. | |
6313 | */ | |
8b7a5bbe | 6314 | mask = FIELD_EX64(wcr, DBGWCR, MASK); |
9ee98ce8 PM |
6315 | if (mask == 1 || mask == 2) { |
6316 | /* Reserved values of MASK; we must act as if the mask value was | |
6317 | * some non-reserved value, or as if the watchpoint were disabled. | |
6318 | * We choose the latter. | |
6319 | */ | |
6320 | return; | |
6321 | } else if (mask) { | |
6322 | /* Watchpoint covers an aligned area up to 2GB in size */ | |
6323 | len = 1ULL << mask; | |
6324 | /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE | |
6325 | * whether the watchpoint fires when the unmasked bits match; we opt | |
6326 | * to generate the exceptions. | |
6327 | */ | |
6328 | wvr &= ~(len - 1); | |
6329 | } else { | |
6330 | /* Watchpoint covers bytes defined by the byte address select bits */ | |
8b7a5bbe | 6331 | int bas = FIELD_EX64(wcr, DBGWCR, BAS); |
9ee98ce8 PM |
6332 | int basstart; |
6333 | ||
9ee98ce8 PM |
6334 | if (extract64(wvr, 2, 1)) { |
6335 | /* Deprecated case of an only 4-aligned address. BAS[7:4] are | |
6336 | * ignored, and BAS[3:0] define which bytes to watch. | |
6337 | */ | |
6338 | bas &= 0xf; | |
6339 | } | |
ae1111d4 RH |
6340 | |
6341 | if (bas == 0) { | |
6342 | /* This must act as if the watchpoint is disabled */ | |
6343 | return; | |
6344 | } | |
6345 | ||
9ee98ce8 PM |
6346 | /* The BAS bits are supposed to be programmed to indicate a contiguous |
6347 | * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether | |
6348 | * we fire for each byte in the word/doubleword addressed by the WVR. | |
6349 | * We choose to ignore any non-zero bits after the first range of 1s. | |
6350 | */ | |
6351 | basstart = ctz32(bas); | |
6352 | len = cto32(bas >> basstart); | |
6353 | wvr += basstart; | |
6354 | } | |
6355 | ||
6356 | cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, | |
6357 | &env->cpu_watchpoint[n]); | |
6358 | } | |
6359 | ||
6360 | void hw_watchpoint_update_all(ARMCPU *cpu) | |
6361 | { | |
6362 | int i; | |
6363 | CPUARMState *env = &cpu->env; | |
6364 | ||
6365 | /* Completely clear out existing QEMU watchpoints and our array, to | |
6366 | * avoid possible stale entries following migration load. | |
6367 | */ | |
6368 | cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); | |
6369 | memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); | |
6370 | ||
6371 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { | |
6372 | hw_watchpoint_update(cpu, i); | |
6373 | } | |
6374 | } | |
6375 | ||
6376 | static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6377 | uint64_t value) | |
6378 | { | |
2fc0cc0e | 6379 | ARMCPU *cpu = env_archcpu(env); |
9ee98ce8 PM |
6380 | int i = ri->crm; |
6381 | ||
777ab8d8 | 6382 | /* |
9ee98ce8 | 6383 | * Bits [1:0] are RES0. |
777ab8d8 RH |
6384 | * |
6385 | * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA) | |
6386 | * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if | |
6387 | * they contain the value written. It is CONSTRAINED UNPREDICTABLE | |
6388 | * whether the RESS bits are ignored when comparing an address. | |
6389 | * | |
6390 | * Therefore we are allowed to compare the entire register, which lets | |
6391 | * us avoid considering whether or not FEAT_LVA is actually enabled. | |
9ee98ce8 | 6392 | */ |
777ab8d8 | 6393 | value &= ~3ULL; |
9ee98ce8 PM |
6394 | |
6395 | raw_write(env, ri, value); | |
6396 | hw_watchpoint_update(cpu, i); | |
6397 | } | |
6398 | ||
6399 | static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6400 | uint64_t value) | |
6401 | { | |
2fc0cc0e | 6402 | ARMCPU *cpu = env_archcpu(env); |
9ee98ce8 PM |
6403 | int i = ri->crm; |
6404 | ||
6405 | raw_write(env, ri, value); | |
6406 | hw_watchpoint_update(cpu, i); | |
6407 | } | |
6408 | ||
46747d15 PM |
6409 | void hw_breakpoint_update(ARMCPU *cpu, int n) |
6410 | { | |
6411 | CPUARMState *env = &cpu->env; | |
6412 | uint64_t bvr = env->cp15.dbgbvr[n]; | |
6413 | uint64_t bcr = env->cp15.dbgbcr[n]; | |
6414 | vaddr addr; | |
6415 | int bt; | |
6416 | int flags = BP_CPU; | |
6417 | ||
6418 | if (env->cpu_breakpoint[n]) { | |
6419 | cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); | |
6420 | env->cpu_breakpoint[n] = NULL; | |
6421 | } | |
6422 | ||
6423 | if (!extract64(bcr, 0, 1)) { | |
6424 | /* E bit clear : watchpoint disabled */ | |
6425 | return; | |
6426 | } | |
6427 | ||
6428 | bt = extract64(bcr, 20, 4); | |
6429 | ||
6430 | switch (bt) { | |
6431 | case 4: /* unlinked address mismatch (reserved if AArch64) */ | |
6432 | case 5: /* linked address mismatch (reserved if AArch64) */ | |
6433 | qemu_log_mask(LOG_UNIMP, | |
0221c8fd | 6434 | "arm: address mismatch breakpoint types not implemented\n"); |
46747d15 PM |
6435 | return; |
6436 | case 0: /* unlinked address match */ | |
6437 | case 1: /* linked address match */ | |
6438 | { | |
777ab8d8 RH |
6439 | /* |
6440 | * Bits [1:0] are RES0. | |
6441 | * | |
6442 | * It is IMPLEMENTATION DEFINED whether bits [63:49] | |
6443 | * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit | |
6444 | * of the VA field ([48] or [52] for FEAT_LVA), or whether the | |
6445 | * value is read as written. It is CONSTRAINED UNPREDICTABLE | |
6446 | * whether the RESS bits are ignored when comparing an address. | |
6447 | * Therefore we are allowed to compare the entire register, which | |
6448 | * lets us avoid considering whether FEAT_LVA is actually enabled. | |
6449 | * | |
6450 | * The BAS field is used to allow setting breakpoints on 16-bit | |
6451 | * wide instructions; it is CONSTRAINED UNPREDICTABLE whether | |
46747d15 PM |
6452 | * a bp will fire if the addresses covered by the bp and the addresses |
6453 | * covered by the insn overlap but the insn doesn't start at the | |
6454 | * start of the bp address range. We choose to require the insn and | |
6455 | * the bp to have the same address. The constraints on writing to | |
6456 | * BAS enforced in dbgbcr_write mean we have only four cases: | |
6457 | * 0b0000 => no breakpoint | |
6458 | * 0b0011 => breakpoint on addr | |
6459 | * 0b1100 => breakpoint on addr + 2 | |
6460 | * 0b1111 => breakpoint on addr | |
6461 | * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). | |
6462 | */ | |
6463 | int bas = extract64(bcr, 5, 4); | |
777ab8d8 | 6464 | addr = bvr & ~3ULL; |
46747d15 PM |
6465 | if (bas == 0) { |
6466 | return; | |
6467 | } | |
6468 | if (bas == 0xc) { | |
6469 | addr += 2; | |
6470 | } | |
6471 | break; | |
6472 | } | |
6473 | case 2: /* unlinked context ID match */ | |
6474 | case 8: /* unlinked VMID match (reserved if no EL2) */ | |
6475 | case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ | |
6476 | qemu_log_mask(LOG_UNIMP, | |
0221c8fd | 6477 | "arm: unlinked context breakpoint types not implemented\n"); |
46747d15 PM |
6478 | return; |
6479 | case 9: /* linked VMID match (reserved if no EL2) */ | |
6480 | case 11: /* linked context ID and VMID match (reserved if no EL2) */ | |
6481 | case 3: /* linked context ID match */ | |
6482 | default: | |
6483 | /* We must generate no events for Linked context matches (unless | |
6484 | * they are linked to by some other bp/wp, which is handled in | |
6485 | * updates for the linking bp/wp). We choose to also generate no events | |
6486 | * for reserved values. | |
6487 | */ | |
6488 | return; | |
6489 | } | |
6490 | ||
6491 | cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); | |
6492 | } | |
6493 | ||
6494 | void hw_breakpoint_update_all(ARMCPU *cpu) | |
6495 | { | |
6496 | int i; | |
6497 | CPUARMState *env = &cpu->env; | |
6498 | ||
6499 | /* Completely clear out existing QEMU breakpoints and our array, to | |
6500 | * avoid possible stale entries following migration load. | |
6501 | */ | |
6502 | cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); | |
6503 | memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); | |
6504 | ||
6505 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { | |
6506 | hw_breakpoint_update(cpu, i); | |
6507 | } | |
6508 | } | |
6509 | ||
6510 | static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6511 | uint64_t value) | |
6512 | { | |
2fc0cc0e | 6513 | ARMCPU *cpu = env_archcpu(env); |
46747d15 PM |
6514 | int i = ri->crm; |
6515 | ||
6516 | raw_write(env, ri, value); | |
6517 | hw_breakpoint_update(cpu, i); | |
6518 | } | |
6519 | ||
6520 | static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6521 | uint64_t value) | |
6522 | { | |
2fc0cc0e | 6523 | ARMCPU *cpu = env_archcpu(env); |
46747d15 PM |
6524 | int i = ri->crm; |
6525 | ||
6526 | /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only | |
6527 | * copy of BAS[0]. | |
6528 | */ | |
6529 | value = deposit64(value, 6, 1, extract64(value, 5, 1)); | |
6530 | value = deposit64(value, 8, 1, extract64(value, 7, 1)); | |
6531 | ||
6532 | raw_write(env, ri, value); | |
6533 | hw_breakpoint_update(cpu, i); | |
6534 | } | |
6535 | ||
50300698 | 6536 | static void define_debug_regs(ARMCPU *cpu) |
0b45451e | 6537 | { |
50300698 PM |
6538 | /* Define v7 and v8 architectural debug registers. |
6539 | * These are just dummy implementations for now. | |
0b45451e PM |
6540 | */ |
6541 | int i; | |
3ff6fc91 | 6542 | int wrps, brps, ctx_cmps; |
54a78718 RH |
6543 | |
6544 | /* | |
6545 | * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot | |
6546 | * use AArch32. Given that bit 15 is RES1, if the value is 0 then | |
6547 | * the register must not exist for this cpu. | |
6548 | */ | |
6549 | if (cpu->isar.dbgdidr != 0) { | |
6550 | ARMCPRegInfo dbgdidr = { | |
6551 | .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, | |
6552 | .opc1 = 0, .opc2 = 0, | |
6553 | .access = PL0_R, .accessfn = access_tda, | |
6554 | .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr, | |
6555 | }; | |
6556 | define_one_arm_cp_reg(cpu, &dbgdidr); | |
6557 | } | |
48eb3ae6 | 6558 | |
3ff6fc91 | 6559 | /* Note that all these register fields hold "number of Xs minus 1". */ |
88ce6c6e PM |
6560 | brps = arm_num_brps(cpu); |
6561 | wrps = arm_num_wrps(cpu); | |
6562 | ctx_cmps = arm_num_ctx_cmps(cpu); | |
3ff6fc91 PM |
6563 | |
6564 | assert(ctx_cmps <= brps); | |
48eb3ae6 | 6565 | |
50300698 PM |
6566 | define_arm_cp_regs(cpu, debug_cp_reginfo); |
6567 | ||
6568 | if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { | |
6569 | define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); | |
6570 | } | |
6571 | ||
88ce6c6e | 6572 | for (i = 0; i < brps; i++) { |
0b45451e | 6573 | ARMCPRegInfo dbgregs[] = { |
10aae104 PM |
6574 | { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH, |
6575 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, | |
d6c8cf81 | 6576 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
6577 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), |
6578 | .writefn = dbgbvr_write, .raw_writefn = raw_write | |
6579 | }, | |
10aae104 PM |
6580 | { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH, |
6581 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, | |
d6c8cf81 | 6582 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
6583 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), |
6584 | .writefn = dbgbcr_write, .raw_writefn = raw_write | |
6585 | }, | |
48eb3ae6 PM |
6586 | }; |
6587 | define_arm_cp_regs(cpu, dbgregs); | |
6588 | } | |
6589 | ||
88ce6c6e | 6590 | for (i = 0; i < wrps; i++) { |
48eb3ae6 | 6591 | ARMCPRegInfo dbgregs[] = { |
10aae104 PM |
6592 | { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH, |
6593 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, | |
d6c8cf81 | 6594 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
6595 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), |
6596 | .writefn = dbgwvr_write, .raw_writefn = raw_write | |
6597 | }, | |
10aae104 PM |
6598 | { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH, |
6599 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, | |
d6c8cf81 | 6600 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
6601 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), |
6602 | .writefn = dbgwcr_write, .raw_writefn = raw_write | |
6603 | }, | |
0b45451e PM |
6604 | }; |
6605 | define_arm_cp_regs(cpu, dbgregs); | |
6606 | } | |
6607 | } | |
6608 | ||
24183fb6 PM |
6609 | static void define_pmu_regs(ARMCPU *cpu) |
6610 | { | |
6611 | /* | |
6612 | * v7 performance monitor control register: same implementor | |
6613 | * field as main ID register, and we implement four counters in | |
6614 | * addition to the cycle count register. | |
6615 | */ | |
21c2dd77 | 6616 | unsigned int i, pmcrn = PMCR_NUM_COUNTERS; |
24183fb6 PM |
6617 | ARMCPRegInfo pmcr = { |
6618 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | |
6619 | .access = PL0_RW, | |
6620 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6621 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), | |
6622 | .accessfn = pmreg_access, .writefn = pmcr_write, | |
6623 | .raw_writefn = raw_write, | |
6624 | }; | |
6625 | ARMCPRegInfo pmcr64 = { | |
6626 | .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, | |
6627 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, | |
6628 | .access = PL0_RW, .accessfn = pmreg_access, | |
6629 | .type = ARM_CP_IO, | |
6630 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), | |
21c2dd77 PM |
6631 | .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) | |
6632 | PMCRLC, | |
24183fb6 PM |
6633 | .writefn = pmcr_write, .raw_writefn = raw_write, |
6634 | }; | |
6635 | define_one_arm_cp_reg(cpu, &pmcr); | |
6636 | define_one_arm_cp_reg(cpu, &pmcr64); | |
6637 | for (i = 0; i < pmcrn; i++) { | |
6638 | char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i); | |
6639 | char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i); | |
6640 | char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i); | |
6641 | char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i); | |
6642 | ARMCPRegInfo pmev_regs[] = { | |
6643 | { .name = pmevcntr_name, .cp = 15, .crn = 14, | |
6644 | .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, | |
6645 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6646 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, | |
6647 | .accessfn = pmreg_access }, | |
6648 | { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64, | |
6649 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)), | |
6650 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, | |
6651 | .type = ARM_CP_IO, | |
6652 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, | |
6653 | .raw_readfn = pmevcntr_rawread, | |
6654 | .raw_writefn = pmevcntr_rawwrite }, | |
6655 | { .name = pmevtyper_name, .cp = 15, .crn = 14, | |
6656 | .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, | |
6657 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6658 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | |
6659 | .accessfn = pmreg_access }, | |
6660 | { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64, | |
6661 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)), | |
6662 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, | |
6663 | .type = ARM_CP_IO, | |
6664 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | |
6665 | .raw_writefn = pmevtyper_rawwrite }, | |
24183fb6 PM |
6666 | }; |
6667 | define_arm_cp_regs(cpu, pmev_regs); | |
6668 | g_free(pmevcntr_name); | |
6669 | g_free(pmevcntr_el0_name); | |
6670 | g_free(pmevtyper_name); | |
6671 | g_free(pmevtyper_el0_name); | |
6672 | } | |
a6179538 | 6673 | if (cpu_isar_feature(aa32_pmu_8_1, cpu)) { |
24183fb6 PM |
6674 | ARMCPRegInfo v81_pmu_regs[] = { |
6675 | { .name = "PMCEID2", .state = ARM_CP_STATE_AA32, | |
6676 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4, | |
6677 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6678 | .resetvalue = extract64(cpu->pmceid0, 32, 32) }, | |
6679 | { .name = "PMCEID3", .state = ARM_CP_STATE_AA32, | |
6680 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5, | |
6681 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6682 | .resetvalue = extract64(cpu->pmceid1, 32, 32) }, | |
24183fb6 PM |
6683 | }; |
6684 | define_arm_cp_regs(cpu, v81_pmu_regs); | |
6685 | } | |
15dd1ebd PM |
6686 | if (cpu_isar_feature(any_pmu_8_4, cpu)) { |
6687 | static const ARMCPRegInfo v84_pmmir = { | |
6688 | .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH, | |
6689 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6, | |
6690 | .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6691 | .resetvalue = 0 | |
6692 | }; | |
6693 | define_one_arm_cp_reg(cpu, &v84_pmmir); | |
6694 | } | |
24183fb6 PM |
6695 | } |
6696 | ||
96a8b92e PM |
6697 | /* We don't know until after realize whether there's a GICv3 |
6698 | * attached, and that is what registers the gicv3 sysregs. | |
6699 | * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1 | |
6700 | * at runtime. | |
6701 | */ | |
6702 | static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
6703 | { | |
2fc0cc0e | 6704 | ARMCPU *cpu = env_archcpu(env); |
8a130a7b | 6705 | uint64_t pfr1 = cpu->isar.id_pfr1; |
96a8b92e PM |
6706 | |
6707 | if (env->gicv3state) { | |
6708 | pfr1 |= 1 << 28; | |
6709 | } | |
6710 | return pfr1; | |
6711 | } | |
6712 | ||
976b99b6 | 6713 | #ifndef CONFIG_USER_ONLY |
96a8b92e PM |
6714 | static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) |
6715 | { | |
2fc0cc0e | 6716 | ARMCPU *cpu = env_archcpu(env); |
47576b94 | 6717 | uint64_t pfr0 = cpu->isar.id_aa64pfr0; |
96a8b92e PM |
6718 | |
6719 | if (env->gicv3state) { | |
6720 | pfr0 |= 1 << 24; | |
6721 | } | |
6722 | return pfr0; | |
6723 | } | |
976b99b6 | 6724 | #endif |
96a8b92e | 6725 | |
2d7137c1 | 6726 | /* Shared logic between LORID and the rest of the LOR* registers. |
9bd268ba | 6727 | * Secure state exclusion has already been dealt with. |
2d7137c1 | 6728 | */ |
9bd268ba RDC |
6729 | static CPAccessResult access_lor_ns(CPUARMState *env, |
6730 | const ARMCPRegInfo *ri, bool isread) | |
2d7137c1 RH |
6731 | { |
6732 | int el = arm_current_el(env); | |
6733 | ||
6734 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) { | |
6735 | return CP_ACCESS_TRAP_EL2; | |
6736 | } | |
6737 | if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { | |
6738 | return CP_ACCESS_TRAP_EL3; | |
6739 | } | |
6740 | return CP_ACCESS_OK; | |
6741 | } | |
6742 | ||
2d7137c1 RH |
6743 | static CPAccessResult access_lor_other(CPUARMState *env, |
6744 | const ARMCPRegInfo *ri, bool isread) | |
6745 | { | |
6746 | if (arm_is_secure_below_el3(env)) { | |
6747 | /* Access denied in secure mode. */ | |
6748 | return CP_ACCESS_TRAP; | |
6749 | } | |
9bd268ba | 6750 | return access_lor_ns(env, ri, isread); |
2d7137c1 RH |
6751 | } |
6752 | ||
d8564ee4 RH |
6753 | /* |
6754 | * A trivial implementation of ARMv8.1-LOR leaves all of these | |
6755 | * registers fixed at 0, which indicates that there are zero | |
6756 | * supported Limited Ordering regions. | |
6757 | */ | |
6758 | static const ARMCPRegInfo lor_reginfo[] = { | |
6759 | { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, | |
6760 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, | |
6761 | .access = PL1_RW, .accessfn = access_lor_other, | |
6762 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6763 | { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, | |
6764 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, | |
6765 | .access = PL1_RW, .accessfn = access_lor_other, | |
6766 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6767 | { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, | |
6768 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, | |
6769 | .access = PL1_RW, .accessfn = access_lor_other, | |
6770 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6771 | { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, | |
6772 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, | |
6773 | .access = PL1_RW, .accessfn = access_lor_other, | |
6774 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6775 | { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, | |
6776 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, | |
9bd268ba | 6777 | .access = PL1_R, .accessfn = access_lor_ns, |
d8564ee4 | 6778 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
d8564ee4 RH |
6779 | }; |
6780 | ||
967aa94f RH |
6781 | #ifdef TARGET_AARCH64 |
6782 | static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, | |
6783 | bool isread) | |
6784 | { | |
6785 | int el = arm_current_el(env); | |
6786 | ||
6787 | if (el < 2 && | |
6788 | arm_feature(env, ARM_FEATURE_EL2) && | |
6789 | !(arm_hcr_el2_eff(env) & HCR_APK)) { | |
6790 | return CP_ACCESS_TRAP_EL2; | |
6791 | } | |
6792 | if (el < 3 && | |
6793 | arm_feature(env, ARM_FEATURE_EL3) && | |
6794 | !(env->cp15.scr_el3 & SCR_APK)) { | |
6795 | return CP_ACCESS_TRAP_EL3; | |
6796 | } | |
6797 | return CP_ACCESS_OK; | |
6798 | } | |
6799 | ||
6800 | static const ARMCPRegInfo pauth_reginfo[] = { | |
6801 | { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64, | |
6802 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0, | |
6803 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6804 | .fieldoffset = offsetof(CPUARMState, keys.apda.lo) }, |
967aa94f RH |
6805 | { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6806 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1, | |
6807 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6808 | .fieldoffset = offsetof(CPUARMState, keys.apda.hi) }, |
967aa94f RH |
6809 | { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
6810 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2, | |
6811 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6812 | .fieldoffset = offsetof(CPUARMState, keys.apdb.lo) }, |
967aa94f RH |
6813 | { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6814 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3, | |
6815 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6816 | .fieldoffset = offsetof(CPUARMState, keys.apdb.hi) }, |
967aa94f RH |
6817 | { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
6818 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0, | |
6819 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6820 | .fieldoffset = offsetof(CPUARMState, keys.apga.lo) }, |
967aa94f RH |
6821 | { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6822 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1, | |
6823 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6824 | .fieldoffset = offsetof(CPUARMState, keys.apga.hi) }, |
967aa94f RH |
6825 | { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
6826 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0, | |
6827 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6828 | .fieldoffset = offsetof(CPUARMState, keys.apia.lo) }, |
967aa94f RH |
6829 | { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6830 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1, | |
6831 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6832 | .fieldoffset = offsetof(CPUARMState, keys.apia.hi) }, |
967aa94f RH |
6833 | { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
6834 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2, | |
6835 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6836 | .fieldoffset = offsetof(CPUARMState, keys.apib.lo) }, |
967aa94f RH |
6837 | { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6838 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3, | |
6839 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6840 | .fieldoffset = offsetof(CPUARMState, keys.apib.hi) }, |
967aa94f | 6841 | }; |
de390645 | 6842 | |
84940ed8 RC |
6843 | static const ARMCPRegInfo tlbirange_reginfo[] = { |
6844 | { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64, | |
6845 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1, | |
6846 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6847 | .writefn = tlbi_aa64_rvae1is_write }, | |
6848 | { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64, | |
6849 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3, | |
6850 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6851 | .writefn = tlbi_aa64_rvae1is_write }, | |
6852 | { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64, | |
6853 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5, | |
6854 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6855 | .writefn = tlbi_aa64_rvae1is_write }, | |
6856 | { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64, | |
6857 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7, | |
6858 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6859 | .writefn = tlbi_aa64_rvae1is_write }, | |
6860 | { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64, | |
6861 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, | |
6862 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6863 | .writefn = tlbi_aa64_rvae1is_write }, | |
6864 | { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64, | |
6865 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3, | |
6866 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6867 | .writefn = tlbi_aa64_rvae1is_write }, | |
6868 | { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64, | |
6869 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5, | |
6870 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6871 | .writefn = tlbi_aa64_rvae1is_write }, | |
6872 | { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64, | |
6873 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7, | |
6874 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6875 | .writefn = tlbi_aa64_rvae1is_write }, | |
6876 | { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64, | |
6877 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, | |
6878 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6879 | .writefn = tlbi_aa64_rvae1_write }, | |
6880 | { .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64, | |
6881 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3, | |
6882 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6883 | .writefn = tlbi_aa64_rvae1_write }, | |
6884 | { .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64, | |
6885 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5, | |
6886 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6887 | .writefn = tlbi_aa64_rvae1_write }, | |
6888 | { .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64, | |
6889 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7, | |
6890 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6891 | .writefn = tlbi_aa64_rvae1_write }, | |
6892 | { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64, | |
6893 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2, | |
6894 | .access = PL2_W, .type = ARM_CP_NOP }, | |
6895 | { .name = "TLBI_RIPAS2LE1IS", .state = ARM_CP_STATE_AA64, | |
6896 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 6, | |
6897 | .access = PL2_W, .type = ARM_CP_NOP }, | |
6898 | { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64, | |
6899 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1, | |
6900 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
6901 | .writefn = tlbi_aa64_rvae2is_write }, | |
6902 | { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64, | |
6903 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5, | |
6904 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
6905 | .writefn = tlbi_aa64_rvae2is_write }, | |
6906 | { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64, | |
6907 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2, | |
6908 | .access = PL2_W, .type = ARM_CP_NOP }, | |
6909 | { .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64, | |
6910 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 6, | |
6911 | .access = PL2_W, .type = ARM_CP_NOP }, | |
6912 | { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64, | |
6913 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1, | |
6914 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
6915 | .writefn = tlbi_aa64_rvae2is_write }, | |
6916 | { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64, | |
6917 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5, | |
6918 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
6919 | .writefn = tlbi_aa64_rvae2is_write }, | |
6920 | { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64, | |
6921 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1, | |
6922 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
6923 | .writefn = tlbi_aa64_rvae2_write }, | |
6924 | { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64, | |
6925 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5, | |
6926 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
6927 | .writefn = tlbi_aa64_rvae2_write }, | |
6928 | { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64, | |
6929 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1, | |
6930 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6931 | .writefn = tlbi_aa64_rvae3is_write }, | |
6932 | { .name = "TLBI_RVALE3IS", .state = ARM_CP_STATE_AA64, | |
6933 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 5, | |
6934 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6935 | .writefn = tlbi_aa64_rvae3is_write }, | |
6936 | { .name = "TLBI_RVAE3OS", .state = ARM_CP_STATE_AA64, | |
6937 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 1, | |
6938 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6939 | .writefn = tlbi_aa64_rvae3is_write }, | |
6940 | { .name = "TLBI_RVALE3OS", .state = ARM_CP_STATE_AA64, | |
6941 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 5, | |
6942 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6943 | .writefn = tlbi_aa64_rvae3is_write }, | |
6944 | { .name = "TLBI_RVAE3", .state = ARM_CP_STATE_AA64, | |
6945 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 1, | |
6946 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6947 | .writefn = tlbi_aa64_rvae3_write }, | |
6948 | { .name = "TLBI_RVALE3", .state = ARM_CP_STATE_AA64, | |
6949 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5, | |
6950 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6951 | .writefn = tlbi_aa64_rvae3_write }, | |
84940ed8 RC |
6952 | }; |
6953 | ||
7113d618 RC |
6954 | static const ARMCPRegInfo tlbios_reginfo[] = { |
6955 | { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64, | |
6956 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0, | |
6957 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6958 | .writefn = tlbi_aa64_vmalle1is_write }, | |
b7469ef9 IH |
6959 | { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64, |
6960 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1, | |
6961 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6962 | .writefn = tlbi_aa64_vae1is_write }, | |
7113d618 RC |
6963 | { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64, |
6964 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2, | |
6965 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6966 | .writefn = tlbi_aa64_vmalle1is_write }, | |
b7469ef9 IH |
6967 | { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64, |
6968 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3, | |
6969 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6970 | .writefn = tlbi_aa64_vae1is_write }, | |
6971 | { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64, | |
6972 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5, | |
6973 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6974 | .writefn = tlbi_aa64_vae1is_write }, | |
6975 | { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64, | |
6976 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7, | |
6977 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6978 | .writefn = tlbi_aa64_vae1is_write }, | |
7113d618 RC |
6979 | { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64, |
6980 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0, | |
6981 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
6982 | .writefn = tlbi_aa64_alle2is_write }, | |
b7469ef9 IH |
6983 | { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64, |
6984 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1, | |
6985 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
6986 | .writefn = tlbi_aa64_vae2is_write }, | |
7113d618 RC |
6987 | { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64, |
6988 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4, | |
6989 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
6990 | .writefn = tlbi_aa64_alle1is_write }, | |
b7469ef9 IH |
6991 | { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64, |
6992 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5, | |
6993 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
6994 | .writefn = tlbi_aa64_vae2is_write }, | |
7113d618 RC |
6995 | { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64, |
6996 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6, | |
6997 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
6998 | .writefn = tlbi_aa64_alle1is_write }, | |
6999 | { .name = "TLBI_IPAS2E1OS", .state = ARM_CP_STATE_AA64, | |
7000 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 0, | |
7001 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7002 | { .name = "TLBI_RIPAS2E1OS", .state = ARM_CP_STATE_AA64, | |
7003 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 3, | |
7004 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7005 | { .name = "TLBI_IPAS2LE1OS", .state = ARM_CP_STATE_AA64, | |
7006 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 4, | |
7007 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7008 | { .name = "TLBI_RIPAS2LE1OS", .state = ARM_CP_STATE_AA64, | |
7009 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 7, | |
7010 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7011 | { .name = "TLBI_ALLE3OS", .state = ARM_CP_STATE_AA64, | |
7012 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 0, | |
7013 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7014 | .writefn = tlbi_aa64_alle3is_write }, | |
b7469ef9 IH |
7015 | { .name = "TLBI_VAE3OS", .state = ARM_CP_STATE_AA64, |
7016 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 1, | |
7017 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7018 | .writefn = tlbi_aa64_vae3is_write }, | |
7019 | { .name = "TLBI_VALE3OS", .state = ARM_CP_STATE_AA64, | |
7020 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5, | |
7021 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7022 | .writefn = tlbi_aa64_vae3is_write }, | |
7113d618 RC |
7023 | }; |
7024 | ||
de390645 RH |
7025 | static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) |
7026 | { | |
7027 | Error *err = NULL; | |
7028 | uint64_t ret; | |
7029 | ||
7030 | /* Success sets NZCV = 0000. */ | |
7031 | env->NF = env->CF = env->VF = 0, env->ZF = 1; | |
7032 | ||
7033 | if (qemu_guest_getrandom(&ret, sizeof(ret), &err) < 0) { | |
7034 | /* | |
7035 | * ??? Failed, for unknown reasons in the crypto subsystem. | |
7036 | * The best we can do is log the reason and return the | |
7037 | * timed-out indication to the guest. There is no reason | |
7038 | * we know to expect this failure to be transitory, so the | |
7039 | * guest may well hang retrying the operation. | |
7040 | */ | |
7041 | qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", | |
7042 | ri->name, error_get_pretty(err)); | |
7043 | error_free(err); | |
7044 | ||
7045 | env->ZF = 0; /* NZCF = 0100 */ | |
7046 | return 0; | |
7047 | } | |
7048 | return ret; | |
7049 | } | |
7050 | ||
7051 | /* We do not support re-seeding, so the two registers operate the same. */ | |
7052 | static const ARMCPRegInfo rndr_reginfo[] = { | |
7053 | { .name = "RNDR", .state = ARM_CP_STATE_AA64, | |
7054 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | |
7055 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 0, | |
7056 | .access = PL0_R, .readfn = rndr_readfn }, | |
7057 | { .name = "RNDRRS", .state = ARM_CP_STATE_AA64, | |
7058 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | |
7059 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1, | |
7060 | .access = PL0_R, .readfn = rndr_readfn }, | |
de390645 | 7061 | }; |
0d57b499 BM |
7062 | |
7063 | #ifndef CONFIG_USER_ONLY | |
7064 | static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, | |
7065 | uint64_t value) | |
7066 | { | |
7067 | ARMCPU *cpu = env_archcpu(env); | |
7068 | /* CTR_EL0 System register -> DminLine, bits [19:16] */ | |
7069 | uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF); | |
7070 | uint64_t vaddr_in = (uint64_t) value; | |
7071 | uint64_t vaddr = vaddr_in & ~(dline_size - 1); | |
7072 | void *haddr; | |
7073 | int mem_idx = cpu_mmu_index(env, false); | |
7074 | ||
7075 | /* This won't be crossing page boundaries */ | |
7076 | haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC()); | |
7077 | if (haddr) { | |
7078 | ||
7079 | ram_addr_t offset; | |
7080 | MemoryRegion *mr; | |
7081 | ||
7082 | /* RCU lock is already being held */ | |
7083 | mr = memory_region_from_host(haddr, &offset); | |
7084 | ||
7085 | if (mr) { | |
4dfe59d1 | 7086 | memory_region_writeback(mr, offset, dline_size); |
0d57b499 BM |
7087 | } |
7088 | } | |
7089 | } | |
7090 | ||
7091 | static const ARMCPRegInfo dcpop_reg[] = { | |
7092 | { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64, | |
7093 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1, | |
7094 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | |
1bed4d2e | 7095 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, |
0d57b499 BM |
7096 | }; |
7097 | ||
7098 | static const ARMCPRegInfo dcpodp_reg[] = { | |
7099 | { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64, | |
7100 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1, | |
7101 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | |
1bed4d2e | 7102 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, |
0d57b499 BM |
7103 | }; |
7104 | #endif /*CONFIG_USER_ONLY*/ | |
7105 | ||
4b779ceb RH |
7106 | static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInfo *ri, |
7107 | bool isread) | |
7108 | { | |
7109 | if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID5)) { | |
7110 | return CP_ACCESS_TRAP_EL2; | |
7111 | } | |
7112 | ||
7113 | return CP_ACCESS_OK; | |
7114 | } | |
7115 | ||
7116 | static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri, | |
7117 | bool isread) | |
7118 | { | |
7119 | int el = arm_current_el(env); | |
7120 | ||
0da067f2 | 7121 | if (el < 2 && arm_is_el2_enabled(env)) { |
4301acd7 RH |
7122 | uint64_t hcr = arm_hcr_el2_eff(env); |
7123 | if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { | |
7124 | return CP_ACCESS_TRAP_EL2; | |
7125 | } | |
4b779ceb RH |
7126 | } |
7127 | if (el < 3 && | |
7128 | arm_feature(env, ARM_FEATURE_EL3) && | |
7129 | !(env->cp15.scr_el3 & SCR_ATA)) { | |
7130 | return CP_ACCESS_TRAP_EL3; | |
7131 | } | |
7132 | return CP_ACCESS_OK; | |
7133 | } | |
7134 | ||
7135 | static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
7136 | { | |
7137 | return env->pstate & PSTATE_TCO; | |
7138 | } | |
7139 | ||
7140 | static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
7141 | { | |
7142 | env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); | |
7143 | } | |
7144 | ||
7145 | static const ARMCPRegInfo mte_reginfo[] = { | |
7146 | { .name = "TFSRE0_EL1", .state = ARM_CP_STATE_AA64, | |
7147 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 1, | |
7148 | .access = PL1_RW, .accessfn = access_mte, | |
7149 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) }, | |
7150 | { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64, | |
7151 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 0, | |
7152 | .access = PL1_RW, .accessfn = access_mte, | |
7153 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) }, | |
7154 | { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64, | |
7155 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 6, .opc2 = 0, | |
7156 | .access = PL2_RW, .accessfn = access_mte, | |
7157 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) }, | |
7158 | { .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64, | |
7159 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 6, .opc2 = 0, | |
7160 | .access = PL3_RW, | |
7161 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) }, | |
7162 | { .name = "RGSR_EL1", .state = ARM_CP_STATE_AA64, | |
7163 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5, | |
7164 | .access = PL1_RW, .accessfn = access_mte, | |
7165 | .fieldoffset = offsetof(CPUARMState, cp15.rgsr_el1) }, | |
7166 | { .name = "GCR_EL1", .state = ARM_CP_STATE_AA64, | |
7167 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6, | |
7168 | .access = PL1_RW, .accessfn = access_mte, | |
7169 | .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, | |
7170 | { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, | |
7171 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, | |
7172 | .access = PL1_R, .accessfn = access_aa64_tid5, | |
7173 | .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, | |
7174 | { .name = "TCO", .state = ARM_CP_STATE_AA64, | |
7175 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | |
7176 | .type = ARM_CP_NO_RAW, | |
7177 | .access = PL0_RW, .readfn = tco_read, .writefn = tco_write }, | |
5463df16 RH |
7178 | { .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64, |
7179 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3, | |
7180 | .type = ARM_CP_NOP, .access = PL1_W, | |
7181 | .accessfn = aa64_cacheop_poc_access }, | |
7182 | { .name = "DC_IGSW", .state = ARM_CP_STATE_AA64, | |
7183 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4, | |
7184 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | |
7185 | { .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64, | |
7186 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5, | |
7187 | .type = ARM_CP_NOP, .access = PL1_W, | |
7188 | .accessfn = aa64_cacheop_poc_access }, | |
7189 | { .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64, | |
7190 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6, | |
7191 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | |
7192 | { .name = "DC_CGSW", .state = ARM_CP_STATE_AA64, | |
7193 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4, | |
7194 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | |
7195 | { .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64, | |
7196 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6, | |
7197 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | |
7198 | { .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64, | |
7199 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4, | |
7200 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | |
7201 | { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64, | |
7202 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6, | |
7203 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | |
4b779ceb RH |
7204 | }; |
7205 | ||
7206 | static const ARMCPRegInfo mte_tco_ro_reginfo[] = { | |
7207 | { .name = "TCO", .state = ARM_CP_STATE_AA64, | |
7208 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | |
7209 | .type = ARM_CP_CONST, .access = PL0_RW, }, | |
4b779ceb | 7210 | }; |
5463df16 RH |
7211 | |
7212 | static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | |
7213 | { .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64, | |
7214 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3, | |
7215 | .type = ARM_CP_NOP, .access = PL0_W, | |
7216 | .accessfn = aa64_cacheop_poc_access }, | |
7217 | { .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64, | |
7218 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5, | |
7219 | .type = ARM_CP_NOP, .access = PL0_W, | |
7220 | .accessfn = aa64_cacheop_poc_access }, | |
7221 | { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64, | |
7222 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3, | |
7223 | .type = ARM_CP_NOP, .access = PL0_W, | |
7224 | .accessfn = aa64_cacheop_poc_access }, | |
7225 | { .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64, | |
7226 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5, | |
7227 | .type = ARM_CP_NOP, .access = PL0_W, | |
7228 | .accessfn = aa64_cacheop_poc_access }, | |
7229 | { .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64, | |
7230 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3, | |
7231 | .type = ARM_CP_NOP, .access = PL0_W, | |
7232 | .accessfn = aa64_cacheop_poc_access }, | |
7233 | { .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64, | |
7234 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5, | |
7235 | .type = ARM_CP_NOP, .access = PL0_W, | |
7236 | .accessfn = aa64_cacheop_poc_access }, | |
7237 | { .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64, | |
7238 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3, | |
7239 | .type = ARM_CP_NOP, .access = PL0_W, | |
7240 | .accessfn = aa64_cacheop_poc_access }, | |
7241 | { .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64, | |
7242 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, | |
7243 | .type = ARM_CP_NOP, .access = PL0_W, | |
7244 | .accessfn = aa64_cacheop_poc_access }, | |
eb821168 RH |
7245 | { .name = "DC_GVA", .state = ARM_CP_STATE_AA64, |
7246 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3, | |
7247 | .access = PL0_W, .type = ARM_CP_DC_GVA, | |
7248 | #ifndef CONFIG_USER_ONLY | |
7249 | /* Avoid overhead of an access check that always passes in user-mode */ | |
7250 | .accessfn = aa64_zva_access, | |
7251 | #endif | |
7252 | }, | |
7253 | { .name = "DC_GZVA", .state = ARM_CP_STATE_AA64, | |
7254 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 4, | |
7255 | .access = PL0_W, .type = ARM_CP_DC_GZVA, | |
7256 | #ifndef CONFIG_USER_ONLY | |
7257 | /* Avoid overhead of an access check that always passes in user-mode */ | |
7258 | .accessfn = aa64_zva_access, | |
7259 | #endif | |
7260 | }, | |
5463df16 RH |
7261 | }; |
7262 | ||
967aa94f RH |
7263 | #endif |
7264 | ||
cb570bd3 RH |
7265 | static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, |
7266 | bool isread) | |
7267 | { | |
7268 | int el = arm_current_el(env); | |
7269 | ||
7270 | if (el == 0) { | |
7271 | uint64_t sctlr = arm_sctlr(env, el); | |
7272 | if (!(sctlr & SCTLR_EnRCTX)) { | |
7273 | return CP_ACCESS_TRAP; | |
7274 | } | |
7275 | } else if (el == 1) { | |
7276 | uint64_t hcr = arm_hcr_el2_eff(env); | |
7277 | if (hcr & HCR_NV) { | |
7278 | return CP_ACCESS_TRAP_EL2; | |
7279 | } | |
7280 | } | |
7281 | return CP_ACCESS_OK; | |
7282 | } | |
7283 | ||
7284 | static const ARMCPRegInfo predinv_reginfo[] = { | |
7285 | { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64, | |
7286 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4, | |
7287 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
7288 | { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64, | |
7289 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5, | |
7290 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
7291 | { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64, | |
7292 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7, | |
7293 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
7294 | /* | |
7295 | * Note the AArch32 opcodes have a different OPC1. | |
7296 | */ | |
7297 | { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32, | |
7298 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4, | |
7299 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
7300 | { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32, | |
7301 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5, | |
7302 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
7303 | { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32, | |
7304 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7, | |
7305 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
cb570bd3 RH |
7306 | }; |
7307 | ||
957e6155 PM |
7308 | static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri) |
7309 | { | |
7310 | /* Read the high 32 bits of the current CCSIDR */ | |
7311 | return extract64(ccsidr_read(env, ri), 32, 32); | |
7312 | } | |
7313 | ||
7314 | static const ARMCPRegInfo ccsidr2_reginfo[] = { | |
7315 | { .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH, | |
7316 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2, | |
7317 | .access = PL1_R, | |
7318 | .accessfn = access_aa64_tid2, | |
7319 | .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW }, | |
957e6155 PM |
7320 | }; |
7321 | ||
6a4ef4e5 MZ |
7322 | static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri, |
7323 | bool isread) | |
7324 | { | |
7325 | if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) { | |
7326 | return CP_ACCESS_TRAP_EL2; | |
7327 | } | |
7328 | ||
7329 | return CP_ACCESS_OK; | |
7330 | } | |
7331 | ||
7332 | static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri, | |
7333 | bool isread) | |
7334 | { | |
7335 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
7336 | return access_aa64_tid3(env, ri, isread); | |
7337 | } | |
7338 | ||
7339 | return CP_ACCESS_OK; | |
7340 | } | |
7341 | ||
f96f3d5f MZ |
7342 | static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri, |
7343 | bool isread) | |
7344 | { | |
7345 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID0)) { | |
7346 | return CP_ACCESS_TRAP_EL2; | |
7347 | } | |
7348 | ||
7349 | return CP_ACCESS_OK; | |
7350 | } | |
7351 | ||
8e228c9e PM |
7352 | static CPAccessResult access_joscr_jmcr(CPUARMState *env, |
7353 | const ARMCPRegInfo *ri, bool isread) | |
7354 | { | |
7355 | /* | |
7356 | * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only | |
7357 | * in v7A, not in v8A. | |
7358 | */ | |
7359 | if (!arm_feature(env, ARM_FEATURE_V8) && | |
7360 | arm_current_el(env) < 2 && !arm_is_secure_below_el3(env) && | |
7361 | (env->cp15.hstr_el2 & HSTR_TJDBX)) { | |
7362 | return CP_ACCESS_TRAP_EL2; | |
7363 | } | |
7364 | return CP_ACCESS_OK; | |
7365 | } | |
7366 | ||
f96f3d5f MZ |
7367 | static const ARMCPRegInfo jazelle_regs[] = { |
7368 | { .name = "JIDR", | |
7369 | .cp = 14, .crn = 0, .crm = 0, .opc1 = 7, .opc2 = 0, | |
7370 | .access = PL1_R, .accessfn = access_jazelle, | |
7371 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
7372 | { .name = "JOSCR", | |
7373 | .cp = 14, .crn = 1, .crm = 0, .opc1 = 7, .opc2 = 0, | |
8e228c9e | 7374 | .accessfn = access_joscr_jmcr, |
f96f3d5f MZ |
7375 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
7376 | { .name = "JMCR", | |
7377 | .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0, | |
8e228c9e | 7378 | .accessfn = access_joscr_jmcr, |
f96f3d5f | 7379 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f96f3d5f MZ |
7380 | }; |
7381 | ||
e2a1a461 RH |
7382 | static const ARMCPRegInfo vhe_reginfo[] = { |
7383 | { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, | |
7384 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, | |
7385 | .access = PL2_RW, | |
7386 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) }, | |
ed30da8e RH |
7387 | { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, |
7388 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, | |
7389 | .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, | |
7390 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) }, | |
8c94b071 RH |
7391 | #ifndef CONFIG_USER_ONLY |
7392 | { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64, | |
7393 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 2, | |
7394 | .fieldoffset = | |
7395 | offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval), | |
7396 | .type = ARM_CP_IO, .access = PL2_RW, | |
7397 | .writefn = gt_hv_cval_write, .raw_writefn = raw_write }, | |
7398 | { .name = "CNTHV_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
7399 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 0, | |
7400 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, | |
7401 | .resetfn = gt_hv_timer_reset, | |
7402 | .readfn = gt_hv_tval_read, .writefn = gt_hv_tval_write }, | |
7403 | { .name = "CNTHV_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
7404 | .type = ARM_CP_IO, | |
7405 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 1, | |
7406 | .access = PL2_RW, | |
7407 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].ctl), | |
7408 | .writefn = gt_hv_ctl_write, .raw_writefn = raw_write }, | |
bb5972e4 RH |
7409 | { .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64, |
7410 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1, | |
7411 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
7412 | .access = PL2_RW, .accessfn = e2h_access, | |
7413 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), | |
7414 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write }, | |
7415 | { .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64, | |
7416 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1, | |
7417 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
7418 | .access = PL2_RW, .accessfn = e2h_access, | |
7419 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), | |
7420 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write }, | |
7421 | { .name = "CNTP_TVAL_EL02", .state = ARM_CP_STATE_AA64, | |
7422 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 0, | |
7423 | .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, | |
7424 | .access = PL2_RW, .accessfn = e2h_access, | |
7425 | .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write }, | |
7426 | { .name = "CNTV_TVAL_EL02", .state = ARM_CP_STATE_AA64, | |
7427 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 0, | |
7428 | .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, | |
7429 | .access = PL2_RW, .accessfn = e2h_access, | |
7430 | .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write }, | |
7431 | { .name = "CNTP_CVAL_EL02", .state = ARM_CP_STATE_AA64, | |
7432 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 2, | |
7433 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
7434 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
7435 | .access = PL2_RW, .accessfn = e2h_access, | |
7436 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write }, | |
7437 | { .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64, | |
7438 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2, | |
7439 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
7440 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
7441 | .access = PL2_RW, .accessfn = e2h_access, | |
7442 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write }, | |
8c94b071 | 7443 | #endif |
e2a1a461 RH |
7444 | }; |
7445 | ||
04b07d29 RH |
7446 | #ifndef CONFIG_USER_ONLY |
7447 | static const ARMCPRegInfo ats1e1_reginfo[] = { | |
7448 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
7449 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, | |
7450 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
7451 | .writefn = ats_write64 }, | |
7452 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, | |
7453 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, | |
7454 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
7455 | .writefn = ats_write64 }, | |
04b07d29 RH |
7456 | }; |
7457 | ||
7458 | static const ARMCPRegInfo ats1cp_reginfo[] = { | |
7459 | { .name = "ATS1CPRP", | |
7460 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, | |
7461 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
7462 | .writefn = ats_write }, | |
7463 | { .name = "ATS1CPWP", | |
7464 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, | |
7465 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
7466 | .writefn = ats_write }, | |
04b07d29 RH |
7467 | }; |
7468 | #endif | |
7469 | ||
f6287c24 PM |
7470 | /* |
7471 | * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and | |
7472 | * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field | |
7473 | * is non-zero, which is never for ARMv7, optionally in ARMv8 | |
7474 | * and mandatorily for ARMv8.2 and up. | |
7475 | * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's | |
7476 | * implementation is RAZ/WI we can ignore this detail, as we | |
7477 | * do for ACTLR. | |
7478 | */ | |
7479 | static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = { | |
7480 | { .name = "ACTLR2", .state = ARM_CP_STATE_AA32, | |
7481 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 3, | |
99602377 RH |
7482 | .access = PL1_RW, .accessfn = access_tacr, |
7483 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
f6287c24 PM |
7484 | { .name = "HACTLR2", .state = ARM_CP_STATE_AA32, |
7485 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3, | |
7486 | .access = PL2_RW, .type = ARM_CP_CONST, | |
7487 | .resetvalue = 0 }, | |
f6287c24 PM |
7488 | }; |
7489 | ||
2ceb98c0 PM |
7490 | void register_cp_regs_for_features(ARMCPU *cpu) |
7491 | { | |
7492 | /* Register all the coprocessor registers based on feature bits */ | |
7493 | CPUARMState *env = &cpu->env; | |
7494 | if (arm_feature(env, ARM_FEATURE_M)) { | |
7495 | /* M profile has no coprocessor registers */ | |
7496 | return; | |
7497 | } | |
7498 | ||
e9aa6c21 | 7499 | define_arm_cp_regs(cpu, cp_reginfo); |
9449fdf6 PM |
7500 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
7501 | /* Must go early as it is full of wildcards that may be | |
7502 | * overridden by later definitions. | |
7503 | */ | |
7504 | define_arm_cp_regs(cpu, not_v8_cp_reginfo); | |
7505 | } | |
7506 | ||
7d57f408 | 7507 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8515a092 PM |
7508 | /* The ID registers all have impdef reset values */ |
7509 | ARMCPRegInfo v6_idregs[] = { | |
0ff644a7 PM |
7510 | { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, |
7511 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
7512 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7513 | .accessfn = access_aa32_tid3, |
8a130a7b | 7514 | .resetvalue = cpu->isar.id_pfr0 }, |
96a8b92e PM |
7515 | /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know |
7516 | * the value of the GIC field until after we define these regs. | |
7517 | */ | |
0ff644a7 PM |
7518 | { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, |
7519 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | |
96a8b92e | 7520 | .access = PL1_R, .type = ARM_CP_NO_RAW, |
6a4ef4e5 | 7521 | .accessfn = access_aa32_tid3, |
96a8b92e PM |
7522 | .readfn = id_pfr1_read, |
7523 | .writefn = arm_cp_write_ignore }, | |
0ff644a7 PM |
7524 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, |
7525 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | |
7526 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7527 | .accessfn = access_aa32_tid3, |
a6179538 | 7528 | .resetvalue = cpu->isar.id_dfr0 }, |
0ff644a7 PM |
7529 | { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, |
7530 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, | |
7531 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7532 | .accessfn = access_aa32_tid3, |
8515a092 | 7533 | .resetvalue = cpu->id_afr0 }, |
0ff644a7 PM |
7534 | { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, |
7535 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, | |
7536 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7537 | .accessfn = access_aa32_tid3, |
10054016 | 7538 | .resetvalue = cpu->isar.id_mmfr0 }, |
0ff644a7 PM |
7539 | { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, |
7540 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, | |
7541 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7542 | .accessfn = access_aa32_tid3, |
10054016 | 7543 | .resetvalue = cpu->isar.id_mmfr1 }, |
0ff644a7 PM |
7544 | { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, |
7545 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, | |
7546 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7547 | .accessfn = access_aa32_tid3, |
10054016 | 7548 | .resetvalue = cpu->isar.id_mmfr2 }, |
0ff644a7 PM |
7549 | { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, |
7550 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, | |
7551 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7552 | .accessfn = access_aa32_tid3, |
10054016 | 7553 | .resetvalue = cpu->isar.id_mmfr3 }, |
0ff644a7 PM |
7554 | { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, |
7555 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
7556 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7557 | .accessfn = access_aa32_tid3, |
47576b94 | 7558 | .resetvalue = cpu->isar.id_isar0 }, |
0ff644a7 PM |
7559 | { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, |
7560 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, | |
7561 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7562 | .accessfn = access_aa32_tid3, |
47576b94 | 7563 | .resetvalue = cpu->isar.id_isar1 }, |
0ff644a7 PM |
7564 | { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, |
7565 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
7566 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7567 | .accessfn = access_aa32_tid3, |
47576b94 | 7568 | .resetvalue = cpu->isar.id_isar2 }, |
0ff644a7 PM |
7569 | { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, |
7570 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, | |
7571 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7572 | .accessfn = access_aa32_tid3, |
47576b94 | 7573 | .resetvalue = cpu->isar.id_isar3 }, |
0ff644a7 PM |
7574 | { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, |
7575 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, | |
7576 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7577 | .accessfn = access_aa32_tid3, |
47576b94 | 7578 | .resetvalue = cpu->isar.id_isar4 }, |
0ff644a7 PM |
7579 | { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, |
7580 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, | |
7581 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7582 | .accessfn = access_aa32_tid3, |
47576b94 | 7583 | .resetvalue = cpu->isar.id_isar5 }, |
e20d84c1 PM |
7584 | { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, |
7585 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, | |
7586 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7587 | .accessfn = access_aa32_tid3, |
10054016 | 7588 | .resetvalue = cpu->isar.id_mmfr4 }, |
802abf40 | 7589 | { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
7590 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, |
7591 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7592 | .accessfn = access_aa32_tid3, |
47576b94 | 7593 | .resetvalue = cpu->isar.id_isar6 }, |
8515a092 PM |
7594 | }; |
7595 | define_arm_cp_regs(cpu, v6_idregs); | |
7d57f408 PM |
7596 | define_arm_cp_regs(cpu, v6_cp_reginfo); |
7597 | } else { | |
7598 | define_arm_cp_regs(cpu, not_v6_cp_reginfo); | |
7599 | } | |
4d31c596 PM |
7600 | if (arm_feature(env, ARM_FEATURE_V6K)) { |
7601 | define_arm_cp_regs(cpu, v6k_cp_reginfo); | |
7602 | } | |
5e5cf9e3 | 7603 | if (arm_feature(env, ARM_FEATURE_V7MP) && |
452a0955 | 7604 | !arm_feature(env, ARM_FEATURE_PMSA)) { |
995939a6 PM |
7605 | define_arm_cp_regs(cpu, v7mp_cp_reginfo); |
7606 | } | |
327dd510 AL |
7607 | if (arm_feature(env, ARM_FEATURE_V7VE)) { |
7608 | define_arm_cp_regs(cpu, pmovsset_cp_reginfo); | |
7609 | } | |
e9aa6c21 | 7610 | if (arm_feature(env, ARM_FEATURE_V7)) { |
776d4e5c | 7611 | ARMCPRegInfo clidr = { |
7da845b0 PM |
7612 | .name = "CLIDR", .state = ARM_CP_STATE_BOTH, |
7613 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | |
630fcd4d MZ |
7614 | .access = PL1_R, .type = ARM_CP_CONST, |
7615 | .accessfn = access_aa64_tid2, | |
7616 | .resetvalue = cpu->clidr | |
776d4e5c | 7617 | }; |
776d4e5c | 7618 | define_one_arm_cp_reg(cpu, &clidr); |
e9aa6c21 | 7619 | define_arm_cp_regs(cpu, v7_cp_reginfo); |
50300698 | 7620 | define_debug_regs(cpu); |
24183fb6 | 7621 | define_pmu_regs(cpu); |
7d57f408 PM |
7622 | } else { |
7623 | define_arm_cp_regs(cpu, not_v7_cp_reginfo); | |
e9aa6c21 | 7624 | } |
b0d2b7d0 | 7625 | if (arm_feature(env, ARM_FEATURE_V8)) { |
e20d84c1 PM |
7626 | /* AArch64 ID registers, which all have impdef reset values. |
7627 | * Note that within the ID register ranges the unused slots | |
7628 | * must all RAZ, not UNDEF; future architecture versions may | |
7629 | * define new registers here. | |
7630 | */ | |
e60cef86 | 7631 | ARMCPRegInfo v8_idregs[] = { |
976b99b6 AB |
7632 | /* |
7633 | * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system | |
7634 | * emulation because we don't know the right value for the | |
7635 | * GIC field until after we define these regs. | |
96a8b92e | 7636 | */ |
e60cef86 PM |
7637 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, |
7638 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | |
976b99b6 AB |
7639 | .access = PL1_R, |
7640 | #ifdef CONFIG_USER_ONLY | |
7641 | .type = ARM_CP_CONST, | |
7642 | .resetvalue = cpu->isar.id_aa64pfr0 | |
7643 | #else | |
7644 | .type = ARM_CP_NO_RAW, | |
6a4ef4e5 | 7645 | .accessfn = access_aa64_tid3, |
96a8b92e | 7646 | .readfn = id_aa64pfr0_read, |
976b99b6 AB |
7647 | .writefn = arm_cp_write_ignore |
7648 | #endif | |
7649 | }, | |
e60cef86 PM |
7650 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, |
7651 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | |
7652 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7653 | .accessfn = access_aa64_tid3, |
47576b94 | 7654 | .resetvalue = cpu->isar.id_aa64pfr1}, |
e20d84c1 PM |
7655 | { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7656 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, | |
7657 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7658 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7659 | .resetvalue = 0 }, |
7660 | { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7661 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, | |
7662 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7663 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7664 | .resetvalue = 0 }, |
9516d772 | 7665 | { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
7666 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, |
7667 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7668 | .accessfn = access_aa64_tid3, |
2dc10fa2 | 7669 | .resetvalue = cpu->isar.id_aa64zfr0 }, |
e20d84c1 PM |
7670 | { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7671 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, | |
7672 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7673 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7674 | .resetvalue = 0 }, |
7675 | { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7676 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, | |
7677 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7678 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7679 | .resetvalue = 0 }, |
7680 | { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7681 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, | |
7682 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7683 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7684 | .resetvalue = 0 }, |
e60cef86 PM |
7685 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, |
7686 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | |
7687 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7688 | .accessfn = access_aa64_tid3, |
2a609df8 | 7689 | .resetvalue = cpu->isar.id_aa64dfr0 }, |
e60cef86 PM |
7690 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, |
7691 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | |
7692 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7693 | .accessfn = access_aa64_tid3, |
2a609df8 | 7694 | .resetvalue = cpu->isar.id_aa64dfr1 }, |
e20d84c1 PM |
7695 | { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7696 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, | |
7697 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7698 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7699 | .resetvalue = 0 }, |
7700 | { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7701 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, | |
7702 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7703 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7704 | .resetvalue = 0 }, |
e60cef86 PM |
7705 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, |
7706 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | |
7707 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7708 | .accessfn = access_aa64_tid3, |
e60cef86 PM |
7709 | .resetvalue = cpu->id_aa64afr0 }, |
7710 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | |
7711 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | |
7712 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7713 | .accessfn = access_aa64_tid3, |
e60cef86 | 7714 | .resetvalue = cpu->id_aa64afr1 }, |
e20d84c1 PM |
7715 | { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7716 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, | |
7717 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7718 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7719 | .resetvalue = 0 }, |
7720 | { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7721 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, | |
7722 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7723 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7724 | .resetvalue = 0 }, |
e60cef86 PM |
7725 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, |
7726 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | |
7727 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7728 | .accessfn = access_aa64_tid3, |
47576b94 | 7729 | .resetvalue = cpu->isar.id_aa64isar0 }, |
e60cef86 PM |
7730 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, |
7731 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | |
7732 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7733 | .accessfn = access_aa64_tid3, |
47576b94 | 7734 | .resetvalue = cpu->isar.id_aa64isar1 }, |
e20d84c1 PM |
7735 | { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7736 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, | |
7737 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7738 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7739 | .resetvalue = 0 }, |
7740 | { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7741 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, | |
7742 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7743 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7744 | .resetvalue = 0 }, |
7745 | { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7746 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, | |
7747 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7748 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7749 | .resetvalue = 0 }, |
7750 | { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7751 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, | |
7752 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7753 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7754 | .resetvalue = 0 }, |
7755 | { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7756 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, | |
7757 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7758 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7759 | .resetvalue = 0 }, |
7760 | { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7761 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, | |
7762 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7763 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7764 | .resetvalue = 0 }, |
e60cef86 PM |
7765 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, |
7766 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
7767 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7768 | .accessfn = access_aa64_tid3, |
3dc91ddb | 7769 | .resetvalue = cpu->isar.id_aa64mmfr0 }, |
e60cef86 PM |
7770 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, |
7771 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | |
7772 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7773 | .accessfn = access_aa64_tid3, |
3dc91ddb | 7774 | .resetvalue = cpu->isar.id_aa64mmfr1 }, |
64761e10 | 7775 | { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
7776 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, |
7777 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7778 | .accessfn = access_aa64_tid3, |
64761e10 | 7779 | .resetvalue = cpu->isar.id_aa64mmfr2 }, |
e20d84c1 PM |
7780 | { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7781 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, | |
7782 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7783 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7784 | .resetvalue = 0 }, |
7785 | { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7786 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, | |
7787 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7788 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7789 | .resetvalue = 0 }, |
7790 | { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7791 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, | |
7792 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7793 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7794 | .resetvalue = 0 }, |
7795 | { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7796 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, | |
7797 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7798 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7799 | .resetvalue = 0 }, |
7800 | { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7801 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, | |
7802 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7803 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7804 | .resetvalue = 0 }, |
a50c0f51 PM |
7805 | { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, |
7806 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
7807 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7808 | .accessfn = access_aa64_tid3, |
47576b94 | 7809 | .resetvalue = cpu->isar.mvfr0 }, |
a50c0f51 PM |
7810 | { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, |
7811 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
7812 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7813 | .accessfn = access_aa64_tid3, |
47576b94 | 7814 | .resetvalue = cpu->isar.mvfr1 }, |
a50c0f51 PM |
7815 | { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, |
7816 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
7817 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7818 | .accessfn = access_aa64_tid3, |
47576b94 | 7819 | .resetvalue = cpu->isar.mvfr2 }, |
e20d84c1 PM |
7820 | { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7821 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, | |
7822 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7823 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7824 | .resetvalue = 0 }, |
1d51bc96 | 7825 | { .name = "ID_PFR2", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
7826 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, |
7827 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7828 | .accessfn = access_aa64_tid3, |
1d51bc96 | 7829 | .resetvalue = cpu->isar.id_pfr2 }, |
e20d84c1 PM |
7830 | { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7831 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, | |
7832 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7833 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7834 | .resetvalue = 0 }, |
7835 | { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7836 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, | |
7837 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7838 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7839 | .resetvalue = 0 }, |
7840 | { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7841 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, | |
7842 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7843 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7844 | .resetvalue = 0 }, |
4054bfa9 AF |
7845 | { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, |
7846 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, | |
7847 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
cad86737 | 7848 | .resetvalue = extract64(cpu->pmceid0, 0, 32) }, |
4054bfa9 AF |
7849 | { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, |
7850 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, | |
7851 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
7852 | .resetvalue = cpu->pmceid0 }, | |
7853 | { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, | |
7854 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, | |
7855 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
cad86737 | 7856 | .resetvalue = extract64(cpu->pmceid1, 0, 32) }, |
4054bfa9 AF |
7857 | { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, |
7858 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, | |
7859 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
7860 | .resetvalue = cpu->pmceid1 }, | |
e60cef86 | 7861 | }; |
6c5c0fec | 7862 | #ifdef CONFIG_USER_ONLY |
10b0220e | 7863 | static const ARMCPRegUserSpaceInfo v8_user_idregs[] = { |
6c5c0fec AB |
7864 | { .name = "ID_AA64PFR0_EL1", |
7865 | .exported_bits = 0x000f000f00ff0000, | |
7866 | .fixed_bits = 0x0000000000000011 }, | |
7867 | { .name = "ID_AA64PFR1_EL1", | |
7868 | .exported_bits = 0x00000000000000f0 }, | |
d040242e AB |
7869 | { .name = "ID_AA64PFR*_EL1_RESERVED", |
7870 | .is_glob = true }, | |
6c5c0fec AB |
7871 | { .name = "ID_AA64ZFR0_EL1" }, |
7872 | { .name = "ID_AA64MMFR0_EL1", | |
7873 | .fixed_bits = 0x00000000ff000000 }, | |
7874 | { .name = "ID_AA64MMFR1_EL1" }, | |
d040242e AB |
7875 | { .name = "ID_AA64MMFR*_EL1_RESERVED", |
7876 | .is_glob = true }, | |
6c5c0fec AB |
7877 | { .name = "ID_AA64DFR0_EL1", |
7878 | .fixed_bits = 0x0000000000000006 }, | |
7879 | { .name = "ID_AA64DFR1_EL1" }, | |
d040242e AB |
7880 | { .name = "ID_AA64DFR*_EL1_RESERVED", |
7881 | .is_glob = true }, | |
7882 | { .name = "ID_AA64AFR*", | |
7883 | .is_glob = true }, | |
6c5c0fec AB |
7884 | { .name = "ID_AA64ISAR0_EL1", |
7885 | .exported_bits = 0x00fffffff0fffff0 }, | |
7886 | { .name = "ID_AA64ISAR1_EL1", | |
7887 | .exported_bits = 0x000000f0ffffffff }, | |
d040242e AB |
7888 | { .name = "ID_AA64ISAR*_EL1_RESERVED", |
7889 | .is_glob = true }, | |
6c5c0fec AB |
7890 | }; |
7891 | modify_arm_cp_regs(v8_idregs, v8_user_idregs); | |
7892 | #endif | |
be8e8128 GB |
7893 | /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ |
7894 | if (!arm_feature(env, ARM_FEATURE_EL3) && | |
7895 | !arm_feature(env, ARM_FEATURE_EL2)) { | |
7896 | ARMCPRegInfo rvbar = { | |
7897 | .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, | |
7898 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, | |
4a7319b7 EI |
7899 | .access = PL1_R, |
7900 | .fieldoffset = offsetof(CPUARMState, cp15.rvbar), | |
be8e8128 GB |
7901 | }; |
7902 | define_one_arm_cp_reg(cpu, &rvbar); | |
7903 | } | |
e60cef86 | 7904 | define_arm_cp_regs(cpu, v8_idregs); |
b0d2b7d0 PM |
7905 | define_arm_cp_regs(cpu, v8_cp_reginfo); |
7906 | } | |
3b685ba7 | 7907 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
f0d574d6 | 7908 | uint64_t vmpidr_def = mpidr_read_val(env); |
731de9e6 EI |
7909 | ARMCPRegInfo vpidr_regs[] = { |
7910 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | |
7911 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
7912 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
36476562 PM |
7913 | .resetvalue = cpu->midr, .type = ARM_CP_ALIAS, |
7914 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) }, | |
731de9e6 EI |
7915 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, |
7916 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
7917 | .access = PL2_RW, .resetvalue = cpu->midr, | |
7918 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
f0d574d6 EI |
7919 | { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, |
7920 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
7921 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
36476562 PM |
7922 | .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS, |
7923 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) }, | |
f0d574d6 EI |
7924 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, |
7925 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
7926 | .access = PL2_RW, | |
7927 | .resetvalue = vmpidr_def, | |
7928 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | |
731de9e6 EI |
7929 | }; |
7930 | define_arm_cp_regs(cpu, vpidr_regs); | |
4771cd01 | 7931 | define_arm_cp_regs(cpu, el2_cp_reginfo); |
ce4afed8 PM |
7932 | if (arm_feature(env, ARM_FEATURE_V8)) { |
7933 | define_arm_cp_regs(cpu, el2_v8_cp_reginfo); | |
7934 | } | |
e9152ee9 RDC |
7935 | if (cpu_isar_feature(aa64_sel2, cpu)) { |
7936 | define_arm_cp_regs(cpu, el2_sec_cp_reginfo); | |
7937 | } | |
be8e8128 GB |
7938 | /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ |
7939 | if (!arm_feature(env, ARM_FEATURE_EL3)) { | |
7940 | ARMCPRegInfo rvbar = { | |
7941 | .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, | |
7942 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, | |
4a7319b7 EI |
7943 | .access = PL2_R, |
7944 | .fieldoffset = offsetof(CPUARMState, cp15.rvbar), | |
be8e8128 GB |
7945 | }; |
7946 | define_one_arm_cp_reg(cpu, &rvbar); | |
7947 | } | |
d42e3c26 EI |
7948 | } else { |
7949 | /* If EL2 is missing but higher ELs are enabled, we need to | |
7950 | * register the no_el2 reginfos. | |
7951 | */ | |
7952 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
f0d574d6 EI |
7953 | /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value |
7954 | * of MIDR_EL1 and MPIDR_EL1. | |
731de9e6 EI |
7955 | */ |
7956 | ARMCPRegInfo vpidr_regs[] = { | |
7957 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH, | |
7958 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
93dd1e61 | 7959 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
731de9e6 EI |
7960 | .type = ARM_CP_CONST, .resetvalue = cpu->midr, |
7961 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
f0d574d6 EI |
7962 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
7963 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
93dd1e61 | 7964 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
f0d574d6 EI |
7965 | .type = ARM_CP_NO_RAW, |
7966 | .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, | |
731de9e6 EI |
7967 | }; |
7968 | define_arm_cp_regs(cpu, vpidr_regs); | |
4771cd01 | 7969 | define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); |
ce4afed8 PM |
7970 | if (arm_feature(env, ARM_FEATURE_V8)) { |
7971 | define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo); | |
7972 | } | |
d42e3c26 | 7973 | } |
3b685ba7 | 7974 | } |
81547d66 | 7975 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0f1a3b24 | 7976 | define_arm_cp_regs(cpu, el3_cp_reginfo); |
e24fdd23 PM |
7977 | ARMCPRegInfo el3_regs[] = { |
7978 | { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, | |
7979 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, | |
4a7319b7 EI |
7980 | .access = PL3_R, |
7981 | .fieldoffset = offsetof(CPUARMState, cp15.rvbar), | |
7982 | }, | |
e24fdd23 PM |
7983 | { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, |
7984 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, | |
7985 | .access = PL3_RW, | |
7986 | .raw_writefn = raw_write, .writefn = sctlr_write, | |
7987 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), | |
7988 | .resetvalue = cpu->reset_sctlr }, | |
be8e8128 | 7989 | }; |
e24fdd23 PM |
7990 | |
7991 | define_arm_cp_regs(cpu, el3_regs); | |
81547d66 | 7992 | } |
2f027fc5 PM |
7993 | /* The behaviour of NSACR is sufficiently various that we don't |
7994 | * try to describe it in a single reginfo: | |
7995 | * if EL3 is 64 bit, then trap to EL3 from S EL1, | |
7996 | * reads as constant 0xc00 from NS EL1 and NS EL2 | |
7997 | * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 | |
7998 | * if v7 without EL3, register doesn't exist | |
7999 | * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 | |
8000 | */ | |
8001 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
8002 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
10b0220e | 8003 | static const ARMCPRegInfo nsacr = { |
2f027fc5 PM |
8004 | .name = "NSACR", .type = ARM_CP_CONST, |
8005 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
8006 | .access = PL1_RW, .accessfn = nsacr_access, | |
8007 | .resetvalue = 0xc00 | |
8008 | }; | |
8009 | define_one_arm_cp_reg(cpu, &nsacr); | |
8010 | } else { | |
10b0220e | 8011 | static const ARMCPRegInfo nsacr = { |
2f027fc5 PM |
8012 | .name = "NSACR", |
8013 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
8014 | .access = PL3_RW | PL1_R, | |
8015 | .resetvalue = 0, | |
8016 | .fieldoffset = offsetof(CPUARMState, cp15.nsacr) | |
8017 | }; | |
8018 | define_one_arm_cp_reg(cpu, &nsacr); | |
8019 | } | |
8020 | } else { | |
8021 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
10b0220e | 8022 | static const ARMCPRegInfo nsacr = { |
2f027fc5 PM |
8023 | .name = "NSACR", .type = ARM_CP_CONST, |
8024 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
8025 | .access = PL1_R, | |
8026 | .resetvalue = 0xc00 | |
8027 | }; | |
8028 | define_one_arm_cp_reg(cpu, &nsacr); | |
8029 | } | |
8030 | } | |
8031 | ||
452a0955 | 8032 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
6cb0b013 PC |
8033 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8034 | /* PMSAv6 not implemented */ | |
8035 | assert(arm_feature(env, ARM_FEATURE_V7)); | |
8036 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); | |
8037 | define_arm_cp_regs(cpu, pmsav7_cp_reginfo); | |
8038 | } else { | |
8039 | define_arm_cp_regs(cpu, pmsav5_cp_reginfo); | |
8040 | } | |
18032bec | 8041 | } else { |
8e5d75c9 | 8042 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); |
18032bec | 8043 | define_arm_cp_regs(cpu, vmsa_cp_reginfo); |
4036b7d1 PM |
8044 | /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */ |
8045 | if (cpu_isar_feature(aa32_hpd, cpu)) { | |
ab638a32 RH |
8046 | define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); |
8047 | } | |
18032bec | 8048 | } |
c326b979 PM |
8049 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
8050 | define_arm_cp_regs(cpu, t2ee_cp_reginfo); | |
8051 | } | |
6cc7a3ae PM |
8052 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
8053 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); | |
8054 | } | |
4a501606 PM |
8055 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
8056 | define_arm_cp_regs(cpu, vapa_cp_reginfo); | |
8057 | } | |
c4804214 PM |
8058 | if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { |
8059 | define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); | |
8060 | } | |
8061 | if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { | |
8062 | define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); | |
8063 | } | |
8064 | if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { | |
8065 | define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); | |
8066 | } | |
18032bec PM |
8067 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
8068 | define_arm_cp_regs(cpu, omap_cp_reginfo); | |
8069 | } | |
34f90529 PM |
8070 | if (arm_feature(env, ARM_FEATURE_STRONGARM)) { |
8071 | define_arm_cp_regs(cpu, strongarm_cp_reginfo); | |
8072 | } | |
1047b9d7 PM |
8073 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
8074 | define_arm_cp_regs(cpu, xscale_cp_reginfo); | |
8075 | } | |
8076 | if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { | |
8077 | define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); | |
8078 | } | |
7ac681cf PM |
8079 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8080 | define_arm_cp_regs(cpu, lpae_cp_reginfo); | |
8081 | } | |
873b73c0 | 8082 | if (cpu_isar_feature(aa32_jazelle, cpu)) { |
f96f3d5f MZ |
8083 | define_arm_cp_regs(cpu, jazelle_regs); |
8084 | } | |
7884849c PM |
8085 | /* Slightly awkwardly, the OMAP and StrongARM cores need all of |
8086 | * cp15 crn=0 to be writes-ignored, whereas for other cores they should | |
8087 | * be read-only (ie write causes UNDEF exception). | |
8088 | */ | |
8089 | { | |
00a29f3d PM |
8090 | ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { |
8091 | /* Pre-v8 MIDR space. | |
8092 | * Note that the MIDR isn't a simple constant register because | |
7884849c PM |
8093 | * of the TI925 behaviour where writes to another register can |
8094 | * cause the MIDR value to change. | |
97ce8d61 PC |
8095 | * |
8096 | * Unimplemented registers in the c15 0 0 0 space default to | |
8097 | * MIDR. Define MIDR first as this entire space, then CTR, TCMTR | |
8098 | * and friends override accordingly. | |
7884849c PM |
8099 | */ |
8100 | { .name = "MIDR", | |
97ce8d61 | 8101 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, |
7884849c | 8102 | .access = PL1_R, .resetvalue = cpu->midr, |
d4e6df63 | 8103 | .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, |
731de9e6 | 8104 | .readfn = midr_read, |
97ce8d61 PC |
8105 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
8106 | .type = ARM_CP_OVERRIDE }, | |
7884849c PM |
8107 | /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ |
8108 | { .name = "DUMMY", | |
8109 | .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, | |
8110 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8111 | { .name = "DUMMY", | |
8112 | .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, | |
8113 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8114 | { .name = "DUMMY", | |
8115 | .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, | |
8116 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8117 | { .name = "DUMMY", | |
8118 | .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, | |
8119 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8120 | { .name = "DUMMY", | |
8121 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | |
8122 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
7884849c | 8123 | }; |
00a29f3d | 8124 | ARMCPRegInfo id_v8_midr_cp_reginfo[] = { |
00a29f3d PM |
8125 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, |
8126 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, | |
731de9e6 EI |
8127 | .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, |
8128 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), | |
8129 | .readfn = midr_read }, | |
ac00c79f SF |
8130 | /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ |
8131 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
8132 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
8133 | .access = PL1_R, .resetvalue = cpu->midr }, | |
8134 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
8135 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, | |
8136 | .access = PL1_R, .resetvalue = cpu->midr }, | |
00a29f3d PM |
8137 | { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, |
8138 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, | |
93fbc983 MZ |
8139 | .access = PL1_R, |
8140 | .accessfn = access_aa64_tid1, | |
8141 | .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, | |
00a29f3d PM |
8142 | }; |
8143 | ARMCPRegInfo id_cp_reginfo[] = { | |
8144 | /* These are common to v8 and pre-v8 */ | |
8145 | { .name = "CTR", | |
8146 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, | |
630fcd4d MZ |
8147 | .access = PL1_R, .accessfn = ctr_el0_access, |
8148 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
00a29f3d PM |
8149 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, |
8150 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, | |
8151 | .access = PL0_R, .accessfn = ctr_el0_access, | |
8152 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
8153 | /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ | |
8154 | { .name = "TCMTR", | |
8155 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, | |
93fbc983 MZ |
8156 | .access = PL1_R, |
8157 | .accessfn = access_aa32_tid1, | |
8158 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
00a29f3d | 8159 | }; |
8085ce63 PC |
8160 | /* TLBTR is specific to VMSA */ |
8161 | ARMCPRegInfo id_tlbtr_reginfo = { | |
8162 | .name = "TLBTR", | |
8163 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, | |
93fbc983 MZ |
8164 | .access = PL1_R, |
8165 | .accessfn = access_aa32_tid1, | |
8166 | .type = ARM_CP_CONST, .resetvalue = 0, | |
8085ce63 | 8167 | }; |
3281af81 PC |
8168 | /* MPUIR is specific to PMSA V6+ */ |
8169 | ARMCPRegInfo id_mpuir_reginfo = { | |
8170 | .name = "MPUIR", | |
8171 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
8172 | .access = PL1_R, .type = ARM_CP_CONST, | |
8173 | .resetvalue = cpu->pmsav7_dregion << 8 | |
8174 | }; | |
10b0220e | 8175 | static const ARMCPRegInfo crn0_wi_reginfo = { |
7884849c PM |
8176 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, |
8177 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | |
8178 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | |
8179 | }; | |
6c5c0fec | 8180 | #ifdef CONFIG_USER_ONLY |
10b0220e | 8181 | static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = { |
6c5c0fec AB |
8182 | { .name = "MIDR_EL1", |
8183 | .exported_bits = 0x00000000ffffffff }, | |
8184 | { .name = "REVIDR_EL1" }, | |
6c5c0fec AB |
8185 | }; |
8186 | modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo); | |
8187 | #endif | |
7884849c PM |
8188 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || |
8189 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | |
5809ac57 | 8190 | size_t i; |
7884849c | 8191 | /* Register the blanket "writes ignored" value first to cover the |
a703eda1 PC |
8192 | * whole space. Then update the specific ID registers to allow write |
8193 | * access, so that they ignore writes rather than causing them to | |
8194 | * UNDEF. | |
7884849c PM |
8195 | */ |
8196 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | |
5809ac57 RH |
8197 | for (i = 0; i < ARRAY_SIZE(id_pre_v8_midr_cp_reginfo); ++i) { |
8198 | id_pre_v8_midr_cp_reginfo[i].access = PL1_RW; | |
00a29f3d | 8199 | } |
5809ac57 RH |
8200 | for (i = 0; i < ARRAY_SIZE(id_cp_reginfo); ++i) { |
8201 | id_cp_reginfo[i].access = PL1_RW; | |
7884849c | 8202 | } |
10006112 | 8203 | id_mpuir_reginfo.access = PL1_RW; |
3281af81 | 8204 | id_tlbtr_reginfo.access = PL1_RW; |
7884849c | 8205 | } |
00a29f3d PM |
8206 | if (arm_feature(env, ARM_FEATURE_V8)) { |
8207 | define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); | |
8208 | } else { | |
8209 | define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); | |
8210 | } | |
a703eda1 | 8211 | define_arm_cp_regs(cpu, id_cp_reginfo); |
452a0955 | 8212 | if (!arm_feature(env, ARM_FEATURE_PMSA)) { |
8085ce63 | 8213 | define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); |
3281af81 PC |
8214 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8215 | define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); | |
8085ce63 | 8216 | } |
7884849c PM |
8217 | } |
8218 | ||
97ce8d61 | 8219 | if (arm_feature(env, ARM_FEATURE_MPIDR)) { |
52264166 AB |
8220 | ARMCPRegInfo mpidr_cp_reginfo[] = { |
8221 | { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
8222 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | |
8223 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, | |
52264166 AB |
8224 | }; |
8225 | #ifdef CONFIG_USER_ONLY | |
10b0220e | 8226 | static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = { |
52264166 AB |
8227 | { .name = "MPIDR_EL1", |
8228 | .fixed_bits = 0x0000000080000000 }, | |
52264166 AB |
8229 | }; |
8230 | modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); | |
8231 | #endif | |
97ce8d61 PC |
8232 | define_arm_cp_regs(cpu, mpidr_cp_reginfo); |
8233 | } | |
8234 | ||
2771db27 | 8235 | if (arm_feature(env, ARM_FEATURE_AUXCR)) { |
834a6c69 PM |
8236 | ARMCPRegInfo auxcr_reginfo[] = { |
8237 | { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, | |
8238 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, | |
99602377 RH |
8239 | .access = PL1_RW, .accessfn = access_tacr, |
8240 | .type = ARM_CP_CONST, .resetvalue = cpu->reset_auxcr }, | |
834a6c69 PM |
8241 | { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, |
8242 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, | |
8243 | .access = PL2_RW, .type = ARM_CP_CONST, | |
8244 | .resetvalue = 0 }, | |
8245 | { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, | |
8246 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, | |
8247 | .access = PL3_RW, .type = ARM_CP_CONST, | |
8248 | .resetvalue = 0 }, | |
2771db27 | 8249 | }; |
834a6c69 | 8250 | define_arm_cp_regs(cpu, auxcr_reginfo); |
f6287c24 PM |
8251 | if (cpu_isar_feature(aa32_ac2, cpu)) { |
8252 | define_arm_cp_regs(cpu, actlr2_hactlr2_reginfo); | |
0e0456ab | 8253 | } |
2771db27 PM |
8254 | } |
8255 | ||
d8ba780b | 8256 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
d56974af LM |
8257 | /* |
8258 | * CBAR is IMPDEF, but common on Arm Cortex-A implementations. | |
8259 | * There are two flavours: | |
8260 | * (1) older 32-bit only cores have a simple 32-bit CBAR | |
8261 | * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a | |
8262 | * 32-bit register visible to AArch32 at a different encoding | |
8263 | * to the "flavour 1" register and with the bits rearranged to | |
8264 | * be able to squash a 64-bit address into the 32-bit view. | |
8265 | * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but | |
8266 | * in future if we support AArch32-only configs of some of the | |
8267 | * AArch64 cores we might need to add a specific feature flag | |
8268 | * to indicate cores with "flavour 2" CBAR. | |
8269 | */ | |
f318cec6 PM |
8270 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
8271 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | |
8272 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | |
8273 | | extract64(cpu->reset_cbar, 32, 12); | |
8274 | ARMCPRegInfo cbar_reginfo[] = { | |
8275 | { .name = "CBAR", | |
8276 | .type = ARM_CP_CONST, | |
d56974af LM |
8277 | .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0, |
8278 | .access = PL1_R, .resetvalue = cbar32 }, | |
f318cec6 PM |
8279 | { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, |
8280 | .type = ARM_CP_CONST, | |
8281 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | |
d56974af | 8282 | .access = PL1_R, .resetvalue = cpu->reset_cbar }, |
f318cec6 PM |
8283 | }; |
8284 | /* We don't implement a r/w 64 bit CBAR currently */ | |
8285 | assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); | |
8286 | define_arm_cp_regs(cpu, cbar_reginfo); | |
8287 | } else { | |
8288 | ARMCPRegInfo cbar = { | |
8289 | .name = "CBAR", | |
8290 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
8291 | .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, | |
8292 | .fieldoffset = offsetof(CPUARMState, | |
8293 | cp15.c15_config_base_address) | |
8294 | }; | |
8295 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | |
8296 | cbar.access = PL1_R; | |
8297 | cbar.fieldoffset = 0; | |
8298 | cbar.type = ARM_CP_CONST; | |
8299 | } | |
8300 | define_one_arm_cp_reg(cpu, &cbar); | |
8301 | } | |
d8ba780b PC |
8302 | } |
8303 | ||
91db4642 | 8304 | if (arm_feature(env, ARM_FEATURE_VBAR)) { |
10b0220e | 8305 | static const ARMCPRegInfo vbar_cp_reginfo[] = { |
91db4642 CLG |
8306 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, |
8307 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | |
8308 | .access = PL1_RW, .writefn = vbar_write, | |
8309 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), | |
8310 | offsetof(CPUARMState, cp15.vbar_ns) }, | |
8311 | .resetvalue = 0 }, | |
91db4642 CLG |
8312 | }; |
8313 | define_arm_cp_regs(cpu, vbar_cp_reginfo); | |
8314 | } | |
8315 | ||
2771db27 PM |
8316 | /* Generic registers whose values depend on the implementation */ |
8317 | { | |
8318 | ARMCPRegInfo sctlr = { | |
5ebafdf3 | 8319 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, |
137feaa9 | 8320 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, |
84929218 | 8321 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
137feaa9 FA |
8322 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), |
8323 | offsetof(CPUARMState, cp15.sctlr_ns) }, | |
d4e6df63 PM |
8324 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, |
8325 | .raw_writefn = raw_write, | |
2771db27 PM |
8326 | }; |
8327 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
8328 | /* Normally we would always end the TB on an SCTLR write, but Linux | |
8329 | * arch/arm/mach-pxa/sleep.S expects two instructions following | |
8330 | * an MMU enable to execute from cache. Imitate this behaviour. | |
8331 | */ | |
8332 | sctlr.type |= ARM_CP_SUPPRESS_TB_END; | |
8333 | } | |
8334 | define_one_arm_cp_reg(cpu, &sctlr); | |
8335 | } | |
5be5e8ed | 8336 | |
2d7137c1 | 8337 | if (cpu_isar_feature(aa64_lor, cpu)) { |
2d7137c1 RH |
8338 | define_arm_cp_regs(cpu, lor_reginfo); |
8339 | } | |
220f508f RH |
8340 | if (cpu_isar_feature(aa64_pan, cpu)) { |
8341 | define_one_arm_cp_reg(cpu, &pan_reginfo); | |
8342 | } | |
04b07d29 RH |
8343 | #ifndef CONFIG_USER_ONLY |
8344 | if (cpu_isar_feature(aa64_ats1e1, cpu)) { | |
8345 | define_arm_cp_regs(cpu, ats1e1_reginfo); | |
8346 | } | |
8347 | if (cpu_isar_feature(aa32_ats1e1, cpu)) { | |
8348 | define_arm_cp_regs(cpu, ats1cp_reginfo); | |
8349 | } | |
8350 | #endif | |
9eeb7a1c RH |
8351 | if (cpu_isar_feature(aa64_uao, cpu)) { |
8352 | define_one_arm_cp_reg(cpu, &uao_reginfo); | |
8353 | } | |
2d7137c1 | 8354 | |
dc8b1853 RC |
8355 | if (cpu_isar_feature(aa64_dit, cpu)) { |
8356 | define_one_arm_cp_reg(cpu, &dit_reginfo); | |
8357 | } | |
f2f68a78 RC |
8358 | if (cpu_isar_feature(aa64_ssbs, cpu)) { |
8359 | define_one_arm_cp_reg(cpu, &ssbs_reginfo); | |
8360 | } | |
dc8b1853 | 8361 | |
e2a1a461 RH |
8362 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { |
8363 | define_arm_cp_regs(cpu, vhe_reginfo); | |
8364 | } | |
8365 | ||
cd208a1c | 8366 | if (cpu_isar_feature(aa64_sve, cpu)) { |
5be5e8ed RH |
8367 | define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); |
8368 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
8369 | define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); | |
8370 | } else { | |
8371 | define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo); | |
8372 | } | |
8373 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
8374 | define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); | |
8375 | } | |
8376 | } | |
967aa94f RH |
8377 | |
8378 | #ifdef TARGET_AARCH64 | |
8379 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
8380 | define_arm_cp_regs(cpu, pauth_reginfo); | |
8381 | } | |
de390645 RH |
8382 | if (cpu_isar_feature(aa64_rndr, cpu)) { |
8383 | define_arm_cp_regs(cpu, rndr_reginfo); | |
8384 | } | |
84940ed8 RC |
8385 | if (cpu_isar_feature(aa64_tlbirange, cpu)) { |
8386 | define_arm_cp_regs(cpu, tlbirange_reginfo); | |
8387 | } | |
7113d618 RC |
8388 | if (cpu_isar_feature(aa64_tlbios, cpu)) { |
8389 | define_arm_cp_regs(cpu, tlbios_reginfo); | |
8390 | } | |
0d57b499 BM |
8391 | #ifndef CONFIG_USER_ONLY |
8392 | /* Data Cache clean instructions up to PoP */ | |
8393 | if (cpu_isar_feature(aa64_dcpop, cpu)) { | |
8394 | define_one_arm_cp_reg(cpu, dcpop_reg); | |
8395 | ||
8396 | if (cpu_isar_feature(aa64_dcpodp, cpu)) { | |
8397 | define_one_arm_cp_reg(cpu, dcpodp_reg); | |
8398 | } | |
8399 | } | |
8400 | #endif /*CONFIG_USER_ONLY*/ | |
4b779ceb RH |
8401 | |
8402 | /* | |
8403 | * If full MTE is enabled, add all of the system registers. | |
8404 | * If only "instructions available at EL0" are enabled, | |
8405 | * then define only a RAZ/WI version of PSTATE.TCO. | |
8406 | */ | |
8407 | if (cpu_isar_feature(aa64_mte, cpu)) { | |
8408 | define_arm_cp_regs(cpu, mte_reginfo); | |
5463df16 | 8409 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); |
4b779ceb RH |
8410 | } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { |
8411 | define_arm_cp_regs(cpu, mte_tco_ro_reginfo); | |
5463df16 | 8412 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); |
4b779ceb | 8413 | } |
967aa94f | 8414 | #endif |
cb570bd3 | 8415 | |
22e57073 | 8416 | if (cpu_isar_feature(any_predinv, cpu)) { |
cb570bd3 RH |
8417 | define_arm_cp_regs(cpu, predinv_reginfo); |
8418 | } | |
e2cce18f | 8419 | |
957e6155 PM |
8420 | if (cpu_isar_feature(any_ccidx, cpu)) { |
8421 | define_arm_cp_regs(cpu, ccsidr2_reginfo); | |
8422 | } | |
8423 | ||
e2cce18f RH |
8424 | #ifndef CONFIG_USER_ONLY |
8425 | /* | |
8426 | * Register redirections and aliases must be done last, | |
8427 | * after the registers from the other extensions have been defined. | |
8428 | */ | |
8429 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { | |
8430 | define_arm_vh_e2h_redirects_aliases(cpu); | |
8431 | } | |
8432 | #endif | |
2ceb98c0 PM |
8433 | } |
8434 | ||
777dc784 PM |
8435 | /* Sort alphabetically by type name, except for "any". */ |
8436 | static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) | |
5adb4839 | 8437 | { |
777dc784 PM |
8438 | ObjectClass *class_a = (ObjectClass *)a; |
8439 | ObjectClass *class_b = (ObjectClass *)b; | |
8440 | const char *name_a, *name_b; | |
5adb4839 | 8441 | |
777dc784 PM |
8442 | name_a = object_class_get_name(class_a); |
8443 | name_b = object_class_get_name(class_b); | |
51492fd1 | 8444 | if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 | 8445 | return 1; |
51492fd1 | 8446 | } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 PM |
8447 | return -1; |
8448 | } else { | |
8449 | return strcmp(name_a, name_b); | |
5adb4839 PB |
8450 | } |
8451 | } | |
8452 | ||
777dc784 | 8453 | static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
40f137e1 | 8454 | { |
777dc784 | 8455 | ObjectClass *oc = data; |
51492fd1 AF |
8456 | const char *typename; |
8457 | char *name; | |
3371d272 | 8458 | |
51492fd1 AF |
8459 | typename = object_class_get_name(oc); |
8460 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
0442428a | 8461 | qemu_printf(" %s\n", name); |
51492fd1 | 8462 | g_free(name); |
777dc784 PM |
8463 | } |
8464 | ||
0442428a | 8465 | void arm_cpu_list(void) |
777dc784 | 8466 | { |
777dc784 PM |
8467 | GSList *list; |
8468 | ||
8469 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
8470 | list = g_slist_sort(list, arm_cpu_list_compare); | |
0442428a MA |
8471 | qemu_printf("Available CPUs:\n"); |
8472 | g_slist_foreach(list, arm_cpu_list_entry, NULL); | |
777dc784 | 8473 | g_slist_free(list); |
40f137e1 PB |
8474 | } |
8475 | ||
78027bb6 CR |
8476 | static void arm_cpu_add_definition(gpointer data, gpointer user_data) |
8477 | { | |
8478 | ObjectClass *oc = data; | |
8479 | CpuDefinitionInfoList **cpu_list = user_data; | |
78027bb6 CR |
8480 | CpuDefinitionInfo *info; |
8481 | const char *typename; | |
8482 | ||
8483 | typename = object_class_get_name(oc); | |
8484 | info = g_malloc0(sizeof(*info)); | |
8485 | info->name = g_strndup(typename, | |
8486 | strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
8ed877b7 | 8487 | info->q_typename = g_strdup(typename); |
78027bb6 | 8488 | |
54aa3de7 | 8489 | QAPI_LIST_PREPEND(*cpu_list, info); |
78027bb6 CR |
8490 | } |
8491 | ||
25a9d6ca | 8492 | CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) |
78027bb6 CR |
8493 | { |
8494 | CpuDefinitionInfoList *cpu_list = NULL; | |
8495 | GSList *list; | |
8496 | ||
8497 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
8498 | g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); | |
8499 | g_slist_free(list); | |
8500 | ||
8501 | return cpu_list; | |
8502 | } | |
8503 | ||
6e6efd61 | 8504 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
51a79b03 | 8505 | void *opaque, int state, int secstate, |
9c513e78 AB |
8506 | int crm, int opc1, int opc2, |
8507 | const char *name) | |
6e6efd61 PM |
8508 | { |
8509 | /* Private utility function for define_one_arm_cp_reg_with_opaque(): | |
8510 | * add a single reginfo struct to the hash table. | |
8511 | */ | |
8512 | uint32_t *key = g_new(uint32_t, 1); | |
8513 | ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); | |
8514 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | |
3f3c82a5 FA |
8515 | int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; |
8516 | ||
9c513e78 | 8517 | r2->name = g_strdup(name); |
3f3c82a5 FA |
8518 | /* Reset the secure state to the specific incoming state. This is |
8519 | * necessary as the register may have been defined with both states. | |
8520 | */ | |
8521 | r2->secure = secstate; | |
8522 | ||
8523 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
8524 | /* Register is banked (using both entries in array). | |
8525 | * Overwriting fieldoffset as the array is only used to define | |
8526 | * banked registers but later only fieldoffset is used. | |
f5a0a5a5 | 8527 | */ |
3f3c82a5 FA |
8528 | r2->fieldoffset = r->bank_fieldoffsets[ns]; |
8529 | } | |
8530 | ||
8531 | if (state == ARM_CP_STATE_AA32) { | |
8532 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
8533 | /* If the register is banked then we don't need to migrate or | |
8534 | * reset the 32-bit instance in certain cases: | |
8535 | * | |
8536 | * 1) If the register has both 32-bit and 64-bit instances then we | |
8537 | * can count on the 64-bit instance taking care of the | |
8538 | * non-secure bank. | |
8539 | * 2) If ARMv8 is enabled then we can count on a 64-bit version | |
8540 | * taking care of the secure bank. This requires that separate | |
8541 | * 32 and 64-bit definitions are provided. | |
8542 | */ | |
8543 | if ((r->state == ARM_CP_STATE_BOTH && ns) || | |
8544 | (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { | |
7a0e58fa | 8545 | r2->type |= ARM_CP_ALIAS; |
3f3c82a5 FA |
8546 | } |
8547 | } else if ((secstate != r->secure) && !ns) { | |
8548 | /* The register is not banked so we only want to allow migration of | |
8549 | * the non-secure instance. | |
8550 | */ | |
7a0e58fa | 8551 | r2->type |= ARM_CP_ALIAS; |
58a1d8ce | 8552 | } |
3f3c82a5 FA |
8553 | |
8554 | if (r->state == ARM_CP_STATE_BOTH) { | |
8555 | /* We assume it is a cp15 register if the .cp field is left unset. | |
8556 | */ | |
8557 | if (r2->cp == 0) { | |
8558 | r2->cp = 15; | |
8559 | } | |
8560 | ||
e03b5686 | 8561 | #if HOST_BIG_ENDIAN |
3f3c82a5 FA |
8562 | if (r2->fieldoffset) { |
8563 | r2->fieldoffset += sizeof(uint32_t); | |
8564 | } | |
f5a0a5a5 | 8565 | #endif |
3f3c82a5 | 8566 | } |
f5a0a5a5 PM |
8567 | } |
8568 | if (state == ARM_CP_STATE_AA64) { | |
8569 | /* To allow abbreviation of ARMCPRegInfo | |
8570 | * definitions, we treat cp == 0 as equivalent to | |
8571 | * the value for "standard guest-visible sysreg". | |
58a1d8ce PM |
8572 | * STATE_BOTH definitions are also always "standard |
8573 | * sysreg" in their AArch64 view (the .cp value may | |
8574 | * be non-zero for the benefit of the AArch32 view). | |
f5a0a5a5 | 8575 | */ |
58a1d8ce | 8576 | if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { |
f5a0a5a5 PM |
8577 | r2->cp = CP_REG_ARM64_SYSREG_CP; |
8578 | } | |
8579 | *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | |
8580 | r2->opc0, opc1, opc2); | |
8581 | } else { | |
51a79b03 | 8582 | *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); |
f5a0a5a5 | 8583 | } |
6e6efd61 PM |
8584 | if (opaque) { |
8585 | r2->opaque = opaque; | |
8586 | } | |
67ed771d PM |
8587 | /* reginfo passed to helpers is correct for the actual access, |
8588 | * and is never ARM_CP_STATE_BOTH: | |
8589 | */ | |
8590 | r2->state = state; | |
6e6efd61 PM |
8591 | /* Make sure reginfo passed to helpers for wildcarded regs |
8592 | * has the correct crm/opc1/opc2 for this reg, not CP_ANY: | |
8593 | */ | |
8594 | r2->crm = crm; | |
8595 | r2->opc1 = opc1; | |
8596 | r2->opc2 = opc2; | |
8597 | /* By convention, for wildcarded registers only the first | |
8598 | * entry is used for migration; the others are marked as | |
7a0e58fa | 8599 | * ALIAS so we don't try to transfer the register |
6e6efd61 | 8600 | * multiple times. Special registers (ie NOP/WFI) are |
7a0e58fa | 8601 | * never migratable and not even raw-accessible. |
6e6efd61 | 8602 | */ |
7a0e58fa PM |
8603 | if ((r->type & ARM_CP_SPECIAL)) { |
8604 | r2->type |= ARM_CP_NO_RAW; | |
8605 | } | |
8606 | if (((r->crm == CP_ANY) && crm != 0) || | |
6e6efd61 PM |
8607 | ((r->opc1 == CP_ANY) && opc1 != 0) || |
8608 | ((r->opc2 == CP_ANY) && opc2 != 0)) { | |
1f163787 | 8609 | r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB; |
6e6efd61 PM |
8610 | } |
8611 | ||
375421cc PM |
8612 | /* Check that raw accesses are either forbidden or handled. Note that |
8613 | * we can't assert this earlier because the setup of fieldoffset for | |
8614 | * banked registers has to be done first. | |
8615 | */ | |
8616 | if (!(r2->type & ARM_CP_NO_RAW)) { | |
8617 | assert(!raw_accessors_invalid(r2)); | |
8618 | } | |
8619 | ||
6e6efd61 PM |
8620 | /* Overriding of an existing definition must be explicitly |
8621 | * requested. | |
8622 | */ | |
8623 | if (!(r->type & ARM_CP_OVERRIDE)) { | |
8624 | ARMCPRegInfo *oldreg; | |
8625 | oldreg = g_hash_table_lookup(cpu->cp_regs, key); | |
8626 | if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { | |
8627 | fprintf(stderr, "Register redefined: cp=%d %d bit " | |
8628 | "crn=%d crm=%d opc1=%d opc2=%d, " | |
8629 | "was %s, now %s\n", r2->cp, 32 + 32 * is64, | |
8630 | r2->crn, r2->crm, r2->opc1, r2->opc2, | |
8631 | oldreg->name, r2->name); | |
8632 | g_assert_not_reached(); | |
8633 | } | |
8634 | } | |
8635 | g_hash_table_insert(cpu->cp_regs, key, r2); | |
8636 | } | |
8637 | ||
8638 | ||
4b6a83fb PM |
8639 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
8640 | const ARMCPRegInfo *r, void *opaque) | |
8641 | { | |
8642 | /* Define implementations of coprocessor registers. | |
8643 | * We store these in a hashtable because typically | |
8644 | * there are less than 150 registers in a space which | |
8645 | * is 16*16*16*8*8 = 262144 in size. | |
8646 | * Wildcarding is supported for the crm, opc1 and opc2 fields. | |
8647 | * If a register is defined twice then the second definition is | |
8648 | * used, so this can be used to define some generic registers and | |
8649 | * then override them with implementation specific variations. | |
8650 | * At least one of the original and the second definition should | |
8651 | * include ARM_CP_OVERRIDE in its type bits -- this is just a guard | |
8652 | * against accidental use. | |
f5a0a5a5 PM |
8653 | * |
8654 | * The state field defines whether the register is to be | |
8655 | * visible in the AArch32 or AArch64 execution state. If the | |
8656 | * state is set to ARM_CP_STATE_BOTH then we synthesise a | |
8657 | * reginfo structure for the AArch32 view, which sees the lower | |
8658 | * 32 bits of the 64 bit register. | |
8659 | * | |
8660 | * Only registers visible in AArch64 may set r->opc0; opc0 cannot | |
8661 | * be wildcarded. AArch64 registers are always considered to be 64 | |
8662 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | |
8663 | * the register, if any. | |
4b6a83fb | 8664 | */ |
f5a0a5a5 | 8665 | int crm, opc1, opc2, state; |
4b6a83fb PM |
8666 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
8667 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | |
8668 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | |
8669 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | |
8670 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | |
8671 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | |
8672 | /* 64 bit registers have only CRm and Opc1 fields */ | |
8673 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | |
f5a0a5a5 PM |
8674 | /* op0 only exists in the AArch64 encodings */ |
8675 | assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); | |
8676 | /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ | |
8677 | assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); | |
cd8be50e PM |
8678 | /* |
8679 | * This API is only for Arm's system coprocessors (14 and 15) or | |
8680 | * (M-profile or v7A-and-earlier only) for implementation defined | |
8681 | * coprocessors in the range 0..7. Our decode assumes this, since | |
8682 | * 8..13 can be used for other insns including VFP and Neon. See | |
8683 | * valid_cp() in translate.c. Assert here that we haven't tried | |
8684 | * to use an invalid coprocessor number. | |
8685 | */ | |
8686 | switch (r->state) { | |
8687 | case ARM_CP_STATE_BOTH: | |
8688 | /* 0 has a special meaning, but otherwise the same rules as AA32. */ | |
8689 | if (r->cp == 0) { | |
8690 | break; | |
8691 | } | |
8692 | /* fall through */ | |
8693 | case ARM_CP_STATE_AA32: | |
8694 | if (arm_feature(&cpu->env, ARM_FEATURE_V8) && | |
8695 | !arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
8696 | assert(r->cp >= 14 && r->cp <= 15); | |
8697 | } else { | |
8698 | assert(r->cp < 8 || (r->cp >= 14 && r->cp <= 15)); | |
8699 | } | |
8700 | break; | |
8701 | case ARM_CP_STATE_AA64: | |
8702 | assert(r->cp == 0 || r->cp == CP_REG_ARM64_SYSREG_CP); | |
8703 | break; | |
8704 | default: | |
8705 | g_assert_not_reached(); | |
8706 | } | |
f5a0a5a5 PM |
8707 | /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 |
8708 | * encodes a minimum access level for the register. We roll this | |
8709 | * runtime check into our general permission check code, so check | |
8710 | * here that the reginfo's specified permissions are strict enough | |
8711 | * to encompass the generic architectural permission check. | |
8712 | */ | |
8713 | if (r->state != ARM_CP_STATE_AA32) { | |
8714 | int mask = 0; | |
8715 | switch (r->opc1) { | |
b5bd7440 AB |
8716 | case 0: |
8717 | /* min_EL EL1, but some accessible to EL0 via kernel ABI */ | |
8718 | mask = PL0U_R | PL1_RW; | |
8719 | break; | |
8720 | case 1: case 2: | |
f5a0a5a5 PM |
8721 | /* min_EL EL1 */ |
8722 | mask = PL1_RW; | |
8723 | break; | |
8724 | case 3: | |
8725 | /* min_EL EL0 */ | |
8726 | mask = PL0_RW; | |
8727 | break; | |
8728 | case 4: | |
b4ecf60f | 8729 | case 5: |
f5a0a5a5 PM |
8730 | /* min_EL EL2 */ |
8731 | mask = PL2_RW; | |
8732 | break; | |
f5a0a5a5 PM |
8733 | case 6: |
8734 | /* min_EL EL3 */ | |
8735 | mask = PL3_RW; | |
8736 | break; | |
8737 | case 7: | |
8738 | /* min_EL EL1, secure mode only (we don't check the latter) */ | |
8739 | mask = PL1_RW; | |
8740 | break; | |
8741 | default: | |
8742 | /* broken reginfo with out-of-range opc1 */ | |
8743 | assert(false); | |
8744 | break; | |
8745 | } | |
8746 | /* assert our permissions are not too lax (stricter is fine) */ | |
8747 | assert((r->access & ~mask) == 0); | |
8748 | } | |
8749 | ||
4b6a83fb PM |
8750 | /* Check that the register definition has enough info to handle |
8751 | * reads and writes if they are permitted. | |
8752 | */ | |
8753 | if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { | |
8754 | if (r->access & PL3_R) { | |
3f3c82a5 FA |
8755 | assert((r->fieldoffset || |
8756 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
8757 | r->readfn); | |
4b6a83fb PM |
8758 | } |
8759 | if (r->access & PL3_W) { | |
3f3c82a5 FA |
8760 | assert((r->fieldoffset || |
8761 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
8762 | r->writefn); | |
4b6a83fb PM |
8763 | } |
8764 | } | |
5809ac57 | 8765 | |
4b6a83fb PM |
8766 | for (crm = crmmin; crm <= crmmax; crm++) { |
8767 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | |
8768 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | |
f5a0a5a5 PM |
8769 | for (state = ARM_CP_STATE_AA32; |
8770 | state <= ARM_CP_STATE_AA64; state++) { | |
8771 | if (r->state != state && r->state != ARM_CP_STATE_BOTH) { | |
8772 | continue; | |
8773 | } | |
3f3c82a5 FA |
8774 | if (state == ARM_CP_STATE_AA32) { |
8775 | /* Under AArch32 CP registers can be common | |
8776 | * (same for secure and non-secure world) or banked. | |
8777 | */ | |
9c513e78 AB |
8778 | char *name; |
8779 | ||
3f3c82a5 FA |
8780 | switch (r->secure) { |
8781 | case ARM_CP_SECSTATE_S: | |
8782 | case ARM_CP_SECSTATE_NS: | |
8783 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
9c513e78 AB |
8784 | r->secure, crm, opc1, opc2, |
8785 | r->name); | |
3f3c82a5 FA |
8786 | break; |
8787 | default: | |
9c513e78 | 8788 | name = g_strdup_printf("%s_S", r->name); |
3f3c82a5 FA |
8789 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
8790 | ARM_CP_SECSTATE_S, | |
9c513e78 AB |
8791 | crm, opc1, opc2, name); |
8792 | g_free(name); | |
3f3c82a5 FA |
8793 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
8794 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 8795 | crm, opc1, opc2, r->name); |
3f3c82a5 FA |
8796 | break; |
8797 | } | |
8798 | } else { | |
8799 | /* AArch64 registers get mapped to non-secure instance | |
8800 | * of AArch32 */ | |
8801 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
8802 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 8803 | crm, opc1, opc2, r->name); |
3f3c82a5 | 8804 | } |
f5a0a5a5 | 8805 | } |
4b6a83fb PM |
8806 | } |
8807 | } | |
8808 | } | |
8809 | } | |
8810 | ||
5809ac57 RH |
8811 | /* Define a whole list of registers */ |
8812 | void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs, | |
8813 | void *opaque, size_t len) | |
4b6a83fb | 8814 | { |
5809ac57 RH |
8815 | size_t i; |
8816 | for (i = 0; i < len; ++i) { | |
8817 | define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque); | |
4b6a83fb PM |
8818 | } |
8819 | } | |
8820 | ||
6c5c0fec AB |
8821 | /* |
8822 | * Modify ARMCPRegInfo for access from userspace. | |
8823 | * | |
8824 | * This is a data driven modification directed by | |
8825 | * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as | |
8826 | * user-space cannot alter any values and dynamic values pertaining to | |
8827 | * execution state are hidden from user space view anyway. | |
8828 | */ | |
5809ac57 RH |
8829 | void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, |
8830 | const ARMCPRegUserSpaceInfo *mods, | |
8831 | size_t mods_len) | |
6c5c0fec | 8832 | { |
5809ac57 RH |
8833 | for (size_t mi = 0; mi < mods_len; ++mi) { |
8834 | const ARMCPRegUserSpaceInfo *m = mods + mi; | |
d040242e | 8835 | GPatternSpec *pat = NULL; |
5809ac57 | 8836 | |
d040242e AB |
8837 | if (m->is_glob) { |
8838 | pat = g_pattern_spec_new(m->name); | |
8839 | } | |
5809ac57 RH |
8840 | for (size_t ri = 0; ri < regs_len; ++ri) { |
8841 | ARMCPRegInfo *r = regs + ri; | |
8842 | ||
d040242e AB |
8843 | if (pat && g_pattern_match_string(pat, r->name)) { |
8844 | r->type = ARM_CP_CONST; | |
8845 | r->access = PL0U_R; | |
8846 | r->resetvalue = 0; | |
8847 | /* continue */ | |
8848 | } else if (strcmp(r->name, m->name) == 0) { | |
6c5c0fec AB |
8849 | r->type = ARM_CP_CONST; |
8850 | r->access = PL0U_R; | |
8851 | r->resetvalue &= m->exported_bits; | |
8852 | r->resetvalue |= m->fixed_bits; | |
8853 | break; | |
8854 | } | |
8855 | } | |
d040242e AB |
8856 | if (pat) { |
8857 | g_pattern_spec_free(pat); | |
8858 | } | |
6c5c0fec AB |
8859 | } |
8860 | } | |
8861 | ||
60322b39 | 8862 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) |
4b6a83fb | 8863 | { |
60322b39 | 8864 | return g_hash_table_lookup(cpregs, &encoded_cp); |
4b6a83fb PM |
8865 | } |
8866 | ||
c4241c7d PM |
8867 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
8868 | uint64_t value) | |
4b6a83fb PM |
8869 | { |
8870 | /* Helper coprocessor write function for write-ignore registers */ | |
4b6a83fb PM |
8871 | } |
8872 | ||
c4241c7d | 8873 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) |
4b6a83fb PM |
8874 | { |
8875 | /* Helper coprocessor write function for read-as-zero registers */ | |
4b6a83fb PM |
8876 | return 0; |
8877 | } | |
8878 | ||
f5a0a5a5 PM |
8879 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) |
8880 | { | |
8881 | /* Helper coprocessor reset function for do-nothing-on-reset registers */ | |
8882 | } | |
8883 | ||
af393ffc | 8884 | static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) |
37064a8b PM |
8885 | { |
8886 | /* Return true if it is not valid for us to switch to | |
8887 | * this CPU mode (ie all the UNPREDICTABLE cases in | |
8888 | * the ARM ARM CPSRWriteByInstr pseudocode). | |
8889 | */ | |
af393ffc PM |
8890 | |
8891 | /* Changes to or from Hyp via MSR and CPS are illegal. */ | |
8892 | if (write_type == CPSRWriteByInstr && | |
8893 | ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || | |
8894 | mode == ARM_CPU_MODE_HYP)) { | |
8895 | return 1; | |
8896 | } | |
8897 | ||
37064a8b PM |
8898 | switch (mode) { |
8899 | case ARM_CPU_MODE_USR: | |
10eacda7 | 8900 | return 0; |
37064a8b PM |
8901 | case ARM_CPU_MODE_SYS: |
8902 | case ARM_CPU_MODE_SVC: | |
8903 | case ARM_CPU_MODE_ABT: | |
8904 | case ARM_CPU_MODE_UND: | |
8905 | case ARM_CPU_MODE_IRQ: | |
8906 | case ARM_CPU_MODE_FIQ: | |
52ff951b PM |
8907 | /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 |
8908 | * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) | |
8909 | */ | |
10eacda7 PM |
8910 | /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR |
8911 | * and CPS are treated as illegal mode changes. | |
8912 | */ | |
8913 | if (write_type == CPSRWriteByInstr && | |
10eacda7 | 8914 | (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && |
7c208e0f | 8915 | (arm_hcr_el2_eff(env) & HCR_TGE)) { |
10eacda7 PM |
8916 | return 1; |
8917 | } | |
37064a8b | 8918 | return 0; |
e6c8fc07 | 8919 | case ARM_CPU_MODE_HYP: |
e6ef0169 | 8920 | return !arm_is_el2_enabled(env) || arm_current_el(env) < 2; |
027fc527 | 8921 | case ARM_CPU_MODE_MON: |
58ae2d1f | 8922 | return arm_current_el(env) < 3; |
37064a8b PM |
8923 | default: |
8924 | return 1; | |
8925 | } | |
8926 | } | |
8927 | ||
2f4a40e5 AZ |
8928 | uint32_t cpsr_read(CPUARMState *env) |
8929 | { | |
8930 | int ZF; | |
6fbe23d5 PB |
8931 | ZF = (env->ZF == 0); |
8932 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
8933 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
8934 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
8935 | | ((env->condexec_bits & 0xfc) << 8) | |
af519934 | 8936 | | (env->GE << 16) | (env->daif & CPSR_AIF); |
2f4a40e5 AZ |
8937 | } |
8938 | ||
50866ba5 PM |
8939 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, |
8940 | CPSRWriteType write_type) | |
2f4a40e5 | 8941 | { |
6e8801f9 | 8942 | uint32_t changed_daif; |
e784807c PM |
8943 | bool rebuild_hflags = (write_type != CPSRWriteRaw) && |
8944 | (mask & (CPSR_M | CPSR_E | CPSR_IL)); | |
6e8801f9 | 8945 | |
2f4a40e5 | 8946 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
8947 | env->ZF = (~val) & CPSR_Z; |
8948 | env->NF = val; | |
2f4a40e5 AZ |
8949 | env->CF = (val >> 29) & 1; |
8950 | env->VF = (val << 3) & 0x80000000; | |
8951 | } | |
8952 | if (mask & CPSR_Q) | |
8953 | env->QF = ((val & CPSR_Q) != 0); | |
8954 | if (mask & CPSR_T) | |
8955 | env->thumb = ((val & CPSR_T) != 0); | |
8956 | if (mask & CPSR_IT_0_1) { | |
8957 | env->condexec_bits &= ~3; | |
8958 | env->condexec_bits |= (val >> 25) & 3; | |
8959 | } | |
8960 | if (mask & CPSR_IT_2_7) { | |
8961 | env->condexec_bits &= 3; | |
8962 | env->condexec_bits |= (val >> 8) & 0xfc; | |
8963 | } | |
8964 | if (mask & CPSR_GE) { | |
8965 | env->GE = (val >> 16) & 0xf; | |
8966 | } | |
8967 | ||
6e8801f9 FA |
8968 | /* In a V7 implementation that includes the security extensions but does |
8969 | * not include Virtualization Extensions the SCR.FW and SCR.AW bits control | |
8970 | * whether non-secure software is allowed to change the CPSR_F and CPSR_A | |
8971 | * bits respectively. | |
8972 | * | |
8973 | * In a V8 implementation, it is permitted for privileged software to | |
8974 | * change the CPSR A/F bits regardless of the SCR.AW/FW bits. | |
8975 | */ | |
f8c88bbc | 8976 | if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && |
6e8801f9 FA |
8977 | arm_feature(env, ARM_FEATURE_EL3) && |
8978 | !arm_feature(env, ARM_FEATURE_EL2) && | |
8979 | !arm_is_secure(env)) { | |
8980 | ||
8981 | changed_daif = (env->daif ^ val) & mask; | |
8982 | ||
8983 | if (changed_daif & CPSR_A) { | |
8984 | /* Check to see if we are allowed to change the masking of async | |
8985 | * abort exceptions from a non-secure state. | |
8986 | */ | |
8987 | if (!(env->cp15.scr_el3 & SCR_AW)) { | |
8988 | qemu_log_mask(LOG_GUEST_ERROR, | |
8989 | "Ignoring attempt to switch CPSR_A flag from " | |
8990 | "non-secure world with SCR.AW bit clear\n"); | |
8991 | mask &= ~CPSR_A; | |
8992 | } | |
8993 | } | |
8994 | ||
8995 | if (changed_daif & CPSR_F) { | |
8996 | /* Check to see if we are allowed to change the masking of FIQ | |
8997 | * exceptions from a non-secure state. | |
8998 | */ | |
8999 | if (!(env->cp15.scr_el3 & SCR_FW)) { | |
9000 | qemu_log_mask(LOG_GUEST_ERROR, | |
9001 | "Ignoring attempt to switch CPSR_F flag from " | |
9002 | "non-secure world with SCR.FW bit clear\n"); | |
9003 | mask &= ~CPSR_F; | |
9004 | } | |
9005 | ||
9006 | /* Check whether non-maskable FIQ (NMFI) support is enabled. | |
9007 | * If this bit is set software is not allowed to mask | |
9008 | * FIQs, but is allowed to set CPSR_F to 0. | |
9009 | */ | |
9010 | if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && | |
9011 | (val & CPSR_F)) { | |
9012 | qemu_log_mask(LOG_GUEST_ERROR, | |
9013 | "Ignoring attempt to enable CPSR_F flag " | |
9014 | "(non-maskable FIQ [NMFI] support enabled)\n"); | |
9015 | mask &= ~CPSR_F; | |
9016 | } | |
9017 | } | |
9018 | } | |
9019 | ||
4cc35614 PM |
9020 | env->daif &= ~(CPSR_AIF & mask); |
9021 | env->daif |= val & CPSR_AIF & mask; | |
9022 | ||
f8c88bbc PM |
9023 | if (write_type != CPSRWriteRaw && |
9024 | ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { | |
8c4f0eb9 PM |
9025 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { |
9026 | /* Note that we can only get here in USR mode if this is a | |
9027 | * gdb stub write; for this case we follow the architectural | |
9028 | * behaviour for guest writes in USR mode of ignoring an attempt | |
9029 | * to switch mode. (Those are caught by translate.c for writes | |
9030 | * triggered by guest instructions.) | |
9031 | */ | |
9032 | mask &= ~CPSR_M; | |
9033 | } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { | |
81907a58 PM |
9034 | /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in |
9035 | * v7, and has defined behaviour in v8: | |
9036 | * + leave CPSR.M untouched | |
9037 | * + allow changes to the other CPSR fields | |
9038 | * + set PSTATE.IL | |
9039 | * For user changes via the GDB stub, we don't set PSTATE.IL, | |
9040 | * as this would be unnecessarily harsh for a user error. | |
37064a8b PM |
9041 | */ |
9042 | mask &= ~CPSR_M; | |
81907a58 PM |
9043 | if (write_type != CPSRWriteByGDBStub && |
9044 | arm_feature(env, ARM_FEATURE_V8)) { | |
9045 | mask |= CPSR_IL; | |
9046 | val |= CPSR_IL; | |
9047 | } | |
81e37284 PM |
9048 | qemu_log_mask(LOG_GUEST_ERROR, |
9049 | "Illegal AArch32 mode switch attempt from %s to %s\n", | |
9050 | aarch32_mode_name(env->uncached_cpsr), | |
9051 | aarch32_mode_name(val)); | |
37064a8b | 9052 | } else { |
81e37284 PM |
9053 | qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n", |
9054 | write_type == CPSRWriteExceptionReturn ? | |
9055 | "Exception return from AArch32" : | |
9056 | "AArch32 mode switch from", | |
9057 | aarch32_mode_name(env->uncached_cpsr), | |
9058 | aarch32_mode_name(val), env->regs[15]); | |
37064a8b PM |
9059 | switch_mode(env, val & CPSR_M); |
9060 | } | |
2f4a40e5 AZ |
9061 | } |
9062 | mask &= ~CACHED_CPSR_BITS; | |
9063 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
e784807c PM |
9064 | if (rebuild_hflags) { |
9065 | arm_rebuild_hflags(env); | |
9066 | } | |
2f4a40e5 AZ |
9067 | } |
9068 | ||
b26eefb6 PB |
9069 | /* Sign/zero extend */ |
9070 | uint32_t HELPER(sxtb16)(uint32_t x) | |
9071 | { | |
9072 | uint32_t res; | |
9073 | res = (uint16_t)(int8_t)x; | |
9074 | res |= (uint32_t)(int8_t)(x >> 16) << 16; | |
9075 | return res; | |
9076 | } | |
9077 | ||
e5346292 PM |
9078 | static void handle_possible_div0_trap(CPUARMState *env, uintptr_t ra) |
9079 | { | |
9080 | /* | |
9081 | * Take a division-by-zero exception if necessary; otherwise return | |
9082 | * to get the usual non-trapping division behaviour (result of 0) | |
9083 | */ | |
9084 | if (arm_feature(env, ARM_FEATURE_M) | |
9085 | && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { | |
9086 | raise_exception_ra(env, EXCP_DIVBYZERO, 0, 1, ra); | |
9087 | } | |
9088 | } | |
9089 | ||
b26eefb6 PB |
9090 | uint32_t HELPER(uxtb16)(uint32_t x) |
9091 | { | |
9092 | uint32_t res; | |
9093 | res = (uint16_t)(uint8_t)x; | |
9094 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; | |
9095 | return res; | |
9096 | } | |
9097 | ||
e5346292 | 9098 | int32_t HELPER(sdiv)(CPUARMState *env, int32_t num, int32_t den) |
3670669c | 9099 | { |
fc7a5038 | 9100 | if (den == 0) { |
e5346292 | 9101 | handle_possible_div0_trap(env, GETPC()); |
fc7a5038 PM |
9102 | return 0; |
9103 | } | |
9104 | if (num == INT_MIN && den == -1) { | |
9105 | return INT_MIN; | |
9106 | } | |
3670669c PB |
9107 | return num / den; |
9108 | } | |
9109 | ||
e5346292 | 9110 | uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den) |
3670669c | 9111 | { |
fc7a5038 | 9112 | if (den == 0) { |
e5346292 | 9113 | handle_possible_div0_trap(env, GETPC()); |
fc7a5038 PM |
9114 | return 0; |
9115 | } | |
3670669c PB |
9116 | return num / den; |
9117 | } | |
9118 | ||
9119 | uint32_t HELPER(rbit)(uint32_t x) | |
9120 | { | |
42fedbca | 9121 | return revbit32(x); |
3670669c PB |
9122 | } |
9123 | ||
c47eaf9f | 9124 | #ifdef CONFIG_USER_ONLY |
b5ff1b31 | 9125 | |
affdb64d | 9126 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 | 9127 | { |
2fc0cc0e | 9128 | ARMCPU *cpu = env_archcpu(env); |
a47dddd7 AF |
9129 | |
9130 | if (mode != ARM_CPU_MODE_USR) { | |
9131 | cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); | |
9132 | } | |
b5ff1b31 FB |
9133 | } |
9134 | ||
012a906b GB |
9135 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
9136 | uint32_t cur_el, bool secure) | |
9e729b57 EI |
9137 | { |
9138 | return 1; | |
9139 | } | |
9140 | ||
ce02049d GB |
9141 | void aarch64_sync_64_to_32(CPUARMState *env) |
9142 | { | |
9143 | g_assert_not_reached(); | |
9144 | } | |
9145 | ||
b5ff1b31 FB |
9146 | #else |
9147 | ||
affdb64d | 9148 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
9149 | { |
9150 | int old_mode; | |
9151 | int i; | |
9152 | ||
9153 | old_mode = env->uncached_cpsr & CPSR_M; | |
9154 | if (mode == old_mode) | |
9155 | return; | |
9156 | ||
9157 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
9158 | memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 9159 | memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
9160 | } else if (mode == ARM_CPU_MODE_FIQ) { |
9161 | memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 9162 | memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
9163 | } |
9164 | ||
f5206413 | 9165 | i = bank_number(old_mode); |
b5ff1b31 | 9166 | env->banked_r13[i] = env->regs[13]; |
b5ff1b31 FB |
9167 | env->banked_spsr[i] = env->spsr; |
9168 | ||
f5206413 | 9169 | i = bank_number(mode); |
b5ff1b31 | 9170 | env->regs[13] = env->banked_r13[i]; |
b5ff1b31 | 9171 | env->spsr = env->banked_spsr[i]; |
593cfa2b PM |
9172 | |
9173 | env->banked_r14[r14_bank_number(old_mode)] = env->regs[14]; | |
9174 | env->regs[14] = env->banked_r14[r14_bank_number(mode)]; | |
b5ff1b31 FB |
9175 | } |
9176 | ||
0eeb17d6 GB |
9177 | /* Physical Interrupt Target EL Lookup Table |
9178 | * | |
9179 | * [ From ARM ARM section G1.13.4 (Table G1-15) ] | |
9180 | * | |
9181 | * The below multi-dimensional table is used for looking up the target | |
9182 | * exception level given numerous condition criteria. Specifically, the | |
9183 | * target EL is based on SCR and HCR routing controls as well as the | |
9184 | * currently executing EL and secure state. | |
9185 | * | |
9186 | * Dimensions: | |
9187 | * target_el_table[2][2][2][2][2][4] | |
9188 | * | | | | | +--- Current EL | |
9189 | * | | | | +------ Non-secure(0)/Secure(1) | |
9190 | * | | | +--------- HCR mask override | |
9191 | * | | +------------ SCR exec state control | |
9192 | * | +--------------- SCR mask override | |
9193 | * +------------------ 32-bit(0)/64-bit(1) EL3 | |
9194 | * | |
9195 | * The table values are as such: | |
9196 | * 0-3 = EL0-EL3 | |
9197 | * -1 = Cannot occur | |
9198 | * | |
9199 | * The ARM ARM target EL table includes entries indicating that an "exception | |
9200 | * is not taken". The two cases where this is applicable are: | |
9201 | * 1) An exception is taken from EL3 but the SCR does not have the exception | |
9202 | * routed to EL3. | |
9203 | * 2) An exception is taken from EL2 but the HCR does not have the exception | |
9204 | * routed to EL2. | |
9205 | * In these two cases, the below table contain a target of EL1. This value is | |
9206 | * returned as it is expected that the consumer of the table data will check | |
9207 | * for "target EL >= current EL" to ensure the exception is not taken. | |
9208 | * | |
9209 | * SCR HCR | |
9210 | * 64 EA AMO From | |
9211 | * BIT IRQ IMO Non-secure Secure | |
9212 | * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 | |
9213 | */ | |
82c39f6a | 9214 | static const int8_t target_el_table[2][2][2][2][2][4] = { |
0eeb17d6 GB |
9215 | {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, |
9216 | {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, | |
9217 | {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, | |
9218 | {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, | |
9219 | {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
9220 | {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, | |
9221 | {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
9222 | {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, | |
9223 | {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, | |
6c85f906 RDC |
9224 | {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},}, |
9225 | {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },}, | |
9226 | {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},}, | |
0eeb17d6 GB |
9227 | {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, |
9228 | {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, | |
6c85f906 RDC |
9229 | {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },}, |
9230 | {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},}, | |
0eeb17d6 GB |
9231 | }; |
9232 | ||
9233 | /* | |
9234 | * Determine the target EL for physical exceptions | |
9235 | */ | |
012a906b GB |
9236 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
9237 | uint32_t cur_el, bool secure) | |
0eeb17d6 GB |
9238 | { |
9239 | CPUARMState *env = cs->env_ptr; | |
f7778444 RH |
9240 | bool rw; |
9241 | bool scr; | |
9242 | bool hcr; | |
0eeb17d6 | 9243 | int target_el; |
2cde031f | 9244 | /* Is the highest EL AArch64? */ |
f7778444 RH |
9245 | bool is64 = arm_feature(env, ARM_FEATURE_AARCH64); |
9246 | uint64_t hcr_el2; | |
2cde031f SS |
9247 | |
9248 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
9249 | rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); | |
9250 | } else { | |
9251 | /* Either EL2 is the highest EL (and so the EL2 register width | |
9252 | * is given by is64); or there is no EL2 or EL3, in which case | |
9253 | * the value of 'rw' does not affect the table lookup anyway. | |
9254 | */ | |
9255 | rw = is64; | |
9256 | } | |
0eeb17d6 | 9257 | |
f7778444 | 9258 | hcr_el2 = arm_hcr_el2_eff(env); |
0eeb17d6 GB |
9259 | switch (excp_idx) { |
9260 | case EXCP_IRQ: | |
9261 | scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); | |
f7778444 | 9262 | hcr = hcr_el2 & HCR_IMO; |
0eeb17d6 GB |
9263 | break; |
9264 | case EXCP_FIQ: | |
9265 | scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); | |
f7778444 | 9266 | hcr = hcr_el2 & HCR_FMO; |
0eeb17d6 GB |
9267 | break; |
9268 | default: | |
9269 | scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); | |
f7778444 | 9270 | hcr = hcr_el2 & HCR_AMO; |
0eeb17d6 GB |
9271 | break; |
9272 | }; | |
9273 | ||
d1b31428 RH |
9274 | /* |
9275 | * For these purposes, TGE and AMO/IMO/FMO both force the | |
9276 | * interrupt to EL2. Fold TGE into the bit extracted above. | |
9277 | */ | |
9278 | hcr |= (hcr_el2 & HCR_TGE) != 0; | |
9279 | ||
0eeb17d6 GB |
9280 | /* Perform a table-lookup for the target EL given the current state */ |
9281 | target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; | |
9282 | ||
9283 | assert(target_el > 0); | |
9284 | ||
9285 | return target_el; | |
9286 | } | |
9287 | ||
fc6177af | 9288 | void arm_log_exception(CPUState *cs) |
b59f479b | 9289 | { |
fc6177af PM |
9290 | int idx = cs->exception_index; |
9291 | ||
b59f479b PMD |
9292 | if (qemu_loglevel_mask(CPU_LOG_INT)) { |
9293 | const char *exc = NULL; | |
9294 | static const char * const excnames[] = { | |
9295 | [EXCP_UDEF] = "Undefined Instruction", | |
9296 | [EXCP_SWI] = "SVC", | |
9297 | [EXCP_PREFETCH_ABORT] = "Prefetch Abort", | |
9298 | [EXCP_DATA_ABORT] = "Data Abort", | |
9299 | [EXCP_IRQ] = "IRQ", | |
9300 | [EXCP_FIQ] = "FIQ", | |
9301 | [EXCP_BKPT] = "Breakpoint", | |
9302 | [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", | |
9303 | [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", | |
9304 | [EXCP_HVC] = "Hypervisor Call", | |
9305 | [EXCP_HYP_TRAP] = "Hypervisor Trap", | |
9306 | [EXCP_SMC] = "Secure Monitor Call", | |
9307 | [EXCP_VIRQ] = "Virtual IRQ", | |
9308 | [EXCP_VFIQ] = "Virtual FIQ", | |
9309 | [EXCP_SEMIHOST] = "Semihosting call", | |
9310 | [EXCP_NOCP] = "v7M NOCP UsageFault", | |
9311 | [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", | |
9312 | [EXCP_STKOF] = "v8M STKOF UsageFault", | |
9313 | [EXCP_LAZYFP] = "v7M exception during lazy FP stacking", | |
9314 | [EXCP_LSERR] = "v8M LSERR UsageFault", | |
9315 | [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", | |
e5346292 | 9316 | [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault", |
b59f479b PMD |
9317 | }; |
9318 | ||
9319 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | |
9320 | exc = excnames[idx]; | |
9321 | } | |
9322 | if (!exc) { | |
9323 | exc = "unknown"; | |
9324 | } | |
fc6177af PM |
9325 | qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s] on CPU %d\n", |
9326 | idx, exc, cs->cpu_index); | |
b59f479b PMD |
9327 | } |
9328 | } | |
9329 | ||
a356dacf | 9330 | /* |
7aab5a8c PMD |
9331 | * Function used to synchronize QEMU's AArch64 register set with AArch32 |
9332 | * register set. This is necessary when switching between AArch32 and AArch64 | |
9333 | * execution state. | |
a356dacf | 9334 | */ |
7aab5a8c | 9335 | void aarch64_sync_32_to_64(CPUARMState *env) |
9ee6e8bb | 9336 | { |
7aab5a8c PMD |
9337 | int i; |
9338 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
9339 | ||
9340 | /* We can blanket copy R[0:7] to X[0:7] */ | |
9341 | for (i = 0; i < 8; i++) { | |
9342 | env->xregs[i] = env->regs[i]; | |
fd592d89 | 9343 | } |
70d74660 | 9344 | |
9a223097 | 9345 | /* |
7aab5a8c PMD |
9346 | * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. |
9347 | * Otherwise, they come from the banked user regs. | |
fd592d89 | 9348 | */ |
7aab5a8c PMD |
9349 | if (mode == ARM_CPU_MODE_FIQ) { |
9350 | for (i = 8; i < 13; i++) { | |
9351 | env->xregs[i] = env->usr_regs[i - 8]; | |
9352 | } | |
9353 | } else { | |
9354 | for (i = 8; i < 13; i++) { | |
9355 | env->xregs[i] = env->regs[i]; | |
9356 | } | |
fd592d89 | 9357 | } |
9ee6e8bb | 9358 | |
7aab5a8c PMD |
9359 | /* |
9360 | * Registers x13-x23 are the various mode SP and FP registers. Registers | |
9361 | * r13 and r14 are only copied if we are in that mode, otherwise we copy | |
9362 | * from the mode banked register. | |
9363 | */ | |
9364 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { | |
9365 | env->xregs[13] = env->regs[13]; | |
9366 | env->xregs[14] = env->regs[14]; | |
9367 | } else { | |
9368 | env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; | |
9369 | /* HYP is an exception in that it is copied from r14 */ | |
9370 | if (mode == ARM_CPU_MODE_HYP) { | |
9371 | env->xregs[14] = env->regs[14]; | |
95695eff | 9372 | } else { |
7aab5a8c | 9373 | env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)]; |
95695eff | 9374 | } |
95695eff PM |
9375 | } |
9376 | ||
7aab5a8c PMD |
9377 | if (mode == ARM_CPU_MODE_HYP) { |
9378 | env->xregs[15] = env->regs[13]; | |
9379 | } else { | |
9380 | env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; | |
95695eff PM |
9381 | } |
9382 | ||
7aab5a8c PMD |
9383 | if (mode == ARM_CPU_MODE_IRQ) { |
9384 | env->xregs[16] = env->regs[14]; | |
9385 | env->xregs[17] = env->regs[13]; | |
9386 | } else { | |
9387 | env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)]; | |
9388 | env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; | |
9389 | } | |
95695eff | 9390 | |
7aab5a8c PMD |
9391 | if (mode == ARM_CPU_MODE_SVC) { |
9392 | env->xregs[18] = env->regs[14]; | |
9393 | env->xregs[19] = env->regs[13]; | |
9394 | } else { | |
9395 | env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)]; | |
9396 | env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; | |
9397 | } | |
95695eff | 9398 | |
7aab5a8c PMD |
9399 | if (mode == ARM_CPU_MODE_ABT) { |
9400 | env->xregs[20] = env->regs[14]; | |
9401 | env->xregs[21] = env->regs[13]; | |
9402 | } else { | |
9403 | env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)]; | |
9404 | env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; | |
9405 | } | |
e33cf0f8 | 9406 | |
7aab5a8c PMD |
9407 | if (mode == ARM_CPU_MODE_UND) { |
9408 | env->xregs[22] = env->regs[14]; | |
9409 | env->xregs[23] = env->regs[13]; | |
9410 | } else { | |
9411 | env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)]; | |
9412 | env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; | |
e33cf0f8 PM |
9413 | } |
9414 | ||
9415 | /* | |
7aab5a8c PMD |
9416 | * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ |
9417 | * mode, then we can copy from r8-r14. Otherwise, we copy from the | |
9418 | * FIQ bank for r8-r14. | |
e33cf0f8 | 9419 | */ |
7aab5a8c PMD |
9420 | if (mode == ARM_CPU_MODE_FIQ) { |
9421 | for (i = 24; i < 31; i++) { | |
9422 | env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ | |
9423 | } | |
9424 | } else { | |
9425 | for (i = 24; i < 29; i++) { | |
9426 | env->xregs[i] = env->fiq_regs[i - 24]; | |
e33cf0f8 | 9427 | } |
7aab5a8c PMD |
9428 | env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; |
9429 | env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)]; | |
e33cf0f8 | 9430 | } |
7aab5a8c PMD |
9431 | |
9432 | env->pc = env->regs[15]; | |
e33cf0f8 PM |
9433 | } |
9434 | ||
9a223097 | 9435 | /* |
7aab5a8c PMD |
9436 | * Function used to synchronize QEMU's AArch32 register set with AArch64 |
9437 | * register set. This is necessary when switching between AArch32 and AArch64 | |
9438 | * execution state. | |
de2db7ec | 9439 | */ |
7aab5a8c | 9440 | void aarch64_sync_64_to_32(CPUARMState *env) |
9ee6e8bb | 9441 | { |
7aab5a8c PMD |
9442 | int i; |
9443 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
abc24d86 | 9444 | |
7aab5a8c PMD |
9445 | /* We can blanket copy X[0:7] to R[0:7] */ |
9446 | for (i = 0; i < 8; i++) { | |
9447 | env->regs[i] = env->xregs[i]; | |
de2db7ec | 9448 | } |
3f0cddee | 9449 | |
9a223097 | 9450 | /* |
7aab5a8c PMD |
9451 | * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. |
9452 | * Otherwise, we copy x8-x12 into the banked user regs. | |
de2db7ec | 9453 | */ |
7aab5a8c PMD |
9454 | if (mode == ARM_CPU_MODE_FIQ) { |
9455 | for (i = 8; i < 13; i++) { | |
9456 | env->usr_regs[i - 8] = env->xregs[i]; | |
9457 | } | |
9458 | } else { | |
9459 | for (i = 8; i < 13; i++) { | |
9460 | env->regs[i] = env->xregs[i]; | |
9461 | } | |
fb602cb7 PM |
9462 | } |
9463 | ||
9a223097 | 9464 | /* |
7aab5a8c PMD |
9465 | * Registers r13 & r14 depend on the current mode. |
9466 | * If we are in a given mode, we copy the corresponding x registers to r13 | |
9467 | * and r14. Otherwise, we copy the x register to the banked r13 and r14 | |
9468 | * for the mode. | |
fb602cb7 | 9469 | */ |
7aab5a8c PMD |
9470 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { |
9471 | env->regs[13] = env->xregs[13]; | |
9472 | env->regs[14] = env->xregs[14]; | |
fb602cb7 | 9473 | } else { |
7aab5a8c | 9474 | env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; |
fb602cb7 | 9475 | |
7aab5a8c PMD |
9476 | /* |
9477 | * HYP is an exception in that it does not have its own banked r14 but | |
9478 | * shares the USR r14 | |
9479 | */ | |
9480 | if (mode == ARM_CPU_MODE_HYP) { | |
9481 | env->regs[14] = env->xregs[14]; | |
9482 | } else { | |
9483 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; | |
9484 | } | |
9485 | } | |
fb602cb7 | 9486 | |
7aab5a8c PMD |
9487 | if (mode == ARM_CPU_MODE_HYP) { |
9488 | env->regs[13] = env->xregs[15]; | |
fb602cb7 | 9489 | } else { |
7aab5a8c | 9490 | env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; |
fb602cb7 | 9491 | } |
d02a8698 | 9492 | |
7aab5a8c PMD |
9493 | if (mode == ARM_CPU_MODE_IRQ) { |
9494 | env->regs[14] = env->xregs[16]; | |
9495 | env->regs[13] = env->xregs[17]; | |
d02a8698 | 9496 | } else { |
7aab5a8c PMD |
9497 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; |
9498 | env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; | |
d02a8698 PM |
9499 | } |
9500 | ||
7aab5a8c PMD |
9501 | if (mode == ARM_CPU_MODE_SVC) { |
9502 | env->regs[14] = env->xregs[18]; | |
9503 | env->regs[13] = env->xregs[19]; | |
9504 | } else { | |
9505 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; | |
9506 | env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; | |
fb602cb7 PM |
9507 | } |
9508 | ||
7aab5a8c PMD |
9509 | if (mode == ARM_CPU_MODE_ABT) { |
9510 | env->regs[14] = env->xregs[20]; | |
9511 | env->regs[13] = env->xregs[21]; | |
9512 | } else { | |
9513 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; | |
9514 | env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; | |
ce02049d GB |
9515 | } |
9516 | ||
9517 | if (mode == ARM_CPU_MODE_UND) { | |
3a9148d0 SS |
9518 | env->regs[14] = env->xregs[22]; |
9519 | env->regs[13] = env->xregs[23]; | |
ce02049d | 9520 | } else { |
593cfa2b | 9521 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; |
3a9148d0 | 9522 | env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; |
ce02049d GB |
9523 | } |
9524 | ||
9525 | /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ | |
9526 | * mode, then we can copy to r8-r14. Otherwise, we copy to the | |
9527 | * FIQ bank for r8-r14. | |
9528 | */ | |
9529 | if (mode == ARM_CPU_MODE_FIQ) { | |
9530 | for (i = 24; i < 31; i++) { | |
9531 | env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ | |
9532 | } | |
9533 | } else { | |
9534 | for (i = 24; i < 29; i++) { | |
9535 | env->fiq_regs[i - 24] = env->xregs[i]; | |
9536 | } | |
9537 | env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; | |
593cfa2b | 9538 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; |
ce02049d GB |
9539 | } |
9540 | ||
9541 | env->regs[15] = env->pc; | |
9542 | } | |
9543 | ||
dea8378b PM |
9544 | static void take_aarch32_exception(CPUARMState *env, int new_mode, |
9545 | uint32_t mask, uint32_t offset, | |
9546 | uint32_t newpc) | |
9547 | { | |
4a2696c0 RH |
9548 | int new_el; |
9549 | ||
dea8378b PM |
9550 | /* Change the CPU state so as to actually take the exception. */ |
9551 | switch_mode(env, new_mode); | |
4a2696c0 | 9552 | |
dea8378b PM |
9553 | /* |
9554 | * For exceptions taken to AArch32 we must clear the SS bit in both | |
9555 | * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. | |
9556 | */ | |
f944a854 | 9557 | env->pstate &= ~PSTATE_SS; |
dea8378b PM |
9558 | env->spsr = cpsr_read(env); |
9559 | /* Clear IT bits. */ | |
9560 | env->condexec_bits = 0; | |
9561 | /* Switch to the new mode, and to the correct instruction set. */ | |
9562 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; | |
88828bf1 CD |
9563 | |
9564 | /* This must be after mode switching. */ | |
9565 | new_el = arm_current_el(env); | |
9566 | ||
dea8378b PM |
9567 | /* Set new mode endianness */ |
9568 | env->uncached_cpsr &= ~CPSR_E; | |
4a2696c0 | 9569 | if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { |
dea8378b PM |
9570 | env->uncached_cpsr |= CPSR_E; |
9571 | } | |
829f9fd3 PM |
9572 | /* J and IL must always be cleared for exception entry */ |
9573 | env->uncached_cpsr &= ~(CPSR_IL | CPSR_J); | |
dea8378b PM |
9574 | env->daif |= mask; |
9575 | ||
f2f68a78 RC |
9576 | if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) { |
9577 | if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) { | |
9578 | env->uncached_cpsr |= CPSR_SSBS; | |
9579 | } else { | |
9580 | env->uncached_cpsr &= ~CPSR_SSBS; | |
9581 | } | |
9582 | } | |
9583 | ||
dea8378b PM |
9584 | if (new_mode == ARM_CPU_MODE_HYP) { |
9585 | env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0; | |
9586 | env->elr_el[2] = env->regs[15]; | |
9587 | } else { | |
4a2696c0 | 9588 | /* CPSR.PAN is normally preserved preserved unless... */ |
f8af1143 | 9589 | if (cpu_isar_feature(aa32_pan, env_archcpu(env))) { |
4a2696c0 RH |
9590 | switch (new_el) { |
9591 | case 3: | |
9592 | if (!arm_is_secure_below_el3(env)) { | |
9593 | /* ... the target is EL3, from non-secure state. */ | |
9594 | env->uncached_cpsr &= ~CPSR_PAN; | |
9595 | break; | |
9596 | } | |
9597 | /* ... the target is EL3, from secure state ... */ | |
9598 | /* fall through */ | |
9599 | case 1: | |
9600 | /* ... the target is EL1 and SCTLR.SPAN is 0. */ | |
9601 | if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { | |
9602 | env->uncached_cpsr |= CPSR_PAN; | |
9603 | } | |
9604 | break; | |
9605 | } | |
9606 | } | |
dea8378b PM |
9607 | /* |
9608 | * this is a lie, as there was no c1_sys on V4T/V5, but who cares | |
9609 | * and we should just guard the thumb mode on V4 | |
9610 | */ | |
9611 | if (arm_feature(env, ARM_FEATURE_V4T)) { | |
9612 | env->thumb = | |
9613 | (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; | |
9614 | } | |
9615 | env->regs[14] = env->regs[15] + offset; | |
9616 | } | |
9617 | env->regs[15] = newpc; | |
a8a79c7a | 9618 | arm_rebuild_hflags(env); |
dea8378b PM |
9619 | } |
9620 | ||
b9bc21ff PM |
9621 | static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) |
9622 | { | |
9623 | /* | |
9624 | * Handle exception entry to Hyp mode; this is sufficiently | |
9625 | * different to entry to other AArch32 modes that we handle it | |
9626 | * separately here. | |
9627 | * | |
9628 | * The vector table entry used is always the 0x14 Hyp mode entry point, | |
2c023d36 | 9629 | * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp. |
b9bc21ff PM |
9630 | * The offset applied to the preferred return address is always zero |
9631 | * (see DDI0487C.a section G1.12.3). | |
9632 | * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. | |
9633 | */ | |
9634 | uint32_t addr, mask; | |
9635 | ARMCPU *cpu = ARM_CPU(cs); | |
9636 | CPUARMState *env = &cpu->env; | |
9637 | ||
9638 | switch (cs->exception_index) { | |
9639 | case EXCP_UDEF: | |
9640 | addr = 0x04; | |
9641 | break; | |
9642 | case EXCP_SWI: | |
2c023d36 | 9643 | addr = 0x08; |
b9bc21ff PM |
9644 | break; |
9645 | case EXCP_BKPT: | |
9646 | /* Fall through to prefetch abort. */ | |
9647 | case EXCP_PREFETCH_ABORT: | |
9648 | env->cp15.ifar_s = env->exception.vaddress; | |
9649 | qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n", | |
9650 | (uint32_t)env->exception.vaddress); | |
9651 | addr = 0x0c; | |
9652 | break; | |
9653 | case EXCP_DATA_ABORT: | |
9654 | env->cp15.dfar_s = env->exception.vaddress; | |
9655 | qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n", | |
9656 | (uint32_t)env->exception.vaddress); | |
9657 | addr = 0x10; | |
9658 | break; | |
9659 | case EXCP_IRQ: | |
9660 | addr = 0x18; | |
9661 | break; | |
9662 | case EXCP_FIQ: | |
9663 | addr = 0x1c; | |
9664 | break; | |
9665 | case EXCP_HVC: | |
9666 | addr = 0x08; | |
9667 | break; | |
9668 | case EXCP_HYP_TRAP: | |
9669 | addr = 0x14; | |
9bbb4ef9 | 9670 | break; |
b9bc21ff PM |
9671 | default: |
9672 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
9673 | } | |
9674 | ||
9675 | if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) { | |
2ed08180 PM |
9676 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
9677 | /* | |
9678 | * QEMU syndrome values are v8-style. v7 has the IL bit | |
9679 | * UNK/SBZP for "field not valid" cases, where v8 uses RES1. | |
9680 | * If this is a v7 CPU, squash the IL bit in those cases. | |
9681 | */ | |
9682 | if (cs->exception_index == EXCP_PREFETCH_ABORT || | |
9683 | (cs->exception_index == EXCP_DATA_ABORT && | |
9684 | !(env->exception.syndrome & ARM_EL_ISV)) || | |
9685 | syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) { | |
9686 | env->exception.syndrome &= ~ARM_EL_IL; | |
9687 | } | |
9688 | } | |
b9bc21ff PM |
9689 | env->cp15.esr_el[2] = env->exception.syndrome; |
9690 | } | |
9691 | ||
9692 | if (arm_current_el(env) != 2 && addr < 0x14) { | |
9693 | addr = 0x14; | |
9694 | } | |
9695 | ||
9696 | mask = 0; | |
9697 | if (!(env->cp15.scr_el3 & SCR_EA)) { | |
9698 | mask |= CPSR_A; | |
9699 | } | |
9700 | if (!(env->cp15.scr_el3 & SCR_IRQ)) { | |
9701 | mask |= CPSR_I; | |
9702 | } | |
9703 | if (!(env->cp15.scr_el3 & SCR_FIQ)) { | |
9704 | mask |= CPSR_F; | |
9705 | } | |
9706 | ||
9707 | addr += env->cp15.hvbar; | |
9708 | ||
9709 | take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr); | |
9710 | } | |
9711 | ||
966f758c | 9712 | static void arm_cpu_do_interrupt_aarch32(CPUState *cs) |
b5ff1b31 | 9713 | { |
97a8ea5a AF |
9714 | ARMCPU *cpu = ARM_CPU(cs); |
9715 | CPUARMState *env = &cpu->env; | |
b5ff1b31 FB |
9716 | uint32_t addr; |
9717 | uint32_t mask; | |
9718 | int new_mode; | |
9719 | uint32_t offset; | |
16a906fd | 9720 | uint32_t moe; |
b5ff1b31 | 9721 | |
16a906fd | 9722 | /* If this is a debug exception we must update the DBGDSCR.MOE bits */ |
64b91e3f | 9723 | switch (syn_get_ec(env->exception.syndrome)) { |
16a906fd PM |
9724 | case EC_BREAKPOINT: |
9725 | case EC_BREAKPOINT_SAME_EL: | |
9726 | moe = 1; | |
9727 | break; | |
9728 | case EC_WATCHPOINT: | |
9729 | case EC_WATCHPOINT_SAME_EL: | |
9730 | moe = 10; | |
9731 | break; | |
9732 | case EC_AA32_BKPT: | |
9733 | moe = 3; | |
9734 | break; | |
9735 | case EC_VECTORCATCH: | |
9736 | moe = 5; | |
9737 | break; | |
9738 | default: | |
9739 | moe = 0; | |
9740 | break; | |
9741 | } | |
9742 | ||
9743 | if (moe) { | |
9744 | env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); | |
9745 | } | |
9746 | ||
b9bc21ff PM |
9747 | if (env->exception.target_el == 2) { |
9748 | arm_cpu_do_interrupt_aarch32_hyp(cs); | |
9749 | return; | |
9750 | } | |
9751 | ||
27103424 | 9752 | switch (cs->exception_index) { |
b5ff1b31 FB |
9753 | case EXCP_UDEF: |
9754 | new_mode = ARM_CPU_MODE_UND; | |
9755 | addr = 0x04; | |
9756 | mask = CPSR_I; | |
9757 | if (env->thumb) | |
9758 | offset = 2; | |
9759 | else | |
9760 | offset = 4; | |
9761 | break; | |
9762 | case EXCP_SWI: | |
9763 | new_mode = ARM_CPU_MODE_SVC; | |
9764 | addr = 0x08; | |
9765 | mask = CPSR_I; | |
601d70b9 | 9766 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
9767 | offset = 0; |
9768 | break; | |
06c949e6 | 9769 | case EXCP_BKPT: |
9ee6e8bb PB |
9770 | /* Fall through to prefetch abort. */ |
9771 | case EXCP_PREFETCH_ABORT: | |
88ca1c2d | 9772 | A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); |
b848ce2b | 9773 | A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); |
3f1beaca | 9774 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", |
88ca1c2d | 9775 | env->exception.fsr, (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
9776 | new_mode = ARM_CPU_MODE_ABT; |
9777 | addr = 0x0c; | |
9778 | mask = CPSR_A | CPSR_I; | |
9779 | offset = 4; | |
9780 | break; | |
9781 | case EXCP_DATA_ABORT: | |
4a7e2d73 | 9782 | A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); |
b848ce2b | 9783 | A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); |
3f1beaca | 9784 | qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", |
4a7e2d73 | 9785 | env->exception.fsr, |
6cd8a264 | 9786 | (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
9787 | new_mode = ARM_CPU_MODE_ABT; |
9788 | addr = 0x10; | |
9789 | mask = CPSR_A | CPSR_I; | |
9790 | offset = 8; | |
9791 | break; | |
9792 | case EXCP_IRQ: | |
9793 | new_mode = ARM_CPU_MODE_IRQ; | |
9794 | addr = 0x18; | |
9795 | /* Disable IRQ and imprecise data aborts. */ | |
9796 | mask = CPSR_A | CPSR_I; | |
9797 | offset = 4; | |
de38d23b FA |
9798 | if (env->cp15.scr_el3 & SCR_IRQ) { |
9799 | /* IRQ routed to monitor mode */ | |
9800 | new_mode = ARM_CPU_MODE_MON; | |
9801 | mask |= CPSR_F; | |
9802 | } | |
b5ff1b31 FB |
9803 | break; |
9804 | case EXCP_FIQ: | |
9805 | new_mode = ARM_CPU_MODE_FIQ; | |
9806 | addr = 0x1c; | |
9807 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
9808 | mask = CPSR_A | CPSR_I | CPSR_F; | |
de38d23b FA |
9809 | if (env->cp15.scr_el3 & SCR_FIQ) { |
9810 | /* FIQ routed to monitor mode */ | |
9811 | new_mode = ARM_CPU_MODE_MON; | |
9812 | } | |
b5ff1b31 FB |
9813 | offset = 4; |
9814 | break; | |
87a4b270 PM |
9815 | case EXCP_VIRQ: |
9816 | new_mode = ARM_CPU_MODE_IRQ; | |
9817 | addr = 0x18; | |
9818 | /* Disable IRQ and imprecise data aborts. */ | |
9819 | mask = CPSR_A | CPSR_I; | |
9820 | offset = 4; | |
9821 | break; | |
9822 | case EXCP_VFIQ: | |
9823 | new_mode = ARM_CPU_MODE_FIQ; | |
9824 | addr = 0x1c; | |
9825 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
9826 | mask = CPSR_A | CPSR_I | CPSR_F; | |
9827 | offset = 4; | |
9828 | break; | |
dbe9d163 FA |
9829 | case EXCP_SMC: |
9830 | new_mode = ARM_CPU_MODE_MON; | |
9831 | addr = 0x08; | |
9832 | mask = CPSR_A | CPSR_I | CPSR_F; | |
9833 | offset = 0; | |
9834 | break; | |
b5ff1b31 | 9835 | default: |
a47dddd7 | 9836 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
b5ff1b31 FB |
9837 | return; /* Never happens. Keep compiler happy. */ |
9838 | } | |
e89e51a1 FA |
9839 | |
9840 | if (new_mode == ARM_CPU_MODE_MON) { | |
9841 | addr += env->cp15.mvbar; | |
137feaa9 | 9842 | } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { |
e89e51a1 | 9843 | /* High vectors. When enabled, base address cannot be remapped. */ |
b5ff1b31 | 9844 | addr += 0xffff0000; |
8641136c NR |
9845 | } else { |
9846 | /* ARM v7 architectures provide a vector base address register to remap | |
9847 | * the interrupt vector table. | |
e89e51a1 | 9848 | * This register is only followed in non-monitor mode, and is banked. |
8641136c NR |
9849 | * Note: only bits 31:5 are valid. |
9850 | */ | |
fb6c91ba | 9851 | addr += A32_BANKED_CURRENT_REG_GET(env, vbar); |
b5ff1b31 | 9852 | } |
dbe9d163 FA |
9853 | |
9854 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
9855 | env->cp15.scr_el3 &= ~SCR_NS; | |
9856 | } | |
9857 | ||
dea8378b | 9858 | take_aarch32_exception(env, new_mode, mask, offset, addr); |
b5ff1b31 FB |
9859 | } |
9860 | ||
a65dabf7 PM |
9861 | static int aarch64_regnum(CPUARMState *env, int aarch32_reg) |
9862 | { | |
9863 | /* | |
9864 | * Return the register number of the AArch64 view of the AArch32 | |
9865 | * register @aarch32_reg. The CPUARMState CPSR is assumed to still | |
9866 | * be that of the AArch32 mode the exception came from. | |
9867 | */ | |
9868 | int mode = env->uncached_cpsr & CPSR_M; | |
9869 | ||
9870 | switch (aarch32_reg) { | |
9871 | case 0 ... 7: | |
9872 | return aarch32_reg; | |
9873 | case 8 ... 12: | |
9874 | return mode == ARM_CPU_MODE_FIQ ? aarch32_reg + 16 : aarch32_reg; | |
9875 | case 13: | |
9876 | switch (mode) { | |
9877 | case ARM_CPU_MODE_USR: | |
9878 | case ARM_CPU_MODE_SYS: | |
9879 | return 13; | |
9880 | case ARM_CPU_MODE_HYP: | |
9881 | return 15; | |
9882 | case ARM_CPU_MODE_IRQ: | |
9883 | return 17; | |
9884 | case ARM_CPU_MODE_SVC: | |
9885 | return 19; | |
9886 | case ARM_CPU_MODE_ABT: | |
9887 | return 21; | |
9888 | case ARM_CPU_MODE_UND: | |
9889 | return 23; | |
9890 | case ARM_CPU_MODE_FIQ: | |
9891 | return 29; | |
9892 | default: | |
9893 | g_assert_not_reached(); | |
9894 | } | |
9895 | case 14: | |
9896 | switch (mode) { | |
9897 | case ARM_CPU_MODE_USR: | |
9898 | case ARM_CPU_MODE_SYS: | |
9899 | case ARM_CPU_MODE_HYP: | |
9900 | return 14; | |
9901 | case ARM_CPU_MODE_IRQ: | |
9902 | return 16; | |
9903 | case ARM_CPU_MODE_SVC: | |
9904 | return 18; | |
9905 | case ARM_CPU_MODE_ABT: | |
9906 | return 20; | |
9907 | case ARM_CPU_MODE_UND: | |
9908 | return 22; | |
9909 | case ARM_CPU_MODE_FIQ: | |
9910 | return 30; | |
9911 | default: | |
9912 | g_assert_not_reached(); | |
9913 | } | |
9914 | case 15: | |
9915 | return 31; | |
9916 | default: | |
9917 | g_assert_not_reached(); | |
9918 | } | |
9919 | } | |
9920 | ||
f944a854 RC |
9921 | static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env) |
9922 | { | |
9923 | uint32_t ret = cpsr_read(env); | |
9924 | ||
9925 | /* Move DIT to the correct location for SPSR_ELx */ | |
9926 | if (ret & CPSR_DIT) { | |
9927 | ret &= ~CPSR_DIT; | |
9928 | ret |= PSTATE_DIT; | |
9929 | } | |
9930 | /* Merge PSTATE.SS into SPSR_ELx */ | |
9931 | ret |= env->pstate & PSTATE_SS; | |
9932 | ||
9933 | return ret; | |
9934 | } | |
9935 | ||
966f758c PM |
9936 | /* Handle exception entry to a target EL which is using AArch64 */ |
9937 | static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | |
f3a9b694 PM |
9938 | { |
9939 | ARMCPU *cpu = ARM_CPU(cs); | |
9940 | CPUARMState *env = &cpu->env; | |
9941 | unsigned int new_el = env->exception.target_el; | |
9942 | target_ulong addr = env->cp15.vbar_el[new_el]; | |
9943 | unsigned int new_mode = aarch64_pstate_mode(new_el, true); | |
4a2696c0 | 9944 | unsigned int old_mode; |
0ab5953b | 9945 | unsigned int cur_el = arm_current_el(env); |
a65dabf7 | 9946 | int rt; |
0ab5953b | 9947 | |
9a05f7b6 RH |
9948 | /* |
9949 | * Note that new_el can never be 0. If cur_el is 0, then | |
9950 | * el0_a64 is is_a64(), else el0_a64 is ignored. | |
9951 | */ | |
9952 | aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); | |
f3a9b694 | 9953 | |
0ab5953b | 9954 | if (cur_el < new_el) { |
3d6f7617 PM |
9955 | /* Entry vector offset depends on whether the implemented EL |
9956 | * immediately lower than the target level is using AArch32 or AArch64 | |
9957 | */ | |
9958 | bool is_aa64; | |
cb092fbb | 9959 | uint64_t hcr; |
3d6f7617 PM |
9960 | |
9961 | switch (new_el) { | |
9962 | case 3: | |
9963 | is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; | |
9964 | break; | |
9965 | case 2: | |
cb092fbb RH |
9966 | hcr = arm_hcr_el2_eff(env); |
9967 | if ((hcr & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { | |
9968 | is_aa64 = (hcr & HCR_RW) != 0; | |
9969 | break; | |
9970 | } | |
9971 | /* fall through */ | |
3d6f7617 PM |
9972 | case 1: |
9973 | is_aa64 = is_a64(env); | |
9974 | break; | |
9975 | default: | |
9976 | g_assert_not_reached(); | |
9977 | } | |
9978 | ||
9979 | if (is_aa64) { | |
f3a9b694 PM |
9980 | addr += 0x400; |
9981 | } else { | |
9982 | addr += 0x600; | |
9983 | } | |
9984 | } else if (pstate_read(env) & PSTATE_SP) { | |
9985 | addr += 0x200; | |
9986 | } | |
9987 | ||
f3a9b694 PM |
9988 | switch (cs->exception_index) { |
9989 | case EXCP_PREFETCH_ABORT: | |
9990 | case EXCP_DATA_ABORT: | |
9991 | env->cp15.far_el[new_el] = env->exception.vaddress; | |
9992 | qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", | |
9993 | env->cp15.far_el[new_el]); | |
9994 | /* fall through */ | |
9995 | case EXCP_BKPT: | |
9996 | case EXCP_UDEF: | |
9997 | case EXCP_SWI: | |
9998 | case EXCP_HVC: | |
9999 | case EXCP_HYP_TRAP: | |
10000 | case EXCP_SMC: | |
a65dabf7 PM |
10001 | switch (syn_get_ec(env->exception.syndrome)) { |
10002 | case EC_ADVSIMDFPACCESSTRAP: | |
4be42f40 PM |
10003 | /* |
10004 | * QEMU internal FP/SIMD syndromes from AArch32 include the | |
10005 | * TA and coproc fields which are only exposed if the exception | |
10006 | * is taken to AArch32 Hyp mode. Mask them out to get a valid | |
10007 | * AArch64 format syndrome. | |
10008 | */ | |
10009 | env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20); | |
a65dabf7 PM |
10010 | break; |
10011 | case EC_CP14RTTRAP: | |
10012 | case EC_CP15RTTRAP: | |
10013 | case EC_CP14DTTRAP: | |
10014 | /* | |
10015 | * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently | |
10016 | * the raw register field from the insn; when taking this to | |
10017 | * AArch64 we must convert it to the AArch64 view of the register | |
10018 | * number. Notice that we read a 4-bit AArch32 register number and | |
10019 | * write back a 5-bit AArch64 one. | |
10020 | */ | |
10021 | rt = extract32(env->exception.syndrome, 5, 4); | |
10022 | rt = aarch64_regnum(env, rt); | |
10023 | env->exception.syndrome = deposit32(env->exception.syndrome, | |
10024 | 5, 5, rt); | |
10025 | break; | |
10026 | case EC_CP15RRTTRAP: | |
10027 | case EC_CP14RRTTRAP: | |
10028 | /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */ | |
10029 | rt = extract32(env->exception.syndrome, 5, 4); | |
10030 | rt = aarch64_regnum(env, rt); | |
10031 | env->exception.syndrome = deposit32(env->exception.syndrome, | |
10032 | 5, 5, rt); | |
10033 | rt = extract32(env->exception.syndrome, 10, 4); | |
10034 | rt = aarch64_regnum(env, rt); | |
10035 | env->exception.syndrome = deposit32(env->exception.syndrome, | |
10036 | 10, 5, rt); | |
10037 | break; | |
4be42f40 | 10038 | } |
f3a9b694 PM |
10039 | env->cp15.esr_el[new_el] = env->exception.syndrome; |
10040 | break; | |
10041 | case EXCP_IRQ: | |
10042 | case EXCP_VIRQ: | |
10043 | addr += 0x80; | |
10044 | break; | |
10045 | case EXCP_FIQ: | |
10046 | case EXCP_VFIQ: | |
10047 | addr += 0x100; | |
10048 | break; | |
f3a9b694 PM |
10049 | default: |
10050 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
10051 | } | |
10052 | ||
10053 | if (is_a64(env)) { | |
4a2696c0 | 10054 | old_mode = pstate_read(env); |
f3a9b694 PM |
10055 | aarch64_save_sp(env, arm_current_el(env)); |
10056 | env->elr_el[new_el] = env->pc; | |
10057 | } else { | |
f944a854 | 10058 | old_mode = cpsr_read_for_spsr_elx(env); |
f3a9b694 PM |
10059 | env->elr_el[new_el] = env->regs[15]; |
10060 | ||
10061 | aarch64_sync_32_to_64(env); | |
10062 | ||
10063 | env->condexec_bits = 0; | |
10064 | } | |
4a2696c0 RH |
10065 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode; |
10066 | ||
f3a9b694 PM |
10067 | qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", |
10068 | env->elr_el[new_el]); | |
10069 | ||
4a2696c0 RH |
10070 | if (cpu_isar_feature(aa64_pan, cpu)) { |
10071 | /* The value of PSTATE.PAN is normally preserved, except when ... */ | |
10072 | new_mode |= old_mode & PSTATE_PAN; | |
10073 | switch (new_el) { | |
10074 | case 2: | |
10075 | /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */ | |
10076 | if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) | |
10077 | != (HCR_E2H | HCR_TGE)) { | |
10078 | break; | |
10079 | } | |
10080 | /* fall through */ | |
10081 | case 1: | |
10082 | /* ... the target is EL1 ... */ | |
10083 | /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */ | |
10084 | if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) == 0) { | |
10085 | new_mode |= PSTATE_PAN; | |
10086 | } | |
10087 | break; | |
10088 | } | |
10089 | } | |
34669338 RH |
10090 | if (cpu_isar_feature(aa64_mte, cpu)) { |
10091 | new_mode |= PSTATE_TCO; | |
10092 | } | |
4a2696c0 | 10093 | |
f2f68a78 RC |
10094 | if (cpu_isar_feature(aa64_ssbs, cpu)) { |
10095 | if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) { | |
10096 | new_mode |= PSTATE_SSBS; | |
10097 | } else { | |
10098 | new_mode &= ~PSTATE_SSBS; | |
10099 | } | |
10100 | } | |
10101 | ||
f3a9b694 | 10102 | pstate_write(env, PSTATE_DAIF | new_mode); |
53221552 | 10103 | env->aarch64 = true; |
f3a9b694 | 10104 | aarch64_restore_sp(env, new_el); |
a8a79c7a | 10105 | helper_rebuild_hflags_a64(env, new_el); |
f3a9b694 PM |
10106 | |
10107 | env->pc = addr; | |
10108 | ||
10109 | qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", | |
10110 | new_el, env->pc, pstate_read(env)); | |
966f758c PM |
10111 | } |
10112 | ||
ed6e6ba9 AB |
10113 | /* |
10114 | * Do semihosting call and set the appropriate return value. All the | |
10115 | * permission and validity checks have been done at translate time. | |
10116 | * | |
10117 | * We only see semihosting exceptions in TCG only as they are not | |
10118 | * trapped to the hypervisor in KVM. | |
10119 | */ | |
91f78c58 | 10120 | #ifdef CONFIG_TCG |
ed6e6ba9 AB |
10121 | static void handle_semihosting(CPUState *cs) |
10122 | { | |
904c04de PM |
10123 | ARMCPU *cpu = ARM_CPU(cs); |
10124 | CPUARMState *env = &cpu->env; | |
10125 | ||
10126 | if (is_a64(env)) { | |
ed6e6ba9 AB |
10127 | qemu_log_mask(CPU_LOG_INT, |
10128 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
10129 | env->xregs[0]); | |
0bb446d8 | 10130 | env->xregs[0] = do_common_semihosting(cs); |
4ff5ef9e | 10131 | env->pc += 4; |
904c04de | 10132 | } else { |
904c04de PM |
10133 | qemu_log_mask(CPU_LOG_INT, |
10134 | "...handling as semihosting call 0x%x\n", | |
10135 | env->regs[0]); | |
0bb446d8 | 10136 | env->regs[0] = do_common_semihosting(cs); |
4ff5ef9e | 10137 | env->regs[15] += env->thumb ? 2 : 4; |
904c04de PM |
10138 | } |
10139 | } | |
ed6e6ba9 | 10140 | #endif |
904c04de | 10141 | |
966f758c PM |
10142 | /* Handle a CPU exception for A and R profile CPUs. |
10143 | * Do any appropriate logging, handle PSCI calls, and then hand off | |
10144 | * to the AArch64-entry or AArch32-entry function depending on the | |
10145 | * target exception level's register width. | |
853bfef4 CF |
10146 | * |
10147 | * Note: this is used for both TCG (as the do_interrupt tcg op), | |
10148 | * and KVM to re-inject guest debug exceptions, and to | |
10149 | * inject a Synchronous-External-Abort. | |
966f758c PM |
10150 | */ |
10151 | void arm_cpu_do_interrupt(CPUState *cs) | |
10152 | { | |
10153 | ARMCPU *cpu = ARM_CPU(cs); | |
10154 | CPUARMState *env = &cpu->env; | |
10155 | unsigned int new_el = env->exception.target_el; | |
10156 | ||
531c60a9 | 10157 | assert(!arm_feature(env, ARM_FEATURE_M)); |
966f758c | 10158 | |
fc6177af | 10159 | arm_log_exception(cs); |
966f758c PM |
10160 | qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), |
10161 | new_el); | |
10162 | if (qemu_loglevel_mask(CPU_LOG_INT) | |
10163 | && !excp_is_internal(cs->exception_index)) { | |
6568da45 | 10164 | qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", |
64b91e3f | 10165 | syn_get_ec(env->exception.syndrome), |
966f758c PM |
10166 | env->exception.syndrome); |
10167 | } | |
10168 | ||
10169 | if (arm_is_psci_call(cpu, cs->exception_index)) { | |
10170 | arm_handle_psci_call(cpu); | |
10171 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | |
10172 | return; | |
10173 | } | |
10174 | ||
ed6e6ba9 AB |
10175 | /* |
10176 | * Semihosting semantics depend on the register width of the code | |
10177 | * that caused the exception, not the target exception level, so | |
10178 | * must be handled here. | |
966f758c | 10179 | */ |
ed6e6ba9 AB |
10180 | #ifdef CONFIG_TCG |
10181 | if (cs->exception_index == EXCP_SEMIHOST) { | |
10182 | handle_semihosting(cs); | |
904c04de PM |
10183 | return; |
10184 | } | |
ed6e6ba9 | 10185 | #endif |
904c04de | 10186 | |
b5c53d1b AL |
10187 | /* Hooks may change global state so BQL should be held, also the |
10188 | * BQL needs to be held for any modification of | |
10189 | * cs->interrupt_request. | |
10190 | */ | |
10191 | g_assert(qemu_mutex_iothread_locked()); | |
10192 | ||
10193 | arm_call_pre_el_change_hook(cpu); | |
10194 | ||
904c04de PM |
10195 | assert(!excp_is_internal(cs->exception_index)); |
10196 | if (arm_el_is_aa64(env, new_el)) { | |
966f758c PM |
10197 | arm_cpu_do_interrupt_aarch64(cs); |
10198 | } else { | |
10199 | arm_cpu_do_interrupt_aarch32(cs); | |
10200 | } | |
f3a9b694 | 10201 | |
bd7d00fc PM |
10202 | arm_call_el_change_hook(cpu); |
10203 | ||
f3a9b694 PM |
10204 | if (!kvm_enabled()) { |
10205 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
10206 | } | |
10207 | } | |
c47eaf9f | 10208 | #endif /* !CONFIG_USER_ONLY */ |
0480f69a | 10209 | |
aaec1432 RH |
10210 | uint64_t arm_sctlr(CPUARMState *env, int el) |
10211 | { | |
10212 | /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ | |
10213 | if (el == 0) { | |
10214 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0); | |
b6ad6062 RDC |
10215 | el = (mmu_idx == ARMMMUIdx_E20_0 || mmu_idx == ARMMMUIdx_SE20_0) |
10216 | ? 2 : 1; | |
aaec1432 RH |
10217 | } |
10218 | return env->cp15.sctlr_el[el]; | |
10219 | } | |
c47eaf9f | 10220 | |
0480f69a | 10221 | /* Return the SCTLR value which controls this address translation regime */ |
aaec1432 | 10222 | static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) |
0480f69a PM |
10223 | { |
10224 | return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; | |
10225 | } | |
10226 | ||
aaec1432 RH |
10227 | #ifndef CONFIG_USER_ONLY |
10228 | ||
0480f69a PM |
10229 | /* Return true if the specified stage of address translation is disabled */ |
10230 | static inline bool regime_translation_disabled(CPUARMState *env, | |
10231 | ARMMMUIdx mmu_idx) | |
10232 | { | |
e04a5752 RDC |
10233 | uint64_t hcr_el2; |
10234 | ||
29c483a5 | 10235 | if (arm_feature(env, ARM_FEATURE_M)) { |
ecf5e8ea | 10236 | switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & |
3bef7012 PM |
10237 | (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { |
10238 | case R_V7M_MPU_CTRL_ENABLE_MASK: | |
10239 | /* Enabled, but not for HardFault and NMI */ | |
62593718 | 10240 | return mmu_idx & ARM_MMU_IDX_M_NEGPRI; |
3bef7012 PM |
10241 | case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: |
10242 | /* Enabled for all cases */ | |
10243 | return false; | |
10244 | case 0: | |
10245 | default: | |
10246 | /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but | |
10247 | * we warned about that in armv7m_nvic.c when the guest set it. | |
10248 | */ | |
10249 | return true; | |
10250 | } | |
29c483a5 MD |
10251 | } |
10252 | ||
e04a5752 RDC |
10253 | hcr_el2 = arm_hcr_el2_eff(env); |
10254 | ||
b1a10c86 | 10255 | if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { |
9d1bab33 | 10256 | /* HCR.DC means HCR.VM behaves as 1 */ |
e04a5752 | 10257 | return (hcr_el2 & (HCR_DC | HCR_VM)) == 0; |
0480f69a | 10258 | } |
3d0e3080 | 10259 | |
e04a5752 | 10260 | if (hcr_el2 & HCR_TGE) { |
3d0e3080 PM |
10261 | /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ |
10262 | if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) { | |
10263 | return true; | |
10264 | } | |
10265 | } | |
10266 | ||
e04a5752 | 10267 | if ((hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { |
9d1bab33 PM |
10268 | /* HCR.DC means SCTLR_EL1.M behaves as 0 */ |
10269 | return true; | |
10270 | } | |
10271 | ||
0480f69a PM |
10272 | return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; |
10273 | } | |
10274 | ||
73462ddd PC |
10275 | static inline bool regime_translation_big_endian(CPUARMState *env, |
10276 | ARMMMUIdx mmu_idx) | |
10277 | { | |
10278 | return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; | |
10279 | } | |
10280 | ||
c47eaf9f PM |
10281 | /* Return the TTBR associated with this translation regime */ |
10282 | static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, | |
10283 | int ttbrn) | |
10284 | { | |
97fa9350 | 10285 | if (mmu_idx == ARMMMUIdx_Stage2) { |
c47eaf9f PM |
10286 | return env->cp15.vttbr_el2; |
10287 | } | |
b1a10c86 RDC |
10288 | if (mmu_idx == ARMMMUIdx_Stage2_S) { |
10289 | return env->cp15.vsttbr_el2; | |
10290 | } | |
c47eaf9f PM |
10291 | if (ttbrn == 0) { |
10292 | return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; | |
10293 | } else { | |
10294 | return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; | |
10295 | } | |
10296 | } | |
10297 | ||
10298 | #endif /* !CONFIG_USER_ONLY */ | |
10299 | ||
8bd5c820 PM |
10300 | /* Convert a possible stage1+2 MMU index into the appropriate |
10301 | * stage 1 MMU index | |
10302 | */ | |
10303 | static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) | |
10304 | { | |
b9f6033c | 10305 | switch (mmu_idx) { |
b1a10c86 RDC |
10306 | case ARMMMUIdx_SE10_0: |
10307 | return ARMMMUIdx_Stage1_SE0; | |
10308 | case ARMMMUIdx_SE10_1: | |
10309 | return ARMMMUIdx_Stage1_SE1; | |
10310 | case ARMMMUIdx_SE10_1_PAN: | |
10311 | return ARMMMUIdx_Stage1_SE1_PAN; | |
b9f6033c RH |
10312 | case ARMMMUIdx_E10_0: |
10313 | return ARMMMUIdx_Stage1_E0; | |
10314 | case ARMMMUIdx_E10_1: | |
10315 | return ARMMMUIdx_Stage1_E1; | |
452ef8cb RH |
10316 | case ARMMMUIdx_E10_1_PAN: |
10317 | return ARMMMUIdx_Stage1_E1_PAN; | |
b9f6033c RH |
10318 | default: |
10319 | return mmu_idx; | |
8bd5c820 | 10320 | } |
8bd5c820 PM |
10321 | } |
10322 | ||
0480f69a PM |
10323 | /* Return true if the translation regime is using LPAE format page tables */ |
10324 | static inline bool regime_using_lpae_format(CPUARMState *env, | |
10325 | ARMMMUIdx mmu_idx) | |
10326 | { | |
10327 | int el = regime_el(env, mmu_idx); | |
10328 | if (el == 2 || arm_el_is_aa64(env, el)) { | |
10329 | return true; | |
10330 | } | |
10331 | if (arm_feature(env, ARM_FEATURE_LPAE) | |
10332 | && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { | |
10333 | return true; | |
10334 | } | |
10335 | return false; | |
10336 | } | |
10337 | ||
deb2db99 AR |
10338 | /* Returns true if the stage 1 translation regime is using LPAE format page |
10339 | * tables. Used when raising alignment exceptions, whose FSR changes depending | |
10340 | * on whether the long or short descriptor format is in use. */ | |
10341 | bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) | |
30901475 | 10342 | { |
8bd5c820 | 10343 | mmu_idx = stage_1_mmu_idx(mmu_idx); |
deb2db99 | 10344 | |
30901475 AB |
10345 | return regime_using_lpae_format(env, mmu_idx); |
10346 | } | |
10347 | ||
c47eaf9f | 10348 | #ifndef CONFIG_USER_ONLY |
0480f69a PM |
10349 | static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) |
10350 | { | |
10351 | switch (mmu_idx) { | |
fba37aed | 10352 | case ARMMMUIdx_SE10_0: |
b9f6033c | 10353 | case ARMMMUIdx_E20_0: |
b6ad6062 | 10354 | case ARMMMUIdx_SE20_0: |
2859d7b5 | 10355 | case ARMMMUIdx_Stage1_E0: |
b1a10c86 | 10356 | case ARMMMUIdx_Stage1_SE0: |
e7b921c2 | 10357 | case ARMMMUIdx_MUser: |
871bec7c | 10358 | case ARMMMUIdx_MSUser: |
62593718 PM |
10359 | case ARMMMUIdx_MUserNegPri: |
10360 | case ARMMMUIdx_MSUserNegPri: | |
0480f69a PM |
10361 | return true; |
10362 | default: | |
10363 | return false; | |
01b98b68 RH |
10364 | case ARMMMUIdx_E10_0: |
10365 | case ARMMMUIdx_E10_1: | |
452ef8cb | 10366 | case ARMMMUIdx_E10_1_PAN: |
0480f69a PM |
10367 | g_assert_not_reached(); |
10368 | } | |
10369 | } | |
10370 | ||
0fbf5238 AJ |
10371 | /* Translate section/page access permissions to page |
10372 | * R/W protection flags | |
d76951b6 AJ |
10373 | * |
10374 | * @env: CPUARMState | |
10375 | * @mmu_idx: MMU index indicating required translation regime | |
10376 | * @ap: The 3-bit access permissions (AP[2:0]) | |
10377 | * @domain_prot: The 2-bit domain access permissions | |
0fbf5238 AJ |
10378 | */ |
10379 | static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, | |
10380 | int ap, int domain_prot) | |
10381 | { | |
554b0b09 PM |
10382 | bool is_user = regime_is_user(env, mmu_idx); |
10383 | ||
10384 | if (domain_prot == 3) { | |
10385 | return PAGE_READ | PAGE_WRITE; | |
10386 | } | |
10387 | ||
554b0b09 PM |
10388 | switch (ap) { |
10389 | case 0: | |
10390 | if (arm_feature(env, ARM_FEATURE_V7)) { | |
10391 | return 0; | |
10392 | } | |
554b0b09 PM |
10393 | switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) { |
10394 | case SCTLR_S: | |
10395 | return is_user ? 0 : PAGE_READ; | |
10396 | case SCTLR_R: | |
10397 | return PAGE_READ; | |
10398 | default: | |
10399 | return 0; | |
10400 | } | |
10401 | case 1: | |
10402 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
10403 | case 2: | |
87c3d486 | 10404 | if (is_user) { |
0fbf5238 | 10405 | return PAGE_READ; |
87c3d486 | 10406 | } else { |
554b0b09 | 10407 | return PAGE_READ | PAGE_WRITE; |
87c3d486 | 10408 | } |
554b0b09 PM |
10409 | case 3: |
10410 | return PAGE_READ | PAGE_WRITE; | |
10411 | case 4: /* Reserved. */ | |
10412 | return 0; | |
10413 | case 5: | |
0fbf5238 | 10414 | return is_user ? 0 : PAGE_READ; |
554b0b09 | 10415 | case 6: |
0fbf5238 | 10416 | return PAGE_READ; |
554b0b09 | 10417 | case 7: |
87c3d486 | 10418 | if (!arm_feature(env, ARM_FEATURE_V6K)) { |
554b0b09 | 10419 | return 0; |
87c3d486 | 10420 | } |
0fbf5238 | 10421 | return PAGE_READ; |
554b0b09 | 10422 | default: |
0fbf5238 | 10423 | g_assert_not_reached(); |
554b0b09 | 10424 | } |
b5ff1b31 FB |
10425 | } |
10426 | ||
d76951b6 AJ |
10427 | /* Translate section/page access permissions to page |
10428 | * R/W protection flags. | |
10429 | * | |
d76951b6 | 10430 | * @ap: The 2-bit simple AP (AP[2:1]) |
d8e052b3 | 10431 | * @is_user: TRUE if accessing from PL0 |
d76951b6 | 10432 | */ |
d8e052b3 | 10433 | static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user) |
d76951b6 | 10434 | { |
d76951b6 AJ |
10435 | switch (ap) { |
10436 | case 0: | |
10437 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
10438 | case 1: | |
10439 | return PAGE_READ | PAGE_WRITE; | |
10440 | case 2: | |
10441 | return is_user ? 0 : PAGE_READ; | |
10442 | case 3: | |
10443 | return PAGE_READ; | |
10444 | default: | |
10445 | g_assert_not_reached(); | |
10446 | } | |
10447 | } | |
10448 | ||
d8e052b3 AJ |
10449 | static inline int |
10450 | simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) | |
10451 | { | |
10452 | return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); | |
10453 | } | |
10454 | ||
6ab1a5ee EI |
10455 | /* Translate S2 section/page access permissions to protection flags |
10456 | * | |
10457 | * @env: CPUARMState | |
10458 | * @s2ap: The 2-bit stage2 access permissions (S2AP) | |
ce3125be PM |
10459 | * @xn: XN (execute-never) bits |
10460 | * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0 | |
6ab1a5ee | 10461 | */ |
ce3125be | 10462 | static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) |
6ab1a5ee EI |
10463 | { |
10464 | int prot = 0; | |
10465 | ||
10466 | if (s2ap & 1) { | |
10467 | prot |= PAGE_READ; | |
10468 | } | |
10469 | if (s2ap & 2) { | |
10470 | prot |= PAGE_WRITE; | |
10471 | } | |
ce3125be PM |
10472 | |
10473 | if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) { | |
10474 | switch (xn) { | |
10475 | case 0: | |
dfda6837 | 10476 | prot |= PAGE_EXEC; |
ce3125be PM |
10477 | break; |
10478 | case 1: | |
10479 | if (s1_is_el0) { | |
10480 | prot |= PAGE_EXEC; | |
10481 | } | |
10482 | break; | |
10483 | case 2: | |
10484 | break; | |
10485 | case 3: | |
10486 | if (!s1_is_el0) { | |
10487 | prot |= PAGE_EXEC; | |
10488 | } | |
10489 | break; | |
10490 | default: | |
10491 | g_assert_not_reached(); | |
10492 | } | |
10493 | } else { | |
10494 | if (!extract32(xn, 1, 1)) { | |
10495 | if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { | |
10496 | prot |= PAGE_EXEC; | |
10497 | } | |
dfda6837 | 10498 | } |
6ab1a5ee EI |
10499 | } |
10500 | return prot; | |
10501 | } | |
10502 | ||
d8e052b3 AJ |
10503 | /* Translate section/page access permissions to protection flags |
10504 | * | |
10505 | * @env: CPUARMState | |
10506 | * @mmu_idx: MMU index indicating required translation regime | |
10507 | * @is_aa64: TRUE if AArch64 | |
10508 | * @ap: The 2-bit simple AP (AP[2:1]) | |
10509 | * @ns: NS (non-secure) bit | |
10510 | * @xn: XN (execute-never) bit | |
10511 | * @pxn: PXN (privileged execute-never) bit | |
10512 | */ | |
10513 | static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, | |
10514 | int ap, int ns, int xn, int pxn) | |
10515 | { | |
10516 | bool is_user = regime_is_user(env, mmu_idx); | |
10517 | int prot_rw, user_rw; | |
10518 | bool have_wxn; | |
10519 | int wxn = 0; | |
10520 | ||
97fa9350 | 10521 | assert(mmu_idx != ARMMMUIdx_Stage2); |
b1a10c86 | 10522 | assert(mmu_idx != ARMMMUIdx_Stage2_S); |
d8e052b3 AJ |
10523 | |
10524 | user_rw = simple_ap_to_rw_prot_is_user(ap, true); | |
10525 | if (is_user) { | |
10526 | prot_rw = user_rw; | |
10527 | } else { | |
81636b70 | 10528 | if (user_rw && regime_is_pan(env, mmu_idx)) { |
f4e1dbc5 PM |
10529 | /* PAN forbids data accesses but doesn't affect insn fetch */ |
10530 | prot_rw = 0; | |
10531 | } else { | |
10532 | prot_rw = simple_ap_to_rw_prot_is_user(ap, false); | |
81636b70 | 10533 | } |
d8e052b3 AJ |
10534 | } |
10535 | ||
10536 | if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { | |
10537 | return prot_rw; | |
10538 | } | |
10539 | ||
10540 | /* TODO have_wxn should be replaced with | |
10541 | * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) | |
10542 | * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE | |
10543 | * compatible processors have EL2, which is required for [U]WXN. | |
10544 | */ | |
10545 | have_wxn = arm_feature(env, ARM_FEATURE_LPAE); | |
10546 | ||
10547 | if (have_wxn) { | |
10548 | wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN; | |
10549 | } | |
10550 | ||
10551 | if (is_aa64) { | |
339370b9 RH |
10552 | if (regime_has_2_ranges(mmu_idx) && !is_user) { |
10553 | xn = pxn || (user_rw & PAGE_WRITE); | |
d8e052b3 AJ |
10554 | } |
10555 | } else if (arm_feature(env, ARM_FEATURE_V7)) { | |
10556 | switch (regime_el(env, mmu_idx)) { | |
10557 | case 1: | |
10558 | case 3: | |
10559 | if (is_user) { | |
10560 | xn = xn || !(user_rw & PAGE_READ); | |
10561 | } else { | |
10562 | int uwxn = 0; | |
10563 | if (have_wxn) { | |
10564 | uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN; | |
10565 | } | |
10566 | xn = xn || !(prot_rw & PAGE_READ) || pxn || | |
10567 | (uwxn && (user_rw & PAGE_WRITE)); | |
10568 | } | |
10569 | break; | |
10570 | case 2: | |
10571 | break; | |
10572 | } | |
10573 | } else { | |
10574 | xn = wxn = 0; | |
10575 | } | |
10576 | ||
10577 | if (xn || (wxn && (prot_rw & PAGE_WRITE))) { | |
10578 | return prot_rw; | |
10579 | } | |
10580 | return prot_rw | PAGE_EXEC; | |
10581 | } | |
10582 | ||
0480f69a PM |
10583 | static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, |
10584 | uint32_t *table, uint32_t address) | |
b2fa1797 | 10585 | { |
0480f69a | 10586 | /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ |
0480f69a | 10587 | TCR *tcr = regime_tcr(env, mmu_idx); |
11f136ee | 10588 | |
11f136ee FA |
10589 | if (address & tcr->mask) { |
10590 | if (tcr->raw_tcr & TTBCR_PD1) { | |
e389be16 FA |
10591 | /* Translation table walk disabled for TTBR1 */ |
10592 | return false; | |
10593 | } | |
aef878be | 10594 | *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; |
e389be16 | 10595 | } else { |
11f136ee | 10596 | if (tcr->raw_tcr & TTBCR_PD0) { |
e389be16 FA |
10597 | /* Translation table walk disabled for TTBR0 */ |
10598 | return false; | |
10599 | } | |
aef878be | 10600 | *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; |
e389be16 FA |
10601 | } |
10602 | *table |= (address >> 18) & 0x3ffc; | |
10603 | return true; | |
b2fa1797 PB |
10604 | } |
10605 | ||
37785977 EI |
10606 | /* Translate a S1 pagetable walk through S2 if needed. */ |
10607 | static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, | |
3d4bd397 | 10608 | hwaddr addr, bool *is_secure, |
37785977 EI |
10609 | ARMMMUFaultInfo *fi) |
10610 | { | |
fee7aa46 | 10611 | if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && |
97fa9350 | 10612 | !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { |
37785977 EI |
10613 | target_ulong s2size; |
10614 | hwaddr s2pa; | |
10615 | int s2prot; | |
10616 | int ret; | |
b1a10c86 RDC |
10617 | ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S |
10618 | : ARMMMUIdx_Stage2; | |
eadb2feb | 10619 | ARMCacheAttrs cacheattrs = {}; |
3d4bd397 RDC |
10620 | MemTxAttrs txattrs = {}; |
10621 | ||
b1a10c86 | 10622 | ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false, |
59dff859 | 10623 | &s2pa, &txattrs, &s2prot, &s2size, fi, |
a6d6f37a | 10624 | &cacheattrs); |
37785977 | 10625 | if (ret) { |
3b39d734 | 10626 | assert(fi->type != ARMFault_None); |
37785977 EI |
10627 | fi->s2addr = addr; |
10628 | fi->stage2 = true; | |
10629 | fi->s1ptw = true; | |
9861248f | 10630 | fi->s1ns = !*is_secure; |
37785977 EI |
10631 | return ~0; |
10632 | } | |
e04a5752 RDC |
10633 | if ((arm_hcr_el2_eff(env) & HCR_PTW) && |
10634 | (cacheattrs.attrs & 0xf0) == 0) { | |
a6d6f37a RH |
10635 | /* |
10636 | * PTW set and S1 walk touched S2 Device memory: | |
10637 | * generate Permission fault. | |
10638 | */ | |
eadb2feb PM |
10639 | fi->type = ARMFault_Permission; |
10640 | fi->s2addr = addr; | |
10641 | fi->stage2 = true; | |
10642 | fi->s1ptw = true; | |
9861248f | 10643 | fi->s1ns = !*is_secure; |
eadb2feb PM |
10644 | return ~0; |
10645 | } | |
588c6dd1 RDC |
10646 | |
10647 | if (arm_is_secure_below_el3(env)) { | |
10648 | /* Check if page table walk is to secure or non-secure PA space. */ | |
10649 | if (*is_secure) { | |
10650 | *is_secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); | |
10651 | } else { | |
10652 | *is_secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); | |
10653 | } | |
10654 | } else { | |
10655 | assert(!*is_secure); | |
10656 | } | |
10657 | ||
37785977 EI |
10658 | addr = s2pa; |
10659 | } | |
10660 | return addr; | |
10661 | } | |
10662 | ||
14577270 | 10663 | /* All loads done in the course of a page table walk go through here. */ |
a614e698 | 10664 | static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, |
3795a6de | 10665 | ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) |
ebca90e4 | 10666 | { |
a614e698 EI |
10667 | ARMCPU *cpu = ARM_CPU(cs); |
10668 | CPUARMState *env = &cpu->env; | |
ebca90e4 | 10669 | MemTxAttrs attrs = {}; |
3b39d734 | 10670 | MemTxResult result = MEMTX_OK; |
5ce4ff65 | 10671 | AddressSpace *as; |
3b39d734 | 10672 | uint32_t data; |
ebca90e4 | 10673 | |
3d4bd397 | 10674 | addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); |
ebca90e4 | 10675 | attrs.secure = is_secure; |
5ce4ff65 | 10676 | as = arm_addressspace(cs, attrs); |
a614e698 EI |
10677 | if (fi->s1ptw) { |
10678 | return 0; | |
10679 | } | |
73462ddd | 10680 | if (regime_translation_big_endian(env, mmu_idx)) { |
3b39d734 | 10681 | data = address_space_ldl_be(as, addr, attrs, &result); |
73462ddd | 10682 | } else { |
3b39d734 | 10683 | data = address_space_ldl_le(as, addr, attrs, &result); |
73462ddd | 10684 | } |
3b39d734 PM |
10685 | if (result == MEMTX_OK) { |
10686 | return data; | |
10687 | } | |
10688 | fi->type = ARMFault_SyncExternalOnWalk; | |
10689 | fi->ea = arm_extabort_type(result); | |
10690 | return 0; | |
ebca90e4 PM |
10691 | } |
10692 | ||
37785977 | 10693 | static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, |
3795a6de | 10694 | ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) |
ebca90e4 | 10695 | { |
37785977 EI |
10696 | ARMCPU *cpu = ARM_CPU(cs); |
10697 | CPUARMState *env = &cpu->env; | |
ebca90e4 | 10698 | MemTxAttrs attrs = {}; |
3b39d734 | 10699 | MemTxResult result = MEMTX_OK; |
5ce4ff65 | 10700 | AddressSpace *as; |
9aea1ea3 | 10701 | uint64_t data; |
ebca90e4 | 10702 | |
3d4bd397 | 10703 | addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); |
ebca90e4 | 10704 | attrs.secure = is_secure; |
5ce4ff65 | 10705 | as = arm_addressspace(cs, attrs); |
37785977 EI |
10706 | if (fi->s1ptw) { |
10707 | return 0; | |
10708 | } | |
73462ddd | 10709 | if (regime_translation_big_endian(env, mmu_idx)) { |
3b39d734 | 10710 | data = address_space_ldq_be(as, addr, attrs, &result); |
73462ddd | 10711 | } else { |
3b39d734 PM |
10712 | data = address_space_ldq_le(as, addr, attrs, &result); |
10713 | } | |
10714 | if (result == MEMTX_OK) { | |
10715 | return data; | |
73462ddd | 10716 | } |
3b39d734 PM |
10717 | fi->type = ARMFault_SyncExternalOnWalk; |
10718 | fi->ea = arm_extabort_type(result); | |
10719 | return 0; | |
ebca90e4 PM |
10720 | } |
10721 | ||
b7cc4e82 | 10722 | static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, |
03ae85f8 | 10723 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
b7cc4e82 | 10724 | hwaddr *phys_ptr, int *prot, |
f989983e | 10725 | target_ulong *page_size, |
e14b5a23 | 10726 | ARMMMUFaultInfo *fi) |
b5ff1b31 | 10727 | { |
2fc0cc0e | 10728 | CPUState *cs = env_cpu(env); |
f989983e | 10729 | int level = 1; |
b5ff1b31 FB |
10730 | uint32_t table; |
10731 | uint32_t desc; | |
10732 | int type; | |
10733 | int ap; | |
e389be16 | 10734 | int domain = 0; |
dd4ebc2e | 10735 | int domain_prot; |
a8170e5e | 10736 | hwaddr phys_addr; |
0480f69a | 10737 | uint32_t dacr; |
b5ff1b31 | 10738 | |
9ee6e8bb PB |
10739 | /* Pagetable walk. */ |
10740 | /* Lookup l1 descriptor. */ | |
0480f69a | 10741 | if (!get_level1_table_address(env, mmu_idx, &table, address)) { |
e389be16 | 10742 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ |
f989983e | 10743 | fi->type = ARMFault_Translation; |
e389be16 FA |
10744 | goto do_fault; |
10745 | } | |
a614e698 | 10746 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 10747 | mmu_idx, fi); |
3b39d734 PM |
10748 | if (fi->type != ARMFault_None) { |
10749 | goto do_fault; | |
10750 | } | |
9ee6e8bb | 10751 | type = (desc & 3); |
dd4ebc2e | 10752 | domain = (desc >> 5) & 0x0f; |
0480f69a PM |
10753 | if (regime_el(env, mmu_idx) == 1) { |
10754 | dacr = env->cp15.dacr_ns; | |
10755 | } else { | |
10756 | dacr = env->cp15.dacr_s; | |
10757 | } | |
10758 | domain_prot = (dacr >> (domain * 2)) & 3; | |
9ee6e8bb | 10759 | if (type == 0) { |
601d70b9 | 10760 | /* Section translation fault. */ |
f989983e | 10761 | fi->type = ARMFault_Translation; |
9ee6e8bb PB |
10762 | goto do_fault; |
10763 | } | |
f989983e PM |
10764 | if (type != 2) { |
10765 | level = 2; | |
10766 | } | |
dd4ebc2e | 10767 | if (domain_prot == 0 || domain_prot == 2) { |
f989983e | 10768 | fi->type = ARMFault_Domain; |
9ee6e8bb PB |
10769 | goto do_fault; |
10770 | } | |
10771 | if (type == 2) { | |
10772 | /* 1Mb section. */ | |
10773 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
10774 | ap = (desc >> 10) & 3; | |
d4c430a8 | 10775 | *page_size = 1024 * 1024; |
9ee6e8bb PB |
10776 | } else { |
10777 | /* Lookup l2 entry. */ | |
554b0b09 PM |
10778 | if (type == 1) { |
10779 | /* Coarse pagetable. */ | |
10780 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
10781 | } else { | |
10782 | /* Fine pagetable. */ | |
10783 | table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); | |
10784 | } | |
a614e698 | 10785 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 10786 | mmu_idx, fi); |
3b39d734 PM |
10787 | if (fi->type != ARMFault_None) { |
10788 | goto do_fault; | |
10789 | } | |
9ee6e8bb PB |
10790 | switch (desc & 3) { |
10791 | case 0: /* Page translation fault. */ | |
f989983e | 10792 | fi->type = ARMFault_Translation; |
9ee6e8bb PB |
10793 | goto do_fault; |
10794 | case 1: /* 64k page. */ | |
10795 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
10796 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
d4c430a8 | 10797 | *page_size = 0x10000; |
ce819861 | 10798 | break; |
9ee6e8bb PB |
10799 | case 2: /* 4k page. */ |
10800 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
c10f7fc3 | 10801 | ap = (desc >> (4 + ((address >> 9) & 6))) & 3; |
d4c430a8 | 10802 | *page_size = 0x1000; |
ce819861 | 10803 | break; |
fc1891c7 | 10804 | case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ |
554b0b09 | 10805 | if (type == 1) { |
fc1891c7 PM |
10806 | /* ARMv6/XScale extended small page format */ |
10807 | if (arm_feature(env, ARM_FEATURE_XSCALE) | |
10808 | || arm_feature(env, ARM_FEATURE_V6)) { | |
554b0b09 | 10809 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
fc1891c7 | 10810 | *page_size = 0x1000; |
554b0b09 | 10811 | } else { |
fc1891c7 PM |
10812 | /* UNPREDICTABLE in ARMv5; we choose to take a |
10813 | * page translation fault. | |
10814 | */ | |
f989983e | 10815 | fi->type = ARMFault_Translation; |
554b0b09 PM |
10816 | goto do_fault; |
10817 | } | |
10818 | } else { | |
10819 | phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); | |
fc1891c7 | 10820 | *page_size = 0x400; |
554b0b09 | 10821 | } |
9ee6e8bb | 10822 | ap = (desc >> 4) & 3; |
ce819861 PB |
10823 | break; |
10824 | default: | |
9ee6e8bb PB |
10825 | /* Never happens, but compiler isn't smart enough to tell. */ |
10826 | abort(); | |
ce819861 | 10827 | } |
9ee6e8bb | 10828 | } |
0fbf5238 AJ |
10829 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); |
10830 | *prot |= *prot ? PAGE_EXEC : 0; | |
10831 | if (!(*prot & (1 << access_type))) { | |
9ee6e8bb | 10832 | /* Access permission fault. */ |
f989983e | 10833 | fi->type = ARMFault_Permission; |
9ee6e8bb PB |
10834 | goto do_fault; |
10835 | } | |
10836 | *phys_ptr = phys_addr; | |
b7cc4e82 | 10837 | return false; |
9ee6e8bb | 10838 | do_fault: |
f989983e PM |
10839 | fi->domain = domain; |
10840 | fi->level = level; | |
b7cc4e82 | 10841 | return true; |
9ee6e8bb PB |
10842 | } |
10843 | ||
b7cc4e82 | 10844 | static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, |
03ae85f8 | 10845 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
b7cc4e82 | 10846 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, |
f06cf243 | 10847 | target_ulong *page_size, ARMMMUFaultInfo *fi) |
9ee6e8bb | 10848 | { |
2fc0cc0e | 10849 | CPUState *cs = env_cpu(env); |
0ae0326b | 10850 | ARMCPU *cpu = env_archcpu(env); |
f06cf243 | 10851 | int level = 1; |
9ee6e8bb PB |
10852 | uint32_t table; |
10853 | uint32_t desc; | |
10854 | uint32_t xn; | |
de9b05b8 | 10855 | uint32_t pxn = 0; |
9ee6e8bb PB |
10856 | int type; |
10857 | int ap; | |
de9b05b8 | 10858 | int domain = 0; |
dd4ebc2e | 10859 | int domain_prot; |
a8170e5e | 10860 | hwaddr phys_addr; |
0480f69a | 10861 | uint32_t dacr; |
8bf5b6a9 | 10862 | bool ns; |
9ee6e8bb PB |
10863 | |
10864 | /* Pagetable walk. */ | |
10865 | /* Lookup l1 descriptor. */ | |
0480f69a | 10866 | if (!get_level1_table_address(env, mmu_idx, &table, address)) { |
e389be16 | 10867 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ |
f06cf243 | 10868 | fi->type = ARMFault_Translation; |
e389be16 FA |
10869 | goto do_fault; |
10870 | } | |
a614e698 | 10871 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 10872 | mmu_idx, fi); |
3b39d734 PM |
10873 | if (fi->type != ARMFault_None) { |
10874 | goto do_fault; | |
10875 | } | |
9ee6e8bb | 10876 | type = (desc & 3); |
0ae0326b | 10877 | if (type == 0 || (type == 3 && !cpu_isar_feature(aa32_pxn, cpu))) { |
de9b05b8 PM |
10878 | /* Section translation fault, or attempt to use the encoding |
10879 | * which is Reserved on implementations without PXN. | |
10880 | */ | |
f06cf243 | 10881 | fi->type = ARMFault_Translation; |
9ee6e8bb | 10882 | goto do_fault; |
de9b05b8 PM |
10883 | } |
10884 | if ((type == 1) || !(desc & (1 << 18))) { | |
10885 | /* Page or Section. */ | |
dd4ebc2e | 10886 | domain = (desc >> 5) & 0x0f; |
9ee6e8bb | 10887 | } |
0480f69a PM |
10888 | if (regime_el(env, mmu_idx) == 1) { |
10889 | dacr = env->cp15.dacr_ns; | |
10890 | } else { | |
10891 | dacr = env->cp15.dacr_s; | |
10892 | } | |
f06cf243 PM |
10893 | if (type == 1) { |
10894 | level = 2; | |
10895 | } | |
0480f69a | 10896 | domain_prot = (dacr >> (domain * 2)) & 3; |
dd4ebc2e | 10897 | if (domain_prot == 0 || domain_prot == 2) { |
f06cf243 PM |
10898 | /* Section or Page domain fault */ |
10899 | fi->type = ARMFault_Domain; | |
9ee6e8bb PB |
10900 | goto do_fault; |
10901 | } | |
de9b05b8 | 10902 | if (type != 1) { |
9ee6e8bb PB |
10903 | if (desc & (1 << 18)) { |
10904 | /* Supersection. */ | |
10905 | phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); | |
4e42a6ca SF |
10906 | phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32; |
10907 | phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36; | |
d4c430a8 | 10908 | *page_size = 0x1000000; |
b5ff1b31 | 10909 | } else { |
9ee6e8bb PB |
10910 | /* Section. */ |
10911 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
d4c430a8 | 10912 | *page_size = 0x100000; |
b5ff1b31 | 10913 | } |
9ee6e8bb PB |
10914 | ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
10915 | xn = desc & (1 << 4); | |
de9b05b8 | 10916 | pxn = desc & 1; |
8bf5b6a9 | 10917 | ns = extract32(desc, 19, 1); |
9ee6e8bb | 10918 | } else { |
0ae0326b | 10919 | if (cpu_isar_feature(aa32_pxn, cpu)) { |
de9b05b8 PM |
10920 | pxn = (desc >> 2) & 1; |
10921 | } | |
8bf5b6a9 | 10922 | ns = extract32(desc, 3, 1); |
9ee6e8bb PB |
10923 | /* Lookup l2 entry. */ |
10924 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
a614e698 | 10925 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 10926 | mmu_idx, fi); |
3b39d734 PM |
10927 | if (fi->type != ARMFault_None) { |
10928 | goto do_fault; | |
10929 | } | |
9ee6e8bb PB |
10930 | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
10931 | switch (desc & 3) { | |
10932 | case 0: /* Page translation fault. */ | |
f06cf243 | 10933 | fi->type = ARMFault_Translation; |
b5ff1b31 | 10934 | goto do_fault; |
9ee6e8bb PB |
10935 | case 1: /* 64k page. */ |
10936 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
10937 | xn = desc & (1 << 15); | |
d4c430a8 | 10938 | *page_size = 0x10000; |
9ee6e8bb PB |
10939 | break; |
10940 | case 2: case 3: /* 4k page. */ | |
10941 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
10942 | xn = desc & 1; | |
d4c430a8 | 10943 | *page_size = 0x1000; |
9ee6e8bb PB |
10944 | break; |
10945 | default: | |
10946 | /* Never happens, but compiler isn't smart enough to tell. */ | |
10947 | abort(); | |
b5ff1b31 | 10948 | } |
9ee6e8bb | 10949 | } |
dd4ebc2e | 10950 | if (domain_prot == 3) { |
c0034328 JR |
10951 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
10952 | } else { | |
0480f69a | 10953 | if (pxn && !regime_is_user(env, mmu_idx)) { |
de9b05b8 PM |
10954 | xn = 1; |
10955 | } | |
f06cf243 PM |
10956 | if (xn && access_type == MMU_INST_FETCH) { |
10957 | fi->type = ARMFault_Permission; | |
c0034328 | 10958 | goto do_fault; |
f06cf243 | 10959 | } |
9ee6e8bb | 10960 | |
d76951b6 AJ |
10961 | if (arm_feature(env, ARM_FEATURE_V6K) && |
10962 | (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { | |
10963 | /* The simplified model uses AP[0] as an access control bit. */ | |
10964 | if ((ap & 1) == 0) { | |
10965 | /* Access flag fault. */ | |
f06cf243 | 10966 | fi->type = ARMFault_AccessFlag; |
d76951b6 AJ |
10967 | goto do_fault; |
10968 | } | |
10969 | *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); | |
10970 | } else { | |
10971 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); | |
c0034328 | 10972 | } |
0fbf5238 AJ |
10973 | if (*prot && !xn) { |
10974 | *prot |= PAGE_EXEC; | |
10975 | } | |
10976 | if (!(*prot & (1 << access_type))) { | |
c0034328 | 10977 | /* Access permission fault. */ |
f06cf243 | 10978 | fi->type = ARMFault_Permission; |
c0034328 JR |
10979 | goto do_fault; |
10980 | } | |
3ad493fc | 10981 | } |
8bf5b6a9 PM |
10982 | if (ns) { |
10983 | /* The NS bit will (as required by the architecture) have no effect if | |
10984 | * the CPU doesn't support TZ or this is a non-secure translation | |
10985 | * regime, because the attribute will already be non-secure. | |
10986 | */ | |
10987 | attrs->secure = false; | |
10988 | } | |
9ee6e8bb | 10989 | *phys_ptr = phys_addr; |
b7cc4e82 | 10990 | return false; |
b5ff1b31 | 10991 | do_fault: |
f06cf243 PM |
10992 | fi->domain = domain; |
10993 | fi->level = level; | |
b7cc4e82 | 10994 | return true; |
b5ff1b31 FB |
10995 | } |
10996 | ||
1853d5a9 | 10997 | /* |
a0e966c9 | 10998 | * check_s2_mmu_setup |
1853d5a9 EI |
10999 | * @cpu: ARMCPU |
11000 | * @is_aa64: True if the translation regime is in AArch64 state | |
11001 | * @startlevel: Suggested starting level | |
11002 | * @inputsize: Bitsize of IPAs | |
11003 | * @stride: Page-table stride (See the ARM ARM) | |
11004 | * | |
a0e966c9 EI |
11005 | * Returns true if the suggested S2 translation parameters are OK and |
11006 | * false otherwise. | |
1853d5a9 | 11007 | */ |
a0e966c9 | 11008 | static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, |
49ba115b | 11009 | int inputsize, int stride, int outputsize) |
1853d5a9 | 11010 | { |
98d68ec2 EI |
11011 | const int grainsize = stride + 3; |
11012 | int startsizecheck; | |
11013 | ||
ef56c242 RH |
11014 | /* |
11015 | * Negative levels are usually not allowed... | |
11016 | * Except for FEAT_LPA2, 4k page table, 52-bit address space, which | |
11017 | * begins with level -1. Note that previous feature tests will have | |
11018 | * eliminated this combination if it is not enabled. | |
11019 | */ | |
11020 | if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) { | |
1853d5a9 EI |
11021 | return false; |
11022 | } | |
11023 | ||
98d68ec2 EI |
11024 | startsizecheck = inputsize - ((3 - level) * stride + grainsize); |
11025 | if (startsizecheck < 1 || startsizecheck > stride + 4) { | |
11026 | return false; | |
11027 | } | |
11028 | ||
1853d5a9 | 11029 | if (is_aa64) { |
1853d5a9 EI |
11030 | switch (stride) { |
11031 | case 13: /* 64KB Pages. */ | |
49ba115b | 11032 | if (level == 0 || (level == 1 && outputsize <= 42)) { |
1853d5a9 EI |
11033 | return false; |
11034 | } | |
11035 | break; | |
11036 | case 11: /* 16KB Pages. */ | |
49ba115b | 11037 | if (level == 0 || (level == 1 && outputsize <= 40)) { |
1853d5a9 EI |
11038 | return false; |
11039 | } | |
11040 | break; | |
11041 | case 9: /* 4KB Pages. */ | |
49ba115b | 11042 | if (level == 0 && outputsize <= 42) { |
1853d5a9 EI |
11043 | return false; |
11044 | } | |
11045 | break; | |
11046 | default: | |
11047 | g_assert_not_reached(); | |
11048 | } | |
3526423e EI |
11049 | |
11050 | /* Inputsize checks. */ | |
49ba115b RH |
11051 | if (inputsize > outputsize && |
11052 | (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) { | |
3526423e EI |
11053 | /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ |
11054 | return false; | |
11055 | } | |
1853d5a9 | 11056 | } else { |
1853d5a9 EI |
11057 | /* AArch32 only supports 4KB pages. Assert on that. */ |
11058 | assert(stride == 9); | |
11059 | ||
11060 | if (level == 0) { | |
11061 | return false; | |
11062 | } | |
1853d5a9 EI |
11063 | } |
11064 | return true; | |
11065 | } | |
11066 | ||
5b2d261d AB |
11067 | /* Translate from the 4-bit stage 2 representation of |
11068 | * memory attributes (without cache-allocation hints) to | |
11069 | * the 8-bit representation of the stage 1 MAIR registers | |
11070 | * (which includes allocation hints). | |
11071 | * | |
11072 | * ref: shared/translation/attrs/S2AttrDecode() | |
11073 | * .../S2ConvertAttrsHints() | |
11074 | */ | |
11075 | static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) | |
11076 | { | |
11077 | uint8_t hiattr = extract32(s2attrs, 2, 2); | |
11078 | uint8_t loattr = extract32(s2attrs, 0, 2); | |
11079 | uint8_t hihint = 0, lohint = 0; | |
11080 | ||
11081 | if (hiattr != 0) { /* normal memory */ | |
e04a5752 | 11082 | if (arm_hcr_el2_eff(env) & HCR_CD) { /* cache disabled */ |
5b2d261d AB |
11083 | hiattr = loattr = 1; /* non-cacheable */ |
11084 | } else { | |
11085 | if (hiattr != 1) { /* Write-through or write-back */ | |
11086 | hihint = 3; /* RW allocate */ | |
11087 | } | |
11088 | if (loattr != 1) { /* Write-through or write-back */ | |
11089 | lohint = 3; /* RW allocate */ | |
11090 | } | |
11091 | } | |
11092 | } | |
11093 | ||
11094 | return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; | |
11095 | } | |
c47eaf9f | 11096 | #endif /* !CONFIG_USER_ONLY */ |
5b2d261d | 11097 | |
f4ecc015 RH |
11098 | /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */ |
11099 | static const uint8_t pamax_map[] = { | |
11100 | [0] = 32, | |
11101 | [1] = 36, | |
11102 | [2] = 40, | |
11103 | [3] = 42, | |
11104 | [4] = 44, | |
11105 | [5] = 48, | |
7a928f43 | 11106 | [6] = 52, |
f4ecc015 RH |
11107 | }; |
11108 | ||
71a77257 RH |
11109 | /* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */ |
11110 | unsigned int arm_pamax(ARMCPU *cpu) | |
11111 | { | |
71a77257 RH |
11112 | unsigned int parange = |
11113 | FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); | |
11114 | ||
11115 | /* | |
11116 | * id_aa64mmfr0 is a read-only register so values outside of the | |
11117 | * supported mappings can be considered an implementation error. | |
11118 | */ | |
11119 | assert(parange < ARRAY_SIZE(pamax_map)); | |
11120 | return pamax_map[parange]; | |
11121 | } | |
11122 | ||
b830a5ee RH |
11123 | static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) |
11124 | { | |
11125 | if (regime_has_2_ranges(mmu_idx)) { | |
11126 | return extract64(tcr, 37, 2); | |
b1a10c86 | 11127 | } else if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { |
b830a5ee RH |
11128 | return 0; /* VTCR_EL2 */ |
11129 | } else { | |
3e270f67 RH |
11130 | /* Replicate the single TBI bit so we always have 2 bits. */ |
11131 | return extract32(tcr, 20, 1) * 3; | |
b830a5ee RH |
11132 | } |
11133 | } | |
11134 | ||
11135 | static int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) | |
11136 | { | |
11137 | if (regime_has_2_ranges(mmu_idx)) { | |
11138 | return extract64(tcr, 51, 2); | |
b1a10c86 | 11139 | } else if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { |
b830a5ee RH |
11140 | return 0; /* VTCR_EL2 */ |
11141 | } else { | |
3e270f67 RH |
11142 | /* Replicate the single TBID bit so we always have 2 bits. */ |
11143 | return extract32(tcr, 29, 1) * 3; | |
b830a5ee RH |
11144 | } |
11145 | } | |
11146 | ||
81ae05fa RH |
11147 | static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx) |
11148 | { | |
11149 | if (regime_has_2_ranges(mmu_idx)) { | |
11150 | return extract64(tcr, 57, 2); | |
11151 | } else { | |
11152 | /* Replicate the single TCMA bit so we always have 2 bits. */ | |
11153 | return extract32(tcr, 30, 1) * 3; | |
11154 | } | |
11155 | } | |
11156 | ||
b830a5ee RH |
11157 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, |
11158 | ARMMMUIdx mmu_idx, bool data) | |
ba97be9f RH |
11159 | { |
11160 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | |
ef56c242 RH |
11161 | bool epd, hpd, using16k, using64k, tsz_oob, ds; |
11162 | int select, tsz, tbi, max_tsz, min_tsz, ps, sh; | |
11163 | ARMCPU *cpu = env_archcpu(env); | |
ba97be9f | 11164 | |
339370b9 | 11165 | if (!regime_has_2_ranges(mmu_idx)) { |
71d18164 | 11166 | select = 0; |
ba97be9f RH |
11167 | tsz = extract32(tcr, 0, 6); |
11168 | using64k = extract32(tcr, 14, 1); | |
11169 | using16k = extract32(tcr, 15, 1); | |
b1a10c86 | 11170 | if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { |
ba97be9f | 11171 | /* VTCR_EL2 */ |
b830a5ee | 11172 | hpd = false; |
ba97be9f | 11173 | } else { |
ba97be9f RH |
11174 | hpd = extract32(tcr, 24, 1); |
11175 | } | |
11176 | epd = false; | |
ef56c242 | 11177 | sh = extract32(tcr, 12, 2); |
f4ecc015 | 11178 | ps = extract32(tcr, 16, 3); |
ef56c242 | 11179 | ds = extract64(tcr, 32, 1); |
ba97be9f | 11180 | } else { |
71d18164 RH |
11181 | /* |
11182 | * Bit 55 is always between the two regions, and is canonical for | |
11183 | * determining if address tagging is enabled. | |
11184 | */ | |
11185 | select = extract64(va, 55, 1); | |
11186 | if (!select) { | |
11187 | tsz = extract32(tcr, 0, 6); | |
11188 | epd = extract32(tcr, 7, 1); | |
ef56c242 | 11189 | sh = extract32(tcr, 12, 2); |
71d18164 RH |
11190 | using64k = extract32(tcr, 14, 1); |
11191 | using16k = extract32(tcr, 15, 1); | |
71d18164 | 11192 | hpd = extract64(tcr, 41, 1); |
71d18164 RH |
11193 | } else { |
11194 | int tg = extract32(tcr, 30, 2); | |
11195 | using16k = tg == 1; | |
11196 | using64k = tg == 3; | |
11197 | tsz = extract32(tcr, 16, 6); | |
11198 | epd = extract32(tcr, 23, 1); | |
ef56c242 | 11199 | sh = extract32(tcr, 28, 2); |
71d18164 | 11200 | hpd = extract64(tcr, 42, 1); |
71d18164 | 11201 | } |
f4ecc015 | 11202 | ps = extract64(tcr, 32, 3); |
ef56c242 | 11203 | ds = extract64(tcr, 59, 1); |
ba97be9f | 11204 | } |
c36c65ea | 11205 | |
ef56c242 | 11206 | if (cpu_isar_feature(aa64_st, cpu)) { |
c36c65ea RDC |
11207 | max_tsz = 48 - using64k; |
11208 | } else { | |
11209 | max_tsz = 39; | |
11210 | } | |
0af312b6 | 11211 | |
ef56c242 RH |
11212 | /* |
11213 | * DS is RES0 unless FEAT_LPA2 is supported for the given page size; | |
11214 | * adjust the effective value of DS, as documented. | |
11215 | */ | |
0af312b6 RH |
11216 | min_tsz = 16; |
11217 | if (using64k) { | |
ef56c242 RH |
11218 | if (cpu_isar_feature(aa64_lva, cpu)) { |
11219 | min_tsz = 12; | |
11220 | } | |
11221 | ds = false; | |
11222 | } else if (ds) { | |
11223 | switch (mmu_idx) { | |
11224 | case ARMMMUIdx_Stage2: | |
11225 | case ARMMMUIdx_Stage2_S: | |
11226 | if (using16k) { | |
11227 | ds = cpu_isar_feature(aa64_tgran16_2_lpa2, cpu); | |
11228 | } else { | |
11229 | ds = cpu_isar_feature(aa64_tgran4_2_lpa2, cpu); | |
11230 | } | |
11231 | break; | |
11232 | default: | |
11233 | if (using16k) { | |
11234 | ds = cpu_isar_feature(aa64_tgran16_lpa2, cpu); | |
11235 | } else { | |
11236 | ds = cpu_isar_feature(aa64_tgran4_lpa2, cpu); | |
11237 | } | |
11238 | break; | |
11239 | } | |
11240 | if (ds) { | |
0af312b6 RH |
11241 | min_tsz = 12; |
11242 | } | |
11243 | } | |
c36c65ea | 11244 | |
ebf93ce7 RH |
11245 | if (tsz > max_tsz) { |
11246 | tsz = max_tsz; | |
11247 | tsz_oob = true; | |
11248 | } else if (tsz < min_tsz) { | |
11249 | tsz = min_tsz; | |
11250 | tsz_oob = true; | |
11251 | } else { | |
11252 | tsz_oob = false; | |
11253 | } | |
ba97be9f | 11254 | |
b830a5ee RH |
11255 | /* Present TBI as a composite with TBID. */ |
11256 | tbi = aa64_va_parameter_tbi(tcr, mmu_idx); | |
11257 | if (!data) { | |
11258 | tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); | |
11259 | } | |
11260 | tbi = (tbi >> select) & 1; | |
11261 | ||
ba97be9f RH |
11262 | return (ARMVAParameters) { |
11263 | .tsz = tsz, | |
f4ecc015 | 11264 | .ps = ps, |
ef56c242 | 11265 | .sh = sh, |
ba97be9f RH |
11266 | .select = select, |
11267 | .tbi = tbi, | |
11268 | .epd = epd, | |
11269 | .hpd = hpd, | |
11270 | .using16k = using16k, | |
11271 | .using64k = using64k, | |
ebf93ce7 | 11272 | .tsz_oob = tsz_oob, |
ef56c242 | 11273 | .ds = ds, |
ba97be9f RH |
11274 | }; |
11275 | } | |
11276 | ||
c47eaf9f | 11277 | #ifndef CONFIG_USER_ONLY |
ba97be9f RH |
11278 | static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, |
11279 | ARMMMUIdx mmu_idx) | |
11280 | { | |
11281 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | |
11282 | uint32_t el = regime_el(env, mmu_idx); | |
11283 | int select, tsz; | |
11284 | bool epd, hpd; | |
11285 | ||
b1a10c86 RDC |
11286 | assert(mmu_idx != ARMMMUIdx_Stage2_S); |
11287 | ||
97fa9350 | 11288 | if (mmu_idx == ARMMMUIdx_Stage2) { |
ba97be9f RH |
11289 | /* VTCR */ |
11290 | bool sext = extract32(tcr, 4, 1); | |
11291 | bool sign = extract32(tcr, 3, 1); | |
11292 | ||
11293 | /* | |
11294 | * If the sign-extend bit is not the same as t0sz[3], the result | |
11295 | * is unpredictable. Flag this as a guest error. | |
11296 | */ | |
11297 | if (sign != sext) { | |
11298 | qemu_log_mask(LOG_GUEST_ERROR, | |
11299 | "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); | |
11300 | } | |
11301 | tsz = sextract32(tcr, 0, 4) + 8; | |
11302 | select = 0; | |
11303 | hpd = false; | |
11304 | epd = false; | |
11305 | } else if (el == 2) { | |
11306 | /* HTCR */ | |
11307 | tsz = extract32(tcr, 0, 3); | |
11308 | select = 0; | |
11309 | hpd = extract64(tcr, 24, 1); | |
11310 | epd = false; | |
11311 | } else { | |
11312 | int t0sz = extract32(tcr, 0, 3); | |
11313 | int t1sz = extract32(tcr, 16, 3); | |
11314 | ||
11315 | if (t1sz == 0) { | |
11316 | select = va > (0xffffffffu >> t0sz); | |
11317 | } else { | |
11318 | /* Note that we will detect errors later. */ | |
11319 | select = va >= ~(0xffffffffu >> t1sz); | |
11320 | } | |
11321 | if (!select) { | |
11322 | tsz = t0sz; | |
11323 | epd = extract32(tcr, 7, 1); | |
11324 | hpd = extract64(tcr, 41, 1); | |
11325 | } else { | |
11326 | tsz = t1sz; | |
11327 | epd = extract32(tcr, 23, 1); | |
11328 | hpd = extract64(tcr, 42, 1); | |
11329 | } | |
11330 | /* For aarch32, hpd0 is not enabled without t2e as well. */ | |
11331 | hpd &= extract32(tcr, 6, 1); | |
11332 | } | |
11333 | ||
11334 | return (ARMVAParameters) { | |
11335 | .tsz = tsz, | |
11336 | .select = select, | |
11337 | .epd = epd, | |
11338 | .hpd = hpd, | |
11339 | }; | |
11340 | } | |
11341 | ||
ff7de2fc PM |
11342 | /** |
11343 | * get_phys_addr_lpae: perform one stage of page table walk, LPAE format | |
11344 | * | |
11345 | * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, | |
11346 | * prot and page_size may not be filled in, and the populated fsr value provides | |
11347 | * information on why the translation aborted, in the format of a long-format | |
11348 | * DFSR/IFSR fault register, with the following caveats: | |
11349 | * * the WnR bit is never set (the caller must do this). | |
11350 | * | |
11351 | * @env: CPUARMState | |
11352 | * @address: virtual address to get physical address for | |
11353 | * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH | |
11354 | * @mmu_idx: MMU index indicating required translation regime | |
11355 | * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page table | |
11356 | * walk), must be true if this is stage 2 of a stage 1+2 walk for an | |
11357 | * EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ignored. | |
11358 | * @phys_ptr: set to the physical address corresponding to the virtual address | |
11359 | * @attrs: set to the memory transaction attributes to use | |
11360 | * @prot: set to the permissions for the page containing phys_ptr | |
11361 | * @page_size_ptr: set to the size of the page containing phys_ptr | |
11362 | * @fi: set to fault info if the translation fails | |
11363 | * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes | |
11364 | */ | |
98e87797 | 11365 | static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, |
03ae85f8 | 11366 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
ff7de2fc | 11367 | bool s1_is_el0, |
b7cc4e82 | 11368 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, |
da909b2c | 11369 | target_ulong *page_size_ptr, |
5b2d261d | 11370 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) |
3dde962f | 11371 | { |
2fc0cc0e | 11372 | ARMCPU *cpu = env_archcpu(env); |
1853d5a9 | 11373 | CPUState *cs = CPU(cpu); |
3dde962f | 11374 | /* Read an LPAE long-descriptor translation table. */ |
da909b2c | 11375 | ARMFaultType fault_type = ARMFault_Translation; |
1b4093ea | 11376 | uint32_t level; |
ba97be9f | 11377 | ARMVAParameters param; |
3dde962f | 11378 | uint64_t ttbr; |
dddb5223 | 11379 | hwaddr descaddr, indexmask, indexmask_grainsize; |
3dde962f | 11380 | uint32_t tableattrs; |
36d820af | 11381 | target_ulong page_size; |
3dde962f | 11382 | uint32_t attrs; |
ba97be9f | 11383 | int32_t stride; |
49ba115b | 11384 | int addrsize, inputsize, outputsize; |
0480f69a | 11385 | TCR *tcr = regime_tcr(env, mmu_idx); |
d8e052b3 | 11386 | int ap, ns, xn, pxn; |
88e8add8 | 11387 | uint32_t el = regime_el(env, mmu_idx); |
6109769a | 11388 | uint64_t descaddrmask; |
6e99f762 | 11389 | bool aarch64 = arm_el_is_aa64(env, el); |
1bafc2ba | 11390 | bool guarded = false; |
0480f69a | 11391 | |
07d1be3b | 11392 | /* TODO: This code does not support shareability levels. */ |
6e99f762 | 11393 | if (aarch64) { |
f4ecc015 RH |
11394 | int ps; |
11395 | ||
ba97be9f RH |
11396 | param = aa64_va_parameters(env, address, mmu_idx, |
11397 | access_type != MMU_INST_FETCH); | |
1b4093ea | 11398 | level = 0; |
ebf93ce7 RH |
11399 | |
11400 | /* | |
11401 | * If TxSZ is programmed to a value larger than the maximum, | |
11402 | * or smaller than the effective minimum, it is IMPLEMENTATION | |
11403 | * DEFINED whether we behave as if the field were programmed | |
11404 | * within bounds, or if a level 0 Translation fault is generated. | |
11405 | * | |
11406 | * With FEAT_LVA, fault on less than minimum becomes required, | |
11407 | * so our choice is to always raise the fault. | |
11408 | */ | |
11409 | if (param.tsz_oob) { | |
11410 | fault_type = ARMFault_Translation; | |
11411 | goto do_fault; | |
11412 | } | |
11413 | ||
ba97be9f RH |
11414 | addrsize = 64 - 8 * param.tbi; |
11415 | inputsize = 64 - param.tsz; | |
f4ecc015 RH |
11416 | |
11417 | /* | |
11418 | * Bound PS by PARANGE to find the effective output address size. | |
11419 | * ID_AA64MMFR0 is a read-only register so values outside of the | |
11420 | * supported mappings can be considered an implementation error. | |
11421 | */ | |
11422 | ps = FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); | |
11423 | ps = MIN(ps, param.ps); | |
11424 | assert(ps < ARRAY_SIZE(pamax_map)); | |
11425 | outputsize = pamax_map[ps]; | |
d0a2cbce | 11426 | } else { |
ba97be9f | 11427 | param = aa32_va_parameters(env, address, mmu_idx); |
1b4093ea | 11428 | level = 1; |
97fa9350 | 11429 | addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32); |
ba97be9f | 11430 | inputsize = addrsize - param.tsz; |
49ba115b | 11431 | outputsize = 40; |
2c8dd318 | 11432 | } |
3dde962f | 11433 | |
ba97be9f RH |
11434 | /* |
11435 | * We determined the region when collecting the parameters, but we | |
11436 | * have not yet validated that the address is valid for the region. | |
11437 | * Extract the top bits and verify that they all match select. | |
36d820af RH |
11438 | * |
11439 | * For aa32, if inputsize == addrsize, then we have selected the | |
11440 | * region by exclusion in aa32_va_parameters and there is no more | |
11441 | * validation to do here. | |
11442 | */ | |
11443 | if (inputsize < addrsize) { | |
11444 | target_ulong top_bits = sextract64(address, inputsize, | |
11445 | addrsize - inputsize); | |
03f27724 | 11446 | if (-top_bits != param.select) { |
36d820af RH |
11447 | /* The gap between the two regions is a Translation fault */ |
11448 | fault_type = ARMFault_Translation; | |
11449 | goto do_fault; | |
11450 | } | |
3dde962f PM |
11451 | } |
11452 | ||
ba97be9f RH |
11453 | if (param.using64k) { |
11454 | stride = 13; | |
11455 | } else if (param.using16k) { | |
11456 | stride = 11; | |
11457 | } else { | |
11458 | stride = 9; | |
11459 | } | |
11460 | ||
3dde962f PM |
11461 | /* Note that QEMU ignores shareability and cacheability attributes, |
11462 | * so we don't need to do anything with the SH, ORGN, IRGN fields | |
11463 | * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the | |
11464 | * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently | |
11465 | * implement any ASID-like capability so we can ignore it (instead | |
11466 | * we will always flush the TLB any time the ASID is changed). | |
11467 | */ | |
ba97be9f | 11468 | ttbr = regime_ttbr(env, mmu_idx, param.select); |
3dde962f | 11469 | |
0480f69a | 11470 | /* Here we should have set up all the parameters for the translation: |
6e99f762 | 11471 | * inputsize, ttbr, epd, stride, tbi |
0480f69a PM |
11472 | */ |
11473 | ||
ba97be9f | 11474 | if (param.epd) { |
88e8add8 GB |
11475 | /* Translation table walk disabled => Translation fault on TLB miss |
11476 | * Note: This is always 0 on 64-bit EL2 and EL3. | |
11477 | */ | |
3dde962f PM |
11478 | goto do_fault; |
11479 | } | |
11480 | ||
b1a10c86 | 11481 | if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) { |
1853d5a9 EI |
11482 | /* The starting level depends on the virtual address size (which can |
11483 | * be up to 48 bits) and the translation granule size. It indicates | |
11484 | * the number of strides (stride bits at a time) needed to | |
11485 | * consume the bits of the input address. In the pseudocode this is: | |
11486 | * level = 4 - RoundUp((inputsize - grainsize) / stride) | |
11487 | * where their 'inputsize' is our 'inputsize', 'grainsize' is | |
11488 | * our 'stride + 3' and 'stride' is our 'stride'. | |
11489 | * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: | |
11490 | * = 4 - (inputsize - stride - 3 + stride - 1) / stride | |
11491 | * = 4 - (inputsize - 4) / stride; | |
11492 | */ | |
11493 | level = 4 - (inputsize - 4) / stride; | |
11494 | } else { | |
11495 | /* For stage 2 translations the starting level is specified by the | |
11496 | * VTCR_EL2.SL0 field (whose interpretation depends on the page size) | |
11497 | */ | |
1b4093ea | 11498 | uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); |
ef56c242 | 11499 | uint32_t sl2 = extract64(tcr->raw_tcr, 33, 1); |
1b4093ea | 11500 | uint32_t startlevel; |
1853d5a9 EI |
11501 | bool ok; |
11502 | ||
ef56c242 RH |
11503 | /* SL2 is RES0 unless DS=1 & 4kb granule. */ |
11504 | if (param.ds && stride == 9 && sl2) { | |
11505 | if (sl0 != 0) { | |
11506 | level = 0; | |
11507 | fault_type = ARMFault_Translation; | |
11508 | goto do_fault; | |
11509 | } | |
11510 | startlevel = -1; | |
11511 | } else if (!aarch64 || stride == 9) { | |
1853d5a9 | 11512 | /* AArch32 or 4KB pages */ |
1b4093ea | 11513 | startlevel = 2 - sl0; |
c36c65ea RDC |
11514 | |
11515 | if (cpu_isar_feature(aa64_st, cpu)) { | |
11516 | startlevel &= 3; | |
11517 | } | |
1853d5a9 EI |
11518 | } else { |
11519 | /* 16KB or 64KB pages */ | |
1b4093ea | 11520 | startlevel = 3 - sl0; |
1853d5a9 EI |
11521 | } |
11522 | ||
11523 | /* Check that the starting level is valid. */ | |
6e99f762 | 11524 | ok = check_s2_mmu_setup(cpu, aarch64, startlevel, |
49ba115b | 11525 | inputsize, stride, outputsize); |
1853d5a9 | 11526 | if (!ok) { |
da909b2c | 11527 | fault_type = ARMFault_Translation; |
1853d5a9 EI |
11528 | goto do_fault; |
11529 | } | |
1b4093ea | 11530 | level = startlevel; |
1853d5a9 | 11531 | } |
3dde962f | 11532 | |
d06449f2 RH |
11533 | indexmask_grainsize = MAKE_64BIT_MASK(0, stride + 3); |
11534 | indexmask = MAKE_64BIT_MASK(0, inputsize - (stride * (4 - level))); | |
3dde962f PM |
11535 | |
11536 | /* Now we can extract the actual base address from the TTBR */ | |
2c8dd318 | 11537 | descaddr = extract64(ttbr, 0, 48); |
f4ecc015 RH |
11538 | |
11539 | /* | |
7a928f43 RH |
11540 | * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR. |
11541 | * | |
11542 | * Otherwise, if the base address is out of range, raise AddressSizeFault. | |
f4ecc015 RH |
11543 | * In the pseudocode, this is !IsZero(baseregister<47:outputsize>), |
11544 | * but we've just cleared the bits above 47, so simplify the test. | |
11545 | */ | |
7a928f43 RH |
11546 | if (outputsize > 48) { |
11547 | descaddr |= extract64(ttbr, 2, 4) << 48; | |
11548 | } else if (descaddr >> outputsize) { | |
f4ecc015 RH |
11549 | level = 0; |
11550 | fault_type = ARMFault_AddressSize; | |
11551 | goto do_fault; | |
11552 | } | |
11553 | ||
41a4bf1f PM |
11554 | /* |
11555 | * We rely on this masking to clear the RES0 bits at the bottom of the TTBR | |
11556 | * and also to mask out CnP (bit 0) which could validly be non-zero. | |
11557 | */ | |
dddb5223 | 11558 | descaddr &= ~indexmask; |
3dde962f | 11559 | |
f4ecc015 RH |
11560 | /* |
11561 | * For AArch32, the address field in the descriptor goes up to bit 39 | |
11562 | * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0 | |
11563 | * or an AddressSize fault is raised. So for v8 we extract those SBZ | |
11564 | * bits as part of the address, which will be checked via outputsize. | |
ef56c242 RH |
11565 | * For AArch64, the address field goes up to bit 47, or 49 with FEAT_LPA2; |
11566 | * the highest bits of a 52-bit output are placed elsewhere. | |
6109769a | 11567 | */ |
ef56c242 RH |
11568 | if (param.ds) { |
11569 | descaddrmask = MAKE_64BIT_MASK(0, 50); | |
11570 | } else if (arm_feature(env, ARM_FEATURE_V8)) { | |
f4ecc015 RH |
11571 | descaddrmask = MAKE_64BIT_MASK(0, 48); |
11572 | } else { | |
11573 | descaddrmask = MAKE_64BIT_MASK(0, 40); | |
11574 | } | |
11575 | descaddrmask &= ~indexmask_grainsize; | |
6109769a | 11576 | |
ebca90e4 PM |
11577 | /* Secure accesses start with the page table in secure memory and |
11578 | * can be downgraded to non-secure at any step. Non-secure accesses | |
11579 | * remain non-secure. We implement this by just ORing in the NSTable/NS | |
11580 | * bits at each step. | |
11581 | */ | |
11582 | tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); | |
3dde962f PM |
11583 | for (;;) { |
11584 | uint64_t descriptor; | |
ebca90e4 | 11585 | bool nstable; |
3dde962f | 11586 | |
dddb5223 | 11587 | descaddr |= (address >> (stride * (4 - level))) & indexmask; |
2c8dd318 | 11588 | descaddr &= ~7ULL; |
ebca90e4 | 11589 | nstable = extract32(tableattrs, 4, 1); |
3795a6de | 11590 | descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi); |
3b39d734 | 11591 | if (fi->type != ARMFault_None) { |
37785977 EI |
11592 | goto do_fault; |
11593 | } | |
11594 | ||
3dde962f PM |
11595 | if (!(descriptor & 1) || |
11596 | (!(descriptor & 2) && (level == 3))) { | |
11597 | /* Invalid, or the Reserved level 3 encoding */ | |
11598 | goto do_fault; | |
11599 | } | |
f4ecc015 | 11600 | |
6109769a | 11601 | descaddr = descriptor & descaddrmask; |
7a928f43 RH |
11602 | |
11603 | /* | |
11604 | * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12] | |
ef56c242 RH |
11605 | * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of |
11606 | * descaddr are in [9:8]. Otherwise, if descaddr is out of range, | |
11607 | * raise AddressSizeFault. | |
7a928f43 RH |
11608 | */ |
11609 | if (outputsize > 48) { | |
ef56c242 RH |
11610 | if (param.ds) { |
11611 | descaddr |= extract64(descriptor, 8, 2) << 50; | |
11612 | } else { | |
11613 | descaddr |= extract64(descriptor, 12, 4) << 48; | |
11614 | } | |
7a928f43 | 11615 | } else if (descaddr >> outputsize) { |
f4ecc015 RH |
11616 | fault_type = ARMFault_AddressSize; |
11617 | goto do_fault; | |
11618 | } | |
3dde962f PM |
11619 | |
11620 | if ((descriptor & 2) && (level < 3)) { | |
037c13c5 | 11621 | /* Table entry. The top five bits are attributes which may |
3dde962f PM |
11622 | * propagate down through lower levels of the table (and |
11623 | * which are all arranged so that 0 means "no effect", so | |
11624 | * we can gather them up by ORing in the bits at each level). | |
11625 | */ | |
11626 | tableattrs |= extract64(descriptor, 59, 5); | |
11627 | level++; | |
dddb5223 | 11628 | indexmask = indexmask_grainsize; |
3dde962f PM |
11629 | continue; |
11630 | } | |
39a1fd25 PM |
11631 | /* |
11632 | * Block entry at level 1 or 2, or page entry at level 3. | |
3dde962f | 11633 | * These are basically the same thing, although the number |
39a1fd25 PM |
11634 | * of bits we pull in from the vaddr varies. Note that although |
11635 | * descaddrmask masks enough of the low bits of the descriptor | |
11636 | * to give a correct page or table address, the address field | |
11637 | * in a block descriptor is smaller; so we need to explicitly | |
11638 | * clear the lower bits here before ORing in the low vaddr bits. | |
3dde962f | 11639 | */ |
973a5434 | 11640 | page_size = (1ULL << ((stride * (4 - level)) + 3)); |
39a1fd25 | 11641 | descaddr &= ~(page_size - 1); |
3dde962f | 11642 | descaddr |= (address & (page_size - 1)); |
6ab1a5ee | 11643 | /* Extract attributes from the descriptor */ |
d615efac IC |
11644 | attrs = extract64(descriptor, 2, 10) |
11645 | | (extract64(descriptor, 52, 12) << 10); | |
6ab1a5ee | 11646 | |
b1a10c86 | 11647 | if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { |
6ab1a5ee EI |
11648 | /* Stage 2 table descriptors do not include any attribute fields */ |
11649 | break; | |
11650 | } | |
11651 | /* Merge in attributes from table descriptors */ | |
037c13c5 | 11652 | attrs |= nstable << 3; /* NS */ |
1bafc2ba | 11653 | guarded = extract64(descriptor, 50, 1); /* GP */ |
ba97be9f | 11654 | if (param.hpd) { |
037c13c5 RH |
11655 | /* HPD disables all the table attributes except NSTable. */ |
11656 | break; | |
11657 | } | |
11658 | attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ | |
3dde962f PM |
11659 | /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 |
11660 | * means "force PL1 access only", which means forcing AP[1] to 0. | |
11661 | */ | |
037c13c5 RH |
11662 | attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */ |
11663 | attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */ | |
3dde962f PM |
11664 | break; |
11665 | } | |
11666 | /* Here descaddr is the final physical address, and attributes | |
11667 | * are all in attrs. | |
11668 | */ | |
da909b2c | 11669 | fault_type = ARMFault_AccessFlag; |
3dde962f PM |
11670 | if ((attrs & (1 << 8)) == 0) { |
11671 | /* Access flag */ | |
11672 | goto do_fault; | |
11673 | } | |
d8e052b3 AJ |
11674 | |
11675 | ap = extract32(attrs, 4, 2); | |
d8e052b3 | 11676 | |
b1a10c86 RDC |
11677 | if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { |
11678 | ns = mmu_idx == ARMMMUIdx_Stage2; | |
ce3125be PM |
11679 | xn = extract32(attrs, 11, 2); |
11680 | *prot = get_S2prot(env, ap, xn, s1_is_el0); | |
6ab1a5ee EI |
11681 | } else { |
11682 | ns = extract32(attrs, 3, 1); | |
ce3125be | 11683 | xn = extract32(attrs, 12, 1); |
6ab1a5ee | 11684 | pxn = extract32(attrs, 11, 1); |
6e99f762 | 11685 | *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); |
6ab1a5ee | 11686 | } |
d8e052b3 | 11687 | |
da909b2c | 11688 | fault_type = ARMFault_Permission; |
d8e052b3 | 11689 | if (!(*prot & (1 << access_type))) { |
3dde962f PM |
11690 | goto do_fault; |
11691 | } | |
3dde962f | 11692 | |
8bf5b6a9 PM |
11693 | if (ns) { |
11694 | /* The NS bit will (as required by the architecture) have no effect if | |
11695 | * the CPU doesn't support TZ or this is a non-secure translation | |
11696 | * regime, because the attribute will already be non-secure. | |
11697 | */ | |
11698 | txattrs->secure = false; | |
11699 | } | |
1bafc2ba RH |
11700 | /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */ |
11701 | if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { | |
149d3b31 | 11702 | arm_tlb_bti_gp(txattrs) = true; |
1bafc2ba | 11703 | } |
5b2d261d | 11704 | |
b1a10c86 | 11705 | if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { |
7e98e21c RH |
11706 | cacheattrs->attrs = convert_stage2_attrs(env, extract32(attrs, 0, 4)); |
11707 | } else { | |
11708 | /* Index into MAIR registers for cache attributes */ | |
11709 | uint8_t attrindx = extract32(attrs, 0, 3); | |
11710 | uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; | |
11711 | assert(attrindx <= 7); | |
11712 | cacheattrs->attrs = extract64(mair, attrindx * 8, 8); | |
5b2d261d | 11713 | } |
ef56c242 RH |
11714 | |
11715 | /* | |
11716 | * For FEAT_LPA2 and effective DS, the SH field in the attributes | |
11717 | * was re-purposed for output address bits. The SH attribute in | |
11718 | * that case comes from TCR_ELx, which we extracted earlier. | |
11719 | */ | |
11720 | if (param.ds) { | |
11721 | cacheattrs->shareability = param.sh; | |
11722 | } else { | |
11723 | cacheattrs->shareability = extract32(attrs, 6, 2); | |
11724 | } | |
5b2d261d | 11725 | |
3dde962f PM |
11726 | *phys_ptr = descaddr; |
11727 | *page_size_ptr = page_size; | |
b7cc4e82 | 11728 | return false; |
3dde962f PM |
11729 | |
11730 | do_fault: | |
da909b2c PM |
11731 | fi->type = fault_type; |
11732 | fi->level = level; | |
37785977 | 11733 | /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ |
b1a10c86 RDC |
11734 | fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_Stage2 || |
11735 | mmu_idx == ARMMMUIdx_Stage2_S); | |
9861248f | 11736 | fi->s1ns = mmu_idx == ARMMMUIdx_Stage2; |
b7cc4e82 | 11737 | return true; |
3dde962f PM |
11738 | } |
11739 | ||
f6bda88f PC |
11740 | static inline void get_phys_addr_pmsav7_default(CPUARMState *env, |
11741 | ARMMMUIdx mmu_idx, | |
11742 | int32_t address, int *prot) | |
11743 | { | |
3a00d560 MD |
11744 | if (!arm_feature(env, ARM_FEATURE_M)) { |
11745 | *prot = PAGE_READ | PAGE_WRITE; | |
11746 | switch (address) { | |
11747 | case 0xF0000000 ... 0xFFFFFFFF: | |
11748 | if (regime_sctlr(env, mmu_idx) & SCTLR_V) { | |
11749 | /* hivecs execing is ok */ | |
11750 | *prot |= PAGE_EXEC; | |
11751 | } | |
11752 | break; | |
11753 | case 0x00000000 ... 0x7FFFFFFF: | |
f6bda88f | 11754 | *prot |= PAGE_EXEC; |
3a00d560 MD |
11755 | break; |
11756 | } | |
11757 | } else { | |
11758 | /* Default system address map for M profile cores. | |
11759 | * The architecture specifies which regions are execute-never; | |
11760 | * at the MPU level no other checks are defined. | |
11761 | */ | |
11762 | switch (address) { | |
11763 | case 0x00000000 ... 0x1fffffff: /* ROM */ | |
11764 | case 0x20000000 ... 0x3fffffff: /* SRAM */ | |
11765 | case 0x60000000 ... 0x7fffffff: /* RAM */ | |
11766 | case 0x80000000 ... 0x9fffffff: /* RAM */ | |
11767 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
11768 | break; | |
11769 | case 0x40000000 ... 0x5fffffff: /* Peripheral */ | |
11770 | case 0xa0000000 ... 0xbfffffff: /* Device */ | |
11771 | case 0xc0000000 ... 0xdfffffff: /* Device */ | |
11772 | case 0xe0000000 ... 0xffffffff: /* System */ | |
11773 | *prot = PAGE_READ | PAGE_WRITE; | |
11774 | break; | |
11775 | default: | |
11776 | g_assert_not_reached(); | |
f6bda88f | 11777 | } |
f6bda88f | 11778 | } |
f6bda88f PC |
11779 | } |
11780 | ||
29c483a5 MD |
11781 | static bool pmsav7_use_background_region(ARMCPU *cpu, |
11782 | ARMMMUIdx mmu_idx, bool is_user) | |
11783 | { | |
11784 | /* Return true if we should use the default memory map as a | |
11785 | * "background" region if there are no hits against any MPU regions. | |
11786 | */ | |
11787 | CPUARMState *env = &cpu->env; | |
11788 | ||
11789 | if (is_user) { | |
11790 | return false; | |
11791 | } | |
11792 | ||
11793 | if (arm_feature(env, ARM_FEATURE_M)) { | |
ecf5e8ea PM |
11794 | return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] |
11795 | & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; | |
29c483a5 MD |
11796 | } else { |
11797 | return regime_sctlr(env, mmu_idx) & SCTLR_BR; | |
11798 | } | |
11799 | } | |
11800 | ||
38aaa60c PM |
11801 | static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address) |
11802 | { | |
11803 | /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */ | |
11804 | return arm_feature(env, ARM_FEATURE_M) && | |
11805 | extract32(address, 20, 12) == 0xe00; | |
11806 | } | |
11807 | ||
bf446a11 PM |
11808 | static inline bool m_is_system_region(CPUARMState *env, uint32_t address) |
11809 | { | |
11810 | /* True if address is in the M profile system region | |
11811 | * 0xe0000000 - 0xffffffff | |
11812 | */ | |
11813 | return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7; | |
11814 | } | |
11815 | ||
f6bda88f | 11816 | static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, |
03ae85f8 | 11817 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
9375ad15 | 11818 | hwaddr *phys_ptr, int *prot, |
e5e40999 | 11819 | target_ulong *page_size, |
9375ad15 | 11820 | ARMMMUFaultInfo *fi) |
f6bda88f | 11821 | { |
2fc0cc0e | 11822 | ARMCPU *cpu = env_archcpu(env); |
f6bda88f PC |
11823 | int n; |
11824 | bool is_user = regime_is_user(env, mmu_idx); | |
11825 | ||
11826 | *phys_ptr = address; | |
e5e40999 | 11827 | *page_size = TARGET_PAGE_SIZE; |
f6bda88f PC |
11828 | *prot = 0; |
11829 | ||
38aaa60c PM |
11830 | if (regime_translation_disabled(env, mmu_idx) || |
11831 | m_is_ppb_region(env, address)) { | |
11832 | /* MPU disabled or M profile PPB access: use default memory map. | |
11833 | * The other case which uses the default memory map in the | |
11834 | * v7M ARM ARM pseudocode is exception vector reads from the vector | |
11835 | * table. In QEMU those accesses are done in arm_v7m_load_vector(), | |
11836 | * which always does a direct read using address_space_ldl(), rather | |
11837 | * than going via this function, so we don't need to check that here. | |
11838 | */ | |
f6bda88f PC |
11839 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); |
11840 | } else { /* MPU enabled */ | |
11841 | for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { | |
11842 | /* region search */ | |
11843 | uint32_t base = env->pmsav7.drbar[n]; | |
11844 | uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5); | |
11845 | uint32_t rmask; | |
11846 | bool srdis = false; | |
11847 | ||
11848 | if (!(env->pmsav7.drsr[n] & 0x1)) { | |
11849 | continue; | |
11850 | } | |
11851 | ||
11852 | if (!rsize) { | |
c9f9f124 MD |
11853 | qemu_log_mask(LOG_GUEST_ERROR, |
11854 | "DRSR[%d]: Rsize field cannot be 0\n", n); | |
f6bda88f PC |
11855 | continue; |
11856 | } | |
11857 | rsize++; | |
11858 | rmask = (1ull << rsize) - 1; | |
11859 | ||
11860 | if (base & rmask) { | |
c9f9f124 MD |
11861 | qemu_log_mask(LOG_GUEST_ERROR, |
11862 | "DRBAR[%d]: 0x%" PRIx32 " misaligned " | |
11863 | "to DRSR region size, mask = 0x%" PRIx32 "\n", | |
11864 | n, base, rmask); | |
f6bda88f PC |
11865 | continue; |
11866 | } | |
11867 | ||
11868 | if (address < base || address > base + rmask) { | |
9d2b5a58 PM |
11869 | /* |
11870 | * Address not in this region. We must check whether the | |
11871 | * region covers addresses in the same page as our address. | |
11872 | * In that case we must not report a size that covers the | |
11873 | * whole page for a subsequent hit against a different MPU | |
11874 | * region or the background region, because it would result in | |
11875 | * incorrect TLB hits for subsequent accesses to addresses that | |
11876 | * are in this MPU region. | |
11877 | */ | |
11878 | if (ranges_overlap(base, rmask, | |
11879 | address & TARGET_PAGE_MASK, | |
11880 | TARGET_PAGE_SIZE)) { | |
11881 | *page_size = 1; | |
11882 | } | |
f6bda88f PC |
11883 | continue; |
11884 | } | |
11885 | ||
11886 | /* Region matched */ | |
11887 | ||
11888 | if (rsize >= 8) { /* no subregions for regions < 256 bytes */ | |
11889 | int i, snd; | |
11890 | uint32_t srdis_mask; | |
11891 | ||
11892 | rsize -= 3; /* sub region size (power of 2) */ | |
11893 | snd = ((address - base) >> rsize) & 0x7; | |
11894 | srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1); | |
11895 | ||
11896 | srdis_mask = srdis ? 0x3 : 0x0; | |
11897 | for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) { | |
11898 | /* This will check in groups of 2, 4 and then 8, whether | |
11899 | * the subregion bits are consistent. rsize is incremented | |
11900 | * back up to give the region size, considering consistent | |
11901 | * adjacent subregions as one region. Stop testing if rsize | |
11902 | * is already big enough for an entire QEMU page. | |
11903 | */ | |
11904 | int snd_rounded = snd & ~(i - 1); | |
11905 | uint32_t srdis_multi = extract32(env->pmsav7.drsr[n], | |
11906 | snd_rounded + 8, i); | |
11907 | if (srdis_mask ^ srdis_multi) { | |
11908 | break; | |
11909 | } | |
11910 | srdis_mask = (srdis_mask << i) | srdis_mask; | |
11911 | rsize++; | |
11912 | } | |
11913 | } | |
f6bda88f PC |
11914 | if (srdis) { |
11915 | continue; | |
11916 | } | |
e5e40999 PM |
11917 | if (rsize < TARGET_PAGE_BITS) { |
11918 | *page_size = 1 << rsize; | |
11919 | } | |
f6bda88f PC |
11920 | break; |
11921 | } | |
11922 | ||
11923 | if (n == -1) { /* no hits */ | |
29c483a5 | 11924 | if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { |
f6bda88f | 11925 | /* background fault */ |
9375ad15 | 11926 | fi->type = ARMFault_Background; |
f6bda88f PC |
11927 | return true; |
11928 | } | |
11929 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | |
11930 | } else { /* a MPU hit! */ | |
11931 | uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); | |
bf446a11 PM |
11932 | uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1); |
11933 | ||
11934 | if (m_is_system_region(env, address)) { | |
11935 | /* System space is always execute never */ | |
11936 | xn = 1; | |
11937 | } | |
f6bda88f PC |
11938 | |
11939 | if (is_user) { /* User mode AP bit decoding */ | |
11940 | switch (ap) { | |
11941 | case 0: | |
11942 | case 1: | |
11943 | case 5: | |
11944 | break; /* no access */ | |
11945 | case 3: | |
11946 | *prot |= PAGE_WRITE; | |
11947 | /* fall through */ | |
11948 | case 2: | |
11949 | case 6: | |
11950 | *prot |= PAGE_READ | PAGE_EXEC; | |
11951 | break; | |
8638f1ad PM |
11952 | case 7: |
11953 | /* for v7M, same as 6; for R profile a reserved value */ | |
11954 | if (arm_feature(env, ARM_FEATURE_M)) { | |
11955 | *prot |= PAGE_READ | PAGE_EXEC; | |
11956 | break; | |
11957 | } | |
11958 | /* fall through */ | |
f6bda88f PC |
11959 | default: |
11960 | qemu_log_mask(LOG_GUEST_ERROR, | |
c9f9f124 MD |
11961 | "DRACR[%d]: Bad value for AP bits: 0x%" |
11962 | PRIx32 "\n", n, ap); | |
f6bda88f PC |
11963 | } |
11964 | } else { /* Priv. mode AP bits decoding */ | |
11965 | switch (ap) { | |
11966 | case 0: | |
11967 | break; /* no access */ | |
11968 | case 1: | |
11969 | case 2: | |
11970 | case 3: | |
11971 | *prot |= PAGE_WRITE; | |
11972 | /* fall through */ | |
11973 | case 5: | |
11974 | case 6: | |
11975 | *prot |= PAGE_READ | PAGE_EXEC; | |
11976 | break; | |
8638f1ad PM |
11977 | case 7: |
11978 | /* for v7M, same as 6; for R profile a reserved value */ | |
11979 | if (arm_feature(env, ARM_FEATURE_M)) { | |
11980 | *prot |= PAGE_READ | PAGE_EXEC; | |
11981 | break; | |
11982 | } | |
11983 | /* fall through */ | |
f6bda88f PC |
11984 | default: |
11985 | qemu_log_mask(LOG_GUEST_ERROR, | |
c9f9f124 MD |
11986 | "DRACR[%d]: Bad value for AP bits: 0x%" |
11987 | PRIx32 "\n", n, ap); | |
f6bda88f PC |
11988 | } |
11989 | } | |
11990 | ||
11991 | /* execute never */ | |
bf446a11 | 11992 | if (xn) { |
f6bda88f PC |
11993 | *prot &= ~PAGE_EXEC; |
11994 | } | |
11995 | } | |
11996 | } | |
11997 | ||
9375ad15 PM |
11998 | fi->type = ARMFault_Permission; |
11999 | fi->level = 1; | |
f6bda88f PC |
12000 | return !(*prot & (1 << access_type)); |
12001 | } | |
12002 | ||
35337cc3 PM |
12003 | static bool v8m_is_sau_exempt(CPUARMState *env, |
12004 | uint32_t address, MMUAccessType access_type) | |
12005 | { | |
12006 | /* The architecture specifies that certain address ranges are | |
12007 | * exempt from v8M SAU/IDAU checks. | |
12008 | */ | |
12009 | return | |
12010 | (access_type == MMU_INST_FETCH && m_is_system_region(env, address)) || | |
12011 | (address >= 0xe0000000 && address <= 0xe0002fff) || | |
12012 | (address >= 0xe000e000 && address <= 0xe000efff) || | |
12013 | (address >= 0xe002e000 && address <= 0xe002efff) || | |
12014 | (address >= 0xe0040000 && address <= 0xe0041fff) || | |
12015 | (address >= 0xe00ff000 && address <= 0xe00fffff); | |
12016 | } | |
12017 | ||
787a7e76 | 12018 | void v8m_security_lookup(CPUARMState *env, uint32_t address, |
35337cc3 PM |
12019 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
12020 | V8M_SAttributes *sattrs) | |
12021 | { | |
12022 | /* Look up the security attributes for this address. Compare the | |
12023 | * pseudocode SecurityCheck() function. | |
12024 | * We assume the caller has zero-initialized *sattrs. | |
12025 | */ | |
2fc0cc0e | 12026 | ARMCPU *cpu = env_archcpu(env); |
35337cc3 | 12027 | int r; |
181962fd PM |
12028 | bool idau_exempt = false, idau_ns = true, idau_nsc = true; |
12029 | int idau_region = IREGION_NOTVALID; | |
72042435 PM |
12030 | uint32_t addr_page_base = address & TARGET_PAGE_MASK; |
12031 | uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); | |
35337cc3 | 12032 | |
181962fd PM |
12033 | if (cpu->idau) { |
12034 | IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau); | |
12035 | IDAUInterface *ii = IDAU_INTERFACE(cpu->idau); | |
12036 | ||
12037 | iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns, | |
12038 | &idau_nsc); | |
12039 | } | |
35337cc3 PM |
12040 | |
12041 | if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) { | |
12042 | /* 0xf0000000..0xffffffff is always S for insn fetches */ | |
12043 | return; | |
12044 | } | |
12045 | ||
181962fd | 12046 | if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) { |
35337cc3 PM |
12047 | sattrs->ns = !regime_is_secure(env, mmu_idx); |
12048 | return; | |
12049 | } | |
12050 | ||
181962fd PM |
12051 | if (idau_region != IREGION_NOTVALID) { |
12052 | sattrs->irvalid = true; | |
12053 | sattrs->iregion = idau_region; | |
12054 | } | |
12055 | ||
35337cc3 PM |
12056 | switch (env->sau.ctrl & 3) { |
12057 | case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */ | |
12058 | break; | |
12059 | case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */ | |
12060 | sattrs->ns = true; | |
12061 | break; | |
12062 | default: /* SAU.ENABLE == 1 */ | |
12063 | for (r = 0; r < cpu->sau_sregion; r++) { | |
12064 | if (env->sau.rlar[r] & 1) { | |
12065 | uint32_t base = env->sau.rbar[r] & ~0x1f; | |
12066 | uint32_t limit = env->sau.rlar[r] | 0x1f; | |
12067 | ||
12068 | if (base <= address && limit >= address) { | |
72042435 PM |
12069 | if (base > addr_page_base || limit < addr_page_limit) { |
12070 | sattrs->subpage = true; | |
12071 | } | |
35337cc3 PM |
12072 | if (sattrs->srvalid) { |
12073 | /* If we hit in more than one region then we must report | |
12074 | * as Secure, not NS-Callable, with no valid region | |
12075 | * number info. | |
12076 | */ | |
12077 | sattrs->ns = false; | |
12078 | sattrs->nsc = false; | |
12079 | sattrs->sregion = 0; | |
12080 | sattrs->srvalid = false; | |
12081 | break; | |
12082 | } else { | |
12083 | if (env->sau.rlar[r] & 2) { | |
12084 | sattrs->nsc = true; | |
12085 | } else { | |
12086 | sattrs->ns = true; | |
12087 | } | |
12088 | sattrs->srvalid = true; | |
12089 | sattrs->sregion = r; | |
12090 | } | |
9d2b5a58 PM |
12091 | } else { |
12092 | /* | |
12093 | * Address not in this region. We must check whether the | |
12094 | * region covers addresses in the same page as our address. | |
12095 | * In that case we must not report a size that covers the | |
12096 | * whole page for a subsequent hit against a different MPU | |
12097 | * region or the background region, because it would result | |
12098 | * in incorrect TLB hits for subsequent accesses to | |
12099 | * addresses that are in this MPU region. | |
12100 | */ | |
12101 | if (limit >= base && | |
12102 | ranges_overlap(base, limit - base + 1, | |
12103 | addr_page_base, | |
12104 | TARGET_PAGE_SIZE)) { | |
12105 | sattrs->subpage = true; | |
12106 | } | |
35337cc3 PM |
12107 | } |
12108 | } | |
12109 | } | |
7e3f1223 TR |
12110 | break; |
12111 | } | |
35337cc3 | 12112 | |
7e3f1223 TR |
12113 | /* |
12114 | * The IDAU will override the SAU lookup results if it specifies | |
12115 | * higher security than the SAU does. | |
12116 | */ | |
12117 | if (!idau_ns) { | |
12118 | if (sattrs->ns || (!idau_nsc && sattrs->nsc)) { | |
12119 | sattrs->ns = false; | |
12120 | sattrs->nsc = idau_nsc; | |
181962fd | 12121 | } |
35337cc3 PM |
12122 | } |
12123 | } | |
12124 | ||
787a7e76 | 12125 | bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, |
54317c0f PM |
12126 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
12127 | hwaddr *phys_ptr, MemTxAttrs *txattrs, | |
72042435 PM |
12128 | int *prot, bool *is_subpage, |
12129 | ARMMMUFaultInfo *fi, uint32_t *mregion) | |
54317c0f PM |
12130 | { |
12131 | /* Perform a PMSAv8 MPU lookup (without also doing the SAU check | |
12132 | * that a full phys-to-virt translation does). | |
12133 | * mregion is (if not NULL) set to the region number which matched, | |
12134 | * or -1 if no region number is returned (MPU off, address did not | |
12135 | * hit a region, address hit in multiple regions). | |
72042435 PM |
12136 | * We set is_subpage to true if the region hit doesn't cover the |
12137 | * entire TARGET_PAGE the address is within. | |
54317c0f | 12138 | */ |
2fc0cc0e | 12139 | ARMCPU *cpu = env_archcpu(env); |
504e3cc3 | 12140 | bool is_user = regime_is_user(env, mmu_idx); |
62c58ee0 | 12141 | uint32_t secure = regime_is_secure(env, mmu_idx); |
504e3cc3 PM |
12142 | int n; |
12143 | int matchregion = -1; | |
12144 | bool hit = false; | |
72042435 PM |
12145 | uint32_t addr_page_base = address & TARGET_PAGE_MASK; |
12146 | uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); | |
504e3cc3 | 12147 | |
72042435 | 12148 | *is_subpage = false; |
504e3cc3 PM |
12149 | *phys_ptr = address; |
12150 | *prot = 0; | |
54317c0f PM |
12151 | if (mregion) { |
12152 | *mregion = -1; | |
35337cc3 PM |
12153 | } |
12154 | ||
504e3cc3 PM |
12155 | /* Unlike the ARM ARM pseudocode, we don't need to check whether this |
12156 | * was an exception vector read from the vector table (which is always | |
12157 | * done using the default system address map), because those accesses | |
12158 | * are done in arm_v7m_load_vector(), which always does a direct | |
12159 | * read using address_space_ldl(), rather than going via this function. | |
12160 | */ | |
12161 | if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ | |
12162 | hit = true; | |
12163 | } else if (m_is_ppb_region(env, address)) { | |
12164 | hit = true; | |
504e3cc3 | 12165 | } else { |
cff21316 PM |
12166 | if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) { |
12167 | hit = true; | |
12168 | } | |
12169 | ||
504e3cc3 PM |
12170 | for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { |
12171 | /* region search */ | |
12172 | /* Note that the base address is bits [31:5] from the register | |
12173 | * with bits [4:0] all zeroes, but the limit address is bits | |
12174 | * [31:5] from the register with bits [4:0] all ones. | |
12175 | */ | |
62c58ee0 PM |
12176 | uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f; |
12177 | uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f; | |
504e3cc3 | 12178 | |
62c58ee0 | 12179 | if (!(env->pmsav8.rlar[secure][n] & 0x1)) { |
504e3cc3 PM |
12180 | /* Region disabled */ |
12181 | continue; | |
12182 | } | |
12183 | ||
12184 | if (address < base || address > limit) { | |
9d2b5a58 PM |
12185 | /* |
12186 | * Address not in this region. We must check whether the | |
12187 | * region covers addresses in the same page as our address. | |
12188 | * In that case we must not report a size that covers the | |
12189 | * whole page for a subsequent hit against a different MPU | |
12190 | * region or the background region, because it would result in | |
12191 | * incorrect TLB hits for subsequent accesses to addresses that | |
12192 | * are in this MPU region. | |
12193 | */ | |
12194 | if (limit >= base && | |
12195 | ranges_overlap(base, limit - base + 1, | |
12196 | addr_page_base, | |
12197 | TARGET_PAGE_SIZE)) { | |
12198 | *is_subpage = true; | |
12199 | } | |
504e3cc3 PM |
12200 | continue; |
12201 | } | |
12202 | ||
72042435 PM |
12203 | if (base > addr_page_base || limit < addr_page_limit) { |
12204 | *is_subpage = true; | |
12205 | } | |
12206 | ||
cff21316 | 12207 | if (matchregion != -1) { |
504e3cc3 PM |
12208 | /* Multiple regions match -- always a failure (unlike |
12209 | * PMSAv7 where highest-numbered-region wins) | |
12210 | */ | |
3f551b5b PM |
12211 | fi->type = ARMFault_Permission; |
12212 | fi->level = 1; | |
504e3cc3 PM |
12213 | return true; |
12214 | } | |
12215 | ||
12216 | matchregion = n; | |
12217 | hit = true; | |
504e3cc3 PM |
12218 | } |
12219 | } | |
12220 | ||
12221 | if (!hit) { | |
12222 | /* background fault */ | |
3f551b5b | 12223 | fi->type = ARMFault_Background; |
504e3cc3 PM |
12224 | return true; |
12225 | } | |
12226 | ||
12227 | if (matchregion == -1) { | |
12228 | /* hit using the background region */ | |
12229 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | |
12230 | } else { | |
62c58ee0 PM |
12231 | uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2); |
12232 | uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1); | |
cad8e2e3 PM |
12233 | bool pxn = false; |
12234 | ||
12235 | if (arm_feature(env, ARM_FEATURE_V8_1M)) { | |
12236 | pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1); | |
12237 | } | |
504e3cc3 PM |
12238 | |
12239 | if (m_is_system_region(env, address)) { | |
12240 | /* System space is always execute never */ | |
12241 | xn = 1; | |
12242 | } | |
12243 | ||
12244 | *prot = simple_ap_to_rw_prot(env, mmu_idx, ap); | |
cad8e2e3 | 12245 | if (*prot && !xn && !(pxn && !is_user)) { |
504e3cc3 PM |
12246 | *prot |= PAGE_EXEC; |
12247 | } | |
12248 | /* We don't need to look the attribute up in the MAIR0/MAIR1 | |
12249 | * registers because that only tells us about cacheability. | |
12250 | */ | |
54317c0f PM |
12251 | if (mregion) { |
12252 | *mregion = matchregion; | |
12253 | } | |
504e3cc3 PM |
12254 | } |
12255 | ||
3f551b5b PM |
12256 | fi->type = ARMFault_Permission; |
12257 | fi->level = 1; | |
504e3cc3 PM |
12258 | return !(*prot & (1 << access_type)); |
12259 | } | |
12260 | ||
54317c0f PM |
12261 | |
12262 | static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, | |
12263 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
12264 | hwaddr *phys_ptr, MemTxAttrs *txattrs, | |
72042435 PM |
12265 | int *prot, target_ulong *page_size, |
12266 | ARMMMUFaultInfo *fi) | |
54317c0f PM |
12267 | { |
12268 | uint32_t secure = regime_is_secure(env, mmu_idx); | |
12269 | V8M_SAttributes sattrs = {}; | |
72042435 PM |
12270 | bool ret; |
12271 | bool mpu_is_subpage; | |
54317c0f PM |
12272 | |
12273 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
12274 | v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs); | |
12275 | if (access_type == MMU_INST_FETCH) { | |
12276 | /* Instruction fetches always use the MMU bank and the | |
12277 | * transaction attribute determined by the fetch address, | |
12278 | * regardless of CPU state. This is painful for QEMU | |
12279 | * to handle, because it would mean we need to encode | |
12280 | * into the mmu_idx not just the (user, negpri) information | |
12281 | * for the current security state but also that for the | |
12282 | * other security state, which would balloon the number | |
12283 | * of mmu_idx values needed alarmingly. | |
12284 | * Fortunately we can avoid this because it's not actually | |
12285 | * possible to arbitrarily execute code from memory with | |
12286 | * the wrong security attribute: it will always generate | |
12287 | * an exception of some kind or another, apart from the | |
12288 | * special case of an NS CPU executing an SG instruction | |
12289 | * in S&NSC memory. So we always just fail the translation | |
12290 | * here and sort things out in the exception handler | |
12291 | * (including possibly emulating an SG instruction). | |
12292 | */ | |
12293 | if (sattrs.ns != !secure) { | |
3f551b5b PM |
12294 | if (sattrs.nsc) { |
12295 | fi->type = ARMFault_QEMU_NSCExec; | |
12296 | } else { | |
12297 | fi->type = ARMFault_QEMU_SFault; | |
12298 | } | |
72042435 | 12299 | *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; |
54317c0f PM |
12300 | *phys_ptr = address; |
12301 | *prot = 0; | |
12302 | return true; | |
12303 | } | |
12304 | } else { | |
12305 | /* For data accesses we always use the MMU bank indicated | |
12306 | * by the current CPU state, but the security attributes | |
12307 | * might downgrade a secure access to nonsecure. | |
12308 | */ | |
12309 | if (sattrs.ns) { | |
12310 | txattrs->secure = false; | |
12311 | } else if (!secure) { | |
12312 | /* NS access to S memory must fault. | |
12313 | * Architecturally we should first check whether the | |
12314 | * MPU information for this address indicates that we | |
12315 | * are doing an unaligned access to Device memory, which | |
12316 | * should generate a UsageFault instead. QEMU does not | |
12317 | * currently check for that kind of unaligned access though. | |
12318 | * If we added it we would need to do so as a special case | |
12319 | * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). | |
12320 | */ | |
3f551b5b | 12321 | fi->type = ARMFault_QEMU_SFault; |
72042435 | 12322 | *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; |
54317c0f PM |
12323 | *phys_ptr = address; |
12324 | *prot = 0; | |
12325 | return true; | |
12326 | } | |
12327 | } | |
12328 | } | |
12329 | ||
72042435 PM |
12330 | ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, |
12331 | txattrs, prot, &mpu_is_subpage, fi, NULL); | |
72042435 PM |
12332 | *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; |
12333 | return ret; | |
54317c0f PM |
12334 | } |
12335 | ||
13689d43 | 12336 | static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, |
03ae85f8 | 12337 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
53a4e5c5 PM |
12338 | hwaddr *phys_ptr, int *prot, |
12339 | ARMMMUFaultInfo *fi) | |
9ee6e8bb PB |
12340 | { |
12341 | int n; | |
12342 | uint32_t mask; | |
12343 | uint32_t base; | |
0480f69a | 12344 | bool is_user = regime_is_user(env, mmu_idx); |
9ee6e8bb | 12345 | |
3279adb9 PM |
12346 | if (regime_translation_disabled(env, mmu_idx)) { |
12347 | /* MPU disabled. */ | |
12348 | *phys_ptr = address; | |
12349 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
12350 | return false; | |
12351 | } | |
12352 | ||
9ee6e8bb PB |
12353 | *phys_ptr = address; |
12354 | for (n = 7; n >= 0; n--) { | |
554b0b09 | 12355 | base = env->cp15.c6_region[n]; |
87c3d486 | 12356 | if ((base & 1) == 0) { |
554b0b09 | 12357 | continue; |
87c3d486 | 12358 | } |
554b0b09 PM |
12359 | mask = 1 << ((base >> 1) & 0x1f); |
12360 | /* Keep this shift separate from the above to avoid an | |
12361 | (undefined) << 32. */ | |
12362 | mask = (mask << 1) - 1; | |
87c3d486 | 12363 | if (((base ^ address) & ~mask) == 0) { |
554b0b09 | 12364 | break; |
87c3d486 | 12365 | } |
9ee6e8bb | 12366 | } |
87c3d486 | 12367 | if (n < 0) { |
53a4e5c5 | 12368 | fi->type = ARMFault_Background; |
b7cc4e82 | 12369 | return true; |
87c3d486 | 12370 | } |
9ee6e8bb | 12371 | |
03ae85f8 | 12372 | if (access_type == MMU_INST_FETCH) { |
7e09797c | 12373 | mask = env->cp15.pmsav5_insn_ap; |
9ee6e8bb | 12374 | } else { |
7e09797c | 12375 | mask = env->cp15.pmsav5_data_ap; |
9ee6e8bb PB |
12376 | } |
12377 | mask = (mask >> (n * 4)) & 0xf; | |
12378 | switch (mask) { | |
12379 | case 0: | |
53a4e5c5 PM |
12380 | fi->type = ARMFault_Permission; |
12381 | fi->level = 1; | |
b7cc4e82 | 12382 | return true; |
9ee6e8bb | 12383 | case 1: |
87c3d486 | 12384 | if (is_user) { |
53a4e5c5 PM |
12385 | fi->type = ARMFault_Permission; |
12386 | fi->level = 1; | |
b7cc4e82 | 12387 | return true; |
87c3d486 | 12388 | } |
554b0b09 PM |
12389 | *prot = PAGE_READ | PAGE_WRITE; |
12390 | break; | |
9ee6e8bb | 12391 | case 2: |
554b0b09 | 12392 | *prot = PAGE_READ; |
87c3d486 | 12393 | if (!is_user) { |
554b0b09 | 12394 | *prot |= PAGE_WRITE; |
87c3d486 | 12395 | } |
554b0b09 | 12396 | break; |
9ee6e8bb | 12397 | case 3: |
554b0b09 PM |
12398 | *prot = PAGE_READ | PAGE_WRITE; |
12399 | break; | |
9ee6e8bb | 12400 | case 5: |
87c3d486 | 12401 | if (is_user) { |
53a4e5c5 PM |
12402 | fi->type = ARMFault_Permission; |
12403 | fi->level = 1; | |
b7cc4e82 | 12404 | return true; |
87c3d486 | 12405 | } |
554b0b09 PM |
12406 | *prot = PAGE_READ; |
12407 | break; | |
9ee6e8bb | 12408 | case 6: |
554b0b09 PM |
12409 | *prot = PAGE_READ; |
12410 | break; | |
9ee6e8bb | 12411 | default: |
554b0b09 | 12412 | /* Bad permission. */ |
53a4e5c5 PM |
12413 | fi->type = ARMFault_Permission; |
12414 | fi->level = 1; | |
b7cc4e82 | 12415 | return true; |
9ee6e8bb | 12416 | } |
3ad493fc | 12417 | *prot |= PAGE_EXEC; |
b7cc4e82 | 12418 | return false; |
9ee6e8bb PB |
12419 | } |
12420 | ||
5b2d261d AB |
12421 | /* Combine either inner or outer cacheability attributes for normal |
12422 | * memory, according to table D4-42 and pseudocode procedure | |
12423 | * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). | |
12424 | * | |
12425 | * NB: only stage 1 includes allocation hints (RW bits), leading to | |
12426 | * some asymmetry. | |
12427 | */ | |
12428 | static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2) | |
12429 | { | |
12430 | if (s1 == 4 || s2 == 4) { | |
12431 | /* non-cacheable has precedence */ | |
12432 | return 4; | |
12433 | } else if (extract32(s1, 2, 2) == 0 || extract32(s1, 2, 2) == 2) { | |
12434 | /* stage 1 write-through takes precedence */ | |
12435 | return s1; | |
12436 | } else if (extract32(s2, 2, 2) == 2) { | |
12437 | /* stage 2 write-through takes precedence, but the allocation hint | |
12438 | * is still taken from stage 1 | |
12439 | */ | |
12440 | return (2 << 2) | extract32(s1, 0, 2); | |
12441 | } else { /* write-back */ | |
12442 | return s1; | |
12443 | } | |
12444 | } | |
12445 | ||
12446 | /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 | |
12447 | * and CombineS1S2Desc() | |
12448 | * | |
12449 | * @s1: Attributes from stage 1 walk | |
12450 | * @s2: Attributes from stage 2 walk | |
12451 | */ | |
12452 | static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) | |
12453 | { | |
337a03f0 | 12454 | uint8_t s1lo, s2lo, s1hi, s2hi; |
5b2d261d | 12455 | ARMCacheAttrs ret; |
337a03f0 RH |
12456 | bool tagged = false; |
12457 | ||
12458 | if (s1.attrs == 0xf0) { | |
12459 | tagged = true; | |
12460 | s1.attrs = 0xff; | |
12461 | } | |
12462 | ||
12463 | s1lo = extract32(s1.attrs, 0, 4); | |
12464 | s2lo = extract32(s2.attrs, 0, 4); | |
12465 | s1hi = extract32(s1.attrs, 4, 4); | |
12466 | s2hi = extract32(s2.attrs, 4, 4); | |
5b2d261d AB |
12467 | |
12468 | /* Combine shareability attributes (table D4-43) */ | |
12469 | if (s1.shareability == 2 || s2.shareability == 2) { | |
12470 | /* if either are outer-shareable, the result is outer-shareable */ | |
12471 | ret.shareability = 2; | |
12472 | } else if (s1.shareability == 3 || s2.shareability == 3) { | |
12473 | /* if either are inner-shareable, the result is inner-shareable */ | |
12474 | ret.shareability = 3; | |
12475 | } else { | |
12476 | /* both non-shareable */ | |
12477 | ret.shareability = 0; | |
12478 | } | |
12479 | ||
12480 | /* Combine memory type and cacheability attributes */ | |
12481 | if (s1hi == 0 || s2hi == 0) { | |
12482 | /* Device has precedence over normal */ | |
12483 | if (s1lo == 0 || s2lo == 0) { | |
12484 | /* nGnRnE has precedence over anything */ | |
12485 | ret.attrs = 0; | |
12486 | } else if (s1lo == 4 || s2lo == 4) { | |
12487 | /* non-Reordering has precedence over Reordering */ | |
12488 | ret.attrs = 4; /* nGnRE */ | |
12489 | } else if (s1lo == 8 || s2lo == 8) { | |
12490 | /* non-Gathering has precedence over Gathering */ | |
12491 | ret.attrs = 8; /* nGRE */ | |
12492 | } else { | |
12493 | ret.attrs = 0xc; /* GRE */ | |
12494 | } | |
12495 | ||
12496 | /* Any location for which the resultant memory type is any | |
12497 | * type of Device memory is always treated as Outer Shareable. | |
12498 | */ | |
12499 | ret.shareability = 2; | |
12500 | } else { /* Normal memory */ | |
12501 | /* Outer/inner cacheability combine independently */ | |
12502 | ret.attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4 | |
12503 | | combine_cacheattr_nibble(s1lo, s2lo); | |
12504 | ||
12505 | if (ret.attrs == 0x44) { | |
12506 | /* Any location for which the resultant memory type is Normal | |
12507 | * Inner Non-cacheable, Outer Non-cacheable is always treated | |
12508 | * as Outer Shareable. | |
12509 | */ | |
12510 | ret.shareability = 2; | |
12511 | } | |
12512 | } | |
12513 | ||
337a03f0 RH |
12514 | /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */ |
12515 | if (tagged && ret.attrs == 0xff) { | |
12516 | ret.attrs = 0xf0; | |
12517 | } | |
12518 | ||
5b2d261d AB |
12519 | return ret; |
12520 | } | |
12521 | ||
12522 | ||
702a9357 PM |
12523 | /* get_phys_addr - get the physical address for this virtual address |
12524 | * | |
12525 | * Find the physical address corresponding to the given virtual address, | |
12526 | * by doing a translation table walk on MMU based systems or using the | |
12527 | * MPU state on MPU based systems. | |
12528 | * | |
b7cc4e82 PC |
12529 | * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, |
12530 | * prot and page_size may not be filled in, and the populated fsr value provides | |
702a9357 PM |
12531 | * information on why the translation aborted, in the format of a |
12532 | * DFSR/IFSR fault register, with the following caveats: | |
12533 | * * we honour the short vs long DFSR format differences. | |
12534 | * * the WnR bit is never set (the caller must do this). | |
f6bda88f | 12535 | * * for PSMAv5 based systems we don't bother to return a full FSR format |
702a9357 PM |
12536 | * value. |
12537 | * | |
12538 | * @env: CPUARMState | |
12539 | * @address: virtual address to get physical address for | |
12540 | * @access_type: 0 for read, 1 for write, 2 for execute | |
d3649702 | 12541 | * @mmu_idx: MMU index indicating required translation regime |
702a9357 | 12542 | * @phys_ptr: set to the physical address corresponding to the virtual address |
8bf5b6a9 | 12543 | * @attrs: set to the memory transaction attributes to use |
702a9357 PM |
12544 | * @prot: set to the permissions for the page containing phys_ptr |
12545 | * @page_size: set to the size of the page containing phys_ptr | |
5b2d261d AB |
12546 | * @fi: set to fault info if the translation fails |
12547 | * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes | |
702a9357 | 12548 | */ |
ebae861f PMD |
12549 | bool get_phys_addr(CPUARMState *env, target_ulong address, |
12550 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
12551 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, | |
12552 | target_ulong *page_size, | |
12553 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) | |
9ee6e8bb | 12554 | { |
7879460a RDC |
12555 | ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx); |
12556 | ||
12557 | if (mmu_idx != s1_mmu_idx) { | |
9b539263 | 12558 | /* Call ourselves recursively to do the stage 1 and then stage 2 |
7879460a | 12559 | * translations if mmu_idx is a two-stage regime. |
0480f69a | 12560 | */ |
9b539263 EI |
12561 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
12562 | hwaddr ipa; | |
12563 | int s2_prot; | |
12564 | int ret; | |
6c05a866 | 12565 | bool ipa_secure; |
5b2d261d | 12566 | ARMCacheAttrs cacheattrs2 = {}; |
b1a10c86 RDC |
12567 | ARMMMUIdx s2_mmu_idx; |
12568 | bool is_el0; | |
9b539263 | 12569 | |
7879460a RDC |
12570 | ret = get_phys_addr(env, address, access_type, s1_mmu_idx, &ipa, |
12571 | attrs, prot, page_size, fi, cacheattrs); | |
9b539263 EI |
12572 | |
12573 | /* If S1 fails or S2 is disabled, return early. */ | |
97fa9350 | 12574 | if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) { |
9b539263 EI |
12575 | *phys_ptr = ipa; |
12576 | return ret; | |
12577 | } | |
12578 | ||
6c05a866 | 12579 | ipa_secure = attrs->secure; |
bcd7a8cf | 12580 | if (arm_is_secure_below_el3(env)) { |
6c05a866 | 12581 | if (ipa_secure) { |
bcd7a8cf IH |
12582 | attrs->secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); |
12583 | } else { | |
12584 | attrs->secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); | |
12585 | } | |
12586 | } else { | |
6c05a866 | 12587 | assert(!ipa_secure); |
bcd7a8cf IH |
12588 | } |
12589 | ||
b1a10c86 RDC |
12590 | s2_mmu_idx = attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; |
12591 | is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0; | |
12592 | ||
9b539263 | 12593 | /* S1 is done. Now do S2 translation. */ |
b1a10c86 | 12594 | ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, is_el0, |
9b539263 | 12595 | phys_ptr, attrs, &s2_prot, |
7e98e21c | 12596 | page_size, fi, &cacheattrs2); |
9b539263 EI |
12597 | fi->s2addr = ipa; |
12598 | /* Combine the S1 and S2 perms. */ | |
12599 | *prot &= s2_prot; | |
5b2d261d | 12600 | |
7e98e21c RH |
12601 | /* If S2 fails, return early. */ |
12602 | if (ret) { | |
12603 | return ret; | |
5b2d261d AB |
12604 | } |
12605 | ||
7e98e21c | 12606 | /* Combine the S1 and S2 cache attributes. */ |
e04a5752 | 12607 | if (arm_hcr_el2_eff(env) & HCR_DC) { |
7e98e21c RH |
12608 | /* |
12609 | * HCR.DC forces the first stage attributes to | |
12610 | * Normal Non-Shareable, | |
12611 | * Inner Write-Back Read-Allocate Write-Allocate, | |
12612 | * Outer Write-Back Read-Allocate Write-Allocate. | |
337a03f0 | 12613 | * Do not overwrite Tagged within attrs. |
7e98e21c | 12614 | */ |
337a03f0 RH |
12615 | if (cacheattrs->attrs != 0xf0) { |
12616 | cacheattrs->attrs = 0xff; | |
12617 | } | |
7e98e21c RH |
12618 | cacheattrs->shareability = 0; |
12619 | } | |
12620 | *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2); | |
b1a10c86 RDC |
12621 | |
12622 | /* Check if IPA translates to secure or non-secure PA space. */ | |
12623 | if (arm_is_secure_below_el3(env)) { | |
6c05a866 | 12624 | if (ipa_secure) { |
b1a10c86 RDC |
12625 | attrs->secure = |
12626 | !(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW)); | |
12627 | } else { | |
12628 | attrs->secure = | |
12629 | !((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA | VTCR_NSW)) | |
d3b2d191 | 12630 | || (env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW))); |
b1a10c86 RDC |
12631 | } |
12632 | } | |
7e98e21c | 12633 | return 0; |
9b539263 EI |
12634 | } else { |
12635 | /* | |
12636 | * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. | |
12637 | */ | |
8bd5c820 | 12638 | mmu_idx = stage_1_mmu_idx(mmu_idx); |
9b539263 | 12639 | } |
0480f69a | 12640 | } |
d3649702 | 12641 | |
8bf5b6a9 PM |
12642 | /* The page table entries may downgrade secure to non-secure, but |
12643 | * cannot upgrade an non-secure translation regime's attributes | |
12644 | * to secure. | |
12645 | */ | |
12646 | attrs->secure = regime_is_secure(env, mmu_idx); | |
0995bf8c | 12647 | attrs->user = regime_is_user(env, mmu_idx); |
8bf5b6a9 | 12648 | |
0480f69a PM |
12649 | /* Fast Context Switch Extension. This doesn't exist at all in v8. |
12650 | * In v7 and earlier it affects all stage 1 translations. | |
12651 | */ | |
97fa9350 | 12652 | if (address < 0x02000000 && mmu_idx != ARMMMUIdx_Stage2 |
0480f69a PM |
12653 | && !arm_feature(env, ARM_FEATURE_V8)) { |
12654 | if (regime_el(env, mmu_idx) == 3) { | |
12655 | address += env->cp15.fcseidr_s; | |
12656 | } else { | |
12657 | address += env->cp15.fcseidr_ns; | |
12658 | } | |
54bf36ed | 12659 | } |
9ee6e8bb | 12660 | |
3279adb9 | 12661 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
c9f9f124 | 12662 | bool ret; |
f6bda88f | 12663 | *page_size = TARGET_PAGE_SIZE; |
3279adb9 | 12664 | |
504e3cc3 PM |
12665 | if (arm_feature(env, ARM_FEATURE_V8)) { |
12666 | /* PMSAv8 */ | |
12667 | ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, | |
72042435 | 12668 | phys_ptr, attrs, prot, page_size, fi); |
504e3cc3 | 12669 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
3279adb9 PM |
12670 | /* PMSAv7 */ |
12671 | ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, | |
e5e40999 | 12672 | phys_ptr, prot, page_size, fi); |
3279adb9 PM |
12673 | } else { |
12674 | /* Pre-v7 MPU */ | |
12675 | ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, | |
53a4e5c5 | 12676 | phys_ptr, prot, fi); |
3279adb9 PM |
12677 | } |
12678 | qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 | |
c9f9f124 | 12679 | " mmu_idx %u -> %s (prot %c%c%c)\n", |
709e4407 PM |
12680 | access_type == MMU_DATA_LOAD ? "reading" : |
12681 | (access_type == MMU_DATA_STORE ? "writing" : "execute"), | |
c9f9f124 MD |
12682 | (uint32_t)address, mmu_idx, |
12683 | ret ? "Miss" : "Hit", | |
12684 | *prot & PAGE_READ ? 'r' : '-', | |
12685 | *prot & PAGE_WRITE ? 'w' : '-', | |
12686 | *prot & PAGE_EXEC ? 'x' : '-'); | |
12687 | ||
12688 | return ret; | |
f6bda88f PC |
12689 | } |
12690 | ||
3279adb9 PM |
12691 | /* Definitely a real MMU, not an MPU */ |
12692 | ||
0480f69a | 12693 | if (regime_translation_disabled(env, mmu_idx)) { |
337a03f0 RH |
12694 | uint64_t hcr; |
12695 | uint8_t memattr; | |
12696 | ||
cebfb648 RH |
12697 | /* |
12698 | * MMU disabled. S1 addresses within aa64 translation regimes are | |
12699 | * still checked for bounds -- see AArch64.TranslateAddressS1Off. | |
12700 | */ | |
b1a10c86 | 12701 | if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) { |
cebfb648 RH |
12702 | int r_el = regime_el(env, mmu_idx); |
12703 | if (arm_el_is_aa64(env, r_el)) { | |
12704 | int pamax = arm_pamax(env_archcpu(env)); | |
12705 | uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr; | |
12706 | int addrtop, tbi; | |
12707 | ||
12708 | tbi = aa64_va_parameter_tbi(tcr, mmu_idx); | |
12709 | if (access_type == MMU_INST_FETCH) { | |
12710 | tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); | |
12711 | } | |
12712 | tbi = (tbi >> extract64(address, 55, 1)) & 1; | |
12713 | addrtop = (tbi ? 55 : 63); | |
12714 | ||
12715 | if (extract64(address, pamax, addrtop - pamax + 1) != 0) { | |
12716 | fi->type = ARMFault_AddressSize; | |
12717 | fi->level = 0; | |
12718 | fi->stage2 = false; | |
12719 | return 1; | |
12720 | } | |
12721 | ||
12722 | /* | |
12723 | * When TBI is disabled, we've just validated that all of the | |
12724 | * bits above PAMax are zero, so logically we only need to | |
12725 | * clear the top byte for TBI. But it's clearer to follow | |
12726 | * the pseudocode set of addrdesc.paddress. | |
12727 | */ | |
12728 | address = extract64(address, 0, 52); | |
12729 | } | |
12730 | } | |
9ee6e8bb | 12731 | *phys_ptr = address; |
3ad493fc | 12732 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
d4c430a8 | 12733 | *page_size = TARGET_PAGE_SIZE; |
337a03f0 RH |
12734 | |
12735 | /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ | |
12736 | hcr = arm_hcr_el2_eff(env); | |
12737 | cacheattrs->shareability = 0; | |
12738 | if (hcr & HCR_DC) { | |
12739 | if (hcr & HCR_DCT) { | |
12740 | memattr = 0xf0; /* Tagged, Normal, WB, RWA */ | |
12741 | } else { | |
12742 | memattr = 0xff; /* Normal, WB, RWA */ | |
12743 | } | |
12744 | } else if (access_type == MMU_INST_FETCH) { | |
12745 | if (regime_sctlr(env, mmu_idx) & SCTLR_I) { | |
12746 | memattr = 0xee; /* Normal, WT, RA, NT */ | |
12747 | } else { | |
12748 | memattr = 0x44; /* Normal, NC, No */ | |
12749 | } | |
12750 | cacheattrs->shareability = 2; /* outer sharable */ | |
12751 | } else { | |
12752 | memattr = 0x00; /* Device, nGnRnE */ | |
12753 | } | |
12754 | cacheattrs->attrs = memattr; | |
9ee6e8bb | 12755 | return 0; |
0480f69a PM |
12756 | } |
12757 | ||
0480f69a | 12758 | if (regime_using_lpae_format(env, mmu_idx)) { |
ff7de2fc | 12759 | return get_phys_addr_lpae(env, address, access_type, mmu_idx, false, |
bc52bfeb PM |
12760 | phys_ptr, attrs, prot, page_size, |
12761 | fi, cacheattrs); | |
0480f69a | 12762 | } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { |
bc52bfeb PM |
12763 | return get_phys_addr_v6(env, address, access_type, mmu_idx, |
12764 | phys_ptr, attrs, prot, page_size, fi); | |
9ee6e8bb | 12765 | } else { |
bc52bfeb | 12766 | return get_phys_addr_v5(env, address, access_type, mmu_idx, |
f989983e | 12767 | phys_ptr, prot, page_size, fi); |
9ee6e8bb PB |
12768 | } |
12769 | } | |
12770 | ||
0faea0c7 PM |
12771 | hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, |
12772 | MemTxAttrs *attrs) | |
b5ff1b31 | 12773 | { |
00b941e5 | 12774 | ARMCPU *cpu = ARM_CPU(cs); |
d3649702 | 12775 | CPUARMState *env = &cpu->env; |
a8170e5e | 12776 | hwaddr phys_addr; |
d4c430a8 | 12777 | target_ulong page_size; |
b5ff1b31 | 12778 | int prot; |
b7cc4e82 | 12779 | bool ret; |
e14b5a23 | 12780 | ARMMMUFaultInfo fi = {}; |
50494a27 | 12781 | ARMMMUIdx mmu_idx = arm_mmu_idx(env); |
7e98e21c | 12782 | ARMCacheAttrs cacheattrs = {}; |
b5ff1b31 | 12783 | |
0faea0c7 PM |
12784 | *attrs = (MemTxAttrs) {}; |
12785 | ||
a9dd161f | 12786 | ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &phys_addr, |
7e98e21c | 12787 | attrs, &prot, &page_size, &fi, &cacheattrs); |
b5ff1b31 | 12788 | |
b7cc4e82 | 12789 | if (ret) { |
b5ff1b31 | 12790 | return -1; |
00b941e5 | 12791 | } |
b5ff1b31 FB |
12792 | return phys_addr; |
12793 | } | |
12794 | ||
b5ff1b31 | 12795 | #endif |
6ddbc6e4 PB |
12796 | |
12797 | /* Note that signed overflow is undefined in C. The following routines are | |
12798 | careful to use unsigned types where modulo arithmetic is required. | |
12799 | Failure to do so _will_ break on newer gcc. */ | |
12800 | ||
12801 | /* Signed saturating arithmetic. */ | |
12802 | ||
1654b2d6 | 12803 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
12804 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
12805 | { | |
12806 | uint16_t res; | |
12807 | ||
12808 | res = a + b; | |
12809 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
12810 | if (a & 0x8000) | |
12811 | res = 0x8000; | |
12812 | else | |
12813 | res = 0x7fff; | |
12814 | } | |
12815 | return res; | |
12816 | } | |
12817 | ||
1654b2d6 | 12818 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
12819 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
12820 | { | |
12821 | uint8_t res; | |
12822 | ||
12823 | res = a + b; | |
12824 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
12825 | if (a & 0x80) | |
12826 | res = 0x80; | |
12827 | else | |
12828 | res = 0x7f; | |
12829 | } | |
12830 | return res; | |
12831 | } | |
12832 | ||
1654b2d6 | 12833 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
12834 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
12835 | { | |
12836 | uint16_t res; | |
12837 | ||
12838 | res = a - b; | |
12839 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
12840 | if (a & 0x8000) | |
12841 | res = 0x8000; | |
12842 | else | |
12843 | res = 0x7fff; | |
12844 | } | |
12845 | return res; | |
12846 | } | |
12847 | ||
1654b2d6 | 12848 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
12849 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
12850 | { | |
12851 | uint8_t res; | |
12852 | ||
12853 | res = a - b; | |
12854 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
12855 | if (a & 0x80) | |
12856 | res = 0x80; | |
12857 | else | |
12858 | res = 0x7f; | |
12859 | } | |
12860 | return res; | |
12861 | } | |
12862 | ||
12863 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
12864 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
12865 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
12866 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
12867 | #define PFX q | |
12868 | ||
12869 | #include "op_addsub.h" | |
12870 | ||
12871 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 12872 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
12873 | { |
12874 | uint16_t res; | |
12875 | res = a + b; | |
12876 | if (res < a) | |
12877 | res = 0xffff; | |
12878 | return res; | |
12879 | } | |
12880 | ||
460a09c1 | 12881 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 | 12882 | { |
4c4fd3f8 | 12883 | if (a > b) |
6ddbc6e4 PB |
12884 | return a - b; |
12885 | else | |
12886 | return 0; | |
12887 | } | |
12888 | ||
12889 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
12890 | { | |
12891 | uint8_t res; | |
12892 | res = a + b; | |
12893 | if (res < a) | |
12894 | res = 0xff; | |
12895 | return res; | |
12896 | } | |
12897 | ||
12898 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
12899 | { | |
4c4fd3f8 | 12900 | if (a > b) |
6ddbc6e4 PB |
12901 | return a - b; |
12902 | else | |
12903 | return 0; | |
12904 | } | |
12905 | ||
12906 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
12907 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
12908 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
12909 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
12910 | #define PFX uq | |
12911 | ||
12912 | #include "op_addsub.h" | |
12913 | ||
12914 | /* Signed modulo arithmetic. */ | |
12915 | #define SARITH16(a, b, n, op) do { \ | |
12916 | int32_t sum; \ | |
db6e2e65 | 12917 | sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
6ddbc6e4 PB |
12918 | RESULT(sum, n, 16); \ |
12919 | if (sum >= 0) \ | |
12920 | ge |= 3 << (n * 2); \ | |
12921 | } while(0) | |
12922 | ||
12923 | #define SARITH8(a, b, n, op) do { \ | |
12924 | int32_t sum; \ | |
db6e2e65 | 12925 | sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
6ddbc6e4 PB |
12926 | RESULT(sum, n, 8); \ |
12927 | if (sum >= 0) \ | |
12928 | ge |= 1 << n; \ | |
12929 | } while(0) | |
12930 | ||
12931 | ||
12932 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
12933 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
12934 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
12935 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
12936 | #define PFX s | |
12937 | #define ARITH_GE | |
12938 | ||
12939 | #include "op_addsub.h" | |
12940 | ||
12941 | /* Unsigned modulo arithmetic. */ | |
12942 | #define ADD16(a, b, n) do { \ | |
12943 | uint32_t sum; \ | |
12944 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
12945 | RESULT(sum, n, 16); \ | |
a87aa10b | 12946 | if ((sum >> 16) == 1) \ |
6ddbc6e4 PB |
12947 | ge |= 3 << (n * 2); \ |
12948 | } while(0) | |
12949 | ||
12950 | #define ADD8(a, b, n) do { \ | |
12951 | uint32_t sum; \ | |
12952 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
12953 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
12954 | if ((sum >> 8) == 1) \ |
12955 | ge |= 1 << n; \ | |
6ddbc6e4 PB |
12956 | } while(0) |
12957 | ||
12958 | #define SUB16(a, b, n) do { \ | |
12959 | uint32_t sum; \ | |
12960 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
12961 | RESULT(sum, n, 16); \ | |
12962 | if ((sum >> 16) == 0) \ | |
12963 | ge |= 3 << (n * 2); \ | |
12964 | } while(0) | |
12965 | ||
12966 | #define SUB8(a, b, n) do { \ | |
12967 | uint32_t sum; \ | |
12968 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
12969 | RESULT(sum, n, 8); \ | |
12970 | if ((sum >> 8) == 0) \ | |
a87aa10b | 12971 | ge |= 1 << n; \ |
6ddbc6e4 PB |
12972 | } while(0) |
12973 | ||
12974 | #define PFX u | |
12975 | #define ARITH_GE | |
12976 | ||
12977 | #include "op_addsub.h" | |
12978 | ||
12979 | /* Halved signed arithmetic. */ | |
12980 | #define ADD16(a, b, n) \ | |
12981 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
12982 | #define SUB16(a, b, n) \ | |
12983 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
12984 | #define ADD8(a, b, n) \ | |
12985 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
12986 | #define SUB8(a, b, n) \ | |
12987 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
12988 | #define PFX sh | |
12989 | ||
12990 | #include "op_addsub.h" | |
12991 | ||
12992 | /* Halved unsigned arithmetic. */ | |
12993 | #define ADD16(a, b, n) \ | |
12994 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
12995 | #define SUB16(a, b, n) \ | |
12996 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
12997 | #define ADD8(a, b, n) \ | |
12998 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
12999 | #define SUB8(a, b, n) \ | |
13000 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
13001 | #define PFX uh | |
13002 | ||
13003 | #include "op_addsub.h" | |
13004 | ||
13005 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
13006 | { | |
13007 | if (a > b) | |
13008 | return a - b; | |
13009 | else | |
13010 | return b - a; | |
13011 | } | |
13012 | ||
13013 | /* Unsigned sum of absolute byte differences. */ | |
13014 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
13015 | { | |
13016 | uint32_t sum; | |
13017 | sum = do_usad(a, b); | |
13018 | sum += do_usad(a >> 8, b >> 8); | |
bdc3b6f5 | 13019 | sum += do_usad(a >> 16, b >> 16); |
6ddbc6e4 PB |
13020 | sum += do_usad(a >> 24, b >> 24); |
13021 | return sum; | |
13022 | } | |
13023 | ||
13024 | /* For ARMv6 SEL instruction. */ | |
13025 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
13026 | { | |
13027 | uint32_t mask; | |
13028 | ||
13029 | mask = 0; | |
13030 | if (flags & 1) | |
13031 | mask |= 0xff; | |
13032 | if (flags & 2) | |
13033 | mask |= 0xff00; | |
13034 | if (flags & 4) | |
13035 | mask |= 0xff0000; | |
13036 | if (flags & 8) | |
13037 | mask |= 0xff000000; | |
13038 | return (a & mask) | (b & ~mask); | |
13039 | } | |
13040 | ||
aa633469 PM |
13041 | /* CRC helpers. |
13042 | * The upper bytes of val (above the number specified by 'bytes') must have | |
13043 | * been zeroed out by the caller. | |
13044 | */ | |
eb0ecd5a WN |
13045 | uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) |
13046 | { | |
13047 | uint8_t buf[4]; | |
13048 | ||
aa633469 | 13049 | stl_le_p(buf, val); |
eb0ecd5a WN |
13050 | |
13051 | /* zlib crc32 converts the accumulator and output to one's complement. */ | |
13052 | return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | |
13053 | } | |
13054 | ||
13055 | uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | |
13056 | { | |
13057 | uint8_t buf[4]; | |
13058 | ||
aa633469 | 13059 | stl_le_p(buf, val); |
eb0ecd5a WN |
13060 | |
13061 | /* Linux crc32c converts the output to one's complement. */ | |
13062 | return crc32c(acc, buf, bytes) ^ 0xffffffff; | |
13063 | } | |
a9e01311 RH |
13064 | |
13065 | /* Return the exception level to which FP-disabled exceptions should | |
13066 | * be taken, or 0 if FP is enabled. | |
13067 | */ | |
ced31551 | 13068 | int fp_exception_el(CPUARMState *env, int cur_el) |
a9e01311 | 13069 | { |
55faa212 | 13070 | #ifndef CONFIG_USER_ONLY |
d5a6fa2d RH |
13071 | uint64_t hcr_el2; |
13072 | ||
a9e01311 RH |
13073 | /* CPACR and the CPTR registers don't exist before v6, so FP is |
13074 | * always accessible | |
13075 | */ | |
13076 | if (!arm_feature(env, ARM_FEATURE_V6)) { | |
13077 | return 0; | |
13078 | } | |
13079 | ||
d87513c0 PM |
13080 | if (arm_feature(env, ARM_FEATURE_M)) { |
13081 | /* CPACR can cause a NOCP UsageFault taken to current security state */ | |
13082 | if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) { | |
13083 | return 1; | |
13084 | } | |
13085 | ||
13086 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) { | |
13087 | if (!extract32(env->v7m.nsacr, 10, 1)) { | |
13088 | /* FP insns cause a NOCP UsageFault taken to Secure */ | |
13089 | return 3; | |
13090 | } | |
13091 | } | |
13092 | ||
13093 | return 0; | |
13094 | } | |
13095 | ||
d5a6fa2d RH |
13096 | hcr_el2 = arm_hcr_el2_eff(env); |
13097 | ||
a9e01311 RH |
13098 | /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: |
13099 | * 0, 2 : trap EL0 and EL1/PL1 accesses | |
13100 | * 1 : trap only EL0 accesses | |
13101 | * 3 : trap no accesses | |
c2ddb7cf | 13102 | * This register is ignored if E2H+TGE are both set. |
a9e01311 | 13103 | */ |
d5a6fa2d | 13104 | if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { |
c2ddb7cf RH |
13105 | int fpen = extract32(env->cp15.cpacr_el1, 20, 2); |
13106 | ||
13107 | switch (fpen) { | |
13108 | case 0: | |
13109 | case 2: | |
13110 | if (cur_el == 0 || cur_el == 1) { | |
13111 | /* Trap to PL1, which might be EL1 or EL3 */ | |
13112 | if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { | |
13113 | return 3; | |
13114 | } | |
13115 | return 1; | |
13116 | } | |
13117 | if (cur_el == 3 && !is_a64(env)) { | |
13118 | /* Secure PL1 running at EL3 */ | |
a9e01311 RH |
13119 | return 3; |
13120 | } | |
c2ddb7cf RH |
13121 | break; |
13122 | case 1: | |
13123 | if (cur_el == 0) { | |
13124 | return 1; | |
13125 | } | |
13126 | break; | |
13127 | case 3: | |
13128 | break; | |
a9e01311 | 13129 | } |
a9e01311 RH |
13130 | } |
13131 | ||
fc1120a7 PM |
13132 | /* |
13133 | * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode | |
13134 | * to control non-secure access to the FPU. It doesn't have any | |
13135 | * effect if EL3 is AArch64 or if EL3 doesn't exist at all. | |
13136 | */ | |
13137 | if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
13138 | cur_el <= 2 && !arm_is_secure_below_el3(env))) { | |
13139 | if (!extract32(env->cp15.nsacr, 10, 1)) { | |
13140 | /* FP insns act as UNDEF */ | |
13141 | return cur_el == 2 ? 2 : 1; | |
13142 | } | |
13143 | } | |
13144 | ||
d5a6fa2d RH |
13145 | /* |
13146 | * CPTR_EL2 is present in v7VE or v8, and changes format | |
13147 | * with HCR_EL2.E2H (regardless of TGE). | |
a9e01311 | 13148 | */ |
d5a6fa2d RH |
13149 | if (cur_el <= 2) { |
13150 | if (hcr_el2 & HCR_E2H) { | |
13151 | /* Check CPTR_EL2.FPEN. */ | |
13152 | switch (extract32(env->cp15.cptr_el[2], 20, 2)) { | |
13153 | case 1: | |
13154 | if (cur_el != 0 || !(hcr_el2 & HCR_TGE)) { | |
13155 | break; | |
13156 | } | |
13157 | /* fall through */ | |
13158 | case 0: | |
13159 | case 2: | |
13160 | return 2; | |
13161 | } | |
13162 | } else if (arm_is_el2_enabled(env)) { | |
13163 | if (env->cp15.cptr_el[2] & CPTR_TFP) { | |
13164 | return 2; | |
13165 | } | |
13166 | } | |
a9e01311 RH |
13167 | } |
13168 | ||
13169 | /* CPTR_EL3 : present in v8 */ | |
a7b66ada | 13170 | if (env->cp15.cptr_el[3] & CPTR_TFP) { |
a9e01311 RH |
13171 | /* Trap all FP ops to EL3 */ |
13172 | return 3; | |
13173 | } | |
55faa212 | 13174 | #endif |
a9e01311 RH |
13175 | return 0; |
13176 | } | |
13177 | ||
b9f6033c RH |
13178 | /* Return the exception level we're running at if this is our mmu_idx */ |
13179 | int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) | |
13180 | { | |
13181 | if (mmu_idx & ARM_MMU_IDX_M) { | |
13182 | return mmu_idx & ARM_MMU_IDX_M_PRIV; | |
13183 | } | |
13184 | ||
13185 | switch (mmu_idx) { | |
13186 | case ARMMMUIdx_E10_0: | |
13187 | case ARMMMUIdx_E20_0: | |
13188 | case ARMMMUIdx_SE10_0: | |
b6ad6062 | 13189 | case ARMMMUIdx_SE20_0: |
b9f6033c RH |
13190 | return 0; |
13191 | case ARMMMUIdx_E10_1: | |
452ef8cb | 13192 | case ARMMMUIdx_E10_1_PAN: |
b9f6033c | 13193 | case ARMMMUIdx_SE10_1: |
452ef8cb | 13194 | case ARMMMUIdx_SE10_1_PAN: |
b9f6033c RH |
13195 | return 1; |
13196 | case ARMMMUIdx_E2: | |
13197 | case ARMMMUIdx_E20_2: | |
452ef8cb | 13198 | case ARMMMUIdx_E20_2_PAN: |
b6ad6062 RDC |
13199 | case ARMMMUIdx_SE2: |
13200 | case ARMMMUIdx_SE20_2: | |
13201 | case ARMMMUIdx_SE20_2_PAN: | |
b9f6033c RH |
13202 | return 2; |
13203 | case ARMMMUIdx_SE3: | |
13204 | return 3; | |
13205 | default: | |
13206 | g_assert_not_reached(); | |
13207 | } | |
13208 | } | |
13209 | ||
7aab5a8c | 13210 | #ifndef CONFIG_TCG |
65e4655c RH |
13211 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
13212 | { | |
7aab5a8c | 13213 | g_assert_not_reached(); |
65e4655c | 13214 | } |
7aab5a8c | 13215 | #endif |
65e4655c | 13216 | |
164690b2 | 13217 | ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) |
65e4655c | 13218 | { |
b6ad6062 RDC |
13219 | ARMMMUIdx idx; |
13220 | uint64_t hcr; | |
13221 | ||
65e4655c | 13222 | if (arm_feature(env, ARM_FEATURE_M)) { |
50494a27 | 13223 | return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); |
65e4655c RH |
13224 | } |
13225 | ||
6003d980 | 13226 | /* See ARM pseudo-function ELIsInHost. */ |
b9f6033c RH |
13227 | switch (el) { |
13228 | case 0: | |
b6ad6062 RDC |
13229 | hcr = arm_hcr_el2_eff(env); |
13230 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
13231 | idx = ARMMMUIdx_E20_0; | |
13232 | } else { | |
13233 | idx = ARMMMUIdx_E10_0; | |
6003d980 | 13234 | } |
b6ad6062 | 13235 | break; |
b9f6033c | 13236 | case 1: |
66412260 | 13237 | if (env->pstate & PSTATE_PAN) { |
b6ad6062 RDC |
13238 | idx = ARMMMUIdx_E10_1_PAN; |
13239 | } else { | |
13240 | idx = ARMMMUIdx_E10_1; | |
66412260 | 13241 | } |
b6ad6062 | 13242 | break; |
b9f6033c | 13243 | case 2: |
6003d980 | 13244 | /* Note that TGE does not apply at EL2. */ |
b6ad6062 | 13245 | if (arm_hcr_el2_eff(env) & HCR_E2H) { |
66412260 | 13246 | if (env->pstate & PSTATE_PAN) { |
b6ad6062 RDC |
13247 | idx = ARMMMUIdx_E20_2_PAN; |
13248 | } else { | |
13249 | idx = ARMMMUIdx_E20_2; | |
66412260 | 13250 | } |
b6ad6062 RDC |
13251 | } else { |
13252 | idx = ARMMMUIdx_E2; | |
6003d980 | 13253 | } |
b6ad6062 | 13254 | break; |
b9f6033c RH |
13255 | case 3: |
13256 | return ARMMMUIdx_SE3; | |
13257 | default: | |
13258 | g_assert_not_reached(); | |
65e4655c | 13259 | } |
b6ad6062 RDC |
13260 | |
13261 | if (arm_is_secure_below_el3(env)) { | |
13262 | idx &= ~ARM_MMU_IDX_A_NS; | |
13263 | } | |
13264 | ||
13265 | return idx; | |
50494a27 RH |
13266 | } |
13267 | ||
164690b2 RH |
13268 | ARMMMUIdx arm_mmu_idx(CPUARMState *env) |
13269 | { | |
13270 | return arm_mmu_idx_el(env, arm_current_el(env)); | |
13271 | } | |
13272 | ||
64be86ab RH |
13273 | #ifndef CONFIG_USER_ONLY |
13274 | ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) | |
13275 | { | |
13276 | return stage_1_mmu_idx(arm_mmu_idx(env)); | |
13277 | } | |
13278 | #endif | |
13279 | ||
3902bfc6 RH |
13280 | static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, |
13281 | ARMMMUIdx mmu_idx, | |
13282 | CPUARMTBFlags flags) | |
fdd1b228 | 13283 | { |
a729a46b RH |
13284 | DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el); |
13285 | DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); | |
fdd1b228 | 13286 | |
fdd1b228 | 13287 | if (arm_singlestep_active(env)) { |
a729a46b | 13288 | DP_TBFLAG_ANY(flags, SS_ACTIVE, 1); |
fdd1b228 RH |
13289 | } |
13290 | return flags; | |
13291 | } | |
13292 | ||
3902bfc6 RH |
13293 | static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el, |
13294 | ARMMMUIdx mmu_idx, | |
13295 | CPUARMTBFlags flags) | |
43eccfb6 | 13296 | { |
8061a649 RH |
13297 | bool sctlr_b = arm_sctlr_b(env); |
13298 | ||
13299 | if (sctlr_b) { | |
a729a46b | 13300 | DP_TBFLAG_A32(flags, SCTLR__B, 1); |
8061a649 RH |
13301 | } |
13302 | if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { | |
a729a46b | 13303 | DP_TBFLAG_ANY(flags, BE_DATA, 1); |
8061a649 | 13304 | } |
a729a46b | 13305 | DP_TBFLAG_A32(flags, NS, !access_secure_reg(env)); |
43eccfb6 RH |
13306 | |
13307 | return rebuild_hflags_common(env, fp_el, mmu_idx, flags); | |
13308 | } | |
13309 | ||
3902bfc6 RH |
13310 | static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, |
13311 | ARMMMUIdx mmu_idx) | |
6e33ced5 | 13312 | { |
3902bfc6 | 13313 | CPUARMTBFlags flags = {}; |
4479ec30 RH |
13314 | uint32_t ccr = env->v7m.ccr[env->v7m.secure]; |
13315 | ||
13316 | /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */ | |
13317 | if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) { | |
13318 | DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); | |
13319 | } | |
6e33ced5 RH |
13320 | |
13321 | if (arm_v7m_is_handler_mode(env)) { | |
a729a46b | 13322 | DP_TBFLAG_M32(flags, HANDLER, 1); |
6e33ced5 RH |
13323 | } |
13324 | ||
13325 | /* | |
13326 | * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN | |
13327 | * is suppressing them because the requested execution priority | |
13328 | * is less than 0. | |
13329 | */ | |
13330 | if (arm_feature(env, ARM_FEATURE_V8) && | |
13331 | !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && | |
4479ec30 | 13332 | (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) { |
a729a46b | 13333 | DP_TBFLAG_M32(flags, STACKCHECK, 1); |
6e33ced5 RH |
13334 | } |
13335 | ||
13336 | return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); | |
13337 | } | |
13338 | ||
3902bfc6 | 13339 | static CPUARMTBFlags rebuild_hflags_aprofile(CPUARMState *env) |
83f4baef | 13340 | { |
3902bfc6 | 13341 | CPUARMTBFlags flags = {}; |
83f4baef | 13342 | |
a729a46b | 13343 | DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env)); |
83f4baef RH |
13344 | return flags; |
13345 | } | |
13346 | ||
3902bfc6 RH |
13347 | static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, |
13348 | ARMMMUIdx mmu_idx) | |
c747224c | 13349 | { |
3902bfc6 | 13350 | CPUARMTBFlags flags = rebuild_hflags_aprofile(env); |
4479ec30 RH |
13351 | int el = arm_current_el(env); |
13352 | ||
13353 | if (arm_sctlr(env, el) & SCTLR_A) { | |
13354 | DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); | |
13355 | } | |
0a54d68e RH |
13356 | |
13357 | if (arm_el_is_aa64(env, 1)) { | |
a729a46b | 13358 | DP_TBFLAG_A32(flags, VFPEN, 1); |
0a54d68e | 13359 | } |
5bb0a20b | 13360 | |
4479ec30 | 13361 | if (el < 2 && env->cp15.hstr_el2 && |
5bb0a20b | 13362 | (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { |
a729a46b | 13363 | DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); |
5bb0a20b MZ |
13364 | } |
13365 | ||
520d1621 PM |
13366 | if (env->uncached_cpsr & CPSR_IL) { |
13367 | DP_TBFLAG_ANY(flags, PSTATE__IL, 1); | |
13368 | } | |
13369 | ||
83f4baef | 13370 | return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); |
c747224c RH |
13371 | } |
13372 | ||
3902bfc6 RH |
13373 | static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, |
13374 | ARMMMUIdx mmu_idx) | |
a9e01311 | 13375 | { |
3902bfc6 | 13376 | CPUARMTBFlags flags = rebuild_hflags_aprofile(env); |
d4d7503a | 13377 | ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); |
b830a5ee | 13378 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; |
d4d7503a RH |
13379 | uint64_t sctlr; |
13380 | int tbii, tbid; | |
b9adaa70 | 13381 | |
a729a46b | 13382 | DP_TBFLAG_ANY(flags, AARCH64_STATE, 1); |
cd208a1c | 13383 | |
339370b9 | 13384 | /* Get control bits for tagged addresses. */ |
b830a5ee RH |
13385 | tbid = aa64_va_parameter_tbi(tcr, mmu_idx); |
13386 | tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); | |
5d8634f5 | 13387 | |
a729a46b RH |
13388 | DP_TBFLAG_A64(flags, TBII, tbii); |
13389 | DP_TBFLAG_A64(flags, TBID, tbid); | |
d4d7503a RH |
13390 | |
13391 | if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { | |
13392 | int sve_el = sve_exception_el(env, el); | |
13393 | uint32_t zcr_len; | |
5d8634f5 | 13394 | |
d4d7503a RH |
13395 | /* |
13396 | * If SVE is disabled, but FP is enabled, | |
13397 | * then the effective len is 0. | |
13398 | */ | |
13399 | if (sve_el != 0 && fp_el == 0) { | |
13400 | zcr_len = 0; | |
13401 | } else { | |
13402 | zcr_len = sve_zcr_len_for_el(env, el); | |
5d8634f5 | 13403 | } |
a729a46b RH |
13404 | DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); |
13405 | DP_TBFLAG_A64(flags, ZCR_LEN, zcr_len); | |
d4d7503a | 13406 | } |
1db5e96c | 13407 | |
aaec1432 | 13408 | sctlr = regime_sctlr(env, stage1); |
1db5e96c | 13409 | |
4479ec30 RH |
13410 | if (sctlr & SCTLR_A) { |
13411 | DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); | |
13412 | } | |
13413 | ||
8061a649 | 13414 | if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { |
a729a46b | 13415 | DP_TBFLAG_ANY(flags, BE_DATA, 1); |
8061a649 RH |
13416 | } |
13417 | ||
d4d7503a RH |
13418 | if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { |
13419 | /* | |
13420 | * In order to save space in flags, we record only whether | |
13421 | * pauth is "inactive", meaning all insns are implemented as | |
13422 | * a nop, or "active" when some action must be performed. | |
13423 | * The decision of which action to take is left to a helper. | |
13424 | */ | |
13425 | if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { | |
a729a46b | 13426 | DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1); |
1db5e96c | 13427 | } |
d4d7503a | 13428 | } |
0816ef1b | 13429 | |
d4d7503a RH |
13430 | if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { |
13431 | /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ | |
13432 | if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { | |
a729a46b | 13433 | DP_TBFLAG_A64(flags, BT, 1); |
0816ef1b | 13434 | } |
d4d7503a | 13435 | } |
08f1434a | 13436 | |
cc28fc30 | 13437 | /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ |
7a8014ab RH |
13438 | if (!(env->pstate & PSTATE_UAO)) { |
13439 | switch (mmu_idx) { | |
13440 | case ARMMMUIdx_E10_1: | |
13441 | case ARMMMUIdx_E10_1_PAN: | |
13442 | case ARMMMUIdx_SE10_1: | |
13443 | case ARMMMUIdx_SE10_1_PAN: | |
13444 | /* TODO: ARMv8.3-NV */ | |
a729a46b | 13445 | DP_TBFLAG_A64(flags, UNPRIV, 1); |
7a8014ab RH |
13446 | break; |
13447 | case ARMMMUIdx_E20_2: | |
13448 | case ARMMMUIdx_E20_2_PAN: | |
b6ad6062 RDC |
13449 | case ARMMMUIdx_SE20_2: |
13450 | case ARMMMUIdx_SE20_2_PAN: | |
7a8014ab RH |
13451 | /* |
13452 | * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is | |
13453 | * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR. | |
13454 | */ | |
13455 | if (env->cp15.hcr_el2 & HCR_TGE) { | |
a729a46b | 13456 | DP_TBFLAG_A64(flags, UNPRIV, 1); |
7a8014ab RH |
13457 | } |
13458 | break; | |
13459 | default: | |
13460 | break; | |
cc28fc30 | 13461 | } |
cc28fc30 RH |
13462 | } |
13463 | ||
520d1621 PM |
13464 | if (env->pstate & PSTATE_IL) { |
13465 | DP_TBFLAG_ANY(flags, PSTATE__IL, 1); | |
13466 | } | |
13467 | ||
81ae05fa RH |
13468 | if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { |
13469 | /* | |
13470 | * Set MTE_ACTIVE if any access may be Checked, and leave clear | |
13471 | * if all accesses must be Unchecked: | |
13472 | * 1) If no TBI, then there are no tags in the address to check, | |
13473 | * 2) If Tag Check Override, then all accesses are Unchecked, | |
13474 | * 3) If Tag Check Fail == 0, then Checked access have no effect, | |
13475 | * 4) If no Allocation Tag Access, then all accesses are Unchecked. | |
13476 | */ | |
13477 | if (allocation_tag_access_enabled(env, el, sctlr)) { | |
a729a46b | 13478 | DP_TBFLAG_A64(flags, ATA, 1); |
81ae05fa RH |
13479 | if (tbid |
13480 | && !(env->pstate & PSTATE_TCO) | |
13481 | && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) { | |
a729a46b | 13482 | DP_TBFLAG_A64(flags, MTE_ACTIVE, 1); |
81ae05fa RH |
13483 | } |
13484 | } | |
13485 | /* And again for unprivileged accesses, if required. */ | |
a729a46b | 13486 | if (EX_TBFLAG_A64(flags, UNPRIV) |
81ae05fa RH |
13487 | && tbid |
13488 | && !(env->pstate & PSTATE_TCO) | |
2d928adf | 13489 | && (sctlr & SCTLR_TCF0) |
81ae05fa | 13490 | && allocation_tag_access_enabled(env, 0, sctlr)) { |
a729a46b | 13491 | DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); |
81ae05fa RH |
13492 | } |
13493 | /* Cache TCMA as well as TBI. */ | |
a729a46b | 13494 | DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx)); |
81ae05fa RH |
13495 | } |
13496 | ||
d4d7503a RH |
13497 | return rebuild_hflags_common(env, fp_el, mmu_idx, flags); |
13498 | } | |
13499 | ||
3902bfc6 | 13500 | static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env) |
3d74e2e9 RH |
13501 | { |
13502 | int el = arm_current_el(env); | |
13503 | int fp_el = fp_exception_el(env, el); | |
164690b2 | 13504 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); |
3d74e2e9 RH |
13505 | |
13506 | if (is_a64(env)) { | |
13507 | return rebuild_hflags_a64(env, el, fp_el, mmu_idx); | |
13508 | } else if (arm_feature(env, ARM_FEATURE_M)) { | |
13509 | return rebuild_hflags_m32(env, fp_el, mmu_idx); | |
13510 | } else { | |
13511 | return rebuild_hflags_a32(env, fp_el, mmu_idx); | |
13512 | } | |
13513 | } | |
13514 | ||
13515 | void arm_rebuild_hflags(CPUARMState *env) | |
13516 | { | |
13517 | env->hflags = rebuild_hflags_internal(env); | |
13518 | } | |
13519 | ||
19717e9b PM |
13520 | /* |
13521 | * If we have triggered a EL state change we can't rely on the | |
13522 | * translator having passed it to us, we need to recompute. | |
13523 | */ | |
13524 | void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env) | |
13525 | { | |
13526 | int el = arm_current_el(env); | |
13527 | int fp_el = fp_exception_el(env, el); | |
13528 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
3902bfc6 | 13529 | |
19717e9b PM |
13530 | env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); |
13531 | } | |
13532 | ||
14f3c588 RH |
13533 | void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) |
13534 | { | |
13535 | int fp_el = fp_exception_el(env, el); | |
13536 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
13537 | ||
13538 | env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); | |
13539 | } | |
13540 | ||
f80741d1 AB |
13541 | /* |
13542 | * If we have triggered a EL state change we can't rely on the | |
563152e0 | 13543 | * translator having passed it to us, we need to recompute. |
f80741d1 AB |
13544 | */ |
13545 | void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) | |
13546 | { | |
13547 | int el = arm_current_el(env); | |
13548 | int fp_el = fp_exception_el(env, el); | |
13549 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
13550 | env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); | |
13551 | } | |
13552 | ||
14f3c588 RH |
13553 | void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) |
13554 | { | |
13555 | int fp_el = fp_exception_el(env, el); | |
13556 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
13557 | ||
13558 | env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); | |
13559 | } | |
13560 | ||
13561 | void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) | |
13562 | { | |
13563 | int fp_el = fp_exception_el(env, el); | |
13564 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
13565 | ||
13566 | env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx); | |
13567 | } | |
13568 | ||
0ee8b24a PMD |
13569 | static inline void assert_hflags_rebuild_correctly(CPUARMState *env) |
13570 | { | |
13571 | #ifdef CONFIG_DEBUG_TCG | |
3902bfc6 RH |
13572 | CPUARMTBFlags c = env->hflags; |
13573 | CPUARMTBFlags r = rebuild_hflags_internal(env); | |
0ee8b24a | 13574 | |
a378206a RH |
13575 | if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) { |
13576 | fprintf(stderr, "TCG hflags mismatch " | |
13577 | "(current:(0x%08x,0x" TARGET_FMT_lx ")" | |
13578 | " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n", | |
13579 | c.flags, c.flags2, r.flags, r.flags2); | |
0ee8b24a PMD |
13580 | abort(); |
13581 | } | |
13582 | #endif | |
13583 | } | |
13584 | ||
26702213 PM |
13585 | static bool mve_no_pred(CPUARMState *env) |
13586 | { | |
13587 | /* | |
13588 | * Return true if there is definitely no predication of MVE | |
13589 | * instructions by VPR or LTPSIZE. (Returning false even if there | |
13590 | * isn't any predication is OK; generated code will just be | |
13591 | * a little worse.) | |
13592 | * If the CPU does not implement MVE then this TB flag is always 0. | |
13593 | * | |
13594 | * NOTE: if you change this logic, the "recalculate s->mve_no_pred" | |
13595 | * logic in gen_update_fp_context() needs to be updated to match. | |
13596 | * | |
13597 | * We do not include the effect of the ECI bits here -- they are | |
13598 | * tracked in other TB flags. This simplifies the logic for | |
13599 | * "when did we emit code that changes the MVE_NO_PRED TB flag | |
13600 | * and thus need to end the TB?". | |
13601 | */ | |
13602 | if (cpu_isar_feature(aa32_mve, env_archcpu(env))) { | |
13603 | return false; | |
13604 | } | |
13605 | if (env->v7m.vpr) { | |
13606 | return false; | |
13607 | } | |
13608 | if (env->v7m.ltpsize < 4) { | |
13609 | return false; | |
13610 | } | |
13611 | return true; | |
13612 | } | |
13613 | ||
d4d7503a RH |
13614 | void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, |
13615 | target_ulong *cs_base, uint32_t *pflags) | |
13616 | { | |
3902bfc6 | 13617 | CPUARMTBFlags flags; |
d4d7503a | 13618 | |
0ee8b24a | 13619 | assert_hflags_rebuild_correctly(env); |
3902bfc6 | 13620 | flags = env->hflags; |
3d74e2e9 | 13621 | |
a729a46b | 13622 | if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { |
d4d7503a | 13623 | *pc = env->pc; |
d4d7503a | 13624 | if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { |
a729a46b | 13625 | DP_TBFLAG_A64(flags, BTYPE, env->btype); |
08f1434a | 13626 | } |
a9e01311 RH |
13627 | } else { |
13628 | *pc = env->regs[15]; | |
6e33ced5 RH |
13629 | |
13630 | if (arm_feature(env, ARM_FEATURE_M)) { | |
9550d1bd RH |
13631 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && |
13632 | FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) | |
13633 | != env->v7m.secure) { | |
a729a46b | 13634 | DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1); |
9550d1bd RH |
13635 | } |
13636 | ||
13637 | if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && | |
13638 | (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || | |
13639 | (env->v7m.secure && | |
13640 | !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { | |
13641 | /* | |
13642 | * ASPEN is set, but FPCA/SFPA indicate that there is no | |
13643 | * active FP context; we must create a new FP context before | |
13644 | * executing any FP insn. | |
13645 | */ | |
a729a46b | 13646 | DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1); |
9550d1bd RH |
13647 | } |
13648 | ||
13649 | bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; | |
13650 | if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { | |
a729a46b | 13651 | DP_TBFLAG_M32(flags, LSPACT, 1); |
9550d1bd | 13652 | } |
26702213 PM |
13653 | |
13654 | if (mve_no_pred(env)) { | |
13655 | DP_TBFLAG_M32(flags, MVE_NO_PRED, 1); | |
13656 | } | |
6e33ced5 | 13657 | } else { |
bbad7c62 RH |
13658 | /* |
13659 | * Note that XSCALE_CPAR shares bits with VECSTRIDE. | |
13660 | * Note that VECLEN+VECSTRIDE are RES0 for M-profile. | |
13661 | */ | |
13662 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
a729a46b | 13663 | DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); |
bbad7c62 | 13664 | } else { |
a729a46b RH |
13665 | DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); |
13666 | DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); | |
bbad7c62 | 13667 | } |
0a54d68e | 13668 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { |
a729a46b | 13669 | DP_TBFLAG_A32(flags, VFPEN, 1); |
0a54d68e | 13670 | } |
6e33ced5 RH |
13671 | } |
13672 | ||
a729a46b RH |
13673 | DP_TBFLAG_AM32(flags, THUMB, env->thumb); |
13674 | DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits); | |
d4d7503a | 13675 | } |
a9e01311 | 13676 | |
60e12c37 RH |
13677 | /* |
13678 | * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine | |
a9e01311 RH |
13679 | * states defined in the ARM ARM for software singlestep: |
13680 | * SS_ACTIVE PSTATE.SS State | |
13681 | * 0 x Inactive (the TB flag for SS is always 0) | |
13682 | * 1 0 Active-pending | |
13683 | * 1 1 Active-not-pending | |
ae6eb1e9 | 13684 | * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. |
a9e01311 | 13685 | */ |
a729a46b RH |
13686 | if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { |
13687 | DP_TBFLAG_ANY(flags, PSTATE__SS, 1); | |
a9e01311 | 13688 | } |
a9e01311 | 13689 | |
3902bfc6 | 13690 | *pflags = flags.flags; |
a378206a | 13691 | *cs_base = flags.flags2; |
a9e01311 | 13692 | } |
0ab5953b RH |
13693 | |
13694 | #ifdef TARGET_AARCH64 | |
13695 | /* | |
13696 | * The manual says that when SVE is enabled and VQ is widened the | |
13697 | * implementation is allowed to zero the previously inaccessible | |
13698 | * portion of the registers. The corollary to that is that when | |
13699 | * SVE is enabled and VQ is narrowed we are also allowed to zero | |
13700 | * the now inaccessible portion of the registers. | |
13701 | * | |
13702 | * The intent of this is that no predicate bit beyond VQ is ever set. | |
13703 | * Which means that some operations on predicate registers themselves | |
13704 | * may operate on full uint64_t or even unrolled across the maximum | |
13705 | * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally | |
13706 | * may well be cheaper than conditionals to restrict the operation | |
13707 | * to the relevant portion of a uint16_t[16]. | |
13708 | */ | |
13709 | void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) | |
13710 | { | |
13711 | int i, j; | |
13712 | uint64_t pmask; | |
13713 | ||
13714 | assert(vq >= 1 && vq <= ARM_MAX_VQ); | |
2fc0cc0e | 13715 | assert(vq <= env_archcpu(env)->sve_max_vq); |
0ab5953b RH |
13716 | |
13717 | /* Zap the high bits of the zregs. */ | |
13718 | for (i = 0; i < 32; i++) { | |
13719 | memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)); | |
13720 | } | |
13721 | ||
13722 | /* Zap the high bits of the pregs and ffr. */ | |
13723 | pmask = 0; | |
13724 | if (vq & 3) { | |
13725 | pmask = ~(-1ULL << (16 * (vq & 3))); | |
13726 | } | |
13727 | for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) { | |
13728 | for (i = 0; i < 17; ++i) { | |
13729 | env->vfp.pregs[i].p[j] &= pmask; | |
13730 | } | |
13731 | pmask = 0; | |
13732 | } | |
13733 | } | |
13734 | ||
13735 | /* | |
13736 | * Notice a change in SVE vector size when changing EL. | |
13737 | */ | |
9a05f7b6 RH |
13738 | void aarch64_sve_change_el(CPUARMState *env, int old_el, |
13739 | int new_el, bool el0_a64) | |
0ab5953b | 13740 | { |
2fc0cc0e | 13741 | ARMCPU *cpu = env_archcpu(env); |
0ab5953b | 13742 | int old_len, new_len; |
9a05f7b6 | 13743 | bool old_a64, new_a64; |
0ab5953b RH |
13744 | |
13745 | /* Nothing to do if no SVE. */ | |
cd208a1c | 13746 | if (!cpu_isar_feature(aa64_sve, cpu)) { |
0ab5953b RH |
13747 | return; |
13748 | } | |
13749 | ||
13750 | /* Nothing to do if FP is disabled in either EL. */ | |
13751 | if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) { | |
13752 | return; | |
13753 | } | |
13754 | ||
13755 | /* | |
13756 | * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped | |
13757 | * at ELx, or not available because the EL is in AArch32 state, then | |
13758 | * for all purposes other than a direct read, the ZCR_ELx.LEN field | |
13759 | * has an effective value of 0". | |
13760 | * | |
13761 | * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0). | |
13762 | * If we ignore aa32 state, we would fail to see the vq4->vq0 transition | |
13763 | * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that | |
13764 | * we already have the correct register contents when encountering the | |
13765 | * vq0->vq0 transition between EL0->EL1. | |
13766 | */ | |
9a05f7b6 RH |
13767 | old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; |
13768 | old_len = (old_a64 && !sve_exception_el(env, old_el) | |
0ab5953b | 13769 | ? sve_zcr_len_for_el(env, old_el) : 0); |
9a05f7b6 RH |
13770 | new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; |
13771 | new_len = (new_a64 && !sve_exception_el(env, new_el) | |
0ab5953b RH |
13772 | ? sve_zcr_len_for_el(env, new_el) : 0); |
13773 | ||
13774 | /* When changing vector length, clear inaccessible state. */ | |
13775 | if (new_len < old_len) { | |
13776 | aarch64_sve_narrow_vq(env, new_len + 1); | |
13777 | } | |
13778 | } | |
13779 | #endif |