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Commit | Line | Data |
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ed3baad1 PMD |
1 | /* |
2 | * ARM generic helpers. | |
3 | * | |
4 | * This code is licensed under the GNU GPL v2 or later. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0-or-later | |
7 | */ | |
db725815 | 8 | |
74c21bd0 | 9 | #include "qemu/osdep.h" |
63159601 | 10 | #include "qemu/units.h" |
181962fd | 11 | #include "target/arm/idau.h" |
194cbc49 | 12 | #include "trace.h" |
b5ff1b31 | 13 | #include "cpu.h" |
ccd38087 | 14 | #include "internals.h" |
022c62cb | 15 | #include "exec/gdbstub.h" |
2ef6175a | 16 | #include "exec/helper-proto.h" |
1de7afc9 | 17 | #include "qemu/host-utils.h" |
db725815 | 18 | #include "qemu/main-loop.h" |
1de7afc9 | 19 | #include "qemu/bitops.h" |
eb0ecd5a | 20 | #include "qemu/crc32c.h" |
0442428a | 21 | #include "qemu/qemu-print.h" |
63c91552 | 22 | #include "exec/exec-all.h" |
eb0ecd5a | 23 | #include <zlib.h> /* For crc32 */ |
64552b6b | 24 | #include "hw/irq.h" |
f1672e6f | 25 | #include "hw/semihosting/semihost.h" |
b2e23725 | 26 | #include "sysemu/cpus.h" |
f3a9b694 | 27 | #include "sysemu/kvm.h" |
2a609df8 | 28 | #include "sysemu/tcg.h" |
9d2b5a58 | 29 | #include "qemu/range.h" |
7f7b4e7a | 30 | #include "qapi/qapi-commands-machine-target.h" |
de390645 RH |
31 | #include "qapi/error.h" |
32 | #include "qemu/guest-random.h" | |
91f78c58 PMD |
33 | #ifdef CONFIG_TCG |
34 | #include "arm_ldst.h" | |
7aab5a8c | 35 | #include "exec/cpu_ldst.h" |
91f78c58 | 36 | #endif |
0b03bdfc | 37 | |
352c98e5 LV |
38 | #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ |
39 | ||
4a501606 | 40 | #ifndef CONFIG_USER_ONLY |
7c2cb42b | 41 | |
37785977 | 42 | static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
03ae85f8 | 43 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
37785977 | 44 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, |
da909b2c | 45 | target_ulong *page_size_ptr, |
5b2d261d | 46 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); |
4a501606 PM |
47 | #endif |
48 | ||
affdb64d PM |
49 | static void switch_mode(CPUARMState *env, int mode); |
50 | ||
0ecb72a5 | 51 | static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 | 52 | { |
a6627f5f RH |
53 | ARMCPU *cpu = env_archcpu(env); |
54 | int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; | |
56aebc89 PB |
55 | |
56 | /* VFP data registers are always little-endian. */ | |
56aebc89 | 57 | if (reg < nregs) { |
9a2b5256 | 58 | stq_le_p(buf, *aa32_vfp_dreg(env, reg)); |
56aebc89 PB |
59 | return 8; |
60 | } | |
61 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
62 | /* Aliases for Q regs. */ | |
63 | nregs += 16; | |
64 | if (reg < nregs) { | |
9a2b5256 RH |
65 | uint64_t *q = aa32_vfp_qreg(env, reg - 32); |
66 | stq_le_p(buf, q[0]); | |
67 | stq_le_p(buf + 8, q[1]); | |
56aebc89 PB |
68 | return 16; |
69 | } | |
70 | } | |
71 | switch (reg - nregs) { | |
72 | case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; | |
b0a909a4 | 73 | case 1: stl_p(buf, vfp_get_fpscr(env)); return 4; |
56aebc89 PB |
74 | case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; |
75 | } | |
76 | return 0; | |
77 | } | |
78 | ||
0ecb72a5 | 79 | static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 | 80 | { |
a6627f5f RH |
81 | ARMCPU *cpu = env_archcpu(env); |
82 | int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; | |
56aebc89 | 83 | |
56aebc89 | 84 | if (reg < nregs) { |
9a2b5256 | 85 | *aa32_vfp_dreg(env, reg) = ldq_le_p(buf); |
56aebc89 PB |
86 | return 8; |
87 | } | |
88 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
89 | nregs += 16; | |
90 | if (reg < nregs) { | |
9a2b5256 RH |
91 | uint64_t *q = aa32_vfp_qreg(env, reg - 32); |
92 | q[0] = ldq_le_p(buf); | |
93 | q[1] = ldq_le_p(buf + 8); | |
56aebc89 PB |
94 | return 16; |
95 | } | |
96 | } | |
97 | switch (reg - nregs) { | |
98 | case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; | |
b0a909a4 | 99 | case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4; |
71b3c3de | 100 | case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
56aebc89 PB |
101 | } |
102 | return 0; | |
103 | } | |
104 | ||
6a669427 PM |
105 | static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
106 | { | |
107 | switch (reg) { | |
108 | case 0 ... 31: | |
109 | /* 128 bit FP register */ | |
9a2b5256 RH |
110 | { |
111 | uint64_t *q = aa64_vfp_qreg(env, reg); | |
112 | stq_le_p(buf, q[0]); | |
113 | stq_le_p(buf + 8, q[1]); | |
114 | return 16; | |
115 | } | |
6a669427 PM |
116 | case 32: |
117 | /* FPSR */ | |
118 | stl_p(buf, vfp_get_fpsr(env)); | |
119 | return 4; | |
120 | case 33: | |
121 | /* FPCR */ | |
122 | stl_p(buf, vfp_get_fpcr(env)); | |
123 | return 4; | |
124 | default: | |
125 | return 0; | |
126 | } | |
127 | } | |
128 | ||
129 | static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) | |
130 | { | |
131 | switch (reg) { | |
132 | case 0 ... 31: | |
133 | /* 128 bit FP register */ | |
9a2b5256 RH |
134 | { |
135 | uint64_t *q = aa64_vfp_qreg(env, reg); | |
136 | q[0] = ldq_le_p(buf); | |
137 | q[1] = ldq_le_p(buf + 8); | |
138 | return 16; | |
139 | } | |
6a669427 PM |
140 | case 32: |
141 | /* FPSR */ | |
142 | vfp_set_fpsr(env, ldl_p(buf)); | |
143 | return 4; | |
144 | case 33: | |
145 | /* FPCR */ | |
146 | vfp_set_fpcr(env, ldl_p(buf)); | |
147 | return 4; | |
148 | default: | |
149 | return 0; | |
150 | } | |
151 | } | |
152 | ||
c4241c7d | 153 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) |
d4e6df63 | 154 | { |
375421cc | 155 | assert(ri->fieldoffset); |
67ed771d | 156 | if (cpreg_field_is_64bit(ri)) { |
c4241c7d | 157 | return CPREG_FIELD64(env, ri); |
22d9e1a9 | 158 | } else { |
c4241c7d | 159 | return CPREG_FIELD32(env, ri); |
22d9e1a9 | 160 | } |
d4e6df63 PM |
161 | } |
162 | ||
c4241c7d PM |
163 | static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
164 | uint64_t value) | |
d4e6df63 | 165 | { |
375421cc | 166 | assert(ri->fieldoffset); |
67ed771d | 167 | if (cpreg_field_is_64bit(ri)) { |
22d9e1a9 PM |
168 | CPREG_FIELD64(env, ri) = value; |
169 | } else { | |
170 | CPREG_FIELD32(env, ri) = value; | |
171 | } | |
d4e6df63 PM |
172 | } |
173 | ||
11f136ee FA |
174 | static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) |
175 | { | |
176 | return (char *)env + ri->fieldoffset; | |
177 | } | |
178 | ||
49a66191 | 179 | uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) |
721fae12 | 180 | { |
59a1c327 | 181 | /* Raw read of a coprocessor register (as needed for migration, etc). */ |
721fae12 | 182 | if (ri->type & ARM_CP_CONST) { |
59a1c327 | 183 | return ri->resetvalue; |
721fae12 | 184 | } else if (ri->raw_readfn) { |
59a1c327 | 185 | return ri->raw_readfn(env, ri); |
721fae12 | 186 | } else if (ri->readfn) { |
59a1c327 | 187 | return ri->readfn(env, ri); |
721fae12 | 188 | } else { |
59a1c327 | 189 | return raw_read(env, ri); |
721fae12 | 190 | } |
721fae12 PM |
191 | } |
192 | ||
59a1c327 | 193 | static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, |
7900e9f1 | 194 | uint64_t v) |
721fae12 PM |
195 | { |
196 | /* Raw write of a coprocessor register (as needed for migration, etc). | |
721fae12 PM |
197 | * Note that constant registers are treated as write-ignored; the |
198 | * caller should check for success by whether a readback gives the | |
199 | * value written. | |
200 | */ | |
201 | if (ri->type & ARM_CP_CONST) { | |
59a1c327 | 202 | return; |
721fae12 | 203 | } else if (ri->raw_writefn) { |
c4241c7d | 204 | ri->raw_writefn(env, ri, v); |
721fae12 | 205 | } else if (ri->writefn) { |
c4241c7d | 206 | ri->writefn(env, ri, v); |
721fae12 | 207 | } else { |
afb2530f | 208 | raw_write(env, ri, v); |
721fae12 | 209 | } |
721fae12 PM |
210 | } |
211 | ||
200bf5b7 AB |
212 | static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg) |
213 | { | |
2fc0cc0e | 214 | ARMCPU *cpu = env_archcpu(env); |
200bf5b7 AB |
215 | const ARMCPRegInfo *ri; |
216 | uint32_t key; | |
217 | ||
218 | key = cpu->dyn_xml.cpregs_keys[reg]; | |
219 | ri = get_arm_cp_reginfo(cpu->cp_regs, key); | |
220 | if (ri) { | |
221 | if (cpreg_field_is_64bit(ri)) { | |
222 | return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); | |
223 | } else { | |
224 | return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); | |
225 | } | |
226 | } | |
227 | return 0; | |
228 | } | |
229 | ||
230 | static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) | |
231 | { | |
232 | return 0; | |
233 | } | |
234 | ||
375421cc PM |
235 | static bool raw_accessors_invalid(const ARMCPRegInfo *ri) |
236 | { | |
237 | /* Return true if the regdef would cause an assertion if you called | |
238 | * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a | |
239 | * program bug for it not to have the NO_RAW flag). | |
240 | * NB that returning false here doesn't necessarily mean that calling | |
241 | * read/write_raw_cp_reg() is safe, because we can't distinguish "has | |
242 | * read/write access functions which are safe for raw use" from "has | |
243 | * read/write access functions which have side effects but has forgotten | |
244 | * to provide raw access functions". | |
245 | * The tests here line up with the conditions in read/write_raw_cp_reg() | |
246 | * and assertions in raw_read()/raw_write(). | |
247 | */ | |
248 | if ((ri->type & ARM_CP_CONST) || | |
249 | ri->fieldoffset || | |
250 | ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { | |
251 | return false; | |
252 | } | |
253 | return true; | |
254 | } | |
255 | ||
b698e4ee | 256 | bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync) |
721fae12 PM |
257 | { |
258 | /* Write the coprocessor state from cpu->env to the (index,value) list. */ | |
259 | int i; | |
260 | bool ok = true; | |
261 | ||
262 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
263 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
264 | const ARMCPRegInfo *ri; | |
b698e4ee | 265 | uint64_t newval; |
59a1c327 | 266 | |
60322b39 | 267 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
268 | if (!ri) { |
269 | ok = false; | |
270 | continue; | |
271 | } | |
7a0e58fa | 272 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
273 | continue; |
274 | } | |
b698e4ee PM |
275 | |
276 | newval = read_raw_cp_reg(&cpu->env, ri); | |
277 | if (kvm_sync) { | |
278 | /* | |
279 | * Only sync if the previous list->cpustate sync succeeded. | |
280 | * Rather than tracking the success/failure state for every | |
281 | * item in the list, we just recheck "does the raw write we must | |
282 | * have made in write_list_to_cpustate() read back OK" here. | |
283 | */ | |
284 | uint64_t oldval = cpu->cpreg_values[i]; | |
285 | ||
286 | if (oldval == newval) { | |
287 | continue; | |
288 | } | |
289 | ||
290 | write_raw_cp_reg(&cpu->env, ri, oldval); | |
291 | if (read_raw_cp_reg(&cpu->env, ri) != oldval) { | |
292 | continue; | |
293 | } | |
294 | ||
295 | write_raw_cp_reg(&cpu->env, ri, newval); | |
296 | } | |
297 | cpu->cpreg_values[i] = newval; | |
721fae12 PM |
298 | } |
299 | return ok; | |
300 | } | |
301 | ||
302 | bool write_list_to_cpustate(ARMCPU *cpu) | |
303 | { | |
304 | int i; | |
305 | bool ok = true; | |
306 | ||
307 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
308 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
309 | uint64_t v = cpu->cpreg_values[i]; | |
721fae12 PM |
310 | const ARMCPRegInfo *ri; |
311 | ||
60322b39 | 312 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
313 | if (!ri) { |
314 | ok = false; | |
315 | continue; | |
316 | } | |
7a0e58fa | 317 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
318 | continue; |
319 | } | |
320 | /* Write value and confirm it reads back as written | |
321 | * (to catch read-only registers and partially read-only | |
322 | * registers where the incoming migration value doesn't match) | |
323 | */ | |
59a1c327 PM |
324 | write_raw_cp_reg(&cpu->env, ri, v); |
325 | if (read_raw_cp_reg(&cpu->env, ri) != v) { | |
721fae12 PM |
326 | ok = false; |
327 | } | |
328 | } | |
329 | return ok; | |
330 | } | |
331 | ||
332 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | |
333 | { | |
334 | ARMCPU *cpu = opaque; | |
335 | uint64_t regidx; | |
336 | const ARMCPRegInfo *ri; | |
337 | ||
338 | regidx = *(uint32_t *)key; | |
60322b39 | 339 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 | 340 | |
7a0e58fa | 341 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
342 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); |
343 | /* The value array need not be initialized at this point */ | |
344 | cpu->cpreg_array_len++; | |
345 | } | |
346 | } | |
347 | ||
348 | static void count_cpreg(gpointer key, gpointer opaque) | |
349 | { | |
350 | ARMCPU *cpu = opaque; | |
351 | uint64_t regidx; | |
352 | const ARMCPRegInfo *ri; | |
353 | ||
354 | regidx = *(uint32_t *)key; | |
60322b39 | 355 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 | 356 | |
7a0e58fa | 357 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
358 | cpu->cpreg_array_len++; |
359 | } | |
360 | } | |
361 | ||
362 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | |
363 | { | |
cbf239b7 AR |
364 | uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); |
365 | uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); | |
721fae12 | 366 | |
cbf239b7 AR |
367 | if (aidx > bidx) { |
368 | return 1; | |
369 | } | |
370 | if (aidx < bidx) { | |
371 | return -1; | |
372 | } | |
373 | return 0; | |
721fae12 PM |
374 | } |
375 | ||
376 | void init_cpreg_list(ARMCPU *cpu) | |
377 | { | |
378 | /* Initialise the cpreg_tuples[] array based on the cp_regs hash. | |
379 | * Note that we require cpreg_tuples[] to be sorted by key ID. | |
380 | */ | |
57b6d95e | 381 | GList *keys; |
721fae12 PM |
382 | int arraylen; |
383 | ||
57b6d95e | 384 | keys = g_hash_table_get_keys(cpu->cp_regs); |
721fae12 PM |
385 | keys = g_list_sort(keys, cpreg_key_compare); |
386 | ||
387 | cpu->cpreg_array_len = 0; | |
388 | ||
389 | g_list_foreach(keys, count_cpreg, cpu); | |
390 | ||
391 | arraylen = cpu->cpreg_array_len; | |
392 | cpu->cpreg_indexes = g_new(uint64_t, arraylen); | |
393 | cpu->cpreg_values = g_new(uint64_t, arraylen); | |
394 | cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); | |
395 | cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); | |
396 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; | |
397 | cpu->cpreg_array_len = 0; | |
398 | ||
399 | g_list_foreach(keys, add_cpreg_to_list, cpu); | |
400 | ||
401 | assert(cpu->cpreg_array_len == arraylen); | |
402 | ||
403 | g_list_free(keys); | |
404 | } | |
405 | ||
68e9c2fe EI |
406 | /* |
407 | * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but | |
408 | * they are accessible when EL3 is using AArch64 regardless of EL3.NS. | |
409 | * | |
410 | * access_el3_aa32ns: Used to check AArch32 register views. | |
411 | * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views. | |
412 | */ | |
413 | static CPAccessResult access_el3_aa32ns(CPUARMState *env, | |
3f208fd7 PM |
414 | const ARMCPRegInfo *ri, |
415 | bool isread) | |
68e9c2fe EI |
416 | { |
417 | bool secure = arm_is_secure_below_el3(env); | |
418 | ||
419 | assert(!arm_el_is_aa64(env, 3)); | |
420 | if (secure) { | |
421 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
422 | } | |
423 | return CP_ACCESS_OK; | |
424 | } | |
425 | ||
426 | static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env, | |
3f208fd7 PM |
427 | const ARMCPRegInfo *ri, |
428 | bool isread) | |
68e9c2fe EI |
429 | { |
430 | if (!arm_el_is_aa64(env, 3)) { | |
3f208fd7 | 431 | return access_el3_aa32ns(env, ri, isread); |
68e9c2fe EI |
432 | } |
433 | return CP_ACCESS_OK; | |
434 | } | |
435 | ||
5513c3ab PM |
436 | /* Some secure-only AArch32 registers trap to EL3 if used from |
437 | * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). | |
438 | * Note that an access from Secure EL1 can only happen if EL3 is AArch64. | |
439 | * We assume that the .access field is set to PL1_RW. | |
440 | */ | |
441 | static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, | |
3f208fd7 PM |
442 | const ARMCPRegInfo *ri, |
443 | bool isread) | |
5513c3ab PM |
444 | { |
445 | if (arm_current_el(env) == 3) { | |
446 | return CP_ACCESS_OK; | |
447 | } | |
448 | if (arm_is_secure_below_el3(env)) { | |
449 | return CP_ACCESS_TRAP_EL3; | |
450 | } | |
451 | /* This will be EL1 NS and EL2 NS, which just UNDEF */ | |
452 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
453 | } | |
454 | ||
187f678d PM |
455 | /* Check for traps to "powerdown debug" registers, which are controlled |
456 | * by MDCR.TDOSA | |
457 | */ | |
458 | static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, | |
459 | bool isread) | |
460 | { | |
461 | int el = arm_current_el(env); | |
30ac6339 PM |
462 | bool mdcr_el2_tdosa = (env->cp15.mdcr_el2 & MDCR_TDOSA) || |
463 | (env->cp15.mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 464 | (arm_hcr_el2_eff(env) & HCR_TGE); |
187f678d | 465 | |
30ac6339 | 466 | if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) { |
187f678d PM |
467 | return CP_ACCESS_TRAP_EL2; |
468 | } | |
469 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { | |
470 | return CP_ACCESS_TRAP_EL3; | |
471 | } | |
472 | return CP_ACCESS_OK; | |
473 | } | |
474 | ||
91b0a238 PM |
475 | /* Check for traps to "debug ROM" registers, which are controlled |
476 | * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. | |
477 | */ | |
478 | static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, | |
479 | bool isread) | |
480 | { | |
481 | int el = arm_current_el(env); | |
30ac6339 PM |
482 | bool mdcr_el2_tdra = (env->cp15.mdcr_el2 & MDCR_TDRA) || |
483 | (env->cp15.mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 484 | (arm_hcr_el2_eff(env) & HCR_TGE); |
91b0a238 | 485 | |
30ac6339 | 486 | if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) { |
91b0a238 PM |
487 | return CP_ACCESS_TRAP_EL2; |
488 | } | |
489 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
490 | return CP_ACCESS_TRAP_EL3; | |
491 | } | |
492 | return CP_ACCESS_OK; | |
493 | } | |
494 | ||
d6c8cf81 PM |
495 | /* Check for traps to general debug registers, which are controlled |
496 | * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. | |
497 | */ | |
498 | static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, | |
499 | bool isread) | |
500 | { | |
501 | int el = arm_current_el(env); | |
30ac6339 PM |
502 | bool mdcr_el2_tda = (env->cp15.mdcr_el2 & MDCR_TDA) || |
503 | (env->cp15.mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 504 | (arm_hcr_el2_eff(env) & HCR_TGE); |
d6c8cf81 | 505 | |
30ac6339 | 506 | if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) { |
d6c8cf81 PM |
507 | return CP_ACCESS_TRAP_EL2; |
508 | } | |
509 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
510 | return CP_ACCESS_TRAP_EL3; | |
511 | } | |
512 | return CP_ACCESS_OK; | |
513 | } | |
514 | ||
1fce1ba9 PM |
515 | /* Check for traps to performance monitor registers, which are controlled |
516 | * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. | |
517 | */ | |
518 | static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, | |
519 | bool isread) | |
520 | { | |
521 | int el = arm_current_el(env); | |
522 | ||
523 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) | |
524 | && !arm_is_secure_below_el3(env)) { | |
525 | return CP_ACCESS_TRAP_EL2; | |
526 | } | |
527 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
528 | return CP_ACCESS_TRAP_EL3; | |
529 | } | |
530 | return CP_ACCESS_OK; | |
531 | } | |
532 | ||
84929218 RH |
533 | /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ |
534 | static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, | |
535 | bool isread) | |
536 | { | |
537 | if (arm_current_el(env) == 1) { | |
538 | uint64_t trap = isread ? HCR_TRVM : HCR_TVM; | |
539 | if (arm_hcr_el2_eff(env) & trap) { | |
540 | return CP_ACCESS_TRAP_EL2; | |
541 | } | |
542 | } | |
543 | return CP_ACCESS_OK; | |
544 | } | |
545 | ||
1803d271 RH |
546 | /* Check for traps from EL1 due to HCR_EL2.TSW. */ |
547 | static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri, | |
548 | bool isread) | |
549 | { | |
550 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) { | |
551 | return CP_ACCESS_TRAP_EL2; | |
552 | } | |
553 | return CP_ACCESS_OK; | |
554 | } | |
555 | ||
99602377 RH |
556 | /* Check for traps from EL1 due to HCR_EL2.TACR. */ |
557 | static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri, | |
558 | bool isread) | |
559 | { | |
560 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TACR)) { | |
561 | return CP_ACCESS_TRAP_EL2; | |
562 | } | |
563 | return CP_ACCESS_OK; | |
564 | } | |
565 | ||
c4241c7d | 566 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
c983fe6c | 567 | { |
2fc0cc0e | 568 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 569 | |
8d5c773e | 570 | raw_write(env, ri, value); |
d10eb08f | 571 | tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ |
c983fe6c PM |
572 | } |
573 | ||
c4241c7d | 574 | static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
08de207b | 575 | { |
2fc0cc0e | 576 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 577 | |
8d5c773e | 578 | if (raw_read(env, ri) != value) { |
08de207b PM |
579 | /* Unlike real hardware the qemu TLB uses virtual addresses, |
580 | * not modified virtual addresses, so this causes a TLB flush. | |
581 | */ | |
d10eb08f | 582 | tlb_flush(CPU(cpu)); |
8d5c773e | 583 | raw_write(env, ri, value); |
08de207b | 584 | } |
08de207b | 585 | } |
c4241c7d PM |
586 | |
587 | static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
588 | uint64_t value) | |
08de207b | 589 | { |
2fc0cc0e | 590 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 591 | |
452a0955 | 592 | if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) |
014406b5 | 593 | && !extended_addresses_enabled(env)) { |
08de207b PM |
594 | /* For VMSA (when not using the LPAE long descriptor page table |
595 | * format) this register includes the ASID, so do a TLB flush. | |
596 | * For PMSA it is purely a process ID and no action is needed. | |
597 | */ | |
d10eb08f | 598 | tlb_flush(CPU(cpu)); |
08de207b | 599 | } |
8d5c773e | 600 | raw_write(env, ri, value); |
08de207b PM |
601 | } |
602 | ||
b4ab8ce9 PM |
603 | /* IS variants of TLB operations must affect all cores */ |
604 | static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
605 | uint64_t value) | |
606 | { | |
29a0af61 | 607 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
608 | |
609 | tlb_flush_all_cpus_synced(cs); | |
610 | } | |
611 | ||
612 | static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
613 | uint64_t value) | |
614 | { | |
29a0af61 | 615 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
616 | |
617 | tlb_flush_all_cpus_synced(cs); | |
618 | } | |
619 | ||
620 | static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
621 | uint64_t value) | |
622 | { | |
29a0af61 | 623 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
624 | |
625 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
626 | } | |
627 | ||
628 | static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
629 | uint64_t value) | |
630 | { | |
29a0af61 | 631 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
632 | |
633 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
634 | } | |
635 | ||
636 | /* | |
637 | * Non-IS variants of TLB operations are upgraded to | |
638 | * IS versions if we are at NS EL1 and HCR_EL2.FB is set to | |
639 | * force broadcast of these operations. | |
640 | */ | |
641 | static bool tlb_force_broadcast(CPUARMState *env) | |
642 | { | |
643 | return (env->cp15.hcr_el2 & HCR_FB) && | |
644 | arm_current_el(env) == 1 && arm_is_secure_below_el3(env); | |
645 | } | |
646 | ||
c4241c7d PM |
647 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
648 | uint64_t value) | |
d929823f PM |
649 | { |
650 | /* Invalidate all (TLBIALL) */ | |
527db2be | 651 | CPUState *cs = env_cpu(env); |
00c8cb0a | 652 | |
b4ab8ce9 | 653 | if (tlb_force_broadcast(env)) { |
527db2be RH |
654 | tlb_flush_all_cpus_synced(cs); |
655 | } else { | |
656 | tlb_flush(cs); | |
b4ab8ce9 | 657 | } |
d929823f PM |
658 | } |
659 | ||
c4241c7d PM |
660 | static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
661 | uint64_t value) | |
d929823f PM |
662 | { |
663 | /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ | |
527db2be | 664 | CPUState *cs = env_cpu(env); |
31b030d4 | 665 | |
527db2be | 666 | value &= TARGET_PAGE_MASK; |
b4ab8ce9 | 667 | if (tlb_force_broadcast(env)) { |
527db2be RH |
668 | tlb_flush_page_all_cpus_synced(cs, value); |
669 | } else { | |
670 | tlb_flush_page(cs, value); | |
b4ab8ce9 | 671 | } |
d929823f PM |
672 | } |
673 | ||
c4241c7d PM |
674 | static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
675 | uint64_t value) | |
d929823f PM |
676 | { |
677 | /* Invalidate by ASID (TLBIASID) */ | |
527db2be | 678 | CPUState *cs = env_cpu(env); |
00c8cb0a | 679 | |
b4ab8ce9 | 680 | if (tlb_force_broadcast(env)) { |
527db2be RH |
681 | tlb_flush_all_cpus_synced(cs); |
682 | } else { | |
683 | tlb_flush(cs); | |
b4ab8ce9 | 684 | } |
d929823f PM |
685 | } |
686 | ||
c4241c7d PM |
687 | static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
688 | uint64_t value) | |
d929823f PM |
689 | { |
690 | /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ | |
527db2be | 691 | CPUState *cs = env_cpu(env); |
31b030d4 | 692 | |
527db2be | 693 | value &= TARGET_PAGE_MASK; |
b4ab8ce9 | 694 | if (tlb_force_broadcast(env)) { |
527db2be RH |
695 | tlb_flush_page_all_cpus_synced(cs, value); |
696 | } else { | |
697 | tlb_flush_page(cs, value); | |
b4ab8ce9 | 698 | } |
fa439fc5 PM |
699 | } |
700 | ||
541ef8c2 SS |
701 | static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, |
702 | uint64_t value) | |
703 | { | |
29a0af61 | 704 | CPUState *cs = env_cpu(env); |
541ef8c2 | 705 | |
0336cbf8 | 706 | tlb_flush_by_mmuidx(cs, |
01b98b68 | 707 | ARMMMUIdxBit_E10_1 | |
452ef8cb | 708 | ARMMMUIdxBit_E10_1_PAN | |
01b98b68 | 709 | ARMMMUIdxBit_E10_0 | |
97fa9350 | 710 | ARMMMUIdxBit_Stage2); |
541ef8c2 SS |
711 | } |
712 | ||
713 | static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
714 | uint64_t value) | |
715 | { | |
29a0af61 | 716 | CPUState *cs = env_cpu(env); |
541ef8c2 | 717 | |
a67cf277 | 718 | tlb_flush_by_mmuidx_all_cpus_synced(cs, |
01b98b68 | 719 | ARMMMUIdxBit_E10_1 | |
452ef8cb | 720 | ARMMMUIdxBit_E10_1_PAN | |
01b98b68 | 721 | ARMMMUIdxBit_E10_0 | |
97fa9350 | 722 | ARMMMUIdxBit_Stage2); |
541ef8c2 SS |
723 | } |
724 | ||
725 | static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
726 | uint64_t value) | |
727 | { | |
728 | /* Invalidate by IPA. This has to invalidate any structures that | |
729 | * contain only stage 2 translation information, but does not need | |
730 | * to apply to structures that contain combined stage 1 and stage 2 | |
731 | * translation information. | |
732 | * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. | |
733 | */ | |
29a0af61 | 734 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
735 | uint64_t pageaddr; |
736 | ||
737 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
738 | return; | |
739 | } | |
740 | ||
741 | pageaddr = sextract64(value << 12, 0, 40); | |
742 | ||
97fa9350 | 743 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2); |
541ef8c2 SS |
744 | } |
745 | ||
746 | static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
747 | uint64_t value) | |
748 | { | |
29a0af61 | 749 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
750 | uint64_t pageaddr; |
751 | ||
752 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
753 | return; | |
754 | } | |
755 | ||
756 | pageaddr = sextract64(value << 12, 0, 40); | |
757 | ||
a67cf277 | 758 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
97fa9350 | 759 | ARMMMUIdxBit_Stage2); |
541ef8c2 SS |
760 | } |
761 | ||
762 | static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
763 | uint64_t value) | |
764 | { | |
29a0af61 | 765 | CPUState *cs = env_cpu(env); |
541ef8c2 | 766 | |
e013b741 | 767 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); |
541ef8c2 SS |
768 | } |
769 | ||
770 | static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
771 | uint64_t value) | |
772 | { | |
29a0af61 | 773 | CPUState *cs = env_cpu(env); |
541ef8c2 | 774 | |
e013b741 | 775 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); |
541ef8c2 SS |
776 | } |
777 | ||
778 | static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
779 | uint64_t value) | |
780 | { | |
29a0af61 | 781 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
782 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
783 | ||
e013b741 | 784 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); |
541ef8c2 SS |
785 | } |
786 | ||
787 | static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
788 | uint64_t value) | |
789 | { | |
29a0af61 | 790 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
791 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
792 | ||
a67cf277 | 793 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
e013b741 | 794 | ARMMMUIdxBit_E2); |
541ef8c2 SS |
795 | } |
796 | ||
e9aa6c21 | 797 | static const ARMCPRegInfo cp_reginfo[] = { |
54bf36ed FA |
798 | /* Define the secure and non-secure FCSE identifier CP registers |
799 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
800 | * the secure register to be properly reset and migrated. There is also no | |
801 | * v8 EL1 version of the register so the non-secure instance stands alone. | |
802 | */ | |
9c513e78 | 803 | { .name = "FCSEIDR", |
54bf36ed FA |
804 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
805 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, | |
806 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), | |
807 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, | |
9c513e78 | 808 | { .name = "FCSEIDR_S", |
54bf36ed FA |
809 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
810 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
811 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), | |
d4e6df63 | 812 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, |
54bf36ed FA |
813 | /* Define the secure and non-secure context identifier CP registers |
814 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
815 | * the secure register to be properly reset and migrated. In the | |
816 | * non-secure case, the 32-bit register will have reset and migration | |
817 | * disabled during registration as it is handled by the 64-bit instance. | |
818 | */ | |
819 | { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
014406b5 | 820 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
84929218 RH |
821 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
822 | .secure = ARM_CP_SECSTATE_NS, | |
54bf36ed FA |
823 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), |
824 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, | |
9c513e78 | 825 | { .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32, |
54bf36ed | 826 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
84929218 RH |
827 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
828 | .secure = ARM_CP_SECSTATE_S, | |
54bf36ed | 829 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), |
d4e6df63 | 830 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, |
9449fdf6 PM |
831 | REGINFO_SENTINEL |
832 | }; | |
833 | ||
834 | static const ARMCPRegInfo not_v8_cp_reginfo[] = { | |
835 | /* NB: Some of these registers exist in v8 but with more precise | |
836 | * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). | |
837 | */ | |
838 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
839 | { .name = "DACR", |
840 | .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, | |
84929218 | 841 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
0c17d68c FA |
842 | .writefn = dacr_write, .raw_writefn = raw_write, |
843 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
844 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a903c449 EI |
845 | /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. |
846 | * For v6 and v5, these mappings are overly broad. | |
4fdd17dd | 847 | */ |
a903c449 EI |
848 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0, |
849 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
850 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1, | |
851 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
852 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4, | |
853 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
854 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8, | |
4fdd17dd | 855 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, |
c4804214 PM |
856 | /* Cache maintenance ops; some of this space may be overridden later. */ |
857 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | |
858 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | |
859 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | |
e9aa6c21 PM |
860 | REGINFO_SENTINEL |
861 | }; | |
862 | ||
7d57f408 PM |
863 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
864 | /* Not all pre-v6 cores implemented this WFI, so this is slightly | |
865 | * over-broad. | |
866 | */ | |
867 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | |
868 | .access = PL1_W, .type = ARM_CP_WFI }, | |
869 | REGINFO_SENTINEL | |
870 | }; | |
871 | ||
872 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | |
873 | /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which | |
874 | * is UNPREDICTABLE; we choose to NOP as most implementations do). | |
875 | */ | |
876 | { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
877 | .access = PL1_W, .type = ARM_CP_WFI }, | |
34f90529 PM |
878 | /* L1 cache lockdown. Not architectural in v6 and earlier but in practice |
879 | * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and | |
880 | * OMAPCP will override this space. | |
881 | */ | |
882 | { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, | |
883 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), | |
884 | .resetvalue = 0 }, | |
885 | { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, | |
886 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), | |
887 | .resetvalue = 0 }, | |
776d4e5c PM |
888 | /* v6 doesn't have the cache ID registers but Linux reads them anyway */ |
889 | { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, | |
7a0e58fa | 890 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 891 | .resetvalue = 0 }, |
50300698 PM |
892 | /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; |
893 | * implementing it as RAZ means the "debug architecture version" bits | |
894 | * will read as a reserved value, which should cause Linux to not try | |
895 | * to use the debug hardware. | |
896 | */ | |
897 | { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
898 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
995939a6 PM |
899 | /* MMU TLB control. Note that the wildcarding means we cover not just |
900 | * the unified TLB ops but also the dside/iside/inner-shareable variants. | |
901 | */ | |
902 | { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, | |
903 | .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, | |
7a0e58fa | 904 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
905 | { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, |
906 | .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, | |
7a0e58fa | 907 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
908 | { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, |
909 | .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, | |
7a0e58fa | 910 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
911 | { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, |
912 | .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, | |
7a0e58fa | 913 | .type = ARM_CP_NO_RAW }, |
a903c449 EI |
914 | { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2, |
915 | .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, | |
916 | { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, | |
917 | .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, | |
7d57f408 PM |
918 | REGINFO_SENTINEL |
919 | }; | |
920 | ||
c4241c7d PM |
921 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
922 | uint64_t value) | |
2771db27 | 923 | { |
f0aff255 FA |
924 | uint32_t mask = 0; |
925 | ||
926 | /* In ARMv8 most bits of CPACR_EL1 are RES0. */ | |
927 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
928 | /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. | |
929 | * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. | |
930 | * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. | |
931 | */ | |
7fbc6a40 | 932 | if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { |
f0aff255 FA |
933 | /* VFP coprocessor: cp10 & cp11 [23:20] */ |
934 | mask |= (1 << 31) | (1 << 30) | (0xf << 20); | |
935 | ||
936 | if (!arm_feature(env, ARM_FEATURE_NEON)) { | |
937 | /* ASEDIS [31] bit is RAO/WI */ | |
938 | value |= (1 << 31); | |
939 | } | |
940 | ||
941 | /* VFPv3 and upwards with NEON implement 32 double precision | |
942 | * registers (D0-D31). | |
943 | */ | |
a6627f5f | 944 | if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { |
f0aff255 FA |
945 | /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ |
946 | value |= (1 << 30); | |
947 | } | |
948 | } | |
949 | value &= mask; | |
2771db27 | 950 | } |
fc1120a7 PM |
951 | |
952 | /* | |
953 | * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 | |
954 | * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. | |
955 | */ | |
956 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
957 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
958 | value &= ~(0xf << 20); | |
959 | value |= env->cp15.cpacr_el1 & (0xf << 20); | |
960 | } | |
961 | ||
7ebd5f2e | 962 | env->cp15.cpacr_el1 = value; |
2771db27 PM |
963 | } |
964 | ||
fc1120a7 PM |
965 | static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
966 | { | |
967 | /* | |
968 | * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 | |
969 | * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. | |
970 | */ | |
971 | uint64_t value = env->cp15.cpacr_el1; | |
972 | ||
973 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
974 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
975 | value &= ~(0xf << 20); | |
976 | } | |
977 | return value; | |
978 | } | |
979 | ||
980 | ||
5deac39c PM |
981 | static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
982 | { | |
983 | /* Call cpacr_write() so that we reset with the correct RAO bits set | |
984 | * for our CPU features. | |
985 | */ | |
986 | cpacr_write(env, ri, 0); | |
987 | } | |
988 | ||
3f208fd7 PM |
989 | static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
990 | bool isread) | |
c6f19164 GB |
991 | { |
992 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
993 | /* Check if CPACR accesses are to be trapped to EL2 */ | |
994 | if (arm_current_el(env) == 1 && | |
995 | (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) { | |
996 | return CP_ACCESS_TRAP_EL2; | |
997 | /* Check if CPACR accesses are to be trapped to EL3 */ | |
998 | } else if (arm_current_el(env) < 3 && | |
999 | (env->cp15.cptr_el[3] & CPTR_TCPAC)) { | |
1000 | return CP_ACCESS_TRAP_EL3; | |
1001 | } | |
1002 | } | |
1003 | ||
1004 | return CP_ACCESS_OK; | |
1005 | } | |
1006 | ||
3f208fd7 PM |
1007 | static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1008 | bool isread) | |
c6f19164 GB |
1009 | { |
1010 | /* Check if CPTR accesses are set to trap to EL3 */ | |
1011 | if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) { | |
1012 | return CP_ACCESS_TRAP_EL3; | |
1013 | } | |
1014 | ||
1015 | return CP_ACCESS_OK; | |
1016 | } | |
1017 | ||
7d57f408 PM |
1018 | static const ARMCPRegInfo v6_cp_reginfo[] = { |
1019 | /* prefetch by MVA in v6, NOP in v7 */ | |
1020 | { .name = "MVA_prefetch", | |
1021 | .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, | |
1022 | .access = PL1_W, .type = ARM_CP_NOP }, | |
6df99dec SS |
1023 | /* We need to break the TB after ISB to execute self-modifying code |
1024 | * correctly and also to take any pending interrupts immediately. | |
1025 | * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. | |
1026 | */ | |
7d57f408 | 1027 | { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, |
6df99dec | 1028 | .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, |
091fd17c | 1029 | { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
7d57f408 | 1030 | .access = PL0_W, .type = ARM_CP_NOP }, |
091fd17c | 1031 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
7d57f408 | 1032 | .access = PL0_W, .type = ARM_CP_NOP }, |
06d76f31 | 1033 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
84929218 | 1034 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
b848ce2b FA |
1035 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), |
1036 | offsetof(CPUARMState, cp15.ifar_ns) }, | |
06d76f31 PM |
1037 | .resetvalue = 0, }, |
1038 | /* Watchpoint Fault Address Register : should actually only be present | |
1039 | * for 1136, 1176, 11MPCore. | |
1040 | */ | |
1041 | { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1042 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, | |
34222fb8 | 1043 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, |
c6f19164 | 1044 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, |
7ebd5f2e | 1045 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), |
fc1120a7 | 1046 | .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read }, |
7d57f408 PM |
1047 | REGINFO_SENTINEL |
1048 | }; | |
1049 | ||
7ece99b1 AL |
1050 | /* Definitions for the PMU registers */ |
1051 | #define PMCRN_MASK 0xf800 | |
1052 | #define PMCRN_SHIFT 11 | |
f4efb4b2 | 1053 | #define PMCRLC 0x40 |
a1ed04dd PM |
1054 | #define PMCRDP 0x20 |
1055 | #define PMCRX 0x10 | |
7ece99b1 AL |
1056 | #define PMCRD 0x8 |
1057 | #define PMCRC 0x4 | |
5ecdd3e4 | 1058 | #define PMCRP 0x2 |
7ece99b1 | 1059 | #define PMCRE 0x1 |
62d96ff4 PM |
1060 | /* |
1061 | * Mask of PMCR bits writeable by guest (not including WO bits like C, P, | |
1062 | * which can be written as 1 to trigger behaviour but which stay RAZ). | |
1063 | */ | |
1064 | #define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) | |
7ece99b1 | 1065 | |
033614c4 AL |
1066 | #define PMXEVTYPER_P 0x80000000 |
1067 | #define PMXEVTYPER_U 0x40000000 | |
1068 | #define PMXEVTYPER_NSK 0x20000000 | |
1069 | #define PMXEVTYPER_NSU 0x10000000 | |
1070 | #define PMXEVTYPER_NSH 0x08000000 | |
1071 | #define PMXEVTYPER_M 0x04000000 | |
1072 | #define PMXEVTYPER_MT 0x02000000 | |
1073 | #define PMXEVTYPER_EVTCOUNT 0x0000ffff | |
1074 | #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \ | |
1075 | PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ | |
1076 | PMXEVTYPER_M | PMXEVTYPER_MT | \ | |
1077 | PMXEVTYPER_EVTCOUNT) | |
1078 | ||
4b8afa1f AL |
1079 | #define PMCCFILTR 0xf8000000 |
1080 | #define PMCCFILTR_M PMXEVTYPER_M | |
1081 | #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) | |
1082 | ||
7ece99b1 AL |
1083 | static inline uint32_t pmu_num_counters(CPUARMState *env) |
1084 | { | |
1085 | return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; | |
1086 | } | |
1087 | ||
1088 | /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ | |
1089 | static inline uint64_t pmu_counter_mask(CPUARMState *env) | |
1090 | { | |
1091 | return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); | |
1092 | } | |
1093 | ||
57a4a11b AL |
1094 | typedef struct pm_event { |
1095 | uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ | |
1096 | /* If the event is supported on this CPU (used to generate PMCEID[01]) */ | |
1097 | bool (*supported)(CPUARMState *); | |
1098 | /* | |
1099 | * Retrieve the current count of the underlying event. The programmed | |
1100 | * counters hold a difference from the return value from this function | |
1101 | */ | |
1102 | uint64_t (*get_count)(CPUARMState *); | |
4e7beb0c AL |
1103 | /* |
1104 | * Return how many nanoseconds it will take (at a minimum) for count events | |
1105 | * to occur. A negative value indicates the counter will never overflow, or | |
1106 | * that the counter has otherwise arranged for the overflow bit to be set | |
1107 | * and the PMU interrupt to be raised on overflow. | |
1108 | */ | |
1109 | int64_t (*ns_per_count)(uint64_t); | |
57a4a11b AL |
1110 | } pm_event; |
1111 | ||
b2e23725 AL |
1112 | static bool event_always_supported(CPUARMState *env) |
1113 | { | |
1114 | return true; | |
1115 | } | |
1116 | ||
0d4bfd7d AL |
1117 | static uint64_t swinc_get_count(CPUARMState *env) |
1118 | { | |
1119 | /* | |
1120 | * SW_INCR events are written directly to the pmevcntr's by writes to | |
1121 | * PMSWINC, so there is no underlying count maintained by the PMU itself | |
1122 | */ | |
1123 | return 0; | |
1124 | } | |
1125 | ||
4e7beb0c AL |
1126 | static int64_t swinc_ns_per(uint64_t ignored) |
1127 | { | |
1128 | return -1; | |
1129 | } | |
1130 | ||
b2e23725 AL |
1131 | /* |
1132 | * Return the underlying cycle count for the PMU cycle counters. If we're in | |
1133 | * usermode, simply return 0. | |
1134 | */ | |
1135 | static uint64_t cycles_get_count(CPUARMState *env) | |
1136 | { | |
1137 | #ifndef CONFIG_USER_ONLY | |
1138 | return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
1139 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); | |
1140 | #else | |
1141 | return cpu_get_host_ticks(); | |
1142 | #endif | |
1143 | } | |
1144 | ||
1145 | #ifndef CONFIG_USER_ONLY | |
4e7beb0c AL |
1146 | static int64_t cycles_ns_per(uint64_t cycles) |
1147 | { | |
1148 | return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles; | |
1149 | } | |
1150 | ||
b2e23725 AL |
1151 | static bool instructions_supported(CPUARMState *env) |
1152 | { | |
1153 | return use_icount == 1 /* Precise instruction counting */; | |
1154 | } | |
1155 | ||
1156 | static uint64_t instructions_get_count(CPUARMState *env) | |
1157 | { | |
1158 | return (uint64_t)cpu_get_icount_raw(); | |
1159 | } | |
4e7beb0c AL |
1160 | |
1161 | static int64_t instructions_ns_per(uint64_t icount) | |
1162 | { | |
1163 | return cpu_icount_to_ns((int64_t)icount); | |
1164 | } | |
b2e23725 AL |
1165 | #endif |
1166 | ||
0727f63b PM |
1167 | static bool pmu_8_1_events_supported(CPUARMState *env) |
1168 | { | |
1169 | /* For events which are supported in any v8.1 PMU */ | |
1170 | return cpu_isar_feature(any_pmu_8_1, env_archcpu(env)); | |
1171 | } | |
1172 | ||
15dd1ebd PM |
1173 | static bool pmu_8_4_events_supported(CPUARMState *env) |
1174 | { | |
1175 | /* For events which are supported in any v8.1 PMU */ | |
1176 | return cpu_isar_feature(any_pmu_8_4, env_archcpu(env)); | |
1177 | } | |
1178 | ||
0727f63b PM |
1179 | static uint64_t zero_event_get_count(CPUARMState *env) |
1180 | { | |
1181 | /* For events which on QEMU never fire, so their count is always zero */ | |
1182 | return 0; | |
1183 | } | |
1184 | ||
1185 | static int64_t zero_event_ns_per(uint64_t cycles) | |
1186 | { | |
1187 | /* An event which never fires can never overflow */ | |
1188 | return -1; | |
1189 | } | |
1190 | ||
57a4a11b | 1191 | static const pm_event pm_events[] = { |
0d4bfd7d AL |
1192 | { .number = 0x000, /* SW_INCR */ |
1193 | .supported = event_always_supported, | |
1194 | .get_count = swinc_get_count, | |
4e7beb0c | 1195 | .ns_per_count = swinc_ns_per, |
0d4bfd7d | 1196 | }, |
b2e23725 AL |
1197 | #ifndef CONFIG_USER_ONLY |
1198 | { .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */ | |
1199 | .supported = instructions_supported, | |
1200 | .get_count = instructions_get_count, | |
4e7beb0c | 1201 | .ns_per_count = instructions_ns_per, |
b2e23725 AL |
1202 | }, |
1203 | { .number = 0x011, /* CPU_CYCLES, Cycle */ | |
1204 | .supported = event_always_supported, | |
1205 | .get_count = cycles_get_count, | |
4e7beb0c | 1206 | .ns_per_count = cycles_ns_per, |
0727f63b | 1207 | }, |
b2e23725 | 1208 | #endif |
0727f63b PM |
1209 | { .number = 0x023, /* STALL_FRONTEND */ |
1210 | .supported = pmu_8_1_events_supported, | |
1211 | .get_count = zero_event_get_count, | |
1212 | .ns_per_count = zero_event_ns_per, | |
1213 | }, | |
1214 | { .number = 0x024, /* STALL_BACKEND */ | |
1215 | .supported = pmu_8_1_events_supported, | |
1216 | .get_count = zero_event_get_count, | |
1217 | .ns_per_count = zero_event_ns_per, | |
1218 | }, | |
15dd1ebd PM |
1219 | { .number = 0x03c, /* STALL */ |
1220 | .supported = pmu_8_4_events_supported, | |
1221 | .get_count = zero_event_get_count, | |
1222 | .ns_per_count = zero_event_ns_per, | |
1223 | }, | |
57a4a11b AL |
1224 | }; |
1225 | ||
1226 | /* | |
1227 | * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of | |
1228 | * events (i.e. the statistical profiling extension), this implementation | |
1229 | * should first be updated to something sparse instead of the current | |
1230 | * supported_event_map[] array. | |
1231 | */ | |
15dd1ebd | 1232 | #define MAX_EVENT_ID 0x3c |
57a4a11b AL |
1233 | #define UNSUPPORTED_EVENT UINT16_MAX |
1234 | static uint16_t supported_event_map[MAX_EVENT_ID + 1]; | |
1235 | ||
1236 | /* | |
bf8d0969 AL |
1237 | * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map |
1238 | * of ARM event numbers to indices in our pm_events array. | |
57a4a11b AL |
1239 | * |
1240 | * Note: Events in the 0x40XX range are not currently supported. | |
1241 | */ | |
bf8d0969 | 1242 | void pmu_init(ARMCPU *cpu) |
57a4a11b | 1243 | { |
57a4a11b AL |
1244 | unsigned int i; |
1245 | ||
bf8d0969 AL |
1246 | /* |
1247 | * Empty supported_event_map and cpu->pmceid[01] before adding supported | |
1248 | * events to them | |
1249 | */ | |
57a4a11b AL |
1250 | for (i = 0; i < ARRAY_SIZE(supported_event_map); i++) { |
1251 | supported_event_map[i] = UNSUPPORTED_EVENT; | |
1252 | } | |
bf8d0969 AL |
1253 | cpu->pmceid0 = 0; |
1254 | cpu->pmceid1 = 0; | |
57a4a11b AL |
1255 | |
1256 | for (i = 0; i < ARRAY_SIZE(pm_events); i++) { | |
1257 | const pm_event *cnt = &pm_events[i]; | |
1258 | assert(cnt->number <= MAX_EVENT_ID); | |
1259 | /* We do not currently support events in the 0x40xx range */ | |
1260 | assert(cnt->number <= 0x3f); | |
1261 | ||
bf8d0969 | 1262 | if (cnt->supported(&cpu->env)) { |
57a4a11b | 1263 | supported_event_map[cnt->number] = i; |
67da43d6 | 1264 | uint64_t event_mask = 1ULL << (cnt->number & 0x1f); |
bf8d0969 AL |
1265 | if (cnt->number & 0x20) { |
1266 | cpu->pmceid1 |= event_mask; | |
1267 | } else { | |
1268 | cpu->pmceid0 |= event_mask; | |
1269 | } | |
57a4a11b AL |
1270 | } |
1271 | } | |
57a4a11b AL |
1272 | } |
1273 | ||
5ecdd3e4 AL |
1274 | /* |
1275 | * Check at runtime whether a PMU event is supported for the current machine | |
1276 | */ | |
1277 | static bool event_supported(uint16_t number) | |
1278 | { | |
1279 | if (number > MAX_EVENT_ID) { | |
1280 | return false; | |
1281 | } | |
1282 | return supported_event_map[number] != UNSUPPORTED_EVENT; | |
1283 | } | |
1284 | ||
3f208fd7 PM |
1285 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1286 | bool isread) | |
200ac0ef | 1287 | { |
3b163b01 | 1288 | /* Performance monitor registers user accessibility is controlled |
1fce1ba9 PM |
1289 | * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable |
1290 | * trapping to EL2 or EL3 for other accesses. | |
200ac0ef | 1291 | */ |
1fce1ba9 PM |
1292 | int el = arm_current_el(env); |
1293 | ||
6ecd0b6b | 1294 | if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { |
fcd25206 | 1295 | return CP_ACCESS_TRAP; |
200ac0ef | 1296 | } |
1fce1ba9 PM |
1297 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) |
1298 | && !arm_is_secure_below_el3(env)) { | |
1299 | return CP_ACCESS_TRAP_EL2; | |
1300 | } | |
1301 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
1302 | return CP_ACCESS_TRAP_EL3; | |
1303 | } | |
1304 | ||
fcd25206 | 1305 | return CP_ACCESS_OK; |
200ac0ef PM |
1306 | } |
1307 | ||
6ecd0b6b AB |
1308 | static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, |
1309 | const ARMCPRegInfo *ri, | |
1310 | bool isread) | |
1311 | { | |
1312 | /* ER: event counter read trap control */ | |
1313 | if (arm_feature(env, ARM_FEATURE_V8) | |
1314 | && arm_current_el(env) == 0 | |
1315 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 | |
1316 | && isread) { | |
1317 | return CP_ACCESS_OK; | |
1318 | } | |
1319 | ||
1320 | return pmreg_access(env, ri, isread); | |
1321 | } | |
1322 | ||
1323 | static CPAccessResult pmreg_access_swinc(CPUARMState *env, | |
1324 | const ARMCPRegInfo *ri, | |
1325 | bool isread) | |
1326 | { | |
1327 | /* SW: software increment write trap control */ | |
1328 | if (arm_feature(env, ARM_FEATURE_V8) | |
1329 | && arm_current_el(env) == 0 | |
1330 | && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 | |
1331 | && !isread) { | |
1332 | return CP_ACCESS_OK; | |
1333 | } | |
1334 | ||
1335 | return pmreg_access(env, ri, isread); | |
1336 | } | |
1337 | ||
6ecd0b6b AB |
1338 | static CPAccessResult pmreg_access_selr(CPUARMState *env, |
1339 | const ARMCPRegInfo *ri, | |
1340 | bool isread) | |
1341 | { | |
1342 | /* ER: event counter read trap control */ | |
1343 | if (arm_feature(env, ARM_FEATURE_V8) | |
1344 | && arm_current_el(env) == 0 | |
1345 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { | |
1346 | return CP_ACCESS_OK; | |
1347 | } | |
1348 | ||
1349 | return pmreg_access(env, ri, isread); | |
1350 | } | |
1351 | ||
1352 | static CPAccessResult pmreg_access_ccntr(CPUARMState *env, | |
1353 | const ARMCPRegInfo *ri, | |
1354 | bool isread) | |
1355 | { | |
1356 | /* CR: cycle counter read trap control */ | |
1357 | if (arm_feature(env, ARM_FEATURE_V8) | |
1358 | && arm_current_el(env) == 0 | |
1359 | && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 | |
1360 | && isread) { | |
1361 | return CP_ACCESS_OK; | |
1362 | } | |
1363 | ||
1364 | return pmreg_access(env, ri, isread); | |
1365 | } | |
1366 | ||
033614c4 AL |
1367 | /* Returns true if the counter (pass 31 for PMCCNTR) should count events using |
1368 | * the current EL, security state, and register configuration. | |
1369 | */ | |
1370 | static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) | |
87124fde | 1371 | { |
033614c4 AL |
1372 | uint64_t filter; |
1373 | bool e, p, u, nsk, nsu, nsh, m; | |
1374 | bool enabled, prohibited, filtered; | |
1375 | bool secure = arm_is_secure(env); | |
1376 | int el = arm_current_el(env); | |
1377 | uint8_t hpmn = env->cp15.mdcr_el2 & MDCR_HPMN; | |
87124fde | 1378 | |
cbbb3041 AJ |
1379 | if (!arm_feature(env, ARM_FEATURE_PMU)) { |
1380 | return false; | |
1381 | } | |
1382 | ||
033614c4 AL |
1383 | if (!arm_feature(env, ARM_FEATURE_EL2) || |
1384 | (counter < hpmn || counter == 31)) { | |
1385 | e = env->cp15.c9_pmcr & PMCRE; | |
1386 | } else { | |
1387 | e = env->cp15.mdcr_el2 & MDCR_HPME; | |
87124fde | 1388 | } |
033614c4 | 1389 | enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); |
87124fde | 1390 | |
033614c4 AL |
1391 | if (!secure) { |
1392 | if (el == 2 && (counter < hpmn || counter == 31)) { | |
1393 | prohibited = env->cp15.mdcr_el2 & MDCR_HPMD; | |
1394 | } else { | |
1395 | prohibited = false; | |
1396 | } | |
1397 | } else { | |
1398 | prohibited = arm_feature(env, ARM_FEATURE_EL3) && | |
1399 | (env->cp15.mdcr_el3 & MDCR_SPME); | |
1400 | } | |
1401 | ||
1402 | if (prohibited && counter == 31) { | |
1403 | prohibited = env->cp15.c9_pmcr & PMCRDP; | |
1404 | } | |
1405 | ||
5ecdd3e4 AL |
1406 | if (counter == 31) { |
1407 | filter = env->cp15.pmccfiltr_el0; | |
1408 | } else { | |
1409 | filter = env->cp15.c14_pmevtyper[counter]; | |
1410 | } | |
033614c4 AL |
1411 | |
1412 | p = filter & PMXEVTYPER_P; | |
1413 | u = filter & PMXEVTYPER_U; | |
1414 | nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); | |
1415 | nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); | |
1416 | nsh = arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); | |
1417 | m = arm_el_is_aa64(env, 1) && | |
1418 | arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); | |
1419 | ||
1420 | if (el == 0) { | |
1421 | filtered = secure ? u : u != nsu; | |
1422 | } else if (el == 1) { | |
1423 | filtered = secure ? p : p != nsk; | |
1424 | } else if (el == 2) { | |
1425 | filtered = !nsh; | |
1426 | } else { /* EL3 */ | |
1427 | filtered = m != p; | |
1428 | } | |
1429 | ||
5ecdd3e4 AL |
1430 | if (counter != 31) { |
1431 | /* | |
1432 | * If not checking PMCCNTR, ensure the counter is setup to an event we | |
1433 | * support | |
1434 | */ | |
1435 | uint16_t event = filter & PMXEVTYPER_EVTCOUNT; | |
1436 | if (!event_supported(event)) { | |
1437 | return false; | |
1438 | } | |
1439 | } | |
1440 | ||
033614c4 | 1441 | return enabled && !prohibited && !filtered; |
87124fde | 1442 | } |
033614c4 | 1443 | |
f4efb4b2 AL |
1444 | static void pmu_update_irq(CPUARMState *env) |
1445 | { | |
2fc0cc0e | 1446 | ARMCPU *cpu = env_archcpu(env); |
f4efb4b2 AL |
1447 | qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && |
1448 | (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); | |
1449 | } | |
1450 | ||
5d05b9d4 AL |
1451 | /* |
1452 | * Ensure c15_ccnt is the guest-visible count so that operations such as | |
1453 | * enabling/disabling the counter or filtering, modifying the count itself, | |
1454 | * etc. can be done logically. This is essentially a no-op if the counter is | |
1455 | * not enabled at the time of the call. | |
1456 | */ | |
f2b2f53f | 1457 | static void pmccntr_op_start(CPUARMState *env) |
ec7b4ce4 | 1458 | { |
b2e23725 | 1459 | uint64_t cycles = cycles_get_count(env); |
ec7b4ce4 | 1460 | |
033614c4 | 1461 | if (pmu_counter_enabled(env, 31)) { |
5d05b9d4 AL |
1462 | uint64_t eff_cycles = cycles; |
1463 | if (env->cp15.c9_pmcr & PMCRD) { | |
1464 | /* Increment once every 64 processor clock cycles */ | |
1465 | eff_cycles /= 64; | |
1466 | } | |
1467 | ||
f4efb4b2 AL |
1468 | uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta; |
1469 | ||
1470 | uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \ | |
1471 | 1ull << 63 : 1ull << 31; | |
1472 | if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { | |
1473 | env->cp15.c9_pmovsr |= (1 << 31); | |
1474 | pmu_update_irq(env); | |
1475 | } | |
1476 | ||
1477 | env->cp15.c15_ccnt = new_pmccntr; | |
ec7b4ce4 | 1478 | } |
5d05b9d4 AL |
1479 | env->cp15.c15_ccnt_delta = cycles; |
1480 | } | |
ec7b4ce4 | 1481 | |
5d05b9d4 AL |
1482 | /* |
1483 | * If PMCCNTR is enabled, recalculate the delta between the clock and the | |
1484 | * guest-visible count. A call to pmccntr_op_finish should follow every call to | |
1485 | * pmccntr_op_start. | |
1486 | */ | |
f2b2f53f | 1487 | static void pmccntr_op_finish(CPUARMState *env) |
5d05b9d4 | 1488 | { |
033614c4 | 1489 | if (pmu_counter_enabled(env, 31)) { |
4e7beb0c AL |
1490 | #ifndef CONFIG_USER_ONLY |
1491 | /* Calculate when the counter will next overflow */ | |
1492 | uint64_t remaining_cycles = -env->cp15.c15_ccnt; | |
1493 | if (!(env->cp15.c9_pmcr & PMCRLC)) { | |
1494 | remaining_cycles = (uint32_t)remaining_cycles; | |
1495 | } | |
1496 | int64_t overflow_in = cycles_ns_per(remaining_cycles); | |
1497 | ||
1498 | if (overflow_in > 0) { | |
1499 | int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
1500 | overflow_in; | |
2fc0cc0e | 1501 | ARMCPU *cpu = env_archcpu(env); |
4e7beb0c AL |
1502 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); |
1503 | } | |
1504 | #endif | |
5d05b9d4 | 1505 | |
4e7beb0c | 1506 | uint64_t prev_cycles = env->cp15.c15_ccnt_delta; |
5d05b9d4 AL |
1507 | if (env->cp15.c9_pmcr & PMCRD) { |
1508 | /* Increment once every 64 processor clock cycles */ | |
1509 | prev_cycles /= 64; | |
1510 | } | |
5d05b9d4 | 1511 | env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt; |
ec7b4ce4 AF |
1512 | } |
1513 | } | |
1514 | ||
5ecdd3e4 AL |
1515 | static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) |
1516 | { | |
1517 | ||
1518 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; | |
1519 | uint64_t count = 0; | |
1520 | if (event_supported(event)) { | |
1521 | uint16_t event_idx = supported_event_map[event]; | |
1522 | count = pm_events[event_idx].get_count(env); | |
1523 | } | |
1524 | ||
1525 | if (pmu_counter_enabled(env, counter)) { | |
f4efb4b2 AL |
1526 | uint32_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter]; |
1527 | ||
1528 | if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & INT32_MIN) { | |
1529 | env->cp15.c9_pmovsr |= (1 << counter); | |
1530 | pmu_update_irq(env); | |
1531 | } | |
1532 | env->cp15.c14_pmevcntr[counter] = new_pmevcntr; | |
5ecdd3e4 AL |
1533 | } |
1534 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1535 | } | |
1536 | ||
1537 | static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) | |
1538 | { | |
1539 | if (pmu_counter_enabled(env, counter)) { | |
4e7beb0c AL |
1540 | #ifndef CONFIG_USER_ONLY |
1541 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; | |
1542 | uint16_t event_idx = supported_event_map[event]; | |
1543 | uint64_t delta = UINT32_MAX - | |
1544 | (uint32_t)env->cp15.c14_pmevcntr[counter] + 1; | |
1545 | int64_t overflow_in = pm_events[event_idx].ns_per_count(delta); | |
1546 | ||
1547 | if (overflow_in > 0) { | |
1548 | int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
1549 | overflow_in; | |
2fc0cc0e | 1550 | ARMCPU *cpu = env_archcpu(env); |
4e7beb0c AL |
1551 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); |
1552 | } | |
1553 | #endif | |
1554 | ||
5ecdd3e4 AL |
1555 | env->cp15.c14_pmevcntr_delta[counter] -= |
1556 | env->cp15.c14_pmevcntr[counter]; | |
1557 | } | |
1558 | } | |
1559 | ||
5d05b9d4 AL |
1560 | void pmu_op_start(CPUARMState *env) |
1561 | { | |
5ecdd3e4 | 1562 | unsigned int i; |
5d05b9d4 | 1563 | pmccntr_op_start(env); |
5ecdd3e4 AL |
1564 | for (i = 0; i < pmu_num_counters(env); i++) { |
1565 | pmevcntr_op_start(env, i); | |
1566 | } | |
5d05b9d4 AL |
1567 | } |
1568 | ||
1569 | void pmu_op_finish(CPUARMState *env) | |
1570 | { | |
5ecdd3e4 | 1571 | unsigned int i; |
5d05b9d4 | 1572 | pmccntr_op_finish(env); |
5ecdd3e4 AL |
1573 | for (i = 0; i < pmu_num_counters(env); i++) { |
1574 | pmevcntr_op_finish(env, i); | |
1575 | } | |
5d05b9d4 AL |
1576 | } |
1577 | ||
033614c4 AL |
1578 | void pmu_pre_el_change(ARMCPU *cpu, void *ignored) |
1579 | { | |
1580 | pmu_op_start(&cpu->env); | |
1581 | } | |
1582 | ||
1583 | void pmu_post_el_change(ARMCPU *cpu, void *ignored) | |
1584 | { | |
1585 | pmu_op_finish(&cpu->env); | |
1586 | } | |
1587 | ||
4e7beb0c AL |
1588 | void arm_pmu_timer_cb(void *opaque) |
1589 | { | |
1590 | ARMCPU *cpu = opaque; | |
1591 | ||
1592 | /* | |
1593 | * Update all the counter values based on the current underlying counts, | |
1594 | * triggering interrupts to be raised, if necessary. pmu_op_finish() also | |
1595 | * has the effect of setting the cpu->pmu_timer to the next earliest time a | |
1596 | * counter may expire. | |
1597 | */ | |
1598 | pmu_op_start(&cpu->env); | |
1599 | pmu_op_finish(&cpu->env); | |
1600 | } | |
1601 | ||
c4241c7d PM |
1602 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1603 | uint64_t value) | |
200ac0ef | 1604 | { |
5d05b9d4 | 1605 | pmu_op_start(env); |
7c2cb42b AF |
1606 | |
1607 | if (value & PMCRC) { | |
1608 | /* The counter has been reset */ | |
1609 | env->cp15.c15_ccnt = 0; | |
1610 | } | |
1611 | ||
5ecdd3e4 AL |
1612 | if (value & PMCRP) { |
1613 | unsigned int i; | |
1614 | for (i = 0; i < pmu_num_counters(env); i++) { | |
1615 | env->cp15.c14_pmevcntr[i] = 0; | |
1616 | } | |
1617 | } | |
1618 | ||
62d96ff4 PM |
1619 | env->cp15.c9_pmcr &= ~PMCR_WRITEABLE_MASK; |
1620 | env->cp15.c9_pmcr |= (value & PMCR_WRITEABLE_MASK); | |
7c2cb42b | 1621 | |
5d05b9d4 | 1622 | pmu_op_finish(env); |
7c2cb42b AF |
1623 | } |
1624 | ||
0d4bfd7d AL |
1625 | static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1626 | uint64_t value) | |
1627 | { | |
1628 | unsigned int i; | |
1629 | for (i = 0; i < pmu_num_counters(env); i++) { | |
1630 | /* Increment a counter's count iff: */ | |
1631 | if ((value & (1 << i)) && /* counter's bit is set */ | |
1632 | /* counter is enabled and not filtered */ | |
1633 | pmu_counter_enabled(env, i) && | |
1634 | /* counter is SW_INCR */ | |
1635 | (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { | |
1636 | pmevcntr_op_start(env, i); | |
f4efb4b2 AL |
1637 | |
1638 | /* | |
1639 | * Detect if this write causes an overflow since we can't predict | |
1640 | * PMSWINC overflows like we can for other events | |
1641 | */ | |
1642 | uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; | |
1643 | ||
1644 | if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { | |
1645 | env->cp15.c9_pmovsr |= (1 << i); | |
1646 | pmu_update_irq(env); | |
1647 | } | |
1648 | ||
1649 | env->cp15.c14_pmevcntr[i] = new_pmswinc; | |
1650 | ||
0d4bfd7d AL |
1651 | pmevcntr_op_finish(env, i); |
1652 | } | |
1653 | } | |
1654 | } | |
1655 | ||
7c2cb42b AF |
1656 | static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1657 | { | |
5d05b9d4 AL |
1658 | uint64_t ret; |
1659 | pmccntr_op_start(env); | |
1660 | ret = env->cp15.c15_ccnt; | |
1661 | pmccntr_op_finish(env); | |
1662 | return ret; | |
7c2cb42b AF |
1663 | } |
1664 | ||
6b040780 WH |
1665 | static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1666 | uint64_t value) | |
1667 | { | |
1668 | /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and | |
1669 | * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the | |
1670 | * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are | |
1671 | * accessed. | |
1672 | */ | |
1673 | env->cp15.c9_pmselr = value & 0x1f; | |
1674 | } | |
1675 | ||
7c2cb42b AF |
1676 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1677 | uint64_t value) | |
1678 | { | |
5d05b9d4 AL |
1679 | pmccntr_op_start(env); |
1680 | env->cp15.c15_ccnt = value; | |
1681 | pmccntr_op_finish(env); | |
200ac0ef | 1682 | } |
421c7ebd PC |
1683 | |
1684 | static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1685 | uint64_t value) | |
1686 | { | |
1687 | uint64_t cur_val = pmccntr_read(env, NULL); | |
1688 | ||
1689 | pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); | |
1690 | } | |
1691 | ||
0614601c AF |
1692 | static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1693 | uint64_t value) | |
1694 | { | |
5d05b9d4 | 1695 | pmccntr_op_start(env); |
4b8afa1f AL |
1696 | env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0; |
1697 | pmccntr_op_finish(env); | |
1698 | } | |
1699 | ||
1700 | static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1701 | uint64_t value) | |
1702 | { | |
1703 | pmccntr_op_start(env); | |
1704 | /* M is not accessible from AArch32 */ | |
1705 | env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | | |
1706 | (value & PMCCFILTR); | |
5d05b9d4 | 1707 | pmccntr_op_finish(env); |
0614601c AF |
1708 | } |
1709 | ||
4b8afa1f AL |
1710 | static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri) |
1711 | { | |
1712 | /* M is not visible in AArch32 */ | |
1713 | return env->cp15.pmccfiltr_el0 & PMCCFILTR; | |
1714 | } | |
1715 | ||
c4241c7d | 1716 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1717 | uint64_t value) |
1718 | { | |
7ece99b1 | 1719 | value &= pmu_counter_mask(env); |
200ac0ef | 1720 | env->cp15.c9_pmcnten |= value; |
200ac0ef PM |
1721 | } |
1722 | ||
c4241c7d PM |
1723 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1724 | uint64_t value) | |
200ac0ef | 1725 | { |
7ece99b1 | 1726 | value &= pmu_counter_mask(env); |
200ac0ef | 1727 | env->cp15.c9_pmcnten &= ~value; |
200ac0ef PM |
1728 | } |
1729 | ||
c4241c7d PM |
1730 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1731 | uint64_t value) | |
200ac0ef | 1732 | { |
599b71e2 | 1733 | value &= pmu_counter_mask(env); |
200ac0ef | 1734 | env->cp15.c9_pmovsr &= ~value; |
f4efb4b2 | 1735 | pmu_update_irq(env); |
200ac0ef PM |
1736 | } |
1737 | ||
327dd510 AL |
1738 | static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1739 | uint64_t value) | |
1740 | { | |
1741 | value &= pmu_counter_mask(env); | |
1742 | env->cp15.c9_pmovsr |= value; | |
f4efb4b2 | 1743 | pmu_update_irq(env); |
327dd510 AL |
1744 | } |
1745 | ||
5ecdd3e4 AL |
1746 | static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1747 | uint64_t value, const uint8_t counter) | |
200ac0ef | 1748 | { |
5ecdd3e4 AL |
1749 | if (counter == 31) { |
1750 | pmccfiltr_write(env, ri, value); | |
1751 | } else if (counter < pmu_num_counters(env)) { | |
1752 | pmevcntr_op_start(env, counter); | |
1753 | ||
1754 | /* | |
1755 | * If this counter's event type is changing, store the current | |
1756 | * underlying count for the new type in c14_pmevcntr_delta[counter] so | |
1757 | * pmevcntr_op_finish has the correct baseline when it converts back to | |
1758 | * a delta. | |
1759 | */ | |
1760 | uint16_t old_event = env->cp15.c14_pmevtyper[counter] & | |
1761 | PMXEVTYPER_EVTCOUNT; | |
1762 | uint16_t new_event = value & PMXEVTYPER_EVTCOUNT; | |
1763 | if (old_event != new_event) { | |
1764 | uint64_t count = 0; | |
1765 | if (event_supported(new_event)) { | |
1766 | uint16_t event_idx = supported_event_map[new_event]; | |
1767 | count = pm_events[event_idx].get_count(env); | |
1768 | } | |
1769 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1770 | } | |
1771 | ||
1772 | env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK; | |
1773 | pmevcntr_op_finish(env, counter); | |
1774 | } | |
fdb86656 WH |
1775 | /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when |
1776 | * PMSELR value is equal to or greater than the number of implemented | |
1777 | * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. | |
1778 | */ | |
5ecdd3e4 AL |
1779 | } |
1780 | ||
1781 | static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1782 | const uint8_t counter) | |
1783 | { | |
1784 | if (counter == 31) { | |
1785 | return env->cp15.pmccfiltr_el0; | |
1786 | } else if (counter < pmu_num_counters(env)) { | |
1787 | return env->cp15.c14_pmevtyper[counter]; | |
1788 | } else { | |
1789 | /* | |
1790 | * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER | |
1791 | * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). | |
1792 | */ | |
1793 | return 0; | |
1794 | } | |
1795 | } | |
1796 | ||
1797 | static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, | |
1798 | uint64_t value) | |
1799 | { | |
1800 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1801 | pmevtyper_write(env, ri, value, counter); | |
1802 | } | |
1803 | ||
1804 | static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1805 | uint64_t value) | |
1806 | { | |
1807 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1808 | env->cp15.c14_pmevtyper[counter] = value; | |
1809 | ||
1810 | /* | |
1811 | * pmevtyper_rawwrite is called between a pair of pmu_op_start and | |
1812 | * pmu_op_finish calls when loading saved state for a migration. Because | |
1813 | * we're potentially updating the type of event here, the value written to | |
1814 | * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a | |
1815 | * different counter type. Therefore, we need to set this value to the | |
1816 | * current count for the counter type we're writing so that pmu_op_finish | |
1817 | * has the correct count for its calculation. | |
1818 | */ | |
1819 | uint16_t event = value & PMXEVTYPER_EVTCOUNT; | |
1820 | if (event_supported(event)) { | |
1821 | uint16_t event_idx = supported_event_map[event]; | |
1822 | env->cp15.c14_pmevcntr_delta[counter] = | |
1823 | pm_events[event_idx].get_count(env); | |
fdb86656 WH |
1824 | } |
1825 | } | |
1826 | ||
5ecdd3e4 AL |
1827 | static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) |
1828 | { | |
1829 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1830 | return pmevtyper_read(env, ri, counter); | |
1831 | } | |
1832 | ||
1833 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1834 | uint64_t value) | |
1835 | { | |
1836 | pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1837 | } | |
1838 | ||
fdb86656 WH |
1839 | static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1840 | { | |
5ecdd3e4 AL |
1841 | return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); |
1842 | } | |
1843 | ||
1844 | static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1845 | uint64_t value, uint8_t counter) | |
1846 | { | |
1847 | if (counter < pmu_num_counters(env)) { | |
1848 | pmevcntr_op_start(env, counter); | |
1849 | env->cp15.c14_pmevcntr[counter] = value; | |
1850 | pmevcntr_op_finish(env, counter); | |
1851 | } | |
1852 | /* | |
1853 | * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR | |
1854 | * are CONSTRAINED UNPREDICTABLE. | |
fdb86656 | 1855 | */ |
5ecdd3e4 AL |
1856 | } |
1857 | ||
1858 | static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1859 | uint8_t counter) | |
1860 | { | |
1861 | if (counter < pmu_num_counters(env)) { | |
1862 | uint64_t ret; | |
1863 | pmevcntr_op_start(env, counter); | |
1864 | ret = env->cp15.c14_pmevcntr[counter]; | |
1865 | pmevcntr_op_finish(env, counter); | |
1866 | return ret; | |
fdb86656 | 1867 | } else { |
5ecdd3e4 AL |
1868 | /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR |
1869 | * are CONSTRAINED UNPREDICTABLE. */ | |
fdb86656 WH |
1870 | return 0; |
1871 | } | |
200ac0ef PM |
1872 | } |
1873 | ||
5ecdd3e4 AL |
1874 | static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, |
1875 | uint64_t value) | |
1876 | { | |
1877 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1878 | pmevcntr_write(env, ri, value, counter); | |
1879 | } | |
1880 | ||
1881 | static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) | |
1882 | { | |
1883 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1884 | return pmevcntr_read(env, ri, counter); | |
1885 | } | |
1886 | ||
1887 | static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1888 | uint64_t value) | |
1889 | { | |
1890 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1891 | assert(counter < pmu_num_counters(env)); | |
1892 | env->cp15.c14_pmevcntr[counter] = value; | |
1893 | pmevcntr_write(env, ri, value, counter); | |
1894 | } | |
1895 | ||
1896 | static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri) | |
1897 | { | |
1898 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1899 | assert(counter < pmu_num_counters(env)); | |
1900 | return env->cp15.c14_pmevcntr[counter]; | |
1901 | } | |
1902 | ||
1903 | static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1904 | uint64_t value) | |
1905 | { | |
1906 | pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1907 | } | |
1908 | ||
1909 | static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1910 | { | |
1911 | return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); | |
1912 | } | |
1913 | ||
c4241c7d | 1914 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1915 | uint64_t value) |
1916 | { | |
6ecd0b6b AB |
1917 | if (arm_feature(env, ARM_FEATURE_V8)) { |
1918 | env->cp15.c9_pmuserenr = value & 0xf; | |
1919 | } else { | |
1920 | env->cp15.c9_pmuserenr = value & 1; | |
1921 | } | |
200ac0ef PM |
1922 | } |
1923 | ||
c4241c7d PM |
1924 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1925 | uint64_t value) | |
200ac0ef PM |
1926 | { |
1927 | /* We have no event counters so only the C bit can be changed */ | |
7ece99b1 | 1928 | value &= pmu_counter_mask(env); |
200ac0ef | 1929 | env->cp15.c9_pminten |= value; |
f4efb4b2 | 1930 | pmu_update_irq(env); |
200ac0ef PM |
1931 | } |
1932 | ||
c4241c7d PM |
1933 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1934 | uint64_t value) | |
200ac0ef | 1935 | { |
7ece99b1 | 1936 | value &= pmu_counter_mask(env); |
200ac0ef | 1937 | env->cp15.c9_pminten &= ~value; |
f4efb4b2 | 1938 | pmu_update_irq(env); |
200ac0ef PM |
1939 | } |
1940 | ||
c4241c7d PM |
1941 | static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1942 | uint64_t value) | |
8641136c | 1943 | { |
a505d7fe PM |
1944 | /* Note that even though the AArch64 view of this register has bits |
1945 | * [10:0] all RES0 we can only mask the bottom 5, to comply with the | |
1946 | * architectural requirements for bits which are RES0 only in some | |
1947 | * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 | |
1948 | * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) | |
1949 | */ | |
855ea66d | 1950 | raw_write(env, ri, value & ~0x1FULL); |
8641136c NR |
1951 | } |
1952 | ||
64e0e2de EI |
1953 | static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
1954 | { | |
ea22747c RH |
1955 | /* Begin with base v8.0 state. */ |
1956 | uint32_t valid_mask = 0x3fff; | |
2fc0cc0e | 1957 | ARMCPU *cpu = env_archcpu(env); |
ea22747c RH |
1958 | |
1959 | if (arm_el_is_aa64(env, 3)) { | |
1960 | value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ | |
1961 | valid_mask &= ~SCR_NET; | |
1962 | } else { | |
1963 | valid_mask &= ~(SCR_RW | SCR_ST); | |
1964 | } | |
64e0e2de EI |
1965 | |
1966 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | |
1967 | valid_mask &= ~SCR_HCE; | |
1968 | ||
1969 | /* On ARMv7, SMD (or SCD as it is called in v7) is only | |
1970 | * supported if EL2 exists. The bit is UNK/SBZP when | |
1971 | * EL2 is unavailable. In QEMU ARMv7, we force it to always zero | |
1972 | * when EL2 is unavailable. | |
4eb27640 | 1973 | * On ARMv8, this bit is always available. |
64e0e2de | 1974 | */ |
4eb27640 GB |
1975 | if (arm_feature(env, ARM_FEATURE_V7) && |
1976 | !arm_feature(env, ARM_FEATURE_V8)) { | |
64e0e2de EI |
1977 | valid_mask &= ~SCR_SMD; |
1978 | } | |
1979 | } | |
2d7137c1 RH |
1980 | if (cpu_isar_feature(aa64_lor, cpu)) { |
1981 | valid_mask |= SCR_TLOR; | |
1982 | } | |
ef682cdb RH |
1983 | if (cpu_isar_feature(aa64_pauth, cpu)) { |
1984 | valid_mask |= SCR_API | SCR_APK; | |
1985 | } | |
64e0e2de EI |
1986 | |
1987 | /* Clear all-context RES0 bits. */ | |
1988 | value &= valid_mask; | |
1989 | raw_write(env, ri, value); | |
1990 | } | |
1991 | ||
630fcd4d MZ |
1992 | static CPAccessResult access_aa64_tid2(CPUARMState *env, |
1993 | const ARMCPRegInfo *ri, | |
1994 | bool isread) | |
1995 | { | |
1996 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) { | |
1997 | return CP_ACCESS_TRAP_EL2; | |
1998 | } | |
1999 | ||
2000 | return CP_ACCESS_OK; | |
2001 | } | |
2002 | ||
c4241c7d | 2003 | static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
776d4e5c | 2004 | { |
2fc0cc0e | 2005 | ARMCPU *cpu = env_archcpu(env); |
b85a1fd6 FA |
2006 | |
2007 | /* Acquire the CSSELR index from the bank corresponding to the CCSIDR | |
2008 | * bank | |
2009 | */ | |
2010 | uint32_t index = A32_BANKED_REG_GET(env, csselr, | |
2011 | ri->secure & ARM_CP_SECSTATE_S); | |
2012 | ||
2013 | return cpu->ccsidr[index]; | |
776d4e5c PM |
2014 | } |
2015 | ||
c4241c7d PM |
2016 | static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2017 | uint64_t value) | |
776d4e5c | 2018 | { |
8d5c773e | 2019 | raw_write(env, ri, value & 0xf); |
776d4e5c PM |
2020 | } |
2021 | ||
1090b9c6 PM |
2022 | static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2023 | { | |
29a0af61 | 2024 | CPUState *cs = env_cpu(env); |
f7778444 | 2025 | uint64_t hcr_el2 = arm_hcr_el2_eff(env); |
1090b9c6 | 2026 | uint64_t ret = 0; |
7cf95aed MZ |
2027 | bool allow_virt = (arm_current_el(env) == 1 && |
2028 | (!arm_is_secure_below_el3(env) || | |
2029 | (env->cp15.scr_el3 & SCR_EEL2))); | |
1090b9c6 | 2030 | |
7cf95aed | 2031 | if (allow_virt && (hcr_el2 & HCR_IMO)) { |
636540e9 PM |
2032 | if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { |
2033 | ret |= CPSR_I; | |
2034 | } | |
2035 | } else { | |
2036 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { | |
2037 | ret |= CPSR_I; | |
2038 | } | |
1090b9c6 | 2039 | } |
636540e9 | 2040 | |
7cf95aed | 2041 | if (allow_virt && (hcr_el2 & HCR_FMO)) { |
636540e9 PM |
2042 | if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { |
2043 | ret |= CPSR_F; | |
2044 | } | |
2045 | } else { | |
2046 | if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { | |
2047 | ret |= CPSR_F; | |
2048 | } | |
1090b9c6 | 2049 | } |
636540e9 | 2050 | |
1090b9c6 PM |
2051 | /* External aborts are not possible in QEMU so A bit is always clear */ |
2052 | return ret; | |
2053 | } | |
2054 | ||
93fbc983 MZ |
2055 | static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInfo *ri, |
2056 | bool isread) | |
2057 | { | |
2058 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID1)) { | |
2059 | return CP_ACCESS_TRAP_EL2; | |
2060 | } | |
2061 | ||
2062 | return CP_ACCESS_OK; | |
2063 | } | |
2064 | ||
2065 | static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInfo *ri, | |
2066 | bool isread) | |
2067 | { | |
2068 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
2069 | return access_aa64_tid1(env, ri, isread); | |
2070 | } | |
2071 | ||
2072 | return CP_ACCESS_OK; | |
2073 | } | |
2074 | ||
e9aa6c21 | 2075 | static const ARMCPRegInfo v7_cp_reginfo[] = { |
7d57f408 PM |
2076 | /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ |
2077 | { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
2078 | .access = PL1_W, .type = ARM_CP_NOP }, | |
200ac0ef PM |
2079 | /* Performance monitors are implementation defined in v7, |
2080 | * but with an ARM recommended set of registers, which we | |
ac689a2e | 2081 | * follow. |
200ac0ef PM |
2082 | * |
2083 | * Performance registers fall into three categories: | |
2084 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) | |
2085 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) | |
2086 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) | |
2087 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW | |
2088 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. | |
2089 | */ | |
2090 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 2091 | .access = PL0_RW, .type = ARM_CP_ALIAS, |
8521466b | 2092 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), |
fcd25206 PM |
2093 | .writefn = pmcntenset_write, |
2094 | .accessfn = pmreg_access, | |
2095 | .raw_writefn = raw_write }, | |
8521466b AF |
2096 | { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, |
2097 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, | |
2098 | .access = PL0_RW, .accessfn = pmreg_access, | |
2099 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, | |
2100 | .writefn = pmcntenset_write, .raw_writefn = raw_write }, | |
200ac0ef | 2101 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
8521466b AF |
2102 | .access = PL0_RW, |
2103 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
2104 | .accessfn = pmreg_access, |
2105 | .writefn = pmcntenclr_write, | |
7a0e58fa | 2106 | .type = ARM_CP_ALIAS }, |
8521466b AF |
2107 | { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, |
2108 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, | |
2109 | .access = PL0_RW, .accessfn = pmreg_access, | |
7a0e58fa | 2110 | .type = ARM_CP_ALIAS, |
8521466b AF |
2111 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), |
2112 | .writefn = pmcntenclr_write }, | |
200ac0ef | 2113 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
f4efb4b2 | 2114 | .access = PL0_RW, .type = ARM_CP_IO, |
e4e91a21 | 2115 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
fcd25206 PM |
2116 | .accessfn = pmreg_access, |
2117 | .writefn = pmovsr_write, | |
2118 | .raw_writefn = raw_write }, | |
978364f1 AF |
2119 | { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, |
2120 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, | |
2121 | .access = PL0_RW, .accessfn = pmreg_access, | |
f4efb4b2 | 2122 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
978364f1 AF |
2123 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
2124 | .writefn = pmovsr_write, | |
2125 | .raw_writefn = raw_write }, | |
200ac0ef | 2126 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
f4efb4b2 AL |
2127 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
2128 | .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
0d4bfd7d AL |
2129 | .writefn = pmswinc_write }, |
2130 | { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64, | |
2131 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4, | |
f4efb4b2 AL |
2132 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
2133 | .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
0d4bfd7d | 2134 | .writefn = pmswinc_write }, |
6b040780 WH |
2135 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, |
2136 | .access = PL0_RW, .type = ARM_CP_ALIAS, | |
2137 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), | |
6ecd0b6b | 2138 | .accessfn = pmreg_access_selr, .writefn = pmselr_write, |
6b040780 WH |
2139 | .raw_writefn = raw_write}, |
2140 | { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, | |
2141 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, | |
6ecd0b6b | 2142 | .access = PL0_RW, .accessfn = pmreg_access_selr, |
6b040780 WH |
2143 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), |
2144 | .writefn = pmselr_write, .raw_writefn = raw_write, }, | |
200ac0ef | 2145 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
169c8938 | 2146 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO, |
421c7ebd | 2147 | .readfn = pmccntr_read, .writefn = pmccntr_write32, |
6ecd0b6b | 2148 | .accessfn = pmreg_access_ccntr }, |
8521466b AF |
2149 | { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, |
2150 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, | |
6ecd0b6b | 2151 | .access = PL0_RW, .accessfn = pmreg_access_ccntr, |
8521466b | 2152 | .type = ARM_CP_IO, |
980ebe87 AL |
2153 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt), |
2154 | .readfn = pmccntr_read, .writefn = pmccntr_write, | |
2155 | .raw_readfn = raw_read, .raw_writefn = raw_write, }, | |
4b8afa1f AL |
2156 | { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7, |
2157 | .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32, | |
2158 | .access = PL0_RW, .accessfn = pmreg_access, | |
2159 | .type = ARM_CP_ALIAS | ARM_CP_IO, | |
2160 | .resetvalue = 0, }, | |
8521466b AF |
2161 | { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, |
2162 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, | |
980ebe87 | 2163 | .writefn = pmccfiltr_write, .raw_writefn = raw_write, |
8521466b AF |
2164 | .access = PL0_RW, .accessfn = pmreg_access, |
2165 | .type = ARM_CP_IO, | |
2166 | .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), | |
2167 | .resetvalue = 0, }, | |
200ac0ef | 2168 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
5ecdd3e4 AL |
2169 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
2170 | .accessfn = pmreg_access, | |
fdb86656 WH |
2171 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
2172 | { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, | |
2173 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, | |
5ecdd3e4 AL |
2174 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
2175 | .accessfn = pmreg_access, | |
fdb86656 | 2176 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
200ac0ef | 2177 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
5ecdd3e4 AL |
2178 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
2179 | .accessfn = pmreg_access_xevcntr, | |
2180 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, | |
2181 | { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64, | |
2182 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2, | |
2183 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
2184 | .accessfn = pmreg_access_xevcntr, | |
2185 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, | |
200ac0ef | 2186 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
1fce1ba9 | 2187 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, |
e4e91a21 | 2188 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr), |
200ac0ef | 2189 | .resetvalue = 0, |
d4e6df63 | 2190 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
8a83ffc2 AF |
2191 | { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, |
2192 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, | |
1fce1ba9 | 2193 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, |
8a83ffc2 AF |
2194 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), |
2195 | .resetvalue = 0, | |
2196 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, | |
200ac0ef | 2197 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
1fce1ba9 | 2198 | .access = PL1_RW, .accessfn = access_tpm, |
b7d793ad | 2199 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
e6ec5457 | 2200 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), |
200ac0ef | 2201 | .resetvalue = 0, |
d4e6df63 | 2202 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
e6ec5457 WH |
2203 | { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, |
2204 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, | |
2205 | .access = PL1_RW, .accessfn = access_tpm, | |
2206 | .type = ARM_CP_IO, | |
2207 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
2208 | .writefn = pmintenset_write, .raw_writefn = raw_write, | |
2209 | .resetvalue = 0x0 }, | |
200ac0ef | 2210 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
fc5f6856 AL |
2211 | .access = PL1_RW, .accessfn = access_tpm, |
2212 | .type = ARM_CP_ALIAS | ARM_CP_IO, | |
200ac0ef | 2213 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
b061a82b | 2214 | .writefn = pmintenclr_write, }, |
978364f1 AF |
2215 | { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, |
2216 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, | |
fc5f6856 AL |
2217 | .access = PL1_RW, .accessfn = access_tpm, |
2218 | .type = ARM_CP_ALIAS | ARM_CP_IO, | |
978364f1 AF |
2219 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
2220 | .writefn = pmintenclr_write }, | |
7da845b0 PM |
2221 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, |
2222 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | |
630fcd4d MZ |
2223 | .access = PL1_R, |
2224 | .accessfn = access_aa64_tid2, | |
2225 | .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, | |
7da845b0 PM |
2226 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, |
2227 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | |
630fcd4d MZ |
2228 | .access = PL1_RW, |
2229 | .accessfn = access_aa64_tid2, | |
2230 | .writefn = csselr_write, .resetvalue = 0, | |
b85a1fd6 FA |
2231 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), |
2232 | offsetof(CPUARMState, cp15.csselr_ns) } }, | |
776d4e5c PM |
2233 | /* Auxiliary ID register: this actually has an IMPDEF value but for now |
2234 | * just RAZ for all cores: | |
2235 | */ | |
0ff644a7 PM |
2236 | { .name = "AIDR", .state = ARM_CP_STATE_BOTH, |
2237 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, | |
93fbc983 MZ |
2238 | .access = PL1_R, .type = ARM_CP_CONST, |
2239 | .accessfn = access_aa64_tid1, | |
2240 | .resetvalue = 0 }, | |
f32cdad5 PM |
2241 | /* Auxiliary fault status registers: these also are IMPDEF, and we |
2242 | * choose to RAZ/WI for all cores. | |
2243 | */ | |
2244 | { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, | |
2245 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, | |
84929218 RH |
2246 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
2247 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
f32cdad5 PM |
2248 | { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, |
2249 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, | |
84929218 RH |
2250 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
2251 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b0fe2427 PM |
2252 | /* MAIR can just read-as-written because we don't implement caches |
2253 | * and so don't need to care about memory attributes. | |
2254 | */ | |
2255 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | |
2256 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | |
84929218 RH |
2257 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
2258 | .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), | |
b0fe2427 | 2259 | .resetvalue = 0 }, |
4cfb8ad8 PM |
2260 | { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, |
2261 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, | |
2262 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), | |
2263 | .resetvalue = 0 }, | |
b0fe2427 PM |
2264 | /* For non-long-descriptor page tables these are PRRR and NMRR; |
2265 | * regardless they still act as reads-as-written for QEMU. | |
b0fe2427 | 2266 | */ |
1281f8e3 | 2267 | /* MAIR0/1 are defined separately from their 64-bit counterpart which |
be693c87 GB |
2268 | * allows them to assign the correct fieldoffset based on the endianness |
2269 | * handled in the field definitions. | |
2270 | */ | |
a903c449 | 2271 | { .name = "MAIR0", .state = ARM_CP_STATE_AA32, |
84929218 RH |
2272 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, |
2273 | .access = PL1_RW, .accessfn = access_tvm_trvm, | |
be693c87 GB |
2274 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), |
2275 | offsetof(CPUARMState, cp15.mair0_ns) }, | |
b0fe2427 | 2276 | .resetfn = arm_cp_reset_ignore }, |
a903c449 | 2277 | { .name = "MAIR1", .state = ARM_CP_STATE_AA32, |
84929218 RH |
2278 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, |
2279 | .access = PL1_RW, .accessfn = access_tvm_trvm, | |
be693c87 GB |
2280 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), |
2281 | offsetof(CPUARMState, cp15.mair1_ns) }, | |
b0fe2427 | 2282 | .resetfn = arm_cp_reset_ignore }, |
1090b9c6 PM |
2283 | { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, |
2284 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, | |
7a0e58fa | 2285 | .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, |
995939a6 PM |
2286 | /* 32 bit ITLB invalidates */ |
2287 | { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, | |
7a0e58fa | 2288 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 2289 | { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, |
7a0e58fa | 2290 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 2291 | { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, |
7a0e58fa | 2292 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 PM |
2293 | /* 32 bit DTLB invalidates */ |
2294 | { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, | |
7a0e58fa | 2295 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 2296 | { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, |
7a0e58fa | 2297 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 2298 | { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, |
7a0e58fa | 2299 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 PM |
2300 | /* 32 bit TLB invalidates */ |
2301 | { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | |
7a0e58fa | 2302 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 2303 | { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
7a0e58fa | 2304 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 2305 | { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
7a0e58fa | 2306 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 | 2307 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
7a0e58fa | 2308 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, |
995939a6 PM |
2309 | REGINFO_SENTINEL |
2310 | }; | |
2311 | ||
2312 | static const ARMCPRegInfo v7mp_cp_reginfo[] = { | |
2313 | /* 32 bit TLB invalidates, Inner Shareable */ | |
2314 | { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | |
7a0e58fa | 2315 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write }, |
995939a6 | 2316 | { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
7a0e58fa | 2317 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, |
995939a6 | 2318 | { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
7a0e58fa | 2319 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 2320 | .writefn = tlbiasid_is_write }, |
995939a6 | 2321 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
7a0e58fa | 2322 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 2323 | .writefn = tlbimvaa_is_write }, |
e9aa6c21 PM |
2324 | REGINFO_SENTINEL |
2325 | }; | |
2326 | ||
327dd510 AL |
2327 | static const ARMCPRegInfo pmovsset_cp_reginfo[] = { |
2328 | /* PMOVSSET is not implemented in v7 before v7ve */ | |
2329 | { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3, | |
2330 | .access = PL0_RW, .accessfn = pmreg_access, | |
f4efb4b2 | 2331 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
327dd510 AL |
2332 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
2333 | .writefn = pmovsset_write, | |
2334 | .raw_writefn = raw_write }, | |
2335 | { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64, | |
2336 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3, | |
2337 | .access = PL0_RW, .accessfn = pmreg_access, | |
f4efb4b2 | 2338 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
327dd510 AL |
2339 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
2340 | .writefn = pmovsset_write, | |
2341 | .raw_writefn = raw_write }, | |
2342 | REGINFO_SENTINEL | |
2343 | }; | |
2344 | ||
c4241c7d PM |
2345 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2346 | uint64_t value) | |
c326b979 PM |
2347 | { |
2348 | value &= 1; | |
2349 | env->teecr = value; | |
c326b979 PM |
2350 | } |
2351 | ||
3f208fd7 PM |
2352 | static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2353 | bool isread) | |
c326b979 | 2354 | { |
dcbff19b | 2355 | if (arm_current_el(env) == 0 && (env->teecr & 1)) { |
92611c00 | 2356 | return CP_ACCESS_TRAP; |
c326b979 | 2357 | } |
92611c00 | 2358 | return CP_ACCESS_OK; |
c326b979 PM |
2359 | } |
2360 | ||
2361 | static const ARMCPRegInfo t2ee_cp_reginfo[] = { | |
2362 | { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, | |
2363 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), | |
2364 | .resetvalue = 0, | |
2365 | .writefn = teecr_write }, | |
2366 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, | |
2367 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | |
92611c00 | 2368 | .accessfn = teehbr_access, .resetvalue = 0 }, |
c326b979 PM |
2369 | REGINFO_SENTINEL |
2370 | }; | |
2371 | ||
4d31c596 | 2372 | static const ARMCPRegInfo v6k_cp_reginfo[] = { |
e4fe830b PM |
2373 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, |
2374 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | |
2375 | .access = PL0_RW, | |
54bf36ed | 2376 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, |
4d31c596 PM |
2377 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
2378 | .access = PL0_RW, | |
54bf36ed FA |
2379 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), |
2380 | offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, | |
e4fe830b PM |
2381 | .resetfn = arm_cp_reset_ignore }, |
2382 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | |
2383 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | |
2384 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
2385 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), |
2386 | .resetvalue = 0}, | |
4d31c596 PM |
2387 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
2388 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
2389 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), |
2390 | offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, | |
e4fe830b | 2391 | .resetfn = arm_cp_reset_ignore }, |
54bf36ed | 2392 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, |
e4fe830b | 2393 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, |
4d31c596 | 2394 | .access = PL1_RW, |
54bf36ed FA |
2395 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, |
2396 | { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, | |
2397 | .access = PL1_RW, | |
2398 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), | |
2399 | offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, | |
2400 | .resetvalue = 0 }, | |
4d31c596 PM |
2401 | REGINFO_SENTINEL |
2402 | }; | |
2403 | ||
55d284af PM |
2404 | #ifndef CONFIG_USER_ONLY |
2405 | ||
3f208fd7 PM |
2406 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2407 | bool isread) | |
00108f2d | 2408 | { |
75502672 PM |
2409 | /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. |
2410 | * Writable only at the highest implemented exception level. | |
2411 | */ | |
2412 | int el = arm_current_el(env); | |
5bc84371 RH |
2413 | uint64_t hcr; |
2414 | uint32_t cntkctl; | |
75502672 PM |
2415 | |
2416 | switch (el) { | |
2417 | case 0: | |
5bc84371 RH |
2418 | hcr = arm_hcr_el2_eff(env); |
2419 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2420 | cntkctl = env->cp15.cnthctl_el2; | |
2421 | } else { | |
2422 | cntkctl = env->cp15.c14_cntkctl; | |
2423 | } | |
2424 | if (!extract32(cntkctl, 0, 2)) { | |
75502672 PM |
2425 | return CP_ACCESS_TRAP; |
2426 | } | |
2427 | break; | |
2428 | case 1: | |
2429 | if (!isread && ri->state == ARM_CP_STATE_AA32 && | |
2430 | arm_is_secure_below_el3(env)) { | |
2431 | /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ | |
2432 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2433 | } | |
2434 | break; | |
2435 | case 2: | |
2436 | case 3: | |
2437 | break; | |
00108f2d | 2438 | } |
75502672 PM |
2439 | |
2440 | if (!isread && el < arm_highest_el(env)) { | |
2441 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2442 | } | |
2443 | ||
00108f2d PM |
2444 | return CP_ACCESS_OK; |
2445 | } | |
2446 | ||
3f208fd7 PM |
2447 | static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, |
2448 | bool isread) | |
00108f2d | 2449 | { |
0b6440af EI |
2450 | unsigned int cur_el = arm_current_el(env); |
2451 | bool secure = arm_is_secure(env); | |
5bc84371 | 2452 | uint64_t hcr = arm_hcr_el2_eff(env); |
0b6440af | 2453 | |
5bc84371 RH |
2454 | switch (cur_el) { |
2455 | case 0: | |
2456 | /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */ | |
2457 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2458 | return (extract32(env->cp15.cnthctl_el2, timeridx, 1) | |
2459 | ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); | |
2460 | } | |
0b6440af | 2461 | |
5bc84371 RH |
2462 | /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */ |
2463 | if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) { | |
2464 | return CP_ACCESS_TRAP; | |
2465 | } | |
2466 | ||
2467 | /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */ | |
2468 | if (hcr & HCR_E2H) { | |
2469 | if (timeridx == GTIMER_PHYS && | |
2470 | !extract32(env->cp15.cnthctl_el2, 10, 1)) { | |
2471 | return CP_ACCESS_TRAP_EL2; | |
2472 | } | |
2473 | } else { | |
2474 | /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */ | |
2475 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
2476 | timeridx == GTIMER_PHYS && !secure && | |
2477 | !extract32(env->cp15.cnthctl_el2, 1, 1)) { | |
2478 | return CP_ACCESS_TRAP_EL2; | |
2479 | } | |
2480 | } | |
2481 | break; | |
2482 | ||
2483 | case 1: | |
2484 | /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */ | |
2485 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
2486 | timeridx == GTIMER_PHYS && !secure && | |
2487 | (hcr & HCR_E2H | |
2488 | ? !extract32(env->cp15.cnthctl_el2, 10, 1) | |
2489 | : !extract32(env->cp15.cnthctl_el2, 0, 1))) { | |
2490 | return CP_ACCESS_TRAP_EL2; | |
2491 | } | |
2492 | break; | |
0b6440af | 2493 | } |
00108f2d PM |
2494 | return CP_ACCESS_OK; |
2495 | } | |
2496 | ||
3f208fd7 PM |
2497 | static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, |
2498 | bool isread) | |
00108f2d | 2499 | { |
0b6440af EI |
2500 | unsigned int cur_el = arm_current_el(env); |
2501 | bool secure = arm_is_secure(env); | |
5bc84371 | 2502 | uint64_t hcr = arm_hcr_el2_eff(env); |
0b6440af | 2503 | |
5bc84371 RH |
2504 | switch (cur_el) { |
2505 | case 0: | |
2506 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2507 | /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */ | |
2508 | return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1) | |
2509 | ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); | |
2510 | } | |
0b6440af | 2511 | |
5bc84371 RH |
2512 | /* |
2513 | * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from | |
2514 | * EL0 if EL0[PV]TEN is zero. | |
2515 | */ | |
2516 | if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { | |
2517 | return CP_ACCESS_TRAP; | |
2518 | } | |
2519 | /* fall through */ | |
2520 | ||
2521 | case 1: | |
2522 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
2523 | timeridx == GTIMER_PHYS && !secure) { | |
2524 | if (hcr & HCR_E2H) { | |
2525 | /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */ | |
2526 | if (!extract32(env->cp15.cnthctl_el2, 11, 1)) { | |
2527 | return CP_ACCESS_TRAP_EL2; | |
2528 | } | |
2529 | } else { | |
2530 | /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */ | |
2531 | if (!extract32(env->cp15.cnthctl_el2, 1, 1)) { | |
2532 | return CP_ACCESS_TRAP_EL2; | |
2533 | } | |
2534 | } | |
2535 | } | |
2536 | break; | |
0b6440af | 2537 | } |
00108f2d PM |
2538 | return CP_ACCESS_OK; |
2539 | } | |
2540 | ||
2541 | static CPAccessResult gt_pct_access(CPUARMState *env, | |
3f208fd7 PM |
2542 | const ARMCPRegInfo *ri, |
2543 | bool isread) | |
00108f2d | 2544 | { |
3f208fd7 | 2545 | return gt_counter_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2546 | } |
2547 | ||
2548 | static CPAccessResult gt_vct_access(CPUARMState *env, | |
3f208fd7 PM |
2549 | const ARMCPRegInfo *ri, |
2550 | bool isread) | |
00108f2d | 2551 | { |
3f208fd7 | 2552 | return gt_counter_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2553 | } |
2554 | ||
3f208fd7 PM |
2555 | static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2556 | bool isread) | |
00108f2d | 2557 | { |
3f208fd7 | 2558 | return gt_timer_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2559 | } |
2560 | ||
3f208fd7 PM |
2561 | static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2562 | bool isread) | |
00108f2d | 2563 | { |
3f208fd7 | 2564 | return gt_timer_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2565 | } |
2566 | ||
b4d3978c | 2567 | static CPAccessResult gt_stimer_access(CPUARMState *env, |
3f208fd7 PM |
2568 | const ARMCPRegInfo *ri, |
2569 | bool isread) | |
b4d3978c PM |
2570 | { |
2571 | /* The AArch64 register view of the secure physical timer is | |
2572 | * always accessible from EL3, and configurably accessible from | |
2573 | * Secure EL1. | |
2574 | */ | |
2575 | switch (arm_current_el(env)) { | |
2576 | case 1: | |
2577 | if (!arm_is_secure(env)) { | |
2578 | return CP_ACCESS_TRAP; | |
2579 | } | |
2580 | if (!(env->cp15.scr_el3 & SCR_ST)) { | |
2581 | return CP_ACCESS_TRAP_EL3; | |
2582 | } | |
2583 | return CP_ACCESS_OK; | |
2584 | case 0: | |
2585 | case 2: | |
2586 | return CP_ACCESS_TRAP; | |
2587 | case 3: | |
2588 | return CP_ACCESS_OK; | |
2589 | default: | |
2590 | g_assert_not_reached(); | |
2591 | } | |
2592 | } | |
2593 | ||
55d284af PM |
2594 | static uint64_t gt_get_countervalue(CPUARMState *env) |
2595 | { | |
7def8754 AJ |
2596 | ARMCPU *cpu = env_archcpu(env); |
2597 | ||
2598 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu); | |
55d284af PM |
2599 | } |
2600 | ||
2601 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) | |
2602 | { | |
2603 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; | |
2604 | ||
2605 | if (gt->ctl & 1) { | |
2606 | /* Timer enabled: calculate and set current ISTATUS, irq, and | |
2607 | * reset timer to when ISTATUS next has to change | |
2608 | */ | |
edac4d8a EI |
2609 | uint64_t offset = timeridx == GTIMER_VIRT ? |
2610 | cpu->env.cp15.cntvoff_el2 : 0; | |
55d284af PM |
2611 | uint64_t count = gt_get_countervalue(&cpu->env); |
2612 | /* Note that this must be unsigned 64 bit arithmetic: */ | |
edac4d8a | 2613 | int istatus = count - offset >= gt->cval; |
55d284af | 2614 | uint64_t nexttick; |
194cbc49 | 2615 | int irqstate; |
55d284af PM |
2616 | |
2617 | gt->ctl = deposit32(gt->ctl, 2, 1, istatus); | |
194cbc49 PM |
2618 | |
2619 | irqstate = (istatus && !(gt->ctl & 2)); | |
2620 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
2621 | ||
55d284af PM |
2622 | if (istatus) { |
2623 | /* Next transition is when count rolls back over to zero */ | |
2624 | nexttick = UINT64_MAX; | |
2625 | } else { | |
2626 | /* Next transition is when we hit cval */ | |
edac4d8a | 2627 | nexttick = gt->cval + offset; |
55d284af PM |
2628 | } |
2629 | /* Note that the desired next expiry time might be beyond the | |
2630 | * signed-64-bit range of a QEMUTimer -- in this case we just | |
2631 | * set the timer for as far in the future as possible. When the | |
2632 | * timer expires we will reset the timer for any remaining period. | |
2633 | */ | |
7def8754 | 2634 | if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { |
4a0245b6 AJ |
2635 | timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX); |
2636 | } else { | |
2637 | timer_mod(cpu->gt_timer[timeridx], nexttick); | |
55d284af | 2638 | } |
194cbc49 | 2639 | trace_arm_gt_recalc(timeridx, irqstate, nexttick); |
55d284af PM |
2640 | } else { |
2641 | /* Timer disabled: ISTATUS and timer output always clear */ | |
2642 | gt->ctl &= ~4; | |
2643 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); | |
bc72ad67 | 2644 | timer_del(cpu->gt_timer[timeridx]); |
194cbc49 | 2645 | trace_arm_gt_recalc_disabled(timeridx); |
55d284af PM |
2646 | } |
2647 | } | |
2648 | ||
0e3eca4c EI |
2649 | static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, |
2650 | int timeridx) | |
55d284af | 2651 | { |
2fc0cc0e | 2652 | ARMCPU *cpu = env_archcpu(env); |
55d284af | 2653 | |
bc72ad67 | 2654 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
2655 | } |
2656 | ||
c4241c7d | 2657 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
55d284af | 2658 | { |
c4241c7d | 2659 | return gt_get_countervalue(env); |
55d284af PM |
2660 | } |
2661 | ||
53d1f856 RH |
2662 | static uint64_t gt_virt_cnt_offset(CPUARMState *env) |
2663 | { | |
2664 | uint64_t hcr; | |
2665 | ||
2666 | switch (arm_current_el(env)) { | |
2667 | case 2: | |
2668 | hcr = arm_hcr_el2_eff(env); | |
2669 | if (hcr & HCR_E2H) { | |
2670 | return 0; | |
2671 | } | |
2672 | break; | |
2673 | case 0: | |
2674 | hcr = arm_hcr_el2_eff(env); | |
2675 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2676 | return 0; | |
2677 | } | |
2678 | break; | |
2679 | } | |
2680 | ||
2681 | return env->cp15.cntvoff_el2; | |
2682 | } | |
2683 | ||
edac4d8a EI |
2684 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2685 | { | |
53d1f856 | 2686 | return gt_get_countervalue(env) - gt_virt_cnt_offset(env); |
edac4d8a EI |
2687 | } |
2688 | ||
c4241c7d | 2689 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2690 | int timeridx, |
c4241c7d | 2691 | uint64_t value) |
55d284af | 2692 | { |
194cbc49 | 2693 | trace_arm_gt_cval_write(timeridx, value); |
55d284af | 2694 | env->cp15.c14_timer[timeridx].cval = value; |
2fc0cc0e | 2695 | gt_recalc_timer(env_archcpu(env), timeridx); |
55d284af | 2696 | } |
c4241c7d | 2697 | |
0e3eca4c EI |
2698 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, |
2699 | int timeridx) | |
55d284af | 2700 | { |
53d1f856 RH |
2701 | uint64_t offset = 0; |
2702 | ||
2703 | switch (timeridx) { | |
2704 | case GTIMER_VIRT: | |
8c94b071 | 2705 | case GTIMER_HYPVIRT: |
53d1f856 RH |
2706 | offset = gt_virt_cnt_offset(env); |
2707 | break; | |
2708 | } | |
55d284af | 2709 | |
c4241c7d | 2710 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - |
edac4d8a | 2711 | (gt_get_countervalue(env) - offset)); |
55d284af PM |
2712 | } |
2713 | ||
c4241c7d | 2714 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2715 | int timeridx, |
c4241c7d | 2716 | uint64_t value) |
55d284af | 2717 | { |
53d1f856 RH |
2718 | uint64_t offset = 0; |
2719 | ||
2720 | switch (timeridx) { | |
2721 | case GTIMER_VIRT: | |
8c94b071 | 2722 | case GTIMER_HYPVIRT: |
53d1f856 RH |
2723 | offset = gt_virt_cnt_offset(env); |
2724 | break; | |
2725 | } | |
55d284af | 2726 | |
194cbc49 | 2727 | trace_arm_gt_tval_write(timeridx, value); |
edac4d8a | 2728 | env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + |
18084b2f | 2729 | sextract64(value, 0, 32); |
2fc0cc0e | 2730 | gt_recalc_timer(env_archcpu(env), timeridx); |
55d284af PM |
2731 | } |
2732 | ||
c4241c7d | 2733 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2734 | int timeridx, |
c4241c7d | 2735 | uint64_t value) |
55d284af | 2736 | { |
2fc0cc0e | 2737 | ARMCPU *cpu = env_archcpu(env); |
55d284af PM |
2738 | uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; |
2739 | ||
194cbc49 | 2740 | trace_arm_gt_ctl_write(timeridx, value); |
d3afacc7 | 2741 | env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); |
55d284af PM |
2742 | if ((oldval ^ value) & 1) { |
2743 | /* Enable toggled */ | |
2744 | gt_recalc_timer(cpu, timeridx); | |
d3afacc7 | 2745 | } else if ((oldval ^ value) & 2) { |
55d284af PM |
2746 | /* IMASK toggled: don't need to recalculate, |
2747 | * just set the interrupt line based on ISTATUS | |
2748 | */ | |
194cbc49 PM |
2749 | int irqstate = (oldval & 4) && !(value & 2); |
2750 | ||
2751 | trace_arm_gt_imask_toggle(timeridx, irqstate); | |
2752 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
55d284af | 2753 | } |
55d284af PM |
2754 | } |
2755 | ||
0e3eca4c EI |
2756 | static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2757 | { | |
2758 | gt_timer_reset(env, ri, GTIMER_PHYS); | |
2759 | } | |
2760 | ||
2761 | static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2762 | uint64_t value) | |
2763 | { | |
2764 | gt_cval_write(env, ri, GTIMER_PHYS, value); | |
2765 | } | |
2766 | ||
2767 | static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2768 | { | |
2769 | return gt_tval_read(env, ri, GTIMER_PHYS); | |
2770 | } | |
2771 | ||
2772 | static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2773 | uint64_t value) | |
2774 | { | |
2775 | gt_tval_write(env, ri, GTIMER_PHYS, value); | |
2776 | } | |
2777 | ||
2778 | static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2779 | uint64_t value) | |
2780 | { | |
2781 | gt_ctl_write(env, ri, GTIMER_PHYS, value); | |
2782 | } | |
2783 | ||
bb5972e4 RH |
2784 | static int gt_phys_redir_timeridx(CPUARMState *env) |
2785 | { | |
2786 | switch (arm_mmu_idx(env)) { | |
2787 | case ARMMMUIdx_E20_0: | |
2788 | case ARMMMUIdx_E20_2: | |
452ef8cb | 2789 | case ARMMMUIdx_E20_2_PAN: |
bb5972e4 RH |
2790 | return GTIMER_HYP; |
2791 | default: | |
2792 | return GTIMER_PHYS; | |
2793 | } | |
2794 | } | |
2795 | ||
2796 | static int gt_virt_redir_timeridx(CPUARMState *env) | |
2797 | { | |
2798 | switch (arm_mmu_idx(env)) { | |
2799 | case ARMMMUIdx_E20_0: | |
2800 | case ARMMMUIdx_E20_2: | |
452ef8cb | 2801 | case ARMMMUIdx_E20_2_PAN: |
bb5972e4 RH |
2802 | return GTIMER_HYPVIRT; |
2803 | default: | |
2804 | return GTIMER_VIRT; | |
2805 | } | |
2806 | } | |
2807 | ||
2808 | static uint64_t gt_phys_redir_cval_read(CPUARMState *env, | |
2809 | const ARMCPRegInfo *ri) | |
2810 | { | |
2811 | int timeridx = gt_phys_redir_timeridx(env); | |
2812 | return env->cp15.c14_timer[timeridx].cval; | |
2813 | } | |
2814 | ||
2815 | static void gt_phys_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2816 | uint64_t value) | |
2817 | { | |
2818 | int timeridx = gt_phys_redir_timeridx(env); | |
2819 | gt_cval_write(env, ri, timeridx, value); | |
2820 | } | |
2821 | ||
2822 | static uint64_t gt_phys_redir_tval_read(CPUARMState *env, | |
2823 | const ARMCPRegInfo *ri) | |
2824 | { | |
2825 | int timeridx = gt_phys_redir_timeridx(env); | |
2826 | return gt_tval_read(env, ri, timeridx); | |
2827 | } | |
2828 | ||
2829 | static void gt_phys_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2830 | uint64_t value) | |
2831 | { | |
2832 | int timeridx = gt_phys_redir_timeridx(env); | |
2833 | gt_tval_write(env, ri, timeridx, value); | |
2834 | } | |
2835 | ||
2836 | static uint64_t gt_phys_redir_ctl_read(CPUARMState *env, | |
2837 | const ARMCPRegInfo *ri) | |
2838 | { | |
2839 | int timeridx = gt_phys_redir_timeridx(env); | |
2840 | return env->cp15.c14_timer[timeridx].ctl; | |
2841 | } | |
2842 | ||
2843 | static void gt_phys_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2844 | uint64_t value) | |
2845 | { | |
2846 | int timeridx = gt_phys_redir_timeridx(env); | |
2847 | gt_ctl_write(env, ri, timeridx, value); | |
2848 | } | |
2849 | ||
0e3eca4c EI |
2850 | static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2851 | { | |
2852 | gt_timer_reset(env, ri, GTIMER_VIRT); | |
2853 | } | |
2854 | ||
2855 | static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2856 | uint64_t value) | |
2857 | { | |
2858 | gt_cval_write(env, ri, GTIMER_VIRT, value); | |
2859 | } | |
2860 | ||
2861 | static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2862 | { | |
2863 | return gt_tval_read(env, ri, GTIMER_VIRT); | |
2864 | } | |
2865 | ||
2866 | static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2867 | uint64_t value) | |
2868 | { | |
2869 | gt_tval_write(env, ri, GTIMER_VIRT, value); | |
2870 | } | |
2871 | ||
2872 | static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2873 | uint64_t value) | |
2874 | { | |
2875 | gt_ctl_write(env, ri, GTIMER_VIRT, value); | |
2876 | } | |
2877 | ||
edac4d8a EI |
2878 | static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2879 | uint64_t value) | |
2880 | { | |
2fc0cc0e | 2881 | ARMCPU *cpu = env_archcpu(env); |
edac4d8a | 2882 | |
194cbc49 | 2883 | trace_arm_gt_cntvoff_write(value); |
edac4d8a EI |
2884 | raw_write(env, ri, value); |
2885 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
2886 | } | |
2887 | ||
bb5972e4 RH |
2888 | static uint64_t gt_virt_redir_cval_read(CPUARMState *env, |
2889 | const ARMCPRegInfo *ri) | |
2890 | { | |
2891 | int timeridx = gt_virt_redir_timeridx(env); | |
2892 | return env->cp15.c14_timer[timeridx].cval; | |
2893 | } | |
2894 | ||
2895 | static void gt_virt_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2896 | uint64_t value) | |
2897 | { | |
2898 | int timeridx = gt_virt_redir_timeridx(env); | |
2899 | gt_cval_write(env, ri, timeridx, value); | |
2900 | } | |
2901 | ||
2902 | static uint64_t gt_virt_redir_tval_read(CPUARMState *env, | |
2903 | const ARMCPRegInfo *ri) | |
2904 | { | |
2905 | int timeridx = gt_virt_redir_timeridx(env); | |
2906 | return gt_tval_read(env, ri, timeridx); | |
2907 | } | |
2908 | ||
2909 | static void gt_virt_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2910 | uint64_t value) | |
2911 | { | |
2912 | int timeridx = gt_virt_redir_timeridx(env); | |
2913 | gt_tval_write(env, ri, timeridx, value); | |
2914 | } | |
2915 | ||
2916 | static uint64_t gt_virt_redir_ctl_read(CPUARMState *env, | |
2917 | const ARMCPRegInfo *ri) | |
2918 | { | |
2919 | int timeridx = gt_virt_redir_timeridx(env); | |
2920 | return env->cp15.c14_timer[timeridx].ctl; | |
2921 | } | |
2922 | ||
2923 | static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2924 | uint64_t value) | |
2925 | { | |
2926 | int timeridx = gt_virt_redir_timeridx(env); | |
2927 | gt_ctl_write(env, ri, timeridx, value); | |
2928 | } | |
2929 | ||
b0e66d95 EI |
2930 | static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2931 | { | |
2932 | gt_timer_reset(env, ri, GTIMER_HYP); | |
2933 | } | |
2934 | ||
2935 | static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2936 | uint64_t value) | |
2937 | { | |
2938 | gt_cval_write(env, ri, GTIMER_HYP, value); | |
2939 | } | |
2940 | ||
2941 | static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2942 | { | |
2943 | return gt_tval_read(env, ri, GTIMER_HYP); | |
2944 | } | |
2945 | ||
2946 | static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2947 | uint64_t value) | |
2948 | { | |
2949 | gt_tval_write(env, ri, GTIMER_HYP, value); | |
2950 | } | |
2951 | ||
2952 | static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2953 | uint64_t value) | |
2954 | { | |
2955 | gt_ctl_write(env, ri, GTIMER_HYP, value); | |
2956 | } | |
2957 | ||
b4d3978c PM |
2958 | static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2959 | { | |
2960 | gt_timer_reset(env, ri, GTIMER_SEC); | |
2961 | } | |
2962 | ||
2963 | static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2964 | uint64_t value) | |
2965 | { | |
2966 | gt_cval_write(env, ri, GTIMER_SEC, value); | |
2967 | } | |
2968 | ||
2969 | static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2970 | { | |
2971 | return gt_tval_read(env, ri, GTIMER_SEC); | |
2972 | } | |
2973 | ||
2974 | static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2975 | uint64_t value) | |
2976 | { | |
2977 | gt_tval_write(env, ri, GTIMER_SEC, value); | |
2978 | } | |
2979 | ||
2980 | static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2981 | uint64_t value) | |
2982 | { | |
2983 | gt_ctl_write(env, ri, GTIMER_SEC, value); | |
2984 | } | |
2985 | ||
8c94b071 RH |
2986 | static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2987 | { | |
2988 | gt_timer_reset(env, ri, GTIMER_HYPVIRT); | |
2989 | } | |
2990 | ||
2991 | static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2992 | uint64_t value) | |
2993 | { | |
2994 | gt_cval_write(env, ri, GTIMER_HYPVIRT, value); | |
2995 | } | |
2996 | ||
2997 | static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2998 | { | |
2999 | return gt_tval_read(env, ri, GTIMER_HYPVIRT); | |
3000 | } | |
3001 | ||
3002 | static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3003 | uint64_t value) | |
3004 | { | |
3005 | gt_tval_write(env, ri, GTIMER_HYPVIRT, value); | |
3006 | } | |
3007 | ||
3008 | static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3009 | uint64_t value) | |
3010 | { | |
3011 | gt_ctl_write(env, ri, GTIMER_HYPVIRT, value); | |
3012 | } | |
3013 | ||
55d284af PM |
3014 | void arm_gt_ptimer_cb(void *opaque) |
3015 | { | |
3016 | ARMCPU *cpu = opaque; | |
3017 | ||
3018 | gt_recalc_timer(cpu, GTIMER_PHYS); | |
3019 | } | |
3020 | ||
3021 | void arm_gt_vtimer_cb(void *opaque) | |
3022 | { | |
3023 | ARMCPU *cpu = opaque; | |
3024 | ||
3025 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
3026 | } | |
3027 | ||
b0e66d95 EI |
3028 | void arm_gt_htimer_cb(void *opaque) |
3029 | { | |
3030 | ARMCPU *cpu = opaque; | |
3031 | ||
3032 | gt_recalc_timer(cpu, GTIMER_HYP); | |
3033 | } | |
3034 | ||
b4d3978c PM |
3035 | void arm_gt_stimer_cb(void *opaque) |
3036 | { | |
3037 | ARMCPU *cpu = opaque; | |
3038 | ||
3039 | gt_recalc_timer(cpu, GTIMER_SEC); | |
3040 | } | |
3041 | ||
8c94b071 RH |
3042 | void arm_gt_hvtimer_cb(void *opaque) |
3043 | { | |
3044 | ARMCPU *cpu = opaque; | |
3045 | ||
3046 | gt_recalc_timer(cpu, GTIMER_HYPVIRT); | |
3047 | } | |
3048 | ||
96eec6b2 AJ |
3049 | static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque) |
3050 | { | |
3051 | ARMCPU *cpu = env_archcpu(env); | |
3052 | ||
3053 | cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz; | |
3054 | } | |
3055 | ||
55d284af PM |
3056 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
3057 | /* Note that CNTFRQ is purely reads-as-written for the benefit | |
3058 | * of software; writing it doesn't actually change the timer frequency. | |
3059 | * Our reset value matches the fixed frequency we implement the timer at. | |
3060 | */ | |
3061 | { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 3062 | .type = ARM_CP_ALIAS, |
a7adc4b7 PM |
3063 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, |
3064 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), | |
a7adc4b7 PM |
3065 | }, |
3066 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, | |
3067 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
3068 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
55d284af | 3069 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), |
96eec6b2 | 3070 | .resetfn = arm_gt_cntfrq_reset, |
55d284af PM |
3071 | }, |
3072 | /* overall control: mostly access permissions */ | |
a7adc4b7 PM |
3073 | { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, |
3074 | .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, | |
55d284af PM |
3075 | .access = PL1_RW, |
3076 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), | |
3077 | .resetvalue = 0, | |
3078 | }, | |
3079 | /* per-timer control */ | |
3080 | { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
9ff9dd3c | 3081 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 3082 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
a7adc4b7 PM |
3083 | .accessfn = gt_ptimer_access, |
3084 | .fieldoffset = offsetoflow32(CPUARMState, | |
3085 | cp15.c14_timer[GTIMER_PHYS].ctl), | |
bb5972e4 RH |
3086 | .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read, |
3087 | .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write, | |
a7adc4b7 | 3088 | }, |
9c513e78 | 3089 | { .name = "CNTP_CTL_S", |
9ff9dd3c PM |
3090 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, |
3091 | .secure = ARM_CP_SECSTATE_S, | |
daf1dc5f | 3092 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
9ff9dd3c PM |
3093 | .accessfn = gt_ptimer_access, |
3094 | .fieldoffset = offsetoflow32(CPUARMState, | |
3095 | cp15.c14_timer[GTIMER_SEC].ctl), | |
3096 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
3097 | }, | |
a7adc4b7 PM |
3098 | { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, |
3099 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, | |
daf1dc5f | 3100 | .type = ARM_CP_IO, .access = PL0_RW, |
a7adc4b7 | 3101 | .accessfn = gt_ptimer_access, |
55d284af PM |
3102 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), |
3103 | .resetvalue = 0, | |
bb5972e4 RH |
3104 | .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read, |
3105 | .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write, | |
55d284af PM |
3106 | }, |
3107 | { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, | |
daf1dc5f | 3108 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
a7adc4b7 PM |
3109 | .accessfn = gt_vtimer_access, |
3110 | .fieldoffset = offsetoflow32(CPUARMState, | |
3111 | cp15.c14_timer[GTIMER_VIRT].ctl), | |
bb5972e4 RH |
3112 | .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read, |
3113 | .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write, | |
a7adc4b7 PM |
3114 | }, |
3115 | { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
3116 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, | |
daf1dc5f | 3117 | .type = ARM_CP_IO, .access = PL0_RW, |
a7adc4b7 | 3118 | .accessfn = gt_vtimer_access, |
55d284af PM |
3119 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), |
3120 | .resetvalue = 0, | |
bb5972e4 RH |
3121 | .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read, |
3122 | .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write, | |
55d284af PM |
3123 | }, |
3124 | /* TimerValue views: a 32 bit downcounting view of the underlying state */ | |
3125 | { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
9ff9dd3c | 3126 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 3127 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
00108f2d | 3128 | .accessfn = gt_ptimer_access, |
bb5972e4 | 3129 | .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write, |
55d284af | 3130 | }, |
9c513e78 | 3131 | { .name = "CNTP_TVAL_S", |
9ff9dd3c PM |
3132 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, |
3133 | .secure = ARM_CP_SECSTATE_S, | |
daf1dc5f | 3134 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
9ff9dd3c PM |
3135 | .accessfn = gt_ptimer_access, |
3136 | .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, | |
3137 | }, | |
a7adc4b7 PM |
3138 | { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
3139 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, | |
daf1dc5f | 3140 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
0e3eca4c | 3141 | .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, |
bb5972e4 | 3142 | .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write, |
a7adc4b7 | 3143 | }, |
55d284af | 3144 | { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, |
daf1dc5f | 3145 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
00108f2d | 3146 | .accessfn = gt_vtimer_access, |
bb5972e4 | 3147 | .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write, |
55d284af | 3148 | }, |
a7adc4b7 PM |
3149 | { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
3150 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, | |
daf1dc5f | 3151 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
0e3eca4c | 3152 | .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, |
bb5972e4 | 3153 | .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write, |
a7adc4b7 | 3154 | }, |
55d284af PM |
3155 | /* The counter itself */ |
3156 | { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, | |
7a0e58fa | 3157 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 3158 | .accessfn = gt_pct_access, |
a7adc4b7 PM |
3159 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
3160 | }, | |
3161 | { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, | |
3162 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, | |
7a0e58fa | 3163 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 3164 | .accessfn = gt_pct_access, .readfn = gt_cnt_read, |
55d284af PM |
3165 | }, |
3166 | { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, | |
7a0e58fa | 3167 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 3168 | .accessfn = gt_vct_access, |
edac4d8a | 3169 | .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, |
a7adc4b7 PM |
3170 | }, |
3171 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
3172 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
7a0e58fa | 3173 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 3174 | .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, |
55d284af PM |
3175 | }, |
3176 | /* Comparison value, indicating when the timer goes off */ | |
3177 | { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, | |
9ff9dd3c | 3178 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 3179 | .access = PL0_RW, |
7a0e58fa | 3180 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 3181 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), |
b061a82b | 3182 | .accessfn = gt_ptimer_access, |
bb5972e4 RH |
3183 | .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read, |
3184 | .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write, | |
a7adc4b7 | 3185 | }, |
9c513e78 | 3186 | { .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2, |
9ff9dd3c | 3187 | .secure = ARM_CP_SECSTATE_S, |
daf1dc5f | 3188 | .access = PL0_RW, |
9ff9dd3c PM |
3189 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
3190 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
3191 | .accessfn = gt_ptimer_access, | |
3192 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
3193 | }, | |
a7adc4b7 PM |
3194 | { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, |
3195 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, | |
daf1dc5f | 3196 | .access = PL0_RW, |
a7adc4b7 PM |
3197 | .type = ARM_CP_IO, |
3198 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
12cde08a | 3199 | .resetvalue = 0, .accessfn = gt_ptimer_access, |
bb5972e4 RH |
3200 | .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read, |
3201 | .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write, | |
55d284af PM |
3202 | }, |
3203 | { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, | |
daf1dc5f | 3204 | .access = PL0_RW, |
7a0e58fa | 3205 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 3206 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), |
b061a82b | 3207 | .accessfn = gt_vtimer_access, |
bb5972e4 RH |
3208 | .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read, |
3209 | .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write, | |
a7adc4b7 PM |
3210 | }, |
3211 | { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
3212 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, | |
daf1dc5f | 3213 | .access = PL0_RW, |
a7adc4b7 PM |
3214 | .type = ARM_CP_IO, |
3215 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
3216 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
bb5972e4 RH |
3217 | .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read, |
3218 | .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write, | |
55d284af | 3219 | }, |
b4d3978c PM |
3220 | /* Secure timer -- this is actually restricted to only EL3 |
3221 | * and configurably Secure-EL1 via the accessfn. | |
3222 | */ | |
3223 | { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, | |
3224 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, | |
3225 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, | |
3226 | .accessfn = gt_stimer_access, | |
3227 | .readfn = gt_sec_tval_read, | |
3228 | .writefn = gt_sec_tval_write, | |
3229 | .resetfn = gt_sec_timer_reset, | |
3230 | }, | |
3231 | { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64, | |
3232 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1, | |
3233 | .type = ARM_CP_IO, .access = PL1_RW, | |
3234 | .accessfn = gt_stimer_access, | |
3235 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), | |
3236 | .resetvalue = 0, | |
3237 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
3238 | }, | |
3239 | { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, | |
3240 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, | |
3241 | .type = ARM_CP_IO, .access = PL1_RW, | |
3242 | .accessfn = gt_stimer_access, | |
3243 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
3244 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
3245 | }, | |
55d284af PM |
3246 | REGINFO_SENTINEL |
3247 | }; | |
3248 | ||
bb5972e4 RH |
3249 | static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3250 | bool isread) | |
3251 | { | |
3252 | if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { | |
3253 | return CP_ACCESS_TRAP; | |
3254 | } | |
3255 | return CP_ACCESS_OK; | |
3256 | } | |
3257 | ||
55d284af | 3258 | #else |
26c4a83b AB |
3259 | |
3260 | /* In user-mode most of the generic timer registers are inaccessible | |
3261 | * however modern kernels (4.12+) allow access to cntvct_el0 | |
55d284af | 3262 | */ |
26c4a83b AB |
3263 | |
3264 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3265 | { | |
7def8754 AJ |
3266 | ARMCPU *cpu = env_archcpu(env); |
3267 | ||
26c4a83b AB |
3268 | /* Currently we have no support for QEMUTimer in linux-user so we |
3269 | * can't call gt_get_countervalue(env), instead we directly | |
3270 | * call the lower level functions. | |
3271 | */ | |
7def8754 | 3272 | return cpu_get_clock() / gt_cntfrq_period_ns(cpu); |
26c4a83b AB |
3273 | } |
3274 | ||
6cc7a3ae | 3275 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
26c4a83b AB |
3276 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, |
3277 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
3278 | .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */, | |
3279 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), | |
3280 | .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE, | |
3281 | }, | |
3282 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
3283 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
3284 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
3285 | .readfn = gt_virt_cnt_read, | |
3286 | }, | |
6cc7a3ae PM |
3287 | REGINFO_SENTINEL |
3288 | }; | |
3289 | ||
55d284af PM |
3290 | #endif |
3291 | ||
c4241c7d | 3292 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 3293 | { |
891a2fe7 | 3294 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8d5c773e | 3295 | raw_write(env, ri, value); |
891a2fe7 | 3296 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8d5c773e | 3297 | raw_write(env, ri, value & 0xfffff6ff); |
4a501606 | 3298 | } else { |
8d5c773e | 3299 | raw_write(env, ri, value & 0xfffff1ff); |
4a501606 | 3300 | } |
4a501606 PM |
3301 | } |
3302 | ||
3303 | #ifndef CONFIG_USER_ONLY | |
3304 | /* get_phys_addr() isn't present for user-mode-only targets */ | |
702a9357 | 3305 | |
3f208fd7 PM |
3306 | static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3307 | bool isread) | |
92611c00 PM |
3308 | { |
3309 | if (ri->opc2 & 4) { | |
87562e4f PM |
3310 | /* The ATS12NSO* operations must trap to EL3 if executed in |
3311 | * Secure EL1 (which can only happen if EL3 is AArch64). | |
3312 | * They are simply UNDEF if executed from NS EL1. | |
3313 | * They function normally from EL2 or EL3. | |
92611c00 | 3314 | */ |
87562e4f PM |
3315 | if (arm_current_el(env) == 1) { |
3316 | if (arm_is_secure_below_el3(env)) { | |
3317 | return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; | |
3318 | } | |
3319 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
3320 | } | |
92611c00 PM |
3321 | } |
3322 | return CP_ACCESS_OK; | |
3323 | } | |
3324 | ||
060e8a48 | 3325 | static uint64_t do_ats_write(CPUARMState *env, uint64_t value, |
03ae85f8 | 3326 | MMUAccessType access_type, ARMMMUIdx mmu_idx) |
4a501606 | 3327 | { |
a8170e5e | 3328 | hwaddr phys_addr; |
4a501606 PM |
3329 | target_ulong page_size; |
3330 | int prot; | |
b7cc4e82 | 3331 | bool ret; |
01c097f7 | 3332 | uint64_t par64; |
1313e2d7 | 3333 | bool format64 = false; |
8bf5b6a9 | 3334 | MemTxAttrs attrs = {}; |
e14b5a23 | 3335 | ARMMMUFaultInfo fi = {}; |
5b2d261d | 3336 | ARMCacheAttrs cacheattrs = {}; |
4a501606 | 3337 | |
5b2d261d | 3338 | ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, |
bc52bfeb | 3339 | &prot, &page_size, &fi, &cacheattrs); |
1313e2d7 | 3340 | |
0710b2fa PM |
3341 | if (ret) { |
3342 | /* | |
3343 | * Some kinds of translation fault must cause exceptions rather | |
3344 | * than being reported in the PAR. | |
3345 | */ | |
3346 | int current_el = arm_current_el(env); | |
3347 | int target_el; | |
3348 | uint32_t syn, fsr, fsc; | |
3349 | bool take_exc = false; | |
3350 | ||
3351 | if (fi.s1ptw && current_el == 1 && !arm_is_secure(env) | |
fee7aa46 | 3352 | && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { |
0710b2fa PM |
3353 | /* |
3354 | * Synchronous stage 2 fault on an access made as part of the | |
3355 | * translation table walk for AT S1E0* or AT S1E1* insn | |
3356 | * executed from NS EL1. If this is a synchronous external abort | |
3357 | * and SCR_EL3.EA == 1, then we take a synchronous external abort | |
3358 | * to EL3. Otherwise the fault is taken as an exception to EL2, | |
3359 | * and HPFAR_EL2 holds the faulting IPA. | |
3360 | */ | |
3361 | if (fi.type == ARMFault_SyncExternalOnWalk && | |
3362 | (env->cp15.scr_el3 & SCR_EA)) { | |
3363 | target_el = 3; | |
3364 | } else { | |
3365 | env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; | |
3366 | target_el = 2; | |
3367 | } | |
3368 | take_exc = true; | |
3369 | } else if (fi.type == ARMFault_SyncExternalOnWalk) { | |
3370 | /* | |
3371 | * Synchronous external aborts during a translation table walk | |
3372 | * are taken as Data Abort exceptions. | |
3373 | */ | |
3374 | if (fi.stage2) { | |
3375 | if (current_el == 3) { | |
3376 | target_el = 3; | |
3377 | } else { | |
3378 | target_el = 2; | |
3379 | } | |
3380 | } else { | |
3381 | target_el = exception_target_el(env); | |
3382 | } | |
3383 | take_exc = true; | |
3384 | } | |
3385 | ||
3386 | if (take_exc) { | |
3387 | /* Construct FSR and FSC using same logic as arm_deliver_fault() */ | |
3388 | if (target_el == 2 || arm_el_is_aa64(env, target_el) || | |
3389 | arm_s1_regime_using_lpae_format(env, mmu_idx)) { | |
3390 | fsr = arm_fi_to_lfsc(&fi); | |
3391 | fsc = extract32(fsr, 0, 6); | |
3392 | } else { | |
3393 | fsr = arm_fi_to_sfsc(&fi); | |
3394 | fsc = 0x3f; | |
3395 | } | |
3396 | /* | |
3397 | * Report exception with ESR indicating a fault due to a | |
3398 | * translation table walk for a cache maintenance instruction. | |
3399 | */ | |
3400 | syn = syn_data_abort_no_iss(current_el == target_el, | |
3401 | fi.ea, 1, fi.s1ptw, 1, fsc); | |
3402 | env->exception.vaddress = value; | |
3403 | env->exception.fsr = fsr; | |
3404 | raise_exception(env, EXCP_DATA_ABORT, syn, target_el); | |
3405 | } | |
3406 | } | |
3407 | ||
1313e2d7 EI |
3408 | if (is_a64(env)) { |
3409 | format64 = true; | |
3410 | } else if (arm_feature(env, ARM_FEATURE_LPAE)) { | |
3411 | /* | |
3412 | * ATS1Cxx: | |
3413 | * * TTBCR.EAE determines whether the result is returned using the | |
3414 | * 32-bit or the 64-bit PAR format | |
3415 | * * Instructions executed in Hyp mode always use the 64bit format | |
3416 | * | |
3417 | * ATS1S2NSOxx uses the 64bit format if any of the following is true: | |
3418 | * * The Non-secure TTBCR.EAE bit is set to 1 | |
3419 | * * The implementation includes EL2, and the value of HCR.VM is 1 | |
3420 | * | |
9d1bab33 PM |
3421 | * (Note that HCR.DC makes HCR.VM behave as if it is 1.) |
3422 | * | |
23463e0e | 3423 | * ATS1Hx always uses the 64bit format. |
1313e2d7 EI |
3424 | */ |
3425 | format64 = arm_s1_regime_using_lpae_format(env, mmu_idx); | |
3426 | ||
3427 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
452ef8cb RH |
3428 | if (mmu_idx == ARMMMUIdx_E10_0 || |
3429 | mmu_idx == ARMMMUIdx_E10_1 || | |
3430 | mmu_idx == ARMMMUIdx_E10_1_PAN) { | |
9d1bab33 | 3431 | format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC); |
1313e2d7 EI |
3432 | } else { |
3433 | format64 |= arm_current_el(env) == 2; | |
3434 | } | |
3435 | } | |
3436 | } | |
3437 | ||
3438 | if (format64) { | |
5efe9ed4 | 3439 | /* Create a 64-bit PAR */ |
01c097f7 | 3440 | par64 = (1 << 11); /* LPAE bit always set */ |
b7cc4e82 | 3441 | if (!ret) { |
702a9357 | 3442 | par64 |= phys_addr & ~0xfffULL; |
8bf5b6a9 PM |
3443 | if (!attrs.secure) { |
3444 | par64 |= (1 << 9); /* NS */ | |
3445 | } | |
5b2d261d AB |
3446 | par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */ |
3447 | par64 |= cacheattrs.shareability << 7; /* SH */ | |
4a501606 | 3448 | } else { |
5efe9ed4 PM |
3449 | uint32_t fsr = arm_fi_to_lfsc(&fi); |
3450 | ||
702a9357 | 3451 | par64 |= 1; /* F */ |
b7cc4e82 | 3452 | par64 |= (fsr & 0x3f) << 1; /* FS */ |
0f7b791b PM |
3453 | if (fi.stage2) { |
3454 | par64 |= (1 << 9); /* S */ | |
3455 | } | |
3456 | if (fi.s1ptw) { | |
3457 | par64 |= (1 << 8); /* PTW */ | |
3458 | } | |
4a501606 PM |
3459 | } |
3460 | } else { | |
b7cc4e82 | 3461 | /* fsr is a DFSR/IFSR value for the short descriptor |
702a9357 PM |
3462 | * translation table format (with WnR always clear). |
3463 | * Convert it to a 32-bit PAR. | |
3464 | */ | |
b7cc4e82 | 3465 | if (!ret) { |
702a9357 PM |
3466 | /* We do not set any attribute bits in the PAR */ |
3467 | if (page_size == (1 << 24) | |
3468 | && arm_feature(env, ARM_FEATURE_V7)) { | |
01c097f7 | 3469 | par64 = (phys_addr & 0xff000000) | (1 << 1); |
702a9357 | 3470 | } else { |
01c097f7 | 3471 | par64 = phys_addr & 0xfffff000; |
702a9357 | 3472 | } |
8bf5b6a9 PM |
3473 | if (!attrs.secure) { |
3474 | par64 |= (1 << 9); /* NS */ | |
3475 | } | |
702a9357 | 3476 | } else { |
5efe9ed4 PM |
3477 | uint32_t fsr = arm_fi_to_sfsc(&fi); |
3478 | ||
b7cc4e82 PC |
3479 | par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | |
3480 | ((fsr & 0xf) << 1) | 1; | |
702a9357 | 3481 | } |
4a501606 | 3482 | } |
060e8a48 PM |
3483 | return par64; |
3484 | } | |
3485 | ||
3486 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | |
3487 | { | |
03ae85f8 | 3488 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
060e8a48 | 3489 | uint64_t par64; |
d3649702 PM |
3490 | ARMMMUIdx mmu_idx; |
3491 | int el = arm_current_el(env); | |
3492 | bool secure = arm_is_secure_below_el3(env); | |
060e8a48 | 3493 | |
d3649702 PM |
3494 | switch (ri->opc2 & 6) { |
3495 | case 0: | |
04b07d29 | 3496 | /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */ |
d3649702 PM |
3497 | switch (el) { |
3498 | case 3: | |
127b2b08 | 3499 | mmu_idx = ARMMMUIdx_SE3; |
d3649702 PM |
3500 | break; |
3501 | case 2: | |
04b07d29 RH |
3502 | g_assert(!secure); /* TODO: ARMv8.4-SecEL2 */ |
3503 | /* fall through */ | |
d3649702 | 3504 | case 1: |
04b07d29 RH |
3505 | if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) { |
3506 | mmu_idx = (secure ? ARMMMUIdx_SE10_1_PAN | |
3507 | : ARMMMUIdx_Stage1_E1_PAN); | |
3508 | } else { | |
3509 | mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; | |
3510 | } | |
d3649702 PM |
3511 | break; |
3512 | default: | |
3513 | g_assert_not_reached(); | |
3514 | } | |
3515 | break; | |
3516 | case 2: | |
3517 | /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ | |
3518 | switch (el) { | |
3519 | case 3: | |
fba37aed | 3520 | mmu_idx = ARMMMUIdx_SE10_0; |
d3649702 PM |
3521 | break; |
3522 | case 2: | |
2859d7b5 | 3523 | mmu_idx = ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3524 | break; |
3525 | case 1: | |
fba37aed | 3526 | mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3527 | break; |
3528 | default: | |
3529 | g_assert_not_reached(); | |
3530 | } | |
3531 | break; | |
3532 | case 4: | |
3533 | /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ | |
01b98b68 | 3534 | mmu_idx = ARMMMUIdx_E10_1; |
d3649702 PM |
3535 | break; |
3536 | case 6: | |
3537 | /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ | |
01b98b68 | 3538 | mmu_idx = ARMMMUIdx_E10_0; |
d3649702 PM |
3539 | break; |
3540 | default: | |
3541 | g_assert_not_reached(); | |
3542 | } | |
3543 | ||
3544 | par64 = do_ats_write(env, value, access_type, mmu_idx); | |
01c097f7 FA |
3545 | |
3546 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
4a501606 | 3547 | } |
060e8a48 | 3548 | |
14db7fe0 PM |
3549 | static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3550 | uint64_t value) | |
3551 | { | |
03ae85f8 | 3552 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
14db7fe0 PM |
3553 | uint64_t par64; |
3554 | ||
e013b741 | 3555 | par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2); |
14db7fe0 PM |
3556 | |
3557 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
3558 | } | |
3559 | ||
3f208fd7 PM |
3560 | static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3561 | bool isread) | |
2a47df95 PM |
3562 | { |
3563 | if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) { | |
3564 | return CP_ACCESS_TRAP; | |
3565 | } | |
3566 | return CP_ACCESS_OK; | |
3567 | } | |
3568 | ||
060e8a48 PM |
3569 | static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, |
3570 | uint64_t value) | |
3571 | { | |
03ae85f8 | 3572 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
d3649702 PM |
3573 | ARMMMUIdx mmu_idx; |
3574 | int secure = arm_is_secure_below_el3(env); | |
3575 | ||
3576 | switch (ri->opc2 & 6) { | |
3577 | case 0: | |
3578 | switch (ri->opc1) { | |
04b07d29 RH |
3579 | case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ |
3580 | if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) { | |
3581 | mmu_idx = (secure ? ARMMMUIdx_SE10_1_PAN | |
3582 | : ARMMMUIdx_Stage1_E1_PAN); | |
3583 | } else { | |
3584 | mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; | |
3585 | } | |
d3649702 PM |
3586 | break; |
3587 | case 4: /* AT S1E2R, AT S1E2W */ | |
e013b741 | 3588 | mmu_idx = ARMMMUIdx_E2; |
d3649702 PM |
3589 | break; |
3590 | case 6: /* AT S1E3R, AT S1E3W */ | |
127b2b08 | 3591 | mmu_idx = ARMMMUIdx_SE3; |
d3649702 PM |
3592 | break; |
3593 | default: | |
3594 | g_assert_not_reached(); | |
3595 | } | |
3596 | break; | |
3597 | case 2: /* AT S1E0R, AT S1E0W */ | |
fba37aed | 3598 | mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3599 | break; |
3600 | case 4: /* AT S12E1R, AT S12E1W */ | |
fba37aed | 3601 | mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1; |
d3649702 PM |
3602 | break; |
3603 | case 6: /* AT S12E0R, AT S12E0W */ | |
fba37aed | 3604 | mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0; |
d3649702 PM |
3605 | break; |
3606 | default: | |
3607 | g_assert_not_reached(); | |
3608 | } | |
060e8a48 | 3609 | |
d3649702 | 3610 | env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); |
060e8a48 | 3611 | } |
4a501606 PM |
3612 | #endif |
3613 | ||
3614 | static const ARMCPRegInfo vapa_cp_reginfo[] = { | |
3615 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, | |
3616 | .access = PL1_RW, .resetvalue = 0, | |
01c097f7 FA |
3617 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), |
3618 | offsetoflow32(CPUARMState, cp15.par_ns) }, | |
4a501606 PM |
3619 | .writefn = par_write }, |
3620 | #ifndef CONFIG_USER_ONLY | |
87562e4f | 3621 | /* This underdecoding is safe because the reginfo is NO_RAW. */ |
4a501606 | 3622 | { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, |
92611c00 | 3623 | .access = PL1_W, .accessfn = ats_access, |
0710b2fa | 3624 | .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
4a501606 PM |
3625 | #endif |
3626 | REGINFO_SENTINEL | |
3627 | }; | |
3628 | ||
18032bec PM |
3629 | /* Return basic MPU access permission bits. */ |
3630 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
3631 | { | |
3632 | uint32_t ret; | |
3633 | uint32_t mask; | |
3634 | int i; | |
3635 | ret = 0; | |
3636 | mask = 3; | |
3637 | for (i = 0; i < 16; i += 2) { | |
3638 | ret |= (val >> i) & mask; | |
3639 | mask <<= 2; | |
3640 | } | |
3641 | return ret; | |
3642 | } | |
3643 | ||
3644 | /* Pad basic MPU access permission bits to extended format. */ | |
3645 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
3646 | { | |
3647 | uint32_t ret; | |
3648 | uint32_t mask; | |
3649 | int i; | |
3650 | ret = 0; | |
3651 | mask = 3; | |
3652 | for (i = 0; i < 16; i += 2) { | |
3653 | ret |= (val & mask) << i; | |
3654 | mask <<= 2; | |
3655 | } | |
3656 | return ret; | |
3657 | } | |
3658 | ||
c4241c7d PM |
3659 | static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3660 | uint64_t value) | |
18032bec | 3661 | { |
7e09797c | 3662 | env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3663 | } |
3664 | ||
c4241c7d | 3665 | static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3666 | { |
7e09797c | 3667 | return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); |
18032bec PM |
3668 | } |
3669 | ||
c4241c7d PM |
3670 | static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3671 | uint64_t value) | |
18032bec | 3672 | { |
7e09797c | 3673 | env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3674 | } |
3675 | ||
c4241c7d | 3676 | static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3677 | { |
7e09797c | 3678 | return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); |
18032bec PM |
3679 | } |
3680 | ||
6cb0b013 PC |
3681 | static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) |
3682 | { | |
3683 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); | |
3684 | ||
3685 | if (!u32p) { | |
3686 | return 0; | |
3687 | } | |
3688 | ||
1bc04a88 | 3689 | u32p += env->pmsav7.rnr[M_REG_NS]; |
6cb0b013 PC |
3690 | return *u32p; |
3691 | } | |
3692 | ||
3693 | static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3694 | uint64_t value) | |
3695 | { | |
2fc0cc0e | 3696 | ARMCPU *cpu = env_archcpu(env); |
6cb0b013 PC |
3697 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); |
3698 | ||
3699 | if (!u32p) { | |
3700 | return; | |
3701 | } | |
3702 | ||
1bc04a88 | 3703 | u32p += env->pmsav7.rnr[M_REG_NS]; |
d10eb08f | 3704 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ |
6cb0b013 PC |
3705 | *u32p = value; |
3706 | } | |
3707 | ||
6cb0b013 PC |
3708 | static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3709 | uint64_t value) | |
3710 | { | |
2fc0cc0e | 3711 | ARMCPU *cpu = env_archcpu(env); |
6cb0b013 PC |
3712 | uint32_t nrgs = cpu->pmsav7_dregion; |
3713 | ||
3714 | if (value >= nrgs) { | |
3715 | qemu_log_mask(LOG_GUEST_ERROR, | |
3716 | "PMSAv7 RGNR write >= # supported regions, %" PRIu32 | |
3717 | " > %" PRIu32 "\n", (uint32_t)value, nrgs); | |
3718 | return; | |
3719 | } | |
3720 | ||
3721 | raw_write(env, ri, value); | |
3722 | } | |
3723 | ||
3724 | static const ARMCPRegInfo pmsav7_cp_reginfo[] = { | |
69ceea64 PM |
3725 | /* Reset for all these registers is handled in arm_cpu_reset(), |
3726 | * because the PMSAv7 is also used by M-profile CPUs, which do | |
3727 | * not register cpregs but still need the state to be reset. | |
3728 | */ | |
6cb0b013 PC |
3729 | { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, |
3730 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3731 | .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), | |
69ceea64 PM |
3732 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3733 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3734 | { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, |
3735 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3736 | .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), | |
69ceea64 PM |
3737 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3738 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3739 | { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, |
3740 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3741 | .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), | |
69ceea64 PM |
3742 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3743 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3744 | { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, |
3745 | .access = PL1_RW, | |
1bc04a88 | 3746 | .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), |
69ceea64 PM |
3747 | .writefn = pmsav7_rgnr_write, |
3748 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3749 | REGINFO_SENTINEL |
3750 | }; | |
3751 | ||
18032bec PM |
3752 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { |
3753 | { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 3754 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 3755 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
18032bec PM |
3756 | .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, |
3757 | { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 3758 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 3759 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
18032bec PM |
3760 | .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, |
3761 | { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, | |
3762 | .access = PL1_RW, | |
7e09797c PM |
3763 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
3764 | .resetvalue = 0, }, | |
18032bec PM |
3765 | { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, |
3766 | .access = PL1_RW, | |
7e09797c PM |
3767 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
3768 | .resetvalue = 0, }, | |
ecce5c3c PM |
3769 | { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
3770 | .access = PL1_RW, | |
3771 | .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, | |
3772 | { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
3773 | .access = PL1_RW, | |
3774 | .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, | |
06d76f31 | 3775 | /* Protection region base and size registers */ |
e508a92b PM |
3776 | { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, |
3777 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3778 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, | |
3779 | { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, | |
3780 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3781 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, | |
3782 | { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, | |
3783 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3784 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, | |
3785 | { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, | |
3786 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3787 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, | |
3788 | { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, | |
3789 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3790 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, | |
3791 | { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, | |
3792 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3793 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, | |
3794 | { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, | |
3795 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3796 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, | |
3797 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | |
3798 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3799 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | |
18032bec PM |
3800 | REGINFO_SENTINEL |
3801 | }; | |
3802 | ||
c4241c7d PM |
3803 | static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3804 | uint64_t value) | |
ecce5c3c | 3805 | { |
11f136ee | 3806 | TCR *tcr = raw_ptr(env, ri); |
2ebcebe2 PM |
3807 | int maskshift = extract32(value, 0, 3); |
3808 | ||
e389be16 FA |
3809 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
3810 | if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { | |
3811 | /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when | |
3812 | * using Long-desciptor translation table format */ | |
3813 | value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); | |
3814 | } else if (arm_feature(env, ARM_FEATURE_EL3)) { | |
3815 | /* In an implementation that includes the Security Extensions | |
3816 | * TTBCR has additional fields PD0 [4] and PD1 [5] for | |
3817 | * Short-descriptor translation table format. | |
3818 | */ | |
3819 | value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; | |
3820 | } else { | |
3821 | value &= TTBCR_N; | |
3822 | } | |
e42c4db3 | 3823 | } |
e389be16 | 3824 | |
b6af0975 | 3825 | /* Update the masks corresponding to the TCR bank being written |
11f136ee | 3826 | * Note that we always calculate mask and base_mask, but |
e42c4db3 | 3827 | * they are only used for short-descriptor tables (ie if EAE is 0); |
11f136ee FA |
3828 | * for long-descriptor tables the TCR fields are used differently |
3829 | * and the mask and base_mask values are meaningless. | |
e42c4db3 | 3830 | */ |
11f136ee FA |
3831 | tcr->raw_tcr = value; |
3832 | tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift); | |
3833 | tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift); | |
ecce5c3c PM |
3834 | } |
3835 | ||
c4241c7d PM |
3836 | static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3837 | uint64_t value) | |
d4e6df63 | 3838 | { |
2fc0cc0e | 3839 | ARMCPU *cpu = env_archcpu(env); |
ab638a32 | 3840 | TCR *tcr = raw_ptr(env, ri); |
00c8cb0a | 3841 | |
d4e6df63 PM |
3842 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
3843 | /* With LPAE the TTBCR could result in a change of ASID | |
3844 | * via the TTBCR.A1 bit, so do a TLB flush. | |
3845 | */ | |
d10eb08f | 3846 | tlb_flush(CPU(cpu)); |
d4e6df63 | 3847 | } |
ab638a32 RH |
3848 | /* Preserve the high half of TCR_EL1, set via TTBCR2. */ |
3849 | value = deposit64(tcr->raw_tcr, 0, 32, value); | |
c4241c7d | 3850 | vmsa_ttbcr_raw_write(env, ri, value); |
d4e6df63 PM |
3851 | } |
3852 | ||
ecce5c3c PM |
3853 | static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
3854 | { | |
11f136ee FA |
3855 | TCR *tcr = raw_ptr(env, ri); |
3856 | ||
3857 | /* Reset both the TCR as well as the masks corresponding to the bank of | |
3858 | * the TCR being reset. | |
3859 | */ | |
3860 | tcr->raw_tcr = 0; | |
3861 | tcr->mask = 0; | |
3862 | tcr->base_mask = 0xffffc000u; | |
ecce5c3c PM |
3863 | } |
3864 | ||
d06dc933 | 3865 | static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, |
cb2e37df PM |
3866 | uint64_t value) |
3867 | { | |
2fc0cc0e | 3868 | ARMCPU *cpu = env_archcpu(env); |
11f136ee | 3869 | TCR *tcr = raw_ptr(env, ri); |
00c8cb0a | 3870 | |
cb2e37df | 3871 | /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ |
d10eb08f | 3872 | tlb_flush(CPU(cpu)); |
11f136ee | 3873 | tcr->raw_tcr = value; |
cb2e37df PM |
3874 | } |
3875 | ||
327ed10f PM |
3876 | static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3877 | uint64_t value) | |
3878 | { | |
93f379b0 RH |
3879 | /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ |
3880 | if (cpreg_field_is_64bit(ri) && | |
3881 | extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { | |
2fc0cc0e | 3882 | ARMCPU *cpu = env_archcpu(env); |
d10eb08f | 3883 | tlb_flush(CPU(cpu)); |
327ed10f PM |
3884 | } |
3885 | raw_write(env, ri, value); | |
3886 | } | |
3887 | ||
ed30da8e RH |
3888 | static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3889 | uint64_t value) | |
3890 | { | |
d06dc933 RH |
3891 | /* |
3892 | * If we are running with E2&0 regime, then an ASID is active. | |
3893 | * Flush if that might be changing. Note we're not checking | |
3894 | * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that | |
3895 | * holds the active ASID, only checking the field that might. | |
3896 | */ | |
3897 | if (extract64(raw_read(env, ri) ^ value, 48, 16) && | |
3898 | (arm_hcr_el2_eff(env) & HCR_E2H)) { | |
3899 | tlb_flush_by_mmuidx(env_cpu(env), | |
452ef8cb RH |
3900 | ARMMMUIdxBit_E20_2 | |
3901 | ARMMMUIdxBit_E20_2_PAN | | |
3902 | ARMMMUIdxBit_E20_0); | |
d06dc933 | 3903 | } |
ed30da8e RH |
3904 | raw_write(env, ri, value); |
3905 | } | |
3906 | ||
b698e9cf EI |
3907 | static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3908 | uint64_t value) | |
3909 | { | |
2fc0cc0e | 3910 | ARMCPU *cpu = env_archcpu(env); |
b698e9cf EI |
3911 | CPUState *cs = CPU(cpu); |
3912 | ||
97fa9350 RH |
3913 | /* |
3914 | * A change in VMID to the stage2 page table (Stage2) invalidates | |
3915 | * the combined stage 1&2 tlbs (EL10_1 and EL10_0). | |
3916 | */ | |
b698e9cf | 3917 | if (raw_read(env, ri) != value) { |
0336cbf8 | 3918 | tlb_flush_by_mmuidx(cs, |
01b98b68 | 3919 | ARMMMUIdxBit_E10_1 | |
452ef8cb | 3920 | ARMMMUIdxBit_E10_1_PAN | |
01b98b68 | 3921 | ARMMMUIdxBit_E10_0 | |
97fa9350 | 3922 | ARMMMUIdxBit_Stage2); |
b698e9cf EI |
3923 | raw_write(env, ri, value); |
3924 | } | |
3925 | } | |
3926 | ||
8e5d75c9 | 3927 | static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { |
18032bec | 3928 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, |
84929218 | 3929 | .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS, |
4a7e2d73 | 3930 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), |
b061a82b | 3931 | offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, |
18032bec | 3932 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, |
84929218 | 3933 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
88ca1c2d FA |
3934 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), |
3935 | offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, | |
8e5d75c9 | 3936 | { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, |
84929218 | 3937 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
8e5d75c9 PC |
3938 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), |
3939 | offsetof(CPUARMState, cp15.dfar_ns) } }, | |
3940 | { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, | |
3941 | .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, | |
84929218 RH |
3942 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3943 | .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), | |
8e5d75c9 PC |
3944 | .resetvalue = 0, }, |
3945 | REGINFO_SENTINEL | |
3946 | }; | |
3947 | ||
3948 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { | |
6cd8a264 RH |
3949 | { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, |
3950 | .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, | |
84929218 | 3951 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
d81c519c | 3952 | .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, |
327ed10f | 3953 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af | 3954 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, |
84929218 RH |
3955 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3956 | .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
7dd8c9af FA |
3957 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
3958 | offsetof(CPUARMState, cp15.ttbr0_ns) } }, | |
327ed10f | 3959 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af | 3960 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, |
84929218 RH |
3961 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3962 | .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
7dd8c9af FA |
3963 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
3964 | offsetof(CPUARMState, cp15.ttbr1_ns) } }, | |
cb2e37df PM |
3965 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, |
3966 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | |
84929218 RH |
3967 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3968 | .writefn = vmsa_tcr_el12_write, | |
cb2e37df | 3969 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, |
11f136ee | 3970 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, |
cb2e37df | 3971 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
84929218 RH |
3972 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3973 | .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, | |
b061a82b | 3974 | .raw_writefn = vmsa_ttbcr_raw_write, |
11f136ee FA |
3975 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), |
3976 | offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, | |
18032bec PM |
3977 | REGINFO_SENTINEL |
3978 | }; | |
3979 | ||
ab638a32 RH |
3980 | /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing |
3981 | * qemu tlbs nor adjusting cached masks. | |
3982 | */ | |
3983 | static const ARMCPRegInfo ttbcr2_reginfo = { | |
3984 | .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3, | |
84929218 RH |
3985 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3986 | .type = ARM_CP_ALIAS, | |
ab638a32 RH |
3987 | .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), |
3988 | offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, | |
3989 | }; | |
3990 | ||
c4241c7d PM |
3991 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3992 | uint64_t value) | |
1047b9d7 PM |
3993 | { |
3994 | env->cp15.c15_ticonfig = value & 0xe7; | |
3995 | /* The OS_TYPE bit in this register changes the reported CPUID! */ | |
3996 | env->cp15.c0_cpuid = (value & (1 << 5)) ? | |
3997 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1047b9d7 PM |
3998 | } |
3999 | ||
c4241c7d PM |
4000 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4001 | uint64_t value) | |
1047b9d7 PM |
4002 | { |
4003 | env->cp15.c15_threadid = value & 0xffff; | |
1047b9d7 PM |
4004 | } |
4005 | ||
c4241c7d PM |
4006 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4007 | uint64_t value) | |
1047b9d7 PM |
4008 | { |
4009 | /* Wait-for-interrupt (deprecated) */ | |
2fc0cc0e | 4010 | cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); |
1047b9d7 PM |
4011 | } |
4012 | ||
c4241c7d PM |
4013 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4014 | uint64_t value) | |
c4804214 PM |
4015 | { |
4016 | /* On OMAP there are registers indicating the max/min index of dcache lines | |
4017 | * containing a dirty line; cache flush operations have to reset these. | |
4018 | */ | |
4019 | env->cp15.c15_i_max = 0x000; | |
4020 | env->cp15.c15_i_min = 0xff0; | |
c4804214 PM |
4021 | } |
4022 | ||
18032bec PM |
4023 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
4024 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, | |
4025 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, | |
d81c519c | 4026 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 4027 | .resetvalue = 0, }, |
1047b9d7 PM |
4028 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
4029 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
4030 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
4031 | .access = PL1_RW, | |
4032 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, | |
4033 | .writefn = omap_ticonfig_write }, | |
4034 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, | |
4035 | .access = PL1_RW, | |
4036 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, | |
4037 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, | |
4038 | .access = PL1_RW, .resetvalue = 0xff0, | |
4039 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, | |
4040 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, | |
4041 | .access = PL1_RW, | |
4042 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, | |
4043 | .writefn = omap_threadid_write }, | |
4044 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, | |
4045 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
7a0e58fa | 4046 | .type = ARM_CP_NO_RAW, |
1047b9d7 PM |
4047 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
4048 | /* TODO: Peripheral port remap register: | |
4049 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller | |
4050 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), | |
4051 | * when MMU is off. | |
4052 | */ | |
c4804214 | 4053 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
d4e6df63 | 4054 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
7a0e58fa | 4055 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, |
c4804214 | 4056 | .writefn = omap_cachemaint_write }, |
34f90529 PM |
4057 | { .name = "C9", .cp = 15, .crn = 9, |
4058 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | |
4059 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | |
1047b9d7 PM |
4060 | REGINFO_SENTINEL |
4061 | }; | |
4062 | ||
c4241c7d PM |
4063 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4064 | uint64_t value) | |
1047b9d7 | 4065 | { |
c0f4af17 | 4066 | env->cp15.c15_cpar = value & 0x3fff; |
1047b9d7 PM |
4067 | } |
4068 | ||
4069 | static const ARMCPRegInfo xscale_cp_reginfo[] = { | |
4070 | { .name = "XSCALE_CPAR", | |
4071 | .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
4072 | .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, | |
4073 | .writefn = xscale_cpar_write, }, | |
2771db27 PM |
4074 | { .name = "XSCALE_AUXCR", |
4075 | .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, | |
4076 | .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), | |
4077 | .resetvalue = 0, }, | |
3b771579 PM |
4078 | /* XScale specific cache-lockdown: since we have no cache we NOP these |
4079 | * and hope the guest does not really rely on cache behaviour. | |
4080 | */ | |
4081 | { .name = "XSCALE_LOCK_ICACHE_LINE", | |
4082 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
4083 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4084 | { .name = "XSCALE_UNLOCK_ICACHE", | |
4085 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
4086 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4087 | { .name = "XSCALE_DCACHE_LOCK", | |
4088 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, | |
4089 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
4090 | { .name = "XSCALE_UNLOCK_DCACHE", | |
4091 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, | |
4092 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1047b9d7 PM |
4093 | REGINFO_SENTINEL |
4094 | }; | |
4095 | ||
4096 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | |
4097 | /* RAZ/WI the whole crn=15 space, when we don't have a more specific | |
4098 | * implementation of this implementation-defined space. | |
4099 | * Ideally this should eventually disappear in favour of actually | |
4100 | * implementing the correct behaviour for all cores. | |
4101 | */ | |
4102 | { .name = "C15_IMPDEF", .cp = 15, .crn = 15, | |
4103 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
3671cd87 | 4104 | .access = PL1_RW, |
7a0e58fa | 4105 | .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, |
d4e6df63 | 4106 | .resetvalue = 0 }, |
18032bec PM |
4107 | REGINFO_SENTINEL |
4108 | }; | |
4109 | ||
c4804214 PM |
4110 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
4111 | /* Cache status: RAZ because we have no cache so it's always clean */ | |
4112 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | |
7a0e58fa | 4113 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4114 | .resetvalue = 0 }, |
c4804214 PM |
4115 | REGINFO_SENTINEL |
4116 | }; | |
4117 | ||
4118 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | |
4119 | /* We never have a a block transfer operation in progress */ | |
4120 | { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, | |
7a0e58fa | 4121 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4122 | .resetvalue = 0 }, |
30b05bba PM |
4123 | /* The cache ops themselves: these all NOP for QEMU */ |
4124 | { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, | |
4125 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
4126 | { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, | |
4127 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
4128 | { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, | |
4129 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
4130 | { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, | |
4131 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
4132 | { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, | |
4133 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
4134 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, | |
4135 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
c4804214 PM |
4136 | REGINFO_SENTINEL |
4137 | }; | |
4138 | ||
4139 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | |
4140 | /* The cache test-and-clean instructions always return (1 << 30) | |
4141 | * to indicate that there are no dirty cache lines. | |
4142 | */ | |
4143 | { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, | |
7a0e58fa | 4144 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4145 | .resetvalue = (1 << 30) }, |
c4804214 | 4146 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
7a0e58fa | 4147 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4148 | .resetvalue = (1 << 30) }, |
c4804214 PM |
4149 | REGINFO_SENTINEL |
4150 | }; | |
4151 | ||
34f90529 PM |
4152 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
4153 | /* Ignore ReadBuffer accesses */ | |
4154 | { .name = "C9_READBUFFER", .cp = 15, .crn = 9, | |
4155 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
d4e6df63 | 4156 | .access = PL1_RW, .resetvalue = 0, |
7a0e58fa | 4157 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, |
34f90529 PM |
4158 | REGINFO_SENTINEL |
4159 | }; | |
4160 | ||
731de9e6 EI |
4161 | static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4162 | { | |
2fc0cc0e | 4163 | ARMCPU *cpu = env_archcpu(env); |
731de9e6 EI |
4164 | unsigned int cur_el = arm_current_el(env); |
4165 | bool secure = arm_is_secure(env); | |
4166 | ||
4167 | if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { | |
4168 | return env->cp15.vpidr_el2; | |
4169 | } | |
4170 | return raw_read(env, ri); | |
4171 | } | |
4172 | ||
06a7e647 | 4173 | static uint64_t mpidr_read_val(CPUARMState *env) |
81bdde9d | 4174 | { |
2fc0cc0e | 4175 | ARMCPU *cpu = env_archcpu(env); |
eb5e1d3c PF |
4176 | uint64_t mpidr = cpu->mp_affinity; |
4177 | ||
81bdde9d | 4178 | if (arm_feature(env, ARM_FEATURE_V7MP)) { |
78dbbbe4 | 4179 | mpidr |= (1U << 31); |
81bdde9d PM |
4180 | /* Cores which are uniprocessor (non-coherent) |
4181 | * but still implement the MP extensions set | |
a8e81b31 | 4182 | * bit 30. (For instance, Cortex-R5). |
81bdde9d | 4183 | */ |
a8e81b31 PC |
4184 | if (cpu->mp_is_up) { |
4185 | mpidr |= (1u << 30); | |
4186 | } | |
81bdde9d | 4187 | } |
c4241c7d | 4188 | return mpidr; |
81bdde9d PM |
4189 | } |
4190 | ||
06a7e647 EI |
4191 | static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4192 | { | |
f0d574d6 EI |
4193 | unsigned int cur_el = arm_current_el(env); |
4194 | bool secure = arm_is_secure(env); | |
4195 | ||
4196 | if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { | |
4197 | return env->cp15.vmpidr_el2; | |
4198 | } | |
06a7e647 EI |
4199 | return mpidr_read_val(env); |
4200 | } | |
4201 | ||
7ac681cf | 4202 | static const ARMCPRegInfo lpae_cp_reginfo[] = { |
a903c449 | 4203 | /* NOP AMAIR0/1 */ |
b0fe2427 PM |
4204 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, |
4205 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | |
84929218 RH |
4206 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4207 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b0fe2427 | 4208 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ |
7ac681cf | 4209 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
84929218 RH |
4210 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4211 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
891a2fe7 | 4212 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
01c097f7 FA |
4213 | .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, |
4214 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), | |
4215 | offsetof(CPUARMState, cp15.par_ns)} }, | |
891a2fe7 | 4216 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, |
84929218 RH |
4217 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4218 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
7dd8c9af FA |
4219 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
4220 | offsetof(CPUARMState, cp15.ttbr0_ns) }, | |
b061a82b | 4221 | .writefn = vmsa_ttbr_write, }, |
891a2fe7 | 4222 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
84929218 RH |
4223 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4224 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
7dd8c9af FA |
4225 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
4226 | offsetof(CPUARMState, cp15.ttbr1_ns) }, | |
b061a82b | 4227 | .writefn = vmsa_ttbr_write, }, |
7ac681cf PM |
4228 | REGINFO_SENTINEL |
4229 | }; | |
4230 | ||
c4241c7d | 4231 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 4232 | { |
c4241c7d | 4233 | return vfp_get_fpcr(env); |
b0d2b7d0 PM |
4234 | } |
4235 | ||
c4241c7d PM |
4236 | static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4237 | uint64_t value) | |
b0d2b7d0 PM |
4238 | { |
4239 | vfp_set_fpcr(env, value); | |
b0d2b7d0 PM |
4240 | } |
4241 | ||
c4241c7d | 4242 | static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 4243 | { |
c4241c7d | 4244 | return vfp_get_fpsr(env); |
b0d2b7d0 PM |
4245 | } |
4246 | ||
c4241c7d PM |
4247 | static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4248 | uint64_t value) | |
b0d2b7d0 PM |
4249 | { |
4250 | vfp_set_fpsr(env, value); | |
b0d2b7d0 PM |
4251 | } |
4252 | ||
3f208fd7 PM |
4253 | static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4254 | bool isread) | |
c2b820fe | 4255 | { |
aaec1432 | 4256 | if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { |
c2b820fe PM |
4257 | return CP_ACCESS_TRAP; |
4258 | } | |
4259 | return CP_ACCESS_OK; | |
4260 | } | |
4261 | ||
4262 | static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4263 | uint64_t value) | |
4264 | { | |
4265 | env->daif = value & PSTATE_DAIF; | |
4266 | } | |
4267 | ||
220f508f RH |
4268 | static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4269 | { | |
4270 | return env->pstate & PSTATE_PAN; | |
4271 | } | |
4272 | ||
4273 | static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4274 | uint64_t value) | |
4275 | { | |
4276 | env->pstate = (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN); | |
4277 | } | |
4278 | ||
4279 | static const ARMCPRegInfo pan_reginfo = { | |
4280 | .name = "PAN", .state = ARM_CP_STATE_AA64, | |
4281 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 3, | |
4282 | .type = ARM_CP_NO_RAW, .access = PL1_RW, | |
4283 | .readfn = aa64_pan_read, .writefn = aa64_pan_write | |
4284 | }; | |
4285 | ||
9eeb7a1c RH |
4286 | static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4287 | { | |
4288 | return env->pstate & PSTATE_UAO; | |
4289 | } | |
4290 | ||
4291 | static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4292 | uint64_t value) | |
4293 | { | |
4294 | env->pstate = (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO); | |
4295 | } | |
4296 | ||
4297 | static const ARMCPRegInfo uao_reginfo = { | |
4298 | .name = "UAO", .state = ARM_CP_STATE_AA64, | |
4299 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4, | |
4300 | .type = ARM_CP_NO_RAW, .access = PL1_RW, | |
4301 | .readfn = aa64_uao_read, .writefn = aa64_uao_write | |
4302 | }; | |
4303 | ||
8af35c37 | 4304 | static CPAccessResult aa64_cacheop_access(CPUARMState *env, |
3f208fd7 PM |
4305 | const ARMCPRegInfo *ri, |
4306 | bool isread) | |
8af35c37 PM |
4307 | { |
4308 | /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless | |
4309 | * SCTLR_EL1.UCI is set. | |
4310 | */ | |
aaec1432 | 4311 | if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UCI)) { |
8af35c37 PM |
4312 | return CP_ACCESS_TRAP; |
4313 | } | |
4314 | return CP_ACCESS_OK; | |
4315 | } | |
4316 | ||
1bed4d2e RH |
4317 | static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, |
4318 | const ARMCPRegInfo *ri, | |
4319 | bool isread) | |
4320 | { | |
4321 | /* Cache invalidate/clean to Point of Coherency or Persistence... */ | |
4322 | switch (arm_current_el(env)) { | |
4323 | case 0: | |
4324 | /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ | |
4325 | if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { | |
4326 | return CP_ACCESS_TRAP; | |
4327 | } | |
4328 | /* fall through */ | |
4329 | case 1: | |
4330 | /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */ | |
4331 | if (arm_hcr_el2_eff(env) & HCR_TPCP) { | |
4332 | return CP_ACCESS_TRAP_EL2; | |
4333 | } | |
4334 | break; | |
4335 | } | |
4336 | return CP_ACCESS_OK; | |
4337 | } | |
4338 | ||
dbb1fb27 AB |
4339 | /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions |
4340 | * Page D4-1736 (DDI0487A.b) | |
4341 | */ | |
4342 | ||
b7e0730d RH |
4343 | static int vae1_tlbmask(CPUARMState *env) |
4344 | { | |
85d0dc9f | 4345 | /* Since we exclude secure first, we may read HCR_EL2 directly. */ |
b7e0730d | 4346 | if (arm_is_secure_below_el3(env)) { |
452ef8cb RH |
4347 | return ARMMMUIdxBit_SE10_1 | |
4348 | ARMMMUIdxBit_SE10_1_PAN | | |
4349 | ARMMMUIdxBit_SE10_0; | |
85d0dc9f RH |
4350 | } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) |
4351 | == (HCR_E2H | HCR_TGE)) { | |
452ef8cb RH |
4352 | return ARMMMUIdxBit_E20_2 | |
4353 | ARMMMUIdxBit_E20_2_PAN | | |
4354 | ARMMMUIdxBit_E20_0; | |
b7e0730d | 4355 | } else { |
452ef8cb RH |
4356 | return ARMMMUIdxBit_E10_1 | |
4357 | ARMMMUIdxBit_E10_1_PAN | | |
4358 | ARMMMUIdxBit_E10_0; | |
b7e0730d RH |
4359 | } |
4360 | } | |
4361 | ||
fd3ed969 PM |
4362 | static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4363 | uint64_t value) | |
168aa23b | 4364 | { |
29a0af61 | 4365 | CPUState *cs = env_cpu(env); |
b7e0730d | 4366 | int mask = vae1_tlbmask(env); |
dbb1fb27 | 4367 | |
b7e0730d | 4368 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
168aa23b PM |
4369 | } |
4370 | ||
b4ab8ce9 PM |
4371 | static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4372 | uint64_t value) | |
4373 | { | |
29a0af61 | 4374 | CPUState *cs = env_cpu(env); |
b7e0730d | 4375 | int mask = vae1_tlbmask(env); |
b4ab8ce9 PM |
4376 | |
4377 | if (tlb_force_broadcast(env)) { | |
527db2be RH |
4378 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
4379 | } else { | |
4380 | tlb_flush_by_mmuidx(cs, mask); | |
b4ab8ce9 | 4381 | } |
b4ab8ce9 PM |
4382 | } |
4383 | ||
90c19cdf | 4384 | static int alle1_tlbmask(CPUARMState *env) |
168aa23b | 4385 | { |
90c19cdf RH |
4386 | /* |
4387 | * Note that the 'ALL' scope must invalidate both stage 1 and | |
fd3ed969 PM |
4388 | * stage 2 translations, whereas most other scopes only invalidate |
4389 | * stage 1 translations. | |
4390 | */ | |
fd3ed969 | 4391 | if (arm_is_secure_below_el3(env)) { |
452ef8cb RH |
4392 | return ARMMMUIdxBit_SE10_1 | |
4393 | ARMMMUIdxBit_SE10_1_PAN | | |
4394 | ARMMMUIdxBit_SE10_0; | |
90c19cdf | 4395 | } else if (arm_feature(env, ARM_FEATURE_EL2)) { |
452ef8cb RH |
4396 | return ARMMMUIdxBit_E10_1 | |
4397 | ARMMMUIdxBit_E10_1_PAN | | |
4398 | ARMMMUIdxBit_E10_0 | | |
4399 | ARMMMUIdxBit_Stage2; | |
fd3ed969 | 4400 | } else { |
452ef8cb RH |
4401 | return ARMMMUIdxBit_E10_1 | |
4402 | ARMMMUIdxBit_E10_1_PAN | | |
4403 | ARMMMUIdxBit_E10_0; | |
fd3ed969 | 4404 | } |
168aa23b PM |
4405 | } |
4406 | ||
85d0dc9f RH |
4407 | static int e2_tlbmask(CPUARMState *env) |
4408 | { | |
4409 | /* TODO: ARMv8.4-SecEL2 */ | |
452ef8cb RH |
4410 | return ARMMMUIdxBit_E20_0 | |
4411 | ARMMMUIdxBit_E20_2 | | |
4412 | ARMMMUIdxBit_E20_2_PAN | | |
4413 | ARMMMUIdxBit_E2; | |
85d0dc9f RH |
4414 | } |
4415 | ||
90c19cdf RH |
4416 | static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4417 | uint64_t value) | |
4418 | { | |
4419 | CPUState *cs = env_cpu(env); | |
4420 | int mask = alle1_tlbmask(env); | |
4421 | ||
4422 | tlb_flush_by_mmuidx(cs, mask); | |
4423 | } | |
4424 | ||
fd3ed969 | 4425 | static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
fa439fc5 PM |
4426 | uint64_t value) |
4427 | { | |
85d0dc9f RH |
4428 | CPUState *cs = env_cpu(env); |
4429 | int mask = e2_tlbmask(env); | |
fd3ed969 | 4430 | |
85d0dc9f | 4431 | tlb_flush_by_mmuidx(cs, mask); |
fd3ed969 PM |
4432 | } |
4433 | ||
43efaa33 PM |
4434 | static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4435 | uint64_t value) | |
4436 | { | |
2fc0cc0e | 4437 | ARMCPU *cpu = env_archcpu(env); |
43efaa33 PM |
4438 | CPUState *cs = CPU(cpu); |
4439 | ||
127b2b08 | 4440 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3); |
43efaa33 PM |
4441 | } |
4442 | ||
fd3ed969 PM |
4443 | static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4444 | uint64_t value) | |
4445 | { | |
29a0af61 | 4446 | CPUState *cs = env_cpu(env); |
90c19cdf RH |
4447 | int mask = alle1_tlbmask(env); |
4448 | ||
4449 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); | |
fa439fc5 PM |
4450 | } |
4451 | ||
2bfb9d75 PM |
4452 | static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4453 | uint64_t value) | |
4454 | { | |
29a0af61 | 4455 | CPUState *cs = env_cpu(env); |
85d0dc9f | 4456 | int mask = e2_tlbmask(env); |
2bfb9d75 | 4457 | |
85d0dc9f | 4458 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
2bfb9d75 PM |
4459 | } |
4460 | ||
43efaa33 PM |
4461 | static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4462 | uint64_t value) | |
4463 | { | |
29a0af61 | 4464 | CPUState *cs = env_cpu(env); |
43efaa33 | 4465 | |
127b2b08 | 4466 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3); |
43efaa33 PM |
4467 | } |
4468 | ||
fd3ed969 PM |
4469 | static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4470 | uint64_t value) | |
fa439fc5 | 4471 | { |
fd3ed969 PM |
4472 | /* Invalidate by VA, EL2 |
4473 | * Currently handles both VAE2 and VALE2, since we don't support | |
4474 | * flush-last-level-only. | |
4475 | */ | |
85d0dc9f RH |
4476 | CPUState *cs = env_cpu(env); |
4477 | int mask = e2_tlbmask(env); | |
fd3ed969 PM |
4478 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
4479 | ||
85d0dc9f | 4480 | tlb_flush_page_by_mmuidx(cs, pageaddr, mask); |
fd3ed969 PM |
4481 | } |
4482 | ||
43efaa33 PM |
4483 | static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4484 | uint64_t value) | |
4485 | { | |
4486 | /* Invalidate by VA, EL3 | |
4487 | * Currently handles both VAE3 and VALE3, since we don't support | |
4488 | * flush-last-level-only. | |
4489 | */ | |
2fc0cc0e | 4490 | ARMCPU *cpu = env_archcpu(env); |
43efaa33 PM |
4491 | CPUState *cs = CPU(cpu); |
4492 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
4493 | ||
127b2b08 | 4494 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3); |
43efaa33 PM |
4495 | } |
4496 | ||
fd3ed969 PM |
4497 | static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4498 | uint64_t value) | |
4499 | { | |
90c19cdf RH |
4500 | CPUState *cs = env_cpu(env); |
4501 | int mask = vae1_tlbmask(env); | |
fa439fc5 PM |
4502 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
4503 | ||
90c19cdf | 4504 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); |
fa439fc5 PM |
4505 | } |
4506 | ||
b4ab8ce9 PM |
4507 | static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4508 | uint64_t value) | |
4509 | { | |
4510 | /* Invalidate by VA, EL1&0 (AArch64 version). | |
4511 | * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, | |
4512 | * since we don't support flush-for-specific-ASID-only or | |
4513 | * flush-last-level-only. | |
4514 | */ | |
90c19cdf RH |
4515 | CPUState *cs = env_cpu(env); |
4516 | int mask = vae1_tlbmask(env); | |
b4ab8ce9 PM |
4517 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
4518 | ||
4519 | if (tlb_force_broadcast(env)) { | |
527db2be RH |
4520 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); |
4521 | } else { | |
4522 | tlb_flush_page_by_mmuidx(cs, pageaddr, mask); | |
b4ab8ce9 | 4523 | } |
b4ab8ce9 PM |
4524 | } |
4525 | ||
fd3ed969 PM |
4526 | static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4527 | uint64_t value) | |
fa439fc5 | 4528 | { |
29a0af61 | 4529 | CPUState *cs = env_cpu(env); |
fd3ed969 | 4530 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
fa439fc5 | 4531 | |
a67cf277 | 4532 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
e013b741 | 4533 | ARMMMUIdxBit_E2); |
fa439fc5 PM |
4534 | } |
4535 | ||
43efaa33 PM |
4536 | static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4537 | uint64_t value) | |
4538 | { | |
29a0af61 | 4539 | CPUState *cs = env_cpu(env); |
43efaa33 PM |
4540 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
4541 | ||
a67cf277 | 4542 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
127b2b08 | 4543 | ARMMMUIdxBit_SE3); |
43efaa33 PM |
4544 | } |
4545 | ||
cea66e91 PM |
4546 | static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4547 | uint64_t value) | |
4548 | { | |
4549 | /* Invalidate by IPA. This has to invalidate any structures that | |
4550 | * contain only stage 2 translation information, but does not need | |
4551 | * to apply to structures that contain combined stage 1 and stage 2 | |
4552 | * translation information. | |
4553 | * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. | |
4554 | */ | |
2fc0cc0e | 4555 | ARMCPU *cpu = env_archcpu(env); |
cea66e91 PM |
4556 | CPUState *cs = CPU(cpu); |
4557 | uint64_t pageaddr; | |
4558 | ||
4559 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
4560 | return; | |
4561 | } | |
4562 | ||
4563 | pageaddr = sextract64(value << 12, 0, 48); | |
4564 | ||
97fa9350 | 4565 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2); |
cea66e91 PM |
4566 | } |
4567 | ||
4568 | static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4569 | uint64_t value) | |
4570 | { | |
29a0af61 | 4571 | CPUState *cs = env_cpu(env); |
cea66e91 PM |
4572 | uint64_t pageaddr; |
4573 | ||
4574 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
4575 | return; | |
4576 | } | |
4577 | ||
4578 | pageaddr = sextract64(value << 12, 0, 48); | |
4579 | ||
a67cf277 | 4580 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
97fa9350 | 4581 | ARMMMUIdxBit_Stage2); |
cea66e91 PM |
4582 | } |
4583 | ||
3f208fd7 PM |
4584 | static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4585 | bool isread) | |
aca3f40b | 4586 | { |
4351cb72 RH |
4587 | int cur_el = arm_current_el(env); |
4588 | ||
4589 | if (cur_el < 2) { | |
4590 | uint64_t hcr = arm_hcr_el2_eff(env); | |
4591 | ||
4592 | if (cur_el == 0) { | |
4593 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
4594 | if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) { | |
4595 | return CP_ACCESS_TRAP_EL2; | |
4596 | } | |
4597 | } else { | |
4598 | if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) { | |
4599 | return CP_ACCESS_TRAP; | |
4600 | } | |
4601 | if (hcr & HCR_TDZ) { | |
4602 | return CP_ACCESS_TRAP_EL2; | |
4603 | } | |
4604 | } | |
4605 | } else if (hcr & HCR_TDZ) { | |
4606 | return CP_ACCESS_TRAP_EL2; | |
4607 | } | |
aca3f40b PM |
4608 | } |
4609 | return CP_ACCESS_OK; | |
4610 | } | |
4611 | ||
4612 | static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
4613 | { | |
2fc0cc0e | 4614 | ARMCPU *cpu = env_archcpu(env); |
aca3f40b PM |
4615 | int dzp_bit = 1 << 4; |
4616 | ||
4617 | /* DZP indicates whether DC ZVA access is allowed */ | |
3f208fd7 | 4618 | if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) { |
aca3f40b PM |
4619 | dzp_bit = 0; |
4620 | } | |
4621 | return cpu->dcz_blocksize | dzp_bit; | |
4622 | } | |
4623 | ||
3f208fd7 PM |
4624 | static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4625 | bool isread) | |
f502cfc2 | 4626 | { |
cdcf1405 | 4627 | if (!(env->pstate & PSTATE_SP)) { |
f502cfc2 PM |
4628 | /* Access to SP_EL0 is undefined if it's being used as |
4629 | * the stack pointer. | |
4630 | */ | |
4631 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
4632 | } | |
4633 | return CP_ACCESS_OK; | |
4634 | } | |
4635 | ||
4636 | static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
4637 | { | |
4638 | return env->pstate & PSTATE_SP; | |
4639 | } | |
4640 | ||
4641 | static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
4642 | { | |
4643 | update_spsel(env, val); | |
4644 | } | |
4645 | ||
137feaa9 FA |
4646 | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4647 | uint64_t value) | |
4648 | { | |
2fc0cc0e | 4649 | ARMCPU *cpu = env_archcpu(env); |
137feaa9 FA |
4650 | |
4651 | if (raw_read(env, ri) == value) { | |
4652 | /* Skip the TLB flush if nothing actually changed; Linux likes | |
4653 | * to do a lot of pointless SCTLR writes. | |
4654 | */ | |
4655 | return; | |
4656 | } | |
4657 | ||
06312feb PM |
4658 | if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { |
4659 | /* M bit is RAZ/WI for PMSA with no MPU implemented */ | |
4660 | value &= ~SCTLR_M; | |
4661 | } | |
4662 | ||
137feaa9 FA |
4663 | raw_write(env, ri, value); |
4664 | /* ??? Lots of these bits are not implemented. */ | |
4665 | /* This may enable/disable the MMU, so do a TLB flush. */ | |
d10eb08f | 4666 | tlb_flush(CPU(cpu)); |
2e5dcf36 RH |
4667 | |
4668 | if (ri->type & ARM_CP_SUPPRESS_TB_END) { | |
4669 | /* | |
4670 | * Normally we would always end the TB on an SCTLR write; see the | |
4671 | * comment in ARMCPRegInfo sctlr initialization below for why Xscale | |
4672 | * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild | |
4673 | * of hflags from the translator, so do it here. | |
4674 | */ | |
4675 | arm_rebuild_hflags(env); | |
4676 | } | |
137feaa9 FA |
4677 | } |
4678 | ||
3f208fd7 PM |
4679 | static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4680 | bool isread) | |
03fbf20f PM |
4681 | { |
4682 | if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { | |
f2cae609 | 4683 | return CP_ACCESS_TRAP_FP_EL2; |
03fbf20f PM |
4684 | } |
4685 | if (env->cp15.cptr_el[3] & CPTR_TFP) { | |
f2cae609 | 4686 | return CP_ACCESS_TRAP_FP_EL3; |
03fbf20f PM |
4687 | } |
4688 | return CP_ACCESS_OK; | |
4689 | } | |
4690 | ||
a8d64e73 PM |
4691 | static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4692 | uint64_t value) | |
4693 | { | |
4694 | env->cp15.mdcr_el3 = value & SDCR_VALID_MASK; | |
4695 | } | |
4696 | ||
b0d2b7d0 PM |
4697 | static const ARMCPRegInfo v8_cp_reginfo[] = { |
4698 | /* Minimal set of EL0-visible registers. This will need to be expanded | |
4699 | * significantly for system emulation of AArch64 CPUs. | |
4700 | */ | |
4701 | { .name = "NZCV", .state = ARM_CP_STATE_AA64, | |
4702 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, | |
4703 | .access = PL0_RW, .type = ARM_CP_NZCV }, | |
c2b820fe PM |
4704 | { .name = "DAIF", .state = ARM_CP_STATE_AA64, |
4705 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, | |
7a0e58fa | 4706 | .type = ARM_CP_NO_RAW, |
c2b820fe PM |
4707 | .access = PL0_RW, .accessfn = aa64_daif_access, |
4708 | .fieldoffset = offsetof(CPUARMState, daif), | |
4709 | .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, | |
b0d2b7d0 PM |
4710 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, |
4711 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | |
b916c9c3 | 4712 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 4713 | .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, |
b0d2b7d0 PM |
4714 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, |
4715 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | |
b916c9c3 | 4716 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 4717 | .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, |
b0d2b7d0 PM |
4718 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, |
4719 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | |
7a0e58fa | 4720 | .access = PL0_R, .type = ARM_CP_NO_RAW, |
aca3f40b PM |
4721 | .readfn = aa64_dczid_read }, |
4722 | { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, | |
4723 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, | |
4724 | .access = PL0_W, .type = ARM_CP_DC_ZVA, | |
4725 | #ifndef CONFIG_USER_ONLY | |
4726 | /* Avoid overhead of an access check that always passes in user-mode */ | |
4727 | .accessfn = aa64_zva_access, | |
4728 | #endif | |
4729 | }, | |
0eef9d98 PM |
4730 | { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, |
4731 | .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, | |
4732 | .access = PL1_R, .type = ARM_CP_CURRENTEL }, | |
8af35c37 PM |
4733 | /* Cache ops: all NOPs since we don't emulate caches */ |
4734 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, | |
4735 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
4736 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4737 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, | |
4738 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
4739 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4740 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, | |
4741 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | |
4742 | .access = PL0_W, .type = ARM_CP_NOP, | |
4743 | .accessfn = aa64_cacheop_access }, | |
4744 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, | |
4745 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
1bed4d2e RH |
4746 | .access = PL1_W, .accessfn = aa64_cacheop_poc_access, |
4747 | .type = ARM_CP_NOP }, | |
8af35c37 PM |
4748 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, |
4749 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
1803d271 | 4750 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
8af35c37 PM |
4751 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, |
4752 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | |
4753 | .access = PL0_W, .type = ARM_CP_NOP, | |
1bed4d2e | 4754 | .accessfn = aa64_cacheop_poc_access }, |
8af35c37 PM |
4755 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, |
4756 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
1803d271 | 4757 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
8af35c37 PM |
4758 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, |
4759 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | |
4760 | .access = PL0_W, .type = ARM_CP_NOP, | |
4761 | .accessfn = aa64_cacheop_access }, | |
4762 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, | |
4763 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | |
4764 | .access = PL0_W, .type = ARM_CP_NOP, | |
1bed4d2e | 4765 | .accessfn = aa64_cacheop_poc_access }, |
8af35c37 PM |
4766 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, |
4767 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
1803d271 | 4768 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
168aa23b PM |
4769 | /* TLBI operations */ |
4770 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 4771 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, |
7a0e58fa | 4772 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4773 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 4774 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4775 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
7a0e58fa | 4776 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4777 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4778 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4779 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
7a0e58fa | 4780 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4781 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 4782 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4783 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
7a0e58fa | 4784 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4785 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4786 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4787 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
7a0e58fa | 4788 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4789 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4790 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4791 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
7a0e58fa | 4792 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4793 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4794 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4795 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, |
7a0e58fa | 4796 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4797 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 4798 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4799 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
7a0e58fa | 4800 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4801 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4802 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4803 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
7a0e58fa | 4804 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4805 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 4806 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4807 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
7a0e58fa | 4808 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4809 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4810 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4811 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
7a0e58fa | 4812 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4813 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4814 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4815 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
7a0e58fa | 4816 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4817 | .writefn = tlbi_aa64_vae1_write }, |
cea66e91 PM |
4818 | { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, |
4819 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
4820 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4821 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
4822 | { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, | |
4823 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
4824 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4825 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
83ddf975 PM |
4826 | { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, |
4827 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
4828 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 4829 | .writefn = tlbi_aa64_alle1is_write }, |
43efaa33 PM |
4830 | { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, |
4831 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, | |
4832 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4833 | .writefn = tlbi_aa64_alle1is_write }, | |
cea66e91 PM |
4834 | { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, |
4835 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
4836 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4837 | .writefn = tlbi_aa64_ipas2e1_write }, | |
4838 | { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, | |
4839 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
4840 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4841 | .writefn = tlbi_aa64_ipas2e1_write }, | |
83ddf975 PM |
4842 | { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, |
4843 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
4844 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 4845 | .writefn = tlbi_aa64_alle1_write }, |
43efaa33 PM |
4846 | { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, |
4847 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, | |
4848 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4849 | .writefn = tlbi_aa64_alle1is_write }, | |
19525524 PM |
4850 | #ifndef CONFIG_USER_ONLY |
4851 | /* 64 bit address translation operations */ | |
4852 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
4853 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, | |
0710b2fa PM |
4854 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4855 | .writefn = ats_write64 }, | |
19525524 PM |
4856 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, |
4857 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, | |
0710b2fa PM |
4858 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4859 | .writefn = ats_write64 }, | |
19525524 PM |
4860 | { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, |
4861 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, | |
0710b2fa PM |
4862 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4863 | .writefn = ats_write64 }, | |
19525524 PM |
4864 | { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, |
4865 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, | |
0710b2fa PM |
4866 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4867 | .writefn = ats_write64 }, | |
2a47df95 | 4868 | { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4869 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, |
0710b2fa PM |
4870 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4871 | .writefn = ats_write64 }, | |
2a47df95 | 4872 | { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4873 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, |
0710b2fa PM |
4874 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4875 | .writefn = ats_write64 }, | |
2a47df95 | 4876 | { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4877 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, |
0710b2fa PM |
4878 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4879 | .writefn = ats_write64 }, | |
2a47df95 | 4880 | { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4881 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, |
0710b2fa PM |
4882 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4883 | .writefn = ats_write64 }, | |
2a47df95 PM |
4884 | /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ |
4885 | { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, | |
4886 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, | |
0710b2fa PM |
4887 | .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4888 | .writefn = ats_write64 }, | |
2a47df95 PM |
4889 | { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, |
4890 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, | |
0710b2fa PM |
4891 | .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4892 | .writefn = ats_write64 }, | |
c96fc9b5 EI |
4893 | { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, |
4894 | .type = ARM_CP_ALIAS, | |
4895 | .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, | |
4896 | .access = PL1_RW, .resetvalue = 0, | |
4897 | .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), | |
4898 | .writefn = par_write }, | |
19525524 | 4899 | #endif |
995939a6 | 4900 | /* TLB invalidate last level of translation table walk */ |
9449fdf6 | 4901 | { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
7a0e58fa | 4902 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, |
9449fdf6 | 4903 | { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
7a0e58fa | 4904 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 4905 | .writefn = tlbimvaa_is_write }, |
9449fdf6 | 4906 | { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
7a0e58fa | 4907 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
9449fdf6 | 4908 | { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
7a0e58fa | 4909 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, |
541ef8c2 SS |
4910 | { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, |
4911 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4912 | .writefn = tlbimva_hyp_write }, | |
4913 | { .name = "TLBIMVALHIS", | |
4914 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
4915 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4916 | .writefn = tlbimva_hyp_is_write }, | |
4917 | { .name = "TLBIIPAS2", | |
4918 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
4919 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4920 | .writefn = tlbiipas2_write }, | |
4921 | { .name = "TLBIIPAS2IS", | |
4922 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
4923 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4924 | .writefn = tlbiipas2_is_write }, | |
4925 | { .name = "TLBIIPAS2L", | |
4926 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
4927 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4928 | .writefn = tlbiipas2_write }, | |
4929 | { .name = "TLBIIPAS2LIS", | |
4930 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
4931 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4932 | .writefn = tlbiipas2_is_write }, | |
9449fdf6 PM |
4933 | /* 32 bit cache operations */ |
4934 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
4935 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4936 | { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, | |
4937 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4938 | { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
4939 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4940 | { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, | |
4941 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4942 | { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, | |
4943 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4944 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | |
4945 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4946 | { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
1bed4d2e | 4947 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 4948 | { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, |
1803d271 | 4949 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 4950 | { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, |
1bed4d2e | 4951 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 4952 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, |
1803d271 | 4953 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 PM |
4954 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, |
4955 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4956 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, | |
1bed4d2e | 4957 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 4958 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, |
1803d271 | 4959 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 4960 | /* MMU Domain access control / MPU write buffer control */ |
0c17d68c | 4961 | { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, |
84929218 | 4962 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
0c17d68c FA |
4963 | .writefn = dacr_write, .raw_writefn = raw_write, |
4964 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
4965 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a0618a19 | 4966 | { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4967 | .type = ARM_CP_ALIAS, |
a0618a19 | 4968 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, |
6947f059 EI |
4969 | .access = PL1_RW, |
4970 | .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, | |
a65f1de9 | 4971 | { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4972 | .type = ARM_CP_ALIAS, |
a65f1de9 | 4973 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
4974 | .access = PL1_RW, |
4975 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, | |
f502cfc2 PM |
4976 | /* We rely on the access checks not allowing the guest to write to the |
4977 | * state field when SPSel indicates that it's being used as the stack | |
4978 | * pointer. | |
4979 | */ | |
4980 | { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, | |
4981 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, | |
4982 | .access = PL1_RW, .accessfn = sp_el0_access, | |
7a0e58fa | 4983 | .type = ARM_CP_ALIAS, |
f502cfc2 | 4984 | .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, |
884b4dee GB |
4985 | { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, |
4986 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 4987 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
884b4dee | 4988 | .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, |
f502cfc2 PM |
4989 | { .name = "SPSel", .state = ARM_CP_STATE_AA64, |
4990 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, | |
7a0e58fa | 4991 | .type = ARM_CP_NO_RAW, |
f502cfc2 | 4992 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, |
03fbf20f PM |
4993 | { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, |
4994 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, | |
4995 | .type = ARM_CP_ALIAS, | |
4996 | .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), | |
4997 | .access = PL2_RW, .accessfn = fpexc32_access }, | |
6a43e0b6 PM |
4998 | { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, |
4999 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, | |
5000 | .access = PL2_RW, .resetvalue = 0, | |
5001 | .writefn = dacr_write, .raw_writefn = raw_write, | |
5002 | .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, | |
5003 | { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, | |
5004 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, | |
5005 | .access = PL2_RW, .resetvalue = 0, | |
5006 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, | |
5007 | { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, | |
5008 | .type = ARM_CP_ALIAS, | |
5009 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, | |
5010 | .access = PL2_RW, | |
5011 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, | |
5012 | { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, | |
5013 | .type = ARM_CP_ALIAS, | |
5014 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, | |
5015 | .access = PL2_RW, | |
5016 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, | |
5017 | { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, | |
5018 | .type = ARM_CP_ALIAS, | |
5019 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, | |
5020 | .access = PL2_RW, | |
5021 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, | |
5022 | { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, | |
5023 | .type = ARM_CP_ALIAS, | |
5024 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, | |
5025 | .access = PL2_RW, | |
5026 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, | |
a8d64e73 PM |
5027 | { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, |
5028 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, | |
5029 | .resetvalue = 0, | |
5030 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) }, | |
5031 | { .name = "SDCR", .type = ARM_CP_ALIAS, | |
5032 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1, | |
5033 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, | |
5034 | .writefn = sdcr_write, | |
5035 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, | |
b0d2b7d0 PM |
5036 | REGINFO_SENTINEL |
5037 | }; | |
5038 | ||
d42e3c26 | 5039 | /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ |
4771cd01 | 5040 | static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { |
d79e0c06 | 5041 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, |
d42e3c26 EI |
5042 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, |
5043 | .access = PL2_RW, | |
5044 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | |
ce4afed8 | 5045 | { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH, |
7a0e58fa | 5046 | .type = ARM_CP_NO_RAW, |
f149e3e8 EI |
5047 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
5048 | .access = PL2_RW, | |
ce4afed8 | 5049 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
831a2fca PM |
5050 | { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, |
5051 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, | |
5052 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
68e78e33 PM |
5053 | { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, |
5054 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, | |
5055 | .access = PL2_RW, | |
5056 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
c6f19164 GB |
5057 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
5058 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
5059 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
95f949ac EI |
5060 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
5061 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
5062 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5063 | .resetvalue = 0 }, | |
5064 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
b5ede85b | 5065 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, |
95f949ac | 5066 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
2179ef95 PM |
5067 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
5068 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
5069 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5070 | .resetvalue = 0 }, | |
55b53c71 | 5071 | { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, |
b5ede85b | 5072 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, |
2179ef95 PM |
5073 | .access = PL2_RW, .type = ARM_CP_CONST, |
5074 | .resetvalue = 0 }, | |
37cd6c24 PM |
5075 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
5076 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
5077 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5078 | .resetvalue = 0 }, | |
5079 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
5080 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
5081 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5082 | .resetvalue = 0 }, | |
06ec4c8c EI |
5083 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
5084 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
5085 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
68e9c2fe EI |
5086 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH, |
5087 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
5088 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
5089 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b698e9cf EI |
5090 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
5091 | .cp = 15, .opc1 = 6, .crm = 2, | |
5092 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
5093 | .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | |
5094 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
5095 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
5096 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b9cb5323 EI |
5097 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
5098 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
5099 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
ff05f37b EI |
5100 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
5101 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
5102 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
a57633c0 EI |
5103 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
5104 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
5105 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5106 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
5107 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
5108 | .resetvalue = 0 }, | |
0b6440af EI |
5109 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
5110 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
5111 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
edac4d8a EI |
5112 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
5113 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
5114 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5115 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
5116 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
5117 | .resetvalue = 0 }, | |
b0e66d95 EI |
5118 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
5119 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
5120 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5121 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
5122 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
5123 | .resetvalue = 0 }, | |
5124 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
5125 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
5126 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5127 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
5128 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
5129 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
14cc7b54 SF |
5130 | { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, |
5131 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | |
d6c8cf81 PM |
5132 | .access = PL2_RW, .accessfn = access_tda, |
5133 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
59e05530 EI |
5134 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, |
5135 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
5136 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
5137 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2a5a9abd AF |
5138 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
5139 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
5140 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
cba517c3 PM |
5141 | { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, |
5142 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, | |
5143 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5144 | { .name = "HIFAR", .state = ARM_CP_STATE_AA32, | |
5145 | .type = ARM_CP_CONST, | |
5146 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | |
5147 | .access = PL2_RW, .resetvalue = 0 }, | |
d42e3c26 EI |
5148 | REGINFO_SENTINEL |
5149 | }; | |
5150 | ||
ce4afed8 PM |
5151 | /* Ditto, but for registers which exist in ARMv8 but not v7 */ |
5152 | static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { | |
5153 | { .name = "HCR2", .state = ARM_CP_STATE_AA32, | |
5154 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, | |
5155 | .access = PL2_RW, | |
5156 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5157 | REGINFO_SENTINEL | |
5158 | }; | |
5159 | ||
d1fb4da2 | 5160 | static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) |
f149e3e8 | 5161 | { |
2fc0cc0e | 5162 | ARMCPU *cpu = env_archcpu(env); |
d1fb4da2 RH |
5163 | |
5164 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
5165 | valid_mask |= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */ | |
5166 | } else { | |
5167 | valid_mask |= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */ | |
5168 | } | |
f149e3e8 EI |
5169 | |
5170 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
5171 | valid_mask &= ~HCR_HCD; | |
77077a83 JK |
5172 | } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { |
5173 | /* Architecturally HCR.TSC is RES0 if EL3 is not implemented. | |
5174 | * However, if we're using the SMC PSCI conduit then QEMU is | |
5175 | * effectively acting like EL3 firmware and so the guest at | |
5176 | * EL2 should retain the ability to prevent EL1 from being | |
5177 | * able to make SMC calls into the ersatz firmware, so in | |
5178 | * that case HCR.TSC should be read/write. | |
5179 | */ | |
f149e3e8 EI |
5180 | valid_mask &= ~HCR_TSC; |
5181 | } | |
d1fb4da2 RH |
5182 | |
5183 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
5184 | if (cpu_isar_feature(aa64_vh, cpu)) { | |
5185 | valid_mask |= HCR_E2H; | |
5186 | } | |
5187 | if (cpu_isar_feature(aa64_lor, cpu)) { | |
5188 | valid_mask |= HCR_TLOR; | |
5189 | } | |
5190 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
5191 | valid_mask |= HCR_API | HCR_APK; | |
5192 | } | |
ef682cdb | 5193 | } |
f149e3e8 EI |
5194 | |
5195 | /* Clear RES0 bits. */ | |
5196 | value &= valid_mask; | |
5197 | ||
5198 | /* These bits change the MMU setup: | |
5199 | * HCR_VM enables stage 2 translation | |
5200 | * HCR_PTW forbids certain page-table setups | |
5201 | * HCR_DC Disables stage1 and enables stage2 translation | |
5202 | */ | |
ce4afed8 | 5203 | if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { |
d10eb08f | 5204 | tlb_flush(CPU(cpu)); |
f149e3e8 | 5205 | } |
ce4afed8 | 5206 | env->cp15.hcr_el2 = value; |
89430fc6 PM |
5207 | |
5208 | /* | |
5209 | * Updates to VI and VF require us to update the status of | |
5210 | * virtual interrupts, which are the logical OR of these bits | |
5211 | * and the state of the input lines from the GIC. (This requires | |
5212 | * that we have the iothread lock, which is done by marking the | |
5213 | * reginfo structs as ARM_CP_IO.) | |
5214 | * Note that if a write to HCR pends a VIRQ or VFIQ it is never | |
5215 | * possible for it to be taken immediately, because VIRQ and | |
5216 | * VFIQ are masked unless running at EL0 or EL1, and HCR | |
5217 | * can only be written at EL2. | |
5218 | */ | |
5219 | g_assert(qemu_mutex_iothread_locked()); | |
5220 | arm_cpu_update_virq(cpu); | |
5221 | arm_cpu_update_vfiq(cpu); | |
ce4afed8 PM |
5222 | } |
5223 | ||
d1fb4da2 RH |
5224 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
5225 | { | |
5226 | do_hcr_write(env, value, 0); | |
5227 | } | |
5228 | ||
ce4afed8 PM |
5229 | static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, |
5230 | uint64_t value) | |
5231 | { | |
5232 | /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */ | |
5233 | value = deposit64(env->cp15.hcr_el2, 32, 32, value); | |
d1fb4da2 | 5234 | do_hcr_write(env, value, MAKE_64BIT_MASK(0, 32)); |
ce4afed8 PM |
5235 | } |
5236 | ||
5237 | static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, | |
5238 | uint64_t value) | |
5239 | { | |
5240 | /* Handle HCR write, i.e. write to low half of HCR_EL2 */ | |
5241 | value = deposit64(env->cp15.hcr_el2, 0, 32, value); | |
d1fb4da2 | 5242 | do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32)); |
f149e3e8 EI |
5243 | } |
5244 | ||
f7778444 RH |
5245 | /* |
5246 | * Return the effective value of HCR_EL2. | |
5247 | * Bits that are not included here: | |
5248 | * RW (read from SCR_EL3.RW as needed) | |
5249 | */ | |
5250 | uint64_t arm_hcr_el2_eff(CPUARMState *env) | |
5251 | { | |
5252 | uint64_t ret = env->cp15.hcr_el2; | |
5253 | ||
5254 | if (arm_is_secure_below_el3(env)) { | |
5255 | /* | |
5256 | * "This register has no effect if EL2 is not enabled in the | |
5257 | * current Security state". This is ARMv8.4-SecEL2 speak for | |
5258 | * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1). | |
5259 | * | |
5260 | * Prior to that, the language was "In an implementation that | |
5261 | * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves | |
5262 | * as if this field is 0 for all purposes other than a direct | |
5263 | * read or write access of HCR_EL2". With lots of enumeration | |
5264 | * on a per-field basis. In current QEMU, this is condition | |
5265 | * is arm_is_secure_below_el3. | |
5266 | * | |
5267 | * Since the v8.4 language applies to the entire register, and | |
5268 | * appears to be backward compatible, use that. | |
5269 | */ | |
4990e1d3 RH |
5270 | return 0; |
5271 | } | |
5272 | ||
5273 | /* | |
5274 | * For a cpu that supports both aarch64 and aarch32, we can set bits | |
5275 | * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32. | |
5276 | * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32. | |
5277 | */ | |
5278 | if (!arm_el_is_aa64(env, 2)) { | |
5279 | uint64_t aa32_valid; | |
5280 | ||
5281 | /* | |
5282 | * These bits are up-to-date as of ARMv8.6. | |
5283 | * For HCR, it's easiest to list just the 2 bits that are invalid. | |
5284 | * For HCR2, list those that are valid. | |
5285 | */ | |
5286 | aa32_valid = MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ); | |
5287 | aa32_valid |= (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNCE | | |
5288 | HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS); | |
5289 | ret &= aa32_valid; | |
5290 | } | |
5291 | ||
5292 | if (ret & HCR_TGE) { | |
5293 | /* These bits are up-to-date as of ARMv8.6. */ | |
f7778444 RH |
5294 | if (ret & HCR_E2H) { |
5295 | ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | | |
5296 | HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | | |
5297 | HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | | |
4990e1d3 RH |
5298 | HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE | |
5299 | HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT | | |
5300 | HCR_TTLBIS | HCR_TTLBOS | HCR_TID5); | |
f7778444 RH |
5301 | } else { |
5302 | ret |= HCR_FMO | HCR_IMO | HCR_AMO; | |
5303 | } | |
5304 | ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | | |
5305 | HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | | |
5306 | HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | | |
5307 | HCR_TLOR); | |
5308 | } | |
5309 | ||
5310 | return ret; | |
5311 | } | |
5312 | ||
fc1120a7 PM |
5313 | static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5314 | uint64_t value) | |
5315 | { | |
5316 | /* | |
5317 | * For A-profile AArch32 EL3, if NSACR.CP10 | |
5318 | * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. | |
5319 | */ | |
5320 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
5321 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
5322 | value &= ~(0x3 << 10); | |
5323 | value |= env->cp15.cptr_el[2] & (0x3 << 10); | |
5324 | } | |
5325 | env->cp15.cptr_el[2] = value; | |
5326 | } | |
5327 | ||
5328 | static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5329 | { | |
5330 | /* | |
5331 | * For A-profile AArch32 EL3, if NSACR.CP10 | |
5332 | * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. | |
5333 | */ | |
5334 | uint64_t value = env->cp15.cptr_el[2]; | |
5335 | ||
5336 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
5337 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
5338 | value |= 0x3 << 10; | |
5339 | } | |
5340 | return value; | |
5341 | } | |
5342 | ||
4771cd01 | 5343 | static const ARMCPRegInfo el2_cp_reginfo[] = { |
f149e3e8 | 5344 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
89430fc6 | 5345 | .type = ARM_CP_IO, |
f149e3e8 EI |
5346 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
5347 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
c624ea0f | 5348 | .writefn = hcr_write }, |
ce4afed8 | 5349 | { .name = "HCR", .state = ARM_CP_STATE_AA32, |
89430fc6 | 5350 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
5351 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
5352 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
c624ea0f | 5353 | .writefn = hcr_writelow }, |
831a2fca PM |
5354 | { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, |
5355 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, | |
5356 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3b685ba7 | 5357 | { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5358 | .type = ARM_CP_ALIAS, |
3b685ba7 EI |
5359 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, |
5360 | .access = PL2_RW, | |
5361 | .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, | |
68e78e33 | 5362 | { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, |
f2c30f42 EI |
5363 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, |
5364 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, | |
cba517c3 | 5365 | { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, |
63b60551 EI |
5366 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, |
5367 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, | |
cba517c3 PM |
5368 | { .name = "HIFAR", .state = ARM_CP_STATE_AA32, |
5369 | .type = ARM_CP_ALIAS, | |
5370 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | |
5371 | .access = PL2_RW, | |
5372 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) }, | |
3b685ba7 | 5373 | { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5374 | .type = ARM_CP_ALIAS, |
3b685ba7 | 5375 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
5376 | .access = PL2_RW, |
5377 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, | |
d79e0c06 | 5378 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, |
d42e3c26 EI |
5379 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, |
5380 | .access = PL2_RW, .writefn = vbar_write, | |
5381 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), | |
5382 | .resetvalue = 0 }, | |
884b4dee GB |
5383 | { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, |
5384 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 5385 | .access = PL3_RW, .type = ARM_CP_ALIAS, |
884b4dee | 5386 | .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, |
c6f19164 GB |
5387 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
5388 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
5389 | .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, | |
fc1120a7 PM |
5390 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]), |
5391 | .readfn = cptr_el2_read, .writefn = cptr_el2_write }, | |
95f949ac EI |
5392 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
5393 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
5394 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), | |
5395 | .resetvalue = 0 }, | |
5396 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
b5ede85b | 5397 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, |
95f949ac EI |
5398 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
5399 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, | |
2179ef95 PM |
5400 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
5401 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
5402 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5403 | .resetvalue = 0 }, | |
5404 | /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ | |
55b53c71 | 5405 | { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, |
b5ede85b | 5406 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, |
2179ef95 PM |
5407 | .access = PL2_RW, .type = ARM_CP_CONST, |
5408 | .resetvalue = 0 }, | |
37cd6c24 PM |
5409 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
5410 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
5411 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5412 | .resetvalue = 0 }, | |
5413 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
5414 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
5415 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5416 | .resetvalue = 0 }, | |
06ec4c8c EI |
5417 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
5418 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
d06dc933 RH |
5419 | .access = PL2_RW, .writefn = vmsa_tcr_el12_write, |
5420 | /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */ | |
06ec4c8c | 5421 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, |
68e9c2fe EI |
5422 | { .name = "VTCR", .state = ARM_CP_STATE_AA32, |
5423 | .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 | 5424 | .type = ARM_CP_ALIAS, |
68e9c2fe EI |
5425 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
5426 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, | |
5427 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, | |
5428 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 PM |
5429 | .access = PL2_RW, |
5430 | /* no .writefn needed as this can't cause an ASID change; | |
5431 | * no .raw_writefn or .resetfn needed as we never use mask/base_mask | |
5432 | */ | |
68e9c2fe | 5433 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, |
b698e9cf EI |
5434 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
5435 | .cp = 15, .opc1 = 6, .crm = 2, | |
5436 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
5437 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
5438 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), | |
5439 | .writefn = vttbr_write }, | |
5440 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
5441 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
5442 | .access = PL2_RW, .writefn = vttbr_write, | |
5443 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, | |
b9cb5323 EI |
5444 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
5445 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
5446 | .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, | |
5447 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, | |
ff05f37b EI |
5448 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
5449 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
5450 | .access = PL2_RW, .resetvalue = 0, | |
5451 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, | |
a57633c0 EI |
5452 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
5453 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
ed30da8e | 5454 | .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write, |
a57633c0 EI |
5455 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
5456 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
5457 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
a57633c0 | 5458 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
541ef8c2 SS |
5459 | { .name = "TLBIALLNSNH", |
5460 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
5461 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5462 | .writefn = tlbiall_nsnh_write }, | |
5463 | { .name = "TLBIALLNSNHIS", | |
5464 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
5465 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5466 | .writefn = tlbiall_nsnh_is_write }, | |
5467 | { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
5468 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5469 | .writefn = tlbiall_hyp_write }, | |
5470 | { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
5471 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5472 | .writefn = tlbiall_hyp_is_write }, | |
5473 | { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
5474 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5475 | .writefn = tlbimva_hyp_write }, | |
5476 | { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
5477 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5478 | .writefn = tlbimva_hyp_is_write }, | |
51da9014 EI |
5479 | { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, |
5480 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
5481 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 5482 | .writefn = tlbi_aa64_alle2_write }, |
8742d49d EI |
5483 | { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, |
5484 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
5485 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 5486 | .writefn = tlbi_aa64_vae2_write }, |
2bfb9d75 PM |
5487 | { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, |
5488 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, | |
5489 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
5490 | .writefn = tlbi_aa64_vae2_write }, | |
5491 | { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, | |
5492 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
5493 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
5494 | .writefn = tlbi_aa64_alle2is_write }, | |
8742d49d EI |
5495 | { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, |
5496 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
5497 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 5498 | .writefn = tlbi_aa64_vae2is_write }, |
2bfb9d75 PM |
5499 | { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, |
5500 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
5501 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
5502 | .writefn = tlbi_aa64_vae2is_write }, | |
edac4d8a | 5503 | #ifndef CONFIG_USER_ONLY |
2a47df95 PM |
5504 | /* Unlike the other EL2-related AT operations, these must |
5505 | * UNDEF from EL3 if EL2 is not implemented, which is why we | |
5506 | * define them here rather than with the rest of the AT ops. | |
5507 | */ | |
5508 | { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, | |
5509 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
5510 | .access = PL2_W, .accessfn = at_s1e2_access, | |
0710b2fa | 5511 | .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, |
2a47df95 PM |
5512 | { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, |
5513 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | |
5514 | .access = PL2_W, .accessfn = at_s1e2_access, | |
0710b2fa | 5515 | .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, |
14db7fe0 PM |
5516 | /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE |
5517 | * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 | |
5518 | * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose | |
5519 | * to behave as if SCR.NS was 1. | |
5520 | */ | |
5521 | { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
5522 | .access = PL2_W, | |
0710b2fa | 5523 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
14db7fe0 PM |
5524 | { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, |
5525 | .access = PL2_W, | |
0710b2fa | 5526 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
0b6440af EI |
5527 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
5528 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
5529 | /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the | |
5530 | * reset values as IMPDEF. We choose to reset to 3 to comply with | |
5531 | * both ARMv7 and ARMv8. | |
5532 | */ | |
5533 | .access = PL2_RW, .resetvalue = 3, | |
5534 | .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, | |
edac4d8a EI |
5535 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
5536 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
5537 | .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, | |
5538 | .writefn = gt_cntvoff_write, | |
5539 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
5540 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
5541 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, | |
5542 | .writefn = gt_cntvoff_write, | |
5543 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
b0e66d95 EI |
5544 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
5545 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
5546 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
5547 | .type = ARM_CP_IO, .access = PL2_RW, | |
5548 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
5549 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
5550 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
5551 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO, | |
5552 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
5553 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
5554 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
d44ec156 | 5555 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, |
b0e66d95 EI |
5556 | .resetfn = gt_hyp_timer_reset, |
5557 | .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, | |
5558 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
5559 | .type = ARM_CP_IO, | |
5560 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
5561 | .access = PL2_RW, | |
5562 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), | |
5563 | .resetvalue = 0, | |
5564 | .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, | |
edac4d8a | 5565 | #endif |
14cc7b54 SF |
5566 | /* The only field of MDCR_EL2 that has a defined architectural reset value |
5567 | * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we | |
5ecdd3e4 | 5568 | * don't implement any PMU event counters, so using zero as a reset |
14cc7b54 SF |
5569 | * value for MDCR_EL2 is okay |
5570 | */ | |
5571 | { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, | |
5572 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | |
5573 | .access = PL2_RW, .resetvalue = 0, | |
5574 | .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), }, | |
59e05530 EI |
5575 | { .name = "HPFAR", .state = ARM_CP_STATE_AA32, |
5576 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
5577 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
5578 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
5579 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, | |
5580 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
5581 | .access = PL2_RW, | |
5582 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
2a5a9abd AF |
5583 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
5584 | .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
5585 | .access = PL2_RW, | |
5586 | .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, | |
3b685ba7 EI |
5587 | REGINFO_SENTINEL |
5588 | }; | |
5589 | ||
ce4afed8 PM |
5590 | static const ARMCPRegInfo el2_v8_cp_reginfo[] = { |
5591 | { .name = "HCR2", .state = ARM_CP_STATE_AA32, | |
89430fc6 | 5592 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
5593 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, |
5594 | .access = PL2_RW, | |
5595 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2), | |
5596 | .writefn = hcr_writehigh }, | |
5597 | REGINFO_SENTINEL | |
5598 | }; | |
5599 | ||
2f027fc5 PM |
5600 | static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5601 | bool isread) | |
5602 | { | |
5603 | /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. | |
5604 | * At Secure EL1 it traps to EL3. | |
5605 | */ | |
5606 | if (arm_current_el(env) == 3) { | |
5607 | return CP_ACCESS_OK; | |
5608 | } | |
5609 | if (arm_is_secure_below_el3(env)) { | |
5610 | return CP_ACCESS_TRAP_EL3; | |
5611 | } | |
5612 | /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ | |
5613 | if (isread) { | |
5614 | return CP_ACCESS_OK; | |
5615 | } | |
5616 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
5617 | } | |
5618 | ||
60fb1a87 GB |
5619 | static const ARMCPRegInfo el3_cp_reginfo[] = { |
5620 | { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, | |
5621 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, | |
5622 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), | |
5623 | .resetvalue = 0, .writefn = scr_write }, | |
f80741d1 | 5624 | { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL, |
60fb1a87 | 5625 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, |
efe4a274 PM |
5626 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
5627 | .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), | |
b061a82b | 5628 | .writefn = scr_write }, |
60fb1a87 GB |
5629 | { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, |
5630 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, | |
5631 | .access = PL3_RW, .resetvalue = 0, | |
5632 | .fieldoffset = offsetof(CPUARMState, cp15.sder) }, | |
5633 | { .name = "SDER", | |
5634 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, | |
5635 | .access = PL3_RW, .resetvalue = 0, | |
5636 | .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, | |
60fb1a87 | 5637 | { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, |
efe4a274 PM |
5638 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
5639 | .writefn = vbar_write, .resetvalue = 0, | |
60fb1a87 | 5640 | .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, |
7dd8c9af FA |
5641 | { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, |
5642 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, | |
f478847f | 5643 | .access = PL3_RW, .resetvalue = 0, |
7dd8c9af | 5644 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, |
11f136ee FA |
5645 | { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, |
5646 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, | |
6459b94c PM |
5647 | .access = PL3_RW, |
5648 | /* no .writefn needed as this can't cause an ASID change; | |
811595a2 PM |
5649 | * we must provide a .raw_writefn and .resetfn because we handle |
5650 | * reset and migration for the AArch32 TTBCR(S), which might be | |
5651 | * using mask and base_mask. | |
6459b94c | 5652 | */ |
811595a2 | 5653 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, |
11f136ee | 5654 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, |
81547d66 | 5655 | { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5656 | .type = ARM_CP_ALIAS, |
81547d66 EI |
5657 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, |
5658 | .access = PL3_RW, | |
5659 | .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, | |
f2c30f42 | 5660 | { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, |
f2c30f42 EI |
5661 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, |
5662 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, | |
63b60551 EI |
5663 | { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, |
5664 | .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, | |
5665 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, | |
81547d66 | 5666 | { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5667 | .type = ARM_CP_ALIAS, |
81547d66 | 5668 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
5669 | .access = PL3_RW, |
5670 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) }, | |
a1ba125c EI |
5671 | { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, |
5672 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, | |
5673 | .access = PL3_RW, .writefn = vbar_write, | |
5674 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), | |
5675 | .resetvalue = 0 }, | |
c6f19164 GB |
5676 | { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, |
5677 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, | |
5678 | .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, | |
5679 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, | |
4cfb8ad8 PM |
5680 | { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, |
5681 | .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, | |
5682 | .access = PL3_RW, .resetvalue = 0, | |
5683 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, | |
2179ef95 PM |
5684 | { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64, |
5685 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, | |
5686 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5687 | .resetvalue = 0 }, | |
37cd6c24 PM |
5688 | { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, |
5689 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, | |
5690 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5691 | .resetvalue = 0 }, | |
5692 | { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, | |
5693 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, | |
5694 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5695 | .resetvalue = 0 }, | |
43efaa33 PM |
5696 | { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, |
5697 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, | |
5698 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5699 | .writefn = tlbi_aa64_alle3is_write }, | |
5700 | { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, | |
5701 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, | |
5702 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5703 | .writefn = tlbi_aa64_vae3is_write }, | |
5704 | { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, | |
5705 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, | |
5706 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5707 | .writefn = tlbi_aa64_vae3is_write }, | |
5708 | { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, | |
5709 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, | |
5710 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5711 | .writefn = tlbi_aa64_alle3_write }, | |
5712 | { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, | |
5713 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, | |
5714 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5715 | .writefn = tlbi_aa64_vae3_write }, | |
5716 | { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, | |
5717 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, | |
5718 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5719 | .writefn = tlbi_aa64_vae3_write }, | |
0f1a3b24 FA |
5720 | REGINFO_SENTINEL |
5721 | }; | |
5722 | ||
e2cce18f RH |
5723 | #ifndef CONFIG_USER_ONLY |
5724 | /* Test if system register redirection is to occur in the current state. */ | |
5725 | static bool redirect_for_e2h(CPUARMState *env) | |
5726 | { | |
5727 | return arm_current_el(env) == 2 && (arm_hcr_el2_eff(env) & HCR_E2H); | |
5728 | } | |
5729 | ||
5730 | static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5731 | { | |
5732 | CPReadFn *readfn; | |
5733 | ||
5734 | if (redirect_for_e2h(env)) { | |
5735 | /* Switch to the saved EL2 version of the register. */ | |
5736 | ri = ri->opaque; | |
5737 | readfn = ri->readfn; | |
5738 | } else { | |
5739 | readfn = ri->orig_readfn; | |
5740 | } | |
5741 | if (readfn == NULL) { | |
5742 | readfn = raw_read; | |
5743 | } | |
5744 | return readfn(env, ri); | |
5745 | } | |
5746 | ||
5747 | static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5748 | uint64_t value) | |
5749 | { | |
5750 | CPWriteFn *writefn; | |
5751 | ||
5752 | if (redirect_for_e2h(env)) { | |
5753 | /* Switch to the saved EL2 version of the register. */ | |
5754 | ri = ri->opaque; | |
5755 | writefn = ri->writefn; | |
5756 | } else { | |
5757 | writefn = ri->orig_writefn; | |
5758 | } | |
5759 | if (writefn == NULL) { | |
5760 | writefn = raw_write; | |
5761 | } | |
5762 | writefn(env, ri, value); | |
5763 | } | |
5764 | ||
5765 | static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) | |
5766 | { | |
5767 | struct E2HAlias { | |
5768 | uint32_t src_key, dst_key, new_key; | |
5769 | const char *src_name, *dst_name, *new_name; | |
5770 | bool (*feature)(const ARMISARegisters *id); | |
5771 | }; | |
5772 | ||
5773 | #define K(op0, op1, crn, crm, op2) \ | |
5774 | ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) | |
5775 | ||
5776 | static const struct E2HAlias aliases[] = { | |
5777 | { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), | |
5778 | "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, | |
5779 | { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), | |
5780 | "CPACR", "CPTR_EL2", "CPACR_EL12" }, | |
5781 | { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), | |
5782 | "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, | |
5783 | { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), | |
5784 | "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, | |
5785 | { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), | |
5786 | "TCR_EL1", "TCR_EL2", "TCR_EL12" }, | |
5787 | { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), | |
5788 | "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, | |
5789 | { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), | |
5790 | "ELR_EL1", "ELR_EL2", "ELR_EL12" }, | |
5791 | { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0), | |
5792 | "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" }, | |
5793 | { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1), | |
5794 | "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" }, | |
5795 | { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0), | |
5796 | "ESR_EL1", "ESR_EL2", "ESR_EL12" }, | |
5797 | { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0), | |
5798 | "FAR_EL1", "FAR_EL2", "FAR_EL12" }, | |
5799 | { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), | |
5800 | "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, | |
5801 | { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), | |
5802 | "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" }, | |
5803 | { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), | |
5804 | "VBAR", "VBAR_EL2", "VBAR_EL12" }, | |
5805 | { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), | |
5806 | "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, | |
5807 | { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), | |
5808 | "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" }, | |
5809 | ||
5810 | /* | |
5811 | * Note that redirection of ZCR is mentioned in the description | |
5812 | * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but | |
5813 | * not in the summary table. | |
5814 | */ | |
5815 | { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), | |
5816 | "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, | |
5817 | ||
5818 | /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ | |
5819 | /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ | |
5820 | }; | |
5821 | #undef K | |
5822 | ||
5823 | size_t i; | |
5824 | ||
5825 | for (i = 0; i < ARRAY_SIZE(aliases); i++) { | |
5826 | const struct E2HAlias *a = &aliases[i]; | |
5827 | ARMCPRegInfo *src_reg, *dst_reg; | |
5828 | ||
5829 | if (a->feature && !a->feature(&cpu->isar)) { | |
5830 | continue; | |
5831 | } | |
5832 | ||
5833 | src_reg = g_hash_table_lookup(cpu->cp_regs, &a->src_key); | |
5834 | dst_reg = g_hash_table_lookup(cpu->cp_regs, &a->dst_key); | |
5835 | g_assert(src_reg != NULL); | |
5836 | g_assert(dst_reg != NULL); | |
5837 | ||
5838 | /* Cross-compare names to detect typos in the keys. */ | |
5839 | g_assert(strcmp(src_reg->name, a->src_name) == 0); | |
5840 | g_assert(strcmp(dst_reg->name, a->dst_name) == 0); | |
5841 | ||
5842 | /* None of the core system registers use opaque; we will. */ | |
5843 | g_assert(src_reg->opaque == NULL); | |
5844 | ||
5845 | /* Create alias before redirection so we dup the right data. */ | |
5846 | if (a->new_key) { | |
5847 | ARMCPRegInfo *new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo)); | |
5848 | uint32_t *new_key = g_memdup(&a->new_key, sizeof(uint32_t)); | |
5849 | bool ok; | |
5850 | ||
5851 | new_reg->name = a->new_name; | |
5852 | new_reg->type |= ARM_CP_ALIAS; | |
5853 | /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ | |
5854 | new_reg->access &= PL2_RW | PL3_RW; | |
5855 | ||
5856 | ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg); | |
5857 | g_assert(ok); | |
5858 | } | |
5859 | ||
5860 | src_reg->opaque = dst_reg; | |
5861 | src_reg->orig_readfn = src_reg->readfn ?: raw_read; | |
5862 | src_reg->orig_writefn = src_reg->writefn ?: raw_write; | |
5863 | if (!src_reg->raw_readfn) { | |
5864 | src_reg->raw_readfn = raw_read; | |
5865 | } | |
5866 | if (!src_reg->raw_writefn) { | |
5867 | src_reg->raw_writefn = raw_write; | |
5868 | } | |
5869 | src_reg->readfn = el2_e2h_read; | |
5870 | src_reg->writefn = el2_e2h_write; | |
5871 | } | |
5872 | } | |
5873 | #endif | |
5874 | ||
3f208fd7 PM |
5875 | static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5876 | bool isread) | |
7da845b0 | 5877 | { |
97475a89 RH |
5878 | int cur_el = arm_current_el(env); |
5879 | ||
5880 | if (cur_el < 2) { | |
5881 | uint64_t hcr = arm_hcr_el2_eff(env); | |
5882 | ||
5883 | if (cur_el == 0) { | |
5884 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
5885 | if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) { | |
5886 | return CP_ACCESS_TRAP_EL2; | |
5887 | } | |
5888 | } else { | |
5889 | if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) { | |
5890 | return CP_ACCESS_TRAP; | |
5891 | } | |
5892 | if (hcr & HCR_TID2) { | |
5893 | return CP_ACCESS_TRAP_EL2; | |
5894 | } | |
5895 | } | |
5896 | } else if (hcr & HCR_TID2) { | |
5897 | return CP_ACCESS_TRAP_EL2; | |
5898 | } | |
7da845b0 | 5899 | } |
630fcd4d MZ |
5900 | |
5901 | if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) { | |
5902 | return CP_ACCESS_TRAP_EL2; | |
5903 | } | |
5904 | ||
7da845b0 PM |
5905 | return CP_ACCESS_OK; |
5906 | } | |
5907 | ||
1424ca8d DM |
5908 | static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5909 | uint64_t value) | |
5910 | { | |
5911 | /* Writes to OSLAR_EL1 may update the OS lock status, which can be | |
5912 | * read via a bit in OSLSR_EL1. | |
5913 | */ | |
5914 | int oslock; | |
5915 | ||
5916 | if (ri->state == ARM_CP_STATE_AA32) { | |
5917 | oslock = (value == 0xC5ACCE55); | |
5918 | } else { | |
5919 | oslock = value & 1; | |
5920 | } | |
5921 | ||
5922 | env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); | |
5923 | } | |
5924 | ||
50300698 | 5925 | static const ARMCPRegInfo debug_cp_reginfo[] = { |
50300698 | 5926 | /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped |
10aae104 PM |
5927 | * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; |
5928 | * unlike DBGDRAR it is never accessible from EL0. | |
5929 | * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 | |
5930 | * accessor. | |
50300698 PM |
5931 | */ |
5932 | { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
91b0a238 PM |
5933 | .access = PL0_R, .accessfn = access_tdra, |
5934 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
10aae104 PM |
5935 | { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, |
5936 | .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, | |
91b0a238 PM |
5937 | .access = PL1_R, .accessfn = access_tdra, |
5938 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
50300698 | 5939 | { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
91b0a238 PM |
5940 | .access = PL0_R, .accessfn = access_tdra, |
5941 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
17a9eb53 | 5942 | /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ |
10aae104 PM |
5943 | { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, |
5944 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
d6c8cf81 | 5945 | .access = PL1_RW, .accessfn = access_tda, |
0e5e8935 PM |
5946 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), |
5947 | .resetvalue = 0 }, | |
5e8b12ff PM |
5948 | /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. |
5949 | * We don't implement the configurable EL0 access. | |
5950 | */ | |
5951 | { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH, | |
5952 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
7a0e58fa | 5953 | .type = ARM_CP_ALIAS, |
d6c8cf81 | 5954 | .access = PL1_R, .accessfn = access_tda, |
b061a82b | 5955 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, |
10aae104 PM |
5956 | { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, |
5957 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, | |
1424ca8d | 5958 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
187f678d | 5959 | .accessfn = access_tdosa, |
1424ca8d DM |
5960 | .writefn = oslar_write }, |
5961 | { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, | |
5962 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, | |
5963 | .access = PL1_R, .resetvalue = 10, | |
187f678d | 5964 | .accessfn = access_tdosa, |
1424ca8d | 5965 | .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, |
5e8b12ff PM |
5966 | /* Dummy OSDLR_EL1: 32-bit Linux will read this */ |
5967 | { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, | |
5968 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, | |
187f678d PM |
5969 | .access = PL1_RW, .accessfn = access_tdosa, |
5970 | .type = ARM_CP_NOP }, | |
5e8b12ff PM |
5971 | /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't |
5972 | * implement vector catch debug events yet. | |
5973 | */ | |
5974 | { .name = "DBGVCR", | |
5975 | .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
d6c8cf81 PM |
5976 | .access = PL1_RW, .accessfn = access_tda, |
5977 | .type = ARM_CP_NOP }, | |
4d2ec4da PM |
5978 | /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor |
5979 | * to save and restore a 32-bit guest's DBGVCR) | |
5980 | */ | |
5981 | { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, | |
5982 | .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, | |
5983 | .access = PL2_RW, .accessfn = access_tda, | |
5984 | .type = ARM_CP_NOP }, | |
5dbdc434 PM |
5985 | /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications |
5986 | * Channel but Linux may try to access this register. The 32-bit | |
5987 | * alias is DBGDCCINT. | |
5988 | */ | |
5989 | { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, | |
5990 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
5991 | .access = PL1_RW, .accessfn = access_tda, | |
5992 | .type = ARM_CP_NOP }, | |
50300698 PM |
5993 | REGINFO_SENTINEL |
5994 | }; | |
5995 | ||
5996 | static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | |
5997 | /* 64 bit access versions of the (dummy) debug registers */ | |
5998 | { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, | |
5999 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
6000 | { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | |
6001 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
6002 | REGINFO_SENTINEL | |
6003 | }; | |
6004 | ||
60eed086 RH |
6005 | /* Return the exception level to which exceptions should be taken |
6006 | * via SVEAccessTrap. If an exception should be routed through | |
6007 | * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should | |
6008 | * take care of raising that exception. | |
6009 | * C.f. the ARM pseudocode function CheckSVEEnabled. | |
5be5e8ed | 6010 | */ |
ced31551 | 6011 | int sve_exception_el(CPUARMState *env, int el) |
5be5e8ed RH |
6012 | { |
6013 | #ifndef CONFIG_USER_ONLY | |
c2ddb7cf RH |
6014 | uint64_t hcr_el2 = arm_hcr_el2_eff(env); |
6015 | ||
6016 | if (el <= 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { | |
60eed086 RH |
6017 | bool disabled = false; |
6018 | ||
6019 | /* The CPACR.ZEN controls traps to EL1: | |
6020 | * 0, 2 : trap EL0 and EL1 accesses | |
6021 | * 1 : trap only EL0 accesses | |
6022 | * 3 : trap no accesses | |
6023 | */ | |
6024 | if (!extract32(env->cp15.cpacr_el1, 16, 1)) { | |
6025 | disabled = true; | |
6026 | } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) { | |
2de7ace2 | 6027 | disabled = el == 0; |
5be5e8ed | 6028 | } |
60eed086 RH |
6029 | if (disabled) { |
6030 | /* route_to_el2 */ | |
c2ddb7cf | 6031 | return hcr_el2 & HCR_TGE ? 2 : 1; |
5be5e8ed | 6032 | } |
5be5e8ed | 6033 | |
60eed086 RH |
6034 | /* Check CPACR.FPEN. */ |
6035 | if (!extract32(env->cp15.cpacr_el1, 20, 1)) { | |
6036 | disabled = true; | |
6037 | } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) { | |
2de7ace2 | 6038 | disabled = el == 0; |
5be5e8ed | 6039 | } |
60eed086 RH |
6040 | if (disabled) { |
6041 | return 0; | |
5be5e8ed | 6042 | } |
5be5e8ed RH |
6043 | } |
6044 | ||
60eed086 RH |
6045 | /* CPTR_EL2. Since TZ and TFP are positive, |
6046 | * they will be zero when EL2 is not present. | |
6047 | */ | |
2de7ace2 | 6048 | if (el <= 2 && !arm_is_secure_below_el3(env)) { |
60eed086 RH |
6049 | if (env->cp15.cptr_el[2] & CPTR_TZ) { |
6050 | return 2; | |
6051 | } | |
6052 | if (env->cp15.cptr_el[2] & CPTR_TFP) { | |
6053 | return 0; | |
6054 | } | |
5be5e8ed RH |
6055 | } |
6056 | ||
60eed086 RH |
6057 | /* CPTR_EL3. Since EZ is negative we must check for EL3. */ |
6058 | if (arm_feature(env, ARM_FEATURE_EL3) | |
6059 | && !(env->cp15.cptr_el[3] & CPTR_EZ)) { | |
5be5e8ed RH |
6060 | return 3; |
6061 | } | |
6062 | #endif | |
6063 | return 0; | |
6064 | } | |
6065 | ||
0df9142d AJ |
6066 | static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) |
6067 | { | |
6e553f2a | 6068 | uint32_t end_len; |
0df9142d | 6069 | |
6e553f2a RH |
6070 | end_len = start_len &= 0xf; |
6071 | if (!test_bit(start_len, cpu->sve_vq_map)) { | |
6072 | end_len = find_last_bit(cpu->sve_vq_map, start_len); | |
6073 | assert(end_len < start_len); | |
6074 | } | |
6075 | return end_len; | |
0df9142d AJ |
6076 | } |
6077 | ||
0ab5953b RH |
6078 | /* |
6079 | * Given that SVE is enabled, return the vector length for EL. | |
6080 | */ | |
ced31551 | 6081 | uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) |
0ab5953b | 6082 | { |
2fc0cc0e | 6083 | ARMCPU *cpu = env_archcpu(env); |
0ab5953b RH |
6084 | uint32_t zcr_len = cpu->sve_max_vq - 1; |
6085 | ||
6086 | if (el <= 1) { | |
6087 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); | |
6088 | } | |
6a02a732 | 6089 | if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) { |
0ab5953b RH |
6090 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); |
6091 | } | |
6a02a732 | 6092 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0ab5953b RH |
6093 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); |
6094 | } | |
0df9142d AJ |
6095 | |
6096 | return sve_zcr_get_valid_len(cpu, zcr_len); | |
0ab5953b RH |
6097 | } |
6098 | ||
5be5e8ed RH |
6099 | static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
6100 | uint64_t value) | |
6101 | { | |
0ab5953b RH |
6102 | int cur_el = arm_current_el(env); |
6103 | int old_len = sve_zcr_len_for_el(env, cur_el); | |
6104 | int new_len; | |
6105 | ||
5be5e8ed | 6106 | /* Bits other than [3:0] are RAZ/WI. */ |
7b351d98 | 6107 | QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16); |
5be5e8ed | 6108 | raw_write(env, ri, value & 0xf); |
0ab5953b RH |
6109 | |
6110 | /* | |
6111 | * Because we arrived here, we know both FP and SVE are enabled; | |
6112 | * otherwise we would have trapped access to the ZCR_ELn register. | |
6113 | */ | |
6114 | new_len = sve_zcr_len_for_el(env, cur_el); | |
6115 | if (new_len < old_len) { | |
6116 | aarch64_sve_narrow_vq(env, new_len + 1); | |
6117 | } | |
5be5e8ed RH |
6118 | } |
6119 | ||
6120 | static const ARMCPRegInfo zcr_el1_reginfo = { | |
6121 | .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | |
6122 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 6123 | .access = PL1_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
6124 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), |
6125 | .writefn = zcr_write, .raw_writefn = raw_write | |
6126 | }; | |
6127 | ||
6128 | static const ARMCPRegInfo zcr_el2_reginfo = { | |
6129 | .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | |
6130 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 6131 | .access = PL2_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
6132 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), |
6133 | .writefn = zcr_write, .raw_writefn = raw_write | |
6134 | }; | |
6135 | ||
6136 | static const ARMCPRegInfo zcr_no_el2_reginfo = { | |
6137 | .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | |
6138 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 6139 | .access = PL2_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
6140 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore |
6141 | }; | |
6142 | ||
6143 | static const ARMCPRegInfo zcr_el3_reginfo = { | |
6144 | .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | |
6145 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 6146 | .access = PL3_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
6147 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), |
6148 | .writefn = zcr_write, .raw_writefn = raw_write | |
6149 | }; | |
6150 | ||
9ee98ce8 PM |
6151 | void hw_watchpoint_update(ARMCPU *cpu, int n) |
6152 | { | |
6153 | CPUARMState *env = &cpu->env; | |
6154 | vaddr len = 0; | |
6155 | vaddr wvr = env->cp15.dbgwvr[n]; | |
6156 | uint64_t wcr = env->cp15.dbgwcr[n]; | |
6157 | int mask; | |
6158 | int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; | |
6159 | ||
6160 | if (env->cpu_watchpoint[n]) { | |
6161 | cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); | |
6162 | env->cpu_watchpoint[n] = NULL; | |
6163 | } | |
6164 | ||
6165 | if (!extract64(wcr, 0, 1)) { | |
6166 | /* E bit clear : watchpoint disabled */ | |
6167 | return; | |
6168 | } | |
6169 | ||
6170 | switch (extract64(wcr, 3, 2)) { | |
6171 | case 0: | |
6172 | /* LSC 00 is reserved and must behave as if the wp is disabled */ | |
6173 | return; | |
6174 | case 1: | |
6175 | flags |= BP_MEM_READ; | |
6176 | break; | |
6177 | case 2: | |
6178 | flags |= BP_MEM_WRITE; | |
6179 | break; | |
6180 | case 3: | |
6181 | flags |= BP_MEM_ACCESS; | |
6182 | break; | |
6183 | } | |
6184 | ||
6185 | /* Attempts to use both MASK and BAS fields simultaneously are | |
6186 | * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, | |
6187 | * thus generating a watchpoint for every byte in the masked region. | |
6188 | */ | |
6189 | mask = extract64(wcr, 24, 4); | |
6190 | if (mask == 1 || mask == 2) { | |
6191 | /* Reserved values of MASK; we must act as if the mask value was | |
6192 | * some non-reserved value, or as if the watchpoint were disabled. | |
6193 | * We choose the latter. | |
6194 | */ | |
6195 | return; | |
6196 | } else if (mask) { | |
6197 | /* Watchpoint covers an aligned area up to 2GB in size */ | |
6198 | len = 1ULL << mask; | |
6199 | /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE | |
6200 | * whether the watchpoint fires when the unmasked bits match; we opt | |
6201 | * to generate the exceptions. | |
6202 | */ | |
6203 | wvr &= ~(len - 1); | |
6204 | } else { | |
6205 | /* Watchpoint covers bytes defined by the byte address select bits */ | |
6206 | int bas = extract64(wcr, 5, 8); | |
6207 | int basstart; | |
6208 | ||
6209 | if (bas == 0) { | |
6210 | /* This must act as if the watchpoint is disabled */ | |
6211 | return; | |
6212 | } | |
6213 | ||
6214 | if (extract64(wvr, 2, 1)) { | |
6215 | /* Deprecated case of an only 4-aligned address. BAS[7:4] are | |
6216 | * ignored, and BAS[3:0] define which bytes to watch. | |
6217 | */ | |
6218 | bas &= 0xf; | |
6219 | } | |
6220 | /* The BAS bits are supposed to be programmed to indicate a contiguous | |
6221 | * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether | |
6222 | * we fire for each byte in the word/doubleword addressed by the WVR. | |
6223 | * We choose to ignore any non-zero bits after the first range of 1s. | |
6224 | */ | |
6225 | basstart = ctz32(bas); | |
6226 | len = cto32(bas >> basstart); | |
6227 | wvr += basstart; | |
6228 | } | |
6229 | ||
6230 | cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, | |
6231 | &env->cpu_watchpoint[n]); | |
6232 | } | |
6233 | ||
6234 | void hw_watchpoint_update_all(ARMCPU *cpu) | |
6235 | { | |
6236 | int i; | |
6237 | CPUARMState *env = &cpu->env; | |
6238 | ||
6239 | /* Completely clear out existing QEMU watchpoints and our array, to | |
6240 | * avoid possible stale entries following migration load. | |
6241 | */ | |
6242 | cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); | |
6243 | memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); | |
6244 | ||
6245 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { | |
6246 | hw_watchpoint_update(cpu, i); | |
6247 | } | |
6248 | } | |
6249 | ||
6250 | static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6251 | uint64_t value) | |
6252 | { | |
2fc0cc0e | 6253 | ARMCPU *cpu = env_archcpu(env); |
9ee98ce8 PM |
6254 | int i = ri->crm; |
6255 | ||
6256 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, the | |
6257 | * register reads and behaves as if values written are sign extended. | |
6258 | * Bits [1:0] are RES0. | |
6259 | */ | |
6260 | value = sextract64(value, 0, 49) & ~3ULL; | |
6261 | ||
6262 | raw_write(env, ri, value); | |
6263 | hw_watchpoint_update(cpu, i); | |
6264 | } | |
6265 | ||
6266 | static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6267 | uint64_t value) | |
6268 | { | |
2fc0cc0e | 6269 | ARMCPU *cpu = env_archcpu(env); |
9ee98ce8 PM |
6270 | int i = ri->crm; |
6271 | ||
6272 | raw_write(env, ri, value); | |
6273 | hw_watchpoint_update(cpu, i); | |
6274 | } | |
6275 | ||
46747d15 PM |
6276 | void hw_breakpoint_update(ARMCPU *cpu, int n) |
6277 | { | |
6278 | CPUARMState *env = &cpu->env; | |
6279 | uint64_t bvr = env->cp15.dbgbvr[n]; | |
6280 | uint64_t bcr = env->cp15.dbgbcr[n]; | |
6281 | vaddr addr; | |
6282 | int bt; | |
6283 | int flags = BP_CPU; | |
6284 | ||
6285 | if (env->cpu_breakpoint[n]) { | |
6286 | cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); | |
6287 | env->cpu_breakpoint[n] = NULL; | |
6288 | } | |
6289 | ||
6290 | if (!extract64(bcr, 0, 1)) { | |
6291 | /* E bit clear : watchpoint disabled */ | |
6292 | return; | |
6293 | } | |
6294 | ||
6295 | bt = extract64(bcr, 20, 4); | |
6296 | ||
6297 | switch (bt) { | |
6298 | case 4: /* unlinked address mismatch (reserved if AArch64) */ | |
6299 | case 5: /* linked address mismatch (reserved if AArch64) */ | |
6300 | qemu_log_mask(LOG_UNIMP, | |
0221c8fd | 6301 | "arm: address mismatch breakpoint types not implemented\n"); |
46747d15 PM |
6302 | return; |
6303 | case 0: /* unlinked address match */ | |
6304 | case 1: /* linked address match */ | |
6305 | { | |
6306 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, | |
6307 | * we behave as if the register was sign extended. Bits [1:0] are | |
6308 | * RES0. The BAS field is used to allow setting breakpoints on 16 | |
6309 | * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether | |
6310 | * a bp will fire if the addresses covered by the bp and the addresses | |
6311 | * covered by the insn overlap but the insn doesn't start at the | |
6312 | * start of the bp address range. We choose to require the insn and | |
6313 | * the bp to have the same address. The constraints on writing to | |
6314 | * BAS enforced in dbgbcr_write mean we have only four cases: | |
6315 | * 0b0000 => no breakpoint | |
6316 | * 0b0011 => breakpoint on addr | |
6317 | * 0b1100 => breakpoint on addr + 2 | |
6318 | * 0b1111 => breakpoint on addr | |
6319 | * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). | |
6320 | */ | |
6321 | int bas = extract64(bcr, 5, 4); | |
6322 | addr = sextract64(bvr, 0, 49) & ~3ULL; | |
6323 | if (bas == 0) { | |
6324 | return; | |
6325 | } | |
6326 | if (bas == 0xc) { | |
6327 | addr += 2; | |
6328 | } | |
6329 | break; | |
6330 | } | |
6331 | case 2: /* unlinked context ID match */ | |
6332 | case 8: /* unlinked VMID match (reserved if no EL2) */ | |
6333 | case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ | |
6334 | qemu_log_mask(LOG_UNIMP, | |
0221c8fd | 6335 | "arm: unlinked context breakpoint types not implemented\n"); |
46747d15 PM |
6336 | return; |
6337 | case 9: /* linked VMID match (reserved if no EL2) */ | |
6338 | case 11: /* linked context ID and VMID match (reserved if no EL2) */ | |
6339 | case 3: /* linked context ID match */ | |
6340 | default: | |
6341 | /* We must generate no events for Linked context matches (unless | |
6342 | * they are linked to by some other bp/wp, which is handled in | |
6343 | * updates for the linking bp/wp). We choose to also generate no events | |
6344 | * for reserved values. | |
6345 | */ | |
6346 | return; | |
6347 | } | |
6348 | ||
6349 | cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); | |
6350 | } | |
6351 | ||
6352 | void hw_breakpoint_update_all(ARMCPU *cpu) | |
6353 | { | |
6354 | int i; | |
6355 | CPUARMState *env = &cpu->env; | |
6356 | ||
6357 | /* Completely clear out existing QEMU breakpoints and our array, to | |
6358 | * avoid possible stale entries following migration load. | |
6359 | */ | |
6360 | cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); | |
6361 | memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); | |
6362 | ||
6363 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { | |
6364 | hw_breakpoint_update(cpu, i); | |
6365 | } | |
6366 | } | |
6367 | ||
6368 | static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6369 | uint64_t value) | |
6370 | { | |
2fc0cc0e | 6371 | ARMCPU *cpu = env_archcpu(env); |
46747d15 PM |
6372 | int i = ri->crm; |
6373 | ||
6374 | raw_write(env, ri, value); | |
6375 | hw_breakpoint_update(cpu, i); | |
6376 | } | |
6377 | ||
6378 | static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6379 | uint64_t value) | |
6380 | { | |
2fc0cc0e | 6381 | ARMCPU *cpu = env_archcpu(env); |
46747d15 PM |
6382 | int i = ri->crm; |
6383 | ||
6384 | /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only | |
6385 | * copy of BAS[0]. | |
6386 | */ | |
6387 | value = deposit64(value, 6, 1, extract64(value, 5, 1)); | |
6388 | value = deposit64(value, 8, 1, extract64(value, 7, 1)); | |
6389 | ||
6390 | raw_write(env, ri, value); | |
6391 | hw_breakpoint_update(cpu, i); | |
6392 | } | |
6393 | ||
50300698 | 6394 | static void define_debug_regs(ARMCPU *cpu) |
0b45451e | 6395 | { |
50300698 PM |
6396 | /* Define v7 and v8 architectural debug registers. |
6397 | * These are just dummy implementations for now. | |
0b45451e PM |
6398 | */ |
6399 | int i; | |
3ff6fc91 | 6400 | int wrps, brps, ctx_cmps; |
48eb3ae6 PM |
6401 | ARMCPRegInfo dbgdidr = { |
6402 | .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
d6c8cf81 | 6403 | .access = PL0_R, .accessfn = access_tda, |
4426d361 | 6404 | .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr, |
48eb3ae6 PM |
6405 | }; |
6406 | ||
3ff6fc91 | 6407 | /* Note that all these register fields hold "number of Xs minus 1". */ |
88ce6c6e PM |
6408 | brps = arm_num_brps(cpu); |
6409 | wrps = arm_num_wrps(cpu); | |
6410 | ctx_cmps = arm_num_ctx_cmps(cpu); | |
3ff6fc91 PM |
6411 | |
6412 | assert(ctx_cmps <= brps); | |
48eb3ae6 | 6413 | |
48eb3ae6 | 6414 | define_one_arm_cp_reg(cpu, &dbgdidr); |
50300698 PM |
6415 | define_arm_cp_regs(cpu, debug_cp_reginfo); |
6416 | ||
6417 | if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { | |
6418 | define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); | |
6419 | } | |
6420 | ||
88ce6c6e | 6421 | for (i = 0; i < brps; i++) { |
0b45451e | 6422 | ARMCPRegInfo dbgregs[] = { |
10aae104 PM |
6423 | { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH, |
6424 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, | |
d6c8cf81 | 6425 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
6426 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), |
6427 | .writefn = dbgbvr_write, .raw_writefn = raw_write | |
6428 | }, | |
10aae104 PM |
6429 | { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH, |
6430 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, | |
d6c8cf81 | 6431 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
6432 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), |
6433 | .writefn = dbgbcr_write, .raw_writefn = raw_write | |
6434 | }, | |
48eb3ae6 PM |
6435 | REGINFO_SENTINEL |
6436 | }; | |
6437 | define_arm_cp_regs(cpu, dbgregs); | |
6438 | } | |
6439 | ||
88ce6c6e | 6440 | for (i = 0; i < wrps; i++) { |
48eb3ae6 | 6441 | ARMCPRegInfo dbgregs[] = { |
10aae104 PM |
6442 | { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH, |
6443 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, | |
d6c8cf81 | 6444 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
6445 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), |
6446 | .writefn = dbgwvr_write, .raw_writefn = raw_write | |
6447 | }, | |
10aae104 PM |
6448 | { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH, |
6449 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, | |
d6c8cf81 | 6450 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
6451 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), |
6452 | .writefn = dbgwcr_write, .raw_writefn = raw_write | |
6453 | }, | |
6454 | REGINFO_SENTINEL | |
0b45451e PM |
6455 | }; |
6456 | define_arm_cp_regs(cpu, dbgregs); | |
6457 | } | |
6458 | } | |
6459 | ||
24183fb6 PM |
6460 | static void define_pmu_regs(ARMCPU *cpu) |
6461 | { | |
6462 | /* | |
6463 | * v7 performance monitor control register: same implementor | |
6464 | * field as main ID register, and we implement four counters in | |
6465 | * addition to the cycle count register. | |
6466 | */ | |
6467 | unsigned int i, pmcrn = 4; | |
6468 | ARMCPRegInfo pmcr = { | |
6469 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | |
6470 | .access = PL0_RW, | |
6471 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6472 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), | |
6473 | .accessfn = pmreg_access, .writefn = pmcr_write, | |
6474 | .raw_writefn = raw_write, | |
6475 | }; | |
6476 | ARMCPRegInfo pmcr64 = { | |
6477 | .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, | |
6478 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, | |
6479 | .access = PL0_RW, .accessfn = pmreg_access, | |
6480 | .type = ARM_CP_IO, | |
6481 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), | |
62d96ff4 PM |
6482 | .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) | |
6483 | PMCRLC, | |
24183fb6 PM |
6484 | .writefn = pmcr_write, .raw_writefn = raw_write, |
6485 | }; | |
6486 | define_one_arm_cp_reg(cpu, &pmcr); | |
6487 | define_one_arm_cp_reg(cpu, &pmcr64); | |
6488 | for (i = 0; i < pmcrn; i++) { | |
6489 | char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i); | |
6490 | char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i); | |
6491 | char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i); | |
6492 | char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i); | |
6493 | ARMCPRegInfo pmev_regs[] = { | |
6494 | { .name = pmevcntr_name, .cp = 15, .crn = 14, | |
6495 | .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, | |
6496 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6497 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, | |
6498 | .accessfn = pmreg_access }, | |
6499 | { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64, | |
6500 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)), | |
6501 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, | |
6502 | .type = ARM_CP_IO, | |
6503 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, | |
6504 | .raw_readfn = pmevcntr_rawread, | |
6505 | .raw_writefn = pmevcntr_rawwrite }, | |
6506 | { .name = pmevtyper_name, .cp = 15, .crn = 14, | |
6507 | .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, | |
6508 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6509 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | |
6510 | .accessfn = pmreg_access }, | |
6511 | { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64, | |
6512 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)), | |
6513 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, | |
6514 | .type = ARM_CP_IO, | |
6515 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | |
6516 | .raw_writefn = pmevtyper_rawwrite }, | |
6517 | REGINFO_SENTINEL | |
6518 | }; | |
6519 | define_arm_cp_regs(cpu, pmev_regs); | |
6520 | g_free(pmevcntr_name); | |
6521 | g_free(pmevcntr_el0_name); | |
6522 | g_free(pmevtyper_name); | |
6523 | g_free(pmevtyper_el0_name); | |
6524 | } | |
a6179538 | 6525 | if (cpu_isar_feature(aa32_pmu_8_1, cpu)) { |
24183fb6 PM |
6526 | ARMCPRegInfo v81_pmu_regs[] = { |
6527 | { .name = "PMCEID2", .state = ARM_CP_STATE_AA32, | |
6528 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4, | |
6529 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6530 | .resetvalue = extract64(cpu->pmceid0, 32, 32) }, | |
6531 | { .name = "PMCEID3", .state = ARM_CP_STATE_AA32, | |
6532 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5, | |
6533 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6534 | .resetvalue = extract64(cpu->pmceid1, 32, 32) }, | |
6535 | REGINFO_SENTINEL | |
6536 | }; | |
6537 | define_arm_cp_regs(cpu, v81_pmu_regs); | |
6538 | } | |
15dd1ebd PM |
6539 | if (cpu_isar_feature(any_pmu_8_4, cpu)) { |
6540 | static const ARMCPRegInfo v84_pmmir = { | |
6541 | .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH, | |
6542 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6, | |
6543 | .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6544 | .resetvalue = 0 | |
6545 | }; | |
6546 | define_one_arm_cp_reg(cpu, &v84_pmmir); | |
6547 | } | |
24183fb6 PM |
6548 | } |
6549 | ||
96a8b92e PM |
6550 | /* We don't know until after realize whether there's a GICv3 |
6551 | * attached, and that is what registers the gicv3 sysregs. | |
6552 | * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1 | |
6553 | * at runtime. | |
6554 | */ | |
6555 | static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
6556 | { | |
2fc0cc0e | 6557 | ARMCPU *cpu = env_archcpu(env); |
96a8b92e PM |
6558 | uint64_t pfr1 = cpu->id_pfr1; |
6559 | ||
6560 | if (env->gicv3state) { | |
6561 | pfr1 |= 1 << 28; | |
6562 | } | |
6563 | return pfr1; | |
6564 | } | |
6565 | ||
6566 | static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
6567 | { | |
2fc0cc0e | 6568 | ARMCPU *cpu = env_archcpu(env); |
47576b94 | 6569 | uint64_t pfr0 = cpu->isar.id_aa64pfr0; |
96a8b92e PM |
6570 | |
6571 | if (env->gicv3state) { | |
6572 | pfr0 |= 1 << 24; | |
6573 | } | |
6574 | return pfr0; | |
6575 | } | |
6576 | ||
2d7137c1 RH |
6577 | /* Shared logic between LORID and the rest of the LOR* registers. |
6578 | * Secure state has already been delt with. | |
6579 | */ | |
6580 | static CPAccessResult access_lor_ns(CPUARMState *env) | |
6581 | { | |
6582 | int el = arm_current_el(env); | |
6583 | ||
6584 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) { | |
6585 | return CP_ACCESS_TRAP_EL2; | |
6586 | } | |
6587 | if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { | |
6588 | return CP_ACCESS_TRAP_EL3; | |
6589 | } | |
6590 | return CP_ACCESS_OK; | |
6591 | } | |
6592 | ||
6593 | static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri, | |
6594 | bool isread) | |
6595 | { | |
6596 | if (arm_is_secure_below_el3(env)) { | |
6597 | /* Access ok in secure mode. */ | |
6598 | return CP_ACCESS_OK; | |
6599 | } | |
6600 | return access_lor_ns(env); | |
6601 | } | |
6602 | ||
6603 | static CPAccessResult access_lor_other(CPUARMState *env, | |
6604 | const ARMCPRegInfo *ri, bool isread) | |
6605 | { | |
6606 | if (arm_is_secure_below_el3(env)) { | |
6607 | /* Access denied in secure mode. */ | |
6608 | return CP_ACCESS_TRAP; | |
6609 | } | |
6610 | return access_lor_ns(env); | |
6611 | } | |
6612 | ||
d8564ee4 RH |
6613 | /* |
6614 | * A trivial implementation of ARMv8.1-LOR leaves all of these | |
6615 | * registers fixed at 0, which indicates that there are zero | |
6616 | * supported Limited Ordering regions. | |
6617 | */ | |
6618 | static const ARMCPRegInfo lor_reginfo[] = { | |
6619 | { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, | |
6620 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, | |
6621 | .access = PL1_RW, .accessfn = access_lor_other, | |
6622 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6623 | { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, | |
6624 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, | |
6625 | .access = PL1_RW, .accessfn = access_lor_other, | |
6626 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6627 | { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, | |
6628 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, | |
6629 | .access = PL1_RW, .accessfn = access_lor_other, | |
6630 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6631 | { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, | |
6632 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, | |
6633 | .access = PL1_RW, .accessfn = access_lor_other, | |
6634 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6635 | { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, | |
6636 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, | |
6637 | .access = PL1_R, .accessfn = access_lorid, | |
6638 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6639 | REGINFO_SENTINEL | |
6640 | }; | |
6641 | ||
967aa94f RH |
6642 | #ifdef TARGET_AARCH64 |
6643 | static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, | |
6644 | bool isread) | |
6645 | { | |
6646 | int el = arm_current_el(env); | |
6647 | ||
6648 | if (el < 2 && | |
6649 | arm_feature(env, ARM_FEATURE_EL2) && | |
6650 | !(arm_hcr_el2_eff(env) & HCR_APK)) { | |
6651 | return CP_ACCESS_TRAP_EL2; | |
6652 | } | |
6653 | if (el < 3 && | |
6654 | arm_feature(env, ARM_FEATURE_EL3) && | |
6655 | !(env->cp15.scr_el3 & SCR_APK)) { | |
6656 | return CP_ACCESS_TRAP_EL3; | |
6657 | } | |
6658 | return CP_ACCESS_OK; | |
6659 | } | |
6660 | ||
6661 | static const ARMCPRegInfo pauth_reginfo[] = { | |
6662 | { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64, | |
6663 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0, | |
6664 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6665 | .fieldoffset = offsetof(CPUARMState, keys.apda.lo) }, |
967aa94f RH |
6666 | { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6667 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1, | |
6668 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6669 | .fieldoffset = offsetof(CPUARMState, keys.apda.hi) }, |
967aa94f RH |
6670 | { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
6671 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2, | |
6672 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6673 | .fieldoffset = offsetof(CPUARMState, keys.apdb.lo) }, |
967aa94f RH |
6674 | { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6675 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3, | |
6676 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6677 | .fieldoffset = offsetof(CPUARMState, keys.apdb.hi) }, |
967aa94f RH |
6678 | { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
6679 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0, | |
6680 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6681 | .fieldoffset = offsetof(CPUARMState, keys.apga.lo) }, |
967aa94f RH |
6682 | { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6683 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1, | |
6684 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6685 | .fieldoffset = offsetof(CPUARMState, keys.apga.hi) }, |
967aa94f RH |
6686 | { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
6687 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0, | |
6688 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6689 | .fieldoffset = offsetof(CPUARMState, keys.apia.lo) }, |
967aa94f RH |
6690 | { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6691 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1, | |
6692 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6693 | .fieldoffset = offsetof(CPUARMState, keys.apia.hi) }, |
967aa94f RH |
6694 | { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
6695 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2, | |
6696 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6697 | .fieldoffset = offsetof(CPUARMState, keys.apib.lo) }, |
967aa94f RH |
6698 | { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6699 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3, | |
6700 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6701 | .fieldoffset = offsetof(CPUARMState, keys.apib.hi) }, |
967aa94f RH |
6702 | REGINFO_SENTINEL |
6703 | }; | |
de390645 RH |
6704 | |
6705 | static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) | |
6706 | { | |
6707 | Error *err = NULL; | |
6708 | uint64_t ret; | |
6709 | ||
6710 | /* Success sets NZCV = 0000. */ | |
6711 | env->NF = env->CF = env->VF = 0, env->ZF = 1; | |
6712 | ||
6713 | if (qemu_guest_getrandom(&ret, sizeof(ret), &err) < 0) { | |
6714 | /* | |
6715 | * ??? Failed, for unknown reasons in the crypto subsystem. | |
6716 | * The best we can do is log the reason and return the | |
6717 | * timed-out indication to the guest. There is no reason | |
6718 | * we know to expect this failure to be transitory, so the | |
6719 | * guest may well hang retrying the operation. | |
6720 | */ | |
6721 | qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", | |
6722 | ri->name, error_get_pretty(err)); | |
6723 | error_free(err); | |
6724 | ||
6725 | env->ZF = 0; /* NZCF = 0100 */ | |
6726 | return 0; | |
6727 | } | |
6728 | return ret; | |
6729 | } | |
6730 | ||
6731 | /* We do not support re-seeding, so the two registers operate the same. */ | |
6732 | static const ARMCPRegInfo rndr_reginfo[] = { | |
6733 | { .name = "RNDR", .state = ARM_CP_STATE_AA64, | |
6734 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | |
6735 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 0, | |
6736 | .access = PL0_R, .readfn = rndr_readfn }, | |
6737 | { .name = "RNDRRS", .state = ARM_CP_STATE_AA64, | |
6738 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | |
6739 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1, | |
6740 | .access = PL0_R, .readfn = rndr_readfn }, | |
6741 | REGINFO_SENTINEL | |
6742 | }; | |
0d57b499 BM |
6743 | |
6744 | #ifndef CONFIG_USER_ONLY | |
6745 | static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, | |
6746 | uint64_t value) | |
6747 | { | |
6748 | ARMCPU *cpu = env_archcpu(env); | |
6749 | /* CTR_EL0 System register -> DminLine, bits [19:16] */ | |
6750 | uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF); | |
6751 | uint64_t vaddr_in = (uint64_t) value; | |
6752 | uint64_t vaddr = vaddr_in & ~(dline_size - 1); | |
6753 | void *haddr; | |
6754 | int mem_idx = cpu_mmu_index(env, false); | |
6755 | ||
6756 | /* This won't be crossing page boundaries */ | |
6757 | haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC()); | |
6758 | if (haddr) { | |
6759 | ||
6760 | ram_addr_t offset; | |
6761 | MemoryRegion *mr; | |
6762 | ||
6763 | /* RCU lock is already being held */ | |
6764 | mr = memory_region_from_host(haddr, &offset); | |
6765 | ||
6766 | if (mr) { | |
6767 | memory_region_do_writeback(mr, offset, dline_size); | |
6768 | } | |
6769 | } | |
6770 | } | |
6771 | ||
6772 | static const ARMCPRegInfo dcpop_reg[] = { | |
6773 | { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64, | |
6774 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1, | |
6775 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | |
1bed4d2e | 6776 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, |
0d57b499 BM |
6777 | REGINFO_SENTINEL |
6778 | }; | |
6779 | ||
6780 | static const ARMCPRegInfo dcpodp_reg[] = { | |
6781 | { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64, | |
6782 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1, | |
6783 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | |
1bed4d2e | 6784 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, |
0d57b499 BM |
6785 | REGINFO_SENTINEL |
6786 | }; | |
6787 | #endif /*CONFIG_USER_ONLY*/ | |
6788 | ||
967aa94f RH |
6789 | #endif |
6790 | ||
cb570bd3 RH |
6791 | static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, |
6792 | bool isread) | |
6793 | { | |
6794 | int el = arm_current_el(env); | |
6795 | ||
6796 | if (el == 0) { | |
6797 | uint64_t sctlr = arm_sctlr(env, el); | |
6798 | if (!(sctlr & SCTLR_EnRCTX)) { | |
6799 | return CP_ACCESS_TRAP; | |
6800 | } | |
6801 | } else if (el == 1) { | |
6802 | uint64_t hcr = arm_hcr_el2_eff(env); | |
6803 | if (hcr & HCR_NV) { | |
6804 | return CP_ACCESS_TRAP_EL2; | |
6805 | } | |
6806 | } | |
6807 | return CP_ACCESS_OK; | |
6808 | } | |
6809 | ||
6810 | static const ARMCPRegInfo predinv_reginfo[] = { | |
6811 | { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64, | |
6812 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4, | |
6813 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
6814 | { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64, | |
6815 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5, | |
6816 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
6817 | { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64, | |
6818 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7, | |
6819 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
6820 | /* | |
6821 | * Note the AArch32 opcodes have a different OPC1. | |
6822 | */ | |
6823 | { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32, | |
6824 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4, | |
6825 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
6826 | { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32, | |
6827 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5, | |
6828 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
6829 | { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32, | |
6830 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7, | |
6831 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
6832 | REGINFO_SENTINEL | |
6833 | }; | |
6834 | ||
957e6155 PM |
6835 | static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri) |
6836 | { | |
6837 | /* Read the high 32 bits of the current CCSIDR */ | |
6838 | return extract64(ccsidr_read(env, ri), 32, 32); | |
6839 | } | |
6840 | ||
6841 | static const ARMCPRegInfo ccsidr2_reginfo[] = { | |
6842 | { .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH, | |
6843 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2, | |
6844 | .access = PL1_R, | |
6845 | .accessfn = access_aa64_tid2, | |
6846 | .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW }, | |
6847 | REGINFO_SENTINEL | |
6848 | }; | |
6849 | ||
6a4ef4e5 MZ |
6850 | static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri, |
6851 | bool isread) | |
6852 | { | |
6853 | if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) { | |
6854 | return CP_ACCESS_TRAP_EL2; | |
6855 | } | |
6856 | ||
6857 | return CP_ACCESS_OK; | |
6858 | } | |
6859 | ||
6860 | static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri, | |
6861 | bool isread) | |
6862 | { | |
6863 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
6864 | return access_aa64_tid3(env, ri, isread); | |
6865 | } | |
6866 | ||
6867 | return CP_ACCESS_OK; | |
6868 | } | |
6869 | ||
f96f3d5f MZ |
6870 | static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri, |
6871 | bool isread) | |
6872 | { | |
6873 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID0)) { | |
6874 | return CP_ACCESS_TRAP_EL2; | |
6875 | } | |
6876 | ||
6877 | return CP_ACCESS_OK; | |
6878 | } | |
6879 | ||
6880 | static const ARMCPRegInfo jazelle_regs[] = { | |
6881 | { .name = "JIDR", | |
6882 | .cp = 14, .crn = 0, .crm = 0, .opc1 = 7, .opc2 = 0, | |
6883 | .access = PL1_R, .accessfn = access_jazelle, | |
6884 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6885 | { .name = "JOSCR", | |
6886 | .cp = 14, .crn = 1, .crm = 0, .opc1 = 7, .opc2 = 0, | |
6887 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6888 | { .name = "JMCR", | |
6889 | .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0, | |
6890 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6891 | REGINFO_SENTINEL | |
6892 | }; | |
6893 | ||
e2a1a461 RH |
6894 | static const ARMCPRegInfo vhe_reginfo[] = { |
6895 | { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, | |
6896 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, | |
6897 | .access = PL2_RW, | |
6898 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) }, | |
ed30da8e RH |
6899 | { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, |
6900 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, | |
6901 | .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, | |
6902 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) }, | |
8c94b071 RH |
6903 | #ifndef CONFIG_USER_ONLY |
6904 | { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64, | |
6905 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 2, | |
6906 | .fieldoffset = | |
6907 | offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval), | |
6908 | .type = ARM_CP_IO, .access = PL2_RW, | |
6909 | .writefn = gt_hv_cval_write, .raw_writefn = raw_write }, | |
6910 | { .name = "CNTHV_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
6911 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 0, | |
6912 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, | |
6913 | .resetfn = gt_hv_timer_reset, | |
6914 | .readfn = gt_hv_tval_read, .writefn = gt_hv_tval_write }, | |
6915 | { .name = "CNTHV_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
6916 | .type = ARM_CP_IO, | |
6917 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 1, | |
6918 | .access = PL2_RW, | |
6919 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].ctl), | |
6920 | .writefn = gt_hv_ctl_write, .raw_writefn = raw_write }, | |
bb5972e4 RH |
6921 | { .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64, |
6922 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1, | |
6923 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6924 | .access = PL2_RW, .accessfn = e2h_access, | |
6925 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), | |
6926 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write }, | |
6927 | { .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64, | |
6928 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1, | |
6929 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6930 | .access = PL2_RW, .accessfn = e2h_access, | |
6931 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), | |
6932 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write }, | |
6933 | { .name = "CNTP_TVAL_EL02", .state = ARM_CP_STATE_AA64, | |
6934 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 0, | |
6935 | .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, | |
6936 | .access = PL2_RW, .accessfn = e2h_access, | |
6937 | .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write }, | |
6938 | { .name = "CNTV_TVAL_EL02", .state = ARM_CP_STATE_AA64, | |
6939 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 0, | |
6940 | .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, | |
6941 | .access = PL2_RW, .accessfn = e2h_access, | |
6942 | .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write }, | |
6943 | { .name = "CNTP_CVAL_EL02", .state = ARM_CP_STATE_AA64, | |
6944 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 2, | |
6945 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6946 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
6947 | .access = PL2_RW, .accessfn = e2h_access, | |
6948 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write }, | |
6949 | { .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64, | |
6950 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2, | |
6951 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6952 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
6953 | .access = PL2_RW, .accessfn = e2h_access, | |
6954 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write }, | |
8c94b071 | 6955 | #endif |
e2a1a461 RH |
6956 | REGINFO_SENTINEL |
6957 | }; | |
6958 | ||
04b07d29 RH |
6959 | #ifndef CONFIG_USER_ONLY |
6960 | static const ARMCPRegInfo ats1e1_reginfo[] = { | |
6961 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
6962 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, | |
6963 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
6964 | .writefn = ats_write64 }, | |
6965 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, | |
6966 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, | |
6967 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
6968 | .writefn = ats_write64 }, | |
6969 | REGINFO_SENTINEL | |
6970 | }; | |
6971 | ||
6972 | static const ARMCPRegInfo ats1cp_reginfo[] = { | |
6973 | { .name = "ATS1CPRP", | |
6974 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, | |
6975 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
6976 | .writefn = ats_write }, | |
6977 | { .name = "ATS1CPWP", | |
6978 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, | |
6979 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
6980 | .writefn = ats_write }, | |
6981 | REGINFO_SENTINEL | |
6982 | }; | |
6983 | #endif | |
6984 | ||
f6287c24 PM |
6985 | /* |
6986 | * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and | |
6987 | * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field | |
6988 | * is non-zero, which is never for ARMv7, optionally in ARMv8 | |
6989 | * and mandatorily for ARMv8.2 and up. | |
6990 | * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's | |
6991 | * implementation is RAZ/WI we can ignore this detail, as we | |
6992 | * do for ACTLR. | |
6993 | */ | |
6994 | static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = { | |
6995 | { .name = "ACTLR2", .state = ARM_CP_STATE_AA32, | |
6996 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 3, | |
99602377 RH |
6997 | .access = PL1_RW, .accessfn = access_tacr, |
6998 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
f6287c24 PM |
6999 | { .name = "HACTLR2", .state = ARM_CP_STATE_AA32, |
7000 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3, | |
7001 | .access = PL2_RW, .type = ARM_CP_CONST, | |
7002 | .resetvalue = 0 }, | |
7003 | REGINFO_SENTINEL | |
7004 | }; | |
7005 | ||
2ceb98c0 PM |
7006 | void register_cp_regs_for_features(ARMCPU *cpu) |
7007 | { | |
7008 | /* Register all the coprocessor registers based on feature bits */ | |
7009 | CPUARMState *env = &cpu->env; | |
7010 | if (arm_feature(env, ARM_FEATURE_M)) { | |
7011 | /* M profile has no coprocessor registers */ | |
7012 | return; | |
7013 | } | |
7014 | ||
e9aa6c21 | 7015 | define_arm_cp_regs(cpu, cp_reginfo); |
9449fdf6 PM |
7016 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
7017 | /* Must go early as it is full of wildcards that may be | |
7018 | * overridden by later definitions. | |
7019 | */ | |
7020 | define_arm_cp_regs(cpu, not_v8_cp_reginfo); | |
7021 | } | |
7022 | ||
7d57f408 | 7023 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8515a092 PM |
7024 | /* The ID registers all have impdef reset values */ |
7025 | ARMCPRegInfo v6_idregs[] = { | |
0ff644a7 PM |
7026 | { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, |
7027 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
7028 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7029 | .accessfn = access_aa32_tid3, |
8515a092 | 7030 | .resetvalue = cpu->id_pfr0 }, |
96a8b92e PM |
7031 | /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know |
7032 | * the value of the GIC field until after we define these regs. | |
7033 | */ | |
0ff644a7 PM |
7034 | { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, |
7035 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | |
96a8b92e | 7036 | .access = PL1_R, .type = ARM_CP_NO_RAW, |
6a4ef4e5 | 7037 | .accessfn = access_aa32_tid3, |
96a8b92e PM |
7038 | .readfn = id_pfr1_read, |
7039 | .writefn = arm_cp_write_ignore }, | |
0ff644a7 PM |
7040 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, |
7041 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | |
7042 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7043 | .accessfn = access_aa32_tid3, |
a6179538 | 7044 | .resetvalue = cpu->isar.id_dfr0 }, |
0ff644a7 PM |
7045 | { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, |
7046 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, | |
7047 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7048 | .accessfn = access_aa32_tid3, |
8515a092 | 7049 | .resetvalue = cpu->id_afr0 }, |
0ff644a7 PM |
7050 | { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, |
7051 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, | |
7052 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7053 | .accessfn = access_aa32_tid3, |
10054016 | 7054 | .resetvalue = cpu->isar.id_mmfr0 }, |
0ff644a7 PM |
7055 | { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, |
7056 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, | |
7057 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7058 | .accessfn = access_aa32_tid3, |
10054016 | 7059 | .resetvalue = cpu->isar.id_mmfr1 }, |
0ff644a7 PM |
7060 | { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, |
7061 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, | |
7062 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7063 | .accessfn = access_aa32_tid3, |
10054016 | 7064 | .resetvalue = cpu->isar.id_mmfr2 }, |
0ff644a7 PM |
7065 | { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, |
7066 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, | |
7067 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7068 | .accessfn = access_aa32_tid3, |
10054016 | 7069 | .resetvalue = cpu->isar.id_mmfr3 }, |
0ff644a7 PM |
7070 | { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, |
7071 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
7072 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7073 | .accessfn = access_aa32_tid3, |
47576b94 | 7074 | .resetvalue = cpu->isar.id_isar0 }, |
0ff644a7 PM |
7075 | { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, |
7076 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, | |
7077 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7078 | .accessfn = access_aa32_tid3, |
47576b94 | 7079 | .resetvalue = cpu->isar.id_isar1 }, |
0ff644a7 PM |
7080 | { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, |
7081 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
7082 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7083 | .accessfn = access_aa32_tid3, |
47576b94 | 7084 | .resetvalue = cpu->isar.id_isar2 }, |
0ff644a7 PM |
7085 | { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, |
7086 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, | |
7087 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7088 | .accessfn = access_aa32_tid3, |
47576b94 | 7089 | .resetvalue = cpu->isar.id_isar3 }, |
0ff644a7 PM |
7090 | { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, |
7091 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, | |
7092 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7093 | .accessfn = access_aa32_tid3, |
47576b94 | 7094 | .resetvalue = cpu->isar.id_isar4 }, |
0ff644a7 PM |
7095 | { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, |
7096 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, | |
7097 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7098 | .accessfn = access_aa32_tid3, |
47576b94 | 7099 | .resetvalue = cpu->isar.id_isar5 }, |
e20d84c1 PM |
7100 | { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, |
7101 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, | |
7102 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7103 | .accessfn = access_aa32_tid3, |
10054016 | 7104 | .resetvalue = cpu->isar.id_mmfr4 }, |
802abf40 | 7105 | { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
7106 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, |
7107 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7108 | .accessfn = access_aa32_tid3, |
47576b94 | 7109 | .resetvalue = cpu->isar.id_isar6 }, |
8515a092 PM |
7110 | REGINFO_SENTINEL |
7111 | }; | |
7112 | define_arm_cp_regs(cpu, v6_idregs); | |
7d57f408 PM |
7113 | define_arm_cp_regs(cpu, v6_cp_reginfo); |
7114 | } else { | |
7115 | define_arm_cp_regs(cpu, not_v6_cp_reginfo); | |
7116 | } | |
4d31c596 PM |
7117 | if (arm_feature(env, ARM_FEATURE_V6K)) { |
7118 | define_arm_cp_regs(cpu, v6k_cp_reginfo); | |
7119 | } | |
5e5cf9e3 | 7120 | if (arm_feature(env, ARM_FEATURE_V7MP) && |
452a0955 | 7121 | !arm_feature(env, ARM_FEATURE_PMSA)) { |
995939a6 PM |
7122 | define_arm_cp_regs(cpu, v7mp_cp_reginfo); |
7123 | } | |
327dd510 AL |
7124 | if (arm_feature(env, ARM_FEATURE_V7VE)) { |
7125 | define_arm_cp_regs(cpu, pmovsset_cp_reginfo); | |
7126 | } | |
e9aa6c21 | 7127 | if (arm_feature(env, ARM_FEATURE_V7)) { |
776d4e5c | 7128 | ARMCPRegInfo clidr = { |
7da845b0 PM |
7129 | .name = "CLIDR", .state = ARM_CP_STATE_BOTH, |
7130 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | |
630fcd4d MZ |
7131 | .access = PL1_R, .type = ARM_CP_CONST, |
7132 | .accessfn = access_aa64_tid2, | |
7133 | .resetvalue = cpu->clidr | |
776d4e5c | 7134 | }; |
776d4e5c | 7135 | define_one_arm_cp_reg(cpu, &clidr); |
e9aa6c21 | 7136 | define_arm_cp_regs(cpu, v7_cp_reginfo); |
50300698 | 7137 | define_debug_regs(cpu); |
24183fb6 | 7138 | define_pmu_regs(cpu); |
7d57f408 PM |
7139 | } else { |
7140 | define_arm_cp_regs(cpu, not_v7_cp_reginfo); | |
e9aa6c21 | 7141 | } |
b0d2b7d0 | 7142 | if (arm_feature(env, ARM_FEATURE_V8)) { |
e20d84c1 PM |
7143 | /* AArch64 ID registers, which all have impdef reset values. |
7144 | * Note that within the ID register ranges the unused slots | |
7145 | * must all RAZ, not UNDEF; future architecture versions may | |
7146 | * define new registers here. | |
7147 | */ | |
e60cef86 | 7148 | ARMCPRegInfo v8_idregs[] = { |
96a8b92e PM |
7149 | /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't |
7150 | * know the right value for the GIC field until after we | |
7151 | * define these regs. | |
7152 | */ | |
e60cef86 PM |
7153 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, |
7154 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | |
96a8b92e | 7155 | .access = PL1_R, .type = ARM_CP_NO_RAW, |
6a4ef4e5 | 7156 | .accessfn = access_aa64_tid3, |
96a8b92e PM |
7157 | .readfn = id_aa64pfr0_read, |
7158 | .writefn = arm_cp_write_ignore }, | |
e60cef86 PM |
7159 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, |
7160 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | |
7161 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7162 | .accessfn = access_aa64_tid3, |
47576b94 | 7163 | .resetvalue = cpu->isar.id_aa64pfr1}, |
e20d84c1 PM |
7164 | { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7165 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, | |
7166 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7167 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7168 | .resetvalue = 0 }, |
7169 | { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7170 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, | |
7171 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7172 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7173 | .resetvalue = 0 }, |
9516d772 | 7174 | { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
7175 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, |
7176 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7177 | .accessfn = access_aa64_tid3, |
9516d772 | 7178 | /* At present, only SVEver == 0 is defined anyway. */ |
e20d84c1 PM |
7179 | .resetvalue = 0 }, |
7180 | { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7181 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, | |
7182 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7183 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7184 | .resetvalue = 0 }, |
7185 | { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7186 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, | |
7187 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7188 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7189 | .resetvalue = 0 }, |
7190 | { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7191 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, | |
7192 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7193 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7194 | .resetvalue = 0 }, |
e60cef86 PM |
7195 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, |
7196 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | |
7197 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7198 | .accessfn = access_aa64_tid3, |
2a609df8 | 7199 | .resetvalue = cpu->isar.id_aa64dfr0 }, |
e60cef86 PM |
7200 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, |
7201 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | |
7202 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7203 | .accessfn = access_aa64_tid3, |
2a609df8 | 7204 | .resetvalue = cpu->isar.id_aa64dfr1 }, |
e20d84c1 PM |
7205 | { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7206 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, | |
7207 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7208 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7209 | .resetvalue = 0 }, |
7210 | { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7211 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, | |
7212 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7213 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7214 | .resetvalue = 0 }, |
e60cef86 PM |
7215 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, |
7216 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | |
7217 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7218 | .accessfn = access_aa64_tid3, |
e60cef86 PM |
7219 | .resetvalue = cpu->id_aa64afr0 }, |
7220 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | |
7221 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | |
7222 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7223 | .accessfn = access_aa64_tid3, |
e60cef86 | 7224 | .resetvalue = cpu->id_aa64afr1 }, |
e20d84c1 PM |
7225 | { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7226 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, | |
7227 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7228 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7229 | .resetvalue = 0 }, |
7230 | { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7231 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, | |
7232 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7233 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7234 | .resetvalue = 0 }, |
e60cef86 PM |
7235 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, |
7236 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | |
7237 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7238 | .accessfn = access_aa64_tid3, |
47576b94 | 7239 | .resetvalue = cpu->isar.id_aa64isar0 }, |
e60cef86 PM |
7240 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, |
7241 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | |
7242 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7243 | .accessfn = access_aa64_tid3, |
47576b94 | 7244 | .resetvalue = cpu->isar.id_aa64isar1 }, |
e20d84c1 PM |
7245 | { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7246 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, | |
7247 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7248 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7249 | .resetvalue = 0 }, |
7250 | { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7251 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, | |
7252 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7253 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7254 | .resetvalue = 0 }, |
7255 | { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7256 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, | |
7257 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7258 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7259 | .resetvalue = 0 }, |
7260 | { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7261 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, | |
7262 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7263 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7264 | .resetvalue = 0 }, |
7265 | { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7266 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, | |
7267 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7268 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7269 | .resetvalue = 0 }, |
7270 | { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7271 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, | |
7272 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7273 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7274 | .resetvalue = 0 }, |
e60cef86 PM |
7275 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, |
7276 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
7277 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7278 | .accessfn = access_aa64_tid3, |
3dc91ddb | 7279 | .resetvalue = cpu->isar.id_aa64mmfr0 }, |
e60cef86 PM |
7280 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, |
7281 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | |
7282 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7283 | .accessfn = access_aa64_tid3, |
3dc91ddb | 7284 | .resetvalue = cpu->isar.id_aa64mmfr1 }, |
64761e10 | 7285 | { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
7286 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, |
7287 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7288 | .accessfn = access_aa64_tid3, |
64761e10 | 7289 | .resetvalue = cpu->isar.id_aa64mmfr2 }, |
e20d84c1 PM |
7290 | { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7291 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, | |
7292 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7293 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7294 | .resetvalue = 0 }, |
7295 | { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7296 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, | |
7297 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7298 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7299 | .resetvalue = 0 }, |
7300 | { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7301 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, | |
7302 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7303 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7304 | .resetvalue = 0 }, |
7305 | { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7306 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, | |
7307 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7308 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7309 | .resetvalue = 0 }, |
7310 | { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7311 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, | |
7312 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7313 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7314 | .resetvalue = 0 }, |
a50c0f51 PM |
7315 | { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, |
7316 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
7317 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7318 | .accessfn = access_aa64_tid3, |
47576b94 | 7319 | .resetvalue = cpu->isar.mvfr0 }, |
a50c0f51 PM |
7320 | { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, |
7321 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
7322 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7323 | .accessfn = access_aa64_tid3, |
47576b94 | 7324 | .resetvalue = cpu->isar.mvfr1 }, |
a50c0f51 PM |
7325 | { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, |
7326 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
7327 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7328 | .accessfn = access_aa64_tid3, |
47576b94 | 7329 | .resetvalue = cpu->isar.mvfr2 }, |
e20d84c1 PM |
7330 | { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7331 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, | |
7332 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7333 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7334 | .resetvalue = 0 }, |
7335 | { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7336 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, | |
7337 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7338 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7339 | .resetvalue = 0 }, |
7340 | { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7341 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, | |
7342 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7343 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7344 | .resetvalue = 0 }, |
7345 | { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7346 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, | |
7347 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7348 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7349 | .resetvalue = 0 }, |
7350 | { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7351 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, | |
7352 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7353 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7354 | .resetvalue = 0 }, |
4054bfa9 AF |
7355 | { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, |
7356 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, | |
7357 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
cad86737 | 7358 | .resetvalue = extract64(cpu->pmceid0, 0, 32) }, |
4054bfa9 AF |
7359 | { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, |
7360 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, | |
7361 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
7362 | .resetvalue = cpu->pmceid0 }, | |
7363 | { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, | |
7364 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, | |
7365 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
cad86737 | 7366 | .resetvalue = extract64(cpu->pmceid1, 0, 32) }, |
4054bfa9 AF |
7367 | { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, |
7368 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, | |
7369 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
7370 | .resetvalue = cpu->pmceid1 }, | |
e60cef86 PM |
7371 | REGINFO_SENTINEL |
7372 | }; | |
6c5c0fec AB |
7373 | #ifdef CONFIG_USER_ONLY |
7374 | ARMCPRegUserSpaceInfo v8_user_idregs[] = { | |
7375 | { .name = "ID_AA64PFR0_EL1", | |
7376 | .exported_bits = 0x000f000f00ff0000, | |
7377 | .fixed_bits = 0x0000000000000011 }, | |
7378 | { .name = "ID_AA64PFR1_EL1", | |
7379 | .exported_bits = 0x00000000000000f0 }, | |
d040242e AB |
7380 | { .name = "ID_AA64PFR*_EL1_RESERVED", |
7381 | .is_glob = true }, | |
6c5c0fec AB |
7382 | { .name = "ID_AA64ZFR0_EL1" }, |
7383 | { .name = "ID_AA64MMFR0_EL1", | |
7384 | .fixed_bits = 0x00000000ff000000 }, | |
7385 | { .name = "ID_AA64MMFR1_EL1" }, | |
d040242e AB |
7386 | { .name = "ID_AA64MMFR*_EL1_RESERVED", |
7387 | .is_glob = true }, | |
6c5c0fec AB |
7388 | { .name = "ID_AA64DFR0_EL1", |
7389 | .fixed_bits = 0x0000000000000006 }, | |
7390 | { .name = "ID_AA64DFR1_EL1" }, | |
d040242e AB |
7391 | { .name = "ID_AA64DFR*_EL1_RESERVED", |
7392 | .is_glob = true }, | |
7393 | { .name = "ID_AA64AFR*", | |
7394 | .is_glob = true }, | |
6c5c0fec AB |
7395 | { .name = "ID_AA64ISAR0_EL1", |
7396 | .exported_bits = 0x00fffffff0fffff0 }, | |
7397 | { .name = "ID_AA64ISAR1_EL1", | |
7398 | .exported_bits = 0x000000f0ffffffff }, | |
d040242e AB |
7399 | { .name = "ID_AA64ISAR*_EL1_RESERVED", |
7400 | .is_glob = true }, | |
6c5c0fec AB |
7401 | REGUSERINFO_SENTINEL |
7402 | }; | |
7403 | modify_arm_cp_regs(v8_idregs, v8_user_idregs); | |
7404 | #endif | |
be8e8128 GB |
7405 | /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ |
7406 | if (!arm_feature(env, ARM_FEATURE_EL3) && | |
7407 | !arm_feature(env, ARM_FEATURE_EL2)) { | |
7408 | ARMCPRegInfo rvbar = { | |
7409 | .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, | |
7410 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, | |
7411 | .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar | |
7412 | }; | |
7413 | define_one_arm_cp_reg(cpu, &rvbar); | |
7414 | } | |
e60cef86 | 7415 | define_arm_cp_regs(cpu, v8_idregs); |
b0d2b7d0 PM |
7416 | define_arm_cp_regs(cpu, v8_cp_reginfo); |
7417 | } | |
3b685ba7 | 7418 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
f0d574d6 | 7419 | uint64_t vmpidr_def = mpidr_read_val(env); |
731de9e6 EI |
7420 | ARMCPRegInfo vpidr_regs[] = { |
7421 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | |
7422 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
7423 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
36476562 PM |
7424 | .resetvalue = cpu->midr, .type = ARM_CP_ALIAS, |
7425 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) }, | |
731de9e6 EI |
7426 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, |
7427 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
7428 | .access = PL2_RW, .resetvalue = cpu->midr, | |
7429 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
f0d574d6 EI |
7430 | { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, |
7431 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
7432 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
36476562 PM |
7433 | .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS, |
7434 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) }, | |
f0d574d6 EI |
7435 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, |
7436 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
7437 | .access = PL2_RW, | |
7438 | .resetvalue = vmpidr_def, | |
7439 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | |
731de9e6 EI |
7440 | REGINFO_SENTINEL |
7441 | }; | |
7442 | define_arm_cp_regs(cpu, vpidr_regs); | |
4771cd01 | 7443 | define_arm_cp_regs(cpu, el2_cp_reginfo); |
ce4afed8 PM |
7444 | if (arm_feature(env, ARM_FEATURE_V8)) { |
7445 | define_arm_cp_regs(cpu, el2_v8_cp_reginfo); | |
7446 | } | |
be8e8128 GB |
7447 | /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ |
7448 | if (!arm_feature(env, ARM_FEATURE_EL3)) { | |
7449 | ARMCPRegInfo rvbar = { | |
7450 | .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, | |
7451 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, | |
7452 | .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar | |
7453 | }; | |
7454 | define_one_arm_cp_reg(cpu, &rvbar); | |
7455 | } | |
d42e3c26 EI |
7456 | } else { |
7457 | /* If EL2 is missing but higher ELs are enabled, we need to | |
7458 | * register the no_el2 reginfos. | |
7459 | */ | |
7460 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
f0d574d6 EI |
7461 | /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value |
7462 | * of MIDR_EL1 and MPIDR_EL1. | |
731de9e6 EI |
7463 | */ |
7464 | ARMCPRegInfo vpidr_regs[] = { | |
7465 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH, | |
7466 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
7467 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
7468 | .type = ARM_CP_CONST, .resetvalue = cpu->midr, | |
7469 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
f0d574d6 EI |
7470 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
7471 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
7472 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
7473 | .type = ARM_CP_NO_RAW, | |
7474 | .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, | |
731de9e6 EI |
7475 | REGINFO_SENTINEL |
7476 | }; | |
7477 | define_arm_cp_regs(cpu, vpidr_regs); | |
4771cd01 | 7478 | define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); |
ce4afed8 PM |
7479 | if (arm_feature(env, ARM_FEATURE_V8)) { |
7480 | define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo); | |
7481 | } | |
d42e3c26 | 7482 | } |
3b685ba7 | 7483 | } |
81547d66 | 7484 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0f1a3b24 | 7485 | define_arm_cp_regs(cpu, el3_cp_reginfo); |
e24fdd23 PM |
7486 | ARMCPRegInfo el3_regs[] = { |
7487 | { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, | |
7488 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, | |
7489 | .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, | |
7490 | { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, | |
7491 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, | |
7492 | .access = PL3_RW, | |
7493 | .raw_writefn = raw_write, .writefn = sctlr_write, | |
7494 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), | |
7495 | .resetvalue = cpu->reset_sctlr }, | |
7496 | REGINFO_SENTINEL | |
be8e8128 | 7497 | }; |
e24fdd23 PM |
7498 | |
7499 | define_arm_cp_regs(cpu, el3_regs); | |
81547d66 | 7500 | } |
2f027fc5 PM |
7501 | /* The behaviour of NSACR is sufficiently various that we don't |
7502 | * try to describe it in a single reginfo: | |
7503 | * if EL3 is 64 bit, then trap to EL3 from S EL1, | |
7504 | * reads as constant 0xc00 from NS EL1 and NS EL2 | |
7505 | * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 | |
7506 | * if v7 without EL3, register doesn't exist | |
7507 | * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 | |
7508 | */ | |
7509 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
7510 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
7511 | ARMCPRegInfo nsacr = { | |
7512 | .name = "NSACR", .type = ARM_CP_CONST, | |
7513 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
7514 | .access = PL1_RW, .accessfn = nsacr_access, | |
7515 | .resetvalue = 0xc00 | |
7516 | }; | |
7517 | define_one_arm_cp_reg(cpu, &nsacr); | |
7518 | } else { | |
7519 | ARMCPRegInfo nsacr = { | |
7520 | .name = "NSACR", | |
7521 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
7522 | .access = PL3_RW | PL1_R, | |
7523 | .resetvalue = 0, | |
7524 | .fieldoffset = offsetof(CPUARMState, cp15.nsacr) | |
7525 | }; | |
7526 | define_one_arm_cp_reg(cpu, &nsacr); | |
7527 | } | |
7528 | } else { | |
7529 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
7530 | ARMCPRegInfo nsacr = { | |
7531 | .name = "NSACR", .type = ARM_CP_CONST, | |
7532 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
7533 | .access = PL1_R, | |
7534 | .resetvalue = 0xc00 | |
7535 | }; | |
7536 | define_one_arm_cp_reg(cpu, &nsacr); | |
7537 | } | |
7538 | } | |
7539 | ||
452a0955 | 7540 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
6cb0b013 PC |
7541 | if (arm_feature(env, ARM_FEATURE_V6)) { |
7542 | /* PMSAv6 not implemented */ | |
7543 | assert(arm_feature(env, ARM_FEATURE_V7)); | |
7544 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); | |
7545 | define_arm_cp_regs(cpu, pmsav7_cp_reginfo); | |
7546 | } else { | |
7547 | define_arm_cp_regs(cpu, pmsav5_cp_reginfo); | |
7548 | } | |
18032bec | 7549 | } else { |
8e5d75c9 | 7550 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); |
18032bec | 7551 | define_arm_cp_regs(cpu, vmsa_cp_reginfo); |
4036b7d1 PM |
7552 | /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */ |
7553 | if (cpu_isar_feature(aa32_hpd, cpu)) { | |
ab638a32 RH |
7554 | define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); |
7555 | } | |
18032bec | 7556 | } |
c326b979 PM |
7557 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
7558 | define_arm_cp_regs(cpu, t2ee_cp_reginfo); | |
7559 | } | |
6cc7a3ae PM |
7560 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
7561 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); | |
7562 | } | |
4a501606 PM |
7563 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
7564 | define_arm_cp_regs(cpu, vapa_cp_reginfo); | |
7565 | } | |
c4804214 PM |
7566 | if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { |
7567 | define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); | |
7568 | } | |
7569 | if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { | |
7570 | define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); | |
7571 | } | |
7572 | if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { | |
7573 | define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); | |
7574 | } | |
18032bec PM |
7575 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
7576 | define_arm_cp_regs(cpu, omap_cp_reginfo); | |
7577 | } | |
34f90529 PM |
7578 | if (arm_feature(env, ARM_FEATURE_STRONGARM)) { |
7579 | define_arm_cp_regs(cpu, strongarm_cp_reginfo); | |
7580 | } | |
1047b9d7 PM |
7581 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
7582 | define_arm_cp_regs(cpu, xscale_cp_reginfo); | |
7583 | } | |
7584 | if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { | |
7585 | define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); | |
7586 | } | |
7ac681cf PM |
7587 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
7588 | define_arm_cp_regs(cpu, lpae_cp_reginfo); | |
7589 | } | |
873b73c0 | 7590 | if (cpu_isar_feature(aa32_jazelle, cpu)) { |
f96f3d5f MZ |
7591 | define_arm_cp_regs(cpu, jazelle_regs); |
7592 | } | |
7884849c PM |
7593 | /* Slightly awkwardly, the OMAP and StrongARM cores need all of |
7594 | * cp15 crn=0 to be writes-ignored, whereas for other cores they should | |
7595 | * be read-only (ie write causes UNDEF exception). | |
7596 | */ | |
7597 | { | |
00a29f3d PM |
7598 | ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { |
7599 | /* Pre-v8 MIDR space. | |
7600 | * Note that the MIDR isn't a simple constant register because | |
7884849c PM |
7601 | * of the TI925 behaviour where writes to another register can |
7602 | * cause the MIDR value to change. | |
97ce8d61 PC |
7603 | * |
7604 | * Unimplemented registers in the c15 0 0 0 space default to | |
7605 | * MIDR. Define MIDR first as this entire space, then CTR, TCMTR | |
7606 | * and friends override accordingly. | |
7884849c PM |
7607 | */ |
7608 | { .name = "MIDR", | |
97ce8d61 | 7609 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, |
7884849c | 7610 | .access = PL1_R, .resetvalue = cpu->midr, |
d4e6df63 | 7611 | .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, |
731de9e6 | 7612 | .readfn = midr_read, |
97ce8d61 PC |
7613 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
7614 | .type = ARM_CP_OVERRIDE }, | |
7884849c PM |
7615 | /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ |
7616 | { .name = "DUMMY", | |
7617 | .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, | |
7618 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
7619 | { .name = "DUMMY", | |
7620 | .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, | |
7621 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
7622 | { .name = "DUMMY", | |
7623 | .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, | |
7624 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
7625 | { .name = "DUMMY", | |
7626 | .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, | |
7627 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
7628 | { .name = "DUMMY", | |
7629 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | |
7630 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
7631 | REGINFO_SENTINEL | |
7632 | }; | |
00a29f3d | 7633 | ARMCPRegInfo id_v8_midr_cp_reginfo[] = { |
00a29f3d PM |
7634 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, |
7635 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, | |
731de9e6 EI |
7636 | .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, |
7637 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), | |
7638 | .readfn = midr_read }, | |
ac00c79f SF |
7639 | /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ |
7640 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
7641 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
7642 | .access = PL1_R, .resetvalue = cpu->midr }, | |
7643 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
7644 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, | |
7645 | .access = PL1_R, .resetvalue = cpu->midr }, | |
00a29f3d PM |
7646 | { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, |
7647 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, | |
93fbc983 MZ |
7648 | .access = PL1_R, |
7649 | .accessfn = access_aa64_tid1, | |
7650 | .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, | |
00a29f3d PM |
7651 | REGINFO_SENTINEL |
7652 | }; | |
7653 | ARMCPRegInfo id_cp_reginfo[] = { | |
7654 | /* These are common to v8 and pre-v8 */ | |
7655 | { .name = "CTR", | |
7656 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, | |
630fcd4d MZ |
7657 | .access = PL1_R, .accessfn = ctr_el0_access, |
7658 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
00a29f3d PM |
7659 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, |
7660 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, | |
7661 | .access = PL0_R, .accessfn = ctr_el0_access, | |
7662 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
7663 | /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ | |
7664 | { .name = "TCMTR", | |
7665 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, | |
93fbc983 MZ |
7666 | .access = PL1_R, |
7667 | .accessfn = access_aa32_tid1, | |
7668 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
00a29f3d PM |
7669 | REGINFO_SENTINEL |
7670 | }; | |
8085ce63 PC |
7671 | /* TLBTR is specific to VMSA */ |
7672 | ARMCPRegInfo id_tlbtr_reginfo = { | |
7673 | .name = "TLBTR", | |
7674 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, | |
93fbc983 MZ |
7675 | .access = PL1_R, |
7676 | .accessfn = access_aa32_tid1, | |
7677 | .type = ARM_CP_CONST, .resetvalue = 0, | |
8085ce63 | 7678 | }; |
3281af81 PC |
7679 | /* MPUIR is specific to PMSA V6+ */ |
7680 | ARMCPRegInfo id_mpuir_reginfo = { | |
7681 | .name = "MPUIR", | |
7682 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
7683 | .access = PL1_R, .type = ARM_CP_CONST, | |
7684 | .resetvalue = cpu->pmsav7_dregion << 8 | |
7685 | }; | |
7884849c PM |
7686 | ARMCPRegInfo crn0_wi_reginfo = { |
7687 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, | |
7688 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | |
7689 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | |
7690 | }; | |
6c5c0fec AB |
7691 | #ifdef CONFIG_USER_ONLY |
7692 | ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = { | |
7693 | { .name = "MIDR_EL1", | |
7694 | .exported_bits = 0x00000000ffffffff }, | |
7695 | { .name = "REVIDR_EL1" }, | |
7696 | REGUSERINFO_SENTINEL | |
7697 | }; | |
7698 | modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo); | |
7699 | #endif | |
7884849c PM |
7700 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || |
7701 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | |
7702 | ARMCPRegInfo *r; | |
7703 | /* Register the blanket "writes ignored" value first to cover the | |
a703eda1 PC |
7704 | * whole space. Then update the specific ID registers to allow write |
7705 | * access, so that they ignore writes rather than causing them to | |
7706 | * UNDEF. | |
7884849c PM |
7707 | */ |
7708 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | |
00a29f3d PM |
7709 | for (r = id_pre_v8_midr_cp_reginfo; |
7710 | r->type != ARM_CP_SENTINEL; r++) { | |
7711 | r->access = PL1_RW; | |
7712 | } | |
7884849c PM |
7713 | for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { |
7714 | r->access = PL1_RW; | |
7884849c | 7715 | } |
10006112 | 7716 | id_mpuir_reginfo.access = PL1_RW; |
3281af81 | 7717 | id_tlbtr_reginfo.access = PL1_RW; |
7884849c | 7718 | } |
00a29f3d PM |
7719 | if (arm_feature(env, ARM_FEATURE_V8)) { |
7720 | define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); | |
7721 | } else { | |
7722 | define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); | |
7723 | } | |
a703eda1 | 7724 | define_arm_cp_regs(cpu, id_cp_reginfo); |
452a0955 | 7725 | if (!arm_feature(env, ARM_FEATURE_PMSA)) { |
8085ce63 | 7726 | define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); |
3281af81 PC |
7727 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
7728 | define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); | |
8085ce63 | 7729 | } |
7884849c PM |
7730 | } |
7731 | ||
97ce8d61 | 7732 | if (arm_feature(env, ARM_FEATURE_MPIDR)) { |
52264166 AB |
7733 | ARMCPRegInfo mpidr_cp_reginfo[] = { |
7734 | { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
7735 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | |
7736 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, | |
7737 | REGINFO_SENTINEL | |
7738 | }; | |
7739 | #ifdef CONFIG_USER_ONLY | |
7740 | ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = { | |
7741 | { .name = "MPIDR_EL1", | |
7742 | .fixed_bits = 0x0000000080000000 }, | |
7743 | REGUSERINFO_SENTINEL | |
7744 | }; | |
7745 | modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); | |
7746 | #endif | |
97ce8d61 PC |
7747 | define_arm_cp_regs(cpu, mpidr_cp_reginfo); |
7748 | } | |
7749 | ||
2771db27 | 7750 | if (arm_feature(env, ARM_FEATURE_AUXCR)) { |
834a6c69 PM |
7751 | ARMCPRegInfo auxcr_reginfo[] = { |
7752 | { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, | |
7753 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, | |
99602377 RH |
7754 | .access = PL1_RW, .accessfn = access_tacr, |
7755 | .type = ARM_CP_CONST, .resetvalue = cpu->reset_auxcr }, | |
834a6c69 PM |
7756 | { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, |
7757 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, | |
7758 | .access = PL2_RW, .type = ARM_CP_CONST, | |
7759 | .resetvalue = 0 }, | |
7760 | { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, | |
7761 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, | |
7762 | .access = PL3_RW, .type = ARM_CP_CONST, | |
7763 | .resetvalue = 0 }, | |
7764 | REGINFO_SENTINEL | |
2771db27 | 7765 | }; |
834a6c69 | 7766 | define_arm_cp_regs(cpu, auxcr_reginfo); |
f6287c24 PM |
7767 | if (cpu_isar_feature(aa32_ac2, cpu)) { |
7768 | define_arm_cp_regs(cpu, actlr2_hactlr2_reginfo); | |
0e0456ab | 7769 | } |
2771db27 PM |
7770 | } |
7771 | ||
d8ba780b | 7772 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
d56974af LM |
7773 | /* |
7774 | * CBAR is IMPDEF, but common on Arm Cortex-A implementations. | |
7775 | * There are two flavours: | |
7776 | * (1) older 32-bit only cores have a simple 32-bit CBAR | |
7777 | * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a | |
7778 | * 32-bit register visible to AArch32 at a different encoding | |
7779 | * to the "flavour 1" register and with the bits rearranged to | |
7780 | * be able to squash a 64-bit address into the 32-bit view. | |
7781 | * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but | |
7782 | * in future if we support AArch32-only configs of some of the | |
7783 | * AArch64 cores we might need to add a specific feature flag | |
7784 | * to indicate cores with "flavour 2" CBAR. | |
7785 | */ | |
f318cec6 PM |
7786 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
7787 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | |
7788 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | |
7789 | | extract64(cpu->reset_cbar, 32, 12); | |
7790 | ARMCPRegInfo cbar_reginfo[] = { | |
7791 | { .name = "CBAR", | |
7792 | .type = ARM_CP_CONST, | |
d56974af LM |
7793 | .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0, |
7794 | .access = PL1_R, .resetvalue = cbar32 }, | |
f318cec6 PM |
7795 | { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, |
7796 | .type = ARM_CP_CONST, | |
7797 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | |
d56974af | 7798 | .access = PL1_R, .resetvalue = cpu->reset_cbar }, |
f318cec6 PM |
7799 | REGINFO_SENTINEL |
7800 | }; | |
7801 | /* We don't implement a r/w 64 bit CBAR currently */ | |
7802 | assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); | |
7803 | define_arm_cp_regs(cpu, cbar_reginfo); | |
7804 | } else { | |
7805 | ARMCPRegInfo cbar = { | |
7806 | .name = "CBAR", | |
7807 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
7808 | .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, | |
7809 | .fieldoffset = offsetof(CPUARMState, | |
7810 | cp15.c15_config_base_address) | |
7811 | }; | |
7812 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | |
7813 | cbar.access = PL1_R; | |
7814 | cbar.fieldoffset = 0; | |
7815 | cbar.type = ARM_CP_CONST; | |
7816 | } | |
7817 | define_one_arm_cp_reg(cpu, &cbar); | |
7818 | } | |
d8ba780b PC |
7819 | } |
7820 | ||
91db4642 CLG |
7821 | if (arm_feature(env, ARM_FEATURE_VBAR)) { |
7822 | ARMCPRegInfo vbar_cp_reginfo[] = { | |
7823 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, | |
7824 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7825 | .access = PL1_RW, .writefn = vbar_write, | |
7826 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), | |
7827 | offsetof(CPUARMState, cp15.vbar_ns) }, | |
7828 | .resetvalue = 0 }, | |
7829 | REGINFO_SENTINEL | |
7830 | }; | |
7831 | define_arm_cp_regs(cpu, vbar_cp_reginfo); | |
7832 | } | |
7833 | ||
2771db27 PM |
7834 | /* Generic registers whose values depend on the implementation */ |
7835 | { | |
7836 | ARMCPRegInfo sctlr = { | |
5ebafdf3 | 7837 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, |
137feaa9 | 7838 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, |
84929218 | 7839 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
137feaa9 FA |
7840 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), |
7841 | offsetof(CPUARMState, cp15.sctlr_ns) }, | |
d4e6df63 PM |
7842 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, |
7843 | .raw_writefn = raw_write, | |
2771db27 PM |
7844 | }; |
7845 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
7846 | /* Normally we would always end the TB on an SCTLR write, but Linux | |
7847 | * arch/arm/mach-pxa/sleep.S expects two instructions following | |
7848 | * an MMU enable to execute from cache. Imitate this behaviour. | |
7849 | */ | |
7850 | sctlr.type |= ARM_CP_SUPPRESS_TB_END; | |
7851 | } | |
7852 | define_one_arm_cp_reg(cpu, &sctlr); | |
7853 | } | |
5be5e8ed | 7854 | |
2d7137c1 | 7855 | if (cpu_isar_feature(aa64_lor, cpu)) { |
2d7137c1 RH |
7856 | define_arm_cp_regs(cpu, lor_reginfo); |
7857 | } | |
220f508f RH |
7858 | if (cpu_isar_feature(aa64_pan, cpu)) { |
7859 | define_one_arm_cp_reg(cpu, &pan_reginfo); | |
7860 | } | |
04b07d29 RH |
7861 | #ifndef CONFIG_USER_ONLY |
7862 | if (cpu_isar_feature(aa64_ats1e1, cpu)) { | |
7863 | define_arm_cp_regs(cpu, ats1e1_reginfo); | |
7864 | } | |
7865 | if (cpu_isar_feature(aa32_ats1e1, cpu)) { | |
7866 | define_arm_cp_regs(cpu, ats1cp_reginfo); | |
7867 | } | |
7868 | #endif | |
9eeb7a1c RH |
7869 | if (cpu_isar_feature(aa64_uao, cpu)) { |
7870 | define_one_arm_cp_reg(cpu, &uao_reginfo); | |
7871 | } | |
2d7137c1 | 7872 | |
e2a1a461 RH |
7873 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { |
7874 | define_arm_cp_regs(cpu, vhe_reginfo); | |
7875 | } | |
7876 | ||
cd208a1c | 7877 | if (cpu_isar_feature(aa64_sve, cpu)) { |
5be5e8ed RH |
7878 | define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); |
7879 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
7880 | define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); | |
7881 | } else { | |
7882 | define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo); | |
7883 | } | |
7884 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
7885 | define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); | |
7886 | } | |
7887 | } | |
967aa94f RH |
7888 | |
7889 | #ifdef TARGET_AARCH64 | |
7890 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
7891 | define_arm_cp_regs(cpu, pauth_reginfo); | |
7892 | } | |
de390645 RH |
7893 | if (cpu_isar_feature(aa64_rndr, cpu)) { |
7894 | define_arm_cp_regs(cpu, rndr_reginfo); | |
7895 | } | |
0d57b499 BM |
7896 | #ifndef CONFIG_USER_ONLY |
7897 | /* Data Cache clean instructions up to PoP */ | |
7898 | if (cpu_isar_feature(aa64_dcpop, cpu)) { | |
7899 | define_one_arm_cp_reg(cpu, dcpop_reg); | |
7900 | ||
7901 | if (cpu_isar_feature(aa64_dcpodp, cpu)) { | |
7902 | define_one_arm_cp_reg(cpu, dcpodp_reg); | |
7903 | } | |
7904 | } | |
7905 | #endif /*CONFIG_USER_ONLY*/ | |
967aa94f | 7906 | #endif |
cb570bd3 | 7907 | |
22e57073 | 7908 | if (cpu_isar_feature(any_predinv, cpu)) { |
cb570bd3 RH |
7909 | define_arm_cp_regs(cpu, predinv_reginfo); |
7910 | } | |
e2cce18f | 7911 | |
957e6155 PM |
7912 | if (cpu_isar_feature(any_ccidx, cpu)) { |
7913 | define_arm_cp_regs(cpu, ccsidr2_reginfo); | |
7914 | } | |
7915 | ||
e2cce18f RH |
7916 | #ifndef CONFIG_USER_ONLY |
7917 | /* | |
7918 | * Register redirections and aliases must be done last, | |
7919 | * after the registers from the other extensions have been defined. | |
7920 | */ | |
7921 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { | |
7922 | define_arm_vh_e2h_redirects_aliases(cpu); | |
7923 | } | |
7924 | #endif | |
2ceb98c0 PM |
7925 | } |
7926 | ||
14969266 AF |
7927 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) |
7928 | { | |
22169d41 | 7929 | CPUState *cs = CPU(cpu); |
14969266 AF |
7930 | CPUARMState *env = &cpu->env; |
7931 | ||
6a669427 PM |
7932 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
7933 | gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, | |
7934 | aarch64_fpu_gdb_set_reg, | |
7935 | 34, "aarch64-fpu.xml", 0); | |
7936 | } else if (arm_feature(env, ARM_FEATURE_NEON)) { | |
22169d41 | 7937 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 | 7938 | 51, "arm-neon.xml", 0); |
a6627f5f | 7939 | } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { |
22169d41 | 7940 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 | 7941 | 35, "arm-vfp3.xml", 0); |
7fbc6a40 | 7942 | } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { |
22169d41 | 7943 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
7944 | 19, "arm-vfp.xml", 0); |
7945 | } | |
200bf5b7 AB |
7946 | gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, |
7947 | arm_gen_dynamic_xml(cs), | |
7948 | "system-registers.xml", 0); | |
40f137e1 PB |
7949 | } |
7950 | ||
777dc784 PM |
7951 | /* Sort alphabetically by type name, except for "any". */ |
7952 | static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) | |
5adb4839 | 7953 | { |
777dc784 PM |
7954 | ObjectClass *class_a = (ObjectClass *)a; |
7955 | ObjectClass *class_b = (ObjectClass *)b; | |
7956 | const char *name_a, *name_b; | |
5adb4839 | 7957 | |
777dc784 PM |
7958 | name_a = object_class_get_name(class_a); |
7959 | name_b = object_class_get_name(class_b); | |
51492fd1 | 7960 | if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 | 7961 | return 1; |
51492fd1 | 7962 | } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 PM |
7963 | return -1; |
7964 | } else { | |
7965 | return strcmp(name_a, name_b); | |
5adb4839 PB |
7966 | } |
7967 | } | |
7968 | ||
777dc784 | 7969 | static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
40f137e1 | 7970 | { |
777dc784 | 7971 | ObjectClass *oc = data; |
51492fd1 AF |
7972 | const char *typename; |
7973 | char *name; | |
3371d272 | 7974 | |
51492fd1 AF |
7975 | typename = object_class_get_name(oc); |
7976 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
0442428a | 7977 | qemu_printf(" %s\n", name); |
51492fd1 | 7978 | g_free(name); |
777dc784 PM |
7979 | } |
7980 | ||
0442428a | 7981 | void arm_cpu_list(void) |
777dc784 | 7982 | { |
777dc784 PM |
7983 | GSList *list; |
7984 | ||
7985 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
7986 | list = g_slist_sort(list, arm_cpu_list_compare); | |
0442428a MA |
7987 | qemu_printf("Available CPUs:\n"); |
7988 | g_slist_foreach(list, arm_cpu_list_entry, NULL); | |
777dc784 | 7989 | g_slist_free(list); |
40f137e1 PB |
7990 | } |
7991 | ||
78027bb6 CR |
7992 | static void arm_cpu_add_definition(gpointer data, gpointer user_data) |
7993 | { | |
7994 | ObjectClass *oc = data; | |
7995 | CpuDefinitionInfoList **cpu_list = user_data; | |
7996 | CpuDefinitionInfoList *entry; | |
7997 | CpuDefinitionInfo *info; | |
7998 | const char *typename; | |
7999 | ||
8000 | typename = object_class_get_name(oc); | |
8001 | info = g_malloc0(sizeof(*info)); | |
8002 | info->name = g_strndup(typename, | |
8003 | strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
8ed877b7 | 8004 | info->q_typename = g_strdup(typename); |
78027bb6 CR |
8005 | |
8006 | entry = g_malloc0(sizeof(*entry)); | |
8007 | entry->value = info; | |
8008 | entry->next = *cpu_list; | |
8009 | *cpu_list = entry; | |
8010 | } | |
8011 | ||
25a9d6ca | 8012 | CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) |
78027bb6 CR |
8013 | { |
8014 | CpuDefinitionInfoList *cpu_list = NULL; | |
8015 | GSList *list; | |
8016 | ||
8017 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
8018 | g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); | |
8019 | g_slist_free(list); | |
8020 | ||
8021 | return cpu_list; | |
8022 | } | |
8023 | ||
6e6efd61 | 8024 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
51a79b03 | 8025 | void *opaque, int state, int secstate, |
9c513e78 AB |
8026 | int crm, int opc1, int opc2, |
8027 | const char *name) | |
6e6efd61 PM |
8028 | { |
8029 | /* Private utility function for define_one_arm_cp_reg_with_opaque(): | |
8030 | * add a single reginfo struct to the hash table. | |
8031 | */ | |
8032 | uint32_t *key = g_new(uint32_t, 1); | |
8033 | ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); | |
8034 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | |
3f3c82a5 FA |
8035 | int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; |
8036 | ||
9c513e78 | 8037 | r2->name = g_strdup(name); |
3f3c82a5 FA |
8038 | /* Reset the secure state to the specific incoming state. This is |
8039 | * necessary as the register may have been defined with both states. | |
8040 | */ | |
8041 | r2->secure = secstate; | |
8042 | ||
8043 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
8044 | /* Register is banked (using both entries in array). | |
8045 | * Overwriting fieldoffset as the array is only used to define | |
8046 | * banked registers but later only fieldoffset is used. | |
f5a0a5a5 | 8047 | */ |
3f3c82a5 FA |
8048 | r2->fieldoffset = r->bank_fieldoffsets[ns]; |
8049 | } | |
8050 | ||
8051 | if (state == ARM_CP_STATE_AA32) { | |
8052 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
8053 | /* If the register is banked then we don't need to migrate or | |
8054 | * reset the 32-bit instance in certain cases: | |
8055 | * | |
8056 | * 1) If the register has both 32-bit and 64-bit instances then we | |
8057 | * can count on the 64-bit instance taking care of the | |
8058 | * non-secure bank. | |
8059 | * 2) If ARMv8 is enabled then we can count on a 64-bit version | |
8060 | * taking care of the secure bank. This requires that separate | |
8061 | * 32 and 64-bit definitions are provided. | |
8062 | */ | |
8063 | if ((r->state == ARM_CP_STATE_BOTH && ns) || | |
8064 | (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { | |
7a0e58fa | 8065 | r2->type |= ARM_CP_ALIAS; |
3f3c82a5 FA |
8066 | } |
8067 | } else if ((secstate != r->secure) && !ns) { | |
8068 | /* The register is not banked so we only want to allow migration of | |
8069 | * the non-secure instance. | |
8070 | */ | |
7a0e58fa | 8071 | r2->type |= ARM_CP_ALIAS; |
58a1d8ce | 8072 | } |
3f3c82a5 FA |
8073 | |
8074 | if (r->state == ARM_CP_STATE_BOTH) { | |
8075 | /* We assume it is a cp15 register if the .cp field is left unset. | |
8076 | */ | |
8077 | if (r2->cp == 0) { | |
8078 | r2->cp = 15; | |
8079 | } | |
8080 | ||
f5a0a5a5 | 8081 | #ifdef HOST_WORDS_BIGENDIAN |
3f3c82a5 FA |
8082 | if (r2->fieldoffset) { |
8083 | r2->fieldoffset += sizeof(uint32_t); | |
8084 | } | |
f5a0a5a5 | 8085 | #endif |
3f3c82a5 | 8086 | } |
f5a0a5a5 PM |
8087 | } |
8088 | if (state == ARM_CP_STATE_AA64) { | |
8089 | /* To allow abbreviation of ARMCPRegInfo | |
8090 | * definitions, we treat cp == 0 as equivalent to | |
8091 | * the value for "standard guest-visible sysreg". | |
58a1d8ce PM |
8092 | * STATE_BOTH definitions are also always "standard |
8093 | * sysreg" in their AArch64 view (the .cp value may | |
8094 | * be non-zero for the benefit of the AArch32 view). | |
f5a0a5a5 | 8095 | */ |
58a1d8ce | 8096 | if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { |
f5a0a5a5 PM |
8097 | r2->cp = CP_REG_ARM64_SYSREG_CP; |
8098 | } | |
8099 | *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | |
8100 | r2->opc0, opc1, opc2); | |
8101 | } else { | |
51a79b03 | 8102 | *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); |
f5a0a5a5 | 8103 | } |
6e6efd61 PM |
8104 | if (opaque) { |
8105 | r2->opaque = opaque; | |
8106 | } | |
67ed771d PM |
8107 | /* reginfo passed to helpers is correct for the actual access, |
8108 | * and is never ARM_CP_STATE_BOTH: | |
8109 | */ | |
8110 | r2->state = state; | |
6e6efd61 PM |
8111 | /* Make sure reginfo passed to helpers for wildcarded regs |
8112 | * has the correct crm/opc1/opc2 for this reg, not CP_ANY: | |
8113 | */ | |
8114 | r2->crm = crm; | |
8115 | r2->opc1 = opc1; | |
8116 | r2->opc2 = opc2; | |
8117 | /* By convention, for wildcarded registers only the first | |
8118 | * entry is used for migration; the others are marked as | |
7a0e58fa | 8119 | * ALIAS so we don't try to transfer the register |
6e6efd61 | 8120 | * multiple times. Special registers (ie NOP/WFI) are |
7a0e58fa | 8121 | * never migratable and not even raw-accessible. |
6e6efd61 | 8122 | */ |
7a0e58fa PM |
8123 | if ((r->type & ARM_CP_SPECIAL)) { |
8124 | r2->type |= ARM_CP_NO_RAW; | |
8125 | } | |
8126 | if (((r->crm == CP_ANY) && crm != 0) || | |
6e6efd61 PM |
8127 | ((r->opc1 == CP_ANY) && opc1 != 0) || |
8128 | ((r->opc2 == CP_ANY) && opc2 != 0)) { | |
1f163787 | 8129 | r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB; |
6e6efd61 PM |
8130 | } |
8131 | ||
375421cc PM |
8132 | /* Check that raw accesses are either forbidden or handled. Note that |
8133 | * we can't assert this earlier because the setup of fieldoffset for | |
8134 | * banked registers has to be done first. | |
8135 | */ | |
8136 | if (!(r2->type & ARM_CP_NO_RAW)) { | |
8137 | assert(!raw_accessors_invalid(r2)); | |
8138 | } | |
8139 | ||
6e6efd61 PM |
8140 | /* Overriding of an existing definition must be explicitly |
8141 | * requested. | |
8142 | */ | |
8143 | if (!(r->type & ARM_CP_OVERRIDE)) { | |
8144 | ARMCPRegInfo *oldreg; | |
8145 | oldreg = g_hash_table_lookup(cpu->cp_regs, key); | |
8146 | if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { | |
8147 | fprintf(stderr, "Register redefined: cp=%d %d bit " | |
8148 | "crn=%d crm=%d opc1=%d opc2=%d, " | |
8149 | "was %s, now %s\n", r2->cp, 32 + 32 * is64, | |
8150 | r2->crn, r2->crm, r2->opc1, r2->opc2, | |
8151 | oldreg->name, r2->name); | |
8152 | g_assert_not_reached(); | |
8153 | } | |
8154 | } | |
8155 | g_hash_table_insert(cpu->cp_regs, key, r2); | |
8156 | } | |
8157 | ||
8158 | ||
4b6a83fb PM |
8159 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
8160 | const ARMCPRegInfo *r, void *opaque) | |
8161 | { | |
8162 | /* Define implementations of coprocessor registers. | |
8163 | * We store these in a hashtable because typically | |
8164 | * there are less than 150 registers in a space which | |
8165 | * is 16*16*16*8*8 = 262144 in size. | |
8166 | * Wildcarding is supported for the crm, opc1 and opc2 fields. | |
8167 | * If a register is defined twice then the second definition is | |
8168 | * used, so this can be used to define some generic registers and | |
8169 | * then override them with implementation specific variations. | |
8170 | * At least one of the original and the second definition should | |
8171 | * include ARM_CP_OVERRIDE in its type bits -- this is just a guard | |
8172 | * against accidental use. | |
f5a0a5a5 PM |
8173 | * |
8174 | * The state field defines whether the register is to be | |
8175 | * visible in the AArch32 or AArch64 execution state. If the | |
8176 | * state is set to ARM_CP_STATE_BOTH then we synthesise a | |
8177 | * reginfo structure for the AArch32 view, which sees the lower | |
8178 | * 32 bits of the 64 bit register. | |
8179 | * | |
8180 | * Only registers visible in AArch64 may set r->opc0; opc0 cannot | |
8181 | * be wildcarded. AArch64 registers are always considered to be 64 | |
8182 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | |
8183 | * the register, if any. | |
4b6a83fb | 8184 | */ |
f5a0a5a5 | 8185 | int crm, opc1, opc2, state; |
4b6a83fb PM |
8186 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
8187 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | |
8188 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | |
8189 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | |
8190 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | |
8191 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | |
8192 | /* 64 bit registers have only CRm and Opc1 fields */ | |
8193 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | |
f5a0a5a5 PM |
8194 | /* op0 only exists in the AArch64 encodings */ |
8195 | assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); | |
8196 | /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ | |
8197 | assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); | |
8198 | /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 | |
8199 | * encodes a minimum access level for the register. We roll this | |
8200 | * runtime check into our general permission check code, so check | |
8201 | * here that the reginfo's specified permissions are strict enough | |
8202 | * to encompass the generic architectural permission check. | |
8203 | */ | |
8204 | if (r->state != ARM_CP_STATE_AA32) { | |
8205 | int mask = 0; | |
8206 | switch (r->opc1) { | |
b5bd7440 AB |
8207 | case 0: |
8208 | /* min_EL EL1, but some accessible to EL0 via kernel ABI */ | |
8209 | mask = PL0U_R | PL1_RW; | |
8210 | break; | |
8211 | case 1: case 2: | |
f5a0a5a5 PM |
8212 | /* min_EL EL1 */ |
8213 | mask = PL1_RW; | |
8214 | break; | |
8215 | case 3: | |
8216 | /* min_EL EL0 */ | |
8217 | mask = PL0_RW; | |
8218 | break; | |
8219 | case 4: | |
b4ecf60f | 8220 | case 5: |
f5a0a5a5 PM |
8221 | /* min_EL EL2 */ |
8222 | mask = PL2_RW; | |
8223 | break; | |
f5a0a5a5 PM |
8224 | case 6: |
8225 | /* min_EL EL3 */ | |
8226 | mask = PL3_RW; | |
8227 | break; | |
8228 | case 7: | |
8229 | /* min_EL EL1, secure mode only (we don't check the latter) */ | |
8230 | mask = PL1_RW; | |
8231 | break; | |
8232 | default: | |
8233 | /* broken reginfo with out-of-range opc1 */ | |
8234 | assert(false); | |
8235 | break; | |
8236 | } | |
8237 | /* assert our permissions are not too lax (stricter is fine) */ | |
8238 | assert((r->access & ~mask) == 0); | |
8239 | } | |
8240 | ||
4b6a83fb PM |
8241 | /* Check that the register definition has enough info to handle |
8242 | * reads and writes if they are permitted. | |
8243 | */ | |
8244 | if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { | |
8245 | if (r->access & PL3_R) { | |
3f3c82a5 FA |
8246 | assert((r->fieldoffset || |
8247 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
8248 | r->readfn); | |
4b6a83fb PM |
8249 | } |
8250 | if (r->access & PL3_W) { | |
3f3c82a5 FA |
8251 | assert((r->fieldoffset || |
8252 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
8253 | r->writefn); | |
4b6a83fb PM |
8254 | } |
8255 | } | |
8256 | /* Bad type field probably means missing sentinel at end of reg list */ | |
8257 | assert(cptype_valid(r->type)); | |
8258 | for (crm = crmmin; crm <= crmmax; crm++) { | |
8259 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | |
8260 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | |
f5a0a5a5 PM |
8261 | for (state = ARM_CP_STATE_AA32; |
8262 | state <= ARM_CP_STATE_AA64; state++) { | |
8263 | if (r->state != state && r->state != ARM_CP_STATE_BOTH) { | |
8264 | continue; | |
8265 | } | |
3f3c82a5 FA |
8266 | if (state == ARM_CP_STATE_AA32) { |
8267 | /* Under AArch32 CP registers can be common | |
8268 | * (same for secure and non-secure world) or banked. | |
8269 | */ | |
9c513e78 AB |
8270 | char *name; |
8271 | ||
3f3c82a5 FA |
8272 | switch (r->secure) { |
8273 | case ARM_CP_SECSTATE_S: | |
8274 | case ARM_CP_SECSTATE_NS: | |
8275 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
9c513e78 AB |
8276 | r->secure, crm, opc1, opc2, |
8277 | r->name); | |
3f3c82a5 FA |
8278 | break; |
8279 | default: | |
9c513e78 | 8280 | name = g_strdup_printf("%s_S", r->name); |
3f3c82a5 FA |
8281 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
8282 | ARM_CP_SECSTATE_S, | |
9c513e78 AB |
8283 | crm, opc1, opc2, name); |
8284 | g_free(name); | |
3f3c82a5 FA |
8285 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
8286 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 8287 | crm, opc1, opc2, r->name); |
3f3c82a5 FA |
8288 | break; |
8289 | } | |
8290 | } else { | |
8291 | /* AArch64 registers get mapped to non-secure instance | |
8292 | * of AArch32 */ | |
8293 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
8294 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 8295 | crm, opc1, opc2, r->name); |
3f3c82a5 | 8296 | } |
f5a0a5a5 | 8297 | } |
4b6a83fb PM |
8298 | } |
8299 | } | |
8300 | } | |
8301 | } | |
8302 | ||
8303 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
8304 | const ARMCPRegInfo *regs, void *opaque) | |
8305 | { | |
8306 | /* Define a whole list of registers */ | |
8307 | const ARMCPRegInfo *r; | |
8308 | for (r = regs; r->type != ARM_CP_SENTINEL; r++) { | |
8309 | define_one_arm_cp_reg_with_opaque(cpu, r, opaque); | |
8310 | } | |
8311 | } | |
8312 | ||
6c5c0fec AB |
8313 | /* |
8314 | * Modify ARMCPRegInfo for access from userspace. | |
8315 | * | |
8316 | * This is a data driven modification directed by | |
8317 | * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as | |
8318 | * user-space cannot alter any values and dynamic values pertaining to | |
8319 | * execution state are hidden from user space view anyway. | |
8320 | */ | |
8321 | void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods) | |
8322 | { | |
8323 | const ARMCPRegUserSpaceInfo *m; | |
8324 | ARMCPRegInfo *r; | |
8325 | ||
8326 | for (m = mods; m->name; m++) { | |
d040242e AB |
8327 | GPatternSpec *pat = NULL; |
8328 | if (m->is_glob) { | |
8329 | pat = g_pattern_spec_new(m->name); | |
8330 | } | |
6c5c0fec | 8331 | for (r = regs; r->type != ARM_CP_SENTINEL; r++) { |
d040242e AB |
8332 | if (pat && g_pattern_match_string(pat, r->name)) { |
8333 | r->type = ARM_CP_CONST; | |
8334 | r->access = PL0U_R; | |
8335 | r->resetvalue = 0; | |
8336 | /* continue */ | |
8337 | } else if (strcmp(r->name, m->name) == 0) { | |
6c5c0fec AB |
8338 | r->type = ARM_CP_CONST; |
8339 | r->access = PL0U_R; | |
8340 | r->resetvalue &= m->exported_bits; | |
8341 | r->resetvalue |= m->fixed_bits; | |
8342 | break; | |
8343 | } | |
8344 | } | |
d040242e AB |
8345 | if (pat) { |
8346 | g_pattern_spec_free(pat); | |
8347 | } | |
6c5c0fec AB |
8348 | } |
8349 | } | |
8350 | ||
60322b39 | 8351 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) |
4b6a83fb | 8352 | { |
60322b39 | 8353 | return g_hash_table_lookup(cpregs, &encoded_cp); |
4b6a83fb PM |
8354 | } |
8355 | ||
c4241c7d PM |
8356 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
8357 | uint64_t value) | |
4b6a83fb PM |
8358 | { |
8359 | /* Helper coprocessor write function for write-ignore registers */ | |
4b6a83fb PM |
8360 | } |
8361 | ||
c4241c7d | 8362 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) |
4b6a83fb PM |
8363 | { |
8364 | /* Helper coprocessor write function for read-as-zero registers */ | |
4b6a83fb PM |
8365 | return 0; |
8366 | } | |
8367 | ||
f5a0a5a5 PM |
8368 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) |
8369 | { | |
8370 | /* Helper coprocessor reset function for do-nothing-on-reset registers */ | |
8371 | } | |
8372 | ||
af393ffc | 8373 | static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) |
37064a8b PM |
8374 | { |
8375 | /* Return true if it is not valid for us to switch to | |
8376 | * this CPU mode (ie all the UNPREDICTABLE cases in | |
8377 | * the ARM ARM CPSRWriteByInstr pseudocode). | |
8378 | */ | |
af393ffc PM |
8379 | |
8380 | /* Changes to or from Hyp via MSR and CPS are illegal. */ | |
8381 | if (write_type == CPSRWriteByInstr && | |
8382 | ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || | |
8383 | mode == ARM_CPU_MODE_HYP)) { | |
8384 | return 1; | |
8385 | } | |
8386 | ||
37064a8b PM |
8387 | switch (mode) { |
8388 | case ARM_CPU_MODE_USR: | |
10eacda7 | 8389 | return 0; |
37064a8b PM |
8390 | case ARM_CPU_MODE_SYS: |
8391 | case ARM_CPU_MODE_SVC: | |
8392 | case ARM_CPU_MODE_ABT: | |
8393 | case ARM_CPU_MODE_UND: | |
8394 | case ARM_CPU_MODE_IRQ: | |
8395 | case ARM_CPU_MODE_FIQ: | |
52ff951b PM |
8396 | /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 |
8397 | * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) | |
8398 | */ | |
10eacda7 PM |
8399 | /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR |
8400 | * and CPS are treated as illegal mode changes. | |
8401 | */ | |
8402 | if (write_type == CPSRWriteByInstr && | |
10eacda7 | 8403 | (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && |
7c208e0f | 8404 | (arm_hcr_el2_eff(env) & HCR_TGE)) { |
10eacda7 PM |
8405 | return 1; |
8406 | } | |
37064a8b | 8407 | return 0; |
e6c8fc07 PM |
8408 | case ARM_CPU_MODE_HYP: |
8409 | return !arm_feature(env, ARM_FEATURE_EL2) | |
2d2a4549 | 8410 | || arm_current_el(env) < 2 || arm_is_secure_below_el3(env); |
027fc527 | 8411 | case ARM_CPU_MODE_MON: |
58ae2d1f | 8412 | return arm_current_el(env) < 3; |
37064a8b PM |
8413 | default: |
8414 | return 1; | |
8415 | } | |
8416 | } | |
8417 | ||
2f4a40e5 AZ |
8418 | uint32_t cpsr_read(CPUARMState *env) |
8419 | { | |
8420 | int ZF; | |
6fbe23d5 PB |
8421 | ZF = (env->ZF == 0); |
8422 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
8423 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
8424 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
8425 | | ((env->condexec_bits & 0xfc) << 8) | |
af519934 | 8426 | | (env->GE << 16) | (env->daif & CPSR_AIF); |
2f4a40e5 AZ |
8427 | } |
8428 | ||
50866ba5 PM |
8429 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, |
8430 | CPSRWriteType write_type) | |
2f4a40e5 | 8431 | { |
6e8801f9 FA |
8432 | uint32_t changed_daif; |
8433 | ||
2f4a40e5 | 8434 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
8435 | env->ZF = (~val) & CPSR_Z; |
8436 | env->NF = val; | |
2f4a40e5 AZ |
8437 | env->CF = (val >> 29) & 1; |
8438 | env->VF = (val << 3) & 0x80000000; | |
8439 | } | |
8440 | if (mask & CPSR_Q) | |
8441 | env->QF = ((val & CPSR_Q) != 0); | |
8442 | if (mask & CPSR_T) | |
8443 | env->thumb = ((val & CPSR_T) != 0); | |
8444 | if (mask & CPSR_IT_0_1) { | |
8445 | env->condexec_bits &= ~3; | |
8446 | env->condexec_bits |= (val >> 25) & 3; | |
8447 | } | |
8448 | if (mask & CPSR_IT_2_7) { | |
8449 | env->condexec_bits &= 3; | |
8450 | env->condexec_bits |= (val >> 8) & 0xfc; | |
8451 | } | |
8452 | if (mask & CPSR_GE) { | |
8453 | env->GE = (val >> 16) & 0xf; | |
8454 | } | |
8455 | ||
6e8801f9 FA |
8456 | /* In a V7 implementation that includes the security extensions but does |
8457 | * not include Virtualization Extensions the SCR.FW and SCR.AW bits control | |
8458 | * whether non-secure software is allowed to change the CPSR_F and CPSR_A | |
8459 | * bits respectively. | |
8460 | * | |
8461 | * In a V8 implementation, it is permitted for privileged software to | |
8462 | * change the CPSR A/F bits regardless of the SCR.AW/FW bits. | |
8463 | */ | |
f8c88bbc | 8464 | if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && |
6e8801f9 FA |
8465 | arm_feature(env, ARM_FEATURE_EL3) && |
8466 | !arm_feature(env, ARM_FEATURE_EL2) && | |
8467 | !arm_is_secure(env)) { | |
8468 | ||
8469 | changed_daif = (env->daif ^ val) & mask; | |
8470 | ||
8471 | if (changed_daif & CPSR_A) { | |
8472 | /* Check to see if we are allowed to change the masking of async | |
8473 | * abort exceptions from a non-secure state. | |
8474 | */ | |
8475 | if (!(env->cp15.scr_el3 & SCR_AW)) { | |
8476 | qemu_log_mask(LOG_GUEST_ERROR, | |
8477 | "Ignoring attempt to switch CPSR_A flag from " | |
8478 | "non-secure world with SCR.AW bit clear\n"); | |
8479 | mask &= ~CPSR_A; | |
8480 | } | |
8481 | } | |
8482 | ||
8483 | if (changed_daif & CPSR_F) { | |
8484 | /* Check to see if we are allowed to change the masking of FIQ | |
8485 | * exceptions from a non-secure state. | |
8486 | */ | |
8487 | if (!(env->cp15.scr_el3 & SCR_FW)) { | |
8488 | qemu_log_mask(LOG_GUEST_ERROR, | |
8489 | "Ignoring attempt to switch CPSR_F flag from " | |
8490 | "non-secure world with SCR.FW bit clear\n"); | |
8491 | mask &= ~CPSR_F; | |
8492 | } | |
8493 | ||
8494 | /* Check whether non-maskable FIQ (NMFI) support is enabled. | |
8495 | * If this bit is set software is not allowed to mask | |
8496 | * FIQs, but is allowed to set CPSR_F to 0. | |
8497 | */ | |
8498 | if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && | |
8499 | (val & CPSR_F)) { | |
8500 | qemu_log_mask(LOG_GUEST_ERROR, | |
8501 | "Ignoring attempt to enable CPSR_F flag " | |
8502 | "(non-maskable FIQ [NMFI] support enabled)\n"); | |
8503 | mask &= ~CPSR_F; | |
8504 | } | |
8505 | } | |
8506 | } | |
8507 | ||
4cc35614 PM |
8508 | env->daif &= ~(CPSR_AIF & mask); |
8509 | env->daif |= val & CPSR_AIF & mask; | |
8510 | ||
f8c88bbc PM |
8511 | if (write_type != CPSRWriteRaw && |
8512 | ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { | |
8c4f0eb9 PM |
8513 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { |
8514 | /* Note that we can only get here in USR mode if this is a | |
8515 | * gdb stub write; for this case we follow the architectural | |
8516 | * behaviour for guest writes in USR mode of ignoring an attempt | |
8517 | * to switch mode. (Those are caught by translate.c for writes | |
8518 | * triggered by guest instructions.) | |
8519 | */ | |
8520 | mask &= ~CPSR_M; | |
8521 | } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { | |
81907a58 PM |
8522 | /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in |
8523 | * v7, and has defined behaviour in v8: | |
8524 | * + leave CPSR.M untouched | |
8525 | * + allow changes to the other CPSR fields | |
8526 | * + set PSTATE.IL | |
8527 | * For user changes via the GDB stub, we don't set PSTATE.IL, | |
8528 | * as this would be unnecessarily harsh for a user error. | |
37064a8b PM |
8529 | */ |
8530 | mask &= ~CPSR_M; | |
81907a58 PM |
8531 | if (write_type != CPSRWriteByGDBStub && |
8532 | arm_feature(env, ARM_FEATURE_V8)) { | |
8533 | mask |= CPSR_IL; | |
8534 | val |= CPSR_IL; | |
8535 | } | |
81e37284 PM |
8536 | qemu_log_mask(LOG_GUEST_ERROR, |
8537 | "Illegal AArch32 mode switch attempt from %s to %s\n", | |
8538 | aarch32_mode_name(env->uncached_cpsr), | |
8539 | aarch32_mode_name(val)); | |
37064a8b | 8540 | } else { |
81e37284 PM |
8541 | qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n", |
8542 | write_type == CPSRWriteExceptionReturn ? | |
8543 | "Exception return from AArch32" : | |
8544 | "AArch32 mode switch from", | |
8545 | aarch32_mode_name(env->uncached_cpsr), | |
8546 | aarch32_mode_name(val), env->regs[15]); | |
37064a8b PM |
8547 | switch_mode(env, val & CPSR_M); |
8548 | } | |
2f4a40e5 AZ |
8549 | } |
8550 | mask &= ~CACHED_CPSR_BITS; | |
8551 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
8552 | } | |
8553 | ||
b26eefb6 PB |
8554 | /* Sign/zero extend */ |
8555 | uint32_t HELPER(sxtb16)(uint32_t x) | |
8556 | { | |
8557 | uint32_t res; | |
8558 | res = (uint16_t)(int8_t)x; | |
8559 | res |= (uint32_t)(int8_t)(x >> 16) << 16; | |
8560 | return res; | |
8561 | } | |
8562 | ||
8563 | uint32_t HELPER(uxtb16)(uint32_t x) | |
8564 | { | |
8565 | uint32_t res; | |
8566 | res = (uint16_t)(uint8_t)x; | |
8567 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; | |
8568 | return res; | |
8569 | } | |
8570 | ||
3670669c PB |
8571 | int32_t HELPER(sdiv)(int32_t num, int32_t den) |
8572 | { | |
8573 | if (den == 0) | |
8574 | return 0; | |
686eeb93 AJ |
8575 | if (num == INT_MIN && den == -1) |
8576 | return INT_MIN; | |
3670669c PB |
8577 | return num / den; |
8578 | } | |
8579 | ||
8580 | uint32_t HELPER(udiv)(uint32_t num, uint32_t den) | |
8581 | { | |
8582 | if (den == 0) | |
8583 | return 0; | |
8584 | return num / den; | |
8585 | } | |
8586 | ||
8587 | uint32_t HELPER(rbit)(uint32_t x) | |
8588 | { | |
42fedbca | 8589 | return revbit32(x); |
3670669c PB |
8590 | } |
8591 | ||
c47eaf9f | 8592 | #ifdef CONFIG_USER_ONLY |
b5ff1b31 | 8593 | |
affdb64d | 8594 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 | 8595 | { |
2fc0cc0e | 8596 | ARMCPU *cpu = env_archcpu(env); |
a47dddd7 AF |
8597 | |
8598 | if (mode != ARM_CPU_MODE_USR) { | |
8599 | cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); | |
8600 | } | |
b5ff1b31 FB |
8601 | } |
8602 | ||
012a906b GB |
8603 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
8604 | uint32_t cur_el, bool secure) | |
9e729b57 EI |
8605 | { |
8606 | return 1; | |
8607 | } | |
8608 | ||
ce02049d GB |
8609 | void aarch64_sync_64_to_32(CPUARMState *env) |
8610 | { | |
8611 | g_assert_not_reached(); | |
8612 | } | |
8613 | ||
b5ff1b31 FB |
8614 | #else |
8615 | ||
affdb64d | 8616 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
8617 | { |
8618 | int old_mode; | |
8619 | int i; | |
8620 | ||
8621 | old_mode = env->uncached_cpsr & CPSR_M; | |
8622 | if (mode == old_mode) | |
8623 | return; | |
8624 | ||
8625 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
8626 | memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 8627 | memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
8628 | } else if (mode == ARM_CPU_MODE_FIQ) { |
8629 | memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 8630 | memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
8631 | } |
8632 | ||
f5206413 | 8633 | i = bank_number(old_mode); |
b5ff1b31 | 8634 | env->banked_r13[i] = env->regs[13]; |
b5ff1b31 FB |
8635 | env->banked_spsr[i] = env->spsr; |
8636 | ||
f5206413 | 8637 | i = bank_number(mode); |
b5ff1b31 | 8638 | env->regs[13] = env->banked_r13[i]; |
b5ff1b31 | 8639 | env->spsr = env->banked_spsr[i]; |
593cfa2b PM |
8640 | |
8641 | env->banked_r14[r14_bank_number(old_mode)] = env->regs[14]; | |
8642 | env->regs[14] = env->banked_r14[r14_bank_number(mode)]; | |
b5ff1b31 FB |
8643 | } |
8644 | ||
0eeb17d6 GB |
8645 | /* Physical Interrupt Target EL Lookup Table |
8646 | * | |
8647 | * [ From ARM ARM section G1.13.4 (Table G1-15) ] | |
8648 | * | |
8649 | * The below multi-dimensional table is used for looking up the target | |
8650 | * exception level given numerous condition criteria. Specifically, the | |
8651 | * target EL is based on SCR and HCR routing controls as well as the | |
8652 | * currently executing EL and secure state. | |
8653 | * | |
8654 | * Dimensions: | |
8655 | * target_el_table[2][2][2][2][2][4] | |
8656 | * | | | | | +--- Current EL | |
8657 | * | | | | +------ Non-secure(0)/Secure(1) | |
8658 | * | | | +--------- HCR mask override | |
8659 | * | | +------------ SCR exec state control | |
8660 | * | +--------------- SCR mask override | |
8661 | * +------------------ 32-bit(0)/64-bit(1) EL3 | |
8662 | * | |
8663 | * The table values are as such: | |
8664 | * 0-3 = EL0-EL3 | |
8665 | * -1 = Cannot occur | |
8666 | * | |
8667 | * The ARM ARM target EL table includes entries indicating that an "exception | |
8668 | * is not taken". The two cases where this is applicable are: | |
8669 | * 1) An exception is taken from EL3 but the SCR does not have the exception | |
8670 | * routed to EL3. | |
8671 | * 2) An exception is taken from EL2 but the HCR does not have the exception | |
8672 | * routed to EL2. | |
8673 | * In these two cases, the below table contain a target of EL1. This value is | |
8674 | * returned as it is expected that the consumer of the table data will check | |
8675 | * for "target EL >= current EL" to ensure the exception is not taken. | |
8676 | * | |
8677 | * SCR HCR | |
8678 | * 64 EA AMO From | |
8679 | * BIT IRQ IMO Non-secure Secure | |
8680 | * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 | |
8681 | */ | |
82c39f6a | 8682 | static const int8_t target_el_table[2][2][2][2][2][4] = { |
0eeb17d6 GB |
8683 | {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, |
8684 | {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, | |
8685 | {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, | |
8686 | {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, | |
8687 | {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
8688 | {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, | |
8689 | {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
8690 | {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, | |
8691 | {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, | |
8692 | {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},}, | |
8693 | {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },}, | |
8694 | {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},}, | |
8695 | {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, | |
8696 | {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, | |
8697 | {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, | |
8698 | {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},}, | |
8699 | }; | |
8700 | ||
8701 | /* | |
8702 | * Determine the target EL for physical exceptions | |
8703 | */ | |
012a906b GB |
8704 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
8705 | uint32_t cur_el, bool secure) | |
0eeb17d6 GB |
8706 | { |
8707 | CPUARMState *env = cs->env_ptr; | |
f7778444 RH |
8708 | bool rw; |
8709 | bool scr; | |
8710 | bool hcr; | |
0eeb17d6 | 8711 | int target_el; |
2cde031f | 8712 | /* Is the highest EL AArch64? */ |
f7778444 RH |
8713 | bool is64 = arm_feature(env, ARM_FEATURE_AARCH64); |
8714 | uint64_t hcr_el2; | |
2cde031f SS |
8715 | |
8716 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
8717 | rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); | |
8718 | } else { | |
8719 | /* Either EL2 is the highest EL (and so the EL2 register width | |
8720 | * is given by is64); or there is no EL2 or EL3, in which case | |
8721 | * the value of 'rw' does not affect the table lookup anyway. | |
8722 | */ | |
8723 | rw = is64; | |
8724 | } | |
0eeb17d6 | 8725 | |
f7778444 | 8726 | hcr_el2 = arm_hcr_el2_eff(env); |
0eeb17d6 GB |
8727 | switch (excp_idx) { |
8728 | case EXCP_IRQ: | |
8729 | scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); | |
f7778444 | 8730 | hcr = hcr_el2 & HCR_IMO; |
0eeb17d6 GB |
8731 | break; |
8732 | case EXCP_FIQ: | |
8733 | scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); | |
f7778444 | 8734 | hcr = hcr_el2 & HCR_FMO; |
0eeb17d6 GB |
8735 | break; |
8736 | default: | |
8737 | scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); | |
f7778444 | 8738 | hcr = hcr_el2 & HCR_AMO; |
0eeb17d6 GB |
8739 | break; |
8740 | }; | |
8741 | ||
d1b31428 RH |
8742 | /* |
8743 | * For these purposes, TGE and AMO/IMO/FMO both force the | |
8744 | * interrupt to EL2. Fold TGE into the bit extracted above. | |
8745 | */ | |
8746 | hcr |= (hcr_el2 & HCR_TGE) != 0; | |
8747 | ||
0eeb17d6 GB |
8748 | /* Perform a table-lookup for the target EL given the current state */ |
8749 | target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; | |
8750 | ||
8751 | assert(target_el > 0); | |
8752 | ||
8753 | return target_el; | |
8754 | } | |
8755 | ||
b59f479b PMD |
8756 | void arm_log_exception(int idx) |
8757 | { | |
8758 | if (qemu_loglevel_mask(CPU_LOG_INT)) { | |
8759 | const char *exc = NULL; | |
8760 | static const char * const excnames[] = { | |
8761 | [EXCP_UDEF] = "Undefined Instruction", | |
8762 | [EXCP_SWI] = "SVC", | |
8763 | [EXCP_PREFETCH_ABORT] = "Prefetch Abort", | |
8764 | [EXCP_DATA_ABORT] = "Data Abort", | |
8765 | [EXCP_IRQ] = "IRQ", | |
8766 | [EXCP_FIQ] = "FIQ", | |
8767 | [EXCP_BKPT] = "Breakpoint", | |
8768 | [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", | |
8769 | [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", | |
8770 | [EXCP_HVC] = "Hypervisor Call", | |
8771 | [EXCP_HYP_TRAP] = "Hypervisor Trap", | |
8772 | [EXCP_SMC] = "Secure Monitor Call", | |
8773 | [EXCP_VIRQ] = "Virtual IRQ", | |
8774 | [EXCP_VFIQ] = "Virtual FIQ", | |
8775 | [EXCP_SEMIHOST] = "Semihosting call", | |
8776 | [EXCP_NOCP] = "v7M NOCP UsageFault", | |
8777 | [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", | |
8778 | [EXCP_STKOF] = "v8M STKOF UsageFault", | |
8779 | [EXCP_LAZYFP] = "v7M exception during lazy FP stacking", | |
8780 | [EXCP_LSERR] = "v8M LSERR UsageFault", | |
8781 | [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", | |
8782 | }; | |
8783 | ||
8784 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | |
8785 | exc = excnames[idx]; | |
8786 | } | |
8787 | if (!exc) { | |
8788 | exc = "unknown"; | |
8789 | } | |
8790 | qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); | |
8791 | } | |
8792 | } | |
8793 | ||
a356dacf | 8794 | /* |
7aab5a8c PMD |
8795 | * Function used to synchronize QEMU's AArch64 register set with AArch32 |
8796 | * register set. This is necessary when switching between AArch32 and AArch64 | |
8797 | * execution state. | |
a356dacf | 8798 | */ |
7aab5a8c | 8799 | void aarch64_sync_32_to_64(CPUARMState *env) |
9ee6e8bb | 8800 | { |
7aab5a8c PMD |
8801 | int i; |
8802 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
8803 | ||
8804 | /* We can blanket copy R[0:7] to X[0:7] */ | |
8805 | for (i = 0; i < 8; i++) { | |
8806 | env->xregs[i] = env->regs[i]; | |
fd592d89 | 8807 | } |
70d74660 | 8808 | |
9a223097 | 8809 | /* |
7aab5a8c PMD |
8810 | * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. |
8811 | * Otherwise, they come from the banked user regs. | |
fd592d89 | 8812 | */ |
7aab5a8c PMD |
8813 | if (mode == ARM_CPU_MODE_FIQ) { |
8814 | for (i = 8; i < 13; i++) { | |
8815 | env->xregs[i] = env->usr_regs[i - 8]; | |
8816 | } | |
8817 | } else { | |
8818 | for (i = 8; i < 13; i++) { | |
8819 | env->xregs[i] = env->regs[i]; | |
8820 | } | |
fd592d89 | 8821 | } |
9ee6e8bb | 8822 | |
7aab5a8c PMD |
8823 | /* |
8824 | * Registers x13-x23 are the various mode SP and FP registers. Registers | |
8825 | * r13 and r14 are only copied if we are in that mode, otherwise we copy | |
8826 | * from the mode banked register. | |
8827 | */ | |
8828 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { | |
8829 | env->xregs[13] = env->regs[13]; | |
8830 | env->xregs[14] = env->regs[14]; | |
8831 | } else { | |
8832 | env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; | |
8833 | /* HYP is an exception in that it is copied from r14 */ | |
8834 | if (mode == ARM_CPU_MODE_HYP) { | |
8835 | env->xregs[14] = env->regs[14]; | |
95695eff | 8836 | } else { |
7aab5a8c | 8837 | env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)]; |
95695eff | 8838 | } |
95695eff PM |
8839 | } |
8840 | ||
7aab5a8c PMD |
8841 | if (mode == ARM_CPU_MODE_HYP) { |
8842 | env->xregs[15] = env->regs[13]; | |
8843 | } else { | |
8844 | env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; | |
95695eff PM |
8845 | } |
8846 | ||
7aab5a8c PMD |
8847 | if (mode == ARM_CPU_MODE_IRQ) { |
8848 | env->xregs[16] = env->regs[14]; | |
8849 | env->xregs[17] = env->regs[13]; | |
8850 | } else { | |
8851 | env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)]; | |
8852 | env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; | |
8853 | } | |
95695eff | 8854 | |
7aab5a8c PMD |
8855 | if (mode == ARM_CPU_MODE_SVC) { |
8856 | env->xregs[18] = env->regs[14]; | |
8857 | env->xregs[19] = env->regs[13]; | |
8858 | } else { | |
8859 | env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)]; | |
8860 | env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; | |
8861 | } | |
95695eff | 8862 | |
7aab5a8c PMD |
8863 | if (mode == ARM_CPU_MODE_ABT) { |
8864 | env->xregs[20] = env->regs[14]; | |
8865 | env->xregs[21] = env->regs[13]; | |
8866 | } else { | |
8867 | env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)]; | |
8868 | env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; | |
8869 | } | |
e33cf0f8 | 8870 | |
7aab5a8c PMD |
8871 | if (mode == ARM_CPU_MODE_UND) { |
8872 | env->xregs[22] = env->regs[14]; | |
8873 | env->xregs[23] = env->regs[13]; | |
8874 | } else { | |
8875 | env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)]; | |
8876 | env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; | |
e33cf0f8 PM |
8877 | } |
8878 | ||
8879 | /* | |
7aab5a8c PMD |
8880 | * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ |
8881 | * mode, then we can copy from r8-r14. Otherwise, we copy from the | |
8882 | * FIQ bank for r8-r14. | |
e33cf0f8 | 8883 | */ |
7aab5a8c PMD |
8884 | if (mode == ARM_CPU_MODE_FIQ) { |
8885 | for (i = 24; i < 31; i++) { | |
8886 | env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ | |
8887 | } | |
8888 | } else { | |
8889 | for (i = 24; i < 29; i++) { | |
8890 | env->xregs[i] = env->fiq_regs[i - 24]; | |
e33cf0f8 | 8891 | } |
7aab5a8c PMD |
8892 | env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; |
8893 | env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)]; | |
e33cf0f8 | 8894 | } |
7aab5a8c PMD |
8895 | |
8896 | env->pc = env->regs[15]; | |
e33cf0f8 PM |
8897 | } |
8898 | ||
9a223097 | 8899 | /* |
7aab5a8c PMD |
8900 | * Function used to synchronize QEMU's AArch32 register set with AArch64 |
8901 | * register set. This is necessary when switching between AArch32 and AArch64 | |
8902 | * execution state. | |
de2db7ec | 8903 | */ |
7aab5a8c | 8904 | void aarch64_sync_64_to_32(CPUARMState *env) |
9ee6e8bb | 8905 | { |
7aab5a8c PMD |
8906 | int i; |
8907 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
abc24d86 | 8908 | |
7aab5a8c PMD |
8909 | /* We can blanket copy X[0:7] to R[0:7] */ |
8910 | for (i = 0; i < 8; i++) { | |
8911 | env->regs[i] = env->xregs[i]; | |
de2db7ec | 8912 | } |
3f0cddee | 8913 | |
9a223097 | 8914 | /* |
7aab5a8c PMD |
8915 | * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. |
8916 | * Otherwise, we copy x8-x12 into the banked user regs. | |
de2db7ec | 8917 | */ |
7aab5a8c PMD |
8918 | if (mode == ARM_CPU_MODE_FIQ) { |
8919 | for (i = 8; i < 13; i++) { | |
8920 | env->usr_regs[i - 8] = env->xregs[i]; | |
8921 | } | |
8922 | } else { | |
8923 | for (i = 8; i < 13; i++) { | |
8924 | env->regs[i] = env->xregs[i]; | |
8925 | } | |
fb602cb7 PM |
8926 | } |
8927 | ||
9a223097 | 8928 | /* |
7aab5a8c PMD |
8929 | * Registers r13 & r14 depend on the current mode. |
8930 | * If we are in a given mode, we copy the corresponding x registers to r13 | |
8931 | * and r14. Otherwise, we copy the x register to the banked r13 and r14 | |
8932 | * for the mode. | |
fb602cb7 | 8933 | */ |
7aab5a8c PMD |
8934 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { |
8935 | env->regs[13] = env->xregs[13]; | |
8936 | env->regs[14] = env->xregs[14]; | |
fb602cb7 | 8937 | } else { |
7aab5a8c | 8938 | env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; |
fb602cb7 | 8939 | |
7aab5a8c PMD |
8940 | /* |
8941 | * HYP is an exception in that it does not have its own banked r14 but | |
8942 | * shares the USR r14 | |
8943 | */ | |
8944 | if (mode == ARM_CPU_MODE_HYP) { | |
8945 | env->regs[14] = env->xregs[14]; | |
8946 | } else { | |
8947 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; | |
8948 | } | |
8949 | } | |
fb602cb7 | 8950 | |
7aab5a8c PMD |
8951 | if (mode == ARM_CPU_MODE_HYP) { |
8952 | env->regs[13] = env->xregs[15]; | |
fb602cb7 | 8953 | } else { |
7aab5a8c | 8954 | env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; |
fb602cb7 | 8955 | } |
d02a8698 | 8956 | |
7aab5a8c PMD |
8957 | if (mode == ARM_CPU_MODE_IRQ) { |
8958 | env->regs[14] = env->xregs[16]; | |
8959 | env->regs[13] = env->xregs[17]; | |
d02a8698 | 8960 | } else { |
7aab5a8c PMD |
8961 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; |
8962 | env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; | |
d02a8698 PM |
8963 | } |
8964 | ||
7aab5a8c PMD |
8965 | if (mode == ARM_CPU_MODE_SVC) { |
8966 | env->regs[14] = env->xregs[18]; | |
8967 | env->regs[13] = env->xregs[19]; | |
8968 | } else { | |
8969 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; | |
8970 | env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; | |
fb602cb7 PM |
8971 | } |
8972 | ||
7aab5a8c PMD |
8973 | if (mode == ARM_CPU_MODE_ABT) { |
8974 | env->regs[14] = env->xregs[20]; | |
8975 | env->regs[13] = env->xregs[21]; | |
8976 | } else { | |
8977 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; | |
8978 | env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; | |
ce02049d GB |
8979 | } |
8980 | ||
8981 | if (mode == ARM_CPU_MODE_UND) { | |
3a9148d0 SS |
8982 | env->regs[14] = env->xregs[22]; |
8983 | env->regs[13] = env->xregs[23]; | |
ce02049d | 8984 | } else { |
593cfa2b | 8985 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; |
3a9148d0 | 8986 | env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; |
ce02049d GB |
8987 | } |
8988 | ||
8989 | /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ | |
8990 | * mode, then we can copy to r8-r14. Otherwise, we copy to the | |
8991 | * FIQ bank for r8-r14. | |
8992 | */ | |
8993 | if (mode == ARM_CPU_MODE_FIQ) { | |
8994 | for (i = 24; i < 31; i++) { | |
8995 | env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ | |
8996 | } | |
8997 | } else { | |
8998 | for (i = 24; i < 29; i++) { | |
8999 | env->fiq_regs[i - 24] = env->xregs[i]; | |
9000 | } | |
9001 | env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; | |
593cfa2b | 9002 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; |
ce02049d GB |
9003 | } |
9004 | ||
9005 | env->regs[15] = env->pc; | |
9006 | } | |
9007 | ||
dea8378b PM |
9008 | static void take_aarch32_exception(CPUARMState *env, int new_mode, |
9009 | uint32_t mask, uint32_t offset, | |
9010 | uint32_t newpc) | |
9011 | { | |
4a2696c0 RH |
9012 | int new_el; |
9013 | ||
dea8378b PM |
9014 | /* Change the CPU state so as to actually take the exception. */ |
9015 | switch_mode(env, new_mode); | |
4a2696c0 RH |
9016 | new_el = arm_current_el(env); |
9017 | ||
dea8378b PM |
9018 | /* |
9019 | * For exceptions taken to AArch32 we must clear the SS bit in both | |
9020 | * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. | |
9021 | */ | |
9022 | env->uncached_cpsr &= ~PSTATE_SS; | |
9023 | env->spsr = cpsr_read(env); | |
9024 | /* Clear IT bits. */ | |
9025 | env->condexec_bits = 0; | |
9026 | /* Switch to the new mode, and to the correct instruction set. */ | |
9027 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; | |
9028 | /* Set new mode endianness */ | |
9029 | env->uncached_cpsr &= ~CPSR_E; | |
4a2696c0 | 9030 | if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { |
dea8378b PM |
9031 | env->uncached_cpsr |= CPSR_E; |
9032 | } | |
829f9fd3 PM |
9033 | /* J and IL must always be cleared for exception entry */ |
9034 | env->uncached_cpsr &= ~(CPSR_IL | CPSR_J); | |
dea8378b PM |
9035 | env->daif |= mask; |
9036 | ||
9037 | if (new_mode == ARM_CPU_MODE_HYP) { | |
9038 | env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0; | |
9039 | env->elr_el[2] = env->regs[15]; | |
9040 | } else { | |
4a2696c0 | 9041 | /* CPSR.PAN is normally preserved preserved unless... */ |
f8af1143 | 9042 | if (cpu_isar_feature(aa32_pan, env_archcpu(env))) { |
4a2696c0 RH |
9043 | switch (new_el) { |
9044 | case 3: | |
9045 | if (!arm_is_secure_below_el3(env)) { | |
9046 | /* ... the target is EL3, from non-secure state. */ | |
9047 | env->uncached_cpsr &= ~CPSR_PAN; | |
9048 | break; | |
9049 | } | |
9050 | /* ... the target is EL3, from secure state ... */ | |
9051 | /* fall through */ | |
9052 | case 1: | |
9053 | /* ... the target is EL1 and SCTLR.SPAN is 0. */ | |
9054 | if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { | |
9055 | env->uncached_cpsr |= CPSR_PAN; | |
9056 | } | |
9057 | break; | |
9058 | } | |
9059 | } | |
dea8378b PM |
9060 | /* |
9061 | * this is a lie, as there was no c1_sys on V4T/V5, but who cares | |
9062 | * and we should just guard the thumb mode on V4 | |
9063 | */ | |
9064 | if (arm_feature(env, ARM_FEATURE_V4T)) { | |
9065 | env->thumb = | |
9066 | (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; | |
9067 | } | |
9068 | env->regs[14] = env->regs[15] + offset; | |
9069 | } | |
9070 | env->regs[15] = newpc; | |
a8a79c7a | 9071 | arm_rebuild_hflags(env); |
dea8378b PM |
9072 | } |
9073 | ||
b9bc21ff PM |
9074 | static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) |
9075 | { | |
9076 | /* | |
9077 | * Handle exception entry to Hyp mode; this is sufficiently | |
9078 | * different to entry to other AArch32 modes that we handle it | |
9079 | * separately here. | |
9080 | * | |
9081 | * The vector table entry used is always the 0x14 Hyp mode entry point, | |
9082 | * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp. | |
9083 | * The offset applied to the preferred return address is always zero | |
9084 | * (see DDI0487C.a section G1.12.3). | |
9085 | * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. | |
9086 | */ | |
9087 | uint32_t addr, mask; | |
9088 | ARMCPU *cpu = ARM_CPU(cs); | |
9089 | CPUARMState *env = &cpu->env; | |
9090 | ||
9091 | switch (cs->exception_index) { | |
9092 | case EXCP_UDEF: | |
9093 | addr = 0x04; | |
9094 | break; | |
9095 | case EXCP_SWI: | |
9096 | addr = 0x14; | |
9097 | break; | |
9098 | case EXCP_BKPT: | |
9099 | /* Fall through to prefetch abort. */ | |
9100 | case EXCP_PREFETCH_ABORT: | |
9101 | env->cp15.ifar_s = env->exception.vaddress; | |
9102 | qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n", | |
9103 | (uint32_t)env->exception.vaddress); | |
9104 | addr = 0x0c; | |
9105 | break; | |
9106 | case EXCP_DATA_ABORT: | |
9107 | env->cp15.dfar_s = env->exception.vaddress; | |
9108 | qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n", | |
9109 | (uint32_t)env->exception.vaddress); | |
9110 | addr = 0x10; | |
9111 | break; | |
9112 | case EXCP_IRQ: | |
9113 | addr = 0x18; | |
9114 | break; | |
9115 | case EXCP_FIQ: | |
9116 | addr = 0x1c; | |
9117 | break; | |
9118 | case EXCP_HVC: | |
9119 | addr = 0x08; | |
9120 | break; | |
9121 | case EXCP_HYP_TRAP: | |
9122 | addr = 0x14; | |
9bbb4ef9 | 9123 | break; |
b9bc21ff PM |
9124 | default: |
9125 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
9126 | } | |
9127 | ||
9128 | if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) { | |
2ed08180 PM |
9129 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
9130 | /* | |
9131 | * QEMU syndrome values are v8-style. v7 has the IL bit | |
9132 | * UNK/SBZP for "field not valid" cases, where v8 uses RES1. | |
9133 | * If this is a v7 CPU, squash the IL bit in those cases. | |
9134 | */ | |
9135 | if (cs->exception_index == EXCP_PREFETCH_ABORT || | |
9136 | (cs->exception_index == EXCP_DATA_ABORT && | |
9137 | !(env->exception.syndrome & ARM_EL_ISV)) || | |
9138 | syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) { | |
9139 | env->exception.syndrome &= ~ARM_EL_IL; | |
9140 | } | |
9141 | } | |
b9bc21ff PM |
9142 | env->cp15.esr_el[2] = env->exception.syndrome; |
9143 | } | |
9144 | ||
9145 | if (arm_current_el(env) != 2 && addr < 0x14) { | |
9146 | addr = 0x14; | |
9147 | } | |
9148 | ||
9149 | mask = 0; | |
9150 | if (!(env->cp15.scr_el3 & SCR_EA)) { | |
9151 | mask |= CPSR_A; | |
9152 | } | |
9153 | if (!(env->cp15.scr_el3 & SCR_IRQ)) { | |
9154 | mask |= CPSR_I; | |
9155 | } | |
9156 | if (!(env->cp15.scr_el3 & SCR_FIQ)) { | |
9157 | mask |= CPSR_F; | |
9158 | } | |
9159 | ||
9160 | addr += env->cp15.hvbar; | |
9161 | ||
9162 | take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr); | |
9163 | } | |
9164 | ||
966f758c | 9165 | static void arm_cpu_do_interrupt_aarch32(CPUState *cs) |
b5ff1b31 | 9166 | { |
97a8ea5a AF |
9167 | ARMCPU *cpu = ARM_CPU(cs); |
9168 | CPUARMState *env = &cpu->env; | |
b5ff1b31 FB |
9169 | uint32_t addr; |
9170 | uint32_t mask; | |
9171 | int new_mode; | |
9172 | uint32_t offset; | |
16a906fd | 9173 | uint32_t moe; |
b5ff1b31 | 9174 | |
16a906fd | 9175 | /* If this is a debug exception we must update the DBGDSCR.MOE bits */ |
64b91e3f | 9176 | switch (syn_get_ec(env->exception.syndrome)) { |
16a906fd PM |
9177 | case EC_BREAKPOINT: |
9178 | case EC_BREAKPOINT_SAME_EL: | |
9179 | moe = 1; | |
9180 | break; | |
9181 | case EC_WATCHPOINT: | |
9182 | case EC_WATCHPOINT_SAME_EL: | |
9183 | moe = 10; | |
9184 | break; | |
9185 | case EC_AA32_BKPT: | |
9186 | moe = 3; | |
9187 | break; | |
9188 | case EC_VECTORCATCH: | |
9189 | moe = 5; | |
9190 | break; | |
9191 | default: | |
9192 | moe = 0; | |
9193 | break; | |
9194 | } | |
9195 | ||
9196 | if (moe) { | |
9197 | env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); | |
9198 | } | |
9199 | ||
b9bc21ff PM |
9200 | if (env->exception.target_el == 2) { |
9201 | arm_cpu_do_interrupt_aarch32_hyp(cs); | |
9202 | return; | |
9203 | } | |
9204 | ||
27103424 | 9205 | switch (cs->exception_index) { |
b5ff1b31 FB |
9206 | case EXCP_UDEF: |
9207 | new_mode = ARM_CPU_MODE_UND; | |
9208 | addr = 0x04; | |
9209 | mask = CPSR_I; | |
9210 | if (env->thumb) | |
9211 | offset = 2; | |
9212 | else | |
9213 | offset = 4; | |
9214 | break; | |
9215 | case EXCP_SWI: | |
9216 | new_mode = ARM_CPU_MODE_SVC; | |
9217 | addr = 0x08; | |
9218 | mask = CPSR_I; | |
601d70b9 | 9219 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
9220 | offset = 0; |
9221 | break; | |
06c949e6 | 9222 | case EXCP_BKPT: |
9ee6e8bb PB |
9223 | /* Fall through to prefetch abort. */ |
9224 | case EXCP_PREFETCH_ABORT: | |
88ca1c2d | 9225 | A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); |
b848ce2b | 9226 | A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); |
3f1beaca | 9227 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", |
88ca1c2d | 9228 | env->exception.fsr, (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
9229 | new_mode = ARM_CPU_MODE_ABT; |
9230 | addr = 0x0c; | |
9231 | mask = CPSR_A | CPSR_I; | |
9232 | offset = 4; | |
9233 | break; | |
9234 | case EXCP_DATA_ABORT: | |
4a7e2d73 | 9235 | A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); |
b848ce2b | 9236 | A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); |
3f1beaca | 9237 | qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", |
4a7e2d73 | 9238 | env->exception.fsr, |
6cd8a264 | 9239 | (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
9240 | new_mode = ARM_CPU_MODE_ABT; |
9241 | addr = 0x10; | |
9242 | mask = CPSR_A | CPSR_I; | |
9243 | offset = 8; | |
9244 | break; | |
9245 | case EXCP_IRQ: | |
9246 | new_mode = ARM_CPU_MODE_IRQ; | |
9247 | addr = 0x18; | |
9248 | /* Disable IRQ and imprecise data aborts. */ | |
9249 | mask = CPSR_A | CPSR_I; | |
9250 | offset = 4; | |
de38d23b FA |
9251 | if (env->cp15.scr_el3 & SCR_IRQ) { |
9252 | /* IRQ routed to monitor mode */ | |
9253 | new_mode = ARM_CPU_MODE_MON; | |
9254 | mask |= CPSR_F; | |
9255 | } | |
b5ff1b31 FB |
9256 | break; |
9257 | case EXCP_FIQ: | |
9258 | new_mode = ARM_CPU_MODE_FIQ; | |
9259 | addr = 0x1c; | |
9260 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
9261 | mask = CPSR_A | CPSR_I | CPSR_F; | |
de38d23b FA |
9262 | if (env->cp15.scr_el3 & SCR_FIQ) { |
9263 | /* FIQ routed to monitor mode */ | |
9264 | new_mode = ARM_CPU_MODE_MON; | |
9265 | } | |
b5ff1b31 FB |
9266 | offset = 4; |
9267 | break; | |
87a4b270 PM |
9268 | case EXCP_VIRQ: |
9269 | new_mode = ARM_CPU_MODE_IRQ; | |
9270 | addr = 0x18; | |
9271 | /* Disable IRQ and imprecise data aborts. */ | |
9272 | mask = CPSR_A | CPSR_I; | |
9273 | offset = 4; | |
9274 | break; | |
9275 | case EXCP_VFIQ: | |
9276 | new_mode = ARM_CPU_MODE_FIQ; | |
9277 | addr = 0x1c; | |
9278 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
9279 | mask = CPSR_A | CPSR_I | CPSR_F; | |
9280 | offset = 4; | |
9281 | break; | |
dbe9d163 FA |
9282 | case EXCP_SMC: |
9283 | new_mode = ARM_CPU_MODE_MON; | |
9284 | addr = 0x08; | |
9285 | mask = CPSR_A | CPSR_I | CPSR_F; | |
9286 | offset = 0; | |
9287 | break; | |
b5ff1b31 | 9288 | default: |
a47dddd7 | 9289 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
b5ff1b31 FB |
9290 | return; /* Never happens. Keep compiler happy. */ |
9291 | } | |
e89e51a1 FA |
9292 | |
9293 | if (new_mode == ARM_CPU_MODE_MON) { | |
9294 | addr += env->cp15.mvbar; | |
137feaa9 | 9295 | } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { |
e89e51a1 | 9296 | /* High vectors. When enabled, base address cannot be remapped. */ |
b5ff1b31 | 9297 | addr += 0xffff0000; |
8641136c NR |
9298 | } else { |
9299 | /* ARM v7 architectures provide a vector base address register to remap | |
9300 | * the interrupt vector table. | |
e89e51a1 | 9301 | * This register is only followed in non-monitor mode, and is banked. |
8641136c NR |
9302 | * Note: only bits 31:5 are valid. |
9303 | */ | |
fb6c91ba | 9304 | addr += A32_BANKED_CURRENT_REG_GET(env, vbar); |
b5ff1b31 | 9305 | } |
dbe9d163 FA |
9306 | |
9307 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
9308 | env->cp15.scr_el3 &= ~SCR_NS; | |
9309 | } | |
9310 | ||
dea8378b | 9311 | take_aarch32_exception(env, new_mode, mask, offset, addr); |
b5ff1b31 FB |
9312 | } |
9313 | ||
966f758c PM |
9314 | /* Handle exception entry to a target EL which is using AArch64 */ |
9315 | static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | |
f3a9b694 PM |
9316 | { |
9317 | ARMCPU *cpu = ARM_CPU(cs); | |
9318 | CPUARMState *env = &cpu->env; | |
9319 | unsigned int new_el = env->exception.target_el; | |
9320 | target_ulong addr = env->cp15.vbar_el[new_el]; | |
9321 | unsigned int new_mode = aarch64_pstate_mode(new_el, true); | |
4a2696c0 | 9322 | unsigned int old_mode; |
0ab5953b RH |
9323 | unsigned int cur_el = arm_current_el(env); |
9324 | ||
9a05f7b6 RH |
9325 | /* |
9326 | * Note that new_el can never be 0. If cur_el is 0, then | |
9327 | * el0_a64 is is_a64(), else el0_a64 is ignored. | |
9328 | */ | |
9329 | aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); | |
f3a9b694 | 9330 | |
0ab5953b | 9331 | if (cur_el < new_el) { |
3d6f7617 PM |
9332 | /* Entry vector offset depends on whether the implemented EL |
9333 | * immediately lower than the target level is using AArch32 or AArch64 | |
9334 | */ | |
9335 | bool is_aa64; | |
cb092fbb | 9336 | uint64_t hcr; |
3d6f7617 PM |
9337 | |
9338 | switch (new_el) { | |
9339 | case 3: | |
9340 | is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; | |
9341 | break; | |
9342 | case 2: | |
cb092fbb RH |
9343 | hcr = arm_hcr_el2_eff(env); |
9344 | if ((hcr & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { | |
9345 | is_aa64 = (hcr & HCR_RW) != 0; | |
9346 | break; | |
9347 | } | |
9348 | /* fall through */ | |
3d6f7617 PM |
9349 | case 1: |
9350 | is_aa64 = is_a64(env); | |
9351 | break; | |
9352 | default: | |
9353 | g_assert_not_reached(); | |
9354 | } | |
9355 | ||
9356 | if (is_aa64) { | |
f3a9b694 PM |
9357 | addr += 0x400; |
9358 | } else { | |
9359 | addr += 0x600; | |
9360 | } | |
9361 | } else if (pstate_read(env) & PSTATE_SP) { | |
9362 | addr += 0x200; | |
9363 | } | |
9364 | ||
f3a9b694 PM |
9365 | switch (cs->exception_index) { |
9366 | case EXCP_PREFETCH_ABORT: | |
9367 | case EXCP_DATA_ABORT: | |
9368 | env->cp15.far_el[new_el] = env->exception.vaddress; | |
9369 | qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", | |
9370 | env->cp15.far_el[new_el]); | |
9371 | /* fall through */ | |
9372 | case EXCP_BKPT: | |
9373 | case EXCP_UDEF: | |
9374 | case EXCP_SWI: | |
9375 | case EXCP_HVC: | |
9376 | case EXCP_HYP_TRAP: | |
9377 | case EXCP_SMC: | |
4be42f40 PM |
9378 | if (syn_get_ec(env->exception.syndrome) == EC_ADVSIMDFPACCESSTRAP) { |
9379 | /* | |
9380 | * QEMU internal FP/SIMD syndromes from AArch32 include the | |
9381 | * TA and coproc fields which are only exposed if the exception | |
9382 | * is taken to AArch32 Hyp mode. Mask them out to get a valid | |
9383 | * AArch64 format syndrome. | |
9384 | */ | |
9385 | env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20); | |
9386 | } | |
f3a9b694 PM |
9387 | env->cp15.esr_el[new_el] = env->exception.syndrome; |
9388 | break; | |
9389 | case EXCP_IRQ: | |
9390 | case EXCP_VIRQ: | |
9391 | addr += 0x80; | |
9392 | break; | |
9393 | case EXCP_FIQ: | |
9394 | case EXCP_VFIQ: | |
9395 | addr += 0x100; | |
9396 | break; | |
f3a9b694 PM |
9397 | default: |
9398 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
9399 | } | |
9400 | ||
9401 | if (is_a64(env)) { | |
4a2696c0 | 9402 | old_mode = pstate_read(env); |
f3a9b694 PM |
9403 | aarch64_save_sp(env, arm_current_el(env)); |
9404 | env->elr_el[new_el] = env->pc; | |
9405 | } else { | |
4a2696c0 | 9406 | old_mode = cpsr_read(env); |
f3a9b694 PM |
9407 | env->elr_el[new_el] = env->regs[15]; |
9408 | ||
9409 | aarch64_sync_32_to_64(env); | |
9410 | ||
9411 | env->condexec_bits = 0; | |
9412 | } | |
4a2696c0 RH |
9413 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode; |
9414 | ||
f3a9b694 PM |
9415 | qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", |
9416 | env->elr_el[new_el]); | |
9417 | ||
4a2696c0 RH |
9418 | if (cpu_isar_feature(aa64_pan, cpu)) { |
9419 | /* The value of PSTATE.PAN is normally preserved, except when ... */ | |
9420 | new_mode |= old_mode & PSTATE_PAN; | |
9421 | switch (new_el) { | |
9422 | case 2: | |
9423 | /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */ | |
9424 | if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) | |
9425 | != (HCR_E2H | HCR_TGE)) { | |
9426 | break; | |
9427 | } | |
9428 | /* fall through */ | |
9429 | case 1: | |
9430 | /* ... the target is EL1 ... */ | |
9431 | /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */ | |
9432 | if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) == 0) { | |
9433 | new_mode |= PSTATE_PAN; | |
9434 | } | |
9435 | break; | |
9436 | } | |
9437 | } | |
9438 | ||
f3a9b694 PM |
9439 | pstate_write(env, PSTATE_DAIF | new_mode); |
9440 | env->aarch64 = 1; | |
9441 | aarch64_restore_sp(env, new_el); | |
a8a79c7a | 9442 | helper_rebuild_hflags_a64(env, new_el); |
f3a9b694 PM |
9443 | |
9444 | env->pc = addr; | |
9445 | ||
9446 | qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", | |
9447 | new_el, env->pc, pstate_read(env)); | |
966f758c PM |
9448 | } |
9449 | ||
ed6e6ba9 AB |
9450 | /* |
9451 | * Do semihosting call and set the appropriate return value. All the | |
9452 | * permission and validity checks have been done at translate time. | |
9453 | * | |
9454 | * We only see semihosting exceptions in TCG only as they are not | |
9455 | * trapped to the hypervisor in KVM. | |
9456 | */ | |
91f78c58 | 9457 | #ifdef CONFIG_TCG |
ed6e6ba9 AB |
9458 | static void handle_semihosting(CPUState *cs) |
9459 | { | |
904c04de PM |
9460 | ARMCPU *cpu = ARM_CPU(cs); |
9461 | CPUARMState *env = &cpu->env; | |
9462 | ||
9463 | if (is_a64(env)) { | |
ed6e6ba9 AB |
9464 | qemu_log_mask(CPU_LOG_INT, |
9465 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
9466 | env->xregs[0]); | |
9467 | env->xregs[0] = do_arm_semihosting(env); | |
4ff5ef9e | 9468 | env->pc += 4; |
904c04de | 9469 | } else { |
904c04de PM |
9470 | qemu_log_mask(CPU_LOG_INT, |
9471 | "...handling as semihosting call 0x%x\n", | |
9472 | env->regs[0]); | |
9473 | env->regs[0] = do_arm_semihosting(env); | |
4ff5ef9e | 9474 | env->regs[15] += env->thumb ? 2 : 4; |
904c04de PM |
9475 | } |
9476 | } | |
ed6e6ba9 | 9477 | #endif |
904c04de | 9478 | |
966f758c PM |
9479 | /* Handle a CPU exception for A and R profile CPUs. |
9480 | * Do any appropriate logging, handle PSCI calls, and then hand off | |
9481 | * to the AArch64-entry or AArch32-entry function depending on the | |
9482 | * target exception level's register width. | |
9483 | */ | |
9484 | void arm_cpu_do_interrupt(CPUState *cs) | |
9485 | { | |
9486 | ARMCPU *cpu = ARM_CPU(cs); | |
9487 | CPUARMState *env = &cpu->env; | |
9488 | unsigned int new_el = env->exception.target_el; | |
9489 | ||
531c60a9 | 9490 | assert(!arm_feature(env, ARM_FEATURE_M)); |
966f758c PM |
9491 | |
9492 | arm_log_exception(cs->exception_index); | |
9493 | qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), | |
9494 | new_el); | |
9495 | if (qemu_loglevel_mask(CPU_LOG_INT) | |
9496 | && !excp_is_internal(cs->exception_index)) { | |
6568da45 | 9497 | qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", |
64b91e3f | 9498 | syn_get_ec(env->exception.syndrome), |
966f758c PM |
9499 | env->exception.syndrome); |
9500 | } | |
9501 | ||
9502 | if (arm_is_psci_call(cpu, cs->exception_index)) { | |
9503 | arm_handle_psci_call(cpu); | |
9504 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | |
9505 | return; | |
9506 | } | |
9507 | ||
ed6e6ba9 AB |
9508 | /* |
9509 | * Semihosting semantics depend on the register width of the code | |
9510 | * that caused the exception, not the target exception level, so | |
9511 | * must be handled here. | |
966f758c | 9512 | */ |
ed6e6ba9 AB |
9513 | #ifdef CONFIG_TCG |
9514 | if (cs->exception_index == EXCP_SEMIHOST) { | |
9515 | handle_semihosting(cs); | |
904c04de PM |
9516 | return; |
9517 | } | |
ed6e6ba9 | 9518 | #endif |
904c04de | 9519 | |
b5c53d1b AL |
9520 | /* Hooks may change global state so BQL should be held, also the |
9521 | * BQL needs to be held for any modification of | |
9522 | * cs->interrupt_request. | |
9523 | */ | |
9524 | g_assert(qemu_mutex_iothread_locked()); | |
9525 | ||
9526 | arm_call_pre_el_change_hook(cpu); | |
9527 | ||
904c04de PM |
9528 | assert(!excp_is_internal(cs->exception_index)); |
9529 | if (arm_el_is_aa64(env, new_el)) { | |
966f758c PM |
9530 | arm_cpu_do_interrupt_aarch64(cs); |
9531 | } else { | |
9532 | arm_cpu_do_interrupt_aarch32(cs); | |
9533 | } | |
f3a9b694 | 9534 | |
bd7d00fc PM |
9535 | arm_call_el_change_hook(cpu); |
9536 | ||
f3a9b694 PM |
9537 | if (!kvm_enabled()) { |
9538 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
9539 | } | |
9540 | } | |
c47eaf9f | 9541 | #endif /* !CONFIG_USER_ONLY */ |
0480f69a PM |
9542 | |
9543 | /* Return the exception level which controls this address translation regime */ | |
b9f6033c | 9544 | static uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) |
0480f69a PM |
9545 | { |
9546 | switch (mmu_idx) { | |
b9f6033c RH |
9547 | case ARMMMUIdx_E20_0: |
9548 | case ARMMMUIdx_E20_2: | |
452ef8cb | 9549 | case ARMMMUIdx_E20_2_PAN: |
97fa9350 | 9550 | case ARMMMUIdx_Stage2: |
e013b741 | 9551 | case ARMMMUIdx_E2: |
0480f69a | 9552 | return 2; |
127b2b08 | 9553 | case ARMMMUIdx_SE3: |
0480f69a | 9554 | return 3; |
fba37aed | 9555 | case ARMMMUIdx_SE10_0: |
0480f69a | 9556 | return arm_el_is_aa64(env, 3) ? 1 : 3; |
fba37aed | 9557 | case ARMMMUIdx_SE10_1: |
452ef8cb | 9558 | case ARMMMUIdx_SE10_1_PAN: |
2859d7b5 RH |
9559 | case ARMMMUIdx_Stage1_E0: |
9560 | case ARMMMUIdx_Stage1_E1: | |
452ef8cb | 9561 | case ARMMMUIdx_Stage1_E1_PAN: |
b9f6033c RH |
9562 | case ARMMMUIdx_E10_0: |
9563 | case ARMMMUIdx_E10_1: | |
452ef8cb | 9564 | case ARMMMUIdx_E10_1_PAN: |
62593718 PM |
9565 | case ARMMMUIdx_MPrivNegPri: |
9566 | case ARMMMUIdx_MUserNegPri: | |
e7b921c2 PM |
9567 | case ARMMMUIdx_MPriv: |
9568 | case ARMMMUIdx_MUser: | |
62593718 PM |
9569 | case ARMMMUIdx_MSPrivNegPri: |
9570 | case ARMMMUIdx_MSUserNegPri: | |
66787c78 | 9571 | case ARMMMUIdx_MSPriv: |
66787c78 | 9572 | case ARMMMUIdx_MSUser: |
0480f69a PM |
9573 | return 1; |
9574 | default: | |
9575 | g_assert_not_reached(); | |
9576 | } | |
9577 | } | |
9578 | ||
aaec1432 RH |
9579 | uint64_t arm_sctlr(CPUARMState *env, int el) |
9580 | { | |
9581 | /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ | |
9582 | if (el == 0) { | |
9583 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0); | |
9584 | el = (mmu_idx == ARMMMUIdx_E20_0 ? 2 : 1); | |
9585 | } | |
9586 | return env->cp15.sctlr_el[el]; | |
9587 | } | |
c47eaf9f | 9588 | |
0480f69a | 9589 | /* Return the SCTLR value which controls this address translation regime */ |
aaec1432 | 9590 | static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) |
0480f69a PM |
9591 | { |
9592 | return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; | |
9593 | } | |
9594 | ||
aaec1432 RH |
9595 | #ifndef CONFIG_USER_ONLY |
9596 | ||
0480f69a PM |
9597 | /* Return true if the specified stage of address translation is disabled */ |
9598 | static inline bool regime_translation_disabled(CPUARMState *env, | |
9599 | ARMMMUIdx mmu_idx) | |
9600 | { | |
29c483a5 | 9601 | if (arm_feature(env, ARM_FEATURE_M)) { |
ecf5e8ea | 9602 | switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & |
3bef7012 PM |
9603 | (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { |
9604 | case R_V7M_MPU_CTRL_ENABLE_MASK: | |
9605 | /* Enabled, but not for HardFault and NMI */ | |
62593718 | 9606 | return mmu_idx & ARM_MMU_IDX_M_NEGPRI; |
3bef7012 PM |
9607 | case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: |
9608 | /* Enabled for all cases */ | |
9609 | return false; | |
9610 | case 0: | |
9611 | default: | |
9612 | /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but | |
9613 | * we warned about that in armv7m_nvic.c when the guest set it. | |
9614 | */ | |
9615 | return true; | |
9616 | } | |
29c483a5 MD |
9617 | } |
9618 | ||
97fa9350 | 9619 | if (mmu_idx == ARMMMUIdx_Stage2) { |
9d1bab33 PM |
9620 | /* HCR.DC means HCR.VM behaves as 1 */ |
9621 | return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) == 0; | |
0480f69a | 9622 | } |
3d0e3080 PM |
9623 | |
9624 | if (env->cp15.hcr_el2 & HCR_TGE) { | |
9625 | /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ | |
9626 | if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) { | |
9627 | return true; | |
9628 | } | |
9629 | } | |
9630 | ||
fee7aa46 | 9631 | if ((env->cp15.hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { |
9d1bab33 PM |
9632 | /* HCR.DC means SCTLR_EL1.M behaves as 0 */ |
9633 | return true; | |
9634 | } | |
9635 | ||
0480f69a PM |
9636 | return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; |
9637 | } | |
9638 | ||
73462ddd PC |
9639 | static inline bool regime_translation_big_endian(CPUARMState *env, |
9640 | ARMMMUIdx mmu_idx) | |
9641 | { | |
9642 | return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; | |
9643 | } | |
9644 | ||
c47eaf9f PM |
9645 | /* Return the TTBR associated with this translation regime */ |
9646 | static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, | |
9647 | int ttbrn) | |
9648 | { | |
97fa9350 | 9649 | if (mmu_idx == ARMMMUIdx_Stage2) { |
c47eaf9f PM |
9650 | return env->cp15.vttbr_el2; |
9651 | } | |
9652 | if (ttbrn == 0) { | |
9653 | return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; | |
9654 | } else { | |
9655 | return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; | |
9656 | } | |
9657 | } | |
9658 | ||
9659 | #endif /* !CONFIG_USER_ONLY */ | |
9660 | ||
0480f69a PM |
9661 | /* Return the TCR controlling this translation regime */ |
9662 | static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) | |
9663 | { | |
97fa9350 | 9664 | if (mmu_idx == ARMMMUIdx_Stage2) { |
68e9c2fe | 9665 | return &env->cp15.vtcr_el2; |
0480f69a PM |
9666 | } |
9667 | return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; | |
9668 | } | |
9669 | ||
8bd5c820 PM |
9670 | /* Convert a possible stage1+2 MMU index into the appropriate |
9671 | * stage 1 MMU index | |
9672 | */ | |
9673 | static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) | |
9674 | { | |
b9f6033c RH |
9675 | switch (mmu_idx) { |
9676 | case ARMMMUIdx_E10_0: | |
9677 | return ARMMMUIdx_Stage1_E0; | |
9678 | case ARMMMUIdx_E10_1: | |
9679 | return ARMMMUIdx_Stage1_E1; | |
452ef8cb RH |
9680 | case ARMMMUIdx_E10_1_PAN: |
9681 | return ARMMMUIdx_Stage1_E1_PAN; | |
b9f6033c RH |
9682 | default: |
9683 | return mmu_idx; | |
8bd5c820 | 9684 | } |
8bd5c820 PM |
9685 | } |
9686 | ||
0480f69a PM |
9687 | /* Return true if the translation regime is using LPAE format page tables */ |
9688 | static inline bool regime_using_lpae_format(CPUARMState *env, | |
9689 | ARMMMUIdx mmu_idx) | |
9690 | { | |
9691 | int el = regime_el(env, mmu_idx); | |
9692 | if (el == 2 || arm_el_is_aa64(env, el)) { | |
9693 | return true; | |
9694 | } | |
9695 | if (arm_feature(env, ARM_FEATURE_LPAE) | |
9696 | && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { | |
9697 | return true; | |
9698 | } | |
9699 | return false; | |
9700 | } | |
9701 | ||
deb2db99 AR |
9702 | /* Returns true if the stage 1 translation regime is using LPAE format page |
9703 | * tables. Used when raising alignment exceptions, whose FSR changes depending | |
9704 | * on whether the long or short descriptor format is in use. */ | |
9705 | bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) | |
30901475 | 9706 | { |
8bd5c820 | 9707 | mmu_idx = stage_1_mmu_idx(mmu_idx); |
deb2db99 | 9708 | |
30901475 AB |
9709 | return regime_using_lpae_format(env, mmu_idx); |
9710 | } | |
9711 | ||
c47eaf9f | 9712 | #ifndef CONFIG_USER_ONLY |
0480f69a PM |
9713 | static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) |
9714 | { | |
9715 | switch (mmu_idx) { | |
fba37aed | 9716 | case ARMMMUIdx_SE10_0: |
b9f6033c | 9717 | case ARMMMUIdx_E20_0: |
2859d7b5 | 9718 | case ARMMMUIdx_Stage1_E0: |
e7b921c2 | 9719 | case ARMMMUIdx_MUser: |
871bec7c | 9720 | case ARMMMUIdx_MSUser: |
62593718 PM |
9721 | case ARMMMUIdx_MUserNegPri: |
9722 | case ARMMMUIdx_MSUserNegPri: | |
0480f69a PM |
9723 | return true; |
9724 | default: | |
9725 | return false; | |
01b98b68 RH |
9726 | case ARMMMUIdx_E10_0: |
9727 | case ARMMMUIdx_E10_1: | |
452ef8cb | 9728 | case ARMMMUIdx_E10_1_PAN: |
0480f69a PM |
9729 | g_assert_not_reached(); |
9730 | } | |
9731 | } | |
9732 | ||
0fbf5238 AJ |
9733 | /* Translate section/page access permissions to page |
9734 | * R/W protection flags | |
d76951b6 AJ |
9735 | * |
9736 | * @env: CPUARMState | |
9737 | * @mmu_idx: MMU index indicating required translation regime | |
9738 | * @ap: The 3-bit access permissions (AP[2:0]) | |
9739 | * @domain_prot: The 2-bit domain access permissions | |
0fbf5238 AJ |
9740 | */ |
9741 | static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, | |
9742 | int ap, int domain_prot) | |
9743 | { | |
554b0b09 PM |
9744 | bool is_user = regime_is_user(env, mmu_idx); |
9745 | ||
9746 | if (domain_prot == 3) { | |
9747 | return PAGE_READ | PAGE_WRITE; | |
9748 | } | |
9749 | ||
554b0b09 PM |
9750 | switch (ap) { |
9751 | case 0: | |
9752 | if (arm_feature(env, ARM_FEATURE_V7)) { | |
9753 | return 0; | |
9754 | } | |
554b0b09 PM |
9755 | switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) { |
9756 | case SCTLR_S: | |
9757 | return is_user ? 0 : PAGE_READ; | |
9758 | case SCTLR_R: | |
9759 | return PAGE_READ; | |
9760 | default: | |
9761 | return 0; | |
9762 | } | |
9763 | case 1: | |
9764 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
9765 | case 2: | |
87c3d486 | 9766 | if (is_user) { |
0fbf5238 | 9767 | return PAGE_READ; |
87c3d486 | 9768 | } else { |
554b0b09 | 9769 | return PAGE_READ | PAGE_WRITE; |
87c3d486 | 9770 | } |
554b0b09 PM |
9771 | case 3: |
9772 | return PAGE_READ | PAGE_WRITE; | |
9773 | case 4: /* Reserved. */ | |
9774 | return 0; | |
9775 | case 5: | |
0fbf5238 | 9776 | return is_user ? 0 : PAGE_READ; |
554b0b09 | 9777 | case 6: |
0fbf5238 | 9778 | return PAGE_READ; |
554b0b09 | 9779 | case 7: |
87c3d486 | 9780 | if (!arm_feature(env, ARM_FEATURE_V6K)) { |
554b0b09 | 9781 | return 0; |
87c3d486 | 9782 | } |
0fbf5238 | 9783 | return PAGE_READ; |
554b0b09 | 9784 | default: |
0fbf5238 | 9785 | g_assert_not_reached(); |
554b0b09 | 9786 | } |
b5ff1b31 FB |
9787 | } |
9788 | ||
d76951b6 AJ |
9789 | /* Translate section/page access permissions to page |
9790 | * R/W protection flags. | |
9791 | * | |
d76951b6 | 9792 | * @ap: The 2-bit simple AP (AP[2:1]) |
d8e052b3 | 9793 | * @is_user: TRUE if accessing from PL0 |
d76951b6 | 9794 | */ |
d8e052b3 | 9795 | static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user) |
d76951b6 | 9796 | { |
d76951b6 AJ |
9797 | switch (ap) { |
9798 | case 0: | |
9799 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
9800 | case 1: | |
9801 | return PAGE_READ | PAGE_WRITE; | |
9802 | case 2: | |
9803 | return is_user ? 0 : PAGE_READ; | |
9804 | case 3: | |
9805 | return PAGE_READ; | |
9806 | default: | |
9807 | g_assert_not_reached(); | |
9808 | } | |
9809 | } | |
9810 | ||
d8e052b3 AJ |
9811 | static inline int |
9812 | simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) | |
9813 | { | |
9814 | return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); | |
9815 | } | |
9816 | ||
6ab1a5ee EI |
9817 | /* Translate S2 section/page access permissions to protection flags |
9818 | * | |
9819 | * @env: CPUARMState | |
9820 | * @s2ap: The 2-bit stage2 access permissions (S2AP) | |
9821 | * @xn: XN (execute-never) bit | |
9822 | */ | |
9823 | static int get_S2prot(CPUARMState *env, int s2ap, int xn) | |
9824 | { | |
9825 | int prot = 0; | |
9826 | ||
9827 | if (s2ap & 1) { | |
9828 | prot |= PAGE_READ; | |
9829 | } | |
9830 | if (s2ap & 2) { | |
9831 | prot |= PAGE_WRITE; | |
9832 | } | |
9833 | if (!xn) { | |
dfda6837 SS |
9834 | if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { |
9835 | prot |= PAGE_EXEC; | |
9836 | } | |
6ab1a5ee EI |
9837 | } |
9838 | return prot; | |
9839 | } | |
9840 | ||
d8e052b3 AJ |
9841 | /* Translate section/page access permissions to protection flags |
9842 | * | |
9843 | * @env: CPUARMState | |
9844 | * @mmu_idx: MMU index indicating required translation regime | |
9845 | * @is_aa64: TRUE if AArch64 | |
9846 | * @ap: The 2-bit simple AP (AP[2:1]) | |
9847 | * @ns: NS (non-secure) bit | |
9848 | * @xn: XN (execute-never) bit | |
9849 | * @pxn: PXN (privileged execute-never) bit | |
9850 | */ | |
9851 | static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, | |
9852 | int ap, int ns, int xn, int pxn) | |
9853 | { | |
9854 | bool is_user = regime_is_user(env, mmu_idx); | |
9855 | int prot_rw, user_rw; | |
9856 | bool have_wxn; | |
9857 | int wxn = 0; | |
9858 | ||
97fa9350 | 9859 | assert(mmu_idx != ARMMMUIdx_Stage2); |
d8e052b3 AJ |
9860 | |
9861 | user_rw = simple_ap_to_rw_prot_is_user(ap, true); | |
9862 | if (is_user) { | |
9863 | prot_rw = user_rw; | |
9864 | } else { | |
81636b70 RH |
9865 | if (user_rw && regime_is_pan(env, mmu_idx)) { |
9866 | return 0; | |
9867 | } | |
d8e052b3 AJ |
9868 | prot_rw = simple_ap_to_rw_prot_is_user(ap, false); |
9869 | } | |
9870 | ||
9871 | if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { | |
9872 | return prot_rw; | |
9873 | } | |
9874 | ||
9875 | /* TODO have_wxn should be replaced with | |
9876 | * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) | |
9877 | * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE | |
9878 | * compatible processors have EL2, which is required for [U]WXN. | |
9879 | */ | |
9880 | have_wxn = arm_feature(env, ARM_FEATURE_LPAE); | |
9881 | ||
9882 | if (have_wxn) { | |
9883 | wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN; | |
9884 | } | |
9885 | ||
9886 | if (is_aa64) { | |
339370b9 RH |
9887 | if (regime_has_2_ranges(mmu_idx) && !is_user) { |
9888 | xn = pxn || (user_rw & PAGE_WRITE); | |
d8e052b3 AJ |
9889 | } |
9890 | } else if (arm_feature(env, ARM_FEATURE_V7)) { | |
9891 | switch (regime_el(env, mmu_idx)) { | |
9892 | case 1: | |
9893 | case 3: | |
9894 | if (is_user) { | |
9895 | xn = xn || !(user_rw & PAGE_READ); | |
9896 | } else { | |
9897 | int uwxn = 0; | |
9898 | if (have_wxn) { | |
9899 | uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN; | |
9900 | } | |
9901 | xn = xn || !(prot_rw & PAGE_READ) || pxn || | |
9902 | (uwxn && (user_rw & PAGE_WRITE)); | |
9903 | } | |
9904 | break; | |
9905 | case 2: | |
9906 | break; | |
9907 | } | |
9908 | } else { | |
9909 | xn = wxn = 0; | |
9910 | } | |
9911 | ||
9912 | if (xn || (wxn && (prot_rw & PAGE_WRITE))) { | |
9913 | return prot_rw; | |
9914 | } | |
9915 | return prot_rw | PAGE_EXEC; | |
9916 | } | |
9917 | ||
0480f69a PM |
9918 | static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, |
9919 | uint32_t *table, uint32_t address) | |
b2fa1797 | 9920 | { |
0480f69a | 9921 | /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ |
0480f69a | 9922 | TCR *tcr = regime_tcr(env, mmu_idx); |
11f136ee | 9923 | |
11f136ee FA |
9924 | if (address & tcr->mask) { |
9925 | if (tcr->raw_tcr & TTBCR_PD1) { | |
e389be16 FA |
9926 | /* Translation table walk disabled for TTBR1 */ |
9927 | return false; | |
9928 | } | |
aef878be | 9929 | *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; |
e389be16 | 9930 | } else { |
11f136ee | 9931 | if (tcr->raw_tcr & TTBCR_PD0) { |
e389be16 FA |
9932 | /* Translation table walk disabled for TTBR0 */ |
9933 | return false; | |
9934 | } | |
aef878be | 9935 | *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; |
e389be16 FA |
9936 | } |
9937 | *table |= (address >> 18) & 0x3ffc; | |
9938 | return true; | |
b2fa1797 PB |
9939 | } |
9940 | ||
37785977 EI |
9941 | /* Translate a S1 pagetable walk through S2 if needed. */ |
9942 | static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, | |
9943 | hwaddr addr, MemTxAttrs txattrs, | |
37785977 EI |
9944 | ARMMMUFaultInfo *fi) |
9945 | { | |
fee7aa46 | 9946 | if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && |
97fa9350 | 9947 | !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { |
37785977 EI |
9948 | target_ulong s2size; |
9949 | hwaddr s2pa; | |
9950 | int s2prot; | |
9951 | int ret; | |
eadb2feb PM |
9952 | ARMCacheAttrs cacheattrs = {}; |
9953 | ARMCacheAttrs *pcacheattrs = NULL; | |
9954 | ||
9955 | if (env->cp15.hcr_el2 & HCR_PTW) { | |
9956 | /* | |
9957 | * PTW means we must fault if this S1 walk touches S2 Device | |
9958 | * memory; otherwise we don't care about the attributes and can | |
9959 | * save the S2 translation the effort of computing them. | |
9960 | */ | |
9961 | pcacheattrs = &cacheattrs; | |
9962 | } | |
37785977 | 9963 | |
97fa9350 | 9964 | ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_Stage2, &s2pa, |
eadb2feb | 9965 | &txattrs, &s2prot, &s2size, fi, pcacheattrs); |
37785977 | 9966 | if (ret) { |
3b39d734 | 9967 | assert(fi->type != ARMFault_None); |
37785977 EI |
9968 | fi->s2addr = addr; |
9969 | fi->stage2 = true; | |
9970 | fi->s1ptw = true; | |
9971 | return ~0; | |
9972 | } | |
eadb2feb PM |
9973 | if (pcacheattrs && (pcacheattrs->attrs & 0xf0) == 0) { |
9974 | /* Access was to Device memory: generate Permission fault */ | |
9975 | fi->type = ARMFault_Permission; | |
9976 | fi->s2addr = addr; | |
9977 | fi->stage2 = true; | |
9978 | fi->s1ptw = true; | |
9979 | return ~0; | |
9980 | } | |
37785977 EI |
9981 | addr = s2pa; |
9982 | } | |
9983 | return addr; | |
9984 | } | |
9985 | ||
14577270 | 9986 | /* All loads done in the course of a page table walk go through here. */ |
a614e698 | 9987 | static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, |
3795a6de | 9988 | ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) |
ebca90e4 | 9989 | { |
a614e698 EI |
9990 | ARMCPU *cpu = ARM_CPU(cs); |
9991 | CPUARMState *env = &cpu->env; | |
ebca90e4 | 9992 | MemTxAttrs attrs = {}; |
3b39d734 | 9993 | MemTxResult result = MEMTX_OK; |
5ce4ff65 | 9994 | AddressSpace *as; |
3b39d734 | 9995 | uint32_t data; |
ebca90e4 PM |
9996 | |
9997 | attrs.secure = is_secure; | |
5ce4ff65 | 9998 | as = arm_addressspace(cs, attrs); |
3795a6de | 9999 | addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi); |
a614e698 EI |
10000 | if (fi->s1ptw) { |
10001 | return 0; | |
10002 | } | |
73462ddd | 10003 | if (regime_translation_big_endian(env, mmu_idx)) { |
3b39d734 | 10004 | data = address_space_ldl_be(as, addr, attrs, &result); |
73462ddd | 10005 | } else { |
3b39d734 | 10006 | data = address_space_ldl_le(as, addr, attrs, &result); |
73462ddd | 10007 | } |
3b39d734 PM |
10008 | if (result == MEMTX_OK) { |
10009 | return data; | |
10010 | } | |
10011 | fi->type = ARMFault_SyncExternalOnWalk; | |
10012 | fi->ea = arm_extabort_type(result); | |
10013 | return 0; | |
ebca90e4 PM |
10014 | } |
10015 | ||
37785977 | 10016 | static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, |
3795a6de | 10017 | ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) |
ebca90e4 | 10018 | { |
37785977 EI |
10019 | ARMCPU *cpu = ARM_CPU(cs); |
10020 | CPUARMState *env = &cpu->env; | |
ebca90e4 | 10021 | MemTxAttrs attrs = {}; |
3b39d734 | 10022 | MemTxResult result = MEMTX_OK; |
5ce4ff65 | 10023 | AddressSpace *as; |
9aea1ea3 | 10024 | uint64_t data; |
ebca90e4 PM |
10025 | |
10026 | attrs.secure = is_secure; | |
5ce4ff65 | 10027 | as = arm_addressspace(cs, attrs); |
3795a6de | 10028 | addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi); |
37785977 EI |
10029 | if (fi->s1ptw) { |
10030 | return 0; | |
10031 | } | |
73462ddd | 10032 | if (regime_translation_big_endian(env, mmu_idx)) { |
3b39d734 | 10033 | data = address_space_ldq_be(as, addr, attrs, &result); |
73462ddd | 10034 | } else { |
3b39d734 PM |
10035 | data = address_space_ldq_le(as, addr, attrs, &result); |
10036 | } | |
10037 | if (result == MEMTX_OK) { | |
10038 | return data; | |
73462ddd | 10039 | } |
3b39d734 PM |
10040 | fi->type = ARMFault_SyncExternalOnWalk; |
10041 | fi->ea = arm_extabort_type(result); | |
10042 | return 0; | |
ebca90e4 PM |
10043 | } |
10044 | ||
b7cc4e82 | 10045 | static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, |
03ae85f8 | 10046 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
b7cc4e82 | 10047 | hwaddr *phys_ptr, int *prot, |
f989983e | 10048 | target_ulong *page_size, |
e14b5a23 | 10049 | ARMMMUFaultInfo *fi) |
b5ff1b31 | 10050 | { |
2fc0cc0e | 10051 | CPUState *cs = env_cpu(env); |
f989983e | 10052 | int level = 1; |
b5ff1b31 FB |
10053 | uint32_t table; |
10054 | uint32_t desc; | |
10055 | int type; | |
10056 | int ap; | |
e389be16 | 10057 | int domain = 0; |
dd4ebc2e | 10058 | int domain_prot; |
a8170e5e | 10059 | hwaddr phys_addr; |
0480f69a | 10060 | uint32_t dacr; |
b5ff1b31 | 10061 | |
9ee6e8bb PB |
10062 | /* Pagetable walk. */ |
10063 | /* Lookup l1 descriptor. */ | |
0480f69a | 10064 | if (!get_level1_table_address(env, mmu_idx, &table, address)) { |
e389be16 | 10065 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ |
f989983e | 10066 | fi->type = ARMFault_Translation; |
e389be16 FA |
10067 | goto do_fault; |
10068 | } | |
a614e698 | 10069 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 10070 | mmu_idx, fi); |
3b39d734 PM |
10071 | if (fi->type != ARMFault_None) { |
10072 | goto do_fault; | |
10073 | } | |
9ee6e8bb | 10074 | type = (desc & 3); |
dd4ebc2e | 10075 | domain = (desc >> 5) & 0x0f; |
0480f69a PM |
10076 | if (regime_el(env, mmu_idx) == 1) { |
10077 | dacr = env->cp15.dacr_ns; | |
10078 | } else { | |
10079 | dacr = env->cp15.dacr_s; | |
10080 | } | |
10081 | domain_prot = (dacr >> (domain * 2)) & 3; | |
9ee6e8bb | 10082 | if (type == 0) { |
601d70b9 | 10083 | /* Section translation fault. */ |
f989983e | 10084 | fi->type = ARMFault_Translation; |
9ee6e8bb PB |
10085 | goto do_fault; |
10086 | } | |
f989983e PM |
10087 | if (type != 2) { |
10088 | level = 2; | |
10089 | } | |
dd4ebc2e | 10090 | if (domain_prot == 0 || domain_prot == 2) { |
f989983e | 10091 | fi->type = ARMFault_Domain; |
9ee6e8bb PB |
10092 | goto do_fault; |
10093 | } | |
10094 | if (type == 2) { | |
10095 | /* 1Mb section. */ | |
10096 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
10097 | ap = (desc >> 10) & 3; | |
d4c430a8 | 10098 | *page_size = 1024 * 1024; |
9ee6e8bb PB |
10099 | } else { |
10100 | /* Lookup l2 entry. */ | |
554b0b09 PM |
10101 | if (type == 1) { |
10102 | /* Coarse pagetable. */ | |
10103 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
10104 | } else { | |
10105 | /* Fine pagetable. */ | |
10106 | table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); | |
10107 | } | |
a614e698 | 10108 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 10109 | mmu_idx, fi); |
3b39d734 PM |
10110 | if (fi->type != ARMFault_None) { |
10111 | goto do_fault; | |
10112 | } | |
9ee6e8bb PB |
10113 | switch (desc & 3) { |
10114 | case 0: /* Page translation fault. */ | |
f989983e | 10115 | fi->type = ARMFault_Translation; |
9ee6e8bb PB |
10116 | goto do_fault; |
10117 | case 1: /* 64k page. */ | |
10118 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
10119 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
d4c430a8 | 10120 | *page_size = 0x10000; |
ce819861 | 10121 | break; |
9ee6e8bb PB |
10122 | case 2: /* 4k page. */ |
10123 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
c10f7fc3 | 10124 | ap = (desc >> (4 + ((address >> 9) & 6))) & 3; |
d4c430a8 | 10125 | *page_size = 0x1000; |
ce819861 | 10126 | break; |
fc1891c7 | 10127 | case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ |
554b0b09 | 10128 | if (type == 1) { |
fc1891c7 PM |
10129 | /* ARMv6/XScale extended small page format */ |
10130 | if (arm_feature(env, ARM_FEATURE_XSCALE) | |
10131 | || arm_feature(env, ARM_FEATURE_V6)) { | |
554b0b09 | 10132 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
fc1891c7 | 10133 | *page_size = 0x1000; |
554b0b09 | 10134 | } else { |
fc1891c7 PM |
10135 | /* UNPREDICTABLE in ARMv5; we choose to take a |
10136 | * page translation fault. | |
10137 | */ | |
f989983e | 10138 | fi->type = ARMFault_Translation; |
554b0b09 PM |
10139 | goto do_fault; |
10140 | } | |
10141 | } else { | |
10142 | phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); | |
fc1891c7 | 10143 | *page_size = 0x400; |
554b0b09 | 10144 | } |
9ee6e8bb | 10145 | ap = (desc >> 4) & 3; |
ce819861 PB |
10146 | break; |
10147 | default: | |
9ee6e8bb PB |
10148 | /* Never happens, but compiler isn't smart enough to tell. */ |
10149 | abort(); | |
ce819861 | 10150 | } |
9ee6e8bb | 10151 | } |
0fbf5238 AJ |
10152 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); |
10153 | *prot |= *prot ? PAGE_EXEC : 0; | |
10154 | if (!(*prot & (1 << access_type))) { | |
9ee6e8bb | 10155 | /* Access permission fault. */ |
f989983e | 10156 | fi->type = ARMFault_Permission; |
9ee6e8bb PB |
10157 | goto do_fault; |
10158 | } | |
10159 | *phys_ptr = phys_addr; | |
b7cc4e82 | 10160 | return false; |
9ee6e8bb | 10161 | do_fault: |
f989983e PM |
10162 | fi->domain = domain; |
10163 | fi->level = level; | |
b7cc4e82 | 10164 | return true; |
9ee6e8bb PB |
10165 | } |
10166 | ||
b7cc4e82 | 10167 | static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, |
03ae85f8 | 10168 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
b7cc4e82 | 10169 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, |
f06cf243 | 10170 | target_ulong *page_size, ARMMMUFaultInfo *fi) |
9ee6e8bb | 10171 | { |
2fc0cc0e | 10172 | CPUState *cs = env_cpu(env); |
f06cf243 | 10173 | int level = 1; |
9ee6e8bb PB |
10174 | uint32_t table; |
10175 | uint32_t desc; | |
10176 | uint32_t xn; | |
de9b05b8 | 10177 | uint32_t pxn = 0; |
9ee6e8bb PB |
10178 | int type; |
10179 | int ap; | |
de9b05b8 | 10180 | int domain = 0; |
dd4ebc2e | 10181 | int domain_prot; |
a8170e5e | 10182 | hwaddr phys_addr; |
0480f69a | 10183 | uint32_t dacr; |
8bf5b6a9 | 10184 | bool ns; |
9ee6e8bb PB |
10185 | |
10186 | /* Pagetable walk. */ | |
10187 | /* Lookup l1 descriptor. */ | |
0480f69a | 10188 | if (!get_level1_table_address(env, mmu_idx, &table, address)) { |
e389be16 | 10189 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ |
f06cf243 | 10190 | fi->type = ARMFault_Translation; |
e389be16 FA |
10191 | goto do_fault; |
10192 | } | |
a614e698 | 10193 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 10194 | mmu_idx, fi); |
3b39d734 PM |
10195 | if (fi->type != ARMFault_None) { |
10196 | goto do_fault; | |
10197 | } | |
9ee6e8bb | 10198 | type = (desc & 3); |
de9b05b8 PM |
10199 | if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { |
10200 | /* Section translation fault, or attempt to use the encoding | |
10201 | * which is Reserved on implementations without PXN. | |
10202 | */ | |
f06cf243 | 10203 | fi->type = ARMFault_Translation; |
9ee6e8bb | 10204 | goto do_fault; |
de9b05b8 PM |
10205 | } |
10206 | if ((type == 1) || !(desc & (1 << 18))) { | |
10207 | /* Page or Section. */ | |
dd4ebc2e | 10208 | domain = (desc >> 5) & 0x0f; |
9ee6e8bb | 10209 | } |
0480f69a PM |
10210 | if (regime_el(env, mmu_idx) == 1) { |
10211 | dacr = env->cp15.dacr_ns; | |
10212 | } else { | |
10213 | dacr = env->cp15.dacr_s; | |
10214 | } | |
f06cf243 PM |
10215 | if (type == 1) { |
10216 | level = 2; | |
10217 | } | |
0480f69a | 10218 | domain_prot = (dacr >> (domain * 2)) & 3; |
dd4ebc2e | 10219 | if (domain_prot == 0 || domain_prot == 2) { |
f06cf243 PM |
10220 | /* Section or Page domain fault */ |
10221 | fi->type = ARMFault_Domain; | |
9ee6e8bb PB |
10222 | goto do_fault; |
10223 | } | |
de9b05b8 | 10224 | if (type != 1) { |
9ee6e8bb PB |
10225 | if (desc & (1 << 18)) { |
10226 | /* Supersection. */ | |
10227 | phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); | |
4e42a6ca SF |
10228 | phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32; |
10229 | phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36; | |
d4c430a8 | 10230 | *page_size = 0x1000000; |
b5ff1b31 | 10231 | } else { |
9ee6e8bb PB |
10232 | /* Section. */ |
10233 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
d4c430a8 | 10234 | *page_size = 0x100000; |
b5ff1b31 | 10235 | } |
9ee6e8bb PB |
10236 | ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
10237 | xn = desc & (1 << 4); | |
de9b05b8 | 10238 | pxn = desc & 1; |
8bf5b6a9 | 10239 | ns = extract32(desc, 19, 1); |
9ee6e8bb | 10240 | } else { |
de9b05b8 PM |
10241 | if (arm_feature(env, ARM_FEATURE_PXN)) { |
10242 | pxn = (desc >> 2) & 1; | |
10243 | } | |
8bf5b6a9 | 10244 | ns = extract32(desc, 3, 1); |
9ee6e8bb PB |
10245 | /* Lookup l2 entry. */ |
10246 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
a614e698 | 10247 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 10248 | mmu_idx, fi); |
3b39d734 PM |
10249 | if (fi->type != ARMFault_None) { |
10250 | goto do_fault; | |
10251 | } | |
9ee6e8bb PB |
10252 | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
10253 | switch (desc & 3) { | |
10254 | case 0: /* Page translation fault. */ | |
f06cf243 | 10255 | fi->type = ARMFault_Translation; |
b5ff1b31 | 10256 | goto do_fault; |
9ee6e8bb PB |
10257 | case 1: /* 64k page. */ |
10258 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
10259 | xn = desc & (1 << 15); | |
d4c430a8 | 10260 | *page_size = 0x10000; |
9ee6e8bb PB |
10261 | break; |
10262 | case 2: case 3: /* 4k page. */ | |
10263 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
10264 | xn = desc & 1; | |
d4c430a8 | 10265 | *page_size = 0x1000; |
9ee6e8bb PB |
10266 | break; |
10267 | default: | |
10268 | /* Never happens, but compiler isn't smart enough to tell. */ | |
10269 | abort(); | |
b5ff1b31 | 10270 | } |
9ee6e8bb | 10271 | } |
dd4ebc2e | 10272 | if (domain_prot == 3) { |
c0034328 JR |
10273 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
10274 | } else { | |
0480f69a | 10275 | if (pxn && !regime_is_user(env, mmu_idx)) { |
de9b05b8 PM |
10276 | xn = 1; |
10277 | } | |
f06cf243 PM |
10278 | if (xn && access_type == MMU_INST_FETCH) { |
10279 | fi->type = ARMFault_Permission; | |
c0034328 | 10280 | goto do_fault; |
f06cf243 | 10281 | } |
9ee6e8bb | 10282 | |
d76951b6 AJ |
10283 | if (arm_feature(env, ARM_FEATURE_V6K) && |
10284 | (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { | |
10285 | /* The simplified model uses AP[0] as an access control bit. */ | |
10286 | if ((ap & 1) == 0) { | |
10287 | /* Access flag fault. */ | |
f06cf243 | 10288 | fi->type = ARMFault_AccessFlag; |
d76951b6 AJ |
10289 | goto do_fault; |
10290 | } | |
10291 | *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); | |
10292 | } else { | |
10293 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); | |
c0034328 | 10294 | } |
0fbf5238 AJ |
10295 | if (*prot && !xn) { |
10296 | *prot |= PAGE_EXEC; | |
10297 | } | |
10298 | if (!(*prot & (1 << access_type))) { | |
c0034328 | 10299 | /* Access permission fault. */ |
f06cf243 | 10300 | fi->type = ARMFault_Permission; |
c0034328 JR |
10301 | goto do_fault; |
10302 | } | |
3ad493fc | 10303 | } |
8bf5b6a9 PM |
10304 | if (ns) { |
10305 | /* The NS bit will (as required by the architecture) have no effect if | |
10306 | * the CPU doesn't support TZ or this is a non-secure translation | |
10307 | * regime, because the attribute will already be non-secure. | |
10308 | */ | |
10309 | attrs->secure = false; | |
10310 | } | |
9ee6e8bb | 10311 | *phys_ptr = phys_addr; |
b7cc4e82 | 10312 | return false; |
b5ff1b31 | 10313 | do_fault: |
f06cf243 PM |
10314 | fi->domain = domain; |
10315 | fi->level = level; | |
b7cc4e82 | 10316 | return true; |
b5ff1b31 FB |
10317 | } |
10318 | ||
1853d5a9 | 10319 | /* |
a0e966c9 | 10320 | * check_s2_mmu_setup |
1853d5a9 EI |
10321 | * @cpu: ARMCPU |
10322 | * @is_aa64: True if the translation regime is in AArch64 state | |
10323 | * @startlevel: Suggested starting level | |
10324 | * @inputsize: Bitsize of IPAs | |
10325 | * @stride: Page-table stride (See the ARM ARM) | |
10326 | * | |
a0e966c9 EI |
10327 | * Returns true if the suggested S2 translation parameters are OK and |
10328 | * false otherwise. | |
1853d5a9 | 10329 | */ |
a0e966c9 EI |
10330 | static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, |
10331 | int inputsize, int stride) | |
1853d5a9 | 10332 | { |
98d68ec2 EI |
10333 | const int grainsize = stride + 3; |
10334 | int startsizecheck; | |
10335 | ||
1853d5a9 EI |
10336 | /* Negative levels are never allowed. */ |
10337 | if (level < 0) { | |
10338 | return false; | |
10339 | } | |
10340 | ||
98d68ec2 EI |
10341 | startsizecheck = inputsize - ((3 - level) * stride + grainsize); |
10342 | if (startsizecheck < 1 || startsizecheck > stride + 4) { | |
10343 | return false; | |
10344 | } | |
10345 | ||
1853d5a9 | 10346 | if (is_aa64) { |
3526423e | 10347 | CPUARMState *env = &cpu->env; |
1853d5a9 EI |
10348 | unsigned int pamax = arm_pamax(cpu); |
10349 | ||
10350 | switch (stride) { | |
10351 | case 13: /* 64KB Pages. */ | |
10352 | if (level == 0 || (level == 1 && pamax <= 42)) { | |
10353 | return false; | |
10354 | } | |
10355 | break; | |
10356 | case 11: /* 16KB Pages. */ | |
10357 | if (level == 0 || (level == 1 && pamax <= 40)) { | |
10358 | return false; | |
10359 | } | |
10360 | break; | |
10361 | case 9: /* 4KB Pages. */ | |
10362 | if (level == 0 && pamax <= 42) { | |
10363 | return false; | |
10364 | } | |
10365 | break; | |
10366 | default: | |
10367 | g_assert_not_reached(); | |
10368 | } | |
3526423e EI |
10369 | |
10370 | /* Inputsize checks. */ | |
10371 | if (inputsize > pamax && | |
10372 | (arm_el_is_aa64(env, 1) || inputsize > 40)) { | |
10373 | /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ | |
10374 | return false; | |
10375 | } | |
1853d5a9 | 10376 | } else { |
1853d5a9 EI |
10377 | /* AArch32 only supports 4KB pages. Assert on that. */ |
10378 | assert(stride == 9); | |
10379 | ||
10380 | if (level == 0) { | |
10381 | return false; | |
10382 | } | |
1853d5a9 EI |
10383 | } |
10384 | return true; | |
10385 | } | |
10386 | ||
5b2d261d AB |
10387 | /* Translate from the 4-bit stage 2 representation of |
10388 | * memory attributes (without cache-allocation hints) to | |
10389 | * the 8-bit representation of the stage 1 MAIR registers | |
10390 | * (which includes allocation hints). | |
10391 | * | |
10392 | * ref: shared/translation/attrs/S2AttrDecode() | |
10393 | * .../S2ConvertAttrsHints() | |
10394 | */ | |
10395 | static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) | |
10396 | { | |
10397 | uint8_t hiattr = extract32(s2attrs, 2, 2); | |
10398 | uint8_t loattr = extract32(s2attrs, 0, 2); | |
10399 | uint8_t hihint = 0, lohint = 0; | |
10400 | ||
10401 | if (hiattr != 0) { /* normal memory */ | |
10402 | if ((env->cp15.hcr_el2 & HCR_CD) != 0) { /* cache disabled */ | |
10403 | hiattr = loattr = 1; /* non-cacheable */ | |
10404 | } else { | |
10405 | if (hiattr != 1) { /* Write-through or write-back */ | |
10406 | hihint = 3; /* RW allocate */ | |
10407 | } | |
10408 | if (loattr != 1) { /* Write-through or write-back */ | |
10409 | lohint = 3; /* RW allocate */ | |
10410 | } | |
10411 | } | |
10412 | } | |
10413 | ||
10414 | return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; | |
10415 | } | |
c47eaf9f | 10416 | #endif /* !CONFIG_USER_ONLY */ |
5b2d261d | 10417 | |
b830a5ee RH |
10418 | static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) |
10419 | { | |
10420 | if (regime_has_2_ranges(mmu_idx)) { | |
10421 | return extract64(tcr, 37, 2); | |
10422 | } else if (mmu_idx == ARMMMUIdx_Stage2) { | |
10423 | return 0; /* VTCR_EL2 */ | |
10424 | } else { | |
10425 | return extract32(tcr, 20, 1); | |
10426 | } | |
10427 | } | |
10428 | ||
10429 | static int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) | |
10430 | { | |
10431 | if (regime_has_2_ranges(mmu_idx)) { | |
10432 | return extract64(tcr, 51, 2); | |
10433 | } else if (mmu_idx == ARMMMUIdx_Stage2) { | |
10434 | return 0; /* VTCR_EL2 */ | |
10435 | } else { | |
10436 | return extract32(tcr, 29, 1); | |
10437 | } | |
10438 | } | |
10439 | ||
10440 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | |
10441 | ARMMMUIdx mmu_idx, bool data) | |
ba97be9f RH |
10442 | { |
10443 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | |
b830a5ee RH |
10444 | bool epd, hpd, using16k, using64k; |
10445 | int select, tsz, tbi; | |
ba97be9f | 10446 | |
339370b9 | 10447 | if (!regime_has_2_ranges(mmu_idx)) { |
71d18164 | 10448 | select = 0; |
ba97be9f RH |
10449 | tsz = extract32(tcr, 0, 6); |
10450 | using64k = extract32(tcr, 14, 1); | |
10451 | using16k = extract32(tcr, 15, 1); | |
97fa9350 | 10452 | if (mmu_idx == ARMMMUIdx_Stage2) { |
ba97be9f | 10453 | /* VTCR_EL2 */ |
b830a5ee | 10454 | hpd = false; |
ba97be9f | 10455 | } else { |
ba97be9f RH |
10456 | hpd = extract32(tcr, 24, 1); |
10457 | } | |
10458 | epd = false; | |
ba97be9f | 10459 | } else { |
71d18164 RH |
10460 | /* |
10461 | * Bit 55 is always between the two regions, and is canonical for | |
10462 | * determining if address tagging is enabled. | |
10463 | */ | |
10464 | select = extract64(va, 55, 1); | |
10465 | if (!select) { | |
10466 | tsz = extract32(tcr, 0, 6); | |
10467 | epd = extract32(tcr, 7, 1); | |
10468 | using64k = extract32(tcr, 14, 1); | |
10469 | using16k = extract32(tcr, 15, 1); | |
71d18164 | 10470 | hpd = extract64(tcr, 41, 1); |
71d18164 RH |
10471 | } else { |
10472 | int tg = extract32(tcr, 30, 2); | |
10473 | using16k = tg == 1; | |
10474 | using64k = tg == 3; | |
10475 | tsz = extract32(tcr, 16, 6); | |
10476 | epd = extract32(tcr, 23, 1); | |
71d18164 | 10477 | hpd = extract64(tcr, 42, 1); |
71d18164 | 10478 | } |
ba97be9f RH |
10479 | } |
10480 | tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ | |
10481 | tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ | |
10482 | ||
b830a5ee RH |
10483 | /* Present TBI as a composite with TBID. */ |
10484 | tbi = aa64_va_parameter_tbi(tcr, mmu_idx); | |
10485 | if (!data) { | |
10486 | tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); | |
10487 | } | |
10488 | tbi = (tbi >> select) & 1; | |
10489 | ||
ba97be9f RH |
10490 | return (ARMVAParameters) { |
10491 | .tsz = tsz, | |
10492 | .select = select, | |
10493 | .tbi = tbi, | |
10494 | .epd = epd, | |
10495 | .hpd = hpd, | |
10496 | .using16k = using16k, | |
10497 | .using64k = using64k, | |
10498 | }; | |
10499 | } | |
10500 | ||
c47eaf9f | 10501 | #ifndef CONFIG_USER_ONLY |
ba97be9f RH |
10502 | static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, |
10503 | ARMMMUIdx mmu_idx) | |
10504 | { | |
10505 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | |
10506 | uint32_t el = regime_el(env, mmu_idx); | |
10507 | int select, tsz; | |
10508 | bool epd, hpd; | |
10509 | ||
97fa9350 | 10510 | if (mmu_idx == ARMMMUIdx_Stage2) { |
ba97be9f RH |
10511 | /* VTCR */ |
10512 | bool sext = extract32(tcr, 4, 1); | |
10513 | bool sign = extract32(tcr, 3, 1); | |
10514 | ||
10515 | /* | |
10516 | * If the sign-extend bit is not the same as t0sz[3], the result | |
10517 | * is unpredictable. Flag this as a guest error. | |
10518 | */ | |
10519 | if (sign != sext) { | |
10520 | qemu_log_mask(LOG_GUEST_ERROR, | |
10521 | "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); | |
10522 | } | |
10523 | tsz = sextract32(tcr, 0, 4) + 8; | |
10524 | select = 0; | |
10525 | hpd = false; | |
10526 | epd = false; | |
10527 | } else if (el == 2) { | |
10528 | /* HTCR */ | |
10529 | tsz = extract32(tcr, 0, 3); | |
10530 | select = 0; | |
10531 | hpd = extract64(tcr, 24, 1); | |
10532 | epd = false; | |
10533 | } else { | |
10534 | int t0sz = extract32(tcr, 0, 3); | |
10535 | int t1sz = extract32(tcr, 16, 3); | |
10536 | ||
10537 | if (t1sz == 0) { | |
10538 | select = va > (0xffffffffu >> t0sz); | |
10539 | } else { | |
10540 | /* Note that we will detect errors later. */ | |
10541 | select = va >= ~(0xffffffffu >> t1sz); | |
10542 | } | |
10543 | if (!select) { | |
10544 | tsz = t0sz; | |
10545 | epd = extract32(tcr, 7, 1); | |
10546 | hpd = extract64(tcr, 41, 1); | |
10547 | } else { | |
10548 | tsz = t1sz; | |
10549 | epd = extract32(tcr, 23, 1); | |
10550 | hpd = extract64(tcr, 42, 1); | |
10551 | } | |
10552 | /* For aarch32, hpd0 is not enabled without t2e as well. */ | |
10553 | hpd &= extract32(tcr, 6, 1); | |
10554 | } | |
10555 | ||
10556 | return (ARMVAParameters) { | |
10557 | .tsz = tsz, | |
10558 | .select = select, | |
10559 | .epd = epd, | |
10560 | .hpd = hpd, | |
10561 | }; | |
10562 | } | |
10563 | ||
b7cc4e82 | 10564 | static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
03ae85f8 | 10565 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
b7cc4e82 | 10566 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, |
da909b2c | 10567 | target_ulong *page_size_ptr, |
5b2d261d | 10568 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) |
3dde962f | 10569 | { |
2fc0cc0e | 10570 | ARMCPU *cpu = env_archcpu(env); |
1853d5a9 | 10571 | CPUState *cs = CPU(cpu); |
3dde962f | 10572 | /* Read an LPAE long-descriptor translation table. */ |
da909b2c | 10573 | ARMFaultType fault_type = ARMFault_Translation; |
1b4093ea | 10574 | uint32_t level; |
ba97be9f | 10575 | ARMVAParameters param; |
3dde962f | 10576 | uint64_t ttbr; |
dddb5223 | 10577 | hwaddr descaddr, indexmask, indexmask_grainsize; |
3dde962f | 10578 | uint32_t tableattrs; |
36d820af | 10579 | target_ulong page_size; |
3dde962f | 10580 | uint32_t attrs; |
ba97be9f RH |
10581 | int32_t stride; |
10582 | int addrsize, inputsize; | |
0480f69a | 10583 | TCR *tcr = regime_tcr(env, mmu_idx); |
d8e052b3 | 10584 | int ap, ns, xn, pxn; |
88e8add8 | 10585 | uint32_t el = regime_el(env, mmu_idx); |
6109769a | 10586 | uint64_t descaddrmask; |
6e99f762 | 10587 | bool aarch64 = arm_el_is_aa64(env, el); |
1bafc2ba | 10588 | bool guarded = false; |
0480f69a PM |
10589 | |
10590 | /* TODO: | |
88e8add8 GB |
10591 | * This code does not handle the different format TCR for VTCR_EL2. |
10592 | * This code also does not support shareability levels. | |
10593 | * Attribute and permission bit handling should also be checked when adding | |
10594 | * support for those page table walks. | |
0480f69a | 10595 | */ |
6e99f762 | 10596 | if (aarch64) { |
ba97be9f RH |
10597 | param = aa64_va_parameters(env, address, mmu_idx, |
10598 | access_type != MMU_INST_FETCH); | |
1b4093ea | 10599 | level = 0; |
ba97be9f RH |
10600 | addrsize = 64 - 8 * param.tbi; |
10601 | inputsize = 64 - param.tsz; | |
d0a2cbce | 10602 | } else { |
ba97be9f | 10603 | param = aa32_va_parameters(env, address, mmu_idx); |
1b4093ea | 10604 | level = 1; |
97fa9350 | 10605 | addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32); |
ba97be9f | 10606 | inputsize = addrsize - param.tsz; |
2c8dd318 | 10607 | } |
3dde962f | 10608 | |
ba97be9f RH |
10609 | /* |
10610 | * We determined the region when collecting the parameters, but we | |
10611 | * have not yet validated that the address is valid for the region. | |
10612 | * Extract the top bits and verify that they all match select. | |
36d820af RH |
10613 | * |
10614 | * For aa32, if inputsize == addrsize, then we have selected the | |
10615 | * region by exclusion in aa32_va_parameters and there is no more | |
10616 | * validation to do here. | |
10617 | */ | |
10618 | if (inputsize < addrsize) { | |
10619 | target_ulong top_bits = sextract64(address, inputsize, | |
10620 | addrsize - inputsize); | |
03f27724 | 10621 | if (-top_bits != param.select) { |
36d820af RH |
10622 | /* The gap between the two regions is a Translation fault */ |
10623 | fault_type = ARMFault_Translation; | |
10624 | goto do_fault; | |
10625 | } | |
3dde962f PM |
10626 | } |
10627 | ||
ba97be9f RH |
10628 | if (param.using64k) { |
10629 | stride = 13; | |
10630 | } else if (param.using16k) { | |
10631 | stride = 11; | |
10632 | } else { | |
10633 | stride = 9; | |
10634 | } | |
10635 | ||
3dde962f PM |
10636 | /* Note that QEMU ignores shareability and cacheability attributes, |
10637 | * so we don't need to do anything with the SH, ORGN, IRGN fields | |
10638 | * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the | |
10639 | * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently | |
10640 | * implement any ASID-like capability so we can ignore it (instead | |
10641 | * we will always flush the TLB any time the ASID is changed). | |
10642 | */ | |
ba97be9f | 10643 | ttbr = regime_ttbr(env, mmu_idx, param.select); |
3dde962f | 10644 | |
0480f69a | 10645 | /* Here we should have set up all the parameters for the translation: |
6e99f762 | 10646 | * inputsize, ttbr, epd, stride, tbi |
0480f69a PM |
10647 | */ |
10648 | ||
ba97be9f | 10649 | if (param.epd) { |
88e8add8 GB |
10650 | /* Translation table walk disabled => Translation fault on TLB miss |
10651 | * Note: This is always 0 on 64-bit EL2 and EL3. | |
10652 | */ | |
3dde962f PM |
10653 | goto do_fault; |
10654 | } | |
10655 | ||
97fa9350 | 10656 | if (mmu_idx != ARMMMUIdx_Stage2) { |
1853d5a9 EI |
10657 | /* The starting level depends on the virtual address size (which can |
10658 | * be up to 48 bits) and the translation granule size. It indicates | |
10659 | * the number of strides (stride bits at a time) needed to | |
10660 | * consume the bits of the input address. In the pseudocode this is: | |
10661 | * level = 4 - RoundUp((inputsize - grainsize) / stride) | |
10662 | * where their 'inputsize' is our 'inputsize', 'grainsize' is | |
10663 | * our 'stride + 3' and 'stride' is our 'stride'. | |
10664 | * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: | |
10665 | * = 4 - (inputsize - stride - 3 + stride - 1) / stride | |
10666 | * = 4 - (inputsize - 4) / stride; | |
10667 | */ | |
10668 | level = 4 - (inputsize - 4) / stride; | |
10669 | } else { | |
10670 | /* For stage 2 translations the starting level is specified by the | |
10671 | * VTCR_EL2.SL0 field (whose interpretation depends on the page size) | |
10672 | */ | |
1b4093ea SS |
10673 | uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); |
10674 | uint32_t startlevel; | |
1853d5a9 EI |
10675 | bool ok; |
10676 | ||
6e99f762 | 10677 | if (!aarch64 || stride == 9) { |
1853d5a9 | 10678 | /* AArch32 or 4KB pages */ |
1b4093ea | 10679 | startlevel = 2 - sl0; |
1853d5a9 EI |
10680 | } else { |
10681 | /* 16KB or 64KB pages */ | |
1b4093ea | 10682 | startlevel = 3 - sl0; |
1853d5a9 EI |
10683 | } |
10684 | ||
10685 | /* Check that the starting level is valid. */ | |
6e99f762 | 10686 | ok = check_s2_mmu_setup(cpu, aarch64, startlevel, |
1b4093ea | 10687 | inputsize, stride); |
1853d5a9 | 10688 | if (!ok) { |
da909b2c | 10689 | fault_type = ARMFault_Translation; |
1853d5a9 EI |
10690 | goto do_fault; |
10691 | } | |
1b4093ea | 10692 | level = startlevel; |
1853d5a9 | 10693 | } |
3dde962f | 10694 | |
dddb5223 SS |
10695 | indexmask_grainsize = (1ULL << (stride + 3)) - 1; |
10696 | indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; | |
3dde962f PM |
10697 | |
10698 | /* Now we can extract the actual base address from the TTBR */ | |
2c8dd318 | 10699 | descaddr = extract64(ttbr, 0, 48); |
41a4bf1f PM |
10700 | /* |
10701 | * We rely on this masking to clear the RES0 bits at the bottom of the TTBR | |
10702 | * and also to mask out CnP (bit 0) which could validly be non-zero. | |
10703 | */ | |
dddb5223 | 10704 | descaddr &= ~indexmask; |
3dde962f | 10705 | |
6109769a | 10706 | /* The address field in the descriptor goes up to bit 39 for ARMv7 |
dddb5223 SS |
10707 | * but up to bit 47 for ARMv8, but we use the descaddrmask |
10708 | * up to bit 39 for AArch32, because we don't need other bits in that case | |
10709 | * to construct next descriptor address (anyway they should be all zeroes). | |
6109769a | 10710 | */ |
6e99f762 | 10711 | descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) & |
dddb5223 | 10712 | ~indexmask_grainsize; |
6109769a | 10713 | |
ebca90e4 PM |
10714 | /* Secure accesses start with the page table in secure memory and |
10715 | * can be downgraded to non-secure at any step. Non-secure accesses | |
10716 | * remain non-secure. We implement this by just ORing in the NSTable/NS | |
10717 | * bits at each step. | |
10718 | */ | |
10719 | tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); | |
3dde962f PM |
10720 | for (;;) { |
10721 | uint64_t descriptor; | |
ebca90e4 | 10722 | bool nstable; |
3dde962f | 10723 | |
dddb5223 | 10724 | descaddr |= (address >> (stride * (4 - level))) & indexmask; |
2c8dd318 | 10725 | descaddr &= ~7ULL; |
ebca90e4 | 10726 | nstable = extract32(tableattrs, 4, 1); |
3795a6de | 10727 | descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi); |
3b39d734 | 10728 | if (fi->type != ARMFault_None) { |
37785977 EI |
10729 | goto do_fault; |
10730 | } | |
10731 | ||
3dde962f PM |
10732 | if (!(descriptor & 1) || |
10733 | (!(descriptor & 2) && (level == 3))) { | |
10734 | /* Invalid, or the Reserved level 3 encoding */ | |
10735 | goto do_fault; | |
10736 | } | |
6109769a | 10737 | descaddr = descriptor & descaddrmask; |
3dde962f PM |
10738 | |
10739 | if ((descriptor & 2) && (level < 3)) { | |
037c13c5 | 10740 | /* Table entry. The top five bits are attributes which may |
3dde962f PM |
10741 | * propagate down through lower levels of the table (and |
10742 | * which are all arranged so that 0 means "no effect", so | |
10743 | * we can gather them up by ORing in the bits at each level). | |
10744 | */ | |
10745 | tableattrs |= extract64(descriptor, 59, 5); | |
10746 | level++; | |
dddb5223 | 10747 | indexmask = indexmask_grainsize; |
3dde962f PM |
10748 | continue; |
10749 | } | |
10750 | /* Block entry at level 1 or 2, or page entry at level 3. | |
10751 | * These are basically the same thing, although the number | |
10752 | * of bits we pull in from the vaddr varies. | |
10753 | */ | |
973a5434 | 10754 | page_size = (1ULL << ((stride * (4 - level)) + 3)); |
3dde962f | 10755 | descaddr |= (address & (page_size - 1)); |
6ab1a5ee | 10756 | /* Extract attributes from the descriptor */ |
d615efac IC |
10757 | attrs = extract64(descriptor, 2, 10) |
10758 | | (extract64(descriptor, 52, 12) << 10); | |
6ab1a5ee | 10759 | |
97fa9350 | 10760 | if (mmu_idx == ARMMMUIdx_Stage2) { |
6ab1a5ee EI |
10761 | /* Stage 2 table descriptors do not include any attribute fields */ |
10762 | break; | |
10763 | } | |
10764 | /* Merge in attributes from table descriptors */ | |
037c13c5 | 10765 | attrs |= nstable << 3; /* NS */ |
1bafc2ba | 10766 | guarded = extract64(descriptor, 50, 1); /* GP */ |
ba97be9f | 10767 | if (param.hpd) { |
037c13c5 RH |
10768 | /* HPD disables all the table attributes except NSTable. */ |
10769 | break; | |
10770 | } | |
10771 | attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ | |
3dde962f PM |
10772 | /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 |
10773 | * means "force PL1 access only", which means forcing AP[1] to 0. | |
10774 | */ | |
037c13c5 RH |
10775 | attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */ |
10776 | attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */ | |
3dde962f PM |
10777 | break; |
10778 | } | |
10779 | /* Here descaddr is the final physical address, and attributes | |
10780 | * are all in attrs. | |
10781 | */ | |
da909b2c | 10782 | fault_type = ARMFault_AccessFlag; |
3dde962f PM |
10783 | if ((attrs & (1 << 8)) == 0) { |
10784 | /* Access flag */ | |
10785 | goto do_fault; | |
10786 | } | |
d8e052b3 AJ |
10787 | |
10788 | ap = extract32(attrs, 4, 2); | |
d8e052b3 | 10789 | xn = extract32(attrs, 12, 1); |
d8e052b3 | 10790 | |
97fa9350 | 10791 | if (mmu_idx == ARMMMUIdx_Stage2) { |
6ab1a5ee EI |
10792 | ns = true; |
10793 | *prot = get_S2prot(env, ap, xn); | |
10794 | } else { | |
10795 | ns = extract32(attrs, 3, 1); | |
10796 | pxn = extract32(attrs, 11, 1); | |
6e99f762 | 10797 | *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); |
6ab1a5ee | 10798 | } |
d8e052b3 | 10799 | |
da909b2c | 10800 | fault_type = ARMFault_Permission; |
d8e052b3 | 10801 | if (!(*prot & (1 << access_type))) { |
3dde962f PM |
10802 | goto do_fault; |
10803 | } | |
3dde962f | 10804 | |
8bf5b6a9 PM |
10805 | if (ns) { |
10806 | /* The NS bit will (as required by the architecture) have no effect if | |
10807 | * the CPU doesn't support TZ or this is a non-secure translation | |
10808 | * regime, because the attribute will already be non-secure. | |
10809 | */ | |
10810 | txattrs->secure = false; | |
10811 | } | |
1bafc2ba RH |
10812 | /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */ |
10813 | if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { | |
10814 | txattrs->target_tlb_bit0 = true; | |
10815 | } | |
5b2d261d AB |
10816 | |
10817 | if (cacheattrs != NULL) { | |
97fa9350 | 10818 | if (mmu_idx == ARMMMUIdx_Stage2) { |
5b2d261d AB |
10819 | cacheattrs->attrs = convert_stage2_attrs(env, |
10820 | extract32(attrs, 0, 4)); | |
10821 | } else { | |
10822 | /* Index into MAIR registers for cache attributes */ | |
10823 | uint8_t attrindx = extract32(attrs, 0, 3); | |
10824 | uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; | |
10825 | assert(attrindx <= 7); | |
10826 | cacheattrs->attrs = extract64(mair, attrindx * 8, 8); | |
10827 | } | |
10828 | cacheattrs->shareability = extract32(attrs, 6, 2); | |
10829 | } | |
10830 | ||
3dde962f PM |
10831 | *phys_ptr = descaddr; |
10832 | *page_size_ptr = page_size; | |
b7cc4e82 | 10833 | return false; |
3dde962f PM |
10834 | |
10835 | do_fault: | |
da909b2c PM |
10836 | fi->type = fault_type; |
10837 | fi->level = level; | |
37785977 | 10838 | /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ |
97fa9350 | 10839 | fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_Stage2); |
b7cc4e82 | 10840 | return true; |
3dde962f PM |
10841 | } |
10842 | ||
f6bda88f PC |
10843 | static inline void get_phys_addr_pmsav7_default(CPUARMState *env, |
10844 | ARMMMUIdx mmu_idx, | |
10845 | int32_t address, int *prot) | |
10846 | { | |
3a00d560 MD |
10847 | if (!arm_feature(env, ARM_FEATURE_M)) { |
10848 | *prot = PAGE_READ | PAGE_WRITE; | |
10849 | switch (address) { | |
10850 | case 0xF0000000 ... 0xFFFFFFFF: | |
10851 | if (regime_sctlr(env, mmu_idx) & SCTLR_V) { | |
10852 | /* hivecs execing is ok */ | |
10853 | *prot |= PAGE_EXEC; | |
10854 | } | |
10855 | break; | |
10856 | case 0x00000000 ... 0x7FFFFFFF: | |
f6bda88f | 10857 | *prot |= PAGE_EXEC; |
3a00d560 MD |
10858 | break; |
10859 | } | |
10860 | } else { | |
10861 | /* Default system address map for M profile cores. | |
10862 | * The architecture specifies which regions are execute-never; | |
10863 | * at the MPU level no other checks are defined. | |
10864 | */ | |
10865 | switch (address) { | |
10866 | case 0x00000000 ... 0x1fffffff: /* ROM */ | |
10867 | case 0x20000000 ... 0x3fffffff: /* SRAM */ | |
10868 | case 0x60000000 ... 0x7fffffff: /* RAM */ | |
10869 | case 0x80000000 ... 0x9fffffff: /* RAM */ | |
10870 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
10871 | break; | |
10872 | case 0x40000000 ... 0x5fffffff: /* Peripheral */ | |
10873 | case 0xa0000000 ... 0xbfffffff: /* Device */ | |
10874 | case 0xc0000000 ... 0xdfffffff: /* Device */ | |
10875 | case 0xe0000000 ... 0xffffffff: /* System */ | |
10876 | *prot = PAGE_READ | PAGE_WRITE; | |
10877 | break; | |
10878 | default: | |
10879 | g_assert_not_reached(); | |
f6bda88f | 10880 | } |
f6bda88f | 10881 | } |
f6bda88f PC |
10882 | } |
10883 | ||
29c483a5 MD |
10884 | static bool pmsav7_use_background_region(ARMCPU *cpu, |
10885 | ARMMMUIdx mmu_idx, bool is_user) | |
10886 | { | |
10887 | /* Return true if we should use the default memory map as a | |
10888 | * "background" region if there are no hits against any MPU regions. | |
10889 | */ | |
10890 | CPUARMState *env = &cpu->env; | |
10891 | ||
10892 | if (is_user) { | |
10893 | return false; | |
10894 | } | |
10895 | ||
10896 | if (arm_feature(env, ARM_FEATURE_M)) { | |
ecf5e8ea PM |
10897 | return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] |
10898 | & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; | |
29c483a5 MD |
10899 | } else { |
10900 | return regime_sctlr(env, mmu_idx) & SCTLR_BR; | |
10901 | } | |
10902 | } | |
10903 | ||
38aaa60c PM |
10904 | static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address) |
10905 | { | |
10906 | /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */ | |
10907 | return arm_feature(env, ARM_FEATURE_M) && | |
10908 | extract32(address, 20, 12) == 0xe00; | |
10909 | } | |
10910 | ||
bf446a11 PM |
10911 | static inline bool m_is_system_region(CPUARMState *env, uint32_t address) |
10912 | { | |
10913 | /* True if address is in the M profile system region | |
10914 | * 0xe0000000 - 0xffffffff | |
10915 | */ | |
10916 | return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7; | |
10917 | } | |
10918 | ||
f6bda88f | 10919 | static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, |
03ae85f8 | 10920 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
9375ad15 | 10921 | hwaddr *phys_ptr, int *prot, |
e5e40999 | 10922 | target_ulong *page_size, |
9375ad15 | 10923 | ARMMMUFaultInfo *fi) |
f6bda88f | 10924 | { |
2fc0cc0e | 10925 | ARMCPU *cpu = env_archcpu(env); |
f6bda88f PC |
10926 | int n; |
10927 | bool is_user = regime_is_user(env, mmu_idx); | |
10928 | ||
10929 | *phys_ptr = address; | |
e5e40999 | 10930 | *page_size = TARGET_PAGE_SIZE; |
f6bda88f PC |
10931 | *prot = 0; |
10932 | ||
38aaa60c PM |
10933 | if (regime_translation_disabled(env, mmu_idx) || |
10934 | m_is_ppb_region(env, address)) { | |
10935 | /* MPU disabled or M profile PPB access: use default memory map. | |
10936 | * The other case which uses the default memory map in the | |
10937 | * v7M ARM ARM pseudocode is exception vector reads from the vector | |
10938 | * table. In QEMU those accesses are done in arm_v7m_load_vector(), | |
10939 | * which always does a direct read using address_space_ldl(), rather | |
10940 | * than going via this function, so we don't need to check that here. | |
10941 | */ | |
f6bda88f PC |
10942 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); |
10943 | } else { /* MPU enabled */ | |
10944 | for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { | |
10945 | /* region search */ | |
10946 | uint32_t base = env->pmsav7.drbar[n]; | |
10947 | uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5); | |
10948 | uint32_t rmask; | |
10949 | bool srdis = false; | |
10950 | ||
10951 | if (!(env->pmsav7.drsr[n] & 0x1)) { | |
10952 | continue; | |
10953 | } | |
10954 | ||
10955 | if (!rsize) { | |
c9f9f124 MD |
10956 | qemu_log_mask(LOG_GUEST_ERROR, |
10957 | "DRSR[%d]: Rsize field cannot be 0\n", n); | |
f6bda88f PC |
10958 | continue; |
10959 | } | |
10960 | rsize++; | |
10961 | rmask = (1ull << rsize) - 1; | |
10962 | ||
10963 | if (base & rmask) { | |
c9f9f124 MD |
10964 | qemu_log_mask(LOG_GUEST_ERROR, |
10965 | "DRBAR[%d]: 0x%" PRIx32 " misaligned " | |
10966 | "to DRSR region size, mask = 0x%" PRIx32 "\n", | |
10967 | n, base, rmask); | |
f6bda88f PC |
10968 | continue; |
10969 | } | |
10970 | ||
10971 | if (address < base || address > base + rmask) { | |
9d2b5a58 PM |
10972 | /* |
10973 | * Address not in this region. We must check whether the | |
10974 | * region covers addresses in the same page as our address. | |
10975 | * In that case we must not report a size that covers the | |
10976 | * whole page for a subsequent hit against a different MPU | |
10977 | * region or the background region, because it would result in | |
10978 | * incorrect TLB hits for subsequent accesses to addresses that | |
10979 | * are in this MPU region. | |
10980 | */ | |
10981 | if (ranges_overlap(base, rmask, | |
10982 | address & TARGET_PAGE_MASK, | |
10983 | TARGET_PAGE_SIZE)) { | |
10984 | *page_size = 1; | |
10985 | } | |
f6bda88f PC |
10986 | continue; |
10987 | } | |
10988 | ||
10989 | /* Region matched */ | |
10990 | ||
10991 | if (rsize >= 8) { /* no subregions for regions < 256 bytes */ | |
10992 | int i, snd; | |
10993 | uint32_t srdis_mask; | |
10994 | ||
10995 | rsize -= 3; /* sub region size (power of 2) */ | |
10996 | snd = ((address - base) >> rsize) & 0x7; | |
10997 | srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1); | |
10998 | ||
10999 | srdis_mask = srdis ? 0x3 : 0x0; | |
11000 | for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) { | |
11001 | /* This will check in groups of 2, 4 and then 8, whether | |
11002 | * the subregion bits are consistent. rsize is incremented | |
11003 | * back up to give the region size, considering consistent | |
11004 | * adjacent subregions as one region. Stop testing if rsize | |
11005 | * is already big enough for an entire QEMU page. | |
11006 | */ | |
11007 | int snd_rounded = snd & ~(i - 1); | |
11008 | uint32_t srdis_multi = extract32(env->pmsav7.drsr[n], | |
11009 | snd_rounded + 8, i); | |
11010 | if (srdis_mask ^ srdis_multi) { | |
11011 | break; | |
11012 | } | |
11013 | srdis_mask = (srdis_mask << i) | srdis_mask; | |
11014 | rsize++; | |
11015 | } | |
11016 | } | |
f6bda88f PC |
11017 | if (srdis) { |
11018 | continue; | |
11019 | } | |
e5e40999 PM |
11020 | if (rsize < TARGET_PAGE_BITS) { |
11021 | *page_size = 1 << rsize; | |
11022 | } | |
f6bda88f PC |
11023 | break; |
11024 | } | |
11025 | ||
11026 | if (n == -1) { /* no hits */ | |
29c483a5 | 11027 | if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { |
f6bda88f | 11028 | /* background fault */ |
9375ad15 | 11029 | fi->type = ARMFault_Background; |
f6bda88f PC |
11030 | return true; |
11031 | } | |
11032 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | |
11033 | } else { /* a MPU hit! */ | |
11034 | uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); | |
bf446a11 PM |
11035 | uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1); |
11036 | ||
11037 | if (m_is_system_region(env, address)) { | |
11038 | /* System space is always execute never */ | |
11039 | xn = 1; | |
11040 | } | |
f6bda88f PC |
11041 | |
11042 | if (is_user) { /* User mode AP bit decoding */ | |
11043 | switch (ap) { | |
11044 | case 0: | |
11045 | case 1: | |
11046 | case 5: | |
11047 | break; /* no access */ | |
11048 | case 3: | |
11049 | *prot |= PAGE_WRITE; | |
11050 | /* fall through */ | |
11051 | case 2: | |
11052 | case 6: | |
11053 | *prot |= PAGE_READ | PAGE_EXEC; | |
11054 | break; | |
8638f1ad PM |
11055 | case 7: |
11056 | /* for v7M, same as 6; for R profile a reserved value */ | |
11057 | if (arm_feature(env, ARM_FEATURE_M)) { | |
11058 | *prot |= PAGE_READ | PAGE_EXEC; | |
11059 | break; | |
11060 | } | |
11061 | /* fall through */ | |
f6bda88f PC |
11062 | default: |
11063 | qemu_log_mask(LOG_GUEST_ERROR, | |
c9f9f124 MD |
11064 | "DRACR[%d]: Bad value for AP bits: 0x%" |
11065 | PRIx32 "\n", n, ap); | |
f6bda88f PC |
11066 | } |
11067 | } else { /* Priv. mode AP bits decoding */ | |
11068 | switch (ap) { | |
11069 | case 0: | |
11070 | break; /* no access */ | |
11071 | case 1: | |
11072 | case 2: | |
11073 | case 3: | |
11074 | *prot |= PAGE_WRITE; | |
11075 | /* fall through */ | |
11076 | case 5: | |
11077 | case 6: | |
11078 | *prot |= PAGE_READ | PAGE_EXEC; | |
11079 | break; | |
8638f1ad PM |
11080 | case 7: |
11081 | /* for v7M, same as 6; for R profile a reserved value */ | |
11082 | if (arm_feature(env, ARM_FEATURE_M)) { | |
11083 | *prot |= PAGE_READ | PAGE_EXEC; | |
11084 | break; | |
11085 | } | |
11086 | /* fall through */ | |
f6bda88f PC |
11087 | default: |
11088 | qemu_log_mask(LOG_GUEST_ERROR, | |
c9f9f124 MD |
11089 | "DRACR[%d]: Bad value for AP bits: 0x%" |
11090 | PRIx32 "\n", n, ap); | |
f6bda88f PC |
11091 | } |
11092 | } | |
11093 | ||
11094 | /* execute never */ | |
bf446a11 | 11095 | if (xn) { |
f6bda88f PC |
11096 | *prot &= ~PAGE_EXEC; |
11097 | } | |
11098 | } | |
11099 | } | |
11100 | ||
9375ad15 PM |
11101 | fi->type = ARMFault_Permission; |
11102 | fi->level = 1; | |
f6bda88f PC |
11103 | return !(*prot & (1 << access_type)); |
11104 | } | |
11105 | ||
35337cc3 PM |
11106 | static bool v8m_is_sau_exempt(CPUARMState *env, |
11107 | uint32_t address, MMUAccessType access_type) | |
11108 | { | |
11109 | /* The architecture specifies that certain address ranges are | |
11110 | * exempt from v8M SAU/IDAU checks. | |
11111 | */ | |
11112 | return | |
11113 | (access_type == MMU_INST_FETCH && m_is_system_region(env, address)) || | |
11114 | (address >= 0xe0000000 && address <= 0xe0002fff) || | |
11115 | (address >= 0xe000e000 && address <= 0xe000efff) || | |
11116 | (address >= 0xe002e000 && address <= 0xe002efff) || | |
11117 | (address >= 0xe0040000 && address <= 0xe0041fff) || | |
11118 | (address >= 0xe00ff000 && address <= 0xe00fffff); | |
11119 | } | |
11120 | ||
787a7e76 | 11121 | void v8m_security_lookup(CPUARMState *env, uint32_t address, |
35337cc3 PM |
11122 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
11123 | V8M_SAttributes *sattrs) | |
11124 | { | |
11125 | /* Look up the security attributes for this address. Compare the | |
11126 | * pseudocode SecurityCheck() function. | |
11127 | * We assume the caller has zero-initialized *sattrs. | |
11128 | */ | |
2fc0cc0e | 11129 | ARMCPU *cpu = env_archcpu(env); |
35337cc3 | 11130 | int r; |
181962fd PM |
11131 | bool idau_exempt = false, idau_ns = true, idau_nsc = true; |
11132 | int idau_region = IREGION_NOTVALID; | |
72042435 PM |
11133 | uint32_t addr_page_base = address & TARGET_PAGE_MASK; |
11134 | uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); | |
35337cc3 | 11135 | |
181962fd PM |
11136 | if (cpu->idau) { |
11137 | IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau); | |
11138 | IDAUInterface *ii = IDAU_INTERFACE(cpu->idau); | |
11139 | ||
11140 | iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns, | |
11141 | &idau_nsc); | |
11142 | } | |
35337cc3 PM |
11143 | |
11144 | if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) { | |
11145 | /* 0xf0000000..0xffffffff is always S for insn fetches */ | |
11146 | return; | |
11147 | } | |
11148 | ||
181962fd | 11149 | if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) { |
35337cc3 PM |
11150 | sattrs->ns = !regime_is_secure(env, mmu_idx); |
11151 | return; | |
11152 | } | |
11153 | ||
181962fd PM |
11154 | if (idau_region != IREGION_NOTVALID) { |
11155 | sattrs->irvalid = true; | |
11156 | sattrs->iregion = idau_region; | |
11157 | } | |
11158 | ||
35337cc3 PM |
11159 | switch (env->sau.ctrl & 3) { |
11160 | case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */ | |
11161 | break; | |
11162 | case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */ | |
11163 | sattrs->ns = true; | |
11164 | break; | |
11165 | default: /* SAU.ENABLE == 1 */ | |
11166 | for (r = 0; r < cpu->sau_sregion; r++) { | |
11167 | if (env->sau.rlar[r] & 1) { | |
11168 | uint32_t base = env->sau.rbar[r] & ~0x1f; | |
11169 | uint32_t limit = env->sau.rlar[r] | 0x1f; | |
11170 | ||
11171 | if (base <= address && limit >= address) { | |
72042435 PM |
11172 | if (base > addr_page_base || limit < addr_page_limit) { |
11173 | sattrs->subpage = true; | |
11174 | } | |
35337cc3 PM |
11175 | if (sattrs->srvalid) { |
11176 | /* If we hit in more than one region then we must report | |
11177 | * as Secure, not NS-Callable, with no valid region | |
11178 | * number info. | |
11179 | */ | |
11180 | sattrs->ns = false; | |
11181 | sattrs->nsc = false; | |
11182 | sattrs->sregion = 0; | |
11183 | sattrs->srvalid = false; | |
11184 | break; | |
11185 | } else { | |
11186 | if (env->sau.rlar[r] & 2) { | |
11187 | sattrs->nsc = true; | |
11188 | } else { | |
11189 | sattrs->ns = true; | |
11190 | } | |
11191 | sattrs->srvalid = true; | |
11192 | sattrs->sregion = r; | |
11193 | } | |
9d2b5a58 PM |
11194 | } else { |
11195 | /* | |
11196 | * Address not in this region. We must check whether the | |
11197 | * region covers addresses in the same page as our address. | |
11198 | * In that case we must not report a size that covers the | |
11199 | * whole page for a subsequent hit against a different MPU | |
11200 | * region or the background region, because it would result | |
11201 | * in incorrect TLB hits for subsequent accesses to | |
11202 | * addresses that are in this MPU region. | |
11203 | */ | |
11204 | if (limit >= base && | |
11205 | ranges_overlap(base, limit - base + 1, | |
11206 | addr_page_base, | |
11207 | TARGET_PAGE_SIZE)) { | |
11208 | sattrs->subpage = true; | |
11209 | } | |
35337cc3 PM |
11210 | } |
11211 | } | |
11212 | } | |
7e3f1223 TR |
11213 | break; |
11214 | } | |
35337cc3 | 11215 | |
7e3f1223 TR |
11216 | /* |
11217 | * The IDAU will override the SAU lookup results if it specifies | |
11218 | * higher security than the SAU does. | |
11219 | */ | |
11220 | if (!idau_ns) { | |
11221 | if (sattrs->ns || (!idau_nsc && sattrs->nsc)) { | |
11222 | sattrs->ns = false; | |
11223 | sattrs->nsc = idau_nsc; | |
181962fd | 11224 | } |
35337cc3 PM |
11225 | } |
11226 | } | |
11227 | ||
787a7e76 | 11228 | bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, |
54317c0f PM |
11229 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
11230 | hwaddr *phys_ptr, MemTxAttrs *txattrs, | |
72042435 PM |
11231 | int *prot, bool *is_subpage, |
11232 | ARMMMUFaultInfo *fi, uint32_t *mregion) | |
54317c0f PM |
11233 | { |
11234 | /* Perform a PMSAv8 MPU lookup (without also doing the SAU check | |
11235 | * that a full phys-to-virt translation does). | |
11236 | * mregion is (if not NULL) set to the region number which matched, | |
11237 | * or -1 if no region number is returned (MPU off, address did not | |
11238 | * hit a region, address hit in multiple regions). | |
72042435 PM |
11239 | * We set is_subpage to true if the region hit doesn't cover the |
11240 | * entire TARGET_PAGE the address is within. | |
54317c0f | 11241 | */ |
2fc0cc0e | 11242 | ARMCPU *cpu = env_archcpu(env); |
504e3cc3 | 11243 | bool is_user = regime_is_user(env, mmu_idx); |
62c58ee0 | 11244 | uint32_t secure = regime_is_secure(env, mmu_idx); |
504e3cc3 PM |
11245 | int n; |
11246 | int matchregion = -1; | |
11247 | bool hit = false; | |
72042435 PM |
11248 | uint32_t addr_page_base = address & TARGET_PAGE_MASK; |
11249 | uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); | |
504e3cc3 | 11250 | |
72042435 | 11251 | *is_subpage = false; |
504e3cc3 PM |
11252 | *phys_ptr = address; |
11253 | *prot = 0; | |
54317c0f PM |
11254 | if (mregion) { |
11255 | *mregion = -1; | |
35337cc3 PM |
11256 | } |
11257 | ||
504e3cc3 PM |
11258 | /* Unlike the ARM ARM pseudocode, we don't need to check whether this |
11259 | * was an exception vector read from the vector table (which is always | |
11260 | * done using the default system address map), because those accesses | |
11261 | * are done in arm_v7m_load_vector(), which always does a direct | |
11262 | * read using address_space_ldl(), rather than going via this function. | |
11263 | */ | |
11264 | if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ | |
11265 | hit = true; | |
11266 | } else if (m_is_ppb_region(env, address)) { | |
11267 | hit = true; | |
504e3cc3 | 11268 | } else { |
cff21316 PM |
11269 | if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) { |
11270 | hit = true; | |
11271 | } | |
11272 | ||
504e3cc3 PM |
11273 | for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { |
11274 | /* region search */ | |
11275 | /* Note that the base address is bits [31:5] from the register | |
11276 | * with bits [4:0] all zeroes, but the limit address is bits | |
11277 | * [31:5] from the register with bits [4:0] all ones. | |
11278 | */ | |
62c58ee0 PM |
11279 | uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f; |
11280 | uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f; | |
504e3cc3 | 11281 | |
62c58ee0 | 11282 | if (!(env->pmsav8.rlar[secure][n] & 0x1)) { |
504e3cc3 PM |
11283 | /* Region disabled */ |
11284 | continue; | |
11285 | } | |
11286 | ||
11287 | if (address < base || address > limit) { | |
9d2b5a58 PM |
11288 | /* |
11289 | * Address not in this region. We must check whether the | |
11290 | * region covers addresses in the same page as our address. | |
11291 | * In that case we must not report a size that covers the | |
11292 | * whole page for a subsequent hit against a different MPU | |
11293 | * region or the background region, because it would result in | |
11294 | * incorrect TLB hits for subsequent accesses to addresses that | |
11295 | * are in this MPU region. | |
11296 | */ | |
11297 | if (limit >= base && | |
11298 | ranges_overlap(base, limit - base + 1, | |
11299 | addr_page_base, | |
11300 | TARGET_PAGE_SIZE)) { | |
11301 | *is_subpage = true; | |
11302 | } | |
504e3cc3 PM |
11303 | continue; |
11304 | } | |
11305 | ||
72042435 PM |
11306 | if (base > addr_page_base || limit < addr_page_limit) { |
11307 | *is_subpage = true; | |
11308 | } | |
11309 | ||
cff21316 | 11310 | if (matchregion != -1) { |
504e3cc3 PM |
11311 | /* Multiple regions match -- always a failure (unlike |
11312 | * PMSAv7 where highest-numbered-region wins) | |
11313 | */ | |
3f551b5b PM |
11314 | fi->type = ARMFault_Permission; |
11315 | fi->level = 1; | |
504e3cc3 PM |
11316 | return true; |
11317 | } | |
11318 | ||
11319 | matchregion = n; | |
11320 | hit = true; | |
504e3cc3 PM |
11321 | } |
11322 | } | |
11323 | ||
11324 | if (!hit) { | |
11325 | /* background fault */ | |
3f551b5b | 11326 | fi->type = ARMFault_Background; |
504e3cc3 PM |
11327 | return true; |
11328 | } | |
11329 | ||
11330 | if (matchregion == -1) { | |
11331 | /* hit using the background region */ | |
11332 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | |
11333 | } else { | |
62c58ee0 PM |
11334 | uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2); |
11335 | uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1); | |
504e3cc3 PM |
11336 | |
11337 | if (m_is_system_region(env, address)) { | |
11338 | /* System space is always execute never */ | |
11339 | xn = 1; | |
11340 | } | |
11341 | ||
11342 | *prot = simple_ap_to_rw_prot(env, mmu_idx, ap); | |
11343 | if (*prot && !xn) { | |
11344 | *prot |= PAGE_EXEC; | |
11345 | } | |
11346 | /* We don't need to look the attribute up in the MAIR0/MAIR1 | |
11347 | * registers because that only tells us about cacheability. | |
11348 | */ | |
54317c0f PM |
11349 | if (mregion) { |
11350 | *mregion = matchregion; | |
11351 | } | |
504e3cc3 PM |
11352 | } |
11353 | ||
3f551b5b PM |
11354 | fi->type = ARMFault_Permission; |
11355 | fi->level = 1; | |
504e3cc3 PM |
11356 | return !(*prot & (1 << access_type)); |
11357 | } | |
11358 | ||
54317c0f PM |
11359 | |
11360 | static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, | |
11361 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
11362 | hwaddr *phys_ptr, MemTxAttrs *txattrs, | |
72042435 PM |
11363 | int *prot, target_ulong *page_size, |
11364 | ARMMMUFaultInfo *fi) | |
54317c0f PM |
11365 | { |
11366 | uint32_t secure = regime_is_secure(env, mmu_idx); | |
11367 | V8M_SAttributes sattrs = {}; | |
72042435 PM |
11368 | bool ret; |
11369 | bool mpu_is_subpage; | |
54317c0f PM |
11370 | |
11371 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
11372 | v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs); | |
11373 | if (access_type == MMU_INST_FETCH) { | |
11374 | /* Instruction fetches always use the MMU bank and the | |
11375 | * transaction attribute determined by the fetch address, | |
11376 | * regardless of CPU state. This is painful for QEMU | |
11377 | * to handle, because it would mean we need to encode | |
11378 | * into the mmu_idx not just the (user, negpri) information | |
11379 | * for the current security state but also that for the | |
11380 | * other security state, which would balloon the number | |
11381 | * of mmu_idx values needed alarmingly. | |
11382 | * Fortunately we can avoid this because it's not actually | |
11383 | * possible to arbitrarily execute code from memory with | |
11384 | * the wrong security attribute: it will always generate | |
11385 | * an exception of some kind or another, apart from the | |
11386 | * special case of an NS CPU executing an SG instruction | |
11387 | * in S&NSC memory. So we always just fail the translation | |
11388 | * here and sort things out in the exception handler | |
11389 | * (including possibly emulating an SG instruction). | |
11390 | */ | |
11391 | if (sattrs.ns != !secure) { | |
3f551b5b PM |
11392 | if (sattrs.nsc) { |
11393 | fi->type = ARMFault_QEMU_NSCExec; | |
11394 | } else { | |
11395 | fi->type = ARMFault_QEMU_SFault; | |
11396 | } | |
72042435 | 11397 | *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; |
54317c0f PM |
11398 | *phys_ptr = address; |
11399 | *prot = 0; | |
11400 | return true; | |
11401 | } | |
11402 | } else { | |
11403 | /* For data accesses we always use the MMU bank indicated | |
11404 | * by the current CPU state, but the security attributes | |
11405 | * might downgrade a secure access to nonsecure. | |
11406 | */ | |
11407 | if (sattrs.ns) { | |
11408 | txattrs->secure = false; | |
11409 | } else if (!secure) { | |
11410 | /* NS access to S memory must fault. | |
11411 | * Architecturally we should first check whether the | |
11412 | * MPU information for this address indicates that we | |
11413 | * are doing an unaligned access to Device memory, which | |
11414 | * should generate a UsageFault instead. QEMU does not | |
11415 | * currently check for that kind of unaligned access though. | |
11416 | * If we added it we would need to do so as a special case | |
11417 | * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). | |
11418 | */ | |
3f551b5b | 11419 | fi->type = ARMFault_QEMU_SFault; |
72042435 | 11420 | *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; |
54317c0f PM |
11421 | *phys_ptr = address; |
11422 | *prot = 0; | |
11423 | return true; | |
11424 | } | |
11425 | } | |
11426 | } | |
11427 | ||
72042435 PM |
11428 | ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, |
11429 | txattrs, prot, &mpu_is_subpage, fi, NULL); | |
72042435 PM |
11430 | *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; |
11431 | return ret; | |
54317c0f PM |
11432 | } |
11433 | ||
13689d43 | 11434 | static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, |
03ae85f8 | 11435 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
53a4e5c5 PM |
11436 | hwaddr *phys_ptr, int *prot, |
11437 | ARMMMUFaultInfo *fi) | |
9ee6e8bb PB |
11438 | { |
11439 | int n; | |
11440 | uint32_t mask; | |
11441 | uint32_t base; | |
0480f69a | 11442 | bool is_user = regime_is_user(env, mmu_idx); |
9ee6e8bb | 11443 | |
3279adb9 PM |
11444 | if (regime_translation_disabled(env, mmu_idx)) { |
11445 | /* MPU disabled. */ | |
11446 | *phys_ptr = address; | |
11447 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
11448 | return false; | |
11449 | } | |
11450 | ||
9ee6e8bb PB |
11451 | *phys_ptr = address; |
11452 | for (n = 7; n >= 0; n--) { | |
554b0b09 | 11453 | base = env->cp15.c6_region[n]; |
87c3d486 | 11454 | if ((base & 1) == 0) { |
554b0b09 | 11455 | continue; |
87c3d486 | 11456 | } |
554b0b09 PM |
11457 | mask = 1 << ((base >> 1) & 0x1f); |
11458 | /* Keep this shift separate from the above to avoid an | |
11459 | (undefined) << 32. */ | |
11460 | mask = (mask << 1) - 1; | |
87c3d486 | 11461 | if (((base ^ address) & ~mask) == 0) { |
554b0b09 | 11462 | break; |
87c3d486 | 11463 | } |
9ee6e8bb | 11464 | } |
87c3d486 | 11465 | if (n < 0) { |
53a4e5c5 | 11466 | fi->type = ARMFault_Background; |
b7cc4e82 | 11467 | return true; |
87c3d486 | 11468 | } |
9ee6e8bb | 11469 | |
03ae85f8 | 11470 | if (access_type == MMU_INST_FETCH) { |
7e09797c | 11471 | mask = env->cp15.pmsav5_insn_ap; |
9ee6e8bb | 11472 | } else { |
7e09797c | 11473 | mask = env->cp15.pmsav5_data_ap; |
9ee6e8bb PB |
11474 | } |
11475 | mask = (mask >> (n * 4)) & 0xf; | |
11476 | switch (mask) { | |
11477 | case 0: | |
53a4e5c5 PM |
11478 | fi->type = ARMFault_Permission; |
11479 | fi->level = 1; | |
b7cc4e82 | 11480 | return true; |
9ee6e8bb | 11481 | case 1: |
87c3d486 | 11482 | if (is_user) { |
53a4e5c5 PM |
11483 | fi->type = ARMFault_Permission; |
11484 | fi->level = 1; | |
b7cc4e82 | 11485 | return true; |
87c3d486 | 11486 | } |
554b0b09 PM |
11487 | *prot = PAGE_READ | PAGE_WRITE; |
11488 | break; | |
9ee6e8bb | 11489 | case 2: |
554b0b09 | 11490 | *prot = PAGE_READ; |
87c3d486 | 11491 | if (!is_user) { |
554b0b09 | 11492 | *prot |= PAGE_WRITE; |
87c3d486 | 11493 | } |
554b0b09 | 11494 | break; |
9ee6e8bb | 11495 | case 3: |
554b0b09 PM |
11496 | *prot = PAGE_READ | PAGE_WRITE; |
11497 | break; | |
9ee6e8bb | 11498 | case 5: |
87c3d486 | 11499 | if (is_user) { |
53a4e5c5 PM |
11500 | fi->type = ARMFault_Permission; |
11501 | fi->level = 1; | |
b7cc4e82 | 11502 | return true; |
87c3d486 | 11503 | } |
554b0b09 PM |
11504 | *prot = PAGE_READ; |
11505 | break; | |
9ee6e8bb | 11506 | case 6: |
554b0b09 PM |
11507 | *prot = PAGE_READ; |
11508 | break; | |
9ee6e8bb | 11509 | default: |
554b0b09 | 11510 | /* Bad permission. */ |
53a4e5c5 PM |
11511 | fi->type = ARMFault_Permission; |
11512 | fi->level = 1; | |
b7cc4e82 | 11513 | return true; |
9ee6e8bb | 11514 | } |
3ad493fc | 11515 | *prot |= PAGE_EXEC; |
b7cc4e82 | 11516 | return false; |
9ee6e8bb PB |
11517 | } |
11518 | ||
5b2d261d AB |
11519 | /* Combine either inner or outer cacheability attributes for normal |
11520 | * memory, according to table D4-42 and pseudocode procedure | |
11521 | * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). | |
11522 | * | |
11523 | * NB: only stage 1 includes allocation hints (RW bits), leading to | |
11524 | * some asymmetry. | |
11525 | */ | |
11526 | static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2) | |
11527 | { | |
11528 | if (s1 == 4 || s2 == 4) { | |
11529 | /* non-cacheable has precedence */ | |
11530 | return 4; | |
11531 | } else if (extract32(s1, 2, 2) == 0 || extract32(s1, 2, 2) == 2) { | |
11532 | /* stage 1 write-through takes precedence */ | |
11533 | return s1; | |
11534 | } else if (extract32(s2, 2, 2) == 2) { | |
11535 | /* stage 2 write-through takes precedence, but the allocation hint | |
11536 | * is still taken from stage 1 | |
11537 | */ | |
11538 | return (2 << 2) | extract32(s1, 0, 2); | |
11539 | } else { /* write-back */ | |
11540 | return s1; | |
11541 | } | |
11542 | } | |
11543 | ||
11544 | /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 | |
11545 | * and CombineS1S2Desc() | |
11546 | * | |
11547 | * @s1: Attributes from stage 1 walk | |
11548 | * @s2: Attributes from stage 2 walk | |
11549 | */ | |
11550 | static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) | |
11551 | { | |
11552 | uint8_t s1lo = extract32(s1.attrs, 0, 4), s2lo = extract32(s2.attrs, 0, 4); | |
11553 | uint8_t s1hi = extract32(s1.attrs, 4, 4), s2hi = extract32(s2.attrs, 4, 4); | |
11554 | ARMCacheAttrs ret; | |
11555 | ||
11556 | /* Combine shareability attributes (table D4-43) */ | |
11557 | if (s1.shareability == 2 || s2.shareability == 2) { | |
11558 | /* if either are outer-shareable, the result is outer-shareable */ | |
11559 | ret.shareability = 2; | |
11560 | } else if (s1.shareability == 3 || s2.shareability == 3) { | |
11561 | /* if either are inner-shareable, the result is inner-shareable */ | |
11562 | ret.shareability = 3; | |
11563 | } else { | |
11564 | /* both non-shareable */ | |
11565 | ret.shareability = 0; | |
11566 | } | |
11567 | ||
11568 | /* Combine memory type and cacheability attributes */ | |
11569 | if (s1hi == 0 || s2hi == 0) { | |
11570 | /* Device has precedence over normal */ | |
11571 | if (s1lo == 0 || s2lo == 0) { | |
11572 | /* nGnRnE has precedence over anything */ | |
11573 | ret.attrs = 0; | |
11574 | } else if (s1lo == 4 || s2lo == 4) { | |
11575 | /* non-Reordering has precedence over Reordering */ | |
11576 | ret.attrs = 4; /* nGnRE */ | |
11577 | } else if (s1lo == 8 || s2lo == 8) { | |
11578 | /* non-Gathering has precedence over Gathering */ | |
11579 | ret.attrs = 8; /* nGRE */ | |
11580 | } else { | |
11581 | ret.attrs = 0xc; /* GRE */ | |
11582 | } | |
11583 | ||
11584 | /* Any location for which the resultant memory type is any | |
11585 | * type of Device memory is always treated as Outer Shareable. | |
11586 | */ | |
11587 | ret.shareability = 2; | |
11588 | } else { /* Normal memory */ | |
11589 | /* Outer/inner cacheability combine independently */ | |
11590 | ret.attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4 | |
11591 | | combine_cacheattr_nibble(s1lo, s2lo); | |
11592 | ||
11593 | if (ret.attrs == 0x44) { | |
11594 | /* Any location for which the resultant memory type is Normal | |
11595 | * Inner Non-cacheable, Outer Non-cacheable is always treated | |
11596 | * as Outer Shareable. | |
11597 | */ | |
11598 | ret.shareability = 2; | |
11599 | } | |
11600 | } | |
11601 | ||
11602 | return ret; | |
11603 | } | |
11604 | ||
11605 | ||
702a9357 PM |
11606 | /* get_phys_addr - get the physical address for this virtual address |
11607 | * | |
11608 | * Find the physical address corresponding to the given virtual address, | |
11609 | * by doing a translation table walk on MMU based systems or using the | |
11610 | * MPU state on MPU based systems. | |
11611 | * | |
b7cc4e82 PC |
11612 | * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, |
11613 | * prot and page_size may not be filled in, and the populated fsr value provides | |
702a9357 PM |
11614 | * information on why the translation aborted, in the format of a |
11615 | * DFSR/IFSR fault register, with the following caveats: | |
11616 | * * we honour the short vs long DFSR format differences. | |
11617 | * * the WnR bit is never set (the caller must do this). | |
f6bda88f | 11618 | * * for PSMAv5 based systems we don't bother to return a full FSR format |
702a9357 PM |
11619 | * value. |
11620 | * | |
11621 | * @env: CPUARMState | |
11622 | * @address: virtual address to get physical address for | |
11623 | * @access_type: 0 for read, 1 for write, 2 for execute | |
d3649702 | 11624 | * @mmu_idx: MMU index indicating required translation regime |
702a9357 | 11625 | * @phys_ptr: set to the physical address corresponding to the virtual address |
8bf5b6a9 | 11626 | * @attrs: set to the memory transaction attributes to use |
702a9357 PM |
11627 | * @prot: set to the permissions for the page containing phys_ptr |
11628 | * @page_size: set to the size of the page containing phys_ptr | |
5b2d261d AB |
11629 | * @fi: set to fault info if the translation fails |
11630 | * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes | |
702a9357 | 11631 | */ |
ebae861f PMD |
11632 | bool get_phys_addr(CPUARMState *env, target_ulong address, |
11633 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
11634 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, | |
11635 | target_ulong *page_size, | |
11636 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) | |
9ee6e8bb | 11637 | { |
452ef8cb RH |
11638 | if (mmu_idx == ARMMMUIdx_E10_0 || |
11639 | mmu_idx == ARMMMUIdx_E10_1 || | |
11640 | mmu_idx == ARMMMUIdx_E10_1_PAN) { | |
9b539263 EI |
11641 | /* Call ourselves recursively to do the stage 1 and then stage 2 |
11642 | * translations. | |
0480f69a | 11643 | */ |
9b539263 EI |
11644 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
11645 | hwaddr ipa; | |
11646 | int s2_prot; | |
11647 | int ret; | |
5b2d261d | 11648 | ARMCacheAttrs cacheattrs2 = {}; |
9b539263 EI |
11649 | |
11650 | ret = get_phys_addr(env, address, access_type, | |
8bd5c820 | 11651 | stage_1_mmu_idx(mmu_idx), &ipa, attrs, |
bc52bfeb | 11652 | prot, page_size, fi, cacheattrs); |
9b539263 EI |
11653 | |
11654 | /* If S1 fails or S2 is disabled, return early. */ | |
97fa9350 | 11655 | if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) { |
9b539263 EI |
11656 | *phys_ptr = ipa; |
11657 | return ret; | |
11658 | } | |
11659 | ||
11660 | /* S1 is done. Now do S2 translation. */ | |
97fa9350 | 11661 | ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_Stage2, |
9b539263 | 11662 | phys_ptr, attrs, &s2_prot, |
da909b2c | 11663 | page_size, fi, |
5b2d261d | 11664 | cacheattrs != NULL ? &cacheattrs2 : NULL); |
9b539263 EI |
11665 | fi->s2addr = ipa; |
11666 | /* Combine the S1 and S2 perms. */ | |
11667 | *prot &= s2_prot; | |
5b2d261d AB |
11668 | |
11669 | /* Combine the S1 and S2 cache attributes, if needed */ | |
11670 | if (!ret && cacheattrs != NULL) { | |
9d1bab33 PM |
11671 | if (env->cp15.hcr_el2 & HCR_DC) { |
11672 | /* | |
11673 | * HCR.DC forces the first stage attributes to | |
11674 | * Normal Non-Shareable, | |
11675 | * Inner Write-Back Read-Allocate Write-Allocate, | |
11676 | * Outer Write-Back Read-Allocate Write-Allocate. | |
11677 | */ | |
11678 | cacheattrs->attrs = 0xff; | |
11679 | cacheattrs->shareability = 0; | |
11680 | } | |
5b2d261d AB |
11681 | *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2); |
11682 | } | |
11683 | ||
9b539263 EI |
11684 | return ret; |
11685 | } else { | |
11686 | /* | |
11687 | * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. | |
11688 | */ | |
8bd5c820 | 11689 | mmu_idx = stage_1_mmu_idx(mmu_idx); |
9b539263 | 11690 | } |
0480f69a | 11691 | } |
d3649702 | 11692 | |
8bf5b6a9 PM |
11693 | /* The page table entries may downgrade secure to non-secure, but |
11694 | * cannot upgrade an non-secure translation regime's attributes | |
11695 | * to secure. | |
11696 | */ | |
11697 | attrs->secure = regime_is_secure(env, mmu_idx); | |
0995bf8c | 11698 | attrs->user = regime_is_user(env, mmu_idx); |
8bf5b6a9 | 11699 | |
0480f69a PM |
11700 | /* Fast Context Switch Extension. This doesn't exist at all in v8. |
11701 | * In v7 and earlier it affects all stage 1 translations. | |
11702 | */ | |
97fa9350 | 11703 | if (address < 0x02000000 && mmu_idx != ARMMMUIdx_Stage2 |
0480f69a PM |
11704 | && !arm_feature(env, ARM_FEATURE_V8)) { |
11705 | if (regime_el(env, mmu_idx) == 3) { | |
11706 | address += env->cp15.fcseidr_s; | |
11707 | } else { | |
11708 | address += env->cp15.fcseidr_ns; | |
11709 | } | |
54bf36ed | 11710 | } |
9ee6e8bb | 11711 | |
3279adb9 | 11712 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
c9f9f124 | 11713 | bool ret; |
f6bda88f | 11714 | *page_size = TARGET_PAGE_SIZE; |
3279adb9 | 11715 | |
504e3cc3 PM |
11716 | if (arm_feature(env, ARM_FEATURE_V8)) { |
11717 | /* PMSAv8 */ | |
11718 | ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, | |
72042435 | 11719 | phys_ptr, attrs, prot, page_size, fi); |
504e3cc3 | 11720 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
3279adb9 PM |
11721 | /* PMSAv7 */ |
11722 | ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, | |
e5e40999 | 11723 | phys_ptr, prot, page_size, fi); |
3279adb9 PM |
11724 | } else { |
11725 | /* Pre-v7 MPU */ | |
11726 | ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, | |
53a4e5c5 | 11727 | phys_ptr, prot, fi); |
3279adb9 PM |
11728 | } |
11729 | qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 | |
c9f9f124 | 11730 | " mmu_idx %u -> %s (prot %c%c%c)\n", |
709e4407 PM |
11731 | access_type == MMU_DATA_LOAD ? "reading" : |
11732 | (access_type == MMU_DATA_STORE ? "writing" : "execute"), | |
c9f9f124 MD |
11733 | (uint32_t)address, mmu_idx, |
11734 | ret ? "Miss" : "Hit", | |
11735 | *prot & PAGE_READ ? 'r' : '-', | |
11736 | *prot & PAGE_WRITE ? 'w' : '-', | |
11737 | *prot & PAGE_EXEC ? 'x' : '-'); | |
11738 | ||
11739 | return ret; | |
f6bda88f PC |
11740 | } |
11741 | ||
3279adb9 PM |
11742 | /* Definitely a real MMU, not an MPU */ |
11743 | ||
0480f69a | 11744 | if (regime_translation_disabled(env, mmu_idx)) { |
3279adb9 | 11745 | /* MMU disabled. */ |
9ee6e8bb | 11746 | *phys_ptr = address; |
3ad493fc | 11747 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
d4c430a8 | 11748 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb | 11749 | return 0; |
0480f69a PM |
11750 | } |
11751 | ||
0480f69a | 11752 | if (regime_using_lpae_format(env, mmu_idx)) { |
bc52bfeb PM |
11753 | return get_phys_addr_lpae(env, address, access_type, mmu_idx, |
11754 | phys_ptr, attrs, prot, page_size, | |
11755 | fi, cacheattrs); | |
0480f69a | 11756 | } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { |
bc52bfeb PM |
11757 | return get_phys_addr_v6(env, address, access_type, mmu_idx, |
11758 | phys_ptr, attrs, prot, page_size, fi); | |
9ee6e8bb | 11759 | } else { |
bc52bfeb | 11760 | return get_phys_addr_v5(env, address, access_type, mmu_idx, |
f989983e | 11761 | phys_ptr, prot, page_size, fi); |
9ee6e8bb PB |
11762 | } |
11763 | } | |
11764 | ||
0faea0c7 PM |
11765 | hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, |
11766 | MemTxAttrs *attrs) | |
b5ff1b31 | 11767 | { |
00b941e5 | 11768 | ARMCPU *cpu = ARM_CPU(cs); |
d3649702 | 11769 | CPUARMState *env = &cpu->env; |
a8170e5e | 11770 | hwaddr phys_addr; |
d4c430a8 | 11771 | target_ulong page_size; |
b5ff1b31 | 11772 | int prot; |
b7cc4e82 | 11773 | bool ret; |
e14b5a23 | 11774 | ARMMMUFaultInfo fi = {}; |
50494a27 | 11775 | ARMMMUIdx mmu_idx = arm_mmu_idx(env); |
b5ff1b31 | 11776 | |
0faea0c7 PM |
11777 | *attrs = (MemTxAttrs) {}; |
11778 | ||
8bd5c820 | 11779 | ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr, |
bc52bfeb | 11780 | attrs, &prot, &page_size, &fi, NULL); |
b5ff1b31 | 11781 | |
b7cc4e82 | 11782 | if (ret) { |
b5ff1b31 | 11783 | return -1; |
00b941e5 | 11784 | } |
b5ff1b31 FB |
11785 | return phys_addr; |
11786 | } | |
11787 | ||
b5ff1b31 | 11788 | #endif |
6ddbc6e4 PB |
11789 | |
11790 | /* Note that signed overflow is undefined in C. The following routines are | |
11791 | careful to use unsigned types where modulo arithmetic is required. | |
11792 | Failure to do so _will_ break on newer gcc. */ | |
11793 | ||
11794 | /* Signed saturating arithmetic. */ | |
11795 | ||
1654b2d6 | 11796 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
11797 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
11798 | { | |
11799 | uint16_t res; | |
11800 | ||
11801 | res = a + b; | |
11802 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
11803 | if (a & 0x8000) | |
11804 | res = 0x8000; | |
11805 | else | |
11806 | res = 0x7fff; | |
11807 | } | |
11808 | return res; | |
11809 | } | |
11810 | ||
1654b2d6 | 11811 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
11812 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
11813 | { | |
11814 | uint8_t res; | |
11815 | ||
11816 | res = a + b; | |
11817 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
11818 | if (a & 0x80) | |
11819 | res = 0x80; | |
11820 | else | |
11821 | res = 0x7f; | |
11822 | } | |
11823 | return res; | |
11824 | } | |
11825 | ||
1654b2d6 | 11826 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
11827 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
11828 | { | |
11829 | uint16_t res; | |
11830 | ||
11831 | res = a - b; | |
11832 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
11833 | if (a & 0x8000) | |
11834 | res = 0x8000; | |
11835 | else | |
11836 | res = 0x7fff; | |
11837 | } | |
11838 | return res; | |
11839 | } | |
11840 | ||
1654b2d6 | 11841 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
11842 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
11843 | { | |
11844 | uint8_t res; | |
11845 | ||
11846 | res = a - b; | |
11847 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
11848 | if (a & 0x80) | |
11849 | res = 0x80; | |
11850 | else | |
11851 | res = 0x7f; | |
11852 | } | |
11853 | return res; | |
11854 | } | |
11855 | ||
11856 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
11857 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
11858 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
11859 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
11860 | #define PFX q | |
11861 | ||
11862 | #include "op_addsub.h" | |
11863 | ||
11864 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 11865 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
11866 | { |
11867 | uint16_t res; | |
11868 | res = a + b; | |
11869 | if (res < a) | |
11870 | res = 0xffff; | |
11871 | return res; | |
11872 | } | |
11873 | ||
460a09c1 | 11874 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 | 11875 | { |
4c4fd3f8 | 11876 | if (a > b) |
6ddbc6e4 PB |
11877 | return a - b; |
11878 | else | |
11879 | return 0; | |
11880 | } | |
11881 | ||
11882 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
11883 | { | |
11884 | uint8_t res; | |
11885 | res = a + b; | |
11886 | if (res < a) | |
11887 | res = 0xff; | |
11888 | return res; | |
11889 | } | |
11890 | ||
11891 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
11892 | { | |
4c4fd3f8 | 11893 | if (a > b) |
6ddbc6e4 PB |
11894 | return a - b; |
11895 | else | |
11896 | return 0; | |
11897 | } | |
11898 | ||
11899 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
11900 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
11901 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
11902 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
11903 | #define PFX uq | |
11904 | ||
11905 | #include "op_addsub.h" | |
11906 | ||
11907 | /* Signed modulo arithmetic. */ | |
11908 | #define SARITH16(a, b, n, op) do { \ | |
11909 | int32_t sum; \ | |
db6e2e65 | 11910 | sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
6ddbc6e4 PB |
11911 | RESULT(sum, n, 16); \ |
11912 | if (sum >= 0) \ | |
11913 | ge |= 3 << (n * 2); \ | |
11914 | } while(0) | |
11915 | ||
11916 | #define SARITH8(a, b, n, op) do { \ | |
11917 | int32_t sum; \ | |
db6e2e65 | 11918 | sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
6ddbc6e4 PB |
11919 | RESULT(sum, n, 8); \ |
11920 | if (sum >= 0) \ | |
11921 | ge |= 1 << n; \ | |
11922 | } while(0) | |
11923 | ||
11924 | ||
11925 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
11926 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
11927 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
11928 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
11929 | #define PFX s | |
11930 | #define ARITH_GE | |
11931 | ||
11932 | #include "op_addsub.h" | |
11933 | ||
11934 | /* Unsigned modulo arithmetic. */ | |
11935 | #define ADD16(a, b, n) do { \ | |
11936 | uint32_t sum; \ | |
11937 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
11938 | RESULT(sum, n, 16); \ | |
a87aa10b | 11939 | if ((sum >> 16) == 1) \ |
6ddbc6e4 PB |
11940 | ge |= 3 << (n * 2); \ |
11941 | } while(0) | |
11942 | ||
11943 | #define ADD8(a, b, n) do { \ | |
11944 | uint32_t sum; \ | |
11945 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
11946 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
11947 | if ((sum >> 8) == 1) \ |
11948 | ge |= 1 << n; \ | |
6ddbc6e4 PB |
11949 | } while(0) |
11950 | ||
11951 | #define SUB16(a, b, n) do { \ | |
11952 | uint32_t sum; \ | |
11953 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
11954 | RESULT(sum, n, 16); \ | |
11955 | if ((sum >> 16) == 0) \ | |
11956 | ge |= 3 << (n * 2); \ | |
11957 | } while(0) | |
11958 | ||
11959 | #define SUB8(a, b, n) do { \ | |
11960 | uint32_t sum; \ | |
11961 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
11962 | RESULT(sum, n, 8); \ | |
11963 | if ((sum >> 8) == 0) \ | |
a87aa10b | 11964 | ge |= 1 << n; \ |
6ddbc6e4 PB |
11965 | } while(0) |
11966 | ||
11967 | #define PFX u | |
11968 | #define ARITH_GE | |
11969 | ||
11970 | #include "op_addsub.h" | |
11971 | ||
11972 | /* Halved signed arithmetic. */ | |
11973 | #define ADD16(a, b, n) \ | |
11974 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
11975 | #define SUB16(a, b, n) \ | |
11976 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
11977 | #define ADD8(a, b, n) \ | |
11978 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
11979 | #define SUB8(a, b, n) \ | |
11980 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
11981 | #define PFX sh | |
11982 | ||
11983 | #include "op_addsub.h" | |
11984 | ||
11985 | /* Halved unsigned arithmetic. */ | |
11986 | #define ADD16(a, b, n) \ | |
11987 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
11988 | #define SUB16(a, b, n) \ | |
11989 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
11990 | #define ADD8(a, b, n) \ | |
11991 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
11992 | #define SUB8(a, b, n) \ | |
11993 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
11994 | #define PFX uh | |
11995 | ||
11996 | #include "op_addsub.h" | |
11997 | ||
11998 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
11999 | { | |
12000 | if (a > b) | |
12001 | return a - b; | |
12002 | else | |
12003 | return b - a; | |
12004 | } | |
12005 | ||
12006 | /* Unsigned sum of absolute byte differences. */ | |
12007 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
12008 | { | |
12009 | uint32_t sum; | |
12010 | sum = do_usad(a, b); | |
12011 | sum += do_usad(a >> 8, b >> 8); | |
12012 | sum += do_usad(a >> 16, b >>16); | |
12013 | sum += do_usad(a >> 24, b >> 24); | |
12014 | return sum; | |
12015 | } | |
12016 | ||
12017 | /* For ARMv6 SEL instruction. */ | |
12018 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
12019 | { | |
12020 | uint32_t mask; | |
12021 | ||
12022 | mask = 0; | |
12023 | if (flags & 1) | |
12024 | mask |= 0xff; | |
12025 | if (flags & 2) | |
12026 | mask |= 0xff00; | |
12027 | if (flags & 4) | |
12028 | mask |= 0xff0000; | |
12029 | if (flags & 8) | |
12030 | mask |= 0xff000000; | |
12031 | return (a & mask) | (b & ~mask); | |
12032 | } | |
12033 | ||
aa633469 PM |
12034 | /* CRC helpers. |
12035 | * The upper bytes of val (above the number specified by 'bytes') must have | |
12036 | * been zeroed out by the caller. | |
12037 | */ | |
eb0ecd5a WN |
12038 | uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) |
12039 | { | |
12040 | uint8_t buf[4]; | |
12041 | ||
aa633469 | 12042 | stl_le_p(buf, val); |
eb0ecd5a WN |
12043 | |
12044 | /* zlib crc32 converts the accumulator and output to one's complement. */ | |
12045 | return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | |
12046 | } | |
12047 | ||
12048 | uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | |
12049 | { | |
12050 | uint8_t buf[4]; | |
12051 | ||
aa633469 | 12052 | stl_le_p(buf, val); |
eb0ecd5a WN |
12053 | |
12054 | /* Linux crc32c converts the output to one's complement. */ | |
12055 | return crc32c(acc, buf, bytes) ^ 0xffffffff; | |
12056 | } | |
a9e01311 RH |
12057 | |
12058 | /* Return the exception level to which FP-disabled exceptions should | |
12059 | * be taken, or 0 if FP is enabled. | |
12060 | */ | |
ced31551 | 12061 | int fp_exception_el(CPUARMState *env, int cur_el) |
a9e01311 | 12062 | { |
55faa212 | 12063 | #ifndef CONFIG_USER_ONLY |
a9e01311 RH |
12064 | /* CPACR and the CPTR registers don't exist before v6, so FP is |
12065 | * always accessible | |
12066 | */ | |
12067 | if (!arm_feature(env, ARM_FEATURE_V6)) { | |
12068 | return 0; | |
12069 | } | |
12070 | ||
d87513c0 PM |
12071 | if (arm_feature(env, ARM_FEATURE_M)) { |
12072 | /* CPACR can cause a NOCP UsageFault taken to current security state */ | |
12073 | if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) { | |
12074 | return 1; | |
12075 | } | |
12076 | ||
12077 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) { | |
12078 | if (!extract32(env->v7m.nsacr, 10, 1)) { | |
12079 | /* FP insns cause a NOCP UsageFault taken to Secure */ | |
12080 | return 3; | |
12081 | } | |
12082 | } | |
12083 | ||
12084 | return 0; | |
12085 | } | |
12086 | ||
a9e01311 RH |
12087 | /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: |
12088 | * 0, 2 : trap EL0 and EL1/PL1 accesses | |
12089 | * 1 : trap only EL0 accesses | |
12090 | * 3 : trap no accesses | |
c2ddb7cf | 12091 | * This register is ignored if E2H+TGE are both set. |
a9e01311 | 12092 | */ |
c2ddb7cf RH |
12093 | if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { |
12094 | int fpen = extract32(env->cp15.cpacr_el1, 20, 2); | |
12095 | ||
12096 | switch (fpen) { | |
12097 | case 0: | |
12098 | case 2: | |
12099 | if (cur_el == 0 || cur_el == 1) { | |
12100 | /* Trap to PL1, which might be EL1 or EL3 */ | |
12101 | if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { | |
12102 | return 3; | |
12103 | } | |
12104 | return 1; | |
12105 | } | |
12106 | if (cur_el == 3 && !is_a64(env)) { | |
12107 | /* Secure PL1 running at EL3 */ | |
a9e01311 RH |
12108 | return 3; |
12109 | } | |
c2ddb7cf RH |
12110 | break; |
12111 | case 1: | |
12112 | if (cur_el == 0) { | |
12113 | return 1; | |
12114 | } | |
12115 | break; | |
12116 | case 3: | |
12117 | break; | |
a9e01311 | 12118 | } |
a9e01311 RH |
12119 | } |
12120 | ||
fc1120a7 PM |
12121 | /* |
12122 | * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode | |
12123 | * to control non-secure access to the FPU. It doesn't have any | |
12124 | * effect if EL3 is AArch64 or if EL3 doesn't exist at all. | |
12125 | */ | |
12126 | if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
12127 | cur_el <= 2 && !arm_is_secure_below_el3(env))) { | |
12128 | if (!extract32(env->cp15.nsacr, 10, 1)) { | |
12129 | /* FP insns act as UNDEF */ | |
12130 | return cur_el == 2 ? 2 : 1; | |
12131 | } | |
12132 | } | |
12133 | ||
a9e01311 RH |
12134 | /* For the CPTR registers we don't need to guard with an ARM_FEATURE |
12135 | * check because zero bits in the registers mean "don't trap". | |
12136 | */ | |
12137 | ||
12138 | /* CPTR_EL2 : present in v7VE or v8 */ | |
12139 | if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1) | |
12140 | && !arm_is_secure_below_el3(env)) { | |
12141 | /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ | |
12142 | return 2; | |
12143 | } | |
12144 | ||
12145 | /* CPTR_EL3 : present in v8 */ | |
12146 | if (extract32(env->cp15.cptr_el[3], 10, 1)) { | |
12147 | /* Trap all FP ops to EL3 */ | |
12148 | return 3; | |
12149 | } | |
55faa212 | 12150 | #endif |
a9e01311 RH |
12151 | return 0; |
12152 | } | |
12153 | ||
b9f6033c RH |
12154 | /* Return the exception level we're running at if this is our mmu_idx */ |
12155 | int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) | |
12156 | { | |
12157 | if (mmu_idx & ARM_MMU_IDX_M) { | |
12158 | return mmu_idx & ARM_MMU_IDX_M_PRIV; | |
12159 | } | |
12160 | ||
12161 | switch (mmu_idx) { | |
12162 | case ARMMMUIdx_E10_0: | |
12163 | case ARMMMUIdx_E20_0: | |
12164 | case ARMMMUIdx_SE10_0: | |
12165 | return 0; | |
12166 | case ARMMMUIdx_E10_1: | |
452ef8cb | 12167 | case ARMMMUIdx_E10_1_PAN: |
b9f6033c | 12168 | case ARMMMUIdx_SE10_1: |
452ef8cb | 12169 | case ARMMMUIdx_SE10_1_PAN: |
b9f6033c RH |
12170 | return 1; |
12171 | case ARMMMUIdx_E2: | |
12172 | case ARMMMUIdx_E20_2: | |
452ef8cb | 12173 | case ARMMMUIdx_E20_2_PAN: |
b9f6033c RH |
12174 | return 2; |
12175 | case ARMMMUIdx_SE3: | |
12176 | return 3; | |
12177 | default: | |
12178 | g_assert_not_reached(); | |
12179 | } | |
12180 | } | |
12181 | ||
7aab5a8c | 12182 | #ifndef CONFIG_TCG |
65e4655c RH |
12183 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
12184 | { | |
7aab5a8c | 12185 | g_assert_not_reached(); |
65e4655c | 12186 | } |
7aab5a8c | 12187 | #endif |
65e4655c | 12188 | |
164690b2 | 12189 | ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) |
65e4655c | 12190 | { |
65e4655c | 12191 | if (arm_feature(env, ARM_FEATURE_M)) { |
50494a27 | 12192 | return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); |
65e4655c RH |
12193 | } |
12194 | ||
6003d980 | 12195 | /* See ARM pseudo-function ELIsInHost. */ |
b9f6033c RH |
12196 | switch (el) { |
12197 | case 0: | |
b9f6033c RH |
12198 | if (arm_is_secure_below_el3(env)) { |
12199 | return ARMMMUIdx_SE10_0; | |
12200 | } | |
6003d980 RH |
12201 | if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE) |
12202 | && arm_el_is_aa64(env, 2)) { | |
12203 | return ARMMMUIdx_E20_0; | |
12204 | } | |
b9f6033c RH |
12205 | return ARMMMUIdx_E10_0; |
12206 | case 1: | |
12207 | if (arm_is_secure_below_el3(env)) { | |
66412260 RH |
12208 | if (env->pstate & PSTATE_PAN) { |
12209 | return ARMMMUIdx_SE10_1_PAN; | |
12210 | } | |
b9f6033c RH |
12211 | return ARMMMUIdx_SE10_1; |
12212 | } | |
66412260 RH |
12213 | if (env->pstate & PSTATE_PAN) { |
12214 | return ARMMMUIdx_E10_1_PAN; | |
12215 | } | |
b9f6033c RH |
12216 | return ARMMMUIdx_E10_1; |
12217 | case 2: | |
b9f6033c | 12218 | /* TODO: ARMv8.4-SecEL2 */ |
6003d980 RH |
12219 | /* Note that TGE does not apply at EL2. */ |
12220 | if ((env->cp15.hcr_el2 & HCR_E2H) && arm_el_is_aa64(env, 2)) { | |
66412260 RH |
12221 | if (env->pstate & PSTATE_PAN) { |
12222 | return ARMMMUIdx_E20_2_PAN; | |
12223 | } | |
6003d980 RH |
12224 | return ARMMMUIdx_E20_2; |
12225 | } | |
b9f6033c RH |
12226 | return ARMMMUIdx_E2; |
12227 | case 3: | |
12228 | return ARMMMUIdx_SE3; | |
12229 | default: | |
12230 | g_assert_not_reached(); | |
65e4655c | 12231 | } |
50494a27 RH |
12232 | } |
12233 | ||
164690b2 RH |
12234 | ARMMMUIdx arm_mmu_idx(CPUARMState *env) |
12235 | { | |
12236 | return arm_mmu_idx_el(env, arm_current_el(env)); | |
12237 | } | |
12238 | ||
50494a27 RH |
12239 | int cpu_mmu_index(CPUARMState *env, bool ifetch) |
12240 | { | |
12241 | return arm_to_core_mmu_idx(arm_mmu_idx(env)); | |
65e4655c RH |
12242 | } |
12243 | ||
64be86ab RH |
12244 | #ifndef CONFIG_USER_ONLY |
12245 | ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) | |
12246 | { | |
12247 | return stage_1_mmu_idx(arm_mmu_idx(env)); | |
12248 | } | |
12249 | #endif | |
12250 | ||
fdd1b228 RH |
12251 | static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, |
12252 | ARMMMUIdx mmu_idx, uint32_t flags) | |
12253 | { | |
12254 | flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); | |
12255 | flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, | |
12256 | arm_to_core_mmu_idx(mmu_idx)); | |
12257 | ||
fdd1b228 RH |
12258 | if (arm_singlestep_active(env)) { |
12259 | flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); | |
12260 | } | |
12261 | return flags; | |
12262 | } | |
12263 | ||
43eccfb6 RH |
12264 | static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, |
12265 | ARMMMUIdx mmu_idx, uint32_t flags) | |
12266 | { | |
8061a649 RH |
12267 | bool sctlr_b = arm_sctlr_b(env); |
12268 | ||
12269 | if (sctlr_b) { | |
12270 | flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, 1); | |
12271 | } | |
12272 | if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { | |
12273 | flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); | |
12274 | } | |
43eccfb6 RH |
12275 | flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); |
12276 | ||
12277 | return rebuild_hflags_common(env, fp_el, mmu_idx, flags); | |
12278 | } | |
12279 | ||
6e33ced5 RH |
12280 | static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, |
12281 | ARMMMUIdx mmu_idx) | |
12282 | { | |
12283 | uint32_t flags = 0; | |
12284 | ||
12285 | if (arm_v7m_is_handler_mode(env)) { | |
79cabf1f | 12286 | flags = FIELD_DP32(flags, TBFLAG_M32, HANDLER, 1); |
6e33ced5 RH |
12287 | } |
12288 | ||
12289 | /* | |
12290 | * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN | |
12291 | * is suppressing them because the requested execution priority | |
12292 | * is less than 0. | |
12293 | */ | |
12294 | if (arm_feature(env, ARM_FEATURE_V8) && | |
12295 | !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && | |
12296 | (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { | |
79cabf1f | 12297 | flags = FIELD_DP32(flags, TBFLAG_M32, STACKCHECK, 1); |
6e33ced5 RH |
12298 | } |
12299 | ||
12300 | return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); | |
12301 | } | |
12302 | ||
83f4baef RH |
12303 | static uint32_t rebuild_hflags_aprofile(CPUARMState *env) |
12304 | { | |
12305 | int flags = 0; | |
12306 | ||
12307 | flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, | |
12308 | arm_debug_target_el(env)); | |
12309 | return flags; | |
12310 | } | |
12311 | ||
c747224c RH |
12312 | static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, |
12313 | ARMMMUIdx mmu_idx) | |
12314 | { | |
83f4baef | 12315 | uint32_t flags = rebuild_hflags_aprofile(env); |
0a54d68e RH |
12316 | |
12317 | if (arm_el_is_aa64(env, 1)) { | |
12318 | flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); | |
12319 | } | |
5bb0a20b MZ |
12320 | |
12321 | if (arm_current_el(env) < 2 && env->cp15.hstr_el2 && | |
12322 | (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { | |
12323 | flags = FIELD_DP32(flags, TBFLAG_A32, HSTR_ACTIVE, 1); | |
12324 | } | |
12325 | ||
83f4baef | 12326 | return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); |
c747224c RH |
12327 | } |
12328 | ||
d4d7503a RH |
12329 | static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, |
12330 | ARMMMUIdx mmu_idx) | |
a9e01311 | 12331 | { |
83f4baef | 12332 | uint32_t flags = rebuild_hflags_aprofile(env); |
d4d7503a | 12333 | ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); |
b830a5ee | 12334 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; |
d4d7503a RH |
12335 | uint64_t sctlr; |
12336 | int tbii, tbid; | |
b9adaa70 | 12337 | |
d4d7503a | 12338 | flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); |
cd208a1c | 12339 | |
339370b9 | 12340 | /* Get control bits for tagged addresses. */ |
b830a5ee RH |
12341 | tbid = aa64_va_parameter_tbi(tcr, mmu_idx); |
12342 | tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); | |
5d8634f5 | 12343 | |
d4d7503a RH |
12344 | flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); |
12345 | flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); | |
12346 | ||
12347 | if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { | |
12348 | int sve_el = sve_exception_el(env, el); | |
12349 | uint32_t zcr_len; | |
5d8634f5 | 12350 | |
d4d7503a RH |
12351 | /* |
12352 | * If SVE is disabled, but FP is enabled, | |
12353 | * then the effective len is 0. | |
12354 | */ | |
12355 | if (sve_el != 0 && fp_el == 0) { | |
12356 | zcr_len = 0; | |
12357 | } else { | |
12358 | zcr_len = sve_zcr_len_for_el(env, el); | |
5d8634f5 | 12359 | } |
d4d7503a RH |
12360 | flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); |
12361 | flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); | |
12362 | } | |
1db5e96c | 12363 | |
aaec1432 | 12364 | sctlr = regime_sctlr(env, stage1); |
1db5e96c | 12365 | |
8061a649 RH |
12366 | if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { |
12367 | flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); | |
12368 | } | |
12369 | ||
d4d7503a RH |
12370 | if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { |
12371 | /* | |
12372 | * In order to save space in flags, we record only whether | |
12373 | * pauth is "inactive", meaning all insns are implemented as | |
12374 | * a nop, or "active" when some action must be performed. | |
12375 | * The decision of which action to take is left to a helper. | |
12376 | */ | |
12377 | if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { | |
12378 | flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); | |
1db5e96c | 12379 | } |
d4d7503a | 12380 | } |
0816ef1b | 12381 | |
d4d7503a RH |
12382 | if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { |
12383 | /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ | |
12384 | if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { | |
12385 | flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); | |
0816ef1b | 12386 | } |
d4d7503a | 12387 | } |
08f1434a | 12388 | |
cc28fc30 | 12389 | /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ |
7a8014ab RH |
12390 | if (!(env->pstate & PSTATE_UAO)) { |
12391 | switch (mmu_idx) { | |
12392 | case ARMMMUIdx_E10_1: | |
12393 | case ARMMMUIdx_E10_1_PAN: | |
12394 | case ARMMMUIdx_SE10_1: | |
12395 | case ARMMMUIdx_SE10_1_PAN: | |
12396 | /* TODO: ARMv8.3-NV */ | |
cc28fc30 | 12397 | flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); |
7a8014ab RH |
12398 | break; |
12399 | case ARMMMUIdx_E20_2: | |
12400 | case ARMMMUIdx_E20_2_PAN: | |
12401 | /* TODO: ARMv8.4-SecEL2 */ | |
12402 | /* | |
12403 | * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is | |
12404 | * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR. | |
12405 | */ | |
12406 | if (env->cp15.hcr_el2 & HCR_TGE) { | |
12407 | flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); | |
12408 | } | |
12409 | break; | |
12410 | default: | |
12411 | break; | |
cc28fc30 | 12412 | } |
cc28fc30 RH |
12413 | } |
12414 | ||
d4d7503a RH |
12415 | return rebuild_hflags_common(env, fp_el, mmu_idx, flags); |
12416 | } | |
12417 | ||
3d74e2e9 RH |
12418 | static uint32_t rebuild_hflags_internal(CPUARMState *env) |
12419 | { | |
12420 | int el = arm_current_el(env); | |
12421 | int fp_el = fp_exception_el(env, el); | |
164690b2 | 12422 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); |
3d74e2e9 RH |
12423 | |
12424 | if (is_a64(env)) { | |
12425 | return rebuild_hflags_a64(env, el, fp_el, mmu_idx); | |
12426 | } else if (arm_feature(env, ARM_FEATURE_M)) { | |
12427 | return rebuild_hflags_m32(env, fp_el, mmu_idx); | |
12428 | } else { | |
12429 | return rebuild_hflags_a32(env, fp_el, mmu_idx); | |
12430 | } | |
12431 | } | |
12432 | ||
12433 | void arm_rebuild_hflags(CPUARMState *env) | |
12434 | { | |
12435 | env->hflags = rebuild_hflags_internal(env); | |
12436 | } | |
12437 | ||
14f3c588 RH |
12438 | void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) |
12439 | { | |
12440 | int fp_el = fp_exception_el(env, el); | |
12441 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
12442 | ||
12443 | env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); | |
12444 | } | |
12445 | ||
f80741d1 AB |
12446 | /* |
12447 | * If we have triggered a EL state change we can't rely on the | |
12448 | * translator having passed it too us, we need to recompute. | |
12449 | */ | |
12450 | void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) | |
12451 | { | |
12452 | int el = arm_current_el(env); | |
12453 | int fp_el = fp_exception_el(env, el); | |
12454 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
12455 | env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); | |
12456 | } | |
12457 | ||
14f3c588 RH |
12458 | void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) |
12459 | { | |
12460 | int fp_el = fp_exception_el(env, el); | |
12461 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
12462 | ||
12463 | env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); | |
12464 | } | |
12465 | ||
12466 | void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) | |
12467 | { | |
12468 | int fp_el = fp_exception_el(env, el); | |
12469 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
12470 | ||
12471 | env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx); | |
12472 | } | |
12473 | ||
0ee8b24a PMD |
12474 | static inline void assert_hflags_rebuild_correctly(CPUARMState *env) |
12475 | { | |
12476 | #ifdef CONFIG_DEBUG_TCG | |
12477 | uint32_t env_flags_current = env->hflags; | |
12478 | uint32_t env_flags_rebuilt = rebuild_hflags_internal(env); | |
12479 | ||
12480 | if (unlikely(env_flags_current != env_flags_rebuilt)) { | |
12481 | fprintf(stderr, "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n", | |
12482 | env_flags_current, env_flags_rebuilt); | |
12483 | abort(); | |
12484 | } | |
12485 | #endif | |
12486 | } | |
12487 | ||
d4d7503a RH |
12488 | void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, |
12489 | target_ulong *cs_base, uint32_t *pflags) | |
12490 | { | |
e979972a RH |
12491 | uint32_t flags = env->hflags; |
12492 | uint32_t pstate_for_ss; | |
d4d7503a | 12493 | |
9b253fe5 | 12494 | *cs_base = 0; |
0ee8b24a | 12495 | assert_hflags_rebuild_correctly(env); |
3d74e2e9 | 12496 | |
e979972a | 12497 | if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) { |
d4d7503a | 12498 | *pc = env->pc; |
d4d7503a | 12499 | if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { |
08f1434a RH |
12500 | flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); |
12501 | } | |
60e12c37 | 12502 | pstate_for_ss = env->pstate; |
a9e01311 RH |
12503 | } else { |
12504 | *pc = env->regs[15]; | |
6e33ced5 RH |
12505 | |
12506 | if (arm_feature(env, ARM_FEATURE_M)) { | |
9550d1bd RH |
12507 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && |
12508 | FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) | |
12509 | != env->v7m.secure) { | |
79cabf1f | 12510 | flags = FIELD_DP32(flags, TBFLAG_M32, FPCCR_S_WRONG, 1); |
9550d1bd RH |
12511 | } |
12512 | ||
12513 | if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && | |
12514 | (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || | |
12515 | (env->v7m.secure && | |
12516 | !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { | |
12517 | /* | |
12518 | * ASPEN is set, but FPCA/SFPA indicate that there is no | |
12519 | * active FP context; we must create a new FP context before | |
12520 | * executing any FP insn. | |
12521 | */ | |
79cabf1f | 12522 | flags = FIELD_DP32(flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED, 1); |
9550d1bd RH |
12523 | } |
12524 | ||
12525 | bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; | |
12526 | if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { | |
79cabf1f | 12527 | flags = FIELD_DP32(flags, TBFLAG_M32, LSPACT, 1); |
9550d1bd | 12528 | } |
6e33ced5 | 12529 | } else { |
bbad7c62 RH |
12530 | /* |
12531 | * Note that XSCALE_CPAR shares bits with VECSTRIDE. | |
12532 | * Note that VECLEN+VECSTRIDE are RES0 for M-profile. | |
12533 | */ | |
12534 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
12535 | flags = FIELD_DP32(flags, TBFLAG_A32, | |
12536 | XSCALE_CPAR, env->cp15.c15_cpar); | |
12537 | } else { | |
12538 | flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, | |
12539 | env->vfp.vec_len); | |
12540 | flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, | |
12541 | env->vfp.vec_stride); | |
12542 | } | |
0a54d68e RH |
12543 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { |
12544 | flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); | |
12545 | } | |
6e33ced5 RH |
12546 | } |
12547 | ||
79cabf1f RH |
12548 | flags = FIELD_DP32(flags, TBFLAG_AM32, THUMB, env->thumb); |
12549 | flags = FIELD_DP32(flags, TBFLAG_AM32, CONDEXEC, env->condexec_bits); | |
60e12c37 | 12550 | pstate_for_ss = env->uncached_cpsr; |
d4d7503a | 12551 | } |
a9e01311 | 12552 | |
60e12c37 RH |
12553 | /* |
12554 | * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine | |
a9e01311 RH |
12555 | * states defined in the ARM ARM for software singlestep: |
12556 | * SS_ACTIVE PSTATE.SS State | |
12557 | * 0 x Inactive (the TB flag for SS is always 0) | |
12558 | * 1 0 Active-pending | |
12559 | * 1 1 Active-not-pending | |
fdd1b228 | 12560 | * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. |
a9e01311 | 12561 | */ |
60e12c37 RH |
12562 | if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) && |
12563 | (pstate_for_ss & PSTATE_SS)) { | |
12564 | flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); | |
a9e01311 | 12565 | } |
a9e01311 | 12566 | |
b9adaa70 | 12567 | *pflags = flags; |
a9e01311 | 12568 | } |
0ab5953b RH |
12569 | |
12570 | #ifdef TARGET_AARCH64 | |
12571 | /* | |
12572 | * The manual says that when SVE is enabled and VQ is widened the | |
12573 | * implementation is allowed to zero the previously inaccessible | |
12574 | * portion of the registers. The corollary to that is that when | |
12575 | * SVE is enabled and VQ is narrowed we are also allowed to zero | |
12576 | * the now inaccessible portion of the registers. | |
12577 | * | |
12578 | * The intent of this is that no predicate bit beyond VQ is ever set. | |
12579 | * Which means that some operations on predicate registers themselves | |
12580 | * may operate on full uint64_t or even unrolled across the maximum | |
12581 | * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally | |
12582 | * may well be cheaper than conditionals to restrict the operation | |
12583 | * to the relevant portion of a uint16_t[16]. | |
12584 | */ | |
12585 | void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) | |
12586 | { | |
12587 | int i, j; | |
12588 | uint64_t pmask; | |
12589 | ||
12590 | assert(vq >= 1 && vq <= ARM_MAX_VQ); | |
2fc0cc0e | 12591 | assert(vq <= env_archcpu(env)->sve_max_vq); |
0ab5953b RH |
12592 | |
12593 | /* Zap the high bits of the zregs. */ | |
12594 | for (i = 0; i < 32; i++) { | |
12595 | memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)); | |
12596 | } | |
12597 | ||
12598 | /* Zap the high bits of the pregs and ffr. */ | |
12599 | pmask = 0; | |
12600 | if (vq & 3) { | |
12601 | pmask = ~(-1ULL << (16 * (vq & 3))); | |
12602 | } | |
12603 | for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) { | |
12604 | for (i = 0; i < 17; ++i) { | |
12605 | env->vfp.pregs[i].p[j] &= pmask; | |
12606 | } | |
12607 | pmask = 0; | |
12608 | } | |
12609 | } | |
12610 | ||
12611 | /* | |
12612 | * Notice a change in SVE vector size when changing EL. | |
12613 | */ | |
9a05f7b6 RH |
12614 | void aarch64_sve_change_el(CPUARMState *env, int old_el, |
12615 | int new_el, bool el0_a64) | |
0ab5953b | 12616 | { |
2fc0cc0e | 12617 | ARMCPU *cpu = env_archcpu(env); |
0ab5953b | 12618 | int old_len, new_len; |
9a05f7b6 | 12619 | bool old_a64, new_a64; |
0ab5953b RH |
12620 | |
12621 | /* Nothing to do if no SVE. */ | |
cd208a1c | 12622 | if (!cpu_isar_feature(aa64_sve, cpu)) { |
0ab5953b RH |
12623 | return; |
12624 | } | |
12625 | ||
12626 | /* Nothing to do if FP is disabled in either EL. */ | |
12627 | if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) { | |
12628 | return; | |
12629 | } | |
12630 | ||
12631 | /* | |
12632 | * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped | |
12633 | * at ELx, or not available because the EL is in AArch32 state, then | |
12634 | * for all purposes other than a direct read, the ZCR_ELx.LEN field | |
12635 | * has an effective value of 0". | |
12636 | * | |
12637 | * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0). | |
12638 | * If we ignore aa32 state, we would fail to see the vq4->vq0 transition | |
12639 | * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that | |
12640 | * we already have the correct register contents when encountering the | |
12641 | * vq0->vq0 transition between EL0->EL1. | |
12642 | */ | |
9a05f7b6 RH |
12643 | old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; |
12644 | old_len = (old_a64 && !sve_exception_el(env, old_el) | |
0ab5953b | 12645 | ? sve_zcr_len_for_el(env, old_el) : 0); |
9a05f7b6 RH |
12646 | new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; |
12647 | new_len = (new_a64 && !sve_exception_el(env, new_el) | |
0ab5953b RH |
12648 | ? sve_zcr_len_for_el(env, new_el) : 0); |
12649 | ||
12650 | /* When changing vector length, clear inaccessible state. */ | |
12651 | if (new_len < old_len) { | |
12652 | aarch64_sve_narrow_vq(env, new_len + 1); | |
12653 | } | |
12654 | } | |
12655 | #endif |