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Commit | Line | Data |
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ed3baad1 PMD |
1 | /* |
2 | * ARM generic helpers. | |
3 | * | |
4 | * This code is licensed under the GNU GPL v2 or later. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0-or-later | |
7 | */ | |
db725815 | 8 | |
74c21bd0 | 9 | #include "qemu/osdep.h" |
63159601 | 10 | #include "qemu/units.h" |
181962fd | 11 | #include "target/arm/idau.h" |
194cbc49 | 12 | #include "trace.h" |
b5ff1b31 | 13 | #include "cpu.h" |
ccd38087 | 14 | #include "internals.h" |
2ef6175a | 15 | #include "exec/helper-proto.h" |
1de7afc9 | 16 | #include "qemu/host-utils.h" |
db725815 | 17 | #include "qemu/main-loop.h" |
1de7afc9 | 18 | #include "qemu/bitops.h" |
eb0ecd5a | 19 | #include "qemu/crc32c.h" |
0442428a | 20 | #include "qemu/qemu-print.h" |
63c91552 | 21 | #include "exec/exec-all.h" |
eb0ecd5a | 22 | #include <zlib.h> /* For crc32 */ |
64552b6b | 23 | #include "hw/irq.h" |
6b5fe137 | 24 | #include "semihosting/semihost.h" |
b2e23725 | 25 | #include "sysemu/cpus.h" |
740b1759 | 26 | #include "sysemu/cpu-timers.h" |
f3a9b694 | 27 | #include "sysemu/kvm.h" |
2a609df8 | 28 | #include "sysemu/tcg.h" |
9d2b5a58 | 29 | #include "qemu/range.h" |
7f7b4e7a | 30 | #include "qapi/qapi-commands-machine-target.h" |
de390645 RH |
31 | #include "qapi/error.h" |
32 | #include "qemu/guest-random.h" | |
91f78c58 PMD |
33 | #ifdef CONFIG_TCG |
34 | #include "arm_ldst.h" | |
7aab5a8c | 35 | #include "exec/cpu_ldst.h" |
6b5fe137 | 36 | #include "semihosting/common-semi.h" |
91f78c58 | 37 | #endif |
0b03bdfc | 38 | |
352c98e5 | 39 | #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ |
21c2dd77 | 40 | #define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */ |
352c98e5 | 41 | |
4a501606 | 42 | #ifndef CONFIG_USER_ONLY |
7c2cb42b | 43 | |
98e87797 | 44 | static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, |
03ae85f8 | 45 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
ff7de2fc | 46 | bool s1_is_el0, |
37785977 | 47 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, |
da909b2c | 48 | target_ulong *page_size_ptr, |
7e98e21c RH |
49 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) |
50 | __attribute__((nonnull)); | |
4a501606 PM |
51 | #endif |
52 | ||
affdb64d | 53 | static void switch_mode(CPUARMState *env, int mode); |
ea04dce7 | 54 | static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); |
affdb64d | 55 | |
c4241c7d | 56 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) |
d4e6df63 | 57 | { |
375421cc | 58 | assert(ri->fieldoffset); |
67ed771d | 59 | if (cpreg_field_is_64bit(ri)) { |
c4241c7d | 60 | return CPREG_FIELD64(env, ri); |
22d9e1a9 | 61 | } else { |
c4241c7d | 62 | return CPREG_FIELD32(env, ri); |
22d9e1a9 | 63 | } |
d4e6df63 PM |
64 | } |
65 | ||
c4241c7d PM |
66 | static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
67 | uint64_t value) | |
d4e6df63 | 68 | { |
375421cc | 69 | assert(ri->fieldoffset); |
67ed771d | 70 | if (cpreg_field_is_64bit(ri)) { |
22d9e1a9 PM |
71 | CPREG_FIELD64(env, ri) = value; |
72 | } else { | |
73 | CPREG_FIELD32(env, ri) = value; | |
74 | } | |
d4e6df63 PM |
75 | } |
76 | ||
11f136ee FA |
77 | static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) |
78 | { | |
79 | return (char *)env + ri->fieldoffset; | |
80 | } | |
81 | ||
49a66191 | 82 | uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) |
721fae12 | 83 | { |
59a1c327 | 84 | /* Raw read of a coprocessor register (as needed for migration, etc). */ |
721fae12 | 85 | if (ri->type & ARM_CP_CONST) { |
59a1c327 | 86 | return ri->resetvalue; |
721fae12 | 87 | } else if (ri->raw_readfn) { |
59a1c327 | 88 | return ri->raw_readfn(env, ri); |
721fae12 | 89 | } else if (ri->readfn) { |
59a1c327 | 90 | return ri->readfn(env, ri); |
721fae12 | 91 | } else { |
59a1c327 | 92 | return raw_read(env, ri); |
721fae12 | 93 | } |
721fae12 PM |
94 | } |
95 | ||
59a1c327 | 96 | static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, |
7900e9f1 | 97 | uint64_t v) |
721fae12 PM |
98 | { |
99 | /* Raw write of a coprocessor register (as needed for migration, etc). | |
721fae12 PM |
100 | * Note that constant registers are treated as write-ignored; the |
101 | * caller should check for success by whether a readback gives the | |
102 | * value written. | |
103 | */ | |
104 | if (ri->type & ARM_CP_CONST) { | |
59a1c327 | 105 | return; |
721fae12 | 106 | } else if (ri->raw_writefn) { |
c4241c7d | 107 | ri->raw_writefn(env, ri, v); |
721fae12 | 108 | } else if (ri->writefn) { |
c4241c7d | 109 | ri->writefn(env, ri, v); |
721fae12 | 110 | } else { |
afb2530f | 111 | raw_write(env, ri, v); |
721fae12 | 112 | } |
721fae12 PM |
113 | } |
114 | ||
375421cc PM |
115 | static bool raw_accessors_invalid(const ARMCPRegInfo *ri) |
116 | { | |
117 | /* Return true if the regdef would cause an assertion if you called | |
118 | * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a | |
119 | * program bug for it not to have the NO_RAW flag). | |
120 | * NB that returning false here doesn't necessarily mean that calling | |
121 | * read/write_raw_cp_reg() is safe, because we can't distinguish "has | |
122 | * read/write access functions which are safe for raw use" from "has | |
123 | * read/write access functions which have side effects but has forgotten | |
124 | * to provide raw access functions". | |
125 | * The tests here line up with the conditions in read/write_raw_cp_reg() | |
126 | * and assertions in raw_read()/raw_write(). | |
127 | */ | |
128 | if ((ri->type & ARM_CP_CONST) || | |
129 | ri->fieldoffset || | |
130 | ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { | |
131 | return false; | |
132 | } | |
133 | return true; | |
134 | } | |
135 | ||
b698e4ee | 136 | bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync) |
721fae12 PM |
137 | { |
138 | /* Write the coprocessor state from cpu->env to the (index,value) list. */ | |
139 | int i; | |
140 | bool ok = true; | |
141 | ||
142 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
143 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
144 | const ARMCPRegInfo *ri; | |
b698e4ee | 145 | uint64_t newval; |
59a1c327 | 146 | |
60322b39 | 147 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
148 | if (!ri) { |
149 | ok = false; | |
150 | continue; | |
151 | } | |
7a0e58fa | 152 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
153 | continue; |
154 | } | |
b698e4ee PM |
155 | |
156 | newval = read_raw_cp_reg(&cpu->env, ri); | |
157 | if (kvm_sync) { | |
158 | /* | |
159 | * Only sync if the previous list->cpustate sync succeeded. | |
160 | * Rather than tracking the success/failure state for every | |
161 | * item in the list, we just recheck "does the raw write we must | |
162 | * have made in write_list_to_cpustate() read back OK" here. | |
163 | */ | |
164 | uint64_t oldval = cpu->cpreg_values[i]; | |
165 | ||
166 | if (oldval == newval) { | |
167 | continue; | |
168 | } | |
169 | ||
170 | write_raw_cp_reg(&cpu->env, ri, oldval); | |
171 | if (read_raw_cp_reg(&cpu->env, ri) != oldval) { | |
172 | continue; | |
173 | } | |
174 | ||
175 | write_raw_cp_reg(&cpu->env, ri, newval); | |
176 | } | |
177 | cpu->cpreg_values[i] = newval; | |
721fae12 PM |
178 | } |
179 | return ok; | |
180 | } | |
181 | ||
182 | bool write_list_to_cpustate(ARMCPU *cpu) | |
183 | { | |
184 | int i; | |
185 | bool ok = true; | |
186 | ||
187 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
188 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
189 | uint64_t v = cpu->cpreg_values[i]; | |
721fae12 PM |
190 | const ARMCPRegInfo *ri; |
191 | ||
60322b39 | 192 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
193 | if (!ri) { |
194 | ok = false; | |
195 | continue; | |
196 | } | |
7a0e58fa | 197 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
198 | continue; |
199 | } | |
200 | /* Write value and confirm it reads back as written | |
201 | * (to catch read-only registers and partially read-only | |
202 | * registers where the incoming migration value doesn't match) | |
203 | */ | |
59a1c327 PM |
204 | write_raw_cp_reg(&cpu->env, ri, v); |
205 | if (read_raw_cp_reg(&cpu->env, ri) != v) { | |
721fae12 PM |
206 | ok = false; |
207 | } | |
208 | } | |
209 | return ok; | |
210 | } | |
211 | ||
212 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | |
213 | { | |
214 | ARMCPU *cpu = opaque; | |
215 | uint64_t regidx; | |
216 | const ARMCPRegInfo *ri; | |
217 | ||
218 | regidx = *(uint32_t *)key; | |
60322b39 | 219 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 | 220 | |
7a0e58fa | 221 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
222 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); |
223 | /* The value array need not be initialized at this point */ | |
224 | cpu->cpreg_array_len++; | |
225 | } | |
226 | } | |
227 | ||
228 | static void count_cpreg(gpointer key, gpointer opaque) | |
229 | { | |
230 | ARMCPU *cpu = opaque; | |
231 | uint64_t regidx; | |
232 | const ARMCPRegInfo *ri; | |
233 | ||
234 | regidx = *(uint32_t *)key; | |
60322b39 | 235 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 | 236 | |
7a0e58fa | 237 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
238 | cpu->cpreg_array_len++; |
239 | } | |
240 | } | |
241 | ||
242 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | |
243 | { | |
cbf239b7 AR |
244 | uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); |
245 | uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); | |
721fae12 | 246 | |
cbf239b7 AR |
247 | if (aidx > bidx) { |
248 | return 1; | |
249 | } | |
250 | if (aidx < bidx) { | |
251 | return -1; | |
252 | } | |
253 | return 0; | |
721fae12 PM |
254 | } |
255 | ||
256 | void init_cpreg_list(ARMCPU *cpu) | |
257 | { | |
258 | /* Initialise the cpreg_tuples[] array based on the cp_regs hash. | |
259 | * Note that we require cpreg_tuples[] to be sorted by key ID. | |
260 | */ | |
57b6d95e | 261 | GList *keys; |
721fae12 PM |
262 | int arraylen; |
263 | ||
57b6d95e | 264 | keys = g_hash_table_get_keys(cpu->cp_regs); |
721fae12 PM |
265 | keys = g_list_sort(keys, cpreg_key_compare); |
266 | ||
267 | cpu->cpreg_array_len = 0; | |
268 | ||
269 | g_list_foreach(keys, count_cpreg, cpu); | |
270 | ||
271 | arraylen = cpu->cpreg_array_len; | |
272 | cpu->cpreg_indexes = g_new(uint64_t, arraylen); | |
273 | cpu->cpreg_values = g_new(uint64_t, arraylen); | |
274 | cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); | |
275 | cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); | |
276 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; | |
277 | cpu->cpreg_array_len = 0; | |
278 | ||
279 | g_list_foreach(keys, add_cpreg_to_list, cpu); | |
280 | ||
281 | assert(cpu->cpreg_array_len == arraylen); | |
282 | ||
283 | g_list_free(keys); | |
284 | } | |
285 | ||
68e9c2fe | 286 | /* |
93dd1e61 | 287 | * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0. |
68e9c2fe EI |
288 | */ |
289 | static CPAccessResult access_el3_aa32ns(CPUARMState *env, | |
3f208fd7 PM |
290 | const ARMCPRegInfo *ri, |
291 | bool isread) | |
68e9c2fe | 292 | { |
93dd1e61 EI |
293 | if (!is_a64(env) && arm_current_el(env) == 3 && |
294 | arm_is_secure_below_el3(env)) { | |
68e9c2fe EI |
295 | return CP_ACCESS_TRAP_UNCATEGORIZED; |
296 | } | |
297 | return CP_ACCESS_OK; | |
298 | } | |
299 | ||
5513c3ab PM |
300 | /* Some secure-only AArch32 registers trap to EL3 if used from |
301 | * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). | |
302 | * Note that an access from Secure EL1 can only happen if EL3 is AArch64. | |
303 | * We assume that the .access field is set to PL1_RW. | |
304 | */ | |
305 | static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, | |
3f208fd7 PM |
306 | const ARMCPRegInfo *ri, |
307 | bool isread) | |
5513c3ab PM |
308 | { |
309 | if (arm_current_el(env) == 3) { | |
310 | return CP_ACCESS_OK; | |
311 | } | |
312 | if (arm_is_secure_below_el3(env)) { | |
926c1b97 RDC |
313 | if (env->cp15.scr_el3 & SCR_EEL2) { |
314 | return CP_ACCESS_TRAP_EL2; | |
315 | } | |
5513c3ab PM |
316 | return CP_ACCESS_TRAP_EL3; |
317 | } | |
318 | /* This will be EL1 NS and EL2 NS, which just UNDEF */ | |
319 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
320 | } | |
321 | ||
59dd089c RDC |
322 | static uint64_t arm_mdcr_el2_eff(CPUARMState *env) |
323 | { | |
324 | return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0; | |
325 | } | |
326 | ||
187f678d PM |
327 | /* Check for traps to "powerdown debug" registers, which are controlled |
328 | * by MDCR.TDOSA | |
329 | */ | |
330 | static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, | |
331 | bool isread) | |
332 | { | |
333 | int el = arm_current_el(env); | |
59dd089c RDC |
334 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
335 | bool mdcr_el2_tdosa = (mdcr_el2 & MDCR_TDOSA) || (mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 336 | (arm_hcr_el2_eff(env) & HCR_TGE); |
187f678d | 337 | |
59dd089c | 338 | if (el < 2 && mdcr_el2_tdosa) { |
187f678d PM |
339 | return CP_ACCESS_TRAP_EL2; |
340 | } | |
341 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { | |
342 | return CP_ACCESS_TRAP_EL3; | |
343 | } | |
344 | return CP_ACCESS_OK; | |
345 | } | |
346 | ||
91b0a238 PM |
347 | /* Check for traps to "debug ROM" registers, which are controlled |
348 | * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. | |
349 | */ | |
350 | static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, | |
351 | bool isread) | |
352 | { | |
353 | int el = arm_current_el(env); | |
59dd089c RDC |
354 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
355 | bool mdcr_el2_tdra = (mdcr_el2 & MDCR_TDRA) || (mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 356 | (arm_hcr_el2_eff(env) & HCR_TGE); |
91b0a238 | 357 | |
59dd089c | 358 | if (el < 2 && mdcr_el2_tdra) { |
91b0a238 PM |
359 | return CP_ACCESS_TRAP_EL2; |
360 | } | |
361 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
362 | return CP_ACCESS_TRAP_EL3; | |
363 | } | |
364 | return CP_ACCESS_OK; | |
365 | } | |
366 | ||
d6c8cf81 PM |
367 | /* Check for traps to general debug registers, which are controlled |
368 | * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. | |
369 | */ | |
370 | static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, | |
371 | bool isread) | |
372 | { | |
373 | int el = arm_current_el(env); | |
59dd089c RDC |
374 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
375 | bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 376 | (arm_hcr_el2_eff(env) & HCR_TGE); |
d6c8cf81 | 377 | |
59dd089c | 378 | if (el < 2 && mdcr_el2_tda) { |
d6c8cf81 PM |
379 | return CP_ACCESS_TRAP_EL2; |
380 | } | |
381 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
382 | return CP_ACCESS_TRAP_EL3; | |
383 | } | |
384 | return CP_ACCESS_OK; | |
385 | } | |
386 | ||
1fce1ba9 PM |
387 | /* Check for traps to performance monitor registers, which are controlled |
388 | * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. | |
389 | */ | |
390 | static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, | |
391 | bool isread) | |
392 | { | |
393 | int el = arm_current_el(env); | |
59dd089c | 394 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
1fce1ba9 | 395 | |
59dd089c | 396 | if (el < 2 && (mdcr_el2 & MDCR_TPM)) { |
1fce1ba9 PM |
397 | return CP_ACCESS_TRAP_EL2; |
398 | } | |
399 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
400 | return CP_ACCESS_TRAP_EL3; | |
401 | } | |
402 | return CP_ACCESS_OK; | |
403 | } | |
404 | ||
84929218 RH |
405 | /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ |
406 | static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, | |
407 | bool isread) | |
408 | { | |
409 | if (arm_current_el(env) == 1) { | |
410 | uint64_t trap = isread ? HCR_TRVM : HCR_TVM; | |
411 | if (arm_hcr_el2_eff(env) & trap) { | |
412 | return CP_ACCESS_TRAP_EL2; | |
413 | } | |
414 | } | |
415 | return CP_ACCESS_OK; | |
416 | } | |
417 | ||
1803d271 RH |
418 | /* Check for traps from EL1 due to HCR_EL2.TSW. */ |
419 | static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri, | |
420 | bool isread) | |
421 | { | |
422 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) { | |
423 | return CP_ACCESS_TRAP_EL2; | |
424 | } | |
425 | return CP_ACCESS_OK; | |
426 | } | |
427 | ||
99602377 RH |
428 | /* Check for traps from EL1 due to HCR_EL2.TACR. */ |
429 | static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri, | |
430 | bool isread) | |
431 | { | |
432 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TACR)) { | |
433 | return CP_ACCESS_TRAP_EL2; | |
434 | } | |
435 | return CP_ACCESS_OK; | |
436 | } | |
437 | ||
30881b73 RH |
438 | /* Check for traps from EL1 due to HCR_EL2.TTLB. */ |
439 | static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri, | |
440 | bool isread) | |
441 | { | |
442 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TTLB)) { | |
443 | return CP_ACCESS_TRAP_EL2; | |
444 | } | |
445 | return CP_ACCESS_OK; | |
446 | } | |
447 | ||
c4241c7d | 448 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
c983fe6c | 449 | { |
2fc0cc0e | 450 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 451 | |
8d5c773e | 452 | raw_write(env, ri, value); |
d10eb08f | 453 | tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ |
c983fe6c PM |
454 | } |
455 | ||
c4241c7d | 456 | static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
08de207b | 457 | { |
2fc0cc0e | 458 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 459 | |
8d5c773e | 460 | if (raw_read(env, ri) != value) { |
08de207b PM |
461 | /* Unlike real hardware the qemu TLB uses virtual addresses, |
462 | * not modified virtual addresses, so this causes a TLB flush. | |
463 | */ | |
d10eb08f | 464 | tlb_flush(CPU(cpu)); |
8d5c773e | 465 | raw_write(env, ri, value); |
08de207b | 466 | } |
08de207b | 467 | } |
c4241c7d PM |
468 | |
469 | static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
470 | uint64_t value) | |
08de207b | 471 | { |
2fc0cc0e | 472 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 473 | |
452a0955 | 474 | if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) |
014406b5 | 475 | && !extended_addresses_enabled(env)) { |
08de207b PM |
476 | /* For VMSA (when not using the LPAE long descriptor page table |
477 | * format) this register includes the ASID, so do a TLB flush. | |
478 | * For PMSA it is purely a process ID and no action is needed. | |
479 | */ | |
d10eb08f | 480 | tlb_flush(CPU(cpu)); |
08de207b | 481 | } |
8d5c773e | 482 | raw_write(env, ri, value); |
08de207b PM |
483 | } |
484 | ||
b4ab8ce9 PM |
485 | /* IS variants of TLB operations must affect all cores */ |
486 | static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
487 | uint64_t value) | |
488 | { | |
29a0af61 | 489 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
490 | |
491 | tlb_flush_all_cpus_synced(cs); | |
492 | } | |
493 | ||
494 | static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
495 | uint64_t value) | |
496 | { | |
29a0af61 | 497 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
498 | |
499 | tlb_flush_all_cpus_synced(cs); | |
500 | } | |
501 | ||
502 | static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
503 | uint64_t value) | |
504 | { | |
29a0af61 | 505 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
506 | |
507 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
508 | } | |
509 | ||
510 | static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
511 | uint64_t value) | |
512 | { | |
29a0af61 | 513 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
514 | |
515 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
516 | } | |
517 | ||
518 | /* | |
519 | * Non-IS variants of TLB operations are upgraded to | |
373e7ffd | 520 | * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to |
b4ab8ce9 PM |
521 | * force broadcast of these operations. |
522 | */ | |
523 | static bool tlb_force_broadcast(CPUARMState *env) | |
524 | { | |
373e7ffd | 525 | return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB); |
b4ab8ce9 PM |
526 | } |
527 | ||
c4241c7d PM |
528 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
529 | uint64_t value) | |
d929823f PM |
530 | { |
531 | /* Invalidate all (TLBIALL) */ | |
527db2be | 532 | CPUState *cs = env_cpu(env); |
00c8cb0a | 533 | |
b4ab8ce9 | 534 | if (tlb_force_broadcast(env)) { |
527db2be RH |
535 | tlb_flush_all_cpus_synced(cs); |
536 | } else { | |
537 | tlb_flush(cs); | |
b4ab8ce9 | 538 | } |
d929823f PM |
539 | } |
540 | ||
c4241c7d PM |
541 | static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
542 | uint64_t value) | |
d929823f PM |
543 | { |
544 | /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ | |
527db2be | 545 | CPUState *cs = env_cpu(env); |
31b030d4 | 546 | |
527db2be | 547 | value &= TARGET_PAGE_MASK; |
b4ab8ce9 | 548 | if (tlb_force_broadcast(env)) { |
527db2be RH |
549 | tlb_flush_page_all_cpus_synced(cs, value); |
550 | } else { | |
551 | tlb_flush_page(cs, value); | |
b4ab8ce9 | 552 | } |
d929823f PM |
553 | } |
554 | ||
c4241c7d PM |
555 | static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
556 | uint64_t value) | |
d929823f PM |
557 | { |
558 | /* Invalidate by ASID (TLBIASID) */ | |
527db2be | 559 | CPUState *cs = env_cpu(env); |
00c8cb0a | 560 | |
b4ab8ce9 | 561 | if (tlb_force_broadcast(env)) { |
527db2be RH |
562 | tlb_flush_all_cpus_synced(cs); |
563 | } else { | |
564 | tlb_flush(cs); | |
b4ab8ce9 | 565 | } |
d929823f PM |
566 | } |
567 | ||
c4241c7d PM |
568 | static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
569 | uint64_t value) | |
d929823f PM |
570 | { |
571 | /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ | |
527db2be | 572 | CPUState *cs = env_cpu(env); |
31b030d4 | 573 | |
527db2be | 574 | value &= TARGET_PAGE_MASK; |
b4ab8ce9 | 575 | if (tlb_force_broadcast(env)) { |
527db2be RH |
576 | tlb_flush_page_all_cpus_synced(cs, value); |
577 | } else { | |
578 | tlb_flush_page(cs, value); | |
b4ab8ce9 | 579 | } |
fa439fc5 PM |
580 | } |
581 | ||
541ef8c2 SS |
582 | static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, |
583 | uint64_t value) | |
584 | { | |
29a0af61 | 585 | CPUState *cs = env_cpu(env); |
541ef8c2 | 586 | |
0336cbf8 | 587 | tlb_flush_by_mmuidx(cs, |
01b98b68 | 588 | ARMMMUIdxBit_E10_1 | |
452ef8cb | 589 | ARMMMUIdxBit_E10_1_PAN | |
bf05340c | 590 | ARMMMUIdxBit_E10_0); |
541ef8c2 SS |
591 | } |
592 | ||
593 | static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
594 | uint64_t value) | |
595 | { | |
29a0af61 | 596 | CPUState *cs = env_cpu(env); |
541ef8c2 | 597 | |
a67cf277 | 598 | tlb_flush_by_mmuidx_all_cpus_synced(cs, |
01b98b68 | 599 | ARMMMUIdxBit_E10_1 | |
452ef8cb | 600 | ARMMMUIdxBit_E10_1_PAN | |
bf05340c | 601 | ARMMMUIdxBit_E10_0); |
541ef8c2 SS |
602 | } |
603 | ||
541ef8c2 SS |
604 | |
605 | static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
606 | uint64_t value) | |
607 | { | |
29a0af61 | 608 | CPUState *cs = env_cpu(env); |
541ef8c2 | 609 | |
e013b741 | 610 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); |
541ef8c2 SS |
611 | } |
612 | ||
613 | static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
614 | uint64_t value) | |
615 | { | |
29a0af61 | 616 | CPUState *cs = env_cpu(env); |
541ef8c2 | 617 | |
e013b741 | 618 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); |
541ef8c2 SS |
619 | } |
620 | ||
621 | static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
622 | uint64_t value) | |
623 | { | |
29a0af61 | 624 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
625 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
626 | ||
e013b741 | 627 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); |
541ef8c2 SS |
628 | } |
629 | ||
630 | static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
631 | uint64_t value) | |
632 | { | |
29a0af61 | 633 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
634 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
635 | ||
a67cf277 | 636 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
e013b741 | 637 | ARMMMUIdxBit_E2); |
541ef8c2 SS |
638 | } |
639 | ||
e9aa6c21 | 640 | static const ARMCPRegInfo cp_reginfo[] = { |
54bf36ed FA |
641 | /* Define the secure and non-secure FCSE identifier CP registers |
642 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
643 | * the secure register to be properly reset and migrated. There is also no | |
644 | * v8 EL1 version of the register so the non-secure instance stands alone. | |
645 | */ | |
9c513e78 | 646 | { .name = "FCSEIDR", |
54bf36ed FA |
647 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
648 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, | |
649 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), | |
650 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, | |
9c513e78 | 651 | { .name = "FCSEIDR_S", |
54bf36ed FA |
652 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
653 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
654 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), | |
d4e6df63 | 655 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, |
54bf36ed FA |
656 | /* Define the secure and non-secure context identifier CP registers |
657 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
658 | * the secure register to be properly reset and migrated. In the | |
659 | * non-secure case, the 32-bit register will have reset and migration | |
660 | * disabled during registration as it is handled by the 64-bit instance. | |
661 | */ | |
662 | { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
014406b5 | 663 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
84929218 RH |
664 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
665 | .secure = ARM_CP_SECSTATE_NS, | |
54bf36ed FA |
666 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), |
667 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, | |
9c513e78 | 668 | { .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32, |
54bf36ed | 669 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
84929218 RH |
670 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
671 | .secure = ARM_CP_SECSTATE_S, | |
54bf36ed | 672 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), |
d4e6df63 | 673 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, |
9449fdf6 PM |
674 | REGINFO_SENTINEL |
675 | }; | |
676 | ||
677 | static const ARMCPRegInfo not_v8_cp_reginfo[] = { | |
678 | /* NB: Some of these registers exist in v8 but with more precise | |
679 | * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). | |
680 | */ | |
681 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
682 | { .name = "DACR", |
683 | .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, | |
84929218 | 684 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
0c17d68c FA |
685 | .writefn = dacr_write, .raw_writefn = raw_write, |
686 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
687 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a903c449 EI |
688 | /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. |
689 | * For v6 and v5, these mappings are overly broad. | |
4fdd17dd | 690 | */ |
a903c449 EI |
691 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0, |
692 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
693 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1, | |
694 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
695 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4, | |
696 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
697 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8, | |
4fdd17dd | 698 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, |
c4804214 PM |
699 | /* Cache maintenance ops; some of this space may be overridden later. */ |
700 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | |
701 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | |
702 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | |
e9aa6c21 PM |
703 | REGINFO_SENTINEL |
704 | }; | |
705 | ||
7d57f408 PM |
706 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
707 | /* Not all pre-v6 cores implemented this WFI, so this is slightly | |
708 | * over-broad. | |
709 | */ | |
710 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | |
711 | .access = PL1_W, .type = ARM_CP_WFI }, | |
712 | REGINFO_SENTINEL | |
713 | }; | |
714 | ||
715 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | |
716 | /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which | |
717 | * is UNPREDICTABLE; we choose to NOP as most implementations do). | |
718 | */ | |
719 | { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
720 | .access = PL1_W, .type = ARM_CP_WFI }, | |
34f90529 PM |
721 | /* L1 cache lockdown. Not architectural in v6 and earlier but in practice |
722 | * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and | |
723 | * OMAPCP will override this space. | |
724 | */ | |
725 | { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, | |
726 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), | |
727 | .resetvalue = 0 }, | |
728 | { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, | |
729 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), | |
730 | .resetvalue = 0 }, | |
776d4e5c PM |
731 | /* v6 doesn't have the cache ID registers but Linux reads them anyway */ |
732 | { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, | |
7a0e58fa | 733 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 734 | .resetvalue = 0 }, |
50300698 PM |
735 | /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; |
736 | * implementing it as RAZ means the "debug architecture version" bits | |
737 | * will read as a reserved value, which should cause Linux to not try | |
738 | * to use the debug hardware. | |
739 | */ | |
740 | { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
741 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
995939a6 PM |
742 | /* MMU TLB control. Note that the wildcarding means we cover not just |
743 | * the unified TLB ops but also the dside/iside/inner-shareable variants. | |
744 | */ | |
745 | { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, | |
746 | .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, | |
7a0e58fa | 747 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
748 | { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, |
749 | .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, | |
7a0e58fa | 750 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
751 | { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, |
752 | .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, | |
7a0e58fa | 753 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
754 | { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, |
755 | .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, | |
7a0e58fa | 756 | .type = ARM_CP_NO_RAW }, |
a903c449 EI |
757 | { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2, |
758 | .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, | |
759 | { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, | |
760 | .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, | |
7d57f408 PM |
761 | REGINFO_SENTINEL |
762 | }; | |
763 | ||
c4241c7d PM |
764 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
765 | uint64_t value) | |
2771db27 | 766 | { |
f0aff255 FA |
767 | uint32_t mask = 0; |
768 | ||
769 | /* In ARMv8 most bits of CPACR_EL1 are RES0. */ | |
770 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
771 | /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. | |
772 | * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. | |
773 | * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. | |
774 | */ | |
7fbc6a40 | 775 | if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { |
f0aff255 FA |
776 | /* VFP coprocessor: cp10 & cp11 [23:20] */ |
777 | mask |= (1 << 31) | (1 << 30) | (0xf << 20); | |
778 | ||
779 | if (!arm_feature(env, ARM_FEATURE_NEON)) { | |
780 | /* ASEDIS [31] bit is RAO/WI */ | |
781 | value |= (1 << 31); | |
782 | } | |
783 | ||
784 | /* VFPv3 and upwards with NEON implement 32 double precision | |
785 | * registers (D0-D31). | |
786 | */ | |
a6627f5f | 787 | if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { |
f0aff255 FA |
788 | /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ |
789 | value |= (1 << 30); | |
790 | } | |
791 | } | |
792 | value &= mask; | |
2771db27 | 793 | } |
fc1120a7 PM |
794 | |
795 | /* | |
796 | * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 | |
797 | * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. | |
798 | */ | |
799 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
800 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
801 | value &= ~(0xf << 20); | |
802 | value |= env->cp15.cpacr_el1 & (0xf << 20); | |
803 | } | |
804 | ||
7ebd5f2e | 805 | env->cp15.cpacr_el1 = value; |
2771db27 PM |
806 | } |
807 | ||
fc1120a7 PM |
808 | static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
809 | { | |
810 | /* | |
811 | * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 | |
812 | * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. | |
813 | */ | |
814 | uint64_t value = env->cp15.cpacr_el1; | |
815 | ||
816 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
817 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
818 | value &= ~(0xf << 20); | |
819 | } | |
820 | return value; | |
821 | } | |
822 | ||
823 | ||
5deac39c PM |
824 | static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
825 | { | |
826 | /* Call cpacr_write() so that we reset with the correct RAO bits set | |
827 | * for our CPU features. | |
828 | */ | |
829 | cpacr_write(env, ri, 0); | |
830 | } | |
831 | ||
3f208fd7 PM |
832 | static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
833 | bool isread) | |
c6f19164 GB |
834 | { |
835 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
836 | /* Check if CPACR accesses are to be trapped to EL2 */ | |
e6ef0169 RDC |
837 | if (arm_current_el(env) == 1 && arm_is_el2_enabled(env) && |
838 | (env->cp15.cptr_el[2] & CPTR_TCPAC)) { | |
c6f19164 GB |
839 | return CP_ACCESS_TRAP_EL2; |
840 | /* Check if CPACR accesses are to be trapped to EL3 */ | |
841 | } else if (arm_current_el(env) < 3 && | |
842 | (env->cp15.cptr_el[3] & CPTR_TCPAC)) { | |
843 | return CP_ACCESS_TRAP_EL3; | |
844 | } | |
845 | } | |
846 | ||
847 | return CP_ACCESS_OK; | |
848 | } | |
849 | ||
3f208fd7 PM |
850 | static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
851 | bool isread) | |
c6f19164 GB |
852 | { |
853 | /* Check if CPTR accesses are set to trap to EL3 */ | |
854 | if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) { | |
855 | return CP_ACCESS_TRAP_EL3; | |
856 | } | |
857 | ||
858 | return CP_ACCESS_OK; | |
859 | } | |
860 | ||
7d57f408 PM |
861 | static const ARMCPRegInfo v6_cp_reginfo[] = { |
862 | /* prefetch by MVA in v6, NOP in v7 */ | |
863 | { .name = "MVA_prefetch", | |
864 | .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, | |
865 | .access = PL1_W, .type = ARM_CP_NOP }, | |
6df99dec SS |
866 | /* We need to break the TB after ISB to execute self-modifying code |
867 | * correctly and also to take any pending interrupts immediately. | |
868 | * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. | |
869 | */ | |
7d57f408 | 870 | { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, |
6df99dec | 871 | .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, |
091fd17c | 872 | { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
7d57f408 | 873 | .access = PL0_W, .type = ARM_CP_NOP }, |
091fd17c | 874 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
7d57f408 | 875 | .access = PL0_W, .type = ARM_CP_NOP }, |
06d76f31 | 876 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
84929218 | 877 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
b848ce2b FA |
878 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), |
879 | offsetof(CPUARMState, cp15.ifar_ns) }, | |
06d76f31 PM |
880 | .resetvalue = 0, }, |
881 | /* Watchpoint Fault Address Register : should actually only be present | |
882 | * for 1136, 1176, 11MPCore. | |
883 | */ | |
884 | { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
885 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, | |
34222fb8 | 886 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, |
c6f19164 | 887 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, |
7ebd5f2e | 888 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), |
fc1120a7 | 889 | .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read }, |
7d57f408 PM |
890 | REGINFO_SENTINEL |
891 | }; | |
892 | ||
57a4a11b AL |
893 | typedef struct pm_event { |
894 | uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ | |
895 | /* If the event is supported on this CPU (used to generate PMCEID[01]) */ | |
896 | bool (*supported)(CPUARMState *); | |
897 | /* | |
898 | * Retrieve the current count of the underlying event. The programmed | |
899 | * counters hold a difference from the return value from this function | |
900 | */ | |
901 | uint64_t (*get_count)(CPUARMState *); | |
4e7beb0c AL |
902 | /* |
903 | * Return how many nanoseconds it will take (at a minimum) for count events | |
904 | * to occur. A negative value indicates the counter will never overflow, or | |
905 | * that the counter has otherwise arranged for the overflow bit to be set | |
906 | * and the PMU interrupt to be raised on overflow. | |
907 | */ | |
908 | int64_t (*ns_per_count)(uint64_t); | |
57a4a11b AL |
909 | } pm_event; |
910 | ||
b2e23725 AL |
911 | static bool event_always_supported(CPUARMState *env) |
912 | { | |
913 | return true; | |
914 | } | |
915 | ||
0d4bfd7d AL |
916 | static uint64_t swinc_get_count(CPUARMState *env) |
917 | { | |
918 | /* | |
919 | * SW_INCR events are written directly to the pmevcntr's by writes to | |
920 | * PMSWINC, so there is no underlying count maintained by the PMU itself | |
921 | */ | |
922 | return 0; | |
923 | } | |
924 | ||
4e7beb0c AL |
925 | static int64_t swinc_ns_per(uint64_t ignored) |
926 | { | |
927 | return -1; | |
928 | } | |
929 | ||
b2e23725 AL |
930 | /* |
931 | * Return the underlying cycle count for the PMU cycle counters. If we're in | |
932 | * usermode, simply return 0. | |
933 | */ | |
934 | static uint64_t cycles_get_count(CPUARMState *env) | |
935 | { | |
936 | #ifndef CONFIG_USER_ONLY | |
937 | return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
938 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); | |
939 | #else | |
940 | return cpu_get_host_ticks(); | |
941 | #endif | |
942 | } | |
943 | ||
944 | #ifndef CONFIG_USER_ONLY | |
4e7beb0c AL |
945 | static int64_t cycles_ns_per(uint64_t cycles) |
946 | { | |
947 | return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles; | |
948 | } | |
949 | ||
b2e23725 AL |
950 | static bool instructions_supported(CPUARMState *env) |
951 | { | |
740b1759 | 952 | return icount_enabled() == 1; /* Precise instruction counting */ |
b2e23725 AL |
953 | } |
954 | ||
955 | static uint64_t instructions_get_count(CPUARMState *env) | |
956 | { | |
8191d368 | 957 | return (uint64_t)icount_get_raw(); |
b2e23725 | 958 | } |
4e7beb0c AL |
959 | |
960 | static int64_t instructions_ns_per(uint64_t icount) | |
961 | { | |
8191d368 | 962 | return icount_to_ns((int64_t)icount); |
4e7beb0c | 963 | } |
b2e23725 AL |
964 | #endif |
965 | ||
0727f63b PM |
966 | static bool pmu_8_1_events_supported(CPUARMState *env) |
967 | { | |
968 | /* For events which are supported in any v8.1 PMU */ | |
969 | return cpu_isar_feature(any_pmu_8_1, env_archcpu(env)); | |
970 | } | |
971 | ||
15dd1ebd PM |
972 | static bool pmu_8_4_events_supported(CPUARMState *env) |
973 | { | |
974 | /* For events which are supported in any v8.1 PMU */ | |
975 | return cpu_isar_feature(any_pmu_8_4, env_archcpu(env)); | |
976 | } | |
977 | ||
0727f63b PM |
978 | static uint64_t zero_event_get_count(CPUARMState *env) |
979 | { | |
980 | /* For events which on QEMU never fire, so their count is always zero */ | |
981 | return 0; | |
982 | } | |
983 | ||
984 | static int64_t zero_event_ns_per(uint64_t cycles) | |
985 | { | |
986 | /* An event which never fires can never overflow */ | |
987 | return -1; | |
988 | } | |
989 | ||
57a4a11b | 990 | static const pm_event pm_events[] = { |
0d4bfd7d AL |
991 | { .number = 0x000, /* SW_INCR */ |
992 | .supported = event_always_supported, | |
993 | .get_count = swinc_get_count, | |
4e7beb0c | 994 | .ns_per_count = swinc_ns_per, |
0d4bfd7d | 995 | }, |
b2e23725 AL |
996 | #ifndef CONFIG_USER_ONLY |
997 | { .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */ | |
998 | .supported = instructions_supported, | |
999 | .get_count = instructions_get_count, | |
4e7beb0c | 1000 | .ns_per_count = instructions_ns_per, |
b2e23725 AL |
1001 | }, |
1002 | { .number = 0x011, /* CPU_CYCLES, Cycle */ | |
1003 | .supported = event_always_supported, | |
1004 | .get_count = cycles_get_count, | |
4e7beb0c | 1005 | .ns_per_count = cycles_ns_per, |
0727f63b | 1006 | }, |
b2e23725 | 1007 | #endif |
0727f63b PM |
1008 | { .number = 0x023, /* STALL_FRONTEND */ |
1009 | .supported = pmu_8_1_events_supported, | |
1010 | .get_count = zero_event_get_count, | |
1011 | .ns_per_count = zero_event_ns_per, | |
1012 | }, | |
1013 | { .number = 0x024, /* STALL_BACKEND */ | |
1014 | .supported = pmu_8_1_events_supported, | |
1015 | .get_count = zero_event_get_count, | |
1016 | .ns_per_count = zero_event_ns_per, | |
1017 | }, | |
15dd1ebd PM |
1018 | { .number = 0x03c, /* STALL */ |
1019 | .supported = pmu_8_4_events_supported, | |
1020 | .get_count = zero_event_get_count, | |
1021 | .ns_per_count = zero_event_ns_per, | |
1022 | }, | |
57a4a11b AL |
1023 | }; |
1024 | ||
1025 | /* | |
1026 | * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of | |
1027 | * events (i.e. the statistical profiling extension), this implementation | |
1028 | * should first be updated to something sparse instead of the current | |
1029 | * supported_event_map[] array. | |
1030 | */ | |
15dd1ebd | 1031 | #define MAX_EVENT_ID 0x3c |
57a4a11b AL |
1032 | #define UNSUPPORTED_EVENT UINT16_MAX |
1033 | static uint16_t supported_event_map[MAX_EVENT_ID + 1]; | |
1034 | ||
1035 | /* | |
bf8d0969 AL |
1036 | * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map |
1037 | * of ARM event numbers to indices in our pm_events array. | |
57a4a11b AL |
1038 | * |
1039 | * Note: Events in the 0x40XX range are not currently supported. | |
1040 | */ | |
bf8d0969 | 1041 | void pmu_init(ARMCPU *cpu) |
57a4a11b | 1042 | { |
57a4a11b AL |
1043 | unsigned int i; |
1044 | ||
bf8d0969 AL |
1045 | /* |
1046 | * Empty supported_event_map and cpu->pmceid[01] before adding supported | |
1047 | * events to them | |
1048 | */ | |
57a4a11b AL |
1049 | for (i = 0; i < ARRAY_SIZE(supported_event_map); i++) { |
1050 | supported_event_map[i] = UNSUPPORTED_EVENT; | |
1051 | } | |
bf8d0969 AL |
1052 | cpu->pmceid0 = 0; |
1053 | cpu->pmceid1 = 0; | |
57a4a11b AL |
1054 | |
1055 | for (i = 0; i < ARRAY_SIZE(pm_events); i++) { | |
1056 | const pm_event *cnt = &pm_events[i]; | |
1057 | assert(cnt->number <= MAX_EVENT_ID); | |
1058 | /* We do not currently support events in the 0x40xx range */ | |
1059 | assert(cnt->number <= 0x3f); | |
1060 | ||
bf8d0969 | 1061 | if (cnt->supported(&cpu->env)) { |
57a4a11b | 1062 | supported_event_map[cnt->number] = i; |
67da43d6 | 1063 | uint64_t event_mask = 1ULL << (cnt->number & 0x1f); |
bf8d0969 AL |
1064 | if (cnt->number & 0x20) { |
1065 | cpu->pmceid1 |= event_mask; | |
1066 | } else { | |
1067 | cpu->pmceid0 |= event_mask; | |
1068 | } | |
57a4a11b AL |
1069 | } |
1070 | } | |
57a4a11b AL |
1071 | } |
1072 | ||
5ecdd3e4 AL |
1073 | /* |
1074 | * Check at runtime whether a PMU event is supported for the current machine | |
1075 | */ | |
1076 | static bool event_supported(uint16_t number) | |
1077 | { | |
1078 | if (number > MAX_EVENT_ID) { | |
1079 | return false; | |
1080 | } | |
1081 | return supported_event_map[number] != UNSUPPORTED_EVENT; | |
1082 | } | |
1083 | ||
3f208fd7 PM |
1084 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1085 | bool isread) | |
200ac0ef | 1086 | { |
3b163b01 | 1087 | /* Performance monitor registers user accessibility is controlled |
1fce1ba9 PM |
1088 | * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable |
1089 | * trapping to EL2 or EL3 for other accesses. | |
200ac0ef | 1090 | */ |
1fce1ba9 | 1091 | int el = arm_current_el(env); |
59dd089c | 1092 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
1fce1ba9 | 1093 | |
6ecd0b6b | 1094 | if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { |
fcd25206 | 1095 | return CP_ACCESS_TRAP; |
200ac0ef | 1096 | } |
59dd089c | 1097 | if (el < 2 && (mdcr_el2 & MDCR_TPM)) { |
1fce1ba9 PM |
1098 | return CP_ACCESS_TRAP_EL2; |
1099 | } | |
1100 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
1101 | return CP_ACCESS_TRAP_EL3; | |
1102 | } | |
1103 | ||
fcd25206 | 1104 | return CP_ACCESS_OK; |
200ac0ef PM |
1105 | } |
1106 | ||
6ecd0b6b AB |
1107 | static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, |
1108 | const ARMCPRegInfo *ri, | |
1109 | bool isread) | |
1110 | { | |
1111 | /* ER: event counter read trap control */ | |
1112 | if (arm_feature(env, ARM_FEATURE_V8) | |
1113 | && arm_current_el(env) == 0 | |
1114 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 | |
1115 | && isread) { | |
1116 | return CP_ACCESS_OK; | |
1117 | } | |
1118 | ||
1119 | return pmreg_access(env, ri, isread); | |
1120 | } | |
1121 | ||
1122 | static CPAccessResult pmreg_access_swinc(CPUARMState *env, | |
1123 | const ARMCPRegInfo *ri, | |
1124 | bool isread) | |
1125 | { | |
1126 | /* SW: software increment write trap control */ | |
1127 | if (arm_feature(env, ARM_FEATURE_V8) | |
1128 | && arm_current_el(env) == 0 | |
1129 | && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 | |
1130 | && !isread) { | |
1131 | return CP_ACCESS_OK; | |
1132 | } | |
1133 | ||
1134 | return pmreg_access(env, ri, isread); | |
1135 | } | |
1136 | ||
6ecd0b6b AB |
1137 | static CPAccessResult pmreg_access_selr(CPUARMState *env, |
1138 | const ARMCPRegInfo *ri, | |
1139 | bool isread) | |
1140 | { | |
1141 | /* ER: event counter read trap control */ | |
1142 | if (arm_feature(env, ARM_FEATURE_V8) | |
1143 | && arm_current_el(env) == 0 | |
1144 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { | |
1145 | return CP_ACCESS_OK; | |
1146 | } | |
1147 | ||
1148 | return pmreg_access(env, ri, isread); | |
1149 | } | |
1150 | ||
1151 | static CPAccessResult pmreg_access_ccntr(CPUARMState *env, | |
1152 | const ARMCPRegInfo *ri, | |
1153 | bool isread) | |
1154 | { | |
1155 | /* CR: cycle counter read trap control */ | |
1156 | if (arm_feature(env, ARM_FEATURE_V8) | |
1157 | && arm_current_el(env) == 0 | |
1158 | && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 | |
1159 | && isread) { | |
1160 | return CP_ACCESS_OK; | |
1161 | } | |
1162 | ||
1163 | return pmreg_access(env, ri, isread); | |
1164 | } | |
1165 | ||
033614c4 AL |
1166 | /* Returns true if the counter (pass 31 for PMCCNTR) should count events using |
1167 | * the current EL, security state, and register configuration. | |
1168 | */ | |
1169 | static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) | |
87124fde | 1170 | { |
033614c4 AL |
1171 | uint64_t filter; |
1172 | bool e, p, u, nsk, nsu, nsh, m; | |
1173 | bool enabled, prohibited, filtered; | |
1174 | bool secure = arm_is_secure(env); | |
1175 | int el = arm_current_el(env); | |
59dd089c RDC |
1176 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
1177 | uint8_t hpmn = mdcr_el2 & MDCR_HPMN; | |
87124fde | 1178 | |
cbbb3041 AJ |
1179 | if (!arm_feature(env, ARM_FEATURE_PMU)) { |
1180 | return false; | |
1181 | } | |
1182 | ||
033614c4 AL |
1183 | if (!arm_feature(env, ARM_FEATURE_EL2) || |
1184 | (counter < hpmn || counter == 31)) { | |
1185 | e = env->cp15.c9_pmcr & PMCRE; | |
1186 | } else { | |
59dd089c | 1187 | e = mdcr_el2 & MDCR_HPME; |
87124fde | 1188 | } |
033614c4 | 1189 | enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); |
87124fde | 1190 | |
033614c4 AL |
1191 | if (!secure) { |
1192 | if (el == 2 && (counter < hpmn || counter == 31)) { | |
59dd089c | 1193 | prohibited = mdcr_el2 & MDCR_HPMD; |
033614c4 AL |
1194 | } else { |
1195 | prohibited = false; | |
1196 | } | |
1197 | } else { | |
1198 | prohibited = arm_feature(env, ARM_FEATURE_EL3) && | |
db1f3afb | 1199 | !(env->cp15.mdcr_el3 & MDCR_SPME); |
033614c4 AL |
1200 | } |
1201 | ||
1202 | if (prohibited && counter == 31) { | |
1203 | prohibited = env->cp15.c9_pmcr & PMCRDP; | |
1204 | } | |
1205 | ||
5ecdd3e4 AL |
1206 | if (counter == 31) { |
1207 | filter = env->cp15.pmccfiltr_el0; | |
1208 | } else { | |
1209 | filter = env->cp15.c14_pmevtyper[counter]; | |
1210 | } | |
033614c4 AL |
1211 | |
1212 | p = filter & PMXEVTYPER_P; | |
1213 | u = filter & PMXEVTYPER_U; | |
1214 | nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); | |
1215 | nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); | |
1216 | nsh = arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); | |
1217 | m = arm_el_is_aa64(env, 1) && | |
1218 | arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); | |
1219 | ||
1220 | if (el == 0) { | |
1221 | filtered = secure ? u : u != nsu; | |
1222 | } else if (el == 1) { | |
1223 | filtered = secure ? p : p != nsk; | |
1224 | } else if (el == 2) { | |
1225 | filtered = !nsh; | |
1226 | } else { /* EL3 */ | |
1227 | filtered = m != p; | |
1228 | } | |
1229 | ||
5ecdd3e4 AL |
1230 | if (counter != 31) { |
1231 | /* | |
1232 | * If not checking PMCCNTR, ensure the counter is setup to an event we | |
1233 | * support | |
1234 | */ | |
1235 | uint16_t event = filter & PMXEVTYPER_EVTCOUNT; | |
1236 | if (!event_supported(event)) { | |
1237 | return false; | |
1238 | } | |
1239 | } | |
1240 | ||
033614c4 | 1241 | return enabled && !prohibited && !filtered; |
87124fde | 1242 | } |
033614c4 | 1243 | |
f4efb4b2 AL |
1244 | static void pmu_update_irq(CPUARMState *env) |
1245 | { | |
2fc0cc0e | 1246 | ARMCPU *cpu = env_archcpu(env); |
f4efb4b2 AL |
1247 | qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && |
1248 | (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); | |
1249 | } | |
1250 | ||
5d05b9d4 AL |
1251 | /* |
1252 | * Ensure c15_ccnt is the guest-visible count so that operations such as | |
1253 | * enabling/disabling the counter or filtering, modifying the count itself, | |
1254 | * etc. can be done logically. This is essentially a no-op if the counter is | |
1255 | * not enabled at the time of the call. | |
1256 | */ | |
f2b2f53f | 1257 | static void pmccntr_op_start(CPUARMState *env) |
ec7b4ce4 | 1258 | { |
b2e23725 | 1259 | uint64_t cycles = cycles_get_count(env); |
ec7b4ce4 | 1260 | |
033614c4 | 1261 | if (pmu_counter_enabled(env, 31)) { |
5d05b9d4 AL |
1262 | uint64_t eff_cycles = cycles; |
1263 | if (env->cp15.c9_pmcr & PMCRD) { | |
1264 | /* Increment once every 64 processor clock cycles */ | |
1265 | eff_cycles /= 64; | |
1266 | } | |
1267 | ||
f4efb4b2 AL |
1268 | uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta; |
1269 | ||
1270 | uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \ | |
1271 | 1ull << 63 : 1ull << 31; | |
1272 | if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { | |
1273 | env->cp15.c9_pmovsr |= (1 << 31); | |
1274 | pmu_update_irq(env); | |
1275 | } | |
1276 | ||
1277 | env->cp15.c15_ccnt = new_pmccntr; | |
ec7b4ce4 | 1278 | } |
5d05b9d4 AL |
1279 | env->cp15.c15_ccnt_delta = cycles; |
1280 | } | |
ec7b4ce4 | 1281 | |
5d05b9d4 AL |
1282 | /* |
1283 | * If PMCCNTR is enabled, recalculate the delta between the clock and the | |
1284 | * guest-visible count. A call to pmccntr_op_finish should follow every call to | |
1285 | * pmccntr_op_start. | |
1286 | */ | |
f2b2f53f | 1287 | static void pmccntr_op_finish(CPUARMState *env) |
5d05b9d4 | 1288 | { |
033614c4 | 1289 | if (pmu_counter_enabled(env, 31)) { |
4e7beb0c AL |
1290 | #ifndef CONFIG_USER_ONLY |
1291 | /* Calculate when the counter will next overflow */ | |
1292 | uint64_t remaining_cycles = -env->cp15.c15_ccnt; | |
1293 | if (!(env->cp15.c9_pmcr & PMCRLC)) { | |
1294 | remaining_cycles = (uint32_t)remaining_cycles; | |
1295 | } | |
1296 | int64_t overflow_in = cycles_ns_per(remaining_cycles); | |
1297 | ||
1298 | if (overflow_in > 0) { | |
1299 | int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
1300 | overflow_in; | |
2fc0cc0e | 1301 | ARMCPU *cpu = env_archcpu(env); |
4e7beb0c AL |
1302 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); |
1303 | } | |
1304 | #endif | |
5d05b9d4 | 1305 | |
4e7beb0c | 1306 | uint64_t prev_cycles = env->cp15.c15_ccnt_delta; |
5d05b9d4 AL |
1307 | if (env->cp15.c9_pmcr & PMCRD) { |
1308 | /* Increment once every 64 processor clock cycles */ | |
1309 | prev_cycles /= 64; | |
1310 | } | |
5d05b9d4 | 1311 | env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt; |
ec7b4ce4 AF |
1312 | } |
1313 | } | |
1314 | ||
5ecdd3e4 AL |
1315 | static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) |
1316 | { | |
1317 | ||
1318 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; | |
1319 | uint64_t count = 0; | |
1320 | if (event_supported(event)) { | |
1321 | uint16_t event_idx = supported_event_map[event]; | |
1322 | count = pm_events[event_idx].get_count(env); | |
1323 | } | |
1324 | ||
1325 | if (pmu_counter_enabled(env, counter)) { | |
f4efb4b2 AL |
1326 | uint32_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter]; |
1327 | ||
1328 | if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & INT32_MIN) { | |
1329 | env->cp15.c9_pmovsr |= (1 << counter); | |
1330 | pmu_update_irq(env); | |
1331 | } | |
1332 | env->cp15.c14_pmevcntr[counter] = new_pmevcntr; | |
5ecdd3e4 AL |
1333 | } |
1334 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1335 | } | |
1336 | ||
1337 | static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) | |
1338 | { | |
1339 | if (pmu_counter_enabled(env, counter)) { | |
4e7beb0c AL |
1340 | #ifndef CONFIG_USER_ONLY |
1341 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; | |
1342 | uint16_t event_idx = supported_event_map[event]; | |
1343 | uint64_t delta = UINT32_MAX - | |
1344 | (uint32_t)env->cp15.c14_pmevcntr[counter] + 1; | |
1345 | int64_t overflow_in = pm_events[event_idx].ns_per_count(delta); | |
1346 | ||
1347 | if (overflow_in > 0) { | |
1348 | int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
1349 | overflow_in; | |
2fc0cc0e | 1350 | ARMCPU *cpu = env_archcpu(env); |
4e7beb0c AL |
1351 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); |
1352 | } | |
1353 | #endif | |
1354 | ||
5ecdd3e4 AL |
1355 | env->cp15.c14_pmevcntr_delta[counter] -= |
1356 | env->cp15.c14_pmevcntr[counter]; | |
1357 | } | |
1358 | } | |
1359 | ||
5d05b9d4 AL |
1360 | void pmu_op_start(CPUARMState *env) |
1361 | { | |
5ecdd3e4 | 1362 | unsigned int i; |
5d05b9d4 | 1363 | pmccntr_op_start(env); |
5ecdd3e4 AL |
1364 | for (i = 0; i < pmu_num_counters(env); i++) { |
1365 | pmevcntr_op_start(env, i); | |
1366 | } | |
5d05b9d4 AL |
1367 | } |
1368 | ||
1369 | void pmu_op_finish(CPUARMState *env) | |
1370 | { | |
5ecdd3e4 | 1371 | unsigned int i; |
5d05b9d4 | 1372 | pmccntr_op_finish(env); |
5ecdd3e4 AL |
1373 | for (i = 0; i < pmu_num_counters(env); i++) { |
1374 | pmevcntr_op_finish(env, i); | |
1375 | } | |
5d05b9d4 AL |
1376 | } |
1377 | ||
033614c4 AL |
1378 | void pmu_pre_el_change(ARMCPU *cpu, void *ignored) |
1379 | { | |
1380 | pmu_op_start(&cpu->env); | |
1381 | } | |
1382 | ||
1383 | void pmu_post_el_change(ARMCPU *cpu, void *ignored) | |
1384 | { | |
1385 | pmu_op_finish(&cpu->env); | |
1386 | } | |
1387 | ||
4e7beb0c AL |
1388 | void arm_pmu_timer_cb(void *opaque) |
1389 | { | |
1390 | ARMCPU *cpu = opaque; | |
1391 | ||
1392 | /* | |
1393 | * Update all the counter values based on the current underlying counts, | |
1394 | * triggering interrupts to be raised, if necessary. pmu_op_finish() also | |
1395 | * has the effect of setting the cpu->pmu_timer to the next earliest time a | |
1396 | * counter may expire. | |
1397 | */ | |
1398 | pmu_op_start(&cpu->env); | |
1399 | pmu_op_finish(&cpu->env); | |
1400 | } | |
1401 | ||
c4241c7d PM |
1402 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1403 | uint64_t value) | |
200ac0ef | 1404 | { |
5d05b9d4 | 1405 | pmu_op_start(env); |
7c2cb42b AF |
1406 | |
1407 | if (value & PMCRC) { | |
1408 | /* The counter has been reset */ | |
1409 | env->cp15.c15_ccnt = 0; | |
1410 | } | |
1411 | ||
5ecdd3e4 AL |
1412 | if (value & PMCRP) { |
1413 | unsigned int i; | |
1414 | for (i = 0; i < pmu_num_counters(env); i++) { | |
1415 | env->cp15.c14_pmevcntr[i] = 0; | |
1416 | } | |
1417 | } | |
1418 | ||
62d96ff4 PM |
1419 | env->cp15.c9_pmcr &= ~PMCR_WRITEABLE_MASK; |
1420 | env->cp15.c9_pmcr |= (value & PMCR_WRITEABLE_MASK); | |
7c2cb42b | 1421 | |
5d05b9d4 | 1422 | pmu_op_finish(env); |
7c2cb42b AF |
1423 | } |
1424 | ||
0d4bfd7d AL |
1425 | static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1426 | uint64_t value) | |
1427 | { | |
1428 | unsigned int i; | |
1429 | for (i = 0; i < pmu_num_counters(env); i++) { | |
1430 | /* Increment a counter's count iff: */ | |
1431 | if ((value & (1 << i)) && /* counter's bit is set */ | |
1432 | /* counter is enabled and not filtered */ | |
1433 | pmu_counter_enabled(env, i) && | |
1434 | /* counter is SW_INCR */ | |
1435 | (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { | |
1436 | pmevcntr_op_start(env, i); | |
f4efb4b2 AL |
1437 | |
1438 | /* | |
1439 | * Detect if this write causes an overflow since we can't predict | |
1440 | * PMSWINC overflows like we can for other events | |
1441 | */ | |
1442 | uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; | |
1443 | ||
1444 | if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { | |
1445 | env->cp15.c9_pmovsr |= (1 << i); | |
1446 | pmu_update_irq(env); | |
1447 | } | |
1448 | ||
1449 | env->cp15.c14_pmevcntr[i] = new_pmswinc; | |
1450 | ||
0d4bfd7d AL |
1451 | pmevcntr_op_finish(env, i); |
1452 | } | |
1453 | } | |
1454 | } | |
1455 | ||
7c2cb42b AF |
1456 | static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1457 | { | |
5d05b9d4 AL |
1458 | uint64_t ret; |
1459 | pmccntr_op_start(env); | |
1460 | ret = env->cp15.c15_ccnt; | |
1461 | pmccntr_op_finish(env); | |
1462 | return ret; | |
7c2cb42b AF |
1463 | } |
1464 | ||
6b040780 WH |
1465 | static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1466 | uint64_t value) | |
1467 | { | |
1468 | /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and | |
1469 | * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the | |
1470 | * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are | |
1471 | * accessed. | |
1472 | */ | |
1473 | env->cp15.c9_pmselr = value & 0x1f; | |
1474 | } | |
1475 | ||
7c2cb42b AF |
1476 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1477 | uint64_t value) | |
1478 | { | |
5d05b9d4 AL |
1479 | pmccntr_op_start(env); |
1480 | env->cp15.c15_ccnt = value; | |
1481 | pmccntr_op_finish(env); | |
200ac0ef | 1482 | } |
421c7ebd PC |
1483 | |
1484 | static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1485 | uint64_t value) | |
1486 | { | |
1487 | uint64_t cur_val = pmccntr_read(env, NULL); | |
1488 | ||
1489 | pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); | |
1490 | } | |
1491 | ||
0614601c AF |
1492 | static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1493 | uint64_t value) | |
1494 | { | |
5d05b9d4 | 1495 | pmccntr_op_start(env); |
4b8afa1f AL |
1496 | env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0; |
1497 | pmccntr_op_finish(env); | |
1498 | } | |
1499 | ||
1500 | static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1501 | uint64_t value) | |
1502 | { | |
1503 | pmccntr_op_start(env); | |
1504 | /* M is not accessible from AArch32 */ | |
1505 | env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | | |
1506 | (value & PMCCFILTR); | |
5d05b9d4 | 1507 | pmccntr_op_finish(env); |
0614601c AF |
1508 | } |
1509 | ||
4b8afa1f AL |
1510 | static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri) |
1511 | { | |
1512 | /* M is not visible in AArch32 */ | |
1513 | return env->cp15.pmccfiltr_el0 & PMCCFILTR; | |
1514 | } | |
1515 | ||
c4241c7d | 1516 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1517 | uint64_t value) |
1518 | { | |
7ece99b1 | 1519 | value &= pmu_counter_mask(env); |
200ac0ef | 1520 | env->cp15.c9_pmcnten |= value; |
200ac0ef PM |
1521 | } |
1522 | ||
c4241c7d PM |
1523 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1524 | uint64_t value) | |
200ac0ef | 1525 | { |
7ece99b1 | 1526 | value &= pmu_counter_mask(env); |
200ac0ef | 1527 | env->cp15.c9_pmcnten &= ~value; |
200ac0ef PM |
1528 | } |
1529 | ||
c4241c7d PM |
1530 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1531 | uint64_t value) | |
200ac0ef | 1532 | { |
599b71e2 | 1533 | value &= pmu_counter_mask(env); |
200ac0ef | 1534 | env->cp15.c9_pmovsr &= ~value; |
f4efb4b2 | 1535 | pmu_update_irq(env); |
200ac0ef PM |
1536 | } |
1537 | ||
327dd510 AL |
1538 | static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1539 | uint64_t value) | |
1540 | { | |
1541 | value &= pmu_counter_mask(env); | |
1542 | env->cp15.c9_pmovsr |= value; | |
f4efb4b2 | 1543 | pmu_update_irq(env); |
327dd510 AL |
1544 | } |
1545 | ||
5ecdd3e4 AL |
1546 | static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1547 | uint64_t value, const uint8_t counter) | |
200ac0ef | 1548 | { |
5ecdd3e4 AL |
1549 | if (counter == 31) { |
1550 | pmccfiltr_write(env, ri, value); | |
1551 | } else if (counter < pmu_num_counters(env)) { | |
1552 | pmevcntr_op_start(env, counter); | |
1553 | ||
1554 | /* | |
1555 | * If this counter's event type is changing, store the current | |
1556 | * underlying count for the new type in c14_pmevcntr_delta[counter] so | |
1557 | * pmevcntr_op_finish has the correct baseline when it converts back to | |
1558 | * a delta. | |
1559 | */ | |
1560 | uint16_t old_event = env->cp15.c14_pmevtyper[counter] & | |
1561 | PMXEVTYPER_EVTCOUNT; | |
1562 | uint16_t new_event = value & PMXEVTYPER_EVTCOUNT; | |
1563 | if (old_event != new_event) { | |
1564 | uint64_t count = 0; | |
1565 | if (event_supported(new_event)) { | |
1566 | uint16_t event_idx = supported_event_map[new_event]; | |
1567 | count = pm_events[event_idx].get_count(env); | |
1568 | } | |
1569 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1570 | } | |
1571 | ||
1572 | env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK; | |
1573 | pmevcntr_op_finish(env, counter); | |
1574 | } | |
fdb86656 WH |
1575 | /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when |
1576 | * PMSELR value is equal to or greater than the number of implemented | |
1577 | * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. | |
1578 | */ | |
5ecdd3e4 AL |
1579 | } |
1580 | ||
1581 | static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1582 | const uint8_t counter) | |
1583 | { | |
1584 | if (counter == 31) { | |
1585 | return env->cp15.pmccfiltr_el0; | |
1586 | } else if (counter < pmu_num_counters(env)) { | |
1587 | return env->cp15.c14_pmevtyper[counter]; | |
1588 | } else { | |
1589 | /* | |
1590 | * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER | |
1591 | * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). | |
1592 | */ | |
1593 | return 0; | |
1594 | } | |
1595 | } | |
1596 | ||
1597 | static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, | |
1598 | uint64_t value) | |
1599 | { | |
1600 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1601 | pmevtyper_write(env, ri, value, counter); | |
1602 | } | |
1603 | ||
1604 | static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1605 | uint64_t value) | |
1606 | { | |
1607 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1608 | env->cp15.c14_pmevtyper[counter] = value; | |
1609 | ||
1610 | /* | |
1611 | * pmevtyper_rawwrite is called between a pair of pmu_op_start and | |
1612 | * pmu_op_finish calls when loading saved state for a migration. Because | |
1613 | * we're potentially updating the type of event here, the value written to | |
1614 | * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a | |
1615 | * different counter type. Therefore, we need to set this value to the | |
1616 | * current count for the counter type we're writing so that pmu_op_finish | |
1617 | * has the correct count for its calculation. | |
1618 | */ | |
1619 | uint16_t event = value & PMXEVTYPER_EVTCOUNT; | |
1620 | if (event_supported(event)) { | |
1621 | uint16_t event_idx = supported_event_map[event]; | |
1622 | env->cp15.c14_pmevcntr_delta[counter] = | |
1623 | pm_events[event_idx].get_count(env); | |
fdb86656 WH |
1624 | } |
1625 | } | |
1626 | ||
5ecdd3e4 AL |
1627 | static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) |
1628 | { | |
1629 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1630 | return pmevtyper_read(env, ri, counter); | |
1631 | } | |
1632 | ||
1633 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1634 | uint64_t value) | |
1635 | { | |
1636 | pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1637 | } | |
1638 | ||
fdb86656 WH |
1639 | static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1640 | { | |
5ecdd3e4 AL |
1641 | return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); |
1642 | } | |
1643 | ||
1644 | static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1645 | uint64_t value, uint8_t counter) | |
1646 | { | |
1647 | if (counter < pmu_num_counters(env)) { | |
1648 | pmevcntr_op_start(env, counter); | |
1649 | env->cp15.c14_pmevcntr[counter] = value; | |
1650 | pmevcntr_op_finish(env, counter); | |
1651 | } | |
1652 | /* | |
1653 | * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR | |
1654 | * are CONSTRAINED UNPREDICTABLE. | |
fdb86656 | 1655 | */ |
5ecdd3e4 AL |
1656 | } |
1657 | ||
1658 | static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1659 | uint8_t counter) | |
1660 | { | |
1661 | if (counter < pmu_num_counters(env)) { | |
1662 | uint64_t ret; | |
1663 | pmevcntr_op_start(env, counter); | |
1664 | ret = env->cp15.c14_pmevcntr[counter]; | |
1665 | pmevcntr_op_finish(env, counter); | |
1666 | return ret; | |
fdb86656 | 1667 | } else { |
5ecdd3e4 AL |
1668 | /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR |
1669 | * are CONSTRAINED UNPREDICTABLE. */ | |
fdb86656 WH |
1670 | return 0; |
1671 | } | |
200ac0ef PM |
1672 | } |
1673 | ||
5ecdd3e4 AL |
1674 | static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, |
1675 | uint64_t value) | |
1676 | { | |
1677 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1678 | pmevcntr_write(env, ri, value, counter); | |
1679 | } | |
1680 | ||
1681 | static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) | |
1682 | { | |
1683 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1684 | return pmevcntr_read(env, ri, counter); | |
1685 | } | |
1686 | ||
1687 | static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1688 | uint64_t value) | |
1689 | { | |
1690 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1691 | assert(counter < pmu_num_counters(env)); | |
1692 | env->cp15.c14_pmevcntr[counter] = value; | |
1693 | pmevcntr_write(env, ri, value, counter); | |
1694 | } | |
1695 | ||
1696 | static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri) | |
1697 | { | |
1698 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1699 | assert(counter < pmu_num_counters(env)); | |
1700 | return env->cp15.c14_pmevcntr[counter]; | |
1701 | } | |
1702 | ||
1703 | static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1704 | uint64_t value) | |
1705 | { | |
1706 | pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1707 | } | |
1708 | ||
1709 | static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1710 | { | |
1711 | return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); | |
1712 | } | |
1713 | ||
c4241c7d | 1714 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1715 | uint64_t value) |
1716 | { | |
6ecd0b6b AB |
1717 | if (arm_feature(env, ARM_FEATURE_V8)) { |
1718 | env->cp15.c9_pmuserenr = value & 0xf; | |
1719 | } else { | |
1720 | env->cp15.c9_pmuserenr = value & 1; | |
1721 | } | |
200ac0ef PM |
1722 | } |
1723 | ||
c4241c7d PM |
1724 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1725 | uint64_t value) | |
200ac0ef PM |
1726 | { |
1727 | /* We have no event counters so only the C bit can be changed */ | |
7ece99b1 | 1728 | value &= pmu_counter_mask(env); |
200ac0ef | 1729 | env->cp15.c9_pminten |= value; |
f4efb4b2 | 1730 | pmu_update_irq(env); |
200ac0ef PM |
1731 | } |
1732 | ||
c4241c7d PM |
1733 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1734 | uint64_t value) | |
200ac0ef | 1735 | { |
7ece99b1 | 1736 | value &= pmu_counter_mask(env); |
200ac0ef | 1737 | env->cp15.c9_pminten &= ~value; |
f4efb4b2 | 1738 | pmu_update_irq(env); |
200ac0ef PM |
1739 | } |
1740 | ||
c4241c7d PM |
1741 | static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1742 | uint64_t value) | |
8641136c | 1743 | { |
a505d7fe PM |
1744 | /* Note that even though the AArch64 view of this register has bits |
1745 | * [10:0] all RES0 we can only mask the bottom 5, to comply with the | |
1746 | * architectural requirements for bits which are RES0 only in some | |
1747 | * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 | |
1748 | * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) | |
1749 | */ | |
855ea66d | 1750 | raw_write(env, ri, value & ~0x1FULL); |
8641136c NR |
1751 | } |
1752 | ||
64e0e2de EI |
1753 | static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
1754 | { | |
ea22747c RH |
1755 | /* Begin with base v8.0 state. */ |
1756 | uint32_t valid_mask = 0x3fff; | |
2fc0cc0e | 1757 | ARMCPU *cpu = env_archcpu(env); |
ea22747c | 1758 | |
252e8c69 | 1759 | if (ri->state == ARM_CP_STATE_AA64) { |
10d0ef3e MN |
1760 | if (arm_feature(env, ARM_FEATURE_AARCH64) && |
1761 | !cpu_isar_feature(aa64_aa32_el1, cpu)) { | |
1762 | value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ | |
1763 | } | |
ea22747c | 1764 | valid_mask &= ~SCR_NET; |
252e8c69 RH |
1765 | |
1766 | if (cpu_isar_feature(aa64_lor, cpu)) { | |
1767 | valid_mask |= SCR_TLOR; | |
1768 | } | |
1769 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
1770 | valid_mask |= SCR_API | SCR_APK; | |
1771 | } | |
926c1b97 RDC |
1772 | if (cpu_isar_feature(aa64_sel2, cpu)) { |
1773 | valid_mask |= SCR_EEL2; | |
1774 | } | |
8ddb300b RH |
1775 | if (cpu_isar_feature(aa64_mte, cpu)) { |
1776 | valid_mask |= SCR_ATA; | |
1777 | } | |
ea22747c RH |
1778 | } else { |
1779 | valid_mask &= ~(SCR_RW | SCR_ST); | |
1780 | } | |
64e0e2de EI |
1781 | |
1782 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | |
1783 | valid_mask &= ~SCR_HCE; | |
1784 | ||
1785 | /* On ARMv7, SMD (or SCD as it is called in v7) is only | |
1786 | * supported if EL2 exists. The bit is UNK/SBZP when | |
1787 | * EL2 is unavailable. In QEMU ARMv7, we force it to always zero | |
1788 | * when EL2 is unavailable. | |
4eb27640 | 1789 | * On ARMv8, this bit is always available. |
64e0e2de | 1790 | */ |
4eb27640 GB |
1791 | if (arm_feature(env, ARM_FEATURE_V7) && |
1792 | !arm_feature(env, ARM_FEATURE_V8)) { | |
64e0e2de EI |
1793 | valid_mask &= ~SCR_SMD; |
1794 | } | |
1795 | } | |
1796 | ||
1797 | /* Clear all-context RES0 bits. */ | |
1798 | value &= valid_mask; | |
1799 | raw_write(env, ri, value); | |
1800 | } | |
1801 | ||
10d0ef3e MN |
1802 | static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1803 | { | |
1804 | /* | |
1805 | * scr_write will set the RES1 bits on an AArch64-only CPU. | |
1806 | * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise. | |
1807 | */ | |
1808 | scr_write(env, ri, 0); | |
1809 | } | |
1810 | ||
630fcd4d MZ |
1811 | static CPAccessResult access_aa64_tid2(CPUARMState *env, |
1812 | const ARMCPRegInfo *ri, | |
1813 | bool isread) | |
1814 | { | |
1815 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) { | |
1816 | return CP_ACCESS_TRAP_EL2; | |
1817 | } | |
1818 | ||
1819 | return CP_ACCESS_OK; | |
1820 | } | |
1821 | ||
c4241c7d | 1822 | static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
776d4e5c | 1823 | { |
2fc0cc0e | 1824 | ARMCPU *cpu = env_archcpu(env); |
b85a1fd6 FA |
1825 | |
1826 | /* Acquire the CSSELR index from the bank corresponding to the CCSIDR | |
1827 | * bank | |
1828 | */ | |
1829 | uint32_t index = A32_BANKED_REG_GET(env, csselr, | |
1830 | ri->secure & ARM_CP_SECSTATE_S); | |
1831 | ||
1832 | return cpu->ccsidr[index]; | |
776d4e5c PM |
1833 | } |
1834 | ||
c4241c7d PM |
1835 | static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1836 | uint64_t value) | |
776d4e5c | 1837 | { |
8d5c773e | 1838 | raw_write(env, ri, value & 0xf); |
776d4e5c PM |
1839 | } |
1840 | ||
1090b9c6 PM |
1841 | static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1842 | { | |
29a0af61 | 1843 | CPUState *cs = env_cpu(env); |
cc974d5c RDC |
1844 | bool el1 = arm_current_el(env) == 1; |
1845 | uint64_t hcr_el2 = el1 ? arm_hcr_el2_eff(env) : 0; | |
1090b9c6 PM |
1846 | uint64_t ret = 0; |
1847 | ||
cc974d5c | 1848 | if (hcr_el2 & HCR_IMO) { |
636540e9 PM |
1849 | if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { |
1850 | ret |= CPSR_I; | |
1851 | } | |
1852 | } else { | |
1853 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { | |
1854 | ret |= CPSR_I; | |
1855 | } | |
1090b9c6 | 1856 | } |
636540e9 | 1857 | |
cc974d5c | 1858 | if (hcr_el2 & HCR_FMO) { |
636540e9 PM |
1859 | if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { |
1860 | ret |= CPSR_F; | |
1861 | } | |
1862 | } else { | |
1863 | if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { | |
1864 | ret |= CPSR_F; | |
1865 | } | |
1090b9c6 | 1866 | } |
636540e9 | 1867 | |
1090b9c6 PM |
1868 | /* External aborts are not possible in QEMU so A bit is always clear */ |
1869 | return ret; | |
1870 | } | |
1871 | ||
93fbc983 MZ |
1872 | static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInfo *ri, |
1873 | bool isread) | |
1874 | { | |
1875 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID1)) { | |
1876 | return CP_ACCESS_TRAP_EL2; | |
1877 | } | |
1878 | ||
1879 | return CP_ACCESS_OK; | |
1880 | } | |
1881 | ||
1882 | static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInfo *ri, | |
1883 | bool isread) | |
1884 | { | |
1885 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
1886 | return access_aa64_tid1(env, ri, isread); | |
1887 | } | |
1888 | ||
1889 | return CP_ACCESS_OK; | |
1890 | } | |
1891 | ||
e9aa6c21 | 1892 | static const ARMCPRegInfo v7_cp_reginfo[] = { |
7d57f408 PM |
1893 | /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ |
1894 | { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
1895 | .access = PL1_W, .type = ARM_CP_NOP }, | |
200ac0ef PM |
1896 | /* Performance monitors are implementation defined in v7, |
1897 | * but with an ARM recommended set of registers, which we | |
ac689a2e | 1898 | * follow. |
200ac0ef PM |
1899 | * |
1900 | * Performance registers fall into three categories: | |
1901 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) | |
1902 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) | |
1903 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) | |
1904 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW | |
1905 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. | |
1906 | */ | |
1907 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 1908 | .access = PL0_RW, .type = ARM_CP_ALIAS, |
8521466b | 1909 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), |
fcd25206 PM |
1910 | .writefn = pmcntenset_write, |
1911 | .accessfn = pmreg_access, | |
1912 | .raw_writefn = raw_write }, | |
8521466b AF |
1913 | { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, |
1914 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, | |
1915 | .access = PL0_RW, .accessfn = pmreg_access, | |
1916 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, | |
1917 | .writefn = pmcntenset_write, .raw_writefn = raw_write }, | |
200ac0ef | 1918 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
8521466b AF |
1919 | .access = PL0_RW, |
1920 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
1921 | .accessfn = pmreg_access, |
1922 | .writefn = pmcntenclr_write, | |
7a0e58fa | 1923 | .type = ARM_CP_ALIAS }, |
8521466b AF |
1924 | { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, |
1925 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, | |
1926 | .access = PL0_RW, .accessfn = pmreg_access, | |
7a0e58fa | 1927 | .type = ARM_CP_ALIAS, |
8521466b AF |
1928 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), |
1929 | .writefn = pmcntenclr_write }, | |
200ac0ef | 1930 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
f4efb4b2 | 1931 | .access = PL0_RW, .type = ARM_CP_IO, |
e4e91a21 | 1932 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
fcd25206 PM |
1933 | .accessfn = pmreg_access, |
1934 | .writefn = pmovsr_write, | |
1935 | .raw_writefn = raw_write }, | |
978364f1 AF |
1936 | { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, |
1937 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, | |
1938 | .access = PL0_RW, .accessfn = pmreg_access, | |
f4efb4b2 | 1939 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
978364f1 AF |
1940 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
1941 | .writefn = pmovsr_write, | |
1942 | .raw_writefn = raw_write }, | |
200ac0ef | 1943 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
f4efb4b2 AL |
1944 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
1945 | .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
0d4bfd7d AL |
1946 | .writefn = pmswinc_write }, |
1947 | { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64, | |
1948 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4, | |
f4efb4b2 AL |
1949 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
1950 | .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
0d4bfd7d | 1951 | .writefn = pmswinc_write }, |
6b040780 WH |
1952 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, |
1953 | .access = PL0_RW, .type = ARM_CP_ALIAS, | |
1954 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), | |
6ecd0b6b | 1955 | .accessfn = pmreg_access_selr, .writefn = pmselr_write, |
6b040780 WH |
1956 | .raw_writefn = raw_write}, |
1957 | { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, | |
1958 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, | |
6ecd0b6b | 1959 | .access = PL0_RW, .accessfn = pmreg_access_selr, |
6b040780 WH |
1960 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), |
1961 | .writefn = pmselr_write, .raw_writefn = raw_write, }, | |
200ac0ef | 1962 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
169c8938 | 1963 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO, |
421c7ebd | 1964 | .readfn = pmccntr_read, .writefn = pmccntr_write32, |
6ecd0b6b | 1965 | .accessfn = pmreg_access_ccntr }, |
8521466b AF |
1966 | { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, |
1967 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, | |
6ecd0b6b | 1968 | .access = PL0_RW, .accessfn = pmreg_access_ccntr, |
8521466b | 1969 | .type = ARM_CP_IO, |
980ebe87 AL |
1970 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt), |
1971 | .readfn = pmccntr_read, .writefn = pmccntr_write, | |
1972 | .raw_readfn = raw_read, .raw_writefn = raw_write, }, | |
4b8afa1f AL |
1973 | { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7, |
1974 | .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32, | |
1975 | .access = PL0_RW, .accessfn = pmreg_access, | |
1976 | .type = ARM_CP_ALIAS | ARM_CP_IO, | |
1977 | .resetvalue = 0, }, | |
8521466b AF |
1978 | { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, |
1979 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, | |
980ebe87 | 1980 | .writefn = pmccfiltr_write, .raw_writefn = raw_write, |
8521466b AF |
1981 | .access = PL0_RW, .accessfn = pmreg_access, |
1982 | .type = ARM_CP_IO, | |
1983 | .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), | |
1984 | .resetvalue = 0, }, | |
200ac0ef | 1985 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
5ecdd3e4 AL |
1986 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
1987 | .accessfn = pmreg_access, | |
fdb86656 WH |
1988 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
1989 | { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, | |
1990 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, | |
5ecdd3e4 AL |
1991 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
1992 | .accessfn = pmreg_access, | |
fdb86656 | 1993 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
200ac0ef | 1994 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
5ecdd3e4 AL |
1995 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
1996 | .accessfn = pmreg_access_xevcntr, | |
1997 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, | |
1998 | { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64, | |
1999 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2, | |
2000 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
2001 | .accessfn = pmreg_access_xevcntr, | |
2002 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, | |
200ac0ef | 2003 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
1fce1ba9 | 2004 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, |
e4e91a21 | 2005 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr), |
200ac0ef | 2006 | .resetvalue = 0, |
d4e6df63 | 2007 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
8a83ffc2 AF |
2008 | { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, |
2009 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, | |
1fce1ba9 | 2010 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, |
8a83ffc2 AF |
2011 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), |
2012 | .resetvalue = 0, | |
2013 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, | |
200ac0ef | 2014 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
1fce1ba9 | 2015 | .access = PL1_RW, .accessfn = access_tpm, |
b7d793ad | 2016 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
e6ec5457 | 2017 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), |
200ac0ef | 2018 | .resetvalue = 0, |
d4e6df63 | 2019 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
e6ec5457 WH |
2020 | { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, |
2021 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, | |
2022 | .access = PL1_RW, .accessfn = access_tpm, | |
2023 | .type = ARM_CP_IO, | |
2024 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
2025 | .writefn = pmintenset_write, .raw_writefn = raw_write, | |
2026 | .resetvalue = 0x0 }, | |
200ac0ef | 2027 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
fc5f6856 | 2028 | .access = PL1_RW, .accessfn = access_tpm, |
887c0f15 | 2029 | .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, |
200ac0ef | 2030 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
b061a82b | 2031 | .writefn = pmintenclr_write, }, |
978364f1 AF |
2032 | { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, |
2033 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, | |
fc5f6856 | 2034 | .access = PL1_RW, .accessfn = access_tpm, |
887c0f15 | 2035 | .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, |
978364f1 AF |
2036 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
2037 | .writefn = pmintenclr_write }, | |
7da845b0 PM |
2038 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, |
2039 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | |
630fcd4d MZ |
2040 | .access = PL1_R, |
2041 | .accessfn = access_aa64_tid2, | |
2042 | .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, | |
7da845b0 PM |
2043 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, |
2044 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | |
630fcd4d MZ |
2045 | .access = PL1_RW, |
2046 | .accessfn = access_aa64_tid2, | |
2047 | .writefn = csselr_write, .resetvalue = 0, | |
b85a1fd6 FA |
2048 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), |
2049 | offsetof(CPUARMState, cp15.csselr_ns) } }, | |
776d4e5c PM |
2050 | /* Auxiliary ID register: this actually has an IMPDEF value but for now |
2051 | * just RAZ for all cores: | |
2052 | */ | |
0ff644a7 PM |
2053 | { .name = "AIDR", .state = ARM_CP_STATE_BOTH, |
2054 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, | |
93fbc983 MZ |
2055 | .access = PL1_R, .type = ARM_CP_CONST, |
2056 | .accessfn = access_aa64_tid1, | |
2057 | .resetvalue = 0 }, | |
f32cdad5 PM |
2058 | /* Auxiliary fault status registers: these also are IMPDEF, and we |
2059 | * choose to RAZ/WI for all cores. | |
2060 | */ | |
2061 | { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, | |
2062 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, | |
84929218 RH |
2063 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
2064 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
f32cdad5 PM |
2065 | { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, |
2066 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, | |
84929218 RH |
2067 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
2068 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b0fe2427 PM |
2069 | /* MAIR can just read-as-written because we don't implement caches |
2070 | * and so don't need to care about memory attributes. | |
2071 | */ | |
2072 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | |
2073 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | |
84929218 RH |
2074 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
2075 | .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), | |
b0fe2427 | 2076 | .resetvalue = 0 }, |
4cfb8ad8 PM |
2077 | { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, |
2078 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, | |
2079 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), | |
2080 | .resetvalue = 0 }, | |
b0fe2427 PM |
2081 | /* For non-long-descriptor page tables these are PRRR and NMRR; |
2082 | * regardless they still act as reads-as-written for QEMU. | |
b0fe2427 | 2083 | */ |
1281f8e3 | 2084 | /* MAIR0/1 are defined separately from their 64-bit counterpart which |
be693c87 GB |
2085 | * allows them to assign the correct fieldoffset based on the endianness |
2086 | * handled in the field definitions. | |
2087 | */ | |
a903c449 | 2088 | { .name = "MAIR0", .state = ARM_CP_STATE_AA32, |
84929218 RH |
2089 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, |
2090 | .access = PL1_RW, .accessfn = access_tvm_trvm, | |
be693c87 GB |
2091 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), |
2092 | offsetof(CPUARMState, cp15.mair0_ns) }, | |
b0fe2427 | 2093 | .resetfn = arm_cp_reset_ignore }, |
a903c449 | 2094 | { .name = "MAIR1", .state = ARM_CP_STATE_AA32, |
84929218 RH |
2095 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, |
2096 | .access = PL1_RW, .accessfn = access_tvm_trvm, | |
be693c87 GB |
2097 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), |
2098 | offsetof(CPUARMState, cp15.mair1_ns) }, | |
b0fe2427 | 2099 | .resetfn = arm_cp_reset_ignore }, |
1090b9c6 PM |
2100 | { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, |
2101 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, | |
7a0e58fa | 2102 | .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, |
995939a6 PM |
2103 | /* 32 bit ITLB invalidates */ |
2104 | { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, | |
30881b73 RH |
2105 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2106 | .writefn = tlbiall_write }, | |
995939a6 | 2107 | { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, |
30881b73 RH |
2108 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2109 | .writefn = tlbimva_write }, | |
995939a6 | 2110 | { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, |
30881b73 RH |
2111 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2112 | .writefn = tlbiasid_write }, | |
995939a6 PM |
2113 | /* 32 bit DTLB invalidates */ |
2114 | { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, | |
30881b73 RH |
2115 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2116 | .writefn = tlbiall_write }, | |
995939a6 | 2117 | { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, |
30881b73 RH |
2118 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2119 | .writefn = tlbimva_write }, | |
995939a6 | 2120 | { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, |
30881b73 RH |
2121 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2122 | .writefn = tlbiasid_write }, | |
995939a6 PM |
2123 | /* 32 bit TLB invalidates */ |
2124 | { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | |
30881b73 RH |
2125 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2126 | .writefn = tlbiall_write }, | |
995939a6 | 2127 | { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
30881b73 RH |
2128 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2129 | .writefn = tlbimva_write }, | |
995939a6 | 2130 | { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
30881b73 RH |
2131 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2132 | .writefn = tlbiasid_write }, | |
995939a6 | 2133 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
30881b73 RH |
2134 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2135 | .writefn = tlbimvaa_write }, | |
995939a6 PM |
2136 | REGINFO_SENTINEL |
2137 | }; | |
2138 | ||
2139 | static const ARMCPRegInfo v7mp_cp_reginfo[] = { | |
2140 | /* 32 bit TLB invalidates, Inner Shareable */ | |
2141 | { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | |
30881b73 RH |
2142 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2143 | .writefn = tlbiall_is_write }, | |
995939a6 | 2144 | { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
30881b73 RH |
2145 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2146 | .writefn = tlbimva_is_write }, | |
995939a6 | 2147 | { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
30881b73 | 2148 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
fa439fc5 | 2149 | .writefn = tlbiasid_is_write }, |
995939a6 | 2150 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
30881b73 | 2151 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
fa439fc5 | 2152 | .writefn = tlbimvaa_is_write }, |
e9aa6c21 PM |
2153 | REGINFO_SENTINEL |
2154 | }; | |
2155 | ||
327dd510 AL |
2156 | static const ARMCPRegInfo pmovsset_cp_reginfo[] = { |
2157 | /* PMOVSSET is not implemented in v7 before v7ve */ | |
2158 | { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3, | |
2159 | .access = PL0_RW, .accessfn = pmreg_access, | |
f4efb4b2 | 2160 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
327dd510 AL |
2161 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
2162 | .writefn = pmovsset_write, | |
2163 | .raw_writefn = raw_write }, | |
2164 | { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64, | |
2165 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3, | |
2166 | .access = PL0_RW, .accessfn = pmreg_access, | |
f4efb4b2 | 2167 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
327dd510 AL |
2168 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
2169 | .writefn = pmovsset_write, | |
2170 | .raw_writefn = raw_write }, | |
2171 | REGINFO_SENTINEL | |
2172 | }; | |
2173 | ||
c4241c7d PM |
2174 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2175 | uint64_t value) | |
c326b979 PM |
2176 | { |
2177 | value &= 1; | |
2178 | env->teecr = value; | |
c326b979 PM |
2179 | } |
2180 | ||
cc7613bf PM |
2181 | static CPAccessResult teecr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2182 | bool isread) | |
2183 | { | |
2184 | /* | |
2185 | * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE | |
2186 | * at all, so we don't need to check whether we're v8A. | |
2187 | */ | |
2188 | if (arm_current_el(env) < 2 && !arm_is_secure_below_el3(env) && | |
2189 | (env->cp15.hstr_el2 & HSTR_TTEE)) { | |
2190 | return CP_ACCESS_TRAP_EL2; | |
2191 | } | |
2192 | return CP_ACCESS_OK; | |
2193 | } | |
2194 | ||
3f208fd7 PM |
2195 | static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2196 | bool isread) | |
c326b979 | 2197 | { |
dcbff19b | 2198 | if (arm_current_el(env) == 0 && (env->teecr & 1)) { |
92611c00 | 2199 | return CP_ACCESS_TRAP; |
c326b979 | 2200 | } |
cc7613bf | 2201 | return teecr_access(env, ri, isread); |
c326b979 PM |
2202 | } |
2203 | ||
2204 | static const ARMCPRegInfo t2ee_cp_reginfo[] = { | |
2205 | { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, | |
2206 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), | |
2207 | .resetvalue = 0, | |
cc7613bf | 2208 | .writefn = teecr_write, .accessfn = teecr_access }, |
c326b979 PM |
2209 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, |
2210 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | |
92611c00 | 2211 | .accessfn = teehbr_access, .resetvalue = 0 }, |
c326b979 PM |
2212 | REGINFO_SENTINEL |
2213 | }; | |
2214 | ||
4d31c596 | 2215 | static const ARMCPRegInfo v6k_cp_reginfo[] = { |
e4fe830b PM |
2216 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, |
2217 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | |
2218 | .access = PL0_RW, | |
54bf36ed | 2219 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, |
4d31c596 PM |
2220 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
2221 | .access = PL0_RW, | |
54bf36ed FA |
2222 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), |
2223 | offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, | |
e4fe830b PM |
2224 | .resetfn = arm_cp_reset_ignore }, |
2225 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | |
2226 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | |
2227 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
2228 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), |
2229 | .resetvalue = 0}, | |
4d31c596 PM |
2230 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
2231 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
2232 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), |
2233 | offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, | |
e4fe830b | 2234 | .resetfn = arm_cp_reset_ignore }, |
54bf36ed | 2235 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, |
e4fe830b | 2236 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, |
4d31c596 | 2237 | .access = PL1_RW, |
54bf36ed FA |
2238 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, |
2239 | { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, | |
2240 | .access = PL1_RW, | |
2241 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), | |
2242 | offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, | |
2243 | .resetvalue = 0 }, | |
4d31c596 PM |
2244 | REGINFO_SENTINEL |
2245 | }; | |
2246 | ||
55d284af PM |
2247 | #ifndef CONFIG_USER_ONLY |
2248 | ||
3f208fd7 PM |
2249 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2250 | bool isread) | |
00108f2d | 2251 | { |
75502672 PM |
2252 | /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. |
2253 | * Writable only at the highest implemented exception level. | |
2254 | */ | |
2255 | int el = arm_current_el(env); | |
5bc84371 RH |
2256 | uint64_t hcr; |
2257 | uint32_t cntkctl; | |
75502672 PM |
2258 | |
2259 | switch (el) { | |
2260 | case 0: | |
5bc84371 RH |
2261 | hcr = arm_hcr_el2_eff(env); |
2262 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2263 | cntkctl = env->cp15.cnthctl_el2; | |
2264 | } else { | |
2265 | cntkctl = env->cp15.c14_cntkctl; | |
2266 | } | |
2267 | if (!extract32(cntkctl, 0, 2)) { | |
75502672 PM |
2268 | return CP_ACCESS_TRAP; |
2269 | } | |
2270 | break; | |
2271 | case 1: | |
2272 | if (!isread && ri->state == ARM_CP_STATE_AA32 && | |
2273 | arm_is_secure_below_el3(env)) { | |
2274 | /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ | |
2275 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2276 | } | |
2277 | break; | |
2278 | case 2: | |
2279 | case 3: | |
2280 | break; | |
00108f2d | 2281 | } |
75502672 PM |
2282 | |
2283 | if (!isread && el < arm_highest_el(env)) { | |
2284 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2285 | } | |
2286 | ||
00108f2d PM |
2287 | return CP_ACCESS_OK; |
2288 | } | |
2289 | ||
3f208fd7 PM |
2290 | static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, |
2291 | bool isread) | |
00108f2d | 2292 | { |
0b6440af | 2293 | unsigned int cur_el = arm_current_el(env); |
e6ef0169 | 2294 | bool has_el2 = arm_is_el2_enabled(env); |
5bc84371 | 2295 | uint64_t hcr = arm_hcr_el2_eff(env); |
0b6440af | 2296 | |
5bc84371 RH |
2297 | switch (cur_el) { |
2298 | case 0: | |
2299 | /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */ | |
2300 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2301 | return (extract32(env->cp15.cnthctl_el2, timeridx, 1) | |
2302 | ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); | |
2303 | } | |
0b6440af | 2304 | |
5bc84371 RH |
2305 | /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */ |
2306 | if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) { | |
2307 | return CP_ACCESS_TRAP; | |
2308 | } | |
2309 | ||
2310 | /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */ | |
2311 | if (hcr & HCR_E2H) { | |
2312 | if (timeridx == GTIMER_PHYS && | |
2313 | !extract32(env->cp15.cnthctl_el2, 10, 1)) { | |
2314 | return CP_ACCESS_TRAP_EL2; | |
2315 | } | |
2316 | } else { | |
2317 | /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */ | |
e6ef0169 | 2318 | if (has_el2 && timeridx == GTIMER_PHYS && |
5bc84371 RH |
2319 | !extract32(env->cp15.cnthctl_el2, 1, 1)) { |
2320 | return CP_ACCESS_TRAP_EL2; | |
2321 | } | |
2322 | } | |
2323 | break; | |
2324 | ||
2325 | case 1: | |
2326 | /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */ | |
e6ef0169 | 2327 | if (has_el2 && timeridx == GTIMER_PHYS && |
5bc84371 RH |
2328 | (hcr & HCR_E2H |
2329 | ? !extract32(env->cp15.cnthctl_el2, 10, 1) | |
2330 | : !extract32(env->cp15.cnthctl_el2, 0, 1))) { | |
2331 | return CP_ACCESS_TRAP_EL2; | |
2332 | } | |
2333 | break; | |
0b6440af | 2334 | } |
00108f2d PM |
2335 | return CP_ACCESS_OK; |
2336 | } | |
2337 | ||
3f208fd7 PM |
2338 | static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, |
2339 | bool isread) | |
00108f2d | 2340 | { |
0b6440af | 2341 | unsigned int cur_el = arm_current_el(env); |
e6ef0169 | 2342 | bool has_el2 = arm_is_el2_enabled(env); |
5bc84371 | 2343 | uint64_t hcr = arm_hcr_el2_eff(env); |
0b6440af | 2344 | |
5bc84371 RH |
2345 | switch (cur_el) { |
2346 | case 0: | |
2347 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2348 | /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */ | |
2349 | return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1) | |
2350 | ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); | |
2351 | } | |
0b6440af | 2352 | |
5bc84371 RH |
2353 | /* |
2354 | * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from | |
2355 | * EL0 if EL0[PV]TEN is zero. | |
2356 | */ | |
2357 | if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { | |
2358 | return CP_ACCESS_TRAP; | |
2359 | } | |
2360 | /* fall through */ | |
2361 | ||
2362 | case 1: | |
e6ef0169 | 2363 | if (has_el2 && timeridx == GTIMER_PHYS) { |
5bc84371 RH |
2364 | if (hcr & HCR_E2H) { |
2365 | /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */ | |
2366 | if (!extract32(env->cp15.cnthctl_el2, 11, 1)) { | |
2367 | return CP_ACCESS_TRAP_EL2; | |
2368 | } | |
2369 | } else { | |
2370 | /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */ | |
2371 | if (!extract32(env->cp15.cnthctl_el2, 1, 1)) { | |
2372 | return CP_ACCESS_TRAP_EL2; | |
2373 | } | |
2374 | } | |
2375 | } | |
2376 | break; | |
0b6440af | 2377 | } |
00108f2d PM |
2378 | return CP_ACCESS_OK; |
2379 | } | |
2380 | ||
2381 | static CPAccessResult gt_pct_access(CPUARMState *env, | |
3f208fd7 PM |
2382 | const ARMCPRegInfo *ri, |
2383 | bool isread) | |
00108f2d | 2384 | { |
3f208fd7 | 2385 | return gt_counter_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2386 | } |
2387 | ||
2388 | static CPAccessResult gt_vct_access(CPUARMState *env, | |
3f208fd7 PM |
2389 | const ARMCPRegInfo *ri, |
2390 | bool isread) | |
00108f2d | 2391 | { |
3f208fd7 | 2392 | return gt_counter_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2393 | } |
2394 | ||
3f208fd7 PM |
2395 | static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2396 | bool isread) | |
00108f2d | 2397 | { |
3f208fd7 | 2398 | return gt_timer_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2399 | } |
2400 | ||
3f208fd7 PM |
2401 | static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2402 | bool isread) | |
00108f2d | 2403 | { |
3f208fd7 | 2404 | return gt_timer_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2405 | } |
2406 | ||
b4d3978c | 2407 | static CPAccessResult gt_stimer_access(CPUARMState *env, |
3f208fd7 PM |
2408 | const ARMCPRegInfo *ri, |
2409 | bool isread) | |
b4d3978c PM |
2410 | { |
2411 | /* The AArch64 register view of the secure physical timer is | |
2412 | * always accessible from EL3, and configurably accessible from | |
2413 | * Secure EL1. | |
2414 | */ | |
2415 | switch (arm_current_el(env)) { | |
2416 | case 1: | |
2417 | if (!arm_is_secure(env)) { | |
2418 | return CP_ACCESS_TRAP; | |
2419 | } | |
2420 | if (!(env->cp15.scr_el3 & SCR_ST)) { | |
2421 | return CP_ACCESS_TRAP_EL3; | |
2422 | } | |
2423 | return CP_ACCESS_OK; | |
2424 | case 0: | |
2425 | case 2: | |
2426 | return CP_ACCESS_TRAP; | |
2427 | case 3: | |
2428 | return CP_ACCESS_OK; | |
2429 | default: | |
2430 | g_assert_not_reached(); | |
2431 | } | |
2432 | } | |
2433 | ||
55d284af PM |
2434 | static uint64_t gt_get_countervalue(CPUARMState *env) |
2435 | { | |
7def8754 AJ |
2436 | ARMCPU *cpu = env_archcpu(env); |
2437 | ||
2438 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu); | |
55d284af PM |
2439 | } |
2440 | ||
2441 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) | |
2442 | { | |
2443 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; | |
2444 | ||
2445 | if (gt->ctl & 1) { | |
2446 | /* Timer enabled: calculate and set current ISTATUS, irq, and | |
2447 | * reset timer to when ISTATUS next has to change | |
2448 | */ | |
edac4d8a EI |
2449 | uint64_t offset = timeridx == GTIMER_VIRT ? |
2450 | cpu->env.cp15.cntvoff_el2 : 0; | |
55d284af PM |
2451 | uint64_t count = gt_get_countervalue(&cpu->env); |
2452 | /* Note that this must be unsigned 64 bit arithmetic: */ | |
edac4d8a | 2453 | int istatus = count - offset >= gt->cval; |
55d284af | 2454 | uint64_t nexttick; |
194cbc49 | 2455 | int irqstate; |
55d284af PM |
2456 | |
2457 | gt->ctl = deposit32(gt->ctl, 2, 1, istatus); | |
194cbc49 PM |
2458 | |
2459 | irqstate = (istatus && !(gt->ctl & 2)); | |
2460 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
2461 | ||
55d284af PM |
2462 | if (istatus) { |
2463 | /* Next transition is when count rolls back over to zero */ | |
2464 | nexttick = UINT64_MAX; | |
2465 | } else { | |
2466 | /* Next transition is when we hit cval */ | |
edac4d8a | 2467 | nexttick = gt->cval + offset; |
55d284af PM |
2468 | } |
2469 | /* Note that the desired next expiry time might be beyond the | |
2470 | * signed-64-bit range of a QEMUTimer -- in this case we just | |
2471 | * set the timer for as far in the future as possible. When the | |
2472 | * timer expires we will reset the timer for any remaining period. | |
2473 | */ | |
7def8754 | 2474 | if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { |
4a0245b6 AJ |
2475 | timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX); |
2476 | } else { | |
2477 | timer_mod(cpu->gt_timer[timeridx], nexttick); | |
55d284af | 2478 | } |
194cbc49 | 2479 | trace_arm_gt_recalc(timeridx, irqstate, nexttick); |
55d284af PM |
2480 | } else { |
2481 | /* Timer disabled: ISTATUS and timer output always clear */ | |
2482 | gt->ctl &= ~4; | |
2483 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); | |
bc72ad67 | 2484 | timer_del(cpu->gt_timer[timeridx]); |
194cbc49 | 2485 | trace_arm_gt_recalc_disabled(timeridx); |
55d284af PM |
2486 | } |
2487 | } | |
2488 | ||
0e3eca4c EI |
2489 | static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, |
2490 | int timeridx) | |
55d284af | 2491 | { |
2fc0cc0e | 2492 | ARMCPU *cpu = env_archcpu(env); |
55d284af | 2493 | |
bc72ad67 | 2494 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
2495 | } |
2496 | ||
c4241c7d | 2497 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
55d284af | 2498 | { |
c4241c7d | 2499 | return gt_get_countervalue(env); |
55d284af PM |
2500 | } |
2501 | ||
53d1f856 RH |
2502 | static uint64_t gt_virt_cnt_offset(CPUARMState *env) |
2503 | { | |
2504 | uint64_t hcr; | |
2505 | ||
2506 | switch (arm_current_el(env)) { | |
2507 | case 2: | |
2508 | hcr = arm_hcr_el2_eff(env); | |
2509 | if (hcr & HCR_E2H) { | |
2510 | return 0; | |
2511 | } | |
2512 | break; | |
2513 | case 0: | |
2514 | hcr = arm_hcr_el2_eff(env); | |
2515 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2516 | return 0; | |
2517 | } | |
2518 | break; | |
2519 | } | |
2520 | ||
2521 | return env->cp15.cntvoff_el2; | |
2522 | } | |
2523 | ||
edac4d8a EI |
2524 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2525 | { | |
53d1f856 | 2526 | return gt_get_countervalue(env) - gt_virt_cnt_offset(env); |
edac4d8a EI |
2527 | } |
2528 | ||
c4241c7d | 2529 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2530 | int timeridx, |
c4241c7d | 2531 | uint64_t value) |
55d284af | 2532 | { |
194cbc49 | 2533 | trace_arm_gt_cval_write(timeridx, value); |
55d284af | 2534 | env->cp15.c14_timer[timeridx].cval = value; |
2fc0cc0e | 2535 | gt_recalc_timer(env_archcpu(env), timeridx); |
55d284af | 2536 | } |
c4241c7d | 2537 | |
0e3eca4c EI |
2538 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, |
2539 | int timeridx) | |
55d284af | 2540 | { |
53d1f856 RH |
2541 | uint64_t offset = 0; |
2542 | ||
2543 | switch (timeridx) { | |
2544 | case GTIMER_VIRT: | |
8c94b071 | 2545 | case GTIMER_HYPVIRT: |
53d1f856 RH |
2546 | offset = gt_virt_cnt_offset(env); |
2547 | break; | |
2548 | } | |
55d284af | 2549 | |
c4241c7d | 2550 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - |
edac4d8a | 2551 | (gt_get_countervalue(env) - offset)); |
55d284af PM |
2552 | } |
2553 | ||
c4241c7d | 2554 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2555 | int timeridx, |
c4241c7d | 2556 | uint64_t value) |
55d284af | 2557 | { |
53d1f856 RH |
2558 | uint64_t offset = 0; |
2559 | ||
2560 | switch (timeridx) { | |
2561 | case GTIMER_VIRT: | |
8c94b071 | 2562 | case GTIMER_HYPVIRT: |
53d1f856 RH |
2563 | offset = gt_virt_cnt_offset(env); |
2564 | break; | |
2565 | } | |
55d284af | 2566 | |
194cbc49 | 2567 | trace_arm_gt_tval_write(timeridx, value); |
edac4d8a | 2568 | env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + |
18084b2f | 2569 | sextract64(value, 0, 32); |
2fc0cc0e | 2570 | gt_recalc_timer(env_archcpu(env), timeridx); |
55d284af PM |
2571 | } |
2572 | ||
c4241c7d | 2573 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2574 | int timeridx, |
c4241c7d | 2575 | uint64_t value) |
55d284af | 2576 | { |
2fc0cc0e | 2577 | ARMCPU *cpu = env_archcpu(env); |
55d284af PM |
2578 | uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; |
2579 | ||
194cbc49 | 2580 | trace_arm_gt_ctl_write(timeridx, value); |
d3afacc7 | 2581 | env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); |
55d284af PM |
2582 | if ((oldval ^ value) & 1) { |
2583 | /* Enable toggled */ | |
2584 | gt_recalc_timer(cpu, timeridx); | |
d3afacc7 | 2585 | } else if ((oldval ^ value) & 2) { |
55d284af PM |
2586 | /* IMASK toggled: don't need to recalculate, |
2587 | * just set the interrupt line based on ISTATUS | |
2588 | */ | |
194cbc49 PM |
2589 | int irqstate = (oldval & 4) && !(value & 2); |
2590 | ||
2591 | trace_arm_gt_imask_toggle(timeridx, irqstate); | |
2592 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
55d284af | 2593 | } |
55d284af PM |
2594 | } |
2595 | ||
0e3eca4c EI |
2596 | static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2597 | { | |
2598 | gt_timer_reset(env, ri, GTIMER_PHYS); | |
2599 | } | |
2600 | ||
2601 | static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2602 | uint64_t value) | |
2603 | { | |
2604 | gt_cval_write(env, ri, GTIMER_PHYS, value); | |
2605 | } | |
2606 | ||
2607 | static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2608 | { | |
2609 | return gt_tval_read(env, ri, GTIMER_PHYS); | |
2610 | } | |
2611 | ||
2612 | static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2613 | uint64_t value) | |
2614 | { | |
2615 | gt_tval_write(env, ri, GTIMER_PHYS, value); | |
2616 | } | |
2617 | ||
2618 | static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2619 | uint64_t value) | |
2620 | { | |
2621 | gt_ctl_write(env, ri, GTIMER_PHYS, value); | |
2622 | } | |
2623 | ||
bb5972e4 RH |
2624 | static int gt_phys_redir_timeridx(CPUARMState *env) |
2625 | { | |
2626 | switch (arm_mmu_idx(env)) { | |
2627 | case ARMMMUIdx_E20_0: | |
2628 | case ARMMMUIdx_E20_2: | |
452ef8cb | 2629 | case ARMMMUIdx_E20_2_PAN: |
b6ad6062 RDC |
2630 | case ARMMMUIdx_SE20_0: |
2631 | case ARMMMUIdx_SE20_2: | |
2632 | case ARMMMUIdx_SE20_2_PAN: | |
bb5972e4 RH |
2633 | return GTIMER_HYP; |
2634 | default: | |
2635 | return GTIMER_PHYS; | |
2636 | } | |
2637 | } | |
2638 | ||
2639 | static int gt_virt_redir_timeridx(CPUARMState *env) | |
2640 | { | |
2641 | switch (arm_mmu_idx(env)) { | |
2642 | case ARMMMUIdx_E20_0: | |
2643 | case ARMMMUIdx_E20_2: | |
452ef8cb | 2644 | case ARMMMUIdx_E20_2_PAN: |
b6ad6062 RDC |
2645 | case ARMMMUIdx_SE20_0: |
2646 | case ARMMMUIdx_SE20_2: | |
2647 | case ARMMMUIdx_SE20_2_PAN: | |
bb5972e4 RH |
2648 | return GTIMER_HYPVIRT; |
2649 | default: | |
2650 | return GTIMER_VIRT; | |
2651 | } | |
2652 | } | |
2653 | ||
2654 | static uint64_t gt_phys_redir_cval_read(CPUARMState *env, | |
2655 | const ARMCPRegInfo *ri) | |
2656 | { | |
2657 | int timeridx = gt_phys_redir_timeridx(env); | |
2658 | return env->cp15.c14_timer[timeridx].cval; | |
2659 | } | |
2660 | ||
2661 | static void gt_phys_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2662 | uint64_t value) | |
2663 | { | |
2664 | int timeridx = gt_phys_redir_timeridx(env); | |
2665 | gt_cval_write(env, ri, timeridx, value); | |
2666 | } | |
2667 | ||
2668 | static uint64_t gt_phys_redir_tval_read(CPUARMState *env, | |
2669 | const ARMCPRegInfo *ri) | |
2670 | { | |
2671 | int timeridx = gt_phys_redir_timeridx(env); | |
2672 | return gt_tval_read(env, ri, timeridx); | |
2673 | } | |
2674 | ||
2675 | static void gt_phys_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2676 | uint64_t value) | |
2677 | { | |
2678 | int timeridx = gt_phys_redir_timeridx(env); | |
2679 | gt_tval_write(env, ri, timeridx, value); | |
2680 | } | |
2681 | ||
2682 | static uint64_t gt_phys_redir_ctl_read(CPUARMState *env, | |
2683 | const ARMCPRegInfo *ri) | |
2684 | { | |
2685 | int timeridx = gt_phys_redir_timeridx(env); | |
2686 | return env->cp15.c14_timer[timeridx].ctl; | |
2687 | } | |
2688 | ||
2689 | static void gt_phys_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2690 | uint64_t value) | |
2691 | { | |
2692 | int timeridx = gt_phys_redir_timeridx(env); | |
2693 | gt_ctl_write(env, ri, timeridx, value); | |
2694 | } | |
2695 | ||
0e3eca4c EI |
2696 | static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2697 | { | |
2698 | gt_timer_reset(env, ri, GTIMER_VIRT); | |
2699 | } | |
2700 | ||
2701 | static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2702 | uint64_t value) | |
2703 | { | |
2704 | gt_cval_write(env, ri, GTIMER_VIRT, value); | |
2705 | } | |
2706 | ||
2707 | static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2708 | { | |
2709 | return gt_tval_read(env, ri, GTIMER_VIRT); | |
2710 | } | |
2711 | ||
2712 | static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2713 | uint64_t value) | |
2714 | { | |
2715 | gt_tval_write(env, ri, GTIMER_VIRT, value); | |
2716 | } | |
2717 | ||
2718 | static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2719 | uint64_t value) | |
2720 | { | |
2721 | gt_ctl_write(env, ri, GTIMER_VIRT, value); | |
2722 | } | |
2723 | ||
edac4d8a EI |
2724 | static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2725 | uint64_t value) | |
2726 | { | |
2fc0cc0e | 2727 | ARMCPU *cpu = env_archcpu(env); |
edac4d8a | 2728 | |
194cbc49 | 2729 | trace_arm_gt_cntvoff_write(value); |
edac4d8a EI |
2730 | raw_write(env, ri, value); |
2731 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
2732 | } | |
2733 | ||
bb5972e4 RH |
2734 | static uint64_t gt_virt_redir_cval_read(CPUARMState *env, |
2735 | const ARMCPRegInfo *ri) | |
2736 | { | |
2737 | int timeridx = gt_virt_redir_timeridx(env); | |
2738 | return env->cp15.c14_timer[timeridx].cval; | |
2739 | } | |
2740 | ||
2741 | static void gt_virt_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2742 | uint64_t value) | |
2743 | { | |
2744 | int timeridx = gt_virt_redir_timeridx(env); | |
2745 | gt_cval_write(env, ri, timeridx, value); | |
2746 | } | |
2747 | ||
2748 | static uint64_t gt_virt_redir_tval_read(CPUARMState *env, | |
2749 | const ARMCPRegInfo *ri) | |
2750 | { | |
2751 | int timeridx = gt_virt_redir_timeridx(env); | |
2752 | return gt_tval_read(env, ri, timeridx); | |
2753 | } | |
2754 | ||
2755 | static void gt_virt_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2756 | uint64_t value) | |
2757 | { | |
2758 | int timeridx = gt_virt_redir_timeridx(env); | |
2759 | gt_tval_write(env, ri, timeridx, value); | |
2760 | } | |
2761 | ||
2762 | static uint64_t gt_virt_redir_ctl_read(CPUARMState *env, | |
2763 | const ARMCPRegInfo *ri) | |
2764 | { | |
2765 | int timeridx = gt_virt_redir_timeridx(env); | |
2766 | return env->cp15.c14_timer[timeridx].ctl; | |
2767 | } | |
2768 | ||
2769 | static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2770 | uint64_t value) | |
2771 | { | |
2772 | int timeridx = gt_virt_redir_timeridx(env); | |
2773 | gt_ctl_write(env, ri, timeridx, value); | |
2774 | } | |
2775 | ||
b0e66d95 EI |
2776 | static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2777 | { | |
2778 | gt_timer_reset(env, ri, GTIMER_HYP); | |
2779 | } | |
2780 | ||
2781 | static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2782 | uint64_t value) | |
2783 | { | |
2784 | gt_cval_write(env, ri, GTIMER_HYP, value); | |
2785 | } | |
2786 | ||
2787 | static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2788 | { | |
2789 | return gt_tval_read(env, ri, GTIMER_HYP); | |
2790 | } | |
2791 | ||
2792 | static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2793 | uint64_t value) | |
2794 | { | |
2795 | gt_tval_write(env, ri, GTIMER_HYP, value); | |
2796 | } | |
2797 | ||
2798 | static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2799 | uint64_t value) | |
2800 | { | |
2801 | gt_ctl_write(env, ri, GTIMER_HYP, value); | |
2802 | } | |
2803 | ||
b4d3978c PM |
2804 | static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2805 | { | |
2806 | gt_timer_reset(env, ri, GTIMER_SEC); | |
2807 | } | |
2808 | ||
2809 | static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2810 | uint64_t value) | |
2811 | { | |
2812 | gt_cval_write(env, ri, GTIMER_SEC, value); | |
2813 | } | |
2814 | ||
2815 | static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2816 | { | |
2817 | return gt_tval_read(env, ri, GTIMER_SEC); | |
2818 | } | |
2819 | ||
2820 | static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2821 | uint64_t value) | |
2822 | { | |
2823 | gt_tval_write(env, ri, GTIMER_SEC, value); | |
2824 | } | |
2825 | ||
2826 | static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2827 | uint64_t value) | |
2828 | { | |
2829 | gt_ctl_write(env, ri, GTIMER_SEC, value); | |
2830 | } | |
2831 | ||
8c94b071 RH |
2832 | static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2833 | { | |
2834 | gt_timer_reset(env, ri, GTIMER_HYPVIRT); | |
2835 | } | |
2836 | ||
2837 | static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2838 | uint64_t value) | |
2839 | { | |
2840 | gt_cval_write(env, ri, GTIMER_HYPVIRT, value); | |
2841 | } | |
2842 | ||
2843 | static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2844 | { | |
2845 | return gt_tval_read(env, ri, GTIMER_HYPVIRT); | |
2846 | } | |
2847 | ||
2848 | static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2849 | uint64_t value) | |
2850 | { | |
2851 | gt_tval_write(env, ri, GTIMER_HYPVIRT, value); | |
2852 | } | |
2853 | ||
2854 | static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2855 | uint64_t value) | |
2856 | { | |
2857 | gt_ctl_write(env, ri, GTIMER_HYPVIRT, value); | |
2858 | } | |
2859 | ||
55d284af PM |
2860 | void arm_gt_ptimer_cb(void *opaque) |
2861 | { | |
2862 | ARMCPU *cpu = opaque; | |
2863 | ||
2864 | gt_recalc_timer(cpu, GTIMER_PHYS); | |
2865 | } | |
2866 | ||
2867 | void arm_gt_vtimer_cb(void *opaque) | |
2868 | { | |
2869 | ARMCPU *cpu = opaque; | |
2870 | ||
2871 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
2872 | } | |
2873 | ||
b0e66d95 EI |
2874 | void arm_gt_htimer_cb(void *opaque) |
2875 | { | |
2876 | ARMCPU *cpu = opaque; | |
2877 | ||
2878 | gt_recalc_timer(cpu, GTIMER_HYP); | |
2879 | } | |
2880 | ||
b4d3978c PM |
2881 | void arm_gt_stimer_cb(void *opaque) |
2882 | { | |
2883 | ARMCPU *cpu = opaque; | |
2884 | ||
2885 | gt_recalc_timer(cpu, GTIMER_SEC); | |
2886 | } | |
2887 | ||
8c94b071 RH |
2888 | void arm_gt_hvtimer_cb(void *opaque) |
2889 | { | |
2890 | ARMCPU *cpu = opaque; | |
2891 | ||
2892 | gt_recalc_timer(cpu, GTIMER_HYPVIRT); | |
2893 | } | |
2894 | ||
96eec6b2 AJ |
2895 | static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque) |
2896 | { | |
2897 | ARMCPU *cpu = env_archcpu(env); | |
2898 | ||
2899 | cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz; | |
2900 | } | |
2901 | ||
55d284af PM |
2902 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
2903 | /* Note that CNTFRQ is purely reads-as-written for the benefit | |
2904 | * of software; writing it doesn't actually change the timer frequency. | |
2905 | * Our reset value matches the fixed frequency we implement the timer at. | |
2906 | */ | |
2907 | { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 2908 | .type = ARM_CP_ALIAS, |
a7adc4b7 PM |
2909 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, |
2910 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), | |
a7adc4b7 PM |
2911 | }, |
2912 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, | |
2913 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
2914 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
55d284af | 2915 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), |
96eec6b2 | 2916 | .resetfn = arm_gt_cntfrq_reset, |
55d284af PM |
2917 | }, |
2918 | /* overall control: mostly access permissions */ | |
a7adc4b7 PM |
2919 | { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, |
2920 | .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, | |
55d284af PM |
2921 | .access = PL1_RW, |
2922 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), | |
2923 | .resetvalue = 0, | |
2924 | }, | |
2925 | /* per-timer control */ | |
2926 | { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
9ff9dd3c | 2927 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 2928 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
a7adc4b7 PM |
2929 | .accessfn = gt_ptimer_access, |
2930 | .fieldoffset = offsetoflow32(CPUARMState, | |
2931 | cp15.c14_timer[GTIMER_PHYS].ctl), | |
bb5972e4 RH |
2932 | .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read, |
2933 | .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write, | |
a7adc4b7 | 2934 | }, |
9c513e78 | 2935 | { .name = "CNTP_CTL_S", |
9ff9dd3c PM |
2936 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, |
2937 | .secure = ARM_CP_SECSTATE_S, | |
daf1dc5f | 2938 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
9ff9dd3c PM |
2939 | .accessfn = gt_ptimer_access, |
2940 | .fieldoffset = offsetoflow32(CPUARMState, | |
2941 | cp15.c14_timer[GTIMER_SEC].ctl), | |
2942 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
2943 | }, | |
a7adc4b7 PM |
2944 | { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, |
2945 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, | |
daf1dc5f | 2946 | .type = ARM_CP_IO, .access = PL0_RW, |
a7adc4b7 | 2947 | .accessfn = gt_ptimer_access, |
55d284af PM |
2948 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), |
2949 | .resetvalue = 0, | |
bb5972e4 RH |
2950 | .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read, |
2951 | .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write, | |
55d284af PM |
2952 | }, |
2953 | { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, | |
daf1dc5f | 2954 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
a7adc4b7 PM |
2955 | .accessfn = gt_vtimer_access, |
2956 | .fieldoffset = offsetoflow32(CPUARMState, | |
2957 | cp15.c14_timer[GTIMER_VIRT].ctl), | |
bb5972e4 RH |
2958 | .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read, |
2959 | .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write, | |
a7adc4b7 PM |
2960 | }, |
2961 | { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
2962 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, | |
daf1dc5f | 2963 | .type = ARM_CP_IO, .access = PL0_RW, |
a7adc4b7 | 2964 | .accessfn = gt_vtimer_access, |
55d284af PM |
2965 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), |
2966 | .resetvalue = 0, | |
bb5972e4 RH |
2967 | .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read, |
2968 | .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write, | |
55d284af PM |
2969 | }, |
2970 | /* TimerValue views: a 32 bit downcounting view of the underlying state */ | |
2971 | { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
9ff9dd3c | 2972 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 2973 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
00108f2d | 2974 | .accessfn = gt_ptimer_access, |
bb5972e4 | 2975 | .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write, |
55d284af | 2976 | }, |
9c513e78 | 2977 | { .name = "CNTP_TVAL_S", |
9ff9dd3c PM |
2978 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, |
2979 | .secure = ARM_CP_SECSTATE_S, | |
daf1dc5f | 2980 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
9ff9dd3c PM |
2981 | .accessfn = gt_ptimer_access, |
2982 | .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, | |
2983 | }, | |
a7adc4b7 PM |
2984 | { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
2985 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, | |
daf1dc5f | 2986 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
0e3eca4c | 2987 | .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, |
bb5972e4 | 2988 | .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write, |
a7adc4b7 | 2989 | }, |
55d284af | 2990 | { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, |
daf1dc5f | 2991 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
00108f2d | 2992 | .accessfn = gt_vtimer_access, |
bb5972e4 | 2993 | .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write, |
55d284af | 2994 | }, |
a7adc4b7 PM |
2995 | { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
2996 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, | |
daf1dc5f | 2997 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
0e3eca4c | 2998 | .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, |
bb5972e4 | 2999 | .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write, |
a7adc4b7 | 3000 | }, |
55d284af PM |
3001 | /* The counter itself */ |
3002 | { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, | |
7a0e58fa | 3003 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 3004 | .accessfn = gt_pct_access, |
a7adc4b7 PM |
3005 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
3006 | }, | |
3007 | { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, | |
3008 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, | |
7a0e58fa | 3009 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 3010 | .accessfn = gt_pct_access, .readfn = gt_cnt_read, |
55d284af PM |
3011 | }, |
3012 | { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, | |
7a0e58fa | 3013 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 3014 | .accessfn = gt_vct_access, |
edac4d8a | 3015 | .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, |
a7adc4b7 PM |
3016 | }, |
3017 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
3018 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
7a0e58fa | 3019 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 3020 | .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, |
55d284af PM |
3021 | }, |
3022 | /* Comparison value, indicating when the timer goes off */ | |
3023 | { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, | |
9ff9dd3c | 3024 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 3025 | .access = PL0_RW, |
7a0e58fa | 3026 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 3027 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), |
b061a82b | 3028 | .accessfn = gt_ptimer_access, |
bb5972e4 RH |
3029 | .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read, |
3030 | .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write, | |
a7adc4b7 | 3031 | }, |
9c513e78 | 3032 | { .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2, |
9ff9dd3c | 3033 | .secure = ARM_CP_SECSTATE_S, |
daf1dc5f | 3034 | .access = PL0_RW, |
9ff9dd3c PM |
3035 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
3036 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
3037 | .accessfn = gt_ptimer_access, | |
3038 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
3039 | }, | |
a7adc4b7 PM |
3040 | { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, |
3041 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, | |
daf1dc5f | 3042 | .access = PL0_RW, |
a7adc4b7 PM |
3043 | .type = ARM_CP_IO, |
3044 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
12cde08a | 3045 | .resetvalue = 0, .accessfn = gt_ptimer_access, |
bb5972e4 RH |
3046 | .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read, |
3047 | .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write, | |
55d284af PM |
3048 | }, |
3049 | { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, | |
daf1dc5f | 3050 | .access = PL0_RW, |
7a0e58fa | 3051 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 3052 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), |
b061a82b | 3053 | .accessfn = gt_vtimer_access, |
bb5972e4 RH |
3054 | .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read, |
3055 | .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write, | |
a7adc4b7 PM |
3056 | }, |
3057 | { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
3058 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, | |
daf1dc5f | 3059 | .access = PL0_RW, |
a7adc4b7 PM |
3060 | .type = ARM_CP_IO, |
3061 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
3062 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
bb5972e4 RH |
3063 | .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read, |
3064 | .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write, | |
55d284af | 3065 | }, |
b4d3978c PM |
3066 | /* Secure timer -- this is actually restricted to only EL3 |
3067 | * and configurably Secure-EL1 via the accessfn. | |
3068 | */ | |
3069 | { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, | |
3070 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, | |
3071 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, | |
3072 | .accessfn = gt_stimer_access, | |
3073 | .readfn = gt_sec_tval_read, | |
3074 | .writefn = gt_sec_tval_write, | |
3075 | .resetfn = gt_sec_timer_reset, | |
3076 | }, | |
3077 | { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64, | |
3078 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1, | |
3079 | .type = ARM_CP_IO, .access = PL1_RW, | |
3080 | .accessfn = gt_stimer_access, | |
3081 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), | |
3082 | .resetvalue = 0, | |
3083 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
3084 | }, | |
3085 | { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, | |
3086 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, | |
3087 | .type = ARM_CP_IO, .access = PL1_RW, | |
3088 | .accessfn = gt_stimer_access, | |
3089 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
3090 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
3091 | }, | |
55d284af PM |
3092 | REGINFO_SENTINEL |
3093 | }; | |
3094 | ||
bb5972e4 RH |
3095 | static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3096 | bool isread) | |
3097 | { | |
3098 | if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { | |
3099 | return CP_ACCESS_TRAP; | |
3100 | } | |
3101 | return CP_ACCESS_OK; | |
3102 | } | |
3103 | ||
55d284af | 3104 | #else |
26c4a83b AB |
3105 | |
3106 | /* In user-mode most of the generic timer registers are inaccessible | |
3107 | * however modern kernels (4.12+) allow access to cntvct_el0 | |
55d284af | 3108 | */ |
26c4a83b AB |
3109 | |
3110 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3111 | { | |
7def8754 AJ |
3112 | ARMCPU *cpu = env_archcpu(env); |
3113 | ||
26c4a83b AB |
3114 | /* Currently we have no support for QEMUTimer in linux-user so we |
3115 | * can't call gt_get_countervalue(env), instead we directly | |
3116 | * call the lower level functions. | |
3117 | */ | |
7def8754 | 3118 | return cpu_get_clock() / gt_cntfrq_period_ns(cpu); |
26c4a83b AB |
3119 | } |
3120 | ||
6cc7a3ae | 3121 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
26c4a83b AB |
3122 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, |
3123 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
3124 | .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */, | |
3125 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), | |
3126 | .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE, | |
3127 | }, | |
3128 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
3129 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
3130 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
3131 | .readfn = gt_virt_cnt_read, | |
3132 | }, | |
6cc7a3ae PM |
3133 | REGINFO_SENTINEL |
3134 | }; | |
3135 | ||
55d284af PM |
3136 | #endif |
3137 | ||
c4241c7d | 3138 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 3139 | { |
891a2fe7 | 3140 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8d5c773e | 3141 | raw_write(env, ri, value); |
891a2fe7 | 3142 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8d5c773e | 3143 | raw_write(env, ri, value & 0xfffff6ff); |
4a501606 | 3144 | } else { |
8d5c773e | 3145 | raw_write(env, ri, value & 0xfffff1ff); |
4a501606 | 3146 | } |
4a501606 PM |
3147 | } |
3148 | ||
3149 | #ifndef CONFIG_USER_ONLY | |
3150 | /* get_phys_addr() isn't present for user-mode-only targets */ | |
702a9357 | 3151 | |
3f208fd7 PM |
3152 | static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3153 | bool isread) | |
92611c00 PM |
3154 | { |
3155 | if (ri->opc2 & 4) { | |
926c1b97 | 3156 | /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in |
87562e4f PM |
3157 | * Secure EL1 (which can only happen if EL3 is AArch64). |
3158 | * They are simply UNDEF if executed from NS EL1. | |
3159 | * They function normally from EL2 or EL3. | |
92611c00 | 3160 | */ |
87562e4f PM |
3161 | if (arm_current_el(env) == 1) { |
3162 | if (arm_is_secure_below_el3(env)) { | |
926c1b97 RDC |
3163 | if (env->cp15.scr_el3 & SCR_EEL2) { |
3164 | return CP_ACCESS_TRAP_UNCATEGORIZED_EL2; | |
3165 | } | |
87562e4f PM |
3166 | return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; |
3167 | } | |
3168 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
3169 | } | |
92611c00 PM |
3170 | } |
3171 | return CP_ACCESS_OK; | |
3172 | } | |
3173 | ||
9fb005b0 | 3174 | #ifdef CONFIG_TCG |
060e8a48 | 3175 | static uint64_t do_ats_write(CPUARMState *env, uint64_t value, |
03ae85f8 | 3176 | MMUAccessType access_type, ARMMMUIdx mmu_idx) |
4a501606 | 3177 | { |
a8170e5e | 3178 | hwaddr phys_addr; |
4a501606 PM |
3179 | target_ulong page_size; |
3180 | int prot; | |
b7cc4e82 | 3181 | bool ret; |
01c097f7 | 3182 | uint64_t par64; |
1313e2d7 | 3183 | bool format64 = false; |
8bf5b6a9 | 3184 | MemTxAttrs attrs = {}; |
e14b5a23 | 3185 | ARMMMUFaultInfo fi = {}; |
5b2d261d | 3186 | ARMCacheAttrs cacheattrs = {}; |
4a501606 | 3187 | |
5b2d261d | 3188 | ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, |
bc52bfeb | 3189 | &prot, &page_size, &fi, &cacheattrs); |
1313e2d7 | 3190 | |
0710b2fa PM |
3191 | if (ret) { |
3192 | /* | |
3193 | * Some kinds of translation fault must cause exceptions rather | |
3194 | * than being reported in the PAR. | |
3195 | */ | |
3196 | int current_el = arm_current_el(env); | |
3197 | int target_el; | |
3198 | uint32_t syn, fsr, fsc; | |
3199 | bool take_exc = false; | |
3200 | ||
b1a10c86 | 3201 | if (fi.s1ptw && current_el == 1 |
fee7aa46 | 3202 | && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { |
0710b2fa PM |
3203 | /* |
3204 | * Synchronous stage 2 fault on an access made as part of the | |
3205 | * translation table walk for AT S1E0* or AT S1E1* insn | |
3206 | * executed from NS EL1. If this is a synchronous external abort | |
3207 | * and SCR_EL3.EA == 1, then we take a synchronous external abort | |
3208 | * to EL3. Otherwise the fault is taken as an exception to EL2, | |
3209 | * and HPFAR_EL2 holds the faulting IPA. | |
3210 | */ | |
3211 | if (fi.type == ARMFault_SyncExternalOnWalk && | |
3212 | (env->cp15.scr_el3 & SCR_EA)) { | |
3213 | target_el = 3; | |
3214 | } else { | |
3215 | env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; | |
9861248f RDC |
3216 | if (arm_is_secure_below_el3(env) && fi.s1ns) { |
3217 | env->cp15.hpfar_el2 |= HPFAR_NS; | |
3218 | } | |
0710b2fa PM |
3219 | target_el = 2; |
3220 | } | |
3221 | take_exc = true; | |
3222 | } else if (fi.type == ARMFault_SyncExternalOnWalk) { | |
3223 | /* | |
3224 | * Synchronous external aborts during a translation table walk | |
3225 | * are taken as Data Abort exceptions. | |
3226 | */ | |
3227 | if (fi.stage2) { | |
3228 | if (current_el == 3) { | |
3229 | target_el = 3; | |
3230 | } else { | |
3231 | target_el = 2; | |
3232 | } | |
3233 | } else { | |
3234 | target_el = exception_target_el(env); | |
3235 | } | |
3236 | take_exc = true; | |
3237 | } | |
3238 | ||
3239 | if (take_exc) { | |
3240 | /* Construct FSR and FSC using same logic as arm_deliver_fault() */ | |
3241 | if (target_el == 2 || arm_el_is_aa64(env, target_el) || | |
3242 | arm_s1_regime_using_lpae_format(env, mmu_idx)) { | |
3243 | fsr = arm_fi_to_lfsc(&fi); | |
3244 | fsc = extract32(fsr, 0, 6); | |
3245 | } else { | |
3246 | fsr = arm_fi_to_sfsc(&fi); | |
3247 | fsc = 0x3f; | |
3248 | } | |
3249 | /* | |
3250 | * Report exception with ESR indicating a fault due to a | |
3251 | * translation table walk for a cache maintenance instruction. | |
3252 | */ | |
e24fd076 | 3253 | syn = syn_data_abort_no_iss(current_el == target_el, 0, |
0710b2fa PM |
3254 | fi.ea, 1, fi.s1ptw, 1, fsc); |
3255 | env->exception.vaddress = value; | |
3256 | env->exception.fsr = fsr; | |
3257 | raise_exception(env, EXCP_DATA_ABORT, syn, target_el); | |
3258 | } | |
3259 | } | |
3260 | ||
1313e2d7 EI |
3261 | if (is_a64(env)) { |
3262 | format64 = true; | |
3263 | } else if (arm_feature(env, ARM_FEATURE_LPAE)) { | |
3264 | /* | |
3265 | * ATS1Cxx: | |
3266 | * * TTBCR.EAE determines whether the result is returned using the | |
3267 | * 32-bit or the 64-bit PAR format | |
3268 | * * Instructions executed in Hyp mode always use the 64bit format | |
3269 | * | |
3270 | * ATS1S2NSOxx uses the 64bit format if any of the following is true: | |
3271 | * * The Non-secure TTBCR.EAE bit is set to 1 | |
3272 | * * The implementation includes EL2, and the value of HCR.VM is 1 | |
3273 | * | |
9d1bab33 PM |
3274 | * (Note that HCR.DC makes HCR.VM behave as if it is 1.) |
3275 | * | |
23463e0e | 3276 | * ATS1Hx always uses the 64bit format. |
1313e2d7 EI |
3277 | */ |
3278 | format64 = arm_s1_regime_using_lpae_format(env, mmu_idx); | |
3279 | ||
3280 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
452ef8cb RH |
3281 | if (mmu_idx == ARMMMUIdx_E10_0 || |
3282 | mmu_idx == ARMMMUIdx_E10_1 || | |
3283 | mmu_idx == ARMMMUIdx_E10_1_PAN) { | |
9d1bab33 | 3284 | format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC); |
1313e2d7 EI |
3285 | } else { |
3286 | format64 |= arm_current_el(env) == 2; | |
3287 | } | |
3288 | } | |
3289 | } | |
3290 | ||
3291 | if (format64) { | |
5efe9ed4 | 3292 | /* Create a 64-bit PAR */ |
01c097f7 | 3293 | par64 = (1 << 11); /* LPAE bit always set */ |
b7cc4e82 | 3294 | if (!ret) { |
702a9357 | 3295 | par64 |= phys_addr & ~0xfffULL; |
8bf5b6a9 PM |
3296 | if (!attrs.secure) { |
3297 | par64 |= (1 << 9); /* NS */ | |
3298 | } | |
5b2d261d AB |
3299 | par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */ |
3300 | par64 |= cacheattrs.shareability << 7; /* SH */ | |
4a501606 | 3301 | } else { |
5efe9ed4 PM |
3302 | uint32_t fsr = arm_fi_to_lfsc(&fi); |
3303 | ||
702a9357 | 3304 | par64 |= 1; /* F */ |
b7cc4e82 | 3305 | par64 |= (fsr & 0x3f) << 1; /* FS */ |
0f7b791b PM |
3306 | if (fi.stage2) { |
3307 | par64 |= (1 << 9); /* S */ | |
3308 | } | |
3309 | if (fi.s1ptw) { | |
3310 | par64 |= (1 << 8); /* PTW */ | |
3311 | } | |
4a501606 PM |
3312 | } |
3313 | } else { | |
b7cc4e82 | 3314 | /* fsr is a DFSR/IFSR value for the short descriptor |
702a9357 PM |
3315 | * translation table format (with WnR always clear). |
3316 | * Convert it to a 32-bit PAR. | |
3317 | */ | |
b7cc4e82 | 3318 | if (!ret) { |
702a9357 PM |
3319 | /* We do not set any attribute bits in the PAR */ |
3320 | if (page_size == (1 << 24) | |
3321 | && arm_feature(env, ARM_FEATURE_V7)) { | |
01c097f7 | 3322 | par64 = (phys_addr & 0xff000000) | (1 << 1); |
702a9357 | 3323 | } else { |
01c097f7 | 3324 | par64 = phys_addr & 0xfffff000; |
702a9357 | 3325 | } |
8bf5b6a9 PM |
3326 | if (!attrs.secure) { |
3327 | par64 |= (1 << 9); /* NS */ | |
3328 | } | |
702a9357 | 3329 | } else { |
5efe9ed4 PM |
3330 | uint32_t fsr = arm_fi_to_sfsc(&fi); |
3331 | ||
b7cc4e82 PC |
3332 | par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | |
3333 | ((fsr & 0xf) << 1) | 1; | |
702a9357 | 3334 | } |
4a501606 | 3335 | } |
060e8a48 PM |
3336 | return par64; |
3337 | } | |
9fb005b0 | 3338 | #endif /* CONFIG_TCG */ |
060e8a48 PM |
3339 | |
3340 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | |
3341 | { | |
9fb005b0 | 3342 | #ifdef CONFIG_TCG |
03ae85f8 | 3343 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
060e8a48 | 3344 | uint64_t par64; |
d3649702 PM |
3345 | ARMMMUIdx mmu_idx; |
3346 | int el = arm_current_el(env); | |
3347 | bool secure = arm_is_secure_below_el3(env); | |
060e8a48 | 3348 | |
d3649702 PM |
3349 | switch (ri->opc2 & 6) { |
3350 | case 0: | |
04b07d29 | 3351 | /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */ |
d3649702 PM |
3352 | switch (el) { |
3353 | case 3: | |
127b2b08 | 3354 | mmu_idx = ARMMMUIdx_SE3; |
d3649702 PM |
3355 | break; |
3356 | case 2: | |
b6ad6062 | 3357 | g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ |
04b07d29 | 3358 | /* fall through */ |
d3649702 | 3359 | case 1: |
04b07d29 | 3360 | if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) { |
b1a10c86 | 3361 | mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN |
04b07d29 RH |
3362 | : ARMMMUIdx_Stage1_E1_PAN); |
3363 | } else { | |
b1a10c86 | 3364 | mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1; |
04b07d29 | 3365 | } |
d3649702 PM |
3366 | break; |
3367 | default: | |
3368 | g_assert_not_reached(); | |
3369 | } | |
3370 | break; | |
3371 | case 2: | |
3372 | /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ | |
3373 | switch (el) { | |
3374 | case 3: | |
fba37aed | 3375 | mmu_idx = ARMMMUIdx_SE10_0; |
d3649702 PM |
3376 | break; |
3377 | case 2: | |
b1a10c86 | 3378 | g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ |
2859d7b5 | 3379 | mmu_idx = ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3380 | break; |
3381 | case 1: | |
b1a10c86 | 3382 | mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3383 | break; |
3384 | default: | |
3385 | g_assert_not_reached(); | |
3386 | } | |
3387 | break; | |
3388 | case 4: | |
3389 | /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ | |
01b98b68 | 3390 | mmu_idx = ARMMMUIdx_E10_1; |
d3649702 PM |
3391 | break; |
3392 | case 6: | |
3393 | /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ | |
01b98b68 | 3394 | mmu_idx = ARMMMUIdx_E10_0; |
d3649702 PM |
3395 | break; |
3396 | default: | |
3397 | g_assert_not_reached(); | |
3398 | } | |
3399 | ||
3400 | par64 = do_ats_write(env, value, access_type, mmu_idx); | |
01c097f7 FA |
3401 | |
3402 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
9fb005b0 PMD |
3403 | #else |
3404 | /* Handled by hardware accelerator. */ | |
3405 | g_assert_not_reached(); | |
3406 | #endif /* CONFIG_TCG */ | |
4a501606 | 3407 | } |
060e8a48 | 3408 | |
14db7fe0 PM |
3409 | static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3410 | uint64_t value) | |
3411 | { | |
9fb005b0 | 3412 | #ifdef CONFIG_TCG |
03ae85f8 | 3413 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
14db7fe0 PM |
3414 | uint64_t par64; |
3415 | ||
e013b741 | 3416 | par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2); |
14db7fe0 PM |
3417 | |
3418 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
9fb005b0 PMD |
3419 | #else |
3420 | /* Handled by hardware accelerator. */ | |
3421 | g_assert_not_reached(); | |
3422 | #endif /* CONFIG_TCG */ | |
14db7fe0 PM |
3423 | } |
3424 | ||
3f208fd7 PM |
3425 | static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3426 | bool isread) | |
2a47df95 | 3427 | { |
926c1b97 RDC |
3428 | if (arm_current_el(env) == 3 && |
3429 | !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) { | |
2a47df95 PM |
3430 | return CP_ACCESS_TRAP; |
3431 | } | |
3432 | return CP_ACCESS_OK; | |
3433 | } | |
3434 | ||
060e8a48 PM |
3435 | static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, |
3436 | uint64_t value) | |
3437 | { | |
9fb005b0 | 3438 | #ifdef CONFIG_TCG |
03ae85f8 | 3439 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
d3649702 PM |
3440 | ARMMMUIdx mmu_idx; |
3441 | int secure = arm_is_secure_below_el3(env); | |
3442 | ||
3443 | switch (ri->opc2 & 6) { | |
3444 | case 0: | |
3445 | switch (ri->opc1) { | |
04b07d29 RH |
3446 | case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ |
3447 | if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) { | |
b1a10c86 | 3448 | mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN |
04b07d29 RH |
3449 | : ARMMMUIdx_Stage1_E1_PAN); |
3450 | } else { | |
b1a10c86 | 3451 | mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1; |
04b07d29 | 3452 | } |
d3649702 PM |
3453 | break; |
3454 | case 4: /* AT S1E2R, AT S1E2W */ | |
b6ad6062 | 3455 | mmu_idx = secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2; |
d3649702 PM |
3456 | break; |
3457 | case 6: /* AT S1E3R, AT S1E3W */ | |
127b2b08 | 3458 | mmu_idx = ARMMMUIdx_SE3; |
d3649702 PM |
3459 | break; |
3460 | default: | |
3461 | g_assert_not_reached(); | |
3462 | } | |
3463 | break; | |
3464 | case 2: /* AT S1E0R, AT S1E0W */ | |
b1a10c86 | 3465 | mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3466 | break; |
3467 | case 4: /* AT S12E1R, AT S12E1W */ | |
fba37aed | 3468 | mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1; |
d3649702 PM |
3469 | break; |
3470 | case 6: /* AT S12E0R, AT S12E0W */ | |
fba37aed | 3471 | mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0; |
d3649702 PM |
3472 | break; |
3473 | default: | |
3474 | g_assert_not_reached(); | |
3475 | } | |
060e8a48 | 3476 | |
d3649702 | 3477 | env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); |
9fb005b0 PMD |
3478 | #else |
3479 | /* Handled by hardware accelerator. */ | |
3480 | g_assert_not_reached(); | |
3481 | #endif /* CONFIG_TCG */ | |
060e8a48 | 3482 | } |
4a501606 PM |
3483 | #endif |
3484 | ||
3485 | static const ARMCPRegInfo vapa_cp_reginfo[] = { | |
3486 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, | |
3487 | .access = PL1_RW, .resetvalue = 0, | |
01c097f7 FA |
3488 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), |
3489 | offsetoflow32(CPUARMState, cp15.par_ns) }, | |
4a501606 PM |
3490 | .writefn = par_write }, |
3491 | #ifndef CONFIG_USER_ONLY | |
87562e4f | 3492 | /* This underdecoding is safe because the reginfo is NO_RAW. */ |
4a501606 | 3493 | { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, |
92611c00 | 3494 | .access = PL1_W, .accessfn = ats_access, |
0710b2fa | 3495 | .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
4a501606 PM |
3496 | #endif |
3497 | REGINFO_SENTINEL | |
3498 | }; | |
3499 | ||
18032bec PM |
3500 | /* Return basic MPU access permission bits. */ |
3501 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
3502 | { | |
3503 | uint32_t ret; | |
3504 | uint32_t mask; | |
3505 | int i; | |
3506 | ret = 0; | |
3507 | mask = 3; | |
3508 | for (i = 0; i < 16; i += 2) { | |
3509 | ret |= (val >> i) & mask; | |
3510 | mask <<= 2; | |
3511 | } | |
3512 | return ret; | |
3513 | } | |
3514 | ||
3515 | /* Pad basic MPU access permission bits to extended format. */ | |
3516 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
3517 | { | |
3518 | uint32_t ret; | |
3519 | uint32_t mask; | |
3520 | int i; | |
3521 | ret = 0; | |
3522 | mask = 3; | |
3523 | for (i = 0; i < 16; i += 2) { | |
3524 | ret |= (val & mask) << i; | |
3525 | mask <<= 2; | |
3526 | } | |
3527 | return ret; | |
3528 | } | |
3529 | ||
c4241c7d PM |
3530 | static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3531 | uint64_t value) | |
18032bec | 3532 | { |
7e09797c | 3533 | env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3534 | } |
3535 | ||
c4241c7d | 3536 | static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3537 | { |
7e09797c | 3538 | return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); |
18032bec PM |
3539 | } |
3540 | ||
c4241c7d PM |
3541 | static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3542 | uint64_t value) | |
18032bec | 3543 | { |
7e09797c | 3544 | env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3545 | } |
3546 | ||
c4241c7d | 3547 | static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3548 | { |
7e09797c | 3549 | return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); |
18032bec PM |
3550 | } |
3551 | ||
6cb0b013 PC |
3552 | static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) |
3553 | { | |
3554 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); | |
3555 | ||
3556 | if (!u32p) { | |
3557 | return 0; | |
3558 | } | |
3559 | ||
1bc04a88 | 3560 | u32p += env->pmsav7.rnr[M_REG_NS]; |
6cb0b013 PC |
3561 | return *u32p; |
3562 | } | |
3563 | ||
3564 | static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3565 | uint64_t value) | |
3566 | { | |
2fc0cc0e | 3567 | ARMCPU *cpu = env_archcpu(env); |
6cb0b013 PC |
3568 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); |
3569 | ||
3570 | if (!u32p) { | |
3571 | return; | |
3572 | } | |
3573 | ||
1bc04a88 | 3574 | u32p += env->pmsav7.rnr[M_REG_NS]; |
d10eb08f | 3575 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ |
6cb0b013 PC |
3576 | *u32p = value; |
3577 | } | |
3578 | ||
6cb0b013 PC |
3579 | static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3580 | uint64_t value) | |
3581 | { | |
2fc0cc0e | 3582 | ARMCPU *cpu = env_archcpu(env); |
6cb0b013 PC |
3583 | uint32_t nrgs = cpu->pmsav7_dregion; |
3584 | ||
3585 | if (value >= nrgs) { | |
3586 | qemu_log_mask(LOG_GUEST_ERROR, | |
3587 | "PMSAv7 RGNR write >= # supported regions, %" PRIu32 | |
3588 | " > %" PRIu32 "\n", (uint32_t)value, nrgs); | |
3589 | return; | |
3590 | } | |
3591 | ||
3592 | raw_write(env, ri, value); | |
3593 | } | |
3594 | ||
3595 | static const ARMCPRegInfo pmsav7_cp_reginfo[] = { | |
69ceea64 PM |
3596 | /* Reset for all these registers is handled in arm_cpu_reset(), |
3597 | * because the PMSAv7 is also used by M-profile CPUs, which do | |
3598 | * not register cpregs but still need the state to be reset. | |
3599 | */ | |
6cb0b013 PC |
3600 | { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, |
3601 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3602 | .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), | |
69ceea64 PM |
3603 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3604 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3605 | { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, |
3606 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3607 | .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), | |
69ceea64 PM |
3608 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3609 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3610 | { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, |
3611 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3612 | .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), | |
69ceea64 PM |
3613 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3614 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3615 | { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, |
3616 | .access = PL1_RW, | |
1bc04a88 | 3617 | .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), |
69ceea64 PM |
3618 | .writefn = pmsav7_rgnr_write, |
3619 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3620 | REGINFO_SENTINEL |
3621 | }; | |
3622 | ||
18032bec PM |
3623 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { |
3624 | { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 3625 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 3626 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
18032bec PM |
3627 | .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, |
3628 | { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 3629 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 3630 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
18032bec PM |
3631 | .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, |
3632 | { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, | |
3633 | .access = PL1_RW, | |
7e09797c PM |
3634 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
3635 | .resetvalue = 0, }, | |
18032bec PM |
3636 | { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, |
3637 | .access = PL1_RW, | |
7e09797c PM |
3638 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
3639 | .resetvalue = 0, }, | |
ecce5c3c PM |
3640 | { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
3641 | .access = PL1_RW, | |
3642 | .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, | |
3643 | { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
3644 | .access = PL1_RW, | |
3645 | .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, | |
06d76f31 | 3646 | /* Protection region base and size registers */ |
e508a92b PM |
3647 | { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, |
3648 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3649 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, | |
3650 | { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, | |
3651 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3652 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, | |
3653 | { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, | |
3654 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3655 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, | |
3656 | { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, | |
3657 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3658 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, | |
3659 | { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, | |
3660 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3661 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, | |
3662 | { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, | |
3663 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3664 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, | |
3665 | { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, | |
3666 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3667 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, | |
3668 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | |
3669 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3670 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | |
18032bec PM |
3671 | REGINFO_SENTINEL |
3672 | }; | |
3673 | ||
c4241c7d PM |
3674 | static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3675 | uint64_t value) | |
ecce5c3c | 3676 | { |
11f136ee | 3677 | TCR *tcr = raw_ptr(env, ri); |
2ebcebe2 PM |
3678 | int maskshift = extract32(value, 0, 3); |
3679 | ||
e389be16 FA |
3680 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
3681 | if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { | |
3682 | /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when | |
3683 | * using Long-desciptor translation table format */ | |
3684 | value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); | |
3685 | } else if (arm_feature(env, ARM_FEATURE_EL3)) { | |
3686 | /* In an implementation that includes the Security Extensions | |
3687 | * TTBCR has additional fields PD0 [4] and PD1 [5] for | |
3688 | * Short-descriptor translation table format. | |
3689 | */ | |
3690 | value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; | |
3691 | } else { | |
3692 | value &= TTBCR_N; | |
3693 | } | |
e42c4db3 | 3694 | } |
e389be16 | 3695 | |
b6af0975 | 3696 | /* Update the masks corresponding to the TCR bank being written |
11f136ee | 3697 | * Note that we always calculate mask and base_mask, but |
e42c4db3 | 3698 | * they are only used for short-descriptor tables (ie if EAE is 0); |
11f136ee FA |
3699 | * for long-descriptor tables the TCR fields are used differently |
3700 | * and the mask and base_mask values are meaningless. | |
e42c4db3 | 3701 | */ |
11f136ee FA |
3702 | tcr->raw_tcr = value; |
3703 | tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift); | |
3704 | tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift); | |
ecce5c3c PM |
3705 | } |
3706 | ||
c4241c7d PM |
3707 | static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3708 | uint64_t value) | |
d4e6df63 | 3709 | { |
2fc0cc0e | 3710 | ARMCPU *cpu = env_archcpu(env); |
ab638a32 | 3711 | TCR *tcr = raw_ptr(env, ri); |
00c8cb0a | 3712 | |
d4e6df63 PM |
3713 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
3714 | /* With LPAE the TTBCR could result in a change of ASID | |
3715 | * via the TTBCR.A1 bit, so do a TLB flush. | |
3716 | */ | |
d10eb08f | 3717 | tlb_flush(CPU(cpu)); |
d4e6df63 | 3718 | } |
ab638a32 RH |
3719 | /* Preserve the high half of TCR_EL1, set via TTBCR2. */ |
3720 | value = deposit64(tcr->raw_tcr, 0, 32, value); | |
c4241c7d | 3721 | vmsa_ttbcr_raw_write(env, ri, value); |
d4e6df63 PM |
3722 | } |
3723 | ||
ecce5c3c PM |
3724 | static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
3725 | { | |
11f136ee FA |
3726 | TCR *tcr = raw_ptr(env, ri); |
3727 | ||
3728 | /* Reset both the TCR as well as the masks corresponding to the bank of | |
3729 | * the TCR being reset. | |
3730 | */ | |
3731 | tcr->raw_tcr = 0; | |
3732 | tcr->mask = 0; | |
3733 | tcr->base_mask = 0xffffc000u; | |
ecce5c3c PM |
3734 | } |
3735 | ||
d06dc933 | 3736 | static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, |
cb2e37df PM |
3737 | uint64_t value) |
3738 | { | |
2fc0cc0e | 3739 | ARMCPU *cpu = env_archcpu(env); |
11f136ee | 3740 | TCR *tcr = raw_ptr(env, ri); |
00c8cb0a | 3741 | |
cb2e37df | 3742 | /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ |
d10eb08f | 3743 | tlb_flush(CPU(cpu)); |
11f136ee | 3744 | tcr->raw_tcr = value; |
cb2e37df PM |
3745 | } |
3746 | ||
327ed10f PM |
3747 | static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3748 | uint64_t value) | |
3749 | { | |
93f379b0 RH |
3750 | /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ |
3751 | if (cpreg_field_is_64bit(ri) && | |
3752 | extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { | |
2fc0cc0e | 3753 | ARMCPU *cpu = env_archcpu(env); |
d10eb08f | 3754 | tlb_flush(CPU(cpu)); |
327ed10f PM |
3755 | } |
3756 | raw_write(env, ri, value); | |
3757 | } | |
3758 | ||
ed30da8e RH |
3759 | static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3760 | uint64_t value) | |
3761 | { | |
d06dc933 RH |
3762 | /* |
3763 | * If we are running with E2&0 regime, then an ASID is active. | |
3764 | * Flush if that might be changing. Note we're not checking | |
3765 | * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that | |
3766 | * holds the active ASID, only checking the field that might. | |
3767 | */ | |
3768 | if (extract64(raw_read(env, ri) ^ value, 48, 16) && | |
3769 | (arm_hcr_el2_eff(env) & HCR_E2H)) { | |
b6ad6062 RDC |
3770 | uint16_t mask = ARMMMUIdxBit_E20_2 | |
3771 | ARMMMUIdxBit_E20_2_PAN | | |
3772 | ARMMMUIdxBit_E20_0; | |
3773 | ||
3774 | if (arm_is_secure_below_el3(env)) { | |
3775 | mask >>= ARM_MMU_IDX_A_NS; | |
3776 | } | |
3777 | ||
3778 | tlb_flush_by_mmuidx(env_cpu(env), mask); | |
d06dc933 | 3779 | } |
ed30da8e RH |
3780 | raw_write(env, ri, value); |
3781 | } | |
3782 | ||
b698e9cf EI |
3783 | static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3784 | uint64_t value) | |
3785 | { | |
2fc0cc0e | 3786 | ARMCPU *cpu = env_archcpu(env); |
b698e9cf EI |
3787 | CPUState *cs = CPU(cpu); |
3788 | ||
97fa9350 RH |
3789 | /* |
3790 | * A change in VMID to the stage2 page table (Stage2) invalidates | |
3791 | * the combined stage 1&2 tlbs (EL10_1 and EL10_0). | |
3792 | */ | |
b698e9cf | 3793 | if (raw_read(env, ri) != value) { |
c4f060e8 RDC |
3794 | uint16_t mask = ARMMMUIdxBit_E10_1 | |
3795 | ARMMMUIdxBit_E10_1_PAN | | |
3796 | ARMMMUIdxBit_E10_0; | |
3797 | ||
3798 | if (arm_is_secure_below_el3(env)) { | |
3799 | mask >>= ARM_MMU_IDX_A_NS; | |
3800 | } | |
3801 | ||
3802 | tlb_flush_by_mmuidx(cs, mask); | |
b698e9cf EI |
3803 | raw_write(env, ri, value); |
3804 | } | |
3805 | } | |
3806 | ||
8e5d75c9 | 3807 | static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { |
18032bec | 3808 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, |
84929218 | 3809 | .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS, |
4a7e2d73 | 3810 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), |
b061a82b | 3811 | offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, |
18032bec | 3812 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, |
84929218 | 3813 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
88ca1c2d FA |
3814 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), |
3815 | offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, | |
8e5d75c9 | 3816 | { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, |
84929218 | 3817 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
8e5d75c9 PC |
3818 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), |
3819 | offsetof(CPUARMState, cp15.dfar_ns) } }, | |
3820 | { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, | |
3821 | .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, | |
84929218 RH |
3822 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3823 | .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), | |
8e5d75c9 PC |
3824 | .resetvalue = 0, }, |
3825 | REGINFO_SENTINEL | |
3826 | }; | |
3827 | ||
3828 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { | |
6cd8a264 RH |
3829 | { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, |
3830 | .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, | |
84929218 | 3831 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
d81c519c | 3832 | .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, |
327ed10f | 3833 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af | 3834 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, |
84929218 RH |
3835 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3836 | .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
7dd8c9af FA |
3837 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
3838 | offsetof(CPUARMState, cp15.ttbr0_ns) } }, | |
327ed10f | 3839 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af | 3840 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, |
84929218 RH |
3841 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3842 | .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
7dd8c9af FA |
3843 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
3844 | offsetof(CPUARMState, cp15.ttbr1_ns) } }, | |
cb2e37df PM |
3845 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, |
3846 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | |
84929218 RH |
3847 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3848 | .writefn = vmsa_tcr_el12_write, | |
cb2e37df | 3849 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, |
11f136ee | 3850 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, |
cb2e37df | 3851 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
84929218 RH |
3852 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3853 | .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, | |
b061a82b | 3854 | .raw_writefn = vmsa_ttbcr_raw_write, |
d102058e RH |
3855 | /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */ |
3856 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]), | |
3857 | offsetof(CPUARMState, cp15.tcr_el[1])} }, | |
18032bec PM |
3858 | REGINFO_SENTINEL |
3859 | }; | |
3860 | ||
ab638a32 RH |
3861 | /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing |
3862 | * qemu tlbs nor adjusting cached masks. | |
3863 | */ | |
3864 | static const ARMCPRegInfo ttbcr2_reginfo = { | |
3865 | .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3, | |
84929218 RH |
3866 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3867 | .type = ARM_CP_ALIAS, | |
d102058e RH |
3868 | .bank_fieldoffsets = { |
3869 | offsetofhigh32(CPUARMState, cp15.tcr_el[3].raw_tcr), | |
3870 | offsetofhigh32(CPUARMState, cp15.tcr_el[1].raw_tcr), | |
3871 | }, | |
ab638a32 RH |
3872 | }; |
3873 | ||
c4241c7d PM |
3874 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3875 | uint64_t value) | |
1047b9d7 PM |
3876 | { |
3877 | env->cp15.c15_ticonfig = value & 0xe7; | |
3878 | /* The OS_TYPE bit in this register changes the reported CPUID! */ | |
3879 | env->cp15.c0_cpuid = (value & (1 << 5)) ? | |
3880 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1047b9d7 PM |
3881 | } |
3882 | ||
c4241c7d PM |
3883 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3884 | uint64_t value) | |
1047b9d7 PM |
3885 | { |
3886 | env->cp15.c15_threadid = value & 0xffff; | |
1047b9d7 PM |
3887 | } |
3888 | ||
c4241c7d PM |
3889 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3890 | uint64_t value) | |
1047b9d7 PM |
3891 | { |
3892 | /* Wait-for-interrupt (deprecated) */ | |
2fc0cc0e | 3893 | cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); |
1047b9d7 PM |
3894 | } |
3895 | ||
c4241c7d PM |
3896 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3897 | uint64_t value) | |
c4804214 PM |
3898 | { |
3899 | /* On OMAP there are registers indicating the max/min index of dcache lines | |
3900 | * containing a dirty line; cache flush operations have to reset these. | |
3901 | */ | |
3902 | env->cp15.c15_i_max = 0x000; | |
3903 | env->cp15.c15_i_min = 0xff0; | |
c4804214 PM |
3904 | } |
3905 | ||
18032bec PM |
3906 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
3907 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, | |
3908 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, | |
d81c519c | 3909 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 3910 | .resetvalue = 0, }, |
1047b9d7 PM |
3911 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
3912 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
3913 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
3914 | .access = PL1_RW, | |
3915 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, | |
3916 | .writefn = omap_ticonfig_write }, | |
3917 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, | |
3918 | .access = PL1_RW, | |
3919 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, | |
3920 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, | |
3921 | .access = PL1_RW, .resetvalue = 0xff0, | |
3922 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, | |
3923 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, | |
3924 | .access = PL1_RW, | |
3925 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, | |
3926 | .writefn = omap_threadid_write }, | |
3927 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, | |
3928 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
7a0e58fa | 3929 | .type = ARM_CP_NO_RAW, |
1047b9d7 PM |
3930 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
3931 | /* TODO: Peripheral port remap register: | |
3932 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller | |
3933 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), | |
3934 | * when MMU is off. | |
3935 | */ | |
c4804214 | 3936 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
d4e6df63 | 3937 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
7a0e58fa | 3938 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, |
c4804214 | 3939 | .writefn = omap_cachemaint_write }, |
34f90529 PM |
3940 | { .name = "C9", .cp = 15, .crn = 9, |
3941 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | |
3942 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | |
1047b9d7 PM |
3943 | REGINFO_SENTINEL |
3944 | }; | |
3945 | ||
c4241c7d PM |
3946 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3947 | uint64_t value) | |
1047b9d7 | 3948 | { |
c0f4af17 | 3949 | env->cp15.c15_cpar = value & 0x3fff; |
1047b9d7 PM |
3950 | } |
3951 | ||
3952 | static const ARMCPRegInfo xscale_cp_reginfo[] = { | |
3953 | { .name = "XSCALE_CPAR", | |
3954 | .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
3955 | .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, | |
3956 | .writefn = xscale_cpar_write, }, | |
2771db27 PM |
3957 | { .name = "XSCALE_AUXCR", |
3958 | .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, | |
3959 | .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), | |
3960 | .resetvalue = 0, }, | |
3b771579 PM |
3961 | /* XScale specific cache-lockdown: since we have no cache we NOP these |
3962 | * and hope the guest does not really rely on cache behaviour. | |
3963 | */ | |
3964 | { .name = "XSCALE_LOCK_ICACHE_LINE", | |
3965 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
3966 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3967 | { .name = "XSCALE_UNLOCK_ICACHE", | |
3968 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
3969 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3970 | { .name = "XSCALE_DCACHE_LOCK", | |
3971 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, | |
3972 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
3973 | { .name = "XSCALE_UNLOCK_DCACHE", | |
3974 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, | |
3975 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1047b9d7 PM |
3976 | REGINFO_SENTINEL |
3977 | }; | |
3978 | ||
3979 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | |
3980 | /* RAZ/WI the whole crn=15 space, when we don't have a more specific | |
3981 | * implementation of this implementation-defined space. | |
3982 | * Ideally this should eventually disappear in favour of actually | |
3983 | * implementing the correct behaviour for all cores. | |
3984 | */ | |
3985 | { .name = "C15_IMPDEF", .cp = 15, .crn = 15, | |
3986 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
3671cd87 | 3987 | .access = PL1_RW, |
7a0e58fa | 3988 | .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, |
d4e6df63 | 3989 | .resetvalue = 0 }, |
18032bec PM |
3990 | REGINFO_SENTINEL |
3991 | }; | |
3992 | ||
c4804214 PM |
3993 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
3994 | /* Cache status: RAZ because we have no cache so it's always clean */ | |
3995 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | |
7a0e58fa | 3996 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 3997 | .resetvalue = 0 }, |
c4804214 PM |
3998 | REGINFO_SENTINEL |
3999 | }; | |
4000 | ||
4001 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | |
4002 | /* We never have a a block transfer operation in progress */ | |
4003 | { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, | |
7a0e58fa | 4004 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4005 | .resetvalue = 0 }, |
30b05bba PM |
4006 | /* The cache ops themselves: these all NOP for QEMU */ |
4007 | { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, | |
4008 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
4009 | { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, | |
4010 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
4011 | { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, | |
4012 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
4013 | { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, | |
4014 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
4015 | { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, | |
4016 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
4017 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, | |
4018 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
c4804214 PM |
4019 | REGINFO_SENTINEL |
4020 | }; | |
4021 | ||
4022 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | |
4023 | /* The cache test-and-clean instructions always return (1 << 30) | |
4024 | * to indicate that there are no dirty cache lines. | |
4025 | */ | |
4026 | { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, | |
7a0e58fa | 4027 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4028 | .resetvalue = (1 << 30) }, |
c4804214 | 4029 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
7a0e58fa | 4030 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4031 | .resetvalue = (1 << 30) }, |
c4804214 PM |
4032 | REGINFO_SENTINEL |
4033 | }; | |
4034 | ||
34f90529 PM |
4035 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
4036 | /* Ignore ReadBuffer accesses */ | |
4037 | { .name = "C9_READBUFFER", .cp = 15, .crn = 9, | |
4038 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
d4e6df63 | 4039 | .access = PL1_RW, .resetvalue = 0, |
7a0e58fa | 4040 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, |
34f90529 PM |
4041 | REGINFO_SENTINEL |
4042 | }; | |
4043 | ||
731de9e6 EI |
4044 | static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4045 | { | |
731de9e6 | 4046 | unsigned int cur_el = arm_current_el(env); |
731de9e6 | 4047 | |
e6ef0169 | 4048 | if (arm_is_el2_enabled(env) && cur_el == 1) { |
731de9e6 EI |
4049 | return env->cp15.vpidr_el2; |
4050 | } | |
4051 | return raw_read(env, ri); | |
4052 | } | |
4053 | ||
06a7e647 | 4054 | static uint64_t mpidr_read_val(CPUARMState *env) |
81bdde9d | 4055 | { |
2fc0cc0e | 4056 | ARMCPU *cpu = env_archcpu(env); |
eb5e1d3c PF |
4057 | uint64_t mpidr = cpu->mp_affinity; |
4058 | ||
81bdde9d | 4059 | if (arm_feature(env, ARM_FEATURE_V7MP)) { |
78dbbbe4 | 4060 | mpidr |= (1U << 31); |
81bdde9d PM |
4061 | /* Cores which are uniprocessor (non-coherent) |
4062 | * but still implement the MP extensions set | |
a8e81b31 | 4063 | * bit 30. (For instance, Cortex-R5). |
81bdde9d | 4064 | */ |
a8e81b31 PC |
4065 | if (cpu->mp_is_up) { |
4066 | mpidr |= (1u << 30); | |
4067 | } | |
81bdde9d | 4068 | } |
c4241c7d | 4069 | return mpidr; |
81bdde9d PM |
4070 | } |
4071 | ||
06a7e647 EI |
4072 | static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4073 | { | |
f0d574d6 | 4074 | unsigned int cur_el = arm_current_el(env); |
f0d574d6 | 4075 | |
e6ef0169 | 4076 | if (arm_is_el2_enabled(env) && cur_el == 1) { |
f0d574d6 EI |
4077 | return env->cp15.vmpidr_el2; |
4078 | } | |
06a7e647 EI |
4079 | return mpidr_read_val(env); |
4080 | } | |
4081 | ||
7ac681cf | 4082 | static const ARMCPRegInfo lpae_cp_reginfo[] = { |
a903c449 | 4083 | /* NOP AMAIR0/1 */ |
b0fe2427 PM |
4084 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, |
4085 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | |
84929218 RH |
4086 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4087 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b0fe2427 | 4088 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ |
7ac681cf | 4089 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
84929218 RH |
4090 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4091 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
891a2fe7 | 4092 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
01c097f7 FA |
4093 | .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, |
4094 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), | |
4095 | offsetof(CPUARMState, cp15.par_ns)} }, | |
891a2fe7 | 4096 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, |
84929218 RH |
4097 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4098 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
7dd8c9af FA |
4099 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
4100 | offsetof(CPUARMState, cp15.ttbr0_ns) }, | |
b061a82b | 4101 | .writefn = vmsa_ttbr_write, }, |
891a2fe7 | 4102 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
84929218 RH |
4103 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4104 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
7dd8c9af FA |
4105 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
4106 | offsetof(CPUARMState, cp15.ttbr1_ns) }, | |
b061a82b | 4107 | .writefn = vmsa_ttbr_write, }, |
7ac681cf PM |
4108 | REGINFO_SENTINEL |
4109 | }; | |
4110 | ||
c4241c7d | 4111 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 4112 | { |
c4241c7d | 4113 | return vfp_get_fpcr(env); |
b0d2b7d0 PM |
4114 | } |
4115 | ||
c4241c7d PM |
4116 | static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4117 | uint64_t value) | |
b0d2b7d0 PM |
4118 | { |
4119 | vfp_set_fpcr(env, value); | |
b0d2b7d0 PM |
4120 | } |
4121 | ||
c4241c7d | 4122 | static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 4123 | { |
c4241c7d | 4124 | return vfp_get_fpsr(env); |
b0d2b7d0 PM |
4125 | } |
4126 | ||
c4241c7d PM |
4127 | static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4128 | uint64_t value) | |
b0d2b7d0 PM |
4129 | { |
4130 | vfp_set_fpsr(env, value); | |
b0d2b7d0 PM |
4131 | } |
4132 | ||
3f208fd7 PM |
4133 | static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4134 | bool isread) | |
c2b820fe | 4135 | { |
aaec1432 | 4136 | if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { |
c2b820fe PM |
4137 | return CP_ACCESS_TRAP; |
4138 | } | |
4139 | return CP_ACCESS_OK; | |
4140 | } | |
4141 | ||
4142 | static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4143 | uint64_t value) | |
4144 | { | |
4145 | env->daif = value & PSTATE_DAIF; | |
4146 | } | |
4147 | ||
220f508f RH |
4148 | static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4149 | { | |
4150 | return env->pstate & PSTATE_PAN; | |
4151 | } | |
4152 | ||
4153 | static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4154 | uint64_t value) | |
4155 | { | |
4156 | env->pstate = (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN); | |
4157 | } | |
4158 | ||
4159 | static const ARMCPRegInfo pan_reginfo = { | |
4160 | .name = "PAN", .state = ARM_CP_STATE_AA64, | |
4161 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 3, | |
4162 | .type = ARM_CP_NO_RAW, .access = PL1_RW, | |
4163 | .readfn = aa64_pan_read, .writefn = aa64_pan_write | |
4164 | }; | |
4165 | ||
9eeb7a1c RH |
4166 | static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4167 | { | |
4168 | return env->pstate & PSTATE_UAO; | |
4169 | } | |
4170 | ||
4171 | static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4172 | uint64_t value) | |
4173 | { | |
4174 | env->pstate = (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO); | |
4175 | } | |
4176 | ||
4177 | static const ARMCPRegInfo uao_reginfo = { | |
4178 | .name = "UAO", .state = ARM_CP_STATE_AA64, | |
4179 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4, | |
4180 | .type = ARM_CP_NO_RAW, .access = PL1_RW, | |
4181 | .readfn = aa64_uao_read, .writefn = aa64_uao_write | |
4182 | }; | |
4183 | ||
dc8b1853 RC |
4184 | static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4185 | { | |
4186 | return env->pstate & PSTATE_DIT; | |
4187 | } | |
4188 | ||
4189 | static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4190 | uint64_t value) | |
4191 | { | |
4192 | env->pstate = (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT); | |
4193 | } | |
4194 | ||
4195 | static const ARMCPRegInfo dit_reginfo = { | |
4196 | .name = "DIT", .state = ARM_CP_STATE_AA64, | |
4197 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 5, | |
4198 | .type = ARM_CP_NO_RAW, .access = PL0_RW, | |
4199 | .readfn = aa64_dit_read, .writefn = aa64_dit_write | |
4200 | }; | |
4201 | ||
f2f68a78 RC |
4202 | static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4203 | { | |
4204 | return env->pstate & PSTATE_SSBS; | |
4205 | } | |
4206 | ||
4207 | static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4208 | uint64_t value) | |
4209 | { | |
4210 | env->pstate = (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS); | |
4211 | } | |
4212 | ||
4213 | static const ARMCPRegInfo ssbs_reginfo = { | |
4214 | .name = "SSBS", .state = ARM_CP_STATE_AA64, | |
4215 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 6, | |
4216 | .type = ARM_CP_NO_RAW, .access = PL0_RW, | |
4217 | .readfn = aa64_ssbs_read, .writefn = aa64_ssbs_write | |
4218 | }; | |
4219 | ||
38262d8a RH |
4220 | static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, |
4221 | const ARMCPRegInfo *ri, | |
4222 | bool isread) | |
8af35c37 | 4223 | { |
38262d8a RH |
4224 | /* Cache invalidate/clean to Point of Coherency or Persistence... */ |
4225 | switch (arm_current_el(env)) { | |
4226 | case 0: | |
4227 | /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ | |
4228 | if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { | |
4229 | return CP_ACCESS_TRAP; | |
4230 | } | |
4231 | /* fall through */ | |
4232 | case 1: | |
4233 | /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */ | |
4234 | if (arm_hcr_el2_eff(env) & HCR_TPCP) { | |
4235 | return CP_ACCESS_TRAP_EL2; | |
4236 | } | |
4237 | break; | |
8af35c37 PM |
4238 | } |
4239 | return CP_ACCESS_OK; | |
4240 | } | |
4241 | ||
38262d8a | 4242 | static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, |
1bed4d2e RH |
4243 | const ARMCPRegInfo *ri, |
4244 | bool isread) | |
4245 | { | |
38262d8a | 4246 | /* Cache invalidate/clean to Point of Unification... */ |
1bed4d2e RH |
4247 | switch (arm_current_el(env)) { |
4248 | case 0: | |
4249 | /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ | |
4250 | if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { | |
4251 | return CP_ACCESS_TRAP; | |
4252 | } | |
4253 | /* fall through */ | |
4254 | case 1: | |
38262d8a RH |
4255 | /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */ |
4256 | if (arm_hcr_el2_eff(env) & HCR_TPU) { | |
1bed4d2e RH |
4257 | return CP_ACCESS_TRAP_EL2; |
4258 | } | |
4259 | break; | |
4260 | } | |
4261 | return CP_ACCESS_OK; | |
4262 | } | |
4263 | ||
dbb1fb27 AB |
4264 | /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions |
4265 | * Page D4-1736 (DDI0487A.b) | |
4266 | */ | |
4267 | ||
b7e0730d RH |
4268 | static int vae1_tlbmask(CPUARMState *env) |
4269 | { | |
e04a5752 | 4270 | uint64_t hcr = arm_hcr_el2_eff(env); |
bc944d3a | 4271 | uint16_t mask; |
e04a5752 RDC |
4272 | |
4273 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
bc944d3a RDC |
4274 | mask = ARMMMUIdxBit_E20_2 | |
4275 | ARMMMUIdxBit_E20_2_PAN | | |
4276 | ARMMMUIdxBit_E20_0; | |
b7e0730d | 4277 | } else { |
bc944d3a | 4278 | mask = ARMMMUIdxBit_E10_1 | |
452ef8cb RH |
4279 | ARMMMUIdxBit_E10_1_PAN | |
4280 | ARMMMUIdxBit_E10_0; | |
b7e0730d | 4281 | } |
bc944d3a RDC |
4282 | |
4283 | if (arm_is_secure_below_el3(env)) { | |
4284 | mask >>= ARM_MMU_IDX_A_NS; | |
4285 | } | |
4286 | ||
4287 | return mask; | |
b7e0730d RH |
4288 | } |
4289 | ||
ea04dce7 RH |
4290 | /* Return 56 if TBI is enabled, 64 otherwise. */ |
4291 | static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, | |
4292 | uint64_t addr) | |
4293 | { | |
4294 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | |
4295 | int tbi = aa64_va_parameter_tbi(tcr, mmu_idx); | |
4296 | int select = extract64(addr, 55, 1); | |
4297 | ||
4298 | return (tbi >> select) & 1 ? 56 : 64; | |
4299 | } | |
4300 | ||
4301 | static int vae1_tlbbits(CPUARMState *env, uint64_t addr) | |
4302 | { | |
b6ad6062 | 4303 | uint64_t hcr = arm_hcr_el2_eff(env); |
ea04dce7 RH |
4304 | ARMMMUIdx mmu_idx; |
4305 | ||
4306 | /* Only the regime of the mmu_idx below is significant. */ | |
b6ad6062 | 4307 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { |
ea04dce7 RH |
4308 | mmu_idx = ARMMMUIdx_E20_0; |
4309 | } else { | |
4310 | mmu_idx = ARMMMUIdx_E10_0; | |
4311 | } | |
b6ad6062 RDC |
4312 | |
4313 | if (arm_is_secure_below_el3(env)) { | |
4314 | mmu_idx &= ~ARM_MMU_IDX_A_NS; | |
4315 | } | |
4316 | ||
ea04dce7 RH |
4317 | return tlbbits_for_regime(env, mmu_idx, addr); |
4318 | } | |
4319 | ||
fd3ed969 PM |
4320 | static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4321 | uint64_t value) | |
168aa23b | 4322 | { |
29a0af61 | 4323 | CPUState *cs = env_cpu(env); |
b7e0730d | 4324 | int mask = vae1_tlbmask(env); |
dbb1fb27 | 4325 | |
b7e0730d | 4326 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
168aa23b PM |
4327 | } |
4328 | ||
b4ab8ce9 PM |
4329 | static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4330 | uint64_t value) | |
4331 | { | |
29a0af61 | 4332 | CPUState *cs = env_cpu(env); |
b7e0730d | 4333 | int mask = vae1_tlbmask(env); |
b4ab8ce9 PM |
4334 | |
4335 | if (tlb_force_broadcast(env)) { | |
527db2be RH |
4336 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
4337 | } else { | |
4338 | tlb_flush_by_mmuidx(cs, mask); | |
b4ab8ce9 | 4339 | } |
b4ab8ce9 PM |
4340 | } |
4341 | ||
90c19cdf | 4342 | static int alle1_tlbmask(CPUARMState *env) |
168aa23b | 4343 | { |
90c19cdf RH |
4344 | /* |
4345 | * Note that the 'ALL' scope must invalidate both stage 1 and | |
fd3ed969 PM |
4346 | * stage 2 translations, whereas most other scopes only invalidate |
4347 | * stage 1 translations. | |
4348 | */ | |
fd3ed969 | 4349 | if (arm_is_secure_below_el3(env)) { |
452ef8cb RH |
4350 | return ARMMMUIdxBit_SE10_1 | |
4351 | ARMMMUIdxBit_SE10_1_PAN | | |
4352 | ARMMMUIdxBit_SE10_0; | |
fd3ed969 | 4353 | } else { |
452ef8cb RH |
4354 | return ARMMMUIdxBit_E10_1 | |
4355 | ARMMMUIdxBit_E10_1_PAN | | |
4356 | ARMMMUIdxBit_E10_0; | |
fd3ed969 | 4357 | } |
168aa23b PM |
4358 | } |
4359 | ||
85d0dc9f RH |
4360 | static int e2_tlbmask(CPUARMState *env) |
4361 | { | |
b6ad6062 RDC |
4362 | if (arm_is_secure_below_el3(env)) { |
4363 | return ARMMMUIdxBit_SE20_0 | | |
4364 | ARMMMUIdxBit_SE20_2 | | |
4365 | ARMMMUIdxBit_SE20_2_PAN | | |
4366 | ARMMMUIdxBit_SE2; | |
4367 | } else { | |
4368 | return ARMMMUIdxBit_E20_0 | | |
4369 | ARMMMUIdxBit_E20_2 | | |
4370 | ARMMMUIdxBit_E20_2_PAN | | |
4371 | ARMMMUIdxBit_E2; | |
4372 | } | |
85d0dc9f RH |
4373 | } |
4374 | ||
90c19cdf RH |
4375 | static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4376 | uint64_t value) | |
4377 | { | |
4378 | CPUState *cs = env_cpu(env); | |
4379 | int mask = alle1_tlbmask(env); | |
4380 | ||
4381 | tlb_flush_by_mmuidx(cs, mask); | |
4382 | } | |
4383 | ||
fd3ed969 | 4384 | static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
fa439fc5 PM |
4385 | uint64_t value) |
4386 | { | |
85d0dc9f RH |
4387 | CPUState *cs = env_cpu(env); |
4388 | int mask = e2_tlbmask(env); | |
fd3ed969 | 4389 | |
85d0dc9f | 4390 | tlb_flush_by_mmuidx(cs, mask); |
fd3ed969 PM |
4391 | } |
4392 | ||
43efaa33 PM |
4393 | static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4394 | uint64_t value) | |
4395 | { | |
2fc0cc0e | 4396 | ARMCPU *cpu = env_archcpu(env); |
43efaa33 PM |
4397 | CPUState *cs = CPU(cpu); |
4398 | ||
127b2b08 | 4399 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3); |
43efaa33 PM |
4400 | } |
4401 | ||
fd3ed969 PM |
4402 | static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4403 | uint64_t value) | |
4404 | { | |
29a0af61 | 4405 | CPUState *cs = env_cpu(env); |
90c19cdf RH |
4406 | int mask = alle1_tlbmask(env); |
4407 | ||
4408 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); | |
fa439fc5 PM |
4409 | } |
4410 | ||
2bfb9d75 PM |
4411 | static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4412 | uint64_t value) | |
4413 | { | |
29a0af61 | 4414 | CPUState *cs = env_cpu(env); |
85d0dc9f | 4415 | int mask = e2_tlbmask(env); |
2bfb9d75 | 4416 | |
85d0dc9f | 4417 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
2bfb9d75 PM |
4418 | } |
4419 | ||
43efaa33 PM |
4420 | static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4421 | uint64_t value) | |
4422 | { | |
29a0af61 | 4423 | CPUState *cs = env_cpu(env); |
43efaa33 | 4424 | |
127b2b08 | 4425 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3); |
43efaa33 PM |
4426 | } |
4427 | ||
fd3ed969 PM |
4428 | static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4429 | uint64_t value) | |
fa439fc5 | 4430 | { |
fd3ed969 PM |
4431 | /* Invalidate by VA, EL2 |
4432 | * Currently handles both VAE2 and VALE2, since we don't support | |
4433 | * flush-last-level-only. | |
4434 | */ | |
85d0dc9f RH |
4435 | CPUState *cs = env_cpu(env); |
4436 | int mask = e2_tlbmask(env); | |
fd3ed969 PM |
4437 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
4438 | ||
85d0dc9f | 4439 | tlb_flush_page_by_mmuidx(cs, pageaddr, mask); |
fd3ed969 PM |
4440 | } |
4441 | ||
43efaa33 PM |
4442 | static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4443 | uint64_t value) | |
4444 | { | |
4445 | /* Invalidate by VA, EL3 | |
4446 | * Currently handles both VAE3 and VALE3, since we don't support | |
4447 | * flush-last-level-only. | |
4448 | */ | |
2fc0cc0e | 4449 | ARMCPU *cpu = env_archcpu(env); |
43efaa33 PM |
4450 | CPUState *cs = CPU(cpu); |
4451 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
4452 | ||
127b2b08 | 4453 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3); |
43efaa33 PM |
4454 | } |
4455 | ||
fd3ed969 PM |
4456 | static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4457 | uint64_t value) | |
4458 | { | |
90c19cdf RH |
4459 | CPUState *cs = env_cpu(env); |
4460 | int mask = vae1_tlbmask(env); | |
fa439fc5 | 4461 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ea04dce7 | 4462 | int bits = vae1_tlbbits(env, pageaddr); |
fa439fc5 | 4463 | |
ea04dce7 | 4464 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); |
fa439fc5 PM |
4465 | } |
4466 | ||
b4ab8ce9 PM |
4467 | static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4468 | uint64_t value) | |
4469 | { | |
4470 | /* Invalidate by VA, EL1&0 (AArch64 version). | |
4471 | * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, | |
4472 | * since we don't support flush-for-specific-ASID-only or | |
4473 | * flush-last-level-only. | |
4474 | */ | |
90c19cdf RH |
4475 | CPUState *cs = env_cpu(env); |
4476 | int mask = vae1_tlbmask(env); | |
b4ab8ce9 | 4477 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ea04dce7 | 4478 | int bits = vae1_tlbbits(env, pageaddr); |
b4ab8ce9 PM |
4479 | |
4480 | if (tlb_force_broadcast(env)) { | |
ea04dce7 | 4481 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); |
527db2be | 4482 | } else { |
ea04dce7 | 4483 | tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits); |
b4ab8ce9 | 4484 | } |
b4ab8ce9 PM |
4485 | } |
4486 | ||
fd3ed969 PM |
4487 | static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4488 | uint64_t value) | |
fa439fc5 | 4489 | { |
29a0af61 | 4490 | CPUState *cs = env_cpu(env); |
fd3ed969 | 4491 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
b6ad6062 RDC |
4492 | bool secure = arm_is_secure_below_el3(env); |
4493 | int mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; | |
eb849d8f | 4494 | int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2, |
b6ad6062 | 4495 | pageaddr); |
fa439fc5 | 4496 | |
b6ad6062 | 4497 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); |
fa439fc5 PM |
4498 | } |
4499 | ||
43efaa33 PM |
4500 | static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4501 | uint64_t value) | |
4502 | { | |
29a0af61 | 4503 | CPUState *cs = env_cpu(env); |
43efaa33 | 4504 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ea04dce7 | 4505 | int bits = tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr); |
43efaa33 | 4506 | |
ea04dce7 RH |
4507 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, |
4508 | ARMMMUIdxBit_SE3, bits); | |
43efaa33 PM |
4509 | } |
4510 | ||
84940ed8 RC |
4511 | #ifdef TARGET_AARCH64 |
4512 | static uint64_t tlbi_aa64_range_get_length(CPUARMState *env, | |
4513 | uint64_t value) | |
4514 | { | |
4515 | unsigned int page_shift; | |
4516 | unsigned int page_size_granule; | |
4517 | uint64_t num; | |
4518 | uint64_t scale; | |
4519 | uint64_t exponent; | |
4520 | uint64_t length; | |
4521 | ||
52a9f609 | 4522 | num = extract64(value, 39, 5); |
84940ed8 RC |
4523 | scale = extract64(value, 44, 2); |
4524 | page_size_granule = extract64(value, 46, 2); | |
4525 | ||
84940ed8 RC |
4526 | if (page_size_granule == 0) { |
4527 | qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", | |
4528 | page_size_granule); | |
4529 | return 0; | |
4530 | } | |
4531 | ||
52a9f609 PM |
4532 | page_shift = (page_size_granule - 1) * 2 + 12; |
4533 | ||
84940ed8 RC |
4534 | exponent = (5 * scale) + 1; |
4535 | length = (num + 1) << (exponent + page_shift); | |
4536 | ||
4537 | return length; | |
4538 | } | |
4539 | ||
4540 | static uint64_t tlbi_aa64_range_get_base(CPUARMState *env, uint64_t value, | |
4541 | bool two_ranges) | |
4542 | { | |
4543 | /* TODO: ARMv8.7 FEAT_LPA2 */ | |
4544 | uint64_t pageaddr; | |
4545 | ||
4546 | if (two_ranges) { | |
4547 | pageaddr = sextract64(value, 0, 37) << TARGET_PAGE_BITS; | |
4548 | } else { | |
4549 | pageaddr = extract64(value, 0, 37) << TARGET_PAGE_BITS; | |
4550 | } | |
4551 | ||
4552 | return pageaddr; | |
4553 | } | |
4554 | ||
4555 | static void do_rvae_write(CPUARMState *env, uint64_t value, | |
4556 | int idxmap, bool synced) | |
4557 | { | |
4558 | ARMMMUIdx one_idx = ARM_MMU_IDX_A | ctz32(idxmap); | |
4559 | bool two_ranges = regime_has_2_ranges(one_idx); | |
4560 | uint64_t baseaddr, length; | |
4561 | int bits; | |
4562 | ||
4563 | baseaddr = tlbi_aa64_range_get_base(env, value, two_ranges); | |
4564 | length = tlbi_aa64_range_get_length(env, value); | |
4565 | bits = tlbbits_for_regime(env, one_idx, baseaddr); | |
4566 | ||
4567 | if (synced) { | |
4568 | tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env), | |
4569 | baseaddr, | |
4570 | length, | |
4571 | idxmap, | |
4572 | bits); | |
4573 | } else { | |
4574 | tlb_flush_range_by_mmuidx(env_cpu(env), baseaddr, | |
4575 | length, idxmap, bits); | |
4576 | } | |
4577 | } | |
4578 | ||
4579 | static void tlbi_aa64_rvae1_write(CPUARMState *env, | |
4580 | const ARMCPRegInfo *ri, | |
4581 | uint64_t value) | |
4582 | { | |
4583 | /* | |
4584 | * Invalidate by VA range, EL1&0. | |
4585 | * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1, | |
4586 | * since we don't support flush-for-specific-ASID-only or | |
4587 | * flush-last-level-only. | |
4588 | */ | |
4589 | ||
4590 | do_rvae_write(env, value, vae1_tlbmask(env), | |
4591 | tlb_force_broadcast(env)); | |
4592 | } | |
4593 | ||
4594 | static void tlbi_aa64_rvae1is_write(CPUARMState *env, | |
4595 | const ARMCPRegInfo *ri, | |
4596 | uint64_t value) | |
4597 | { | |
4598 | /* | |
4599 | * Invalidate by VA range, Inner/Outer Shareable EL1&0. | |
4600 | * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS, | |
4601 | * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support | |
4602 | * flush-for-specific-ASID-only, flush-last-level-only or inner/outer | |
4603 | * shareable specific flushes. | |
4604 | */ | |
4605 | ||
4606 | do_rvae_write(env, value, vae1_tlbmask(env), true); | |
4607 | } | |
4608 | ||
4609 | static int vae2_tlbmask(CPUARMState *env) | |
4610 | { | |
4611 | return (arm_is_secure_below_el3(env) | |
4612 | ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2); | |
4613 | } | |
4614 | ||
4615 | static void tlbi_aa64_rvae2_write(CPUARMState *env, | |
4616 | const ARMCPRegInfo *ri, | |
4617 | uint64_t value) | |
4618 | { | |
4619 | /* | |
4620 | * Invalidate by VA range, EL2. | |
4621 | * Currently handles all of RVAE2 and RVALE2, | |
4622 | * since we don't support flush-for-specific-ASID-only or | |
4623 | * flush-last-level-only. | |
4624 | */ | |
4625 | ||
4626 | do_rvae_write(env, value, vae2_tlbmask(env), | |
4627 | tlb_force_broadcast(env)); | |
4628 | ||
4629 | ||
4630 | } | |
4631 | ||
4632 | static void tlbi_aa64_rvae2is_write(CPUARMState *env, | |
4633 | const ARMCPRegInfo *ri, | |
4634 | uint64_t value) | |
4635 | { | |
4636 | /* | |
4637 | * Invalidate by VA range, Inner/Outer Shareable, EL2. | |
4638 | * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS, | |
4639 | * since we don't support flush-for-specific-ASID-only, | |
4640 | * flush-last-level-only or inner/outer shareable specific flushes. | |
4641 | */ | |
4642 | ||
4643 | do_rvae_write(env, value, vae2_tlbmask(env), true); | |
4644 | ||
4645 | } | |
4646 | ||
4647 | static void tlbi_aa64_rvae3_write(CPUARMState *env, | |
4648 | const ARMCPRegInfo *ri, | |
4649 | uint64_t value) | |
4650 | { | |
4651 | /* | |
4652 | * Invalidate by VA range, EL3. | |
4653 | * Currently handles all of RVAE3 and RVALE3, | |
4654 | * since we don't support flush-for-specific-ASID-only or | |
4655 | * flush-last-level-only. | |
4656 | */ | |
4657 | ||
4658 | do_rvae_write(env, value, ARMMMUIdxBit_SE3, | |
4659 | tlb_force_broadcast(env)); | |
4660 | } | |
4661 | ||
4662 | static void tlbi_aa64_rvae3is_write(CPUARMState *env, | |
4663 | const ARMCPRegInfo *ri, | |
4664 | uint64_t value) | |
4665 | { | |
4666 | /* | |
4667 | * Invalidate by VA range, EL3, Inner/Outer Shareable. | |
4668 | * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS, | |
4669 | * since we don't support flush-for-specific-ASID-only, | |
4670 | * flush-last-level-only or inner/outer specific flushes. | |
4671 | */ | |
4672 | ||
4673 | do_rvae_write(env, value, ARMMMUIdxBit_SE3, true); | |
4674 | } | |
4675 | #endif | |
4676 | ||
3f208fd7 PM |
4677 | static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4678 | bool isread) | |
aca3f40b | 4679 | { |
4351cb72 RH |
4680 | int cur_el = arm_current_el(env); |
4681 | ||
4682 | if (cur_el < 2) { | |
4683 | uint64_t hcr = arm_hcr_el2_eff(env); | |
4684 | ||
4685 | if (cur_el == 0) { | |
4686 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
4687 | if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) { | |
4688 | return CP_ACCESS_TRAP_EL2; | |
4689 | } | |
4690 | } else { | |
4691 | if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) { | |
4692 | return CP_ACCESS_TRAP; | |
4693 | } | |
4694 | if (hcr & HCR_TDZ) { | |
4695 | return CP_ACCESS_TRAP_EL2; | |
4696 | } | |
4697 | } | |
4698 | } else if (hcr & HCR_TDZ) { | |
4699 | return CP_ACCESS_TRAP_EL2; | |
4700 | } | |
aca3f40b PM |
4701 | } |
4702 | return CP_ACCESS_OK; | |
4703 | } | |
4704 | ||
4705 | static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
4706 | { | |
2fc0cc0e | 4707 | ARMCPU *cpu = env_archcpu(env); |
aca3f40b PM |
4708 | int dzp_bit = 1 << 4; |
4709 | ||
4710 | /* DZP indicates whether DC ZVA access is allowed */ | |
3f208fd7 | 4711 | if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) { |
aca3f40b PM |
4712 | dzp_bit = 0; |
4713 | } | |
4714 | return cpu->dcz_blocksize | dzp_bit; | |
4715 | } | |
4716 | ||
3f208fd7 PM |
4717 | static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4718 | bool isread) | |
f502cfc2 | 4719 | { |
cdcf1405 | 4720 | if (!(env->pstate & PSTATE_SP)) { |
f502cfc2 PM |
4721 | /* Access to SP_EL0 is undefined if it's being used as |
4722 | * the stack pointer. | |
4723 | */ | |
4724 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
4725 | } | |
4726 | return CP_ACCESS_OK; | |
4727 | } | |
4728 | ||
4729 | static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
4730 | { | |
4731 | return env->pstate & PSTATE_SP; | |
4732 | } | |
4733 | ||
4734 | static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
4735 | { | |
4736 | update_spsel(env, val); | |
4737 | } | |
4738 | ||
137feaa9 FA |
4739 | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4740 | uint64_t value) | |
4741 | { | |
2fc0cc0e | 4742 | ARMCPU *cpu = env_archcpu(env); |
137feaa9 | 4743 | |
f00faf13 RH |
4744 | if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { |
4745 | /* M bit is RAZ/WI for PMSA with no MPU implemented */ | |
4746 | value &= ~SCTLR_M; | |
4747 | } | |
4748 | ||
4749 | /* ??? Lots of these bits are not implemented. */ | |
4750 | ||
4751 | if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) { | |
4752 | if (ri->opc1 == 6) { /* SCTLR_EL3 */ | |
4753 | value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); | |
4754 | } else { | |
4755 | value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | | |
4756 | SCTLR_ATA0 | SCTLR_ATA); | |
4757 | } | |
4758 | } | |
4759 | ||
137feaa9 FA |
4760 | if (raw_read(env, ri) == value) { |
4761 | /* Skip the TLB flush if nothing actually changed; Linux likes | |
4762 | * to do a lot of pointless SCTLR writes. | |
4763 | */ | |
4764 | return; | |
4765 | } | |
4766 | ||
4767 | raw_write(env, ri, value); | |
f00faf13 | 4768 | |
137feaa9 | 4769 | /* This may enable/disable the MMU, so do a TLB flush. */ |
d10eb08f | 4770 | tlb_flush(CPU(cpu)); |
2e5dcf36 RH |
4771 | |
4772 | if (ri->type & ARM_CP_SUPPRESS_TB_END) { | |
4773 | /* | |
4774 | * Normally we would always end the TB on an SCTLR write; see the | |
4775 | * comment in ARMCPRegInfo sctlr initialization below for why Xscale | |
4776 | * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild | |
4777 | * of hflags from the translator, so do it here. | |
4778 | */ | |
4779 | arm_rebuild_hflags(env); | |
4780 | } | |
137feaa9 FA |
4781 | } |
4782 | ||
3f208fd7 PM |
4783 | static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4784 | bool isread) | |
03fbf20f PM |
4785 | { |
4786 | if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { | |
f2cae609 | 4787 | return CP_ACCESS_TRAP_FP_EL2; |
03fbf20f PM |
4788 | } |
4789 | if (env->cp15.cptr_el[3] & CPTR_TFP) { | |
f2cae609 | 4790 | return CP_ACCESS_TRAP_FP_EL3; |
03fbf20f PM |
4791 | } |
4792 | return CP_ACCESS_OK; | |
4793 | } | |
4794 | ||
a8d64e73 PM |
4795 | static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4796 | uint64_t value) | |
4797 | { | |
4798 | env->cp15.mdcr_el3 = value & SDCR_VALID_MASK; | |
4799 | } | |
4800 | ||
b0d2b7d0 PM |
4801 | static const ARMCPRegInfo v8_cp_reginfo[] = { |
4802 | /* Minimal set of EL0-visible registers. This will need to be expanded | |
4803 | * significantly for system emulation of AArch64 CPUs. | |
4804 | */ | |
4805 | { .name = "NZCV", .state = ARM_CP_STATE_AA64, | |
4806 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, | |
4807 | .access = PL0_RW, .type = ARM_CP_NZCV }, | |
c2b820fe PM |
4808 | { .name = "DAIF", .state = ARM_CP_STATE_AA64, |
4809 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, | |
7a0e58fa | 4810 | .type = ARM_CP_NO_RAW, |
c2b820fe PM |
4811 | .access = PL0_RW, .accessfn = aa64_daif_access, |
4812 | .fieldoffset = offsetof(CPUARMState, daif), | |
4813 | .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, | |
b0d2b7d0 PM |
4814 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, |
4815 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | |
b916c9c3 | 4816 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 4817 | .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, |
b0d2b7d0 PM |
4818 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, |
4819 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | |
b916c9c3 | 4820 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 4821 | .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, |
b0d2b7d0 PM |
4822 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, |
4823 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | |
7a0e58fa | 4824 | .access = PL0_R, .type = ARM_CP_NO_RAW, |
aca3f40b PM |
4825 | .readfn = aa64_dczid_read }, |
4826 | { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, | |
4827 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, | |
4828 | .access = PL0_W, .type = ARM_CP_DC_ZVA, | |
4829 | #ifndef CONFIG_USER_ONLY | |
4830 | /* Avoid overhead of an access check that always passes in user-mode */ | |
4831 | .accessfn = aa64_zva_access, | |
4832 | #endif | |
4833 | }, | |
0eef9d98 PM |
4834 | { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, |
4835 | .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, | |
4836 | .access = PL1_R, .type = ARM_CP_CURRENTEL }, | |
8af35c37 PM |
4837 | /* Cache ops: all NOPs since we don't emulate caches */ |
4838 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, | |
4839 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
38262d8a RH |
4840 | .access = PL1_W, .type = ARM_CP_NOP, |
4841 | .accessfn = aa64_cacheop_pou_access }, | |
8af35c37 PM |
4842 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, |
4843 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
38262d8a RH |
4844 | .access = PL1_W, .type = ARM_CP_NOP, |
4845 | .accessfn = aa64_cacheop_pou_access }, | |
8af35c37 PM |
4846 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, |
4847 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | |
4848 | .access = PL0_W, .type = ARM_CP_NOP, | |
38262d8a | 4849 | .accessfn = aa64_cacheop_pou_access }, |
8af35c37 PM |
4850 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, |
4851 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
1bed4d2e RH |
4852 | .access = PL1_W, .accessfn = aa64_cacheop_poc_access, |
4853 | .type = ARM_CP_NOP }, | |
8af35c37 PM |
4854 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, |
4855 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
1803d271 | 4856 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
8af35c37 PM |
4857 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, |
4858 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | |
4859 | .access = PL0_W, .type = ARM_CP_NOP, | |
1bed4d2e | 4860 | .accessfn = aa64_cacheop_poc_access }, |
8af35c37 PM |
4861 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, |
4862 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
1803d271 | 4863 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
8af35c37 PM |
4864 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, |
4865 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | |
4866 | .access = PL0_W, .type = ARM_CP_NOP, | |
38262d8a | 4867 | .accessfn = aa64_cacheop_pou_access }, |
8af35c37 PM |
4868 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, |
4869 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | |
4870 | .access = PL0_W, .type = ARM_CP_NOP, | |
1bed4d2e | 4871 | .accessfn = aa64_cacheop_poc_access }, |
8af35c37 PM |
4872 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, |
4873 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
1803d271 | 4874 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
168aa23b PM |
4875 | /* TLBI operations */ |
4876 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 4877 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, |
30881b73 | 4878 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4879 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 4880 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4881 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
30881b73 | 4882 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4883 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4884 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4885 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
30881b73 | 4886 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4887 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 4888 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4889 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
30881b73 | 4890 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4891 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4892 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4893 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
30881b73 | 4894 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4895 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4896 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4897 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
30881b73 | 4898 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4899 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4900 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4901 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, |
30881b73 | 4902 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4903 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 4904 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4905 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
30881b73 | 4906 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4907 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4908 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4909 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
30881b73 | 4910 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4911 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 4912 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4913 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
30881b73 | 4914 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4915 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4916 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4917 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
30881b73 | 4918 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4919 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4920 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4921 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
30881b73 | 4922 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4923 | .writefn = tlbi_aa64_vae1_write }, |
cea66e91 PM |
4924 | { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, |
4925 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
bf05340c | 4926 | .access = PL2_W, .type = ARM_CP_NOP }, |
cea66e91 PM |
4927 | { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, |
4928 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
bf05340c | 4929 | .access = PL2_W, .type = ARM_CP_NOP }, |
83ddf975 PM |
4930 | { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, |
4931 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
4932 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 4933 | .writefn = tlbi_aa64_alle1is_write }, |
43efaa33 PM |
4934 | { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, |
4935 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, | |
4936 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4937 | .writefn = tlbi_aa64_alle1is_write }, | |
cea66e91 PM |
4938 | { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, |
4939 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
bf05340c | 4940 | .access = PL2_W, .type = ARM_CP_NOP }, |
cea66e91 PM |
4941 | { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, |
4942 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
bf05340c | 4943 | .access = PL2_W, .type = ARM_CP_NOP }, |
83ddf975 PM |
4944 | { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, |
4945 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
4946 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 4947 | .writefn = tlbi_aa64_alle1_write }, |
43efaa33 PM |
4948 | { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, |
4949 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, | |
4950 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4951 | .writefn = tlbi_aa64_alle1is_write }, | |
19525524 PM |
4952 | #ifndef CONFIG_USER_ONLY |
4953 | /* 64 bit address translation operations */ | |
4954 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
4955 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, | |
0710b2fa PM |
4956 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4957 | .writefn = ats_write64 }, | |
19525524 PM |
4958 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, |
4959 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, | |
0710b2fa PM |
4960 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4961 | .writefn = ats_write64 }, | |
19525524 PM |
4962 | { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, |
4963 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, | |
0710b2fa PM |
4964 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4965 | .writefn = ats_write64 }, | |
19525524 PM |
4966 | { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, |
4967 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, | |
0710b2fa PM |
4968 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4969 | .writefn = ats_write64 }, | |
2a47df95 | 4970 | { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4971 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, |
0710b2fa PM |
4972 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4973 | .writefn = ats_write64 }, | |
2a47df95 | 4974 | { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4975 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, |
0710b2fa PM |
4976 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4977 | .writefn = ats_write64 }, | |
2a47df95 | 4978 | { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4979 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, |
0710b2fa PM |
4980 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4981 | .writefn = ats_write64 }, | |
2a47df95 | 4982 | { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4983 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, |
0710b2fa PM |
4984 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4985 | .writefn = ats_write64 }, | |
2a47df95 PM |
4986 | /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ |
4987 | { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, | |
4988 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, | |
0710b2fa PM |
4989 | .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4990 | .writefn = ats_write64 }, | |
2a47df95 PM |
4991 | { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, |
4992 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, | |
0710b2fa PM |
4993 | .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4994 | .writefn = ats_write64 }, | |
c96fc9b5 EI |
4995 | { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, |
4996 | .type = ARM_CP_ALIAS, | |
4997 | .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, | |
4998 | .access = PL1_RW, .resetvalue = 0, | |
4999 | .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), | |
5000 | .writefn = par_write }, | |
19525524 | 5001 | #endif |
995939a6 | 5002 | /* TLB invalidate last level of translation table walk */ |
9449fdf6 | 5003 | { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
30881b73 RH |
5004 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
5005 | .writefn = tlbimva_is_write }, | |
9449fdf6 | 5006 | { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
30881b73 | 5007 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
fa439fc5 | 5008 | .writefn = tlbimvaa_is_write }, |
9449fdf6 | 5009 | { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
30881b73 RH |
5010 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
5011 | .writefn = tlbimva_write }, | |
9449fdf6 | 5012 | { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
30881b73 RH |
5013 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
5014 | .writefn = tlbimvaa_write }, | |
541ef8c2 SS |
5015 | { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, |
5016 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5017 | .writefn = tlbimva_hyp_write }, | |
5018 | { .name = "TLBIMVALHIS", | |
5019 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
5020 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5021 | .writefn = tlbimva_hyp_is_write }, | |
5022 | { .name = "TLBIIPAS2", | |
5023 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
bf05340c | 5024 | .type = ARM_CP_NOP, .access = PL2_W }, |
541ef8c2 SS |
5025 | { .name = "TLBIIPAS2IS", |
5026 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
bf05340c | 5027 | .type = ARM_CP_NOP, .access = PL2_W }, |
541ef8c2 SS |
5028 | { .name = "TLBIIPAS2L", |
5029 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
bf05340c | 5030 | .type = ARM_CP_NOP, .access = PL2_W }, |
541ef8c2 SS |
5031 | { .name = "TLBIIPAS2LIS", |
5032 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
bf05340c | 5033 | .type = ARM_CP_NOP, .access = PL2_W }, |
9449fdf6 PM |
5034 | /* 32 bit cache operations */ |
5035 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
38262d8a | 5036 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, |
9449fdf6 PM |
5037 | { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, |
5038 | .type = ARM_CP_NOP, .access = PL1_W }, | |
5039 | { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
38262d8a | 5040 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, |
9449fdf6 | 5041 | { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, |
38262d8a | 5042 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, |
9449fdf6 PM |
5043 | { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, |
5044 | .type = ARM_CP_NOP, .access = PL1_W }, | |
5045 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | |
5046 | .type = ARM_CP_NOP, .access = PL1_W }, | |
5047 | { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
1bed4d2e | 5048 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 5049 | { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, |
1803d271 | 5050 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 5051 | { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, |
1bed4d2e | 5052 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 5053 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, |
1803d271 | 5054 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 5055 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, |
38262d8a | 5056 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, |
9449fdf6 | 5057 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, |
1bed4d2e | 5058 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 5059 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, |
1803d271 | 5060 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 5061 | /* MMU Domain access control / MPU write buffer control */ |
0c17d68c | 5062 | { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, |
84929218 | 5063 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
0c17d68c FA |
5064 | .writefn = dacr_write, .raw_writefn = raw_write, |
5065 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
5066 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a0618a19 | 5067 | { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5068 | .type = ARM_CP_ALIAS, |
a0618a19 | 5069 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, |
6947f059 EI |
5070 | .access = PL1_RW, |
5071 | .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, | |
a65f1de9 | 5072 | { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5073 | .type = ARM_CP_ALIAS, |
a65f1de9 | 5074 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
5075 | .access = PL1_RW, |
5076 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, | |
f502cfc2 PM |
5077 | /* We rely on the access checks not allowing the guest to write to the |
5078 | * state field when SPSel indicates that it's being used as the stack | |
5079 | * pointer. | |
5080 | */ | |
5081 | { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, | |
5082 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, | |
5083 | .access = PL1_RW, .accessfn = sp_el0_access, | |
7a0e58fa | 5084 | .type = ARM_CP_ALIAS, |
f502cfc2 | 5085 | .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, |
884b4dee GB |
5086 | { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, |
5087 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 5088 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
884b4dee | 5089 | .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, |
f502cfc2 PM |
5090 | { .name = "SPSel", .state = ARM_CP_STATE_AA64, |
5091 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, | |
7a0e58fa | 5092 | .type = ARM_CP_NO_RAW, |
f502cfc2 | 5093 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, |
03fbf20f PM |
5094 | { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, |
5095 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, | |
5096 | .type = ARM_CP_ALIAS, | |
5097 | .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), | |
5098 | .access = PL2_RW, .accessfn = fpexc32_access }, | |
6a43e0b6 PM |
5099 | { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, |
5100 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, | |
5101 | .access = PL2_RW, .resetvalue = 0, | |
5102 | .writefn = dacr_write, .raw_writefn = raw_write, | |
5103 | .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, | |
5104 | { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, | |
5105 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, | |
5106 | .access = PL2_RW, .resetvalue = 0, | |
5107 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, | |
5108 | { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, | |
5109 | .type = ARM_CP_ALIAS, | |
5110 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, | |
5111 | .access = PL2_RW, | |
5112 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, | |
5113 | { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, | |
5114 | .type = ARM_CP_ALIAS, | |
5115 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, | |
5116 | .access = PL2_RW, | |
5117 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, | |
5118 | { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, | |
5119 | .type = ARM_CP_ALIAS, | |
5120 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, | |
5121 | .access = PL2_RW, | |
5122 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, | |
5123 | { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, | |
5124 | .type = ARM_CP_ALIAS, | |
5125 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, | |
5126 | .access = PL2_RW, | |
5127 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, | |
a8d64e73 PM |
5128 | { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, |
5129 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, | |
5130 | .resetvalue = 0, | |
5131 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) }, | |
5132 | { .name = "SDCR", .type = ARM_CP_ALIAS, | |
5133 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1, | |
5134 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, | |
5135 | .writefn = sdcr_write, | |
5136 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, | |
b0d2b7d0 PM |
5137 | REGINFO_SENTINEL |
5138 | }; | |
5139 | ||
d42e3c26 | 5140 | /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ |
4771cd01 | 5141 | static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { |
d79e0c06 | 5142 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, |
d42e3c26 EI |
5143 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, |
5144 | .access = PL2_RW, | |
5145 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | |
ce4afed8 | 5146 | { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH, |
f149e3e8 EI |
5147 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
5148 | .access = PL2_RW, | |
ce4afed8 | 5149 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
831a2fca PM |
5150 | { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, |
5151 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, | |
5152 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
68e78e33 PM |
5153 | { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, |
5154 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, | |
5155 | .access = PL2_RW, | |
5156 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
c6f19164 GB |
5157 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
5158 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
5159 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
95f949ac EI |
5160 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
5161 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
5162 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5163 | .resetvalue = 0 }, | |
5164 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
b5ede85b | 5165 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, |
95f949ac | 5166 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
2179ef95 PM |
5167 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
5168 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
5169 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5170 | .resetvalue = 0 }, | |
55b53c71 | 5171 | { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, |
b5ede85b | 5172 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, |
2179ef95 PM |
5173 | .access = PL2_RW, .type = ARM_CP_CONST, |
5174 | .resetvalue = 0 }, | |
37cd6c24 PM |
5175 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
5176 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
5177 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5178 | .resetvalue = 0 }, | |
5179 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
5180 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
5181 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5182 | .resetvalue = 0 }, | |
06ec4c8c EI |
5183 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
5184 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
5185 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
68e9c2fe EI |
5186 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH, |
5187 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
93dd1e61 | 5188 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
68e9c2fe | 5189 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
b698e9cf EI |
5190 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
5191 | .cp = 15, .opc1 = 6, .crm = 2, | |
5192 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
5193 | .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | |
5194 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
5195 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
5196 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b9cb5323 EI |
5197 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
5198 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
5199 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
ff05f37b EI |
5200 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
5201 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
5202 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
a57633c0 EI |
5203 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
5204 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
5205 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5206 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
5207 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
5208 | .resetvalue = 0 }, | |
0b6440af EI |
5209 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
5210 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
5211 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
edac4d8a EI |
5212 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
5213 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
5214 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5215 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
5216 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
5217 | .resetvalue = 0 }, | |
b0e66d95 EI |
5218 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
5219 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
5220 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5221 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
5222 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
5223 | .resetvalue = 0 }, | |
5224 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
5225 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
5226 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5227 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
5228 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
5229 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
14cc7b54 SF |
5230 | { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, |
5231 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | |
d6c8cf81 PM |
5232 | .access = PL2_RW, .accessfn = access_tda, |
5233 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
59e05530 EI |
5234 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, |
5235 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
93dd1e61 | 5236 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
59e05530 | 5237 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
2a5a9abd AF |
5238 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
5239 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
5240 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
cba517c3 PM |
5241 | { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, |
5242 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, | |
5243 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5244 | { .name = "HIFAR", .state = ARM_CP_STATE_AA32, | |
5245 | .type = ARM_CP_CONST, | |
5246 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | |
5247 | .access = PL2_RW, .resetvalue = 0 }, | |
d42e3c26 EI |
5248 | REGINFO_SENTINEL |
5249 | }; | |
5250 | ||
ce4afed8 PM |
5251 | /* Ditto, but for registers which exist in ARMv8 but not v7 */ |
5252 | static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { | |
5253 | { .name = "HCR2", .state = ARM_CP_STATE_AA32, | |
5254 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, | |
5255 | .access = PL2_RW, | |
5256 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5257 | REGINFO_SENTINEL | |
5258 | }; | |
5259 | ||
d1fb4da2 | 5260 | static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) |
f149e3e8 | 5261 | { |
2fc0cc0e | 5262 | ARMCPU *cpu = env_archcpu(env); |
d1fb4da2 RH |
5263 | |
5264 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
5265 | valid_mask |= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */ | |
5266 | } else { | |
5267 | valid_mask |= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */ | |
5268 | } | |
f149e3e8 EI |
5269 | |
5270 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
5271 | valid_mask &= ~HCR_HCD; | |
77077a83 JK |
5272 | } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { |
5273 | /* Architecturally HCR.TSC is RES0 if EL3 is not implemented. | |
5274 | * However, if we're using the SMC PSCI conduit then QEMU is | |
5275 | * effectively acting like EL3 firmware and so the guest at | |
5276 | * EL2 should retain the ability to prevent EL1 from being | |
5277 | * able to make SMC calls into the ersatz firmware, so in | |
5278 | * that case HCR.TSC should be read/write. | |
5279 | */ | |
f149e3e8 EI |
5280 | valid_mask &= ~HCR_TSC; |
5281 | } | |
d1fb4da2 RH |
5282 | |
5283 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
5284 | if (cpu_isar_feature(aa64_vh, cpu)) { | |
5285 | valid_mask |= HCR_E2H; | |
5286 | } | |
5287 | if (cpu_isar_feature(aa64_lor, cpu)) { | |
5288 | valid_mask |= HCR_TLOR; | |
5289 | } | |
5290 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
5291 | valid_mask |= HCR_API | HCR_APK; | |
5292 | } | |
8ddb300b RH |
5293 | if (cpu_isar_feature(aa64_mte, cpu)) { |
5294 | valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5; | |
5295 | } | |
ef682cdb | 5296 | } |
f149e3e8 EI |
5297 | |
5298 | /* Clear RES0 bits. */ | |
5299 | value &= valid_mask; | |
5300 | ||
8ddb300b RH |
5301 | /* |
5302 | * These bits change the MMU setup: | |
f149e3e8 EI |
5303 | * HCR_VM enables stage 2 translation |
5304 | * HCR_PTW forbids certain page-table setups | |
8ddb300b RH |
5305 | * HCR_DC disables stage1 and enables stage2 translation |
5306 | * HCR_DCT enables tagging on (disabled) stage1 translation | |
f149e3e8 | 5307 | */ |
8ddb300b | 5308 | if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT)) { |
d10eb08f | 5309 | tlb_flush(CPU(cpu)); |
f149e3e8 | 5310 | } |
ce4afed8 | 5311 | env->cp15.hcr_el2 = value; |
89430fc6 PM |
5312 | |
5313 | /* | |
5314 | * Updates to VI and VF require us to update the status of | |
5315 | * virtual interrupts, which are the logical OR of these bits | |
5316 | * and the state of the input lines from the GIC. (This requires | |
5317 | * that we have the iothread lock, which is done by marking the | |
5318 | * reginfo structs as ARM_CP_IO.) | |
5319 | * Note that if a write to HCR pends a VIRQ or VFIQ it is never | |
5320 | * possible for it to be taken immediately, because VIRQ and | |
5321 | * VFIQ are masked unless running at EL0 or EL1, and HCR | |
5322 | * can only be written at EL2. | |
5323 | */ | |
5324 | g_assert(qemu_mutex_iothread_locked()); | |
5325 | arm_cpu_update_virq(cpu); | |
5326 | arm_cpu_update_vfiq(cpu); | |
ce4afed8 PM |
5327 | } |
5328 | ||
d1fb4da2 RH |
5329 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
5330 | { | |
5331 | do_hcr_write(env, value, 0); | |
5332 | } | |
5333 | ||
ce4afed8 PM |
5334 | static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, |
5335 | uint64_t value) | |
5336 | { | |
5337 | /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */ | |
5338 | value = deposit64(env->cp15.hcr_el2, 32, 32, value); | |
d1fb4da2 | 5339 | do_hcr_write(env, value, MAKE_64BIT_MASK(0, 32)); |
ce4afed8 PM |
5340 | } |
5341 | ||
5342 | static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, | |
5343 | uint64_t value) | |
5344 | { | |
5345 | /* Handle HCR write, i.e. write to low half of HCR_EL2 */ | |
5346 | value = deposit64(env->cp15.hcr_el2, 0, 32, value); | |
d1fb4da2 | 5347 | do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32)); |
f149e3e8 EI |
5348 | } |
5349 | ||
f7778444 RH |
5350 | /* |
5351 | * Return the effective value of HCR_EL2. | |
5352 | * Bits that are not included here: | |
5353 | * RW (read from SCR_EL3.RW as needed) | |
5354 | */ | |
5355 | uint64_t arm_hcr_el2_eff(CPUARMState *env) | |
5356 | { | |
5357 | uint64_t ret = env->cp15.hcr_el2; | |
5358 | ||
e6ef0169 | 5359 | if (!arm_is_el2_enabled(env)) { |
f7778444 RH |
5360 | /* |
5361 | * "This register has no effect if EL2 is not enabled in the | |
5362 | * current Security state". This is ARMv8.4-SecEL2 speak for | |
5363 | * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1). | |
5364 | * | |
5365 | * Prior to that, the language was "In an implementation that | |
5366 | * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves | |
5367 | * as if this field is 0 for all purposes other than a direct | |
5368 | * read or write access of HCR_EL2". With lots of enumeration | |
5369 | * on a per-field basis. In current QEMU, this is condition | |
5370 | * is arm_is_secure_below_el3. | |
5371 | * | |
5372 | * Since the v8.4 language applies to the entire register, and | |
5373 | * appears to be backward compatible, use that. | |
5374 | */ | |
4990e1d3 RH |
5375 | return 0; |
5376 | } | |
5377 | ||
5378 | /* | |
5379 | * For a cpu that supports both aarch64 and aarch32, we can set bits | |
5380 | * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32. | |
5381 | * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32. | |
5382 | */ | |
5383 | if (!arm_el_is_aa64(env, 2)) { | |
5384 | uint64_t aa32_valid; | |
5385 | ||
5386 | /* | |
5387 | * These bits are up-to-date as of ARMv8.6. | |
5388 | * For HCR, it's easiest to list just the 2 bits that are invalid. | |
5389 | * For HCR2, list those that are valid. | |
5390 | */ | |
5391 | aa32_valid = MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ); | |
5392 | aa32_valid |= (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNCE | | |
5393 | HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS); | |
5394 | ret &= aa32_valid; | |
5395 | } | |
5396 | ||
5397 | if (ret & HCR_TGE) { | |
5398 | /* These bits are up-to-date as of ARMv8.6. */ | |
f7778444 RH |
5399 | if (ret & HCR_E2H) { |
5400 | ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | | |
5401 | HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | | |
5402 | HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | | |
4990e1d3 RH |
5403 | HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE | |
5404 | HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT | | |
5405 | HCR_TTLBIS | HCR_TTLBOS | HCR_TID5); | |
f7778444 RH |
5406 | } else { |
5407 | ret |= HCR_FMO | HCR_IMO | HCR_AMO; | |
5408 | } | |
5409 | ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | | |
5410 | HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | | |
5411 | HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | | |
5412 | HCR_TLOR); | |
5413 | } | |
5414 | ||
5415 | return ret; | |
5416 | } | |
5417 | ||
fc1120a7 PM |
5418 | static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5419 | uint64_t value) | |
5420 | { | |
5421 | /* | |
5422 | * For A-profile AArch32 EL3, if NSACR.CP10 | |
5423 | * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. | |
5424 | */ | |
5425 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
5426 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
5427 | value &= ~(0x3 << 10); | |
5428 | value |= env->cp15.cptr_el[2] & (0x3 << 10); | |
5429 | } | |
5430 | env->cp15.cptr_el[2] = value; | |
5431 | } | |
5432 | ||
5433 | static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5434 | { | |
5435 | /* | |
5436 | * For A-profile AArch32 EL3, if NSACR.CP10 | |
5437 | * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. | |
5438 | */ | |
5439 | uint64_t value = env->cp15.cptr_el[2]; | |
5440 | ||
5441 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
5442 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
5443 | value |= 0x3 << 10; | |
5444 | } | |
5445 | return value; | |
5446 | } | |
5447 | ||
4771cd01 | 5448 | static const ARMCPRegInfo el2_cp_reginfo[] = { |
f149e3e8 | 5449 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
89430fc6 | 5450 | .type = ARM_CP_IO, |
f149e3e8 EI |
5451 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
5452 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
c624ea0f | 5453 | .writefn = hcr_write }, |
ce4afed8 | 5454 | { .name = "HCR", .state = ARM_CP_STATE_AA32, |
89430fc6 | 5455 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
5456 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
5457 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
c624ea0f | 5458 | .writefn = hcr_writelow }, |
831a2fca PM |
5459 | { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, |
5460 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, | |
5461 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3b685ba7 | 5462 | { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5463 | .type = ARM_CP_ALIAS, |
3b685ba7 EI |
5464 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, |
5465 | .access = PL2_RW, | |
5466 | .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, | |
68e78e33 | 5467 | { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, |
f2c30f42 EI |
5468 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, |
5469 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, | |
cba517c3 | 5470 | { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, |
63b60551 EI |
5471 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, |
5472 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, | |
cba517c3 PM |
5473 | { .name = "HIFAR", .state = ARM_CP_STATE_AA32, |
5474 | .type = ARM_CP_ALIAS, | |
5475 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | |
5476 | .access = PL2_RW, | |
5477 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) }, | |
3b685ba7 | 5478 | { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5479 | .type = ARM_CP_ALIAS, |
3b685ba7 | 5480 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
5481 | .access = PL2_RW, |
5482 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, | |
d79e0c06 | 5483 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, |
d42e3c26 EI |
5484 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, |
5485 | .access = PL2_RW, .writefn = vbar_write, | |
5486 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), | |
5487 | .resetvalue = 0 }, | |
884b4dee GB |
5488 | { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, |
5489 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 5490 | .access = PL3_RW, .type = ARM_CP_ALIAS, |
884b4dee | 5491 | .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, |
c6f19164 GB |
5492 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
5493 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
5494 | .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, | |
fc1120a7 PM |
5495 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]), |
5496 | .readfn = cptr_el2_read, .writefn = cptr_el2_write }, | |
95f949ac EI |
5497 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
5498 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
5499 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), | |
5500 | .resetvalue = 0 }, | |
5501 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
b5ede85b | 5502 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, |
95f949ac EI |
5503 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
5504 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, | |
2179ef95 PM |
5505 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
5506 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
5507 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5508 | .resetvalue = 0 }, | |
5509 | /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ | |
55b53c71 | 5510 | { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, |
b5ede85b | 5511 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, |
2179ef95 PM |
5512 | .access = PL2_RW, .type = ARM_CP_CONST, |
5513 | .resetvalue = 0 }, | |
37cd6c24 PM |
5514 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
5515 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
5516 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5517 | .resetvalue = 0 }, | |
5518 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
5519 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
5520 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5521 | .resetvalue = 0 }, | |
06ec4c8c EI |
5522 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
5523 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
d06dc933 RH |
5524 | .access = PL2_RW, .writefn = vmsa_tcr_el12_write, |
5525 | /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */ | |
06ec4c8c | 5526 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, |
68e9c2fe EI |
5527 | { .name = "VTCR", .state = ARM_CP_STATE_AA32, |
5528 | .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 | 5529 | .type = ARM_CP_ALIAS, |
68e9c2fe EI |
5530 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
5531 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, | |
5532 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, | |
5533 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 PM |
5534 | .access = PL2_RW, |
5535 | /* no .writefn needed as this can't cause an ASID change; | |
5536 | * no .raw_writefn or .resetfn needed as we never use mask/base_mask | |
5537 | */ | |
68e9c2fe | 5538 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, |
b698e9cf EI |
5539 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
5540 | .cp = 15, .opc1 = 6, .crm = 2, | |
5541 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
5542 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
5543 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), | |
5544 | .writefn = vttbr_write }, | |
5545 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
5546 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
5547 | .access = PL2_RW, .writefn = vttbr_write, | |
5548 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, | |
b9cb5323 EI |
5549 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
5550 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
5551 | .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, | |
5552 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, | |
ff05f37b EI |
5553 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
5554 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
5555 | .access = PL2_RW, .resetvalue = 0, | |
5556 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, | |
a57633c0 EI |
5557 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
5558 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
ed30da8e | 5559 | .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write, |
a57633c0 EI |
5560 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
5561 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
5562 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
a57633c0 | 5563 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
541ef8c2 SS |
5564 | { .name = "TLBIALLNSNH", |
5565 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
5566 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5567 | .writefn = tlbiall_nsnh_write }, | |
5568 | { .name = "TLBIALLNSNHIS", | |
5569 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
5570 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5571 | .writefn = tlbiall_nsnh_is_write }, | |
5572 | { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
5573 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5574 | .writefn = tlbiall_hyp_write }, | |
5575 | { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
5576 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5577 | .writefn = tlbiall_hyp_is_write }, | |
5578 | { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
5579 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5580 | .writefn = tlbimva_hyp_write }, | |
5581 | { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
5582 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5583 | .writefn = tlbimva_hyp_is_write }, | |
51da9014 EI |
5584 | { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, |
5585 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
5586 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 5587 | .writefn = tlbi_aa64_alle2_write }, |
8742d49d EI |
5588 | { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, |
5589 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
5590 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 5591 | .writefn = tlbi_aa64_vae2_write }, |
2bfb9d75 PM |
5592 | { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, |
5593 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, | |
5594 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
5595 | .writefn = tlbi_aa64_vae2_write }, | |
5596 | { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, | |
5597 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
5598 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
5599 | .writefn = tlbi_aa64_alle2is_write }, | |
8742d49d EI |
5600 | { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, |
5601 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
5602 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 5603 | .writefn = tlbi_aa64_vae2is_write }, |
2bfb9d75 PM |
5604 | { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, |
5605 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
5606 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
5607 | .writefn = tlbi_aa64_vae2is_write }, | |
edac4d8a | 5608 | #ifndef CONFIG_USER_ONLY |
2a47df95 PM |
5609 | /* Unlike the other EL2-related AT operations, these must |
5610 | * UNDEF from EL3 if EL2 is not implemented, which is why we | |
5611 | * define them here rather than with the rest of the AT ops. | |
5612 | */ | |
5613 | { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, | |
5614 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
5615 | .access = PL2_W, .accessfn = at_s1e2_access, | |
0710b2fa | 5616 | .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, |
2a47df95 PM |
5617 | { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, |
5618 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | |
5619 | .access = PL2_W, .accessfn = at_s1e2_access, | |
0710b2fa | 5620 | .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, |
14db7fe0 PM |
5621 | /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE |
5622 | * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 | |
5623 | * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose | |
5624 | * to behave as if SCR.NS was 1. | |
5625 | */ | |
5626 | { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
5627 | .access = PL2_W, | |
0710b2fa | 5628 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
14db7fe0 PM |
5629 | { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, |
5630 | .access = PL2_W, | |
0710b2fa | 5631 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
0b6440af EI |
5632 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
5633 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
5634 | /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the | |
5635 | * reset values as IMPDEF. We choose to reset to 3 to comply with | |
5636 | * both ARMv7 and ARMv8. | |
5637 | */ | |
5638 | .access = PL2_RW, .resetvalue = 3, | |
5639 | .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, | |
edac4d8a EI |
5640 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
5641 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
5642 | .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, | |
5643 | .writefn = gt_cntvoff_write, | |
5644 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
5645 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
5646 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, | |
5647 | .writefn = gt_cntvoff_write, | |
5648 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
b0e66d95 EI |
5649 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
5650 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
5651 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
5652 | .type = ARM_CP_IO, .access = PL2_RW, | |
5653 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
5654 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
5655 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
5656 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO, | |
5657 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
5658 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
5659 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
d44ec156 | 5660 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, |
b0e66d95 EI |
5661 | .resetfn = gt_hyp_timer_reset, |
5662 | .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, | |
5663 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
5664 | .type = ARM_CP_IO, | |
5665 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
5666 | .access = PL2_RW, | |
5667 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), | |
5668 | .resetvalue = 0, | |
5669 | .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, | |
edac4d8a | 5670 | #endif |
21c2dd77 PM |
5671 | /* The only field of MDCR_EL2 that has a defined architectural reset value |
5672 | * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N. | |
5673 | */ | |
5674 | { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, | |
5675 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | |
5676 | .access = PL2_RW, .resetvalue = PMCR_NUM_COUNTERS, | |
5677 | .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), }, | |
59e05530 EI |
5678 | { .name = "HPFAR", .state = ARM_CP_STATE_AA32, |
5679 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
5680 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
5681 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
5682 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, | |
5683 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
5684 | .access = PL2_RW, | |
5685 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
2a5a9abd AF |
5686 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
5687 | .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
5688 | .access = PL2_RW, | |
5689 | .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, | |
3b685ba7 EI |
5690 | REGINFO_SENTINEL |
5691 | }; | |
5692 | ||
ce4afed8 PM |
5693 | static const ARMCPRegInfo el2_v8_cp_reginfo[] = { |
5694 | { .name = "HCR2", .state = ARM_CP_STATE_AA32, | |
89430fc6 | 5695 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
5696 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, |
5697 | .access = PL2_RW, | |
5698 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2), | |
5699 | .writefn = hcr_writehigh }, | |
5700 | REGINFO_SENTINEL | |
5701 | }; | |
5702 | ||
e9152ee9 RDC |
5703 | static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5704 | bool isread) | |
5705 | { | |
5706 | if (arm_current_el(env) == 3 || arm_is_secure_below_el3(env)) { | |
5707 | return CP_ACCESS_OK; | |
5708 | } | |
5709 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
5710 | } | |
5711 | ||
5712 | static const ARMCPRegInfo el2_sec_cp_reginfo[] = { | |
5713 | { .name = "VSTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
5714 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 0, | |
5715 | .access = PL2_RW, .accessfn = sel2_access, | |
5716 | .fieldoffset = offsetof(CPUARMState, cp15.vsttbr_el2) }, | |
5717 | { .name = "VSTCR_EL2", .state = ARM_CP_STATE_AA64, | |
5718 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2, | |
5719 | .access = PL2_RW, .accessfn = sel2_access, | |
5720 | .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) }, | |
5721 | REGINFO_SENTINEL | |
5722 | }; | |
5723 | ||
2f027fc5 PM |
5724 | static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5725 | bool isread) | |
5726 | { | |
5727 | /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. | |
926c1b97 | 5728 | * At Secure EL1 it traps to EL3 or EL2. |
2f027fc5 PM |
5729 | */ |
5730 | if (arm_current_el(env) == 3) { | |
5731 | return CP_ACCESS_OK; | |
5732 | } | |
5733 | if (arm_is_secure_below_el3(env)) { | |
926c1b97 RDC |
5734 | if (env->cp15.scr_el3 & SCR_EEL2) { |
5735 | return CP_ACCESS_TRAP_EL2; | |
5736 | } | |
2f027fc5 PM |
5737 | return CP_ACCESS_TRAP_EL3; |
5738 | } | |
5739 | /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ | |
5740 | if (isread) { | |
5741 | return CP_ACCESS_OK; | |
5742 | } | |
5743 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
5744 | } | |
5745 | ||
60fb1a87 GB |
5746 | static const ARMCPRegInfo el3_cp_reginfo[] = { |
5747 | { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, | |
5748 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, | |
5749 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), | |
10d0ef3e | 5750 | .resetfn = scr_reset, .writefn = scr_write }, |
f80741d1 | 5751 | { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL, |
60fb1a87 | 5752 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, |
efe4a274 PM |
5753 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
5754 | .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), | |
b061a82b | 5755 | .writefn = scr_write }, |
60fb1a87 GB |
5756 | { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, |
5757 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, | |
5758 | .access = PL3_RW, .resetvalue = 0, | |
5759 | .fieldoffset = offsetof(CPUARMState, cp15.sder) }, | |
5760 | { .name = "SDER", | |
5761 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, | |
5762 | .access = PL3_RW, .resetvalue = 0, | |
5763 | .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, | |
60fb1a87 | 5764 | { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, |
efe4a274 PM |
5765 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
5766 | .writefn = vbar_write, .resetvalue = 0, | |
60fb1a87 | 5767 | .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, |
7dd8c9af FA |
5768 | { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, |
5769 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, | |
f478847f | 5770 | .access = PL3_RW, .resetvalue = 0, |
7dd8c9af | 5771 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, |
11f136ee FA |
5772 | { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, |
5773 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, | |
6459b94c PM |
5774 | .access = PL3_RW, |
5775 | /* no .writefn needed as this can't cause an ASID change; | |
811595a2 PM |
5776 | * we must provide a .raw_writefn and .resetfn because we handle |
5777 | * reset and migration for the AArch32 TTBCR(S), which might be | |
5778 | * using mask and base_mask. | |
6459b94c | 5779 | */ |
811595a2 | 5780 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, |
11f136ee | 5781 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, |
81547d66 | 5782 | { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5783 | .type = ARM_CP_ALIAS, |
81547d66 EI |
5784 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, |
5785 | .access = PL3_RW, | |
5786 | .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, | |
f2c30f42 | 5787 | { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, |
f2c30f42 EI |
5788 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, |
5789 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, | |
63b60551 EI |
5790 | { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, |
5791 | .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, | |
5792 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, | |
81547d66 | 5793 | { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5794 | .type = ARM_CP_ALIAS, |
81547d66 | 5795 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
5796 | .access = PL3_RW, |
5797 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) }, | |
a1ba125c EI |
5798 | { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, |
5799 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, | |
5800 | .access = PL3_RW, .writefn = vbar_write, | |
5801 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), | |
5802 | .resetvalue = 0 }, | |
c6f19164 GB |
5803 | { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, |
5804 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, | |
5805 | .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, | |
5806 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, | |
4cfb8ad8 PM |
5807 | { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, |
5808 | .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, | |
5809 | .access = PL3_RW, .resetvalue = 0, | |
5810 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, | |
2179ef95 PM |
5811 | { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64, |
5812 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, | |
5813 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5814 | .resetvalue = 0 }, | |
37cd6c24 PM |
5815 | { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, |
5816 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, | |
5817 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5818 | .resetvalue = 0 }, | |
5819 | { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, | |
5820 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, | |
5821 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5822 | .resetvalue = 0 }, | |
43efaa33 PM |
5823 | { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, |
5824 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, | |
5825 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5826 | .writefn = tlbi_aa64_alle3is_write }, | |
5827 | { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, | |
5828 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, | |
5829 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5830 | .writefn = tlbi_aa64_vae3is_write }, | |
5831 | { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, | |
5832 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, | |
5833 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5834 | .writefn = tlbi_aa64_vae3is_write }, | |
5835 | { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, | |
5836 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, | |
5837 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5838 | .writefn = tlbi_aa64_alle3_write }, | |
5839 | { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, | |
5840 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, | |
5841 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5842 | .writefn = tlbi_aa64_vae3_write }, | |
5843 | { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, | |
5844 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, | |
5845 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5846 | .writefn = tlbi_aa64_vae3_write }, | |
0f1a3b24 FA |
5847 | REGINFO_SENTINEL |
5848 | }; | |
5849 | ||
e2cce18f RH |
5850 | #ifndef CONFIG_USER_ONLY |
5851 | /* Test if system register redirection is to occur in the current state. */ | |
5852 | static bool redirect_for_e2h(CPUARMState *env) | |
5853 | { | |
5854 | return arm_current_el(env) == 2 && (arm_hcr_el2_eff(env) & HCR_E2H); | |
5855 | } | |
5856 | ||
5857 | static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5858 | { | |
5859 | CPReadFn *readfn; | |
5860 | ||
5861 | if (redirect_for_e2h(env)) { | |
5862 | /* Switch to the saved EL2 version of the register. */ | |
5863 | ri = ri->opaque; | |
5864 | readfn = ri->readfn; | |
5865 | } else { | |
5866 | readfn = ri->orig_readfn; | |
5867 | } | |
5868 | if (readfn == NULL) { | |
5869 | readfn = raw_read; | |
5870 | } | |
5871 | return readfn(env, ri); | |
5872 | } | |
5873 | ||
5874 | static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5875 | uint64_t value) | |
5876 | { | |
5877 | CPWriteFn *writefn; | |
5878 | ||
5879 | if (redirect_for_e2h(env)) { | |
5880 | /* Switch to the saved EL2 version of the register. */ | |
5881 | ri = ri->opaque; | |
5882 | writefn = ri->writefn; | |
5883 | } else { | |
5884 | writefn = ri->orig_writefn; | |
5885 | } | |
5886 | if (writefn == NULL) { | |
5887 | writefn = raw_write; | |
5888 | } | |
5889 | writefn(env, ri, value); | |
5890 | } | |
5891 | ||
5892 | static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) | |
5893 | { | |
5894 | struct E2HAlias { | |
5895 | uint32_t src_key, dst_key, new_key; | |
5896 | const char *src_name, *dst_name, *new_name; | |
5897 | bool (*feature)(const ARMISARegisters *id); | |
5898 | }; | |
5899 | ||
5900 | #define K(op0, op1, crn, crm, op2) \ | |
5901 | ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) | |
5902 | ||
5903 | static const struct E2HAlias aliases[] = { | |
5904 | { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), | |
5905 | "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, | |
5906 | { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), | |
5907 | "CPACR", "CPTR_EL2", "CPACR_EL12" }, | |
5908 | { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), | |
5909 | "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, | |
5910 | { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), | |
5911 | "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, | |
5912 | { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), | |
5913 | "TCR_EL1", "TCR_EL2", "TCR_EL12" }, | |
5914 | { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), | |
5915 | "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, | |
5916 | { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), | |
5917 | "ELR_EL1", "ELR_EL2", "ELR_EL12" }, | |
5918 | { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0), | |
5919 | "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" }, | |
5920 | { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1), | |
5921 | "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" }, | |
5922 | { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0), | |
5923 | "ESR_EL1", "ESR_EL2", "ESR_EL12" }, | |
5924 | { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0), | |
5925 | "FAR_EL1", "FAR_EL2", "FAR_EL12" }, | |
5926 | { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), | |
5927 | "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, | |
5928 | { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), | |
5929 | "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" }, | |
5930 | { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), | |
5931 | "VBAR", "VBAR_EL2", "VBAR_EL12" }, | |
5932 | { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), | |
5933 | "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, | |
5934 | { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), | |
5935 | "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" }, | |
5936 | ||
5937 | /* | |
5938 | * Note that redirection of ZCR is mentioned in the description | |
5939 | * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but | |
5940 | * not in the summary table. | |
5941 | */ | |
5942 | { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), | |
5943 | "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, | |
5944 | ||
4b779ceb RH |
5945 | { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), |
5946 | "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, | |
5947 | ||
e2cce18f RH |
5948 | /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ |
5949 | /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ | |
5950 | }; | |
5951 | #undef K | |
5952 | ||
5953 | size_t i; | |
5954 | ||
5955 | for (i = 0; i < ARRAY_SIZE(aliases); i++) { | |
5956 | const struct E2HAlias *a = &aliases[i]; | |
5957 | ARMCPRegInfo *src_reg, *dst_reg; | |
5958 | ||
5959 | if (a->feature && !a->feature(&cpu->isar)) { | |
5960 | continue; | |
5961 | } | |
5962 | ||
5963 | src_reg = g_hash_table_lookup(cpu->cp_regs, &a->src_key); | |
5964 | dst_reg = g_hash_table_lookup(cpu->cp_regs, &a->dst_key); | |
5965 | g_assert(src_reg != NULL); | |
5966 | g_assert(dst_reg != NULL); | |
5967 | ||
5968 | /* Cross-compare names to detect typos in the keys. */ | |
5969 | g_assert(strcmp(src_reg->name, a->src_name) == 0); | |
5970 | g_assert(strcmp(dst_reg->name, a->dst_name) == 0); | |
5971 | ||
5972 | /* None of the core system registers use opaque; we will. */ | |
5973 | g_assert(src_reg->opaque == NULL); | |
5974 | ||
5975 | /* Create alias before redirection so we dup the right data. */ | |
5976 | if (a->new_key) { | |
5977 | ARMCPRegInfo *new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo)); | |
5978 | uint32_t *new_key = g_memdup(&a->new_key, sizeof(uint32_t)); | |
5979 | bool ok; | |
5980 | ||
5981 | new_reg->name = a->new_name; | |
5982 | new_reg->type |= ARM_CP_ALIAS; | |
5983 | /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ | |
5984 | new_reg->access &= PL2_RW | PL3_RW; | |
5985 | ||
5986 | ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg); | |
5987 | g_assert(ok); | |
5988 | } | |
5989 | ||
5990 | src_reg->opaque = dst_reg; | |
5991 | src_reg->orig_readfn = src_reg->readfn ?: raw_read; | |
5992 | src_reg->orig_writefn = src_reg->writefn ?: raw_write; | |
5993 | if (!src_reg->raw_readfn) { | |
5994 | src_reg->raw_readfn = raw_read; | |
5995 | } | |
5996 | if (!src_reg->raw_writefn) { | |
5997 | src_reg->raw_writefn = raw_write; | |
5998 | } | |
5999 | src_reg->readfn = el2_e2h_read; | |
6000 | src_reg->writefn = el2_e2h_write; | |
6001 | } | |
6002 | } | |
6003 | #endif | |
6004 | ||
3f208fd7 PM |
6005 | static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
6006 | bool isread) | |
7da845b0 | 6007 | { |
97475a89 RH |
6008 | int cur_el = arm_current_el(env); |
6009 | ||
6010 | if (cur_el < 2) { | |
6011 | uint64_t hcr = arm_hcr_el2_eff(env); | |
6012 | ||
6013 | if (cur_el == 0) { | |
6014 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
6015 | if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) { | |
6016 | return CP_ACCESS_TRAP_EL2; | |
6017 | } | |
6018 | } else { | |
6019 | if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) { | |
6020 | return CP_ACCESS_TRAP; | |
6021 | } | |
6022 | if (hcr & HCR_TID2) { | |
6023 | return CP_ACCESS_TRAP_EL2; | |
6024 | } | |
6025 | } | |
6026 | } else if (hcr & HCR_TID2) { | |
6027 | return CP_ACCESS_TRAP_EL2; | |
6028 | } | |
7da845b0 | 6029 | } |
630fcd4d MZ |
6030 | |
6031 | if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) { | |
6032 | return CP_ACCESS_TRAP_EL2; | |
6033 | } | |
6034 | ||
7da845b0 PM |
6035 | return CP_ACCESS_OK; |
6036 | } | |
6037 | ||
1424ca8d DM |
6038 | static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
6039 | uint64_t value) | |
6040 | { | |
6041 | /* Writes to OSLAR_EL1 may update the OS lock status, which can be | |
6042 | * read via a bit in OSLSR_EL1. | |
6043 | */ | |
6044 | int oslock; | |
6045 | ||
6046 | if (ri->state == ARM_CP_STATE_AA32) { | |
6047 | oslock = (value == 0xC5ACCE55); | |
6048 | } else { | |
6049 | oslock = value & 1; | |
6050 | } | |
6051 | ||
6052 | env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); | |
6053 | } | |
6054 | ||
50300698 | 6055 | static const ARMCPRegInfo debug_cp_reginfo[] = { |
50300698 | 6056 | /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped |
10aae104 PM |
6057 | * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; |
6058 | * unlike DBGDRAR it is never accessible from EL0. | |
6059 | * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 | |
6060 | * accessor. | |
50300698 PM |
6061 | */ |
6062 | { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
91b0a238 PM |
6063 | .access = PL0_R, .accessfn = access_tdra, |
6064 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
10aae104 PM |
6065 | { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, |
6066 | .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, | |
91b0a238 PM |
6067 | .access = PL1_R, .accessfn = access_tdra, |
6068 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
50300698 | 6069 | { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
91b0a238 PM |
6070 | .access = PL0_R, .accessfn = access_tdra, |
6071 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
17a9eb53 | 6072 | /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ |
10aae104 PM |
6073 | { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, |
6074 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
d6c8cf81 | 6075 | .access = PL1_RW, .accessfn = access_tda, |
0e5e8935 PM |
6076 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), |
6077 | .resetvalue = 0 }, | |
49a6f3bf NH |
6078 | /* |
6079 | * MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external | |
6080 | * Debug Communication Channel is not implemented. | |
6081 | */ | |
6082 | { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64, | |
6083 | .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0, | |
6084 | .access = PL0_R, .accessfn = access_tda, | |
6085 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6086 | /* | |
6087 | * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as | |
6088 | * it is unlikely a guest will care. | |
5e8b12ff PM |
6089 | * We don't implement the configurable EL0 access. |
6090 | */ | |
49a6f3bf NH |
6091 | { .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32, |
6092 | .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
7a0e58fa | 6093 | .type = ARM_CP_ALIAS, |
d6c8cf81 | 6094 | .access = PL1_R, .accessfn = access_tda, |
b061a82b | 6095 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, |
10aae104 PM |
6096 | { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, |
6097 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, | |
1424ca8d | 6098 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
187f678d | 6099 | .accessfn = access_tdosa, |
1424ca8d DM |
6100 | .writefn = oslar_write }, |
6101 | { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, | |
6102 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, | |
6103 | .access = PL1_R, .resetvalue = 10, | |
187f678d | 6104 | .accessfn = access_tdosa, |
1424ca8d | 6105 | .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, |
5e8b12ff PM |
6106 | /* Dummy OSDLR_EL1: 32-bit Linux will read this */ |
6107 | { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, | |
6108 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, | |
187f678d PM |
6109 | .access = PL1_RW, .accessfn = access_tdosa, |
6110 | .type = ARM_CP_NOP }, | |
5e8b12ff PM |
6111 | /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't |
6112 | * implement vector catch debug events yet. | |
6113 | */ | |
6114 | { .name = "DBGVCR", | |
6115 | .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
d6c8cf81 PM |
6116 | .access = PL1_RW, .accessfn = access_tda, |
6117 | .type = ARM_CP_NOP }, | |
4d2ec4da PM |
6118 | /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor |
6119 | * to save and restore a 32-bit guest's DBGVCR) | |
6120 | */ | |
6121 | { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, | |
6122 | .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, | |
6123 | .access = PL2_RW, .accessfn = access_tda, | |
6124 | .type = ARM_CP_NOP }, | |
5dbdc434 PM |
6125 | /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications |
6126 | * Channel but Linux may try to access this register. The 32-bit | |
6127 | * alias is DBGDCCINT. | |
6128 | */ | |
6129 | { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, | |
6130 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
6131 | .access = PL1_RW, .accessfn = access_tda, | |
6132 | .type = ARM_CP_NOP }, | |
50300698 PM |
6133 | REGINFO_SENTINEL |
6134 | }; | |
6135 | ||
6136 | static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | |
6137 | /* 64 bit access versions of the (dummy) debug registers */ | |
6138 | { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, | |
6139 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
6140 | { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | |
6141 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
6142 | REGINFO_SENTINEL | |
6143 | }; | |
6144 | ||
60eed086 RH |
6145 | /* Return the exception level to which exceptions should be taken |
6146 | * via SVEAccessTrap. If an exception should be routed through | |
6147 | * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should | |
6148 | * take care of raising that exception. | |
6149 | * C.f. the ARM pseudocode function CheckSVEEnabled. | |
5be5e8ed | 6150 | */ |
ced31551 | 6151 | int sve_exception_el(CPUARMState *env, int el) |
5be5e8ed RH |
6152 | { |
6153 | #ifndef CONFIG_USER_ONLY | |
c2ddb7cf RH |
6154 | uint64_t hcr_el2 = arm_hcr_el2_eff(env); |
6155 | ||
6156 | if (el <= 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { | |
7701cee5 RH |
6157 | /* Check CPACR.ZEN. */ |
6158 | switch (extract32(env->cp15.cpacr_el1, 16, 2)) { | |
6159 | case 1: | |
6160 | if (el != 0) { | |
6161 | break; | |
6162 | } | |
6163 | /* fall through */ | |
6164 | case 0: | |
6165 | case 2: | |
60eed086 | 6166 | /* route_to_el2 */ |
c2ddb7cf | 6167 | return hcr_el2 & HCR_TGE ? 2 : 1; |
5be5e8ed | 6168 | } |
5be5e8ed | 6169 | |
60eed086 | 6170 | /* Check CPACR.FPEN. */ |
7701cee5 RH |
6171 | switch (extract32(env->cp15.cpacr_el1, 20, 2)) { |
6172 | case 1: | |
6173 | if (el != 0) { | |
6174 | break; | |
6175 | } | |
6176 | /* fall through */ | |
6177 | case 0: | |
6178 | case 2: | |
60eed086 | 6179 | return 0; |
5be5e8ed | 6180 | } |
5be5e8ed RH |
6181 | } |
6182 | ||
d5a6fa2d RH |
6183 | /* |
6184 | * CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). | |
60eed086 | 6185 | */ |
d5a6fa2d RH |
6186 | if (el <= 2) { |
6187 | if (hcr_el2 & HCR_E2H) { | |
6188 | /* Check CPTR_EL2.ZEN. */ | |
6189 | switch (extract32(env->cp15.cptr_el[2], 16, 2)) { | |
6190 | case 1: | |
6191 | if (el != 0 || !(hcr_el2 & HCR_TGE)) { | |
6192 | break; | |
6193 | } | |
6194 | /* fall through */ | |
6195 | case 0: | |
6196 | case 2: | |
6197 | return 2; | |
6198 | } | |
6199 | ||
6200 | /* Check CPTR_EL2.FPEN. */ | |
6201 | switch (extract32(env->cp15.cptr_el[2], 20, 2)) { | |
6202 | case 1: | |
6203 | if (el == 2 || !(hcr_el2 & HCR_TGE)) { | |
6204 | break; | |
6205 | } | |
6206 | /* fall through */ | |
6207 | case 0: | |
6208 | case 2: | |
6209 | return 0; | |
6210 | } | |
6211 | } else if (arm_is_el2_enabled(env)) { | |
6212 | if (env->cp15.cptr_el[2] & CPTR_TZ) { | |
6213 | return 2; | |
6214 | } | |
6215 | if (env->cp15.cptr_el[2] & CPTR_TFP) { | |
6216 | return 0; | |
6217 | } | |
60eed086 | 6218 | } |
5be5e8ed RH |
6219 | } |
6220 | ||
60eed086 RH |
6221 | /* CPTR_EL3. Since EZ is negative we must check for EL3. */ |
6222 | if (arm_feature(env, ARM_FEATURE_EL3) | |
6223 | && !(env->cp15.cptr_el[3] & CPTR_EZ)) { | |
5be5e8ed RH |
6224 | return 3; |
6225 | } | |
6226 | #endif | |
6227 | return 0; | |
6228 | } | |
6229 | ||
ce440581 | 6230 | uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) |
0df9142d | 6231 | { |
6e553f2a | 6232 | uint32_t end_len; |
0df9142d | 6233 | |
dc0bc8e7 RH |
6234 | start_len = MIN(start_len, ARM_MAX_VQ - 1); |
6235 | end_len = start_len; | |
6236 | ||
6e553f2a RH |
6237 | if (!test_bit(start_len, cpu->sve_vq_map)) { |
6238 | end_len = find_last_bit(cpu->sve_vq_map, start_len); | |
6239 | assert(end_len < start_len); | |
6240 | } | |
6241 | return end_len; | |
0df9142d AJ |
6242 | } |
6243 | ||
0ab5953b RH |
6244 | /* |
6245 | * Given that SVE is enabled, return the vector length for EL. | |
6246 | */ | |
ced31551 | 6247 | uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) |
0ab5953b | 6248 | { |
2fc0cc0e | 6249 | ARMCPU *cpu = env_archcpu(env); |
0ab5953b RH |
6250 | uint32_t zcr_len = cpu->sve_max_vq - 1; |
6251 | ||
63888fa7 RH |
6252 | if (el <= 1 && |
6253 | (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { | |
0ab5953b RH |
6254 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); |
6255 | } | |
6a02a732 | 6256 | if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) { |
0ab5953b RH |
6257 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); |
6258 | } | |
6a02a732 | 6259 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0ab5953b RH |
6260 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); |
6261 | } | |
0df9142d | 6262 | |
ce440581 | 6263 | return aarch64_sve_zcr_get_valid_len(cpu, zcr_len); |
0ab5953b RH |
6264 | } |
6265 | ||
5be5e8ed RH |
6266 | static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
6267 | uint64_t value) | |
6268 | { | |
0ab5953b RH |
6269 | int cur_el = arm_current_el(env); |
6270 | int old_len = sve_zcr_len_for_el(env, cur_el); | |
6271 | int new_len; | |
6272 | ||
5be5e8ed | 6273 | /* Bits other than [3:0] are RAZ/WI. */ |
7b351d98 | 6274 | QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16); |
5be5e8ed | 6275 | raw_write(env, ri, value & 0xf); |
0ab5953b RH |
6276 | |
6277 | /* | |
6278 | * Because we arrived here, we know both FP and SVE are enabled; | |
6279 | * otherwise we would have trapped access to the ZCR_ELn register. | |
6280 | */ | |
6281 | new_len = sve_zcr_len_for_el(env, cur_el); | |
6282 | if (new_len < old_len) { | |
6283 | aarch64_sve_narrow_vq(env, new_len + 1); | |
6284 | } | |
5be5e8ed RH |
6285 | } |
6286 | ||
6287 | static const ARMCPRegInfo zcr_el1_reginfo = { | |
6288 | .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | |
6289 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 6290 | .access = PL1_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
6291 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), |
6292 | .writefn = zcr_write, .raw_writefn = raw_write | |
6293 | }; | |
6294 | ||
6295 | static const ARMCPRegInfo zcr_el2_reginfo = { | |
6296 | .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | |
6297 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 6298 | .access = PL2_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
6299 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), |
6300 | .writefn = zcr_write, .raw_writefn = raw_write | |
6301 | }; | |
6302 | ||
6303 | static const ARMCPRegInfo zcr_no_el2_reginfo = { | |
6304 | .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | |
6305 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 6306 | .access = PL2_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
6307 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore |
6308 | }; | |
6309 | ||
6310 | static const ARMCPRegInfo zcr_el3_reginfo = { | |
6311 | .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | |
6312 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 6313 | .access = PL3_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
6314 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), |
6315 | .writefn = zcr_write, .raw_writefn = raw_write | |
6316 | }; | |
6317 | ||
9ee98ce8 PM |
6318 | void hw_watchpoint_update(ARMCPU *cpu, int n) |
6319 | { | |
6320 | CPUARMState *env = &cpu->env; | |
6321 | vaddr len = 0; | |
6322 | vaddr wvr = env->cp15.dbgwvr[n]; | |
6323 | uint64_t wcr = env->cp15.dbgwcr[n]; | |
6324 | int mask; | |
6325 | int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; | |
6326 | ||
6327 | if (env->cpu_watchpoint[n]) { | |
6328 | cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); | |
6329 | env->cpu_watchpoint[n] = NULL; | |
6330 | } | |
6331 | ||
6332 | if (!extract64(wcr, 0, 1)) { | |
6333 | /* E bit clear : watchpoint disabled */ | |
6334 | return; | |
6335 | } | |
6336 | ||
6337 | switch (extract64(wcr, 3, 2)) { | |
6338 | case 0: | |
6339 | /* LSC 00 is reserved and must behave as if the wp is disabled */ | |
6340 | return; | |
6341 | case 1: | |
6342 | flags |= BP_MEM_READ; | |
6343 | break; | |
6344 | case 2: | |
6345 | flags |= BP_MEM_WRITE; | |
6346 | break; | |
6347 | case 3: | |
6348 | flags |= BP_MEM_ACCESS; | |
6349 | break; | |
6350 | } | |
6351 | ||
6352 | /* Attempts to use both MASK and BAS fields simultaneously are | |
6353 | * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, | |
6354 | * thus generating a watchpoint for every byte in the masked region. | |
6355 | */ | |
6356 | mask = extract64(wcr, 24, 4); | |
6357 | if (mask == 1 || mask == 2) { | |
6358 | /* Reserved values of MASK; we must act as if the mask value was | |
6359 | * some non-reserved value, or as if the watchpoint were disabled. | |
6360 | * We choose the latter. | |
6361 | */ | |
6362 | return; | |
6363 | } else if (mask) { | |
6364 | /* Watchpoint covers an aligned area up to 2GB in size */ | |
6365 | len = 1ULL << mask; | |
6366 | /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE | |
6367 | * whether the watchpoint fires when the unmasked bits match; we opt | |
6368 | * to generate the exceptions. | |
6369 | */ | |
6370 | wvr &= ~(len - 1); | |
6371 | } else { | |
6372 | /* Watchpoint covers bytes defined by the byte address select bits */ | |
6373 | int bas = extract64(wcr, 5, 8); | |
6374 | int basstart; | |
6375 | ||
9ee98ce8 PM |
6376 | if (extract64(wvr, 2, 1)) { |
6377 | /* Deprecated case of an only 4-aligned address. BAS[7:4] are | |
6378 | * ignored, and BAS[3:0] define which bytes to watch. | |
6379 | */ | |
6380 | bas &= 0xf; | |
6381 | } | |
ae1111d4 RH |
6382 | |
6383 | if (bas == 0) { | |
6384 | /* This must act as if the watchpoint is disabled */ | |
6385 | return; | |
6386 | } | |
6387 | ||
9ee98ce8 PM |
6388 | /* The BAS bits are supposed to be programmed to indicate a contiguous |
6389 | * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether | |
6390 | * we fire for each byte in the word/doubleword addressed by the WVR. | |
6391 | * We choose to ignore any non-zero bits after the first range of 1s. | |
6392 | */ | |
6393 | basstart = ctz32(bas); | |
6394 | len = cto32(bas >> basstart); | |
6395 | wvr += basstart; | |
6396 | } | |
6397 | ||
6398 | cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, | |
6399 | &env->cpu_watchpoint[n]); | |
6400 | } | |
6401 | ||
6402 | void hw_watchpoint_update_all(ARMCPU *cpu) | |
6403 | { | |
6404 | int i; | |
6405 | CPUARMState *env = &cpu->env; | |
6406 | ||
6407 | /* Completely clear out existing QEMU watchpoints and our array, to | |
6408 | * avoid possible stale entries following migration load. | |
6409 | */ | |
6410 | cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); | |
6411 | memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); | |
6412 | ||
6413 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { | |
6414 | hw_watchpoint_update(cpu, i); | |
6415 | } | |
6416 | } | |
6417 | ||
6418 | static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6419 | uint64_t value) | |
6420 | { | |
2fc0cc0e | 6421 | ARMCPU *cpu = env_archcpu(env); |
9ee98ce8 PM |
6422 | int i = ri->crm; |
6423 | ||
6424 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, the | |
6425 | * register reads and behaves as if values written are sign extended. | |
6426 | * Bits [1:0] are RES0. | |
6427 | */ | |
6428 | value = sextract64(value, 0, 49) & ~3ULL; | |
6429 | ||
6430 | raw_write(env, ri, value); | |
6431 | hw_watchpoint_update(cpu, i); | |
6432 | } | |
6433 | ||
6434 | static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6435 | uint64_t value) | |
6436 | { | |
2fc0cc0e | 6437 | ARMCPU *cpu = env_archcpu(env); |
9ee98ce8 PM |
6438 | int i = ri->crm; |
6439 | ||
6440 | raw_write(env, ri, value); | |
6441 | hw_watchpoint_update(cpu, i); | |
6442 | } | |
6443 | ||
46747d15 PM |
6444 | void hw_breakpoint_update(ARMCPU *cpu, int n) |
6445 | { | |
6446 | CPUARMState *env = &cpu->env; | |
6447 | uint64_t bvr = env->cp15.dbgbvr[n]; | |
6448 | uint64_t bcr = env->cp15.dbgbcr[n]; | |
6449 | vaddr addr; | |
6450 | int bt; | |
6451 | int flags = BP_CPU; | |
6452 | ||
6453 | if (env->cpu_breakpoint[n]) { | |
6454 | cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); | |
6455 | env->cpu_breakpoint[n] = NULL; | |
6456 | } | |
6457 | ||
6458 | if (!extract64(bcr, 0, 1)) { | |
6459 | /* E bit clear : watchpoint disabled */ | |
6460 | return; | |
6461 | } | |
6462 | ||
6463 | bt = extract64(bcr, 20, 4); | |
6464 | ||
6465 | switch (bt) { | |
6466 | case 4: /* unlinked address mismatch (reserved if AArch64) */ | |
6467 | case 5: /* linked address mismatch (reserved if AArch64) */ | |
6468 | qemu_log_mask(LOG_UNIMP, | |
0221c8fd | 6469 | "arm: address mismatch breakpoint types not implemented\n"); |
46747d15 PM |
6470 | return; |
6471 | case 0: /* unlinked address match */ | |
6472 | case 1: /* linked address match */ | |
6473 | { | |
6474 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, | |
6475 | * we behave as if the register was sign extended. Bits [1:0] are | |
6476 | * RES0. The BAS field is used to allow setting breakpoints on 16 | |
6477 | * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether | |
6478 | * a bp will fire if the addresses covered by the bp and the addresses | |
6479 | * covered by the insn overlap but the insn doesn't start at the | |
6480 | * start of the bp address range. We choose to require the insn and | |
6481 | * the bp to have the same address. The constraints on writing to | |
6482 | * BAS enforced in dbgbcr_write mean we have only four cases: | |
6483 | * 0b0000 => no breakpoint | |
6484 | * 0b0011 => breakpoint on addr | |
6485 | * 0b1100 => breakpoint on addr + 2 | |
6486 | * 0b1111 => breakpoint on addr | |
6487 | * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). | |
6488 | */ | |
6489 | int bas = extract64(bcr, 5, 4); | |
6490 | addr = sextract64(bvr, 0, 49) & ~3ULL; | |
6491 | if (bas == 0) { | |
6492 | return; | |
6493 | } | |
6494 | if (bas == 0xc) { | |
6495 | addr += 2; | |
6496 | } | |
6497 | break; | |
6498 | } | |
6499 | case 2: /* unlinked context ID match */ | |
6500 | case 8: /* unlinked VMID match (reserved if no EL2) */ | |
6501 | case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ | |
6502 | qemu_log_mask(LOG_UNIMP, | |
0221c8fd | 6503 | "arm: unlinked context breakpoint types not implemented\n"); |
46747d15 PM |
6504 | return; |
6505 | case 9: /* linked VMID match (reserved if no EL2) */ | |
6506 | case 11: /* linked context ID and VMID match (reserved if no EL2) */ | |
6507 | case 3: /* linked context ID match */ | |
6508 | default: | |
6509 | /* We must generate no events for Linked context matches (unless | |
6510 | * they are linked to by some other bp/wp, which is handled in | |
6511 | * updates for the linking bp/wp). We choose to also generate no events | |
6512 | * for reserved values. | |
6513 | */ | |
6514 | return; | |
6515 | } | |
6516 | ||
6517 | cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); | |
6518 | } | |
6519 | ||
6520 | void hw_breakpoint_update_all(ARMCPU *cpu) | |
6521 | { | |
6522 | int i; | |
6523 | CPUARMState *env = &cpu->env; | |
6524 | ||
6525 | /* Completely clear out existing QEMU breakpoints and our array, to | |
6526 | * avoid possible stale entries following migration load. | |
6527 | */ | |
6528 | cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); | |
6529 | memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); | |
6530 | ||
6531 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { | |
6532 | hw_breakpoint_update(cpu, i); | |
6533 | } | |
6534 | } | |
6535 | ||
6536 | static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6537 | uint64_t value) | |
6538 | { | |
2fc0cc0e | 6539 | ARMCPU *cpu = env_archcpu(env); |
46747d15 PM |
6540 | int i = ri->crm; |
6541 | ||
6542 | raw_write(env, ri, value); | |
6543 | hw_breakpoint_update(cpu, i); | |
6544 | } | |
6545 | ||
6546 | static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6547 | uint64_t value) | |
6548 | { | |
2fc0cc0e | 6549 | ARMCPU *cpu = env_archcpu(env); |
46747d15 PM |
6550 | int i = ri->crm; |
6551 | ||
6552 | /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only | |
6553 | * copy of BAS[0]. | |
6554 | */ | |
6555 | value = deposit64(value, 6, 1, extract64(value, 5, 1)); | |
6556 | value = deposit64(value, 8, 1, extract64(value, 7, 1)); | |
6557 | ||
6558 | raw_write(env, ri, value); | |
6559 | hw_breakpoint_update(cpu, i); | |
6560 | } | |
6561 | ||
50300698 | 6562 | static void define_debug_regs(ARMCPU *cpu) |
0b45451e | 6563 | { |
50300698 PM |
6564 | /* Define v7 and v8 architectural debug registers. |
6565 | * These are just dummy implementations for now. | |
0b45451e PM |
6566 | */ |
6567 | int i; | |
3ff6fc91 | 6568 | int wrps, brps, ctx_cmps; |
54a78718 RH |
6569 | |
6570 | /* | |
6571 | * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot | |
6572 | * use AArch32. Given that bit 15 is RES1, if the value is 0 then | |
6573 | * the register must not exist for this cpu. | |
6574 | */ | |
6575 | if (cpu->isar.dbgdidr != 0) { | |
6576 | ARMCPRegInfo dbgdidr = { | |
6577 | .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, | |
6578 | .opc1 = 0, .opc2 = 0, | |
6579 | .access = PL0_R, .accessfn = access_tda, | |
6580 | .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr, | |
6581 | }; | |
6582 | define_one_arm_cp_reg(cpu, &dbgdidr); | |
6583 | } | |
48eb3ae6 | 6584 | |
3ff6fc91 | 6585 | /* Note that all these register fields hold "number of Xs minus 1". */ |
88ce6c6e PM |
6586 | brps = arm_num_brps(cpu); |
6587 | wrps = arm_num_wrps(cpu); | |
6588 | ctx_cmps = arm_num_ctx_cmps(cpu); | |
3ff6fc91 PM |
6589 | |
6590 | assert(ctx_cmps <= brps); | |
48eb3ae6 | 6591 | |
50300698 PM |
6592 | define_arm_cp_regs(cpu, debug_cp_reginfo); |
6593 | ||
6594 | if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { | |
6595 | define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); | |
6596 | } | |
6597 | ||
88ce6c6e | 6598 | for (i = 0; i < brps; i++) { |
0b45451e | 6599 | ARMCPRegInfo dbgregs[] = { |
10aae104 PM |
6600 | { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH, |
6601 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, | |
d6c8cf81 | 6602 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
6603 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), |
6604 | .writefn = dbgbvr_write, .raw_writefn = raw_write | |
6605 | }, | |
10aae104 PM |
6606 | { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH, |
6607 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, | |
d6c8cf81 | 6608 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
6609 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), |
6610 | .writefn = dbgbcr_write, .raw_writefn = raw_write | |
6611 | }, | |
48eb3ae6 PM |
6612 | REGINFO_SENTINEL |
6613 | }; | |
6614 | define_arm_cp_regs(cpu, dbgregs); | |
6615 | } | |
6616 | ||
88ce6c6e | 6617 | for (i = 0; i < wrps; i++) { |
48eb3ae6 | 6618 | ARMCPRegInfo dbgregs[] = { |
10aae104 PM |
6619 | { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH, |
6620 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, | |
d6c8cf81 | 6621 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
6622 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), |
6623 | .writefn = dbgwvr_write, .raw_writefn = raw_write | |
6624 | }, | |
10aae104 PM |
6625 | { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH, |
6626 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, | |
d6c8cf81 | 6627 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
6628 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), |
6629 | .writefn = dbgwcr_write, .raw_writefn = raw_write | |
6630 | }, | |
6631 | REGINFO_SENTINEL | |
0b45451e PM |
6632 | }; |
6633 | define_arm_cp_regs(cpu, dbgregs); | |
6634 | } | |
6635 | } | |
6636 | ||
24183fb6 PM |
6637 | static void define_pmu_regs(ARMCPU *cpu) |
6638 | { | |
6639 | /* | |
6640 | * v7 performance monitor control register: same implementor | |
6641 | * field as main ID register, and we implement four counters in | |
6642 | * addition to the cycle count register. | |
6643 | */ | |
21c2dd77 | 6644 | unsigned int i, pmcrn = PMCR_NUM_COUNTERS; |
24183fb6 PM |
6645 | ARMCPRegInfo pmcr = { |
6646 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | |
6647 | .access = PL0_RW, | |
6648 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6649 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), | |
6650 | .accessfn = pmreg_access, .writefn = pmcr_write, | |
6651 | .raw_writefn = raw_write, | |
6652 | }; | |
6653 | ARMCPRegInfo pmcr64 = { | |
6654 | .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, | |
6655 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, | |
6656 | .access = PL0_RW, .accessfn = pmreg_access, | |
6657 | .type = ARM_CP_IO, | |
6658 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), | |
21c2dd77 PM |
6659 | .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) | |
6660 | PMCRLC, | |
24183fb6 PM |
6661 | .writefn = pmcr_write, .raw_writefn = raw_write, |
6662 | }; | |
6663 | define_one_arm_cp_reg(cpu, &pmcr); | |
6664 | define_one_arm_cp_reg(cpu, &pmcr64); | |
6665 | for (i = 0; i < pmcrn; i++) { | |
6666 | char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i); | |
6667 | char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i); | |
6668 | char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i); | |
6669 | char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i); | |
6670 | ARMCPRegInfo pmev_regs[] = { | |
6671 | { .name = pmevcntr_name, .cp = 15, .crn = 14, | |
6672 | .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, | |
6673 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6674 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, | |
6675 | .accessfn = pmreg_access }, | |
6676 | { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64, | |
6677 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)), | |
6678 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, | |
6679 | .type = ARM_CP_IO, | |
6680 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, | |
6681 | .raw_readfn = pmevcntr_rawread, | |
6682 | .raw_writefn = pmevcntr_rawwrite }, | |
6683 | { .name = pmevtyper_name, .cp = 15, .crn = 14, | |
6684 | .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, | |
6685 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6686 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | |
6687 | .accessfn = pmreg_access }, | |
6688 | { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64, | |
6689 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)), | |
6690 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, | |
6691 | .type = ARM_CP_IO, | |
6692 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | |
6693 | .raw_writefn = pmevtyper_rawwrite }, | |
6694 | REGINFO_SENTINEL | |
6695 | }; | |
6696 | define_arm_cp_regs(cpu, pmev_regs); | |
6697 | g_free(pmevcntr_name); | |
6698 | g_free(pmevcntr_el0_name); | |
6699 | g_free(pmevtyper_name); | |
6700 | g_free(pmevtyper_el0_name); | |
6701 | } | |
a6179538 | 6702 | if (cpu_isar_feature(aa32_pmu_8_1, cpu)) { |
24183fb6 PM |
6703 | ARMCPRegInfo v81_pmu_regs[] = { |
6704 | { .name = "PMCEID2", .state = ARM_CP_STATE_AA32, | |
6705 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4, | |
6706 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6707 | .resetvalue = extract64(cpu->pmceid0, 32, 32) }, | |
6708 | { .name = "PMCEID3", .state = ARM_CP_STATE_AA32, | |
6709 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5, | |
6710 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6711 | .resetvalue = extract64(cpu->pmceid1, 32, 32) }, | |
6712 | REGINFO_SENTINEL | |
6713 | }; | |
6714 | define_arm_cp_regs(cpu, v81_pmu_regs); | |
6715 | } | |
15dd1ebd PM |
6716 | if (cpu_isar_feature(any_pmu_8_4, cpu)) { |
6717 | static const ARMCPRegInfo v84_pmmir = { | |
6718 | .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH, | |
6719 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6, | |
6720 | .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6721 | .resetvalue = 0 | |
6722 | }; | |
6723 | define_one_arm_cp_reg(cpu, &v84_pmmir); | |
6724 | } | |
24183fb6 PM |
6725 | } |
6726 | ||
96a8b92e PM |
6727 | /* We don't know until after realize whether there's a GICv3 |
6728 | * attached, and that is what registers the gicv3 sysregs. | |
6729 | * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1 | |
6730 | * at runtime. | |
6731 | */ | |
6732 | static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
6733 | { | |
2fc0cc0e | 6734 | ARMCPU *cpu = env_archcpu(env); |
8a130a7b | 6735 | uint64_t pfr1 = cpu->isar.id_pfr1; |
96a8b92e PM |
6736 | |
6737 | if (env->gicv3state) { | |
6738 | pfr1 |= 1 << 28; | |
6739 | } | |
6740 | return pfr1; | |
6741 | } | |
6742 | ||
976b99b6 | 6743 | #ifndef CONFIG_USER_ONLY |
96a8b92e PM |
6744 | static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) |
6745 | { | |
2fc0cc0e | 6746 | ARMCPU *cpu = env_archcpu(env); |
47576b94 | 6747 | uint64_t pfr0 = cpu->isar.id_aa64pfr0; |
96a8b92e PM |
6748 | |
6749 | if (env->gicv3state) { | |
6750 | pfr0 |= 1 << 24; | |
6751 | } | |
6752 | return pfr0; | |
6753 | } | |
976b99b6 | 6754 | #endif |
96a8b92e | 6755 | |
2d7137c1 | 6756 | /* Shared logic between LORID and the rest of the LOR* registers. |
9bd268ba | 6757 | * Secure state exclusion has already been dealt with. |
2d7137c1 | 6758 | */ |
9bd268ba RDC |
6759 | static CPAccessResult access_lor_ns(CPUARMState *env, |
6760 | const ARMCPRegInfo *ri, bool isread) | |
2d7137c1 RH |
6761 | { |
6762 | int el = arm_current_el(env); | |
6763 | ||
6764 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) { | |
6765 | return CP_ACCESS_TRAP_EL2; | |
6766 | } | |
6767 | if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { | |
6768 | return CP_ACCESS_TRAP_EL3; | |
6769 | } | |
6770 | return CP_ACCESS_OK; | |
6771 | } | |
6772 | ||
2d7137c1 RH |
6773 | static CPAccessResult access_lor_other(CPUARMState *env, |
6774 | const ARMCPRegInfo *ri, bool isread) | |
6775 | { | |
6776 | if (arm_is_secure_below_el3(env)) { | |
6777 | /* Access denied in secure mode. */ | |
6778 | return CP_ACCESS_TRAP; | |
6779 | } | |
9bd268ba | 6780 | return access_lor_ns(env, ri, isread); |
2d7137c1 RH |
6781 | } |
6782 | ||
d8564ee4 RH |
6783 | /* |
6784 | * A trivial implementation of ARMv8.1-LOR leaves all of these | |
6785 | * registers fixed at 0, which indicates that there are zero | |
6786 | * supported Limited Ordering regions. | |
6787 | */ | |
6788 | static const ARMCPRegInfo lor_reginfo[] = { | |
6789 | { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, | |
6790 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, | |
6791 | .access = PL1_RW, .accessfn = access_lor_other, | |
6792 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6793 | { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, | |
6794 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, | |
6795 | .access = PL1_RW, .accessfn = access_lor_other, | |
6796 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6797 | { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, | |
6798 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, | |
6799 | .access = PL1_RW, .accessfn = access_lor_other, | |
6800 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6801 | { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, | |
6802 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, | |
6803 | .access = PL1_RW, .accessfn = access_lor_other, | |
6804 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6805 | { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, | |
6806 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, | |
9bd268ba | 6807 | .access = PL1_R, .accessfn = access_lor_ns, |
d8564ee4 RH |
6808 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
6809 | REGINFO_SENTINEL | |
6810 | }; | |
6811 | ||
967aa94f RH |
6812 | #ifdef TARGET_AARCH64 |
6813 | static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, | |
6814 | bool isread) | |
6815 | { | |
6816 | int el = arm_current_el(env); | |
6817 | ||
6818 | if (el < 2 && | |
6819 | arm_feature(env, ARM_FEATURE_EL2) && | |
6820 | !(arm_hcr_el2_eff(env) & HCR_APK)) { | |
6821 | return CP_ACCESS_TRAP_EL2; | |
6822 | } | |
6823 | if (el < 3 && | |
6824 | arm_feature(env, ARM_FEATURE_EL3) && | |
6825 | !(env->cp15.scr_el3 & SCR_APK)) { | |
6826 | return CP_ACCESS_TRAP_EL3; | |
6827 | } | |
6828 | return CP_ACCESS_OK; | |
6829 | } | |
6830 | ||
6831 | static const ARMCPRegInfo pauth_reginfo[] = { | |
6832 | { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64, | |
6833 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0, | |
6834 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6835 | .fieldoffset = offsetof(CPUARMState, keys.apda.lo) }, |
967aa94f RH |
6836 | { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6837 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1, | |
6838 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6839 | .fieldoffset = offsetof(CPUARMState, keys.apda.hi) }, |
967aa94f RH |
6840 | { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
6841 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2, | |
6842 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6843 | .fieldoffset = offsetof(CPUARMState, keys.apdb.lo) }, |
967aa94f RH |
6844 | { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6845 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3, | |
6846 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6847 | .fieldoffset = offsetof(CPUARMState, keys.apdb.hi) }, |
967aa94f RH |
6848 | { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
6849 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0, | |
6850 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6851 | .fieldoffset = offsetof(CPUARMState, keys.apga.lo) }, |
967aa94f RH |
6852 | { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6853 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1, | |
6854 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6855 | .fieldoffset = offsetof(CPUARMState, keys.apga.hi) }, |
967aa94f RH |
6856 | { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
6857 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0, | |
6858 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6859 | .fieldoffset = offsetof(CPUARMState, keys.apia.lo) }, |
967aa94f RH |
6860 | { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6861 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1, | |
6862 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6863 | .fieldoffset = offsetof(CPUARMState, keys.apia.hi) }, |
967aa94f RH |
6864 | { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
6865 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2, | |
6866 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6867 | .fieldoffset = offsetof(CPUARMState, keys.apib.lo) }, |
967aa94f RH |
6868 | { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6869 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3, | |
6870 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6871 | .fieldoffset = offsetof(CPUARMState, keys.apib.hi) }, |
967aa94f RH |
6872 | REGINFO_SENTINEL |
6873 | }; | |
de390645 | 6874 | |
84940ed8 RC |
6875 | static const ARMCPRegInfo tlbirange_reginfo[] = { |
6876 | { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64, | |
6877 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1, | |
6878 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6879 | .writefn = tlbi_aa64_rvae1is_write }, | |
6880 | { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64, | |
6881 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3, | |
6882 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6883 | .writefn = tlbi_aa64_rvae1is_write }, | |
6884 | { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64, | |
6885 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5, | |
6886 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6887 | .writefn = tlbi_aa64_rvae1is_write }, | |
6888 | { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64, | |
6889 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7, | |
6890 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6891 | .writefn = tlbi_aa64_rvae1is_write }, | |
6892 | { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64, | |
6893 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, | |
6894 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6895 | .writefn = tlbi_aa64_rvae1is_write }, | |
6896 | { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64, | |
6897 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3, | |
6898 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6899 | .writefn = tlbi_aa64_rvae1is_write }, | |
6900 | { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64, | |
6901 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5, | |
6902 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6903 | .writefn = tlbi_aa64_rvae1is_write }, | |
6904 | { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64, | |
6905 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7, | |
6906 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6907 | .writefn = tlbi_aa64_rvae1is_write }, | |
6908 | { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64, | |
6909 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, | |
6910 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6911 | .writefn = tlbi_aa64_rvae1_write }, | |
6912 | { .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64, | |
6913 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3, | |
6914 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6915 | .writefn = tlbi_aa64_rvae1_write }, | |
6916 | { .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64, | |
6917 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5, | |
6918 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6919 | .writefn = tlbi_aa64_rvae1_write }, | |
6920 | { .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64, | |
6921 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7, | |
6922 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6923 | .writefn = tlbi_aa64_rvae1_write }, | |
6924 | { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64, | |
6925 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2, | |
6926 | .access = PL2_W, .type = ARM_CP_NOP }, | |
6927 | { .name = "TLBI_RIPAS2LE1IS", .state = ARM_CP_STATE_AA64, | |
6928 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 6, | |
6929 | .access = PL2_W, .type = ARM_CP_NOP }, | |
6930 | { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64, | |
6931 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1, | |
6932 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
6933 | .writefn = tlbi_aa64_rvae2is_write }, | |
6934 | { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64, | |
6935 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5, | |
6936 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
6937 | .writefn = tlbi_aa64_rvae2is_write }, | |
6938 | { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64, | |
6939 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2, | |
6940 | .access = PL2_W, .type = ARM_CP_NOP }, | |
6941 | { .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64, | |
6942 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 6, | |
6943 | .access = PL2_W, .type = ARM_CP_NOP }, | |
6944 | { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64, | |
6945 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1, | |
6946 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
6947 | .writefn = tlbi_aa64_rvae2is_write }, | |
6948 | { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64, | |
6949 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5, | |
6950 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
6951 | .writefn = tlbi_aa64_rvae2is_write }, | |
6952 | { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64, | |
6953 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1, | |
6954 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
6955 | .writefn = tlbi_aa64_rvae2_write }, | |
6956 | { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64, | |
6957 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5, | |
6958 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
6959 | .writefn = tlbi_aa64_rvae2_write }, | |
6960 | { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64, | |
6961 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1, | |
6962 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6963 | .writefn = tlbi_aa64_rvae3is_write }, | |
6964 | { .name = "TLBI_RVALE3IS", .state = ARM_CP_STATE_AA64, | |
6965 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 5, | |
6966 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6967 | .writefn = tlbi_aa64_rvae3is_write }, | |
6968 | { .name = "TLBI_RVAE3OS", .state = ARM_CP_STATE_AA64, | |
6969 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 1, | |
6970 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6971 | .writefn = tlbi_aa64_rvae3is_write }, | |
6972 | { .name = "TLBI_RVALE3OS", .state = ARM_CP_STATE_AA64, | |
6973 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 5, | |
6974 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6975 | .writefn = tlbi_aa64_rvae3is_write }, | |
6976 | { .name = "TLBI_RVAE3", .state = ARM_CP_STATE_AA64, | |
6977 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 1, | |
6978 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6979 | .writefn = tlbi_aa64_rvae3_write }, | |
6980 | { .name = "TLBI_RVALE3", .state = ARM_CP_STATE_AA64, | |
6981 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5, | |
6982 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6983 | .writefn = tlbi_aa64_rvae3_write }, | |
6984 | REGINFO_SENTINEL | |
6985 | }; | |
6986 | ||
7113d618 RC |
6987 | static const ARMCPRegInfo tlbios_reginfo[] = { |
6988 | { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64, | |
6989 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0, | |
6990 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6991 | .writefn = tlbi_aa64_vmalle1is_write }, | |
b7469ef9 IH |
6992 | { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64, |
6993 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1, | |
6994 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6995 | .writefn = tlbi_aa64_vae1is_write }, | |
7113d618 RC |
6996 | { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64, |
6997 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2, | |
6998 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6999 | .writefn = tlbi_aa64_vmalle1is_write }, | |
b7469ef9 IH |
7000 | { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64, |
7001 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3, | |
7002 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
7003 | .writefn = tlbi_aa64_vae1is_write }, | |
7004 | { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64, | |
7005 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5, | |
7006 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
7007 | .writefn = tlbi_aa64_vae1is_write }, | |
7008 | { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64, | |
7009 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7, | |
7010 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
7011 | .writefn = tlbi_aa64_vae1is_write }, | |
7113d618 RC |
7012 | { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64, |
7013 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0, | |
7014 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
7015 | .writefn = tlbi_aa64_alle2is_write }, | |
b7469ef9 IH |
7016 | { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64, |
7017 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1, | |
7018 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
7019 | .writefn = tlbi_aa64_vae2is_write }, | |
7113d618 RC |
7020 | { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64, |
7021 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4, | |
7022 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
7023 | .writefn = tlbi_aa64_alle1is_write }, | |
b7469ef9 IH |
7024 | { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64, |
7025 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5, | |
7026 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
7027 | .writefn = tlbi_aa64_vae2is_write }, | |
7113d618 RC |
7028 | { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64, |
7029 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6, | |
7030 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
7031 | .writefn = tlbi_aa64_alle1is_write }, | |
7032 | { .name = "TLBI_IPAS2E1OS", .state = ARM_CP_STATE_AA64, | |
7033 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 0, | |
7034 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7035 | { .name = "TLBI_RIPAS2E1OS", .state = ARM_CP_STATE_AA64, | |
7036 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 3, | |
7037 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7038 | { .name = "TLBI_IPAS2LE1OS", .state = ARM_CP_STATE_AA64, | |
7039 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 4, | |
7040 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7041 | { .name = "TLBI_RIPAS2LE1OS", .state = ARM_CP_STATE_AA64, | |
7042 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 7, | |
7043 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7044 | { .name = "TLBI_ALLE3OS", .state = ARM_CP_STATE_AA64, | |
7045 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 0, | |
7046 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7047 | .writefn = tlbi_aa64_alle3is_write }, | |
b7469ef9 IH |
7048 | { .name = "TLBI_VAE3OS", .state = ARM_CP_STATE_AA64, |
7049 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 1, | |
7050 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7051 | .writefn = tlbi_aa64_vae3is_write }, | |
7052 | { .name = "TLBI_VALE3OS", .state = ARM_CP_STATE_AA64, | |
7053 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5, | |
7054 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7055 | .writefn = tlbi_aa64_vae3is_write }, | |
7113d618 RC |
7056 | REGINFO_SENTINEL |
7057 | }; | |
7058 | ||
de390645 RH |
7059 | static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) |
7060 | { | |
7061 | Error *err = NULL; | |
7062 | uint64_t ret; | |
7063 | ||
7064 | /* Success sets NZCV = 0000. */ | |
7065 | env->NF = env->CF = env->VF = 0, env->ZF = 1; | |
7066 | ||
7067 | if (qemu_guest_getrandom(&ret, sizeof(ret), &err) < 0) { | |
7068 | /* | |
7069 | * ??? Failed, for unknown reasons in the crypto subsystem. | |
7070 | * The best we can do is log the reason and return the | |
7071 | * timed-out indication to the guest. There is no reason | |
7072 | * we know to expect this failure to be transitory, so the | |
7073 | * guest may well hang retrying the operation. | |
7074 | */ | |
7075 | qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", | |
7076 | ri->name, error_get_pretty(err)); | |
7077 | error_free(err); | |
7078 | ||
7079 | env->ZF = 0; /* NZCF = 0100 */ | |
7080 | return 0; | |
7081 | } | |
7082 | return ret; | |
7083 | } | |
7084 | ||
7085 | /* We do not support re-seeding, so the two registers operate the same. */ | |
7086 | static const ARMCPRegInfo rndr_reginfo[] = { | |
7087 | { .name = "RNDR", .state = ARM_CP_STATE_AA64, | |
7088 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | |
7089 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 0, | |
7090 | .access = PL0_R, .readfn = rndr_readfn }, | |
7091 | { .name = "RNDRRS", .state = ARM_CP_STATE_AA64, | |
7092 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | |
7093 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1, | |
7094 | .access = PL0_R, .readfn = rndr_readfn }, | |
7095 | REGINFO_SENTINEL | |
7096 | }; | |
0d57b499 BM |
7097 | |
7098 | #ifndef CONFIG_USER_ONLY | |
7099 | static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, | |
7100 | uint64_t value) | |
7101 | { | |
7102 | ARMCPU *cpu = env_archcpu(env); | |
7103 | /* CTR_EL0 System register -> DminLine, bits [19:16] */ | |
7104 | uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF); | |
7105 | uint64_t vaddr_in = (uint64_t) value; | |
7106 | uint64_t vaddr = vaddr_in & ~(dline_size - 1); | |
7107 | void *haddr; | |
7108 | int mem_idx = cpu_mmu_index(env, false); | |
7109 | ||
7110 | /* This won't be crossing page boundaries */ | |
7111 | haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC()); | |
7112 | if (haddr) { | |
7113 | ||
7114 | ram_addr_t offset; | |
7115 | MemoryRegion *mr; | |
7116 | ||
7117 | /* RCU lock is already being held */ | |
7118 | mr = memory_region_from_host(haddr, &offset); | |
7119 | ||
7120 | if (mr) { | |
4dfe59d1 | 7121 | memory_region_writeback(mr, offset, dline_size); |
0d57b499 BM |
7122 | } |
7123 | } | |
7124 | } | |
7125 | ||
7126 | static const ARMCPRegInfo dcpop_reg[] = { | |
7127 | { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64, | |
7128 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1, | |
7129 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | |
1bed4d2e | 7130 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, |
0d57b499 BM |
7131 | REGINFO_SENTINEL |
7132 | }; | |
7133 | ||
7134 | static const ARMCPRegInfo dcpodp_reg[] = { | |
7135 | { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64, | |
7136 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1, | |
7137 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | |
1bed4d2e | 7138 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, |
0d57b499 BM |
7139 | REGINFO_SENTINEL |
7140 | }; | |
7141 | #endif /*CONFIG_USER_ONLY*/ | |
7142 | ||
4b779ceb RH |
7143 | static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInfo *ri, |
7144 | bool isread) | |
7145 | { | |
7146 | if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID5)) { | |
7147 | return CP_ACCESS_TRAP_EL2; | |
7148 | } | |
7149 | ||
7150 | return CP_ACCESS_OK; | |
7151 | } | |
7152 | ||
7153 | static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri, | |
7154 | bool isread) | |
7155 | { | |
7156 | int el = arm_current_el(env); | |
7157 | ||
4301acd7 RH |
7158 | if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { |
7159 | uint64_t hcr = arm_hcr_el2_eff(env); | |
7160 | if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { | |
7161 | return CP_ACCESS_TRAP_EL2; | |
7162 | } | |
4b779ceb RH |
7163 | } |
7164 | if (el < 3 && | |
7165 | arm_feature(env, ARM_FEATURE_EL3) && | |
7166 | !(env->cp15.scr_el3 & SCR_ATA)) { | |
7167 | return CP_ACCESS_TRAP_EL3; | |
7168 | } | |
7169 | return CP_ACCESS_OK; | |
7170 | } | |
7171 | ||
7172 | static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
7173 | { | |
7174 | return env->pstate & PSTATE_TCO; | |
7175 | } | |
7176 | ||
7177 | static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
7178 | { | |
7179 | env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); | |
7180 | } | |
7181 | ||
7182 | static const ARMCPRegInfo mte_reginfo[] = { | |
7183 | { .name = "TFSRE0_EL1", .state = ARM_CP_STATE_AA64, | |
7184 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 1, | |
7185 | .access = PL1_RW, .accessfn = access_mte, | |
7186 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) }, | |
7187 | { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64, | |
7188 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 0, | |
7189 | .access = PL1_RW, .accessfn = access_mte, | |
7190 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) }, | |
7191 | { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64, | |
7192 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 6, .opc2 = 0, | |
7193 | .access = PL2_RW, .accessfn = access_mte, | |
7194 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) }, | |
7195 | { .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64, | |
7196 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 6, .opc2 = 0, | |
7197 | .access = PL3_RW, | |
7198 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) }, | |
7199 | { .name = "RGSR_EL1", .state = ARM_CP_STATE_AA64, | |
7200 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5, | |
7201 | .access = PL1_RW, .accessfn = access_mte, | |
7202 | .fieldoffset = offsetof(CPUARMState, cp15.rgsr_el1) }, | |
7203 | { .name = "GCR_EL1", .state = ARM_CP_STATE_AA64, | |
7204 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6, | |
7205 | .access = PL1_RW, .accessfn = access_mte, | |
7206 | .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, | |
7207 | { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, | |
7208 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, | |
7209 | .access = PL1_R, .accessfn = access_aa64_tid5, | |
7210 | .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, | |
7211 | { .name = "TCO", .state = ARM_CP_STATE_AA64, | |
7212 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | |
7213 | .type = ARM_CP_NO_RAW, | |
7214 | .access = PL0_RW, .readfn = tco_read, .writefn = tco_write }, | |
5463df16 RH |
7215 | { .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64, |
7216 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3, | |
7217 | .type = ARM_CP_NOP, .access = PL1_W, | |
7218 | .accessfn = aa64_cacheop_poc_access }, | |
7219 | { .name = "DC_IGSW", .state = ARM_CP_STATE_AA64, | |
7220 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4, | |
7221 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | |
7222 | { .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64, | |
7223 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5, | |
7224 | .type = ARM_CP_NOP, .access = PL1_W, | |
7225 | .accessfn = aa64_cacheop_poc_access }, | |
7226 | { .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64, | |
7227 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6, | |
7228 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | |
7229 | { .name = "DC_CGSW", .state = ARM_CP_STATE_AA64, | |
7230 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4, | |
7231 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | |
7232 | { .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64, | |
7233 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6, | |
7234 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | |
7235 | { .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64, | |
7236 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4, | |
7237 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | |
7238 | { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64, | |
7239 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6, | |
7240 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | |
4b779ceb RH |
7241 | REGINFO_SENTINEL |
7242 | }; | |
7243 | ||
7244 | static const ARMCPRegInfo mte_tco_ro_reginfo[] = { | |
7245 | { .name = "TCO", .state = ARM_CP_STATE_AA64, | |
7246 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | |
7247 | .type = ARM_CP_CONST, .access = PL0_RW, }, | |
7248 | REGINFO_SENTINEL | |
7249 | }; | |
5463df16 RH |
7250 | |
7251 | static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | |
7252 | { .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64, | |
7253 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3, | |
7254 | .type = ARM_CP_NOP, .access = PL0_W, | |
7255 | .accessfn = aa64_cacheop_poc_access }, | |
7256 | { .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64, | |
7257 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5, | |
7258 | .type = ARM_CP_NOP, .access = PL0_W, | |
7259 | .accessfn = aa64_cacheop_poc_access }, | |
7260 | { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64, | |
7261 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3, | |
7262 | .type = ARM_CP_NOP, .access = PL0_W, | |
7263 | .accessfn = aa64_cacheop_poc_access }, | |
7264 | { .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64, | |
7265 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5, | |
7266 | .type = ARM_CP_NOP, .access = PL0_W, | |
7267 | .accessfn = aa64_cacheop_poc_access }, | |
7268 | { .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64, | |
7269 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3, | |
7270 | .type = ARM_CP_NOP, .access = PL0_W, | |
7271 | .accessfn = aa64_cacheop_poc_access }, | |
7272 | { .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64, | |
7273 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5, | |
7274 | .type = ARM_CP_NOP, .access = PL0_W, | |
7275 | .accessfn = aa64_cacheop_poc_access }, | |
7276 | { .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64, | |
7277 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3, | |
7278 | .type = ARM_CP_NOP, .access = PL0_W, | |
7279 | .accessfn = aa64_cacheop_poc_access }, | |
7280 | { .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64, | |
7281 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, | |
7282 | .type = ARM_CP_NOP, .access = PL0_W, | |
7283 | .accessfn = aa64_cacheop_poc_access }, | |
eb821168 RH |
7284 | { .name = "DC_GVA", .state = ARM_CP_STATE_AA64, |
7285 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3, | |
7286 | .access = PL0_W, .type = ARM_CP_DC_GVA, | |
7287 | #ifndef CONFIG_USER_ONLY | |
7288 | /* Avoid overhead of an access check that always passes in user-mode */ | |
7289 | .accessfn = aa64_zva_access, | |
7290 | #endif | |
7291 | }, | |
7292 | { .name = "DC_GZVA", .state = ARM_CP_STATE_AA64, | |
7293 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 4, | |
7294 | .access = PL0_W, .type = ARM_CP_DC_GZVA, | |
7295 | #ifndef CONFIG_USER_ONLY | |
7296 | /* Avoid overhead of an access check that always passes in user-mode */ | |
7297 | .accessfn = aa64_zva_access, | |
7298 | #endif | |
7299 | }, | |
5463df16 RH |
7300 | REGINFO_SENTINEL |
7301 | }; | |
7302 | ||
967aa94f RH |
7303 | #endif |
7304 | ||
cb570bd3 RH |
7305 | static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, |
7306 | bool isread) | |
7307 | { | |
7308 | int el = arm_current_el(env); | |
7309 | ||
7310 | if (el == 0) { | |
7311 | uint64_t sctlr = arm_sctlr(env, el); | |
7312 | if (!(sctlr & SCTLR_EnRCTX)) { | |
7313 | return CP_ACCESS_TRAP; | |
7314 | } | |
7315 | } else if (el == 1) { | |
7316 | uint64_t hcr = arm_hcr_el2_eff(env); | |
7317 | if (hcr & HCR_NV) { | |
7318 | return CP_ACCESS_TRAP_EL2; | |
7319 | } | |
7320 | } | |
7321 | return CP_ACCESS_OK; | |
7322 | } | |
7323 | ||
7324 | static const ARMCPRegInfo predinv_reginfo[] = { | |
7325 | { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64, | |
7326 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4, | |
7327 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
7328 | { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64, | |
7329 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5, | |
7330 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
7331 | { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64, | |
7332 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7, | |
7333 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
7334 | /* | |
7335 | * Note the AArch32 opcodes have a different OPC1. | |
7336 | */ | |
7337 | { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32, | |
7338 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4, | |
7339 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
7340 | { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32, | |
7341 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5, | |
7342 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
7343 | { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32, | |
7344 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7, | |
7345 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
7346 | REGINFO_SENTINEL | |
7347 | }; | |
7348 | ||
957e6155 PM |
7349 | static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri) |
7350 | { | |
7351 | /* Read the high 32 bits of the current CCSIDR */ | |
7352 | return extract64(ccsidr_read(env, ri), 32, 32); | |
7353 | } | |
7354 | ||
7355 | static const ARMCPRegInfo ccsidr2_reginfo[] = { | |
7356 | { .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH, | |
7357 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2, | |
7358 | .access = PL1_R, | |
7359 | .accessfn = access_aa64_tid2, | |
7360 | .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW }, | |
7361 | REGINFO_SENTINEL | |
7362 | }; | |
7363 | ||
6a4ef4e5 MZ |
7364 | static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri, |
7365 | bool isread) | |
7366 | { | |
7367 | if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) { | |
7368 | return CP_ACCESS_TRAP_EL2; | |
7369 | } | |
7370 | ||
7371 | return CP_ACCESS_OK; | |
7372 | } | |
7373 | ||
7374 | static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri, | |
7375 | bool isread) | |
7376 | { | |
7377 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
7378 | return access_aa64_tid3(env, ri, isread); | |
7379 | } | |
7380 | ||
7381 | return CP_ACCESS_OK; | |
7382 | } | |
7383 | ||
f96f3d5f MZ |
7384 | static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri, |
7385 | bool isread) | |
7386 | { | |
7387 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID0)) { | |
7388 | return CP_ACCESS_TRAP_EL2; | |
7389 | } | |
7390 | ||
7391 | return CP_ACCESS_OK; | |
7392 | } | |
7393 | ||
8e228c9e PM |
7394 | static CPAccessResult access_joscr_jmcr(CPUARMState *env, |
7395 | const ARMCPRegInfo *ri, bool isread) | |
7396 | { | |
7397 | /* | |
7398 | * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only | |
7399 | * in v7A, not in v8A. | |
7400 | */ | |
7401 | if (!arm_feature(env, ARM_FEATURE_V8) && | |
7402 | arm_current_el(env) < 2 && !arm_is_secure_below_el3(env) && | |
7403 | (env->cp15.hstr_el2 & HSTR_TJDBX)) { | |
7404 | return CP_ACCESS_TRAP_EL2; | |
7405 | } | |
7406 | return CP_ACCESS_OK; | |
7407 | } | |
7408 | ||
f96f3d5f MZ |
7409 | static const ARMCPRegInfo jazelle_regs[] = { |
7410 | { .name = "JIDR", | |
7411 | .cp = 14, .crn = 0, .crm = 0, .opc1 = 7, .opc2 = 0, | |
7412 | .access = PL1_R, .accessfn = access_jazelle, | |
7413 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
7414 | { .name = "JOSCR", | |
7415 | .cp = 14, .crn = 1, .crm = 0, .opc1 = 7, .opc2 = 0, | |
8e228c9e | 7416 | .accessfn = access_joscr_jmcr, |
f96f3d5f MZ |
7417 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
7418 | { .name = "JMCR", | |
7419 | .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0, | |
8e228c9e | 7420 | .accessfn = access_joscr_jmcr, |
f96f3d5f MZ |
7421 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
7422 | REGINFO_SENTINEL | |
7423 | }; | |
7424 | ||
e2a1a461 RH |
7425 | static const ARMCPRegInfo vhe_reginfo[] = { |
7426 | { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, | |
7427 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, | |
7428 | .access = PL2_RW, | |
7429 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) }, | |
ed30da8e RH |
7430 | { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, |
7431 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, | |
7432 | .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, | |
7433 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) }, | |
8c94b071 RH |
7434 | #ifndef CONFIG_USER_ONLY |
7435 | { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64, | |
7436 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 2, | |
7437 | .fieldoffset = | |
7438 | offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval), | |
7439 | .type = ARM_CP_IO, .access = PL2_RW, | |
7440 | .writefn = gt_hv_cval_write, .raw_writefn = raw_write }, | |
7441 | { .name = "CNTHV_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
7442 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 0, | |
7443 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, | |
7444 | .resetfn = gt_hv_timer_reset, | |
7445 | .readfn = gt_hv_tval_read, .writefn = gt_hv_tval_write }, | |
7446 | { .name = "CNTHV_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
7447 | .type = ARM_CP_IO, | |
7448 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 1, | |
7449 | .access = PL2_RW, | |
7450 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].ctl), | |
7451 | .writefn = gt_hv_ctl_write, .raw_writefn = raw_write }, | |
bb5972e4 RH |
7452 | { .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64, |
7453 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1, | |
7454 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
7455 | .access = PL2_RW, .accessfn = e2h_access, | |
7456 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), | |
7457 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write }, | |
7458 | { .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64, | |
7459 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1, | |
7460 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
7461 | .access = PL2_RW, .accessfn = e2h_access, | |
7462 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), | |
7463 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write }, | |
7464 | { .name = "CNTP_TVAL_EL02", .state = ARM_CP_STATE_AA64, | |
7465 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 0, | |
7466 | .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, | |
7467 | .access = PL2_RW, .accessfn = e2h_access, | |
7468 | .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write }, | |
7469 | { .name = "CNTV_TVAL_EL02", .state = ARM_CP_STATE_AA64, | |
7470 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 0, | |
7471 | .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, | |
7472 | .access = PL2_RW, .accessfn = e2h_access, | |
7473 | .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write }, | |
7474 | { .name = "CNTP_CVAL_EL02", .state = ARM_CP_STATE_AA64, | |
7475 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 2, | |
7476 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
7477 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
7478 | .access = PL2_RW, .accessfn = e2h_access, | |
7479 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write }, | |
7480 | { .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64, | |
7481 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2, | |
7482 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
7483 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
7484 | .access = PL2_RW, .accessfn = e2h_access, | |
7485 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write }, | |
8c94b071 | 7486 | #endif |
e2a1a461 RH |
7487 | REGINFO_SENTINEL |
7488 | }; | |
7489 | ||
04b07d29 RH |
7490 | #ifndef CONFIG_USER_ONLY |
7491 | static const ARMCPRegInfo ats1e1_reginfo[] = { | |
7492 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
7493 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, | |
7494 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
7495 | .writefn = ats_write64 }, | |
7496 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, | |
7497 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, | |
7498 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
7499 | .writefn = ats_write64 }, | |
7500 | REGINFO_SENTINEL | |
7501 | }; | |
7502 | ||
7503 | static const ARMCPRegInfo ats1cp_reginfo[] = { | |
7504 | { .name = "ATS1CPRP", | |
7505 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, | |
7506 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
7507 | .writefn = ats_write }, | |
7508 | { .name = "ATS1CPWP", | |
7509 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, | |
7510 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
7511 | .writefn = ats_write }, | |
7512 | REGINFO_SENTINEL | |
7513 | }; | |
7514 | #endif | |
7515 | ||
f6287c24 PM |
7516 | /* |
7517 | * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and | |
7518 | * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field | |
7519 | * is non-zero, which is never for ARMv7, optionally in ARMv8 | |
7520 | * and mandatorily for ARMv8.2 and up. | |
7521 | * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's | |
7522 | * implementation is RAZ/WI we can ignore this detail, as we | |
7523 | * do for ACTLR. | |
7524 | */ | |
7525 | static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = { | |
7526 | { .name = "ACTLR2", .state = ARM_CP_STATE_AA32, | |
7527 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 3, | |
99602377 RH |
7528 | .access = PL1_RW, .accessfn = access_tacr, |
7529 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
f6287c24 PM |
7530 | { .name = "HACTLR2", .state = ARM_CP_STATE_AA32, |
7531 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3, | |
7532 | .access = PL2_RW, .type = ARM_CP_CONST, | |
7533 | .resetvalue = 0 }, | |
7534 | REGINFO_SENTINEL | |
7535 | }; | |
7536 | ||
2ceb98c0 PM |
7537 | void register_cp_regs_for_features(ARMCPU *cpu) |
7538 | { | |
7539 | /* Register all the coprocessor registers based on feature bits */ | |
7540 | CPUARMState *env = &cpu->env; | |
7541 | if (arm_feature(env, ARM_FEATURE_M)) { | |
7542 | /* M profile has no coprocessor registers */ | |
7543 | return; | |
7544 | } | |
7545 | ||
e9aa6c21 | 7546 | define_arm_cp_regs(cpu, cp_reginfo); |
9449fdf6 PM |
7547 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
7548 | /* Must go early as it is full of wildcards that may be | |
7549 | * overridden by later definitions. | |
7550 | */ | |
7551 | define_arm_cp_regs(cpu, not_v8_cp_reginfo); | |
7552 | } | |
7553 | ||
7d57f408 | 7554 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8515a092 PM |
7555 | /* The ID registers all have impdef reset values */ |
7556 | ARMCPRegInfo v6_idregs[] = { | |
0ff644a7 PM |
7557 | { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, |
7558 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
7559 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7560 | .accessfn = access_aa32_tid3, |
8a130a7b | 7561 | .resetvalue = cpu->isar.id_pfr0 }, |
96a8b92e PM |
7562 | /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know |
7563 | * the value of the GIC field until after we define these regs. | |
7564 | */ | |
0ff644a7 PM |
7565 | { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, |
7566 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | |
96a8b92e | 7567 | .access = PL1_R, .type = ARM_CP_NO_RAW, |
6a4ef4e5 | 7568 | .accessfn = access_aa32_tid3, |
96a8b92e PM |
7569 | .readfn = id_pfr1_read, |
7570 | .writefn = arm_cp_write_ignore }, | |
0ff644a7 PM |
7571 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, |
7572 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | |
7573 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7574 | .accessfn = access_aa32_tid3, |
a6179538 | 7575 | .resetvalue = cpu->isar.id_dfr0 }, |
0ff644a7 PM |
7576 | { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, |
7577 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, | |
7578 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7579 | .accessfn = access_aa32_tid3, |
8515a092 | 7580 | .resetvalue = cpu->id_afr0 }, |
0ff644a7 PM |
7581 | { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, |
7582 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, | |
7583 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7584 | .accessfn = access_aa32_tid3, |
10054016 | 7585 | .resetvalue = cpu->isar.id_mmfr0 }, |
0ff644a7 PM |
7586 | { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, |
7587 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, | |
7588 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7589 | .accessfn = access_aa32_tid3, |
10054016 | 7590 | .resetvalue = cpu->isar.id_mmfr1 }, |
0ff644a7 PM |
7591 | { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, |
7592 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, | |
7593 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7594 | .accessfn = access_aa32_tid3, |
10054016 | 7595 | .resetvalue = cpu->isar.id_mmfr2 }, |
0ff644a7 PM |
7596 | { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, |
7597 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, | |
7598 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7599 | .accessfn = access_aa32_tid3, |
10054016 | 7600 | .resetvalue = cpu->isar.id_mmfr3 }, |
0ff644a7 PM |
7601 | { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, |
7602 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
7603 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7604 | .accessfn = access_aa32_tid3, |
47576b94 | 7605 | .resetvalue = cpu->isar.id_isar0 }, |
0ff644a7 PM |
7606 | { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, |
7607 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, | |
7608 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7609 | .accessfn = access_aa32_tid3, |
47576b94 | 7610 | .resetvalue = cpu->isar.id_isar1 }, |
0ff644a7 PM |
7611 | { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, |
7612 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
7613 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7614 | .accessfn = access_aa32_tid3, |
47576b94 | 7615 | .resetvalue = cpu->isar.id_isar2 }, |
0ff644a7 PM |
7616 | { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, |
7617 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, | |
7618 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7619 | .accessfn = access_aa32_tid3, |
47576b94 | 7620 | .resetvalue = cpu->isar.id_isar3 }, |
0ff644a7 PM |
7621 | { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, |
7622 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, | |
7623 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7624 | .accessfn = access_aa32_tid3, |
47576b94 | 7625 | .resetvalue = cpu->isar.id_isar4 }, |
0ff644a7 PM |
7626 | { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, |
7627 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, | |
7628 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7629 | .accessfn = access_aa32_tid3, |
47576b94 | 7630 | .resetvalue = cpu->isar.id_isar5 }, |
e20d84c1 PM |
7631 | { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, |
7632 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, | |
7633 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7634 | .accessfn = access_aa32_tid3, |
10054016 | 7635 | .resetvalue = cpu->isar.id_mmfr4 }, |
802abf40 | 7636 | { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
7637 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, |
7638 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7639 | .accessfn = access_aa32_tid3, |
47576b94 | 7640 | .resetvalue = cpu->isar.id_isar6 }, |
8515a092 PM |
7641 | REGINFO_SENTINEL |
7642 | }; | |
7643 | define_arm_cp_regs(cpu, v6_idregs); | |
7d57f408 PM |
7644 | define_arm_cp_regs(cpu, v6_cp_reginfo); |
7645 | } else { | |
7646 | define_arm_cp_regs(cpu, not_v6_cp_reginfo); | |
7647 | } | |
4d31c596 PM |
7648 | if (arm_feature(env, ARM_FEATURE_V6K)) { |
7649 | define_arm_cp_regs(cpu, v6k_cp_reginfo); | |
7650 | } | |
5e5cf9e3 | 7651 | if (arm_feature(env, ARM_FEATURE_V7MP) && |
452a0955 | 7652 | !arm_feature(env, ARM_FEATURE_PMSA)) { |
995939a6 PM |
7653 | define_arm_cp_regs(cpu, v7mp_cp_reginfo); |
7654 | } | |
327dd510 AL |
7655 | if (arm_feature(env, ARM_FEATURE_V7VE)) { |
7656 | define_arm_cp_regs(cpu, pmovsset_cp_reginfo); | |
7657 | } | |
e9aa6c21 | 7658 | if (arm_feature(env, ARM_FEATURE_V7)) { |
776d4e5c | 7659 | ARMCPRegInfo clidr = { |
7da845b0 PM |
7660 | .name = "CLIDR", .state = ARM_CP_STATE_BOTH, |
7661 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | |
630fcd4d MZ |
7662 | .access = PL1_R, .type = ARM_CP_CONST, |
7663 | .accessfn = access_aa64_tid2, | |
7664 | .resetvalue = cpu->clidr | |
776d4e5c | 7665 | }; |
776d4e5c | 7666 | define_one_arm_cp_reg(cpu, &clidr); |
e9aa6c21 | 7667 | define_arm_cp_regs(cpu, v7_cp_reginfo); |
50300698 | 7668 | define_debug_regs(cpu); |
24183fb6 | 7669 | define_pmu_regs(cpu); |
7d57f408 PM |
7670 | } else { |
7671 | define_arm_cp_regs(cpu, not_v7_cp_reginfo); | |
e9aa6c21 | 7672 | } |
b0d2b7d0 | 7673 | if (arm_feature(env, ARM_FEATURE_V8)) { |
e20d84c1 PM |
7674 | /* AArch64 ID registers, which all have impdef reset values. |
7675 | * Note that within the ID register ranges the unused slots | |
7676 | * must all RAZ, not UNDEF; future architecture versions may | |
7677 | * define new registers here. | |
7678 | */ | |
e60cef86 | 7679 | ARMCPRegInfo v8_idregs[] = { |
976b99b6 AB |
7680 | /* |
7681 | * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system | |
7682 | * emulation because we don't know the right value for the | |
7683 | * GIC field until after we define these regs. | |
96a8b92e | 7684 | */ |
e60cef86 PM |
7685 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, |
7686 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | |
976b99b6 AB |
7687 | .access = PL1_R, |
7688 | #ifdef CONFIG_USER_ONLY | |
7689 | .type = ARM_CP_CONST, | |
7690 | .resetvalue = cpu->isar.id_aa64pfr0 | |
7691 | #else | |
7692 | .type = ARM_CP_NO_RAW, | |
6a4ef4e5 | 7693 | .accessfn = access_aa64_tid3, |
96a8b92e | 7694 | .readfn = id_aa64pfr0_read, |
976b99b6 AB |
7695 | .writefn = arm_cp_write_ignore |
7696 | #endif | |
7697 | }, | |
e60cef86 PM |
7698 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, |
7699 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | |
7700 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7701 | .accessfn = access_aa64_tid3, |
47576b94 | 7702 | .resetvalue = cpu->isar.id_aa64pfr1}, |
e20d84c1 PM |
7703 | { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7704 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, | |
7705 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7706 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7707 | .resetvalue = 0 }, |
7708 | { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7709 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, | |
7710 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7711 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7712 | .resetvalue = 0 }, |
9516d772 | 7713 | { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
7714 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, |
7715 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7716 | .accessfn = access_aa64_tid3, |
2dc10fa2 | 7717 | .resetvalue = cpu->isar.id_aa64zfr0 }, |
e20d84c1 PM |
7718 | { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7719 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, | |
7720 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7721 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7722 | .resetvalue = 0 }, |
7723 | { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7724 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, | |
7725 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7726 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7727 | .resetvalue = 0 }, |
7728 | { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7729 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, | |
7730 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7731 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7732 | .resetvalue = 0 }, |
e60cef86 PM |
7733 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, |
7734 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | |
7735 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7736 | .accessfn = access_aa64_tid3, |
2a609df8 | 7737 | .resetvalue = cpu->isar.id_aa64dfr0 }, |
e60cef86 PM |
7738 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, |
7739 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | |
7740 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7741 | .accessfn = access_aa64_tid3, |
2a609df8 | 7742 | .resetvalue = cpu->isar.id_aa64dfr1 }, |
e20d84c1 PM |
7743 | { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7744 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, | |
7745 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7746 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7747 | .resetvalue = 0 }, |
7748 | { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7749 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, | |
7750 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7751 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7752 | .resetvalue = 0 }, |
e60cef86 PM |
7753 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, |
7754 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | |
7755 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7756 | .accessfn = access_aa64_tid3, |
e60cef86 PM |
7757 | .resetvalue = cpu->id_aa64afr0 }, |
7758 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | |
7759 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | |
7760 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7761 | .accessfn = access_aa64_tid3, |
e60cef86 | 7762 | .resetvalue = cpu->id_aa64afr1 }, |
e20d84c1 PM |
7763 | { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7764 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, | |
7765 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7766 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7767 | .resetvalue = 0 }, |
7768 | { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7769 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, | |
7770 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7771 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7772 | .resetvalue = 0 }, |
e60cef86 PM |
7773 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, |
7774 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | |
7775 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7776 | .accessfn = access_aa64_tid3, |
47576b94 | 7777 | .resetvalue = cpu->isar.id_aa64isar0 }, |
e60cef86 PM |
7778 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, |
7779 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | |
7780 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7781 | .accessfn = access_aa64_tid3, |
47576b94 | 7782 | .resetvalue = cpu->isar.id_aa64isar1 }, |
e20d84c1 PM |
7783 | { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7784 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, | |
7785 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7786 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7787 | .resetvalue = 0 }, |
7788 | { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7789 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, | |
7790 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7791 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7792 | .resetvalue = 0 }, |
7793 | { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7794 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, | |
7795 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7796 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7797 | .resetvalue = 0 }, |
7798 | { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7799 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, | |
7800 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7801 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7802 | .resetvalue = 0 }, |
7803 | { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7804 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, | |
7805 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7806 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7807 | .resetvalue = 0 }, |
7808 | { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7809 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, | |
7810 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7811 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7812 | .resetvalue = 0 }, |
e60cef86 PM |
7813 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, |
7814 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
7815 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7816 | .accessfn = access_aa64_tid3, |
3dc91ddb | 7817 | .resetvalue = cpu->isar.id_aa64mmfr0 }, |
e60cef86 PM |
7818 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, |
7819 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | |
7820 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7821 | .accessfn = access_aa64_tid3, |
3dc91ddb | 7822 | .resetvalue = cpu->isar.id_aa64mmfr1 }, |
64761e10 | 7823 | { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
7824 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, |
7825 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7826 | .accessfn = access_aa64_tid3, |
64761e10 | 7827 | .resetvalue = cpu->isar.id_aa64mmfr2 }, |
e20d84c1 PM |
7828 | { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7829 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, | |
7830 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7831 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7832 | .resetvalue = 0 }, |
7833 | { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7834 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, | |
7835 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7836 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7837 | .resetvalue = 0 }, |
7838 | { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7839 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, | |
7840 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7841 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7842 | .resetvalue = 0 }, |
7843 | { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7844 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, | |
7845 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7846 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7847 | .resetvalue = 0 }, |
7848 | { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7849 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, | |
7850 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7851 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7852 | .resetvalue = 0 }, |
a50c0f51 PM |
7853 | { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, |
7854 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
7855 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7856 | .accessfn = access_aa64_tid3, |
47576b94 | 7857 | .resetvalue = cpu->isar.mvfr0 }, |
a50c0f51 PM |
7858 | { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, |
7859 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
7860 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7861 | .accessfn = access_aa64_tid3, |
47576b94 | 7862 | .resetvalue = cpu->isar.mvfr1 }, |
a50c0f51 PM |
7863 | { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, |
7864 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
7865 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7866 | .accessfn = access_aa64_tid3, |
47576b94 | 7867 | .resetvalue = cpu->isar.mvfr2 }, |
e20d84c1 PM |
7868 | { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7869 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, | |
7870 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7871 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7872 | .resetvalue = 0 }, |
1d51bc96 | 7873 | { .name = "ID_PFR2", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
7874 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, |
7875 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7876 | .accessfn = access_aa64_tid3, |
1d51bc96 | 7877 | .resetvalue = cpu->isar.id_pfr2 }, |
e20d84c1 PM |
7878 | { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7879 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, | |
7880 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7881 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7882 | .resetvalue = 0 }, |
7883 | { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7884 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, | |
7885 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7886 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7887 | .resetvalue = 0 }, |
7888 | { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7889 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, | |
7890 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7891 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7892 | .resetvalue = 0 }, |
4054bfa9 AF |
7893 | { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, |
7894 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, | |
7895 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
cad86737 | 7896 | .resetvalue = extract64(cpu->pmceid0, 0, 32) }, |
4054bfa9 AF |
7897 | { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, |
7898 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, | |
7899 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
7900 | .resetvalue = cpu->pmceid0 }, | |
7901 | { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, | |
7902 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, | |
7903 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
cad86737 | 7904 | .resetvalue = extract64(cpu->pmceid1, 0, 32) }, |
4054bfa9 AF |
7905 | { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, |
7906 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, | |
7907 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
7908 | .resetvalue = cpu->pmceid1 }, | |
e60cef86 PM |
7909 | REGINFO_SENTINEL |
7910 | }; | |
6c5c0fec AB |
7911 | #ifdef CONFIG_USER_ONLY |
7912 | ARMCPRegUserSpaceInfo v8_user_idregs[] = { | |
7913 | { .name = "ID_AA64PFR0_EL1", | |
7914 | .exported_bits = 0x000f000f00ff0000, | |
7915 | .fixed_bits = 0x0000000000000011 }, | |
7916 | { .name = "ID_AA64PFR1_EL1", | |
7917 | .exported_bits = 0x00000000000000f0 }, | |
d040242e AB |
7918 | { .name = "ID_AA64PFR*_EL1_RESERVED", |
7919 | .is_glob = true }, | |
6c5c0fec AB |
7920 | { .name = "ID_AA64ZFR0_EL1" }, |
7921 | { .name = "ID_AA64MMFR0_EL1", | |
7922 | .fixed_bits = 0x00000000ff000000 }, | |
7923 | { .name = "ID_AA64MMFR1_EL1" }, | |
d040242e AB |
7924 | { .name = "ID_AA64MMFR*_EL1_RESERVED", |
7925 | .is_glob = true }, | |
6c5c0fec AB |
7926 | { .name = "ID_AA64DFR0_EL1", |
7927 | .fixed_bits = 0x0000000000000006 }, | |
7928 | { .name = "ID_AA64DFR1_EL1" }, | |
d040242e AB |
7929 | { .name = "ID_AA64DFR*_EL1_RESERVED", |
7930 | .is_glob = true }, | |
7931 | { .name = "ID_AA64AFR*", | |
7932 | .is_glob = true }, | |
6c5c0fec AB |
7933 | { .name = "ID_AA64ISAR0_EL1", |
7934 | .exported_bits = 0x00fffffff0fffff0 }, | |
7935 | { .name = "ID_AA64ISAR1_EL1", | |
7936 | .exported_bits = 0x000000f0ffffffff }, | |
d040242e AB |
7937 | { .name = "ID_AA64ISAR*_EL1_RESERVED", |
7938 | .is_glob = true }, | |
6c5c0fec AB |
7939 | REGUSERINFO_SENTINEL |
7940 | }; | |
7941 | modify_arm_cp_regs(v8_idregs, v8_user_idregs); | |
7942 | #endif | |
be8e8128 GB |
7943 | /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ |
7944 | if (!arm_feature(env, ARM_FEATURE_EL3) && | |
7945 | !arm_feature(env, ARM_FEATURE_EL2)) { | |
7946 | ARMCPRegInfo rvbar = { | |
7947 | .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, | |
7948 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, | |
7949 | .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar | |
7950 | }; | |
7951 | define_one_arm_cp_reg(cpu, &rvbar); | |
7952 | } | |
e60cef86 | 7953 | define_arm_cp_regs(cpu, v8_idregs); |
b0d2b7d0 PM |
7954 | define_arm_cp_regs(cpu, v8_cp_reginfo); |
7955 | } | |
3b685ba7 | 7956 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
f0d574d6 | 7957 | uint64_t vmpidr_def = mpidr_read_val(env); |
731de9e6 EI |
7958 | ARMCPRegInfo vpidr_regs[] = { |
7959 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | |
7960 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
7961 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
36476562 PM |
7962 | .resetvalue = cpu->midr, .type = ARM_CP_ALIAS, |
7963 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) }, | |
731de9e6 EI |
7964 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, |
7965 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
7966 | .access = PL2_RW, .resetvalue = cpu->midr, | |
7967 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
f0d574d6 EI |
7968 | { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, |
7969 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
7970 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
36476562 PM |
7971 | .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS, |
7972 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) }, | |
f0d574d6 EI |
7973 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, |
7974 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
7975 | .access = PL2_RW, | |
7976 | .resetvalue = vmpidr_def, | |
7977 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | |
731de9e6 EI |
7978 | REGINFO_SENTINEL |
7979 | }; | |
7980 | define_arm_cp_regs(cpu, vpidr_regs); | |
4771cd01 | 7981 | define_arm_cp_regs(cpu, el2_cp_reginfo); |
ce4afed8 PM |
7982 | if (arm_feature(env, ARM_FEATURE_V8)) { |
7983 | define_arm_cp_regs(cpu, el2_v8_cp_reginfo); | |
7984 | } | |
e9152ee9 RDC |
7985 | if (cpu_isar_feature(aa64_sel2, cpu)) { |
7986 | define_arm_cp_regs(cpu, el2_sec_cp_reginfo); | |
7987 | } | |
be8e8128 GB |
7988 | /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ |
7989 | if (!arm_feature(env, ARM_FEATURE_EL3)) { | |
7990 | ARMCPRegInfo rvbar = { | |
7991 | .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, | |
7992 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, | |
7993 | .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar | |
7994 | }; | |
7995 | define_one_arm_cp_reg(cpu, &rvbar); | |
7996 | } | |
d42e3c26 EI |
7997 | } else { |
7998 | /* If EL2 is missing but higher ELs are enabled, we need to | |
7999 | * register the no_el2 reginfos. | |
8000 | */ | |
8001 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
f0d574d6 EI |
8002 | /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value |
8003 | * of MIDR_EL1 and MPIDR_EL1. | |
731de9e6 EI |
8004 | */ |
8005 | ARMCPRegInfo vpidr_regs[] = { | |
8006 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH, | |
8007 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
93dd1e61 | 8008 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
731de9e6 EI |
8009 | .type = ARM_CP_CONST, .resetvalue = cpu->midr, |
8010 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
f0d574d6 EI |
8011 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
8012 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
93dd1e61 | 8013 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
f0d574d6 EI |
8014 | .type = ARM_CP_NO_RAW, |
8015 | .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, | |
731de9e6 EI |
8016 | REGINFO_SENTINEL |
8017 | }; | |
8018 | define_arm_cp_regs(cpu, vpidr_regs); | |
4771cd01 | 8019 | define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); |
ce4afed8 PM |
8020 | if (arm_feature(env, ARM_FEATURE_V8)) { |
8021 | define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo); | |
8022 | } | |
d42e3c26 | 8023 | } |
3b685ba7 | 8024 | } |
81547d66 | 8025 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0f1a3b24 | 8026 | define_arm_cp_regs(cpu, el3_cp_reginfo); |
e24fdd23 PM |
8027 | ARMCPRegInfo el3_regs[] = { |
8028 | { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, | |
8029 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, | |
8030 | .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, | |
8031 | { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, | |
8032 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, | |
8033 | .access = PL3_RW, | |
8034 | .raw_writefn = raw_write, .writefn = sctlr_write, | |
8035 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), | |
8036 | .resetvalue = cpu->reset_sctlr }, | |
8037 | REGINFO_SENTINEL | |
be8e8128 | 8038 | }; |
e24fdd23 PM |
8039 | |
8040 | define_arm_cp_regs(cpu, el3_regs); | |
81547d66 | 8041 | } |
2f027fc5 PM |
8042 | /* The behaviour of NSACR is sufficiently various that we don't |
8043 | * try to describe it in a single reginfo: | |
8044 | * if EL3 is 64 bit, then trap to EL3 from S EL1, | |
8045 | * reads as constant 0xc00 from NS EL1 and NS EL2 | |
8046 | * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 | |
8047 | * if v7 without EL3, register doesn't exist | |
8048 | * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 | |
8049 | */ | |
8050 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
8051 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
8052 | ARMCPRegInfo nsacr = { | |
8053 | .name = "NSACR", .type = ARM_CP_CONST, | |
8054 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
8055 | .access = PL1_RW, .accessfn = nsacr_access, | |
8056 | .resetvalue = 0xc00 | |
8057 | }; | |
8058 | define_one_arm_cp_reg(cpu, &nsacr); | |
8059 | } else { | |
8060 | ARMCPRegInfo nsacr = { | |
8061 | .name = "NSACR", | |
8062 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
8063 | .access = PL3_RW | PL1_R, | |
8064 | .resetvalue = 0, | |
8065 | .fieldoffset = offsetof(CPUARMState, cp15.nsacr) | |
8066 | }; | |
8067 | define_one_arm_cp_reg(cpu, &nsacr); | |
8068 | } | |
8069 | } else { | |
8070 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
8071 | ARMCPRegInfo nsacr = { | |
8072 | .name = "NSACR", .type = ARM_CP_CONST, | |
8073 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
8074 | .access = PL1_R, | |
8075 | .resetvalue = 0xc00 | |
8076 | }; | |
8077 | define_one_arm_cp_reg(cpu, &nsacr); | |
8078 | } | |
8079 | } | |
8080 | ||
452a0955 | 8081 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
6cb0b013 PC |
8082 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8083 | /* PMSAv6 not implemented */ | |
8084 | assert(arm_feature(env, ARM_FEATURE_V7)); | |
8085 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); | |
8086 | define_arm_cp_regs(cpu, pmsav7_cp_reginfo); | |
8087 | } else { | |
8088 | define_arm_cp_regs(cpu, pmsav5_cp_reginfo); | |
8089 | } | |
18032bec | 8090 | } else { |
8e5d75c9 | 8091 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); |
18032bec | 8092 | define_arm_cp_regs(cpu, vmsa_cp_reginfo); |
4036b7d1 PM |
8093 | /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */ |
8094 | if (cpu_isar_feature(aa32_hpd, cpu)) { | |
ab638a32 RH |
8095 | define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); |
8096 | } | |
18032bec | 8097 | } |
c326b979 PM |
8098 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
8099 | define_arm_cp_regs(cpu, t2ee_cp_reginfo); | |
8100 | } | |
6cc7a3ae PM |
8101 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
8102 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); | |
8103 | } | |
4a501606 PM |
8104 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
8105 | define_arm_cp_regs(cpu, vapa_cp_reginfo); | |
8106 | } | |
c4804214 PM |
8107 | if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { |
8108 | define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); | |
8109 | } | |
8110 | if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { | |
8111 | define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); | |
8112 | } | |
8113 | if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { | |
8114 | define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); | |
8115 | } | |
18032bec PM |
8116 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
8117 | define_arm_cp_regs(cpu, omap_cp_reginfo); | |
8118 | } | |
34f90529 PM |
8119 | if (arm_feature(env, ARM_FEATURE_STRONGARM)) { |
8120 | define_arm_cp_regs(cpu, strongarm_cp_reginfo); | |
8121 | } | |
1047b9d7 PM |
8122 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
8123 | define_arm_cp_regs(cpu, xscale_cp_reginfo); | |
8124 | } | |
8125 | if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { | |
8126 | define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); | |
8127 | } | |
7ac681cf PM |
8128 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8129 | define_arm_cp_regs(cpu, lpae_cp_reginfo); | |
8130 | } | |
873b73c0 | 8131 | if (cpu_isar_feature(aa32_jazelle, cpu)) { |
f96f3d5f MZ |
8132 | define_arm_cp_regs(cpu, jazelle_regs); |
8133 | } | |
7884849c PM |
8134 | /* Slightly awkwardly, the OMAP and StrongARM cores need all of |
8135 | * cp15 crn=0 to be writes-ignored, whereas for other cores they should | |
8136 | * be read-only (ie write causes UNDEF exception). | |
8137 | */ | |
8138 | { | |
00a29f3d PM |
8139 | ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { |
8140 | /* Pre-v8 MIDR space. | |
8141 | * Note that the MIDR isn't a simple constant register because | |
7884849c PM |
8142 | * of the TI925 behaviour where writes to another register can |
8143 | * cause the MIDR value to change. | |
97ce8d61 PC |
8144 | * |
8145 | * Unimplemented registers in the c15 0 0 0 space default to | |
8146 | * MIDR. Define MIDR first as this entire space, then CTR, TCMTR | |
8147 | * and friends override accordingly. | |
7884849c PM |
8148 | */ |
8149 | { .name = "MIDR", | |
97ce8d61 | 8150 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, |
7884849c | 8151 | .access = PL1_R, .resetvalue = cpu->midr, |
d4e6df63 | 8152 | .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, |
731de9e6 | 8153 | .readfn = midr_read, |
97ce8d61 PC |
8154 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
8155 | .type = ARM_CP_OVERRIDE }, | |
7884849c PM |
8156 | /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ |
8157 | { .name = "DUMMY", | |
8158 | .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, | |
8159 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8160 | { .name = "DUMMY", | |
8161 | .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, | |
8162 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8163 | { .name = "DUMMY", | |
8164 | .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, | |
8165 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8166 | { .name = "DUMMY", | |
8167 | .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, | |
8168 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8169 | { .name = "DUMMY", | |
8170 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | |
8171 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8172 | REGINFO_SENTINEL | |
8173 | }; | |
00a29f3d | 8174 | ARMCPRegInfo id_v8_midr_cp_reginfo[] = { |
00a29f3d PM |
8175 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, |
8176 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, | |
731de9e6 EI |
8177 | .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, |
8178 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), | |
8179 | .readfn = midr_read }, | |
ac00c79f SF |
8180 | /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ |
8181 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
8182 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
8183 | .access = PL1_R, .resetvalue = cpu->midr }, | |
8184 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
8185 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, | |
8186 | .access = PL1_R, .resetvalue = cpu->midr }, | |
00a29f3d PM |
8187 | { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, |
8188 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, | |
93fbc983 MZ |
8189 | .access = PL1_R, |
8190 | .accessfn = access_aa64_tid1, | |
8191 | .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, | |
00a29f3d PM |
8192 | REGINFO_SENTINEL |
8193 | }; | |
8194 | ARMCPRegInfo id_cp_reginfo[] = { | |
8195 | /* These are common to v8 and pre-v8 */ | |
8196 | { .name = "CTR", | |
8197 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, | |
630fcd4d MZ |
8198 | .access = PL1_R, .accessfn = ctr_el0_access, |
8199 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
00a29f3d PM |
8200 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, |
8201 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, | |
8202 | .access = PL0_R, .accessfn = ctr_el0_access, | |
8203 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
8204 | /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ | |
8205 | { .name = "TCMTR", | |
8206 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, | |
93fbc983 MZ |
8207 | .access = PL1_R, |
8208 | .accessfn = access_aa32_tid1, | |
8209 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
00a29f3d PM |
8210 | REGINFO_SENTINEL |
8211 | }; | |
8085ce63 PC |
8212 | /* TLBTR is specific to VMSA */ |
8213 | ARMCPRegInfo id_tlbtr_reginfo = { | |
8214 | .name = "TLBTR", | |
8215 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, | |
93fbc983 MZ |
8216 | .access = PL1_R, |
8217 | .accessfn = access_aa32_tid1, | |
8218 | .type = ARM_CP_CONST, .resetvalue = 0, | |
8085ce63 | 8219 | }; |
3281af81 PC |
8220 | /* MPUIR is specific to PMSA V6+ */ |
8221 | ARMCPRegInfo id_mpuir_reginfo = { | |
8222 | .name = "MPUIR", | |
8223 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
8224 | .access = PL1_R, .type = ARM_CP_CONST, | |
8225 | .resetvalue = cpu->pmsav7_dregion << 8 | |
8226 | }; | |
7884849c PM |
8227 | ARMCPRegInfo crn0_wi_reginfo = { |
8228 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, | |
8229 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | |
8230 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | |
8231 | }; | |
6c5c0fec AB |
8232 | #ifdef CONFIG_USER_ONLY |
8233 | ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = { | |
8234 | { .name = "MIDR_EL1", | |
8235 | .exported_bits = 0x00000000ffffffff }, | |
8236 | { .name = "REVIDR_EL1" }, | |
8237 | REGUSERINFO_SENTINEL | |
8238 | }; | |
8239 | modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo); | |
8240 | #endif | |
7884849c PM |
8241 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || |
8242 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | |
8243 | ARMCPRegInfo *r; | |
8244 | /* Register the blanket "writes ignored" value first to cover the | |
a703eda1 PC |
8245 | * whole space. Then update the specific ID registers to allow write |
8246 | * access, so that they ignore writes rather than causing them to | |
8247 | * UNDEF. | |
7884849c PM |
8248 | */ |
8249 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | |
00a29f3d PM |
8250 | for (r = id_pre_v8_midr_cp_reginfo; |
8251 | r->type != ARM_CP_SENTINEL; r++) { | |
8252 | r->access = PL1_RW; | |
8253 | } | |
7884849c PM |
8254 | for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { |
8255 | r->access = PL1_RW; | |
7884849c | 8256 | } |
10006112 | 8257 | id_mpuir_reginfo.access = PL1_RW; |
3281af81 | 8258 | id_tlbtr_reginfo.access = PL1_RW; |
7884849c | 8259 | } |
00a29f3d PM |
8260 | if (arm_feature(env, ARM_FEATURE_V8)) { |
8261 | define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); | |
8262 | } else { | |
8263 | define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); | |
8264 | } | |
a703eda1 | 8265 | define_arm_cp_regs(cpu, id_cp_reginfo); |
452a0955 | 8266 | if (!arm_feature(env, ARM_FEATURE_PMSA)) { |
8085ce63 | 8267 | define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); |
3281af81 PC |
8268 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8269 | define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); | |
8085ce63 | 8270 | } |
7884849c PM |
8271 | } |
8272 | ||
97ce8d61 | 8273 | if (arm_feature(env, ARM_FEATURE_MPIDR)) { |
52264166 AB |
8274 | ARMCPRegInfo mpidr_cp_reginfo[] = { |
8275 | { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
8276 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | |
8277 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, | |
8278 | REGINFO_SENTINEL | |
8279 | }; | |
8280 | #ifdef CONFIG_USER_ONLY | |
8281 | ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = { | |
8282 | { .name = "MPIDR_EL1", | |
8283 | .fixed_bits = 0x0000000080000000 }, | |
8284 | REGUSERINFO_SENTINEL | |
8285 | }; | |
8286 | modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); | |
8287 | #endif | |
97ce8d61 PC |
8288 | define_arm_cp_regs(cpu, mpidr_cp_reginfo); |
8289 | } | |
8290 | ||
2771db27 | 8291 | if (arm_feature(env, ARM_FEATURE_AUXCR)) { |
834a6c69 PM |
8292 | ARMCPRegInfo auxcr_reginfo[] = { |
8293 | { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, | |
8294 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, | |
99602377 RH |
8295 | .access = PL1_RW, .accessfn = access_tacr, |
8296 | .type = ARM_CP_CONST, .resetvalue = cpu->reset_auxcr }, | |
834a6c69 PM |
8297 | { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, |
8298 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, | |
8299 | .access = PL2_RW, .type = ARM_CP_CONST, | |
8300 | .resetvalue = 0 }, | |
8301 | { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, | |
8302 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, | |
8303 | .access = PL3_RW, .type = ARM_CP_CONST, | |
8304 | .resetvalue = 0 }, | |
8305 | REGINFO_SENTINEL | |
2771db27 | 8306 | }; |
834a6c69 | 8307 | define_arm_cp_regs(cpu, auxcr_reginfo); |
f6287c24 PM |
8308 | if (cpu_isar_feature(aa32_ac2, cpu)) { |
8309 | define_arm_cp_regs(cpu, actlr2_hactlr2_reginfo); | |
0e0456ab | 8310 | } |
2771db27 PM |
8311 | } |
8312 | ||
d8ba780b | 8313 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
d56974af LM |
8314 | /* |
8315 | * CBAR is IMPDEF, but common on Arm Cortex-A implementations. | |
8316 | * There are two flavours: | |
8317 | * (1) older 32-bit only cores have a simple 32-bit CBAR | |
8318 | * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a | |
8319 | * 32-bit register visible to AArch32 at a different encoding | |
8320 | * to the "flavour 1" register and with the bits rearranged to | |
8321 | * be able to squash a 64-bit address into the 32-bit view. | |
8322 | * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but | |
8323 | * in future if we support AArch32-only configs of some of the | |
8324 | * AArch64 cores we might need to add a specific feature flag | |
8325 | * to indicate cores with "flavour 2" CBAR. | |
8326 | */ | |
f318cec6 PM |
8327 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
8328 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | |
8329 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | |
8330 | | extract64(cpu->reset_cbar, 32, 12); | |
8331 | ARMCPRegInfo cbar_reginfo[] = { | |
8332 | { .name = "CBAR", | |
8333 | .type = ARM_CP_CONST, | |
d56974af LM |
8334 | .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0, |
8335 | .access = PL1_R, .resetvalue = cbar32 }, | |
f318cec6 PM |
8336 | { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, |
8337 | .type = ARM_CP_CONST, | |
8338 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | |
d56974af | 8339 | .access = PL1_R, .resetvalue = cpu->reset_cbar }, |
f318cec6 PM |
8340 | REGINFO_SENTINEL |
8341 | }; | |
8342 | /* We don't implement a r/w 64 bit CBAR currently */ | |
8343 | assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); | |
8344 | define_arm_cp_regs(cpu, cbar_reginfo); | |
8345 | } else { | |
8346 | ARMCPRegInfo cbar = { | |
8347 | .name = "CBAR", | |
8348 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
8349 | .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, | |
8350 | .fieldoffset = offsetof(CPUARMState, | |
8351 | cp15.c15_config_base_address) | |
8352 | }; | |
8353 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | |
8354 | cbar.access = PL1_R; | |
8355 | cbar.fieldoffset = 0; | |
8356 | cbar.type = ARM_CP_CONST; | |
8357 | } | |
8358 | define_one_arm_cp_reg(cpu, &cbar); | |
8359 | } | |
d8ba780b PC |
8360 | } |
8361 | ||
91db4642 CLG |
8362 | if (arm_feature(env, ARM_FEATURE_VBAR)) { |
8363 | ARMCPRegInfo vbar_cp_reginfo[] = { | |
8364 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, | |
8365 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | |
8366 | .access = PL1_RW, .writefn = vbar_write, | |
8367 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), | |
8368 | offsetof(CPUARMState, cp15.vbar_ns) }, | |
8369 | .resetvalue = 0 }, | |
8370 | REGINFO_SENTINEL | |
8371 | }; | |
8372 | define_arm_cp_regs(cpu, vbar_cp_reginfo); | |
8373 | } | |
8374 | ||
2771db27 PM |
8375 | /* Generic registers whose values depend on the implementation */ |
8376 | { | |
8377 | ARMCPRegInfo sctlr = { | |
5ebafdf3 | 8378 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, |
137feaa9 | 8379 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, |
84929218 | 8380 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
137feaa9 FA |
8381 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), |
8382 | offsetof(CPUARMState, cp15.sctlr_ns) }, | |
d4e6df63 PM |
8383 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, |
8384 | .raw_writefn = raw_write, | |
2771db27 PM |
8385 | }; |
8386 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
8387 | /* Normally we would always end the TB on an SCTLR write, but Linux | |
8388 | * arch/arm/mach-pxa/sleep.S expects two instructions following | |
8389 | * an MMU enable to execute from cache. Imitate this behaviour. | |
8390 | */ | |
8391 | sctlr.type |= ARM_CP_SUPPRESS_TB_END; | |
8392 | } | |
8393 | define_one_arm_cp_reg(cpu, &sctlr); | |
8394 | } | |
5be5e8ed | 8395 | |
2d7137c1 | 8396 | if (cpu_isar_feature(aa64_lor, cpu)) { |
2d7137c1 RH |
8397 | define_arm_cp_regs(cpu, lor_reginfo); |
8398 | } | |
220f508f RH |
8399 | if (cpu_isar_feature(aa64_pan, cpu)) { |
8400 | define_one_arm_cp_reg(cpu, &pan_reginfo); | |
8401 | } | |
04b07d29 RH |
8402 | #ifndef CONFIG_USER_ONLY |
8403 | if (cpu_isar_feature(aa64_ats1e1, cpu)) { | |
8404 | define_arm_cp_regs(cpu, ats1e1_reginfo); | |
8405 | } | |
8406 | if (cpu_isar_feature(aa32_ats1e1, cpu)) { | |
8407 | define_arm_cp_regs(cpu, ats1cp_reginfo); | |
8408 | } | |
8409 | #endif | |
9eeb7a1c RH |
8410 | if (cpu_isar_feature(aa64_uao, cpu)) { |
8411 | define_one_arm_cp_reg(cpu, &uao_reginfo); | |
8412 | } | |
2d7137c1 | 8413 | |
dc8b1853 RC |
8414 | if (cpu_isar_feature(aa64_dit, cpu)) { |
8415 | define_one_arm_cp_reg(cpu, &dit_reginfo); | |
8416 | } | |
f2f68a78 RC |
8417 | if (cpu_isar_feature(aa64_ssbs, cpu)) { |
8418 | define_one_arm_cp_reg(cpu, &ssbs_reginfo); | |
8419 | } | |
dc8b1853 | 8420 | |
e2a1a461 RH |
8421 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { |
8422 | define_arm_cp_regs(cpu, vhe_reginfo); | |
8423 | } | |
8424 | ||
cd208a1c | 8425 | if (cpu_isar_feature(aa64_sve, cpu)) { |
5be5e8ed RH |
8426 | define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); |
8427 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
8428 | define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); | |
8429 | } else { | |
8430 | define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo); | |
8431 | } | |
8432 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
8433 | define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); | |
8434 | } | |
8435 | } | |
967aa94f RH |
8436 | |
8437 | #ifdef TARGET_AARCH64 | |
8438 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
8439 | define_arm_cp_regs(cpu, pauth_reginfo); | |
8440 | } | |
de390645 RH |
8441 | if (cpu_isar_feature(aa64_rndr, cpu)) { |
8442 | define_arm_cp_regs(cpu, rndr_reginfo); | |
8443 | } | |
84940ed8 RC |
8444 | if (cpu_isar_feature(aa64_tlbirange, cpu)) { |
8445 | define_arm_cp_regs(cpu, tlbirange_reginfo); | |
8446 | } | |
7113d618 RC |
8447 | if (cpu_isar_feature(aa64_tlbios, cpu)) { |
8448 | define_arm_cp_regs(cpu, tlbios_reginfo); | |
8449 | } | |
0d57b499 BM |
8450 | #ifndef CONFIG_USER_ONLY |
8451 | /* Data Cache clean instructions up to PoP */ | |
8452 | if (cpu_isar_feature(aa64_dcpop, cpu)) { | |
8453 | define_one_arm_cp_reg(cpu, dcpop_reg); | |
8454 | ||
8455 | if (cpu_isar_feature(aa64_dcpodp, cpu)) { | |
8456 | define_one_arm_cp_reg(cpu, dcpodp_reg); | |
8457 | } | |
8458 | } | |
8459 | #endif /*CONFIG_USER_ONLY*/ | |
4b779ceb RH |
8460 | |
8461 | /* | |
8462 | * If full MTE is enabled, add all of the system registers. | |
8463 | * If only "instructions available at EL0" are enabled, | |
8464 | * then define only a RAZ/WI version of PSTATE.TCO. | |
8465 | */ | |
8466 | if (cpu_isar_feature(aa64_mte, cpu)) { | |
8467 | define_arm_cp_regs(cpu, mte_reginfo); | |
5463df16 | 8468 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); |
4b779ceb RH |
8469 | } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { |
8470 | define_arm_cp_regs(cpu, mte_tco_ro_reginfo); | |
5463df16 | 8471 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); |
4b779ceb | 8472 | } |
967aa94f | 8473 | #endif |
cb570bd3 | 8474 | |
22e57073 | 8475 | if (cpu_isar_feature(any_predinv, cpu)) { |
cb570bd3 RH |
8476 | define_arm_cp_regs(cpu, predinv_reginfo); |
8477 | } | |
e2cce18f | 8478 | |
957e6155 PM |
8479 | if (cpu_isar_feature(any_ccidx, cpu)) { |
8480 | define_arm_cp_regs(cpu, ccsidr2_reginfo); | |
8481 | } | |
8482 | ||
e2cce18f RH |
8483 | #ifndef CONFIG_USER_ONLY |
8484 | /* | |
8485 | * Register redirections and aliases must be done last, | |
8486 | * after the registers from the other extensions have been defined. | |
8487 | */ | |
8488 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { | |
8489 | define_arm_vh_e2h_redirects_aliases(cpu); | |
8490 | } | |
8491 | #endif | |
2ceb98c0 PM |
8492 | } |
8493 | ||
777dc784 PM |
8494 | /* Sort alphabetically by type name, except for "any". */ |
8495 | static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) | |
5adb4839 | 8496 | { |
777dc784 PM |
8497 | ObjectClass *class_a = (ObjectClass *)a; |
8498 | ObjectClass *class_b = (ObjectClass *)b; | |
8499 | const char *name_a, *name_b; | |
5adb4839 | 8500 | |
777dc784 PM |
8501 | name_a = object_class_get_name(class_a); |
8502 | name_b = object_class_get_name(class_b); | |
51492fd1 | 8503 | if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 | 8504 | return 1; |
51492fd1 | 8505 | } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 PM |
8506 | return -1; |
8507 | } else { | |
8508 | return strcmp(name_a, name_b); | |
5adb4839 PB |
8509 | } |
8510 | } | |
8511 | ||
777dc784 | 8512 | static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
40f137e1 | 8513 | { |
777dc784 | 8514 | ObjectClass *oc = data; |
51492fd1 AF |
8515 | const char *typename; |
8516 | char *name; | |
3371d272 | 8517 | |
51492fd1 AF |
8518 | typename = object_class_get_name(oc); |
8519 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
0442428a | 8520 | qemu_printf(" %s\n", name); |
51492fd1 | 8521 | g_free(name); |
777dc784 PM |
8522 | } |
8523 | ||
0442428a | 8524 | void arm_cpu_list(void) |
777dc784 | 8525 | { |
777dc784 PM |
8526 | GSList *list; |
8527 | ||
8528 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
8529 | list = g_slist_sort(list, arm_cpu_list_compare); | |
0442428a MA |
8530 | qemu_printf("Available CPUs:\n"); |
8531 | g_slist_foreach(list, arm_cpu_list_entry, NULL); | |
777dc784 | 8532 | g_slist_free(list); |
40f137e1 PB |
8533 | } |
8534 | ||
78027bb6 CR |
8535 | static void arm_cpu_add_definition(gpointer data, gpointer user_data) |
8536 | { | |
8537 | ObjectClass *oc = data; | |
8538 | CpuDefinitionInfoList **cpu_list = user_data; | |
78027bb6 CR |
8539 | CpuDefinitionInfo *info; |
8540 | const char *typename; | |
8541 | ||
8542 | typename = object_class_get_name(oc); | |
8543 | info = g_malloc0(sizeof(*info)); | |
8544 | info->name = g_strndup(typename, | |
8545 | strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
8ed877b7 | 8546 | info->q_typename = g_strdup(typename); |
78027bb6 | 8547 | |
54aa3de7 | 8548 | QAPI_LIST_PREPEND(*cpu_list, info); |
78027bb6 CR |
8549 | } |
8550 | ||
25a9d6ca | 8551 | CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) |
78027bb6 CR |
8552 | { |
8553 | CpuDefinitionInfoList *cpu_list = NULL; | |
8554 | GSList *list; | |
8555 | ||
8556 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
8557 | g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); | |
8558 | g_slist_free(list); | |
8559 | ||
8560 | return cpu_list; | |
8561 | } | |
8562 | ||
6e6efd61 | 8563 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
51a79b03 | 8564 | void *opaque, int state, int secstate, |
9c513e78 AB |
8565 | int crm, int opc1, int opc2, |
8566 | const char *name) | |
6e6efd61 PM |
8567 | { |
8568 | /* Private utility function for define_one_arm_cp_reg_with_opaque(): | |
8569 | * add a single reginfo struct to the hash table. | |
8570 | */ | |
8571 | uint32_t *key = g_new(uint32_t, 1); | |
8572 | ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); | |
8573 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | |
3f3c82a5 FA |
8574 | int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; |
8575 | ||
9c513e78 | 8576 | r2->name = g_strdup(name); |
3f3c82a5 FA |
8577 | /* Reset the secure state to the specific incoming state. This is |
8578 | * necessary as the register may have been defined with both states. | |
8579 | */ | |
8580 | r2->secure = secstate; | |
8581 | ||
8582 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
8583 | /* Register is banked (using both entries in array). | |
8584 | * Overwriting fieldoffset as the array is only used to define | |
8585 | * banked registers but later only fieldoffset is used. | |
f5a0a5a5 | 8586 | */ |
3f3c82a5 FA |
8587 | r2->fieldoffset = r->bank_fieldoffsets[ns]; |
8588 | } | |
8589 | ||
8590 | if (state == ARM_CP_STATE_AA32) { | |
8591 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
8592 | /* If the register is banked then we don't need to migrate or | |
8593 | * reset the 32-bit instance in certain cases: | |
8594 | * | |
8595 | * 1) If the register has both 32-bit and 64-bit instances then we | |
8596 | * can count on the 64-bit instance taking care of the | |
8597 | * non-secure bank. | |
8598 | * 2) If ARMv8 is enabled then we can count on a 64-bit version | |
8599 | * taking care of the secure bank. This requires that separate | |
8600 | * 32 and 64-bit definitions are provided. | |
8601 | */ | |
8602 | if ((r->state == ARM_CP_STATE_BOTH && ns) || | |
8603 | (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { | |
7a0e58fa | 8604 | r2->type |= ARM_CP_ALIAS; |
3f3c82a5 FA |
8605 | } |
8606 | } else if ((secstate != r->secure) && !ns) { | |
8607 | /* The register is not banked so we only want to allow migration of | |
8608 | * the non-secure instance. | |
8609 | */ | |
7a0e58fa | 8610 | r2->type |= ARM_CP_ALIAS; |
58a1d8ce | 8611 | } |
3f3c82a5 FA |
8612 | |
8613 | if (r->state == ARM_CP_STATE_BOTH) { | |
8614 | /* We assume it is a cp15 register if the .cp field is left unset. | |
8615 | */ | |
8616 | if (r2->cp == 0) { | |
8617 | r2->cp = 15; | |
8618 | } | |
8619 | ||
f5a0a5a5 | 8620 | #ifdef HOST_WORDS_BIGENDIAN |
3f3c82a5 FA |
8621 | if (r2->fieldoffset) { |
8622 | r2->fieldoffset += sizeof(uint32_t); | |
8623 | } | |
f5a0a5a5 | 8624 | #endif |
3f3c82a5 | 8625 | } |
f5a0a5a5 PM |
8626 | } |
8627 | if (state == ARM_CP_STATE_AA64) { | |
8628 | /* To allow abbreviation of ARMCPRegInfo | |
8629 | * definitions, we treat cp == 0 as equivalent to | |
8630 | * the value for "standard guest-visible sysreg". | |
58a1d8ce PM |
8631 | * STATE_BOTH definitions are also always "standard |
8632 | * sysreg" in their AArch64 view (the .cp value may | |
8633 | * be non-zero for the benefit of the AArch32 view). | |
f5a0a5a5 | 8634 | */ |
58a1d8ce | 8635 | if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { |
f5a0a5a5 PM |
8636 | r2->cp = CP_REG_ARM64_SYSREG_CP; |
8637 | } | |
8638 | *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | |
8639 | r2->opc0, opc1, opc2); | |
8640 | } else { | |
51a79b03 | 8641 | *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); |
f5a0a5a5 | 8642 | } |
6e6efd61 PM |
8643 | if (opaque) { |
8644 | r2->opaque = opaque; | |
8645 | } | |
67ed771d PM |
8646 | /* reginfo passed to helpers is correct for the actual access, |
8647 | * and is never ARM_CP_STATE_BOTH: | |
8648 | */ | |
8649 | r2->state = state; | |
6e6efd61 PM |
8650 | /* Make sure reginfo passed to helpers for wildcarded regs |
8651 | * has the correct crm/opc1/opc2 for this reg, not CP_ANY: | |
8652 | */ | |
8653 | r2->crm = crm; | |
8654 | r2->opc1 = opc1; | |
8655 | r2->opc2 = opc2; | |
8656 | /* By convention, for wildcarded registers only the first | |
8657 | * entry is used for migration; the others are marked as | |
7a0e58fa | 8658 | * ALIAS so we don't try to transfer the register |
6e6efd61 | 8659 | * multiple times. Special registers (ie NOP/WFI) are |
7a0e58fa | 8660 | * never migratable and not even raw-accessible. |
6e6efd61 | 8661 | */ |
7a0e58fa PM |
8662 | if ((r->type & ARM_CP_SPECIAL)) { |
8663 | r2->type |= ARM_CP_NO_RAW; | |
8664 | } | |
8665 | if (((r->crm == CP_ANY) && crm != 0) || | |
6e6efd61 PM |
8666 | ((r->opc1 == CP_ANY) && opc1 != 0) || |
8667 | ((r->opc2 == CP_ANY) && opc2 != 0)) { | |
1f163787 | 8668 | r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB; |
6e6efd61 PM |
8669 | } |
8670 | ||
375421cc PM |
8671 | /* Check that raw accesses are either forbidden or handled. Note that |
8672 | * we can't assert this earlier because the setup of fieldoffset for | |
8673 | * banked registers has to be done first. | |
8674 | */ | |
8675 | if (!(r2->type & ARM_CP_NO_RAW)) { | |
8676 | assert(!raw_accessors_invalid(r2)); | |
8677 | } | |
8678 | ||
6e6efd61 PM |
8679 | /* Overriding of an existing definition must be explicitly |
8680 | * requested. | |
8681 | */ | |
8682 | if (!(r->type & ARM_CP_OVERRIDE)) { | |
8683 | ARMCPRegInfo *oldreg; | |
8684 | oldreg = g_hash_table_lookup(cpu->cp_regs, key); | |
8685 | if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { | |
8686 | fprintf(stderr, "Register redefined: cp=%d %d bit " | |
8687 | "crn=%d crm=%d opc1=%d opc2=%d, " | |
8688 | "was %s, now %s\n", r2->cp, 32 + 32 * is64, | |
8689 | r2->crn, r2->crm, r2->opc1, r2->opc2, | |
8690 | oldreg->name, r2->name); | |
8691 | g_assert_not_reached(); | |
8692 | } | |
8693 | } | |
8694 | g_hash_table_insert(cpu->cp_regs, key, r2); | |
8695 | } | |
8696 | ||
8697 | ||
4b6a83fb PM |
8698 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
8699 | const ARMCPRegInfo *r, void *opaque) | |
8700 | { | |
8701 | /* Define implementations of coprocessor registers. | |
8702 | * We store these in a hashtable because typically | |
8703 | * there are less than 150 registers in a space which | |
8704 | * is 16*16*16*8*8 = 262144 in size. | |
8705 | * Wildcarding is supported for the crm, opc1 and opc2 fields. | |
8706 | * If a register is defined twice then the second definition is | |
8707 | * used, so this can be used to define some generic registers and | |
8708 | * then override them with implementation specific variations. | |
8709 | * At least one of the original and the second definition should | |
8710 | * include ARM_CP_OVERRIDE in its type bits -- this is just a guard | |
8711 | * against accidental use. | |
f5a0a5a5 PM |
8712 | * |
8713 | * The state field defines whether the register is to be | |
8714 | * visible in the AArch32 or AArch64 execution state. If the | |
8715 | * state is set to ARM_CP_STATE_BOTH then we synthesise a | |
8716 | * reginfo structure for the AArch32 view, which sees the lower | |
8717 | * 32 bits of the 64 bit register. | |
8718 | * | |
8719 | * Only registers visible in AArch64 may set r->opc0; opc0 cannot | |
8720 | * be wildcarded. AArch64 registers are always considered to be 64 | |
8721 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | |
8722 | * the register, if any. | |
4b6a83fb | 8723 | */ |
f5a0a5a5 | 8724 | int crm, opc1, opc2, state; |
4b6a83fb PM |
8725 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
8726 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | |
8727 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | |
8728 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | |
8729 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | |
8730 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | |
8731 | /* 64 bit registers have only CRm and Opc1 fields */ | |
8732 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | |
f5a0a5a5 PM |
8733 | /* op0 only exists in the AArch64 encodings */ |
8734 | assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); | |
8735 | /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ | |
8736 | assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); | |
cd8be50e PM |
8737 | /* |
8738 | * This API is only for Arm's system coprocessors (14 and 15) or | |
8739 | * (M-profile or v7A-and-earlier only) for implementation defined | |
8740 | * coprocessors in the range 0..7. Our decode assumes this, since | |
8741 | * 8..13 can be used for other insns including VFP and Neon. See | |
8742 | * valid_cp() in translate.c. Assert here that we haven't tried | |
8743 | * to use an invalid coprocessor number. | |
8744 | */ | |
8745 | switch (r->state) { | |
8746 | case ARM_CP_STATE_BOTH: | |
8747 | /* 0 has a special meaning, but otherwise the same rules as AA32. */ | |
8748 | if (r->cp == 0) { | |
8749 | break; | |
8750 | } | |
8751 | /* fall through */ | |
8752 | case ARM_CP_STATE_AA32: | |
8753 | if (arm_feature(&cpu->env, ARM_FEATURE_V8) && | |
8754 | !arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
8755 | assert(r->cp >= 14 && r->cp <= 15); | |
8756 | } else { | |
8757 | assert(r->cp < 8 || (r->cp >= 14 && r->cp <= 15)); | |
8758 | } | |
8759 | break; | |
8760 | case ARM_CP_STATE_AA64: | |
8761 | assert(r->cp == 0 || r->cp == CP_REG_ARM64_SYSREG_CP); | |
8762 | break; | |
8763 | default: | |
8764 | g_assert_not_reached(); | |
8765 | } | |
f5a0a5a5 PM |
8766 | /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 |
8767 | * encodes a minimum access level for the register. We roll this | |
8768 | * runtime check into our general permission check code, so check | |
8769 | * here that the reginfo's specified permissions are strict enough | |
8770 | * to encompass the generic architectural permission check. | |
8771 | */ | |
8772 | if (r->state != ARM_CP_STATE_AA32) { | |
8773 | int mask = 0; | |
8774 | switch (r->opc1) { | |
b5bd7440 AB |
8775 | case 0: |
8776 | /* min_EL EL1, but some accessible to EL0 via kernel ABI */ | |
8777 | mask = PL0U_R | PL1_RW; | |
8778 | break; | |
8779 | case 1: case 2: | |
f5a0a5a5 PM |
8780 | /* min_EL EL1 */ |
8781 | mask = PL1_RW; | |
8782 | break; | |
8783 | case 3: | |
8784 | /* min_EL EL0 */ | |
8785 | mask = PL0_RW; | |
8786 | break; | |
8787 | case 4: | |
b4ecf60f | 8788 | case 5: |
f5a0a5a5 PM |
8789 | /* min_EL EL2 */ |
8790 | mask = PL2_RW; | |
8791 | break; | |
f5a0a5a5 PM |
8792 | case 6: |
8793 | /* min_EL EL3 */ | |
8794 | mask = PL3_RW; | |
8795 | break; | |
8796 | case 7: | |
8797 | /* min_EL EL1, secure mode only (we don't check the latter) */ | |
8798 | mask = PL1_RW; | |
8799 | break; | |
8800 | default: | |
8801 | /* broken reginfo with out-of-range opc1 */ | |
8802 | assert(false); | |
8803 | break; | |
8804 | } | |
8805 | /* assert our permissions are not too lax (stricter is fine) */ | |
8806 | assert((r->access & ~mask) == 0); | |
8807 | } | |
8808 | ||
4b6a83fb PM |
8809 | /* Check that the register definition has enough info to handle |
8810 | * reads and writes if they are permitted. | |
8811 | */ | |
8812 | if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { | |
8813 | if (r->access & PL3_R) { | |
3f3c82a5 FA |
8814 | assert((r->fieldoffset || |
8815 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
8816 | r->readfn); | |
4b6a83fb PM |
8817 | } |
8818 | if (r->access & PL3_W) { | |
3f3c82a5 FA |
8819 | assert((r->fieldoffset || |
8820 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
8821 | r->writefn); | |
4b6a83fb PM |
8822 | } |
8823 | } | |
8824 | /* Bad type field probably means missing sentinel at end of reg list */ | |
8825 | assert(cptype_valid(r->type)); | |
8826 | for (crm = crmmin; crm <= crmmax; crm++) { | |
8827 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | |
8828 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | |
f5a0a5a5 PM |
8829 | for (state = ARM_CP_STATE_AA32; |
8830 | state <= ARM_CP_STATE_AA64; state++) { | |
8831 | if (r->state != state && r->state != ARM_CP_STATE_BOTH) { | |
8832 | continue; | |
8833 | } | |
3f3c82a5 FA |
8834 | if (state == ARM_CP_STATE_AA32) { |
8835 | /* Under AArch32 CP registers can be common | |
8836 | * (same for secure and non-secure world) or banked. | |
8837 | */ | |
9c513e78 AB |
8838 | char *name; |
8839 | ||
3f3c82a5 FA |
8840 | switch (r->secure) { |
8841 | case ARM_CP_SECSTATE_S: | |
8842 | case ARM_CP_SECSTATE_NS: | |
8843 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
9c513e78 AB |
8844 | r->secure, crm, opc1, opc2, |
8845 | r->name); | |
3f3c82a5 FA |
8846 | break; |
8847 | default: | |
9c513e78 | 8848 | name = g_strdup_printf("%s_S", r->name); |
3f3c82a5 FA |
8849 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
8850 | ARM_CP_SECSTATE_S, | |
9c513e78 AB |
8851 | crm, opc1, opc2, name); |
8852 | g_free(name); | |
3f3c82a5 FA |
8853 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
8854 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 8855 | crm, opc1, opc2, r->name); |
3f3c82a5 FA |
8856 | break; |
8857 | } | |
8858 | } else { | |
8859 | /* AArch64 registers get mapped to non-secure instance | |
8860 | * of AArch32 */ | |
8861 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
8862 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 8863 | crm, opc1, opc2, r->name); |
3f3c82a5 | 8864 | } |
f5a0a5a5 | 8865 | } |
4b6a83fb PM |
8866 | } |
8867 | } | |
8868 | } | |
8869 | } | |
8870 | ||
8871 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
8872 | const ARMCPRegInfo *regs, void *opaque) | |
8873 | { | |
8874 | /* Define a whole list of registers */ | |
8875 | const ARMCPRegInfo *r; | |
8876 | for (r = regs; r->type != ARM_CP_SENTINEL; r++) { | |
8877 | define_one_arm_cp_reg_with_opaque(cpu, r, opaque); | |
8878 | } | |
8879 | } | |
8880 | ||
6c5c0fec AB |
8881 | /* |
8882 | * Modify ARMCPRegInfo for access from userspace. | |
8883 | * | |
8884 | * This is a data driven modification directed by | |
8885 | * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as | |
8886 | * user-space cannot alter any values and dynamic values pertaining to | |
8887 | * execution state are hidden from user space view anyway. | |
8888 | */ | |
8889 | void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods) | |
8890 | { | |
8891 | const ARMCPRegUserSpaceInfo *m; | |
8892 | ARMCPRegInfo *r; | |
8893 | ||
8894 | for (m = mods; m->name; m++) { | |
d040242e AB |
8895 | GPatternSpec *pat = NULL; |
8896 | if (m->is_glob) { | |
8897 | pat = g_pattern_spec_new(m->name); | |
8898 | } | |
6c5c0fec | 8899 | for (r = regs; r->type != ARM_CP_SENTINEL; r++) { |
d040242e AB |
8900 | if (pat && g_pattern_match_string(pat, r->name)) { |
8901 | r->type = ARM_CP_CONST; | |
8902 | r->access = PL0U_R; | |
8903 | r->resetvalue = 0; | |
8904 | /* continue */ | |
8905 | } else if (strcmp(r->name, m->name) == 0) { | |
6c5c0fec AB |
8906 | r->type = ARM_CP_CONST; |
8907 | r->access = PL0U_R; | |
8908 | r->resetvalue &= m->exported_bits; | |
8909 | r->resetvalue |= m->fixed_bits; | |
8910 | break; | |
8911 | } | |
8912 | } | |
d040242e AB |
8913 | if (pat) { |
8914 | g_pattern_spec_free(pat); | |
8915 | } | |
6c5c0fec AB |
8916 | } |
8917 | } | |
8918 | ||
60322b39 | 8919 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) |
4b6a83fb | 8920 | { |
60322b39 | 8921 | return g_hash_table_lookup(cpregs, &encoded_cp); |
4b6a83fb PM |
8922 | } |
8923 | ||
c4241c7d PM |
8924 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
8925 | uint64_t value) | |
4b6a83fb PM |
8926 | { |
8927 | /* Helper coprocessor write function for write-ignore registers */ | |
4b6a83fb PM |
8928 | } |
8929 | ||
c4241c7d | 8930 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) |
4b6a83fb PM |
8931 | { |
8932 | /* Helper coprocessor write function for read-as-zero registers */ | |
4b6a83fb PM |
8933 | return 0; |
8934 | } | |
8935 | ||
f5a0a5a5 PM |
8936 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) |
8937 | { | |
8938 | /* Helper coprocessor reset function for do-nothing-on-reset registers */ | |
8939 | } | |
8940 | ||
af393ffc | 8941 | static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) |
37064a8b PM |
8942 | { |
8943 | /* Return true if it is not valid for us to switch to | |
8944 | * this CPU mode (ie all the UNPREDICTABLE cases in | |
8945 | * the ARM ARM CPSRWriteByInstr pseudocode). | |
8946 | */ | |
af393ffc PM |
8947 | |
8948 | /* Changes to or from Hyp via MSR and CPS are illegal. */ | |
8949 | if (write_type == CPSRWriteByInstr && | |
8950 | ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || | |
8951 | mode == ARM_CPU_MODE_HYP)) { | |
8952 | return 1; | |
8953 | } | |
8954 | ||
37064a8b PM |
8955 | switch (mode) { |
8956 | case ARM_CPU_MODE_USR: | |
10eacda7 | 8957 | return 0; |
37064a8b PM |
8958 | case ARM_CPU_MODE_SYS: |
8959 | case ARM_CPU_MODE_SVC: | |
8960 | case ARM_CPU_MODE_ABT: | |
8961 | case ARM_CPU_MODE_UND: | |
8962 | case ARM_CPU_MODE_IRQ: | |
8963 | case ARM_CPU_MODE_FIQ: | |
52ff951b PM |
8964 | /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 |
8965 | * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) | |
8966 | */ | |
10eacda7 PM |
8967 | /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR |
8968 | * and CPS are treated as illegal mode changes. | |
8969 | */ | |
8970 | if (write_type == CPSRWriteByInstr && | |
10eacda7 | 8971 | (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && |
7c208e0f | 8972 | (arm_hcr_el2_eff(env) & HCR_TGE)) { |
10eacda7 PM |
8973 | return 1; |
8974 | } | |
37064a8b | 8975 | return 0; |
e6c8fc07 | 8976 | case ARM_CPU_MODE_HYP: |
e6ef0169 | 8977 | return !arm_is_el2_enabled(env) || arm_current_el(env) < 2; |
027fc527 | 8978 | case ARM_CPU_MODE_MON: |
58ae2d1f | 8979 | return arm_current_el(env) < 3; |
37064a8b PM |
8980 | default: |
8981 | return 1; | |
8982 | } | |
8983 | } | |
8984 | ||
2f4a40e5 AZ |
8985 | uint32_t cpsr_read(CPUARMState *env) |
8986 | { | |
8987 | int ZF; | |
6fbe23d5 PB |
8988 | ZF = (env->ZF == 0); |
8989 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
8990 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
8991 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
8992 | | ((env->condexec_bits & 0xfc) << 8) | |
af519934 | 8993 | | (env->GE << 16) | (env->daif & CPSR_AIF); |
2f4a40e5 AZ |
8994 | } |
8995 | ||
50866ba5 PM |
8996 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, |
8997 | CPSRWriteType write_type) | |
2f4a40e5 | 8998 | { |
6e8801f9 | 8999 | uint32_t changed_daif; |
e784807c PM |
9000 | bool rebuild_hflags = (write_type != CPSRWriteRaw) && |
9001 | (mask & (CPSR_M | CPSR_E | CPSR_IL)); | |
6e8801f9 | 9002 | |
2f4a40e5 | 9003 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
9004 | env->ZF = (~val) & CPSR_Z; |
9005 | env->NF = val; | |
2f4a40e5 AZ |
9006 | env->CF = (val >> 29) & 1; |
9007 | env->VF = (val << 3) & 0x80000000; | |
9008 | } | |
9009 | if (mask & CPSR_Q) | |
9010 | env->QF = ((val & CPSR_Q) != 0); | |
9011 | if (mask & CPSR_T) | |
9012 | env->thumb = ((val & CPSR_T) != 0); | |
9013 | if (mask & CPSR_IT_0_1) { | |
9014 | env->condexec_bits &= ~3; | |
9015 | env->condexec_bits |= (val >> 25) & 3; | |
9016 | } | |
9017 | if (mask & CPSR_IT_2_7) { | |
9018 | env->condexec_bits &= 3; | |
9019 | env->condexec_bits |= (val >> 8) & 0xfc; | |
9020 | } | |
9021 | if (mask & CPSR_GE) { | |
9022 | env->GE = (val >> 16) & 0xf; | |
9023 | } | |
9024 | ||
6e8801f9 FA |
9025 | /* In a V7 implementation that includes the security extensions but does |
9026 | * not include Virtualization Extensions the SCR.FW and SCR.AW bits control | |
9027 | * whether non-secure software is allowed to change the CPSR_F and CPSR_A | |
9028 | * bits respectively. | |
9029 | * | |
9030 | * In a V8 implementation, it is permitted for privileged software to | |
9031 | * change the CPSR A/F bits regardless of the SCR.AW/FW bits. | |
9032 | */ | |
f8c88bbc | 9033 | if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && |
6e8801f9 FA |
9034 | arm_feature(env, ARM_FEATURE_EL3) && |
9035 | !arm_feature(env, ARM_FEATURE_EL2) && | |
9036 | !arm_is_secure(env)) { | |
9037 | ||
9038 | changed_daif = (env->daif ^ val) & mask; | |
9039 | ||
9040 | if (changed_daif & CPSR_A) { | |
9041 | /* Check to see if we are allowed to change the masking of async | |
9042 | * abort exceptions from a non-secure state. | |
9043 | */ | |
9044 | if (!(env->cp15.scr_el3 & SCR_AW)) { | |
9045 | qemu_log_mask(LOG_GUEST_ERROR, | |
9046 | "Ignoring attempt to switch CPSR_A flag from " | |
9047 | "non-secure world with SCR.AW bit clear\n"); | |
9048 | mask &= ~CPSR_A; | |
9049 | } | |
9050 | } | |
9051 | ||
9052 | if (changed_daif & CPSR_F) { | |
9053 | /* Check to see if we are allowed to change the masking of FIQ | |
9054 | * exceptions from a non-secure state. | |
9055 | */ | |
9056 | if (!(env->cp15.scr_el3 & SCR_FW)) { | |
9057 | qemu_log_mask(LOG_GUEST_ERROR, | |
9058 | "Ignoring attempt to switch CPSR_F flag from " | |
9059 | "non-secure world with SCR.FW bit clear\n"); | |
9060 | mask &= ~CPSR_F; | |
9061 | } | |
9062 | ||
9063 | /* Check whether non-maskable FIQ (NMFI) support is enabled. | |
9064 | * If this bit is set software is not allowed to mask | |
9065 | * FIQs, but is allowed to set CPSR_F to 0. | |
9066 | */ | |
9067 | if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && | |
9068 | (val & CPSR_F)) { | |
9069 | qemu_log_mask(LOG_GUEST_ERROR, | |
9070 | "Ignoring attempt to enable CPSR_F flag " | |
9071 | "(non-maskable FIQ [NMFI] support enabled)\n"); | |
9072 | mask &= ~CPSR_F; | |
9073 | } | |
9074 | } | |
9075 | } | |
9076 | ||
4cc35614 PM |
9077 | env->daif &= ~(CPSR_AIF & mask); |
9078 | env->daif |= val & CPSR_AIF & mask; | |
9079 | ||
f8c88bbc PM |
9080 | if (write_type != CPSRWriteRaw && |
9081 | ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { | |
8c4f0eb9 PM |
9082 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { |
9083 | /* Note that we can only get here in USR mode if this is a | |
9084 | * gdb stub write; for this case we follow the architectural | |
9085 | * behaviour for guest writes in USR mode of ignoring an attempt | |
9086 | * to switch mode. (Those are caught by translate.c for writes | |
9087 | * triggered by guest instructions.) | |
9088 | */ | |
9089 | mask &= ~CPSR_M; | |
9090 | } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { | |
81907a58 PM |
9091 | /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in |
9092 | * v7, and has defined behaviour in v8: | |
9093 | * + leave CPSR.M untouched | |
9094 | * + allow changes to the other CPSR fields | |
9095 | * + set PSTATE.IL | |
9096 | * For user changes via the GDB stub, we don't set PSTATE.IL, | |
9097 | * as this would be unnecessarily harsh for a user error. | |
37064a8b PM |
9098 | */ |
9099 | mask &= ~CPSR_M; | |
81907a58 PM |
9100 | if (write_type != CPSRWriteByGDBStub && |
9101 | arm_feature(env, ARM_FEATURE_V8)) { | |
9102 | mask |= CPSR_IL; | |
9103 | val |= CPSR_IL; | |
9104 | } | |
81e37284 PM |
9105 | qemu_log_mask(LOG_GUEST_ERROR, |
9106 | "Illegal AArch32 mode switch attempt from %s to %s\n", | |
9107 | aarch32_mode_name(env->uncached_cpsr), | |
9108 | aarch32_mode_name(val)); | |
37064a8b | 9109 | } else { |
81e37284 PM |
9110 | qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n", |
9111 | write_type == CPSRWriteExceptionReturn ? | |
9112 | "Exception return from AArch32" : | |
9113 | "AArch32 mode switch from", | |
9114 | aarch32_mode_name(env->uncached_cpsr), | |
9115 | aarch32_mode_name(val), env->regs[15]); | |
37064a8b PM |
9116 | switch_mode(env, val & CPSR_M); |
9117 | } | |
2f4a40e5 AZ |
9118 | } |
9119 | mask &= ~CACHED_CPSR_BITS; | |
9120 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
e784807c PM |
9121 | if (rebuild_hflags) { |
9122 | arm_rebuild_hflags(env); | |
9123 | } | |
2f4a40e5 AZ |
9124 | } |
9125 | ||
b26eefb6 PB |
9126 | /* Sign/zero extend */ |
9127 | uint32_t HELPER(sxtb16)(uint32_t x) | |
9128 | { | |
9129 | uint32_t res; | |
9130 | res = (uint16_t)(int8_t)x; | |
9131 | res |= (uint32_t)(int8_t)(x >> 16) << 16; | |
9132 | return res; | |
9133 | } | |
9134 | ||
e5346292 PM |
9135 | static void handle_possible_div0_trap(CPUARMState *env, uintptr_t ra) |
9136 | { | |
9137 | /* | |
9138 | * Take a division-by-zero exception if necessary; otherwise return | |
9139 | * to get the usual non-trapping division behaviour (result of 0) | |
9140 | */ | |
9141 | if (arm_feature(env, ARM_FEATURE_M) | |
9142 | && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { | |
9143 | raise_exception_ra(env, EXCP_DIVBYZERO, 0, 1, ra); | |
9144 | } | |
9145 | } | |
9146 | ||
b26eefb6 PB |
9147 | uint32_t HELPER(uxtb16)(uint32_t x) |
9148 | { | |
9149 | uint32_t res; | |
9150 | res = (uint16_t)(uint8_t)x; | |
9151 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; | |
9152 | return res; | |
9153 | } | |
9154 | ||
e5346292 | 9155 | int32_t HELPER(sdiv)(CPUARMState *env, int32_t num, int32_t den) |
3670669c | 9156 | { |
fc7a5038 | 9157 | if (den == 0) { |
e5346292 | 9158 | handle_possible_div0_trap(env, GETPC()); |
fc7a5038 PM |
9159 | return 0; |
9160 | } | |
9161 | if (num == INT_MIN && den == -1) { | |
9162 | return INT_MIN; | |
9163 | } | |
3670669c PB |
9164 | return num / den; |
9165 | } | |
9166 | ||
e5346292 | 9167 | uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den) |
3670669c | 9168 | { |
fc7a5038 | 9169 | if (den == 0) { |
e5346292 | 9170 | handle_possible_div0_trap(env, GETPC()); |
fc7a5038 PM |
9171 | return 0; |
9172 | } | |
3670669c PB |
9173 | return num / den; |
9174 | } | |
9175 | ||
9176 | uint32_t HELPER(rbit)(uint32_t x) | |
9177 | { | |
42fedbca | 9178 | return revbit32(x); |
3670669c PB |
9179 | } |
9180 | ||
c47eaf9f | 9181 | #ifdef CONFIG_USER_ONLY |
b5ff1b31 | 9182 | |
affdb64d | 9183 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 | 9184 | { |
2fc0cc0e | 9185 | ARMCPU *cpu = env_archcpu(env); |
a47dddd7 AF |
9186 | |
9187 | if (mode != ARM_CPU_MODE_USR) { | |
9188 | cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); | |
9189 | } | |
b5ff1b31 FB |
9190 | } |
9191 | ||
012a906b GB |
9192 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
9193 | uint32_t cur_el, bool secure) | |
9e729b57 EI |
9194 | { |
9195 | return 1; | |
9196 | } | |
9197 | ||
ce02049d GB |
9198 | void aarch64_sync_64_to_32(CPUARMState *env) |
9199 | { | |
9200 | g_assert_not_reached(); | |
9201 | } | |
9202 | ||
b5ff1b31 FB |
9203 | #else |
9204 | ||
affdb64d | 9205 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
9206 | { |
9207 | int old_mode; | |
9208 | int i; | |
9209 | ||
9210 | old_mode = env->uncached_cpsr & CPSR_M; | |
9211 | if (mode == old_mode) | |
9212 | return; | |
9213 | ||
9214 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
9215 | memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 9216 | memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
9217 | } else if (mode == ARM_CPU_MODE_FIQ) { |
9218 | memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 9219 | memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
9220 | } |
9221 | ||
f5206413 | 9222 | i = bank_number(old_mode); |
b5ff1b31 | 9223 | env->banked_r13[i] = env->regs[13]; |
b5ff1b31 FB |
9224 | env->banked_spsr[i] = env->spsr; |
9225 | ||
f5206413 | 9226 | i = bank_number(mode); |
b5ff1b31 | 9227 | env->regs[13] = env->banked_r13[i]; |
b5ff1b31 | 9228 | env->spsr = env->banked_spsr[i]; |
593cfa2b PM |
9229 | |
9230 | env->banked_r14[r14_bank_number(old_mode)] = env->regs[14]; | |
9231 | env->regs[14] = env->banked_r14[r14_bank_number(mode)]; | |
b5ff1b31 FB |
9232 | } |
9233 | ||
0eeb17d6 GB |
9234 | /* Physical Interrupt Target EL Lookup Table |
9235 | * | |
9236 | * [ From ARM ARM section G1.13.4 (Table G1-15) ] | |
9237 | * | |
9238 | * The below multi-dimensional table is used for looking up the target | |
9239 | * exception level given numerous condition criteria. Specifically, the | |
9240 | * target EL is based on SCR and HCR routing controls as well as the | |
9241 | * currently executing EL and secure state. | |
9242 | * | |
9243 | * Dimensions: | |
9244 | * target_el_table[2][2][2][2][2][4] | |
9245 | * | | | | | +--- Current EL | |
9246 | * | | | | +------ Non-secure(0)/Secure(1) | |
9247 | * | | | +--------- HCR mask override | |
9248 | * | | +------------ SCR exec state control | |
9249 | * | +--------------- SCR mask override | |
9250 | * +------------------ 32-bit(0)/64-bit(1) EL3 | |
9251 | * | |
9252 | * The table values are as such: | |
9253 | * 0-3 = EL0-EL3 | |
9254 | * -1 = Cannot occur | |
9255 | * | |
9256 | * The ARM ARM target EL table includes entries indicating that an "exception | |
9257 | * is not taken". The two cases where this is applicable are: | |
9258 | * 1) An exception is taken from EL3 but the SCR does not have the exception | |
9259 | * routed to EL3. | |
9260 | * 2) An exception is taken from EL2 but the HCR does not have the exception | |
9261 | * routed to EL2. | |
9262 | * In these two cases, the below table contain a target of EL1. This value is | |
9263 | * returned as it is expected that the consumer of the table data will check | |
9264 | * for "target EL >= current EL" to ensure the exception is not taken. | |
9265 | * | |
9266 | * SCR HCR | |
9267 | * 64 EA AMO From | |
9268 | * BIT IRQ IMO Non-secure Secure | |
9269 | * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 | |
9270 | */ | |
82c39f6a | 9271 | static const int8_t target_el_table[2][2][2][2][2][4] = { |
0eeb17d6 GB |
9272 | {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, |
9273 | {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, | |
9274 | {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, | |
9275 | {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, | |
9276 | {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
9277 | {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, | |
9278 | {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
9279 | {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, | |
9280 | {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, | |
6c85f906 RDC |
9281 | {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},}, |
9282 | {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },}, | |
9283 | {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},}, | |
0eeb17d6 GB |
9284 | {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, |
9285 | {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, | |
6c85f906 RDC |
9286 | {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },}, |
9287 | {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},}, | |
0eeb17d6 GB |
9288 | }; |
9289 | ||
9290 | /* | |
9291 | * Determine the target EL for physical exceptions | |
9292 | */ | |
012a906b GB |
9293 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
9294 | uint32_t cur_el, bool secure) | |
0eeb17d6 GB |
9295 | { |
9296 | CPUARMState *env = cs->env_ptr; | |
f7778444 RH |
9297 | bool rw; |
9298 | bool scr; | |
9299 | bool hcr; | |
0eeb17d6 | 9300 | int target_el; |
2cde031f | 9301 | /* Is the highest EL AArch64? */ |
f7778444 RH |
9302 | bool is64 = arm_feature(env, ARM_FEATURE_AARCH64); |
9303 | uint64_t hcr_el2; | |
2cde031f SS |
9304 | |
9305 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
9306 | rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); | |
9307 | } else { | |
9308 | /* Either EL2 is the highest EL (and so the EL2 register width | |
9309 | * is given by is64); or there is no EL2 or EL3, in which case | |
9310 | * the value of 'rw' does not affect the table lookup anyway. | |
9311 | */ | |
9312 | rw = is64; | |
9313 | } | |
0eeb17d6 | 9314 | |
f7778444 | 9315 | hcr_el2 = arm_hcr_el2_eff(env); |
0eeb17d6 GB |
9316 | switch (excp_idx) { |
9317 | case EXCP_IRQ: | |
9318 | scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); | |
f7778444 | 9319 | hcr = hcr_el2 & HCR_IMO; |
0eeb17d6 GB |
9320 | break; |
9321 | case EXCP_FIQ: | |
9322 | scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); | |
f7778444 | 9323 | hcr = hcr_el2 & HCR_FMO; |
0eeb17d6 GB |
9324 | break; |
9325 | default: | |
9326 | scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); | |
f7778444 | 9327 | hcr = hcr_el2 & HCR_AMO; |
0eeb17d6 GB |
9328 | break; |
9329 | }; | |
9330 | ||
d1b31428 RH |
9331 | /* |
9332 | * For these purposes, TGE and AMO/IMO/FMO both force the | |
9333 | * interrupt to EL2. Fold TGE into the bit extracted above. | |
9334 | */ | |
9335 | hcr |= (hcr_el2 & HCR_TGE) != 0; | |
9336 | ||
0eeb17d6 GB |
9337 | /* Perform a table-lookup for the target EL given the current state */ |
9338 | target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; | |
9339 | ||
9340 | assert(target_el > 0); | |
9341 | ||
9342 | return target_el; | |
9343 | } | |
9344 | ||
fc6177af | 9345 | void arm_log_exception(CPUState *cs) |
b59f479b | 9346 | { |
fc6177af PM |
9347 | int idx = cs->exception_index; |
9348 | ||
b59f479b PMD |
9349 | if (qemu_loglevel_mask(CPU_LOG_INT)) { |
9350 | const char *exc = NULL; | |
9351 | static const char * const excnames[] = { | |
9352 | [EXCP_UDEF] = "Undefined Instruction", | |
9353 | [EXCP_SWI] = "SVC", | |
9354 | [EXCP_PREFETCH_ABORT] = "Prefetch Abort", | |
9355 | [EXCP_DATA_ABORT] = "Data Abort", | |
9356 | [EXCP_IRQ] = "IRQ", | |
9357 | [EXCP_FIQ] = "FIQ", | |
9358 | [EXCP_BKPT] = "Breakpoint", | |
9359 | [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", | |
9360 | [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", | |
9361 | [EXCP_HVC] = "Hypervisor Call", | |
9362 | [EXCP_HYP_TRAP] = "Hypervisor Trap", | |
9363 | [EXCP_SMC] = "Secure Monitor Call", | |
9364 | [EXCP_VIRQ] = "Virtual IRQ", | |
9365 | [EXCP_VFIQ] = "Virtual FIQ", | |
9366 | [EXCP_SEMIHOST] = "Semihosting call", | |
9367 | [EXCP_NOCP] = "v7M NOCP UsageFault", | |
9368 | [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", | |
9369 | [EXCP_STKOF] = "v8M STKOF UsageFault", | |
9370 | [EXCP_LAZYFP] = "v7M exception during lazy FP stacking", | |
9371 | [EXCP_LSERR] = "v8M LSERR UsageFault", | |
9372 | [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", | |
e5346292 | 9373 | [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault", |
b59f479b PMD |
9374 | }; |
9375 | ||
9376 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | |
9377 | exc = excnames[idx]; | |
9378 | } | |
9379 | if (!exc) { | |
9380 | exc = "unknown"; | |
9381 | } | |
fc6177af PM |
9382 | qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s] on CPU %d\n", |
9383 | idx, exc, cs->cpu_index); | |
b59f479b PMD |
9384 | } |
9385 | } | |
9386 | ||
a356dacf | 9387 | /* |
7aab5a8c PMD |
9388 | * Function used to synchronize QEMU's AArch64 register set with AArch32 |
9389 | * register set. This is necessary when switching between AArch32 and AArch64 | |
9390 | * execution state. | |
a356dacf | 9391 | */ |
7aab5a8c | 9392 | void aarch64_sync_32_to_64(CPUARMState *env) |
9ee6e8bb | 9393 | { |
7aab5a8c PMD |
9394 | int i; |
9395 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
9396 | ||
9397 | /* We can blanket copy R[0:7] to X[0:7] */ | |
9398 | for (i = 0; i < 8; i++) { | |
9399 | env->xregs[i] = env->regs[i]; | |
fd592d89 | 9400 | } |
70d74660 | 9401 | |
9a223097 | 9402 | /* |
7aab5a8c PMD |
9403 | * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. |
9404 | * Otherwise, they come from the banked user regs. | |
fd592d89 | 9405 | */ |
7aab5a8c PMD |
9406 | if (mode == ARM_CPU_MODE_FIQ) { |
9407 | for (i = 8; i < 13; i++) { | |
9408 | env->xregs[i] = env->usr_regs[i - 8]; | |
9409 | } | |
9410 | } else { | |
9411 | for (i = 8; i < 13; i++) { | |
9412 | env->xregs[i] = env->regs[i]; | |
9413 | } | |
fd592d89 | 9414 | } |
9ee6e8bb | 9415 | |
7aab5a8c PMD |
9416 | /* |
9417 | * Registers x13-x23 are the various mode SP and FP registers. Registers | |
9418 | * r13 and r14 are only copied if we are in that mode, otherwise we copy | |
9419 | * from the mode banked register. | |
9420 | */ | |
9421 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { | |
9422 | env->xregs[13] = env->regs[13]; | |
9423 | env->xregs[14] = env->regs[14]; | |
9424 | } else { | |
9425 | env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; | |
9426 | /* HYP is an exception in that it is copied from r14 */ | |
9427 | if (mode == ARM_CPU_MODE_HYP) { | |
9428 | env->xregs[14] = env->regs[14]; | |
95695eff | 9429 | } else { |
7aab5a8c | 9430 | env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)]; |
95695eff | 9431 | } |
95695eff PM |
9432 | } |
9433 | ||
7aab5a8c PMD |
9434 | if (mode == ARM_CPU_MODE_HYP) { |
9435 | env->xregs[15] = env->regs[13]; | |
9436 | } else { | |
9437 | env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; | |
95695eff PM |
9438 | } |
9439 | ||
7aab5a8c PMD |
9440 | if (mode == ARM_CPU_MODE_IRQ) { |
9441 | env->xregs[16] = env->regs[14]; | |
9442 | env->xregs[17] = env->regs[13]; | |
9443 | } else { | |
9444 | env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)]; | |
9445 | env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; | |
9446 | } | |
95695eff | 9447 | |
7aab5a8c PMD |
9448 | if (mode == ARM_CPU_MODE_SVC) { |
9449 | env->xregs[18] = env->regs[14]; | |
9450 | env->xregs[19] = env->regs[13]; | |
9451 | } else { | |
9452 | env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)]; | |
9453 | env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; | |
9454 | } | |
95695eff | 9455 | |
7aab5a8c PMD |
9456 | if (mode == ARM_CPU_MODE_ABT) { |
9457 | env->xregs[20] = env->regs[14]; | |
9458 | env->xregs[21] = env->regs[13]; | |
9459 | } else { | |
9460 | env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)]; | |
9461 | env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; | |
9462 | } | |
e33cf0f8 | 9463 | |
7aab5a8c PMD |
9464 | if (mode == ARM_CPU_MODE_UND) { |
9465 | env->xregs[22] = env->regs[14]; | |
9466 | env->xregs[23] = env->regs[13]; | |
9467 | } else { | |
9468 | env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)]; | |
9469 | env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; | |
e33cf0f8 PM |
9470 | } |
9471 | ||
9472 | /* | |
7aab5a8c PMD |
9473 | * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ |
9474 | * mode, then we can copy from r8-r14. Otherwise, we copy from the | |
9475 | * FIQ bank for r8-r14. | |
e33cf0f8 | 9476 | */ |
7aab5a8c PMD |
9477 | if (mode == ARM_CPU_MODE_FIQ) { |
9478 | for (i = 24; i < 31; i++) { | |
9479 | env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ | |
9480 | } | |
9481 | } else { | |
9482 | for (i = 24; i < 29; i++) { | |
9483 | env->xregs[i] = env->fiq_regs[i - 24]; | |
e33cf0f8 | 9484 | } |
7aab5a8c PMD |
9485 | env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; |
9486 | env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)]; | |
e33cf0f8 | 9487 | } |
7aab5a8c PMD |
9488 | |
9489 | env->pc = env->regs[15]; | |
e33cf0f8 PM |
9490 | } |
9491 | ||
9a223097 | 9492 | /* |
7aab5a8c PMD |
9493 | * Function used to synchronize QEMU's AArch32 register set with AArch64 |
9494 | * register set. This is necessary when switching between AArch32 and AArch64 | |
9495 | * execution state. | |
de2db7ec | 9496 | */ |
7aab5a8c | 9497 | void aarch64_sync_64_to_32(CPUARMState *env) |
9ee6e8bb | 9498 | { |
7aab5a8c PMD |
9499 | int i; |
9500 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
abc24d86 | 9501 | |
7aab5a8c PMD |
9502 | /* We can blanket copy X[0:7] to R[0:7] */ |
9503 | for (i = 0; i < 8; i++) { | |
9504 | env->regs[i] = env->xregs[i]; | |
de2db7ec | 9505 | } |
3f0cddee | 9506 | |
9a223097 | 9507 | /* |
7aab5a8c PMD |
9508 | * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. |
9509 | * Otherwise, we copy x8-x12 into the banked user regs. | |
de2db7ec | 9510 | */ |
7aab5a8c PMD |
9511 | if (mode == ARM_CPU_MODE_FIQ) { |
9512 | for (i = 8; i < 13; i++) { | |
9513 | env->usr_regs[i - 8] = env->xregs[i]; | |
9514 | } | |
9515 | } else { | |
9516 | for (i = 8; i < 13; i++) { | |
9517 | env->regs[i] = env->xregs[i]; | |
9518 | } | |
fb602cb7 PM |
9519 | } |
9520 | ||
9a223097 | 9521 | /* |
7aab5a8c PMD |
9522 | * Registers r13 & r14 depend on the current mode. |
9523 | * If we are in a given mode, we copy the corresponding x registers to r13 | |
9524 | * and r14. Otherwise, we copy the x register to the banked r13 and r14 | |
9525 | * for the mode. | |
fb602cb7 | 9526 | */ |
7aab5a8c PMD |
9527 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { |
9528 | env->regs[13] = env->xregs[13]; | |
9529 | env->regs[14] = env->xregs[14]; | |
fb602cb7 | 9530 | } else { |
7aab5a8c | 9531 | env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; |
fb602cb7 | 9532 | |
7aab5a8c PMD |
9533 | /* |
9534 | * HYP is an exception in that it does not have its own banked r14 but | |
9535 | * shares the USR r14 | |
9536 | */ | |
9537 | if (mode == ARM_CPU_MODE_HYP) { | |
9538 | env->regs[14] = env->xregs[14]; | |
9539 | } else { | |
9540 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; | |
9541 | } | |
9542 | } | |
fb602cb7 | 9543 | |
7aab5a8c PMD |
9544 | if (mode == ARM_CPU_MODE_HYP) { |
9545 | env->regs[13] = env->xregs[15]; | |
fb602cb7 | 9546 | } else { |
7aab5a8c | 9547 | env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; |
fb602cb7 | 9548 | } |
d02a8698 | 9549 | |
7aab5a8c PMD |
9550 | if (mode == ARM_CPU_MODE_IRQ) { |
9551 | env->regs[14] = env->xregs[16]; | |
9552 | env->regs[13] = env->xregs[17]; | |
d02a8698 | 9553 | } else { |
7aab5a8c PMD |
9554 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; |
9555 | env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; | |
d02a8698 PM |
9556 | } |
9557 | ||
7aab5a8c PMD |
9558 | if (mode == ARM_CPU_MODE_SVC) { |
9559 | env->regs[14] = env->xregs[18]; | |
9560 | env->regs[13] = env->xregs[19]; | |
9561 | } else { | |
9562 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; | |
9563 | env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; | |
fb602cb7 PM |
9564 | } |
9565 | ||
7aab5a8c PMD |
9566 | if (mode == ARM_CPU_MODE_ABT) { |
9567 | env->regs[14] = env->xregs[20]; | |
9568 | env->regs[13] = env->xregs[21]; | |
9569 | } else { | |
9570 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; | |
9571 | env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; | |
ce02049d GB |
9572 | } |
9573 | ||
9574 | if (mode == ARM_CPU_MODE_UND) { | |
3a9148d0 SS |
9575 | env->regs[14] = env->xregs[22]; |
9576 | env->regs[13] = env->xregs[23]; | |
ce02049d | 9577 | } else { |
593cfa2b | 9578 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; |
3a9148d0 | 9579 | env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; |
ce02049d GB |
9580 | } |
9581 | ||
9582 | /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ | |
9583 | * mode, then we can copy to r8-r14. Otherwise, we copy to the | |
9584 | * FIQ bank for r8-r14. | |
9585 | */ | |
9586 | if (mode == ARM_CPU_MODE_FIQ) { | |
9587 | for (i = 24; i < 31; i++) { | |
9588 | env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ | |
9589 | } | |
9590 | } else { | |
9591 | for (i = 24; i < 29; i++) { | |
9592 | env->fiq_regs[i - 24] = env->xregs[i]; | |
9593 | } | |
9594 | env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; | |
593cfa2b | 9595 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; |
ce02049d GB |
9596 | } |
9597 | ||
9598 | env->regs[15] = env->pc; | |
9599 | } | |
9600 | ||
dea8378b PM |
9601 | static void take_aarch32_exception(CPUARMState *env, int new_mode, |
9602 | uint32_t mask, uint32_t offset, | |
9603 | uint32_t newpc) | |
9604 | { | |
4a2696c0 RH |
9605 | int new_el; |
9606 | ||
dea8378b PM |
9607 | /* Change the CPU state so as to actually take the exception. */ |
9608 | switch_mode(env, new_mode); | |
4a2696c0 | 9609 | |
dea8378b PM |
9610 | /* |
9611 | * For exceptions taken to AArch32 we must clear the SS bit in both | |
9612 | * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. | |
9613 | */ | |
f944a854 | 9614 | env->pstate &= ~PSTATE_SS; |
dea8378b PM |
9615 | env->spsr = cpsr_read(env); |
9616 | /* Clear IT bits. */ | |
9617 | env->condexec_bits = 0; | |
9618 | /* Switch to the new mode, and to the correct instruction set. */ | |
9619 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; | |
88828bf1 CD |
9620 | |
9621 | /* This must be after mode switching. */ | |
9622 | new_el = arm_current_el(env); | |
9623 | ||
dea8378b PM |
9624 | /* Set new mode endianness */ |
9625 | env->uncached_cpsr &= ~CPSR_E; | |
4a2696c0 | 9626 | if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { |
dea8378b PM |
9627 | env->uncached_cpsr |= CPSR_E; |
9628 | } | |
829f9fd3 PM |
9629 | /* J and IL must always be cleared for exception entry */ |
9630 | env->uncached_cpsr &= ~(CPSR_IL | CPSR_J); | |
dea8378b PM |
9631 | env->daif |= mask; |
9632 | ||
f2f68a78 RC |
9633 | if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) { |
9634 | if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) { | |
9635 | env->uncached_cpsr |= CPSR_SSBS; | |
9636 | } else { | |
9637 | env->uncached_cpsr &= ~CPSR_SSBS; | |
9638 | } | |
9639 | } | |
9640 | ||
dea8378b PM |
9641 | if (new_mode == ARM_CPU_MODE_HYP) { |
9642 | env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0; | |
9643 | env->elr_el[2] = env->regs[15]; | |
9644 | } else { | |
4a2696c0 | 9645 | /* CPSR.PAN is normally preserved preserved unless... */ |
f8af1143 | 9646 | if (cpu_isar_feature(aa32_pan, env_archcpu(env))) { |
4a2696c0 RH |
9647 | switch (new_el) { |
9648 | case 3: | |
9649 | if (!arm_is_secure_below_el3(env)) { | |
9650 | /* ... the target is EL3, from non-secure state. */ | |
9651 | env->uncached_cpsr &= ~CPSR_PAN; | |
9652 | break; | |
9653 | } | |
9654 | /* ... the target is EL3, from secure state ... */ | |
9655 | /* fall through */ | |
9656 | case 1: | |
9657 | /* ... the target is EL1 and SCTLR.SPAN is 0. */ | |
9658 | if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { | |
9659 | env->uncached_cpsr |= CPSR_PAN; | |
9660 | } | |
9661 | break; | |
9662 | } | |
9663 | } | |
dea8378b PM |
9664 | /* |
9665 | * this is a lie, as there was no c1_sys on V4T/V5, but who cares | |
9666 | * and we should just guard the thumb mode on V4 | |
9667 | */ | |
9668 | if (arm_feature(env, ARM_FEATURE_V4T)) { | |
9669 | env->thumb = | |
9670 | (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; | |
9671 | } | |
9672 | env->regs[14] = env->regs[15] + offset; | |
9673 | } | |
9674 | env->regs[15] = newpc; | |
a8a79c7a | 9675 | arm_rebuild_hflags(env); |
dea8378b PM |
9676 | } |
9677 | ||
b9bc21ff PM |
9678 | static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) |
9679 | { | |
9680 | /* | |
9681 | * Handle exception entry to Hyp mode; this is sufficiently | |
9682 | * different to entry to other AArch32 modes that we handle it | |
9683 | * separately here. | |
9684 | * | |
9685 | * The vector table entry used is always the 0x14 Hyp mode entry point, | |
2c023d36 | 9686 | * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp. |
b9bc21ff PM |
9687 | * The offset applied to the preferred return address is always zero |
9688 | * (see DDI0487C.a section G1.12.3). | |
9689 | * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. | |
9690 | */ | |
9691 | uint32_t addr, mask; | |
9692 | ARMCPU *cpu = ARM_CPU(cs); | |
9693 | CPUARMState *env = &cpu->env; | |
9694 | ||
9695 | switch (cs->exception_index) { | |
9696 | case EXCP_UDEF: | |
9697 | addr = 0x04; | |
9698 | break; | |
9699 | case EXCP_SWI: | |
2c023d36 | 9700 | addr = 0x08; |
b9bc21ff PM |
9701 | break; |
9702 | case EXCP_BKPT: | |
9703 | /* Fall through to prefetch abort. */ | |
9704 | case EXCP_PREFETCH_ABORT: | |
9705 | env->cp15.ifar_s = env->exception.vaddress; | |
9706 | qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n", | |
9707 | (uint32_t)env->exception.vaddress); | |
9708 | addr = 0x0c; | |
9709 | break; | |
9710 | case EXCP_DATA_ABORT: | |
9711 | env->cp15.dfar_s = env->exception.vaddress; | |
9712 | qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n", | |
9713 | (uint32_t)env->exception.vaddress); | |
9714 | addr = 0x10; | |
9715 | break; | |
9716 | case EXCP_IRQ: | |
9717 | addr = 0x18; | |
9718 | break; | |
9719 | case EXCP_FIQ: | |
9720 | addr = 0x1c; | |
9721 | break; | |
9722 | case EXCP_HVC: | |
9723 | addr = 0x08; | |
9724 | break; | |
9725 | case EXCP_HYP_TRAP: | |
9726 | addr = 0x14; | |
9bbb4ef9 | 9727 | break; |
b9bc21ff PM |
9728 | default: |
9729 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
9730 | } | |
9731 | ||
9732 | if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) { | |
2ed08180 PM |
9733 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
9734 | /* | |
9735 | * QEMU syndrome values are v8-style. v7 has the IL bit | |
9736 | * UNK/SBZP for "field not valid" cases, where v8 uses RES1. | |
9737 | * If this is a v7 CPU, squash the IL bit in those cases. | |
9738 | */ | |
9739 | if (cs->exception_index == EXCP_PREFETCH_ABORT || | |
9740 | (cs->exception_index == EXCP_DATA_ABORT && | |
9741 | !(env->exception.syndrome & ARM_EL_ISV)) || | |
9742 | syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) { | |
9743 | env->exception.syndrome &= ~ARM_EL_IL; | |
9744 | } | |
9745 | } | |
b9bc21ff PM |
9746 | env->cp15.esr_el[2] = env->exception.syndrome; |
9747 | } | |
9748 | ||
9749 | if (arm_current_el(env) != 2 && addr < 0x14) { | |
9750 | addr = 0x14; | |
9751 | } | |
9752 | ||
9753 | mask = 0; | |
9754 | if (!(env->cp15.scr_el3 & SCR_EA)) { | |
9755 | mask |= CPSR_A; | |
9756 | } | |
9757 | if (!(env->cp15.scr_el3 & SCR_IRQ)) { | |
9758 | mask |= CPSR_I; | |
9759 | } | |
9760 | if (!(env->cp15.scr_el3 & SCR_FIQ)) { | |
9761 | mask |= CPSR_F; | |
9762 | } | |
9763 | ||
9764 | addr += env->cp15.hvbar; | |
9765 | ||
9766 | take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr); | |
9767 | } | |
9768 | ||
966f758c | 9769 | static void arm_cpu_do_interrupt_aarch32(CPUState *cs) |
b5ff1b31 | 9770 | { |
97a8ea5a AF |
9771 | ARMCPU *cpu = ARM_CPU(cs); |
9772 | CPUARMState *env = &cpu->env; | |
b5ff1b31 FB |
9773 | uint32_t addr; |
9774 | uint32_t mask; | |
9775 | int new_mode; | |
9776 | uint32_t offset; | |
16a906fd | 9777 | uint32_t moe; |
b5ff1b31 | 9778 | |
16a906fd | 9779 | /* If this is a debug exception we must update the DBGDSCR.MOE bits */ |
64b91e3f | 9780 | switch (syn_get_ec(env->exception.syndrome)) { |
16a906fd PM |
9781 | case EC_BREAKPOINT: |
9782 | case EC_BREAKPOINT_SAME_EL: | |
9783 | moe = 1; | |
9784 | break; | |
9785 | case EC_WATCHPOINT: | |
9786 | case EC_WATCHPOINT_SAME_EL: | |
9787 | moe = 10; | |
9788 | break; | |
9789 | case EC_AA32_BKPT: | |
9790 | moe = 3; | |
9791 | break; | |
9792 | case EC_VECTORCATCH: | |
9793 | moe = 5; | |
9794 | break; | |
9795 | default: | |
9796 | moe = 0; | |
9797 | break; | |
9798 | } | |
9799 | ||
9800 | if (moe) { | |
9801 | env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); | |
9802 | } | |
9803 | ||
b9bc21ff PM |
9804 | if (env->exception.target_el == 2) { |
9805 | arm_cpu_do_interrupt_aarch32_hyp(cs); | |
9806 | return; | |
9807 | } | |
9808 | ||
27103424 | 9809 | switch (cs->exception_index) { |
b5ff1b31 FB |
9810 | case EXCP_UDEF: |
9811 | new_mode = ARM_CPU_MODE_UND; | |
9812 | addr = 0x04; | |
9813 | mask = CPSR_I; | |
9814 | if (env->thumb) | |
9815 | offset = 2; | |
9816 | else | |
9817 | offset = 4; | |
9818 | break; | |
9819 | case EXCP_SWI: | |
9820 | new_mode = ARM_CPU_MODE_SVC; | |
9821 | addr = 0x08; | |
9822 | mask = CPSR_I; | |
601d70b9 | 9823 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
9824 | offset = 0; |
9825 | break; | |
06c949e6 | 9826 | case EXCP_BKPT: |
9ee6e8bb PB |
9827 | /* Fall through to prefetch abort. */ |
9828 | case EXCP_PREFETCH_ABORT: | |
88ca1c2d | 9829 | A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); |
b848ce2b | 9830 | A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); |
3f1beaca | 9831 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", |
88ca1c2d | 9832 | env->exception.fsr, (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
9833 | new_mode = ARM_CPU_MODE_ABT; |
9834 | addr = 0x0c; | |
9835 | mask = CPSR_A | CPSR_I; | |
9836 | offset = 4; | |
9837 | break; | |
9838 | case EXCP_DATA_ABORT: | |
4a7e2d73 | 9839 | A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); |
b848ce2b | 9840 | A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); |
3f1beaca | 9841 | qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", |
4a7e2d73 | 9842 | env->exception.fsr, |
6cd8a264 | 9843 | (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
9844 | new_mode = ARM_CPU_MODE_ABT; |
9845 | addr = 0x10; | |
9846 | mask = CPSR_A | CPSR_I; | |
9847 | offset = 8; | |
9848 | break; | |
9849 | case EXCP_IRQ: | |
9850 | new_mode = ARM_CPU_MODE_IRQ; | |
9851 | addr = 0x18; | |
9852 | /* Disable IRQ and imprecise data aborts. */ | |
9853 | mask = CPSR_A | CPSR_I; | |
9854 | offset = 4; | |
de38d23b FA |
9855 | if (env->cp15.scr_el3 & SCR_IRQ) { |
9856 | /* IRQ routed to monitor mode */ | |
9857 | new_mode = ARM_CPU_MODE_MON; | |
9858 | mask |= CPSR_F; | |
9859 | } | |
b5ff1b31 FB |
9860 | break; |
9861 | case EXCP_FIQ: | |
9862 | new_mode = ARM_CPU_MODE_FIQ; | |
9863 | addr = 0x1c; | |
9864 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
9865 | mask = CPSR_A | CPSR_I | CPSR_F; | |
de38d23b FA |
9866 | if (env->cp15.scr_el3 & SCR_FIQ) { |
9867 | /* FIQ routed to monitor mode */ | |
9868 | new_mode = ARM_CPU_MODE_MON; | |
9869 | } | |
b5ff1b31 FB |
9870 | offset = 4; |
9871 | break; | |
87a4b270 PM |
9872 | case EXCP_VIRQ: |
9873 | new_mode = ARM_CPU_MODE_IRQ; | |
9874 | addr = 0x18; | |
9875 | /* Disable IRQ and imprecise data aborts. */ | |
9876 | mask = CPSR_A | CPSR_I; | |
9877 | offset = 4; | |
9878 | break; | |
9879 | case EXCP_VFIQ: | |
9880 | new_mode = ARM_CPU_MODE_FIQ; | |
9881 | addr = 0x1c; | |
9882 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
9883 | mask = CPSR_A | CPSR_I | CPSR_F; | |
9884 | offset = 4; | |
9885 | break; | |
dbe9d163 FA |
9886 | case EXCP_SMC: |
9887 | new_mode = ARM_CPU_MODE_MON; | |
9888 | addr = 0x08; | |
9889 | mask = CPSR_A | CPSR_I | CPSR_F; | |
9890 | offset = 0; | |
9891 | break; | |
b5ff1b31 | 9892 | default: |
a47dddd7 | 9893 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
b5ff1b31 FB |
9894 | return; /* Never happens. Keep compiler happy. */ |
9895 | } | |
e89e51a1 FA |
9896 | |
9897 | if (new_mode == ARM_CPU_MODE_MON) { | |
9898 | addr += env->cp15.mvbar; | |
137feaa9 | 9899 | } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { |
e89e51a1 | 9900 | /* High vectors. When enabled, base address cannot be remapped. */ |
b5ff1b31 | 9901 | addr += 0xffff0000; |
8641136c NR |
9902 | } else { |
9903 | /* ARM v7 architectures provide a vector base address register to remap | |
9904 | * the interrupt vector table. | |
e89e51a1 | 9905 | * This register is only followed in non-monitor mode, and is banked. |
8641136c NR |
9906 | * Note: only bits 31:5 are valid. |
9907 | */ | |
fb6c91ba | 9908 | addr += A32_BANKED_CURRENT_REG_GET(env, vbar); |
b5ff1b31 | 9909 | } |
dbe9d163 FA |
9910 | |
9911 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
9912 | env->cp15.scr_el3 &= ~SCR_NS; | |
9913 | } | |
9914 | ||
dea8378b | 9915 | take_aarch32_exception(env, new_mode, mask, offset, addr); |
b5ff1b31 FB |
9916 | } |
9917 | ||
a65dabf7 PM |
9918 | static int aarch64_regnum(CPUARMState *env, int aarch32_reg) |
9919 | { | |
9920 | /* | |
9921 | * Return the register number of the AArch64 view of the AArch32 | |
9922 | * register @aarch32_reg. The CPUARMState CPSR is assumed to still | |
9923 | * be that of the AArch32 mode the exception came from. | |
9924 | */ | |
9925 | int mode = env->uncached_cpsr & CPSR_M; | |
9926 | ||
9927 | switch (aarch32_reg) { | |
9928 | case 0 ... 7: | |
9929 | return aarch32_reg; | |
9930 | case 8 ... 12: | |
9931 | return mode == ARM_CPU_MODE_FIQ ? aarch32_reg + 16 : aarch32_reg; | |
9932 | case 13: | |
9933 | switch (mode) { | |
9934 | case ARM_CPU_MODE_USR: | |
9935 | case ARM_CPU_MODE_SYS: | |
9936 | return 13; | |
9937 | case ARM_CPU_MODE_HYP: | |
9938 | return 15; | |
9939 | case ARM_CPU_MODE_IRQ: | |
9940 | return 17; | |
9941 | case ARM_CPU_MODE_SVC: | |
9942 | return 19; | |
9943 | case ARM_CPU_MODE_ABT: | |
9944 | return 21; | |
9945 | case ARM_CPU_MODE_UND: | |
9946 | return 23; | |
9947 | case ARM_CPU_MODE_FIQ: | |
9948 | return 29; | |
9949 | default: | |
9950 | g_assert_not_reached(); | |
9951 | } | |
9952 | case 14: | |
9953 | switch (mode) { | |
9954 | case ARM_CPU_MODE_USR: | |
9955 | case ARM_CPU_MODE_SYS: | |
9956 | case ARM_CPU_MODE_HYP: | |
9957 | return 14; | |
9958 | case ARM_CPU_MODE_IRQ: | |
9959 | return 16; | |
9960 | case ARM_CPU_MODE_SVC: | |
9961 | return 18; | |
9962 | case ARM_CPU_MODE_ABT: | |
9963 | return 20; | |
9964 | case ARM_CPU_MODE_UND: | |
9965 | return 22; | |
9966 | case ARM_CPU_MODE_FIQ: | |
9967 | return 30; | |
9968 | default: | |
9969 | g_assert_not_reached(); | |
9970 | } | |
9971 | case 15: | |
9972 | return 31; | |
9973 | default: | |
9974 | g_assert_not_reached(); | |
9975 | } | |
9976 | } | |
9977 | ||
f944a854 RC |
9978 | static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env) |
9979 | { | |
9980 | uint32_t ret = cpsr_read(env); | |
9981 | ||
9982 | /* Move DIT to the correct location for SPSR_ELx */ | |
9983 | if (ret & CPSR_DIT) { | |
9984 | ret &= ~CPSR_DIT; | |
9985 | ret |= PSTATE_DIT; | |
9986 | } | |
9987 | /* Merge PSTATE.SS into SPSR_ELx */ | |
9988 | ret |= env->pstate & PSTATE_SS; | |
9989 | ||
9990 | return ret; | |
9991 | } | |
9992 | ||
966f758c PM |
9993 | /* Handle exception entry to a target EL which is using AArch64 */ |
9994 | static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | |
f3a9b694 PM |
9995 | { |
9996 | ARMCPU *cpu = ARM_CPU(cs); | |
9997 | CPUARMState *env = &cpu->env; | |
9998 | unsigned int new_el = env->exception.target_el; | |
9999 | target_ulong addr = env->cp15.vbar_el[new_el]; | |
10000 | unsigned int new_mode = aarch64_pstate_mode(new_el, true); | |
4a2696c0 | 10001 | unsigned int old_mode; |
0ab5953b | 10002 | unsigned int cur_el = arm_current_el(env); |
a65dabf7 | 10003 | int rt; |
0ab5953b | 10004 | |
9a05f7b6 RH |
10005 | /* |
10006 | * Note that new_el can never be 0. If cur_el is 0, then | |
10007 | * el0_a64 is is_a64(), else el0_a64 is ignored. | |
10008 | */ | |
10009 | aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); | |
f3a9b694 | 10010 | |
0ab5953b | 10011 | if (cur_el < new_el) { |
3d6f7617 PM |
10012 | /* Entry vector offset depends on whether the implemented EL |
10013 | * immediately lower than the target level is using AArch32 or AArch64 | |
10014 | */ | |
10015 | bool is_aa64; | |
cb092fbb | 10016 | uint64_t hcr; |
3d6f7617 PM |
10017 | |
10018 | switch (new_el) { | |
10019 | case 3: | |
10020 | is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; | |
10021 | break; | |
10022 | case 2: | |
cb092fbb RH |
10023 | hcr = arm_hcr_el2_eff(env); |
10024 | if ((hcr & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { | |
10025 | is_aa64 = (hcr & HCR_RW) != 0; | |
10026 | break; | |
10027 | } | |
10028 | /* fall through */ | |
3d6f7617 PM |
10029 | case 1: |
10030 | is_aa64 = is_a64(env); | |
10031 | break; | |
10032 | default: | |
10033 | g_assert_not_reached(); | |
10034 | } | |
10035 | ||
10036 | if (is_aa64) { | |
f3a9b694 PM |
10037 | addr += 0x400; |
10038 | } else { | |
10039 | addr += 0x600; | |
10040 | } | |
10041 | } else if (pstate_read(env) & PSTATE_SP) { | |
10042 | addr += 0x200; | |
10043 | } | |
10044 | ||
f3a9b694 PM |
10045 | switch (cs->exception_index) { |
10046 | case EXCP_PREFETCH_ABORT: | |
10047 | case EXCP_DATA_ABORT: | |
10048 | env->cp15.far_el[new_el] = env->exception.vaddress; | |
10049 | qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", | |
10050 | env->cp15.far_el[new_el]); | |
10051 | /* fall through */ | |
10052 | case EXCP_BKPT: | |
10053 | case EXCP_UDEF: | |
10054 | case EXCP_SWI: | |
10055 | case EXCP_HVC: | |
10056 | case EXCP_HYP_TRAP: | |
10057 | case EXCP_SMC: | |
a65dabf7 PM |
10058 | switch (syn_get_ec(env->exception.syndrome)) { |
10059 | case EC_ADVSIMDFPACCESSTRAP: | |
4be42f40 PM |
10060 | /* |
10061 | * QEMU internal FP/SIMD syndromes from AArch32 include the | |
10062 | * TA and coproc fields which are only exposed if the exception | |
10063 | * is taken to AArch32 Hyp mode. Mask them out to get a valid | |
10064 | * AArch64 format syndrome. | |
10065 | */ | |
10066 | env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20); | |
a65dabf7 PM |
10067 | break; |
10068 | case EC_CP14RTTRAP: | |
10069 | case EC_CP15RTTRAP: | |
10070 | case EC_CP14DTTRAP: | |
10071 | /* | |
10072 | * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently | |
10073 | * the raw register field from the insn; when taking this to | |
10074 | * AArch64 we must convert it to the AArch64 view of the register | |
10075 | * number. Notice that we read a 4-bit AArch32 register number and | |
10076 | * write back a 5-bit AArch64 one. | |
10077 | */ | |
10078 | rt = extract32(env->exception.syndrome, 5, 4); | |
10079 | rt = aarch64_regnum(env, rt); | |
10080 | env->exception.syndrome = deposit32(env->exception.syndrome, | |
10081 | 5, 5, rt); | |
10082 | break; | |
10083 | case EC_CP15RRTTRAP: | |
10084 | case EC_CP14RRTTRAP: | |
10085 | /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */ | |
10086 | rt = extract32(env->exception.syndrome, 5, 4); | |
10087 | rt = aarch64_regnum(env, rt); | |
10088 | env->exception.syndrome = deposit32(env->exception.syndrome, | |
10089 | 5, 5, rt); | |
10090 | rt = extract32(env->exception.syndrome, 10, 4); | |
10091 | rt = aarch64_regnum(env, rt); | |
10092 | env->exception.syndrome = deposit32(env->exception.syndrome, | |
10093 | 10, 5, rt); | |
10094 | break; | |
4be42f40 | 10095 | } |
f3a9b694 PM |
10096 | env->cp15.esr_el[new_el] = env->exception.syndrome; |
10097 | break; | |
10098 | case EXCP_IRQ: | |
10099 | case EXCP_VIRQ: | |
10100 | addr += 0x80; | |
10101 | break; | |
10102 | case EXCP_FIQ: | |
10103 | case EXCP_VFIQ: | |
10104 | addr += 0x100; | |
10105 | break; | |
f3a9b694 PM |
10106 | default: |
10107 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
10108 | } | |
10109 | ||
10110 | if (is_a64(env)) { | |
4a2696c0 | 10111 | old_mode = pstate_read(env); |
f3a9b694 PM |
10112 | aarch64_save_sp(env, arm_current_el(env)); |
10113 | env->elr_el[new_el] = env->pc; | |
10114 | } else { | |
f944a854 | 10115 | old_mode = cpsr_read_for_spsr_elx(env); |
f3a9b694 PM |
10116 | env->elr_el[new_el] = env->regs[15]; |
10117 | ||
10118 | aarch64_sync_32_to_64(env); | |
10119 | ||
10120 | env->condexec_bits = 0; | |
10121 | } | |
4a2696c0 RH |
10122 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode; |
10123 | ||
f3a9b694 PM |
10124 | qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", |
10125 | env->elr_el[new_el]); | |
10126 | ||
4a2696c0 RH |
10127 | if (cpu_isar_feature(aa64_pan, cpu)) { |
10128 | /* The value of PSTATE.PAN is normally preserved, except when ... */ | |
10129 | new_mode |= old_mode & PSTATE_PAN; | |
10130 | switch (new_el) { | |
10131 | case 2: | |
10132 | /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */ | |
10133 | if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) | |
10134 | != (HCR_E2H | HCR_TGE)) { | |
10135 | break; | |
10136 | } | |
10137 | /* fall through */ | |
10138 | case 1: | |
10139 | /* ... the target is EL1 ... */ | |
10140 | /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */ | |
10141 | if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) == 0) { | |
10142 | new_mode |= PSTATE_PAN; | |
10143 | } | |
10144 | break; | |
10145 | } | |
10146 | } | |
34669338 RH |
10147 | if (cpu_isar_feature(aa64_mte, cpu)) { |
10148 | new_mode |= PSTATE_TCO; | |
10149 | } | |
4a2696c0 | 10150 | |
f2f68a78 RC |
10151 | if (cpu_isar_feature(aa64_ssbs, cpu)) { |
10152 | if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) { | |
10153 | new_mode |= PSTATE_SSBS; | |
10154 | } else { | |
10155 | new_mode &= ~PSTATE_SSBS; | |
10156 | } | |
10157 | } | |
10158 | ||
f3a9b694 PM |
10159 | pstate_write(env, PSTATE_DAIF | new_mode); |
10160 | env->aarch64 = 1; | |
10161 | aarch64_restore_sp(env, new_el); | |
a8a79c7a | 10162 | helper_rebuild_hflags_a64(env, new_el); |
f3a9b694 PM |
10163 | |
10164 | env->pc = addr; | |
10165 | ||
10166 | qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", | |
10167 | new_el, env->pc, pstate_read(env)); | |
966f758c PM |
10168 | } |
10169 | ||
ed6e6ba9 AB |
10170 | /* |
10171 | * Do semihosting call and set the appropriate return value. All the | |
10172 | * permission and validity checks have been done at translate time. | |
10173 | * | |
10174 | * We only see semihosting exceptions in TCG only as they are not | |
10175 | * trapped to the hypervisor in KVM. | |
10176 | */ | |
91f78c58 | 10177 | #ifdef CONFIG_TCG |
ed6e6ba9 AB |
10178 | static void handle_semihosting(CPUState *cs) |
10179 | { | |
904c04de PM |
10180 | ARMCPU *cpu = ARM_CPU(cs); |
10181 | CPUARMState *env = &cpu->env; | |
10182 | ||
10183 | if (is_a64(env)) { | |
ed6e6ba9 AB |
10184 | qemu_log_mask(CPU_LOG_INT, |
10185 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
10186 | env->xregs[0]); | |
0bb446d8 | 10187 | env->xregs[0] = do_common_semihosting(cs); |
4ff5ef9e | 10188 | env->pc += 4; |
904c04de | 10189 | } else { |
904c04de PM |
10190 | qemu_log_mask(CPU_LOG_INT, |
10191 | "...handling as semihosting call 0x%x\n", | |
10192 | env->regs[0]); | |
0bb446d8 | 10193 | env->regs[0] = do_common_semihosting(cs); |
4ff5ef9e | 10194 | env->regs[15] += env->thumb ? 2 : 4; |
904c04de PM |
10195 | } |
10196 | } | |
ed6e6ba9 | 10197 | #endif |
904c04de | 10198 | |
966f758c PM |
10199 | /* Handle a CPU exception for A and R profile CPUs. |
10200 | * Do any appropriate logging, handle PSCI calls, and then hand off | |
10201 | * to the AArch64-entry or AArch32-entry function depending on the | |
10202 | * target exception level's register width. | |
853bfef4 CF |
10203 | * |
10204 | * Note: this is used for both TCG (as the do_interrupt tcg op), | |
10205 | * and KVM to re-inject guest debug exceptions, and to | |
10206 | * inject a Synchronous-External-Abort. | |
966f758c PM |
10207 | */ |
10208 | void arm_cpu_do_interrupt(CPUState *cs) | |
10209 | { | |
10210 | ARMCPU *cpu = ARM_CPU(cs); | |
10211 | CPUARMState *env = &cpu->env; | |
10212 | unsigned int new_el = env->exception.target_el; | |
10213 | ||
531c60a9 | 10214 | assert(!arm_feature(env, ARM_FEATURE_M)); |
966f758c | 10215 | |
fc6177af | 10216 | arm_log_exception(cs); |
966f758c PM |
10217 | qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), |
10218 | new_el); | |
10219 | if (qemu_loglevel_mask(CPU_LOG_INT) | |
10220 | && !excp_is_internal(cs->exception_index)) { | |
6568da45 | 10221 | qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", |
64b91e3f | 10222 | syn_get_ec(env->exception.syndrome), |
966f758c PM |
10223 | env->exception.syndrome); |
10224 | } | |
10225 | ||
10226 | if (arm_is_psci_call(cpu, cs->exception_index)) { | |
10227 | arm_handle_psci_call(cpu); | |
10228 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | |
10229 | return; | |
10230 | } | |
10231 | ||
ed6e6ba9 AB |
10232 | /* |
10233 | * Semihosting semantics depend on the register width of the code | |
10234 | * that caused the exception, not the target exception level, so | |
10235 | * must be handled here. | |
966f758c | 10236 | */ |
ed6e6ba9 AB |
10237 | #ifdef CONFIG_TCG |
10238 | if (cs->exception_index == EXCP_SEMIHOST) { | |
10239 | handle_semihosting(cs); | |
904c04de PM |
10240 | return; |
10241 | } | |
ed6e6ba9 | 10242 | #endif |
904c04de | 10243 | |
b5c53d1b AL |
10244 | /* Hooks may change global state so BQL should be held, also the |
10245 | * BQL needs to be held for any modification of | |
10246 | * cs->interrupt_request. | |
10247 | */ | |
10248 | g_assert(qemu_mutex_iothread_locked()); | |
10249 | ||
10250 | arm_call_pre_el_change_hook(cpu); | |
10251 | ||
904c04de PM |
10252 | assert(!excp_is_internal(cs->exception_index)); |
10253 | if (arm_el_is_aa64(env, new_el)) { | |
966f758c PM |
10254 | arm_cpu_do_interrupt_aarch64(cs); |
10255 | } else { | |
10256 | arm_cpu_do_interrupt_aarch32(cs); | |
10257 | } | |
f3a9b694 | 10258 | |
bd7d00fc PM |
10259 | arm_call_el_change_hook(cpu); |
10260 | ||
f3a9b694 PM |
10261 | if (!kvm_enabled()) { |
10262 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
10263 | } | |
10264 | } | |
c47eaf9f | 10265 | #endif /* !CONFIG_USER_ONLY */ |
0480f69a | 10266 | |
aaec1432 RH |
10267 | uint64_t arm_sctlr(CPUARMState *env, int el) |
10268 | { | |
10269 | /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ | |
10270 | if (el == 0) { | |
10271 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0); | |
b6ad6062 RDC |
10272 | el = (mmu_idx == ARMMMUIdx_E20_0 || mmu_idx == ARMMMUIdx_SE20_0) |
10273 | ? 2 : 1; | |
aaec1432 RH |
10274 | } |
10275 | return env->cp15.sctlr_el[el]; | |
10276 | } | |
c47eaf9f | 10277 | |
0480f69a | 10278 | /* Return the SCTLR value which controls this address translation regime */ |
aaec1432 | 10279 | static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) |
0480f69a PM |
10280 | { |
10281 | return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; | |
10282 | } | |
10283 | ||
aaec1432 RH |
10284 | #ifndef CONFIG_USER_ONLY |
10285 | ||
0480f69a PM |
10286 | /* Return true if the specified stage of address translation is disabled */ |
10287 | static inline bool regime_translation_disabled(CPUARMState *env, | |
10288 | ARMMMUIdx mmu_idx) | |
10289 | { | |
e04a5752 RDC |
10290 | uint64_t hcr_el2; |
10291 | ||
29c483a5 | 10292 | if (arm_feature(env, ARM_FEATURE_M)) { |
ecf5e8ea | 10293 | switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & |
3bef7012 PM |
10294 | (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { |
10295 | case R_V7M_MPU_CTRL_ENABLE_MASK: | |
10296 | /* Enabled, but not for HardFault and NMI */ | |
62593718 | 10297 | return mmu_idx & ARM_MMU_IDX_M_NEGPRI; |
3bef7012 PM |
10298 | case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: |
10299 | /* Enabled for all cases */ | |
10300 | return false; | |
10301 | case 0: | |
10302 | default: | |
10303 | /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but | |
10304 | * we warned about that in armv7m_nvic.c when the guest set it. | |
10305 | */ | |
10306 | return true; | |
10307 | } | |
29c483a5 MD |
10308 | } |
10309 | ||
e04a5752 RDC |
10310 | hcr_el2 = arm_hcr_el2_eff(env); |
10311 | ||
b1a10c86 | 10312 | if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { |
9d1bab33 | 10313 | /* HCR.DC means HCR.VM behaves as 1 */ |
e04a5752 | 10314 | return (hcr_el2 & (HCR_DC | HCR_VM)) == 0; |
0480f69a | 10315 | } |
3d0e3080 | 10316 | |
e04a5752 | 10317 | if (hcr_el2 & HCR_TGE) { |
3d0e3080 PM |
10318 | /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ |
10319 | if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) { | |
10320 | return true; | |
10321 | } | |
10322 | } | |
10323 | ||
e04a5752 | 10324 | if ((hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { |
9d1bab33 PM |
10325 | /* HCR.DC means SCTLR_EL1.M behaves as 0 */ |
10326 | return true; | |
10327 | } | |
10328 | ||
0480f69a PM |
10329 | return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; |
10330 | } | |
10331 | ||
73462ddd PC |
10332 | static inline bool regime_translation_big_endian(CPUARMState *env, |
10333 | ARMMMUIdx mmu_idx) | |
10334 | { | |
10335 | return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; | |
10336 | } | |
10337 | ||
c47eaf9f PM |
10338 | /* Return the TTBR associated with this translation regime */ |
10339 | static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, | |
10340 | int ttbrn) | |
10341 | { | |
97fa9350 | 10342 | if (mmu_idx == ARMMMUIdx_Stage2) { |
c47eaf9f PM |
10343 | return env->cp15.vttbr_el2; |
10344 | } | |
b1a10c86 RDC |
10345 | if (mmu_idx == ARMMMUIdx_Stage2_S) { |
10346 | return env->cp15.vsttbr_el2; | |
10347 | } | |
c47eaf9f PM |
10348 | if (ttbrn == 0) { |
10349 | return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; | |
10350 | } else { | |
10351 | return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; | |
10352 | } | |
10353 | } | |
10354 | ||
10355 | #endif /* !CONFIG_USER_ONLY */ | |
10356 | ||
8bd5c820 PM |
10357 | /* Convert a possible stage1+2 MMU index into the appropriate |
10358 | * stage 1 MMU index | |
10359 | */ | |
10360 | static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) | |
10361 | { | |
b9f6033c | 10362 | switch (mmu_idx) { |
b1a10c86 RDC |
10363 | case ARMMMUIdx_SE10_0: |
10364 | return ARMMMUIdx_Stage1_SE0; | |
10365 | case ARMMMUIdx_SE10_1: | |
10366 | return ARMMMUIdx_Stage1_SE1; | |
10367 | case ARMMMUIdx_SE10_1_PAN: | |
10368 | return ARMMMUIdx_Stage1_SE1_PAN; | |
b9f6033c RH |
10369 | case ARMMMUIdx_E10_0: |
10370 | return ARMMMUIdx_Stage1_E0; | |
10371 | case ARMMMUIdx_E10_1: | |
10372 | return ARMMMUIdx_Stage1_E1; | |
452ef8cb RH |
10373 | case ARMMMUIdx_E10_1_PAN: |
10374 | return ARMMMUIdx_Stage1_E1_PAN; | |
b9f6033c RH |
10375 | default: |
10376 | return mmu_idx; | |
8bd5c820 | 10377 | } |
8bd5c820 PM |
10378 | } |
10379 | ||
0480f69a PM |
10380 | /* Return true if the translation regime is using LPAE format page tables */ |
10381 | static inline bool regime_using_lpae_format(CPUARMState *env, | |
10382 | ARMMMUIdx mmu_idx) | |
10383 | { | |
10384 | int el = regime_el(env, mmu_idx); | |
10385 | if (el == 2 || arm_el_is_aa64(env, el)) { | |
10386 | return true; | |
10387 | } | |
10388 | if (arm_feature(env, ARM_FEATURE_LPAE) | |
10389 | && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { | |
10390 | return true; | |
10391 | } | |
10392 | return false; | |
10393 | } | |
10394 | ||
deb2db99 AR |
10395 | /* Returns true if the stage 1 translation regime is using LPAE format page |
10396 | * tables. Used when raising alignment exceptions, whose FSR changes depending | |
10397 | * on whether the long or short descriptor format is in use. */ | |
10398 | bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) | |
30901475 | 10399 | { |
8bd5c820 | 10400 | mmu_idx = stage_1_mmu_idx(mmu_idx); |
deb2db99 | 10401 | |
30901475 AB |
10402 | return regime_using_lpae_format(env, mmu_idx); |
10403 | } | |
10404 | ||
c47eaf9f | 10405 | #ifndef CONFIG_USER_ONLY |
0480f69a PM |
10406 | static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) |
10407 | { | |
10408 | switch (mmu_idx) { | |
fba37aed | 10409 | case ARMMMUIdx_SE10_0: |
b9f6033c | 10410 | case ARMMMUIdx_E20_0: |
b6ad6062 | 10411 | case ARMMMUIdx_SE20_0: |
2859d7b5 | 10412 | case ARMMMUIdx_Stage1_E0: |
b1a10c86 | 10413 | case ARMMMUIdx_Stage1_SE0: |
e7b921c2 | 10414 | case ARMMMUIdx_MUser: |
871bec7c | 10415 | case ARMMMUIdx_MSUser: |
62593718 PM |
10416 | case ARMMMUIdx_MUserNegPri: |
10417 | case ARMMMUIdx_MSUserNegPri: | |
0480f69a PM |
10418 | return true; |
10419 | default: | |
10420 | return false; | |
01b98b68 RH |
10421 | case ARMMMUIdx_E10_0: |
10422 | case ARMMMUIdx_E10_1: | |
452ef8cb | 10423 | case ARMMMUIdx_E10_1_PAN: |
0480f69a PM |
10424 | g_assert_not_reached(); |
10425 | } | |
10426 | } | |
10427 | ||
0fbf5238 AJ |
10428 | /* Translate section/page access permissions to page |
10429 | * R/W protection flags | |
d76951b6 AJ |
10430 | * |
10431 | * @env: CPUARMState | |
10432 | * @mmu_idx: MMU index indicating required translation regime | |
10433 | * @ap: The 3-bit access permissions (AP[2:0]) | |
10434 | * @domain_prot: The 2-bit domain access permissions | |
0fbf5238 AJ |
10435 | */ |
10436 | static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, | |
10437 | int ap, int domain_prot) | |
10438 | { | |
554b0b09 PM |
10439 | bool is_user = regime_is_user(env, mmu_idx); |
10440 | ||
10441 | if (domain_prot == 3) { | |
10442 | return PAGE_READ | PAGE_WRITE; | |
10443 | } | |
10444 | ||
554b0b09 PM |
10445 | switch (ap) { |
10446 | case 0: | |
10447 | if (arm_feature(env, ARM_FEATURE_V7)) { | |
10448 | return 0; | |
10449 | } | |
554b0b09 PM |
10450 | switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) { |
10451 | case SCTLR_S: | |
10452 | return is_user ? 0 : PAGE_READ; | |
10453 | case SCTLR_R: | |
10454 | return PAGE_READ; | |
10455 | default: | |
10456 | return 0; | |
10457 | } | |
10458 | case 1: | |
10459 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
10460 | case 2: | |
87c3d486 | 10461 | if (is_user) { |
0fbf5238 | 10462 | return PAGE_READ; |
87c3d486 | 10463 | } else { |
554b0b09 | 10464 | return PAGE_READ | PAGE_WRITE; |
87c3d486 | 10465 | } |
554b0b09 PM |
10466 | case 3: |
10467 | return PAGE_READ | PAGE_WRITE; | |
10468 | case 4: /* Reserved. */ | |
10469 | return 0; | |
10470 | case 5: | |
0fbf5238 | 10471 | return is_user ? 0 : PAGE_READ; |
554b0b09 | 10472 | case 6: |
0fbf5238 | 10473 | return PAGE_READ; |
554b0b09 | 10474 | case 7: |
87c3d486 | 10475 | if (!arm_feature(env, ARM_FEATURE_V6K)) { |
554b0b09 | 10476 | return 0; |
87c3d486 | 10477 | } |
0fbf5238 | 10478 | return PAGE_READ; |
554b0b09 | 10479 | default: |
0fbf5238 | 10480 | g_assert_not_reached(); |
554b0b09 | 10481 | } |
b5ff1b31 FB |
10482 | } |
10483 | ||
d76951b6 AJ |
10484 | /* Translate section/page access permissions to page |
10485 | * R/W protection flags. | |
10486 | * | |
d76951b6 | 10487 | * @ap: The 2-bit simple AP (AP[2:1]) |
d8e052b3 | 10488 | * @is_user: TRUE if accessing from PL0 |
d76951b6 | 10489 | */ |
d8e052b3 | 10490 | static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user) |
d76951b6 | 10491 | { |
d76951b6 AJ |
10492 | switch (ap) { |
10493 | case 0: | |
10494 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
10495 | case 1: | |
10496 | return PAGE_READ | PAGE_WRITE; | |
10497 | case 2: | |
10498 | return is_user ? 0 : PAGE_READ; | |
10499 | case 3: | |
10500 | return PAGE_READ; | |
10501 | default: | |
10502 | g_assert_not_reached(); | |
10503 | } | |
10504 | } | |
10505 | ||
d8e052b3 AJ |
10506 | static inline int |
10507 | simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) | |
10508 | { | |
10509 | return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); | |
10510 | } | |
10511 | ||
6ab1a5ee EI |
10512 | /* Translate S2 section/page access permissions to protection flags |
10513 | * | |
10514 | * @env: CPUARMState | |
10515 | * @s2ap: The 2-bit stage2 access permissions (S2AP) | |
ce3125be PM |
10516 | * @xn: XN (execute-never) bits |
10517 | * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0 | |
6ab1a5ee | 10518 | */ |
ce3125be | 10519 | static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) |
6ab1a5ee EI |
10520 | { |
10521 | int prot = 0; | |
10522 | ||
10523 | if (s2ap & 1) { | |
10524 | prot |= PAGE_READ; | |
10525 | } | |
10526 | if (s2ap & 2) { | |
10527 | prot |= PAGE_WRITE; | |
10528 | } | |
ce3125be PM |
10529 | |
10530 | if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) { | |
10531 | switch (xn) { | |
10532 | case 0: | |
dfda6837 | 10533 | prot |= PAGE_EXEC; |
ce3125be PM |
10534 | break; |
10535 | case 1: | |
10536 | if (s1_is_el0) { | |
10537 | prot |= PAGE_EXEC; | |
10538 | } | |
10539 | break; | |
10540 | case 2: | |
10541 | break; | |
10542 | case 3: | |
10543 | if (!s1_is_el0) { | |
10544 | prot |= PAGE_EXEC; | |
10545 | } | |
10546 | break; | |
10547 | default: | |
10548 | g_assert_not_reached(); | |
10549 | } | |
10550 | } else { | |
10551 | if (!extract32(xn, 1, 1)) { | |
10552 | if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { | |
10553 | prot |= PAGE_EXEC; | |
10554 | } | |
dfda6837 | 10555 | } |
6ab1a5ee EI |
10556 | } |
10557 | return prot; | |
10558 | } | |
10559 | ||
d8e052b3 AJ |
10560 | /* Translate section/page access permissions to protection flags |
10561 | * | |
10562 | * @env: CPUARMState | |
10563 | * @mmu_idx: MMU index indicating required translation regime | |
10564 | * @is_aa64: TRUE if AArch64 | |
10565 | * @ap: The 2-bit simple AP (AP[2:1]) | |
10566 | * @ns: NS (non-secure) bit | |
10567 | * @xn: XN (execute-never) bit | |
10568 | * @pxn: PXN (privileged execute-never) bit | |
10569 | */ | |
10570 | static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, | |
10571 | int ap, int ns, int xn, int pxn) | |
10572 | { | |
10573 | bool is_user = regime_is_user(env, mmu_idx); | |
10574 | int prot_rw, user_rw; | |
10575 | bool have_wxn; | |
10576 | int wxn = 0; | |
10577 | ||
97fa9350 | 10578 | assert(mmu_idx != ARMMMUIdx_Stage2); |
b1a10c86 | 10579 | assert(mmu_idx != ARMMMUIdx_Stage2_S); |
d8e052b3 AJ |
10580 | |
10581 | user_rw = simple_ap_to_rw_prot_is_user(ap, true); | |
10582 | if (is_user) { | |
10583 | prot_rw = user_rw; | |
10584 | } else { | |
81636b70 | 10585 | if (user_rw && regime_is_pan(env, mmu_idx)) { |
f4e1dbc5 PM |
10586 | /* PAN forbids data accesses but doesn't affect insn fetch */ |
10587 | prot_rw = 0; | |
10588 | } else { | |
10589 | prot_rw = simple_ap_to_rw_prot_is_user(ap, false); | |
81636b70 | 10590 | } |
d8e052b3 AJ |
10591 | } |
10592 | ||
10593 | if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { | |
10594 | return prot_rw; | |
10595 | } | |
10596 | ||
10597 | /* TODO have_wxn should be replaced with | |
10598 | * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) | |
10599 | * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE | |
10600 | * compatible processors have EL2, which is required for [U]WXN. | |
10601 | */ | |
10602 | have_wxn = arm_feature(env, ARM_FEATURE_LPAE); | |
10603 | ||
10604 | if (have_wxn) { | |
10605 | wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN; | |
10606 | } | |
10607 | ||
10608 | if (is_aa64) { | |
339370b9 RH |
10609 | if (regime_has_2_ranges(mmu_idx) && !is_user) { |
10610 | xn = pxn || (user_rw & PAGE_WRITE); | |
d8e052b3 AJ |
10611 | } |
10612 | } else if (arm_feature(env, ARM_FEATURE_V7)) { | |
10613 | switch (regime_el(env, mmu_idx)) { | |
10614 | case 1: | |
10615 | case 3: | |
10616 | if (is_user) { | |
10617 | xn = xn || !(user_rw & PAGE_READ); | |
10618 | } else { | |
10619 | int uwxn = 0; | |
10620 | if (have_wxn) { | |
10621 | uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN; | |
10622 | } | |
10623 | xn = xn || !(prot_rw & PAGE_READ) || pxn || | |
10624 | (uwxn && (user_rw & PAGE_WRITE)); | |
10625 | } | |
10626 | break; | |
10627 | case 2: | |
10628 | break; | |
10629 | } | |
10630 | } else { | |
10631 | xn = wxn = 0; | |
10632 | } | |
10633 | ||
10634 | if (xn || (wxn && (prot_rw & PAGE_WRITE))) { | |
10635 | return prot_rw; | |
10636 | } | |
10637 | return prot_rw | PAGE_EXEC; | |
10638 | } | |
10639 | ||
0480f69a PM |
10640 | static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, |
10641 | uint32_t *table, uint32_t address) | |
b2fa1797 | 10642 | { |
0480f69a | 10643 | /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ |
0480f69a | 10644 | TCR *tcr = regime_tcr(env, mmu_idx); |
11f136ee | 10645 | |
11f136ee FA |
10646 | if (address & tcr->mask) { |
10647 | if (tcr->raw_tcr & TTBCR_PD1) { | |
e389be16 FA |
10648 | /* Translation table walk disabled for TTBR1 */ |
10649 | return false; | |
10650 | } | |
aef878be | 10651 | *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; |
e389be16 | 10652 | } else { |
11f136ee | 10653 | if (tcr->raw_tcr & TTBCR_PD0) { |
e389be16 FA |
10654 | /* Translation table walk disabled for TTBR0 */ |
10655 | return false; | |
10656 | } | |
aef878be | 10657 | *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; |
e389be16 FA |
10658 | } |
10659 | *table |= (address >> 18) & 0x3ffc; | |
10660 | return true; | |
b2fa1797 PB |
10661 | } |
10662 | ||
37785977 EI |
10663 | /* Translate a S1 pagetable walk through S2 if needed. */ |
10664 | static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, | |
3d4bd397 | 10665 | hwaddr addr, bool *is_secure, |
37785977 EI |
10666 | ARMMMUFaultInfo *fi) |
10667 | { | |
fee7aa46 | 10668 | if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && |
97fa9350 | 10669 | !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { |
37785977 EI |
10670 | target_ulong s2size; |
10671 | hwaddr s2pa; | |
10672 | int s2prot; | |
10673 | int ret; | |
b1a10c86 RDC |
10674 | ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S |
10675 | : ARMMMUIdx_Stage2; | |
eadb2feb | 10676 | ARMCacheAttrs cacheattrs = {}; |
3d4bd397 RDC |
10677 | MemTxAttrs txattrs = {}; |
10678 | ||
b1a10c86 | 10679 | ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false, |
59dff859 | 10680 | &s2pa, &txattrs, &s2prot, &s2size, fi, |
a6d6f37a | 10681 | &cacheattrs); |
37785977 | 10682 | if (ret) { |
3b39d734 | 10683 | assert(fi->type != ARMFault_None); |
37785977 EI |
10684 | fi->s2addr = addr; |
10685 | fi->stage2 = true; | |
10686 | fi->s1ptw = true; | |
9861248f | 10687 | fi->s1ns = !*is_secure; |
37785977 EI |
10688 | return ~0; |
10689 | } | |
e04a5752 RDC |
10690 | if ((arm_hcr_el2_eff(env) & HCR_PTW) && |
10691 | (cacheattrs.attrs & 0xf0) == 0) { | |
a6d6f37a RH |
10692 | /* |
10693 | * PTW set and S1 walk touched S2 Device memory: | |
10694 | * generate Permission fault. | |
10695 | */ | |
eadb2feb PM |
10696 | fi->type = ARMFault_Permission; |
10697 | fi->s2addr = addr; | |
10698 | fi->stage2 = true; | |
10699 | fi->s1ptw = true; | |
9861248f | 10700 | fi->s1ns = !*is_secure; |
eadb2feb PM |
10701 | return ~0; |
10702 | } | |
588c6dd1 RDC |
10703 | |
10704 | if (arm_is_secure_below_el3(env)) { | |
10705 | /* Check if page table walk is to secure or non-secure PA space. */ | |
10706 | if (*is_secure) { | |
10707 | *is_secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); | |
10708 | } else { | |
10709 | *is_secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); | |
10710 | } | |
10711 | } else { | |
10712 | assert(!*is_secure); | |
10713 | } | |
10714 | ||
37785977 EI |
10715 | addr = s2pa; |
10716 | } | |
10717 | return addr; | |
10718 | } | |
10719 | ||
14577270 | 10720 | /* All loads done in the course of a page table walk go through here. */ |
a614e698 | 10721 | static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, |
3795a6de | 10722 | ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) |
ebca90e4 | 10723 | { |
a614e698 EI |
10724 | ARMCPU *cpu = ARM_CPU(cs); |
10725 | CPUARMState *env = &cpu->env; | |
ebca90e4 | 10726 | MemTxAttrs attrs = {}; |
3b39d734 | 10727 | MemTxResult result = MEMTX_OK; |
5ce4ff65 | 10728 | AddressSpace *as; |
3b39d734 | 10729 | uint32_t data; |
ebca90e4 | 10730 | |
3d4bd397 | 10731 | addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); |
ebca90e4 | 10732 | attrs.secure = is_secure; |
5ce4ff65 | 10733 | as = arm_addressspace(cs, attrs); |
a614e698 EI |
10734 | if (fi->s1ptw) { |
10735 | return 0; | |
10736 | } | |
73462ddd | 10737 | if (regime_translation_big_endian(env, mmu_idx)) { |
3b39d734 | 10738 | data = address_space_ldl_be(as, addr, attrs, &result); |
73462ddd | 10739 | } else { |
3b39d734 | 10740 | data = address_space_ldl_le(as, addr, attrs, &result); |
73462ddd | 10741 | } |
3b39d734 PM |
10742 | if (result == MEMTX_OK) { |
10743 | return data; | |
10744 | } | |
10745 | fi->type = ARMFault_SyncExternalOnWalk; | |
10746 | fi->ea = arm_extabort_type(result); | |
10747 | return 0; | |
ebca90e4 PM |
10748 | } |
10749 | ||
37785977 | 10750 | static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, |
3795a6de | 10751 | ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) |
ebca90e4 | 10752 | { |
37785977 EI |
10753 | ARMCPU *cpu = ARM_CPU(cs); |
10754 | CPUARMState *env = &cpu->env; | |
ebca90e4 | 10755 | MemTxAttrs attrs = {}; |
3b39d734 | 10756 | MemTxResult result = MEMTX_OK; |
5ce4ff65 | 10757 | AddressSpace *as; |
9aea1ea3 | 10758 | uint64_t data; |
ebca90e4 | 10759 | |
3d4bd397 | 10760 | addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); |
ebca90e4 | 10761 | attrs.secure = is_secure; |
5ce4ff65 | 10762 | as = arm_addressspace(cs, attrs); |
37785977 EI |
10763 | if (fi->s1ptw) { |
10764 | return 0; | |
10765 | } | |
73462ddd | 10766 | if (regime_translation_big_endian(env, mmu_idx)) { |
3b39d734 | 10767 | data = address_space_ldq_be(as, addr, attrs, &result); |
73462ddd | 10768 | } else { |
3b39d734 PM |
10769 | data = address_space_ldq_le(as, addr, attrs, &result); |
10770 | } | |
10771 | if (result == MEMTX_OK) { | |
10772 | return data; | |
73462ddd | 10773 | } |
3b39d734 PM |
10774 | fi->type = ARMFault_SyncExternalOnWalk; |
10775 | fi->ea = arm_extabort_type(result); | |
10776 | return 0; | |
ebca90e4 PM |
10777 | } |
10778 | ||
b7cc4e82 | 10779 | static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, |
03ae85f8 | 10780 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
b7cc4e82 | 10781 | hwaddr *phys_ptr, int *prot, |
f989983e | 10782 | target_ulong *page_size, |
e14b5a23 | 10783 | ARMMMUFaultInfo *fi) |
b5ff1b31 | 10784 | { |
2fc0cc0e | 10785 | CPUState *cs = env_cpu(env); |
f989983e | 10786 | int level = 1; |
b5ff1b31 FB |
10787 | uint32_t table; |
10788 | uint32_t desc; | |
10789 | int type; | |
10790 | int ap; | |
e389be16 | 10791 | int domain = 0; |
dd4ebc2e | 10792 | int domain_prot; |
a8170e5e | 10793 | hwaddr phys_addr; |
0480f69a | 10794 | uint32_t dacr; |
b5ff1b31 | 10795 | |
9ee6e8bb PB |
10796 | /* Pagetable walk. */ |
10797 | /* Lookup l1 descriptor. */ | |
0480f69a | 10798 | if (!get_level1_table_address(env, mmu_idx, &table, address)) { |
e389be16 | 10799 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ |
f989983e | 10800 | fi->type = ARMFault_Translation; |
e389be16 FA |
10801 | goto do_fault; |
10802 | } | |
a614e698 | 10803 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 10804 | mmu_idx, fi); |
3b39d734 PM |
10805 | if (fi->type != ARMFault_None) { |
10806 | goto do_fault; | |
10807 | } | |
9ee6e8bb | 10808 | type = (desc & 3); |
dd4ebc2e | 10809 | domain = (desc >> 5) & 0x0f; |
0480f69a PM |
10810 | if (regime_el(env, mmu_idx) == 1) { |
10811 | dacr = env->cp15.dacr_ns; | |
10812 | } else { | |
10813 | dacr = env->cp15.dacr_s; | |
10814 | } | |
10815 | domain_prot = (dacr >> (domain * 2)) & 3; | |
9ee6e8bb | 10816 | if (type == 0) { |
601d70b9 | 10817 | /* Section translation fault. */ |
f989983e | 10818 | fi->type = ARMFault_Translation; |
9ee6e8bb PB |
10819 | goto do_fault; |
10820 | } | |
f989983e PM |
10821 | if (type != 2) { |
10822 | level = 2; | |
10823 | } | |
dd4ebc2e | 10824 | if (domain_prot == 0 || domain_prot == 2) { |
f989983e | 10825 | fi->type = ARMFault_Domain; |
9ee6e8bb PB |
10826 | goto do_fault; |
10827 | } | |
10828 | if (type == 2) { | |
10829 | /* 1Mb section. */ | |
10830 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
10831 | ap = (desc >> 10) & 3; | |
d4c430a8 | 10832 | *page_size = 1024 * 1024; |
9ee6e8bb PB |
10833 | } else { |
10834 | /* Lookup l2 entry. */ | |
554b0b09 PM |
10835 | if (type == 1) { |
10836 | /* Coarse pagetable. */ | |
10837 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
10838 | } else { | |
10839 | /* Fine pagetable. */ | |
10840 | table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); | |
10841 | } | |
a614e698 | 10842 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 10843 | mmu_idx, fi); |
3b39d734 PM |
10844 | if (fi->type != ARMFault_None) { |
10845 | goto do_fault; | |
10846 | } | |
9ee6e8bb PB |
10847 | switch (desc & 3) { |
10848 | case 0: /* Page translation fault. */ | |
f989983e | 10849 | fi->type = ARMFault_Translation; |
9ee6e8bb PB |
10850 | goto do_fault; |
10851 | case 1: /* 64k page. */ | |
10852 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
10853 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
d4c430a8 | 10854 | *page_size = 0x10000; |
ce819861 | 10855 | break; |
9ee6e8bb PB |
10856 | case 2: /* 4k page. */ |
10857 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
c10f7fc3 | 10858 | ap = (desc >> (4 + ((address >> 9) & 6))) & 3; |
d4c430a8 | 10859 | *page_size = 0x1000; |
ce819861 | 10860 | break; |
fc1891c7 | 10861 | case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ |
554b0b09 | 10862 | if (type == 1) { |
fc1891c7 PM |
10863 | /* ARMv6/XScale extended small page format */ |
10864 | if (arm_feature(env, ARM_FEATURE_XSCALE) | |
10865 | || arm_feature(env, ARM_FEATURE_V6)) { | |
554b0b09 | 10866 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
fc1891c7 | 10867 | *page_size = 0x1000; |
554b0b09 | 10868 | } else { |
fc1891c7 PM |
10869 | /* UNPREDICTABLE in ARMv5; we choose to take a |
10870 | * page translation fault. | |
10871 | */ | |
f989983e | 10872 | fi->type = ARMFault_Translation; |
554b0b09 PM |
10873 | goto do_fault; |
10874 | } | |
10875 | } else { | |
10876 | phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); | |
fc1891c7 | 10877 | *page_size = 0x400; |
554b0b09 | 10878 | } |
9ee6e8bb | 10879 | ap = (desc >> 4) & 3; |
ce819861 PB |
10880 | break; |
10881 | default: | |
9ee6e8bb PB |
10882 | /* Never happens, but compiler isn't smart enough to tell. */ |
10883 | abort(); | |
ce819861 | 10884 | } |
9ee6e8bb | 10885 | } |
0fbf5238 AJ |
10886 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); |
10887 | *prot |= *prot ? PAGE_EXEC : 0; | |
10888 | if (!(*prot & (1 << access_type))) { | |
9ee6e8bb | 10889 | /* Access permission fault. */ |
f989983e | 10890 | fi->type = ARMFault_Permission; |
9ee6e8bb PB |
10891 | goto do_fault; |
10892 | } | |
10893 | *phys_ptr = phys_addr; | |
b7cc4e82 | 10894 | return false; |
9ee6e8bb | 10895 | do_fault: |
f989983e PM |
10896 | fi->domain = domain; |
10897 | fi->level = level; | |
b7cc4e82 | 10898 | return true; |
9ee6e8bb PB |
10899 | } |
10900 | ||
b7cc4e82 | 10901 | static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, |
03ae85f8 | 10902 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
b7cc4e82 | 10903 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, |
f06cf243 | 10904 | target_ulong *page_size, ARMMMUFaultInfo *fi) |
9ee6e8bb | 10905 | { |
2fc0cc0e | 10906 | CPUState *cs = env_cpu(env); |
0ae0326b | 10907 | ARMCPU *cpu = env_archcpu(env); |
f06cf243 | 10908 | int level = 1; |
9ee6e8bb PB |
10909 | uint32_t table; |
10910 | uint32_t desc; | |
10911 | uint32_t xn; | |
de9b05b8 | 10912 | uint32_t pxn = 0; |
9ee6e8bb PB |
10913 | int type; |
10914 | int ap; | |
de9b05b8 | 10915 | int domain = 0; |
dd4ebc2e | 10916 | int domain_prot; |
a8170e5e | 10917 | hwaddr phys_addr; |
0480f69a | 10918 | uint32_t dacr; |
8bf5b6a9 | 10919 | bool ns; |
9ee6e8bb PB |
10920 | |
10921 | /* Pagetable walk. */ | |
10922 | /* Lookup l1 descriptor. */ | |
0480f69a | 10923 | if (!get_level1_table_address(env, mmu_idx, &table, address)) { |
e389be16 | 10924 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ |
f06cf243 | 10925 | fi->type = ARMFault_Translation; |
e389be16 FA |
10926 | goto do_fault; |
10927 | } | |
a614e698 | 10928 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 10929 | mmu_idx, fi); |
3b39d734 PM |
10930 | if (fi->type != ARMFault_None) { |
10931 | goto do_fault; | |
10932 | } | |
9ee6e8bb | 10933 | type = (desc & 3); |
0ae0326b | 10934 | if (type == 0 || (type == 3 && !cpu_isar_feature(aa32_pxn, cpu))) { |
de9b05b8 PM |
10935 | /* Section translation fault, or attempt to use the encoding |
10936 | * which is Reserved on implementations without PXN. | |
10937 | */ | |
f06cf243 | 10938 | fi->type = ARMFault_Translation; |
9ee6e8bb | 10939 | goto do_fault; |
de9b05b8 PM |
10940 | } |
10941 | if ((type == 1) || !(desc & (1 << 18))) { | |
10942 | /* Page or Section. */ | |
dd4ebc2e | 10943 | domain = (desc >> 5) & 0x0f; |
9ee6e8bb | 10944 | } |
0480f69a PM |
10945 | if (regime_el(env, mmu_idx) == 1) { |
10946 | dacr = env->cp15.dacr_ns; | |
10947 | } else { | |
10948 | dacr = env->cp15.dacr_s; | |
10949 | } | |
f06cf243 PM |
10950 | if (type == 1) { |
10951 | level = 2; | |
10952 | } | |
0480f69a | 10953 | domain_prot = (dacr >> (domain * 2)) & 3; |
dd4ebc2e | 10954 | if (domain_prot == 0 || domain_prot == 2) { |
f06cf243 PM |
10955 | /* Section or Page domain fault */ |
10956 | fi->type = ARMFault_Domain; | |
9ee6e8bb PB |
10957 | goto do_fault; |
10958 | } | |
de9b05b8 | 10959 | if (type != 1) { |
9ee6e8bb PB |
10960 | if (desc & (1 << 18)) { |
10961 | /* Supersection. */ | |
10962 | phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); | |
4e42a6ca SF |
10963 | phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32; |
10964 | phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36; | |
d4c430a8 | 10965 | *page_size = 0x1000000; |
b5ff1b31 | 10966 | } else { |
9ee6e8bb PB |
10967 | /* Section. */ |
10968 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
d4c430a8 | 10969 | *page_size = 0x100000; |
b5ff1b31 | 10970 | } |
9ee6e8bb PB |
10971 | ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
10972 | xn = desc & (1 << 4); | |
de9b05b8 | 10973 | pxn = desc & 1; |
8bf5b6a9 | 10974 | ns = extract32(desc, 19, 1); |
9ee6e8bb | 10975 | } else { |
0ae0326b | 10976 | if (cpu_isar_feature(aa32_pxn, cpu)) { |
de9b05b8 PM |
10977 | pxn = (desc >> 2) & 1; |
10978 | } | |
8bf5b6a9 | 10979 | ns = extract32(desc, 3, 1); |
9ee6e8bb PB |
10980 | /* Lookup l2 entry. */ |
10981 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
a614e698 | 10982 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 10983 | mmu_idx, fi); |
3b39d734 PM |
10984 | if (fi->type != ARMFault_None) { |
10985 | goto do_fault; | |
10986 | } | |
9ee6e8bb PB |
10987 | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
10988 | switch (desc & 3) { | |
10989 | case 0: /* Page translation fault. */ | |
f06cf243 | 10990 | fi->type = ARMFault_Translation; |
b5ff1b31 | 10991 | goto do_fault; |
9ee6e8bb PB |
10992 | case 1: /* 64k page. */ |
10993 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
10994 | xn = desc & (1 << 15); | |
d4c430a8 | 10995 | *page_size = 0x10000; |
9ee6e8bb PB |
10996 | break; |
10997 | case 2: case 3: /* 4k page. */ | |
10998 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
10999 | xn = desc & 1; | |
d4c430a8 | 11000 | *page_size = 0x1000; |
9ee6e8bb PB |
11001 | break; |
11002 | default: | |
11003 | /* Never happens, but compiler isn't smart enough to tell. */ | |
11004 | abort(); | |
b5ff1b31 | 11005 | } |
9ee6e8bb | 11006 | } |
dd4ebc2e | 11007 | if (domain_prot == 3) { |
c0034328 JR |
11008 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
11009 | } else { | |
0480f69a | 11010 | if (pxn && !regime_is_user(env, mmu_idx)) { |
de9b05b8 PM |
11011 | xn = 1; |
11012 | } | |
f06cf243 PM |
11013 | if (xn && access_type == MMU_INST_FETCH) { |
11014 | fi->type = ARMFault_Permission; | |
c0034328 | 11015 | goto do_fault; |
f06cf243 | 11016 | } |
9ee6e8bb | 11017 | |
d76951b6 AJ |
11018 | if (arm_feature(env, ARM_FEATURE_V6K) && |
11019 | (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { | |
11020 | /* The simplified model uses AP[0] as an access control bit. */ | |
11021 | if ((ap & 1) == 0) { | |
11022 | /* Access flag fault. */ | |
f06cf243 | 11023 | fi->type = ARMFault_AccessFlag; |
d76951b6 AJ |
11024 | goto do_fault; |
11025 | } | |
11026 | *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); | |
11027 | } else { | |
11028 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); | |
c0034328 | 11029 | } |
0fbf5238 AJ |
11030 | if (*prot && !xn) { |
11031 | *prot |= PAGE_EXEC; | |
11032 | } | |
11033 | if (!(*prot & (1 << access_type))) { | |
c0034328 | 11034 | /* Access permission fault. */ |
f06cf243 | 11035 | fi->type = ARMFault_Permission; |
c0034328 JR |
11036 | goto do_fault; |
11037 | } | |
3ad493fc | 11038 | } |
8bf5b6a9 PM |
11039 | if (ns) { |
11040 | /* The NS bit will (as required by the architecture) have no effect if | |
11041 | * the CPU doesn't support TZ or this is a non-secure translation | |
11042 | * regime, because the attribute will already be non-secure. | |
11043 | */ | |
11044 | attrs->secure = false; | |
11045 | } | |
9ee6e8bb | 11046 | *phys_ptr = phys_addr; |
b7cc4e82 | 11047 | return false; |
b5ff1b31 | 11048 | do_fault: |
f06cf243 PM |
11049 | fi->domain = domain; |
11050 | fi->level = level; | |
b7cc4e82 | 11051 | return true; |
b5ff1b31 FB |
11052 | } |
11053 | ||
1853d5a9 | 11054 | /* |
a0e966c9 | 11055 | * check_s2_mmu_setup |
1853d5a9 EI |
11056 | * @cpu: ARMCPU |
11057 | * @is_aa64: True if the translation regime is in AArch64 state | |
11058 | * @startlevel: Suggested starting level | |
11059 | * @inputsize: Bitsize of IPAs | |
11060 | * @stride: Page-table stride (See the ARM ARM) | |
11061 | * | |
a0e966c9 EI |
11062 | * Returns true if the suggested S2 translation parameters are OK and |
11063 | * false otherwise. | |
1853d5a9 | 11064 | */ |
a0e966c9 EI |
11065 | static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, |
11066 | int inputsize, int stride) | |
1853d5a9 | 11067 | { |
98d68ec2 EI |
11068 | const int grainsize = stride + 3; |
11069 | int startsizecheck; | |
11070 | ||
1853d5a9 EI |
11071 | /* Negative levels are never allowed. */ |
11072 | if (level < 0) { | |
11073 | return false; | |
11074 | } | |
11075 | ||
98d68ec2 EI |
11076 | startsizecheck = inputsize - ((3 - level) * stride + grainsize); |
11077 | if (startsizecheck < 1 || startsizecheck > stride + 4) { | |
11078 | return false; | |
11079 | } | |
11080 | ||
1853d5a9 | 11081 | if (is_aa64) { |
3526423e | 11082 | CPUARMState *env = &cpu->env; |
1853d5a9 EI |
11083 | unsigned int pamax = arm_pamax(cpu); |
11084 | ||
11085 | switch (stride) { | |
11086 | case 13: /* 64KB Pages. */ | |
11087 | if (level == 0 || (level == 1 && pamax <= 42)) { | |
11088 | return false; | |
11089 | } | |
11090 | break; | |
11091 | case 11: /* 16KB Pages. */ | |
11092 | if (level == 0 || (level == 1 && pamax <= 40)) { | |
11093 | return false; | |
11094 | } | |
11095 | break; | |
11096 | case 9: /* 4KB Pages. */ | |
11097 | if (level == 0 && pamax <= 42) { | |
11098 | return false; | |
11099 | } | |
11100 | break; | |
11101 | default: | |
11102 | g_assert_not_reached(); | |
11103 | } | |
3526423e EI |
11104 | |
11105 | /* Inputsize checks. */ | |
11106 | if (inputsize > pamax && | |
11107 | (arm_el_is_aa64(env, 1) || inputsize > 40)) { | |
11108 | /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ | |
11109 | return false; | |
11110 | } | |
1853d5a9 | 11111 | } else { |
1853d5a9 EI |
11112 | /* AArch32 only supports 4KB pages. Assert on that. */ |
11113 | assert(stride == 9); | |
11114 | ||
11115 | if (level == 0) { | |
11116 | return false; | |
11117 | } | |
1853d5a9 EI |
11118 | } |
11119 | return true; | |
11120 | } | |
11121 | ||
5b2d261d AB |
11122 | /* Translate from the 4-bit stage 2 representation of |
11123 | * memory attributes (without cache-allocation hints) to | |
11124 | * the 8-bit representation of the stage 1 MAIR registers | |
11125 | * (which includes allocation hints). | |
11126 | * | |
11127 | * ref: shared/translation/attrs/S2AttrDecode() | |
11128 | * .../S2ConvertAttrsHints() | |
11129 | */ | |
11130 | static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) | |
11131 | { | |
11132 | uint8_t hiattr = extract32(s2attrs, 2, 2); | |
11133 | uint8_t loattr = extract32(s2attrs, 0, 2); | |
11134 | uint8_t hihint = 0, lohint = 0; | |
11135 | ||
11136 | if (hiattr != 0) { /* normal memory */ | |
e04a5752 | 11137 | if (arm_hcr_el2_eff(env) & HCR_CD) { /* cache disabled */ |
5b2d261d AB |
11138 | hiattr = loattr = 1; /* non-cacheable */ |
11139 | } else { | |
11140 | if (hiattr != 1) { /* Write-through or write-back */ | |
11141 | hihint = 3; /* RW allocate */ | |
11142 | } | |
11143 | if (loattr != 1) { /* Write-through or write-back */ | |
11144 | lohint = 3; /* RW allocate */ | |
11145 | } | |
11146 | } | |
11147 | } | |
11148 | ||
11149 | return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; | |
11150 | } | |
c47eaf9f | 11151 | #endif /* !CONFIG_USER_ONLY */ |
5b2d261d | 11152 | |
b830a5ee RH |
11153 | static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) |
11154 | { | |
11155 | if (regime_has_2_ranges(mmu_idx)) { | |
11156 | return extract64(tcr, 37, 2); | |
b1a10c86 | 11157 | } else if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { |
b830a5ee RH |
11158 | return 0; /* VTCR_EL2 */ |
11159 | } else { | |
3e270f67 RH |
11160 | /* Replicate the single TBI bit so we always have 2 bits. */ |
11161 | return extract32(tcr, 20, 1) * 3; | |
b830a5ee RH |
11162 | } |
11163 | } | |
11164 | ||
11165 | static int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) | |
11166 | { | |
11167 | if (regime_has_2_ranges(mmu_idx)) { | |
11168 | return extract64(tcr, 51, 2); | |
b1a10c86 | 11169 | } else if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { |
b830a5ee RH |
11170 | return 0; /* VTCR_EL2 */ |
11171 | } else { | |
3e270f67 RH |
11172 | /* Replicate the single TBID bit so we always have 2 bits. */ |
11173 | return extract32(tcr, 29, 1) * 3; | |
b830a5ee RH |
11174 | } |
11175 | } | |
11176 | ||
81ae05fa RH |
11177 | static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx) |
11178 | { | |
11179 | if (regime_has_2_ranges(mmu_idx)) { | |
11180 | return extract64(tcr, 57, 2); | |
11181 | } else { | |
11182 | /* Replicate the single TCMA bit so we always have 2 bits. */ | |
11183 | return extract32(tcr, 30, 1) * 3; | |
11184 | } | |
11185 | } | |
11186 | ||
b830a5ee RH |
11187 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, |
11188 | ARMMMUIdx mmu_idx, bool data) | |
ba97be9f RH |
11189 | { |
11190 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | |
b830a5ee | 11191 | bool epd, hpd, using16k, using64k; |
c36c65ea | 11192 | int select, tsz, tbi, max_tsz; |
ba97be9f | 11193 | |
339370b9 | 11194 | if (!regime_has_2_ranges(mmu_idx)) { |
71d18164 | 11195 | select = 0; |
ba97be9f RH |
11196 | tsz = extract32(tcr, 0, 6); |
11197 | using64k = extract32(tcr, 14, 1); | |
11198 | using16k = extract32(tcr, 15, 1); | |
b1a10c86 | 11199 | if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { |
ba97be9f | 11200 | /* VTCR_EL2 */ |
b830a5ee | 11201 | hpd = false; |
ba97be9f | 11202 | } else { |
ba97be9f RH |
11203 | hpd = extract32(tcr, 24, 1); |
11204 | } | |
11205 | epd = false; | |
ba97be9f | 11206 | } else { |
71d18164 RH |
11207 | /* |
11208 | * Bit 55 is always between the two regions, and is canonical for | |
11209 | * determining if address tagging is enabled. | |
11210 | */ | |
11211 | select = extract64(va, 55, 1); | |
11212 | if (!select) { | |
11213 | tsz = extract32(tcr, 0, 6); | |
11214 | epd = extract32(tcr, 7, 1); | |
11215 | using64k = extract32(tcr, 14, 1); | |
11216 | using16k = extract32(tcr, 15, 1); | |
71d18164 | 11217 | hpd = extract64(tcr, 41, 1); |
71d18164 RH |
11218 | } else { |
11219 | int tg = extract32(tcr, 30, 2); | |
11220 | using16k = tg == 1; | |
11221 | using64k = tg == 3; | |
11222 | tsz = extract32(tcr, 16, 6); | |
11223 | epd = extract32(tcr, 23, 1); | |
71d18164 | 11224 | hpd = extract64(tcr, 42, 1); |
71d18164 | 11225 | } |
ba97be9f | 11226 | } |
c36c65ea RDC |
11227 | |
11228 | if (cpu_isar_feature(aa64_st, env_archcpu(env))) { | |
11229 | max_tsz = 48 - using64k; | |
11230 | } else { | |
11231 | max_tsz = 39; | |
11232 | } | |
11233 | ||
11234 | tsz = MIN(tsz, max_tsz); | |
ba97be9f RH |
11235 | tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ |
11236 | ||
b830a5ee RH |
11237 | /* Present TBI as a composite with TBID. */ |
11238 | tbi = aa64_va_parameter_tbi(tcr, mmu_idx); | |
11239 | if (!data) { | |
11240 | tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); | |
11241 | } | |
11242 | tbi = (tbi >> select) & 1; | |
11243 | ||
ba97be9f RH |
11244 | return (ARMVAParameters) { |
11245 | .tsz = tsz, | |
11246 | .select = select, | |
11247 | .tbi = tbi, | |
11248 | .epd = epd, | |
11249 | .hpd = hpd, | |
11250 | .using16k = using16k, | |
11251 | .using64k = using64k, | |
11252 | }; | |
11253 | } | |
11254 | ||
c47eaf9f | 11255 | #ifndef CONFIG_USER_ONLY |
ba97be9f RH |
11256 | static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, |
11257 | ARMMMUIdx mmu_idx) | |
11258 | { | |
11259 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | |
11260 | uint32_t el = regime_el(env, mmu_idx); | |
11261 | int select, tsz; | |
11262 | bool epd, hpd; | |
11263 | ||
b1a10c86 RDC |
11264 | assert(mmu_idx != ARMMMUIdx_Stage2_S); |
11265 | ||
97fa9350 | 11266 | if (mmu_idx == ARMMMUIdx_Stage2) { |
ba97be9f RH |
11267 | /* VTCR */ |
11268 | bool sext = extract32(tcr, 4, 1); | |
11269 | bool sign = extract32(tcr, 3, 1); | |
11270 | ||
11271 | /* | |
11272 | * If the sign-extend bit is not the same as t0sz[3], the result | |
11273 | * is unpredictable. Flag this as a guest error. | |
11274 | */ | |
11275 | if (sign != sext) { | |
11276 | qemu_log_mask(LOG_GUEST_ERROR, | |
11277 | "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); | |
11278 | } | |
11279 | tsz = sextract32(tcr, 0, 4) + 8; | |
11280 | select = 0; | |
11281 | hpd = false; | |
11282 | epd = false; | |
11283 | } else if (el == 2) { | |
11284 | /* HTCR */ | |
11285 | tsz = extract32(tcr, 0, 3); | |
11286 | select = 0; | |
11287 | hpd = extract64(tcr, 24, 1); | |
11288 | epd = false; | |
11289 | } else { | |
11290 | int t0sz = extract32(tcr, 0, 3); | |
11291 | int t1sz = extract32(tcr, 16, 3); | |
11292 | ||
11293 | if (t1sz == 0) { | |
11294 | select = va > (0xffffffffu >> t0sz); | |
11295 | } else { | |
11296 | /* Note that we will detect errors later. */ | |
11297 | select = va >= ~(0xffffffffu >> t1sz); | |
11298 | } | |
11299 | if (!select) { | |
11300 | tsz = t0sz; | |
11301 | epd = extract32(tcr, 7, 1); | |
11302 | hpd = extract64(tcr, 41, 1); | |
11303 | } else { | |
11304 | tsz = t1sz; | |
11305 | epd = extract32(tcr, 23, 1); | |
11306 | hpd = extract64(tcr, 42, 1); | |
11307 | } | |
11308 | /* For aarch32, hpd0 is not enabled without t2e as well. */ | |
11309 | hpd &= extract32(tcr, 6, 1); | |
11310 | } | |
11311 | ||
11312 | return (ARMVAParameters) { | |
11313 | .tsz = tsz, | |
11314 | .select = select, | |
11315 | .epd = epd, | |
11316 | .hpd = hpd, | |
11317 | }; | |
11318 | } | |
11319 | ||
ff7de2fc PM |
11320 | /** |
11321 | * get_phys_addr_lpae: perform one stage of page table walk, LPAE format | |
11322 | * | |
11323 | * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, | |
11324 | * prot and page_size may not be filled in, and the populated fsr value provides | |
11325 | * information on why the translation aborted, in the format of a long-format | |
11326 | * DFSR/IFSR fault register, with the following caveats: | |
11327 | * * the WnR bit is never set (the caller must do this). | |
11328 | * | |
11329 | * @env: CPUARMState | |
11330 | * @address: virtual address to get physical address for | |
11331 | * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH | |
11332 | * @mmu_idx: MMU index indicating required translation regime | |
11333 | * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page table | |
11334 | * walk), must be true if this is stage 2 of a stage 1+2 walk for an | |
11335 | * EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ignored. | |
11336 | * @phys_ptr: set to the physical address corresponding to the virtual address | |
11337 | * @attrs: set to the memory transaction attributes to use | |
11338 | * @prot: set to the permissions for the page containing phys_ptr | |
11339 | * @page_size_ptr: set to the size of the page containing phys_ptr | |
11340 | * @fi: set to fault info if the translation fails | |
11341 | * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes | |
11342 | */ | |
98e87797 | 11343 | static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, |
03ae85f8 | 11344 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
ff7de2fc | 11345 | bool s1_is_el0, |
b7cc4e82 | 11346 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, |
da909b2c | 11347 | target_ulong *page_size_ptr, |
5b2d261d | 11348 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) |
3dde962f | 11349 | { |
2fc0cc0e | 11350 | ARMCPU *cpu = env_archcpu(env); |
1853d5a9 | 11351 | CPUState *cs = CPU(cpu); |
3dde962f | 11352 | /* Read an LPAE long-descriptor translation table. */ |
da909b2c | 11353 | ARMFaultType fault_type = ARMFault_Translation; |
1b4093ea | 11354 | uint32_t level; |
ba97be9f | 11355 | ARMVAParameters param; |
3dde962f | 11356 | uint64_t ttbr; |
dddb5223 | 11357 | hwaddr descaddr, indexmask, indexmask_grainsize; |
3dde962f | 11358 | uint32_t tableattrs; |
36d820af | 11359 | target_ulong page_size; |
3dde962f | 11360 | uint32_t attrs; |
ba97be9f RH |
11361 | int32_t stride; |
11362 | int addrsize, inputsize; | |
0480f69a | 11363 | TCR *tcr = regime_tcr(env, mmu_idx); |
d8e052b3 | 11364 | int ap, ns, xn, pxn; |
88e8add8 | 11365 | uint32_t el = regime_el(env, mmu_idx); |
6109769a | 11366 | uint64_t descaddrmask; |
6e99f762 | 11367 | bool aarch64 = arm_el_is_aa64(env, el); |
1bafc2ba | 11368 | bool guarded = false; |
0480f69a | 11369 | |
07d1be3b | 11370 | /* TODO: This code does not support shareability levels. */ |
6e99f762 | 11371 | if (aarch64) { |
ba97be9f RH |
11372 | param = aa64_va_parameters(env, address, mmu_idx, |
11373 | access_type != MMU_INST_FETCH); | |
1b4093ea | 11374 | level = 0; |
ba97be9f RH |
11375 | addrsize = 64 - 8 * param.tbi; |
11376 | inputsize = 64 - param.tsz; | |
d0a2cbce | 11377 | } else { |
ba97be9f | 11378 | param = aa32_va_parameters(env, address, mmu_idx); |
1b4093ea | 11379 | level = 1; |
97fa9350 | 11380 | addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32); |
ba97be9f | 11381 | inputsize = addrsize - param.tsz; |
2c8dd318 | 11382 | } |
3dde962f | 11383 | |
ba97be9f RH |
11384 | /* |
11385 | * We determined the region when collecting the parameters, but we | |
11386 | * have not yet validated that the address is valid for the region. | |
11387 | * Extract the top bits and verify that they all match select. | |
36d820af RH |
11388 | * |
11389 | * For aa32, if inputsize == addrsize, then we have selected the | |
11390 | * region by exclusion in aa32_va_parameters and there is no more | |
11391 | * validation to do here. | |
11392 | */ | |
11393 | if (inputsize < addrsize) { | |
11394 | target_ulong top_bits = sextract64(address, inputsize, | |
11395 | addrsize - inputsize); | |
03f27724 | 11396 | if (-top_bits != param.select) { |
36d820af RH |
11397 | /* The gap between the two regions is a Translation fault */ |
11398 | fault_type = ARMFault_Translation; | |
11399 | goto do_fault; | |
11400 | } | |
3dde962f PM |
11401 | } |
11402 | ||
ba97be9f RH |
11403 | if (param.using64k) { |
11404 | stride = 13; | |
11405 | } else if (param.using16k) { | |
11406 | stride = 11; | |
11407 | } else { | |
11408 | stride = 9; | |
11409 | } | |
11410 | ||
3dde962f PM |
11411 | /* Note that QEMU ignores shareability and cacheability attributes, |
11412 | * so we don't need to do anything with the SH, ORGN, IRGN fields | |
11413 | * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the | |
11414 | * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently | |
11415 | * implement any ASID-like capability so we can ignore it (instead | |
11416 | * we will always flush the TLB any time the ASID is changed). | |
11417 | */ | |
ba97be9f | 11418 | ttbr = regime_ttbr(env, mmu_idx, param.select); |
3dde962f | 11419 | |
0480f69a | 11420 | /* Here we should have set up all the parameters for the translation: |
6e99f762 | 11421 | * inputsize, ttbr, epd, stride, tbi |
0480f69a PM |
11422 | */ |
11423 | ||
ba97be9f | 11424 | if (param.epd) { |
88e8add8 GB |
11425 | /* Translation table walk disabled => Translation fault on TLB miss |
11426 | * Note: This is always 0 on 64-bit EL2 and EL3. | |
11427 | */ | |
3dde962f PM |
11428 | goto do_fault; |
11429 | } | |
11430 | ||
b1a10c86 | 11431 | if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) { |
1853d5a9 EI |
11432 | /* The starting level depends on the virtual address size (which can |
11433 | * be up to 48 bits) and the translation granule size. It indicates | |
11434 | * the number of strides (stride bits at a time) needed to | |
11435 | * consume the bits of the input address. In the pseudocode this is: | |
11436 | * level = 4 - RoundUp((inputsize - grainsize) / stride) | |
11437 | * where their 'inputsize' is our 'inputsize', 'grainsize' is | |
11438 | * our 'stride + 3' and 'stride' is our 'stride'. | |
11439 | * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: | |
11440 | * = 4 - (inputsize - stride - 3 + stride - 1) / stride | |
11441 | * = 4 - (inputsize - 4) / stride; | |
11442 | */ | |
11443 | level = 4 - (inputsize - 4) / stride; | |
11444 | } else { | |
11445 | /* For stage 2 translations the starting level is specified by the | |
11446 | * VTCR_EL2.SL0 field (whose interpretation depends on the page size) | |
11447 | */ | |
1b4093ea SS |
11448 | uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); |
11449 | uint32_t startlevel; | |
1853d5a9 EI |
11450 | bool ok; |
11451 | ||
6e99f762 | 11452 | if (!aarch64 || stride == 9) { |
1853d5a9 | 11453 | /* AArch32 or 4KB pages */ |
1b4093ea | 11454 | startlevel = 2 - sl0; |
c36c65ea RDC |
11455 | |
11456 | if (cpu_isar_feature(aa64_st, cpu)) { | |
11457 | startlevel &= 3; | |
11458 | } | |
1853d5a9 EI |
11459 | } else { |
11460 | /* 16KB or 64KB pages */ | |
1b4093ea | 11461 | startlevel = 3 - sl0; |
1853d5a9 EI |
11462 | } |
11463 | ||
11464 | /* Check that the starting level is valid. */ | |
6e99f762 | 11465 | ok = check_s2_mmu_setup(cpu, aarch64, startlevel, |
1b4093ea | 11466 | inputsize, stride); |
1853d5a9 | 11467 | if (!ok) { |
da909b2c | 11468 | fault_type = ARMFault_Translation; |
1853d5a9 EI |
11469 | goto do_fault; |
11470 | } | |
1b4093ea | 11471 | level = startlevel; |
1853d5a9 | 11472 | } |
3dde962f | 11473 | |
dddb5223 SS |
11474 | indexmask_grainsize = (1ULL << (stride + 3)) - 1; |
11475 | indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; | |
3dde962f PM |
11476 | |
11477 | /* Now we can extract the actual base address from the TTBR */ | |
2c8dd318 | 11478 | descaddr = extract64(ttbr, 0, 48); |
41a4bf1f PM |
11479 | /* |
11480 | * We rely on this masking to clear the RES0 bits at the bottom of the TTBR | |
11481 | * and also to mask out CnP (bit 0) which could validly be non-zero. | |
11482 | */ | |
dddb5223 | 11483 | descaddr &= ~indexmask; |
3dde962f | 11484 | |
6109769a | 11485 | /* The address field in the descriptor goes up to bit 39 for ARMv7 |
dddb5223 SS |
11486 | * but up to bit 47 for ARMv8, but we use the descaddrmask |
11487 | * up to bit 39 for AArch32, because we don't need other bits in that case | |
11488 | * to construct next descriptor address (anyway they should be all zeroes). | |
6109769a | 11489 | */ |
6e99f762 | 11490 | descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) & |
dddb5223 | 11491 | ~indexmask_grainsize; |
6109769a | 11492 | |
ebca90e4 PM |
11493 | /* Secure accesses start with the page table in secure memory and |
11494 | * can be downgraded to non-secure at any step. Non-secure accesses | |
11495 | * remain non-secure. We implement this by just ORing in the NSTable/NS | |
11496 | * bits at each step. | |
11497 | */ | |
11498 | tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); | |
3dde962f PM |
11499 | for (;;) { |
11500 | uint64_t descriptor; | |
ebca90e4 | 11501 | bool nstable; |
3dde962f | 11502 | |
dddb5223 | 11503 | descaddr |= (address >> (stride * (4 - level))) & indexmask; |
2c8dd318 | 11504 | descaddr &= ~7ULL; |
ebca90e4 | 11505 | nstable = extract32(tableattrs, 4, 1); |
3795a6de | 11506 | descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi); |
3b39d734 | 11507 | if (fi->type != ARMFault_None) { |
37785977 EI |
11508 | goto do_fault; |
11509 | } | |
11510 | ||
3dde962f PM |
11511 | if (!(descriptor & 1) || |
11512 | (!(descriptor & 2) && (level == 3))) { | |
11513 | /* Invalid, or the Reserved level 3 encoding */ | |
11514 | goto do_fault; | |
11515 | } | |
6109769a | 11516 | descaddr = descriptor & descaddrmask; |
3dde962f PM |
11517 | |
11518 | if ((descriptor & 2) && (level < 3)) { | |
037c13c5 | 11519 | /* Table entry. The top five bits are attributes which may |
3dde962f PM |
11520 | * propagate down through lower levels of the table (and |
11521 | * which are all arranged so that 0 means "no effect", so | |
11522 | * we can gather them up by ORing in the bits at each level). | |
11523 | */ | |
11524 | tableattrs |= extract64(descriptor, 59, 5); | |
11525 | level++; | |
dddb5223 | 11526 | indexmask = indexmask_grainsize; |
3dde962f PM |
11527 | continue; |
11528 | } | |
11529 | /* Block entry at level 1 or 2, or page entry at level 3. | |
11530 | * These are basically the same thing, although the number | |
11531 | * of bits we pull in from the vaddr varies. | |
11532 | */ | |
973a5434 | 11533 | page_size = (1ULL << ((stride * (4 - level)) + 3)); |
3dde962f | 11534 | descaddr |= (address & (page_size - 1)); |
6ab1a5ee | 11535 | /* Extract attributes from the descriptor */ |
d615efac IC |
11536 | attrs = extract64(descriptor, 2, 10) |
11537 | | (extract64(descriptor, 52, 12) << 10); | |
6ab1a5ee | 11538 | |
b1a10c86 | 11539 | if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { |
6ab1a5ee EI |
11540 | /* Stage 2 table descriptors do not include any attribute fields */ |
11541 | break; | |
11542 | } | |
11543 | /* Merge in attributes from table descriptors */ | |
037c13c5 | 11544 | attrs |= nstable << 3; /* NS */ |
1bafc2ba | 11545 | guarded = extract64(descriptor, 50, 1); /* GP */ |
ba97be9f | 11546 | if (param.hpd) { |
037c13c5 RH |
11547 | /* HPD disables all the table attributes except NSTable. */ |
11548 | break; | |
11549 | } | |
11550 | attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ | |
3dde962f PM |
11551 | /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 |
11552 | * means "force PL1 access only", which means forcing AP[1] to 0. | |
11553 | */ | |
037c13c5 RH |
11554 | attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */ |
11555 | attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */ | |
3dde962f PM |
11556 | break; |
11557 | } | |
11558 | /* Here descaddr is the final physical address, and attributes | |
11559 | * are all in attrs. | |
11560 | */ | |
da909b2c | 11561 | fault_type = ARMFault_AccessFlag; |
3dde962f PM |
11562 | if ((attrs & (1 << 8)) == 0) { |
11563 | /* Access flag */ | |
11564 | goto do_fault; | |
11565 | } | |
d8e052b3 AJ |
11566 | |
11567 | ap = extract32(attrs, 4, 2); | |
d8e052b3 | 11568 | |
b1a10c86 RDC |
11569 | if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { |
11570 | ns = mmu_idx == ARMMMUIdx_Stage2; | |
ce3125be PM |
11571 | xn = extract32(attrs, 11, 2); |
11572 | *prot = get_S2prot(env, ap, xn, s1_is_el0); | |
6ab1a5ee EI |
11573 | } else { |
11574 | ns = extract32(attrs, 3, 1); | |
ce3125be | 11575 | xn = extract32(attrs, 12, 1); |
6ab1a5ee | 11576 | pxn = extract32(attrs, 11, 1); |
6e99f762 | 11577 | *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); |
6ab1a5ee | 11578 | } |
d8e052b3 | 11579 | |
da909b2c | 11580 | fault_type = ARMFault_Permission; |
d8e052b3 | 11581 | if (!(*prot & (1 << access_type))) { |
3dde962f PM |
11582 | goto do_fault; |
11583 | } | |
3dde962f | 11584 | |
8bf5b6a9 PM |
11585 | if (ns) { |
11586 | /* The NS bit will (as required by the architecture) have no effect if | |
11587 | * the CPU doesn't support TZ or this is a non-secure translation | |
11588 | * regime, because the attribute will already be non-secure. | |
11589 | */ | |
11590 | txattrs->secure = false; | |
11591 | } | |
1bafc2ba RH |
11592 | /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */ |
11593 | if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { | |
149d3b31 | 11594 | arm_tlb_bti_gp(txattrs) = true; |
1bafc2ba | 11595 | } |
5b2d261d | 11596 | |
b1a10c86 | 11597 | if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { |
7e98e21c RH |
11598 | cacheattrs->attrs = convert_stage2_attrs(env, extract32(attrs, 0, 4)); |
11599 | } else { | |
11600 | /* Index into MAIR registers for cache attributes */ | |
11601 | uint8_t attrindx = extract32(attrs, 0, 3); | |
11602 | uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; | |
11603 | assert(attrindx <= 7); | |
11604 | cacheattrs->attrs = extract64(mair, attrindx * 8, 8); | |
5b2d261d | 11605 | } |
7e98e21c | 11606 | cacheattrs->shareability = extract32(attrs, 6, 2); |
5b2d261d | 11607 | |
3dde962f PM |
11608 | *phys_ptr = descaddr; |
11609 | *page_size_ptr = page_size; | |
b7cc4e82 | 11610 | return false; |
3dde962f PM |
11611 | |
11612 | do_fault: | |
da909b2c PM |
11613 | fi->type = fault_type; |
11614 | fi->level = level; | |
37785977 | 11615 | /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ |
b1a10c86 RDC |
11616 | fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_Stage2 || |
11617 | mmu_idx == ARMMMUIdx_Stage2_S); | |
9861248f | 11618 | fi->s1ns = mmu_idx == ARMMMUIdx_Stage2; |
b7cc4e82 | 11619 | return true; |
3dde962f PM |
11620 | } |
11621 | ||
f6bda88f PC |
11622 | static inline void get_phys_addr_pmsav7_default(CPUARMState *env, |
11623 | ARMMMUIdx mmu_idx, | |
11624 | int32_t address, int *prot) | |
11625 | { | |
3a00d560 MD |
11626 | if (!arm_feature(env, ARM_FEATURE_M)) { |
11627 | *prot = PAGE_READ | PAGE_WRITE; | |
11628 | switch (address) { | |
11629 | case 0xF0000000 ... 0xFFFFFFFF: | |
11630 | if (regime_sctlr(env, mmu_idx) & SCTLR_V) { | |
11631 | /* hivecs execing is ok */ | |
11632 | *prot |= PAGE_EXEC; | |
11633 | } | |
11634 | break; | |
11635 | case 0x00000000 ... 0x7FFFFFFF: | |
f6bda88f | 11636 | *prot |= PAGE_EXEC; |
3a00d560 MD |
11637 | break; |
11638 | } | |
11639 | } else { | |
11640 | /* Default system address map for M profile cores. | |
11641 | * The architecture specifies which regions are execute-never; | |
11642 | * at the MPU level no other checks are defined. | |
11643 | */ | |
11644 | switch (address) { | |
11645 | case 0x00000000 ... 0x1fffffff: /* ROM */ | |
11646 | case 0x20000000 ... 0x3fffffff: /* SRAM */ | |
11647 | case 0x60000000 ... 0x7fffffff: /* RAM */ | |
11648 | case 0x80000000 ... 0x9fffffff: /* RAM */ | |
11649 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
11650 | break; | |
11651 | case 0x40000000 ... 0x5fffffff: /* Peripheral */ | |
11652 | case 0xa0000000 ... 0xbfffffff: /* Device */ | |
11653 | case 0xc0000000 ... 0xdfffffff: /* Device */ | |
11654 | case 0xe0000000 ... 0xffffffff: /* System */ | |
11655 | *prot = PAGE_READ | PAGE_WRITE; | |
11656 | break; | |
11657 | default: | |
11658 | g_assert_not_reached(); | |
f6bda88f | 11659 | } |
f6bda88f | 11660 | } |
f6bda88f PC |
11661 | } |
11662 | ||
29c483a5 MD |
11663 | static bool pmsav7_use_background_region(ARMCPU *cpu, |
11664 | ARMMMUIdx mmu_idx, bool is_user) | |
11665 | { | |
11666 | /* Return true if we should use the default memory map as a | |
11667 | * "background" region if there are no hits against any MPU regions. | |
11668 | */ | |
11669 | CPUARMState *env = &cpu->env; | |
11670 | ||
11671 | if (is_user) { | |
11672 | return false; | |
11673 | } | |
11674 | ||
11675 | if (arm_feature(env, ARM_FEATURE_M)) { | |
ecf5e8ea PM |
11676 | return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] |
11677 | & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; | |
29c483a5 MD |
11678 | } else { |
11679 | return regime_sctlr(env, mmu_idx) & SCTLR_BR; | |
11680 | } | |
11681 | } | |
11682 | ||
38aaa60c PM |
11683 | static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address) |
11684 | { | |
11685 | /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */ | |
11686 | return arm_feature(env, ARM_FEATURE_M) && | |
11687 | extract32(address, 20, 12) == 0xe00; | |
11688 | } | |
11689 | ||
bf446a11 PM |
11690 | static inline bool m_is_system_region(CPUARMState *env, uint32_t address) |
11691 | { | |
11692 | /* True if address is in the M profile system region | |
11693 | * 0xe0000000 - 0xffffffff | |
11694 | */ | |
11695 | return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7; | |
11696 | } | |
11697 | ||
f6bda88f | 11698 | static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, |
03ae85f8 | 11699 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
9375ad15 | 11700 | hwaddr *phys_ptr, int *prot, |
e5e40999 | 11701 | target_ulong *page_size, |
9375ad15 | 11702 | ARMMMUFaultInfo *fi) |
f6bda88f | 11703 | { |
2fc0cc0e | 11704 | ARMCPU *cpu = env_archcpu(env); |
f6bda88f PC |
11705 | int n; |
11706 | bool is_user = regime_is_user(env, mmu_idx); | |
11707 | ||
11708 | *phys_ptr = address; | |
e5e40999 | 11709 | *page_size = TARGET_PAGE_SIZE; |
f6bda88f PC |
11710 | *prot = 0; |
11711 | ||
38aaa60c PM |
11712 | if (regime_translation_disabled(env, mmu_idx) || |
11713 | m_is_ppb_region(env, address)) { | |
11714 | /* MPU disabled or M profile PPB access: use default memory map. | |
11715 | * The other case which uses the default memory map in the | |
11716 | * v7M ARM ARM pseudocode is exception vector reads from the vector | |
11717 | * table. In QEMU those accesses are done in arm_v7m_load_vector(), | |
11718 | * which always does a direct read using address_space_ldl(), rather | |
11719 | * than going via this function, so we don't need to check that here. | |
11720 | */ | |
f6bda88f PC |
11721 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); |
11722 | } else { /* MPU enabled */ | |
11723 | for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { | |
11724 | /* region search */ | |
11725 | uint32_t base = env->pmsav7.drbar[n]; | |
11726 | uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5); | |
11727 | uint32_t rmask; | |
11728 | bool srdis = false; | |
11729 | ||
11730 | if (!(env->pmsav7.drsr[n] & 0x1)) { | |
11731 | continue; | |
11732 | } | |
11733 | ||
11734 | if (!rsize) { | |
c9f9f124 MD |
11735 | qemu_log_mask(LOG_GUEST_ERROR, |
11736 | "DRSR[%d]: Rsize field cannot be 0\n", n); | |
f6bda88f PC |
11737 | continue; |
11738 | } | |
11739 | rsize++; | |
11740 | rmask = (1ull << rsize) - 1; | |
11741 | ||
11742 | if (base & rmask) { | |
c9f9f124 MD |
11743 | qemu_log_mask(LOG_GUEST_ERROR, |
11744 | "DRBAR[%d]: 0x%" PRIx32 " misaligned " | |
11745 | "to DRSR region size, mask = 0x%" PRIx32 "\n", | |
11746 | n, base, rmask); | |
f6bda88f PC |
11747 | continue; |
11748 | } | |
11749 | ||
11750 | if (address < base || address > base + rmask) { | |
9d2b5a58 PM |
11751 | /* |
11752 | * Address not in this region. We must check whether the | |
11753 | * region covers addresses in the same page as our address. | |
11754 | * In that case we must not report a size that covers the | |
11755 | * whole page for a subsequent hit against a different MPU | |
11756 | * region or the background region, because it would result in | |
11757 | * incorrect TLB hits for subsequent accesses to addresses that | |
11758 | * are in this MPU region. | |
11759 | */ | |
11760 | if (ranges_overlap(base, rmask, | |
11761 | address & TARGET_PAGE_MASK, | |
11762 | TARGET_PAGE_SIZE)) { | |
11763 | *page_size = 1; | |
11764 | } | |
f6bda88f PC |
11765 | continue; |
11766 | } | |
11767 | ||
11768 | /* Region matched */ | |
11769 | ||
11770 | if (rsize >= 8) { /* no subregions for regions < 256 bytes */ | |
11771 | int i, snd; | |
11772 | uint32_t srdis_mask; | |
11773 | ||
11774 | rsize -= 3; /* sub region size (power of 2) */ | |
11775 | snd = ((address - base) >> rsize) & 0x7; | |
11776 | srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1); | |
11777 | ||
11778 | srdis_mask = srdis ? 0x3 : 0x0; | |
11779 | for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) { | |
11780 | /* This will check in groups of 2, 4 and then 8, whether | |
11781 | * the subregion bits are consistent. rsize is incremented | |
11782 | * back up to give the region size, considering consistent | |
11783 | * adjacent subregions as one region. Stop testing if rsize | |
11784 | * is already big enough for an entire QEMU page. | |
11785 | */ | |
11786 | int snd_rounded = snd & ~(i - 1); | |
11787 | uint32_t srdis_multi = extract32(env->pmsav7.drsr[n], | |
11788 | snd_rounded + 8, i); | |
11789 | if (srdis_mask ^ srdis_multi) { | |
11790 | break; | |
11791 | } | |
11792 | srdis_mask = (srdis_mask << i) | srdis_mask; | |
11793 | rsize++; | |
11794 | } | |
11795 | } | |
f6bda88f PC |
11796 | if (srdis) { |
11797 | continue; | |
11798 | } | |
e5e40999 PM |
11799 | if (rsize < TARGET_PAGE_BITS) { |
11800 | *page_size = 1 << rsize; | |
11801 | } | |
f6bda88f PC |
11802 | break; |
11803 | } | |
11804 | ||
11805 | if (n == -1) { /* no hits */ | |
29c483a5 | 11806 | if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { |
f6bda88f | 11807 | /* background fault */ |
9375ad15 | 11808 | fi->type = ARMFault_Background; |
f6bda88f PC |
11809 | return true; |
11810 | } | |
11811 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | |
11812 | } else { /* a MPU hit! */ | |
11813 | uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); | |
bf446a11 PM |
11814 | uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1); |
11815 | ||
11816 | if (m_is_system_region(env, address)) { | |
11817 | /* System space is always execute never */ | |
11818 | xn = 1; | |
11819 | } | |
f6bda88f PC |
11820 | |
11821 | if (is_user) { /* User mode AP bit decoding */ | |
11822 | switch (ap) { | |
11823 | case 0: | |
11824 | case 1: | |
11825 | case 5: | |
11826 | break; /* no access */ | |
11827 | case 3: | |
11828 | *prot |= PAGE_WRITE; | |
11829 | /* fall through */ | |
11830 | case 2: | |
11831 | case 6: | |
11832 | *prot |= PAGE_READ | PAGE_EXEC; | |
11833 | break; | |
8638f1ad PM |
11834 | case 7: |
11835 | /* for v7M, same as 6; for R profile a reserved value */ | |
11836 | if (arm_feature(env, ARM_FEATURE_M)) { | |
11837 | *prot |= PAGE_READ | PAGE_EXEC; | |
11838 | break; | |
11839 | } | |
11840 | /* fall through */ | |
f6bda88f PC |
11841 | default: |
11842 | qemu_log_mask(LOG_GUEST_ERROR, | |
c9f9f124 MD |
11843 | "DRACR[%d]: Bad value for AP bits: 0x%" |
11844 | PRIx32 "\n", n, ap); | |
f6bda88f PC |
11845 | } |
11846 | } else { /* Priv. mode AP bits decoding */ | |
11847 | switch (ap) { | |
11848 | case 0: | |
11849 | break; /* no access */ | |
11850 | case 1: | |
11851 | case 2: | |
11852 | case 3: | |
11853 | *prot |= PAGE_WRITE; | |
11854 | /* fall through */ | |
11855 | case 5: | |
11856 | case 6: | |
11857 | *prot |= PAGE_READ | PAGE_EXEC; | |
11858 | break; | |
8638f1ad PM |
11859 | case 7: |
11860 | /* for v7M, same as 6; for R profile a reserved value */ | |
11861 | if (arm_feature(env, ARM_FEATURE_M)) { | |
11862 | *prot |= PAGE_READ | PAGE_EXEC; | |
11863 | break; | |
11864 | } | |
11865 | /* fall through */ | |
f6bda88f PC |
11866 | default: |
11867 | qemu_log_mask(LOG_GUEST_ERROR, | |
c9f9f124 MD |
11868 | "DRACR[%d]: Bad value for AP bits: 0x%" |
11869 | PRIx32 "\n", n, ap); | |
f6bda88f PC |
11870 | } |
11871 | } | |
11872 | ||
11873 | /* execute never */ | |
bf446a11 | 11874 | if (xn) { |
f6bda88f PC |
11875 | *prot &= ~PAGE_EXEC; |
11876 | } | |
11877 | } | |
11878 | } | |
11879 | ||
9375ad15 PM |
11880 | fi->type = ARMFault_Permission; |
11881 | fi->level = 1; | |
f6bda88f PC |
11882 | return !(*prot & (1 << access_type)); |
11883 | } | |
11884 | ||
35337cc3 PM |
11885 | static bool v8m_is_sau_exempt(CPUARMState *env, |
11886 | uint32_t address, MMUAccessType access_type) | |
11887 | { | |
11888 | /* The architecture specifies that certain address ranges are | |
11889 | * exempt from v8M SAU/IDAU checks. | |
11890 | */ | |
11891 | return | |
11892 | (access_type == MMU_INST_FETCH && m_is_system_region(env, address)) || | |
11893 | (address >= 0xe0000000 && address <= 0xe0002fff) || | |
11894 | (address >= 0xe000e000 && address <= 0xe000efff) || | |
11895 | (address >= 0xe002e000 && address <= 0xe002efff) || | |
11896 | (address >= 0xe0040000 && address <= 0xe0041fff) || | |
11897 | (address >= 0xe00ff000 && address <= 0xe00fffff); | |
11898 | } | |
11899 | ||
787a7e76 | 11900 | void v8m_security_lookup(CPUARMState *env, uint32_t address, |
35337cc3 PM |
11901 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
11902 | V8M_SAttributes *sattrs) | |
11903 | { | |
11904 | /* Look up the security attributes for this address. Compare the | |
11905 | * pseudocode SecurityCheck() function. | |
11906 | * We assume the caller has zero-initialized *sattrs. | |
11907 | */ | |
2fc0cc0e | 11908 | ARMCPU *cpu = env_archcpu(env); |
35337cc3 | 11909 | int r; |
181962fd PM |
11910 | bool idau_exempt = false, idau_ns = true, idau_nsc = true; |
11911 | int idau_region = IREGION_NOTVALID; | |
72042435 PM |
11912 | uint32_t addr_page_base = address & TARGET_PAGE_MASK; |
11913 | uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); | |
35337cc3 | 11914 | |
181962fd PM |
11915 | if (cpu->idau) { |
11916 | IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau); | |
11917 | IDAUInterface *ii = IDAU_INTERFACE(cpu->idau); | |
11918 | ||
11919 | iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns, | |
11920 | &idau_nsc); | |
11921 | } | |
35337cc3 PM |
11922 | |
11923 | if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) { | |
11924 | /* 0xf0000000..0xffffffff is always S for insn fetches */ | |
11925 | return; | |
11926 | } | |
11927 | ||
181962fd | 11928 | if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) { |
35337cc3 PM |
11929 | sattrs->ns = !regime_is_secure(env, mmu_idx); |
11930 | return; | |
11931 | } | |
11932 | ||
181962fd PM |
11933 | if (idau_region != IREGION_NOTVALID) { |
11934 | sattrs->irvalid = true; | |
11935 | sattrs->iregion = idau_region; | |
11936 | } | |
11937 | ||
35337cc3 PM |
11938 | switch (env->sau.ctrl & 3) { |
11939 | case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */ | |
11940 | break; | |
11941 | case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */ | |
11942 | sattrs->ns = true; | |
11943 | break; | |
11944 | default: /* SAU.ENABLE == 1 */ | |
11945 | for (r = 0; r < cpu->sau_sregion; r++) { | |
11946 | if (env->sau.rlar[r] & 1) { | |
11947 | uint32_t base = env->sau.rbar[r] & ~0x1f; | |
11948 | uint32_t limit = env->sau.rlar[r] | 0x1f; | |
11949 | ||
11950 | if (base <= address && limit >= address) { | |
72042435 PM |
11951 | if (base > addr_page_base || limit < addr_page_limit) { |
11952 | sattrs->subpage = true; | |
11953 | } | |
35337cc3 PM |
11954 | if (sattrs->srvalid) { |
11955 | /* If we hit in more than one region then we must report | |
11956 | * as Secure, not NS-Callable, with no valid region | |
11957 | * number info. | |
11958 | */ | |
11959 | sattrs->ns = false; | |
11960 | sattrs->nsc = false; | |
11961 | sattrs->sregion = 0; | |
11962 | sattrs->srvalid = false; | |
11963 | break; | |
11964 | } else { | |
11965 | if (env->sau.rlar[r] & 2) { | |
11966 | sattrs->nsc = true; | |
11967 | } else { | |
11968 | sattrs->ns = true; | |
11969 | } | |
11970 | sattrs->srvalid = true; | |
11971 | sattrs->sregion = r; | |
11972 | } | |
9d2b5a58 PM |
11973 | } else { |
11974 | /* | |
11975 | * Address not in this region. We must check whether the | |
11976 | * region covers addresses in the same page as our address. | |
11977 | * In that case we must not report a size that covers the | |
11978 | * whole page for a subsequent hit against a different MPU | |
11979 | * region or the background region, because it would result | |
11980 | * in incorrect TLB hits for subsequent accesses to | |
11981 | * addresses that are in this MPU region. | |
11982 | */ | |
11983 | if (limit >= base && | |
11984 | ranges_overlap(base, limit - base + 1, | |
11985 | addr_page_base, | |
11986 | TARGET_PAGE_SIZE)) { | |
11987 | sattrs->subpage = true; | |
11988 | } | |
35337cc3 PM |
11989 | } |
11990 | } | |
11991 | } | |
7e3f1223 TR |
11992 | break; |
11993 | } | |
35337cc3 | 11994 | |
7e3f1223 TR |
11995 | /* |
11996 | * The IDAU will override the SAU lookup results if it specifies | |
11997 | * higher security than the SAU does. | |
11998 | */ | |
11999 | if (!idau_ns) { | |
12000 | if (sattrs->ns || (!idau_nsc && sattrs->nsc)) { | |
12001 | sattrs->ns = false; | |
12002 | sattrs->nsc = idau_nsc; | |
181962fd | 12003 | } |
35337cc3 PM |
12004 | } |
12005 | } | |
12006 | ||
787a7e76 | 12007 | bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, |
54317c0f PM |
12008 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
12009 | hwaddr *phys_ptr, MemTxAttrs *txattrs, | |
72042435 PM |
12010 | int *prot, bool *is_subpage, |
12011 | ARMMMUFaultInfo *fi, uint32_t *mregion) | |
54317c0f PM |
12012 | { |
12013 | /* Perform a PMSAv8 MPU lookup (without also doing the SAU check | |
12014 | * that a full phys-to-virt translation does). | |
12015 | * mregion is (if not NULL) set to the region number which matched, | |
12016 | * or -1 if no region number is returned (MPU off, address did not | |
12017 | * hit a region, address hit in multiple regions). | |
72042435 PM |
12018 | * We set is_subpage to true if the region hit doesn't cover the |
12019 | * entire TARGET_PAGE the address is within. | |
54317c0f | 12020 | */ |
2fc0cc0e | 12021 | ARMCPU *cpu = env_archcpu(env); |
504e3cc3 | 12022 | bool is_user = regime_is_user(env, mmu_idx); |
62c58ee0 | 12023 | uint32_t secure = regime_is_secure(env, mmu_idx); |
504e3cc3 PM |
12024 | int n; |
12025 | int matchregion = -1; | |
12026 | bool hit = false; | |
72042435 PM |
12027 | uint32_t addr_page_base = address & TARGET_PAGE_MASK; |
12028 | uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); | |
504e3cc3 | 12029 | |
72042435 | 12030 | *is_subpage = false; |
504e3cc3 PM |
12031 | *phys_ptr = address; |
12032 | *prot = 0; | |
54317c0f PM |
12033 | if (mregion) { |
12034 | *mregion = -1; | |
35337cc3 PM |
12035 | } |
12036 | ||
504e3cc3 PM |
12037 | /* Unlike the ARM ARM pseudocode, we don't need to check whether this |
12038 | * was an exception vector read from the vector table (which is always | |
12039 | * done using the default system address map), because those accesses | |
12040 | * are done in arm_v7m_load_vector(), which always does a direct | |
12041 | * read using address_space_ldl(), rather than going via this function. | |
12042 | */ | |
12043 | if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ | |
12044 | hit = true; | |
12045 | } else if (m_is_ppb_region(env, address)) { | |
12046 | hit = true; | |
504e3cc3 | 12047 | } else { |
cff21316 PM |
12048 | if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) { |
12049 | hit = true; | |
12050 | } | |
12051 | ||
504e3cc3 PM |
12052 | for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { |
12053 | /* region search */ | |
12054 | /* Note that the base address is bits [31:5] from the register | |
12055 | * with bits [4:0] all zeroes, but the limit address is bits | |
12056 | * [31:5] from the register with bits [4:0] all ones. | |
12057 | */ | |
62c58ee0 PM |
12058 | uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f; |
12059 | uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f; | |
504e3cc3 | 12060 | |
62c58ee0 | 12061 | if (!(env->pmsav8.rlar[secure][n] & 0x1)) { |
504e3cc3 PM |
12062 | /* Region disabled */ |
12063 | continue; | |
12064 | } | |
12065 | ||
12066 | if (address < base || address > limit) { | |
9d2b5a58 PM |
12067 | /* |
12068 | * Address not in this region. We must check whether the | |
12069 | * region covers addresses in the same page as our address. | |
12070 | * In that case we must not report a size that covers the | |
12071 | * whole page for a subsequent hit against a different MPU | |
12072 | * region or the background region, because it would result in | |
12073 | * incorrect TLB hits for subsequent accesses to addresses that | |
12074 | * are in this MPU region. | |
12075 | */ | |
12076 | if (limit >= base && | |
12077 | ranges_overlap(base, limit - base + 1, | |
12078 | addr_page_base, | |
12079 | TARGET_PAGE_SIZE)) { | |
12080 | *is_subpage = true; | |
12081 | } | |
504e3cc3 PM |
12082 | continue; |
12083 | } | |
12084 | ||
72042435 PM |
12085 | if (base > addr_page_base || limit < addr_page_limit) { |
12086 | *is_subpage = true; | |
12087 | } | |
12088 | ||
cff21316 | 12089 | if (matchregion != -1) { |
504e3cc3 PM |
12090 | /* Multiple regions match -- always a failure (unlike |
12091 | * PMSAv7 where highest-numbered-region wins) | |
12092 | */ | |
3f551b5b PM |
12093 | fi->type = ARMFault_Permission; |
12094 | fi->level = 1; | |
504e3cc3 PM |
12095 | return true; |
12096 | } | |
12097 | ||
12098 | matchregion = n; | |
12099 | hit = true; | |
504e3cc3 PM |
12100 | } |
12101 | } | |
12102 | ||
12103 | if (!hit) { | |
12104 | /* background fault */ | |
3f551b5b | 12105 | fi->type = ARMFault_Background; |
504e3cc3 PM |
12106 | return true; |
12107 | } | |
12108 | ||
12109 | if (matchregion == -1) { | |
12110 | /* hit using the background region */ | |
12111 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | |
12112 | } else { | |
62c58ee0 PM |
12113 | uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2); |
12114 | uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1); | |
cad8e2e3 PM |
12115 | bool pxn = false; |
12116 | ||
12117 | if (arm_feature(env, ARM_FEATURE_V8_1M)) { | |
12118 | pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1); | |
12119 | } | |
504e3cc3 PM |
12120 | |
12121 | if (m_is_system_region(env, address)) { | |
12122 | /* System space is always execute never */ | |
12123 | xn = 1; | |
12124 | } | |
12125 | ||
12126 | *prot = simple_ap_to_rw_prot(env, mmu_idx, ap); | |
cad8e2e3 | 12127 | if (*prot && !xn && !(pxn && !is_user)) { |
504e3cc3 PM |
12128 | *prot |= PAGE_EXEC; |
12129 | } | |
12130 | /* We don't need to look the attribute up in the MAIR0/MAIR1 | |
12131 | * registers because that only tells us about cacheability. | |
12132 | */ | |
54317c0f PM |
12133 | if (mregion) { |
12134 | *mregion = matchregion; | |
12135 | } | |
504e3cc3 PM |
12136 | } |
12137 | ||
3f551b5b PM |
12138 | fi->type = ARMFault_Permission; |
12139 | fi->level = 1; | |
504e3cc3 PM |
12140 | return !(*prot & (1 << access_type)); |
12141 | } | |
12142 | ||
54317c0f PM |
12143 | |
12144 | static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, | |
12145 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
12146 | hwaddr *phys_ptr, MemTxAttrs *txattrs, | |
72042435 PM |
12147 | int *prot, target_ulong *page_size, |
12148 | ARMMMUFaultInfo *fi) | |
54317c0f PM |
12149 | { |
12150 | uint32_t secure = regime_is_secure(env, mmu_idx); | |
12151 | V8M_SAttributes sattrs = {}; | |
72042435 PM |
12152 | bool ret; |
12153 | bool mpu_is_subpage; | |
54317c0f PM |
12154 | |
12155 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
12156 | v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs); | |
12157 | if (access_type == MMU_INST_FETCH) { | |
12158 | /* Instruction fetches always use the MMU bank and the | |
12159 | * transaction attribute determined by the fetch address, | |
12160 | * regardless of CPU state. This is painful for QEMU | |
12161 | * to handle, because it would mean we need to encode | |
12162 | * into the mmu_idx not just the (user, negpri) information | |
12163 | * for the current security state but also that for the | |
12164 | * other security state, which would balloon the number | |
12165 | * of mmu_idx values needed alarmingly. | |
12166 | * Fortunately we can avoid this because it's not actually | |
12167 | * possible to arbitrarily execute code from memory with | |
12168 | * the wrong security attribute: it will always generate | |
12169 | * an exception of some kind or another, apart from the | |
12170 | * special case of an NS CPU executing an SG instruction | |
12171 | * in S&NSC memory. So we always just fail the translation | |
12172 | * here and sort things out in the exception handler | |
12173 | * (including possibly emulating an SG instruction). | |
12174 | */ | |
12175 | if (sattrs.ns != !secure) { | |
3f551b5b PM |
12176 | if (sattrs.nsc) { |
12177 | fi->type = ARMFault_QEMU_NSCExec; | |
12178 | } else { | |
12179 | fi->type = ARMFault_QEMU_SFault; | |
12180 | } | |
72042435 | 12181 | *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; |
54317c0f PM |
12182 | *phys_ptr = address; |
12183 | *prot = 0; | |
12184 | return true; | |
12185 | } | |
12186 | } else { | |
12187 | /* For data accesses we always use the MMU bank indicated | |
12188 | * by the current CPU state, but the security attributes | |
12189 | * might downgrade a secure access to nonsecure. | |
12190 | */ | |
12191 | if (sattrs.ns) { | |
12192 | txattrs->secure = false; | |
12193 | } else if (!secure) { | |
12194 | /* NS access to S memory must fault. | |
12195 | * Architecturally we should first check whether the | |
12196 | * MPU information for this address indicates that we | |
12197 | * are doing an unaligned access to Device memory, which | |
12198 | * should generate a UsageFault instead. QEMU does not | |
12199 | * currently check for that kind of unaligned access though. | |
12200 | * If we added it we would need to do so as a special case | |
12201 | * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). | |
12202 | */ | |
3f551b5b | 12203 | fi->type = ARMFault_QEMU_SFault; |
72042435 | 12204 | *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; |
54317c0f PM |
12205 | *phys_ptr = address; |
12206 | *prot = 0; | |
12207 | return true; | |
12208 | } | |
12209 | } | |
12210 | } | |
12211 | ||
72042435 PM |
12212 | ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, |
12213 | txattrs, prot, &mpu_is_subpage, fi, NULL); | |
72042435 PM |
12214 | *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; |
12215 | return ret; | |
54317c0f PM |
12216 | } |
12217 | ||
13689d43 | 12218 | static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, |
03ae85f8 | 12219 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
53a4e5c5 PM |
12220 | hwaddr *phys_ptr, int *prot, |
12221 | ARMMMUFaultInfo *fi) | |
9ee6e8bb PB |
12222 | { |
12223 | int n; | |
12224 | uint32_t mask; | |
12225 | uint32_t base; | |
0480f69a | 12226 | bool is_user = regime_is_user(env, mmu_idx); |
9ee6e8bb | 12227 | |
3279adb9 PM |
12228 | if (regime_translation_disabled(env, mmu_idx)) { |
12229 | /* MPU disabled. */ | |
12230 | *phys_ptr = address; | |
12231 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
12232 | return false; | |
12233 | } | |
12234 | ||
9ee6e8bb PB |
12235 | *phys_ptr = address; |
12236 | for (n = 7; n >= 0; n--) { | |
554b0b09 | 12237 | base = env->cp15.c6_region[n]; |
87c3d486 | 12238 | if ((base & 1) == 0) { |
554b0b09 | 12239 | continue; |
87c3d486 | 12240 | } |
554b0b09 PM |
12241 | mask = 1 << ((base >> 1) & 0x1f); |
12242 | /* Keep this shift separate from the above to avoid an | |
12243 | (undefined) << 32. */ | |
12244 | mask = (mask << 1) - 1; | |
87c3d486 | 12245 | if (((base ^ address) & ~mask) == 0) { |
554b0b09 | 12246 | break; |
87c3d486 | 12247 | } |
9ee6e8bb | 12248 | } |
87c3d486 | 12249 | if (n < 0) { |
53a4e5c5 | 12250 | fi->type = ARMFault_Background; |
b7cc4e82 | 12251 | return true; |
87c3d486 | 12252 | } |
9ee6e8bb | 12253 | |
03ae85f8 | 12254 | if (access_type == MMU_INST_FETCH) { |
7e09797c | 12255 | mask = env->cp15.pmsav5_insn_ap; |
9ee6e8bb | 12256 | } else { |
7e09797c | 12257 | mask = env->cp15.pmsav5_data_ap; |
9ee6e8bb PB |
12258 | } |
12259 | mask = (mask >> (n * 4)) & 0xf; | |
12260 | switch (mask) { | |
12261 | case 0: | |
53a4e5c5 PM |
12262 | fi->type = ARMFault_Permission; |
12263 | fi->level = 1; | |
b7cc4e82 | 12264 | return true; |
9ee6e8bb | 12265 | case 1: |
87c3d486 | 12266 | if (is_user) { |
53a4e5c5 PM |
12267 | fi->type = ARMFault_Permission; |
12268 | fi->level = 1; | |
b7cc4e82 | 12269 | return true; |
87c3d486 | 12270 | } |
554b0b09 PM |
12271 | *prot = PAGE_READ | PAGE_WRITE; |
12272 | break; | |
9ee6e8bb | 12273 | case 2: |
554b0b09 | 12274 | *prot = PAGE_READ; |
87c3d486 | 12275 | if (!is_user) { |
554b0b09 | 12276 | *prot |= PAGE_WRITE; |
87c3d486 | 12277 | } |
554b0b09 | 12278 | break; |
9ee6e8bb | 12279 | case 3: |
554b0b09 PM |
12280 | *prot = PAGE_READ | PAGE_WRITE; |
12281 | break; | |
9ee6e8bb | 12282 | case 5: |
87c3d486 | 12283 | if (is_user) { |
53a4e5c5 PM |
12284 | fi->type = ARMFault_Permission; |
12285 | fi->level = 1; | |
b7cc4e82 | 12286 | return true; |
87c3d486 | 12287 | } |
554b0b09 PM |
12288 | *prot = PAGE_READ; |
12289 | break; | |
9ee6e8bb | 12290 | case 6: |
554b0b09 PM |
12291 | *prot = PAGE_READ; |
12292 | break; | |
9ee6e8bb | 12293 | default: |
554b0b09 | 12294 | /* Bad permission. */ |
53a4e5c5 PM |
12295 | fi->type = ARMFault_Permission; |
12296 | fi->level = 1; | |
b7cc4e82 | 12297 | return true; |
9ee6e8bb | 12298 | } |
3ad493fc | 12299 | *prot |= PAGE_EXEC; |
b7cc4e82 | 12300 | return false; |
9ee6e8bb PB |
12301 | } |
12302 | ||
5b2d261d AB |
12303 | /* Combine either inner or outer cacheability attributes for normal |
12304 | * memory, according to table D4-42 and pseudocode procedure | |
12305 | * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). | |
12306 | * | |
12307 | * NB: only stage 1 includes allocation hints (RW bits), leading to | |
12308 | * some asymmetry. | |
12309 | */ | |
12310 | static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2) | |
12311 | { | |
12312 | if (s1 == 4 || s2 == 4) { | |
12313 | /* non-cacheable has precedence */ | |
12314 | return 4; | |
12315 | } else if (extract32(s1, 2, 2) == 0 || extract32(s1, 2, 2) == 2) { | |
12316 | /* stage 1 write-through takes precedence */ | |
12317 | return s1; | |
12318 | } else if (extract32(s2, 2, 2) == 2) { | |
12319 | /* stage 2 write-through takes precedence, but the allocation hint | |
12320 | * is still taken from stage 1 | |
12321 | */ | |
12322 | return (2 << 2) | extract32(s1, 0, 2); | |
12323 | } else { /* write-back */ | |
12324 | return s1; | |
12325 | } | |
12326 | } | |
12327 | ||
12328 | /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 | |
12329 | * and CombineS1S2Desc() | |
12330 | * | |
12331 | * @s1: Attributes from stage 1 walk | |
12332 | * @s2: Attributes from stage 2 walk | |
12333 | */ | |
12334 | static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) | |
12335 | { | |
337a03f0 | 12336 | uint8_t s1lo, s2lo, s1hi, s2hi; |
5b2d261d | 12337 | ARMCacheAttrs ret; |
337a03f0 RH |
12338 | bool tagged = false; |
12339 | ||
12340 | if (s1.attrs == 0xf0) { | |
12341 | tagged = true; | |
12342 | s1.attrs = 0xff; | |
12343 | } | |
12344 | ||
12345 | s1lo = extract32(s1.attrs, 0, 4); | |
12346 | s2lo = extract32(s2.attrs, 0, 4); | |
12347 | s1hi = extract32(s1.attrs, 4, 4); | |
12348 | s2hi = extract32(s2.attrs, 4, 4); | |
5b2d261d AB |
12349 | |
12350 | /* Combine shareability attributes (table D4-43) */ | |
12351 | if (s1.shareability == 2 || s2.shareability == 2) { | |
12352 | /* if either are outer-shareable, the result is outer-shareable */ | |
12353 | ret.shareability = 2; | |
12354 | } else if (s1.shareability == 3 || s2.shareability == 3) { | |
12355 | /* if either are inner-shareable, the result is inner-shareable */ | |
12356 | ret.shareability = 3; | |
12357 | } else { | |
12358 | /* both non-shareable */ | |
12359 | ret.shareability = 0; | |
12360 | } | |
12361 | ||
12362 | /* Combine memory type and cacheability attributes */ | |
12363 | if (s1hi == 0 || s2hi == 0) { | |
12364 | /* Device has precedence over normal */ | |
12365 | if (s1lo == 0 || s2lo == 0) { | |
12366 | /* nGnRnE has precedence over anything */ | |
12367 | ret.attrs = 0; | |
12368 | } else if (s1lo == 4 || s2lo == 4) { | |
12369 | /* non-Reordering has precedence over Reordering */ | |
12370 | ret.attrs = 4; /* nGnRE */ | |
12371 | } else if (s1lo == 8 || s2lo == 8) { | |
12372 | /* non-Gathering has precedence over Gathering */ | |
12373 | ret.attrs = 8; /* nGRE */ | |
12374 | } else { | |
12375 | ret.attrs = 0xc; /* GRE */ | |
12376 | } | |
12377 | ||
12378 | /* Any location for which the resultant memory type is any | |
12379 | * type of Device memory is always treated as Outer Shareable. | |
12380 | */ | |
12381 | ret.shareability = 2; | |
12382 | } else { /* Normal memory */ | |
12383 | /* Outer/inner cacheability combine independently */ | |
12384 | ret.attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4 | |
12385 | | combine_cacheattr_nibble(s1lo, s2lo); | |
12386 | ||
12387 | if (ret.attrs == 0x44) { | |
12388 | /* Any location for which the resultant memory type is Normal | |
12389 | * Inner Non-cacheable, Outer Non-cacheable is always treated | |
12390 | * as Outer Shareable. | |
12391 | */ | |
12392 | ret.shareability = 2; | |
12393 | } | |
12394 | } | |
12395 | ||
337a03f0 RH |
12396 | /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */ |
12397 | if (tagged && ret.attrs == 0xff) { | |
12398 | ret.attrs = 0xf0; | |
12399 | } | |
12400 | ||
5b2d261d AB |
12401 | return ret; |
12402 | } | |
12403 | ||
12404 | ||
702a9357 PM |
12405 | /* get_phys_addr - get the physical address for this virtual address |
12406 | * | |
12407 | * Find the physical address corresponding to the given virtual address, | |
12408 | * by doing a translation table walk on MMU based systems or using the | |
12409 | * MPU state on MPU based systems. | |
12410 | * | |
b7cc4e82 PC |
12411 | * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, |
12412 | * prot and page_size may not be filled in, and the populated fsr value provides | |
702a9357 PM |
12413 | * information on why the translation aborted, in the format of a |
12414 | * DFSR/IFSR fault register, with the following caveats: | |
12415 | * * we honour the short vs long DFSR format differences. | |
12416 | * * the WnR bit is never set (the caller must do this). | |
f6bda88f | 12417 | * * for PSMAv5 based systems we don't bother to return a full FSR format |
702a9357 PM |
12418 | * value. |
12419 | * | |
12420 | * @env: CPUARMState | |
12421 | * @address: virtual address to get physical address for | |
12422 | * @access_type: 0 for read, 1 for write, 2 for execute | |
d3649702 | 12423 | * @mmu_idx: MMU index indicating required translation regime |
702a9357 | 12424 | * @phys_ptr: set to the physical address corresponding to the virtual address |
8bf5b6a9 | 12425 | * @attrs: set to the memory transaction attributes to use |
702a9357 PM |
12426 | * @prot: set to the permissions for the page containing phys_ptr |
12427 | * @page_size: set to the size of the page containing phys_ptr | |
5b2d261d AB |
12428 | * @fi: set to fault info if the translation fails |
12429 | * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes | |
702a9357 | 12430 | */ |
ebae861f PMD |
12431 | bool get_phys_addr(CPUARMState *env, target_ulong address, |
12432 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
12433 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, | |
12434 | target_ulong *page_size, | |
12435 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) | |
9ee6e8bb | 12436 | { |
7879460a RDC |
12437 | ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx); |
12438 | ||
12439 | if (mmu_idx != s1_mmu_idx) { | |
9b539263 | 12440 | /* Call ourselves recursively to do the stage 1 and then stage 2 |
7879460a | 12441 | * translations if mmu_idx is a two-stage regime. |
0480f69a | 12442 | */ |
9b539263 EI |
12443 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
12444 | hwaddr ipa; | |
12445 | int s2_prot; | |
12446 | int ret; | |
5b2d261d | 12447 | ARMCacheAttrs cacheattrs2 = {}; |
b1a10c86 RDC |
12448 | ARMMMUIdx s2_mmu_idx; |
12449 | bool is_el0; | |
9b539263 | 12450 | |
7879460a RDC |
12451 | ret = get_phys_addr(env, address, access_type, s1_mmu_idx, &ipa, |
12452 | attrs, prot, page_size, fi, cacheattrs); | |
9b539263 EI |
12453 | |
12454 | /* If S1 fails or S2 is disabled, return early. */ | |
97fa9350 | 12455 | if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) { |
9b539263 EI |
12456 | *phys_ptr = ipa; |
12457 | return ret; | |
12458 | } | |
12459 | ||
b1a10c86 RDC |
12460 | s2_mmu_idx = attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; |
12461 | is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0; | |
12462 | ||
9b539263 | 12463 | /* S1 is done. Now do S2 translation. */ |
b1a10c86 | 12464 | ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, is_el0, |
9b539263 | 12465 | phys_ptr, attrs, &s2_prot, |
7e98e21c | 12466 | page_size, fi, &cacheattrs2); |
9b539263 EI |
12467 | fi->s2addr = ipa; |
12468 | /* Combine the S1 and S2 perms. */ | |
12469 | *prot &= s2_prot; | |
5b2d261d | 12470 | |
7e98e21c RH |
12471 | /* If S2 fails, return early. */ |
12472 | if (ret) { | |
12473 | return ret; | |
5b2d261d AB |
12474 | } |
12475 | ||
7e98e21c | 12476 | /* Combine the S1 and S2 cache attributes. */ |
e04a5752 | 12477 | if (arm_hcr_el2_eff(env) & HCR_DC) { |
7e98e21c RH |
12478 | /* |
12479 | * HCR.DC forces the first stage attributes to | |
12480 | * Normal Non-Shareable, | |
12481 | * Inner Write-Back Read-Allocate Write-Allocate, | |
12482 | * Outer Write-Back Read-Allocate Write-Allocate. | |
337a03f0 | 12483 | * Do not overwrite Tagged within attrs. |
7e98e21c | 12484 | */ |
337a03f0 RH |
12485 | if (cacheattrs->attrs != 0xf0) { |
12486 | cacheattrs->attrs = 0xff; | |
12487 | } | |
7e98e21c RH |
12488 | cacheattrs->shareability = 0; |
12489 | } | |
12490 | *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2); | |
b1a10c86 RDC |
12491 | |
12492 | /* Check if IPA translates to secure or non-secure PA space. */ | |
12493 | if (arm_is_secure_below_el3(env)) { | |
12494 | if (attrs->secure) { | |
12495 | attrs->secure = | |
12496 | !(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW)); | |
12497 | } else { | |
12498 | attrs->secure = | |
12499 | !((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA | VTCR_NSW)) | |
12500 | || (env->cp15.vstcr_el2.raw_tcr & VSTCR_SA)); | |
12501 | } | |
12502 | } | |
7e98e21c | 12503 | return 0; |
9b539263 EI |
12504 | } else { |
12505 | /* | |
12506 | * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. | |
12507 | */ | |
8bd5c820 | 12508 | mmu_idx = stage_1_mmu_idx(mmu_idx); |
9b539263 | 12509 | } |
0480f69a | 12510 | } |
d3649702 | 12511 | |
8bf5b6a9 PM |
12512 | /* The page table entries may downgrade secure to non-secure, but |
12513 | * cannot upgrade an non-secure translation regime's attributes | |
12514 | * to secure. | |
12515 | */ | |
12516 | attrs->secure = regime_is_secure(env, mmu_idx); | |
0995bf8c | 12517 | attrs->user = regime_is_user(env, mmu_idx); |
8bf5b6a9 | 12518 | |
0480f69a PM |
12519 | /* Fast Context Switch Extension. This doesn't exist at all in v8. |
12520 | * In v7 and earlier it affects all stage 1 translations. | |
12521 | */ | |
97fa9350 | 12522 | if (address < 0x02000000 && mmu_idx != ARMMMUIdx_Stage2 |
0480f69a PM |
12523 | && !arm_feature(env, ARM_FEATURE_V8)) { |
12524 | if (regime_el(env, mmu_idx) == 3) { | |
12525 | address += env->cp15.fcseidr_s; | |
12526 | } else { | |
12527 | address += env->cp15.fcseidr_ns; | |
12528 | } | |
54bf36ed | 12529 | } |
9ee6e8bb | 12530 | |
3279adb9 | 12531 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
c9f9f124 | 12532 | bool ret; |
f6bda88f | 12533 | *page_size = TARGET_PAGE_SIZE; |
3279adb9 | 12534 | |
504e3cc3 PM |
12535 | if (arm_feature(env, ARM_FEATURE_V8)) { |
12536 | /* PMSAv8 */ | |
12537 | ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, | |
72042435 | 12538 | phys_ptr, attrs, prot, page_size, fi); |
504e3cc3 | 12539 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
3279adb9 PM |
12540 | /* PMSAv7 */ |
12541 | ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, | |
e5e40999 | 12542 | phys_ptr, prot, page_size, fi); |
3279adb9 PM |
12543 | } else { |
12544 | /* Pre-v7 MPU */ | |
12545 | ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, | |
53a4e5c5 | 12546 | phys_ptr, prot, fi); |
3279adb9 PM |
12547 | } |
12548 | qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 | |
c9f9f124 | 12549 | " mmu_idx %u -> %s (prot %c%c%c)\n", |
709e4407 PM |
12550 | access_type == MMU_DATA_LOAD ? "reading" : |
12551 | (access_type == MMU_DATA_STORE ? "writing" : "execute"), | |
c9f9f124 MD |
12552 | (uint32_t)address, mmu_idx, |
12553 | ret ? "Miss" : "Hit", | |
12554 | *prot & PAGE_READ ? 'r' : '-', | |
12555 | *prot & PAGE_WRITE ? 'w' : '-', | |
12556 | *prot & PAGE_EXEC ? 'x' : '-'); | |
12557 | ||
12558 | return ret; | |
f6bda88f PC |
12559 | } |
12560 | ||
3279adb9 PM |
12561 | /* Definitely a real MMU, not an MPU */ |
12562 | ||
0480f69a | 12563 | if (regime_translation_disabled(env, mmu_idx)) { |
337a03f0 RH |
12564 | uint64_t hcr; |
12565 | uint8_t memattr; | |
12566 | ||
cebfb648 RH |
12567 | /* |
12568 | * MMU disabled. S1 addresses within aa64 translation regimes are | |
12569 | * still checked for bounds -- see AArch64.TranslateAddressS1Off. | |
12570 | */ | |
b1a10c86 | 12571 | if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) { |
cebfb648 RH |
12572 | int r_el = regime_el(env, mmu_idx); |
12573 | if (arm_el_is_aa64(env, r_el)) { | |
12574 | int pamax = arm_pamax(env_archcpu(env)); | |
12575 | uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr; | |
12576 | int addrtop, tbi; | |
12577 | ||
12578 | tbi = aa64_va_parameter_tbi(tcr, mmu_idx); | |
12579 | if (access_type == MMU_INST_FETCH) { | |
12580 | tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); | |
12581 | } | |
12582 | tbi = (tbi >> extract64(address, 55, 1)) & 1; | |
12583 | addrtop = (tbi ? 55 : 63); | |
12584 | ||
12585 | if (extract64(address, pamax, addrtop - pamax + 1) != 0) { | |
12586 | fi->type = ARMFault_AddressSize; | |
12587 | fi->level = 0; | |
12588 | fi->stage2 = false; | |
12589 | return 1; | |
12590 | } | |
12591 | ||
12592 | /* | |
12593 | * When TBI is disabled, we've just validated that all of the | |
12594 | * bits above PAMax are zero, so logically we only need to | |
12595 | * clear the top byte for TBI. But it's clearer to follow | |
12596 | * the pseudocode set of addrdesc.paddress. | |
12597 | */ | |
12598 | address = extract64(address, 0, 52); | |
12599 | } | |
12600 | } | |
9ee6e8bb | 12601 | *phys_ptr = address; |
3ad493fc | 12602 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
d4c430a8 | 12603 | *page_size = TARGET_PAGE_SIZE; |
337a03f0 RH |
12604 | |
12605 | /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ | |
12606 | hcr = arm_hcr_el2_eff(env); | |
12607 | cacheattrs->shareability = 0; | |
12608 | if (hcr & HCR_DC) { | |
12609 | if (hcr & HCR_DCT) { | |
12610 | memattr = 0xf0; /* Tagged, Normal, WB, RWA */ | |
12611 | } else { | |
12612 | memattr = 0xff; /* Normal, WB, RWA */ | |
12613 | } | |
12614 | } else if (access_type == MMU_INST_FETCH) { | |
12615 | if (regime_sctlr(env, mmu_idx) & SCTLR_I) { | |
12616 | memattr = 0xee; /* Normal, WT, RA, NT */ | |
12617 | } else { | |
12618 | memattr = 0x44; /* Normal, NC, No */ | |
12619 | } | |
12620 | cacheattrs->shareability = 2; /* outer sharable */ | |
12621 | } else { | |
12622 | memattr = 0x00; /* Device, nGnRnE */ | |
12623 | } | |
12624 | cacheattrs->attrs = memattr; | |
9ee6e8bb | 12625 | return 0; |
0480f69a PM |
12626 | } |
12627 | ||
0480f69a | 12628 | if (regime_using_lpae_format(env, mmu_idx)) { |
ff7de2fc | 12629 | return get_phys_addr_lpae(env, address, access_type, mmu_idx, false, |
bc52bfeb PM |
12630 | phys_ptr, attrs, prot, page_size, |
12631 | fi, cacheattrs); | |
0480f69a | 12632 | } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { |
bc52bfeb PM |
12633 | return get_phys_addr_v6(env, address, access_type, mmu_idx, |
12634 | phys_ptr, attrs, prot, page_size, fi); | |
9ee6e8bb | 12635 | } else { |
bc52bfeb | 12636 | return get_phys_addr_v5(env, address, access_type, mmu_idx, |
f989983e | 12637 | phys_ptr, prot, page_size, fi); |
9ee6e8bb PB |
12638 | } |
12639 | } | |
12640 | ||
0faea0c7 PM |
12641 | hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, |
12642 | MemTxAttrs *attrs) | |
b5ff1b31 | 12643 | { |
00b941e5 | 12644 | ARMCPU *cpu = ARM_CPU(cs); |
d3649702 | 12645 | CPUARMState *env = &cpu->env; |
a8170e5e | 12646 | hwaddr phys_addr; |
d4c430a8 | 12647 | target_ulong page_size; |
b5ff1b31 | 12648 | int prot; |
b7cc4e82 | 12649 | bool ret; |
e14b5a23 | 12650 | ARMMMUFaultInfo fi = {}; |
50494a27 | 12651 | ARMMMUIdx mmu_idx = arm_mmu_idx(env); |
7e98e21c | 12652 | ARMCacheAttrs cacheattrs = {}; |
b5ff1b31 | 12653 | |
0faea0c7 PM |
12654 | *attrs = (MemTxAttrs) {}; |
12655 | ||
a9dd161f | 12656 | ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &phys_addr, |
7e98e21c | 12657 | attrs, &prot, &page_size, &fi, &cacheattrs); |
b5ff1b31 | 12658 | |
b7cc4e82 | 12659 | if (ret) { |
b5ff1b31 | 12660 | return -1; |
00b941e5 | 12661 | } |
b5ff1b31 FB |
12662 | return phys_addr; |
12663 | } | |
12664 | ||
b5ff1b31 | 12665 | #endif |
6ddbc6e4 PB |
12666 | |
12667 | /* Note that signed overflow is undefined in C. The following routines are | |
12668 | careful to use unsigned types where modulo arithmetic is required. | |
12669 | Failure to do so _will_ break on newer gcc. */ | |
12670 | ||
12671 | /* Signed saturating arithmetic. */ | |
12672 | ||
1654b2d6 | 12673 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
12674 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
12675 | { | |
12676 | uint16_t res; | |
12677 | ||
12678 | res = a + b; | |
12679 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
12680 | if (a & 0x8000) | |
12681 | res = 0x8000; | |
12682 | else | |
12683 | res = 0x7fff; | |
12684 | } | |
12685 | return res; | |
12686 | } | |
12687 | ||
1654b2d6 | 12688 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
12689 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
12690 | { | |
12691 | uint8_t res; | |
12692 | ||
12693 | res = a + b; | |
12694 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
12695 | if (a & 0x80) | |
12696 | res = 0x80; | |
12697 | else | |
12698 | res = 0x7f; | |
12699 | } | |
12700 | return res; | |
12701 | } | |
12702 | ||
1654b2d6 | 12703 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
12704 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
12705 | { | |
12706 | uint16_t res; | |
12707 | ||
12708 | res = a - b; | |
12709 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
12710 | if (a & 0x8000) | |
12711 | res = 0x8000; | |
12712 | else | |
12713 | res = 0x7fff; | |
12714 | } | |
12715 | return res; | |
12716 | } | |
12717 | ||
1654b2d6 | 12718 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
12719 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
12720 | { | |
12721 | uint8_t res; | |
12722 | ||
12723 | res = a - b; | |
12724 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
12725 | if (a & 0x80) | |
12726 | res = 0x80; | |
12727 | else | |
12728 | res = 0x7f; | |
12729 | } | |
12730 | return res; | |
12731 | } | |
12732 | ||
12733 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
12734 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
12735 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
12736 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
12737 | #define PFX q | |
12738 | ||
12739 | #include "op_addsub.h" | |
12740 | ||
12741 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 12742 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
12743 | { |
12744 | uint16_t res; | |
12745 | res = a + b; | |
12746 | if (res < a) | |
12747 | res = 0xffff; | |
12748 | return res; | |
12749 | } | |
12750 | ||
460a09c1 | 12751 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 | 12752 | { |
4c4fd3f8 | 12753 | if (a > b) |
6ddbc6e4 PB |
12754 | return a - b; |
12755 | else | |
12756 | return 0; | |
12757 | } | |
12758 | ||
12759 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
12760 | { | |
12761 | uint8_t res; | |
12762 | res = a + b; | |
12763 | if (res < a) | |
12764 | res = 0xff; | |
12765 | return res; | |
12766 | } | |
12767 | ||
12768 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
12769 | { | |
4c4fd3f8 | 12770 | if (a > b) |
6ddbc6e4 PB |
12771 | return a - b; |
12772 | else | |
12773 | return 0; | |
12774 | } | |
12775 | ||
12776 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
12777 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
12778 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
12779 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
12780 | #define PFX uq | |
12781 | ||
12782 | #include "op_addsub.h" | |
12783 | ||
12784 | /* Signed modulo arithmetic. */ | |
12785 | #define SARITH16(a, b, n, op) do { \ | |
12786 | int32_t sum; \ | |
db6e2e65 | 12787 | sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
6ddbc6e4 PB |
12788 | RESULT(sum, n, 16); \ |
12789 | if (sum >= 0) \ | |
12790 | ge |= 3 << (n * 2); \ | |
12791 | } while(0) | |
12792 | ||
12793 | #define SARITH8(a, b, n, op) do { \ | |
12794 | int32_t sum; \ | |
db6e2e65 | 12795 | sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
6ddbc6e4 PB |
12796 | RESULT(sum, n, 8); \ |
12797 | if (sum >= 0) \ | |
12798 | ge |= 1 << n; \ | |
12799 | } while(0) | |
12800 | ||
12801 | ||
12802 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
12803 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
12804 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
12805 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
12806 | #define PFX s | |
12807 | #define ARITH_GE | |
12808 | ||
12809 | #include "op_addsub.h" | |
12810 | ||
12811 | /* Unsigned modulo arithmetic. */ | |
12812 | #define ADD16(a, b, n) do { \ | |
12813 | uint32_t sum; \ | |
12814 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
12815 | RESULT(sum, n, 16); \ | |
a87aa10b | 12816 | if ((sum >> 16) == 1) \ |
6ddbc6e4 PB |
12817 | ge |= 3 << (n * 2); \ |
12818 | } while(0) | |
12819 | ||
12820 | #define ADD8(a, b, n) do { \ | |
12821 | uint32_t sum; \ | |
12822 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
12823 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
12824 | if ((sum >> 8) == 1) \ |
12825 | ge |= 1 << n; \ | |
6ddbc6e4 PB |
12826 | } while(0) |
12827 | ||
12828 | #define SUB16(a, b, n) do { \ | |
12829 | uint32_t sum; \ | |
12830 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
12831 | RESULT(sum, n, 16); \ | |
12832 | if ((sum >> 16) == 0) \ | |
12833 | ge |= 3 << (n * 2); \ | |
12834 | } while(0) | |
12835 | ||
12836 | #define SUB8(a, b, n) do { \ | |
12837 | uint32_t sum; \ | |
12838 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
12839 | RESULT(sum, n, 8); \ | |
12840 | if ((sum >> 8) == 0) \ | |
a87aa10b | 12841 | ge |= 1 << n; \ |
6ddbc6e4 PB |
12842 | } while(0) |
12843 | ||
12844 | #define PFX u | |
12845 | #define ARITH_GE | |
12846 | ||
12847 | #include "op_addsub.h" | |
12848 | ||
12849 | /* Halved signed arithmetic. */ | |
12850 | #define ADD16(a, b, n) \ | |
12851 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
12852 | #define SUB16(a, b, n) \ | |
12853 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
12854 | #define ADD8(a, b, n) \ | |
12855 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
12856 | #define SUB8(a, b, n) \ | |
12857 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
12858 | #define PFX sh | |
12859 | ||
12860 | #include "op_addsub.h" | |
12861 | ||
12862 | /* Halved unsigned arithmetic. */ | |
12863 | #define ADD16(a, b, n) \ | |
12864 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
12865 | #define SUB16(a, b, n) \ | |
12866 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
12867 | #define ADD8(a, b, n) \ | |
12868 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
12869 | #define SUB8(a, b, n) \ | |
12870 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
12871 | #define PFX uh | |
12872 | ||
12873 | #include "op_addsub.h" | |
12874 | ||
12875 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
12876 | { | |
12877 | if (a > b) | |
12878 | return a - b; | |
12879 | else | |
12880 | return b - a; | |
12881 | } | |
12882 | ||
12883 | /* Unsigned sum of absolute byte differences. */ | |
12884 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
12885 | { | |
12886 | uint32_t sum; | |
12887 | sum = do_usad(a, b); | |
12888 | sum += do_usad(a >> 8, b >> 8); | |
bdc3b6f5 | 12889 | sum += do_usad(a >> 16, b >> 16); |
6ddbc6e4 PB |
12890 | sum += do_usad(a >> 24, b >> 24); |
12891 | return sum; | |
12892 | } | |
12893 | ||
12894 | /* For ARMv6 SEL instruction. */ | |
12895 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
12896 | { | |
12897 | uint32_t mask; | |
12898 | ||
12899 | mask = 0; | |
12900 | if (flags & 1) | |
12901 | mask |= 0xff; | |
12902 | if (flags & 2) | |
12903 | mask |= 0xff00; | |
12904 | if (flags & 4) | |
12905 | mask |= 0xff0000; | |
12906 | if (flags & 8) | |
12907 | mask |= 0xff000000; | |
12908 | return (a & mask) | (b & ~mask); | |
12909 | } | |
12910 | ||
aa633469 PM |
12911 | /* CRC helpers. |
12912 | * The upper bytes of val (above the number specified by 'bytes') must have | |
12913 | * been zeroed out by the caller. | |
12914 | */ | |
eb0ecd5a WN |
12915 | uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) |
12916 | { | |
12917 | uint8_t buf[4]; | |
12918 | ||
aa633469 | 12919 | stl_le_p(buf, val); |
eb0ecd5a WN |
12920 | |
12921 | /* zlib crc32 converts the accumulator and output to one's complement. */ | |
12922 | return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | |
12923 | } | |
12924 | ||
12925 | uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | |
12926 | { | |
12927 | uint8_t buf[4]; | |
12928 | ||
aa633469 | 12929 | stl_le_p(buf, val); |
eb0ecd5a WN |
12930 | |
12931 | /* Linux crc32c converts the output to one's complement. */ | |
12932 | return crc32c(acc, buf, bytes) ^ 0xffffffff; | |
12933 | } | |
a9e01311 RH |
12934 | |
12935 | /* Return the exception level to which FP-disabled exceptions should | |
12936 | * be taken, or 0 if FP is enabled. | |
12937 | */ | |
ced31551 | 12938 | int fp_exception_el(CPUARMState *env, int cur_el) |
a9e01311 | 12939 | { |
55faa212 | 12940 | #ifndef CONFIG_USER_ONLY |
d5a6fa2d RH |
12941 | uint64_t hcr_el2; |
12942 | ||
a9e01311 RH |
12943 | /* CPACR and the CPTR registers don't exist before v6, so FP is |
12944 | * always accessible | |
12945 | */ | |
12946 | if (!arm_feature(env, ARM_FEATURE_V6)) { | |
12947 | return 0; | |
12948 | } | |
12949 | ||
d87513c0 PM |
12950 | if (arm_feature(env, ARM_FEATURE_M)) { |
12951 | /* CPACR can cause a NOCP UsageFault taken to current security state */ | |
12952 | if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) { | |
12953 | return 1; | |
12954 | } | |
12955 | ||
12956 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) { | |
12957 | if (!extract32(env->v7m.nsacr, 10, 1)) { | |
12958 | /* FP insns cause a NOCP UsageFault taken to Secure */ | |
12959 | return 3; | |
12960 | } | |
12961 | } | |
12962 | ||
12963 | return 0; | |
12964 | } | |
12965 | ||
d5a6fa2d RH |
12966 | hcr_el2 = arm_hcr_el2_eff(env); |
12967 | ||
a9e01311 RH |
12968 | /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: |
12969 | * 0, 2 : trap EL0 and EL1/PL1 accesses | |
12970 | * 1 : trap only EL0 accesses | |
12971 | * 3 : trap no accesses | |
c2ddb7cf | 12972 | * This register is ignored if E2H+TGE are both set. |
a9e01311 | 12973 | */ |
d5a6fa2d | 12974 | if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { |
c2ddb7cf RH |
12975 | int fpen = extract32(env->cp15.cpacr_el1, 20, 2); |
12976 | ||
12977 | switch (fpen) { | |
12978 | case 0: | |
12979 | case 2: | |
12980 | if (cur_el == 0 || cur_el == 1) { | |
12981 | /* Trap to PL1, which might be EL1 or EL3 */ | |
12982 | if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { | |
12983 | return 3; | |
12984 | } | |
12985 | return 1; | |
12986 | } | |
12987 | if (cur_el == 3 && !is_a64(env)) { | |
12988 | /* Secure PL1 running at EL3 */ | |
a9e01311 RH |
12989 | return 3; |
12990 | } | |
c2ddb7cf RH |
12991 | break; |
12992 | case 1: | |
12993 | if (cur_el == 0) { | |
12994 | return 1; | |
12995 | } | |
12996 | break; | |
12997 | case 3: | |
12998 | break; | |
a9e01311 | 12999 | } |
a9e01311 RH |
13000 | } |
13001 | ||
fc1120a7 PM |
13002 | /* |
13003 | * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode | |
13004 | * to control non-secure access to the FPU. It doesn't have any | |
13005 | * effect if EL3 is AArch64 or if EL3 doesn't exist at all. | |
13006 | */ | |
13007 | if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
13008 | cur_el <= 2 && !arm_is_secure_below_el3(env))) { | |
13009 | if (!extract32(env->cp15.nsacr, 10, 1)) { | |
13010 | /* FP insns act as UNDEF */ | |
13011 | return cur_el == 2 ? 2 : 1; | |
13012 | } | |
13013 | } | |
13014 | ||
d5a6fa2d RH |
13015 | /* |
13016 | * CPTR_EL2 is present in v7VE or v8, and changes format | |
13017 | * with HCR_EL2.E2H (regardless of TGE). | |
a9e01311 | 13018 | */ |
d5a6fa2d RH |
13019 | if (cur_el <= 2) { |
13020 | if (hcr_el2 & HCR_E2H) { | |
13021 | /* Check CPTR_EL2.FPEN. */ | |
13022 | switch (extract32(env->cp15.cptr_el[2], 20, 2)) { | |
13023 | case 1: | |
13024 | if (cur_el != 0 || !(hcr_el2 & HCR_TGE)) { | |
13025 | break; | |
13026 | } | |
13027 | /* fall through */ | |
13028 | case 0: | |
13029 | case 2: | |
13030 | return 2; | |
13031 | } | |
13032 | } else if (arm_is_el2_enabled(env)) { | |
13033 | if (env->cp15.cptr_el[2] & CPTR_TFP) { | |
13034 | return 2; | |
13035 | } | |
13036 | } | |
a9e01311 RH |
13037 | } |
13038 | ||
13039 | /* CPTR_EL3 : present in v8 */ | |
a7b66ada | 13040 | if (env->cp15.cptr_el[3] & CPTR_TFP) { |
a9e01311 RH |
13041 | /* Trap all FP ops to EL3 */ |
13042 | return 3; | |
13043 | } | |
55faa212 | 13044 | #endif |
a9e01311 RH |
13045 | return 0; |
13046 | } | |
13047 | ||
b9f6033c RH |
13048 | /* Return the exception level we're running at if this is our mmu_idx */ |
13049 | int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) | |
13050 | { | |
13051 | if (mmu_idx & ARM_MMU_IDX_M) { | |
13052 | return mmu_idx & ARM_MMU_IDX_M_PRIV; | |
13053 | } | |
13054 | ||
13055 | switch (mmu_idx) { | |
13056 | case ARMMMUIdx_E10_0: | |
13057 | case ARMMMUIdx_E20_0: | |
13058 | case ARMMMUIdx_SE10_0: | |
b6ad6062 | 13059 | case ARMMMUIdx_SE20_0: |
b9f6033c RH |
13060 | return 0; |
13061 | case ARMMMUIdx_E10_1: | |
452ef8cb | 13062 | case ARMMMUIdx_E10_1_PAN: |
b9f6033c | 13063 | case ARMMMUIdx_SE10_1: |
452ef8cb | 13064 | case ARMMMUIdx_SE10_1_PAN: |
b9f6033c RH |
13065 | return 1; |
13066 | case ARMMMUIdx_E2: | |
13067 | case ARMMMUIdx_E20_2: | |
452ef8cb | 13068 | case ARMMMUIdx_E20_2_PAN: |
b6ad6062 RDC |
13069 | case ARMMMUIdx_SE2: |
13070 | case ARMMMUIdx_SE20_2: | |
13071 | case ARMMMUIdx_SE20_2_PAN: | |
b9f6033c RH |
13072 | return 2; |
13073 | case ARMMMUIdx_SE3: | |
13074 | return 3; | |
13075 | default: | |
13076 | g_assert_not_reached(); | |
13077 | } | |
13078 | } | |
13079 | ||
7aab5a8c | 13080 | #ifndef CONFIG_TCG |
65e4655c RH |
13081 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
13082 | { | |
7aab5a8c | 13083 | g_assert_not_reached(); |
65e4655c | 13084 | } |
7aab5a8c | 13085 | #endif |
65e4655c | 13086 | |
164690b2 | 13087 | ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) |
65e4655c | 13088 | { |
b6ad6062 RDC |
13089 | ARMMMUIdx idx; |
13090 | uint64_t hcr; | |
13091 | ||
65e4655c | 13092 | if (arm_feature(env, ARM_FEATURE_M)) { |
50494a27 | 13093 | return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); |
65e4655c RH |
13094 | } |
13095 | ||
6003d980 | 13096 | /* See ARM pseudo-function ELIsInHost. */ |
b9f6033c RH |
13097 | switch (el) { |
13098 | case 0: | |
b6ad6062 RDC |
13099 | hcr = arm_hcr_el2_eff(env); |
13100 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
13101 | idx = ARMMMUIdx_E20_0; | |
13102 | } else { | |
13103 | idx = ARMMMUIdx_E10_0; | |
6003d980 | 13104 | } |
b6ad6062 | 13105 | break; |
b9f6033c | 13106 | case 1: |
66412260 | 13107 | if (env->pstate & PSTATE_PAN) { |
b6ad6062 RDC |
13108 | idx = ARMMMUIdx_E10_1_PAN; |
13109 | } else { | |
13110 | idx = ARMMMUIdx_E10_1; | |
66412260 | 13111 | } |
b6ad6062 | 13112 | break; |
b9f6033c | 13113 | case 2: |
6003d980 | 13114 | /* Note that TGE does not apply at EL2. */ |
b6ad6062 | 13115 | if (arm_hcr_el2_eff(env) & HCR_E2H) { |
66412260 | 13116 | if (env->pstate & PSTATE_PAN) { |
b6ad6062 RDC |
13117 | idx = ARMMMUIdx_E20_2_PAN; |
13118 | } else { | |
13119 | idx = ARMMMUIdx_E20_2; | |
66412260 | 13120 | } |
b6ad6062 RDC |
13121 | } else { |
13122 | idx = ARMMMUIdx_E2; | |
6003d980 | 13123 | } |
b6ad6062 | 13124 | break; |
b9f6033c RH |
13125 | case 3: |
13126 | return ARMMMUIdx_SE3; | |
13127 | default: | |
13128 | g_assert_not_reached(); | |
65e4655c | 13129 | } |
b6ad6062 RDC |
13130 | |
13131 | if (arm_is_secure_below_el3(env)) { | |
13132 | idx &= ~ARM_MMU_IDX_A_NS; | |
13133 | } | |
13134 | ||
13135 | return idx; | |
50494a27 RH |
13136 | } |
13137 | ||
164690b2 RH |
13138 | ARMMMUIdx arm_mmu_idx(CPUARMState *env) |
13139 | { | |
13140 | return arm_mmu_idx_el(env, arm_current_el(env)); | |
13141 | } | |
13142 | ||
64be86ab RH |
13143 | #ifndef CONFIG_USER_ONLY |
13144 | ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) | |
13145 | { | |
13146 | return stage_1_mmu_idx(arm_mmu_idx(env)); | |
13147 | } | |
13148 | #endif | |
13149 | ||
3902bfc6 RH |
13150 | static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, |
13151 | ARMMMUIdx mmu_idx, | |
13152 | CPUARMTBFlags flags) | |
fdd1b228 | 13153 | { |
a729a46b RH |
13154 | DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el); |
13155 | DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); | |
fdd1b228 | 13156 | |
fdd1b228 | 13157 | if (arm_singlestep_active(env)) { |
a729a46b | 13158 | DP_TBFLAG_ANY(flags, SS_ACTIVE, 1); |
fdd1b228 RH |
13159 | } |
13160 | return flags; | |
13161 | } | |
13162 | ||
3902bfc6 RH |
13163 | static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el, |
13164 | ARMMMUIdx mmu_idx, | |
13165 | CPUARMTBFlags flags) | |
43eccfb6 | 13166 | { |
8061a649 RH |
13167 | bool sctlr_b = arm_sctlr_b(env); |
13168 | ||
13169 | if (sctlr_b) { | |
a729a46b | 13170 | DP_TBFLAG_A32(flags, SCTLR__B, 1); |
8061a649 RH |
13171 | } |
13172 | if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { | |
a729a46b | 13173 | DP_TBFLAG_ANY(flags, BE_DATA, 1); |
8061a649 | 13174 | } |
a729a46b | 13175 | DP_TBFLAG_A32(flags, NS, !access_secure_reg(env)); |
43eccfb6 RH |
13176 | |
13177 | return rebuild_hflags_common(env, fp_el, mmu_idx, flags); | |
13178 | } | |
13179 | ||
3902bfc6 RH |
13180 | static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, |
13181 | ARMMMUIdx mmu_idx) | |
6e33ced5 | 13182 | { |
3902bfc6 | 13183 | CPUARMTBFlags flags = {}; |
4479ec30 RH |
13184 | uint32_t ccr = env->v7m.ccr[env->v7m.secure]; |
13185 | ||
13186 | /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */ | |
13187 | if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) { | |
13188 | DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); | |
13189 | } | |
6e33ced5 RH |
13190 | |
13191 | if (arm_v7m_is_handler_mode(env)) { | |
a729a46b | 13192 | DP_TBFLAG_M32(flags, HANDLER, 1); |
6e33ced5 RH |
13193 | } |
13194 | ||
13195 | /* | |
13196 | * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN | |
13197 | * is suppressing them because the requested execution priority | |
13198 | * is less than 0. | |
13199 | */ | |
13200 | if (arm_feature(env, ARM_FEATURE_V8) && | |
13201 | !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && | |
4479ec30 | 13202 | (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) { |
a729a46b | 13203 | DP_TBFLAG_M32(flags, STACKCHECK, 1); |
6e33ced5 RH |
13204 | } |
13205 | ||
13206 | return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); | |
13207 | } | |
13208 | ||
3902bfc6 | 13209 | static CPUARMTBFlags rebuild_hflags_aprofile(CPUARMState *env) |
83f4baef | 13210 | { |
3902bfc6 | 13211 | CPUARMTBFlags flags = {}; |
83f4baef | 13212 | |
a729a46b | 13213 | DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env)); |
83f4baef RH |
13214 | return flags; |
13215 | } | |
13216 | ||
3902bfc6 RH |
13217 | static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, |
13218 | ARMMMUIdx mmu_idx) | |
c747224c | 13219 | { |
3902bfc6 | 13220 | CPUARMTBFlags flags = rebuild_hflags_aprofile(env); |
4479ec30 RH |
13221 | int el = arm_current_el(env); |
13222 | ||
13223 | if (arm_sctlr(env, el) & SCTLR_A) { | |
13224 | DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); | |
13225 | } | |
0a54d68e RH |
13226 | |
13227 | if (arm_el_is_aa64(env, 1)) { | |
a729a46b | 13228 | DP_TBFLAG_A32(flags, VFPEN, 1); |
0a54d68e | 13229 | } |
5bb0a20b | 13230 | |
4479ec30 | 13231 | if (el < 2 && env->cp15.hstr_el2 && |
5bb0a20b | 13232 | (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { |
a729a46b | 13233 | DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); |
5bb0a20b MZ |
13234 | } |
13235 | ||
520d1621 PM |
13236 | if (env->uncached_cpsr & CPSR_IL) { |
13237 | DP_TBFLAG_ANY(flags, PSTATE__IL, 1); | |
13238 | } | |
13239 | ||
83f4baef | 13240 | return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); |
c747224c RH |
13241 | } |
13242 | ||
3902bfc6 RH |
13243 | static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, |
13244 | ARMMMUIdx mmu_idx) | |
a9e01311 | 13245 | { |
3902bfc6 | 13246 | CPUARMTBFlags flags = rebuild_hflags_aprofile(env); |
d4d7503a | 13247 | ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); |
b830a5ee | 13248 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; |
d4d7503a RH |
13249 | uint64_t sctlr; |
13250 | int tbii, tbid; | |
b9adaa70 | 13251 | |
a729a46b | 13252 | DP_TBFLAG_ANY(flags, AARCH64_STATE, 1); |
cd208a1c | 13253 | |
339370b9 | 13254 | /* Get control bits for tagged addresses. */ |
b830a5ee RH |
13255 | tbid = aa64_va_parameter_tbi(tcr, mmu_idx); |
13256 | tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); | |
5d8634f5 | 13257 | |
a729a46b RH |
13258 | DP_TBFLAG_A64(flags, TBII, tbii); |
13259 | DP_TBFLAG_A64(flags, TBID, tbid); | |
d4d7503a RH |
13260 | |
13261 | if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { | |
13262 | int sve_el = sve_exception_el(env, el); | |
13263 | uint32_t zcr_len; | |
5d8634f5 | 13264 | |
d4d7503a RH |
13265 | /* |
13266 | * If SVE is disabled, but FP is enabled, | |
13267 | * then the effective len is 0. | |
13268 | */ | |
13269 | if (sve_el != 0 && fp_el == 0) { | |
13270 | zcr_len = 0; | |
13271 | } else { | |
13272 | zcr_len = sve_zcr_len_for_el(env, el); | |
5d8634f5 | 13273 | } |
a729a46b RH |
13274 | DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); |
13275 | DP_TBFLAG_A64(flags, ZCR_LEN, zcr_len); | |
d4d7503a | 13276 | } |
1db5e96c | 13277 | |
aaec1432 | 13278 | sctlr = regime_sctlr(env, stage1); |
1db5e96c | 13279 | |
4479ec30 RH |
13280 | if (sctlr & SCTLR_A) { |
13281 | DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); | |
13282 | } | |
13283 | ||
8061a649 | 13284 | if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { |
a729a46b | 13285 | DP_TBFLAG_ANY(flags, BE_DATA, 1); |
8061a649 RH |
13286 | } |
13287 | ||
d4d7503a RH |
13288 | if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { |
13289 | /* | |
13290 | * In order to save space in flags, we record only whether | |
13291 | * pauth is "inactive", meaning all insns are implemented as | |
13292 | * a nop, or "active" when some action must be performed. | |
13293 | * The decision of which action to take is left to a helper. | |
13294 | */ | |
13295 | if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { | |
a729a46b | 13296 | DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1); |
1db5e96c | 13297 | } |
d4d7503a | 13298 | } |
0816ef1b | 13299 | |
d4d7503a RH |
13300 | if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { |
13301 | /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ | |
13302 | if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { | |
a729a46b | 13303 | DP_TBFLAG_A64(flags, BT, 1); |
0816ef1b | 13304 | } |
d4d7503a | 13305 | } |
08f1434a | 13306 | |
cc28fc30 | 13307 | /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ |
7a8014ab RH |
13308 | if (!(env->pstate & PSTATE_UAO)) { |
13309 | switch (mmu_idx) { | |
13310 | case ARMMMUIdx_E10_1: | |
13311 | case ARMMMUIdx_E10_1_PAN: | |
13312 | case ARMMMUIdx_SE10_1: | |
13313 | case ARMMMUIdx_SE10_1_PAN: | |
13314 | /* TODO: ARMv8.3-NV */ | |
a729a46b | 13315 | DP_TBFLAG_A64(flags, UNPRIV, 1); |
7a8014ab RH |
13316 | break; |
13317 | case ARMMMUIdx_E20_2: | |
13318 | case ARMMMUIdx_E20_2_PAN: | |
b6ad6062 RDC |
13319 | case ARMMMUIdx_SE20_2: |
13320 | case ARMMMUIdx_SE20_2_PAN: | |
7a8014ab RH |
13321 | /* |
13322 | * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is | |
13323 | * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR. | |
13324 | */ | |
13325 | if (env->cp15.hcr_el2 & HCR_TGE) { | |
a729a46b | 13326 | DP_TBFLAG_A64(flags, UNPRIV, 1); |
7a8014ab RH |
13327 | } |
13328 | break; | |
13329 | default: | |
13330 | break; | |
cc28fc30 | 13331 | } |
cc28fc30 RH |
13332 | } |
13333 | ||
520d1621 PM |
13334 | if (env->pstate & PSTATE_IL) { |
13335 | DP_TBFLAG_ANY(flags, PSTATE__IL, 1); | |
13336 | } | |
13337 | ||
81ae05fa RH |
13338 | if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { |
13339 | /* | |
13340 | * Set MTE_ACTIVE if any access may be Checked, and leave clear | |
13341 | * if all accesses must be Unchecked: | |
13342 | * 1) If no TBI, then there are no tags in the address to check, | |
13343 | * 2) If Tag Check Override, then all accesses are Unchecked, | |
13344 | * 3) If Tag Check Fail == 0, then Checked access have no effect, | |
13345 | * 4) If no Allocation Tag Access, then all accesses are Unchecked. | |
13346 | */ | |
13347 | if (allocation_tag_access_enabled(env, el, sctlr)) { | |
a729a46b | 13348 | DP_TBFLAG_A64(flags, ATA, 1); |
81ae05fa RH |
13349 | if (tbid |
13350 | && !(env->pstate & PSTATE_TCO) | |
13351 | && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) { | |
a729a46b | 13352 | DP_TBFLAG_A64(flags, MTE_ACTIVE, 1); |
81ae05fa RH |
13353 | } |
13354 | } | |
13355 | /* And again for unprivileged accesses, if required. */ | |
a729a46b | 13356 | if (EX_TBFLAG_A64(flags, UNPRIV) |
81ae05fa RH |
13357 | && tbid |
13358 | && !(env->pstate & PSTATE_TCO) | |
2d928adf | 13359 | && (sctlr & SCTLR_TCF0) |
81ae05fa | 13360 | && allocation_tag_access_enabled(env, 0, sctlr)) { |
a729a46b | 13361 | DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); |
81ae05fa RH |
13362 | } |
13363 | /* Cache TCMA as well as TBI. */ | |
a729a46b | 13364 | DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx)); |
81ae05fa RH |
13365 | } |
13366 | ||
d4d7503a RH |
13367 | return rebuild_hflags_common(env, fp_el, mmu_idx, flags); |
13368 | } | |
13369 | ||
3902bfc6 | 13370 | static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env) |
3d74e2e9 RH |
13371 | { |
13372 | int el = arm_current_el(env); | |
13373 | int fp_el = fp_exception_el(env, el); | |
164690b2 | 13374 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); |
3d74e2e9 RH |
13375 | |
13376 | if (is_a64(env)) { | |
13377 | return rebuild_hflags_a64(env, el, fp_el, mmu_idx); | |
13378 | } else if (arm_feature(env, ARM_FEATURE_M)) { | |
13379 | return rebuild_hflags_m32(env, fp_el, mmu_idx); | |
13380 | } else { | |
13381 | return rebuild_hflags_a32(env, fp_el, mmu_idx); | |
13382 | } | |
13383 | } | |
13384 | ||
13385 | void arm_rebuild_hflags(CPUARMState *env) | |
13386 | { | |
13387 | env->hflags = rebuild_hflags_internal(env); | |
13388 | } | |
13389 | ||
19717e9b PM |
13390 | /* |
13391 | * If we have triggered a EL state change we can't rely on the | |
13392 | * translator having passed it to us, we need to recompute. | |
13393 | */ | |
13394 | void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env) | |
13395 | { | |
13396 | int el = arm_current_el(env); | |
13397 | int fp_el = fp_exception_el(env, el); | |
13398 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
3902bfc6 | 13399 | |
19717e9b PM |
13400 | env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); |
13401 | } | |
13402 | ||
14f3c588 RH |
13403 | void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) |
13404 | { | |
13405 | int fp_el = fp_exception_el(env, el); | |
13406 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
13407 | ||
13408 | env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); | |
13409 | } | |
13410 | ||
f80741d1 AB |
13411 | /* |
13412 | * If we have triggered a EL state change we can't rely on the | |
563152e0 | 13413 | * translator having passed it to us, we need to recompute. |
f80741d1 AB |
13414 | */ |
13415 | void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) | |
13416 | { | |
13417 | int el = arm_current_el(env); | |
13418 | int fp_el = fp_exception_el(env, el); | |
13419 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
13420 | env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); | |
13421 | } | |
13422 | ||
14f3c588 RH |
13423 | void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) |
13424 | { | |
13425 | int fp_el = fp_exception_el(env, el); | |
13426 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
13427 | ||
13428 | env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); | |
13429 | } | |
13430 | ||
13431 | void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) | |
13432 | { | |
13433 | int fp_el = fp_exception_el(env, el); | |
13434 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
13435 | ||
13436 | env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx); | |
13437 | } | |
13438 | ||
0ee8b24a PMD |
13439 | static inline void assert_hflags_rebuild_correctly(CPUARMState *env) |
13440 | { | |
13441 | #ifdef CONFIG_DEBUG_TCG | |
3902bfc6 RH |
13442 | CPUARMTBFlags c = env->hflags; |
13443 | CPUARMTBFlags r = rebuild_hflags_internal(env); | |
0ee8b24a | 13444 | |
a378206a RH |
13445 | if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) { |
13446 | fprintf(stderr, "TCG hflags mismatch " | |
13447 | "(current:(0x%08x,0x" TARGET_FMT_lx ")" | |
13448 | " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n", | |
13449 | c.flags, c.flags2, r.flags, r.flags2); | |
0ee8b24a PMD |
13450 | abort(); |
13451 | } | |
13452 | #endif | |
13453 | } | |
13454 | ||
26702213 PM |
13455 | static bool mve_no_pred(CPUARMState *env) |
13456 | { | |
13457 | /* | |
13458 | * Return true if there is definitely no predication of MVE | |
13459 | * instructions by VPR or LTPSIZE. (Returning false even if there | |
13460 | * isn't any predication is OK; generated code will just be | |
13461 | * a little worse.) | |
13462 | * If the CPU does not implement MVE then this TB flag is always 0. | |
13463 | * | |
13464 | * NOTE: if you change this logic, the "recalculate s->mve_no_pred" | |
13465 | * logic in gen_update_fp_context() needs to be updated to match. | |
13466 | * | |
13467 | * We do not include the effect of the ECI bits here -- they are | |
13468 | * tracked in other TB flags. This simplifies the logic for | |
13469 | * "when did we emit code that changes the MVE_NO_PRED TB flag | |
13470 | * and thus need to end the TB?". | |
13471 | */ | |
13472 | if (cpu_isar_feature(aa32_mve, env_archcpu(env))) { | |
13473 | return false; | |
13474 | } | |
13475 | if (env->v7m.vpr) { | |
13476 | return false; | |
13477 | } | |
13478 | if (env->v7m.ltpsize < 4) { | |
13479 | return false; | |
13480 | } | |
13481 | return true; | |
13482 | } | |
13483 | ||
d4d7503a RH |
13484 | void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, |
13485 | target_ulong *cs_base, uint32_t *pflags) | |
13486 | { | |
3902bfc6 | 13487 | CPUARMTBFlags flags; |
d4d7503a | 13488 | |
0ee8b24a | 13489 | assert_hflags_rebuild_correctly(env); |
3902bfc6 | 13490 | flags = env->hflags; |
3d74e2e9 | 13491 | |
a729a46b | 13492 | if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { |
d4d7503a | 13493 | *pc = env->pc; |
d4d7503a | 13494 | if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { |
a729a46b | 13495 | DP_TBFLAG_A64(flags, BTYPE, env->btype); |
08f1434a | 13496 | } |
a9e01311 RH |
13497 | } else { |
13498 | *pc = env->regs[15]; | |
6e33ced5 RH |
13499 | |
13500 | if (arm_feature(env, ARM_FEATURE_M)) { | |
9550d1bd RH |
13501 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && |
13502 | FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) | |
13503 | != env->v7m.secure) { | |
a729a46b | 13504 | DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1); |
9550d1bd RH |
13505 | } |
13506 | ||
13507 | if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && | |
13508 | (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || | |
13509 | (env->v7m.secure && | |
13510 | !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { | |
13511 | /* | |
13512 | * ASPEN is set, but FPCA/SFPA indicate that there is no | |
13513 | * active FP context; we must create a new FP context before | |
13514 | * executing any FP insn. | |
13515 | */ | |
a729a46b | 13516 | DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1); |
9550d1bd RH |
13517 | } |
13518 | ||
13519 | bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; | |
13520 | if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { | |
a729a46b | 13521 | DP_TBFLAG_M32(flags, LSPACT, 1); |
9550d1bd | 13522 | } |
26702213 PM |
13523 | |
13524 | if (mve_no_pred(env)) { | |
13525 | DP_TBFLAG_M32(flags, MVE_NO_PRED, 1); | |
13526 | } | |
6e33ced5 | 13527 | } else { |
bbad7c62 RH |
13528 | /* |
13529 | * Note that XSCALE_CPAR shares bits with VECSTRIDE. | |
13530 | * Note that VECLEN+VECSTRIDE are RES0 for M-profile. | |
13531 | */ | |
13532 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
a729a46b | 13533 | DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); |
bbad7c62 | 13534 | } else { |
a729a46b RH |
13535 | DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); |
13536 | DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); | |
bbad7c62 | 13537 | } |
0a54d68e | 13538 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { |
a729a46b | 13539 | DP_TBFLAG_A32(flags, VFPEN, 1); |
0a54d68e | 13540 | } |
6e33ced5 RH |
13541 | } |
13542 | ||
a729a46b RH |
13543 | DP_TBFLAG_AM32(flags, THUMB, env->thumb); |
13544 | DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits); | |
d4d7503a | 13545 | } |
a9e01311 | 13546 | |
60e12c37 RH |
13547 | /* |
13548 | * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine | |
a9e01311 RH |
13549 | * states defined in the ARM ARM for software singlestep: |
13550 | * SS_ACTIVE PSTATE.SS State | |
13551 | * 0 x Inactive (the TB flag for SS is always 0) | |
13552 | * 1 0 Active-pending | |
13553 | * 1 1 Active-not-pending | |
ae6eb1e9 | 13554 | * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. |
a9e01311 | 13555 | */ |
a729a46b RH |
13556 | if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { |
13557 | DP_TBFLAG_ANY(flags, PSTATE__SS, 1); | |
a9e01311 | 13558 | } |
a9e01311 | 13559 | |
3902bfc6 | 13560 | *pflags = flags.flags; |
a378206a | 13561 | *cs_base = flags.flags2; |
a9e01311 | 13562 | } |
0ab5953b RH |
13563 | |
13564 | #ifdef TARGET_AARCH64 | |
13565 | /* | |
13566 | * The manual says that when SVE is enabled and VQ is widened the | |
13567 | * implementation is allowed to zero the previously inaccessible | |
13568 | * portion of the registers. The corollary to that is that when | |
13569 | * SVE is enabled and VQ is narrowed we are also allowed to zero | |
13570 | * the now inaccessible portion of the registers. | |
13571 | * | |
13572 | * The intent of this is that no predicate bit beyond VQ is ever set. | |
13573 | * Which means that some operations on predicate registers themselves | |
13574 | * may operate on full uint64_t or even unrolled across the maximum | |
13575 | * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally | |
13576 | * may well be cheaper than conditionals to restrict the operation | |
13577 | * to the relevant portion of a uint16_t[16]. | |
13578 | */ | |
13579 | void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) | |
13580 | { | |
13581 | int i, j; | |
13582 | uint64_t pmask; | |
13583 | ||
13584 | assert(vq >= 1 && vq <= ARM_MAX_VQ); | |
2fc0cc0e | 13585 | assert(vq <= env_archcpu(env)->sve_max_vq); |
0ab5953b RH |
13586 | |
13587 | /* Zap the high bits of the zregs. */ | |
13588 | for (i = 0; i < 32; i++) { | |
13589 | memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)); | |
13590 | } | |
13591 | ||
13592 | /* Zap the high bits of the pregs and ffr. */ | |
13593 | pmask = 0; | |
13594 | if (vq & 3) { | |
13595 | pmask = ~(-1ULL << (16 * (vq & 3))); | |
13596 | } | |
13597 | for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) { | |
13598 | for (i = 0; i < 17; ++i) { | |
13599 | env->vfp.pregs[i].p[j] &= pmask; | |
13600 | } | |
13601 | pmask = 0; | |
13602 | } | |
13603 | } | |
13604 | ||
13605 | /* | |
13606 | * Notice a change in SVE vector size when changing EL. | |
13607 | */ | |
9a05f7b6 RH |
13608 | void aarch64_sve_change_el(CPUARMState *env, int old_el, |
13609 | int new_el, bool el0_a64) | |
0ab5953b | 13610 | { |
2fc0cc0e | 13611 | ARMCPU *cpu = env_archcpu(env); |
0ab5953b | 13612 | int old_len, new_len; |
9a05f7b6 | 13613 | bool old_a64, new_a64; |
0ab5953b RH |
13614 | |
13615 | /* Nothing to do if no SVE. */ | |
cd208a1c | 13616 | if (!cpu_isar_feature(aa64_sve, cpu)) { |
0ab5953b RH |
13617 | return; |
13618 | } | |
13619 | ||
13620 | /* Nothing to do if FP is disabled in either EL. */ | |
13621 | if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) { | |
13622 | return; | |
13623 | } | |
13624 | ||
13625 | /* | |
13626 | * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped | |
13627 | * at ELx, or not available because the EL is in AArch32 state, then | |
13628 | * for all purposes other than a direct read, the ZCR_ELx.LEN field | |
13629 | * has an effective value of 0". | |
13630 | * | |
13631 | * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0). | |
13632 | * If we ignore aa32 state, we would fail to see the vq4->vq0 transition | |
13633 | * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that | |
13634 | * we already have the correct register contents when encountering the | |
13635 | * vq0->vq0 transition between EL0->EL1. | |
13636 | */ | |
9a05f7b6 RH |
13637 | old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; |
13638 | old_len = (old_a64 && !sve_exception_el(env, old_el) | |
0ab5953b | 13639 | ? sve_zcr_len_for_el(env, old_el) : 0); |
9a05f7b6 RH |
13640 | new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; |
13641 | new_len = (new_a64 && !sve_exception_el(env, new_el) | |
0ab5953b RH |
13642 | ? sve_zcr_len_for_el(env, new_el) : 0); |
13643 | ||
13644 | /* When changing vector length, clear inaccessible state. */ | |
13645 | if (new_len < old_len) { | |
13646 | aarch64_sve_narrow_vq(env, new_len + 1); | |
13647 | } | |
13648 | } | |
13649 | #endif |