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Commit | Line | Data |
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ed3baad1 PMD |
1 | /* |
2 | * ARM generic helpers. | |
3 | * | |
4 | * This code is licensed under the GNU GPL v2 or later. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0-or-later | |
7 | */ | |
db725815 | 8 | |
74c21bd0 | 9 | #include "qemu/osdep.h" |
63159601 | 10 | #include "qemu/units.h" |
cd617484 | 11 | #include "qemu/log.h" |
194cbc49 | 12 | #include "trace.h" |
b5ff1b31 | 13 | #include "cpu.h" |
ccd38087 | 14 | #include "internals.h" |
2ef6175a | 15 | #include "exec/helper-proto.h" |
1de7afc9 | 16 | #include "qemu/host-utils.h" |
db725815 | 17 | #include "qemu/main-loop.h" |
b8012ecf | 18 | #include "qemu/timer.h" |
1de7afc9 | 19 | #include "qemu/bitops.h" |
eb0ecd5a | 20 | #include "qemu/crc32c.h" |
0442428a | 21 | #include "qemu/qemu-print.h" |
63c91552 | 22 | #include "exec/exec-all.h" |
eb0ecd5a | 23 | #include <zlib.h> /* For crc32 */ |
64552b6b | 24 | #include "hw/irq.h" |
6b5fe137 | 25 | #include "semihosting/semihost.h" |
b2e23725 | 26 | #include "sysemu/cpus.h" |
740b1759 | 27 | #include "sysemu/cpu-timers.h" |
f3a9b694 | 28 | #include "sysemu/kvm.h" |
9d2b5a58 | 29 | #include "qemu/range.h" |
7f7b4e7a | 30 | #include "qapi/qapi-commands-machine-target.h" |
de390645 RH |
31 | #include "qapi/error.h" |
32 | #include "qemu/guest-random.h" | |
91f78c58 PMD |
33 | #ifdef CONFIG_TCG |
34 | #include "arm_ldst.h" | |
7aab5a8c | 35 | #include "exec/cpu_ldst.h" |
6b5fe137 | 36 | #include "semihosting/common-semi.h" |
91f78c58 | 37 | #endif |
cf7c6d10 | 38 | #include "cpregs.h" |
0b03bdfc | 39 | |
352c98e5 LV |
40 | #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ |
41 | ||
affdb64d PM |
42 | static void switch_mode(CPUARMState *env, int mode); |
43 | ||
c4241c7d | 44 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) |
d4e6df63 | 45 | { |
375421cc | 46 | assert(ri->fieldoffset); |
67ed771d | 47 | if (cpreg_field_is_64bit(ri)) { |
c4241c7d | 48 | return CPREG_FIELD64(env, ri); |
22d9e1a9 | 49 | } else { |
c4241c7d | 50 | return CPREG_FIELD32(env, ri); |
22d9e1a9 | 51 | } |
d4e6df63 PM |
52 | } |
53 | ||
c4241c7d PM |
54 | static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
55 | uint64_t value) | |
d4e6df63 | 56 | { |
375421cc | 57 | assert(ri->fieldoffset); |
67ed771d | 58 | if (cpreg_field_is_64bit(ri)) { |
22d9e1a9 PM |
59 | CPREG_FIELD64(env, ri) = value; |
60 | } else { | |
61 | CPREG_FIELD32(env, ri) = value; | |
62 | } | |
d4e6df63 PM |
63 | } |
64 | ||
11f136ee FA |
65 | static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) |
66 | { | |
67 | return (char *)env + ri->fieldoffset; | |
68 | } | |
69 | ||
49a66191 | 70 | uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) |
721fae12 | 71 | { |
59a1c327 | 72 | /* Raw read of a coprocessor register (as needed for migration, etc). */ |
721fae12 | 73 | if (ri->type & ARM_CP_CONST) { |
59a1c327 | 74 | return ri->resetvalue; |
721fae12 | 75 | } else if (ri->raw_readfn) { |
59a1c327 | 76 | return ri->raw_readfn(env, ri); |
721fae12 | 77 | } else if (ri->readfn) { |
59a1c327 | 78 | return ri->readfn(env, ri); |
721fae12 | 79 | } else { |
59a1c327 | 80 | return raw_read(env, ri); |
721fae12 | 81 | } |
721fae12 PM |
82 | } |
83 | ||
59a1c327 | 84 | static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, |
7900e9f1 | 85 | uint64_t v) |
721fae12 PM |
86 | { |
87 | /* Raw write of a coprocessor register (as needed for migration, etc). | |
721fae12 PM |
88 | * Note that constant registers are treated as write-ignored; the |
89 | * caller should check for success by whether a readback gives the | |
90 | * value written. | |
91 | */ | |
92 | if (ri->type & ARM_CP_CONST) { | |
59a1c327 | 93 | return; |
721fae12 | 94 | } else if (ri->raw_writefn) { |
c4241c7d | 95 | ri->raw_writefn(env, ri, v); |
721fae12 | 96 | } else if (ri->writefn) { |
c4241c7d | 97 | ri->writefn(env, ri, v); |
721fae12 | 98 | } else { |
afb2530f | 99 | raw_write(env, ri, v); |
721fae12 | 100 | } |
721fae12 PM |
101 | } |
102 | ||
375421cc PM |
103 | static bool raw_accessors_invalid(const ARMCPRegInfo *ri) |
104 | { | |
105 | /* Return true if the regdef would cause an assertion if you called | |
106 | * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a | |
107 | * program bug for it not to have the NO_RAW flag). | |
108 | * NB that returning false here doesn't necessarily mean that calling | |
109 | * read/write_raw_cp_reg() is safe, because we can't distinguish "has | |
110 | * read/write access functions which are safe for raw use" from "has | |
111 | * read/write access functions which have side effects but has forgotten | |
112 | * to provide raw access functions". | |
113 | * The tests here line up with the conditions in read/write_raw_cp_reg() | |
114 | * and assertions in raw_read()/raw_write(). | |
115 | */ | |
116 | if ((ri->type & ARM_CP_CONST) || | |
117 | ri->fieldoffset || | |
118 | ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { | |
119 | return false; | |
120 | } | |
121 | return true; | |
122 | } | |
123 | ||
b698e4ee | 124 | bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync) |
721fae12 PM |
125 | { |
126 | /* Write the coprocessor state from cpu->env to the (index,value) list. */ | |
127 | int i; | |
128 | bool ok = true; | |
129 | ||
130 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
131 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
132 | const ARMCPRegInfo *ri; | |
b698e4ee | 133 | uint64_t newval; |
59a1c327 | 134 | |
60322b39 | 135 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
136 | if (!ri) { |
137 | ok = false; | |
138 | continue; | |
139 | } | |
7a0e58fa | 140 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
141 | continue; |
142 | } | |
b698e4ee PM |
143 | |
144 | newval = read_raw_cp_reg(&cpu->env, ri); | |
145 | if (kvm_sync) { | |
146 | /* | |
147 | * Only sync if the previous list->cpustate sync succeeded. | |
148 | * Rather than tracking the success/failure state for every | |
149 | * item in the list, we just recheck "does the raw write we must | |
150 | * have made in write_list_to_cpustate() read back OK" here. | |
151 | */ | |
152 | uint64_t oldval = cpu->cpreg_values[i]; | |
153 | ||
154 | if (oldval == newval) { | |
155 | continue; | |
156 | } | |
157 | ||
158 | write_raw_cp_reg(&cpu->env, ri, oldval); | |
159 | if (read_raw_cp_reg(&cpu->env, ri) != oldval) { | |
160 | continue; | |
161 | } | |
162 | ||
163 | write_raw_cp_reg(&cpu->env, ri, newval); | |
164 | } | |
165 | cpu->cpreg_values[i] = newval; | |
721fae12 PM |
166 | } |
167 | return ok; | |
168 | } | |
169 | ||
170 | bool write_list_to_cpustate(ARMCPU *cpu) | |
171 | { | |
172 | int i; | |
173 | bool ok = true; | |
174 | ||
175 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
176 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
177 | uint64_t v = cpu->cpreg_values[i]; | |
721fae12 PM |
178 | const ARMCPRegInfo *ri; |
179 | ||
60322b39 | 180 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
181 | if (!ri) { |
182 | ok = false; | |
183 | continue; | |
184 | } | |
7a0e58fa | 185 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
186 | continue; |
187 | } | |
188 | /* Write value and confirm it reads back as written | |
189 | * (to catch read-only registers and partially read-only | |
190 | * registers where the incoming migration value doesn't match) | |
191 | */ | |
59a1c327 PM |
192 | write_raw_cp_reg(&cpu->env, ri, v); |
193 | if (read_raw_cp_reg(&cpu->env, ri) != v) { | |
721fae12 PM |
194 | ok = false; |
195 | } | |
196 | } | |
197 | return ok; | |
198 | } | |
199 | ||
200 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | |
201 | { | |
202 | ARMCPU *cpu = opaque; | |
5860362d RH |
203 | uint32_t regidx = (uintptr_t)key; |
204 | const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); | |
721fae12 | 205 | |
7a0e58fa | 206 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
207 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); |
208 | /* The value array need not be initialized at this point */ | |
209 | cpu->cpreg_array_len++; | |
210 | } | |
211 | } | |
212 | ||
213 | static void count_cpreg(gpointer key, gpointer opaque) | |
214 | { | |
215 | ARMCPU *cpu = opaque; | |
721fae12 PM |
216 | const ARMCPRegInfo *ri; |
217 | ||
5860362d | 218 | ri = g_hash_table_lookup(cpu->cp_regs, key); |
721fae12 | 219 | |
7a0e58fa | 220 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
221 | cpu->cpreg_array_len++; |
222 | } | |
223 | } | |
224 | ||
225 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | |
226 | { | |
5860362d RH |
227 | uint64_t aidx = cpreg_to_kvm_id((uintptr_t)a); |
228 | uint64_t bidx = cpreg_to_kvm_id((uintptr_t)b); | |
721fae12 | 229 | |
cbf239b7 AR |
230 | if (aidx > bidx) { |
231 | return 1; | |
232 | } | |
233 | if (aidx < bidx) { | |
234 | return -1; | |
235 | } | |
236 | return 0; | |
721fae12 PM |
237 | } |
238 | ||
239 | void init_cpreg_list(ARMCPU *cpu) | |
240 | { | |
241 | /* Initialise the cpreg_tuples[] array based on the cp_regs hash. | |
242 | * Note that we require cpreg_tuples[] to be sorted by key ID. | |
243 | */ | |
57b6d95e | 244 | GList *keys; |
721fae12 PM |
245 | int arraylen; |
246 | ||
57b6d95e | 247 | keys = g_hash_table_get_keys(cpu->cp_regs); |
721fae12 PM |
248 | keys = g_list_sort(keys, cpreg_key_compare); |
249 | ||
250 | cpu->cpreg_array_len = 0; | |
251 | ||
252 | g_list_foreach(keys, count_cpreg, cpu); | |
253 | ||
254 | arraylen = cpu->cpreg_array_len; | |
255 | cpu->cpreg_indexes = g_new(uint64_t, arraylen); | |
256 | cpu->cpreg_values = g_new(uint64_t, arraylen); | |
257 | cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); | |
258 | cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); | |
259 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; | |
260 | cpu->cpreg_array_len = 0; | |
261 | ||
262 | g_list_foreach(keys, add_cpreg_to_list, cpu); | |
263 | ||
264 | assert(cpu->cpreg_array_len == arraylen); | |
265 | ||
266 | g_list_free(keys); | |
267 | } | |
268 | ||
68e9c2fe | 269 | /* |
93dd1e61 | 270 | * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0. |
68e9c2fe EI |
271 | */ |
272 | static CPAccessResult access_el3_aa32ns(CPUARMState *env, | |
3f208fd7 PM |
273 | const ARMCPRegInfo *ri, |
274 | bool isread) | |
68e9c2fe | 275 | { |
93dd1e61 EI |
276 | if (!is_a64(env) && arm_current_el(env) == 3 && |
277 | arm_is_secure_below_el3(env)) { | |
68e9c2fe EI |
278 | return CP_ACCESS_TRAP_UNCATEGORIZED; |
279 | } | |
280 | return CP_ACCESS_OK; | |
281 | } | |
282 | ||
5513c3ab PM |
283 | /* Some secure-only AArch32 registers trap to EL3 if used from |
284 | * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). | |
285 | * Note that an access from Secure EL1 can only happen if EL3 is AArch64. | |
286 | * We assume that the .access field is set to PL1_RW. | |
287 | */ | |
288 | static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, | |
3f208fd7 PM |
289 | const ARMCPRegInfo *ri, |
290 | bool isread) | |
5513c3ab PM |
291 | { |
292 | if (arm_current_el(env) == 3) { | |
293 | return CP_ACCESS_OK; | |
294 | } | |
295 | if (arm_is_secure_below_el3(env)) { | |
926c1b97 RDC |
296 | if (env->cp15.scr_el3 & SCR_EEL2) { |
297 | return CP_ACCESS_TRAP_EL2; | |
298 | } | |
5513c3ab PM |
299 | return CP_ACCESS_TRAP_EL3; |
300 | } | |
301 | /* This will be EL1 NS and EL2 NS, which just UNDEF */ | |
302 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
303 | } | |
304 | ||
59dd089c RDC |
305 | static uint64_t arm_mdcr_el2_eff(CPUARMState *env) |
306 | { | |
307 | return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0; | |
308 | } | |
309 | ||
187f678d PM |
310 | /* Check for traps to "powerdown debug" registers, which are controlled |
311 | * by MDCR.TDOSA | |
312 | */ | |
313 | static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, | |
314 | bool isread) | |
315 | { | |
316 | int el = arm_current_el(env); | |
59dd089c RDC |
317 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
318 | bool mdcr_el2_tdosa = (mdcr_el2 & MDCR_TDOSA) || (mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 319 | (arm_hcr_el2_eff(env) & HCR_TGE); |
187f678d | 320 | |
59dd089c | 321 | if (el < 2 && mdcr_el2_tdosa) { |
187f678d PM |
322 | return CP_ACCESS_TRAP_EL2; |
323 | } | |
324 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { | |
325 | return CP_ACCESS_TRAP_EL3; | |
326 | } | |
327 | return CP_ACCESS_OK; | |
328 | } | |
329 | ||
91b0a238 PM |
330 | /* Check for traps to "debug ROM" registers, which are controlled |
331 | * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. | |
332 | */ | |
333 | static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, | |
334 | bool isread) | |
335 | { | |
336 | int el = arm_current_el(env); | |
59dd089c RDC |
337 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
338 | bool mdcr_el2_tdra = (mdcr_el2 & MDCR_TDRA) || (mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 339 | (arm_hcr_el2_eff(env) & HCR_TGE); |
91b0a238 | 340 | |
59dd089c | 341 | if (el < 2 && mdcr_el2_tdra) { |
91b0a238 PM |
342 | return CP_ACCESS_TRAP_EL2; |
343 | } | |
344 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
345 | return CP_ACCESS_TRAP_EL3; | |
346 | } | |
347 | return CP_ACCESS_OK; | |
348 | } | |
349 | ||
d6c8cf81 PM |
350 | /* Check for traps to general debug registers, which are controlled |
351 | * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. | |
352 | */ | |
353 | static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, | |
354 | bool isread) | |
355 | { | |
356 | int el = arm_current_el(env); | |
59dd089c RDC |
357 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
358 | bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 359 | (arm_hcr_el2_eff(env) & HCR_TGE); |
d6c8cf81 | 360 | |
59dd089c | 361 | if (el < 2 && mdcr_el2_tda) { |
d6c8cf81 PM |
362 | return CP_ACCESS_TRAP_EL2; |
363 | } | |
364 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
365 | return CP_ACCESS_TRAP_EL3; | |
366 | } | |
367 | return CP_ACCESS_OK; | |
368 | } | |
369 | ||
1fce1ba9 PM |
370 | /* Check for traps to performance monitor registers, which are controlled |
371 | * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. | |
372 | */ | |
373 | static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, | |
374 | bool isread) | |
375 | { | |
376 | int el = arm_current_el(env); | |
59dd089c | 377 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
1fce1ba9 | 378 | |
59dd089c | 379 | if (el < 2 && (mdcr_el2 & MDCR_TPM)) { |
1fce1ba9 PM |
380 | return CP_ACCESS_TRAP_EL2; |
381 | } | |
382 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
383 | return CP_ACCESS_TRAP_EL3; | |
384 | } | |
385 | return CP_ACCESS_OK; | |
386 | } | |
387 | ||
84929218 RH |
388 | /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ |
389 | static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, | |
390 | bool isread) | |
391 | { | |
392 | if (arm_current_el(env) == 1) { | |
393 | uint64_t trap = isread ? HCR_TRVM : HCR_TVM; | |
394 | if (arm_hcr_el2_eff(env) & trap) { | |
395 | return CP_ACCESS_TRAP_EL2; | |
396 | } | |
397 | } | |
398 | return CP_ACCESS_OK; | |
399 | } | |
400 | ||
1803d271 RH |
401 | /* Check for traps from EL1 due to HCR_EL2.TSW. */ |
402 | static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri, | |
403 | bool isread) | |
404 | { | |
405 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) { | |
406 | return CP_ACCESS_TRAP_EL2; | |
407 | } | |
408 | return CP_ACCESS_OK; | |
409 | } | |
410 | ||
99602377 RH |
411 | /* Check for traps from EL1 due to HCR_EL2.TACR. */ |
412 | static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri, | |
413 | bool isread) | |
414 | { | |
415 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TACR)) { | |
416 | return CP_ACCESS_TRAP_EL2; | |
417 | } | |
418 | return CP_ACCESS_OK; | |
419 | } | |
420 | ||
30881b73 RH |
421 | /* Check for traps from EL1 due to HCR_EL2.TTLB. */ |
422 | static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri, | |
423 | bool isread) | |
424 | { | |
425 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TTLB)) { | |
426 | return CP_ACCESS_TRAP_EL2; | |
427 | } | |
428 | return CP_ACCESS_OK; | |
429 | } | |
430 | ||
c4241c7d | 431 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
c983fe6c | 432 | { |
2fc0cc0e | 433 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 434 | |
8d5c773e | 435 | raw_write(env, ri, value); |
d10eb08f | 436 | tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ |
c983fe6c PM |
437 | } |
438 | ||
c4241c7d | 439 | static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
08de207b | 440 | { |
2fc0cc0e | 441 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 442 | |
8d5c773e | 443 | if (raw_read(env, ri) != value) { |
08de207b PM |
444 | /* Unlike real hardware the qemu TLB uses virtual addresses, |
445 | * not modified virtual addresses, so this causes a TLB flush. | |
446 | */ | |
d10eb08f | 447 | tlb_flush(CPU(cpu)); |
8d5c773e | 448 | raw_write(env, ri, value); |
08de207b | 449 | } |
08de207b | 450 | } |
c4241c7d PM |
451 | |
452 | static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
453 | uint64_t value) | |
08de207b | 454 | { |
2fc0cc0e | 455 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 456 | |
452a0955 | 457 | if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) |
014406b5 | 458 | && !extended_addresses_enabled(env)) { |
08de207b PM |
459 | /* For VMSA (when not using the LPAE long descriptor page table |
460 | * format) this register includes the ASID, so do a TLB flush. | |
461 | * For PMSA it is purely a process ID and no action is needed. | |
462 | */ | |
d10eb08f | 463 | tlb_flush(CPU(cpu)); |
08de207b | 464 | } |
8d5c773e | 465 | raw_write(env, ri, value); |
08de207b PM |
466 | } |
467 | ||
b4ab8ce9 PM |
468 | /* IS variants of TLB operations must affect all cores */ |
469 | static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
470 | uint64_t value) | |
471 | { | |
29a0af61 | 472 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
473 | |
474 | tlb_flush_all_cpus_synced(cs); | |
475 | } | |
476 | ||
477 | static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
478 | uint64_t value) | |
479 | { | |
29a0af61 | 480 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
481 | |
482 | tlb_flush_all_cpus_synced(cs); | |
483 | } | |
484 | ||
485 | static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
486 | uint64_t value) | |
487 | { | |
29a0af61 | 488 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
489 | |
490 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
491 | } | |
492 | ||
493 | static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
494 | uint64_t value) | |
495 | { | |
29a0af61 | 496 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
497 | |
498 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
499 | } | |
500 | ||
501 | /* | |
502 | * Non-IS variants of TLB operations are upgraded to | |
373e7ffd | 503 | * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to |
b4ab8ce9 PM |
504 | * force broadcast of these operations. |
505 | */ | |
506 | static bool tlb_force_broadcast(CPUARMState *env) | |
507 | { | |
373e7ffd | 508 | return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB); |
b4ab8ce9 PM |
509 | } |
510 | ||
c4241c7d PM |
511 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
512 | uint64_t value) | |
d929823f PM |
513 | { |
514 | /* Invalidate all (TLBIALL) */ | |
527db2be | 515 | CPUState *cs = env_cpu(env); |
00c8cb0a | 516 | |
b4ab8ce9 | 517 | if (tlb_force_broadcast(env)) { |
527db2be RH |
518 | tlb_flush_all_cpus_synced(cs); |
519 | } else { | |
520 | tlb_flush(cs); | |
b4ab8ce9 | 521 | } |
d929823f PM |
522 | } |
523 | ||
c4241c7d PM |
524 | static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
525 | uint64_t value) | |
d929823f PM |
526 | { |
527 | /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ | |
527db2be | 528 | CPUState *cs = env_cpu(env); |
31b030d4 | 529 | |
527db2be | 530 | value &= TARGET_PAGE_MASK; |
b4ab8ce9 | 531 | if (tlb_force_broadcast(env)) { |
527db2be RH |
532 | tlb_flush_page_all_cpus_synced(cs, value); |
533 | } else { | |
534 | tlb_flush_page(cs, value); | |
b4ab8ce9 | 535 | } |
d929823f PM |
536 | } |
537 | ||
c4241c7d PM |
538 | static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
539 | uint64_t value) | |
d929823f PM |
540 | { |
541 | /* Invalidate by ASID (TLBIASID) */ | |
527db2be | 542 | CPUState *cs = env_cpu(env); |
00c8cb0a | 543 | |
b4ab8ce9 | 544 | if (tlb_force_broadcast(env)) { |
527db2be RH |
545 | tlb_flush_all_cpus_synced(cs); |
546 | } else { | |
547 | tlb_flush(cs); | |
b4ab8ce9 | 548 | } |
d929823f PM |
549 | } |
550 | ||
c4241c7d PM |
551 | static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
552 | uint64_t value) | |
d929823f PM |
553 | { |
554 | /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ | |
527db2be | 555 | CPUState *cs = env_cpu(env); |
31b030d4 | 556 | |
527db2be | 557 | value &= TARGET_PAGE_MASK; |
b4ab8ce9 | 558 | if (tlb_force_broadcast(env)) { |
527db2be RH |
559 | tlb_flush_page_all_cpus_synced(cs, value); |
560 | } else { | |
561 | tlb_flush_page(cs, value); | |
b4ab8ce9 | 562 | } |
fa439fc5 PM |
563 | } |
564 | ||
541ef8c2 SS |
565 | static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, |
566 | uint64_t value) | |
567 | { | |
29a0af61 | 568 | CPUState *cs = env_cpu(env); |
541ef8c2 | 569 | |
0336cbf8 | 570 | tlb_flush_by_mmuidx(cs, |
01b98b68 | 571 | ARMMMUIdxBit_E10_1 | |
452ef8cb | 572 | ARMMMUIdxBit_E10_1_PAN | |
bf05340c | 573 | ARMMMUIdxBit_E10_0); |
541ef8c2 SS |
574 | } |
575 | ||
576 | static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
577 | uint64_t value) | |
578 | { | |
29a0af61 | 579 | CPUState *cs = env_cpu(env); |
541ef8c2 | 580 | |
a67cf277 | 581 | tlb_flush_by_mmuidx_all_cpus_synced(cs, |
01b98b68 | 582 | ARMMMUIdxBit_E10_1 | |
452ef8cb | 583 | ARMMMUIdxBit_E10_1_PAN | |
bf05340c | 584 | ARMMMUIdxBit_E10_0); |
541ef8c2 SS |
585 | } |
586 | ||
541ef8c2 SS |
587 | |
588 | static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
589 | uint64_t value) | |
590 | { | |
29a0af61 | 591 | CPUState *cs = env_cpu(env); |
541ef8c2 | 592 | |
e013b741 | 593 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); |
541ef8c2 SS |
594 | } |
595 | ||
596 | static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
597 | uint64_t value) | |
598 | { | |
29a0af61 | 599 | CPUState *cs = env_cpu(env); |
541ef8c2 | 600 | |
e013b741 | 601 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); |
541ef8c2 SS |
602 | } |
603 | ||
604 | static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
605 | uint64_t value) | |
606 | { | |
29a0af61 | 607 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
608 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
609 | ||
e013b741 | 610 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); |
541ef8c2 SS |
611 | } |
612 | ||
613 | static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
614 | uint64_t value) | |
615 | { | |
29a0af61 | 616 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
617 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
618 | ||
a67cf277 | 619 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
e013b741 | 620 | ARMMMUIdxBit_E2); |
541ef8c2 SS |
621 | } |
622 | ||
e9aa6c21 | 623 | static const ARMCPRegInfo cp_reginfo[] = { |
54bf36ed FA |
624 | /* Define the secure and non-secure FCSE identifier CP registers |
625 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
626 | * the secure register to be properly reset and migrated. There is also no | |
627 | * v8 EL1 version of the register so the non-secure instance stands alone. | |
628 | */ | |
9c513e78 | 629 | { .name = "FCSEIDR", |
54bf36ed FA |
630 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
631 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, | |
632 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), | |
633 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, | |
9c513e78 | 634 | { .name = "FCSEIDR_S", |
54bf36ed FA |
635 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
636 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
637 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), | |
d4e6df63 | 638 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, |
54bf36ed FA |
639 | /* Define the secure and non-secure context identifier CP registers |
640 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
641 | * the secure register to be properly reset and migrated. In the | |
642 | * non-secure case, the 32-bit register will have reset and migration | |
643 | * disabled during registration as it is handled by the 64-bit instance. | |
644 | */ | |
645 | { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
014406b5 | 646 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
84929218 RH |
647 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
648 | .secure = ARM_CP_SECSTATE_NS, | |
54bf36ed FA |
649 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), |
650 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, | |
9c513e78 | 651 | { .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32, |
54bf36ed | 652 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
84929218 RH |
653 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
654 | .secure = ARM_CP_SECSTATE_S, | |
54bf36ed | 655 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), |
d4e6df63 | 656 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, |
9449fdf6 PM |
657 | }; |
658 | ||
659 | static const ARMCPRegInfo not_v8_cp_reginfo[] = { | |
660 | /* NB: Some of these registers exist in v8 but with more precise | |
661 | * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). | |
662 | */ | |
663 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
664 | { .name = "DACR", |
665 | .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, | |
84929218 | 666 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
0c17d68c FA |
667 | .writefn = dacr_write, .raw_writefn = raw_write, |
668 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
669 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a903c449 EI |
670 | /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. |
671 | * For v6 and v5, these mappings are overly broad. | |
4fdd17dd | 672 | */ |
a903c449 EI |
673 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0, |
674 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
675 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1, | |
676 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
677 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4, | |
678 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
679 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8, | |
4fdd17dd | 680 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, |
c4804214 PM |
681 | /* Cache maintenance ops; some of this space may be overridden later. */ |
682 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | |
683 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | |
684 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | |
e9aa6c21 PM |
685 | }; |
686 | ||
7d57f408 PM |
687 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
688 | /* Not all pre-v6 cores implemented this WFI, so this is slightly | |
689 | * over-broad. | |
690 | */ | |
691 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | |
692 | .access = PL1_W, .type = ARM_CP_WFI }, | |
7d57f408 PM |
693 | }; |
694 | ||
695 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | |
696 | /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which | |
697 | * is UNPREDICTABLE; we choose to NOP as most implementations do). | |
698 | */ | |
699 | { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
700 | .access = PL1_W, .type = ARM_CP_WFI }, | |
34f90529 PM |
701 | /* L1 cache lockdown. Not architectural in v6 and earlier but in practice |
702 | * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and | |
703 | * OMAPCP will override this space. | |
704 | */ | |
705 | { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, | |
706 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), | |
707 | .resetvalue = 0 }, | |
708 | { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, | |
709 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), | |
710 | .resetvalue = 0 }, | |
776d4e5c PM |
711 | /* v6 doesn't have the cache ID registers but Linux reads them anyway */ |
712 | { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, | |
7a0e58fa | 713 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 714 | .resetvalue = 0 }, |
50300698 PM |
715 | /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; |
716 | * implementing it as RAZ means the "debug architecture version" bits | |
717 | * will read as a reserved value, which should cause Linux to not try | |
718 | * to use the debug hardware. | |
719 | */ | |
720 | { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
721 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
995939a6 PM |
722 | /* MMU TLB control. Note that the wildcarding means we cover not just |
723 | * the unified TLB ops but also the dside/iside/inner-shareable variants. | |
724 | */ | |
725 | { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, | |
726 | .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, | |
7a0e58fa | 727 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
728 | { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, |
729 | .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, | |
7a0e58fa | 730 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
731 | { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, |
732 | .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, | |
7a0e58fa | 733 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
734 | { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, |
735 | .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, | |
7a0e58fa | 736 | .type = ARM_CP_NO_RAW }, |
a903c449 EI |
737 | { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2, |
738 | .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, | |
739 | { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, | |
740 | .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, | |
7d57f408 PM |
741 | }; |
742 | ||
c4241c7d PM |
743 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
744 | uint64_t value) | |
2771db27 | 745 | { |
f0aff255 FA |
746 | uint32_t mask = 0; |
747 | ||
748 | /* In ARMv8 most bits of CPACR_EL1 are RES0. */ | |
749 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
750 | /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. | |
751 | * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. | |
752 | * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. | |
753 | */ | |
7fbc6a40 | 754 | if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { |
f0aff255 | 755 | /* VFP coprocessor: cp10 & cp11 [23:20] */ |
fab8ad39 RH |
756 | mask |= R_CPACR_ASEDIS_MASK | |
757 | R_CPACR_D32DIS_MASK | | |
758 | R_CPACR_CP11_MASK | | |
759 | R_CPACR_CP10_MASK; | |
f0aff255 FA |
760 | |
761 | if (!arm_feature(env, ARM_FEATURE_NEON)) { | |
762 | /* ASEDIS [31] bit is RAO/WI */ | |
fab8ad39 | 763 | value |= R_CPACR_ASEDIS_MASK; |
f0aff255 FA |
764 | } |
765 | ||
766 | /* VFPv3 and upwards with NEON implement 32 double precision | |
767 | * registers (D0-D31). | |
768 | */ | |
a6627f5f | 769 | if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { |
f0aff255 | 770 | /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ |
fab8ad39 | 771 | value |= R_CPACR_D32DIS_MASK; |
f0aff255 FA |
772 | } |
773 | } | |
774 | value &= mask; | |
2771db27 | 775 | } |
fc1120a7 PM |
776 | |
777 | /* | |
778 | * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 | |
779 | * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. | |
780 | */ | |
781 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
782 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
fab8ad39 RH |
783 | mask = R_CPACR_CP11_MASK | R_CPACR_CP10_MASK; |
784 | value = (value & ~mask) | (env->cp15.cpacr_el1 & mask); | |
fc1120a7 PM |
785 | } |
786 | ||
7ebd5f2e | 787 | env->cp15.cpacr_el1 = value; |
2771db27 PM |
788 | } |
789 | ||
fc1120a7 PM |
790 | static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
791 | { | |
792 | /* | |
793 | * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 | |
794 | * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. | |
795 | */ | |
796 | uint64_t value = env->cp15.cpacr_el1; | |
797 | ||
798 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
799 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
fab8ad39 | 800 | value = ~(R_CPACR_CP11_MASK | R_CPACR_CP10_MASK); |
fc1120a7 PM |
801 | } |
802 | return value; | |
803 | } | |
804 | ||
805 | ||
5deac39c PM |
806 | static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
807 | { | |
808 | /* Call cpacr_write() so that we reset with the correct RAO bits set | |
809 | * for our CPU features. | |
810 | */ | |
811 | cpacr_write(env, ri, 0); | |
812 | } | |
813 | ||
3f208fd7 PM |
814 | static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
815 | bool isread) | |
c6f19164 GB |
816 | { |
817 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
818 | /* Check if CPACR accesses are to be trapped to EL2 */ | |
e6ef0169 | 819 | if (arm_current_el(env) == 1 && arm_is_el2_enabled(env) && |
fab8ad39 | 820 | FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TCPAC)) { |
c6f19164 GB |
821 | return CP_ACCESS_TRAP_EL2; |
822 | /* Check if CPACR accesses are to be trapped to EL3 */ | |
823 | } else if (arm_current_el(env) < 3 && | |
fab8ad39 | 824 | FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { |
c6f19164 GB |
825 | return CP_ACCESS_TRAP_EL3; |
826 | } | |
827 | } | |
828 | ||
829 | return CP_ACCESS_OK; | |
830 | } | |
831 | ||
3f208fd7 PM |
832 | static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
833 | bool isread) | |
c6f19164 GB |
834 | { |
835 | /* Check if CPTR accesses are set to trap to EL3 */ | |
fab8ad39 RH |
836 | if (arm_current_el(env) == 2 && |
837 | FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { | |
c6f19164 GB |
838 | return CP_ACCESS_TRAP_EL3; |
839 | } | |
840 | ||
841 | return CP_ACCESS_OK; | |
842 | } | |
843 | ||
7d57f408 PM |
844 | static const ARMCPRegInfo v6_cp_reginfo[] = { |
845 | /* prefetch by MVA in v6, NOP in v7 */ | |
846 | { .name = "MVA_prefetch", | |
847 | .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, | |
848 | .access = PL1_W, .type = ARM_CP_NOP }, | |
6df99dec SS |
849 | /* We need to break the TB after ISB to execute self-modifying code |
850 | * correctly and also to take any pending interrupts immediately. | |
851 | * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. | |
852 | */ | |
7d57f408 | 853 | { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, |
6df99dec | 854 | .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, |
091fd17c | 855 | { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
7d57f408 | 856 | .access = PL0_W, .type = ARM_CP_NOP }, |
091fd17c | 857 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
7d57f408 | 858 | .access = PL0_W, .type = ARM_CP_NOP }, |
06d76f31 | 859 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
84929218 | 860 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
b848ce2b FA |
861 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), |
862 | offsetof(CPUARMState, cp15.ifar_ns) }, | |
06d76f31 PM |
863 | .resetvalue = 0, }, |
864 | /* Watchpoint Fault Address Register : should actually only be present | |
865 | * for 1136, 1176, 11MPCore. | |
866 | */ | |
867 | { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
868 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, | |
34222fb8 | 869 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, |
c6f19164 | 870 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, |
7ebd5f2e | 871 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), |
fc1120a7 | 872 | .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read }, |
7d57f408 PM |
873 | }; |
874 | ||
57a4a11b AL |
875 | typedef struct pm_event { |
876 | uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ | |
877 | /* If the event is supported on this CPU (used to generate PMCEID[01]) */ | |
878 | bool (*supported)(CPUARMState *); | |
879 | /* | |
880 | * Retrieve the current count of the underlying event. The programmed | |
881 | * counters hold a difference from the return value from this function | |
882 | */ | |
883 | uint64_t (*get_count)(CPUARMState *); | |
4e7beb0c AL |
884 | /* |
885 | * Return how many nanoseconds it will take (at a minimum) for count events | |
886 | * to occur. A negative value indicates the counter will never overflow, or | |
887 | * that the counter has otherwise arranged for the overflow bit to be set | |
888 | * and the PMU interrupt to be raised on overflow. | |
889 | */ | |
890 | int64_t (*ns_per_count)(uint64_t); | |
57a4a11b AL |
891 | } pm_event; |
892 | ||
b2e23725 AL |
893 | static bool event_always_supported(CPUARMState *env) |
894 | { | |
895 | return true; | |
896 | } | |
897 | ||
0d4bfd7d AL |
898 | static uint64_t swinc_get_count(CPUARMState *env) |
899 | { | |
900 | /* | |
901 | * SW_INCR events are written directly to the pmevcntr's by writes to | |
902 | * PMSWINC, so there is no underlying count maintained by the PMU itself | |
903 | */ | |
904 | return 0; | |
905 | } | |
906 | ||
4e7beb0c AL |
907 | static int64_t swinc_ns_per(uint64_t ignored) |
908 | { | |
909 | return -1; | |
910 | } | |
911 | ||
b2e23725 AL |
912 | /* |
913 | * Return the underlying cycle count for the PMU cycle counters. If we're in | |
914 | * usermode, simply return 0. | |
915 | */ | |
916 | static uint64_t cycles_get_count(CPUARMState *env) | |
917 | { | |
918 | #ifndef CONFIG_USER_ONLY | |
919 | return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
920 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); | |
921 | #else | |
922 | return cpu_get_host_ticks(); | |
923 | #endif | |
924 | } | |
925 | ||
926 | #ifndef CONFIG_USER_ONLY | |
4e7beb0c AL |
927 | static int64_t cycles_ns_per(uint64_t cycles) |
928 | { | |
929 | return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles; | |
930 | } | |
931 | ||
b2e23725 AL |
932 | static bool instructions_supported(CPUARMState *env) |
933 | { | |
740b1759 | 934 | return icount_enabled() == 1; /* Precise instruction counting */ |
b2e23725 AL |
935 | } |
936 | ||
937 | static uint64_t instructions_get_count(CPUARMState *env) | |
938 | { | |
8191d368 | 939 | return (uint64_t)icount_get_raw(); |
b2e23725 | 940 | } |
4e7beb0c AL |
941 | |
942 | static int64_t instructions_ns_per(uint64_t icount) | |
943 | { | |
8191d368 | 944 | return icount_to_ns((int64_t)icount); |
4e7beb0c | 945 | } |
b2e23725 AL |
946 | #endif |
947 | ||
0727f63b PM |
948 | static bool pmu_8_1_events_supported(CPUARMState *env) |
949 | { | |
950 | /* For events which are supported in any v8.1 PMU */ | |
951 | return cpu_isar_feature(any_pmu_8_1, env_archcpu(env)); | |
952 | } | |
953 | ||
15dd1ebd PM |
954 | static bool pmu_8_4_events_supported(CPUARMState *env) |
955 | { | |
956 | /* For events which are supported in any v8.1 PMU */ | |
957 | return cpu_isar_feature(any_pmu_8_4, env_archcpu(env)); | |
958 | } | |
959 | ||
0727f63b PM |
960 | static uint64_t zero_event_get_count(CPUARMState *env) |
961 | { | |
962 | /* For events which on QEMU never fire, so their count is always zero */ | |
963 | return 0; | |
964 | } | |
965 | ||
966 | static int64_t zero_event_ns_per(uint64_t cycles) | |
967 | { | |
968 | /* An event which never fires can never overflow */ | |
969 | return -1; | |
970 | } | |
971 | ||
57a4a11b | 972 | static const pm_event pm_events[] = { |
0d4bfd7d AL |
973 | { .number = 0x000, /* SW_INCR */ |
974 | .supported = event_always_supported, | |
975 | .get_count = swinc_get_count, | |
4e7beb0c | 976 | .ns_per_count = swinc_ns_per, |
0d4bfd7d | 977 | }, |
b2e23725 AL |
978 | #ifndef CONFIG_USER_ONLY |
979 | { .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */ | |
980 | .supported = instructions_supported, | |
981 | .get_count = instructions_get_count, | |
4e7beb0c | 982 | .ns_per_count = instructions_ns_per, |
b2e23725 AL |
983 | }, |
984 | { .number = 0x011, /* CPU_CYCLES, Cycle */ | |
985 | .supported = event_always_supported, | |
986 | .get_count = cycles_get_count, | |
4e7beb0c | 987 | .ns_per_count = cycles_ns_per, |
0727f63b | 988 | }, |
b2e23725 | 989 | #endif |
0727f63b PM |
990 | { .number = 0x023, /* STALL_FRONTEND */ |
991 | .supported = pmu_8_1_events_supported, | |
992 | .get_count = zero_event_get_count, | |
993 | .ns_per_count = zero_event_ns_per, | |
994 | }, | |
995 | { .number = 0x024, /* STALL_BACKEND */ | |
996 | .supported = pmu_8_1_events_supported, | |
997 | .get_count = zero_event_get_count, | |
998 | .ns_per_count = zero_event_ns_per, | |
999 | }, | |
15dd1ebd PM |
1000 | { .number = 0x03c, /* STALL */ |
1001 | .supported = pmu_8_4_events_supported, | |
1002 | .get_count = zero_event_get_count, | |
1003 | .ns_per_count = zero_event_ns_per, | |
1004 | }, | |
57a4a11b AL |
1005 | }; |
1006 | ||
1007 | /* | |
1008 | * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of | |
1009 | * events (i.e. the statistical profiling extension), this implementation | |
1010 | * should first be updated to something sparse instead of the current | |
1011 | * supported_event_map[] array. | |
1012 | */ | |
15dd1ebd | 1013 | #define MAX_EVENT_ID 0x3c |
57a4a11b AL |
1014 | #define UNSUPPORTED_EVENT UINT16_MAX |
1015 | static uint16_t supported_event_map[MAX_EVENT_ID + 1]; | |
1016 | ||
1017 | /* | |
bf8d0969 AL |
1018 | * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map |
1019 | * of ARM event numbers to indices in our pm_events array. | |
57a4a11b AL |
1020 | * |
1021 | * Note: Events in the 0x40XX range are not currently supported. | |
1022 | */ | |
bf8d0969 | 1023 | void pmu_init(ARMCPU *cpu) |
57a4a11b | 1024 | { |
57a4a11b AL |
1025 | unsigned int i; |
1026 | ||
bf8d0969 AL |
1027 | /* |
1028 | * Empty supported_event_map and cpu->pmceid[01] before adding supported | |
1029 | * events to them | |
1030 | */ | |
57a4a11b AL |
1031 | for (i = 0; i < ARRAY_SIZE(supported_event_map); i++) { |
1032 | supported_event_map[i] = UNSUPPORTED_EVENT; | |
1033 | } | |
bf8d0969 AL |
1034 | cpu->pmceid0 = 0; |
1035 | cpu->pmceid1 = 0; | |
57a4a11b AL |
1036 | |
1037 | for (i = 0; i < ARRAY_SIZE(pm_events); i++) { | |
1038 | const pm_event *cnt = &pm_events[i]; | |
1039 | assert(cnt->number <= MAX_EVENT_ID); | |
1040 | /* We do not currently support events in the 0x40xx range */ | |
1041 | assert(cnt->number <= 0x3f); | |
1042 | ||
bf8d0969 | 1043 | if (cnt->supported(&cpu->env)) { |
57a4a11b | 1044 | supported_event_map[cnt->number] = i; |
67da43d6 | 1045 | uint64_t event_mask = 1ULL << (cnt->number & 0x1f); |
bf8d0969 AL |
1046 | if (cnt->number & 0x20) { |
1047 | cpu->pmceid1 |= event_mask; | |
1048 | } else { | |
1049 | cpu->pmceid0 |= event_mask; | |
1050 | } | |
57a4a11b AL |
1051 | } |
1052 | } | |
57a4a11b AL |
1053 | } |
1054 | ||
5ecdd3e4 AL |
1055 | /* |
1056 | * Check at runtime whether a PMU event is supported for the current machine | |
1057 | */ | |
1058 | static bool event_supported(uint16_t number) | |
1059 | { | |
1060 | if (number > MAX_EVENT_ID) { | |
1061 | return false; | |
1062 | } | |
1063 | return supported_event_map[number] != UNSUPPORTED_EVENT; | |
1064 | } | |
1065 | ||
3f208fd7 PM |
1066 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1067 | bool isread) | |
200ac0ef | 1068 | { |
3b163b01 | 1069 | /* Performance monitor registers user accessibility is controlled |
1fce1ba9 PM |
1070 | * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable |
1071 | * trapping to EL2 or EL3 for other accesses. | |
200ac0ef | 1072 | */ |
1fce1ba9 | 1073 | int el = arm_current_el(env); |
59dd089c | 1074 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
1fce1ba9 | 1075 | |
6ecd0b6b | 1076 | if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { |
fcd25206 | 1077 | return CP_ACCESS_TRAP; |
200ac0ef | 1078 | } |
59dd089c | 1079 | if (el < 2 && (mdcr_el2 & MDCR_TPM)) { |
1fce1ba9 PM |
1080 | return CP_ACCESS_TRAP_EL2; |
1081 | } | |
1082 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
1083 | return CP_ACCESS_TRAP_EL3; | |
1084 | } | |
1085 | ||
fcd25206 | 1086 | return CP_ACCESS_OK; |
200ac0ef PM |
1087 | } |
1088 | ||
6ecd0b6b AB |
1089 | static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, |
1090 | const ARMCPRegInfo *ri, | |
1091 | bool isread) | |
1092 | { | |
1093 | /* ER: event counter read trap control */ | |
1094 | if (arm_feature(env, ARM_FEATURE_V8) | |
1095 | && arm_current_el(env) == 0 | |
1096 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 | |
1097 | && isread) { | |
1098 | return CP_ACCESS_OK; | |
1099 | } | |
1100 | ||
1101 | return pmreg_access(env, ri, isread); | |
1102 | } | |
1103 | ||
1104 | static CPAccessResult pmreg_access_swinc(CPUARMState *env, | |
1105 | const ARMCPRegInfo *ri, | |
1106 | bool isread) | |
1107 | { | |
1108 | /* SW: software increment write trap control */ | |
1109 | if (arm_feature(env, ARM_FEATURE_V8) | |
1110 | && arm_current_el(env) == 0 | |
1111 | && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 | |
1112 | && !isread) { | |
1113 | return CP_ACCESS_OK; | |
1114 | } | |
1115 | ||
1116 | return pmreg_access(env, ri, isread); | |
1117 | } | |
1118 | ||
6ecd0b6b AB |
1119 | static CPAccessResult pmreg_access_selr(CPUARMState *env, |
1120 | const ARMCPRegInfo *ri, | |
1121 | bool isread) | |
1122 | { | |
1123 | /* ER: event counter read trap control */ | |
1124 | if (arm_feature(env, ARM_FEATURE_V8) | |
1125 | && arm_current_el(env) == 0 | |
1126 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { | |
1127 | return CP_ACCESS_OK; | |
1128 | } | |
1129 | ||
1130 | return pmreg_access(env, ri, isread); | |
1131 | } | |
1132 | ||
1133 | static CPAccessResult pmreg_access_ccntr(CPUARMState *env, | |
1134 | const ARMCPRegInfo *ri, | |
1135 | bool isread) | |
1136 | { | |
1137 | /* CR: cycle counter read trap control */ | |
1138 | if (arm_feature(env, ARM_FEATURE_V8) | |
1139 | && arm_current_el(env) == 0 | |
1140 | && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 | |
1141 | && isread) { | |
1142 | return CP_ACCESS_OK; | |
1143 | } | |
1144 | ||
1145 | return pmreg_access(env, ri, isread); | |
1146 | } | |
1147 | ||
033614c4 AL |
1148 | /* Returns true if the counter (pass 31 for PMCCNTR) should count events using |
1149 | * the current EL, security state, and register configuration. | |
1150 | */ | |
1151 | static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) | |
87124fde | 1152 | { |
033614c4 AL |
1153 | uint64_t filter; |
1154 | bool e, p, u, nsk, nsu, nsh, m; | |
1155 | bool enabled, prohibited, filtered; | |
1156 | bool secure = arm_is_secure(env); | |
1157 | int el = arm_current_el(env); | |
59dd089c RDC |
1158 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
1159 | uint8_t hpmn = mdcr_el2 & MDCR_HPMN; | |
87124fde | 1160 | |
cbbb3041 AJ |
1161 | if (!arm_feature(env, ARM_FEATURE_PMU)) { |
1162 | return false; | |
1163 | } | |
1164 | ||
033614c4 AL |
1165 | if (!arm_feature(env, ARM_FEATURE_EL2) || |
1166 | (counter < hpmn || counter == 31)) { | |
1167 | e = env->cp15.c9_pmcr & PMCRE; | |
1168 | } else { | |
59dd089c | 1169 | e = mdcr_el2 & MDCR_HPME; |
87124fde | 1170 | } |
033614c4 | 1171 | enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); |
87124fde | 1172 | |
033614c4 AL |
1173 | if (!secure) { |
1174 | if (el == 2 && (counter < hpmn || counter == 31)) { | |
59dd089c | 1175 | prohibited = mdcr_el2 & MDCR_HPMD; |
033614c4 AL |
1176 | } else { |
1177 | prohibited = false; | |
1178 | } | |
1179 | } else { | |
1180 | prohibited = arm_feature(env, ARM_FEATURE_EL3) && | |
db1f3afb | 1181 | !(env->cp15.mdcr_el3 & MDCR_SPME); |
033614c4 AL |
1182 | } |
1183 | ||
1184 | if (prohibited && counter == 31) { | |
1185 | prohibited = env->cp15.c9_pmcr & PMCRDP; | |
1186 | } | |
1187 | ||
5ecdd3e4 AL |
1188 | if (counter == 31) { |
1189 | filter = env->cp15.pmccfiltr_el0; | |
1190 | } else { | |
1191 | filter = env->cp15.c14_pmevtyper[counter]; | |
1192 | } | |
033614c4 AL |
1193 | |
1194 | p = filter & PMXEVTYPER_P; | |
1195 | u = filter & PMXEVTYPER_U; | |
1196 | nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); | |
1197 | nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); | |
1198 | nsh = arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); | |
1199 | m = arm_el_is_aa64(env, 1) && | |
1200 | arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); | |
1201 | ||
1202 | if (el == 0) { | |
1203 | filtered = secure ? u : u != nsu; | |
1204 | } else if (el == 1) { | |
1205 | filtered = secure ? p : p != nsk; | |
1206 | } else if (el == 2) { | |
1207 | filtered = !nsh; | |
1208 | } else { /* EL3 */ | |
1209 | filtered = m != p; | |
1210 | } | |
1211 | ||
5ecdd3e4 AL |
1212 | if (counter != 31) { |
1213 | /* | |
1214 | * If not checking PMCCNTR, ensure the counter is setup to an event we | |
1215 | * support | |
1216 | */ | |
1217 | uint16_t event = filter & PMXEVTYPER_EVTCOUNT; | |
1218 | if (!event_supported(event)) { | |
1219 | return false; | |
1220 | } | |
1221 | } | |
1222 | ||
033614c4 | 1223 | return enabled && !prohibited && !filtered; |
87124fde | 1224 | } |
033614c4 | 1225 | |
f4efb4b2 AL |
1226 | static void pmu_update_irq(CPUARMState *env) |
1227 | { | |
2fc0cc0e | 1228 | ARMCPU *cpu = env_archcpu(env); |
f4efb4b2 AL |
1229 | qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && |
1230 | (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); | |
1231 | } | |
1232 | ||
5d05b9d4 AL |
1233 | /* |
1234 | * Ensure c15_ccnt is the guest-visible count so that operations such as | |
1235 | * enabling/disabling the counter or filtering, modifying the count itself, | |
1236 | * etc. can be done logically. This is essentially a no-op if the counter is | |
1237 | * not enabled at the time of the call. | |
1238 | */ | |
f2b2f53f | 1239 | static void pmccntr_op_start(CPUARMState *env) |
ec7b4ce4 | 1240 | { |
b2e23725 | 1241 | uint64_t cycles = cycles_get_count(env); |
ec7b4ce4 | 1242 | |
033614c4 | 1243 | if (pmu_counter_enabled(env, 31)) { |
5d05b9d4 AL |
1244 | uint64_t eff_cycles = cycles; |
1245 | if (env->cp15.c9_pmcr & PMCRD) { | |
1246 | /* Increment once every 64 processor clock cycles */ | |
1247 | eff_cycles /= 64; | |
1248 | } | |
1249 | ||
f4efb4b2 AL |
1250 | uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta; |
1251 | ||
1252 | uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \ | |
1253 | 1ull << 63 : 1ull << 31; | |
1254 | if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { | |
1255 | env->cp15.c9_pmovsr |= (1 << 31); | |
1256 | pmu_update_irq(env); | |
1257 | } | |
1258 | ||
1259 | env->cp15.c15_ccnt = new_pmccntr; | |
ec7b4ce4 | 1260 | } |
5d05b9d4 AL |
1261 | env->cp15.c15_ccnt_delta = cycles; |
1262 | } | |
ec7b4ce4 | 1263 | |
5d05b9d4 AL |
1264 | /* |
1265 | * If PMCCNTR is enabled, recalculate the delta between the clock and the | |
1266 | * guest-visible count. A call to pmccntr_op_finish should follow every call to | |
1267 | * pmccntr_op_start. | |
1268 | */ | |
f2b2f53f | 1269 | static void pmccntr_op_finish(CPUARMState *env) |
5d05b9d4 | 1270 | { |
033614c4 | 1271 | if (pmu_counter_enabled(env, 31)) { |
4e7beb0c AL |
1272 | #ifndef CONFIG_USER_ONLY |
1273 | /* Calculate when the counter will next overflow */ | |
1274 | uint64_t remaining_cycles = -env->cp15.c15_ccnt; | |
1275 | if (!(env->cp15.c9_pmcr & PMCRLC)) { | |
1276 | remaining_cycles = (uint32_t)remaining_cycles; | |
1277 | } | |
1278 | int64_t overflow_in = cycles_ns_per(remaining_cycles); | |
1279 | ||
1280 | if (overflow_in > 0) { | |
1281 | int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
1282 | overflow_in; | |
2fc0cc0e | 1283 | ARMCPU *cpu = env_archcpu(env); |
4e7beb0c AL |
1284 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); |
1285 | } | |
1286 | #endif | |
5d05b9d4 | 1287 | |
4e7beb0c | 1288 | uint64_t prev_cycles = env->cp15.c15_ccnt_delta; |
5d05b9d4 AL |
1289 | if (env->cp15.c9_pmcr & PMCRD) { |
1290 | /* Increment once every 64 processor clock cycles */ | |
1291 | prev_cycles /= 64; | |
1292 | } | |
5d05b9d4 | 1293 | env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt; |
ec7b4ce4 AF |
1294 | } |
1295 | } | |
1296 | ||
5ecdd3e4 AL |
1297 | static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) |
1298 | { | |
1299 | ||
1300 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; | |
1301 | uint64_t count = 0; | |
1302 | if (event_supported(event)) { | |
1303 | uint16_t event_idx = supported_event_map[event]; | |
1304 | count = pm_events[event_idx].get_count(env); | |
1305 | } | |
1306 | ||
1307 | if (pmu_counter_enabled(env, counter)) { | |
f4efb4b2 AL |
1308 | uint32_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter]; |
1309 | ||
1310 | if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & INT32_MIN) { | |
1311 | env->cp15.c9_pmovsr |= (1 << counter); | |
1312 | pmu_update_irq(env); | |
1313 | } | |
1314 | env->cp15.c14_pmevcntr[counter] = new_pmevcntr; | |
5ecdd3e4 AL |
1315 | } |
1316 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1317 | } | |
1318 | ||
1319 | static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) | |
1320 | { | |
1321 | if (pmu_counter_enabled(env, counter)) { | |
4e7beb0c AL |
1322 | #ifndef CONFIG_USER_ONLY |
1323 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; | |
1324 | uint16_t event_idx = supported_event_map[event]; | |
1325 | uint64_t delta = UINT32_MAX - | |
1326 | (uint32_t)env->cp15.c14_pmevcntr[counter] + 1; | |
1327 | int64_t overflow_in = pm_events[event_idx].ns_per_count(delta); | |
1328 | ||
1329 | if (overflow_in > 0) { | |
1330 | int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
1331 | overflow_in; | |
2fc0cc0e | 1332 | ARMCPU *cpu = env_archcpu(env); |
4e7beb0c AL |
1333 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); |
1334 | } | |
1335 | #endif | |
1336 | ||
5ecdd3e4 AL |
1337 | env->cp15.c14_pmevcntr_delta[counter] -= |
1338 | env->cp15.c14_pmevcntr[counter]; | |
1339 | } | |
1340 | } | |
1341 | ||
5d05b9d4 AL |
1342 | void pmu_op_start(CPUARMState *env) |
1343 | { | |
5ecdd3e4 | 1344 | unsigned int i; |
5d05b9d4 | 1345 | pmccntr_op_start(env); |
5ecdd3e4 AL |
1346 | for (i = 0; i < pmu_num_counters(env); i++) { |
1347 | pmevcntr_op_start(env, i); | |
1348 | } | |
5d05b9d4 AL |
1349 | } |
1350 | ||
1351 | void pmu_op_finish(CPUARMState *env) | |
1352 | { | |
5ecdd3e4 | 1353 | unsigned int i; |
5d05b9d4 | 1354 | pmccntr_op_finish(env); |
5ecdd3e4 AL |
1355 | for (i = 0; i < pmu_num_counters(env); i++) { |
1356 | pmevcntr_op_finish(env, i); | |
1357 | } | |
5d05b9d4 AL |
1358 | } |
1359 | ||
033614c4 AL |
1360 | void pmu_pre_el_change(ARMCPU *cpu, void *ignored) |
1361 | { | |
1362 | pmu_op_start(&cpu->env); | |
1363 | } | |
1364 | ||
1365 | void pmu_post_el_change(ARMCPU *cpu, void *ignored) | |
1366 | { | |
1367 | pmu_op_finish(&cpu->env); | |
1368 | } | |
1369 | ||
4e7beb0c AL |
1370 | void arm_pmu_timer_cb(void *opaque) |
1371 | { | |
1372 | ARMCPU *cpu = opaque; | |
1373 | ||
1374 | /* | |
1375 | * Update all the counter values based on the current underlying counts, | |
1376 | * triggering interrupts to be raised, if necessary. pmu_op_finish() also | |
1377 | * has the effect of setting the cpu->pmu_timer to the next earliest time a | |
1378 | * counter may expire. | |
1379 | */ | |
1380 | pmu_op_start(&cpu->env); | |
1381 | pmu_op_finish(&cpu->env); | |
1382 | } | |
1383 | ||
c4241c7d PM |
1384 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1385 | uint64_t value) | |
200ac0ef | 1386 | { |
5d05b9d4 | 1387 | pmu_op_start(env); |
7c2cb42b AF |
1388 | |
1389 | if (value & PMCRC) { | |
1390 | /* The counter has been reset */ | |
1391 | env->cp15.c15_ccnt = 0; | |
1392 | } | |
1393 | ||
5ecdd3e4 AL |
1394 | if (value & PMCRP) { |
1395 | unsigned int i; | |
1396 | for (i = 0; i < pmu_num_counters(env); i++) { | |
1397 | env->cp15.c14_pmevcntr[i] = 0; | |
1398 | } | |
1399 | } | |
1400 | ||
9323e79f PM |
1401 | env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; |
1402 | env->cp15.c9_pmcr |= (value & PMCR_WRITABLE_MASK); | |
7c2cb42b | 1403 | |
5d05b9d4 | 1404 | pmu_op_finish(env); |
7c2cb42b AF |
1405 | } |
1406 | ||
0d4bfd7d AL |
1407 | static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1408 | uint64_t value) | |
1409 | { | |
1410 | unsigned int i; | |
1411 | for (i = 0; i < pmu_num_counters(env); i++) { | |
1412 | /* Increment a counter's count iff: */ | |
1413 | if ((value & (1 << i)) && /* counter's bit is set */ | |
1414 | /* counter is enabled and not filtered */ | |
1415 | pmu_counter_enabled(env, i) && | |
1416 | /* counter is SW_INCR */ | |
1417 | (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { | |
1418 | pmevcntr_op_start(env, i); | |
f4efb4b2 AL |
1419 | |
1420 | /* | |
1421 | * Detect if this write causes an overflow since we can't predict | |
1422 | * PMSWINC overflows like we can for other events | |
1423 | */ | |
1424 | uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; | |
1425 | ||
1426 | if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { | |
1427 | env->cp15.c9_pmovsr |= (1 << i); | |
1428 | pmu_update_irq(env); | |
1429 | } | |
1430 | ||
1431 | env->cp15.c14_pmevcntr[i] = new_pmswinc; | |
1432 | ||
0d4bfd7d AL |
1433 | pmevcntr_op_finish(env, i); |
1434 | } | |
1435 | } | |
1436 | } | |
1437 | ||
7c2cb42b AF |
1438 | static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1439 | { | |
5d05b9d4 AL |
1440 | uint64_t ret; |
1441 | pmccntr_op_start(env); | |
1442 | ret = env->cp15.c15_ccnt; | |
1443 | pmccntr_op_finish(env); | |
1444 | return ret; | |
7c2cb42b AF |
1445 | } |
1446 | ||
6b040780 WH |
1447 | static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1448 | uint64_t value) | |
1449 | { | |
1450 | /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and | |
1451 | * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the | |
1452 | * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are | |
1453 | * accessed. | |
1454 | */ | |
1455 | env->cp15.c9_pmselr = value & 0x1f; | |
1456 | } | |
1457 | ||
7c2cb42b AF |
1458 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1459 | uint64_t value) | |
1460 | { | |
5d05b9d4 AL |
1461 | pmccntr_op_start(env); |
1462 | env->cp15.c15_ccnt = value; | |
1463 | pmccntr_op_finish(env); | |
200ac0ef | 1464 | } |
421c7ebd PC |
1465 | |
1466 | static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1467 | uint64_t value) | |
1468 | { | |
1469 | uint64_t cur_val = pmccntr_read(env, NULL); | |
1470 | ||
1471 | pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); | |
1472 | } | |
1473 | ||
0614601c AF |
1474 | static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1475 | uint64_t value) | |
1476 | { | |
5d05b9d4 | 1477 | pmccntr_op_start(env); |
4b8afa1f AL |
1478 | env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0; |
1479 | pmccntr_op_finish(env); | |
1480 | } | |
1481 | ||
1482 | static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1483 | uint64_t value) | |
1484 | { | |
1485 | pmccntr_op_start(env); | |
1486 | /* M is not accessible from AArch32 */ | |
1487 | env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | | |
1488 | (value & PMCCFILTR); | |
5d05b9d4 | 1489 | pmccntr_op_finish(env); |
0614601c AF |
1490 | } |
1491 | ||
4b8afa1f AL |
1492 | static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri) |
1493 | { | |
1494 | /* M is not visible in AArch32 */ | |
1495 | return env->cp15.pmccfiltr_el0 & PMCCFILTR; | |
1496 | } | |
1497 | ||
c4241c7d | 1498 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1499 | uint64_t value) |
1500 | { | |
7ece99b1 | 1501 | value &= pmu_counter_mask(env); |
200ac0ef | 1502 | env->cp15.c9_pmcnten |= value; |
200ac0ef PM |
1503 | } |
1504 | ||
c4241c7d PM |
1505 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1506 | uint64_t value) | |
200ac0ef | 1507 | { |
7ece99b1 | 1508 | value &= pmu_counter_mask(env); |
200ac0ef | 1509 | env->cp15.c9_pmcnten &= ~value; |
200ac0ef PM |
1510 | } |
1511 | ||
c4241c7d PM |
1512 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1513 | uint64_t value) | |
200ac0ef | 1514 | { |
599b71e2 | 1515 | value &= pmu_counter_mask(env); |
200ac0ef | 1516 | env->cp15.c9_pmovsr &= ~value; |
f4efb4b2 | 1517 | pmu_update_irq(env); |
200ac0ef PM |
1518 | } |
1519 | ||
327dd510 AL |
1520 | static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1521 | uint64_t value) | |
1522 | { | |
1523 | value &= pmu_counter_mask(env); | |
1524 | env->cp15.c9_pmovsr |= value; | |
f4efb4b2 | 1525 | pmu_update_irq(env); |
327dd510 AL |
1526 | } |
1527 | ||
5ecdd3e4 AL |
1528 | static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1529 | uint64_t value, const uint8_t counter) | |
200ac0ef | 1530 | { |
5ecdd3e4 AL |
1531 | if (counter == 31) { |
1532 | pmccfiltr_write(env, ri, value); | |
1533 | } else if (counter < pmu_num_counters(env)) { | |
1534 | pmevcntr_op_start(env, counter); | |
1535 | ||
1536 | /* | |
1537 | * If this counter's event type is changing, store the current | |
1538 | * underlying count for the new type in c14_pmevcntr_delta[counter] so | |
1539 | * pmevcntr_op_finish has the correct baseline when it converts back to | |
1540 | * a delta. | |
1541 | */ | |
1542 | uint16_t old_event = env->cp15.c14_pmevtyper[counter] & | |
1543 | PMXEVTYPER_EVTCOUNT; | |
1544 | uint16_t new_event = value & PMXEVTYPER_EVTCOUNT; | |
1545 | if (old_event != new_event) { | |
1546 | uint64_t count = 0; | |
1547 | if (event_supported(new_event)) { | |
1548 | uint16_t event_idx = supported_event_map[new_event]; | |
1549 | count = pm_events[event_idx].get_count(env); | |
1550 | } | |
1551 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1552 | } | |
1553 | ||
1554 | env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK; | |
1555 | pmevcntr_op_finish(env, counter); | |
1556 | } | |
fdb86656 WH |
1557 | /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when |
1558 | * PMSELR value is equal to or greater than the number of implemented | |
1559 | * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. | |
1560 | */ | |
5ecdd3e4 AL |
1561 | } |
1562 | ||
1563 | static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1564 | const uint8_t counter) | |
1565 | { | |
1566 | if (counter == 31) { | |
1567 | return env->cp15.pmccfiltr_el0; | |
1568 | } else if (counter < pmu_num_counters(env)) { | |
1569 | return env->cp15.c14_pmevtyper[counter]; | |
1570 | } else { | |
1571 | /* | |
1572 | * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER | |
1573 | * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). | |
1574 | */ | |
1575 | return 0; | |
1576 | } | |
1577 | } | |
1578 | ||
1579 | static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, | |
1580 | uint64_t value) | |
1581 | { | |
1582 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1583 | pmevtyper_write(env, ri, value, counter); | |
1584 | } | |
1585 | ||
1586 | static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1587 | uint64_t value) | |
1588 | { | |
1589 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1590 | env->cp15.c14_pmevtyper[counter] = value; | |
1591 | ||
1592 | /* | |
1593 | * pmevtyper_rawwrite is called between a pair of pmu_op_start and | |
1594 | * pmu_op_finish calls when loading saved state for a migration. Because | |
1595 | * we're potentially updating the type of event here, the value written to | |
1596 | * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a | |
1597 | * different counter type. Therefore, we need to set this value to the | |
1598 | * current count for the counter type we're writing so that pmu_op_finish | |
1599 | * has the correct count for its calculation. | |
1600 | */ | |
1601 | uint16_t event = value & PMXEVTYPER_EVTCOUNT; | |
1602 | if (event_supported(event)) { | |
1603 | uint16_t event_idx = supported_event_map[event]; | |
1604 | env->cp15.c14_pmevcntr_delta[counter] = | |
1605 | pm_events[event_idx].get_count(env); | |
fdb86656 WH |
1606 | } |
1607 | } | |
1608 | ||
5ecdd3e4 AL |
1609 | static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) |
1610 | { | |
1611 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1612 | return pmevtyper_read(env, ri, counter); | |
1613 | } | |
1614 | ||
1615 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1616 | uint64_t value) | |
1617 | { | |
1618 | pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1619 | } | |
1620 | ||
fdb86656 WH |
1621 | static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1622 | { | |
5ecdd3e4 AL |
1623 | return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); |
1624 | } | |
1625 | ||
1626 | static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1627 | uint64_t value, uint8_t counter) | |
1628 | { | |
1629 | if (counter < pmu_num_counters(env)) { | |
1630 | pmevcntr_op_start(env, counter); | |
1631 | env->cp15.c14_pmevcntr[counter] = value; | |
1632 | pmevcntr_op_finish(env, counter); | |
1633 | } | |
1634 | /* | |
1635 | * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR | |
1636 | * are CONSTRAINED UNPREDICTABLE. | |
fdb86656 | 1637 | */ |
5ecdd3e4 AL |
1638 | } |
1639 | ||
1640 | static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1641 | uint8_t counter) | |
1642 | { | |
1643 | if (counter < pmu_num_counters(env)) { | |
1644 | uint64_t ret; | |
1645 | pmevcntr_op_start(env, counter); | |
1646 | ret = env->cp15.c14_pmevcntr[counter]; | |
1647 | pmevcntr_op_finish(env, counter); | |
1648 | return ret; | |
fdb86656 | 1649 | } else { |
5ecdd3e4 AL |
1650 | /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR |
1651 | * are CONSTRAINED UNPREDICTABLE. */ | |
fdb86656 WH |
1652 | return 0; |
1653 | } | |
200ac0ef PM |
1654 | } |
1655 | ||
5ecdd3e4 AL |
1656 | static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, |
1657 | uint64_t value) | |
1658 | { | |
1659 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1660 | pmevcntr_write(env, ri, value, counter); | |
1661 | } | |
1662 | ||
1663 | static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) | |
1664 | { | |
1665 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1666 | return pmevcntr_read(env, ri, counter); | |
1667 | } | |
1668 | ||
1669 | static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1670 | uint64_t value) | |
1671 | { | |
1672 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1673 | assert(counter < pmu_num_counters(env)); | |
1674 | env->cp15.c14_pmevcntr[counter] = value; | |
1675 | pmevcntr_write(env, ri, value, counter); | |
1676 | } | |
1677 | ||
1678 | static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri) | |
1679 | { | |
1680 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1681 | assert(counter < pmu_num_counters(env)); | |
1682 | return env->cp15.c14_pmevcntr[counter]; | |
1683 | } | |
1684 | ||
1685 | static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1686 | uint64_t value) | |
1687 | { | |
1688 | pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1689 | } | |
1690 | ||
1691 | static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1692 | { | |
1693 | return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); | |
1694 | } | |
1695 | ||
c4241c7d | 1696 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1697 | uint64_t value) |
1698 | { | |
6ecd0b6b AB |
1699 | if (arm_feature(env, ARM_FEATURE_V8)) { |
1700 | env->cp15.c9_pmuserenr = value & 0xf; | |
1701 | } else { | |
1702 | env->cp15.c9_pmuserenr = value & 1; | |
1703 | } | |
200ac0ef PM |
1704 | } |
1705 | ||
c4241c7d PM |
1706 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1707 | uint64_t value) | |
200ac0ef PM |
1708 | { |
1709 | /* We have no event counters so only the C bit can be changed */ | |
7ece99b1 | 1710 | value &= pmu_counter_mask(env); |
200ac0ef | 1711 | env->cp15.c9_pminten |= value; |
f4efb4b2 | 1712 | pmu_update_irq(env); |
200ac0ef PM |
1713 | } |
1714 | ||
c4241c7d PM |
1715 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1716 | uint64_t value) | |
200ac0ef | 1717 | { |
7ece99b1 | 1718 | value &= pmu_counter_mask(env); |
200ac0ef | 1719 | env->cp15.c9_pminten &= ~value; |
f4efb4b2 | 1720 | pmu_update_irq(env); |
200ac0ef PM |
1721 | } |
1722 | ||
c4241c7d PM |
1723 | static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1724 | uint64_t value) | |
8641136c | 1725 | { |
a505d7fe PM |
1726 | /* Note that even though the AArch64 view of this register has bits |
1727 | * [10:0] all RES0 we can only mask the bottom 5, to comply with the | |
1728 | * architectural requirements for bits which are RES0 only in some | |
1729 | * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 | |
1730 | * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) | |
1731 | */ | |
855ea66d | 1732 | raw_write(env, ri, value & ~0x1FULL); |
8641136c NR |
1733 | } |
1734 | ||
64e0e2de EI |
1735 | static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
1736 | { | |
ea22747c RH |
1737 | /* Begin with base v8.0 state. */ |
1738 | uint32_t valid_mask = 0x3fff; | |
2fc0cc0e | 1739 | ARMCPU *cpu = env_archcpu(env); |
ea22747c | 1740 | |
252e8c69 | 1741 | if (ri->state == ARM_CP_STATE_AA64) { |
10d0ef3e MN |
1742 | if (arm_feature(env, ARM_FEATURE_AARCH64) && |
1743 | !cpu_isar_feature(aa64_aa32_el1, cpu)) { | |
1744 | value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ | |
1745 | } | |
ea22747c | 1746 | valid_mask &= ~SCR_NET; |
252e8c69 | 1747 | |
da3d8b13 RH |
1748 | if (cpu_isar_feature(aa64_ras, cpu)) { |
1749 | valid_mask |= SCR_TERR; | |
1750 | } | |
252e8c69 RH |
1751 | if (cpu_isar_feature(aa64_lor, cpu)) { |
1752 | valid_mask |= SCR_TLOR; | |
1753 | } | |
1754 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
1755 | valid_mask |= SCR_API | SCR_APK; | |
1756 | } | |
926c1b97 RDC |
1757 | if (cpu_isar_feature(aa64_sel2, cpu)) { |
1758 | valid_mask |= SCR_EEL2; | |
1759 | } | |
8ddb300b RH |
1760 | if (cpu_isar_feature(aa64_mte, cpu)) { |
1761 | valid_mask |= SCR_ATA; | |
1762 | } | |
7cb1e618 RH |
1763 | if (cpu_isar_feature(aa64_scxtnum, cpu)) { |
1764 | valid_mask |= SCR_ENSCXT; | |
1765 | } | |
7ac61020 PM |
1766 | if (cpu_isar_feature(aa64_doublefault, cpu)) { |
1767 | valid_mask |= SCR_EASE | SCR_NMEA; | |
1768 | } | |
ea22747c RH |
1769 | } else { |
1770 | valid_mask &= ~(SCR_RW | SCR_ST); | |
da3d8b13 RH |
1771 | if (cpu_isar_feature(aa32_ras, cpu)) { |
1772 | valid_mask |= SCR_TERR; | |
1773 | } | |
ea22747c | 1774 | } |
64e0e2de EI |
1775 | |
1776 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | |
1777 | valid_mask &= ~SCR_HCE; | |
1778 | ||
1779 | /* On ARMv7, SMD (or SCD as it is called in v7) is only | |
1780 | * supported if EL2 exists. The bit is UNK/SBZP when | |
1781 | * EL2 is unavailable. In QEMU ARMv7, we force it to always zero | |
1782 | * when EL2 is unavailable. | |
4eb27640 | 1783 | * On ARMv8, this bit is always available. |
64e0e2de | 1784 | */ |
4eb27640 GB |
1785 | if (arm_feature(env, ARM_FEATURE_V7) && |
1786 | !arm_feature(env, ARM_FEATURE_V8)) { | |
64e0e2de EI |
1787 | valid_mask &= ~SCR_SMD; |
1788 | } | |
1789 | } | |
1790 | ||
1791 | /* Clear all-context RES0 bits. */ | |
1792 | value &= valid_mask; | |
1793 | raw_write(env, ri, value); | |
1794 | } | |
1795 | ||
10d0ef3e MN |
1796 | static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1797 | { | |
1798 | /* | |
1799 | * scr_write will set the RES1 bits on an AArch64-only CPU. | |
1800 | * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise. | |
1801 | */ | |
1802 | scr_write(env, ri, 0); | |
1803 | } | |
1804 | ||
630fcd4d MZ |
1805 | static CPAccessResult access_aa64_tid2(CPUARMState *env, |
1806 | const ARMCPRegInfo *ri, | |
1807 | bool isread) | |
1808 | { | |
1809 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) { | |
1810 | return CP_ACCESS_TRAP_EL2; | |
1811 | } | |
1812 | ||
1813 | return CP_ACCESS_OK; | |
1814 | } | |
1815 | ||
c4241c7d | 1816 | static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
776d4e5c | 1817 | { |
2fc0cc0e | 1818 | ARMCPU *cpu = env_archcpu(env); |
b85a1fd6 FA |
1819 | |
1820 | /* Acquire the CSSELR index from the bank corresponding to the CCSIDR | |
1821 | * bank | |
1822 | */ | |
1823 | uint32_t index = A32_BANKED_REG_GET(env, csselr, | |
1824 | ri->secure & ARM_CP_SECSTATE_S); | |
1825 | ||
1826 | return cpu->ccsidr[index]; | |
776d4e5c PM |
1827 | } |
1828 | ||
c4241c7d PM |
1829 | static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1830 | uint64_t value) | |
776d4e5c | 1831 | { |
8d5c773e | 1832 | raw_write(env, ri, value & 0xf); |
776d4e5c PM |
1833 | } |
1834 | ||
1090b9c6 PM |
1835 | static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1836 | { | |
29a0af61 | 1837 | CPUState *cs = env_cpu(env); |
cc974d5c RDC |
1838 | bool el1 = arm_current_el(env) == 1; |
1839 | uint64_t hcr_el2 = el1 ? arm_hcr_el2_eff(env) : 0; | |
1090b9c6 PM |
1840 | uint64_t ret = 0; |
1841 | ||
cc974d5c | 1842 | if (hcr_el2 & HCR_IMO) { |
636540e9 PM |
1843 | if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { |
1844 | ret |= CPSR_I; | |
1845 | } | |
1846 | } else { | |
1847 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { | |
1848 | ret |= CPSR_I; | |
1849 | } | |
1090b9c6 | 1850 | } |
636540e9 | 1851 | |
cc974d5c | 1852 | if (hcr_el2 & HCR_FMO) { |
636540e9 PM |
1853 | if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { |
1854 | ret |= CPSR_F; | |
1855 | } | |
1856 | } else { | |
1857 | if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { | |
1858 | ret |= CPSR_F; | |
1859 | } | |
1090b9c6 | 1860 | } |
636540e9 | 1861 | |
3c29632f RH |
1862 | if (hcr_el2 & HCR_AMO) { |
1863 | if (cs->interrupt_request & CPU_INTERRUPT_VSERR) { | |
1864 | ret |= CPSR_A; | |
1865 | } | |
1866 | } | |
1867 | ||
1090b9c6 PM |
1868 | return ret; |
1869 | } | |
1870 | ||
93fbc983 MZ |
1871 | static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInfo *ri, |
1872 | bool isread) | |
1873 | { | |
1874 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID1)) { | |
1875 | return CP_ACCESS_TRAP_EL2; | |
1876 | } | |
1877 | ||
1878 | return CP_ACCESS_OK; | |
1879 | } | |
1880 | ||
1881 | static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInfo *ri, | |
1882 | bool isread) | |
1883 | { | |
1884 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
1885 | return access_aa64_tid1(env, ri, isread); | |
1886 | } | |
1887 | ||
1888 | return CP_ACCESS_OK; | |
1889 | } | |
1890 | ||
e9aa6c21 | 1891 | static const ARMCPRegInfo v7_cp_reginfo[] = { |
7d57f408 PM |
1892 | /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ |
1893 | { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
1894 | .access = PL1_W, .type = ARM_CP_NOP }, | |
200ac0ef PM |
1895 | /* Performance monitors are implementation defined in v7, |
1896 | * but with an ARM recommended set of registers, which we | |
ac689a2e | 1897 | * follow. |
200ac0ef PM |
1898 | * |
1899 | * Performance registers fall into three categories: | |
1900 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) | |
1901 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) | |
1902 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) | |
1903 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW | |
1904 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. | |
1905 | */ | |
1906 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 1907 | .access = PL0_RW, .type = ARM_CP_ALIAS, |
8521466b | 1908 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), |
fcd25206 PM |
1909 | .writefn = pmcntenset_write, |
1910 | .accessfn = pmreg_access, | |
1911 | .raw_writefn = raw_write }, | |
8521466b AF |
1912 | { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, |
1913 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, | |
1914 | .access = PL0_RW, .accessfn = pmreg_access, | |
1915 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, | |
1916 | .writefn = pmcntenset_write, .raw_writefn = raw_write }, | |
200ac0ef | 1917 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
8521466b AF |
1918 | .access = PL0_RW, |
1919 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
1920 | .accessfn = pmreg_access, |
1921 | .writefn = pmcntenclr_write, | |
7a0e58fa | 1922 | .type = ARM_CP_ALIAS }, |
8521466b AF |
1923 | { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, |
1924 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, | |
1925 | .access = PL0_RW, .accessfn = pmreg_access, | |
7a0e58fa | 1926 | .type = ARM_CP_ALIAS, |
8521466b AF |
1927 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), |
1928 | .writefn = pmcntenclr_write }, | |
200ac0ef | 1929 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
f4efb4b2 | 1930 | .access = PL0_RW, .type = ARM_CP_IO, |
e4e91a21 | 1931 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
fcd25206 PM |
1932 | .accessfn = pmreg_access, |
1933 | .writefn = pmovsr_write, | |
1934 | .raw_writefn = raw_write }, | |
978364f1 AF |
1935 | { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, |
1936 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, | |
1937 | .access = PL0_RW, .accessfn = pmreg_access, | |
f4efb4b2 | 1938 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
978364f1 AF |
1939 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
1940 | .writefn = pmovsr_write, | |
1941 | .raw_writefn = raw_write }, | |
200ac0ef | 1942 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
f4efb4b2 AL |
1943 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
1944 | .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
0d4bfd7d AL |
1945 | .writefn = pmswinc_write }, |
1946 | { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64, | |
1947 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4, | |
f4efb4b2 AL |
1948 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
1949 | .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
0d4bfd7d | 1950 | .writefn = pmswinc_write }, |
6b040780 WH |
1951 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, |
1952 | .access = PL0_RW, .type = ARM_CP_ALIAS, | |
1953 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), | |
6ecd0b6b | 1954 | .accessfn = pmreg_access_selr, .writefn = pmselr_write, |
6b040780 WH |
1955 | .raw_writefn = raw_write}, |
1956 | { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, | |
1957 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, | |
6ecd0b6b | 1958 | .access = PL0_RW, .accessfn = pmreg_access_selr, |
6b040780 WH |
1959 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), |
1960 | .writefn = pmselr_write, .raw_writefn = raw_write, }, | |
200ac0ef | 1961 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
169c8938 | 1962 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO, |
421c7ebd | 1963 | .readfn = pmccntr_read, .writefn = pmccntr_write32, |
6ecd0b6b | 1964 | .accessfn = pmreg_access_ccntr }, |
8521466b AF |
1965 | { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, |
1966 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, | |
6ecd0b6b | 1967 | .access = PL0_RW, .accessfn = pmreg_access_ccntr, |
8521466b | 1968 | .type = ARM_CP_IO, |
980ebe87 AL |
1969 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt), |
1970 | .readfn = pmccntr_read, .writefn = pmccntr_write, | |
1971 | .raw_readfn = raw_read, .raw_writefn = raw_write, }, | |
4b8afa1f AL |
1972 | { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7, |
1973 | .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32, | |
1974 | .access = PL0_RW, .accessfn = pmreg_access, | |
1975 | .type = ARM_CP_ALIAS | ARM_CP_IO, | |
1976 | .resetvalue = 0, }, | |
8521466b AF |
1977 | { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, |
1978 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, | |
980ebe87 | 1979 | .writefn = pmccfiltr_write, .raw_writefn = raw_write, |
8521466b AF |
1980 | .access = PL0_RW, .accessfn = pmreg_access, |
1981 | .type = ARM_CP_IO, | |
1982 | .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), | |
1983 | .resetvalue = 0, }, | |
200ac0ef | 1984 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
5ecdd3e4 AL |
1985 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
1986 | .accessfn = pmreg_access, | |
fdb86656 WH |
1987 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
1988 | { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, | |
1989 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, | |
5ecdd3e4 AL |
1990 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
1991 | .accessfn = pmreg_access, | |
fdb86656 | 1992 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
200ac0ef | 1993 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
5ecdd3e4 AL |
1994 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
1995 | .accessfn = pmreg_access_xevcntr, | |
1996 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, | |
1997 | { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64, | |
1998 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2, | |
1999 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
2000 | .accessfn = pmreg_access_xevcntr, | |
2001 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, | |
200ac0ef | 2002 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
1fce1ba9 | 2003 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, |
e4e91a21 | 2004 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr), |
200ac0ef | 2005 | .resetvalue = 0, |
d4e6df63 | 2006 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
8a83ffc2 AF |
2007 | { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, |
2008 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, | |
1fce1ba9 | 2009 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, |
8a83ffc2 AF |
2010 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), |
2011 | .resetvalue = 0, | |
2012 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, | |
200ac0ef | 2013 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
1fce1ba9 | 2014 | .access = PL1_RW, .accessfn = access_tpm, |
b7d793ad | 2015 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
e6ec5457 | 2016 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), |
200ac0ef | 2017 | .resetvalue = 0, |
d4e6df63 | 2018 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
e6ec5457 WH |
2019 | { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, |
2020 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, | |
2021 | .access = PL1_RW, .accessfn = access_tpm, | |
2022 | .type = ARM_CP_IO, | |
2023 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
2024 | .writefn = pmintenset_write, .raw_writefn = raw_write, | |
2025 | .resetvalue = 0x0 }, | |
200ac0ef | 2026 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
fc5f6856 | 2027 | .access = PL1_RW, .accessfn = access_tpm, |
887c0f15 | 2028 | .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, |
200ac0ef | 2029 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
b061a82b | 2030 | .writefn = pmintenclr_write, }, |
978364f1 AF |
2031 | { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, |
2032 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, | |
fc5f6856 | 2033 | .access = PL1_RW, .accessfn = access_tpm, |
887c0f15 | 2034 | .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, |
978364f1 AF |
2035 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
2036 | .writefn = pmintenclr_write }, | |
7da845b0 PM |
2037 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, |
2038 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | |
630fcd4d MZ |
2039 | .access = PL1_R, |
2040 | .accessfn = access_aa64_tid2, | |
2041 | .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, | |
7da845b0 PM |
2042 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, |
2043 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | |
630fcd4d MZ |
2044 | .access = PL1_RW, |
2045 | .accessfn = access_aa64_tid2, | |
2046 | .writefn = csselr_write, .resetvalue = 0, | |
b85a1fd6 FA |
2047 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), |
2048 | offsetof(CPUARMState, cp15.csselr_ns) } }, | |
776d4e5c PM |
2049 | /* Auxiliary ID register: this actually has an IMPDEF value but for now |
2050 | * just RAZ for all cores: | |
2051 | */ | |
0ff644a7 PM |
2052 | { .name = "AIDR", .state = ARM_CP_STATE_BOTH, |
2053 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, | |
93fbc983 MZ |
2054 | .access = PL1_R, .type = ARM_CP_CONST, |
2055 | .accessfn = access_aa64_tid1, | |
2056 | .resetvalue = 0 }, | |
f32cdad5 PM |
2057 | /* Auxiliary fault status registers: these also are IMPDEF, and we |
2058 | * choose to RAZ/WI for all cores. | |
2059 | */ | |
2060 | { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, | |
2061 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, | |
84929218 RH |
2062 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
2063 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
f32cdad5 PM |
2064 | { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, |
2065 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, | |
84929218 RH |
2066 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
2067 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b0fe2427 PM |
2068 | /* MAIR can just read-as-written because we don't implement caches |
2069 | * and so don't need to care about memory attributes. | |
2070 | */ | |
2071 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | |
2072 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | |
84929218 RH |
2073 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
2074 | .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), | |
b0fe2427 | 2075 | .resetvalue = 0 }, |
4cfb8ad8 PM |
2076 | { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, |
2077 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, | |
2078 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), | |
2079 | .resetvalue = 0 }, | |
b0fe2427 PM |
2080 | /* For non-long-descriptor page tables these are PRRR and NMRR; |
2081 | * regardless they still act as reads-as-written for QEMU. | |
b0fe2427 | 2082 | */ |
1281f8e3 | 2083 | /* MAIR0/1 are defined separately from their 64-bit counterpart which |
be693c87 GB |
2084 | * allows them to assign the correct fieldoffset based on the endianness |
2085 | * handled in the field definitions. | |
2086 | */ | |
a903c449 | 2087 | { .name = "MAIR0", .state = ARM_CP_STATE_AA32, |
84929218 RH |
2088 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, |
2089 | .access = PL1_RW, .accessfn = access_tvm_trvm, | |
be693c87 GB |
2090 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), |
2091 | offsetof(CPUARMState, cp15.mair0_ns) }, | |
b0fe2427 | 2092 | .resetfn = arm_cp_reset_ignore }, |
a903c449 | 2093 | { .name = "MAIR1", .state = ARM_CP_STATE_AA32, |
84929218 RH |
2094 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, |
2095 | .access = PL1_RW, .accessfn = access_tvm_trvm, | |
be693c87 GB |
2096 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), |
2097 | offsetof(CPUARMState, cp15.mair1_ns) }, | |
b0fe2427 | 2098 | .resetfn = arm_cp_reset_ignore }, |
1090b9c6 PM |
2099 | { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, |
2100 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, | |
7a0e58fa | 2101 | .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, |
995939a6 PM |
2102 | /* 32 bit ITLB invalidates */ |
2103 | { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, | |
30881b73 RH |
2104 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2105 | .writefn = tlbiall_write }, | |
995939a6 | 2106 | { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, |
30881b73 RH |
2107 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2108 | .writefn = tlbimva_write }, | |
995939a6 | 2109 | { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, |
30881b73 RH |
2110 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2111 | .writefn = tlbiasid_write }, | |
995939a6 PM |
2112 | /* 32 bit DTLB invalidates */ |
2113 | { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, | |
30881b73 RH |
2114 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2115 | .writefn = tlbiall_write }, | |
995939a6 | 2116 | { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, |
30881b73 RH |
2117 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2118 | .writefn = tlbimva_write }, | |
995939a6 | 2119 | { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, |
30881b73 RH |
2120 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2121 | .writefn = tlbiasid_write }, | |
995939a6 PM |
2122 | /* 32 bit TLB invalidates */ |
2123 | { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | |
30881b73 RH |
2124 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2125 | .writefn = tlbiall_write }, | |
995939a6 | 2126 | { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
30881b73 RH |
2127 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2128 | .writefn = tlbimva_write }, | |
995939a6 | 2129 | { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
30881b73 RH |
2130 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2131 | .writefn = tlbiasid_write }, | |
995939a6 | 2132 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
30881b73 RH |
2133 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2134 | .writefn = tlbimvaa_write }, | |
995939a6 PM |
2135 | }; |
2136 | ||
2137 | static const ARMCPRegInfo v7mp_cp_reginfo[] = { | |
2138 | /* 32 bit TLB invalidates, Inner Shareable */ | |
2139 | { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | |
30881b73 RH |
2140 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2141 | .writefn = tlbiall_is_write }, | |
995939a6 | 2142 | { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
30881b73 RH |
2143 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2144 | .writefn = tlbimva_is_write }, | |
995939a6 | 2145 | { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
30881b73 | 2146 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
fa439fc5 | 2147 | .writefn = tlbiasid_is_write }, |
995939a6 | 2148 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
30881b73 | 2149 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
fa439fc5 | 2150 | .writefn = tlbimvaa_is_write }, |
e9aa6c21 PM |
2151 | }; |
2152 | ||
327dd510 AL |
2153 | static const ARMCPRegInfo pmovsset_cp_reginfo[] = { |
2154 | /* PMOVSSET is not implemented in v7 before v7ve */ | |
2155 | { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3, | |
2156 | .access = PL0_RW, .accessfn = pmreg_access, | |
f4efb4b2 | 2157 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
327dd510 AL |
2158 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
2159 | .writefn = pmovsset_write, | |
2160 | .raw_writefn = raw_write }, | |
2161 | { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64, | |
2162 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3, | |
2163 | .access = PL0_RW, .accessfn = pmreg_access, | |
f4efb4b2 | 2164 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
327dd510 AL |
2165 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
2166 | .writefn = pmovsset_write, | |
2167 | .raw_writefn = raw_write }, | |
327dd510 AL |
2168 | }; |
2169 | ||
c4241c7d PM |
2170 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2171 | uint64_t value) | |
c326b979 PM |
2172 | { |
2173 | value &= 1; | |
2174 | env->teecr = value; | |
c326b979 PM |
2175 | } |
2176 | ||
cc7613bf PM |
2177 | static CPAccessResult teecr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2178 | bool isread) | |
2179 | { | |
2180 | /* | |
2181 | * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE | |
2182 | * at all, so we don't need to check whether we're v8A. | |
2183 | */ | |
2184 | if (arm_current_el(env) < 2 && !arm_is_secure_below_el3(env) && | |
2185 | (env->cp15.hstr_el2 & HSTR_TTEE)) { | |
2186 | return CP_ACCESS_TRAP_EL2; | |
2187 | } | |
2188 | return CP_ACCESS_OK; | |
2189 | } | |
2190 | ||
3f208fd7 PM |
2191 | static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2192 | bool isread) | |
c326b979 | 2193 | { |
dcbff19b | 2194 | if (arm_current_el(env) == 0 && (env->teecr & 1)) { |
92611c00 | 2195 | return CP_ACCESS_TRAP; |
c326b979 | 2196 | } |
cc7613bf | 2197 | return teecr_access(env, ri, isread); |
c326b979 PM |
2198 | } |
2199 | ||
2200 | static const ARMCPRegInfo t2ee_cp_reginfo[] = { | |
2201 | { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, | |
2202 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), | |
2203 | .resetvalue = 0, | |
cc7613bf | 2204 | .writefn = teecr_write, .accessfn = teecr_access }, |
c326b979 PM |
2205 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, |
2206 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | |
92611c00 | 2207 | .accessfn = teehbr_access, .resetvalue = 0 }, |
c326b979 PM |
2208 | }; |
2209 | ||
4d31c596 | 2210 | static const ARMCPRegInfo v6k_cp_reginfo[] = { |
e4fe830b PM |
2211 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, |
2212 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | |
2213 | .access = PL0_RW, | |
54bf36ed | 2214 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, |
4d31c596 PM |
2215 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
2216 | .access = PL0_RW, | |
54bf36ed FA |
2217 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), |
2218 | offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, | |
e4fe830b PM |
2219 | .resetfn = arm_cp_reset_ignore }, |
2220 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | |
2221 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | |
2222 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
2223 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), |
2224 | .resetvalue = 0}, | |
4d31c596 PM |
2225 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
2226 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
2227 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), |
2228 | offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, | |
e4fe830b | 2229 | .resetfn = arm_cp_reset_ignore }, |
54bf36ed | 2230 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, |
e4fe830b | 2231 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, |
4d31c596 | 2232 | .access = PL1_RW, |
54bf36ed FA |
2233 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, |
2234 | { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, | |
2235 | .access = PL1_RW, | |
2236 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), | |
2237 | offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, | |
2238 | .resetvalue = 0 }, | |
4d31c596 PM |
2239 | }; |
2240 | ||
55d284af PM |
2241 | #ifndef CONFIG_USER_ONLY |
2242 | ||
3f208fd7 PM |
2243 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2244 | bool isread) | |
00108f2d | 2245 | { |
75502672 PM |
2246 | /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. |
2247 | * Writable only at the highest implemented exception level. | |
2248 | */ | |
2249 | int el = arm_current_el(env); | |
5bc84371 RH |
2250 | uint64_t hcr; |
2251 | uint32_t cntkctl; | |
75502672 PM |
2252 | |
2253 | switch (el) { | |
2254 | case 0: | |
5bc84371 RH |
2255 | hcr = arm_hcr_el2_eff(env); |
2256 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2257 | cntkctl = env->cp15.cnthctl_el2; | |
2258 | } else { | |
2259 | cntkctl = env->cp15.c14_cntkctl; | |
2260 | } | |
2261 | if (!extract32(cntkctl, 0, 2)) { | |
75502672 PM |
2262 | return CP_ACCESS_TRAP; |
2263 | } | |
2264 | break; | |
2265 | case 1: | |
2266 | if (!isread && ri->state == ARM_CP_STATE_AA32 && | |
2267 | arm_is_secure_below_el3(env)) { | |
2268 | /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ | |
2269 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2270 | } | |
2271 | break; | |
2272 | case 2: | |
2273 | case 3: | |
2274 | break; | |
00108f2d | 2275 | } |
75502672 PM |
2276 | |
2277 | if (!isread && el < arm_highest_el(env)) { | |
2278 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2279 | } | |
2280 | ||
00108f2d PM |
2281 | return CP_ACCESS_OK; |
2282 | } | |
2283 | ||
3f208fd7 PM |
2284 | static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, |
2285 | bool isread) | |
00108f2d | 2286 | { |
0b6440af | 2287 | unsigned int cur_el = arm_current_el(env); |
e6ef0169 | 2288 | bool has_el2 = arm_is_el2_enabled(env); |
5bc84371 | 2289 | uint64_t hcr = arm_hcr_el2_eff(env); |
0b6440af | 2290 | |
5bc84371 RH |
2291 | switch (cur_el) { |
2292 | case 0: | |
2293 | /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */ | |
2294 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2295 | return (extract32(env->cp15.cnthctl_el2, timeridx, 1) | |
2296 | ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); | |
2297 | } | |
0b6440af | 2298 | |
5bc84371 RH |
2299 | /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */ |
2300 | if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) { | |
2301 | return CP_ACCESS_TRAP; | |
2302 | } | |
2303 | ||
2304 | /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */ | |
2305 | if (hcr & HCR_E2H) { | |
2306 | if (timeridx == GTIMER_PHYS && | |
2307 | !extract32(env->cp15.cnthctl_el2, 10, 1)) { | |
2308 | return CP_ACCESS_TRAP_EL2; | |
2309 | } | |
2310 | } else { | |
2311 | /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */ | |
e6ef0169 | 2312 | if (has_el2 && timeridx == GTIMER_PHYS && |
5bc84371 RH |
2313 | !extract32(env->cp15.cnthctl_el2, 1, 1)) { |
2314 | return CP_ACCESS_TRAP_EL2; | |
2315 | } | |
2316 | } | |
2317 | break; | |
2318 | ||
2319 | case 1: | |
2320 | /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */ | |
e6ef0169 | 2321 | if (has_el2 && timeridx == GTIMER_PHYS && |
5bc84371 RH |
2322 | (hcr & HCR_E2H |
2323 | ? !extract32(env->cp15.cnthctl_el2, 10, 1) | |
2324 | : !extract32(env->cp15.cnthctl_el2, 0, 1))) { | |
2325 | return CP_ACCESS_TRAP_EL2; | |
2326 | } | |
2327 | break; | |
0b6440af | 2328 | } |
00108f2d PM |
2329 | return CP_ACCESS_OK; |
2330 | } | |
2331 | ||
3f208fd7 PM |
2332 | static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, |
2333 | bool isread) | |
00108f2d | 2334 | { |
0b6440af | 2335 | unsigned int cur_el = arm_current_el(env); |
e6ef0169 | 2336 | bool has_el2 = arm_is_el2_enabled(env); |
5bc84371 | 2337 | uint64_t hcr = arm_hcr_el2_eff(env); |
0b6440af | 2338 | |
5bc84371 RH |
2339 | switch (cur_el) { |
2340 | case 0: | |
2341 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2342 | /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */ | |
2343 | return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1) | |
2344 | ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); | |
2345 | } | |
0b6440af | 2346 | |
5bc84371 RH |
2347 | /* |
2348 | * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from | |
2349 | * EL0 if EL0[PV]TEN is zero. | |
2350 | */ | |
2351 | if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { | |
2352 | return CP_ACCESS_TRAP; | |
2353 | } | |
2354 | /* fall through */ | |
2355 | ||
2356 | case 1: | |
e6ef0169 | 2357 | if (has_el2 && timeridx == GTIMER_PHYS) { |
5bc84371 RH |
2358 | if (hcr & HCR_E2H) { |
2359 | /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */ | |
2360 | if (!extract32(env->cp15.cnthctl_el2, 11, 1)) { | |
2361 | return CP_ACCESS_TRAP_EL2; | |
2362 | } | |
2363 | } else { | |
2364 | /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */ | |
2365 | if (!extract32(env->cp15.cnthctl_el2, 1, 1)) { | |
2366 | return CP_ACCESS_TRAP_EL2; | |
2367 | } | |
2368 | } | |
2369 | } | |
2370 | break; | |
0b6440af | 2371 | } |
00108f2d PM |
2372 | return CP_ACCESS_OK; |
2373 | } | |
2374 | ||
2375 | static CPAccessResult gt_pct_access(CPUARMState *env, | |
3f208fd7 PM |
2376 | const ARMCPRegInfo *ri, |
2377 | bool isread) | |
00108f2d | 2378 | { |
3f208fd7 | 2379 | return gt_counter_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2380 | } |
2381 | ||
2382 | static CPAccessResult gt_vct_access(CPUARMState *env, | |
3f208fd7 PM |
2383 | const ARMCPRegInfo *ri, |
2384 | bool isread) | |
00108f2d | 2385 | { |
3f208fd7 | 2386 | return gt_counter_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2387 | } |
2388 | ||
3f208fd7 PM |
2389 | static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2390 | bool isread) | |
00108f2d | 2391 | { |
3f208fd7 | 2392 | return gt_timer_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2393 | } |
2394 | ||
3f208fd7 PM |
2395 | static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2396 | bool isread) | |
00108f2d | 2397 | { |
3f208fd7 | 2398 | return gt_timer_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2399 | } |
2400 | ||
b4d3978c | 2401 | static CPAccessResult gt_stimer_access(CPUARMState *env, |
3f208fd7 PM |
2402 | const ARMCPRegInfo *ri, |
2403 | bool isread) | |
b4d3978c PM |
2404 | { |
2405 | /* The AArch64 register view of the secure physical timer is | |
2406 | * always accessible from EL3, and configurably accessible from | |
2407 | * Secure EL1. | |
2408 | */ | |
2409 | switch (arm_current_el(env)) { | |
2410 | case 1: | |
2411 | if (!arm_is_secure(env)) { | |
2412 | return CP_ACCESS_TRAP; | |
2413 | } | |
2414 | if (!(env->cp15.scr_el3 & SCR_ST)) { | |
2415 | return CP_ACCESS_TRAP_EL3; | |
2416 | } | |
2417 | return CP_ACCESS_OK; | |
2418 | case 0: | |
2419 | case 2: | |
2420 | return CP_ACCESS_TRAP; | |
2421 | case 3: | |
2422 | return CP_ACCESS_OK; | |
2423 | default: | |
2424 | g_assert_not_reached(); | |
2425 | } | |
2426 | } | |
2427 | ||
55d284af PM |
2428 | static uint64_t gt_get_countervalue(CPUARMState *env) |
2429 | { | |
7def8754 AJ |
2430 | ARMCPU *cpu = env_archcpu(env); |
2431 | ||
2432 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu); | |
55d284af PM |
2433 | } |
2434 | ||
2435 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) | |
2436 | { | |
2437 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; | |
2438 | ||
2439 | if (gt->ctl & 1) { | |
2440 | /* Timer enabled: calculate and set current ISTATUS, irq, and | |
2441 | * reset timer to when ISTATUS next has to change | |
2442 | */ | |
edac4d8a EI |
2443 | uint64_t offset = timeridx == GTIMER_VIRT ? |
2444 | cpu->env.cp15.cntvoff_el2 : 0; | |
55d284af PM |
2445 | uint64_t count = gt_get_countervalue(&cpu->env); |
2446 | /* Note that this must be unsigned 64 bit arithmetic: */ | |
edac4d8a | 2447 | int istatus = count - offset >= gt->cval; |
55d284af | 2448 | uint64_t nexttick; |
194cbc49 | 2449 | int irqstate; |
55d284af PM |
2450 | |
2451 | gt->ctl = deposit32(gt->ctl, 2, 1, istatus); | |
194cbc49 PM |
2452 | |
2453 | irqstate = (istatus && !(gt->ctl & 2)); | |
2454 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
2455 | ||
55d284af PM |
2456 | if (istatus) { |
2457 | /* Next transition is when count rolls back over to zero */ | |
2458 | nexttick = UINT64_MAX; | |
2459 | } else { | |
2460 | /* Next transition is when we hit cval */ | |
edac4d8a | 2461 | nexttick = gt->cval + offset; |
55d284af PM |
2462 | } |
2463 | /* Note that the desired next expiry time might be beyond the | |
2464 | * signed-64-bit range of a QEMUTimer -- in this case we just | |
2465 | * set the timer for as far in the future as possible. When the | |
2466 | * timer expires we will reset the timer for any remaining period. | |
2467 | */ | |
7def8754 | 2468 | if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { |
4a0245b6 AJ |
2469 | timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX); |
2470 | } else { | |
2471 | timer_mod(cpu->gt_timer[timeridx], nexttick); | |
55d284af | 2472 | } |
194cbc49 | 2473 | trace_arm_gt_recalc(timeridx, irqstate, nexttick); |
55d284af PM |
2474 | } else { |
2475 | /* Timer disabled: ISTATUS and timer output always clear */ | |
2476 | gt->ctl &= ~4; | |
2477 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); | |
bc72ad67 | 2478 | timer_del(cpu->gt_timer[timeridx]); |
194cbc49 | 2479 | trace_arm_gt_recalc_disabled(timeridx); |
55d284af PM |
2480 | } |
2481 | } | |
2482 | ||
0e3eca4c EI |
2483 | static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, |
2484 | int timeridx) | |
55d284af | 2485 | { |
2fc0cc0e | 2486 | ARMCPU *cpu = env_archcpu(env); |
55d284af | 2487 | |
bc72ad67 | 2488 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
2489 | } |
2490 | ||
c4241c7d | 2491 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
55d284af | 2492 | { |
c4241c7d | 2493 | return gt_get_countervalue(env); |
55d284af PM |
2494 | } |
2495 | ||
53d1f856 RH |
2496 | static uint64_t gt_virt_cnt_offset(CPUARMState *env) |
2497 | { | |
2498 | uint64_t hcr; | |
2499 | ||
2500 | switch (arm_current_el(env)) { | |
2501 | case 2: | |
2502 | hcr = arm_hcr_el2_eff(env); | |
2503 | if (hcr & HCR_E2H) { | |
2504 | return 0; | |
2505 | } | |
2506 | break; | |
2507 | case 0: | |
2508 | hcr = arm_hcr_el2_eff(env); | |
2509 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2510 | return 0; | |
2511 | } | |
2512 | break; | |
2513 | } | |
2514 | ||
2515 | return env->cp15.cntvoff_el2; | |
2516 | } | |
2517 | ||
edac4d8a EI |
2518 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2519 | { | |
53d1f856 | 2520 | return gt_get_countervalue(env) - gt_virt_cnt_offset(env); |
edac4d8a EI |
2521 | } |
2522 | ||
c4241c7d | 2523 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2524 | int timeridx, |
c4241c7d | 2525 | uint64_t value) |
55d284af | 2526 | { |
194cbc49 | 2527 | trace_arm_gt_cval_write(timeridx, value); |
55d284af | 2528 | env->cp15.c14_timer[timeridx].cval = value; |
2fc0cc0e | 2529 | gt_recalc_timer(env_archcpu(env), timeridx); |
55d284af | 2530 | } |
c4241c7d | 2531 | |
0e3eca4c EI |
2532 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, |
2533 | int timeridx) | |
55d284af | 2534 | { |
53d1f856 RH |
2535 | uint64_t offset = 0; |
2536 | ||
2537 | switch (timeridx) { | |
2538 | case GTIMER_VIRT: | |
8c94b071 | 2539 | case GTIMER_HYPVIRT: |
53d1f856 RH |
2540 | offset = gt_virt_cnt_offset(env); |
2541 | break; | |
2542 | } | |
55d284af | 2543 | |
c4241c7d | 2544 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - |
edac4d8a | 2545 | (gt_get_countervalue(env) - offset)); |
55d284af PM |
2546 | } |
2547 | ||
c4241c7d | 2548 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2549 | int timeridx, |
c4241c7d | 2550 | uint64_t value) |
55d284af | 2551 | { |
53d1f856 RH |
2552 | uint64_t offset = 0; |
2553 | ||
2554 | switch (timeridx) { | |
2555 | case GTIMER_VIRT: | |
8c94b071 | 2556 | case GTIMER_HYPVIRT: |
53d1f856 RH |
2557 | offset = gt_virt_cnt_offset(env); |
2558 | break; | |
2559 | } | |
55d284af | 2560 | |
194cbc49 | 2561 | trace_arm_gt_tval_write(timeridx, value); |
edac4d8a | 2562 | env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + |
18084b2f | 2563 | sextract64(value, 0, 32); |
2fc0cc0e | 2564 | gt_recalc_timer(env_archcpu(env), timeridx); |
55d284af PM |
2565 | } |
2566 | ||
c4241c7d | 2567 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2568 | int timeridx, |
c4241c7d | 2569 | uint64_t value) |
55d284af | 2570 | { |
2fc0cc0e | 2571 | ARMCPU *cpu = env_archcpu(env); |
55d284af PM |
2572 | uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; |
2573 | ||
194cbc49 | 2574 | trace_arm_gt_ctl_write(timeridx, value); |
d3afacc7 | 2575 | env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); |
55d284af PM |
2576 | if ((oldval ^ value) & 1) { |
2577 | /* Enable toggled */ | |
2578 | gt_recalc_timer(cpu, timeridx); | |
d3afacc7 | 2579 | } else if ((oldval ^ value) & 2) { |
55d284af PM |
2580 | /* IMASK toggled: don't need to recalculate, |
2581 | * just set the interrupt line based on ISTATUS | |
2582 | */ | |
194cbc49 PM |
2583 | int irqstate = (oldval & 4) && !(value & 2); |
2584 | ||
2585 | trace_arm_gt_imask_toggle(timeridx, irqstate); | |
2586 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
55d284af | 2587 | } |
55d284af PM |
2588 | } |
2589 | ||
0e3eca4c EI |
2590 | static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2591 | { | |
2592 | gt_timer_reset(env, ri, GTIMER_PHYS); | |
2593 | } | |
2594 | ||
2595 | static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2596 | uint64_t value) | |
2597 | { | |
2598 | gt_cval_write(env, ri, GTIMER_PHYS, value); | |
2599 | } | |
2600 | ||
2601 | static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2602 | { | |
2603 | return gt_tval_read(env, ri, GTIMER_PHYS); | |
2604 | } | |
2605 | ||
2606 | static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2607 | uint64_t value) | |
2608 | { | |
2609 | gt_tval_write(env, ri, GTIMER_PHYS, value); | |
2610 | } | |
2611 | ||
2612 | static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2613 | uint64_t value) | |
2614 | { | |
2615 | gt_ctl_write(env, ri, GTIMER_PHYS, value); | |
2616 | } | |
2617 | ||
bb5972e4 RH |
2618 | static int gt_phys_redir_timeridx(CPUARMState *env) |
2619 | { | |
2620 | switch (arm_mmu_idx(env)) { | |
2621 | case ARMMMUIdx_E20_0: | |
2622 | case ARMMMUIdx_E20_2: | |
452ef8cb | 2623 | case ARMMMUIdx_E20_2_PAN: |
b6ad6062 RDC |
2624 | case ARMMMUIdx_SE20_0: |
2625 | case ARMMMUIdx_SE20_2: | |
2626 | case ARMMMUIdx_SE20_2_PAN: | |
bb5972e4 RH |
2627 | return GTIMER_HYP; |
2628 | default: | |
2629 | return GTIMER_PHYS; | |
2630 | } | |
2631 | } | |
2632 | ||
2633 | static int gt_virt_redir_timeridx(CPUARMState *env) | |
2634 | { | |
2635 | switch (arm_mmu_idx(env)) { | |
2636 | case ARMMMUIdx_E20_0: | |
2637 | case ARMMMUIdx_E20_2: | |
452ef8cb | 2638 | case ARMMMUIdx_E20_2_PAN: |
b6ad6062 RDC |
2639 | case ARMMMUIdx_SE20_0: |
2640 | case ARMMMUIdx_SE20_2: | |
2641 | case ARMMMUIdx_SE20_2_PAN: | |
bb5972e4 RH |
2642 | return GTIMER_HYPVIRT; |
2643 | default: | |
2644 | return GTIMER_VIRT; | |
2645 | } | |
2646 | } | |
2647 | ||
2648 | static uint64_t gt_phys_redir_cval_read(CPUARMState *env, | |
2649 | const ARMCPRegInfo *ri) | |
2650 | { | |
2651 | int timeridx = gt_phys_redir_timeridx(env); | |
2652 | return env->cp15.c14_timer[timeridx].cval; | |
2653 | } | |
2654 | ||
2655 | static void gt_phys_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2656 | uint64_t value) | |
2657 | { | |
2658 | int timeridx = gt_phys_redir_timeridx(env); | |
2659 | gt_cval_write(env, ri, timeridx, value); | |
2660 | } | |
2661 | ||
2662 | static uint64_t gt_phys_redir_tval_read(CPUARMState *env, | |
2663 | const ARMCPRegInfo *ri) | |
2664 | { | |
2665 | int timeridx = gt_phys_redir_timeridx(env); | |
2666 | return gt_tval_read(env, ri, timeridx); | |
2667 | } | |
2668 | ||
2669 | static void gt_phys_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2670 | uint64_t value) | |
2671 | { | |
2672 | int timeridx = gt_phys_redir_timeridx(env); | |
2673 | gt_tval_write(env, ri, timeridx, value); | |
2674 | } | |
2675 | ||
2676 | static uint64_t gt_phys_redir_ctl_read(CPUARMState *env, | |
2677 | const ARMCPRegInfo *ri) | |
2678 | { | |
2679 | int timeridx = gt_phys_redir_timeridx(env); | |
2680 | return env->cp15.c14_timer[timeridx].ctl; | |
2681 | } | |
2682 | ||
2683 | static void gt_phys_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2684 | uint64_t value) | |
2685 | { | |
2686 | int timeridx = gt_phys_redir_timeridx(env); | |
2687 | gt_ctl_write(env, ri, timeridx, value); | |
2688 | } | |
2689 | ||
0e3eca4c EI |
2690 | static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2691 | { | |
2692 | gt_timer_reset(env, ri, GTIMER_VIRT); | |
2693 | } | |
2694 | ||
2695 | static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2696 | uint64_t value) | |
2697 | { | |
2698 | gt_cval_write(env, ri, GTIMER_VIRT, value); | |
2699 | } | |
2700 | ||
2701 | static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2702 | { | |
2703 | return gt_tval_read(env, ri, GTIMER_VIRT); | |
2704 | } | |
2705 | ||
2706 | static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2707 | uint64_t value) | |
2708 | { | |
2709 | gt_tval_write(env, ri, GTIMER_VIRT, value); | |
2710 | } | |
2711 | ||
2712 | static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2713 | uint64_t value) | |
2714 | { | |
2715 | gt_ctl_write(env, ri, GTIMER_VIRT, value); | |
2716 | } | |
2717 | ||
edac4d8a EI |
2718 | static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2719 | uint64_t value) | |
2720 | { | |
2fc0cc0e | 2721 | ARMCPU *cpu = env_archcpu(env); |
edac4d8a | 2722 | |
194cbc49 | 2723 | trace_arm_gt_cntvoff_write(value); |
edac4d8a EI |
2724 | raw_write(env, ri, value); |
2725 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
2726 | } | |
2727 | ||
bb5972e4 RH |
2728 | static uint64_t gt_virt_redir_cval_read(CPUARMState *env, |
2729 | const ARMCPRegInfo *ri) | |
2730 | { | |
2731 | int timeridx = gt_virt_redir_timeridx(env); | |
2732 | return env->cp15.c14_timer[timeridx].cval; | |
2733 | } | |
2734 | ||
2735 | static void gt_virt_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2736 | uint64_t value) | |
2737 | { | |
2738 | int timeridx = gt_virt_redir_timeridx(env); | |
2739 | gt_cval_write(env, ri, timeridx, value); | |
2740 | } | |
2741 | ||
2742 | static uint64_t gt_virt_redir_tval_read(CPUARMState *env, | |
2743 | const ARMCPRegInfo *ri) | |
2744 | { | |
2745 | int timeridx = gt_virt_redir_timeridx(env); | |
2746 | return gt_tval_read(env, ri, timeridx); | |
2747 | } | |
2748 | ||
2749 | static void gt_virt_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2750 | uint64_t value) | |
2751 | { | |
2752 | int timeridx = gt_virt_redir_timeridx(env); | |
2753 | gt_tval_write(env, ri, timeridx, value); | |
2754 | } | |
2755 | ||
2756 | static uint64_t gt_virt_redir_ctl_read(CPUARMState *env, | |
2757 | const ARMCPRegInfo *ri) | |
2758 | { | |
2759 | int timeridx = gt_virt_redir_timeridx(env); | |
2760 | return env->cp15.c14_timer[timeridx].ctl; | |
2761 | } | |
2762 | ||
2763 | static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2764 | uint64_t value) | |
2765 | { | |
2766 | int timeridx = gt_virt_redir_timeridx(env); | |
2767 | gt_ctl_write(env, ri, timeridx, value); | |
2768 | } | |
2769 | ||
b0e66d95 EI |
2770 | static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2771 | { | |
2772 | gt_timer_reset(env, ri, GTIMER_HYP); | |
2773 | } | |
2774 | ||
2775 | static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2776 | uint64_t value) | |
2777 | { | |
2778 | gt_cval_write(env, ri, GTIMER_HYP, value); | |
2779 | } | |
2780 | ||
2781 | static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2782 | { | |
2783 | return gt_tval_read(env, ri, GTIMER_HYP); | |
2784 | } | |
2785 | ||
2786 | static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2787 | uint64_t value) | |
2788 | { | |
2789 | gt_tval_write(env, ri, GTIMER_HYP, value); | |
2790 | } | |
2791 | ||
2792 | static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2793 | uint64_t value) | |
2794 | { | |
2795 | gt_ctl_write(env, ri, GTIMER_HYP, value); | |
2796 | } | |
2797 | ||
b4d3978c PM |
2798 | static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2799 | { | |
2800 | gt_timer_reset(env, ri, GTIMER_SEC); | |
2801 | } | |
2802 | ||
2803 | static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2804 | uint64_t value) | |
2805 | { | |
2806 | gt_cval_write(env, ri, GTIMER_SEC, value); | |
2807 | } | |
2808 | ||
2809 | static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2810 | { | |
2811 | return gt_tval_read(env, ri, GTIMER_SEC); | |
2812 | } | |
2813 | ||
2814 | static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2815 | uint64_t value) | |
2816 | { | |
2817 | gt_tval_write(env, ri, GTIMER_SEC, value); | |
2818 | } | |
2819 | ||
2820 | static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2821 | uint64_t value) | |
2822 | { | |
2823 | gt_ctl_write(env, ri, GTIMER_SEC, value); | |
2824 | } | |
2825 | ||
8c94b071 RH |
2826 | static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2827 | { | |
2828 | gt_timer_reset(env, ri, GTIMER_HYPVIRT); | |
2829 | } | |
2830 | ||
2831 | static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2832 | uint64_t value) | |
2833 | { | |
2834 | gt_cval_write(env, ri, GTIMER_HYPVIRT, value); | |
2835 | } | |
2836 | ||
2837 | static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2838 | { | |
2839 | return gt_tval_read(env, ri, GTIMER_HYPVIRT); | |
2840 | } | |
2841 | ||
2842 | static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2843 | uint64_t value) | |
2844 | { | |
2845 | gt_tval_write(env, ri, GTIMER_HYPVIRT, value); | |
2846 | } | |
2847 | ||
2848 | static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2849 | uint64_t value) | |
2850 | { | |
2851 | gt_ctl_write(env, ri, GTIMER_HYPVIRT, value); | |
2852 | } | |
2853 | ||
55d284af PM |
2854 | void arm_gt_ptimer_cb(void *opaque) |
2855 | { | |
2856 | ARMCPU *cpu = opaque; | |
2857 | ||
2858 | gt_recalc_timer(cpu, GTIMER_PHYS); | |
2859 | } | |
2860 | ||
2861 | void arm_gt_vtimer_cb(void *opaque) | |
2862 | { | |
2863 | ARMCPU *cpu = opaque; | |
2864 | ||
2865 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
2866 | } | |
2867 | ||
b0e66d95 EI |
2868 | void arm_gt_htimer_cb(void *opaque) |
2869 | { | |
2870 | ARMCPU *cpu = opaque; | |
2871 | ||
2872 | gt_recalc_timer(cpu, GTIMER_HYP); | |
2873 | } | |
2874 | ||
b4d3978c PM |
2875 | void arm_gt_stimer_cb(void *opaque) |
2876 | { | |
2877 | ARMCPU *cpu = opaque; | |
2878 | ||
2879 | gt_recalc_timer(cpu, GTIMER_SEC); | |
2880 | } | |
2881 | ||
8c94b071 RH |
2882 | void arm_gt_hvtimer_cb(void *opaque) |
2883 | { | |
2884 | ARMCPU *cpu = opaque; | |
2885 | ||
2886 | gt_recalc_timer(cpu, GTIMER_HYPVIRT); | |
2887 | } | |
2888 | ||
96eec6b2 AJ |
2889 | static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque) |
2890 | { | |
2891 | ARMCPU *cpu = env_archcpu(env); | |
2892 | ||
2893 | cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz; | |
2894 | } | |
2895 | ||
55d284af PM |
2896 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
2897 | /* Note that CNTFRQ is purely reads-as-written for the benefit | |
2898 | * of software; writing it doesn't actually change the timer frequency. | |
2899 | * Our reset value matches the fixed frequency we implement the timer at. | |
2900 | */ | |
2901 | { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 2902 | .type = ARM_CP_ALIAS, |
a7adc4b7 PM |
2903 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, |
2904 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), | |
a7adc4b7 PM |
2905 | }, |
2906 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, | |
2907 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
2908 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
55d284af | 2909 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), |
96eec6b2 | 2910 | .resetfn = arm_gt_cntfrq_reset, |
55d284af PM |
2911 | }, |
2912 | /* overall control: mostly access permissions */ | |
a7adc4b7 PM |
2913 | { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, |
2914 | .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, | |
55d284af PM |
2915 | .access = PL1_RW, |
2916 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), | |
2917 | .resetvalue = 0, | |
2918 | }, | |
2919 | /* per-timer control */ | |
2920 | { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
9ff9dd3c | 2921 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 2922 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
a7adc4b7 PM |
2923 | .accessfn = gt_ptimer_access, |
2924 | .fieldoffset = offsetoflow32(CPUARMState, | |
2925 | cp15.c14_timer[GTIMER_PHYS].ctl), | |
bb5972e4 RH |
2926 | .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read, |
2927 | .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write, | |
a7adc4b7 | 2928 | }, |
9c513e78 | 2929 | { .name = "CNTP_CTL_S", |
9ff9dd3c PM |
2930 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, |
2931 | .secure = ARM_CP_SECSTATE_S, | |
daf1dc5f | 2932 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
9ff9dd3c PM |
2933 | .accessfn = gt_ptimer_access, |
2934 | .fieldoffset = offsetoflow32(CPUARMState, | |
2935 | cp15.c14_timer[GTIMER_SEC].ctl), | |
2936 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
2937 | }, | |
a7adc4b7 PM |
2938 | { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, |
2939 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, | |
daf1dc5f | 2940 | .type = ARM_CP_IO, .access = PL0_RW, |
a7adc4b7 | 2941 | .accessfn = gt_ptimer_access, |
55d284af PM |
2942 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), |
2943 | .resetvalue = 0, | |
bb5972e4 RH |
2944 | .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read, |
2945 | .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write, | |
55d284af PM |
2946 | }, |
2947 | { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, | |
daf1dc5f | 2948 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
a7adc4b7 PM |
2949 | .accessfn = gt_vtimer_access, |
2950 | .fieldoffset = offsetoflow32(CPUARMState, | |
2951 | cp15.c14_timer[GTIMER_VIRT].ctl), | |
bb5972e4 RH |
2952 | .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read, |
2953 | .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write, | |
a7adc4b7 PM |
2954 | }, |
2955 | { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
2956 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, | |
daf1dc5f | 2957 | .type = ARM_CP_IO, .access = PL0_RW, |
a7adc4b7 | 2958 | .accessfn = gt_vtimer_access, |
55d284af PM |
2959 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), |
2960 | .resetvalue = 0, | |
bb5972e4 RH |
2961 | .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read, |
2962 | .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write, | |
55d284af PM |
2963 | }, |
2964 | /* TimerValue views: a 32 bit downcounting view of the underlying state */ | |
2965 | { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
9ff9dd3c | 2966 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 2967 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
00108f2d | 2968 | .accessfn = gt_ptimer_access, |
bb5972e4 | 2969 | .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write, |
55d284af | 2970 | }, |
9c513e78 | 2971 | { .name = "CNTP_TVAL_S", |
9ff9dd3c PM |
2972 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, |
2973 | .secure = ARM_CP_SECSTATE_S, | |
daf1dc5f | 2974 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
9ff9dd3c PM |
2975 | .accessfn = gt_ptimer_access, |
2976 | .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, | |
2977 | }, | |
a7adc4b7 PM |
2978 | { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
2979 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, | |
daf1dc5f | 2980 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
0e3eca4c | 2981 | .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, |
bb5972e4 | 2982 | .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write, |
a7adc4b7 | 2983 | }, |
55d284af | 2984 | { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, |
daf1dc5f | 2985 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
00108f2d | 2986 | .accessfn = gt_vtimer_access, |
bb5972e4 | 2987 | .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write, |
55d284af | 2988 | }, |
a7adc4b7 PM |
2989 | { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
2990 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, | |
daf1dc5f | 2991 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
0e3eca4c | 2992 | .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, |
bb5972e4 | 2993 | .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write, |
a7adc4b7 | 2994 | }, |
55d284af PM |
2995 | /* The counter itself */ |
2996 | { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, | |
7a0e58fa | 2997 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 2998 | .accessfn = gt_pct_access, |
a7adc4b7 PM |
2999 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
3000 | }, | |
3001 | { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, | |
3002 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, | |
7a0e58fa | 3003 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 3004 | .accessfn = gt_pct_access, .readfn = gt_cnt_read, |
55d284af PM |
3005 | }, |
3006 | { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, | |
7a0e58fa | 3007 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 3008 | .accessfn = gt_vct_access, |
edac4d8a | 3009 | .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, |
a7adc4b7 PM |
3010 | }, |
3011 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
3012 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
7a0e58fa | 3013 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 3014 | .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, |
55d284af PM |
3015 | }, |
3016 | /* Comparison value, indicating when the timer goes off */ | |
3017 | { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, | |
9ff9dd3c | 3018 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 3019 | .access = PL0_RW, |
7a0e58fa | 3020 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 3021 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), |
b061a82b | 3022 | .accessfn = gt_ptimer_access, |
bb5972e4 RH |
3023 | .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read, |
3024 | .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write, | |
a7adc4b7 | 3025 | }, |
9c513e78 | 3026 | { .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2, |
9ff9dd3c | 3027 | .secure = ARM_CP_SECSTATE_S, |
daf1dc5f | 3028 | .access = PL0_RW, |
9ff9dd3c PM |
3029 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
3030 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
3031 | .accessfn = gt_ptimer_access, | |
3032 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
3033 | }, | |
a7adc4b7 PM |
3034 | { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, |
3035 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, | |
daf1dc5f | 3036 | .access = PL0_RW, |
a7adc4b7 PM |
3037 | .type = ARM_CP_IO, |
3038 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
12cde08a | 3039 | .resetvalue = 0, .accessfn = gt_ptimer_access, |
bb5972e4 RH |
3040 | .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read, |
3041 | .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write, | |
55d284af PM |
3042 | }, |
3043 | { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, | |
daf1dc5f | 3044 | .access = PL0_RW, |
7a0e58fa | 3045 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 3046 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), |
b061a82b | 3047 | .accessfn = gt_vtimer_access, |
bb5972e4 RH |
3048 | .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read, |
3049 | .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write, | |
a7adc4b7 PM |
3050 | }, |
3051 | { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
3052 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, | |
daf1dc5f | 3053 | .access = PL0_RW, |
a7adc4b7 PM |
3054 | .type = ARM_CP_IO, |
3055 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
3056 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
bb5972e4 RH |
3057 | .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read, |
3058 | .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write, | |
55d284af | 3059 | }, |
b4d3978c PM |
3060 | /* Secure timer -- this is actually restricted to only EL3 |
3061 | * and configurably Secure-EL1 via the accessfn. | |
3062 | */ | |
3063 | { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, | |
3064 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, | |
3065 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, | |
3066 | .accessfn = gt_stimer_access, | |
3067 | .readfn = gt_sec_tval_read, | |
3068 | .writefn = gt_sec_tval_write, | |
3069 | .resetfn = gt_sec_timer_reset, | |
3070 | }, | |
3071 | { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64, | |
3072 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1, | |
3073 | .type = ARM_CP_IO, .access = PL1_RW, | |
3074 | .accessfn = gt_stimer_access, | |
3075 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), | |
3076 | .resetvalue = 0, | |
3077 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
3078 | }, | |
3079 | { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, | |
3080 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, | |
3081 | .type = ARM_CP_IO, .access = PL1_RW, | |
3082 | .accessfn = gt_stimer_access, | |
3083 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
3084 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
3085 | }, | |
55d284af PM |
3086 | }; |
3087 | ||
bb5972e4 RH |
3088 | static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3089 | bool isread) | |
3090 | { | |
3091 | if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { | |
3092 | return CP_ACCESS_TRAP; | |
3093 | } | |
3094 | return CP_ACCESS_OK; | |
3095 | } | |
3096 | ||
55d284af | 3097 | #else |
26c4a83b AB |
3098 | |
3099 | /* In user-mode most of the generic timer registers are inaccessible | |
3100 | * however modern kernels (4.12+) allow access to cntvct_el0 | |
55d284af | 3101 | */ |
26c4a83b AB |
3102 | |
3103 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3104 | { | |
7def8754 AJ |
3105 | ARMCPU *cpu = env_archcpu(env); |
3106 | ||
26c4a83b AB |
3107 | /* Currently we have no support for QEMUTimer in linux-user so we |
3108 | * can't call gt_get_countervalue(env), instead we directly | |
3109 | * call the lower level functions. | |
3110 | */ | |
7def8754 | 3111 | return cpu_get_clock() / gt_cntfrq_period_ns(cpu); |
26c4a83b AB |
3112 | } |
3113 | ||
6cc7a3ae | 3114 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
26c4a83b AB |
3115 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, |
3116 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
3117 | .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */, | |
3118 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), | |
3119 | .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE, | |
3120 | }, | |
3121 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
3122 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
3123 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
3124 | .readfn = gt_virt_cnt_read, | |
3125 | }, | |
6cc7a3ae PM |
3126 | }; |
3127 | ||
55d284af PM |
3128 | #endif |
3129 | ||
c4241c7d | 3130 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 3131 | { |
891a2fe7 | 3132 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8d5c773e | 3133 | raw_write(env, ri, value); |
891a2fe7 | 3134 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8d5c773e | 3135 | raw_write(env, ri, value & 0xfffff6ff); |
4a501606 | 3136 | } else { |
8d5c773e | 3137 | raw_write(env, ri, value & 0xfffff1ff); |
4a501606 | 3138 | } |
4a501606 PM |
3139 | } |
3140 | ||
3141 | #ifndef CONFIG_USER_ONLY | |
3142 | /* get_phys_addr() isn't present for user-mode-only targets */ | |
702a9357 | 3143 | |
3f208fd7 PM |
3144 | static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3145 | bool isread) | |
92611c00 PM |
3146 | { |
3147 | if (ri->opc2 & 4) { | |
926c1b97 | 3148 | /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in |
87562e4f PM |
3149 | * Secure EL1 (which can only happen if EL3 is AArch64). |
3150 | * They are simply UNDEF if executed from NS EL1. | |
3151 | * They function normally from EL2 or EL3. | |
92611c00 | 3152 | */ |
87562e4f PM |
3153 | if (arm_current_el(env) == 1) { |
3154 | if (arm_is_secure_below_el3(env)) { | |
926c1b97 RDC |
3155 | if (env->cp15.scr_el3 & SCR_EEL2) { |
3156 | return CP_ACCESS_TRAP_UNCATEGORIZED_EL2; | |
3157 | } | |
87562e4f PM |
3158 | return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; |
3159 | } | |
3160 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
3161 | } | |
92611c00 PM |
3162 | } |
3163 | return CP_ACCESS_OK; | |
3164 | } | |
3165 | ||
9fb005b0 | 3166 | #ifdef CONFIG_TCG |
060e8a48 | 3167 | static uint64_t do_ats_write(CPUARMState *env, uint64_t value, |
03ae85f8 | 3168 | MMUAccessType access_type, ARMMMUIdx mmu_idx) |
4a501606 | 3169 | { |
a8170e5e | 3170 | hwaddr phys_addr; |
4a501606 PM |
3171 | target_ulong page_size; |
3172 | int prot; | |
b7cc4e82 | 3173 | bool ret; |
01c097f7 | 3174 | uint64_t par64; |
1313e2d7 | 3175 | bool format64 = false; |
8bf5b6a9 | 3176 | MemTxAttrs attrs = {}; |
e14b5a23 | 3177 | ARMMMUFaultInfo fi = {}; |
5b2d261d | 3178 | ARMCacheAttrs cacheattrs = {}; |
4a501606 | 3179 | |
5b2d261d | 3180 | ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, |
bc52bfeb | 3181 | &prot, &page_size, &fi, &cacheattrs); |
1313e2d7 | 3182 | |
9f225e60 PM |
3183 | /* |
3184 | * ATS operations only do S1 or S1+S2 translations, so we never | |
3185 | * have to deal with the ARMCacheAttrs format for S2 only. | |
3186 | */ | |
3187 | assert(!cacheattrs.is_s2_format); | |
3188 | ||
0710b2fa PM |
3189 | if (ret) { |
3190 | /* | |
3191 | * Some kinds of translation fault must cause exceptions rather | |
3192 | * than being reported in the PAR. | |
3193 | */ | |
3194 | int current_el = arm_current_el(env); | |
3195 | int target_el; | |
3196 | uint32_t syn, fsr, fsc; | |
3197 | bool take_exc = false; | |
3198 | ||
b1a10c86 | 3199 | if (fi.s1ptw && current_el == 1 |
fee7aa46 | 3200 | && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { |
0710b2fa PM |
3201 | /* |
3202 | * Synchronous stage 2 fault on an access made as part of the | |
3203 | * translation table walk for AT S1E0* or AT S1E1* insn | |
3204 | * executed from NS EL1. If this is a synchronous external abort | |
3205 | * and SCR_EL3.EA == 1, then we take a synchronous external abort | |
3206 | * to EL3. Otherwise the fault is taken as an exception to EL2, | |
3207 | * and HPFAR_EL2 holds the faulting IPA. | |
3208 | */ | |
3209 | if (fi.type == ARMFault_SyncExternalOnWalk && | |
3210 | (env->cp15.scr_el3 & SCR_EA)) { | |
3211 | target_el = 3; | |
3212 | } else { | |
3213 | env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; | |
9861248f RDC |
3214 | if (arm_is_secure_below_el3(env) && fi.s1ns) { |
3215 | env->cp15.hpfar_el2 |= HPFAR_NS; | |
3216 | } | |
0710b2fa PM |
3217 | target_el = 2; |
3218 | } | |
3219 | take_exc = true; | |
3220 | } else if (fi.type == ARMFault_SyncExternalOnWalk) { | |
3221 | /* | |
3222 | * Synchronous external aborts during a translation table walk | |
3223 | * are taken as Data Abort exceptions. | |
3224 | */ | |
3225 | if (fi.stage2) { | |
3226 | if (current_el == 3) { | |
3227 | target_el = 3; | |
3228 | } else { | |
3229 | target_el = 2; | |
3230 | } | |
3231 | } else { | |
3232 | target_el = exception_target_el(env); | |
3233 | } | |
3234 | take_exc = true; | |
3235 | } | |
3236 | ||
3237 | if (take_exc) { | |
3238 | /* Construct FSR and FSC using same logic as arm_deliver_fault() */ | |
3239 | if (target_el == 2 || arm_el_is_aa64(env, target_el) || | |
3240 | arm_s1_regime_using_lpae_format(env, mmu_idx)) { | |
3241 | fsr = arm_fi_to_lfsc(&fi); | |
3242 | fsc = extract32(fsr, 0, 6); | |
3243 | } else { | |
3244 | fsr = arm_fi_to_sfsc(&fi); | |
3245 | fsc = 0x3f; | |
3246 | } | |
3247 | /* | |
3248 | * Report exception with ESR indicating a fault due to a | |
3249 | * translation table walk for a cache maintenance instruction. | |
3250 | */ | |
e24fd076 | 3251 | syn = syn_data_abort_no_iss(current_el == target_el, 0, |
0710b2fa PM |
3252 | fi.ea, 1, fi.s1ptw, 1, fsc); |
3253 | env->exception.vaddress = value; | |
3254 | env->exception.fsr = fsr; | |
3255 | raise_exception(env, EXCP_DATA_ABORT, syn, target_el); | |
3256 | } | |
3257 | } | |
3258 | ||
1313e2d7 EI |
3259 | if (is_a64(env)) { |
3260 | format64 = true; | |
3261 | } else if (arm_feature(env, ARM_FEATURE_LPAE)) { | |
3262 | /* | |
3263 | * ATS1Cxx: | |
3264 | * * TTBCR.EAE determines whether the result is returned using the | |
3265 | * 32-bit or the 64-bit PAR format | |
3266 | * * Instructions executed in Hyp mode always use the 64bit format | |
3267 | * | |
3268 | * ATS1S2NSOxx uses the 64bit format if any of the following is true: | |
3269 | * * The Non-secure TTBCR.EAE bit is set to 1 | |
3270 | * * The implementation includes EL2, and the value of HCR.VM is 1 | |
3271 | * | |
9d1bab33 PM |
3272 | * (Note that HCR.DC makes HCR.VM behave as if it is 1.) |
3273 | * | |
23463e0e | 3274 | * ATS1Hx always uses the 64bit format. |
1313e2d7 EI |
3275 | */ |
3276 | format64 = arm_s1_regime_using_lpae_format(env, mmu_idx); | |
3277 | ||
3278 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
452ef8cb RH |
3279 | if (mmu_idx == ARMMMUIdx_E10_0 || |
3280 | mmu_idx == ARMMMUIdx_E10_1 || | |
3281 | mmu_idx == ARMMMUIdx_E10_1_PAN) { | |
9d1bab33 | 3282 | format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC); |
1313e2d7 EI |
3283 | } else { |
3284 | format64 |= arm_current_el(env) == 2; | |
3285 | } | |
3286 | } | |
3287 | } | |
3288 | ||
3289 | if (format64) { | |
5efe9ed4 | 3290 | /* Create a 64-bit PAR */ |
01c097f7 | 3291 | par64 = (1 << 11); /* LPAE bit always set */ |
b7cc4e82 | 3292 | if (!ret) { |
702a9357 | 3293 | par64 |= phys_addr & ~0xfffULL; |
8bf5b6a9 PM |
3294 | if (!attrs.secure) { |
3295 | par64 |= (1 << 9); /* NS */ | |
3296 | } | |
5b2d261d AB |
3297 | par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */ |
3298 | par64 |= cacheattrs.shareability << 7; /* SH */ | |
4a501606 | 3299 | } else { |
5efe9ed4 PM |
3300 | uint32_t fsr = arm_fi_to_lfsc(&fi); |
3301 | ||
702a9357 | 3302 | par64 |= 1; /* F */ |
b7cc4e82 | 3303 | par64 |= (fsr & 0x3f) << 1; /* FS */ |
0f7b791b PM |
3304 | if (fi.stage2) { |
3305 | par64 |= (1 << 9); /* S */ | |
3306 | } | |
3307 | if (fi.s1ptw) { | |
3308 | par64 |= (1 << 8); /* PTW */ | |
3309 | } | |
4a501606 PM |
3310 | } |
3311 | } else { | |
b7cc4e82 | 3312 | /* fsr is a DFSR/IFSR value for the short descriptor |
702a9357 PM |
3313 | * translation table format (with WnR always clear). |
3314 | * Convert it to a 32-bit PAR. | |
3315 | */ | |
b7cc4e82 | 3316 | if (!ret) { |
702a9357 PM |
3317 | /* We do not set any attribute bits in the PAR */ |
3318 | if (page_size == (1 << 24) | |
3319 | && arm_feature(env, ARM_FEATURE_V7)) { | |
01c097f7 | 3320 | par64 = (phys_addr & 0xff000000) | (1 << 1); |
702a9357 | 3321 | } else { |
01c097f7 | 3322 | par64 = phys_addr & 0xfffff000; |
702a9357 | 3323 | } |
8bf5b6a9 PM |
3324 | if (!attrs.secure) { |
3325 | par64 |= (1 << 9); /* NS */ | |
3326 | } | |
702a9357 | 3327 | } else { |
5efe9ed4 PM |
3328 | uint32_t fsr = arm_fi_to_sfsc(&fi); |
3329 | ||
b7cc4e82 PC |
3330 | par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | |
3331 | ((fsr & 0xf) << 1) | 1; | |
702a9357 | 3332 | } |
4a501606 | 3333 | } |
060e8a48 PM |
3334 | return par64; |
3335 | } | |
9fb005b0 | 3336 | #endif /* CONFIG_TCG */ |
060e8a48 PM |
3337 | |
3338 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | |
3339 | { | |
9fb005b0 | 3340 | #ifdef CONFIG_TCG |
03ae85f8 | 3341 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
060e8a48 | 3342 | uint64_t par64; |
d3649702 PM |
3343 | ARMMMUIdx mmu_idx; |
3344 | int el = arm_current_el(env); | |
3345 | bool secure = arm_is_secure_below_el3(env); | |
060e8a48 | 3346 | |
d3649702 PM |
3347 | switch (ri->opc2 & 6) { |
3348 | case 0: | |
04b07d29 | 3349 | /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */ |
d3649702 PM |
3350 | switch (el) { |
3351 | case 3: | |
127b2b08 | 3352 | mmu_idx = ARMMMUIdx_SE3; |
d3649702 PM |
3353 | break; |
3354 | case 2: | |
b6ad6062 | 3355 | g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ |
04b07d29 | 3356 | /* fall through */ |
d3649702 | 3357 | case 1: |
04b07d29 | 3358 | if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) { |
b1a10c86 | 3359 | mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN |
04b07d29 RH |
3360 | : ARMMMUIdx_Stage1_E1_PAN); |
3361 | } else { | |
b1a10c86 | 3362 | mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1; |
04b07d29 | 3363 | } |
d3649702 PM |
3364 | break; |
3365 | default: | |
3366 | g_assert_not_reached(); | |
3367 | } | |
3368 | break; | |
3369 | case 2: | |
3370 | /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ | |
3371 | switch (el) { | |
3372 | case 3: | |
fba37aed | 3373 | mmu_idx = ARMMMUIdx_SE10_0; |
d3649702 PM |
3374 | break; |
3375 | case 2: | |
b1a10c86 | 3376 | g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ |
2859d7b5 | 3377 | mmu_idx = ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3378 | break; |
3379 | case 1: | |
b1a10c86 | 3380 | mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3381 | break; |
3382 | default: | |
3383 | g_assert_not_reached(); | |
3384 | } | |
3385 | break; | |
3386 | case 4: | |
3387 | /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ | |
01b98b68 | 3388 | mmu_idx = ARMMMUIdx_E10_1; |
d3649702 PM |
3389 | break; |
3390 | case 6: | |
3391 | /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ | |
01b98b68 | 3392 | mmu_idx = ARMMMUIdx_E10_0; |
d3649702 PM |
3393 | break; |
3394 | default: | |
3395 | g_assert_not_reached(); | |
3396 | } | |
3397 | ||
3398 | par64 = do_ats_write(env, value, access_type, mmu_idx); | |
01c097f7 FA |
3399 | |
3400 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
9fb005b0 PMD |
3401 | #else |
3402 | /* Handled by hardware accelerator. */ | |
3403 | g_assert_not_reached(); | |
3404 | #endif /* CONFIG_TCG */ | |
4a501606 | 3405 | } |
060e8a48 | 3406 | |
14db7fe0 PM |
3407 | static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3408 | uint64_t value) | |
3409 | { | |
9fb005b0 | 3410 | #ifdef CONFIG_TCG |
03ae85f8 | 3411 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
14db7fe0 PM |
3412 | uint64_t par64; |
3413 | ||
e013b741 | 3414 | par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2); |
14db7fe0 PM |
3415 | |
3416 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
9fb005b0 PMD |
3417 | #else |
3418 | /* Handled by hardware accelerator. */ | |
3419 | g_assert_not_reached(); | |
3420 | #endif /* CONFIG_TCG */ | |
14db7fe0 PM |
3421 | } |
3422 | ||
3f208fd7 PM |
3423 | static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3424 | bool isread) | |
2a47df95 | 3425 | { |
926c1b97 RDC |
3426 | if (arm_current_el(env) == 3 && |
3427 | !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) { | |
2a47df95 PM |
3428 | return CP_ACCESS_TRAP; |
3429 | } | |
3430 | return CP_ACCESS_OK; | |
3431 | } | |
3432 | ||
060e8a48 PM |
3433 | static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, |
3434 | uint64_t value) | |
3435 | { | |
9fb005b0 | 3436 | #ifdef CONFIG_TCG |
03ae85f8 | 3437 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
d3649702 PM |
3438 | ARMMMUIdx mmu_idx; |
3439 | int secure = arm_is_secure_below_el3(env); | |
3440 | ||
3441 | switch (ri->opc2 & 6) { | |
3442 | case 0: | |
3443 | switch (ri->opc1) { | |
04b07d29 RH |
3444 | case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ |
3445 | if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) { | |
b1a10c86 | 3446 | mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN |
04b07d29 RH |
3447 | : ARMMMUIdx_Stage1_E1_PAN); |
3448 | } else { | |
b1a10c86 | 3449 | mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1; |
04b07d29 | 3450 | } |
d3649702 PM |
3451 | break; |
3452 | case 4: /* AT S1E2R, AT S1E2W */ | |
b6ad6062 | 3453 | mmu_idx = secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2; |
d3649702 PM |
3454 | break; |
3455 | case 6: /* AT S1E3R, AT S1E3W */ | |
127b2b08 | 3456 | mmu_idx = ARMMMUIdx_SE3; |
d3649702 PM |
3457 | break; |
3458 | default: | |
3459 | g_assert_not_reached(); | |
3460 | } | |
3461 | break; | |
3462 | case 2: /* AT S1E0R, AT S1E0W */ | |
b1a10c86 | 3463 | mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3464 | break; |
3465 | case 4: /* AT S12E1R, AT S12E1W */ | |
fba37aed | 3466 | mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1; |
d3649702 PM |
3467 | break; |
3468 | case 6: /* AT S12E0R, AT S12E0W */ | |
fba37aed | 3469 | mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0; |
d3649702 PM |
3470 | break; |
3471 | default: | |
3472 | g_assert_not_reached(); | |
3473 | } | |
060e8a48 | 3474 | |
d3649702 | 3475 | env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); |
9fb005b0 PMD |
3476 | #else |
3477 | /* Handled by hardware accelerator. */ | |
3478 | g_assert_not_reached(); | |
3479 | #endif /* CONFIG_TCG */ | |
060e8a48 | 3480 | } |
4a501606 PM |
3481 | #endif |
3482 | ||
3483 | static const ARMCPRegInfo vapa_cp_reginfo[] = { | |
3484 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, | |
3485 | .access = PL1_RW, .resetvalue = 0, | |
01c097f7 FA |
3486 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), |
3487 | offsetoflow32(CPUARMState, cp15.par_ns) }, | |
4a501606 PM |
3488 | .writefn = par_write }, |
3489 | #ifndef CONFIG_USER_ONLY | |
87562e4f | 3490 | /* This underdecoding is safe because the reginfo is NO_RAW. */ |
4a501606 | 3491 | { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, |
92611c00 | 3492 | .access = PL1_W, .accessfn = ats_access, |
0710b2fa | 3493 | .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
4a501606 | 3494 | #endif |
4a501606 PM |
3495 | }; |
3496 | ||
18032bec PM |
3497 | /* Return basic MPU access permission bits. */ |
3498 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
3499 | { | |
3500 | uint32_t ret; | |
3501 | uint32_t mask; | |
3502 | int i; | |
3503 | ret = 0; | |
3504 | mask = 3; | |
3505 | for (i = 0; i < 16; i += 2) { | |
3506 | ret |= (val >> i) & mask; | |
3507 | mask <<= 2; | |
3508 | } | |
3509 | return ret; | |
3510 | } | |
3511 | ||
3512 | /* Pad basic MPU access permission bits to extended format. */ | |
3513 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
3514 | { | |
3515 | uint32_t ret; | |
3516 | uint32_t mask; | |
3517 | int i; | |
3518 | ret = 0; | |
3519 | mask = 3; | |
3520 | for (i = 0; i < 16; i += 2) { | |
3521 | ret |= (val & mask) << i; | |
3522 | mask <<= 2; | |
3523 | } | |
3524 | return ret; | |
3525 | } | |
3526 | ||
c4241c7d PM |
3527 | static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3528 | uint64_t value) | |
18032bec | 3529 | { |
7e09797c | 3530 | env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3531 | } |
3532 | ||
c4241c7d | 3533 | static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3534 | { |
7e09797c | 3535 | return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); |
18032bec PM |
3536 | } |
3537 | ||
c4241c7d PM |
3538 | static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3539 | uint64_t value) | |
18032bec | 3540 | { |
7e09797c | 3541 | env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3542 | } |
3543 | ||
c4241c7d | 3544 | static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3545 | { |
7e09797c | 3546 | return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); |
18032bec PM |
3547 | } |
3548 | ||
6cb0b013 PC |
3549 | static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) |
3550 | { | |
3551 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); | |
3552 | ||
3553 | if (!u32p) { | |
3554 | return 0; | |
3555 | } | |
3556 | ||
1bc04a88 | 3557 | u32p += env->pmsav7.rnr[M_REG_NS]; |
6cb0b013 PC |
3558 | return *u32p; |
3559 | } | |
3560 | ||
3561 | static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3562 | uint64_t value) | |
3563 | { | |
2fc0cc0e | 3564 | ARMCPU *cpu = env_archcpu(env); |
6cb0b013 PC |
3565 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); |
3566 | ||
3567 | if (!u32p) { | |
3568 | return; | |
3569 | } | |
3570 | ||
1bc04a88 | 3571 | u32p += env->pmsav7.rnr[M_REG_NS]; |
d10eb08f | 3572 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ |
6cb0b013 PC |
3573 | *u32p = value; |
3574 | } | |
3575 | ||
6cb0b013 PC |
3576 | static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3577 | uint64_t value) | |
3578 | { | |
2fc0cc0e | 3579 | ARMCPU *cpu = env_archcpu(env); |
6cb0b013 PC |
3580 | uint32_t nrgs = cpu->pmsav7_dregion; |
3581 | ||
3582 | if (value >= nrgs) { | |
3583 | qemu_log_mask(LOG_GUEST_ERROR, | |
3584 | "PMSAv7 RGNR write >= # supported regions, %" PRIu32 | |
3585 | " > %" PRIu32 "\n", (uint32_t)value, nrgs); | |
3586 | return; | |
3587 | } | |
3588 | ||
3589 | raw_write(env, ri, value); | |
3590 | } | |
3591 | ||
3592 | static const ARMCPRegInfo pmsav7_cp_reginfo[] = { | |
69ceea64 PM |
3593 | /* Reset for all these registers is handled in arm_cpu_reset(), |
3594 | * because the PMSAv7 is also used by M-profile CPUs, which do | |
3595 | * not register cpregs but still need the state to be reset. | |
3596 | */ | |
6cb0b013 PC |
3597 | { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, |
3598 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3599 | .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), | |
69ceea64 PM |
3600 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3601 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3602 | { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, |
3603 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3604 | .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), | |
69ceea64 PM |
3605 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3606 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3607 | { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, |
3608 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3609 | .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), | |
69ceea64 PM |
3610 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3611 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3612 | { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, |
3613 | .access = PL1_RW, | |
1bc04a88 | 3614 | .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), |
69ceea64 PM |
3615 | .writefn = pmsav7_rgnr_write, |
3616 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3617 | }; |
3618 | ||
18032bec PM |
3619 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { |
3620 | { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 3621 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 3622 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
18032bec PM |
3623 | .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, |
3624 | { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 3625 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 3626 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
18032bec PM |
3627 | .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, |
3628 | { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, | |
3629 | .access = PL1_RW, | |
7e09797c PM |
3630 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
3631 | .resetvalue = 0, }, | |
18032bec PM |
3632 | { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, |
3633 | .access = PL1_RW, | |
7e09797c PM |
3634 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
3635 | .resetvalue = 0, }, | |
ecce5c3c PM |
3636 | { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
3637 | .access = PL1_RW, | |
3638 | .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, | |
3639 | { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
3640 | .access = PL1_RW, | |
3641 | .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, | |
06d76f31 | 3642 | /* Protection region base and size registers */ |
e508a92b PM |
3643 | { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, |
3644 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3645 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, | |
3646 | { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, | |
3647 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3648 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, | |
3649 | { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, | |
3650 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3651 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, | |
3652 | { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, | |
3653 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3654 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, | |
3655 | { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, | |
3656 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3657 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, | |
3658 | { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, | |
3659 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3660 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, | |
3661 | { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, | |
3662 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3663 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, | |
3664 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | |
3665 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3666 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | |
18032bec PM |
3667 | }; |
3668 | ||
c4241c7d PM |
3669 | static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3670 | uint64_t value) | |
ecce5c3c | 3671 | { |
11f136ee | 3672 | TCR *tcr = raw_ptr(env, ri); |
2ebcebe2 PM |
3673 | int maskshift = extract32(value, 0, 3); |
3674 | ||
e389be16 FA |
3675 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
3676 | if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { | |
3677 | /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when | |
3678 | * using Long-desciptor translation table format */ | |
3679 | value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); | |
3680 | } else if (arm_feature(env, ARM_FEATURE_EL3)) { | |
3681 | /* In an implementation that includes the Security Extensions | |
3682 | * TTBCR has additional fields PD0 [4] and PD1 [5] for | |
3683 | * Short-descriptor translation table format. | |
3684 | */ | |
3685 | value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; | |
3686 | } else { | |
3687 | value &= TTBCR_N; | |
3688 | } | |
e42c4db3 | 3689 | } |
e389be16 | 3690 | |
b6af0975 | 3691 | /* Update the masks corresponding to the TCR bank being written |
11f136ee | 3692 | * Note that we always calculate mask and base_mask, but |
e42c4db3 | 3693 | * they are only used for short-descriptor tables (ie if EAE is 0); |
11f136ee FA |
3694 | * for long-descriptor tables the TCR fields are used differently |
3695 | * and the mask and base_mask values are meaningless. | |
e42c4db3 | 3696 | */ |
11f136ee FA |
3697 | tcr->raw_tcr = value; |
3698 | tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift); | |
3699 | tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift); | |
ecce5c3c PM |
3700 | } |
3701 | ||
c4241c7d PM |
3702 | static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3703 | uint64_t value) | |
d4e6df63 | 3704 | { |
2fc0cc0e | 3705 | ARMCPU *cpu = env_archcpu(env); |
ab638a32 | 3706 | TCR *tcr = raw_ptr(env, ri); |
00c8cb0a | 3707 | |
d4e6df63 PM |
3708 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
3709 | /* With LPAE the TTBCR could result in a change of ASID | |
3710 | * via the TTBCR.A1 bit, so do a TLB flush. | |
3711 | */ | |
d10eb08f | 3712 | tlb_flush(CPU(cpu)); |
d4e6df63 | 3713 | } |
ab638a32 RH |
3714 | /* Preserve the high half of TCR_EL1, set via TTBCR2. */ |
3715 | value = deposit64(tcr->raw_tcr, 0, 32, value); | |
c4241c7d | 3716 | vmsa_ttbcr_raw_write(env, ri, value); |
d4e6df63 PM |
3717 | } |
3718 | ||
ecce5c3c PM |
3719 | static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
3720 | { | |
11f136ee FA |
3721 | TCR *tcr = raw_ptr(env, ri); |
3722 | ||
3723 | /* Reset both the TCR as well as the masks corresponding to the bank of | |
3724 | * the TCR being reset. | |
3725 | */ | |
3726 | tcr->raw_tcr = 0; | |
3727 | tcr->mask = 0; | |
3728 | tcr->base_mask = 0xffffc000u; | |
ecce5c3c PM |
3729 | } |
3730 | ||
d06dc933 | 3731 | static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, |
cb2e37df PM |
3732 | uint64_t value) |
3733 | { | |
2fc0cc0e | 3734 | ARMCPU *cpu = env_archcpu(env); |
11f136ee | 3735 | TCR *tcr = raw_ptr(env, ri); |
00c8cb0a | 3736 | |
cb2e37df | 3737 | /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ |
d10eb08f | 3738 | tlb_flush(CPU(cpu)); |
11f136ee | 3739 | tcr->raw_tcr = value; |
cb2e37df PM |
3740 | } |
3741 | ||
327ed10f PM |
3742 | static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3743 | uint64_t value) | |
3744 | { | |
93f379b0 RH |
3745 | /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ |
3746 | if (cpreg_field_is_64bit(ri) && | |
3747 | extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { | |
2fc0cc0e | 3748 | ARMCPU *cpu = env_archcpu(env); |
d10eb08f | 3749 | tlb_flush(CPU(cpu)); |
327ed10f PM |
3750 | } |
3751 | raw_write(env, ri, value); | |
3752 | } | |
3753 | ||
ed30da8e RH |
3754 | static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3755 | uint64_t value) | |
3756 | { | |
d06dc933 RH |
3757 | /* |
3758 | * If we are running with E2&0 regime, then an ASID is active. | |
3759 | * Flush if that might be changing. Note we're not checking | |
3760 | * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that | |
3761 | * holds the active ASID, only checking the field that might. | |
3762 | */ | |
3763 | if (extract64(raw_read(env, ri) ^ value, 48, 16) && | |
3764 | (arm_hcr_el2_eff(env) & HCR_E2H)) { | |
b6ad6062 RDC |
3765 | uint16_t mask = ARMMMUIdxBit_E20_2 | |
3766 | ARMMMUIdxBit_E20_2_PAN | | |
3767 | ARMMMUIdxBit_E20_0; | |
3768 | ||
3769 | if (arm_is_secure_below_el3(env)) { | |
3770 | mask >>= ARM_MMU_IDX_A_NS; | |
3771 | } | |
3772 | ||
3773 | tlb_flush_by_mmuidx(env_cpu(env), mask); | |
d06dc933 | 3774 | } |
ed30da8e RH |
3775 | raw_write(env, ri, value); |
3776 | } | |
3777 | ||
b698e9cf EI |
3778 | static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3779 | uint64_t value) | |
3780 | { | |
2fc0cc0e | 3781 | ARMCPU *cpu = env_archcpu(env); |
b698e9cf EI |
3782 | CPUState *cs = CPU(cpu); |
3783 | ||
97fa9350 RH |
3784 | /* |
3785 | * A change in VMID to the stage2 page table (Stage2) invalidates | |
3786 | * the combined stage 1&2 tlbs (EL10_1 and EL10_0). | |
3787 | */ | |
b698e9cf | 3788 | if (raw_read(env, ri) != value) { |
c4f060e8 RDC |
3789 | uint16_t mask = ARMMMUIdxBit_E10_1 | |
3790 | ARMMMUIdxBit_E10_1_PAN | | |
3791 | ARMMMUIdxBit_E10_0; | |
3792 | ||
3793 | if (arm_is_secure_below_el3(env)) { | |
3794 | mask >>= ARM_MMU_IDX_A_NS; | |
3795 | } | |
3796 | ||
3797 | tlb_flush_by_mmuidx(cs, mask); | |
b698e9cf EI |
3798 | raw_write(env, ri, value); |
3799 | } | |
3800 | } | |
3801 | ||
8e5d75c9 | 3802 | static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { |
18032bec | 3803 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, |
84929218 | 3804 | .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS, |
4a7e2d73 | 3805 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), |
b061a82b | 3806 | offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, |
18032bec | 3807 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, |
84929218 | 3808 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
88ca1c2d FA |
3809 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), |
3810 | offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, | |
8e5d75c9 | 3811 | { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, |
84929218 | 3812 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
8e5d75c9 PC |
3813 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), |
3814 | offsetof(CPUARMState, cp15.dfar_ns) } }, | |
3815 | { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, | |
3816 | .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, | |
84929218 RH |
3817 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3818 | .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), | |
8e5d75c9 | 3819 | .resetvalue = 0, }, |
8e5d75c9 PC |
3820 | }; |
3821 | ||
3822 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { | |
6cd8a264 RH |
3823 | { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, |
3824 | .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, | |
84929218 | 3825 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
d81c519c | 3826 | .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, |
327ed10f | 3827 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af | 3828 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, |
84929218 RH |
3829 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3830 | .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
7dd8c9af FA |
3831 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
3832 | offsetof(CPUARMState, cp15.ttbr0_ns) } }, | |
327ed10f | 3833 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af | 3834 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, |
84929218 RH |
3835 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3836 | .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
7dd8c9af FA |
3837 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
3838 | offsetof(CPUARMState, cp15.ttbr1_ns) } }, | |
cb2e37df PM |
3839 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, |
3840 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | |
84929218 RH |
3841 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3842 | .writefn = vmsa_tcr_el12_write, | |
cb2e37df | 3843 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, |
11f136ee | 3844 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, |
cb2e37df | 3845 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
84929218 RH |
3846 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3847 | .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, | |
b061a82b | 3848 | .raw_writefn = vmsa_ttbcr_raw_write, |
d102058e RH |
3849 | /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */ |
3850 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]), | |
3851 | offsetof(CPUARMState, cp15.tcr_el[1])} }, | |
18032bec PM |
3852 | }; |
3853 | ||
ab638a32 RH |
3854 | /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing |
3855 | * qemu tlbs nor adjusting cached masks. | |
3856 | */ | |
3857 | static const ARMCPRegInfo ttbcr2_reginfo = { | |
3858 | .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3, | |
84929218 RH |
3859 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
3860 | .type = ARM_CP_ALIAS, | |
d102058e RH |
3861 | .bank_fieldoffsets = { |
3862 | offsetofhigh32(CPUARMState, cp15.tcr_el[3].raw_tcr), | |
3863 | offsetofhigh32(CPUARMState, cp15.tcr_el[1].raw_tcr), | |
3864 | }, | |
ab638a32 RH |
3865 | }; |
3866 | ||
c4241c7d PM |
3867 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3868 | uint64_t value) | |
1047b9d7 PM |
3869 | { |
3870 | env->cp15.c15_ticonfig = value & 0xe7; | |
3871 | /* The OS_TYPE bit in this register changes the reported CPUID! */ | |
3872 | env->cp15.c0_cpuid = (value & (1 << 5)) ? | |
3873 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1047b9d7 PM |
3874 | } |
3875 | ||
c4241c7d PM |
3876 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3877 | uint64_t value) | |
1047b9d7 PM |
3878 | { |
3879 | env->cp15.c15_threadid = value & 0xffff; | |
1047b9d7 PM |
3880 | } |
3881 | ||
c4241c7d PM |
3882 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3883 | uint64_t value) | |
1047b9d7 PM |
3884 | { |
3885 | /* Wait-for-interrupt (deprecated) */ | |
2fc0cc0e | 3886 | cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); |
1047b9d7 PM |
3887 | } |
3888 | ||
c4241c7d PM |
3889 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3890 | uint64_t value) | |
c4804214 PM |
3891 | { |
3892 | /* On OMAP there are registers indicating the max/min index of dcache lines | |
3893 | * containing a dirty line; cache flush operations have to reset these. | |
3894 | */ | |
3895 | env->cp15.c15_i_max = 0x000; | |
3896 | env->cp15.c15_i_min = 0xff0; | |
c4804214 PM |
3897 | } |
3898 | ||
18032bec PM |
3899 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
3900 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, | |
3901 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, | |
d81c519c | 3902 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 3903 | .resetvalue = 0, }, |
1047b9d7 PM |
3904 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
3905 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
3906 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
3907 | .access = PL1_RW, | |
3908 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, | |
3909 | .writefn = omap_ticonfig_write }, | |
3910 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, | |
3911 | .access = PL1_RW, | |
3912 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, | |
3913 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, | |
3914 | .access = PL1_RW, .resetvalue = 0xff0, | |
3915 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, | |
3916 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, | |
3917 | .access = PL1_RW, | |
3918 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, | |
3919 | .writefn = omap_threadid_write }, | |
3920 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, | |
3921 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
7a0e58fa | 3922 | .type = ARM_CP_NO_RAW, |
1047b9d7 PM |
3923 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
3924 | /* TODO: Peripheral port remap register: | |
3925 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller | |
3926 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), | |
3927 | * when MMU is off. | |
3928 | */ | |
c4804214 | 3929 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
d4e6df63 | 3930 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
7a0e58fa | 3931 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, |
c4804214 | 3932 | .writefn = omap_cachemaint_write }, |
34f90529 PM |
3933 | { .name = "C9", .cp = 15, .crn = 9, |
3934 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | |
3935 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | |
1047b9d7 PM |
3936 | }; |
3937 | ||
c4241c7d PM |
3938 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3939 | uint64_t value) | |
1047b9d7 | 3940 | { |
c0f4af17 | 3941 | env->cp15.c15_cpar = value & 0x3fff; |
1047b9d7 PM |
3942 | } |
3943 | ||
3944 | static const ARMCPRegInfo xscale_cp_reginfo[] = { | |
3945 | { .name = "XSCALE_CPAR", | |
3946 | .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
3947 | .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, | |
3948 | .writefn = xscale_cpar_write, }, | |
2771db27 PM |
3949 | { .name = "XSCALE_AUXCR", |
3950 | .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, | |
3951 | .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), | |
3952 | .resetvalue = 0, }, | |
3b771579 PM |
3953 | /* XScale specific cache-lockdown: since we have no cache we NOP these |
3954 | * and hope the guest does not really rely on cache behaviour. | |
3955 | */ | |
3956 | { .name = "XSCALE_LOCK_ICACHE_LINE", | |
3957 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
3958 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3959 | { .name = "XSCALE_UNLOCK_ICACHE", | |
3960 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
3961 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3962 | { .name = "XSCALE_DCACHE_LOCK", | |
3963 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, | |
3964 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
3965 | { .name = "XSCALE_UNLOCK_DCACHE", | |
3966 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, | |
3967 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1047b9d7 PM |
3968 | }; |
3969 | ||
3970 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | |
3971 | /* RAZ/WI the whole crn=15 space, when we don't have a more specific | |
3972 | * implementation of this implementation-defined space. | |
3973 | * Ideally this should eventually disappear in favour of actually | |
3974 | * implementing the correct behaviour for all cores. | |
3975 | */ | |
3976 | { .name = "C15_IMPDEF", .cp = 15, .crn = 15, | |
3977 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
3671cd87 | 3978 | .access = PL1_RW, |
7a0e58fa | 3979 | .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, |
d4e6df63 | 3980 | .resetvalue = 0 }, |
18032bec PM |
3981 | }; |
3982 | ||
c4804214 PM |
3983 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
3984 | /* Cache status: RAZ because we have no cache so it's always clean */ | |
3985 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | |
7a0e58fa | 3986 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 3987 | .resetvalue = 0 }, |
c4804214 PM |
3988 | }; |
3989 | ||
3990 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | |
3991 | /* We never have a a block transfer operation in progress */ | |
3992 | { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, | |
7a0e58fa | 3993 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 3994 | .resetvalue = 0 }, |
30b05bba PM |
3995 | /* The cache ops themselves: these all NOP for QEMU */ |
3996 | { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, | |
3997 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3998 | { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, | |
3999 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
4000 | { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, | |
4001 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
4002 | { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, | |
4003 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
4004 | { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, | |
4005 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
4006 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, | |
4007 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
c4804214 PM |
4008 | }; |
4009 | ||
4010 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | |
4011 | /* The cache test-and-clean instructions always return (1 << 30) | |
4012 | * to indicate that there are no dirty cache lines. | |
4013 | */ | |
4014 | { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, | |
7a0e58fa | 4015 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4016 | .resetvalue = (1 << 30) }, |
c4804214 | 4017 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
7a0e58fa | 4018 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4019 | .resetvalue = (1 << 30) }, |
c4804214 PM |
4020 | }; |
4021 | ||
34f90529 PM |
4022 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
4023 | /* Ignore ReadBuffer accesses */ | |
4024 | { .name = "C9_READBUFFER", .cp = 15, .crn = 9, | |
4025 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
d4e6df63 | 4026 | .access = PL1_RW, .resetvalue = 0, |
7a0e58fa | 4027 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, |
34f90529 PM |
4028 | }; |
4029 | ||
731de9e6 EI |
4030 | static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4031 | { | |
731de9e6 | 4032 | unsigned int cur_el = arm_current_el(env); |
731de9e6 | 4033 | |
e6ef0169 | 4034 | if (arm_is_el2_enabled(env) && cur_el == 1) { |
731de9e6 EI |
4035 | return env->cp15.vpidr_el2; |
4036 | } | |
4037 | return raw_read(env, ri); | |
4038 | } | |
4039 | ||
06a7e647 | 4040 | static uint64_t mpidr_read_val(CPUARMState *env) |
81bdde9d | 4041 | { |
2fc0cc0e | 4042 | ARMCPU *cpu = env_archcpu(env); |
eb5e1d3c PF |
4043 | uint64_t mpidr = cpu->mp_affinity; |
4044 | ||
81bdde9d | 4045 | if (arm_feature(env, ARM_FEATURE_V7MP)) { |
78dbbbe4 | 4046 | mpidr |= (1U << 31); |
81bdde9d PM |
4047 | /* Cores which are uniprocessor (non-coherent) |
4048 | * but still implement the MP extensions set | |
a8e81b31 | 4049 | * bit 30. (For instance, Cortex-R5). |
81bdde9d | 4050 | */ |
a8e81b31 PC |
4051 | if (cpu->mp_is_up) { |
4052 | mpidr |= (1u << 30); | |
4053 | } | |
81bdde9d | 4054 | } |
c4241c7d | 4055 | return mpidr; |
81bdde9d PM |
4056 | } |
4057 | ||
06a7e647 EI |
4058 | static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4059 | { | |
f0d574d6 | 4060 | unsigned int cur_el = arm_current_el(env); |
f0d574d6 | 4061 | |
e6ef0169 | 4062 | if (arm_is_el2_enabled(env) && cur_el == 1) { |
f0d574d6 EI |
4063 | return env->cp15.vmpidr_el2; |
4064 | } | |
06a7e647 EI |
4065 | return mpidr_read_val(env); |
4066 | } | |
4067 | ||
7ac681cf | 4068 | static const ARMCPRegInfo lpae_cp_reginfo[] = { |
a903c449 | 4069 | /* NOP AMAIR0/1 */ |
b0fe2427 PM |
4070 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, |
4071 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | |
84929218 RH |
4072 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4073 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b0fe2427 | 4074 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ |
7ac681cf | 4075 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
84929218 RH |
4076 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4077 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
891a2fe7 | 4078 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
01c097f7 FA |
4079 | .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, |
4080 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), | |
4081 | offsetof(CPUARMState, cp15.par_ns)} }, | |
891a2fe7 | 4082 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, |
84929218 RH |
4083 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4084 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
7dd8c9af FA |
4085 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
4086 | offsetof(CPUARMState, cp15.ttbr0_ns) }, | |
b061a82b | 4087 | .writefn = vmsa_ttbr_write, }, |
891a2fe7 | 4088 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
84929218 RH |
4089 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4090 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
7dd8c9af FA |
4091 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
4092 | offsetof(CPUARMState, cp15.ttbr1_ns) }, | |
b061a82b | 4093 | .writefn = vmsa_ttbr_write, }, |
7ac681cf PM |
4094 | }; |
4095 | ||
c4241c7d | 4096 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 4097 | { |
c4241c7d | 4098 | return vfp_get_fpcr(env); |
b0d2b7d0 PM |
4099 | } |
4100 | ||
c4241c7d PM |
4101 | static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4102 | uint64_t value) | |
b0d2b7d0 PM |
4103 | { |
4104 | vfp_set_fpcr(env, value); | |
b0d2b7d0 PM |
4105 | } |
4106 | ||
c4241c7d | 4107 | static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 4108 | { |
c4241c7d | 4109 | return vfp_get_fpsr(env); |
b0d2b7d0 PM |
4110 | } |
4111 | ||
c4241c7d PM |
4112 | static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4113 | uint64_t value) | |
b0d2b7d0 PM |
4114 | { |
4115 | vfp_set_fpsr(env, value); | |
b0d2b7d0 PM |
4116 | } |
4117 | ||
3f208fd7 PM |
4118 | static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4119 | bool isread) | |
c2b820fe | 4120 | { |
aaec1432 | 4121 | if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { |
c2b820fe PM |
4122 | return CP_ACCESS_TRAP; |
4123 | } | |
4124 | return CP_ACCESS_OK; | |
4125 | } | |
4126 | ||
4127 | static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4128 | uint64_t value) | |
4129 | { | |
4130 | env->daif = value & PSTATE_DAIF; | |
4131 | } | |
4132 | ||
220f508f RH |
4133 | static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4134 | { | |
4135 | return env->pstate & PSTATE_PAN; | |
4136 | } | |
4137 | ||
4138 | static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4139 | uint64_t value) | |
4140 | { | |
4141 | env->pstate = (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN); | |
4142 | } | |
4143 | ||
4144 | static const ARMCPRegInfo pan_reginfo = { | |
4145 | .name = "PAN", .state = ARM_CP_STATE_AA64, | |
4146 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 3, | |
4147 | .type = ARM_CP_NO_RAW, .access = PL1_RW, | |
4148 | .readfn = aa64_pan_read, .writefn = aa64_pan_write | |
4149 | }; | |
4150 | ||
9eeb7a1c RH |
4151 | static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4152 | { | |
4153 | return env->pstate & PSTATE_UAO; | |
4154 | } | |
4155 | ||
4156 | static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4157 | uint64_t value) | |
4158 | { | |
4159 | env->pstate = (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO); | |
4160 | } | |
4161 | ||
4162 | static const ARMCPRegInfo uao_reginfo = { | |
4163 | .name = "UAO", .state = ARM_CP_STATE_AA64, | |
4164 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4, | |
4165 | .type = ARM_CP_NO_RAW, .access = PL1_RW, | |
4166 | .readfn = aa64_uao_read, .writefn = aa64_uao_write | |
4167 | }; | |
4168 | ||
dc8b1853 RC |
4169 | static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4170 | { | |
4171 | return env->pstate & PSTATE_DIT; | |
4172 | } | |
4173 | ||
4174 | static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4175 | uint64_t value) | |
4176 | { | |
4177 | env->pstate = (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT); | |
4178 | } | |
4179 | ||
4180 | static const ARMCPRegInfo dit_reginfo = { | |
4181 | .name = "DIT", .state = ARM_CP_STATE_AA64, | |
4182 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 5, | |
4183 | .type = ARM_CP_NO_RAW, .access = PL0_RW, | |
4184 | .readfn = aa64_dit_read, .writefn = aa64_dit_write | |
4185 | }; | |
4186 | ||
f2f68a78 RC |
4187 | static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4188 | { | |
4189 | return env->pstate & PSTATE_SSBS; | |
4190 | } | |
4191 | ||
4192 | static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4193 | uint64_t value) | |
4194 | { | |
4195 | env->pstate = (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS); | |
4196 | } | |
4197 | ||
4198 | static const ARMCPRegInfo ssbs_reginfo = { | |
4199 | .name = "SSBS", .state = ARM_CP_STATE_AA64, | |
4200 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 6, | |
4201 | .type = ARM_CP_NO_RAW, .access = PL0_RW, | |
4202 | .readfn = aa64_ssbs_read, .writefn = aa64_ssbs_write | |
4203 | }; | |
4204 | ||
38262d8a RH |
4205 | static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, |
4206 | const ARMCPRegInfo *ri, | |
4207 | bool isread) | |
8af35c37 | 4208 | { |
38262d8a RH |
4209 | /* Cache invalidate/clean to Point of Coherency or Persistence... */ |
4210 | switch (arm_current_el(env)) { | |
4211 | case 0: | |
4212 | /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ | |
4213 | if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { | |
4214 | return CP_ACCESS_TRAP; | |
4215 | } | |
4216 | /* fall through */ | |
4217 | case 1: | |
4218 | /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */ | |
4219 | if (arm_hcr_el2_eff(env) & HCR_TPCP) { | |
4220 | return CP_ACCESS_TRAP_EL2; | |
4221 | } | |
4222 | break; | |
8af35c37 PM |
4223 | } |
4224 | return CP_ACCESS_OK; | |
4225 | } | |
4226 | ||
38262d8a | 4227 | static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, |
1bed4d2e RH |
4228 | const ARMCPRegInfo *ri, |
4229 | bool isread) | |
4230 | { | |
38262d8a | 4231 | /* Cache invalidate/clean to Point of Unification... */ |
1bed4d2e RH |
4232 | switch (arm_current_el(env)) { |
4233 | case 0: | |
4234 | /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ | |
4235 | if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { | |
4236 | return CP_ACCESS_TRAP; | |
4237 | } | |
4238 | /* fall through */ | |
4239 | case 1: | |
38262d8a RH |
4240 | /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */ |
4241 | if (arm_hcr_el2_eff(env) & HCR_TPU) { | |
1bed4d2e RH |
4242 | return CP_ACCESS_TRAP_EL2; |
4243 | } | |
4244 | break; | |
4245 | } | |
4246 | return CP_ACCESS_OK; | |
4247 | } | |
4248 | ||
dbb1fb27 AB |
4249 | /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions |
4250 | * Page D4-1736 (DDI0487A.b) | |
4251 | */ | |
4252 | ||
b7e0730d RH |
4253 | static int vae1_tlbmask(CPUARMState *env) |
4254 | { | |
e04a5752 | 4255 | uint64_t hcr = arm_hcr_el2_eff(env); |
bc944d3a | 4256 | uint16_t mask; |
e04a5752 RDC |
4257 | |
4258 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
bc944d3a RDC |
4259 | mask = ARMMMUIdxBit_E20_2 | |
4260 | ARMMMUIdxBit_E20_2_PAN | | |
4261 | ARMMMUIdxBit_E20_0; | |
b7e0730d | 4262 | } else { |
bc944d3a | 4263 | mask = ARMMMUIdxBit_E10_1 | |
452ef8cb RH |
4264 | ARMMMUIdxBit_E10_1_PAN | |
4265 | ARMMMUIdxBit_E10_0; | |
b7e0730d | 4266 | } |
bc944d3a RDC |
4267 | |
4268 | if (arm_is_secure_below_el3(env)) { | |
4269 | mask >>= ARM_MMU_IDX_A_NS; | |
4270 | } | |
4271 | ||
4272 | return mask; | |
b7e0730d RH |
4273 | } |
4274 | ||
ea04dce7 RH |
4275 | /* Return 56 if TBI is enabled, 64 otherwise. */ |
4276 | static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, | |
4277 | uint64_t addr) | |
4278 | { | |
4279 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | |
4280 | int tbi = aa64_va_parameter_tbi(tcr, mmu_idx); | |
4281 | int select = extract64(addr, 55, 1); | |
4282 | ||
4283 | return (tbi >> select) & 1 ? 56 : 64; | |
4284 | } | |
4285 | ||
4286 | static int vae1_tlbbits(CPUARMState *env, uint64_t addr) | |
4287 | { | |
b6ad6062 | 4288 | uint64_t hcr = arm_hcr_el2_eff(env); |
ea04dce7 RH |
4289 | ARMMMUIdx mmu_idx; |
4290 | ||
4291 | /* Only the regime of the mmu_idx below is significant. */ | |
b6ad6062 | 4292 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { |
ea04dce7 RH |
4293 | mmu_idx = ARMMMUIdx_E20_0; |
4294 | } else { | |
4295 | mmu_idx = ARMMMUIdx_E10_0; | |
4296 | } | |
b6ad6062 RDC |
4297 | |
4298 | if (arm_is_secure_below_el3(env)) { | |
4299 | mmu_idx &= ~ARM_MMU_IDX_A_NS; | |
4300 | } | |
4301 | ||
ea04dce7 RH |
4302 | return tlbbits_for_regime(env, mmu_idx, addr); |
4303 | } | |
4304 | ||
fd3ed969 PM |
4305 | static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4306 | uint64_t value) | |
168aa23b | 4307 | { |
29a0af61 | 4308 | CPUState *cs = env_cpu(env); |
b7e0730d | 4309 | int mask = vae1_tlbmask(env); |
dbb1fb27 | 4310 | |
b7e0730d | 4311 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
168aa23b PM |
4312 | } |
4313 | ||
b4ab8ce9 PM |
4314 | static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4315 | uint64_t value) | |
4316 | { | |
29a0af61 | 4317 | CPUState *cs = env_cpu(env); |
b7e0730d | 4318 | int mask = vae1_tlbmask(env); |
b4ab8ce9 PM |
4319 | |
4320 | if (tlb_force_broadcast(env)) { | |
527db2be RH |
4321 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
4322 | } else { | |
4323 | tlb_flush_by_mmuidx(cs, mask); | |
b4ab8ce9 | 4324 | } |
b4ab8ce9 PM |
4325 | } |
4326 | ||
90c19cdf | 4327 | static int alle1_tlbmask(CPUARMState *env) |
168aa23b | 4328 | { |
90c19cdf RH |
4329 | /* |
4330 | * Note that the 'ALL' scope must invalidate both stage 1 and | |
fd3ed969 PM |
4331 | * stage 2 translations, whereas most other scopes only invalidate |
4332 | * stage 1 translations. | |
4333 | */ | |
fd3ed969 | 4334 | if (arm_is_secure_below_el3(env)) { |
452ef8cb RH |
4335 | return ARMMMUIdxBit_SE10_1 | |
4336 | ARMMMUIdxBit_SE10_1_PAN | | |
4337 | ARMMMUIdxBit_SE10_0; | |
fd3ed969 | 4338 | } else { |
452ef8cb RH |
4339 | return ARMMMUIdxBit_E10_1 | |
4340 | ARMMMUIdxBit_E10_1_PAN | | |
4341 | ARMMMUIdxBit_E10_0; | |
fd3ed969 | 4342 | } |
168aa23b PM |
4343 | } |
4344 | ||
85d0dc9f RH |
4345 | static int e2_tlbmask(CPUARMState *env) |
4346 | { | |
b6ad6062 RDC |
4347 | if (arm_is_secure_below_el3(env)) { |
4348 | return ARMMMUIdxBit_SE20_0 | | |
4349 | ARMMMUIdxBit_SE20_2 | | |
4350 | ARMMMUIdxBit_SE20_2_PAN | | |
4351 | ARMMMUIdxBit_SE2; | |
4352 | } else { | |
4353 | return ARMMMUIdxBit_E20_0 | | |
4354 | ARMMMUIdxBit_E20_2 | | |
4355 | ARMMMUIdxBit_E20_2_PAN | | |
4356 | ARMMMUIdxBit_E2; | |
4357 | } | |
85d0dc9f RH |
4358 | } |
4359 | ||
90c19cdf RH |
4360 | static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4361 | uint64_t value) | |
4362 | { | |
4363 | CPUState *cs = env_cpu(env); | |
4364 | int mask = alle1_tlbmask(env); | |
4365 | ||
4366 | tlb_flush_by_mmuidx(cs, mask); | |
4367 | } | |
4368 | ||
fd3ed969 | 4369 | static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
fa439fc5 PM |
4370 | uint64_t value) |
4371 | { | |
85d0dc9f RH |
4372 | CPUState *cs = env_cpu(env); |
4373 | int mask = e2_tlbmask(env); | |
fd3ed969 | 4374 | |
85d0dc9f | 4375 | tlb_flush_by_mmuidx(cs, mask); |
fd3ed969 PM |
4376 | } |
4377 | ||
43efaa33 PM |
4378 | static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4379 | uint64_t value) | |
4380 | { | |
2fc0cc0e | 4381 | ARMCPU *cpu = env_archcpu(env); |
43efaa33 PM |
4382 | CPUState *cs = CPU(cpu); |
4383 | ||
127b2b08 | 4384 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3); |
43efaa33 PM |
4385 | } |
4386 | ||
fd3ed969 PM |
4387 | static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4388 | uint64_t value) | |
4389 | { | |
29a0af61 | 4390 | CPUState *cs = env_cpu(env); |
90c19cdf RH |
4391 | int mask = alle1_tlbmask(env); |
4392 | ||
4393 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); | |
fa439fc5 PM |
4394 | } |
4395 | ||
2bfb9d75 PM |
4396 | static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4397 | uint64_t value) | |
4398 | { | |
29a0af61 | 4399 | CPUState *cs = env_cpu(env); |
85d0dc9f | 4400 | int mask = e2_tlbmask(env); |
2bfb9d75 | 4401 | |
85d0dc9f | 4402 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
2bfb9d75 PM |
4403 | } |
4404 | ||
43efaa33 PM |
4405 | static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4406 | uint64_t value) | |
4407 | { | |
29a0af61 | 4408 | CPUState *cs = env_cpu(env); |
43efaa33 | 4409 | |
127b2b08 | 4410 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3); |
43efaa33 PM |
4411 | } |
4412 | ||
fd3ed969 PM |
4413 | static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4414 | uint64_t value) | |
fa439fc5 | 4415 | { |
fd3ed969 PM |
4416 | /* Invalidate by VA, EL2 |
4417 | * Currently handles both VAE2 and VALE2, since we don't support | |
4418 | * flush-last-level-only. | |
4419 | */ | |
85d0dc9f RH |
4420 | CPUState *cs = env_cpu(env); |
4421 | int mask = e2_tlbmask(env); | |
fd3ed969 PM |
4422 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
4423 | ||
85d0dc9f | 4424 | tlb_flush_page_by_mmuidx(cs, pageaddr, mask); |
fd3ed969 PM |
4425 | } |
4426 | ||
43efaa33 PM |
4427 | static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4428 | uint64_t value) | |
4429 | { | |
4430 | /* Invalidate by VA, EL3 | |
4431 | * Currently handles both VAE3 and VALE3, since we don't support | |
4432 | * flush-last-level-only. | |
4433 | */ | |
2fc0cc0e | 4434 | ARMCPU *cpu = env_archcpu(env); |
43efaa33 PM |
4435 | CPUState *cs = CPU(cpu); |
4436 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
4437 | ||
127b2b08 | 4438 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3); |
43efaa33 PM |
4439 | } |
4440 | ||
fd3ed969 PM |
4441 | static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4442 | uint64_t value) | |
4443 | { | |
90c19cdf RH |
4444 | CPUState *cs = env_cpu(env); |
4445 | int mask = vae1_tlbmask(env); | |
fa439fc5 | 4446 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ea04dce7 | 4447 | int bits = vae1_tlbbits(env, pageaddr); |
fa439fc5 | 4448 | |
ea04dce7 | 4449 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); |
fa439fc5 PM |
4450 | } |
4451 | ||
b4ab8ce9 PM |
4452 | static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4453 | uint64_t value) | |
4454 | { | |
4455 | /* Invalidate by VA, EL1&0 (AArch64 version). | |
4456 | * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, | |
4457 | * since we don't support flush-for-specific-ASID-only or | |
4458 | * flush-last-level-only. | |
4459 | */ | |
90c19cdf RH |
4460 | CPUState *cs = env_cpu(env); |
4461 | int mask = vae1_tlbmask(env); | |
b4ab8ce9 | 4462 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ea04dce7 | 4463 | int bits = vae1_tlbbits(env, pageaddr); |
b4ab8ce9 PM |
4464 | |
4465 | if (tlb_force_broadcast(env)) { | |
ea04dce7 | 4466 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); |
527db2be | 4467 | } else { |
ea04dce7 | 4468 | tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits); |
b4ab8ce9 | 4469 | } |
b4ab8ce9 PM |
4470 | } |
4471 | ||
fd3ed969 PM |
4472 | static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4473 | uint64_t value) | |
fa439fc5 | 4474 | { |
29a0af61 | 4475 | CPUState *cs = env_cpu(env); |
fd3ed969 | 4476 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
b6ad6062 RDC |
4477 | bool secure = arm_is_secure_below_el3(env); |
4478 | int mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; | |
eb849d8f | 4479 | int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2, |
b6ad6062 | 4480 | pageaddr); |
fa439fc5 | 4481 | |
b6ad6062 | 4482 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); |
fa439fc5 PM |
4483 | } |
4484 | ||
43efaa33 PM |
4485 | static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4486 | uint64_t value) | |
4487 | { | |
29a0af61 | 4488 | CPUState *cs = env_cpu(env); |
43efaa33 | 4489 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ea04dce7 | 4490 | int bits = tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr); |
43efaa33 | 4491 | |
ea04dce7 RH |
4492 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, |
4493 | ARMMMUIdxBit_SE3, bits); | |
43efaa33 PM |
4494 | } |
4495 | ||
84940ed8 | 4496 | #ifdef TARGET_AARCH64 |
ab1cdb47 RH |
4497 | typedef struct { |
4498 | uint64_t base; | |
84940ed8 | 4499 | uint64_t length; |
ab1cdb47 RH |
4500 | } TLBIRange; |
4501 | ||
4502 | static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, | |
4503 | uint64_t value) | |
4504 | { | |
4505 | unsigned int page_size_granule, page_shift, num, scale, exponent; | |
3974ff93 RH |
4506 | /* Extract one bit to represent the va selector in use. */ |
4507 | uint64_t select = sextract64(value, 36, 1); | |
4508 | ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true); | |
ab1cdb47 | 4509 | TLBIRange ret = { }; |
84940ed8 | 4510 | |
84940ed8 RC |
4511 | page_size_granule = extract64(value, 46, 2); |
4512 | ||
3974ff93 RH |
4513 | /* The granule encoded in value must match the granule in use. */ |
4514 | if (page_size_granule != (param.using64k ? 3 : param.using16k ? 2 : 1)) { | |
4515 | qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\n", | |
84940ed8 | 4516 | page_size_granule); |
ab1cdb47 | 4517 | return ret; |
84940ed8 RC |
4518 | } |
4519 | ||
52a9f609 | 4520 | page_shift = (page_size_granule - 1) * 2 + 12; |
ab1cdb47 RH |
4521 | num = extract64(value, 39, 5); |
4522 | scale = extract64(value, 44, 2); | |
84940ed8 | 4523 | exponent = (5 * scale) + 1; |
84940ed8 | 4524 | |
ab1cdb47 | 4525 | ret.length = (num + 1) << (exponent + page_shift); |
84940ed8 | 4526 | |
3974ff93 | 4527 | if (param.select) { |
d976de21 | 4528 | ret.base = sextract64(value, 0, 37); |
84940ed8 | 4529 | } else { |
d976de21 | 4530 | ret.base = extract64(value, 0, 37); |
84940ed8 | 4531 | } |
ef56c242 RH |
4532 | if (param.ds) { |
4533 | /* | |
4534 | * With DS=1, BaseADDR is always shifted 16 so that it is able | |
4535 | * to address all 52 va bits. The input address is perforce | |
4536 | * aligned on a 64k boundary regardless of translation granule. | |
4537 | */ | |
4538 | page_shift = 16; | |
4539 | } | |
d976de21 | 4540 | ret.base <<= page_shift; |
84940ed8 | 4541 | |
ab1cdb47 | 4542 | return ret; |
84940ed8 RC |
4543 | } |
4544 | ||
4545 | static void do_rvae_write(CPUARMState *env, uint64_t value, | |
4546 | int idxmap, bool synced) | |
4547 | { | |
4548 | ARMMMUIdx one_idx = ARM_MMU_IDX_A | ctz32(idxmap); | |
ab1cdb47 | 4549 | TLBIRange range; |
84940ed8 RC |
4550 | int bits; |
4551 | ||
ab1cdb47 RH |
4552 | range = tlbi_aa64_get_range(env, one_idx, value); |
4553 | bits = tlbbits_for_regime(env, one_idx, range.base); | |
84940ed8 RC |
4554 | |
4555 | if (synced) { | |
4556 | tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env), | |
ab1cdb47 RH |
4557 | range.base, |
4558 | range.length, | |
84940ed8 RC |
4559 | idxmap, |
4560 | bits); | |
4561 | } else { | |
ab1cdb47 RH |
4562 | tlb_flush_range_by_mmuidx(env_cpu(env), range.base, |
4563 | range.length, idxmap, bits); | |
84940ed8 RC |
4564 | } |
4565 | } | |
4566 | ||
4567 | static void tlbi_aa64_rvae1_write(CPUARMState *env, | |
4568 | const ARMCPRegInfo *ri, | |
4569 | uint64_t value) | |
4570 | { | |
4571 | /* | |
4572 | * Invalidate by VA range, EL1&0. | |
4573 | * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1, | |
4574 | * since we don't support flush-for-specific-ASID-only or | |
4575 | * flush-last-level-only. | |
4576 | */ | |
4577 | ||
4578 | do_rvae_write(env, value, vae1_tlbmask(env), | |
4579 | tlb_force_broadcast(env)); | |
4580 | } | |
4581 | ||
4582 | static void tlbi_aa64_rvae1is_write(CPUARMState *env, | |
4583 | const ARMCPRegInfo *ri, | |
4584 | uint64_t value) | |
4585 | { | |
4586 | /* | |
4587 | * Invalidate by VA range, Inner/Outer Shareable EL1&0. | |
4588 | * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS, | |
4589 | * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support | |
4590 | * flush-for-specific-ASID-only, flush-last-level-only or inner/outer | |
4591 | * shareable specific flushes. | |
4592 | */ | |
4593 | ||
4594 | do_rvae_write(env, value, vae1_tlbmask(env), true); | |
4595 | } | |
4596 | ||
4597 | static int vae2_tlbmask(CPUARMState *env) | |
4598 | { | |
4599 | return (arm_is_secure_below_el3(env) | |
4600 | ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2); | |
4601 | } | |
4602 | ||
4603 | static void tlbi_aa64_rvae2_write(CPUARMState *env, | |
4604 | const ARMCPRegInfo *ri, | |
4605 | uint64_t value) | |
4606 | { | |
4607 | /* | |
4608 | * Invalidate by VA range, EL2. | |
4609 | * Currently handles all of RVAE2 and RVALE2, | |
4610 | * since we don't support flush-for-specific-ASID-only or | |
4611 | * flush-last-level-only. | |
4612 | */ | |
4613 | ||
4614 | do_rvae_write(env, value, vae2_tlbmask(env), | |
4615 | tlb_force_broadcast(env)); | |
4616 | ||
4617 | ||
4618 | } | |
4619 | ||
4620 | static void tlbi_aa64_rvae2is_write(CPUARMState *env, | |
4621 | const ARMCPRegInfo *ri, | |
4622 | uint64_t value) | |
4623 | { | |
4624 | /* | |
4625 | * Invalidate by VA range, Inner/Outer Shareable, EL2. | |
4626 | * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS, | |
4627 | * since we don't support flush-for-specific-ASID-only, | |
4628 | * flush-last-level-only or inner/outer shareable specific flushes. | |
4629 | */ | |
4630 | ||
4631 | do_rvae_write(env, value, vae2_tlbmask(env), true); | |
4632 | ||
4633 | } | |
4634 | ||
4635 | static void tlbi_aa64_rvae3_write(CPUARMState *env, | |
4636 | const ARMCPRegInfo *ri, | |
4637 | uint64_t value) | |
4638 | { | |
4639 | /* | |
4640 | * Invalidate by VA range, EL3. | |
4641 | * Currently handles all of RVAE3 and RVALE3, | |
4642 | * since we don't support flush-for-specific-ASID-only or | |
4643 | * flush-last-level-only. | |
4644 | */ | |
4645 | ||
4646 | do_rvae_write(env, value, ARMMMUIdxBit_SE3, | |
4647 | tlb_force_broadcast(env)); | |
4648 | } | |
4649 | ||
4650 | static void tlbi_aa64_rvae3is_write(CPUARMState *env, | |
4651 | const ARMCPRegInfo *ri, | |
4652 | uint64_t value) | |
4653 | { | |
4654 | /* | |
4655 | * Invalidate by VA range, EL3, Inner/Outer Shareable. | |
4656 | * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS, | |
4657 | * since we don't support flush-for-specific-ASID-only, | |
4658 | * flush-last-level-only or inner/outer specific flushes. | |
4659 | */ | |
4660 | ||
4661 | do_rvae_write(env, value, ARMMMUIdxBit_SE3, true); | |
4662 | } | |
4663 | #endif | |
4664 | ||
3f208fd7 PM |
4665 | static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4666 | bool isread) | |
aca3f40b | 4667 | { |
4351cb72 RH |
4668 | int cur_el = arm_current_el(env); |
4669 | ||
4670 | if (cur_el < 2) { | |
4671 | uint64_t hcr = arm_hcr_el2_eff(env); | |
4672 | ||
4673 | if (cur_el == 0) { | |
4674 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
4675 | if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) { | |
4676 | return CP_ACCESS_TRAP_EL2; | |
4677 | } | |
4678 | } else { | |
4679 | if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) { | |
4680 | return CP_ACCESS_TRAP; | |
4681 | } | |
4682 | if (hcr & HCR_TDZ) { | |
4683 | return CP_ACCESS_TRAP_EL2; | |
4684 | } | |
4685 | } | |
4686 | } else if (hcr & HCR_TDZ) { | |
4687 | return CP_ACCESS_TRAP_EL2; | |
4688 | } | |
aca3f40b PM |
4689 | } |
4690 | return CP_ACCESS_OK; | |
4691 | } | |
4692 | ||
4693 | static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
4694 | { | |
2fc0cc0e | 4695 | ARMCPU *cpu = env_archcpu(env); |
aca3f40b PM |
4696 | int dzp_bit = 1 << 4; |
4697 | ||
4698 | /* DZP indicates whether DC ZVA access is allowed */ | |
3f208fd7 | 4699 | if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) { |
aca3f40b PM |
4700 | dzp_bit = 0; |
4701 | } | |
4702 | return cpu->dcz_blocksize | dzp_bit; | |
4703 | } | |
4704 | ||
3f208fd7 PM |
4705 | static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4706 | bool isread) | |
f502cfc2 | 4707 | { |
cdcf1405 | 4708 | if (!(env->pstate & PSTATE_SP)) { |
f502cfc2 PM |
4709 | /* Access to SP_EL0 is undefined if it's being used as |
4710 | * the stack pointer. | |
4711 | */ | |
4712 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
4713 | } | |
4714 | return CP_ACCESS_OK; | |
4715 | } | |
4716 | ||
4717 | static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
4718 | { | |
4719 | return env->pstate & PSTATE_SP; | |
4720 | } | |
4721 | ||
4722 | static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
4723 | { | |
4724 | update_spsel(env, val); | |
4725 | } | |
4726 | ||
137feaa9 FA |
4727 | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4728 | uint64_t value) | |
4729 | { | |
2fc0cc0e | 4730 | ARMCPU *cpu = env_archcpu(env); |
137feaa9 | 4731 | |
f00faf13 RH |
4732 | if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { |
4733 | /* M bit is RAZ/WI for PMSA with no MPU implemented */ | |
4734 | value &= ~SCTLR_M; | |
4735 | } | |
4736 | ||
4737 | /* ??? Lots of these bits are not implemented. */ | |
4738 | ||
4739 | if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) { | |
4740 | if (ri->opc1 == 6) { /* SCTLR_EL3 */ | |
4741 | value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); | |
4742 | } else { | |
4743 | value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | | |
4744 | SCTLR_ATA0 | SCTLR_ATA); | |
4745 | } | |
4746 | } | |
4747 | ||
137feaa9 FA |
4748 | if (raw_read(env, ri) == value) { |
4749 | /* Skip the TLB flush if nothing actually changed; Linux likes | |
4750 | * to do a lot of pointless SCTLR writes. | |
4751 | */ | |
4752 | return; | |
4753 | } | |
4754 | ||
4755 | raw_write(env, ri, value); | |
f00faf13 | 4756 | |
137feaa9 | 4757 | /* This may enable/disable the MMU, so do a TLB flush. */ |
d10eb08f | 4758 | tlb_flush(CPU(cpu)); |
2e5dcf36 RH |
4759 | |
4760 | if (ri->type & ARM_CP_SUPPRESS_TB_END) { | |
4761 | /* | |
4762 | * Normally we would always end the TB on an SCTLR write; see the | |
4763 | * comment in ARMCPRegInfo sctlr initialization below for why Xscale | |
4764 | * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild | |
4765 | * of hflags from the translator, so do it here. | |
4766 | */ | |
4767 | arm_rebuild_hflags(env); | |
4768 | } | |
137feaa9 FA |
4769 | } |
4770 | ||
a8d64e73 PM |
4771 | static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4772 | uint64_t value) | |
4773 | { | |
4774 | env->cp15.mdcr_el3 = value & SDCR_VALID_MASK; | |
4775 | } | |
4776 | ||
b0d2b7d0 PM |
4777 | static const ARMCPRegInfo v8_cp_reginfo[] = { |
4778 | /* Minimal set of EL0-visible registers. This will need to be expanded | |
4779 | * significantly for system emulation of AArch64 CPUs. | |
4780 | */ | |
4781 | { .name = "NZCV", .state = ARM_CP_STATE_AA64, | |
4782 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, | |
4783 | .access = PL0_RW, .type = ARM_CP_NZCV }, | |
c2b820fe PM |
4784 | { .name = "DAIF", .state = ARM_CP_STATE_AA64, |
4785 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, | |
7a0e58fa | 4786 | .type = ARM_CP_NO_RAW, |
c2b820fe PM |
4787 | .access = PL0_RW, .accessfn = aa64_daif_access, |
4788 | .fieldoffset = offsetof(CPUARMState, daif), | |
4789 | .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, | |
b0d2b7d0 PM |
4790 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, |
4791 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | |
b916c9c3 | 4792 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 4793 | .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, |
b0d2b7d0 PM |
4794 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, |
4795 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | |
b916c9c3 | 4796 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 4797 | .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, |
b0d2b7d0 PM |
4798 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, |
4799 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | |
7a0e58fa | 4800 | .access = PL0_R, .type = ARM_CP_NO_RAW, |
aca3f40b PM |
4801 | .readfn = aa64_dczid_read }, |
4802 | { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, | |
4803 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, | |
4804 | .access = PL0_W, .type = ARM_CP_DC_ZVA, | |
4805 | #ifndef CONFIG_USER_ONLY | |
4806 | /* Avoid overhead of an access check that always passes in user-mode */ | |
4807 | .accessfn = aa64_zva_access, | |
4808 | #endif | |
4809 | }, | |
0eef9d98 PM |
4810 | { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, |
4811 | .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, | |
4812 | .access = PL1_R, .type = ARM_CP_CURRENTEL }, | |
8af35c37 PM |
4813 | /* Cache ops: all NOPs since we don't emulate caches */ |
4814 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, | |
4815 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
38262d8a RH |
4816 | .access = PL1_W, .type = ARM_CP_NOP, |
4817 | .accessfn = aa64_cacheop_pou_access }, | |
8af35c37 PM |
4818 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, |
4819 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
38262d8a RH |
4820 | .access = PL1_W, .type = ARM_CP_NOP, |
4821 | .accessfn = aa64_cacheop_pou_access }, | |
8af35c37 PM |
4822 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, |
4823 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | |
4824 | .access = PL0_W, .type = ARM_CP_NOP, | |
38262d8a | 4825 | .accessfn = aa64_cacheop_pou_access }, |
8af35c37 PM |
4826 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, |
4827 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
1bed4d2e RH |
4828 | .access = PL1_W, .accessfn = aa64_cacheop_poc_access, |
4829 | .type = ARM_CP_NOP }, | |
8af35c37 PM |
4830 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, |
4831 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
1803d271 | 4832 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
8af35c37 PM |
4833 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, |
4834 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | |
4835 | .access = PL0_W, .type = ARM_CP_NOP, | |
1bed4d2e | 4836 | .accessfn = aa64_cacheop_poc_access }, |
8af35c37 PM |
4837 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, |
4838 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
1803d271 | 4839 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
8af35c37 PM |
4840 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, |
4841 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | |
4842 | .access = PL0_W, .type = ARM_CP_NOP, | |
38262d8a | 4843 | .accessfn = aa64_cacheop_pou_access }, |
8af35c37 PM |
4844 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, |
4845 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | |
4846 | .access = PL0_W, .type = ARM_CP_NOP, | |
1bed4d2e | 4847 | .accessfn = aa64_cacheop_poc_access }, |
8af35c37 PM |
4848 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, |
4849 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
1803d271 | 4850 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
168aa23b PM |
4851 | /* TLBI operations */ |
4852 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 4853 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, |
30881b73 | 4854 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4855 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 4856 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4857 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
30881b73 | 4858 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4859 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4860 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4861 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
30881b73 | 4862 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4863 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 4864 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4865 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
30881b73 | 4866 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4867 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4868 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4869 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
30881b73 | 4870 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4871 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4872 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4873 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
30881b73 | 4874 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4875 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4876 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4877 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, |
30881b73 | 4878 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4879 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 4880 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4881 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
30881b73 | 4882 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4883 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4884 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4885 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
30881b73 | 4886 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4887 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 4888 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4889 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
30881b73 | 4890 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4891 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4892 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4893 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
30881b73 | 4894 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4895 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4896 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4897 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
30881b73 | 4898 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4899 | .writefn = tlbi_aa64_vae1_write }, |
cea66e91 PM |
4900 | { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, |
4901 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
bf05340c | 4902 | .access = PL2_W, .type = ARM_CP_NOP }, |
cea66e91 PM |
4903 | { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, |
4904 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
bf05340c | 4905 | .access = PL2_W, .type = ARM_CP_NOP }, |
83ddf975 PM |
4906 | { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, |
4907 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
4908 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 4909 | .writefn = tlbi_aa64_alle1is_write }, |
43efaa33 PM |
4910 | { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, |
4911 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, | |
4912 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4913 | .writefn = tlbi_aa64_alle1is_write }, | |
cea66e91 PM |
4914 | { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, |
4915 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
bf05340c | 4916 | .access = PL2_W, .type = ARM_CP_NOP }, |
cea66e91 PM |
4917 | { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, |
4918 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
bf05340c | 4919 | .access = PL2_W, .type = ARM_CP_NOP }, |
83ddf975 PM |
4920 | { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, |
4921 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
4922 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 4923 | .writefn = tlbi_aa64_alle1_write }, |
43efaa33 PM |
4924 | { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, |
4925 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, | |
4926 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4927 | .writefn = tlbi_aa64_alle1is_write }, | |
19525524 PM |
4928 | #ifndef CONFIG_USER_ONLY |
4929 | /* 64 bit address translation operations */ | |
4930 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
4931 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, | |
0710b2fa PM |
4932 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4933 | .writefn = ats_write64 }, | |
19525524 PM |
4934 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, |
4935 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, | |
0710b2fa PM |
4936 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4937 | .writefn = ats_write64 }, | |
19525524 PM |
4938 | { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, |
4939 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, | |
0710b2fa PM |
4940 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4941 | .writefn = ats_write64 }, | |
19525524 PM |
4942 | { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, |
4943 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, | |
0710b2fa PM |
4944 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4945 | .writefn = ats_write64 }, | |
2a47df95 | 4946 | { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4947 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, |
0710b2fa PM |
4948 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4949 | .writefn = ats_write64 }, | |
2a47df95 | 4950 | { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4951 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, |
0710b2fa PM |
4952 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4953 | .writefn = ats_write64 }, | |
2a47df95 | 4954 | { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4955 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, |
0710b2fa PM |
4956 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4957 | .writefn = ats_write64 }, | |
2a47df95 | 4958 | { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4959 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, |
0710b2fa PM |
4960 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4961 | .writefn = ats_write64 }, | |
2a47df95 PM |
4962 | /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ |
4963 | { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, | |
4964 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, | |
0710b2fa PM |
4965 | .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4966 | .writefn = ats_write64 }, | |
2a47df95 PM |
4967 | { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, |
4968 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, | |
0710b2fa PM |
4969 | .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4970 | .writefn = ats_write64 }, | |
c96fc9b5 EI |
4971 | { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, |
4972 | .type = ARM_CP_ALIAS, | |
4973 | .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, | |
4974 | .access = PL1_RW, .resetvalue = 0, | |
4975 | .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), | |
4976 | .writefn = par_write }, | |
19525524 | 4977 | #endif |
995939a6 | 4978 | /* TLB invalidate last level of translation table walk */ |
9449fdf6 | 4979 | { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
30881b73 RH |
4980 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
4981 | .writefn = tlbimva_is_write }, | |
9449fdf6 | 4982 | { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
30881b73 | 4983 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
fa439fc5 | 4984 | .writefn = tlbimvaa_is_write }, |
9449fdf6 | 4985 | { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
30881b73 RH |
4986 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
4987 | .writefn = tlbimva_write }, | |
9449fdf6 | 4988 | { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
30881b73 RH |
4989 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
4990 | .writefn = tlbimvaa_write }, | |
541ef8c2 SS |
4991 | { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, |
4992 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4993 | .writefn = tlbimva_hyp_write }, | |
4994 | { .name = "TLBIMVALHIS", | |
4995 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
4996 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4997 | .writefn = tlbimva_hyp_is_write }, | |
4998 | { .name = "TLBIIPAS2", | |
4999 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
bf05340c | 5000 | .type = ARM_CP_NOP, .access = PL2_W }, |
541ef8c2 SS |
5001 | { .name = "TLBIIPAS2IS", |
5002 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
bf05340c | 5003 | .type = ARM_CP_NOP, .access = PL2_W }, |
541ef8c2 SS |
5004 | { .name = "TLBIIPAS2L", |
5005 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
bf05340c | 5006 | .type = ARM_CP_NOP, .access = PL2_W }, |
541ef8c2 SS |
5007 | { .name = "TLBIIPAS2LIS", |
5008 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
bf05340c | 5009 | .type = ARM_CP_NOP, .access = PL2_W }, |
9449fdf6 PM |
5010 | /* 32 bit cache operations */ |
5011 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
38262d8a | 5012 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, |
9449fdf6 PM |
5013 | { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, |
5014 | .type = ARM_CP_NOP, .access = PL1_W }, | |
5015 | { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
38262d8a | 5016 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, |
9449fdf6 | 5017 | { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, |
38262d8a | 5018 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, |
9449fdf6 PM |
5019 | { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, |
5020 | .type = ARM_CP_NOP, .access = PL1_W }, | |
5021 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | |
5022 | .type = ARM_CP_NOP, .access = PL1_W }, | |
5023 | { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
1bed4d2e | 5024 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 5025 | { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, |
1803d271 | 5026 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 5027 | { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, |
1bed4d2e | 5028 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 5029 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, |
1803d271 | 5030 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 5031 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, |
38262d8a | 5032 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, |
9449fdf6 | 5033 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, |
1bed4d2e | 5034 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 5035 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, |
1803d271 | 5036 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 5037 | /* MMU Domain access control / MPU write buffer control */ |
0c17d68c | 5038 | { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, |
84929218 | 5039 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
0c17d68c FA |
5040 | .writefn = dacr_write, .raw_writefn = raw_write, |
5041 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
5042 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a0618a19 | 5043 | { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5044 | .type = ARM_CP_ALIAS, |
a0618a19 | 5045 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, |
6947f059 EI |
5046 | .access = PL1_RW, |
5047 | .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, | |
a65f1de9 | 5048 | { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5049 | .type = ARM_CP_ALIAS, |
a65f1de9 | 5050 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
5051 | .access = PL1_RW, |
5052 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, | |
f502cfc2 PM |
5053 | /* We rely on the access checks not allowing the guest to write to the |
5054 | * state field when SPSel indicates that it's being used as the stack | |
5055 | * pointer. | |
5056 | */ | |
5057 | { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, | |
5058 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, | |
5059 | .access = PL1_RW, .accessfn = sp_el0_access, | |
7a0e58fa | 5060 | .type = ARM_CP_ALIAS, |
f502cfc2 | 5061 | .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, |
884b4dee GB |
5062 | { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, |
5063 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 5064 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
884b4dee | 5065 | .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, |
f502cfc2 PM |
5066 | { .name = "SPSel", .state = ARM_CP_STATE_AA64, |
5067 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, | |
7a0e58fa | 5068 | .type = ARM_CP_NO_RAW, |
f502cfc2 | 5069 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, |
03fbf20f PM |
5070 | { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, |
5071 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, | |
696ba377 RH |
5072 | .access = PL2_RW, |
5073 | .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, | |
a4c88675 | 5074 | .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, |
6a43e0b6 PM |
5075 | { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, |
5076 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, | |
696ba377 | 5077 | .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, |
6a43e0b6 PM |
5078 | .writefn = dacr_write, .raw_writefn = raw_write, |
5079 | .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, | |
5080 | { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, | |
5081 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, | |
696ba377 | 5082 | .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, |
6a43e0b6 PM |
5083 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, |
5084 | { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, | |
5085 | .type = ARM_CP_ALIAS, | |
5086 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, | |
5087 | .access = PL2_RW, | |
5088 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, | |
5089 | { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, | |
5090 | .type = ARM_CP_ALIAS, | |
5091 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, | |
5092 | .access = PL2_RW, | |
5093 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, | |
5094 | { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, | |
5095 | .type = ARM_CP_ALIAS, | |
5096 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, | |
5097 | .access = PL2_RW, | |
5098 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, | |
5099 | { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, | |
5100 | .type = ARM_CP_ALIAS, | |
5101 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, | |
5102 | .access = PL2_RW, | |
5103 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, | |
a8d64e73 PM |
5104 | { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, |
5105 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, | |
5106 | .resetvalue = 0, | |
5107 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) }, | |
5108 | { .name = "SDCR", .type = ARM_CP_ALIAS, | |
5109 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1, | |
5110 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, | |
5111 | .writefn = sdcr_write, | |
5112 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, | |
b0d2b7d0 PM |
5113 | }; |
5114 | ||
d1fb4da2 | 5115 | static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) |
f149e3e8 | 5116 | { |
2fc0cc0e | 5117 | ARMCPU *cpu = env_archcpu(env); |
d1fb4da2 RH |
5118 | |
5119 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
5120 | valid_mask |= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */ | |
5121 | } else { | |
5122 | valid_mask |= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */ | |
5123 | } | |
f149e3e8 EI |
5124 | |
5125 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
5126 | valid_mask &= ~HCR_HCD; | |
77077a83 JK |
5127 | } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { |
5128 | /* Architecturally HCR.TSC is RES0 if EL3 is not implemented. | |
5129 | * However, if we're using the SMC PSCI conduit then QEMU is | |
5130 | * effectively acting like EL3 firmware and so the guest at | |
5131 | * EL2 should retain the ability to prevent EL1 from being | |
5132 | * able to make SMC calls into the ersatz firmware, so in | |
5133 | * that case HCR.TSC should be read/write. | |
5134 | */ | |
f149e3e8 EI |
5135 | valid_mask &= ~HCR_TSC; |
5136 | } | |
d1fb4da2 RH |
5137 | |
5138 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
5139 | if (cpu_isar_feature(aa64_vh, cpu)) { | |
5140 | valid_mask |= HCR_E2H; | |
5141 | } | |
da3d8b13 RH |
5142 | if (cpu_isar_feature(aa64_ras, cpu)) { |
5143 | valid_mask |= HCR_TERR | HCR_TEA; | |
5144 | } | |
d1fb4da2 RH |
5145 | if (cpu_isar_feature(aa64_lor, cpu)) { |
5146 | valid_mask |= HCR_TLOR; | |
5147 | } | |
5148 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
5149 | valid_mask |= HCR_API | HCR_APK; | |
5150 | } | |
8ddb300b RH |
5151 | if (cpu_isar_feature(aa64_mte, cpu)) { |
5152 | valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5; | |
5153 | } | |
7cb1e618 RH |
5154 | if (cpu_isar_feature(aa64_scxtnum, cpu)) { |
5155 | valid_mask |= HCR_ENSCXT; | |
5156 | } | |
8c7e17ef PM |
5157 | if (cpu_isar_feature(aa64_fwb, cpu)) { |
5158 | valid_mask |= HCR_FWB; | |
5159 | } | |
ef682cdb | 5160 | } |
f149e3e8 EI |
5161 | |
5162 | /* Clear RES0 bits. */ | |
5163 | value &= valid_mask; | |
5164 | ||
8ddb300b RH |
5165 | /* |
5166 | * These bits change the MMU setup: | |
f149e3e8 EI |
5167 | * HCR_VM enables stage 2 translation |
5168 | * HCR_PTW forbids certain page-table setups | |
8ddb300b RH |
5169 | * HCR_DC disables stage1 and enables stage2 translation |
5170 | * HCR_DCT enables tagging on (disabled) stage1 translation | |
8c7e17ef | 5171 | * HCR_FWB changes the interpretation of stage2 descriptor bits |
f149e3e8 | 5172 | */ |
8c7e17ef PM |
5173 | if ((env->cp15.hcr_el2 ^ value) & |
5174 | (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT | HCR_FWB)) { | |
d10eb08f | 5175 | tlb_flush(CPU(cpu)); |
f149e3e8 | 5176 | } |
ce4afed8 | 5177 | env->cp15.hcr_el2 = value; |
89430fc6 PM |
5178 | |
5179 | /* | |
5180 | * Updates to VI and VF require us to update the status of | |
5181 | * virtual interrupts, which are the logical OR of these bits | |
5182 | * and the state of the input lines from the GIC. (This requires | |
5183 | * that we have the iothread lock, which is done by marking the | |
5184 | * reginfo structs as ARM_CP_IO.) | |
5185 | * Note that if a write to HCR pends a VIRQ or VFIQ it is never | |
5186 | * possible for it to be taken immediately, because VIRQ and | |
5187 | * VFIQ are masked unless running at EL0 or EL1, and HCR | |
5188 | * can only be written at EL2. | |
5189 | */ | |
5190 | g_assert(qemu_mutex_iothread_locked()); | |
5191 | arm_cpu_update_virq(cpu); | |
5192 | arm_cpu_update_vfiq(cpu); | |
3c29632f | 5193 | arm_cpu_update_vserr(cpu); |
ce4afed8 PM |
5194 | } |
5195 | ||
d1fb4da2 RH |
5196 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
5197 | { | |
5198 | do_hcr_write(env, value, 0); | |
5199 | } | |
5200 | ||
ce4afed8 PM |
5201 | static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, |
5202 | uint64_t value) | |
5203 | { | |
5204 | /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */ | |
5205 | value = deposit64(env->cp15.hcr_el2, 32, 32, value); | |
d1fb4da2 | 5206 | do_hcr_write(env, value, MAKE_64BIT_MASK(0, 32)); |
ce4afed8 PM |
5207 | } |
5208 | ||
5209 | static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, | |
5210 | uint64_t value) | |
5211 | { | |
5212 | /* Handle HCR write, i.e. write to low half of HCR_EL2 */ | |
5213 | value = deposit64(env->cp15.hcr_el2, 0, 32, value); | |
d1fb4da2 | 5214 | do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32)); |
f149e3e8 EI |
5215 | } |
5216 | ||
f7778444 RH |
5217 | /* |
5218 | * Return the effective value of HCR_EL2. | |
5219 | * Bits that are not included here: | |
5220 | * RW (read from SCR_EL3.RW as needed) | |
5221 | */ | |
5222 | uint64_t arm_hcr_el2_eff(CPUARMState *env) | |
5223 | { | |
5224 | uint64_t ret = env->cp15.hcr_el2; | |
5225 | ||
e6ef0169 | 5226 | if (!arm_is_el2_enabled(env)) { |
f7778444 RH |
5227 | /* |
5228 | * "This register has no effect if EL2 is not enabled in the | |
5229 | * current Security state". This is ARMv8.4-SecEL2 speak for | |
5230 | * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1). | |
5231 | * | |
5232 | * Prior to that, the language was "In an implementation that | |
5233 | * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves | |
5234 | * as if this field is 0 for all purposes other than a direct | |
5235 | * read or write access of HCR_EL2". With lots of enumeration | |
5236 | * on a per-field basis. In current QEMU, this is condition | |
5237 | * is arm_is_secure_below_el3. | |
5238 | * | |
5239 | * Since the v8.4 language applies to the entire register, and | |
5240 | * appears to be backward compatible, use that. | |
5241 | */ | |
4990e1d3 RH |
5242 | return 0; |
5243 | } | |
5244 | ||
5245 | /* | |
5246 | * For a cpu that supports both aarch64 and aarch32, we can set bits | |
5247 | * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32. | |
5248 | * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32. | |
5249 | */ | |
5250 | if (!arm_el_is_aa64(env, 2)) { | |
5251 | uint64_t aa32_valid; | |
5252 | ||
5253 | /* | |
5254 | * These bits are up-to-date as of ARMv8.6. | |
5255 | * For HCR, it's easiest to list just the 2 bits that are invalid. | |
5256 | * For HCR2, list those that are valid. | |
5257 | */ | |
5258 | aa32_valid = MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ); | |
5259 | aa32_valid |= (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNCE | | |
5260 | HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS); | |
5261 | ret &= aa32_valid; | |
5262 | } | |
5263 | ||
5264 | if (ret & HCR_TGE) { | |
5265 | /* These bits are up-to-date as of ARMv8.6. */ | |
f7778444 RH |
5266 | if (ret & HCR_E2H) { |
5267 | ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | | |
5268 | HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | | |
5269 | HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | | |
4990e1d3 RH |
5270 | HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE | |
5271 | HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT | | |
5272 | HCR_TTLBIS | HCR_TTLBOS | HCR_TID5); | |
f7778444 RH |
5273 | } else { |
5274 | ret |= HCR_FMO | HCR_IMO | HCR_AMO; | |
5275 | } | |
5276 | ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | | |
5277 | HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | | |
5278 | HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | | |
5279 | HCR_TLOR); | |
5280 | } | |
5281 | ||
5282 | return ret; | |
5283 | } | |
5284 | ||
19668718 RH |
5285 | /* |
5286 | * Corresponds to ARM pseudocode function ELIsInHost(). | |
5287 | */ | |
5288 | bool el_is_in_host(CPUARMState *env, int el) | |
5289 | { | |
5290 | uint64_t mask; | |
5291 | ||
5292 | /* | |
5293 | * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff(). | |
5294 | * Perform the simplest bit tests first, and validate EL2 afterward. | |
5295 | */ | |
5296 | if (el & 1) { | |
5297 | return false; /* EL1 or EL3 */ | |
5298 | } | |
5299 | ||
5300 | /* | |
5301 | * Note that hcr_write() checks isar_feature_aa64_vh(), | |
5302 | * aka HaveVirtHostExt(), in allowing HCR_E2H to be set. | |
5303 | */ | |
5304 | mask = el ? HCR_E2H : HCR_E2H | HCR_TGE; | |
5305 | if ((env->cp15.hcr_el2 & mask) != mask) { | |
5306 | return false; | |
5307 | } | |
5308 | ||
5309 | /* TGE and/or E2H set: double check those bits are currently legal. */ | |
5310 | return arm_is_el2_enabled(env) && arm_el_is_aa64(env, 2); | |
5311 | } | |
5312 | ||
5814d587 RH |
5313 | static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5314 | uint64_t value) | |
5315 | { | |
5316 | uint64_t valid_mask = 0; | |
5317 | ||
5318 | /* No features adding bits to HCRX are implemented. */ | |
5319 | ||
5320 | /* Clear RES0 bits. */ | |
5321 | env->cp15.hcrx_el2 = value & valid_mask; | |
5322 | } | |
5323 | ||
5324 | static CPAccessResult access_hxen(CPUARMState *env, const ARMCPRegInfo *ri, | |
5325 | bool isread) | |
5326 | { | |
5327 | if (arm_current_el(env) < 3 | |
5328 | && arm_feature(env, ARM_FEATURE_EL3) | |
5329 | && !(env->cp15.scr_el3 & SCR_HXEN)) { | |
5330 | return CP_ACCESS_TRAP_EL3; | |
5331 | } | |
5332 | return CP_ACCESS_OK; | |
5333 | } | |
5334 | ||
5335 | static const ARMCPRegInfo hcrx_el2_reginfo = { | |
5336 | .name = "HCRX_EL2", .state = ARM_CP_STATE_AA64, | |
5337 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 2, | |
5338 | .access = PL2_RW, .writefn = hcrx_write, .accessfn = access_hxen, | |
5339 | .fieldoffset = offsetof(CPUARMState, cp15.hcrx_el2), | |
5340 | }; | |
5341 | ||
5342 | /* Return the effective value of HCRX_EL2. */ | |
5343 | uint64_t arm_hcrx_el2_eff(CPUARMState *env) | |
5344 | { | |
5345 | /* | |
5346 | * The bits in this register behave as 0 for all purposes other than | |
5347 | * direct reads of the register if: | |
5348 | * - EL2 is not enabled in the current security state, | |
5349 | * - SCR_EL3.HXEn is 0. | |
5350 | */ | |
5351 | if (!arm_is_el2_enabled(env) | |
5352 | || (arm_feature(env, ARM_FEATURE_EL3) | |
5353 | && !(env->cp15.scr_el3 & SCR_HXEN))) { | |
5354 | return 0; | |
5355 | } | |
5356 | return env->cp15.hcrx_el2; | |
5357 | } | |
5358 | ||
fc1120a7 PM |
5359 | static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5360 | uint64_t value) | |
5361 | { | |
5362 | /* | |
5363 | * For A-profile AArch32 EL3, if NSACR.CP10 | |
5364 | * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. | |
5365 | */ | |
5366 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
5367 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
fab8ad39 RH |
5368 | uint64_t mask = R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; |
5369 | value = (value & ~mask) | (env->cp15.cptr_el[2] & mask); | |
fc1120a7 PM |
5370 | } |
5371 | env->cp15.cptr_el[2] = value; | |
5372 | } | |
5373 | ||
5374 | static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5375 | { | |
5376 | /* | |
5377 | * For A-profile AArch32 EL3, if NSACR.CP10 | |
5378 | * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. | |
5379 | */ | |
5380 | uint64_t value = env->cp15.cptr_el[2]; | |
5381 | ||
5382 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
5383 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
fab8ad39 | 5384 | value |= R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; |
fc1120a7 PM |
5385 | } |
5386 | return value; | |
5387 | } | |
5388 | ||
4771cd01 | 5389 | static const ARMCPRegInfo el2_cp_reginfo[] = { |
f149e3e8 | 5390 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
89430fc6 | 5391 | .type = ARM_CP_IO, |
f149e3e8 EI |
5392 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
5393 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
c624ea0f | 5394 | .writefn = hcr_write }, |
ce4afed8 | 5395 | { .name = "HCR", .state = ARM_CP_STATE_AA32, |
89430fc6 | 5396 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
5397 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
5398 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
c624ea0f | 5399 | .writefn = hcr_writelow }, |
831a2fca PM |
5400 | { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, |
5401 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, | |
5402 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3b685ba7 | 5403 | { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5404 | .type = ARM_CP_ALIAS, |
3b685ba7 EI |
5405 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, |
5406 | .access = PL2_RW, | |
5407 | .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, | |
68e78e33 | 5408 | { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, |
f2c30f42 EI |
5409 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, |
5410 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, | |
cba517c3 | 5411 | { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, |
63b60551 EI |
5412 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, |
5413 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, | |
cba517c3 PM |
5414 | { .name = "HIFAR", .state = ARM_CP_STATE_AA32, |
5415 | .type = ARM_CP_ALIAS, | |
5416 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | |
5417 | .access = PL2_RW, | |
5418 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) }, | |
3b685ba7 | 5419 | { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5420 | .type = ARM_CP_ALIAS, |
3b685ba7 | 5421 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
5422 | .access = PL2_RW, |
5423 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, | |
d79e0c06 | 5424 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, |
d42e3c26 EI |
5425 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, |
5426 | .access = PL2_RW, .writefn = vbar_write, | |
5427 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), | |
5428 | .resetvalue = 0 }, | |
884b4dee GB |
5429 | { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, |
5430 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 5431 | .access = PL3_RW, .type = ARM_CP_ALIAS, |
884b4dee | 5432 | .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, |
c6f19164 GB |
5433 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
5434 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
5435 | .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, | |
fc1120a7 PM |
5436 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]), |
5437 | .readfn = cptr_el2_read, .writefn = cptr_el2_write }, | |
95f949ac EI |
5438 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
5439 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
5440 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), | |
5441 | .resetvalue = 0 }, | |
5442 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
b5ede85b | 5443 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, |
95f949ac EI |
5444 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
5445 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, | |
2179ef95 PM |
5446 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
5447 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
5448 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5449 | .resetvalue = 0 }, | |
5450 | /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ | |
55b53c71 | 5451 | { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, |
b5ede85b | 5452 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, |
2179ef95 PM |
5453 | .access = PL2_RW, .type = ARM_CP_CONST, |
5454 | .resetvalue = 0 }, | |
37cd6c24 PM |
5455 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
5456 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
5457 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5458 | .resetvalue = 0 }, | |
5459 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
5460 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
5461 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5462 | .resetvalue = 0 }, | |
06ec4c8c EI |
5463 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
5464 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
d06dc933 RH |
5465 | .access = PL2_RW, .writefn = vmsa_tcr_el12_write, |
5466 | /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */ | |
06ec4c8c | 5467 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, |
68e9c2fe EI |
5468 | { .name = "VTCR", .state = ARM_CP_STATE_AA32, |
5469 | .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 | 5470 | .type = ARM_CP_ALIAS, |
68e9c2fe EI |
5471 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
5472 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, | |
5473 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, | |
5474 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 PM |
5475 | .access = PL2_RW, |
5476 | /* no .writefn needed as this can't cause an ASID change; | |
5477 | * no .raw_writefn or .resetfn needed as we never use mask/base_mask | |
5478 | */ | |
68e9c2fe | 5479 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, |
b698e9cf EI |
5480 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
5481 | .cp = 15, .opc1 = 6, .crm = 2, | |
5482 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
5483 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
5484 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), | |
5485 | .writefn = vttbr_write }, | |
5486 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
5487 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
5488 | .access = PL2_RW, .writefn = vttbr_write, | |
5489 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, | |
b9cb5323 EI |
5490 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
5491 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
5492 | .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, | |
5493 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, | |
ff05f37b EI |
5494 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
5495 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
5496 | .access = PL2_RW, .resetvalue = 0, | |
5497 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, | |
a57633c0 EI |
5498 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
5499 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
ed30da8e | 5500 | .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write, |
a57633c0 EI |
5501 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
5502 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
5503 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
a57633c0 | 5504 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
541ef8c2 SS |
5505 | { .name = "TLBIALLNSNH", |
5506 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
5507 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5508 | .writefn = tlbiall_nsnh_write }, | |
5509 | { .name = "TLBIALLNSNHIS", | |
5510 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
5511 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5512 | .writefn = tlbiall_nsnh_is_write }, | |
5513 | { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
5514 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5515 | .writefn = tlbiall_hyp_write }, | |
5516 | { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
5517 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5518 | .writefn = tlbiall_hyp_is_write }, | |
5519 | { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
5520 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5521 | .writefn = tlbimva_hyp_write }, | |
5522 | { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
5523 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5524 | .writefn = tlbimva_hyp_is_write }, | |
51da9014 EI |
5525 | { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, |
5526 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
696ba377 | 5527 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
fd3ed969 | 5528 | .writefn = tlbi_aa64_alle2_write }, |
8742d49d EI |
5529 | { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, |
5530 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
696ba377 | 5531 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
fd3ed969 | 5532 | .writefn = tlbi_aa64_vae2_write }, |
2bfb9d75 PM |
5533 | { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, |
5534 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, | |
696ba377 | 5535 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
2bfb9d75 PM |
5536 | .writefn = tlbi_aa64_vae2_write }, |
5537 | { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, | |
5538 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
696ba377 | 5539 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
2bfb9d75 | 5540 | .writefn = tlbi_aa64_alle2is_write }, |
8742d49d EI |
5541 | { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, |
5542 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
696ba377 | 5543 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
fd3ed969 | 5544 | .writefn = tlbi_aa64_vae2is_write }, |
2bfb9d75 PM |
5545 | { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, |
5546 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
696ba377 | 5547 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
2bfb9d75 | 5548 | .writefn = tlbi_aa64_vae2is_write }, |
edac4d8a | 5549 | #ifndef CONFIG_USER_ONLY |
2a47df95 PM |
5550 | /* Unlike the other EL2-related AT operations, these must |
5551 | * UNDEF from EL3 if EL2 is not implemented, which is why we | |
5552 | * define them here rather than with the rest of the AT ops. | |
5553 | */ | |
5554 | { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, | |
5555 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
5556 | .access = PL2_W, .accessfn = at_s1e2_access, | |
696ba377 RH |
5557 | .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, |
5558 | .writefn = ats_write64 }, | |
2a47df95 PM |
5559 | { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, |
5560 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | |
5561 | .access = PL2_W, .accessfn = at_s1e2_access, | |
696ba377 RH |
5562 | .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, |
5563 | .writefn = ats_write64 }, | |
14db7fe0 PM |
5564 | /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE |
5565 | * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 | |
5566 | * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose | |
5567 | * to behave as if SCR.NS was 1. | |
5568 | */ | |
5569 | { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
5570 | .access = PL2_W, | |
0710b2fa | 5571 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
14db7fe0 PM |
5572 | { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, |
5573 | .access = PL2_W, | |
0710b2fa | 5574 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
0b6440af EI |
5575 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
5576 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
5577 | /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the | |
5578 | * reset values as IMPDEF. We choose to reset to 3 to comply with | |
5579 | * both ARMv7 and ARMv8. | |
5580 | */ | |
5581 | .access = PL2_RW, .resetvalue = 3, | |
5582 | .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, | |
edac4d8a EI |
5583 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
5584 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
5585 | .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, | |
5586 | .writefn = gt_cntvoff_write, | |
5587 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
5588 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
5589 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, | |
5590 | .writefn = gt_cntvoff_write, | |
5591 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
b0e66d95 EI |
5592 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
5593 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
5594 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
5595 | .type = ARM_CP_IO, .access = PL2_RW, | |
5596 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
5597 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
5598 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
5599 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO, | |
5600 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
5601 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
5602 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
d44ec156 | 5603 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, |
b0e66d95 EI |
5604 | .resetfn = gt_hyp_timer_reset, |
5605 | .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, | |
5606 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
5607 | .type = ARM_CP_IO, | |
5608 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
5609 | .access = PL2_RW, | |
5610 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), | |
5611 | .resetvalue = 0, | |
5612 | .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, | |
edac4d8a | 5613 | #endif |
59e05530 EI |
5614 | { .name = "HPFAR", .state = ARM_CP_STATE_AA32, |
5615 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
5616 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
5617 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
5618 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, | |
5619 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
5620 | .access = PL2_RW, | |
5621 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
2a5a9abd AF |
5622 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
5623 | .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
5624 | .access = PL2_RW, | |
5625 | .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, | |
3b685ba7 EI |
5626 | }; |
5627 | ||
ce4afed8 PM |
5628 | static const ARMCPRegInfo el2_v8_cp_reginfo[] = { |
5629 | { .name = "HCR2", .state = ARM_CP_STATE_AA32, | |
89430fc6 | 5630 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
5631 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, |
5632 | .access = PL2_RW, | |
5633 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2), | |
5634 | .writefn = hcr_writehigh }, | |
ce4afed8 PM |
5635 | }; |
5636 | ||
e9152ee9 RDC |
5637 | static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5638 | bool isread) | |
5639 | { | |
5640 | if (arm_current_el(env) == 3 || arm_is_secure_below_el3(env)) { | |
5641 | return CP_ACCESS_OK; | |
5642 | } | |
5643 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
5644 | } | |
5645 | ||
5646 | static const ARMCPRegInfo el2_sec_cp_reginfo[] = { | |
5647 | { .name = "VSTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
5648 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 0, | |
5649 | .access = PL2_RW, .accessfn = sel2_access, | |
5650 | .fieldoffset = offsetof(CPUARMState, cp15.vsttbr_el2) }, | |
5651 | { .name = "VSTCR_EL2", .state = ARM_CP_STATE_AA64, | |
5652 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2, | |
5653 | .access = PL2_RW, .accessfn = sel2_access, | |
5654 | .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) }, | |
e9152ee9 RDC |
5655 | }; |
5656 | ||
2f027fc5 PM |
5657 | static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5658 | bool isread) | |
5659 | { | |
5660 | /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. | |
926c1b97 | 5661 | * At Secure EL1 it traps to EL3 or EL2. |
2f027fc5 PM |
5662 | */ |
5663 | if (arm_current_el(env) == 3) { | |
5664 | return CP_ACCESS_OK; | |
5665 | } | |
5666 | if (arm_is_secure_below_el3(env)) { | |
926c1b97 RDC |
5667 | if (env->cp15.scr_el3 & SCR_EEL2) { |
5668 | return CP_ACCESS_TRAP_EL2; | |
5669 | } | |
2f027fc5 PM |
5670 | return CP_ACCESS_TRAP_EL3; |
5671 | } | |
5672 | /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ | |
5673 | if (isread) { | |
5674 | return CP_ACCESS_OK; | |
5675 | } | |
5676 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
5677 | } | |
5678 | ||
60fb1a87 GB |
5679 | static const ARMCPRegInfo el3_cp_reginfo[] = { |
5680 | { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, | |
5681 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, | |
5682 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), | |
10d0ef3e | 5683 | .resetfn = scr_reset, .writefn = scr_write }, |
f80741d1 | 5684 | { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL, |
60fb1a87 | 5685 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, |
efe4a274 PM |
5686 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
5687 | .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), | |
b061a82b | 5688 | .writefn = scr_write }, |
60fb1a87 GB |
5689 | { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, |
5690 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, | |
5691 | .access = PL3_RW, .resetvalue = 0, | |
5692 | .fieldoffset = offsetof(CPUARMState, cp15.sder) }, | |
5693 | { .name = "SDER", | |
5694 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, | |
5695 | .access = PL3_RW, .resetvalue = 0, | |
5696 | .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, | |
60fb1a87 | 5697 | { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, |
efe4a274 PM |
5698 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
5699 | .writefn = vbar_write, .resetvalue = 0, | |
60fb1a87 | 5700 | .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, |
7dd8c9af FA |
5701 | { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, |
5702 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, | |
f478847f | 5703 | .access = PL3_RW, .resetvalue = 0, |
7dd8c9af | 5704 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, |
11f136ee FA |
5705 | { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, |
5706 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, | |
6459b94c PM |
5707 | .access = PL3_RW, |
5708 | /* no .writefn needed as this can't cause an ASID change; | |
811595a2 PM |
5709 | * we must provide a .raw_writefn and .resetfn because we handle |
5710 | * reset and migration for the AArch32 TTBCR(S), which might be | |
5711 | * using mask and base_mask. | |
6459b94c | 5712 | */ |
811595a2 | 5713 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, |
11f136ee | 5714 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, |
81547d66 | 5715 | { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5716 | .type = ARM_CP_ALIAS, |
81547d66 EI |
5717 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, |
5718 | .access = PL3_RW, | |
5719 | .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, | |
f2c30f42 | 5720 | { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, |
f2c30f42 EI |
5721 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, |
5722 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, | |
63b60551 EI |
5723 | { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, |
5724 | .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, | |
5725 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, | |
81547d66 | 5726 | { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5727 | .type = ARM_CP_ALIAS, |
81547d66 | 5728 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
5729 | .access = PL3_RW, |
5730 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) }, | |
a1ba125c EI |
5731 | { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, |
5732 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, | |
5733 | .access = PL3_RW, .writefn = vbar_write, | |
5734 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), | |
5735 | .resetvalue = 0 }, | |
c6f19164 GB |
5736 | { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, |
5737 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, | |
5738 | .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, | |
5739 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, | |
4cfb8ad8 PM |
5740 | { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, |
5741 | .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, | |
5742 | .access = PL3_RW, .resetvalue = 0, | |
5743 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, | |
2179ef95 PM |
5744 | { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64, |
5745 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, | |
5746 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5747 | .resetvalue = 0 }, | |
37cd6c24 PM |
5748 | { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, |
5749 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, | |
5750 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5751 | .resetvalue = 0 }, | |
5752 | { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, | |
5753 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, | |
5754 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5755 | .resetvalue = 0 }, | |
43efaa33 PM |
5756 | { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, |
5757 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, | |
5758 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5759 | .writefn = tlbi_aa64_alle3is_write }, | |
5760 | { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, | |
5761 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, | |
5762 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5763 | .writefn = tlbi_aa64_vae3is_write }, | |
5764 | { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, | |
5765 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, | |
5766 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5767 | .writefn = tlbi_aa64_vae3is_write }, | |
5768 | { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, | |
5769 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, | |
5770 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5771 | .writefn = tlbi_aa64_alle3_write }, | |
5772 | { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, | |
5773 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, | |
5774 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5775 | .writefn = tlbi_aa64_vae3_write }, | |
5776 | { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, | |
5777 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, | |
5778 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5779 | .writefn = tlbi_aa64_vae3_write }, | |
0f1a3b24 FA |
5780 | }; |
5781 | ||
e2cce18f RH |
5782 | #ifndef CONFIG_USER_ONLY |
5783 | /* Test if system register redirection is to occur in the current state. */ | |
5784 | static bool redirect_for_e2h(CPUARMState *env) | |
5785 | { | |
5786 | return arm_current_el(env) == 2 && (arm_hcr_el2_eff(env) & HCR_E2H); | |
5787 | } | |
5788 | ||
5789 | static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5790 | { | |
5791 | CPReadFn *readfn; | |
5792 | ||
5793 | if (redirect_for_e2h(env)) { | |
5794 | /* Switch to the saved EL2 version of the register. */ | |
5795 | ri = ri->opaque; | |
5796 | readfn = ri->readfn; | |
5797 | } else { | |
5798 | readfn = ri->orig_readfn; | |
5799 | } | |
5800 | if (readfn == NULL) { | |
5801 | readfn = raw_read; | |
5802 | } | |
5803 | return readfn(env, ri); | |
5804 | } | |
5805 | ||
5806 | static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5807 | uint64_t value) | |
5808 | { | |
5809 | CPWriteFn *writefn; | |
5810 | ||
5811 | if (redirect_for_e2h(env)) { | |
5812 | /* Switch to the saved EL2 version of the register. */ | |
5813 | ri = ri->opaque; | |
5814 | writefn = ri->writefn; | |
5815 | } else { | |
5816 | writefn = ri->orig_writefn; | |
5817 | } | |
5818 | if (writefn == NULL) { | |
5819 | writefn = raw_write; | |
5820 | } | |
5821 | writefn(env, ri, value); | |
5822 | } | |
5823 | ||
5824 | static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) | |
5825 | { | |
5826 | struct E2HAlias { | |
5827 | uint32_t src_key, dst_key, new_key; | |
5828 | const char *src_name, *dst_name, *new_name; | |
5829 | bool (*feature)(const ARMISARegisters *id); | |
5830 | }; | |
5831 | ||
5832 | #define K(op0, op1, crn, crm, op2) \ | |
5833 | ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) | |
5834 | ||
5835 | static const struct E2HAlias aliases[] = { | |
5836 | { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), | |
5837 | "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, | |
5838 | { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), | |
5839 | "CPACR", "CPTR_EL2", "CPACR_EL12" }, | |
5840 | { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), | |
5841 | "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, | |
5842 | { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), | |
5843 | "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, | |
5844 | { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), | |
5845 | "TCR_EL1", "TCR_EL2", "TCR_EL12" }, | |
5846 | { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), | |
5847 | "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, | |
5848 | { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), | |
5849 | "ELR_EL1", "ELR_EL2", "ELR_EL12" }, | |
5850 | { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0), | |
5851 | "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" }, | |
5852 | { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1), | |
5853 | "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" }, | |
5854 | { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0), | |
5855 | "ESR_EL1", "ESR_EL2", "ESR_EL12" }, | |
5856 | { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0), | |
5857 | "FAR_EL1", "FAR_EL2", "FAR_EL12" }, | |
5858 | { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), | |
5859 | "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, | |
5860 | { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), | |
5861 | "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" }, | |
5862 | { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), | |
5863 | "VBAR", "VBAR_EL2", "VBAR_EL12" }, | |
5864 | { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), | |
5865 | "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, | |
5866 | { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), | |
5867 | "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" }, | |
5868 | ||
5869 | /* | |
5870 | * Note that redirection of ZCR is mentioned in the description | |
5871 | * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but | |
5872 | * not in the summary table. | |
5873 | */ | |
5874 | { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), | |
5875 | "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, | |
5876 | ||
4b779ceb RH |
5877 | { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), |
5878 | "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, | |
5879 | ||
7cb1e618 RH |
5880 | { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), |
5881 | "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", | |
5882 | isar_feature_aa64_scxtnum }, | |
5883 | ||
e2cce18f RH |
5884 | /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ |
5885 | /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ | |
5886 | }; | |
5887 | #undef K | |
5888 | ||
5889 | size_t i; | |
5890 | ||
5891 | for (i = 0; i < ARRAY_SIZE(aliases); i++) { | |
5892 | const struct E2HAlias *a = &aliases[i]; | |
9da35a40 | 5893 | ARMCPRegInfo *src_reg, *dst_reg, *new_reg; |
9da35a40 | 5894 | bool ok; |
e2cce18f RH |
5895 | |
5896 | if (a->feature && !a->feature(&cpu->isar)) { | |
5897 | continue; | |
5898 | } | |
5899 | ||
5860362d RH |
5900 | src_reg = g_hash_table_lookup(cpu->cp_regs, |
5901 | (gpointer)(uintptr_t)a->src_key); | |
5902 | dst_reg = g_hash_table_lookup(cpu->cp_regs, | |
5903 | (gpointer)(uintptr_t)a->dst_key); | |
e2cce18f RH |
5904 | g_assert(src_reg != NULL); |
5905 | g_assert(dst_reg != NULL); | |
5906 | ||
5907 | /* Cross-compare names to detect typos in the keys. */ | |
5908 | g_assert(strcmp(src_reg->name, a->src_name) == 0); | |
5909 | g_assert(strcmp(dst_reg->name, a->dst_name) == 0); | |
5910 | ||
5911 | /* None of the core system registers use opaque; we will. */ | |
5912 | g_assert(src_reg->opaque == NULL); | |
5913 | ||
5914 | /* Create alias before redirection so we dup the right data. */ | |
9da35a40 | 5915 | new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo)); |
9da35a40 RH |
5916 | |
5917 | new_reg->name = a->new_name; | |
5918 | new_reg->type |= ARM_CP_ALIAS; | |
5919 | /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ | |
5920 | new_reg->access &= PL2_RW | PL3_RW; | |
5921 | ||
5860362d RH |
5922 | ok = g_hash_table_insert(cpu->cp_regs, |
5923 | (gpointer)(uintptr_t)a->new_key, new_reg); | |
9da35a40 | 5924 | g_assert(ok); |
e2cce18f RH |
5925 | |
5926 | src_reg->opaque = dst_reg; | |
5927 | src_reg->orig_readfn = src_reg->readfn ?: raw_read; | |
5928 | src_reg->orig_writefn = src_reg->writefn ?: raw_write; | |
5929 | if (!src_reg->raw_readfn) { | |
5930 | src_reg->raw_readfn = raw_read; | |
5931 | } | |
5932 | if (!src_reg->raw_writefn) { | |
5933 | src_reg->raw_writefn = raw_write; | |
5934 | } | |
5935 | src_reg->readfn = el2_e2h_read; | |
5936 | src_reg->writefn = el2_e2h_write; | |
5937 | } | |
5938 | } | |
5939 | #endif | |
5940 | ||
3f208fd7 PM |
5941 | static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5942 | bool isread) | |
7da845b0 | 5943 | { |
97475a89 RH |
5944 | int cur_el = arm_current_el(env); |
5945 | ||
5946 | if (cur_el < 2) { | |
5947 | uint64_t hcr = arm_hcr_el2_eff(env); | |
5948 | ||
5949 | if (cur_el == 0) { | |
5950 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
5951 | if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) { | |
5952 | return CP_ACCESS_TRAP_EL2; | |
5953 | } | |
5954 | } else { | |
5955 | if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) { | |
5956 | return CP_ACCESS_TRAP; | |
5957 | } | |
5958 | if (hcr & HCR_TID2) { | |
5959 | return CP_ACCESS_TRAP_EL2; | |
5960 | } | |
5961 | } | |
5962 | } else if (hcr & HCR_TID2) { | |
5963 | return CP_ACCESS_TRAP_EL2; | |
5964 | } | |
7da845b0 | 5965 | } |
630fcd4d MZ |
5966 | |
5967 | if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) { | |
5968 | return CP_ACCESS_TRAP_EL2; | |
5969 | } | |
5970 | ||
7da845b0 PM |
5971 | return CP_ACCESS_OK; |
5972 | } | |
5973 | ||
1424ca8d DM |
5974 | static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5975 | uint64_t value) | |
5976 | { | |
5977 | /* Writes to OSLAR_EL1 may update the OS lock status, which can be | |
5978 | * read via a bit in OSLSR_EL1. | |
5979 | */ | |
5980 | int oslock; | |
5981 | ||
5982 | if (ri->state == ARM_CP_STATE_AA32) { | |
5983 | oslock = (value == 0xC5ACCE55); | |
5984 | } else { | |
5985 | oslock = value & 1; | |
5986 | } | |
5987 | ||
5988 | env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); | |
5989 | } | |
5990 | ||
50300698 | 5991 | static const ARMCPRegInfo debug_cp_reginfo[] = { |
50300698 | 5992 | /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped |
10aae104 PM |
5993 | * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; |
5994 | * unlike DBGDRAR it is never accessible from EL0. | |
5995 | * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 | |
5996 | * accessor. | |
50300698 PM |
5997 | */ |
5998 | { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
91b0a238 PM |
5999 | .access = PL0_R, .accessfn = access_tdra, |
6000 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
10aae104 PM |
6001 | { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, |
6002 | .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, | |
91b0a238 PM |
6003 | .access = PL1_R, .accessfn = access_tdra, |
6004 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
50300698 | 6005 | { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
91b0a238 PM |
6006 | .access = PL0_R, .accessfn = access_tdra, |
6007 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
17a9eb53 | 6008 | /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ |
10aae104 PM |
6009 | { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, |
6010 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
d6c8cf81 | 6011 | .access = PL1_RW, .accessfn = access_tda, |
0e5e8935 PM |
6012 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), |
6013 | .resetvalue = 0 }, | |
49a6f3bf NH |
6014 | /* |
6015 | * MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external | |
6016 | * Debug Communication Channel is not implemented. | |
6017 | */ | |
6018 | { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64, | |
6019 | .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0, | |
6020 | .access = PL0_R, .accessfn = access_tda, | |
6021 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6022 | /* | |
6023 | * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as | |
6024 | * it is unlikely a guest will care. | |
5e8b12ff PM |
6025 | * We don't implement the configurable EL0 access. |
6026 | */ | |
49a6f3bf NH |
6027 | { .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32, |
6028 | .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
7a0e58fa | 6029 | .type = ARM_CP_ALIAS, |
d6c8cf81 | 6030 | .access = PL1_R, .accessfn = access_tda, |
b061a82b | 6031 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, |
10aae104 PM |
6032 | { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, |
6033 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, | |
1424ca8d | 6034 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
187f678d | 6035 | .accessfn = access_tdosa, |
1424ca8d DM |
6036 | .writefn = oslar_write }, |
6037 | { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, | |
6038 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, | |
6039 | .access = PL1_R, .resetvalue = 10, | |
187f678d | 6040 | .accessfn = access_tdosa, |
1424ca8d | 6041 | .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, |
5e8b12ff PM |
6042 | /* Dummy OSDLR_EL1: 32-bit Linux will read this */ |
6043 | { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, | |
6044 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, | |
187f678d PM |
6045 | .access = PL1_RW, .accessfn = access_tdosa, |
6046 | .type = ARM_CP_NOP }, | |
5e8b12ff PM |
6047 | /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't |
6048 | * implement vector catch debug events yet. | |
6049 | */ | |
6050 | { .name = "DBGVCR", | |
6051 | .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
d6c8cf81 PM |
6052 | .access = PL1_RW, .accessfn = access_tda, |
6053 | .type = ARM_CP_NOP }, | |
4d2ec4da PM |
6054 | /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor |
6055 | * to save and restore a 32-bit guest's DBGVCR) | |
6056 | */ | |
6057 | { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, | |
6058 | .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, | |
6059 | .access = PL2_RW, .accessfn = access_tda, | |
696ba377 | 6060 | .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, |
5dbdc434 PM |
6061 | /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications |
6062 | * Channel but Linux may try to access this register. The 32-bit | |
6063 | * alias is DBGDCCINT. | |
6064 | */ | |
6065 | { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, | |
6066 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
6067 | .access = PL1_RW, .accessfn = access_tda, | |
6068 | .type = ARM_CP_NOP }, | |
50300698 PM |
6069 | }; |
6070 | ||
6071 | static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | |
6072 | /* 64 bit access versions of the (dummy) debug registers */ | |
6073 | { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, | |
6074 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
6075 | { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | |
6076 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
50300698 PM |
6077 | }; |
6078 | ||
58e93b48 RH |
6079 | /* |
6080 | * Check for traps to RAS registers, which are controlled | |
6081 | * by HCR_EL2.TERR and SCR_EL3.TERR. | |
6082 | */ | |
6083 | static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri, | |
6084 | bool isread) | |
6085 | { | |
6086 | int el = arm_current_el(env); | |
6087 | ||
6088 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) { | |
6089 | return CP_ACCESS_TRAP_EL2; | |
6090 | } | |
6091 | if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) { | |
6092 | return CP_ACCESS_TRAP_EL3; | |
6093 | } | |
6094 | return CP_ACCESS_OK; | |
6095 | } | |
6096 | ||
6097 | static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
6098 | { | |
6099 | int el = arm_current_el(env); | |
6100 | ||
6101 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { | |
6102 | return env->cp15.vdisr_el2; | |
6103 | } | |
6104 | if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { | |
6105 | return 0; /* RAZ/WI */ | |
6106 | } | |
6107 | return env->cp15.disr_el1; | |
6108 | } | |
6109 | ||
6110 | static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
6111 | { | |
6112 | int el = arm_current_el(env); | |
6113 | ||
6114 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { | |
6115 | env->cp15.vdisr_el2 = val; | |
6116 | return; | |
6117 | } | |
6118 | if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { | |
6119 | return; /* RAZ/WI */ | |
6120 | } | |
6121 | env->cp15.disr_el1 = val; | |
6122 | } | |
6123 | ||
6124 | /* | |
6125 | * Minimal RAS implementation with no Error Records. | |
6126 | * Which means that all of the Error Record registers: | |
6127 | * ERXADDR_EL1 | |
6128 | * ERXCTLR_EL1 | |
6129 | * ERXFR_EL1 | |
6130 | * ERXMISC0_EL1 | |
6131 | * ERXMISC1_EL1 | |
6132 | * ERXMISC2_EL1 | |
6133 | * ERXMISC3_EL1 | |
6134 | * ERXPFGCDN_EL1 (RASv1p1) | |
6135 | * ERXPFGCTL_EL1 (RASv1p1) | |
6136 | * ERXPFGF_EL1 (RASv1p1) | |
6137 | * ERXSTATUS_EL1 | |
6138 | * and | |
6139 | * ERRSELR_EL1 | |
6140 | * may generate UNDEFINED, which is the effect we get by not | |
6141 | * listing them at all. | |
6142 | */ | |
6143 | static const ARMCPRegInfo minimal_ras_reginfo[] = { | |
6144 | { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH, | |
6145 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1, | |
6146 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1), | |
6147 | .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write }, | |
6148 | { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
6149 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0, | |
6150 | .access = PL1_R, .accessfn = access_terr, | |
6151 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6152 | { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH, | |
6153 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1, | |
6154 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) }, | |
6155 | { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH, | |
6156 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3, | |
6157 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) }, | |
6158 | }; | |
6159 | ||
397d922c RH |
6160 | /* |
6161 | * Return the exception level to which exceptions should be taken | |
6162 | * via SVEAccessTrap. This excludes the check for whether the exception | |
6163 | * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily | |
6164 | * be found by testing 0 < fp_exception_el < sve_exception_el. | |
6165 | * | |
6166 | * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the | |
6167 | * pseudocode does *not* separate out the FP trap checks, but has them | |
6168 | * all in one function. | |
5be5e8ed | 6169 | */ |
ced31551 | 6170 | int sve_exception_el(CPUARMState *env, int el) |
5be5e8ed RH |
6171 | { |
6172 | #ifndef CONFIG_USER_ONLY | |
aa4451b6 | 6173 | if (el <= 1 && !el_is_in_host(env, el)) { |
fab8ad39 | 6174 | switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, ZEN)) { |
7701cee5 RH |
6175 | case 1: |
6176 | if (el != 0) { | |
6177 | break; | |
6178 | } | |
6179 | /* fall through */ | |
6180 | case 0: | |
6181 | case 2: | |
61a8c23a | 6182 | return 1; |
5be5e8ed | 6183 | } |
5be5e8ed RH |
6184 | } |
6185 | ||
7d38cb92 RH |
6186 | if (el <= 2 && arm_is_el2_enabled(env)) { |
6187 | /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */ | |
6188 | if (env->cp15.hcr_el2 & HCR_E2H) { | |
fab8ad39 | 6189 | switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, ZEN)) { |
d5a6fa2d | 6190 | case 1: |
7d38cb92 | 6191 | if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) { |
d5a6fa2d RH |
6192 | break; |
6193 | } | |
6194 | /* fall through */ | |
6195 | case 0: | |
6196 | case 2: | |
6197 | return 2; | |
6198 | } | |
7d38cb92 | 6199 | } else { |
fab8ad39 | 6200 | if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) { |
d5a6fa2d RH |
6201 | return 2; |
6202 | } | |
60eed086 | 6203 | } |
5be5e8ed RH |
6204 | } |
6205 | ||
60eed086 RH |
6206 | /* CPTR_EL3. Since EZ is negative we must check for EL3. */ |
6207 | if (arm_feature(env, ARM_FEATURE_EL3) | |
fab8ad39 | 6208 | && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, EZ)) { |
5be5e8ed RH |
6209 | return 3; |
6210 | } | |
6211 | #endif | |
6212 | return 0; | |
6213 | } | |
6214 | ||
0ab5953b RH |
6215 | /* |
6216 | * Given that SVE is enabled, return the vector length for EL. | |
6217 | */ | |
5ef3cc56 | 6218 | uint32_t sve_vqm1_for_el(CPUARMState *env, int el) |
0ab5953b | 6219 | { |
2fc0cc0e | 6220 | ARMCPU *cpu = env_archcpu(env); |
9b5f4225 | 6221 | uint32_t len = cpu->sve_max_vq - 1; |
0ab5953b | 6222 | |
c6225beb | 6223 | if (el <= 1 && !el_is_in_host(env, el)) { |
9b5f4225 | 6224 | len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[1]); |
0ab5953b | 6225 | } |
6a02a732 | 6226 | if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) { |
9b5f4225 | 6227 | len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[2]); |
0ab5953b | 6228 | } |
6a02a732 | 6229 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
9b5f4225 | 6230 | len = MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[3]); |
0ab5953b | 6231 | } |
0df9142d | 6232 | |
886902ec RH |
6233 | len = 31 - clz32(cpu->sve_vq_map & MAKE_64BIT_MASK(0, len + 1)); |
6234 | return len; | |
0ab5953b RH |
6235 | } |
6236 | ||
5be5e8ed RH |
6237 | static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
6238 | uint64_t value) | |
6239 | { | |
0ab5953b | 6240 | int cur_el = arm_current_el(env); |
5ef3cc56 | 6241 | int old_len = sve_vqm1_for_el(env, cur_el); |
0ab5953b RH |
6242 | int new_len; |
6243 | ||
5be5e8ed | 6244 | /* Bits other than [3:0] are RAZ/WI. */ |
7b351d98 | 6245 | QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16); |
5be5e8ed | 6246 | raw_write(env, ri, value & 0xf); |
0ab5953b RH |
6247 | |
6248 | /* | |
6249 | * Because we arrived here, we know both FP and SVE are enabled; | |
6250 | * otherwise we would have trapped access to the ZCR_ELn register. | |
6251 | */ | |
5ef3cc56 | 6252 | new_len = sve_vqm1_for_el(env, cur_el); |
0ab5953b RH |
6253 | if (new_len < old_len) { |
6254 | aarch64_sve_narrow_vq(env, new_len + 1); | |
6255 | } | |
5be5e8ed RH |
6256 | } |
6257 | ||
60360d82 RH |
6258 | static const ARMCPRegInfo zcr_reginfo[] = { |
6259 | { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | |
6260 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | |
6261 | .access = PL1_RW, .type = ARM_CP_SVE, | |
6262 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), | |
6263 | .writefn = zcr_write, .raw_writefn = raw_write }, | |
6264 | { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | |
6265 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | |
6266 | .access = PL2_RW, .type = ARM_CP_SVE, | |
6267 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), | |
6268 | .writefn = zcr_write, .raw_writefn = raw_write }, | |
6269 | { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | |
6270 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | |
6271 | .access = PL3_RW, .type = ARM_CP_SVE, | |
6272 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), | |
6273 | .writefn = zcr_write, .raw_writefn = raw_write }, | |
5be5e8ed RH |
6274 | }; |
6275 | ||
9ee98ce8 PM |
6276 | void hw_watchpoint_update(ARMCPU *cpu, int n) |
6277 | { | |
6278 | CPUARMState *env = &cpu->env; | |
6279 | vaddr len = 0; | |
6280 | vaddr wvr = env->cp15.dbgwvr[n]; | |
6281 | uint64_t wcr = env->cp15.dbgwcr[n]; | |
6282 | int mask; | |
6283 | int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; | |
6284 | ||
6285 | if (env->cpu_watchpoint[n]) { | |
6286 | cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); | |
6287 | env->cpu_watchpoint[n] = NULL; | |
6288 | } | |
6289 | ||
8b7a5bbe | 6290 | if (!FIELD_EX64(wcr, DBGWCR, E)) { |
9ee98ce8 PM |
6291 | /* E bit clear : watchpoint disabled */ |
6292 | return; | |
6293 | } | |
6294 | ||
8b7a5bbe | 6295 | switch (FIELD_EX64(wcr, DBGWCR, LSC)) { |
9ee98ce8 PM |
6296 | case 0: |
6297 | /* LSC 00 is reserved and must behave as if the wp is disabled */ | |
6298 | return; | |
6299 | case 1: | |
6300 | flags |= BP_MEM_READ; | |
6301 | break; | |
6302 | case 2: | |
6303 | flags |= BP_MEM_WRITE; | |
6304 | break; | |
6305 | case 3: | |
6306 | flags |= BP_MEM_ACCESS; | |
6307 | break; | |
6308 | } | |
6309 | ||
6310 | /* Attempts to use both MASK and BAS fields simultaneously are | |
6311 | * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, | |
6312 | * thus generating a watchpoint for every byte in the masked region. | |
6313 | */ | |
8b7a5bbe | 6314 | mask = FIELD_EX64(wcr, DBGWCR, MASK); |
9ee98ce8 PM |
6315 | if (mask == 1 || mask == 2) { |
6316 | /* Reserved values of MASK; we must act as if the mask value was | |
6317 | * some non-reserved value, or as if the watchpoint were disabled. | |
6318 | * We choose the latter. | |
6319 | */ | |
6320 | return; | |
6321 | } else if (mask) { | |
6322 | /* Watchpoint covers an aligned area up to 2GB in size */ | |
6323 | len = 1ULL << mask; | |
6324 | /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE | |
6325 | * whether the watchpoint fires when the unmasked bits match; we opt | |
6326 | * to generate the exceptions. | |
6327 | */ | |
6328 | wvr &= ~(len - 1); | |
6329 | } else { | |
6330 | /* Watchpoint covers bytes defined by the byte address select bits */ | |
8b7a5bbe | 6331 | int bas = FIELD_EX64(wcr, DBGWCR, BAS); |
9ee98ce8 PM |
6332 | int basstart; |
6333 | ||
9ee98ce8 PM |
6334 | if (extract64(wvr, 2, 1)) { |
6335 | /* Deprecated case of an only 4-aligned address. BAS[7:4] are | |
6336 | * ignored, and BAS[3:0] define which bytes to watch. | |
6337 | */ | |
6338 | bas &= 0xf; | |
6339 | } | |
ae1111d4 RH |
6340 | |
6341 | if (bas == 0) { | |
6342 | /* This must act as if the watchpoint is disabled */ | |
6343 | return; | |
6344 | } | |
6345 | ||
9ee98ce8 PM |
6346 | /* The BAS bits are supposed to be programmed to indicate a contiguous |
6347 | * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether | |
6348 | * we fire for each byte in the word/doubleword addressed by the WVR. | |
6349 | * We choose to ignore any non-zero bits after the first range of 1s. | |
6350 | */ | |
6351 | basstart = ctz32(bas); | |
6352 | len = cto32(bas >> basstart); | |
6353 | wvr += basstart; | |
6354 | } | |
6355 | ||
6356 | cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, | |
6357 | &env->cpu_watchpoint[n]); | |
6358 | } | |
6359 | ||
6360 | void hw_watchpoint_update_all(ARMCPU *cpu) | |
6361 | { | |
6362 | int i; | |
6363 | CPUARMState *env = &cpu->env; | |
6364 | ||
6365 | /* Completely clear out existing QEMU watchpoints and our array, to | |
6366 | * avoid possible stale entries following migration load. | |
6367 | */ | |
6368 | cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); | |
6369 | memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); | |
6370 | ||
6371 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { | |
6372 | hw_watchpoint_update(cpu, i); | |
6373 | } | |
6374 | } | |
6375 | ||
6376 | static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6377 | uint64_t value) | |
6378 | { | |
2fc0cc0e | 6379 | ARMCPU *cpu = env_archcpu(env); |
9ee98ce8 PM |
6380 | int i = ri->crm; |
6381 | ||
777ab8d8 | 6382 | /* |
9ee98ce8 | 6383 | * Bits [1:0] are RES0. |
777ab8d8 RH |
6384 | * |
6385 | * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA) | |
6386 | * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if | |
6387 | * they contain the value written. It is CONSTRAINED UNPREDICTABLE | |
6388 | * whether the RESS bits are ignored when comparing an address. | |
6389 | * | |
6390 | * Therefore we are allowed to compare the entire register, which lets | |
6391 | * us avoid considering whether or not FEAT_LVA is actually enabled. | |
9ee98ce8 | 6392 | */ |
777ab8d8 | 6393 | value &= ~3ULL; |
9ee98ce8 PM |
6394 | |
6395 | raw_write(env, ri, value); | |
6396 | hw_watchpoint_update(cpu, i); | |
6397 | } | |
6398 | ||
6399 | static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6400 | uint64_t value) | |
6401 | { | |
2fc0cc0e | 6402 | ARMCPU *cpu = env_archcpu(env); |
9ee98ce8 PM |
6403 | int i = ri->crm; |
6404 | ||
6405 | raw_write(env, ri, value); | |
6406 | hw_watchpoint_update(cpu, i); | |
6407 | } | |
6408 | ||
46747d15 PM |
6409 | void hw_breakpoint_update(ARMCPU *cpu, int n) |
6410 | { | |
6411 | CPUARMState *env = &cpu->env; | |
6412 | uint64_t bvr = env->cp15.dbgbvr[n]; | |
6413 | uint64_t bcr = env->cp15.dbgbcr[n]; | |
6414 | vaddr addr; | |
6415 | int bt; | |
6416 | int flags = BP_CPU; | |
6417 | ||
6418 | if (env->cpu_breakpoint[n]) { | |
6419 | cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); | |
6420 | env->cpu_breakpoint[n] = NULL; | |
6421 | } | |
6422 | ||
6423 | if (!extract64(bcr, 0, 1)) { | |
6424 | /* E bit clear : watchpoint disabled */ | |
6425 | return; | |
6426 | } | |
6427 | ||
6428 | bt = extract64(bcr, 20, 4); | |
6429 | ||
6430 | switch (bt) { | |
6431 | case 4: /* unlinked address mismatch (reserved if AArch64) */ | |
6432 | case 5: /* linked address mismatch (reserved if AArch64) */ | |
6433 | qemu_log_mask(LOG_UNIMP, | |
0221c8fd | 6434 | "arm: address mismatch breakpoint types not implemented\n"); |
46747d15 PM |
6435 | return; |
6436 | case 0: /* unlinked address match */ | |
6437 | case 1: /* linked address match */ | |
6438 | { | |
777ab8d8 RH |
6439 | /* |
6440 | * Bits [1:0] are RES0. | |
6441 | * | |
6442 | * It is IMPLEMENTATION DEFINED whether bits [63:49] | |
6443 | * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit | |
6444 | * of the VA field ([48] or [52] for FEAT_LVA), or whether the | |
6445 | * value is read as written. It is CONSTRAINED UNPREDICTABLE | |
6446 | * whether the RESS bits are ignored when comparing an address. | |
6447 | * Therefore we are allowed to compare the entire register, which | |
6448 | * lets us avoid considering whether FEAT_LVA is actually enabled. | |
6449 | * | |
6450 | * The BAS field is used to allow setting breakpoints on 16-bit | |
6451 | * wide instructions; it is CONSTRAINED UNPREDICTABLE whether | |
46747d15 PM |
6452 | * a bp will fire if the addresses covered by the bp and the addresses |
6453 | * covered by the insn overlap but the insn doesn't start at the | |
6454 | * start of the bp address range. We choose to require the insn and | |
6455 | * the bp to have the same address. The constraints on writing to | |
6456 | * BAS enforced in dbgbcr_write mean we have only four cases: | |
6457 | * 0b0000 => no breakpoint | |
6458 | * 0b0011 => breakpoint on addr | |
6459 | * 0b1100 => breakpoint on addr + 2 | |
6460 | * 0b1111 => breakpoint on addr | |
6461 | * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). | |
6462 | */ | |
6463 | int bas = extract64(bcr, 5, 4); | |
777ab8d8 | 6464 | addr = bvr & ~3ULL; |
46747d15 PM |
6465 | if (bas == 0) { |
6466 | return; | |
6467 | } | |
6468 | if (bas == 0xc) { | |
6469 | addr += 2; | |
6470 | } | |
6471 | break; | |
6472 | } | |
6473 | case 2: /* unlinked context ID match */ | |
6474 | case 8: /* unlinked VMID match (reserved if no EL2) */ | |
6475 | case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ | |
6476 | qemu_log_mask(LOG_UNIMP, | |
0221c8fd | 6477 | "arm: unlinked context breakpoint types not implemented\n"); |
46747d15 PM |
6478 | return; |
6479 | case 9: /* linked VMID match (reserved if no EL2) */ | |
6480 | case 11: /* linked context ID and VMID match (reserved if no EL2) */ | |
6481 | case 3: /* linked context ID match */ | |
6482 | default: | |
6483 | /* We must generate no events for Linked context matches (unless | |
6484 | * they are linked to by some other bp/wp, which is handled in | |
6485 | * updates for the linking bp/wp). We choose to also generate no events | |
6486 | * for reserved values. | |
6487 | */ | |
6488 | return; | |
6489 | } | |
6490 | ||
6491 | cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); | |
6492 | } | |
6493 | ||
6494 | void hw_breakpoint_update_all(ARMCPU *cpu) | |
6495 | { | |
6496 | int i; | |
6497 | CPUARMState *env = &cpu->env; | |
6498 | ||
6499 | /* Completely clear out existing QEMU breakpoints and our array, to | |
6500 | * avoid possible stale entries following migration load. | |
6501 | */ | |
6502 | cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); | |
6503 | memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); | |
6504 | ||
6505 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { | |
6506 | hw_breakpoint_update(cpu, i); | |
6507 | } | |
6508 | } | |
6509 | ||
6510 | static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6511 | uint64_t value) | |
6512 | { | |
2fc0cc0e | 6513 | ARMCPU *cpu = env_archcpu(env); |
46747d15 PM |
6514 | int i = ri->crm; |
6515 | ||
6516 | raw_write(env, ri, value); | |
6517 | hw_breakpoint_update(cpu, i); | |
6518 | } | |
6519 | ||
6520 | static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6521 | uint64_t value) | |
6522 | { | |
2fc0cc0e | 6523 | ARMCPU *cpu = env_archcpu(env); |
46747d15 PM |
6524 | int i = ri->crm; |
6525 | ||
6526 | /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only | |
6527 | * copy of BAS[0]. | |
6528 | */ | |
6529 | value = deposit64(value, 6, 1, extract64(value, 5, 1)); | |
6530 | value = deposit64(value, 8, 1, extract64(value, 7, 1)); | |
6531 | ||
6532 | raw_write(env, ri, value); | |
6533 | hw_breakpoint_update(cpu, i); | |
6534 | } | |
6535 | ||
50300698 | 6536 | static void define_debug_regs(ARMCPU *cpu) |
0b45451e | 6537 | { |
50300698 PM |
6538 | /* Define v7 and v8 architectural debug registers. |
6539 | * These are just dummy implementations for now. | |
0b45451e PM |
6540 | */ |
6541 | int i; | |
3ff6fc91 | 6542 | int wrps, brps, ctx_cmps; |
54a78718 RH |
6543 | |
6544 | /* | |
6545 | * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot | |
6546 | * use AArch32. Given that bit 15 is RES1, if the value is 0 then | |
6547 | * the register must not exist for this cpu. | |
6548 | */ | |
6549 | if (cpu->isar.dbgdidr != 0) { | |
6550 | ARMCPRegInfo dbgdidr = { | |
6551 | .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, | |
6552 | .opc1 = 0, .opc2 = 0, | |
6553 | .access = PL0_R, .accessfn = access_tda, | |
6554 | .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr, | |
6555 | }; | |
6556 | define_one_arm_cp_reg(cpu, &dbgdidr); | |
6557 | } | |
48eb3ae6 | 6558 | |
88ce6c6e PM |
6559 | brps = arm_num_brps(cpu); |
6560 | wrps = arm_num_wrps(cpu); | |
6561 | ctx_cmps = arm_num_ctx_cmps(cpu); | |
3ff6fc91 PM |
6562 | |
6563 | assert(ctx_cmps <= brps); | |
48eb3ae6 | 6564 | |
50300698 PM |
6565 | define_arm_cp_regs(cpu, debug_cp_reginfo); |
6566 | ||
6567 | if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { | |
6568 | define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); | |
6569 | } | |
6570 | ||
88ce6c6e | 6571 | for (i = 0; i < brps; i++) { |
e1be11a5 CH |
6572 | char *dbgbvr_el1_name = g_strdup_printf("DBGBVR%d_EL1", i); |
6573 | char *dbgbcr_el1_name = g_strdup_printf("DBGBCR%d_EL1", i); | |
0b45451e | 6574 | ARMCPRegInfo dbgregs[] = { |
e1be11a5 | 6575 | { .name = dbgbvr_el1_name, .state = ARM_CP_STATE_BOTH, |
10aae104 | 6576 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, |
d6c8cf81 | 6577 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
6578 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), |
6579 | .writefn = dbgbvr_write, .raw_writefn = raw_write | |
6580 | }, | |
e1be11a5 | 6581 | { .name = dbgbcr_el1_name, .state = ARM_CP_STATE_BOTH, |
10aae104 | 6582 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, |
d6c8cf81 | 6583 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
6584 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), |
6585 | .writefn = dbgbcr_write, .raw_writefn = raw_write | |
6586 | }, | |
48eb3ae6 PM |
6587 | }; |
6588 | define_arm_cp_regs(cpu, dbgregs); | |
e1be11a5 CH |
6589 | g_free(dbgbvr_el1_name); |
6590 | g_free(dbgbcr_el1_name); | |
48eb3ae6 PM |
6591 | } |
6592 | ||
88ce6c6e | 6593 | for (i = 0; i < wrps; i++) { |
e1be11a5 CH |
6594 | char *dbgwvr_el1_name = g_strdup_printf("DBGWVR%d_EL1", i); |
6595 | char *dbgwcr_el1_name = g_strdup_printf("DBGWCR%d_EL1", i); | |
48eb3ae6 | 6596 | ARMCPRegInfo dbgregs[] = { |
e1be11a5 | 6597 | { .name = dbgwvr_el1_name, .state = ARM_CP_STATE_BOTH, |
10aae104 | 6598 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, |
d6c8cf81 | 6599 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
6600 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), |
6601 | .writefn = dbgwvr_write, .raw_writefn = raw_write | |
6602 | }, | |
e1be11a5 | 6603 | { .name = dbgwcr_el1_name, .state = ARM_CP_STATE_BOTH, |
10aae104 | 6604 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, |
d6c8cf81 | 6605 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
6606 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), |
6607 | .writefn = dbgwcr_write, .raw_writefn = raw_write | |
6608 | }, | |
0b45451e PM |
6609 | }; |
6610 | define_arm_cp_regs(cpu, dbgregs); | |
e1be11a5 CH |
6611 | g_free(dbgwvr_el1_name); |
6612 | g_free(dbgwcr_el1_name); | |
0b45451e PM |
6613 | } |
6614 | } | |
6615 | ||
24183fb6 PM |
6616 | static void define_pmu_regs(ARMCPU *cpu) |
6617 | { | |
6618 | /* | |
6619 | * v7 performance monitor control register: same implementor | |
6620 | * field as main ID register, and we implement four counters in | |
6621 | * addition to the cycle count register. | |
6622 | */ | |
24526bb9 | 6623 | unsigned int i, pmcrn = pmu_num_counters(&cpu->env); |
24183fb6 PM |
6624 | ARMCPRegInfo pmcr = { |
6625 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | |
6626 | .access = PL0_RW, | |
6627 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6628 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), | |
6629 | .accessfn = pmreg_access, .writefn = pmcr_write, | |
6630 | .raw_writefn = raw_write, | |
6631 | }; | |
6632 | ARMCPRegInfo pmcr64 = { | |
6633 | .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, | |
6634 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, | |
6635 | .access = PL0_RW, .accessfn = pmreg_access, | |
6636 | .type = ARM_CP_IO, | |
6637 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), | |
24526bb9 | 6638 | .resetvalue = cpu->isar.reset_pmcr_el0, |
24183fb6 PM |
6639 | .writefn = pmcr_write, .raw_writefn = raw_write, |
6640 | }; | |
24526bb9 | 6641 | |
24183fb6 PM |
6642 | define_one_arm_cp_reg(cpu, &pmcr); |
6643 | define_one_arm_cp_reg(cpu, &pmcr64); | |
6644 | for (i = 0; i < pmcrn; i++) { | |
6645 | char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i); | |
6646 | char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i); | |
6647 | char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i); | |
6648 | char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i); | |
6649 | ARMCPRegInfo pmev_regs[] = { | |
6650 | { .name = pmevcntr_name, .cp = 15, .crn = 14, | |
6651 | .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, | |
6652 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6653 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, | |
99a50d1a | 6654 | .accessfn = pmreg_access_xevcntr }, |
24183fb6 PM |
6655 | { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64, |
6656 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)), | |
99a50d1a | 6657 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr, |
24183fb6 PM |
6658 | .type = ARM_CP_IO, |
6659 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, | |
6660 | .raw_readfn = pmevcntr_rawread, | |
6661 | .raw_writefn = pmevcntr_rawwrite }, | |
6662 | { .name = pmevtyper_name, .cp = 15, .crn = 14, | |
6663 | .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, | |
6664 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6665 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | |
6666 | .accessfn = pmreg_access }, | |
6667 | { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64, | |
6668 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)), | |
6669 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, | |
6670 | .type = ARM_CP_IO, | |
6671 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | |
6672 | .raw_writefn = pmevtyper_rawwrite }, | |
24183fb6 PM |
6673 | }; |
6674 | define_arm_cp_regs(cpu, pmev_regs); | |
6675 | g_free(pmevcntr_name); | |
6676 | g_free(pmevcntr_el0_name); | |
6677 | g_free(pmevtyper_name); | |
6678 | g_free(pmevtyper_el0_name); | |
6679 | } | |
a6179538 | 6680 | if (cpu_isar_feature(aa32_pmu_8_1, cpu)) { |
24183fb6 PM |
6681 | ARMCPRegInfo v81_pmu_regs[] = { |
6682 | { .name = "PMCEID2", .state = ARM_CP_STATE_AA32, | |
6683 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4, | |
6684 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6685 | .resetvalue = extract64(cpu->pmceid0, 32, 32) }, | |
6686 | { .name = "PMCEID3", .state = ARM_CP_STATE_AA32, | |
6687 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5, | |
6688 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6689 | .resetvalue = extract64(cpu->pmceid1, 32, 32) }, | |
24183fb6 PM |
6690 | }; |
6691 | define_arm_cp_regs(cpu, v81_pmu_regs); | |
6692 | } | |
15dd1ebd PM |
6693 | if (cpu_isar_feature(any_pmu_8_4, cpu)) { |
6694 | static const ARMCPRegInfo v84_pmmir = { | |
6695 | .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH, | |
6696 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6, | |
6697 | .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6698 | .resetvalue = 0 | |
6699 | }; | |
6700 | define_one_arm_cp_reg(cpu, &v84_pmmir); | |
6701 | } | |
24183fb6 PM |
6702 | } |
6703 | ||
96a8b92e PM |
6704 | /* We don't know until after realize whether there's a GICv3 |
6705 | * attached, and that is what registers the gicv3 sysregs. | |
6706 | * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1 | |
6707 | * at runtime. | |
6708 | */ | |
6709 | static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
6710 | { | |
2fc0cc0e | 6711 | ARMCPU *cpu = env_archcpu(env); |
8a130a7b | 6712 | uint64_t pfr1 = cpu->isar.id_pfr1; |
96a8b92e PM |
6713 | |
6714 | if (env->gicv3state) { | |
6715 | pfr1 |= 1 << 28; | |
6716 | } | |
6717 | return pfr1; | |
6718 | } | |
6719 | ||
976b99b6 | 6720 | #ifndef CONFIG_USER_ONLY |
96a8b92e PM |
6721 | static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) |
6722 | { | |
2fc0cc0e | 6723 | ARMCPU *cpu = env_archcpu(env); |
47576b94 | 6724 | uint64_t pfr0 = cpu->isar.id_aa64pfr0; |
96a8b92e PM |
6725 | |
6726 | if (env->gicv3state) { | |
6727 | pfr0 |= 1 << 24; | |
6728 | } | |
6729 | return pfr0; | |
6730 | } | |
976b99b6 | 6731 | #endif |
96a8b92e | 6732 | |
2d7137c1 | 6733 | /* Shared logic between LORID and the rest of the LOR* registers. |
9bd268ba | 6734 | * Secure state exclusion has already been dealt with. |
2d7137c1 | 6735 | */ |
9bd268ba RDC |
6736 | static CPAccessResult access_lor_ns(CPUARMState *env, |
6737 | const ARMCPRegInfo *ri, bool isread) | |
2d7137c1 RH |
6738 | { |
6739 | int el = arm_current_el(env); | |
6740 | ||
6741 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) { | |
6742 | return CP_ACCESS_TRAP_EL2; | |
6743 | } | |
6744 | if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { | |
6745 | return CP_ACCESS_TRAP_EL3; | |
6746 | } | |
6747 | return CP_ACCESS_OK; | |
6748 | } | |
6749 | ||
2d7137c1 RH |
6750 | static CPAccessResult access_lor_other(CPUARMState *env, |
6751 | const ARMCPRegInfo *ri, bool isread) | |
6752 | { | |
6753 | if (arm_is_secure_below_el3(env)) { | |
6754 | /* Access denied in secure mode. */ | |
6755 | return CP_ACCESS_TRAP; | |
6756 | } | |
9bd268ba | 6757 | return access_lor_ns(env, ri, isread); |
2d7137c1 RH |
6758 | } |
6759 | ||
d8564ee4 RH |
6760 | /* |
6761 | * A trivial implementation of ARMv8.1-LOR leaves all of these | |
6762 | * registers fixed at 0, which indicates that there are zero | |
6763 | * supported Limited Ordering regions. | |
6764 | */ | |
6765 | static const ARMCPRegInfo lor_reginfo[] = { | |
6766 | { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, | |
6767 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, | |
6768 | .access = PL1_RW, .accessfn = access_lor_other, | |
6769 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6770 | { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, | |
6771 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, | |
6772 | .access = PL1_RW, .accessfn = access_lor_other, | |
6773 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6774 | { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, | |
6775 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, | |
6776 | .access = PL1_RW, .accessfn = access_lor_other, | |
6777 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6778 | { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, | |
6779 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, | |
6780 | .access = PL1_RW, .accessfn = access_lor_other, | |
6781 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6782 | { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, | |
6783 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, | |
9bd268ba | 6784 | .access = PL1_R, .accessfn = access_lor_ns, |
d8564ee4 | 6785 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
d8564ee4 RH |
6786 | }; |
6787 | ||
967aa94f RH |
6788 | #ifdef TARGET_AARCH64 |
6789 | static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, | |
6790 | bool isread) | |
6791 | { | |
6792 | int el = arm_current_el(env); | |
6793 | ||
6794 | if (el < 2 && | |
07b034ea | 6795 | arm_is_el2_enabled(env) && |
967aa94f RH |
6796 | !(arm_hcr_el2_eff(env) & HCR_APK)) { |
6797 | return CP_ACCESS_TRAP_EL2; | |
6798 | } | |
6799 | if (el < 3 && | |
6800 | arm_feature(env, ARM_FEATURE_EL3) && | |
6801 | !(env->cp15.scr_el3 & SCR_APK)) { | |
6802 | return CP_ACCESS_TRAP_EL3; | |
6803 | } | |
6804 | return CP_ACCESS_OK; | |
6805 | } | |
6806 | ||
6807 | static const ARMCPRegInfo pauth_reginfo[] = { | |
6808 | { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64, | |
6809 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0, | |
6810 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6811 | .fieldoffset = offsetof(CPUARMState, keys.apda.lo) }, |
967aa94f RH |
6812 | { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6813 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1, | |
6814 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6815 | .fieldoffset = offsetof(CPUARMState, keys.apda.hi) }, |
967aa94f RH |
6816 | { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
6817 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2, | |
6818 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6819 | .fieldoffset = offsetof(CPUARMState, keys.apdb.lo) }, |
967aa94f RH |
6820 | { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6821 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3, | |
6822 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6823 | .fieldoffset = offsetof(CPUARMState, keys.apdb.hi) }, |
967aa94f RH |
6824 | { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
6825 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0, | |
6826 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6827 | .fieldoffset = offsetof(CPUARMState, keys.apga.lo) }, |
967aa94f RH |
6828 | { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6829 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1, | |
6830 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6831 | .fieldoffset = offsetof(CPUARMState, keys.apga.hi) }, |
967aa94f RH |
6832 | { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
6833 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0, | |
6834 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6835 | .fieldoffset = offsetof(CPUARMState, keys.apia.lo) }, |
967aa94f RH |
6836 | { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6837 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1, | |
6838 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6839 | .fieldoffset = offsetof(CPUARMState, keys.apia.hi) }, |
967aa94f RH |
6840 | { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
6841 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2, | |
6842 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6843 | .fieldoffset = offsetof(CPUARMState, keys.apib.lo) }, |
967aa94f RH |
6844 | { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
6845 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3, | |
6846 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 6847 | .fieldoffset = offsetof(CPUARMState, keys.apib.hi) }, |
967aa94f | 6848 | }; |
de390645 | 6849 | |
84940ed8 RC |
6850 | static const ARMCPRegInfo tlbirange_reginfo[] = { |
6851 | { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64, | |
6852 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1, | |
6853 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6854 | .writefn = tlbi_aa64_rvae1is_write }, | |
6855 | { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64, | |
6856 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3, | |
6857 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6858 | .writefn = tlbi_aa64_rvae1is_write }, | |
6859 | { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64, | |
6860 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5, | |
6861 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6862 | .writefn = tlbi_aa64_rvae1is_write }, | |
6863 | { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64, | |
6864 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7, | |
6865 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6866 | .writefn = tlbi_aa64_rvae1is_write }, | |
6867 | { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64, | |
6868 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, | |
6869 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6870 | .writefn = tlbi_aa64_rvae1is_write }, | |
6871 | { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64, | |
6872 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3, | |
6873 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6874 | .writefn = tlbi_aa64_rvae1is_write }, | |
6875 | { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64, | |
6876 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5, | |
6877 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6878 | .writefn = tlbi_aa64_rvae1is_write }, | |
6879 | { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64, | |
6880 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7, | |
6881 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6882 | .writefn = tlbi_aa64_rvae1is_write }, | |
6883 | { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64, | |
6884 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, | |
6885 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6886 | .writefn = tlbi_aa64_rvae1_write }, | |
6887 | { .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64, | |
6888 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3, | |
6889 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6890 | .writefn = tlbi_aa64_rvae1_write }, | |
6891 | { .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64, | |
6892 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5, | |
6893 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6894 | .writefn = tlbi_aa64_rvae1_write }, | |
6895 | { .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64, | |
6896 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7, | |
6897 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6898 | .writefn = tlbi_aa64_rvae1_write }, | |
6899 | { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64, | |
6900 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2, | |
6901 | .access = PL2_W, .type = ARM_CP_NOP }, | |
6902 | { .name = "TLBI_RIPAS2LE1IS", .state = ARM_CP_STATE_AA64, | |
6903 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 6, | |
6904 | .access = PL2_W, .type = ARM_CP_NOP }, | |
6905 | { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64, | |
6906 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1, | |
696ba377 | 6907 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
6908 | .writefn = tlbi_aa64_rvae2is_write }, |
6909 | { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64, | |
6910 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5, | |
696ba377 | 6911 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
6912 | .writefn = tlbi_aa64_rvae2is_write }, |
6913 | { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64, | |
6914 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2, | |
6915 | .access = PL2_W, .type = ARM_CP_NOP }, | |
6916 | { .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64, | |
6917 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 6, | |
6918 | .access = PL2_W, .type = ARM_CP_NOP }, | |
6919 | { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64, | |
6920 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1, | |
696ba377 | 6921 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
6922 | .writefn = tlbi_aa64_rvae2is_write }, |
6923 | { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64, | |
6924 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5, | |
696ba377 | 6925 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
6926 | .writefn = tlbi_aa64_rvae2is_write }, |
6927 | { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64, | |
6928 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1, | |
696ba377 | 6929 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
6930 | .writefn = tlbi_aa64_rvae2_write }, |
6931 | { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64, | |
6932 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5, | |
696ba377 | 6933 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
6934 | .writefn = tlbi_aa64_rvae2_write }, |
6935 | { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64, | |
6936 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1, | |
6937 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6938 | .writefn = tlbi_aa64_rvae3is_write }, | |
6939 | { .name = "TLBI_RVALE3IS", .state = ARM_CP_STATE_AA64, | |
6940 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 5, | |
6941 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6942 | .writefn = tlbi_aa64_rvae3is_write }, | |
6943 | { .name = "TLBI_RVAE3OS", .state = ARM_CP_STATE_AA64, | |
6944 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 1, | |
6945 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6946 | .writefn = tlbi_aa64_rvae3is_write }, | |
6947 | { .name = "TLBI_RVALE3OS", .state = ARM_CP_STATE_AA64, | |
6948 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 5, | |
6949 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6950 | .writefn = tlbi_aa64_rvae3is_write }, | |
6951 | { .name = "TLBI_RVAE3", .state = ARM_CP_STATE_AA64, | |
6952 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 1, | |
6953 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6954 | .writefn = tlbi_aa64_rvae3_write }, | |
6955 | { .name = "TLBI_RVALE3", .state = ARM_CP_STATE_AA64, | |
6956 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5, | |
6957 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6958 | .writefn = tlbi_aa64_rvae3_write }, | |
84940ed8 RC |
6959 | }; |
6960 | ||
7113d618 RC |
6961 | static const ARMCPRegInfo tlbios_reginfo[] = { |
6962 | { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64, | |
6963 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0, | |
6964 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6965 | .writefn = tlbi_aa64_vmalle1is_write }, | |
b7469ef9 IH |
6966 | { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64, |
6967 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1, | |
6968 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6969 | .writefn = tlbi_aa64_vae1is_write }, | |
7113d618 RC |
6970 | { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64, |
6971 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2, | |
6972 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6973 | .writefn = tlbi_aa64_vmalle1is_write }, | |
b7469ef9 IH |
6974 | { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64, |
6975 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3, | |
6976 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6977 | .writefn = tlbi_aa64_vae1is_write }, | |
6978 | { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64, | |
6979 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5, | |
6980 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6981 | .writefn = tlbi_aa64_vae1is_write }, | |
6982 | { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64, | |
6983 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7, | |
6984 | .access = PL1_W, .type = ARM_CP_NO_RAW, | |
6985 | .writefn = tlbi_aa64_vae1is_write }, | |
7113d618 RC |
6986 | { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64, |
6987 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0, | |
696ba377 | 6988 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
7113d618 | 6989 | .writefn = tlbi_aa64_alle2is_write }, |
b7469ef9 IH |
6990 | { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64, |
6991 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1, | |
696ba377 | 6992 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
b7469ef9 | 6993 | .writefn = tlbi_aa64_vae2is_write }, |
7113d618 RC |
6994 | { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64, |
6995 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4, | |
6996 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
6997 | .writefn = tlbi_aa64_alle1is_write }, | |
b7469ef9 IH |
6998 | { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64, |
6999 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5, | |
696ba377 | 7000 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
b7469ef9 | 7001 | .writefn = tlbi_aa64_vae2is_write }, |
7113d618 RC |
7002 | { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64, |
7003 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6, | |
7004 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
7005 | .writefn = tlbi_aa64_alle1is_write }, | |
7006 | { .name = "TLBI_IPAS2E1OS", .state = ARM_CP_STATE_AA64, | |
7007 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 0, | |
7008 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7009 | { .name = "TLBI_RIPAS2E1OS", .state = ARM_CP_STATE_AA64, | |
7010 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 3, | |
7011 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7012 | { .name = "TLBI_IPAS2LE1OS", .state = ARM_CP_STATE_AA64, | |
7013 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 4, | |
7014 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7015 | { .name = "TLBI_RIPAS2LE1OS", .state = ARM_CP_STATE_AA64, | |
7016 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 7, | |
7017 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7018 | { .name = "TLBI_ALLE3OS", .state = ARM_CP_STATE_AA64, | |
7019 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 0, | |
7020 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7021 | .writefn = tlbi_aa64_alle3is_write }, | |
b7469ef9 IH |
7022 | { .name = "TLBI_VAE3OS", .state = ARM_CP_STATE_AA64, |
7023 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 1, | |
7024 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7025 | .writefn = tlbi_aa64_vae3is_write }, | |
7026 | { .name = "TLBI_VALE3OS", .state = ARM_CP_STATE_AA64, | |
7027 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5, | |
7028 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7029 | .writefn = tlbi_aa64_vae3is_write }, | |
7113d618 RC |
7030 | }; |
7031 | ||
de390645 RH |
7032 | static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) |
7033 | { | |
7034 | Error *err = NULL; | |
7035 | uint64_t ret; | |
7036 | ||
7037 | /* Success sets NZCV = 0000. */ | |
7038 | env->NF = env->CF = env->VF = 0, env->ZF = 1; | |
7039 | ||
7040 | if (qemu_guest_getrandom(&ret, sizeof(ret), &err) < 0) { | |
7041 | /* | |
7042 | * ??? Failed, for unknown reasons in the crypto subsystem. | |
7043 | * The best we can do is log the reason and return the | |
7044 | * timed-out indication to the guest. There is no reason | |
7045 | * we know to expect this failure to be transitory, so the | |
7046 | * guest may well hang retrying the operation. | |
7047 | */ | |
7048 | qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", | |
7049 | ri->name, error_get_pretty(err)); | |
7050 | error_free(err); | |
7051 | ||
7052 | env->ZF = 0; /* NZCF = 0100 */ | |
7053 | return 0; | |
7054 | } | |
7055 | return ret; | |
7056 | } | |
7057 | ||
7058 | /* We do not support re-seeding, so the two registers operate the same. */ | |
7059 | static const ARMCPRegInfo rndr_reginfo[] = { | |
7060 | { .name = "RNDR", .state = ARM_CP_STATE_AA64, | |
7061 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | |
7062 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 0, | |
7063 | .access = PL0_R, .readfn = rndr_readfn }, | |
7064 | { .name = "RNDRRS", .state = ARM_CP_STATE_AA64, | |
7065 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | |
7066 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1, | |
7067 | .access = PL0_R, .readfn = rndr_readfn }, | |
de390645 | 7068 | }; |
0d57b499 BM |
7069 | |
7070 | #ifndef CONFIG_USER_ONLY | |
7071 | static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, | |
7072 | uint64_t value) | |
7073 | { | |
7074 | ARMCPU *cpu = env_archcpu(env); | |
7075 | /* CTR_EL0 System register -> DminLine, bits [19:16] */ | |
7076 | uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF); | |
7077 | uint64_t vaddr_in = (uint64_t) value; | |
7078 | uint64_t vaddr = vaddr_in & ~(dline_size - 1); | |
7079 | void *haddr; | |
7080 | int mem_idx = cpu_mmu_index(env, false); | |
7081 | ||
7082 | /* This won't be crossing page boundaries */ | |
7083 | haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC()); | |
7084 | if (haddr) { | |
7085 | ||
7086 | ram_addr_t offset; | |
7087 | MemoryRegion *mr; | |
7088 | ||
7089 | /* RCU lock is already being held */ | |
7090 | mr = memory_region_from_host(haddr, &offset); | |
7091 | ||
7092 | if (mr) { | |
4dfe59d1 | 7093 | memory_region_writeback(mr, offset, dline_size); |
0d57b499 BM |
7094 | } |
7095 | } | |
7096 | } | |
7097 | ||
7098 | static const ARMCPRegInfo dcpop_reg[] = { | |
7099 | { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64, | |
7100 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1, | |
7101 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | |
1bed4d2e | 7102 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, |
0d57b499 BM |
7103 | }; |
7104 | ||
7105 | static const ARMCPRegInfo dcpodp_reg[] = { | |
7106 | { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64, | |
7107 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1, | |
7108 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | |
1bed4d2e | 7109 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, |
0d57b499 BM |
7110 | }; |
7111 | #endif /*CONFIG_USER_ONLY*/ | |
7112 | ||
4b779ceb RH |
7113 | static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInfo *ri, |
7114 | bool isread) | |
7115 | { | |
7116 | if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID5)) { | |
7117 | return CP_ACCESS_TRAP_EL2; | |
7118 | } | |
7119 | ||
7120 | return CP_ACCESS_OK; | |
7121 | } | |
7122 | ||
7123 | static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri, | |
7124 | bool isread) | |
7125 | { | |
7126 | int el = arm_current_el(env); | |
7127 | ||
0da067f2 | 7128 | if (el < 2 && arm_is_el2_enabled(env)) { |
4301acd7 RH |
7129 | uint64_t hcr = arm_hcr_el2_eff(env); |
7130 | if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { | |
7131 | return CP_ACCESS_TRAP_EL2; | |
7132 | } | |
4b779ceb RH |
7133 | } |
7134 | if (el < 3 && | |
7135 | arm_feature(env, ARM_FEATURE_EL3) && | |
7136 | !(env->cp15.scr_el3 & SCR_ATA)) { | |
7137 | return CP_ACCESS_TRAP_EL3; | |
7138 | } | |
7139 | return CP_ACCESS_OK; | |
7140 | } | |
7141 | ||
7142 | static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
7143 | { | |
7144 | return env->pstate & PSTATE_TCO; | |
7145 | } | |
7146 | ||
7147 | static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
7148 | { | |
7149 | env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); | |
7150 | } | |
7151 | ||
7152 | static const ARMCPRegInfo mte_reginfo[] = { | |
7153 | { .name = "TFSRE0_EL1", .state = ARM_CP_STATE_AA64, | |
7154 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 1, | |
7155 | .access = PL1_RW, .accessfn = access_mte, | |
7156 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) }, | |
7157 | { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64, | |
7158 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 0, | |
7159 | .access = PL1_RW, .accessfn = access_mte, | |
7160 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) }, | |
7161 | { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64, | |
7162 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 6, .opc2 = 0, | |
7163 | .access = PL2_RW, .accessfn = access_mte, | |
7164 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) }, | |
7165 | { .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64, | |
7166 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 6, .opc2 = 0, | |
7167 | .access = PL3_RW, | |
7168 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) }, | |
7169 | { .name = "RGSR_EL1", .state = ARM_CP_STATE_AA64, | |
7170 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5, | |
7171 | .access = PL1_RW, .accessfn = access_mte, | |
7172 | .fieldoffset = offsetof(CPUARMState, cp15.rgsr_el1) }, | |
7173 | { .name = "GCR_EL1", .state = ARM_CP_STATE_AA64, | |
7174 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6, | |
7175 | .access = PL1_RW, .accessfn = access_mte, | |
7176 | .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, | |
7177 | { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, | |
7178 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, | |
7179 | .access = PL1_R, .accessfn = access_aa64_tid5, | |
7180 | .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, | |
7181 | { .name = "TCO", .state = ARM_CP_STATE_AA64, | |
7182 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | |
7183 | .type = ARM_CP_NO_RAW, | |
7184 | .access = PL0_RW, .readfn = tco_read, .writefn = tco_write }, | |
5463df16 RH |
7185 | { .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64, |
7186 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3, | |
7187 | .type = ARM_CP_NOP, .access = PL1_W, | |
7188 | .accessfn = aa64_cacheop_poc_access }, | |
7189 | { .name = "DC_IGSW", .state = ARM_CP_STATE_AA64, | |
7190 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4, | |
7191 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | |
7192 | { .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64, | |
7193 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5, | |
7194 | .type = ARM_CP_NOP, .access = PL1_W, | |
7195 | .accessfn = aa64_cacheop_poc_access }, | |
7196 | { .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64, | |
7197 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6, | |
7198 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | |
7199 | { .name = "DC_CGSW", .state = ARM_CP_STATE_AA64, | |
7200 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4, | |
7201 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | |
7202 | { .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64, | |
7203 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6, | |
7204 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | |
7205 | { .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64, | |
7206 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4, | |
7207 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | |
7208 | { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64, | |
7209 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6, | |
7210 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | |
4b779ceb RH |
7211 | }; |
7212 | ||
7213 | static const ARMCPRegInfo mte_tco_ro_reginfo[] = { | |
7214 | { .name = "TCO", .state = ARM_CP_STATE_AA64, | |
7215 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | |
7216 | .type = ARM_CP_CONST, .access = PL0_RW, }, | |
4b779ceb | 7217 | }; |
5463df16 RH |
7218 | |
7219 | static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | |
7220 | { .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64, | |
7221 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3, | |
7222 | .type = ARM_CP_NOP, .access = PL0_W, | |
7223 | .accessfn = aa64_cacheop_poc_access }, | |
7224 | { .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64, | |
7225 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5, | |
7226 | .type = ARM_CP_NOP, .access = PL0_W, | |
7227 | .accessfn = aa64_cacheop_poc_access }, | |
7228 | { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64, | |
7229 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3, | |
7230 | .type = ARM_CP_NOP, .access = PL0_W, | |
7231 | .accessfn = aa64_cacheop_poc_access }, | |
7232 | { .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64, | |
7233 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5, | |
7234 | .type = ARM_CP_NOP, .access = PL0_W, | |
7235 | .accessfn = aa64_cacheop_poc_access }, | |
7236 | { .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64, | |
7237 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3, | |
7238 | .type = ARM_CP_NOP, .access = PL0_W, | |
7239 | .accessfn = aa64_cacheop_poc_access }, | |
7240 | { .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64, | |
7241 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5, | |
7242 | .type = ARM_CP_NOP, .access = PL0_W, | |
7243 | .accessfn = aa64_cacheop_poc_access }, | |
7244 | { .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64, | |
7245 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3, | |
7246 | .type = ARM_CP_NOP, .access = PL0_W, | |
7247 | .accessfn = aa64_cacheop_poc_access }, | |
7248 | { .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64, | |
7249 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, | |
7250 | .type = ARM_CP_NOP, .access = PL0_W, | |
7251 | .accessfn = aa64_cacheop_poc_access }, | |
eb821168 RH |
7252 | { .name = "DC_GVA", .state = ARM_CP_STATE_AA64, |
7253 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3, | |
7254 | .access = PL0_W, .type = ARM_CP_DC_GVA, | |
7255 | #ifndef CONFIG_USER_ONLY | |
7256 | /* Avoid overhead of an access check that always passes in user-mode */ | |
7257 | .accessfn = aa64_zva_access, | |
7258 | #endif | |
7259 | }, | |
7260 | { .name = "DC_GZVA", .state = ARM_CP_STATE_AA64, | |
7261 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 4, | |
7262 | .access = PL0_W, .type = ARM_CP_DC_GZVA, | |
7263 | #ifndef CONFIG_USER_ONLY | |
7264 | /* Avoid overhead of an access check that always passes in user-mode */ | |
7265 | .accessfn = aa64_zva_access, | |
7266 | #endif | |
7267 | }, | |
5463df16 RH |
7268 | }; |
7269 | ||
7cb1e618 RH |
7270 | static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri, |
7271 | bool isread) | |
7272 | { | |
7273 | uint64_t hcr = arm_hcr_el2_eff(env); | |
7274 | int el = arm_current_el(env); | |
7275 | ||
7276 | if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) { | |
7277 | if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { | |
7278 | if (hcr & HCR_TGE) { | |
7279 | return CP_ACCESS_TRAP_EL2; | |
7280 | } | |
7281 | return CP_ACCESS_TRAP; | |
7282 | } | |
7283 | } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { | |
7284 | return CP_ACCESS_TRAP_EL2; | |
7285 | } | |
7286 | if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) { | |
7287 | return CP_ACCESS_TRAP_EL2; | |
7288 | } | |
7289 | if (el < 3 | |
7290 | && arm_feature(env, ARM_FEATURE_EL3) | |
7291 | && !(env->cp15.scr_el3 & SCR_ENSCXT)) { | |
7292 | return CP_ACCESS_TRAP_EL3; | |
7293 | } | |
7294 | return CP_ACCESS_OK; | |
7295 | } | |
7296 | ||
7297 | static const ARMCPRegInfo scxtnum_reginfo[] = { | |
7298 | { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64, | |
7299 | .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7, | |
7300 | .access = PL0_RW, .accessfn = access_scxtnum, | |
7301 | .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) }, | |
7302 | { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64, | |
7303 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7, | |
7304 | .access = PL1_RW, .accessfn = access_scxtnum, | |
7305 | .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) }, | |
7306 | { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64, | |
7307 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7, | |
7308 | .access = PL2_RW, .accessfn = access_scxtnum, | |
7309 | .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) }, | |
7310 | { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64, | |
7311 | .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7, | |
7312 | .access = PL3_RW, | |
7313 | .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) }, | |
7314 | }; | |
7315 | #endif /* TARGET_AARCH64 */ | |
967aa94f | 7316 | |
cb570bd3 RH |
7317 | static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, |
7318 | bool isread) | |
7319 | { | |
7320 | int el = arm_current_el(env); | |
7321 | ||
7322 | if (el == 0) { | |
7323 | uint64_t sctlr = arm_sctlr(env, el); | |
7324 | if (!(sctlr & SCTLR_EnRCTX)) { | |
7325 | return CP_ACCESS_TRAP; | |
7326 | } | |
7327 | } else if (el == 1) { | |
7328 | uint64_t hcr = arm_hcr_el2_eff(env); | |
7329 | if (hcr & HCR_NV) { | |
7330 | return CP_ACCESS_TRAP_EL2; | |
7331 | } | |
7332 | } | |
7333 | return CP_ACCESS_OK; | |
7334 | } | |
7335 | ||
7336 | static const ARMCPRegInfo predinv_reginfo[] = { | |
7337 | { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64, | |
7338 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4, | |
7339 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
7340 | { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64, | |
7341 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5, | |
7342 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
7343 | { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64, | |
7344 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7, | |
7345 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
7346 | /* | |
7347 | * Note the AArch32 opcodes have a different OPC1. | |
7348 | */ | |
7349 | { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32, | |
7350 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4, | |
7351 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
7352 | { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32, | |
7353 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5, | |
7354 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
7355 | { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32, | |
7356 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7, | |
7357 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
cb570bd3 RH |
7358 | }; |
7359 | ||
957e6155 PM |
7360 | static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri) |
7361 | { | |
7362 | /* Read the high 32 bits of the current CCSIDR */ | |
7363 | return extract64(ccsidr_read(env, ri), 32, 32); | |
7364 | } | |
7365 | ||
7366 | static const ARMCPRegInfo ccsidr2_reginfo[] = { | |
7367 | { .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH, | |
7368 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2, | |
7369 | .access = PL1_R, | |
7370 | .accessfn = access_aa64_tid2, | |
7371 | .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW }, | |
957e6155 PM |
7372 | }; |
7373 | ||
6a4ef4e5 MZ |
7374 | static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri, |
7375 | bool isread) | |
7376 | { | |
7377 | if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) { | |
7378 | return CP_ACCESS_TRAP_EL2; | |
7379 | } | |
7380 | ||
7381 | return CP_ACCESS_OK; | |
7382 | } | |
7383 | ||
7384 | static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri, | |
7385 | bool isread) | |
7386 | { | |
7387 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
7388 | return access_aa64_tid3(env, ri, isread); | |
7389 | } | |
7390 | ||
7391 | return CP_ACCESS_OK; | |
7392 | } | |
7393 | ||
f96f3d5f MZ |
7394 | static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri, |
7395 | bool isread) | |
7396 | { | |
7397 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID0)) { | |
7398 | return CP_ACCESS_TRAP_EL2; | |
7399 | } | |
7400 | ||
7401 | return CP_ACCESS_OK; | |
7402 | } | |
7403 | ||
8e228c9e PM |
7404 | static CPAccessResult access_joscr_jmcr(CPUARMState *env, |
7405 | const ARMCPRegInfo *ri, bool isread) | |
7406 | { | |
7407 | /* | |
7408 | * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only | |
7409 | * in v7A, not in v8A. | |
7410 | */ | |
7411 | if (!arm_feature(env, ARM_FEATURE_V8) && | |
7412 | arm_current_el(env) < 2 && !arm_is_secure_below_el3(env) && | |
7413 | (env->cp15.hstr_el2 & HSTR_TJDBX)) { | |
7414 | return CP_ACCESS_TRAP_EL2; | |
7415 | } | |
7416 | return CP_ACCESS_OK; | |
7417 | } | |
7418 | ||
f96f3d5f MZ |
7419 | static const ARMCPRegInfo jazelle_regs[] = { |
7420 | { .name = "JIDR", | |
7421 | .cp = 14, .crn = 0, .crm = 0, .opc1 = 7, .opc2 = 0, | |
7422 | .access = PL1_R, .accessfn = access_jazelle, | |
7423 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
7424 | { .name = "JOSCR", | |
7425 | .cp = 14, .crn = 1, .crm = 0, .opc1 = 7, .opc2 = 0, | |
8e228c9e | 7426 | .accessfn = access_joscr_jmcr, |
f96f3d5f MZ |
7427 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
7428 | { .name = "JMCR", | |
7429 | .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0, | |
8e228c9e | 7430 | .accessfn = access_joscr_jmcr, |
f96f3d5f | 7431 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f96f3d5f MZ |
7432 | }; |
7433 | ||
52d18727 RH |
7434 | static const ARMCPRegInfo contextidr_el2 = { |
7435 | .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, | |
7436 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, | |
7437 | .access = PL2_RW, | |
7438 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) | |
7439 | }; | |
7440 | ||
e2a1a461 | 7441 | static const ARMCPRegInfo vhe_reginfo[] = { |
ed30da8e RH |
7442 | { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, |
7443 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, | |
7444 | .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, | |
7445 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) }, | |
8c94b071 RH |
7446 | #ifndef CONFIG_USER_ONLY |
7447 | { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64, | |
7448 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 2, | |
7449 | .fieldoffset = | |
7450 | offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval), | |
7451 | .type = ARM_CP_IO, .access = PL2_RW, | |
7452 | .writefn = gt_hv_cval_write, .raw_writefn = raw_write }, | |
7453 | { .name = "CNTHV_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
7454 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 0, | |
7455 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, | |
7456 | .resetfn = gt_hv_timer_reset, | |
7457 | .readfn = gt_hv_tval_read, .writefn = gt_hv_tval_write }, | |
7458 | { .name = "CNTHV_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
7459 | .type = ARM_CP_IO, | |
7460 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 1, | |
7461 | .access = PL2_RW, | |
7462 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].ctl), | |
7463 | .writefn = gt_hv_ctl_write, .raw_writefn = raw_write }, | |
bb5972e4 RH |
7464 | { .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64, |
7465 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1, | |
7466 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
7467 | .access = PL2_RW, .accessfn = e2h_access, | |
7468 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), | |
7469 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write }, | |
7470 | { .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64, | |
7471 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1, | |
7472 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
7473 | .access = PL2_RW, .accessfn = e2h_access, | |
7474 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), | |
7475 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write }, | |
7476 | { .name = "CNTP_TVAL_EL02", .state = ARM_CP_STATE_AA64, | |
7477 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 0, | |
7478 | .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, | |
7479 | .access = PL2_RW, .accessfn = e2h_access, | |
7480 | .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write }, | |
7481 | { .name = "CNTV_TVAL_EL02", .state = ARM_CP_STATE_AA64, | |
7482 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 0, | |
7483 | .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, | |
7484 | .access = PL2_RW, .accessfn = e2h_access, | |
7485 | .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write }, | |
7486 | { .name = "CNTP_CVAL_EL02", .state = ARM_CP_STATE_AA64, | |
7487 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 2, | |
7488 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
7489 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
7490 | .access = PL2_RW, .accessfn = e2h_access, | |
7491 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write }, | |
7492 | { .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64, | |
7493 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2, | |
7494 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
7495 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
7496 | .access = PL2_RW, .accessfn = e2h_access, | |
7497 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write }, | |
8c94b071 | 7498 | #endif |
e2a1a461 RH |
7499 | }; |
7500 | ||
04b07d29 RH |
7501 | #ifndef CONFIG_USER_ONLY |
7502 | static const ARMCPRegInfo ats1e1_reginfo[] = { | |
7503 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
7504 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, | |
7505 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
7506 | .writefn = ats_write64 }, | |
7507 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, | |
7508 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, | |
7509 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
7510 | .writefn = ats_write64 }, | |
04b07d29 RH |
7511 | }; |
7512 | ||
7513 | static const ARMCPRegInfo ats1cp_reginfo[] = { | |
7514 | { .name = "ATS1CPRP", | |
7515 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, | |
7516 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
7517 | .writefn = ats_write }, | |
7518 | { .name = "ATS1CPWP", | |
7519 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, | |
7520 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
7521 | .writefn = ats_write }, | |
04b07d29 RH |
7522 | }; |
7523 | #endif | |
7524 | ||
f6287c24 PM |
7525 | /* |
7526 | * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and | |
7527 | * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field | |
7528 | * is non-zero, which is never for ARMv7, optionally in ARMv8 | |
7529 | * and mandatorily for ARMv8.2 and up. | |
7530 | * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's | |
7531 | * implementation is RAZ/WI we can ignore this detail, as we | |
7532 | * do for ACTLR. | |
7533 | */ | |
7534 | static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = { | |
7535 | { .name = "ACTLR2", .state = ARM_CP_STATE_AA32, | |
7536 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 3, | |
99602377 RH |
7537 | .access = PL1_RW, .accessfn = access_tacr, |
7538 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
f6287c24 PM |
7539 | { .name = "HACTLR2", .state = ARM_CP_STATE_AA32, |
7540 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3, | |
7541 | .access = PL2_RW, .type = ARM_CP_CONST, | |
7542 | .resetvalue = 0 }, | |
f6287c24 PM |
7543 | }; |
7544 | ||
2ceb98c0 PM |
7545 | void register_cp_regs_for_features(ARMCPU *cpu) |
7546 | { | |
7547 | /* Register all the coprocessor registers based on feature bits */ | |
7548 | CPUARMState *env = &cpu->env; | |
7549 | if (arm_feature(env, ARM_FEATURE_M)) { | |
7550 | /* M profile has no coprocessor registers */ | |
7551 | return; | |
7552 | } | |
7553 | ||
e9aa6c21 | 7554 | define_arm_cp_regs(cpu, cp_reginfo); |
9449fdf6 PM |
7555 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
7556 | /* Must go early as it is full of wildcards that may be | |
7557 | * overridden by later definitions. | |
7558 | */ | |
7559 | define_arm_cp_regs(cpu, not_v8_cp_reginfo); | |
7560 | } | |
7561 | ||
7d57f408 | 7562 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8515a092 PM |
7563 | /* The ID registers all have impdef reset values */ |
7564 | ARMCPRegInfo v6_idregs[] = { | |
0ff644a7 PM |
7565 | { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, |
7566 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
7567 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7568 | .accessfn = access_aa32_tid3, |
8a130a7b | 7569 | .resetvalue = cpu->isar.id_pfr0 }, |
96a8b92e PM |
7570 | /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know |
7571 | * the value of the GIC field until after we define these regs. | |
7572 | */ | |
0ff644a7 PM |
7573 | { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, |
7574 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | |
96a8b92e | 7575 | .access = PL1_R, .type = ARM_CP_NO_RAW, |
6a4ef4e5 | 7576 | .accessfn = access_aa32_tid3, |
96a8b92e PM |
7577 | .readfn = id_pfr1_read, |
7578 | .writefn = arm_cp_write_ignore }, | |
0ff644a7 PM |
7579 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, |
7580 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | |
7581 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7582 | .accessfn = access_aa32_tid3, |
a6179538 | 7583 | .resetvalue = cpu->isar.id_dfr0 }, |
0ff644a7 PM |
7584 | { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, |
7585 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, | |
7586 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7587 | .accessfn = access_aa32_tid3, |
8515a092 | 7588 | .resetvalue = cpu->id_afr0 }, |
0ff644a7 PM |
7589 | { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, |
7590 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, | |
7591 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7592 | .accessfn = access_aa32_tid3, |
10054016 | 7593 | .resetvalue = cpu->isar.id_mmfr0 }, |
0ff644a7 PM |
7594 | { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, |
7595 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, | |
7596 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7597 | .accessfn = access_aa32_tid3, |
10054016 | 7598 | .resetvalue = cpu->isar.id_mmfr1 }, |
0ff644a7 PM |
7599 | { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, |
7600 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, | |
7601 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7602 | .accessfn = access_aa32_tid3, |
10054016 | 7603 | .resetvalue = cpu->isar.id_mmfr2 }, |
0ff644a7 PM |
7604 | { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, |
7605 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, | |
7606 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7607 | .accessfn = access_aa32_tid3, |
10054016 | 7608 | .resetvalue = cpu->isar.id_mmfr3 }, |
0ff644a7 PM |
7609 | { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, |
7610 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
7611 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7612 | .accessfn = access_aa32_tid3, |
47576b94 | 7613 | .resetvalue = cpu->isar.id_isar0 }, |
0ff644a7 PM |
7614 | { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, |
7615 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, | |
7616 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7617 | .accessfn = access_aa32_tid3, |
47576b94 | 7618 | .resetvalue = cpu->isar.id_isar1 }, |
0ff644a7 PM |
7619 | { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, |
7620 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
7621 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7622 | .accessfn = access_aa32_tid3, |
47576b94 | 7623 | .resetvalue = cpu->isar.id_isar2 }, |
0ff644a7 PM |
7624 | { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, |
7625 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, | |
7626 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7627 | .accessfn = access_aa32_tid3, |
47576b94 | 7628 | .resetvalue = cpu->isar.id_isar3 }, |
0ff644a7 PM |
7629 | { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, |
7630 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, | |
7631 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7632 | .accessfn = access_aa32_tid3, |
47576b94 | 7633 | .resetvalue = cpu->isar.id_isar4 }, |
0ff644a7 PM |
7634 | { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, |
7635 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, | |
7636 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7637 | .accessfn = access_aa32_tid3, |
47576b94 | 7638 | .resetvalue = cpu->isar.id_isar5 }, |
e20d84c1 PM |
7639 | { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, |
7640 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, | |
7641 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7642 | .accessfn = access_aa32_tid3, |
10054016 | 7643 | .resetvalue = cpu->isar.id_mmfr4 }, |
802abf40 | 7644 | { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
7645 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, |
7646 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7647 | .accessfn = access_aa32_tid3, |
47576b94 | 7648 | .resetvalue = cpu->isar.id_isar6 }, |
8515a092 PM |
7649 | }; |
7650 | define_arm_cp_regs(cpu, v6_idregs); | |
7d57f408 PM |
7651 | define_arm_cp_regs(cpu, v6_cp_reginfo); |
7652 | } else { | |
7653 | define_arm_cp_regs(cpu, not_v6_cp_reginfo); | |
7654 | } | |
4d31c596 PM |
7655 | if (arm_feature(env, ARM_FEATURE_V6K)) { |
7656 | define_arm_cp_regs(cpu, v6k_cp_reginfo); | |
7657 | } | |
5e5cf9e3 | 7658 | if (arm_feature(env, ARM_FEATURE_V7MP) && |
452a0955 | 7659 | !arm_feature(env, ARM_FEATURE_PMSA)) { |
995939a6 PM |
7660 | define_arm_cp_regs(cpu, v7mp_cp_reginfo); |
7661 | } | |
327dd510 AL |
7662 | if (arm_feature(env, ARM_FEATURE_V7VE)) { |
7663 | define_arm_cp_regs(cpu, pmovsset_cp_reginfo); | |
7664 | } | |
e9aa6c21 | 7665 | if (arm_feature(env, ARM_FEATURE_V7)) { |
776d4e5c | 7666 | ARMCPRegInfo clidr = { |
7da845b0 PM |
7667 | .name = "CLIDR", .state = ARM_CP_STATE_BOTH, |
7668 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | |
630fcd4d MZ |
7669 | .access = PL1_R, .type = ARM_CP_CONST, |
7670 | .accessfn = access_aa64_tid2, | |
7671 | .resetvalue = cpu->clidr | |
776d4e5c | 7672 | }; |
776d4e5c | 7673 | define_one_arm_cp_reg(cpu, &clidr); |
e9aa6c21 | 7674 | define_arm_cp_regs(cpu, v7_cp_reginfo); |
50300698 | 7675 | define_debug_regs(cpu); |
24183fb6 | 7676 | define_pmu_regs(cpu); |
7d57f408 PM |
7677 | } else { |
7678 | define_arm_cp_regs(cpu, not_v7_cp_reginfo); | |
e9aa6c21 | 7679 | } |
b0d2b7d0 | 7680 | if (arm_feature(env, ARM_FEATURE_V8)) { |
e20d84c1 PM |
7681 | /* AArch64 ID registers, which all have impdef reset values. |
7682 | * Note that within the ID register ranges the unused slots | |
7683 | * must all RAZ, not UNDEF; future architecture versions may | |
7684 | * define new registers here. | |
7685 | */ | |
e60cef86 | 7686 | ARMCPRegInfo v8_idregs[] = { |
976b99b6 AB |
7687 | /* |
7688 | * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system | |
7689 | * emulation because we don't know the right value for the | |
7690 | * GIC field until after we define these regs. | |
96a8b92e | 7691 | */ |
e60cef86 PM |
7692 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, |
7693 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | |
976b99b6 AB |
7694 | .access = PL1_R, |
7695 | #ifdef CONFIG_USER_ONLY | |
7696 | .type = ARM_CP_CONST, | |
7697 | .resetvalue = cpu->isar.id_aa64pfr0 | |
7698 | #else | |
7699 | .type = ARM_CP_NO_RAW, | |
6a4ef4e5 | 7700 | .accessfn = access_aa64_tid3, |
96a8b92e | 7701 | .readfn = id_aa64pfr0_read, |
976b99b6 AB |
7702 | .writefn = arm_cp_write_ignore |
7703 | #endif | |
7704 | }, | |
e60cef86 PM |
7705 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, |
7706 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | |
7707 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7708 | .accessfn = access_aa64_tid3, |
47576b94 | 7709 | .resetvalue = cpu->isar.id_aa64pfr1}, |
e20d84c1 PM |
7710 | { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7711 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, | |
7712 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7713 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7714 | .resetvalue = 0 }, |
7715 | { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7716 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, | |
7717 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7718 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7719 | .resetvalue = 0 }, |
9516d772 | 7720 | { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
7721 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, |
7722 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7723 | .accessfn = access_aa64_tid3, |
2dc10fa2 | 7724 | .resetvalue = cpu->isar.id_aa64zfr0 }, |
414c54d5 | 7725 | { .name = "ID_AA64SMFR0_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
7726 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, |
7727 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7728 | .accessfn = access_aa64_tid3, |
414c54d5 | 7729 | .resetvalue = cpu->isar.id_aa64smfr0 }, |
e20d84c1 PM |
7730 | { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7731 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, | |
7732 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7733 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7734 | .resetvalue = 0 }, |
7735 | { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7736 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, | |
7737 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7738 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7739 | .resetvalue = 0 }, |
e60cef86 PM |
7740 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, |
7741 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | |
7742 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7743 | .accessfn = access_aa64_tid3, |
2a609df8 | 7744 | .resetvalue = cpu->isar.id_aa64dfr0 }, |
e60cef86 PM |
7745 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, |
7746 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | |
7747 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7748 | .accessfn = access_aa64_tid3, |
2a609df8 | 7749 | .resetvalue = cpu->isar.id_aa64dfr1 }, |
e20d84c1 PM |
7750 | { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7751 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, | |
7752 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7753 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7754 | .resetvalue = 0 }, |
7755 | { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7756 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, | |
7757 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7758 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7759 | .resetvalue = 0 }, |
e60cef86 PM |
7760 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, |
7761 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | |
7762 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7763 | .accessfn = access_aa64_tid3, |
e60cef86 PM |
7764 | .resetvalue = cpu->id_aa64afr0 }, |
7765 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | |
7766 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | |
7767 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7768 | .accessfn = access_aa64_tid3, |
e60cef86 | 7769 | .resetvalue = cpu->id_aa64afr1 }, |
e20d84c1 PM |
7770 | { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7771 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, | |
7772 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7773 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7774 | .resetvalue = 0 }, |
7775 | { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7776 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, | |
7777 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7778 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7779 | .resetvalue = 0 }, |
e60cef86 PM |
7780 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, |
7781 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | |
7782 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7783 | .accessfn = access_aa64_tid3, |
47576b94 | 7784 | .resetvalue = cpu->isar.id_aa64isar0 }, |
e60cef86 PM |
7785 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, |
7786 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | |
7787 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7788 | .accessfn = access_aa64_tid3, |
47576b94 | 7789 | .resetvalue = cpu->isar.id_aa64isar1 }, |
e20d84c1 PM |
7790 | { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7791 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, | |
7792 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7793 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7794 | .resetvalue = 0 }, |
7795 | { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7796 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, | |
7797 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7798 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7799 | .resetvalue = 0 }, |
7800 | { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7801 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, | |
7802 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7803 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7804 | .resetvalue = 0 }, |
7805 | { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7806 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, | |
7807 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7808 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7809 | .resetvalue = 0 }, |
7810 | { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7811 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, | |
7812 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7813 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7814 | .resetvalue = 0 }, |
7815 | { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7816 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, | |
7817 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7818 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7819 | .resetvalue = 0 }, |
e60cef86 PM |
7820 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, |
7821 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
7822 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7823 | .accessfn = access_aa64_tid3, |
3dc91ddb | 7824 | .resetvalue = cpu->isar.id_aa64mmfr0 }, |
e60cef86 PM |
7825 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, |
7826 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | |
7827 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7828 | .accessfn = access_aa64_tid3, |
3dc91ddb | 7829 | .resetvalue = cpu->isar.id_aa64mmfr1 }, |
64761e10 | 7830 | { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
7831 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, |
7832 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7833 | .accessfn = access_aa64_tid3, |
64761e10 | 7834 | .resetvalue = cpu->isar.id_aa64mmfr2 }, |
e20d84c1 PM |
7835 | { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7836 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, | |
7837 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7838 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7839 | .resetvalue = 0 }, |
7840 | { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7841 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, | |
7842 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7843 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7844 | .resetvalue = 0 }, |
7845 | { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7846 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, | |
7847 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7848 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7849 | .resetvalue = 0 }, |
7850 | { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7851 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, | |
7852 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7853 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7854 | .resetvalue = 0 }, |
7855 | { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7856 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, | |
7857 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7858 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7859 | .resetvalue = 0 }, |
a50c0f51 PM |
7860 | { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, |
7861 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
7862 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7863 | .accessfn = access_aa64_tid3, |
47576b94 | 7864 | .resetvalue = cpu->isar.mvfr0 }, |
a50c0f51 PM |
7865 | { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, |
7866 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
7867 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7868 | .accessfn = access_aa64_tid3, |
47576b94 | 7869 | .resetvalue = cpu->isar.mvfr1 }, |
a50c0f51 PM |
7870 | { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, |
7871 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
7872 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7873 | .accessfn = access_aa64_tid3, |
47576b94 | 7874 | .resetvalue = cpu->isar.mvfr2 }, |
e20d84c1 PM |
7875 | { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7876 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, | |
7877 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7878 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7879 | .resetvalue = 0 }, |
1d51bc96 | 7880 | { .name = "ID_PFR2", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
7881 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, |
7882 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7883 | .accessfn = access_aa64_tid3, |
1d51bc96 | 7884 | .resetvalue = cpu->isar.id_pfr2 }, |
e20d84c1 PM |
7885 | { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
7886 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, | |
7887 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7888 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7889 | .resetvalue = 0 }, |
7890 | { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7891 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, | |
7892 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7893 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
7894 | .resetvalue = 0 }, |
7895 | { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
7896 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, | |
7897 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 7898 | .accessfn = access_aa64_tid3, |
e20d84c1 | 7899 | .resetvalue = 0 }, |
4054bfa9 AF |
7900 | { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, |
7901 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, | |
7902 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
cad86737 | 7903 | .resetvalue = extract64(cpu->pmceid0, 0, 32) }, |
4054bfa9 AF |
7904 | { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, |
7905 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, | |
7906 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
7907 | .resetvalue = cpu->pmceid0 }, | |
7908 | { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, | |
7909 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, | |
7910 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
cad86737 | 7911 | .resetvalue = extract64(cpu->pmceid1, 0, 32) }, |
4054bfa9 AF |
7912 | { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, |
7913 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, | |
7914 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
7915 | .resetvalue = cpu->pmceid1 }, | |
e60cef86 | 7916 | }; |
6c5c0fec | 7917 | #ifdef CONFIG_USER_ONLY |
10b0220e | 7918 | static const ARMCPRegUserSpaceInfo v8_user_idregs[] = { |
6c5c0fec AB |
7919 | { .name = "ID_AA64PFR0_EL1", |
7920 | .exported_bits = 0x000f000f00ff0000, | |
7921 | .fixed_bits = 0x0000000000000011 }, | |
7922 | { .name = "ID_AA64PFR1_EL1", | |
7923 | .exported_bits = 0x00000000000000f0 }, | |
d040242e AB |
7924 | { .name = "ID_AA64PFR*_EL1_RESERVED", |
7925 | .is_glob = true }, | |
6c5c0fec AB |
7926 | { .name = "ID_AA64ZFR0_EL1" }, |
7927 | { .name = "ID_AA64MMFR0_EL1", | |
7928 | .fixed_bits = 0x00000000ff000000 }, | |
7929 | { .name = "ID_AA64MMFR1_EL1" }, | |
d040242e AB |
7930 | { .name = "ID_AA64MMFR*_EL1_RESERVED", |
7931 | .is_glob = true }, | |
6c5c0fec AB |
7932 | { .name = "ID_AA64DFR0_EL1", |
7933 | .fixed_bits = 0x0000000000000006 }, | |
7934 | { .name = "ID_AA64DFR1_EL1" }, | |
d040242e AB |
7935 | { .name = "ID_AA64DFR*_EL1_RESERVED", |
7936 | .is_glob = true }, | |
7937 | { .name = "ID_AA64AFR*", | |
7938 | .is_glob = true }, | |
6c5c0fec AB |
7939 | { .name = "ID_AA64ISAR0_EL1", |
7940 | .exported_bits = 0x00fffffff0fffff0 }, | |
7941 | { .name = "ID_AA64ISAR1_EL1", | |
7942 | .exported_bits = 0x000000f0ffffffff }, | |
d040242e AB |
7943 | { .name = "ID_AA64ISAR*_EL1_RESERVED", |
7944 | .is_glob = true }, | |
6c5c0fec AB |
7945 | }; |
7946 | modify_arm_cp_regs(v8_idregs, v8_user_idregs); | |
7947 | #endif | |
be8e8128 GB |
7948 | /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ |
7949 | if (!arm_feature(env, ARM_FEATURE_EL3) && | |
7950 | !arm_feature(env, ARM_FEATURE_EL2)) { | |
7951 | ARMCPRegInfo rvbar = { | |
7952 | .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, | |
7953 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, | |
4a7319b7 EI |
7954 | .access = PL1_R, |
7955 | .fieldoffset = offsetof(CPUARMState, cp15.rvbar), | |
be8e8128 GB |
7956 | }; |
7957 | define_one_arm_cp_reg(cpu, &rvbar); | |
7958 | } | |
e60cef86 | 7959 | define_arm_cp_regs(cpu, v8_idregs); |
b0d2b7d0 PM |
7960 | define_arm_cp_regs(cpu, v8_cp_reginfo); |
7961 | } | |
99a90811 RH |
7962 | |
7963 | /* | |
7964 | * Register the base EL2 cpregs. | |
7965 | * Pre v8, these registers are implemented only as part of the | |
7966 | * Virtualization Extensions (EL2 present). Beginning with v8, | |
7967 | * if EL2 is missing but EL3 is enabled, mostly these become | |
7968 | * RES0 from EL3, with some specific exceptions. | |
7969 | */ | |
7970 | if (arm_feature(env, ARM_FEATURE_EL2) | |
7971 | || (arm_feature(env, ARM_FEATURE_EL3) | |
7972 | && arm_feature(env, ARM_FEATURE_V8))) { | |
f0d574d6 | 7973 | uint64_t vmpidr_def = mpidr_read_val(env); |
731de9e6 EI |
7974 | ARMCPRegInfo vpidr_regs[] = { |
7975 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | |
7976 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
7977 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
696ba377 RH |
7978 | .resetvalue = cpu->midr, |
7979 | .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, | |
36476562 | 7980 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) }, |
731de9e6 EI |
7981 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, |
7982 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
7983 | .access = PL2_RW, .resetvalue = cpu->midr, | |
696ba377 | 7984 | .type = ARM_CP_EL3_NO_EL2_C_NZ, |
731de9e6 | 7985 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, |
f0d574d6 EI |
7986 | { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, |
7987 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
7988 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
696ba377 RH |
7989 | .resetvalue = vmpidr_def, |
7990 | .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, | |
36476562 | 7991 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) }, |
f0d574d6 EI |
7992 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, |
7993 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
696ba377 RH |
7994 | .access = PL2_RW, .resetvalue = vmpidr_def, |
7995 | .type = ARM_CP_EL3_NO_EL2_C_NZ, | |
f0d574d6 | 7996 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, |
731de9e6 | 7997 | }; |
24526bb9 PM |
7998 | /* |
7999 | * The only field of MDCR_EL2 that has a defined architectural reset | |
8000 | * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N. | |
8001 | */ | |
8002 | ARMCPRegInfo mdcr_el2 = { | |
8003 | .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, | |
8004 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | |
8005 | .access = PL2_RW, .resetvalue = pmu_num_counters(env), | |
8006 | .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), | |
8007 | }; | |
8008 | define_one_arm_cp_reg(cpu, &mdcr_el2); | |
731de9e6 | 8009 | define_arm_cp_regs(cpu, vpidr_regs); |
4771cd01 | 8010 | define_arm_cp_regs(cpu, el2_cp_reginfo); |
ce4afed8 PM |
8011 | if (arm_feature(env, ARM_FEATURE_V8)) { |
8012 | define_arm_cp_regs(cpu, el2_v8_cp_reginfo); | |
8013 | } | |
e9152ee9 RDC |
8014 | if (cpu_isar_feature(aa64_sel2, cpu)) { |
8015 | define_arm_cp_regs(cpu, el2_sec_cp_reginfo); | |
8016 | } | |
be8e8128 GB |
8017 | /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ |
8018 | if (!arm_feature(env, ARM_FEATURE_EL3)) { | |
8019 | ARMCPRegInfo rvbar = { | |
8020 | .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, | |
8021 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, | |
4a7319b7 EI |
8022 | .access = PL2_R, |
8023 | .fieldoffset = offsetof(CPUARMState, cp15.rvbar), | |
be8e8128 GB |
8024 | }; |
8025 | define_one_arm_cp_reg(cpu, &rvbar); | |
8026 | } | |
3b685ba7 | 8027 | } |
99a90811 RH |
8028 | |
8029 | /* Register the base EL3 cpregs. */ | |
81547d66 | 8030 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0f1a3b24 | 8031 | define_arm_cp_regs(cpu, el3_cp_reginfo); |
e24fdd23 PM |
8032 | ARMCPRegInfo el3_regs[] = { |
8033 | { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, | |
8034 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, | |
4a7319b7 EI |
8035 | .access = PL3_R, |
8036 | .fieldoffset = offsetof(CPUARMState, cp15.rvbar), | |
8037 | }, | |
e24fdd23 PM |
8038 | { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, |
8039 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, | |
8040 | .access = PL3_RW, | |
8041 | .raw_writefn = raw_write, .writefn = sctlr_write, | |
8042 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), | |
8043 | .resetvalue = cpu->reset_sctlr }, | |
be8e8128 | 8044 | }; |
e24fdd23 PM |
8045 | |
8046 | define_arm_cp_regs(cpu, el3_regs); | |
81547d66 | 8047 | } |
2f027fc5 PM |
8048 | /* The behaviour of NSACR is sufficiently various that we don't |
8049 | * try to describe it in a single reginfo: | |
8050 | * if EL3 is 64 bit, then trap to EL3 from S EL1, | |
8051 | * reads as constant 0xc00 from NS EL1 and NS EL2 | |
8052 | * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 | |
8053 | * if v7 without EL3, register doesn't exist | |
8054 | * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 | |
8055 | */ | |
8056 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
8057 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
10b0220e | 8058 | static const ARMCPRegInfo nsacr = { |
2f027fc5 PM |
8059 | .name = "NSACR", .type = ARM_CP_CONST, |
8060 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
8061 | .access = PL1_RW, .accessfn = nsacr_access, | |
8062 | .resetvalue = 0xc00 | |
8063 | }; | |
8064 | define_one_arm_cp_reg(cpu, &nsacr); | |
8065 | } else { | |
10b0220e | 8066 | static const ARMCPRegInfo nsacr = { |
2f027fc5 PM |
8067 | .name = "NSACR", |
8068 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
8069 | .access = PL3_RW | PL1_R, | |
8070 | .resetvalue = 0, | |
8071 | .fieldoffset = offsetof(CPUARMState, cp15.nsacr) | |
8072 | }; | |
8073 | define_one_arm_cp_reg(cpu, &nsacr); | |
8074 | } | |
8075 | } else { | |
8076 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
10b0220e | 8077 | static const ARMCPRegInfo nsacr = { |
2f027fc5 PM |
8078 | .name = "NSACR", .type = ARM_CP_CONST, |
8079 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
8080 | .access = PL1_R, | |
8081 | .resetvalue = 0xc00 | |
8082 | }; | |
8083 | define_one_arm_cp_reg(cpu, &nsacr); | |
8084 | } | |
8085 | } | |
8086 | ||
452a0955 | 8087 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
6cb0b013 PC |
8088 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8089 | /* PMSAv6 not implemented */ | |
8090 | assert(arm_feature(env, ARM_FEATURE_V7)); | |
8091 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); | |
8092 | define_arm_cp_regs(cpu, pmsav7_cp_reginfo); | |
8093 | } else { | |
8094 | define_arm_cp_regs(cpu, pmsav5_cp_reginfo); | |
8095 | } | |
18032bec | 8096 | } else { |
8e5d75c9 | 8097 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); |
18032bec | 8098 | define_arm_cp_regs(cpu, vmsa_cp_reginfo); |
4036b7d1 PM |
8099 | /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */ |
8100 | if (cpu_isar_feature(aa32_hpd, cpu)) { | |
ab638a32 RH |
8101 | define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); |
8102 | } | |
18032bec | 8103 | } |
c326b979 PM |
8104 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
8105 | define_arm_cp_regs(cpu, t2ee_cp_reginfo); | |
8106 | } | |
6cc7a3ae PM |
8107 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
8108 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); | |
8109 | } | |
4a501606 PM |
8110 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
8111 | define_arm_cp_regs(cpu, vapa_cp_reginfo); | |
8112 | } | |
c4804214 PM |
8113 | if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { |
8114 | define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); | |
8115 | } | |
8116 | if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { | |
8117 | define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); | |
8118 | } | |
8119 | if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { | |
8120 | define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); | |
8121 | } | |
18032bec PM |
8122 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
8123 | define_arm_cp_regs(cpu, omap_cp_reginfo); | |
8124 | } | |
34f90529 PM |
8125 | if (arm_feature(env, ARM_FEATURE_STRONGARM)) { |
8126 | define_arm_cp_regs(cpu, strongarm_cp_reginfo); | |
8127 | } | |
1047b9d7 PM |
8128 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
8129 | define_arm_cp_regs(cpu, xscale_cp_reginfo); | |
8130 | } | |
8131 | if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { | |
8132 | define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); | |
8133 | } | |
7ac681cf PM |
8134 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8135 | define_arm_cp_regs(cpu, lpae_cp_reginfo); | |
8136 | } | |
873b73c0 | 8137 | if (cpu_isar_feature(aa32_jazelle, cpu)) { |
f96f3d5f MZ |
8138 | define_arm_cp_regs(cpu, jazelle_regs); |
8139 | } | |
7884849c PM |
8140 | /* Slightly awkwardly, the OMAP and StrongARM cores need all of |
8141 | * cp15 crn=0 to be writes-ignored, whereas for other cores they should | |
8142 | * be read-only (ie write causes UNDEF exception). | |
8143 | */ | |
8144 | { | |
00a29f3d PM |
8145 | ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { |
8146 | /* Pre-v8 MIDR space. | |
8147 | * Note that the MIDR isn't a simple constant register because | |
7884849c PM |
8148 | * of the TI925 behaviour where writes to another register can |
8149 | * cause the MIDR value to change. | |
97ce8d61 PC |
8150 | * |
8151 | * Unimplemented registers in the c15 0 0 0 space default to | |
8152 | * MIDR. Define MIDR first as this entire space, then CTR, TCMTR | |
8153 | * and friends override accordingly. | |
7884849c PM |
8154 | */ |
8155 | { .name = "MIDR", | |
97ce8d61 | 8156 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, |
7884849c | 8157 | .access = PL1_R, .resetvalue = cpu->midr, |
d4e6df63 | 8158 | .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, |
731de9e6 | 8159 | .readfn = midr_read, |
97ce8d61 PC |
8160 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
8161 | .type = ARM_CP_OVERRIDE }, | |
7884849c PM |
8162 | /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ |
8163 | { .name = "DUMMY", | |
8164 | .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, | |
8165 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8166 | { .name = "DUMMY", | |
8167 | .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, | |
8168 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8169 | { .name = "DUMMY", | |
8170 | .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, | |
8171 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8172 | { .name = "DUMMY", | |
8173 | .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, | |
8174 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8175 | { .name = "DUMMY", | |
8176 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | |
8177 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
7884849c | 8178 | }; |
00a29f3d | 8179 | ARMCPRegInfo id_v8_midr_cp_reginfo[] = { |
00a29f3d PM |
8180 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, |
8181 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, | |
731de9e6 EI |
8182 | .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, |
8183 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), | |
8184 | .readfn = midr_read }, | |
ac00c79f SF |
8185 | /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ |
8186 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
8187 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
8188 | .access = PL1_R, .resetvalue = cpu->midr }, | |
8189 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
8190 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, | |
8191 | .access = PL1_R, .resetvalue = cpu->midr }, | |
00a29f3d PM |
8192 | { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, |
8193 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, | |
93fbc983 MZ |
8194 | .access = PL1_R, |
8195 | .accessfn = access_aa64_tid1, | |
8196 | .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, | |
00a29f3d PM |
8197 | }; |
8198 | ARMCPRegInfo id_cp_reginfo[] = { | |
8199 | /* These are common to v8 and pre-v8 */ | |
8200 | { .name = "CTR", | |
8201 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, | |
630fcd4d MZ |
8202 | .access = PL1_R, .accessfn = ctr_el0_access, |
8203 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
00a29f3d PM |
8204 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, |
8205 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, | |
8206 | .access = PL0_R, .accessfn = ctr_el0_access, | |
8207 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
8208 | /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ | |
8209 | { .name = "TCMTR", | |
8210 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, | |
93fbc983 MZ |
8211 | .access = PL1_R, |
8212 | .accessfn = access_aa32_tid1, | |
8213 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
00a29f3d | 8214 | }; |
8085ce63 PC |
8215 | /* TLBTR is specific to VMSA */ |
8216 | ARMCPRegInfo id_tlbtr_reginfo = { | |
8217 | .name = "TLBTR", | |
8218 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, | |
93fbc983 MZ |
8219 | .access = PL1_R, |
8220 | .accessfn = access_aa32_tid1, | |
8221 | .type = ARM_CP_CONST, .resetvalue = 0, | |
8085ce63 | 8222 | }; |
3281af81 PC |
8223 | /* MPUIR is specific to PMSA V6+ */ |
8224 | ARMCPRegInfo id_mpuir_reginfo = { | |
8225 | .name = "MPUIR", | |
8226 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
8227 | .access = PL1_R, .type = ARM_CP_CONST, | |
8228 | .resetvalue = cpu->pmsav7_dregion << 8 | |
8229 | }; | |
10b0220e | 8230 | static const ARMCPRegInfo crn0_wi_reginfo = { |
7884849c PM |
8231 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, |
8232 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | |
8233 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | |
8234 | }; | |
6c5c0fec | 8235 | #ifdef CONFIG_USER_ONLY |
10b0220e | 8236 | static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = { |
6c5c0fec AB |
8237 | { .name = "MIDR_EL1", |
8238 | .exported_bits = 0x00000000ffffffff }, | |
8239 | { .name = "REVIDR_EL1" }, | |
6c5c0fec AB |
8240 | }; |
8241 | modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo); | |
8242 | #endif | |
7884849c PM |
8243 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || |
8244 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | |
5809ac57 | 8245 | size_t i; |
7884849c | 8246 | /* Register the blanket "writes ignored" value first to cover the |
a703eda1 PC |
8247 | * whole space. Then update the specific ID registers to allow write |
8248 | * access, so that they ignore writes rather than causing them to | |
8249 | * UNDEF. | |
7884849c PM |
8250 | */ |
8251 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | |
5809ac57 RH |
8252 | for (i = 0; i < ARRAY_SIZE(id_pre_v8_midr_cp_reginfo); ++i) { |
8253 | id_pre_v8_midr_cp_reginfo[i].access = PL1_RW; | |
00a29f3d | 8254 | } |
5809ac57 RH |
8255 | for (i = 0; i < ARRAY_SIZE(id_cp_reginfo); ++i) { |
8256 | id_cp_reginfo[i].access = PL1_RW; | |
7884849c | 8257 | } |
10006112 | 8258 | id_mpuir_reginfo.access = PL1_RW; |
3281af81 | 8259 | id_tlbtr_reginfo.access = PL1_RW; |
7884849c | 8260 | } |
00a29f3d PM |
8261 | if (arm_feature(env, ARM_FEATURE_V8)) { |
8262 | define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); | |
8263 | } else { | |
8264 | define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); | |
8265 | } | |
a703eda1 | 8266 | define_arm_cp_regs(cpu, id_cp_reginfo); |
452a0955 | 8267 | if (!arm_feature(env, ARM_FEATURE_PMSA)) { |
8085ce63 | 8268 | define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); |
3281af81 PC |
8269 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8270 | define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); | |
8085ce63 | 8271 | } |
7884849c PM |
8272 | } |
8273 | ||
97ce8d61 | 8274 | if (arm_feature(env, ARM_FEATURE_MPIDR)) { |
52264166 AB |
8275 | ARMCPRegInfo mpidr_cp_reginfo[] = { |
8276 | { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
8277 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | |
8278 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, | |
52264166 AB |
8279 | }; |
8280 | #ifdef CONFIG_USER_ONLY | |
10b0220e | 8281 | static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = { |
52264166 AB |
8282 | { .name = "MPIDR_EL1", |
8283 | .fixed_bits = 0x0000000080000000 }, | |
52264166 AB |
8284 | }; |
8285 | modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); | |
8286 | #endif | |
97ce8d61 PC |
8287 | define_arm_cp_regs(cpu, mpidr_cp_reginfo); |
8288 | } | |
8289 | ||
2771db27 | 8290 | if (arm_feature(env, ARM_FEATURE_AUXCR)) { |
834a6c69 PM |
8291 | ARMCPRegInfo auxcr_reginfo[] = { |
8292 | { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, | |
8293 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, | |
99602377 RH |
8294 | .access = PL1_RW, .accessfn = access_tacr, |
8295 | .type = ARM_CP_CONST, .resetvalue = cpu->reset_auxcr }, | |
834a6c69 PM |
8296 | { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, |
8297 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, | |
8298 | .access = PL2_RW, .type = ARM_CP_CONST, | |
8299 | .resetvalue = 0 }, | |
8300 | { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, | |
8301 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, | |
8302 | .access = PL3_RW, .type = ARM_CP_CONST, | |
8303 | .resetvalue = 0 }, | |
2771db27 | 8304 | }; |
834a6c69 | 8305 | define_arm_cp_regs(cpu, auxcr_reginfo); |
f6287c24 PM |
8306 | if (cpu_isar_feature(aa32_ac2, cpu)) { |
8307 | define_arm_cp_regs(cpu, actlr2_hactlr2_reginfo); | |
0e0456ab | 8308 | } |
2771db27 PM |
8309 | } |
8310 | ||
d8ba780b | 8311 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
d56974af LM |
8312 | /* |
8313 | * CBAR is IMPDEF, but common on Arm Cortex-A implementations. | |
8314 | * There are two flavours: | |
8315 | * (1) older 32-bit only cores have a simple 32-bit CBAR | |
8316 | * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a | |
8317 | * 32-bit register visible to AArch32 at a different encoding | |
8318 | * to the "flavour 1" register and with the bits rearranged to | |
8319 | * be able to squash a 64-bit address into the 32-bit view. | |
8320 | * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but | |
8321 | * in future if we support AArch32-only configs of some of the | |
8322 | * AArch64 cores we might need to add a specific feature flag | |
8323 | * to indicate cores with "flavour 2" CBAR. | |
8324 | */ | |
f318cec6 PM |
8325 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
8326 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | |
8327 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | |
8328 | | extract64(cpu->reset_cbar, 32, 12); | |
8329 | ARMCPRegInfo cbar_reginfo[] = { | |
8330 | { .name = "CBAR", | |
8331 | .type = ARM_CP_CONST, | |
d56974af LM |
8332 | .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0, |
8333 | .access = PL1_R, .resetvalue = cbar32 }, | |
f318cec6 PM |
8334 | { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, |
8335 | .type = ARM_CP_CONST, | |
8336 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | |
d56974af | 8337 | .access = PL1_R, .resetvalue = cpu->reset_cbar }, |
f318cec6 PM |
8338 | }; |
8339 | /* We don't implement a r/w 64 bit CBAR currently */ | |
8340 | assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); | |
8341 | define_arm_cp_regs(cpu, cbar_reginfo); | |
8342 | } else { | |
8343 | ARMCPRegInfo cbar = { | |
8344 | .name = "CBAR", | |
8345 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
8346 | .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, | |
8347 | .fieldoffset = offsetof(CPUARMState, | |
8348 | cp15.c15_config_base_address) | |
8349 | }; | |
8350 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | |
8351 | cbar.access = PL1_R; | |
8352 | cbar.fieldoffset = 0; | |
8353 | cbar.type = ARM_CP_CONST; | |
8354 | } | |
8355 | define_one_arm_cp_reg(cpu, &cbar); | |
8356 | } | |
d8ba780b PC |
8357 | } |
8358 | ||
91db4642 | 8359 | if (arm_feature(env, ARM_FEATURE_VBAR)) { |
10b0220e | 8360 | static const ARMCPRegInfo vbar_cp_reginfo[] = { |
91db4642 CLG |
8361 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, |
8362 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | |
8363 | .access = PL1_RW, .writefn = vbar_write, | |
8364 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), | |
8365 | offsetof(CPUARMState, cp15.vbar_ns) }, | |
8366 | .resetvalue = 0 }, | |
91db4642 CLG |
8367 | }; |
8368 | define_arm_cp_regs(cpu, vbar_cp_reginfo); | |
8369 | } | |
8370 | ||
2771db27 PM |
8371 | /* Generic registers whose values depend on the implementation */ |
8372 | { | |
8373 | ARMCPRegInfo sctlr = { | |
5ebafdf3 | 8374 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, |
137feaa9 | 8375 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, |
84929218 | 8376 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
137feaa9 FA |
8377 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), |
8378 | offsetof(CPUARMState, cp15.sctlr_ns) }, | |
d4e6df63 PM |
8379 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, |
8380 | .raw_writefn = raw_write, | |
2771db27 PM |
8381 | }; |
8382 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
8383 | /* Normally we would always end the TB on an SCTLR write, but Linux | |
8384 | * arch/arm/mach-pxa/sleep.S expects two instructions following | |
8385 | * an MMU enable to execute from cache. Imitate this behaviour. | |
8386 | */ | |
8387 | sctlr.type |= ARM_CP_SUPPRESS_TB_END; | |
8388 | } | |
8389 | define_one_arm_cp_reg(cpu, &sctlr); | |
8390 | } | |
5be5e8ed | 8391 | |
2d7137c1 | 8392 | if (cpu_isar_feature(aa64_lor, cpu)) { |
2d7137c1 RH |
8393 | define_arm_cp_regs(cpu, lor_reginfo); |
8394 | } | |
220f508f RH |
8395 | if (cpu_isar_feature(aa64_pan, cpu)) { |
8396 | define_one_arm_cp_reg(cpu, &pan_reginfo); | |
8397 | } | |
04b07d29 RH |
8398 | #ifndef CONFIG_USER_ONLY |
8399 | if (cpu_isar_feature(aa64_ats1e1, cpu)) { | |
8400 | define_arm_cp_regs(cpu, ats1e1_reginfo); | |
8401 | } | |
8402 | if (cpu_isar_feature(aa32_ats1e1, cpu)) { | |
8403 | define_arm_cp_regs(cpu, ats1cp_reginfo); | |
8404 | } | |
8405 | #endif | |
9eeb7a1c RH |
8406 | if (cpu_isar_feature(aa64_uao, cpu)) { |
8407 | define_one_arm_cp_reg(cpu, &uao_reginfo); | |
8408 | } | |
2d7137c1 | 8409 | |
dc8b1853 RC |
8410 | if (cpu_isar_feature(aa64_dit, cpu)) { |
8411 | define_one_arm_cp_reg(cpu, &dit_reginfo); | |
8412 | } | |
f2f68a78 RC |
8413 | if (cpu_isar_feature(aa64_ssbs, cpu)) { |
8414 | define_one_arm_cp_reg(cpu, &ssbs_reginfo); | |
8415 | } | |
58e93b48 RH |
8416 | if (cpu_isar_feature(any_ras, cpu)) { |
8417 | define_arm_cp_regs(cpu, minimal_ras_reginfo); | |
8418 | } | |
dc8b1853 | 8419 | |
52d18727 RH |
8420 | if (cpu_isar_feature(aa64_vh, cpu) || |
8421 | cpu_isar_feature(aa64_debugv8p2, cpu)) { | |
8422 | define_one_arm_cp_reg(cpu, &contextidr_el2); | |
8423 | } | |
e2a1a461 RH |
8424 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { |
8425 | define_arm_cp_regs(cpu, vhe_reginfo); | |
8426 | } | |
8427 | ||
cd208a1c | 8428 | if (cpu_isar_feature(aa64_sve, cpu)) { |
60360d82 | 8429 | define_arm_cp_regs(cpu, zcr_reginfo); |
5be5e8ed | 8430 | } |
967aa94f | 8431 | |
5814d587 RH |
8432 | if (cpu_isar_feature(aa64_hcx, cpu)) { |
8433 | define_one_arm_cp_reg(cpu, &hcrx_el2_reginfo); | |
8434 | } | |
8435 | ||
967aa94f RH |
8436 | #ifdef TARGET_AARCH64 |
8437 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
8438 | define_arm_cp_regs(cpu, pauth_reginfo); | |
8439 | } | |
de390645 RH |
8440 | if (cpu_isar_feature(aa64_rndr, cpu)) { |
8441 | define_arm_cp_regs(cpu, rndr_reginfo); | |
8442 | } | |
84940ed8 RC |
8443 | if (cpu_isar_feature(aa64_tlbirange, cpu)) { |
8444 | define_arm_cp_regs(cpu, tlbirange_reginfo); | |
8445 | } | |
7113d618 RC |
8446 | if (cpu_isar_feature(aa64_tlbios, cpu)) { |
8447 | define_arm_cp_regs(cpu, tlbios_reginfo); | |
8448 | } | |
0d57b499 BM |
8449 | #ifndef CONFIG_USER_ONLY |
8450 | /* Data Cache clean instructions up to PoP */ | |
8451 | if (cpu_isar_feature(aa64_dcpop, cpu)) { | |
8452 | define_one_arm_cp_reg(cpu, dcpop_reg); | |
8453 | ||
8454 | if (cpu_isar_feature(aa64_dcpodp, cpu)) { | |
8455 | define_one_arm_cp_reg(cpu, dcpodp_reg); | |
8456 | } | |
8457 | } | |
8458 | #endif /*CONFIG_USER_ONLY*/ | |
4b779ceb RH |
8459 | |
8460 | /* | |
8461 | * If full MTE is enabled, add all of the system registers. | |
8462 | * If only "instructions available at EL0" are enabled, | |
8463 | * then define only a RAZ/WI version of PSTATE.TCO. | |
8464 | */ | |
8465 | if (cpu_isar_feature(aa64_mte, cpu)) { | |
8466 | define_arm_cp_regs(cpu, mte_reginfo); | |
5463df16 | 8467 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); |
4b779ceb RH |
8468 | } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { |
8469 | define_arm_cp_regs(cpu, mte_tco_ro_reginfo); | |
5463df16 | 8470 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); |
4b779ceb | 8471 | } |
7cb1e618 RH |
8472 | |
8473 | if (cpu_isar_feature(aa64_scxtnum, cpu)) { | |
8474 | define_arm_cp_regs(cpu, scxtnum_reginfo); | |
8475 | } | |
967aa94f | 8476 | #endif |
cb570bd3 | 8477 | |
22e57073 | 8478 | if (cpu_isar_feature(any_predinv, cpu)) { |
cb570bd3 RH |
8479 | define_arm_cp_regs(cpu, predinv_reginfo); |
8480 | } | |
e2cce18f | 8481 | |
957e6155 PM |
8482 | if (cpu_isar_feature(any_ccidx, cpu)) { |
8483 | define_arm_cp_regs(cpu, ccsidr2_reginfo); | |
8484 | } | |
8485 | ||
e2cce18f RH |
8486 | #ifndef CONFIG_USER_ONLY |
8487 | /* | |
8488 | * Register redirections and aliases must be done last, | |
8489 | * after the registers from the other extensions have been defined. | |
8490 | */ | |
8491 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { | |
8492 | define_arm_vh_e2h_redirects_aliases(cpu); | |
8493 | } | |
8494 | #endif | |
2ceb98c0 PM |
8495 | } |
8496 | ||
777dc784 PM |
8497 | /* Sort alphabetically by type name, except for "any". */ |
8498 | static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) | |
5adb4839 | 8499 | { |
777dc784 PM |
8500 | ObjectClass *class_a = (ObjectClass *)a; |
8501 | ObjectClass *class_b = (ObjectClass *)b; | |
8502 | const char *name_a, *name_b; | |
5adb4839 | 8503 | |
777dc784 PM |
8504 | name_a = object_class_get_name(class_a); |
8505 | name_b = object_class_get_name(class_b); | |
51492fd1 | 8506 | if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 | 8507 | return 1; |
51492fd1 | 8508 | } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 PM |
8509 | return -1; |
8510 | } else { | |
8511 | return strcmp(name_a, name_b); | |
5adb4839 PB |
8512 | } |
8513 | } | |
8514 | ||
777dc784 | 8515 | static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
40f137e1 | 8516 | { |
777dc784 | 8517 | ObjectClass *oc = data; |
51492fd1 AF |
8518 | const char *typename; |
8519 | char *name; | |
3371d272 | 8520 | |
51492fd1 AF |
8521 | typename = object_class_get_name(oc); |
8522 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
0442428a | 8523 | qemu_printf(" %s\n", name); |
51492fd1 | 8524 | g_free(name); |
777dc784 PM |
8525 | } |
8526 | ||
0442428a | 8527 | void arm_cpu_list(void) |
777dc784 | 8528 | { |
777dc784 PM |
8529 | GSList *list; |
8530 | ||
8531 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
8532 | list = g_slist_sort(list, arm_cpu_list_compare); | |
0442428a MA |
8533 | qemu_printf("Available CPUs:\n"); |
8534 | g_slist_foreach(list, arm_cpu_list_entry, NULL); | |
777dc784 | 8535 | g_slist_free(list); |
40f137e1 PB |
8536 | } |
8537 | ||
78027bb6 CR |
8538 | static void arm_cpu_add_definition(gpointer data, gpointer user_data) |
8539 | { | |
8540 | ObjectClass *oc = data; | |
8541 | CpuDefinitionInfoList **cpu_list = user_data; | |
78027bb6 CR |
8542 | CpuDefinitionInfo *info; |
8543 | const char *typename; | |
8544 | ||
8545 | typename = object_class_get_name(oc); | |
8546 | info = g_malloc0(sizeof(*info)); | |
8547 | info->name = g_strndup(typename, | |
8548 | strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
8ed877b7 | 8549 | info->q_typename = g_strdup(typename); |
78027bb6 | 8550 | |
54aa3de7 | 8551 | QAPI_LIST_PREPEND(*cpu_list, info); |
78027bb6 CR |
8552 | } |
8553 | ||
25a9d6ca | 8554 | CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) |
78027bb6 CR |
8555 | { |
8556 | CpuDefinitionInfoList *cpu_list = NULL; | |
8557 | GSList *list; | |
8558 | ||
8559 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
8560 | g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); | |
8561 | g_slist_free(list); | |
8562 | ||
8563 | return cpu_list; | |
8564 | } | |
8565 | ||
1859f8c3 RH |
8566 | /* |
8567 | * Private utility function for define_one_arm_cp_reg_with_opaque(): | |
8568 | * add a single reginfo struct to the hash table. | |
8569 | */ | |
6e6efd61 | 8570 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
cbe64585 RH |
8571 | void *opaque, CPState state, |
8572 | CPSecureState secstate, | |
9c513e78 AB |
8573 | int crm, int opc1, int opc2, |
8574 | const char *name) | |
6e6efd61 | 8575 | { |
696ba377 | 8576 | CPUARMState *env = &cpu->env; |
5860362d | 8577 | uint32_t key; |
c27f5d3a | 8578 | ARMCPRegInfo *r2; |
4c8c4541 RH |
8579 | bool is64 = r->type & ARM_CP_64BIT; |
8580 | bool ns = secstate & ARM_CP_SECSTATE_NS; | |
cac65299 | 8581 | int cp = r->cp; |
c27f5d3a | 8582 | size_t name_len; |
696ba377 | 8583 | bool make_const; |
c27f5d3a | 8584 | |
cac65299 RH |
8585 | switch (state) { |
8586 | case ARM_CP_STATE_AA32: | |
8587 | /* We assume it is a cp15 register if the .cp field is left unset. */ | |
8588 | if (cp == 0 && r->state == ARM_CP_STATE_BOTH) { | |
8589 | cp = 15; | |
8590 | } | |
8591 | key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2); | |
8592 | break; | |
8593 | case ARM_CP_STATE_AA64: | |
8594 | /* | |
8595 | * To allow abbreviation of ARMCPRegInfo definitions, we treat | |
8596 | * cp == 0 as equivalent to the value for "standard guest-visible | |
8597 | * sysreg". STATE_BOTH definitions are also always "standard sysreg" | |
8598 | * in their AArch64 view (the .cp value may be non-zero for the | |
8599 | * benefit of the AArch32 view). | |
8600 | */ | |
8601 | if (cp == 0 || r->state == ARM_CP_STATE_BOTH) { | |
8602 | cp = CP_REG_ARM64_SYSREG_CP; | |
8603 | } | |
8604 | key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2); | |
8605 | break; | |
8606 | default: | |
8607 | g_assert_not_reached(); | |
8608 | } | |
8609 | ||
dc44545b RH |
8610 | /* Overriding of an existing definition must be explicitly requested. */ |
8611 | if (!(r->type & ARM_CP_OVERRIDE)) { | |
8612 | const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key); | |
8613 | if (oldreg) { | |
8614 | assert(oldreg->type & ARM_CP_OVERRIDE); | |
8615 | } | |
8616 | } | |
8617 | ||
696ba377 RH |
8618 | /* |
8619 | * Eliminate registers that are not present because the EL is missing. | |
8620 | * Doing this here makes it easier to put all registers for a given | |
8621 | * feature into the same ARMCPRegInfo array and define them all at once. | |
8622 | */ | |
8623 | make_const = false; | |
8624 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
8625 | /* | |
8626 | * An EL2 register without EL2 but with EL3 is (usually) RES0. | |
8627 | * See rule RJFFP in section D1.1.3 of DDI0487H.a. | |
8628 | */ | |
8629 | int min_el = ctz32(r->access) / 2; | |
8630 | if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) { | |
8631 | if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { | |
8632 | return; | |
8633 | } | |
8634 | make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP); | |
8635 | } | |
8636 | } else { | |
8637 | CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2) | |
8638 | ? PL2_RW : PL1_RW); | |
8639 | if ((r->access & max_el) == 0) { | |
8640 | return; | |
8641 | } | |
8642 | } | |
8643 | ||
c27f5d3a RH |
8644 | /* Combine cpreg and name into one allocation. */ |
8645 | name_len = strlen(name) + 1; | |
8646 | r2 = g_malloc(sizeof(*r2) + name_len); | |
8647 | *r2 = *r; | |
8648 | r2->name = memcpy(r2 + 1, name, name_len); | |
3f3c82a5 | 8649 | |
cc946d96 RH |
8650 | /* |
8651 | * Update fields to match the instantiation, overwiting wildcards | |
8652 | * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH. | |
3f3c82a5 | 8653 | */ |
cc946d96 RH |
8654 | r2->cp = cp; |
8655 | r2->crm = crm; | |
8656 | r2->opc1 = opc1; | |
8657 | r2->opc2 = opc2; | |
8658 | r2->state = state; | |
3f3c82a5 | 8659 | r2->secure = secstate; |
cc946d96 RH |
8660 | if (opaque) { |
8661 | r2->opaque = opaque; | |
8662 | } | |
3f3c82a5 | 8663 | |
696ba377 RH |
8664 | if (make_const) { |
8665 | /* This should not have been a very special register to begin. */ | |
8666 | int old_special = r2->type & ARM_CP_SPECIAL_MASK; | |
8667 | assert(old_special == 0 || old_special == ARM_CP_NOP); | |
1859f8c3 | 8668 | /* |
696ba377 RH |
8669 | * Set the special function to CONST, retaining the other flags. |
8670 | * This is important for e.g. ARM_CP_SVE so that we still | |
8671 | * take the SVE trap if CPTR_EL3.EZ == 0. | |
f5a0a5a5 | 8672 | */ |
696ba377 RH |
8673 | r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST; |
8674 | /* | |
8675 | * Usually, these registers become RES0, but there are a few | |
8676 | * special cases like VPIDR_EL2 which have a constant non-zero | |
8677 | * value with writes ignored. | |
8678 | */ | |
8679 | if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { | |
8680 | r2->resetvalue = 0; | |
8681 | } | |
8682 | /* | |
8683 | * ARM_CP_CONST has precedence, so removing the callbacks and | |
8684 | * offsets are not strictly necessary, but it is potentially | |
8685 | * less confusing to debug later. | |
8686 | */ | |
8687 | r2->readfn = NULL; | |
8688 | r2->writefn = NULL; | |
8689 | r2->raw_readfn = NULL; | |
8690 | r2->raw_writefn = NULL; | |
8691 | r2->resetfn = NULL; | |
8692 | r2->fieldoffset = 0; | |
8693 | r2->bank_fieldoffsets[0] = 0; | |
8694 | r2->bank_fieldoffsets[1] = 0; | |
8695 | } else { | |
8696 | bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; | |
3f3c82a5 | 8697 | |
10748a96 | 8698 | if (isbanked) { |
1859f8c3 | 8699 | /* |
696ba377 RH |
8700 | * Register is banked (using both entries in array). |
8701 | * Overwriting fieldoffset as the array is only used to define | |
8702 | * banked registers but later only fieldoffset is used. | |
3f3c82a5 | 8703 | */ |
696ba377 RH |
8704 | r2->fieldoffset = r->bank_fieldoffsets[ns]; |
8705 | } | |
8706 | if (state == ARM_CP_STATE_AA32) { | |
8707 | if (isbanked) { | |
8708 | /* | |
8709 | * If the register is banked then we don't need to migrate or | |
8710 | * reset the 32-bit instance in certain cases: | |
8711 | * | |
8712 | * 1) If the register has both 32-bit and 64-bit instances | |
8713 | * then we can count on the 64-bit instance taking care | |
8714 | * of the non-secure bank. | |
8715 | * 2) If ARMv8 is enabled then we can count on a 64-bit | |
8716 | * version taking care of the secure bank. This requires | |
8717 | * that separate 32 and 64-bit definitions are provided. | |
8718 | */ | |
8719 | if ((r->state == ARM_CP_STATE_BOTH && ns) || | |
8720 | (arm_feature(env, ARM_FEATURE_V8) && !ns)) { | |
8721 | r2->type |= ARM_CP_ALIAS; | |
8722 | } | |
8723 | } else if ((secstate != r->secure) && !ns) { | |
8724 | /* | |
8725 | * The register is not banked so we only want to allow | |
8726 | * migration of the non-secure instance. | |
8727 | */ | |
7a0e58fa | 8728 | r2->type |= ARM_CP_ALIAS; |
3f3c82a5 | 8729 | } |
3f3c82a5 | 8730 | |
696ba377 RH |
8731 | if (HOST_BIG_ENDIAN && |
8732 | r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) { | |
8733 | r2->fieldoffset += sizeof(uint32_t); | |
8734 | } | |
3f3c82a5 | 8735 | } |
f5a0a5a5 | 8736 | } |
cc946d96 | 8737 | |
1859f8c3 RH |
8738 | /* |
8739 | * By convention, for wildcarded registers only the first | |
6e6efd61 | 8740 | * entry is used for migration; the others are marked as |
7a0e58fa | 8741 | * ALIAS so we don't try to transfer the register |
6e6efd61 | 8742 | * multiple times. Special registers (ie NOP/WFI) are |
7a0e58fa | 8743 | * never migratable and not even raw-accessible. |
6e6efd61 | 8744 | */ |
696ba377 | 8745 | if (r2->type & ARM_CP_SPECIAL_MASK) { |
7a0e58fa PM |
8746 | r2->type |= ARM_CP_NO_RAW; |
8747 | } | |
8748 | if (((r->crm == CP_ANY) && crm != 0) || | |
6e6efd61 PM |
8749 | ((r->opc1 == CP_ANY) && opc1 != 0) || |
8750 | ((r->opc2 == CP_ANY) && opc2 != 0)) { | |
1f163787 | 8751 | r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB; |
6e6efd61 PM |
8752 | } |
8753 | ||
1859f8c3 RH |
8754 | /* |
8755 | * Check that raw accesses are either forbidden or handled. Note that | |
375421cc PM |
8756 | * we can't assert this earlier because the setup of fieldoffset for |
8757 | * banked registers has to be done first. | |
8758 | */ | |
8759 | if (!(r2->type & ARM_CP_NO_RAW)) { | |
8760 | assert(!raw_accessors_invalid(r2)); | |
8761 | } | |
8762 | ||
5860362d | 8763 | g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); |
6e6efd61 PM |
8764 | } |
8765 | ||
8766 | ||
4b6a83fb PM |
8767 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
8768 | const ARMCPRegInfo *r, void *opaque) | |
8769 | { | |
8770 | /* Define implementations of coprocessor registers. | |
8771 | * We store these in a hashtable because typically | |
8772 | * there are less than 150 registers in a space which | |
8773 | * is 16*16*16*8*8 = 262144 in size. | |
8774 | * Wildcarding is supported for the crm, opc1 and opc2 fields. | |
8775 | * If a register is defined twice then the second definition is | |
8776 | * used, so this can be used to define some generic registers and | |
8777 | * then override them with implementation specific variations. | |
8778 | * At least one of the original and the second definition should | |
8779 | * include ARM_CP_OVERRIDE in its type bits -- this is just a guard | |
8780 | * against accidental use. | |
f5a0a5a5 PM |
8781 | * |
8782 | * The state field defines whether the register is to be | |
8783 | * visible in the AArch32 or AArch64 execution state. If the | |
8784 | * state is set to ARM_CP_STATE_BOTH then we synthesise a | |
8785 | * reginfo structure for the AArch32 view, which sees the lower | |
8786 | * 32 bits of the 64 bit register. | |
8787 | * | |
8788 | * Only registers visible in AArch64 may set r->opc0; opc0 cannot | |
8789 | * be wildcarded. AArch64 registers are always considered to be 64 | |
8790 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | |
8791 | * the register, if any. | |
4b6a83fb | 8792 | */ |
d95101d6 | 8793 | int crm, opc1, opc2; |
4b6a83fb PM |
8794 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
8795 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | |
8796 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | |
8797 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | |
8798 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | |
8799 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | |
d95101d6 RH |
8800 | CPState state; |
8801 | ||
4b6a83fb PM |
8802 | /* 64 bit registers have only CRm and Opc1 fields */ |
8803 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | |
f5a0a5a5 PM |
8804 | /* op0 only exists in the AArch64 encodings */ |
8805 | assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); | |
8806 | /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ | |
8807 | assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); | |
cd8be50e PM |
8808 | /* |
8809 | * This API is only for Arm's system coprocessors (14 and 15) or | |
8810 | * (M-profile or v7A-and-earlier only) for implementation defined | |
8811 | * coprocessors in the range 0..7. Our decode assumes this, since | |
8812 | * 8..13 can be used for other insns including VFP and Neon. See | |
8813 | * valid_cp() in translate.c. Assert here that we haven't tried | |
8814 | * to use an invalid coprocessor number. | |
8815 | */ | |
8816 | switch (r->state) { | |
8817 | case ARM_CP_STATE_BOTH: | |
8818 | /* 0 has a special meaning, but otherwise the same rules as AA32. */ | |
8819 | if (r->cp == 0) { | |
8820 | break; | |
8821 | } | |
8822 | /* fall through */ | |
8823 | case ARM_CP_STATE_AA32: | |
8824 | if (arm_feature(&cpu->env, ARM_FEATURE_V8) && | |
8825 | !arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
8826 | assert(r->cp >= 14 && r->cp <= 15); | |
8827 | } else { | |
8828 | assert(r->cp < 8 || (r->cp >= 14 && r->cp <= 15)); | |
8829 | } | |
8830 | break; | |
8831 | case ARM_CP_STATE_AA64: | |
8832 | assert(r->cp == 0 || r->cp == CP_REG_ARM64_SYSREG_CP); | |
8833 | break; | |
8834 | default: | |
8835 | g_assert_not_reached(); | |
8836 | } | |
f5a0a5a5 PM |
8837 | /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 |
8838 | * encodes a minimum access level for the register. We roll this | |
8839 | * runtime check into our general permission check code, so check | |
8840 | * here that the reginfo's specified permissions are strict enough | |
8841 | * to encompass the generic architectural permission check. | |
8842 | */ | |
8843 | if (r->state != ARM_CP_STATE_AA32) { | |
39107337 | 8844 | CPAccessRights mask; |
f5a0a5a5 | 8845 | switch (r->opc1) { |
b5bd7440 AB |
8846 | case 0: |
8847 | /* min_EL EL1, but some accessible to EL0 via kernel ABI */ | |
8848 | mask = PL0U_R | PL1_RW; | |
8849 | break; | |
8850 | case 1: case 2: | |
f5a0a5a5 PM |
8851 | /* min_EL EL1 */ |
8852 | mask = PL1_RW; | |
8853 | break; | |
8854 | case 3: | |
8855 | /* min_EL EL0 */ | |
8856 | mask = PL0_RW; | |
8857 | break; | |
8858 | case 4: | |
b4ecf60f | 8859 | case 5: |
f5a0a5a5 PM |
8860 | /* min_EL EL2 */ |
8861 | mask = PL2_RW; | |
8862 | break; | |
f5a0a5a5 PM |
8863 | case 6: |
8864 | /* min_EL EL3 */ | |
8865 | mask = PL3_RW; | |
8866 | break; | |
8867 | case 7: | |
8868 | /* min_EL EL1, secure mode only (we don't check the latter) */ | |
8869 | mask = PL1_RW; | |
8870 | break; | |
8871 | default: | |
8872 | /* broken reginfo with out-of-range opc1 */ | |
d385a605 | 8873 | g_assert_not_reached(); |
f5a0a5a5 PM |
8874 | } |
8875 | /* assert our permissions are not too lax (stricter is fine) */ | |
8876 | assert((r->access & ~mask) == 0); | |
8877 | } | |
8878 | ||
4b6a83fb PM |
8879 | /* Check that the register definition has enough info to handle |
8880 | * reads and writes if they are permitted. | |
8881 | */ | |
87c3f0f2 | 8882 | if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) { |
4b6a83fb | 8883 | if (r->access & PL3_R) { |
3f3c82a5 FA |
8884 | assert((r->fieldoffset || |
8885 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
8886 | r->readfn); | |
4b6a83fb PM |
8887 | } |
8888 | if (r->access & PL3_W) { | |
3f3c82a5 FA |
8889 | assert((r->fieldoffset || |
8890 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
8891 | r->writefn); | |
4b6a83fb PM |
8892 | } |
8893 | } | |
5809ac57 | 8894 | |
4b6a83fb PM |
8895 | for (crm = crmmin; crm <= crmmax; crm++) { |
8896 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | |
8897 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | |
f5a0a5a5 PM |
8898 | for (state = ARM_CP_STATE_AA32; |
8899 | state <= ARM_CP_STATE_AA64; state++) { | |
8900 | if (r->state != state && r->state != ARM_CP_STATE_BOTH) { | |
8901 | continue; | |
8902 | } | |
3f3c82a5 FA |
8903 | if (state == ARM_CP_STATE_AA32) { |
8904 | /* Under AArch32 CP registers can be common | |
8905 | * (same for secure and non-secure world) or banked. | |
8906 | */ | |
9c513e78 AB |
8907 | char *name; |
8908 | ||
3f3c82a5 FA |
8909 | switch (r->secure) { |
8910 | case ARM_CP_SECSTATE_S: | |
8911 | case ARM_CP_SECSTATE_NS: | |
8912 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
9c513e78 AB |
8913 | r->secure, crm, opc1, opc2, |
8914 | r->name); | |
3f3c82a5 | 8915 | break; |
cbe64585 | 8916 | case ARM_CP_SECSTATE_BOTH: |
9c513e78 | 8917 | name = g_strdup_printf("%s_S", r->name); |
3f3c82a5 FA |
8918 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
8919 | ARM_CP_SECSTATE_S, | |
9c513e78 AB |
8920 | crm, opc1, opc2, name); |
8921 | g_free(name); | |
3f3c82a5 FA |
8922 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
8923 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 8924 | crm, opc1, opc2, r->name); |
3f3c82a5 | 8925 | break; |
cbe64585 RH |
8926 | default: |
8927 | g_assert_not_reached(); | |
3f3c82a5 FA |
8928 | } |
8929 | } else { | |
8930 | /* AArch64 registers get mapped to non-secure instance | |
8931 | * of AArch32 */ | |
8932 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
8933 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 8934 | crm, opc1, opc2, r->name); |
3f3c82a5 | 8935 | } |
f5a0a5a5 | 8936 | } |
4b6a83fb PM |
8937 | } |
8938 | } | |
8939 | } | |
8940 | } | |
8941 | ||
5809ac57 RH |
8942 | /* Define a whole list of registers */ |
8943 | void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs, | |
8944 | void *opaque, size_t len) | |
4b6a83fb | 8945 | { |
5809ac57 RH |
8946 | size_t i; |
8947 | for (i = 0; i < len; ++i) { | |
8948 | define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque); | |
4b6a83fb PM |
8949 | } |
8950 | } | |
8951 | ||
6c5c0fec AB |
8952 | /* |
8953 | * Modify ARMCPRegInfo for access from userspace. | |
8954 | * | |
8955 | * This is a data driven modification directed by | |
8956 | * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as | |
8957 | * user-space cannot alter any values and dynamic values pertaining to | |
8958 | * execution state are hidden from user space view anyway. | |
8959 | */ | |
5809ac57 RH |
8960 | void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, |
8961 | const ARMCPRegUserSpaceInfo *mods, | |
8962 | size_t mods_len) | |
6c5c0fec | 8963 | { |
5809ac57 RH |
8964 | for (size_t mi = 0; mi < mods_len; ++mi) { |
8965 | const ARMCPRegUserSpaceInfo *m = mods + mi; | |
d040242e | 8966 | GPatternSpec *pat = NULL; |
5809ac57 | 8967 | |
d040242e AB |
8968 | if (m->is_glob) { |
8969 | pat = g_pattern_spec_new(m->name); | |
8970 | } | |
5809ac57 RH |
8971 | for (size_t ri = 0; ri < regs_len; ++ri) { |
8972 | ARMCPRegInfo *r = regs + ri; | |
8973 | ||
d040242e AB |
8974 | if (pat && g_pattern_match_string(pat, r->name)) { |
8975 | r->type = ARM_CP_CONST; | |
8976 | r->access = PL0U_R; | |
8977 | r->resetvalue = 0; | |
8978 | /* continue */ | |
8979 | } else if (strcmp(r->name, m->name) == 0) { | |
6c5c0fec AB |
8980 | r->type = ARM_CP_CONST; |
8981 | r->access = PL0U_R; | |
8982 | r->resetvalue &= m->exported_bits; | |
8983 | r->resetvalue |= m->fixed_bits; | |
8984 | break; | |
8985 | } | |
8986 | } | |
d040242e AB |
8987 | if (pat) { |
8988 | g_pattern_spec_free(pat); | |
8989 | } | |
6c5c0fec AB |
8990 | } |
8991 | } | |
8992 | ||
60322b39 | 8993 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) |
4b6a83fb | 8994 | { |
5860362d | 8995 | return g_hash_table_lookup(cpregs, (gpointer)(uintptr_t)encoded_cp); |
4b6a83fb PM |
8996 | } |
8997 | ||
c4241c7d PM |
8998 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
8999 | uint64_t value) | |
4b6a83fb PM |
9000 | { |
9001 | /* Helper coprocessor write function for write-ignore registers */ | |
4b6a83fb PM |
9002 | } |
9003 | ||
c4241c7d | 9004 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) |
4b6a83fb PM |
9005 | { |
9006 | /* Helper coprocessor write function for read-as-zero registers */ | |
4b6a83fb PM |
9007 | return 0; |
9008 | } | |
9009 | ||
f5a0a5a5 PM |
9010 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) |
9011 | { | |
9012 | /* Helper coprocessor reset function for do-nothing-on-reset registers */ | |
9013 | } | |
9014 | ||
af393ffc | 9015 | static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) |
37064a8b PM |
9016 | { |
9017 | /* Return true if it is not valid for us to switch to | |
9018 | * this CPU mode (ie all the UNPREDICTABLE cases in | |
9019 | * the ARM ARM CPSRWriteByInstr pseudocode). | |
9020 | */ | |
af393ffc PM |
9021 | |
9022 | /* Changes to or from Hyp via MSR and CPS are illegal. */ | |
9023 | if (write_type == CPSRWriteByInstr && | |
9024 | ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || | |
9025 | mode == ARM_CPU_MODE_HYP)) { | |
9026 | return 1; | |
9027 | } | |
9028 | ||
37064a8b PM |
9029 | switch (mode) { |
9030 | case ARM_CPU_MODE_USR: | |
10eacda7 | 9031 | return 0; |
37064a8b PM |
9032 | case ARM_CPU_MODE_SYS: |
9033 | case ARM_CPU_MODE_SVC: | |
9034 | case ARM_CPU_MODE_ABT: | |
9035 | case ARM_CPU_MODE_UND: | |
9036 | case ARM_CPU_MODE_IRQ: | |
9037 | case ARM_CPU_MODE_FIQ: | |
52ff951b PM |
9038 | /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 |
9039 | * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) | |
9040 | */ | |
10eacda7 PM |
9041 | /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR |
9042 | * and CPS are treated as illegal mode changes. | |
9043 | */ | |
9044 | if (write_type == CPSRWriteByInstr && | |
10eacda7 | 9045 | (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && |
7c208e0f | 9046 | (arm_hcr_el2_eff(env) & HCR_TGE)) { |
10eacda7 PM |
9047 | return 1; |
9048 | } | |
37064a8b | 9049 | return 0; |
e6c8fc07 | 9050 | case ARM_CPU_MODE_HYP: |
e6ef0169 | 9051 | return !arm_is_el2_enabled(env) || arm_current_el(env) < 2; |
027fc527 | 9052 | case ARM_CPU_MODE_MON: |
58ae2d1f | 9053 | return arm_current_el(env) < 3; |
37064a8b PM |
9054 | default: |
9055 | return 1; | |
9056 | } | |
9057 | } | |
9058 | ||
2f4a40e5 AZ |
9059 | uint32_t cpsr_read(CPUARMState *env) |
9060 | { | |
9061 | int ZF; | |
6fbe23d5 PB |
9062 | ZF = (env->ZF == 0); |
9063 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
9064 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
9065 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
9066 | | ((env->condexec_bits & 0xfc) << 8) | |
af519934 | 9067 | | (env->GE << 16) | (env->daif & CPSR_AIF); |
2f4a40e5 AZ |
9068 | } |
9069 | ||
50866ba5 PM |
9070 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, |
9071 | CPSRWriteType write_type) | |
2f4a40e5 | 9072 | { |
6e8801f9 | 9073 | uint32_t changed_daif; |
e784807c PM |
9074 | bool rebuild_hflags = (write_type != CPSRWriteRaw) && |
9075 | (mask & (CPSR_M | CPSR_E | CPSR_IL)); | |
6e8801f9 | 9076 | |
2f4a40e5 | 9077 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
9078 | env->ZF = (~val) & CPSR_Z; |
9079 | env->NF = val; | |
2f4a40e5 AZ |
9080 | env->CF = (val >> 29) & 1; |
9081 | env->VF = (val << 3) & 0x80000000; | |
9082 | } | |
9083 | if (mask & CPSR_Q) | |
9084 | env->QF = ((val & CPSR_Q) != 0); | |
9085 | if (mask & CPSR_T) | |
9086 | env->thumb = ((val & CPSR_T) != 0); | |
9087 | if (mask & CPSR_IT_0_1) { | |
9088 | env->condexec_bits &= ~3; | |
9089 | env->condexec_bits |= (val >> 25) & 3; | |
9090 | } | |
9091 | if (mask & CPSR_IT_2_7) { | |
9092 | env->condexec_bits &= 3; | |
9093 | env->condexec_bits |= (val >> 8) & 0xfc; | |
9094 | } | |
9095 | if (mask & CPSR_GE) { | |
9096 | env->GE = (val >> 16) & 0xf; | |
9097 | } | |
9098 | ||
6e8801f9 FA |
9099 | /* In a V7 implementation that includes the security extensions but does |
9100 | * not include Virtualization Extensions the SCR.FW and SCR.AW bits control | |
9101 | * whether non-secure software is allowed to change the CPSR_F and CPSR_A | |
9102 | * bits respectively. | |
9103 | * | |
9104 | * In a V8 implementation, it is permitted for privileged software to | |
9105 | * change the CPSR A/F bits regardless of the SCR.AW/FW bits. | |
9106 | */ | |
f8c88bbc | 9107 | if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && |
6e8801f9 FA |
9108 | arm_feature(env, ARM_FEATURE_EL3) && |
9109 | !arm_feature(env, ARM_FEATURE_EL2) && | |
9110 | !arm_is_secure(env)) { | |
9111 | ||
9112 | changed_daif = (env->daif ^ val) & mask; | |
9113 | ||
9114 | if (changed_daif & CPSR_A) { | |
9115 | /* Check to see if we are allowed to change the masking of async | |
9116 | * abort exceptions from a non-secure state. | |
9117 | */ | |
9118 | if (!(env->cp15.scr_el3 & SCR_AW)) { | |
9119 | qemu_log_mask(LOG_GUEST_ERROR, | |
9120 | "Ignoring attempt to switch CPSR_A flag from " | |
9121 | "non-secure world with SCR.AW bit clear\n"); | |
9122 | mask &= ~CPSR_A; | |
9123 | } | |
9124 | } | |
9125 | ||
9126 | if (changed_daif & CPSR_F) { | |
9127 | /* Check to see if we are allowed to change the masking of FIQ | |
9128 | * exceptions from a non-secure state. | |
9129 | */ | |
9130 | if (!(env->cp15.scr_el3 & SCR_FW)) { | |
9131 | qemu_log_mask(LOG_GUEST_ERROR, | |
9132 | "Ignoring attempt to switch CPSR_F flag from " | |
9133 | "non-secure world with SCR.FW bit clear\n"); | |
9134 | mask &= ~CPSR_F; | |
9135 | } | |
9136 | ||
9137 | /* Check whether non-maskable FIQ (NMFI) support is enabled. | |
9138 | * If this bit is set software is not allowed to mask | |
9139 | * FIQs, but is allowed to set CPSR_F to 0. | |
9140 | */ | |
9141 | if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && | |
9142 | (val & CPSR_F)) { | |
9143 | qemu_log_mask(LOG_GUEST_ERROR, | |
9144 | "Ignoring attempt to enable CPSR_F flag " | |
9145 | "(non-maskable FIQ [NMFI] support enabled)\n"); | |
9146 | mask &= ~CPSR_F; | |
9147 | } | |
9148 | } | |
9149 | } | |
9150 | ||
4cc35614 PM |
9151 | env->daif &= ~(CPSR_AIF & mask); |
9152 | env->daif |= val & CPSR_AIF & mask; | |
9153 | ||
f8c88bbc PM |
9154 | if (write_type != CPSRWriteRaw && |
9155 | ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { | |
8c4f0eb9 PM |
9156 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { |
9157 | /* Note that we can only get here in USR mode if this is a | |
9158 | * gdb stub write; for this case we follow the architectural | |
9159 | * behaviour for guest writes in USR mode of ignoring an attempt | |
9160 | * to switch mode. (Those are caught by translate.c for writes | |
9161 | * triggered by guest instructions.) | |
9162 | */ | |
9163 | mask &= ~CPSR_M; | |
9164 | } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { | |
81907a58 PM |
9165 | /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in |
9166 | * v7, and has defined behaviour in v8: | |
9167 | * + leave CPSR.M untouched | |
9168 | * + allow changes to the other CPSR fields | |
9169 | * + set PSTATE.IL | |
9170 | * For user changes via the GDB stub, we don't set PSTATE.IL, | |
9171 | * as this would be unnecessarily harsh for a user error. | |
37064a8b PM |
9172 | */ |
9173 | mask &= ~CPSR_M; | |
81907a58 PM |
9174 | if (write_type != CPSRWriteByGDBStub && |
9175 | arm_feature(env, ARM_FEATURE_V8)) { | |
9176 | mask |= CPSR_IL; | |
9177 | val |= CPSR_IL; | |
9178 | } | |
81e37284 PM |
9179 | qemu_log_mask(LOG_GUEST_ERROR, |
9180 | "Illegal AArch32 mode switch attempt from %s to %s\n", | |
9181 | aarch32_mode_name(env->uncached_cpsr), | |
9182 | aarch32_mode_name(val)); | |
37064a8b | 9183 | } else { |
81e37284 PM |
9184 | qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n", |
9185 | write_type == CPSRWriteExceptionReturn ? | |
9186 | "Exception return from AArch32" : | |
9187 | "AArch32 mode switch from", | |
9188 | aarch32_mode_name(env->uncached_cpsr), | |
9189 | aarch32_mode_name(val), env->regs[15]); | |
37064a8b PM |
9190 | switch_mode(env, val & CPSR_M); |
9191 | } | |
2f4a40e5 AZ |
9192 | } |
9193 | mask &= ~CACHED_CPSR_BITS; | |
9194 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
e784807c PM |
9195 | if (rebuild_hflags) { |
9196 | arm_rebuild_hflags(env); | |
9197 | } | |
2f4a40e5 AZ |
9198 | } |
9199 | ||
b26eefb6 PB |
9200 | /* Sign/zero extend */ |
9201 | uint32_t HELPER(sxtb16)(uint32_t x) | |
9202 | { | |
9203 | uint32_t res; | |
9204 | res = (uint16_t)(int8_t)x; | |
9205 | res |= (uint32_t)(int8_t)(x >> 16) << 16; | |
9206 | return res; | |
9207 | } | |
9208 | ||
e5346292 PM |
9209 | static void handle_possible_div0_trap(CPUARMState *env, uintptr_t ra) |
9210 | { | |
9211 | /* | |
9212 | * Take a division-by-zero exception if necessary; otherwise return | |
9213 | * to get the usual non-trapping division behaviour (result of 0) | |
9214 | */ | |
9215 | if (arm_feature(env, ARM_FEATURE_M) | |
9216 | && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { | |
9217 | raise_exception_ra(env, EXCP_DIVBYZERO, 0, 1, ra); | |
9218 | } | |
9219 | } | |
9220 | ||
b26eefb6 PB |
9221 | uint32_t HELPER(uxtb16)(uint32_t x) |
9222 | { | |
9223 | uint32_t res; | |
9224 | res = (uint16_t)(uint8_t)x; | |
9225 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; | |
9226 | return res; | |
9227 | } | |
9228 | ||
e5346292 | 9229 | int32_t HELPER(sdiv)(CPUARMState *env, int32_t num, int32_t den) |
3670669c | 9230 | { |
fc7a5038 | 9231 | if (den == 0) { |
e5346292 | 9232 | handle_possible_div0_trap(env, GETPC()); |
fc7a5038 PM |
9233 | return 0; |
9234 | } | |
9235 | if (num == INT_MIN && den == -1) { | |
9236 | return INT_MIN; | |
9237 | } | |
3670669c PB |
9238 | return num / den; |
9239 | } | |
9240 | ||
e5346292 | 9241 | uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den) |
3670669c | 9242 | { |
fc7a5038 | 9243 | if (den == 0) { |
e5346292 | 9244 | handle_possible_div0_trap(env, GETPC()); |
fc7a5038 PM |
9245 | return 0; |
9246 | } | |
3670669c PB |
9247 | return num / den; |
9248 | } | |
9249 | ||
9250 | uint32_t HELPER(rbit)(uint32_t x) | |
9251 | { | |
42fedbca | 9252 | return revbit32(x); |
3670669c PB |
9253 | } |
9254 | ||
c47eaf9f | 9255 | #ifdef CONFIG_USER_ONLY |
b5ff1b31 | 9256 | |
affdb64d | 9257 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 | 9258 | { |
2fc0cc0e | 9259 | ARMCPU *cpu = env_archcpu(env); |
a47dddd7 AF |
9260 | |
9261 | if (mode != ARM_CPU_MODE_USR) { | |
9262 | cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); | |
9263 | } | |
b5ff1b31 FB |
9264 | } |
9265 | ||
012a906b GB |
9266 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
9267 | uint32_t cur_el, bool secure) | |
9e729b57 EI |
9268 | { |
9269 | return 1; | |
9270 | } | |
9271 | ||
ce02049d GB |
9272 | void aarch64_sync_64_to_32(CPUARMState *env) |
9273 | { | |
9274 | g_assert_not_reached(); | |
9275 | } | |
9276 | ||
b5ff1b31 FB |
9277 | #else |
9278 | ||
affdb64d | 9279 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
9280 | { |
9281 | int old_mode; | |
9282 | int i; | |
9283 | ||
9284 | old_mode = env->uncached_cpsr & CPSR_M; | |
9285 | if (mode == old_mode) | |
9286 | return; | |
9287 | ||
9288 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
9289 | memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 9290 | memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
9291 | } else if (mode == ARM_CPU_MODE_FIQ) { |
9292 | memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 9293 | memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
9294 | } |
9295 | ||
f5206413 | 9296 | i = bank_number(old_mode); |
b5ff1b31 | 9297 | env->banked_r13[i] = env->regs[13]; |
b5ff1b31 FB |
9298 | env->banked_spsr[i] = env->spsr; |
9299 | ||
f5206413 | 9300 | i = bank_number(mode); |
b5ff1b31 | 9301 | env->regs[13] = env->banked_r13[i]; |
b5ff1b31 | 9302 | env->spsr = env->banked_spsr[i]; |
593cfa2b PM |
9303 | |
9304 | env->banked_r14[r14_bank_number(old_mode)] = env->regs[14]; | |
9305 | env->regs[14] = env->banked_r14[r14_bank_number(mode)]; | |
b5ff1b31 FB |
9306 | } |
9307 | ||
0eeb17d6 GB |
9308 | /* Physical Interrupt Target EL Lookup Table |
9309 | * | |
9310 | * [ From ARM ARM section G1.13.4 (Table G1-15) ] | |
9311 | * | |
9312 | * The below multi-dimensional table is used for looking up the target | |
9313 | * exception level given numerous condition criteria. Specifically, the | |
9314 | * target EL is based on SCR and HCR routing controls as well as the | |
9315 | * currently executing EL and secure state. | |
9316 | * | |
9317 | * Dimensions: | |
9318 | * target_el_table[2][2][2][2][2][4] | |
9319 | * | | | | | +--- Current EL | |
9320 | * | | | | +------ Non-secure(0)/Secure(1) | |
9321 | * | | | +--------- HCR mask override | |
9322 | * | | +------------ SCR exec state control | |
9323 | * | +--------------- SCR mask override | |
9324 | * +------------------ 32-bit(0)/64-bit(1) EL3 | |
9325 | * | |
9326 | * The table values are as such: | |
9327 | * 0-3 = EL0-EL3 | |
9328 | * -1 = Cannot occur | |
9329 | * | |
9330 | * The ARM ARM target EL table includes entries indicating that an "exception | |
9331 | * is not taken". The two cases where this is applicable are: | |
9332 | * 1) An exception is taken from EL3 but the SCR does not have the exception | |
9333 | * routed to EL3. | |
9334 | * 2) An exception is taken from EL2 but the HCR does not have the exception | |
9335 | * routed to EL2. | |
9336 | * In these two cases, the below table contain a target of EL1. This value is | |
9337 | * returned as it is expected that the consumer of the table data will check | |
9338 | * for "target EL >= current EL" to ensure the exception is not taken. | |
9339 | * | |
9340 | * SCR HCR | |
9341 | * 64 EA AMO From | |
9342 | * BIT IRQ IMO Non-secure Secure | |
9343 | * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 | |
9344 | */ | |
82c39f6a | 9345 | static const int8_t target_el_table[2][2][2][2][2][4] = { |
0eeb17d6 GB |
9346 | {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, |
9347 | {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, | |
9348 | {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, | |
9349 | {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, | |
9350 | {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
9351 | {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, | |
9352 | {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
9353 | {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, | |
9354 | {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, | |
6c85f906 RDC |
9355 | {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},}, |
9356 | {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },}, | |
9357 | {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},}, | |
0eeb17d6 GB |
9358 | {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, |
9359 | {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, | |
6c85f906 RDC |
9360 | {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },}, |
9361 | {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},}, | |
0eeb17d6 GB |
9362 | }; |
9363 | ||
9364 | /* | |
9365 | * Determine the target EL for physical exceptions | |
9366 | */ | |
012a906b GB |
9367 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
9368 | uint32_t cur_el, bool secure) | |
0eeb17d6 GB |
9369 | { |
9370 | CPUARMState *env = cs->env_ptr; | |
f7778444 RH |
9371 | bool rw; |
9372 | bool scr; | |
9373 | bool hcr; | |
0eeb17d6 | 9374 | int target_el; |
2cde031f | 9375 | /* Is the highest EL AArch64? */ |
f7778444 RH |
9376 | bool is64 = arm_feature(env, ARM_FEATURE_AARCH64); |
9377 | uint64_t hcr_el2; | |
2cde031f SS |
9378 | |
9379 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
9380 | rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); | |
9381 | } else { | |
9382 | /* Either EL2 is the highest EL (and so the EL2 register width | |
9383 | * is given by is64); or there is no EL2 or EL3, in which case | |
9384 | * the value of 'rw' does not affect the table lookup anyway. | |
9385 | */ | |
9386 | rw = is64; | |
9387 | } | |
0eeb17d6 | 9388 | |
f7778444 | 9389 | hcr_el2 = arm_hcr_el2_eff(env); |
0eeb17d6 GB |
9390 | switch (excp_idx) { |
9391 | case EXCP_IRQ: | |
9392 | scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); | |
f7778444 | 9393 | hcr = hcr_el2 & HCR_IMO; |
0eeb17d6 GB |
9394 | break; |
9395 | case EXCP_FIQ: | |
9396 | scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); | |
f7778444 | 9397 | hcr = hcr_el2 & HCR_FMO; |
0eeb17d6 GB |
9398 | break; |
9399 | default: | |
9400 | scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); | |
f7778444 | 9401 | hcr = hcr_el2 & HCR_AMO; |
0eeb17d6 GB |
9402 | break; |
9403 | }; | |
9404 | ||
d1b31428 RH |
9405 | /* |
9406 | * For these purposes, TGE and AMO/IMO/FMO both force the | |
9407 | * interrupt to EL2. Fold TGE into the bit extracted above. | |
9408 | */ | |
9409 | hcr |= (hcr_el2 & HCR_TGE) != 0; | |
9410 | ||
0eeb17d6 GB |
9411 | /* Perform a table-lookup for the target EL given the current state */ |
9412 | target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; | |
9413 | ||
9414 | assert(target_el > 0); | |
9415 | ||
9416 | return target_el; | |
9417 | } | |
9418 | ||
fc6177af | 9419 | void arm_log_exception(CPUState *cs) |
b59f479b | 9420 | { |
fc6177af PM |
9421 | int idx = cs->exception_index; |
9422 | ||
b59f479b PMD |
9423 | if (qemu_loglevel_mask(CPU_LOG_INT)) { |
9424 | const char *exc = NULL; | |
9425 | static const char * const excnames[] = { | |
9426 | [EXCP_UDEF] = "Undefined Instruction", | |
9427 | [EXCP_SWI] = "SVC", | |
9428 | [EXCP_PREFETCH_ABORT] = "Prefetch Abort", | |
9429 | [EXCP_DATA_ABORT] = "Data Abort", | |
9430 | [EXCP_IRQ] = "IRQ", | |
9431 | [EXCP_FIQ] = "FIQ", | |
9432 | [EXCP_BKPT] = "Breakpoint", | |
9433 | [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", | |
9434 | [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", | |
9435 | [EXCP_HVC] = "Hypervisor Call", | |
9436 | [EXCP_HYP_TRAP] = "Hypervisor Trap", | |
9437 | [EXCP_SMC] = "Secure Monitor Call", | |
9438 | [EXCP_VIRQ] = "Virtual IRQ", | |
9439 | [EXCP_VFIQ] = "Virtual FIQ", | |
9440 | [EXCP_SEMIHOST] = "Semihosting call", | |
9441 | [EXCP_NOCP] = "v7M NOCP UsageFault", | |
9442 | [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", | |
9443 | [EXCP_STKOF] = "v8M STKOF UsageFault", | |
9444 | [EXCP_LAZYFP] = "v7M exception during lazy FP stacking", | |
9445 | [EXCP_LSERR] = "v8M LSERR UsageFault", | |
9446 | [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", | |
e5346292 | 9447 | [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault", |
3c29632f | 9448 | [EXCP_VSERR] = "Virtual SERR", |
b59f479b PMD |
9449 | }; |
9450 | ||
9451 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | |
9452 | exc = excnames[idx]; | |
9453 | } | |
9454 | if (!exc) { | |
9455 | exc = "unknown"; | |
9456 | } | |
fc6177af PM |
9457 | qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s] on CPU %d\n", |
9458 | idx, exc, cs->cpu_index); | |
b59f479b PMD |
9459 | } |
9460 | } | |
9461 | ||
a356dacf | 9462 | /* |
7aab5a8c PMD |
9463 | * Function used to synchronize QEMU's AArch64 register set with AArch32 |
9464 | * register set. This is necessary when switching between AArch32 and AArch64 | |
9465 | * execution state. | |
a356dacf | 9466 | */ |
7aab5a8c | 9467 | void aarch64_sync_32_to_64(CPUARMState *env) |
9ee6e8bb | 9468 | { |
7aab5a8c PMD |
9469 | int i; |
9470 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
9471 | ||
9472 | /* We can blanket copy R[0:7] to X[0:7] */ | |
9473 | for (i = 0; i < 8; i++) { | |
9474 | env->xregs[i] = env->regs[i]; | |
fd592d89 | 9475 | } |
70d74660 | 9476 | |
9a223097 | 9477 | /* |
7aab5a8c PMD |
9478 | * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. |
9479 | * Otherwise, they come from the banked user regs. | |
fd592d89 | 9480 | */ |
7aab5a8c PMD |
9481 | if (mode == ARM_CPU_MODE_FIQ) { |
9482 | for (i = 8; i < 13; i++) { | |
9483 | env->xregs[i] = env->usr_regs[i - 8]; | |
9484 | } | |
9485 | } else { | |
9486 | for (i = 8; i < 13; i++) { | |
9487 | env->xregs[i] = env->regs[i]; | |
9488 | } | |
fd592d89 | 9489 | } |
9ee6e8bb | 9490 | |
7aab5a8c PMD |
9491 | /* |
9492 | * Registers x13-x23 are the various mode SP and FP registers. Registers | |
9493 | * r13 and r14 are only copied if we are in that mode, otherwise we copy | |
9494 | * from the mode banked register. | |
9495 | */ | |
9496 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { | |
9497 | env->xregs[13] = env->regs[13]; | |
9498 | env->xregs[14] = env->regs[14]; | |
9499 | } else { | |
9500 | env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; | |
9501 | /* HYP is an exception in that it is copied from r14 */ | |
9502 | if (mode == ARM_CPU_MODE_HYP) { | |
9503 | env->xregs[14] = env->regs[14]; | |
95695eff | 9504 | } else { |
7aab5a8c | 9505 | env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)]; |
95695eff | 9506 | } |
95695eff PM |
9507 | } |
9508 | ||
7aab5a8c PMD |
9509 | if (mode == ARM_CPU_MODE_HYP) { |
9510 | env->xregs[15] = env->regs[13]; | |
9511 | } else { | |
9512 | env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; | |
95695eff PM |
9513 | } |
9514 | ||
7aab5a8c PMD |
9515 | if (mode == ARM_CPU_MODE_IRQ) { |
9516 | env->xregs[16] = env->regs[14]; | |
9517 | env->xregs[17] = env->regs[13]; | |
9518 | } else { | |
9519 | env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)]; | |
9520 | env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; | |
9521 | } | |
95695eff | 9522 | |
7aab5a8c PMD |
9523 | if (mode == ARM_CPU_MODE_SVC) { |
9524 | env->xregs[18] = env->regs[14]; | |
9525 | env->xregs[19] = env->regs[13]; | |
9526 | } else { | |
9527 | env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)]; | |
9528 | env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; | |
9529 | } | |
95695eff | 9530 | |
7aab5a8c PMD |
9531 | if (mode == ARM_CPU_MODE_ABT) { |
9532 | env->xregs[20] = env->regs[14]; | |
9533 | env->xregs[21] = env->regs[13]; | |
9534 | } else { | |
9535 | env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)]; | |
9536 | env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; | |
9537 | } | |
e33cf0f8 | 9538 | |
7aab5a8c PMD |
9539 | if (mode == ARM_CPU_MODE_UND) { |
9540 | env->xregs[22] = env->regs[14]; | |
9541 | env->xregs[23] = env->regs[13]; | |
9542 | } else { | |
9543 | env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)]; | |
9544 | env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; | |
e33cf0f8 PM |
9545 | } |
9546 | ||
9547 | /* | |
7aab5a8c PMD |
9548 | * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ |
9549 | * mode, then we can copy from r8-r14. Otherwise, we copy from the | |
9550 | * FIQ bank for r8-r14. | |
e33cf0f8 | 9551 | */ |
7aab5a8c PMD |
9552 | if (mode == ARM_CPU_MODE_FIQ) { |
9553 | for (i = 24; i < 31; i++) { | |
9554 | env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ | |
9555 | } | |
9556 | } else { | |
9557 | for (i = 24; i < 29; i++) { | |
9558 | env->xregs[i] = env->fiq_regs[i - 24]; | |
e33cf0f8 | 9559 | } |
7aab5a8c PMD |
9560 | env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; |
9561 | env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)]; | |
e33cf0f8 | 9562 | } |
7aab5a8c PMD |
9563 | |
9564 | env->pc = env->regs[15]; | |
e33cf0f8 PM |
9565 | } |
9566 | ||
9a223097 | 9567 | /* |
7aab5a8c PMD |
9568 | * Function used to synchronize QEMU's AArch32 register set with AArch64 |
9569 | * register set. This is necessary when switching between AArch32 and AArch64 | |
9570 | * execution state. | |
de2db7ec | 9571 | */ |
7aab5a8c | 9572 | void aarch64_sync_64_to_32(CPUARMState *env) |
9ee6e8bb | 9573 | { |
7aab5a8c PMD |
9574 | int i; |
9575 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
abc24d86 | 9576 | |
7aab5a8c PMD |
9577 | /* We can blanket copy X[0:7] to R[0:7] */ |
9578 | for (i = 0; i < 8; i++) { | |
9579 | env->regs[i] = env->xregs[i]; | |
de2db7ec | 9580 | } |
3f0cddee | 9581 | |
9a223097 | 9582 | /* |
7aab5a8c PMD |
9583 | * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. |
9584 | * Otherwise, we copy x8-x12 into the banked user regs. | |
de2db7ec | 9585 | */ |
7aab5a8c PMD |
9586 | if (mode == ARM_CPU_MODE_FIQ) { |
9587 | for (i = 8; i < 13; i++) { | |
9588 | env->usr_regs[i - 8] = env->xregs[i]; | |
9589 | } | |
9590 | } else { | |
9591 | for (i = 8; i < 13; i++) { | |
9592 | env->regs[i] = env->xregs[i]; | |
9593 | } | |
fb602cb7 PM |
9594 | } |
9595 | ||
9a223097 | 9596 | /* |
7aab5a8c PMD |
9597 | * Registers r13 & r14 depend on the current mode. |
9598 | * If we are in a given mode, we copy the corresponding x registers to r13 | |
9599 | * and r14. Otherwise, we copy the x register to the banked r13 and r14 | |
9600 | * for the mode. | |
fb602cb7 | 9601 | */ |
7aab5a8c PMD |
9602 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { |
9603 | env->regs[13] = env->xregs[13]; | |
9604 | env->regs[14] = env->xregs[14]; | |
fb602cb7 | 9605 | } else { |
7aab5a8c | 9606 | env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; |
fb602cb7 | 9607 | |
7aab5a8c PMD |
9608 | /* |
9609 | * HYP is an exception in that it does not have its own banked r14 but | |
9610 | * shares the USR r14 | |
9611 | */ | |
9612 | if (mode == ARM_CPU_MODE_HYP) { | |
9613 | env->regs[14] = env->xregs[14]; | |
9614 | } else { | |
9615 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; | |
9616 | } | |
9617 | } | |
fb602cb7 | 9618 | |
7aab5a8c PMD |
9619 | if (mode == ARM_CPU_MODE_HYP) { |
9620 | env->regs[13] = env->xregs[15]; | |
fb602cb7 | 9621 | } else { |
7aab5a8c | 9622 | env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; |
fb602cb7 | 9623 | } |
d02a8698 | 9624 | |
7aab5a8c PMD |
9625 | if (mode == ARM_CPU_MODE_IRQ) { |
9626 | env->regs[14] = env->xregs[16]; | |
9627 | env->regs[13] = env->xregs[17]; | |
d02a8698 | 9628 | } else { |
7aab5a8c PMD |
9629 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; |
9630 | env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; | |
d02a8698 PM |
9631 | } |
9632 | ||
7aab5a8c PMD |
9633 | if (mode == ARM_CPU_MODE_SVC) { |
9634 | env->regs[14] = env->xregs[18]; | |
9635 | env->regs[13] = env->xregs[19]; | |
9636 | } else { | |
9637 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; | |
9638 | env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; | |
fb602cb7 PM |
9639 | } |
9640 | ||
7aab5a8c PMD |
9641 | if (mode == ARM_CPU_MODE_ABT) { |
9642 | env->regs[14] = env->xregs[20]; | |
9643 | env->regs[13] = env->xregs[21]; | |
9644 | } else { | |
9645 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; | |
9646 | env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; | |
ce02049d GB |
9647 | } |
9648 | ||
9649 | if (mode == ARM_CPU_MODE_UND) { | |
3a9148d0 SS |
9650 | env->regs[14] = env->xregs[22]; |
9651 | env->regs[13] = env->xregs[23]; | |
ce02049d | 9652 | } else { |
593cfa2b | 9653 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; |
3a9148d0 | 9654 | env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; |
ce02049d GB |
9655 | } |
9656 | ||
9657 | /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ | |
9658 | * mode, then we can copy to r8-r14. Otherwise, we copy to the | |
9659 | * FIQ bank for r8-r14. | |
9660 | */ | |
9661 | if (mode == ARM_CPU_MODE_FIQ) { | |
9662 | for (i = 24; i < 31; i++) { | |
9663 | env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ | |
9664 | } | |
9665 | } else { | |
9666 | for (i = 24; i < 29; i++) { | |
9667 | env->fiq_regs[i - 24] = env->xregs[i]; | |
9668 | } | |
9669 | env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; | |
593cfa2b | 9670 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; |
ce02049d GB |
9671 | } |
9672 | ||
9673 | env->regs[15] = env->pc; | |
9674 | } | |
9675 | ||
dea8378b PM |
9676 | static void take_aarch32_exception(CPUARMState *env, int new_mode, |
9677 | uint32_t mask, uint32_t offset, | |
9678 | uint32_t newpc) | |
9679 | { | |
4a2696c0 RH |
9680 | int new_el; |
9681 | ||
dea8378b PM |
9682 | /* Change the CPU state so as to actually take the exception. */ |
9683 | switch_mode(env, new_mode); | |
4a2696c0 | 9684 | |
dea8378b PM |
9685 | /* |
9686 | * For exceptions taken to AArch32 we must clear the SS bit in both | |
9687 | * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. | |
9688 | */ | |
f944a854 | 9689 | env->pstate &= ~PSTATE_SS; |
dea8378b PM |
9690 | env->spsr = cpsr_read(env); |
9691 | /* Clear IT bits. */ | |
9692 | env->condexec_bits = 0; | |
9693 | /* Switch to the new mode, and to the correct instruction set. */ | |
9694 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; | |
88828bf1 CD |
9695 | |
9696 | /* This must be after mode switching. */ | |
9697 | new_el = arm_current_el(env); | |
9698 | ||
dea8378b PM |
9699 | /* Set new mode endianness */ |
9700 | env->uncached_cpsr &= ~CPSR_E; | |
4a2696c0 | 9701 | if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { |
dea8378b PM |
9702 | env->uncached_cpsr |= CPSR_E; |
9703 | } | |
829f9fd3 PM |
9704 | /* J and IL must always be cleared for exception entry */ |
9705 | env->uncached_cpsr &= ~(CPSR_IL | CPSR_J); | |
dea8378b PM |
9706 | env->daif |= mask; |
9707 | ||
f2f68a78 RC |
9708 | if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) { |
9709 | if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) { | |
9710 | env->uncached_cpsr |= CPSR_SSBS; | |
9711 | } else { | |
9712 | env->uncached_cpsr &= ~CPSR_SSBS; | |
9713 | } | |
9714 | } | |
9715 | ||
dea8378b PM |
9716 | if (new_mode == ARM_CPU_MODE_HYP) { |
9717 | env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0; | |
9718 | env->elr_el[2] = env->regs[15]; | |
9719 | } else { | |
4a2696c0 | 9720 | /* CPSR.PAN is normally preserved preserved unless... */ |
f8af1143 | 9721 | if (cpu_isar_feature(aa32_pan, env_archcpu(env))) { |
4a2696c0 RH |
9722 | switch (new_el) { |
9723 | case 3: | |
9724 | if (!arm_is_secure_below_el3(env)) { | |
9725 | /* ... the target is EL3, from non-secure state. */ | |
9726 | env->uncached_cpsr &= ~CPSR_PAN; | |
9727 | break; | |
9728 | } | |
9729 | /* ... the target is EL3, from secure state ... */ | |
9730 | /* fall through */ | |
9731 | case 1: | |
9732 | /* ... the target is EL1 and SCTLR.SPAN is 0. */ | |
9733 | if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { | |
9734 | env->uncached_cpsr |= CPSR_PAN; | |
9735 | } | |
9736 | break; | |
9737 | } | |
9738 | } | |
dea8378b PM |
9739 | /* |
9740 | * this is a lie, as there was no c1_sys on V4T/V5, but who cares | |
9741 | * and we should just guard the thumb mode on V4 | |
9742 | */ | |
9743 | if (arm_feature(env, ARM_FEATURE_V4T)) { | |
9744 | env->thumb = | |
9745 | (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; | |
9746 | } | |
9747 | env->regs[14] = env->regs[15] + offset; | |
9748 | } | |
9749 | env->regs[15] = newpc; | |
a8a79c7a | 9750 | arm_rebuild_hflags(env); |
dea8378b PM |
9751 | } |
9752 | ||
b9bc21ff PM |
9753 | static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) |
9754 | { | |
9755 | /* | |
9756 | * Handle exception entry to Hyp mode; this is sufficiently | |
9757 | * different to entry to other AArch32 modes that we handle it | |
9758 | * separately here. | |
9759 | * | |
9760 | * The vector table entry used is always the 0x14 Hyp mode entry point, | |
2c023d36 | 9761 | * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp. |
b9bc21ff PM |
9762 | * The offset applied to the preferred return address is always zero |
9763 | * (see DDI0487C.a section G1.12.3). | |
9764 | * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. | |
9765 | */ | |
9766 | uint32_t addr, mask; | |
9767 | ARMCPU *cpu = ARM_CPU(cs); | |
9768 | CPUARMState *env = &cpu->env; | |
9769 | ||
9770 | switch (cs->exception_index) { | |
9771 | case EXCP_UDEF: | |
9772 | addr = 0x04; | |
9773 | break; | |
9774 | case EXCP_SWI: | |
2c023d36 | 9775 | addr = 0x08; |
b9bc21ff PM |
9776 | break; |
9777 | case EXCP_BKPT: | |
9778 | /* Fall through to prefetch abort. */ | |
9779 | case EXCP_PREFETCH_ABORT: | |
9780 | env->cp15.ifar_s = env->exception.vaddress; | |
9781 | qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n", | |
9782 | (uint32_t)env->exception.vaddress); | |
9783 | addr = 0x0c; | |
9784 | break; | |
9785 | case EXCP_DATA_ABORT: | |
9786 | env->cp15.dfar_s = env->exception.vaddress; | |
9787 | qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n", | |
9788 | (uint32_t)env->exception.vaddress); | |
9789 | addr = 0x10; | |
9790 | break; | |
9791 | case EXCP_IRQ: | |
9792 | addr = 0x18; | |
9793 | break; | |
9794 | case EXCP_FIQ: | |
9795 | addr = 0x1c; | |
9796 | break; | |
9797 | case EXCP_HVC: | |
9798 | addr = 0x08; | |
9799 | break; | |
9800 | case EXCP_HYP_TRAP: | |
9801 | addr = 0x14; | |
9bbb4ef9 | 9802 | break; |
b9bc21ff PM |
9803 | default: |
9804 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
9805 | } | |
9806 | ||
9807 | if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) { | |
2ed08180 PM |
9808 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
9809 | /* | |
9810 | * QEMU syndrome values are v8-style. v7 has the IL bit | |
9811 | * UNK/SBZP for "field not valid" cases, where v8 uses RES1. | |
9812 | * If this is a v7 CPU, squash the IL bit in those cases. | |
9813 | */ | |
9814 | if (cs->exception_index == EXCP_PREFETCH_ABORT || | |
9815 | (cs->exception_index == EXCP_DATA_ABORT && | |
9816 | !(env->exception.syndrome & ARM_EL_ISV)) || | |
9817 | syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) { | |
9818 | env->exception.syndrome &= ~ARM_EL_IL; | |
9819 | } | |
9820 | } | |
b9bc21ff PM |
9821 | env->cp15.esr_el[2] = env->exception.syndrome; |
9822 | } | |
9823 | ||
9824 | if (arm_current_el(env) != 2 && addr < 0x14) { | |
9825 | addr = 0x14; | |
9826 | } | |
9827 | ||
9828 | mask = 0; | |
9829 | if (!(env->cp15.scr_el3 & SCR_EA)) { | |
9830 | mask |= CPSR_A; | |
9831 | } | |
9832 | if (!(env->cp15.scr_el3 & SCR_IRQ)) { | |
9833 | mask |= CPSR_I; | |
9834 | } | |
9835 | if (!(env->cp15.scr_el3 & SCR_FIQ)) { | |
9836 | mask |= CPSR_F; | |
9837 | } | |
9838 | ||
9839 | addr += env->cp15.hvbar; | |
9840 | ||
9841 | take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr); | |
9842 | } | |
9843 | ||
966f758c | 9844 | static void arm_cpu_do_interrupt_aarch32(CPUState *cs) |
b5ff1b31 | 9845 | { |
97a8ea5a AF |
9846 | ARMCPU *cpu = ARM_CPU(cs); |
9847 | CPUARMState *env = &cpu->env; | |
b5ff1b31 FB |
9848 | uint32_t addr; |
9849 | uint32_t mask; | |
9850 | int new_mode; | |
9851 | uint32_t offset; | |
16a906fd | 9852 | uint32_t moe; |
b5ff1b31 | 9853 | |
16a906fd | 9854 | /* If this is a debug exception we must update the DBGDSCR.MOE bits */ |
64b91e3f | 9855 | switch (syn_get_ec(env->exception.syndrome)) { |
16a906fd PM |
9856 | case EC_BREAKPOINT: |
9857 | case EC_BREAKPOINT_SAME_EL: | |
9858 | moe = 1; | |
9859 | break; | |
9860 | case EC_WATCHPOINT: | |
9861 | case EC_WATCHPOINT_SAME_EL: | |
9862 | moe = 10; | |
9863 | break; | |
9864 | case EC_AA32_BKPT: | |
9865 | moe = 3; | |
9866 | break; | |
9867 | case EC_VECTORCATCH: | |
9868 | moe = 5; | |
9869 | break; | |
9870 | default: | |
9871 | moe = 0; | |
9872 | break; | |
9873 | } | |
9874 | ||
9875 | if (moe) { | |
9876 | env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); | |
9877 | } | |
9878 | ||
b9bc21ff PM |
9879 | if (env->exception.target_el == 2) { |
9880 | arm_cpu_do_interrupt_aarch32_hyp(cs); | |
9881 | return; | |
9882 | } | |
9883 | ||
27103424 | 9884 | switch (cs->exception_index) { |
b5ff1b31 FB |
9885 | case EXCP_UDEF: |
9886 | new_mode = ARM_CPU_MODE_UND; | |
9887 | addr = 0x04; | |
9888 | mask = CPSR_I; | |
9889 | if (env->thumb) | |
9890 | offset = 2; | |
9891 | else | |
9892 | offset = 4; | |
9893 | break; | |
9894 | case EXCP_SWI: | |
9895 | new_mode = ARM_CPU_MODE_SVC; | |
9896 | addr = 0x08; | |
9897 | mask = CPSR_I; | |
601d70b9 | 9898 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
9899 | offset = 0; |
9900 | break; | |
06c949e6 | 9901 | case EXCP_BKPT: |
9ee6e8bb PB |
9902 | /* Fall through to prefetch abort. */ |
9903 | case EXCP_PREFETCH_ABORT: | |
88ca1c2d | 9904 | A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); |
b848ce2b | 9905 | A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); |
3f1beaca | 9906 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", |
88ca1c2d | 9907 | env->exception.fsr, (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
9908 | new_mode = ARM_CPU_MODE_ABT; |
9909 | addr = 0x0c; | |
9910 | mask = CPSR_A | CPSR_I; | |
9911 | offset = 4; | |
9912 | break; | |
9913 | case EXCP_DATA_ABORT: | |
4a7e2d73 | 9914 | A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); |
b848ce2b | 9915 | A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); |
3f1beaca | 9916 | qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", |
4a7e2d73 | 9917 | env->exception.fsr, |
6cd8a264 | 9918 | (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
9919 | new_mode = ARM_CPU_MODE_ABT; |
9920 | addr = 0x10; | |
9921 | mask = CPSR_A | CPSR_I; | |
9922 | offset = 8; | |
9923 | break; | |
9924 | case EXCP_IRQ: | |
9925 | new_mode = ARM_CPU_MODE_IRQ; | |
9926 | addr = 0x18; | |
9927 | /* Disable IRQ and imprecise data aborts. */ | |
9928 | mask = CPSR_A | CPSR_I; | |
9929 | offset = 4; | |
de38d23b FA |
9930 | if (env->cp15.scr_el3 & SCR_IRQ) { |
9931 | /* IRQ routed to monitor mode */ | |
9932 | new_mode = ARM_CPU_MODE_MON; | |
9933 | mask |= CPSR_F; | |
9934 | } | |
b5ff1b31 FB |
9935 | break; |
9936 | case EXCP_FIQ: | |
9937 | new_mode = ARM_CPU_MODE_FIQ; | |
9938 | addr = 0x1c; | |
9939 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
9940 | mask = CPSR_A | CPSR_I | CPSR_F; | |
de38d23b FA |
9941 | if (env->cp15.scr_el3 & SCR_FIQ) { |
9942 | /* FIQ routed to monitor mode */ | |
9943 | new_mode = ARM_CPU_MODE_MON; | |
9944 | } | |
b5ff1b31 FB |
9945 | offset = 4; |
9946 | break; | |
87a4b270 PM |
9947 | case EXCP_VIRQ: |
9948 | new_mode = ARM_CPU_MODE_IRQ; | |
9949 | addr = 0x18; | |
9950 | /* Disable IRQ and imprecise data aborts. */ | |
9951 | mask = CPSR_A | CPSR_I; | |
9952 | offset = 4; | |
9953 | break; | |
9954 | case EXCP_VFIQ: | |
9955 | new_mode = ARM_CPU_MODE_FIQ; | |
9956 | addr = 0x1c; | |
9957 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
9958 | mask = CPSR_A | CPSR_I | CPSR_F; | |
9959 | offset = 4; | |
9960 | break; | |
3c29632f RH |
9961 | case EXCP_VSERR: |
9962 | { | |
9963 | /* | |
9964 | * Note that this is reported as a data abort, but the DFAR | |
9965 | * has an UNKNOWN value. Construct the SError syndrome from | |
9966 | * AET and ExT fields. | |
9967 | */ | |
9968 | ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, }; | |
9969 | ||
9970 | if (extended_addresses_enabled(env)) { | |
9971 | env->exception.fsr = arm_fi_to_lfsc(&fi); | |
9972 | } else { | |
9973 | env->exception.fsr = arm_fi_to_sfsc(&fi); | |
9974 | } | |
9975 | env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000; | |
9976 | A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); | |
9977 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n", | |
9978 | env->exception.fsr); | |
9979 | ||
9980 | new_mode = ARM_CPU_MODE_ABT; | |
9981 | addr = 0x10; | |
9982 | mask = CPSR_A | CPSR_I; | |
9983 | offset = 8; | |
9984 | } | |
9985 | break; | |
dbe9d163 FA |
9986 | case EXCP_SMC: |
9987 | new_mode = ARM_CPU_MODE_MON; | |
9988 | addr = 0x08; | |
9989 | mask = CPSR_A | CPSR_I | CPSR_F; | |
9990 | offset = 0; | |
9991 | break; | |
b5ff1b31 | 9992 | default: |
a47dddd7 | 9993 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
b5ff1b31 FB |
9994 | return; /* Never happens. Keep compiler happy. */ |
9995 | } | |
e89e51a1 FA |
9996 | |
9997 | if (new_mode == ARM_CPU_MODE_MON) { | |
9998 | addr += env->cp15.mvbar; | |
137feaa9 | 9999 | } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { |
e89e51a1 | 10000 | /* High vectors. When enabled, base address cannot be remapped. */ |
b5ff1b31 | 10001 | addr += 0xffff0000; |
8641136c NR |
10002 | } else { |
10003 | /* ARM v7 architectures provide a vector base address register to remap | |
10004 | * the interrupt vector table. | |
e89e51a1 | 10005 | * This register is only followed in non-monitor mode, and is banked. |
8641136c NR |
10006 | * Note: only bits 31:5 are valid. |
10007 | */ | |
fb6c91ba | 10008 | addr += A32_BANKED_CURRENT_REG_GET(env, vbar); |
b5ff1b31 | 10009 | } |
dbe9d163 FA |
10010 | |
10011 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
10012 | env->cp15.scr_el3 &= ~SCR_NS; | |
10013 | } | |
10014 | ||
dea8378b | 10015 | take_aarch32_exception(env, new_mode, mask, offset, addr); |
b5ff1b31 FB |
10016 | } |
10017 | ||
a65dabf7 PM |
10018 | static int aarch64_regnum(CPUARMState *env, int aarch32_reg) |
10019 | { | |
10020 | /* | |
10021 | * Return the register number of the AArch64 view of the AArch32 | |
10022 | * register @aarch32_reg. The CPUARMState CPSR is assumed to still | |
10023 | * be that of the AArch32 mode the exception came from. | |
10024 | */ | |
10025 | int mode = env->uncached_cpsr & CPSR_M; | |
10026 | ||
10027 | switch (aarch32_reg) { | |
10028 | case 0 ... 7: | |
10029 | return aarch32_reg; | |
10030 | case 8 ... 12: | |
10031 | return mode == ARM_CPU_MODE_FIQ ? aarch32_reg + 16 : aarch32_reg; | |
10032 | case 13: | |
10033 | switch (mode) { | |
10034 | case ARM_CPU_MODE_USR: | |
10035 | case ARM_CPU_MODE_SYS: | |
10036 | return 13; | |
10037 | case ARM_CPU_MODE_HYP: | |
10038 | return 15; | |
10039 | case ARM_CPU_MODE_IRQ: | |
10040 | return 17; | |
10041 | case ARM_CPU_MODE_SVC: | |
10042 | return 19; | |
10043 | case ARM_CPU_MODE_ABT: | |
10044 | return 21; | |
10045 | case ARM_CPU_MODE_UND: | |
10046 | return 23; | |
10047 | case ARM_CPU_MODE_FIQ: | |
10048 | return 29; | |
10049 | default: | |
10050 | g_assert_not_reached(); | |
10051 | } | |
10052 | case 14: | |
10053 | switch (mode) { | |
10054 | case ARM_CPU_MODE_USR: | |
10055 | case ARM_CPU_MODE_SYS: | |
10056 | case ARM_CPU_MODE_HYP: | |
10057 | return 14; | |
10058 | case ARM_CPU_MODE_IRQ: | |
10059 | return 16; | |
10060 | case ARM_CPU_MODE_SVC: | |
10061 | return 18; | |
10062 | case ARM_CPU_MODE_ABT: | |
10063 | return 20; | |
10064 | case ARM_CPU_MODE_UND: | |
10065 | return 22; | |
10066 | case ARM_CPU_MODE_FIQ: | |
10067 | return 30; | |
10068 | default: | |
10069 | g_assert_not_reached(); | |
10070 | } | |
10071 | case 15: | |
10072 | return 31; | |
10073 | default: | |
10074 | g_assert_not_reached(); | |
10075 | } | |
10076 | } | |
10077 | ||
f944a854 RC |
10078 | static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env) |
10079 | { | |
10080 | uint32_t ret = cpsr_read(env); | |
10081 | ||
10082 | /* Move DIT to the correct location for SPSR_ELx */ | |
10083 | if (ret & CPSR_DIT) { | |
10084 | ret &= ~CPSR_DIT; | |
10085 | ret |= PSTATE_DIT; | |
10086 | } | |
10087 | /* Merge PSTATE.SS into SPSR_ELx */ | |
10088 | ret |= env->pstate & PSTATE_SS; | |
10089 | ||
10090 | return ret; | |
10091 | } | |
10092 | ||
7ac61020 PM |
10093 | static bool syndrome_is_sync_extabt(uint32_t syndrome) |
10094 | { | |
10095 | /* Return true if this syndrome value is a synchronous external abort */ | |
10096 | switch (syn_get_ec(syndrome)) { | |
10097 | case EC_INSNABORT: | |
10098 | case EC_INSNABORT_SAME_EL: | |
10099 | case EC_DATAABORT: | |
10100 | case EC_DATAABORT_SAME_EL: | |
10101 | /* Look at fault status code for all the synchronous ext abort cases */ | |
10102 | switch (syndrome & 0x3f) { | |
10103 | case 0x10: | |
10104 | case 0x13: | |
10105 | case 0x14: | |
10106 | case 0x15: | |
10107 | case 0x16: | |
10108 | case 0x17: | |
10109 | return true; | |
10110 | default: | |
10111 | return false; | |
10112 | } | |
10113 | default: | |
10114 | return false; | |
10115 | } | |
10116 | } | |
10117 | ||
966f758c PM |
10118 | /* Handle exception entry to a target EL which is using AArch64 */ |
10119 | static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | |
f3a9b694 PM |
10120 | { |
10121 | ARMCPU *cpu = ARM_CPU(cs); | |
10122 | CPUARMState *env = &cpu->env; | |
10123 | unsigned int new_el = env->exception.target_el; | |
10124 | target_ulong addr = env->cp15.vbar_el[new_el]; | |
10125 | unsigned int new_mode = aarch64_pstate_mode(new_el, true); | |
4a2696c0 | 10126 | unsigned int old_mode; |
0ab5953b | 10127 | unsigned int cur_el = arm_current_el(env); |
a65dabf7 | 10128 | int rt; |
0ab5953b | 10129 | |
9a05f7b6 RH |
10130 | /* |
10131 | * Note that new_el can never be 0. If cur_el is 0, then | |
10132 | * el0_a64 is is_a64(), else el0_a64 is ignored. | |
10133 | */ | |
10134 | aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); | |
f3a9b694 | 10135 | |
0ab5953b | 10136 | if (cur_el < new_el) { |
3d6f7617 PM |
10137 | /* Entry vector offset depends on whether the implemented EL |
10138 | * immediately lower than the target level is using AArch32 or AArch64 | |
10139 | */ | |
10140 | bool is_aa64; | |
cb092fbb | 10141 | uint64_t hcr; |
3d6f7617 PM |
10142 | |
10143 | switch (new_el) { | |
10144 | case 3: | |
10145 | is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; | |
10146 | break; | |
10147 | case 2: | |
cb092fbb RH |
10148 | hcr = arm_hcr_el2_eff(env); |
10149 | if ((hcr & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { | |
10150 | is_aa64 = (hcr & HCR_RW) != 0; | |
10151 | break; | |
10152 | } | |
10153 | /* fall through */ | |
3d6f7617 PM |
10154 | case 1: |
10155 | is_aa64 = is_a64(env); | |
10156 | break; | |
10157 | default: | |
10158 | g_assert_not_reached(); | |
10159 | } | |
10160 | ||
10161 | if (is_aa64) { | |
f3a9b694 PM |
10162 | addr += 0x400; |
10163 | } else { | |
10164 | addr += 0x600; | |
10165 | } | |
10166 | } else if (pstate_read(env) & PSTATE_SP) { | |
10167 | addr += 0x200; | |
10168 | } | |
10169 | ||
f3a9b694 PM |
10170 | switch (cs->exception_index) { |
10171 | case EXCP_PREFETCH_ABORT: | |
10172 | case EXCP_DATA_ABORT: | |
7ac61020 PM |
10173 | /* |
10174 | * FEAT_DoubleFault allows synchronous external aborts taken to EL3 | |
10175 | * to be taken to the SError vector entrypoint. | |
10176 | */ | |
10177 | if (new_el == 3 && (env->cp15.scr_el3 & SCR_EASE) && | |
10178 | syndrome_is_sync_extabt(env->exception.syndrome)) { | |
10179 | addr += 0x180; | |
10180 | } | |
f3a9b694 PM |
10181 | env->cp15.far_el[new_el] = env->exception.vaddress; |
10182 | qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", | |
10183 | env->cp15.far_el[new_el]); | |
10184 | /* fall through */ | |
10185 | case EXCP_BKPT: | |
10186 | case EXCP_UDEF: | |
10187 | case EXCP_SWI: | |
10188 | case EXCP_HVC: | |
10189 | case EXCP_HYP_TRAP: | |
10190 | case EXCP_SMC: | |
a65dabf7 PM |
10191 | switch (syn_get_ec(env->exception.syndrome)) { |
10192 | case EC_ADVSIMDFPACCESSTRAP: | |
4be42f40 PM |
10193 | /* |
10194 | * QEMU internal FP/SIMD syndromes from AArch32 include the | |
10195 | * TA and coproc fields which are only exposed if the exception | |
10196 | * is taken to AArch32 Hyp mode. Mask them out to get a valid | |
10197 | * AArch64 format syndrome. | |
10198 | */ | |
10199 | env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20); | |
a65dabf7 PM |
10200 | break; |
10201 | case EC_CP14RTTRAP: | |
10202 | case EC_CP15RTTRAP: | |
10203 | case EC_CP14DTTRAP: | |
10204 | /* | |
10205 | * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently | |
10206 | * the raw register field from the insn; when taking this to | |
10207 | * AArch64 we must convert it to the AArch64 view of the register | |
10208 | * number. Notice that we read a 4-bit AArch32 register number and | |
10209 | * write back a 5-bit AArch64 one. | |
10210 | */ | |
10211 | rt = extract32(env->exception.syndrome, 5, 4); | |
10212 | rt = aarch64_regnum(env, rt); | |
10213 | env->exception.syndrome = deposit32(env->exception.syndrome, | |
10214 | 5, 5, rt); | |
10215 | break; | |
10216 | case EC_CP15RRTTRAP: | |
10217 | case EC_CP14RRTTRAP: | |
10218 | /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */ | |
10219 | rt = extract32(env->exception.syndrome, 5, 4); | |
10220 | rt = aarch64_regnum(env, rt); | |
10221 | env->exception.syndrome = deposit32(env->exception.syndrome, | |
10222 | 5, 5, rt); | |
10223 | rt = extract32(env->exception.syndrome, 10, 4); | |
10224 | rt = aarch64_regnum(env, rt); | |
10225 | env->exception.syndrome = deposit32(env->exception.syndrome, | |
10226 | 10, 5, rt); | |
10227 | break; | |
4be42f40 | 10228 | } |
f3a9b694 PM |
10229 | env->cp15.esr_el[new_el] = env->exception.syndrome; |
10230 | break; | |
10231 | case EXCP_IRQ: | |
10232 | case EXCP_VIRQ: | |
10233 | addr += 0x80; | |
10234 | break; | |
10235 | case EXCP_FIQ: | |
10236 | case EXCP_VFIQ: | |
10237 | addr += 0x100; | |
10238 | break; | |
3c29632f RH |
10239 | case EXCP_VSERR: |
10240 | addr += 0x180; | |
10241 | /* Construct the SError syndrome from IDS and ISS fields. */ | |
10242 | env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff); | |
10243 | env->cp15.esr_el[new_el] = env->exception.syndrome; | |
10244 | break; | |
f3a9b694 PM |
10245 | default: |
10246 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
10247 | } | |
10248 | ||
10249 | if (is_a64(env)) { | |
4a2696c0 | 10250 | old_mode = pstate_read(env); |
f3a9b694 PM |
10251 | aarch64_save_sp(env, arm_current_el(env)); |
10252 | env->elr_el[new_el] = env->pc; | |
10253 | } else { | |
f944a854 | 10254 | old_mode = cpsr_read_for_spsr_elx(env); |
f3a9b694 PM |
10255 | env->elr_el[new_el] = env->regs[15]; |
10256 | ||
10257 | aarch64_sync_32_to_64(env); | |
10258 | ||
10259 | env->condexec_bits = 0; | |
10260 | } | |
4a2696c0 RH |
10261 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode; |
10262 | ||
f3a9b694 PM |
10263 | qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", |
10264 | env->elr_el[new_el]); | |
10265 | ||
4a2696c0 RH |
10266 | if (cpu_isar_feature(aa64_pan, cpu)) { |
10267 | /* The value of PSTATE.PAN is normally preserved, except when ... */ | |
10268 | new_mode |= old_mode & PSTATE_PAN; | |
10269 | switch (new_el) { | |
10270 | case 2: | |
10271 | /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */ | |
10272 | if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) | |
10273 | != (HCR_E2H | HCR_TGE)) { | |
10274 | break; | |
10275 | } | |
10276 | /* fall through */ | |
10277 | case 1: | |
10278 | /* ... the target is EL1 ... */ | |
10279 | /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */ | |
10280 | if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) == 0) { | |
10281 | new_mode |= PSTATE_PAN; | |
10282 | } | |
10283 | break; | |
10284 | } | |
10285 | } | |
34669338 RH |
10286 | if (cpu_isar_feature(aa64_mte, cpu)) { |
10287 | new_mode |= PSTATE_TCO; | |
10288 | } | |
4a2696c0 | 10289 | |
f2f68a78 RC |
10290 | if (cpu_isar_feature(aa64_ssbs, cpu)) { |
10291 | if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) { | |
10292 | new_mode |= PSTATE_SSBS; | |
10293 | } else { | |
10294 | new_mode &= ~PSTATE_SSBS; | |
10295 | } | |
10296 | } | |
10297 | ||
f3a9b694 | 10298 | pstate_write(env, PSTATE_DAIF | new_mode); |
53221552 | 10299 | env->aarch64 = true; |
f3a9b694 | 10300 | aarch64_restore_sp(env, new_el); |
a8a79c7a | 10301 | helper_rebuild_hflags_a64(env, new_el); |
f3a9b694 PM |
10302 | |
10303 | env->pc = addr; | |
10304 | ||
10305 | qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", | |
10306 | new_el, env->pc, pstate_read(env)); | |
966f758c PM |
10307 | } |
10308 | ||
ed6e6ba9 AB |
10309 | /* |
10310 | * Do semihosting call and set the appropriate return value. All the | |
10311 | * permission and validity checks have been done at translate time. | |
10312 | * | |
10313 | * We only see semihosting exceptions in TCG only as they are not | |
10314 | * trapped to the hypervisor in KVM. | |
10315 | */ | |
91f78c58 | 10316 | #ifdef CONFIG_TCG |
ed6e6ba9 AB |
10317 | static void handle_semihosting(CPUState *cs) |
10318 | { | |
904c04de PM |
10319 | ARMCPU *cpu = ARM_CPU(cs); |
10320 | CPUARMState *env = &cpu->env; | |
10321 | ||
10322 | if (is_a64(env)) { | |
ed6e6ba9 AB |
10323 | qemu_log_mask(CPU_LOG_INT, |
10324 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
10325 | env->xregs[0]); | |
0bb446d8 | 10326 | env->xregs[0] = do_common_semihosting(cs); |
4ff5ef9e | 10327 | env->pc += 4; |
904c04de | 10328 | } else { |
904c04de PM |
10329 | qemu_log_mask(CPU_LOG_INT, |
10330 | "...handling as semihosting call 0x%x\n", | |
10331 | env->regs[0]); | |
0bb446d8 | 10332 | env->regs[0] = do_common_semihosting(cs); |
4ff5ef9e | 10333 | env->regs[15] += env->thumb ? 2 : 4; |
904c04de PM |
10334 | } |
10335 | } | |
ed6e6ba9 | 10336 | #endif |
904c04de | 10337 | |
966f758c PM |
10338 | /* Handle a CPU exception for A and R profile CPUs. |
10339 | * Do any appropriate logging, handle PSCI calls, and then hand off | |
10340 | * to the AArch64-entry or AArch32-entry function depending on the | |
10341 | * target exception level's register width. | |
853bfef4 CF |
10342 | * |
10343 | * Note: this is used for both TCG (as the do_interrupt tcg op), | |
10344 | * and KVM to re-inject guest debug exceptions, and to | |
10345 | * inject a Synchronous-External-Abort. | |
966f758c PM |
10346 | */ |
10347 | void arm_cpu_do_interrupt(CPUState *cs) | |
10348 | { | |
10349 | ARMCPU *cpu = ARM_CPU(cs); | |
10350 | CPUARMState *env = &cpu->env; | |
10351 | unsigned int new_el = env->exception.target_el; | |
10352 | ||
531c60a9 | 10353 | assert(!arm_feature(env, ARM_FEATURE_M)); |
966f758c | 10354 | |
fc6177af | 10355 | arm_log_exception(cs); |
966f758c PM |
10356 | qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), |
10357 | new_el); | |
10358 | if (qemu_loglevel_mask(CPU_LOG_INT) | |
10359 | && !excp_is_internal(cs->exception_index)) { | |
6568da45 | 10360 | qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", |
64b91e3f | 10361 | syn_get_ec(env->exception.syndrome), |
966f758c PM |
10362 | env->exception.syndrome); |
10363 | } | |
10364 | ||
10365 | if (arm_is_psci_call(cpu, cs->exception_index)) { | |
10366 | arm_handle_psci_call(cpu); | |
10367 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | |
10368 | return; | |
10369 | } | |
10370 | ||
ed6e6ba9 AB |
10371 | /* |
10372 | * Semihosting semantics depend on the register width of the code | |
10373 | * that caused the exception, not the target exception level, so | |
10374 | * must be handled here. | |
966f758c | 10375 | */ |
ed6e6ba9 AB |
10376 | #ifdef CONFIG_TCG |
10377 | if (cs->exception_index == EXCP_SEMIHOST) { | |
10378 | handle_semihosting(cs); | |
904c04de PM |
10379 | return; |
10380 | } | |
ed6e6ba9 | 10381 | #endif |
904c04de | 10382 | |
b5c53d1b AL |
10383 | /* Hooks may change global state so BQL should be held, also the |
10384 | * BQL needs to be held for any modification of | |
10385 | * cs->interrupt_request. | |
10386 | */ | |
10387 | g_assert(qemu_mutex_iothread_locked()); | |
10388 | ||
10389 | arm_call_pre_el_change_hook(cpu); | |
10390 | ||
904c04de PM |
10391 | assert(!excp_is_internal(cs->exception_index)); |
10392 | if (arm_el_is_aa64(env, new_el)) { | |
966f758c PM |
10393 | arm_cpu_do_interrupt_aarch64(cs); |
10394 | } else { | |
10395 | arm_cpu_do_interrupt_aarch32(cs); | |
10396 | } | |
f3a9b694 | 10397 | |
bd7d00fc PM |
10398 | arm_call_el_change_hook(cpu); |
10399 | ||
f3a9b694 PM |
10400 | if (!kvm_enabled()) { |
10401 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
10402 | } | |
10403 | } | |
c47eaf9f | 10404 | #endif /* !CONFIG_USER_ONLY */ |
0480f69a | 10405 | |
aaec1432 RH |
10406 | uint64_t arm_sctlr(CPUARMState *env, int el) |
10407 | { | |
10408 | /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ | |
10409 | if (el == 0) { | |
10410 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0); | |
b6ad6062 RDC |
10411 | el = (mmu_idx == ARMMMUIdx_E20_0 || mmu_idx == ARMMMUIdx_SE20_0) |
10412 | ? 2 : 1; | |
aaec1432 RH |
10413 | } |
10414 | return env->cp15.sctlr_el[el]; | |
10415 | } | |
c47eaf9f | 10416 | |
8ae08860 | 10417 | int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) |
b830a5ee RH |
10418 | { |
10419 | if (regime_has_2_ranges(mmu_idx)) { | |
10420 | return extract64(tcr, 37, 2); | |
b1a10c86 | 10421 | } else if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { |
b830a5ee RH |
10422 | return 0; /* VTCR_EL2 */ |
10423 | } else { | |
3e270f67 RH |
10424 | /* Replicate the single TBI bit so we always have 2 bits. */ |
10425 | return extract32(tcr, 20, 1) * 3; | |
b830a5ee RH |
10426 | } |
10427 | } | |
10428 | ||
8ae08860 | 10429 | int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) |
b830a5ee RH |
10430 | { |
10431 | if (regime_has_2_ranges(mmu_idx)) { | |
10432 | return extract64(tcr, 51, 2); | |
b1a10c86 | 10433 | } else if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { |
b830a5ee RH |
10434 | return 0; /* VTCR_EL2 */ |
10435 | } else { | |
3e270f67 RH |
10436 | /* Replicate the single TBID bit so we always have 2 bits. */ |
10437 | return extract32(tcr, 29, 1) * 3; | |
b830a5ee RH |
10438 | } |
10439 | } | |
10440 | ||
81ae05fa RH |
10441 | static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx) |
10442 | { | |
10443 | if (regime_has_2_ranges(mmu_idx)) { | |
10444 | return extract64(tcr, 57, 2); | |
10445 | } else { | |
10446 | /* Replicate the single TCMA bit so we always have 2 bits. */ | |
10447 | return extract32(tcr, 30, 1) * 3; | |
10448 | } | |
10449 | } | |
10450 | ||
b830a5ee RH |
10451 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, |
10452 | ARMMMUIdx mmu_idx, bool data) | |
ba97be9f RH |
10453 | { |
10454 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | |
ef56c242 RH |
10455 | bool epd, hpd, using16k, using64k, tsz_oob, ds; |
10456 | int select, tsz, tbi, max_tsz, min_tsz, ps, sh; | |
10457 | ARMCPU *cpu = env_archcpu(env); | |
ba97be9f | 10458 | |
339370b9 | 10459 | if (!regime_has_2_ranges(mmu_idx)) { |
71d18164 | 10460 | select = 0; |
ba97be9f RH |
10461 | tsz = extract32(tcr, 0, 6); |
10462 | using64k = extract32(tcr, 14, 1); | |
10463 | using16k = extract32(tcr, 15, 1); | |
b1a10c86 | 10464 | if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { |
ba97be9f | 10465 | /* VTCR_EL2 */ |
b830a5ee | 10466 | hpd = false; |
ba97be9f | 10467 | } else { |
ba97be9f RH |
10468 | hpd = extract32(tcr, 24, 1); |
10469 | } | |
10470 | epd = false; | |
ef56c242 | 10471 | sh = extract32(tcr, 12, 2); |
f4ecc015 | 10472 | ps = extract32(tcr, 16, 3); |
ef56c242 | 10473 | ds = extract64(tcr, 32, 1); |
ba97be9f | 10474 | } else { |
71d18164 RH |
10475 | /* |
10476 | * Bit 55 is always between the two regions, and is canonical for | |
10477 | * determining if address tagging is enabled. | |
10478 | */ | |
10479 | select = extract64(va, 55, 1); | |
10480 | if (!select) { | |
10481 | tsz = extract32(tcr, 0, 6); | |
10482 | epd = extract32(tcr, 7, 1); | |
ef56c242 | 10483 | sh = extract32(tcr, 12, 2); |
71d18164 RH |
10484 | using64k = extract32(tcr, 14, 1); |
10485 | using16k = extract32(tcr, 15, 1); | |
71d18164 | 10486 | hpd = extract64(tcr, 41, 1); |
71d18164 RH |
10487 | } else { |
10488 | int tg = extract32(tcr, 30, 2); | |
10489 | using16k = tg == 1; | |
10490 | using64k = tg == 3; | |
10491 | tsz = extract32(tcr, 16, 6); | |
10492 | epd = extract32(tcr, 23, 1); | |
ef56c242 | 10493 | sh = extract32(tcr, 28, 2); |
71d18164 | 10494 | hpd = extract64(tcr, 42, 1); |
71d18164 | 10495 | } |
f4ecc015 | 10496 | ps = extract64(tcr, 32, 3); |
ef56c242 | 10497 | ds = extract64(tcr, 59, 1); |
ba97be9f | 10498 | } |
c36c65ea | 10499 | |
ef56c242 | 10500 | if (cpu_isar_feature(aa64_st, cpu)) { |
c36c65ea RDC |
10501 | max_tsz = 48 - using64k; |
10502 | } else { | |
10503 | max_tsz = 39; | |
10504 | } | |
0af312b6 | 10505 | |
ef56c242 RH |
10506 | /* |
10507 | * DS is RES0 unless FEAT_LPA2 is supported for the given page size; | |
10508 | * adjust the effective value of DS, as documented. | |
10509 | */ | |
0af312b6 RH |
10510 | min_tsz = 16; |
10511 | if (using64k) { | |
ef56c242 RH |
10512 | if (cpu_isar_feature(aa64_lva, cpu)) { |
10513 | min_tsz = 12; | |
10514 | } | |
10515 | ds = false; | |
10516 | } else if (ds) { | |
10517 | switch (mmu_idx) { | |
10518 | case ARMMMUIdx_Stage2: | |
10519 | case ARMMMUIdx_Stage2_S: | |
10520 | if (using16k) { | |
10521 | ds = cpu_isar_feature(aa64_tgran16_2_lpa2, cpu); | |
10522 | } else { | |
10523 | ds = cpu_isar_feature(aa64_tgran4_2_lpa2, cpu); | |
10524 | } | |
10525 | break; | |
10526 | default: | |
10527 | if (using16k) { | |
10528 | ds = cpu_isar_feature(aa64_tgran16_lpa2, cpu); | |
10529 | } else { | |
10530 | ds = cpu_isar_feature(aa64_tgran4_lpa2, cpu); | |
10531 | } | |
10532 | break; | |
10533 | } | |
10534 | if (ds) { | |
0af312b6 RH |
10535 | min_tsz = 12; |
10536 | } | |
10537 | } | |
c36c65ea | 10538 | |
ebf93ce7 RH |
10539 | if (tsz > max_tsz) { |
10540 | tsz = max_tsz; | |
10541 | tsz_oob = true; | |
10542 | } else if (tsz < min_tsz) { | |
10543 | tsz = min_tsz; | |
10544 | tsz_oob = true; | |
10545 | } else { | |
10546 | tsz_oob = false; | |
10547 | } | |
ba97be9f | 10548 | |
b830a5ee RH |
10549 | /* Present TBI as a composite with TBID. */ |
10550 | tbi = aa64_va_parameter_tbi(tcr, mmu_idx); | |
10551 | if (!data) { | |
10552 | tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); | |
10553 | } | |
10554 | tbi = (tbi >> select) & 1; | |
10555 | ||
ba97be9f RH |
10556 | return (ARMVAParameters) { |
10557 | .tsz = tsz, | |
f4ecc015 | 10558 | .ps = ps, |
ef56c242 | 10559 | .sh = sh, |
ba97be9f RH |
10560 | .select = select, |
10561 | .tbi = tbi, | |
10562 | .epd = epd, | |
10563 | .hpd = hpd, | |
10564 | .using16k = using16k, | |
10565 | .using64k = using64k, | |
ebf93ce7 | 10566 | .tsz_oob = tsz_oob, |
ef56c242 | 10567 | .ds = ds, |
ba97be9f RH |
10568 | }; |
10569 | } | |
10570 | ||
6ddbc6e4 PB |
10571 | /* Note that signed overflow is undefined in C. The following routines are |
10572 | careful to use unsigned types where modulo arithmetic is required. | |
10573 | Failure to do so _will_ break on newer gcc. */ | |
10574 | ||
10575 | /* Signed saturating arithmetic. */ | |
10576 | ||
1654b2d6 | 10577 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
10578 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
10579 | { | |
10580 | uint16_t res; | |
10581 | ||
10582 | res = a + b; | |
10583 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
10584 | if (a & 0x8000) | |
10585 | res = 0x8000; | |
10586 | else | |
10587 | res = 0x7fff; | |
10588 | } | |
10589 | return res; | |
10590 | } | |
10591 | ||
1654b2d6 | 10592 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
10593 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
10594 | { | |
10595 | uint8_t res; | |
10596 | ||
10597 | res = a + b; | |
10598 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
10599 | if (a & 0x80) | |
10600 | res = 0x80; | |
10601 | else | |
10602 | res = 0x7f; | |
10603 | } | |
10604 | return res; | |
10605 | } | |
10606 | ||
1654b2d6 | 10607 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
10608 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
10609 | { | |
10610 | uint16_t res; | |
10611 | ||
10612 | res = a - b; | |
10613 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
10614 | if (a & 0x8000) | |
10615 | res = 0x8000; | |
10616 | else | |
10617 | res = 0x7fff; | |
10618 | } | |
10619 | return res; | |
10620 | } | |
10621 | ||
1654b2d6 | 10622 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
10623 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
10624 | { | |
10625 | uint8_t res; | |
10626 | ||
10627 | res = a - b; | |
10628 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
10629 | if (a & 0x80) | |
10630 | res = 0x80; | |
10631 | else | |
10632 | res = 0x7f; | |
10633 | } | |
10634 | return res; | |
10635 | } | |
10636 | ||
10637 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
10638 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
10639 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
10640 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
10641 | #define PFX q | |
10642 | ||
10643 | #include "op_addsub.h" | |
10644 | ||
10645 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 10646 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
10647 | { |
10648 | uint16_t res; | |
10649 | res = a + b; | |
10650 | if (res < a) | |
10651 | res = 0xffff; | |
10652 | return res; | |
10653 | } | |
10654 | ||
460a09c1 | 10655 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 | 10656 | { |
4c4fd3f8 | 10657 | if (a > b) |
6ddbc6e4 PB |
10658 | return a - b; |
10659 | else | |
10660 | return 0; | |
10661 | } | |
10662 | ||
10663 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
10664 | { | |
10665 | uint8_t res; | |
10666 | res = a + b; | |
10667 | if (res < a) | |
10668 | res = 0xff; | |
10669 | return res; | |
10670 | } | |
10671 | ||
10672 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
10673 | { | |
4c4fd3f8 | 10674 | if (a > b) |
6ddbc6e4 PB |
10675 | return a - b; |
10676 | else | |
10677 | return 0; | |
10678 | } | |
10679 | ||
10680 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
10681 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
10682 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
10683 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
10684 | #define PFX uq | |
10685 | ||
10686 | #include "op_addsub.h" | |
10687 | ||
10688 | /* Signed modulo arithmetic. */ | |
10689 | #define SARITH16(a, b, n, op) do { \ | |
10690 | int32_t sum; \ | |
db6e2e65 | 10691 | sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
6ddbc6e4 PB |
10692 | RESULT(sum, n, 16); \ |
10693 | if (sum >= 0) \ | |
10694 | ge |= 3 << (n * 2); \ | |
10695 | } while(0) | |
10696 | ||
10697 | #define SARITH8(a, b, n, op) do { \ | |
10698 | int32_t sum; \ | |
db6e2e65 | 10699 | sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
6ddbc6e4 PB |
10700 | RESULT(sum, n, 8); \ |
10701 | if (sum >= 0) \ | |
10702 | ge |= 1 << n; \ | |
10703 | } while(0) | |
10704 | ||
10705 | ||
10706 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
10707 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
10708 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
10709 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
10710 | #define PFX s | |
10711 | #define ARITH_GE | |
10712 | ||
10713 | #include "op_addsub.h" | |
10714 | ||
10715 | /* Unsigned modulo arithmetic. */ | |
10716 | #define ADD16(a, b, n) do { \ | |
10717 | uint32_t sum; \ | |
10718 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
10719 | RESULT(sum, n, 16); \ | |
a87aa10b | 10720 | if ((sum >> 16) == 1) \ |
6ddbc6e4 PB |
10721 | ge |= 3 << (n * 2); \ |
10722 | } while(0) | |
10723 | ||
10724 | #define ADD8(a, b, n) do { \ | |
10725 | uint32_t sum; \ | |
10726 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
10727 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
10728 | if ((sum >> 8) == 1) \ |
10729 | ge |= 1 << n; \ | |
6ddbc6e4 PB |
10730 | } while(0) |
10731 | ||
10732 | #define SUB16(a, b, n) do { \ | |
10733 | uint32_t sum; \ | |
10734 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
10735 | RESULT(sum, n, 16); \ | |
10736 | if ((sum >> 16) == 0) \ | |
10737 | ge |= 3 << (n * 2); \ | |
10738 | } while(0) | |
10739 | ||
10740 | #define SUB8(a, b, n) do { \ | |
10741 | uint32_t sum; \ | |
10742 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
10743 | RESULT(sum, n, 8); \ | |
10744 | if ((sum >> 8) == 0) \ | |
a87aa10b | 10745 | ge |= 1 << n; \ |
6ddbc6e4 PB |
10746 | } while(0) |
10747 | ||
10748 | #define PFX u | |
10749 | #define ARITH_GE | |
10750 | ||
10751 | #include "op_addsub.h" | |
10752 | ||
10753 | /* Halved signed arithmetic. */ | |
10754 | #define ADD16(a, b, n) \ | |
10755 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
10756 | #define SUB16(a, b, n) \ | |
10757 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
10758 | #define ADD8(a, b, n) \ | |
10759 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
10760 | #define SUB8(a, b, n) \ | |
10761 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
10762 | #define PFX sh | |
10763 | ||
10764 | #include "op_addsub.h" | |
10765 | ||
10766 | /* Halved unsigned arithmetic. */ | |
10767 | #define ADD16(a, b, n) \ | |
10768 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
10769 | #define SUB16(a, b, n) \ | |
10770 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
10771 | #define ADD8(a, b, n) \ | |
10772 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
10773 | #define SUB8(a, b, n) \ | |
10774 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
10775 | #define PFX uh | |
10776 | ||
10777 | #include "op_addsub.h" | |
10778 | ||
10779 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
10780 | { | |
10781 | if (a > b) | |
10782 | return a - b; | |
10783 | else | |
10784 | return b - a; | |
10785 | } | |
10786 | ||
10787 | /* Unsigned sum of absolute byte differences. */ | |
10788 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
10789 | { | |
10790 | uint32_t sum; | |
10791 | sum = do_usad(a, b); | |
10792 | sum += do_usad(a >> 8, b >> 8); | |
bdc3b6f5 | 10793 | sum += do_usad(a >> 16, b >> 16); |
6ddbc6e4 PB |
10794 | sum += do_usad(a >> 24, b >> 24); |
10795 | return sum; | |
10796 | } | |
10797 | ||
10798 | /* For ARMv6 SEL instruction. */ | |
10799 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
10800 | { | |
10801 | uint32_t mask; | |
10802 | ||
10803 | mask = 0; | |
10804 | if (flags & 1) | |
10805 | mask |= 0xff; | |
10806 | if (flags & 2) | |
10807 | mask |= 0xff00; | |
10808 | if (flags & 4) | |
10809 | mask |= 0xff0000; | |
10810 | if (flags & 8) | |
10811 | mask |= 0xff000000; | |
10812 | return (a & mask) | (b & ~mask); | |
10813 | } | |
10814 | ||
aa633469 PM |
10815 | /* CRC helpers. |
10816 | * The upper bytes of val (above the number specified by 'bytes') must have | |
10817 | * been zeroed out by the caller. | |
10818 | */ | |
eb0ecd5a WN |
10819 | uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) |
10820 | { | |
10821 | uint8_t buf[4]; | |
10822 | ||
aa633469 | 10823 | stl_le_p(buf, val); |
eb0ecd5a WN |
10824 | |
10825 | /* zlib crc32 converts the accumulator and output to one's complement. */ | |
10826 | return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | |
10827 | } | |
10828 | ||
10829 | uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | |
10830 | { | |
10831 | uint8_t buf[4]; | |
10832 | ||
aa633469 | 10833 | stl_le_p(buf, val); |
eb0ecd5a WN |
10834 | |
10835 | /* Linux crc32c converts the output to one's complement. */ | |
10836 | return crc32c(acc, buf, bytes) ^ 0xffffffff; | |
10837 | } | |
a9e01311 RH |
10838 | |
10839 | /* Return the exception level to which FP-disabled exceptions should | |
10840 | * be taken, or 0 if FP is enabled. | |
10841 | */ | |
ced31551 | 10842 | int fp_exception_el(CPUARMState *env, int cur_el) |
a9e01311 | 10843 | { |
55faa212 | 10844 | #ifndef CONFIG_USER_ONLY |
d5a6fa2d RH |
10845 | uint64_t hcr_el2; |
10846 | ||
a9e01311 RH |
10847 | /* CPACR and the CPTR registers don't exist before v6, so FP is |
10848 | * always accessible | |
10849 | */ | |
10850 | if (!arm_feature(env, ARM_FEATURE_V6)) { | |
10851 | return 0; | |
10852 | } | |
10853 | ||
d87513c0 PM |
10854 | if (arm_feature(env, ARM_FEATURE_M)) { |
10855 | /* CPACR can cause a NOCP UsageFault taken to current security state */ | |
10856 | if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) { | |
10857 | return 1; | |
10858 | } | |
10859 | ||
10860 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) { | |
10861 | if (!extract32(env->v7m.nsacr, 10, 1)) { | |
10862 | /* FP insns cause a NOCP UsageFault taken to Secure */ | |
10863 | return 3; | |
10864 | } | |
10865 | } | |
10866 | ||
10867 | return 0; | |
10868 | } | |
10869 | ||
d5a6fa2d RH |
10870 | hcr_el2 = arm_hcr_el2_eff(env); |
10871 | ||
a9e01311 RH |
10872 | /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: |
10873 | * 0, 2 : trap EL0 and EL1/PL1 accesses | |
10874 | * 1 : trap only EL0 accesses | |
10875 | * 3 : trap no accesses | |
c2ddb7cf | 10876 | * This register is ignored if E2H+TGE are both set. |
a9e01311 | 10877 | */ |
d5a6fa2d | 10878 | if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { |
fab8ad39 | 10879 | int fpen = FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN); |
c2ddb7cf RH |
10880 | |
10881 | switch (fpen) { | |
10882 | case 0: | |
10883 | case 2: | |
10884 | if (cur_el == 0 || cur_el == 1) { | |
10885 | /* Trap to PL1, which might be EL1 or EL3 */ | |
10886 | if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { | |
10887 | return 3; | |
10888 | } | |
10889 | return 1; | |
10890 | } | |
10891 | if (cur_el == 3 && !is_a64(env)) { | |
10892 | /* Secure PL1 running at EL3 */ | |
a9e01311 RH |
10893 | return 3; |
10894 | } | |
c2ddb7cf RH |
10895 | break; |
10896 | case 1: | |
10897 | if (cur_el == 0) { | |
10898 | return 1; | |
10899 | } | |
10900 | break; | |
10901 | case 3: | |
10902 | break; | |
a9e01311 | 10903 | } |
a9e01311 RH |
10904 | } |
10905 | ||
fc1120a7 PM |
10906 | /* |
10907 | * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode | |
10908 | * to control non-secure access to the FPU. It doesn't have any | |
10909 | * effect if EL3 is AArch64 or if EL3 doesn't exist at all. | |
10910 | */ | |
10911 | if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
10912 | cur_el <= 2 && !arm_is_secure_below_el3(env))) { | |
10913 | if (!extract32(env->cp15.nsacr, 10, 1)) { | |
10914 | /* FP insns act as UNDEF */ | |
10915 | return cur_el == 2 ? 2 : 1; | |
10916 | } | |
10917 | } | |
10918 | ||
d5a6fa2d RH |
10919 | /* |
10920 | * CPTR_EL2 is present in v7VE or v8, and changes format | |
10921 | * with HCR_EL2.E2H (regardless of TGE). | |
a9e01311 | 10922 | */ |
d5a6fa2d RH |
10923 | if (cur_el <= 2) { |
10924 | if (hcr_el2 & HCR_E2H) { | |
fab8ad39 | 10925 | switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) { |
d5a6fa2d RH |
10926 | case 1: |
10927 | if (cur_el != 0 || !(hcr_el2 & HCR_TGE)) { | |
10928 | break; | |
10929 | } | |
10930 | /* fall through */ | |
10931 | case 0: | |
10932 | case 2: | |
10933 | return 2; | |
10934 | } | |
10935 | } else if (arm_is_el2_enabled(env)) { | |
fab8ad39 | 10936 | if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) { |
d5a6fa2d RH |
10937 | return 2; |
10938 | } | |
10939 | } | |
a9e01311 RH |
10940 | } |
10941 | ||
10942 | /* CPTR_EL3 : present in v8 */ | |
fab8ad39 | 10943 | if (FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TFP)) { |
a9e01311 RH |
10944 | /* Trap all FP ops to EL3 */ |
10945 | return 3; | |
10946 | } | |
55faa212 | 10947 | #endif |
a9e01311 RH |
10948 | return 0; |
10949 | } | |
10950 | ||
b9f6033c RH |
10951 | /* Return the exception level we're running at if this is our mmu_idx */ |
10952 | int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) | |
10953 | { | |
10954 | if (mmu_idx & ARM_MMU_IDX_M) { | |
10955 | return mmu_idx & ARM_MMU_IDX_M_PRIV; | |
10956 | } | |
10957 | ||
10958 | switch (mmu_idx) { | |
10959 | case ARMMMUIdx_E10_0: | |
10960 | case ARMMMUIdx_E20_0: | |
10961 | case ARMMMUIdx_SE10_0: | |
b6ad6062 | 10962 | case ARMMMUIdx_SE20_0: |
b9f6033c RH |
10963 | return 0; |
10964 | case ARMMMUIdx_E10_1: | |
452ef8cb | 10965 | case ARMMMUIdx_E10_1_PAN: |
b9f6033c | 10966 | case ARMMMUIdx_SE10_1: |
452ef8cb | 10967 | case ARMMMUIdx_SE10_1_PAN: |
b9f6033c RH |
10968 | return 1; |
10969 | case ARMMMUIdx_E2: | |
10970 | case ARMMMUIdx_E20_2: | |
452ef8cb | 10971 | case ARMMMUIdx_E20_2_PAN: |
b6ad6062 RDC |
10972 | case ARMMMUIdx_SE2: |
10973 | case ARMMMUIdx_SE20_2: | |
10974 | case ARMMMUIdx_SE20_2_PAN: | |
b9f6033c RH |
10975 | return 2; |
10976 | case ARMMMUIdx_SE3: | |
10977 | return 3; | |
10978 | default: | |
10979 | g_assert_not_reached(); | |
10980 | } | |
10981 | } | |
10982 | ||
7aab5a8c | 10983 | #ifndef CONFIG_TCG |
65e4655c RH |
10984 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
10985 | { | |
7aab5a8c | 10986 | g_assert_not_reached(); |
65e4655c | 10987 | } |
7aab5a8c | 10988 | #endif |
65e4655c | 10989 | |
164690b2 | 10990 | ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) |
65e4655c | 10991 | { |
b6ad6062 RDC |
10992 | ARMMMUIdx idx; |
10993 | uint64_t hcr; | |
10994 | ||
65e4655c | 10995 | if (arm_feature(env, ARM_FEATURE_M)) { |
50494a27 | 10996 | return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); |
65e4655c RH |
10997 | } |
10998 | ||
6003d980 | 10999 | /* See ARM pseudo-function ELIsInHost. */ |
b9f6033c RH |
11000 | switch (el) { |
11001 | case 0: | |
b6ad6062 RDC |
11002 | hcr = arm_hcr_el2_eff(env); |
11003 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
11004 | idx = ARMMMUIdx_E20_0; | |
11005 | } else { | |
11006 | idx = ARMMMUIdx_E10_0; | |
6003d980 | 11007 | } |
b6ad6062 | 11008 | break; |
b9f6033c | 11009 | case 1: |
66412260 | 11010 | if (env->pstate & PSTATE_PAN) { |
b6ad6062 RDC |
11011 | idx = ARMMMUIdx_E10_1_PAN; |
11012 | } else { | |
11013 | idx = ARMMMUIdx_E10_1; | |
66412260 | 11014 | } |
b6ad6062 | 11015 | break; |
b9f6033c | 11016 | case 2: |
6003d980 | 11017 | /* Note that TGE does not apply at EL2. */ |
b6ad6062 | 11018 | if (arm_hcr_el2_eff(env) & HCR_E2H) { |
66412260 | 11019 | if (env->pstate & PSTATE_PAN) { |
b6ad6062 RDC |
11020 | idx = ARMMMUIdx_E20_2_PAN; |
11021 | } else { | |
11022 | idx = ARMMMUIdx_E20_2; | |
66412260 | 11023 | } |
b6ad6062 RDC |
11024 | } else { |
11025 | idx = ARMMMUIdx_E2; | |
6003d980 | 11026 | } |
b6ad6062 | 11027 | break; |
b9f6033c RH |
11028 | case 3: |
11029 | return ARMMMUIdx_SE3; | |
11030 | default: | |
11031 | g_assert_not_reached(); | |
65e4655c | 11032 | } |
b6ad6062 RDC |
11033 | |
11034 | if (arm_is_secure_below_el3(env)) { | |
11035 | idx &= ~ARM_MMU_IDX_A_NS; | |
11036 | } | |
11037 | ||
11038 | return idx; | |
50494a27 RH |
11039 | } |
11040 | ||
164690b2 RH |
11041 | ARMMMUIdx arm_mmu_idx(CPUARMState *env) |
11042 | { | |
11043 | return arm_mmu_idx_el(env, arm_current_el(env)); | |
11044 | } | |
11045 | ||
3902bfc6 RH |
11046 | static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, |
11047 | ARMMMUIdx mmu_idx, | |
11048 | CPUARMTBFlags flags) | |
fdd1b228 | 11049 | { |
a729a46b RH |
11050 | DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el); |
11051 | DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); | |
fdd1b228 | 11052 | |
fdd1b228 | 11053 | if (arm_singlestep_active(env)) { |
a729a46b | 11054 | DP_TBFLAG_ANY(flags, SS_ACTIVE, 1); |
fdd1b228 RH |
11055 | } |
11056 | return flags; | |
11057 | } | |
11058 | ||
3902bfc6 RH |
11059 | static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el, |
11060 | ARMMMUIdx mmu_idx, | |
11061 | CPUARMTBFlags flags) | |
43eccfb6 | 11062 | { |
8061a649 RH |
11063 | bool sctlr_b = arm_sctlr_b(env); |
11064 | ||
11065 | if (sctlr_b) { | |
a729a46b | 11066 | DP_TBFLAG_A32(flags, SCTLR__B, 1); |
8061a649 RH |
11067 | } |
11068 | if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { | |
a729a46b | 11069 | DP_TBFLAG_ANY(flags, BE_DATA, 1); |
8061a649 | 11070 | } |
a729a46b | 11071 | DP_TBFLAG_A32(flags, NS, !access_secure_reg(env)); |
43eccfb6 RH |
11072 | |
11073 | return rebuild_hflags_common(env, fp_el, mmu_idx, flags); | |
11074 | } | |
11075 | ||
3902bfc6 RH |
11076 | static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, |
11077 | ARMMMUIdx mmu_idx) | |
6e33ced5 | 11078 | { |
3902bfc6 | 11079 | CPUARMTBFlags flags = {}; |
4479ec30 RH |
11080 | uint32_t ccr = env->v7m.ccr[env->v7m.secure]; |
11081 | ||
11082 | /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */ | |
11083 | if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) { | |
11084 | DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); | |
11085 | } | |
6e33ced5 RH |
11086 | |
11087 | if (arm_v7m_is_handler_mode(env)) { | |
a729a46b | 11088 | DP_TBFLAG_M32(flags, HANDLER, 1); |
6e33ced5 RH |
11089 | } |
11090 | ||
11091 | /* | |
11092 | * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN | |
11093 | * is suppressing them because the requested execution priority | |
11094 | * is less than 0. | |
11095 | */ | |
11096 | if (arm_feature(env, ARM_FEATURE_V8) && | |
11097 | !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && | |
4479ec30 | 11098 | (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) { |
a729a46b | 11099 | DP_TBFLAG_M32(flags, STACKCHECK, 1); |
6e33ced5 RH |
11100 | } |
11101 | ||
11102 | return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); | |
11103 | } | |
11104 | ||
3902bfc6 RH |
11105 | static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, |
11106 | ARMMMUIdx mmu_idx) | |
c747224c | 11107 | { |
8480e933 | 11108 | CPUARMTBFlags flags = {}; |
4479ec30 RH |
11109 | int el = arm_current_el(env); |
11110 | ||
11111 | if (arm_sctlr(env, el) & SCTLR_A) { | |
11112 | DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); | |
11113 | } | |
0a54d68e RH |
11114 | |
11115 | if (arm_el_is_aa64(env, 1)) { | |
a729a46b | 11116 | DP_TBFLAG_A32(flags, VFPEN, 1); |
0a54d68e | 11117 | } |
5bb0a20b | 11118 | |
4479ec30 | 11119 | if (el < 2 && env->cp15.hstr_el2 && |
5bb0a20b | 11120 | (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { |
a729a46b | 11121 | DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); |
5bb0a20b MZ |
11122 | } |
11123 | ||
520d1621 PM |
11124 | if (env->uncached_cpsr & CPSR_IL) { |
11125 | DP_TBFLAG_ANY(flags, PSTATE__IL, 1); | |
11126 | } | |
11127 | ||
83f4baef | 11128 | return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); |
c747224c RH |
11129 | } |
11130 | ||
3902bfc6 RH |
11131 | static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, |
11132 | ARMMMUIdx mmu_idx) | |
a9e01311 | 11133 | { |
8480e933 | 11134 | CPUARMTBFlags flags = {}; |
d4d7503a | 11135 | ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); |
b830a5ee | 11136 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; |
d4d7503a RH |
11137 | uint64_t sctlr; |
11138 | int tbii, tbid; | |
b9adaa70 | 11139 | |
a729a46b | 11140 | DP_TBFLAG_ANY(flags, AARCH64_STATE, 1); |
cd208a1c | 11141 | |
339370b9 | 11142 | /* Get control bits for tagged addresses. */ |
b830a5ee RH |
11143 | tbid = aa64_va_parameter_tbi(tcr, mmu_idx); |
11144 | tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); | |
5d8634f5 | 11145 | |
a729a46b RH |
11146 | DP_TBFLAG_A64(flags, TBII, tbii); |
11147 | DP_TBFLAG_A64(flags, TBID, tbid); | |
d4d7503a RH |
11148 | |
11149 | if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { | |
11150 | int sve_el = sve_exception_el(env, el); | |
5d8634f5 | 11151 | |
d4d7503a | 11152 | /* |
397d922c RH |
11153 | * If either FP or SVE are disabled, translator does not need len. |
11154 | * If SVE EL > FP EL, FP exception has precedence, and translator | |
11155 | * does not need SVE EL. Save potential re-translations by forcing | |
11156 | * the unneeded data to zero. | |
d4d7503a | 11157 | */ |
397d922c RH |
11158 | if (fp_el != 0) { |
11159 | if (sve_el > fp_el) { | |
11160 | sve_el = 0; | |
11161 | } | |
11162 | } else if (sve_el == 0) { | |
5ef3cc56 | 11163 | DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el)); |
5d8634f5 | 11164 | } |
a729a46b | 11165 | DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); |
d4d7503a | 11166 | } |
1db5e96c | 11167 | |
aaec1432 | 11168 | sctlr = regime_sctlr(env, stage1); |
1db5e96c | 11169 | |
4479ec30 RH |
11170 | if (sctlr & SCTLR_A) { |
11171 | DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); | |
11172 | } | |
11173 | ||
8061a649 | 11174 | if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { |
a729a46b | 11175 | DP_TBFLAG_ANY(flags, BE_DATA, 1); |
8061a649 RH |
11176 | } |
11177 | ||
d4d7503a RH |
11178 | if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { |
11179 | /* | |
11180 | * In order to save space in flags, we record only whether | |
11181 | * pauth is "inactive", meaning all insns are implemented as | |
11182 | * a nop, or "active" when some action must be performed. | |
11183 | * The decision of which action to take is left to a helper. | |
11184 | */ | |
11185 | if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { | |
a729a46b | 11186 | DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1); |
1db5e96c | 11187 | } |
d4d7503a | 11188 | } |
0816ef1b | 11189 | |
d4d7503a RH |
11190 | if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { |
11191 | /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ | |
11192 | if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { | |
a729a46b | 11193 | DP_TBFLAG_A64(flags, BT, 1); |
0816ef1b | 11194 | } |
d4d7503a | 11195 | } |
08f1434a | 11196 | |
cc28fc30 | 11197 | /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ |
7a8014ab RH |
11198 | if (!(env->pstate & PSTATE_UAO)) { |
11199 | switch (mmu_idx) { | |
11200 | case ARMMMUIdx_E10_1: | |
11201 | case ARMMMUIdx_E10_1_PAN: | |
11202 | case ARMMMUIdx_SE10_1: | |
11203 | case ARMMMUIdx_SE10_1_PAN: | |
11204 | /* TODO: ARMv8.3-NV */ | |
a729a46b | 11205 | DP_TBFLAG_A64(flags, UNPRIV, 1); |
7a8014ab RH |
11206 | break; |
11207 | case ARMMMUIdx_E20_2: | |
11208 | case ARMMMUIdx_E20_2_PAN: | |
b6ad6062 RDC |
11209 | case ARMMMUIdx_SE20_2: |
11210 | case ARMMMUIdx_SE20_2_PAN: | |
7a8014ab RH |
11211 | /* |
11212 | * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is | |
11213 | * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR. | |
11214 | */ | |
11215 | if (env->cp15.hcr_el2 & HCR_TGE) { | |
a729a46b | 11216 | DP_TBFLAG_A64(flags, UNPRIV, 1); |
7a8014ab RH |
11217 | } |
11218 | break; | |
11219 | default: | |
11220 | break; | |
cc28fc30 | 11221 | } |
cc28fc30 RH |
11222 | } |
11223 | ||
520d1621 PM |
11224 | if (env->pstate & PSTATE_IL) { |
11225 | DP_TBFLAG_ANY(flags, PSTATE__IL, 1); | |
11226 | } | |
11227 | ||
81ae05fa RH |
11228 | if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { |
11229 | /* | |
11230 | * Set MTE_ACTIVE if any access may be Checked, and leave clear | |
11231 | * if all accesses must be Unchecked: | |
11232 | * 1) If no TBI, then there are no tags in the address to check, | |
11233 | * 2) If Tag Check Override, then all accesses are Unchecked, | |
11234 | * 3) If Tag Check Fail == 0, then Checked access have no effect, | |
11235 | * 4) If no Allocation Tag Access, then all accesses are Unchecked. | |
11236 | */ | |
11237 | if (allocation_tag_access_enabled(env, el, sctlr)) { | |
a729a46b | 11238 | DP_TBFLAG_A64(flags, ATA, 1); |
81ae05fa RH |
11239 | if (tbid |
11240 | && !(env->pstate & PSTATE_TCO) | |
11241 | && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) { | |
a729a46b | 11242 | DP_TBFLAG_A64(flags, MTE_ACTIVE, 1); |
81ae05fa RH |
11243 | } |
11244 | } | |
11245 | /* And again for unprivileged accesses, if required. */ | |
a729a46b | 11246 | if (EX_TBFLAG_A64(flags, UNPRIV) |
81ae05fa RH |
11247 | && tbid |
11248 | && !(env->pstate & PSTATE_TCO) | |
2d928adf | 11249 | && (sctlr & SCTLR_TCF0) |
81ae05fa | 11250 | && allocation_tag_access_enabled(env, 0, sctlr)) { |
a729a46b | 11251 | DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); |
81ae05fa RH |
11252 | } |
11253 | /* Cache TCMA as well as TBI. */ | |
a729a46b | 11254 | DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx)); |
81ae05fa RH |
11255 | } |
11256 | ||
d4d7503a RH |
11257 | return rebuild_hflags_common(env, fp_el, mmu_idx, flags); |
11258 | } | |
11259 | ||
3902bfc6 | 11260 | static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env) |
3d74e2e9 RH |
11261 | { |
11262 | int el = arm_current_el(env); | |
11263 | int fp_el = fp_exception_el(env, el); | |
164690b2 | 11264 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); |
3d74e2e9 RH |
11265 | |
11266 | if (is_a64(env)) { | |
11267 | return rebuild_hflags_a64(env, el, fp_el, mmu_idx); | |
11268 | } else if (arm_feature(env, ARM_FEATURE_M)) { | |
11269 | return rebuild_hflags_m32(env, fp_el, mmu_idx); | |
11270 | } else { | |
11271 | return rebuild_hflags_a32(env, fp_el, mmu_idx); | |
11272 | } | |
11273 | } | |
11274 | ||
11275 | void arm_rebuild_hflags(CPUARMState *env) | |
11276 | { | |
11277 | env->hflags = rebuild_hflags_internal(env); | |
11278 | } | |
11279 | ||
19717e9b PM |
11280 | /* |
11281 | * If we have triggered a EL state change we can't rely on the | |
11282 | * translator having passed it to us, we need to recompute. | |
11283 | */ | |
11284 | void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env) | |
11285 | { | |
11286 | int el = arm_current_el(env); | |
11287 | int fp_el = fp_exception_el(env, el); | |
11288 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
3902bfc6 | 11289 | |
19717e9b PM |
11290 | env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); |
11291 | } | |
11292 | ||
14f3c588 RH |
11293 | void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) |
11294 | { | |
11295 | int fp_el = fp_exception_el(env, el); | |
11296 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
11297 | ||
11298 | env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); | |
11299 | } | |
11300 | ||
f80741d1 AB |
11301 | /* |
11302 | * If we have triggered a EL state change we can't rely on the | |
563152e0 | 11303 | * translator having passed it to us, we need to recompute. |
f80741d1 AB |
11304 | */ |
11305 | void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) | |
11306 | { | |
11307 | int el = arm_current_el(env); | |
11308 | int fp_el = fp_exception_el(env, el); | |
11309 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
11310 | env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); | |
11311 | } | |
11312 | ||
14f3c588 RH |
11313 | void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) |
11314 | { | |
11315 | int fp_el = fp_exception_el(env, el); | |
11316 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
11317 | ||
11318 | env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); | |
11319 | } | |
11320 | ||
11321 | void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) | |
11322 | { | |
11323 | int fp_el = fp_exception_el(env, el); | |
11324 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
11325 | ||
11326 | env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx); | |
11327 | } | |
11328 | ||
0ee8b24a PMD |
11329 | static inline void assert_hflags_rebuild_correctly(CPUARMState *env) |
11330 | { | |
11331 | #ifdef CONFIG_DEBUG_TCG | |
3902bfc6 RH |
11332 | CPUARMTBFlags c = env->hflags; |
11333 | CPUARMTBFlags r = rebuild_hflags_internal(env); | |
0ee8b24a | 11334 | |
a378206a RH |
11335 | if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) { |
11336 | fprintf(stderr, "TCG hflags mismatch " | |
11337 | "(current:(0x%08x,0x" TARGET_FMT_lx ")" | |
11338 | " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n", | |
11339 | c.flags, c.flags2, r.flags, r.flags2); | |
0ee8b24a PMD |
11340 | abort(); |
11341 | } | |
11342 | #endif | |
11343 | } | |
11344 | ||
26702213 PM |
11345 | static bool mve_no_pred(CPUARMState *env) |
11346 | { | |
11347 | /* | |
11348 | * Return true if there is definitely no predication of MVE | |
11349 | * instructions by VPR or LTPSIZE. (Returning false even if there | |
11350 | * isn't any predication is OK; generated code will just be | |
11351 | * a little worse.) | |
11352 | * If the CPU does not implement MVE then this TB flag is always 0. | |
11353 | * | |
11354 | * NOTE: if you change this logic, the "recalculate s->mve_no_pred" | |
11355 | * logic in gen_update_fp_context() needs to be updated to match. | |
11356 | * | |
11357 | * We do not include the effect of the ECI bits here -- they are | |
11358 | * tracked in other TB flags. This simplifies the logic for | |
11359 | * "when did we emit code that changes the MVE_NO_PRED TB flag | |
11360 | * and thus need to end the TB?". | |
11361 | */ | |
11362 | if (cpu_isar_feature(aa32_mve, env_archcpu(env))) { | |
11363 | return false; | |
11364 | } | |
11365 | if (env->v7m.vpr) { | |
11366 | return false; | |
11367 | } | |
11368 | if (env->v7m.ltpsize < 4) { | |
11369 | return false; | |
11370 | } | |
11371 | return true; | |
11372 | } | |
11373 | ||
d4d7503a RH |
11374 | void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, |
11375 | target_ulong *cs_base, uint32_t *pflags) | |
11376 | { | |
3902bfc6 | 11377 | CPUARMTBFlags flags; |
d4d7503a | 11378 | |
0ee8b24a | 11379 | assert_hflags_rebuild_correctly(env); |
3902bfc6 | 11380 | flags = env->hflags; |
3d74e2e9 | 11381 | |
a729a46b | 11382 | if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { |
d4d7503a | 11383 | *pc = env->pc; |
d4d7503a | 11384 | if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { |
a729a46b | 11385 | DP_TBFLAG_A64(flags, BTYPE, env->btype); |
08f1434a | 11386 | } |
a9e01311 RH |
11387 | } else { |
11388 | *pc = env->regs[15]; | |
6e33ced5 RH |
11389 | |
11390 | if (arm_feature(env, ARM_FEATURE_M)) { | |
9550d1bd RH |
11391 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && |
11392 | FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) | |
11393 | != env->v7m.secure) { | |
a729a46b | 11394 | DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1); |
9550d1bd RH |
11395 | } |
11396 | ||
11397 | if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && | |
11398 | (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || | |
11399 | (env->v7m.secure && | |
11400 | !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { | |
11401 | /* | |
11402 | * ASPEN is set, but FPCA/SFPA indicate that there is no | |
11403 | * active FP context; we must create a new FP context before | |
11404 | * executing any FP insn. | |
11405 | */ | |
a729a46b | 11406 | DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1); |
9550d1bd RH |
11407 | } |
11408 | ||
11409 | bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; | |
11410 | if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { | |
a729a46b | 11411 | DP_TBFLAG_M32(flags, LSPACT, 1); |
9550d1bd | 11412 | } |
26702213 PM |
11413 | |
11414 | if (mve_no_pred(env)) { | |
11415 | DP_TBFLAG_M32(flags, MVE_NO_PRED, 1); | |
11416 | } | |
6e33ced5 | 11417 | } else { |
bbad7c62 RH |
11418 | /* |
11419 | * Note that XSCALE_CPAR shares bits with VECSTRIDE. | |
11420 | * Note that VECLEN+VECSTRIDE are RES0 for M-profile. | |
11421 | */ | |
11422 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
a729a46b | 11423 | DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); |
bbad7c62 | 11424 | } else { |
a729a46b RH |
11425 | DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); |
11426 | DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); | |
bbad7c62 | 11427 | } |
0a54d68e | 11428 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { |
a729a46b | 11429 | DP_TBFLAG_A32(flags, VFPEN, 1); |
0a54d68e | 11430 | } |
6e33ced5 RH |
11431 | } |
11432 | ||
a729a46b RH |
11433 | DP_TBFLAG_AM32(flags, THUMB, env->thumb); |
11434 | DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits); | |
d4d7503a | 11435 | } |
a9e01311 | 11436 | |
60e12c37 RH |
11437 | /* |
11438 | * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine | |
a9e01311 RH |
11439 | * states defined in the ARM ARM for software singlestep: |
11440 | * SS_ACTIVE PSTATE.SS State | |
11441 | * 0 x Inactive (the TB flag for SS is always 0) | |
11442 | * 1 0 Active-pending | |
11443 | * 1 1 Active-not-pending | |
ae6eb1e9 | 11444 | * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. |
a9e01311 | 11445 | */ |
a729a46b RH |
11446 | if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { |
11447 | DP_TBFLAG_ANY(flags, PSTATE__SS, 1); | |
a9e01311 | 11448 | } |
a9e01311 | 11449 | |
3902bfc6 | 11450 | *pflags = flags.flags; |
a378206a | 11451 | *cs_base = flags.flags2; |
a9e01311 | 11452 | } |
0ab5953b RH |
11453 | |
11454 | #ifdef TARGET_AARCH64 | |
11455 | /* | |
11456 | * The manual says that when SVE is enabled and VQ is widened the | |
11457 | * implementation is allowed to zero the previously inaccessible | |
11458 | * portion of the registers. The corollary to that is that when | |
11459 | * SVE is enabled and VQ is narrowed we are also allowed to zero | |
11460 | * the now inaccessible portion of the registers. | |
11461 | * | |
11462 | * The intent of this is that no predicate bit beyond VQ is ever set. | |
11463 | * Which means that some operations on predicate registers themselves | |
11464 | * may operate on full uint64_t or even unrolled across the maximum | |
11465 | * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally | |
11466 | * may well be cheaper than conditionals to restrict the operation | |
11467 | * to the relevant portion of a uint16_t[16]. | |
11468 | */ | |
11469 | void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) | |
11470 | { | |
11471 | int i, j; | |
11472 | uint64_t pmask; | |
11473 | ||
11474 | assert(vq >= 1 && vq <= ARM_MAX_VQ); | |
2fc0cc0e | 11475 | assert(vq <= env_archcpu(env)->sve_max_vq); |
0ab5953b RH |
11476 | |
11477 | /* Zap the high bits of the zregs. */ | |
11478 | for (i = 0; i < 32; i++) { | |
11479 | memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)); | |
11480 | } | |
11481 | ||
11482 | /* Zap the high bits of the pregs and ffr. */ | |
11483 | pmask = 0; | |
11484 | if (vq & 3) { | |
11485 | pmask = ~(-1ULL << (16 * (vq & 3))); | |
11486 | } | |
11487 | for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) { | |
11488 | for (i = 0; i < 17; ++i) { | |
11489 | env->vfp.pregs[i].p[j] &= pmask; | |
11490 | } | |
11491 | pmask = 0; | |
11492 | } | |
11493 | } | |
11494 | ||
11495 | /* | |
11496 | * Notice a change in SVE vector size when changing EL. | |
11497 | */ | |
9a05f7b6 RH |
11498 | void aarch64_sve_change_el(CPUARMState *env, int old_el, |
11499 | int new_el, bool el0_a64) | |
0ab5953b | 11500 | { |
2fc0cc0e | 11501 | ARMCPU *cpu = env_archcpu(env); |
0ab5953b | 11502 | int old_len, new_len; |
9a05f7b6 | 11503 | bool old_a64, new_a64; |
0ab5953b RH |
11504 | |
11505 | /* Nothing to do if no SVE. */ | |
cd208a1c | 11506 | if (!cpu_isar_feature(aa64_sve, cpu)) { |
0ab5953b RH |
11507 | return; |
11508 | } | |
11509 | ||
11510 | /* Nothing to do if FP is disabled in either EL. */ | |
11511 | if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) { | |
11512 | return; | |
11513 | } | |
11514 | ||
11515 | /* | |
11516 | * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped | |
11517 | * at ELx, or not available because the EL is in AArch32 state, then | |
11518 | * for all purposes other than a direct read, the ZCR_ELx.LEN field | |
11519 | * has an effective value of 0". | |
11520 | * | |
11521 | * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0). | |
11522 | * If we ignore aa32 state, we would fail to see the vq4->vq0 transition | |
11523 | * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that | |
11524 | * we already have the correct register contents when encountering the | |
11525 | * vq0->vq0 transition between EL0->EL1. | |
11526 | */ | |
9a05f7b6 RH |
11527 | old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; |
11528 | old_len = (old_a64 && !sve_exception_el(env, old_el) | |
5ef3cc56 | 11529 | ? sve_vqm1_for_el(env, old_el) : 0); |
9a05f7b6 RH |
11530 | new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; |
11531 | new_len = (new_a64 && !sve_exception_el(env, new_el) | |
5ef3cc56 | 11532 | ? sve_vqm1_for_el(env, new_el) : 0); |
0ab5953b RH |
11533 | |
11534 | /* When changing vector length, clear inaccessible state. */ | |
11535 | if (new_len < old_len) { | |
11536 | aarch64_sve_narrow_vq(env, new_len + 1); | |
11537 | } | |
11538 | } | |
11539 | #endif |