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Commit | Line | Data |
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ed3baad1 PMD |
1 | /* |
2 | * ARM generic helpers. | |
3 | * | |
4 | * This code is licensed under the GNU GPL v2 or later. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0-or-later | |
7 | */ | |
db725815 | 8 | |
74c21bd0 | 9 | #include "qemu/osdep.h" |
cd617484 | 10 | #include "qemu/log.h" |
194cbc49 | 11 | #include "trace.h" |
b5ff1b31 | 12 | #include "cpu.h" |
ccd38087 | 13 | #include "internals.h" |
5a534314 | 14 | #include "cpu-features.h" |
2ef6175a | 15 | #include "exec/helper-proto.h" |
db725815 | 16 | #include "qemu/main-loop.h" |
b8012ecf | 17 | #include "qemu/timer.h" |
1de7afc9 | 18 | #include "qemu/bitops.h" |
eb0ecd5a | 19 | #include "qemu/crc32c.h" |
0442428a | 20 | #include "qemu/qemu-print.h" |
63c91552 | 21 | #include "exec/exec-all.h" |
eb0ecd5a | 22 | #include <zlib.h> /* For crc32 */ |
64552b6b | 23 | #include "hw/irq.h" |
740b1759 | 24 | #include "sysemu/cpu-timers.h" |
f3a9b694 | 25 | #include "sysemu/kvm.h" |
0c1aaa66 | 26 | #include "sysemu/tcg.h" |
de390645 RH |
27 | #include "qapi/error.h" |
28 | #include "qemu/guest-random.h" | |
91f78c58 | 29 | #ifdef CONFIG_TCG |
6b5fe137 | 30 | #include "semihosting/common-semi.h" |
91f78c58 | 31 | #endif |
cf7c6d10 | 32 | #include "cpregs.h" |
0b03bdfc | 33 | |
352c98e5 LV |
34 | #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ |
35 | ||
affdb64d PM |
36 | static void switch_mode(CPUARMState *env, int mode); |
37 | ||
c4241c7d | 38 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) |
d4e6df63 | 39 | { |
375421cc | 40 | assert(ri->fieldoffset); |
67ed771d | 41 | if (cpreg_field_is_64bit(ri)) { |
c4241c7d | 42 | return CPREG_FIELD64(env, ri); |
22d9e1a9 | 43 | } else { |
c4241c7d | 44 | return CPREG_FIELD32(env, ri); |
22d9e1a9 | 45 | } |
d4e6df63 PM |
46 | } |
47 | ||
f43ee493 | 48 | void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
d4e6df63 | 49 | { |
375421cc | 50 | assert(ri->fieldoffset); |
67ed771d | 51 | if (cpreg_field_is_64bit(ri)) { |
22d9e1a9 PM |
52 | CPREG_FIELD64(env, ri) = value; |
53 | } else { | |
54 | CPREG_FIELD32(env, ri) = value; | |
55 | } | |
d4e6df63 PM |
56 | } |
57 | ||
11f136ee FA |
58 | static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) |
59 | { | |
60 | return (char *)env + ri->fieldoffset; | |
61 | } | |
62 | ||
49a66191 | 63 | uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) |
721fae12 | 64 | { |
59a1c327 | 65 | /* Raw read of a coprocessor register (as needed for migration, etc). */ |
721fae12 | 66 | if (ri->type & ARM_CP_CONST) { |
59a1c327 | 67 | return ri->resetvalue; |
721fae12 | 68 | } else if (ri->raw_readfn) { |
59a1c327 | 69 | return ri->raw_readfn(env, ri); |
721fae12 | 70 | } else if (ri->readfn) { |
59a1c327 | 71 | return ri->readfn(env, ri); |
721fae12 | 72 | } else { |
59a1c327 | 73 | return raw_read(env, ri); |
721fae12 | 74 | } |
721fae12 PM |
75 | } |
76 | ||
59a1c327 | 77 | static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, |
7900e9f1 | 78 | uint64_t v) |
721fae12 | 79 | { |
9b37a28c FR |
80 | /* |
81 | * Raw write of a coprocessor register (as needed for migration, etc). | |
721fae12 PM |
82 | * Note that constant registers are treated as write-ignored; the |
83 | * caller should check for success by whether a readback gives the | |
84 | * value written. | |
85 | */ | |
86 | if (ri->type & ARM_CP_CONST) { | |
59a1c327 | 87 | return; |
721fae12 | 88 | } else if (ri->raw_writefn) { |
c4241c7d | 89 | ri->raw_writefn(env, ri, v); |
721fae12 | 90 | } else if (ri->writefn) { |
c4241c7d | 91 | ri->writefn(env, ri, v); |
721fae12 | 92 | } else { |
afb2530f | 93 | raw_write(env, ri, v); |
721fae12 | 94 | } |
721fae12 PM |
95 | } |
96 | ||
375421cc PM |
97 | static bool raw_accessors_invalid(const ARMCPRegInfo *ri) |
98 | { | |
9b37a28c FR |
99 | /* |
100 | * Return true if the regdef would cause an assertion if you called | |
375421cc PM |
101 | * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a |
102 | * program bug for it not to have the NO_RAW flag). | |
103 | * NB that returning false here doesn't necessarily mean that calling | |
104 | * read/write_raw_cp_reg() is safe, because we can't distinguish "has | |
105 | * read/write access functions which are safe for raw use" from "has | |
106 | * read/write access functions which have side effects but has forgotten | |
107 | * to provide raw access functions". | |
108 | * The tests here line up with the conditions in read/write_raw_cp_reg() | |
109 | * and assertions in raw_read()/raw_write(). | |
110 | */ | |
111 | if ((ri->type & ARM_CP_CONST) || | |
112 | ri->fieldoffset || | |
113 | ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { | |
114 | return false; | |
115 | } | |
116 | return true; | |
117 | } | |
118 | ||
b698e4ee | 119 | bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync) |
721fae12 PM |
120 | { |
121 | /* Write the coprocessor state from cpu->env to the (index,value) list. */ | |
122 | int i; | |
123 | bool ok = true; | |
124 | ||
125 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
126 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
127 | const ARMCPRegInfo *ri; | |
b698e4ee | 128 | uint64_t newval; |
59a1c327 | 129 | |
60322b39 | 130 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
131 | if (!ri) { |
132 | ok = false; | |
133 | continue; | |
134 | } | |
7a0e58fa | 135 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
136 | continue; |
137 | } | |
b698e4ee PM |
138 | |
139 | newval = read_raw_cp_reg(&cpu->env, ri); | |
140 | if (kvm_sync) { | |
141 | /* | |
142 | * Only sync if the previous list->cpustate sync succeeded. | |
143 | * Rather than tracking the success/failure state for every | |
144 | * item in the list, we just recheck "does the raw write we must | |
145 | * have made in write_list_to_cpustate() read back OK" here. | |
146 | */ | |
147 | uint64_t oldval = cpu->cpreg_values[i]; | |
148 | ||
149 | if (oldval == newval) { | |
150 | continue; | |
151 | } | |
152 | ||
153 | write_raw_cp_reg(&cpu->env, ri, oldval); | |
154 | if (read_raw_cp_reg(&cpu->env, ri) != oldval) { | |
155 | continue; | |
156 | } | |
157 | ||
158 | write_raw_cp_reg(&cpu->env, ri, newval); | |
159 | } | |
160 | cpu->cpreg_values[i] = newval; | |
721fae12 PM |
161 | } |
162 | return ok; | |
163 | } | |
164 | ||
165 | bool write_list_to_cpustate(ARMCPU *cpu) | |
166 | { | |
167 | int i; | |
168 | bool ok = true; | |
169 | ||
170 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
171 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
172 | uint64_t v = cpu->cpreg_values[i]; | |
721fae12 PM |
173 | const ARMCPRegInfo *ri; |
174 | ||
60322b39 | 175 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
176 | if (!ri) { |
177 | ok = false; | |
178 | continue; | |
179 | } | |
7a0e58fa | 180 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
181 | continue; |
182 | } | |
9b37a28c FR |
183 | /* |
184 | * Write value and confirm it reads back as written | |
721fae12 PM |
185 | * (to catch read-only registers and partially read-only |
186 | * registers where the incoming migration value doesn't match) | |
187 | */ | |
59a1c327 PM |
188 | write_raw_cp_reg(&cpu->env, ri, v); |
189 | if (read_raw_cp_reg(&cpu->env, ri) != v) { | |
721fae12 PM |
190 | ok = false; |
191 | } | |
192 | } | |
193 | return ok; | |
194 | } | |
195 | ||
196 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | |
197 | { | |
198 | ARMCPU *cpu = opaque; | |
5860362d RH |
199 | uint32_t regidx = (uintptr_t)key; |
200 | const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); | |
721fae12 | 201 | |
04215eb1 | 202 | if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { |
721fae12 PM |
203 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); |
204 | /* The value array need not be initialized at this point */ | |
205 | cpu->cpreg_array_len++; | |
206 | } | |
207 | } | |
208 | ||
209 | static void count_cpreg(gpointer key, gpointer opaque) | |
210 | { | |
211 | ARMCPU *cpu = opaque; | |
721fae12 PM |
212 | const ARMCPRegInfo *ri; |
213 | ||
5860362d | 214 | ri = g_hash_table_lookup(cpu->cp_regs, key); |
721fae12 | 215 | |
04215eb1 | 216 | if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { |
721fae12 PM |
217 | cpu->cpreg_array_len++; |
218 | } | |
219 | } | |
220 | ||
221 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | |
222 | { | |
5860362d RH |
223 | uint64_t aidx = cpreg_to_kvm_id((uintptr_t)a); |
224 | uint64_t bidx = cpreg_to_kvm_id((uintptr_t)b); | |
721fae12 | 225 | |
cbf239b7 AR |
226 | if (aidx > bidx) { |
227 | return 1; | |
228 | } | |
229 | if (aidx < bidx) { | |
230 | return -1; | |
231 | } | |
232 | return 0; | |
721fae12 PM |
233 | } |
234 | ||
235 | void init_cpreg_list(ARMCPU *cpu) | |
236 | { | |
9b37a28c FR |
237 | /* |
238 | * Initialise the cpreg_tuples[] array based on the cp_regs hash. | |
721fae12 PM |
239 | * Note that we require cpreg_tuples[] to be sorted by key ID. |
240 | */ | |
57b6d95e | 241 | GList *keys; |
721fae12 PM |
242 | int arraylen; |
243 | ||
57b6d95e | 244 | keys = g_hash_table_get_keys(cpu->cp_regs); |
721fae12 PM |
245 | keys = g_list_sort(keys, cpreg_key_compare); |
246 | ||
247 | cpu->cpreg_array_len = 0; | |
248 | ||
249 | g_list_foreach(keys, count_cpreg, cpu); | |
250 | ||
251 | arraylen = cpu->cpreg_array_len; | |
252 | cpu->cpreg_indexes = g_new(uint64_t, arraylen); | |
253 | cpu->cpreg_values = g_new(uint64_t, arraylen); | |
254 | cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); | |
255 | cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); | |
256 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; | |
257 | cpu->cpreg_array_len = 0; | |
258 | ||
259 | g_list_foreach(keys, add_cpreg_to_list, cpu); | |
260 | ||
261 | assert(cpu->cpreg_array_len == arraylen); | |
262 | ||
263 | g_list_free(keys); | |
264 | } | |
265 | ||
68e9c2fe | 266 | /* |
93dd1e61 | 267 | * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0. |
68e9c2fe EI |
268 | */ |
269 | static CPAccessResult access_el3_aa32ns(CPUARMState *env, | |
3f208fd7 PM |
270 | const ARMCPRegInfo *ri, |
271 | bool isread) | |
68e9c2fe | 272 | { |
93dd1e61 EI |
273 | if (!is_a64(env) && arm_current_el(env) == 3 && |
274 | arm_is_secure_below_el3(env)) { | |
68e9c2fe EI |
275 | return CP_ACCESS_TRAP_UNCATEGORIZED; |
276 | } | |
277 | return CP_ACCESS_OK; | |
278 | } | |
279 | ||
9b37a28c FR |
280 | /* |
281 | * Some secure-only AArch32 registers trap to EL3 if used from | |
5513c3ab PM |
282 | * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). |
283 | * Note that an access from Secure EL1 can only happen if EL3 is AArch64. | |
284 | * We assume that the .access field is set to PL1_RW. | |
285 | */ | |
286 | static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, | |
3f208fd7 PM |
287 | const ARMCPRegInfo *ri, |
288 | bool isread) | |
5513c3ab PM |
289 | { |
290 | if (arm_current_el(env) == 3) { | |
291 | return CP_ACCESS_OK; | |
292 | } | |
293 | if (arm_is_secure_below_el3(env)) { | |
926c1b97 RDC |
294 | if (env->cp15.scr_el3 & SCR_EEL2) { |
295 | return CP_ACCESS_TRAP_EL2; | |
296 | } | |
5513c3ab PM |
297 | return CP_ACCESS_TRAP_EL3; |
298 | } | |
299 | /* This will be EL1 NS and EL2 NS, which just UNDEF */ | |
300 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
301 | } | |
302 | ||
9b37a28c FR |
303 | /* |
304 | * Check for traps to performance monitor registers, which are controlled | |
1fce1ba9 PM |
305 | * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. |
306 | */ | |
307 | static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, | |
308 | bool isread) | |
309 | { | |
310 | int el = arm_current_el(env); | |
59dd089c | 311 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
1fce1ba9 | 312 | |
59dd089c | 313 | if (el < 2 && (mdcr_el2 & MDCR_TPM)) { |
1fce1ba9 PM |
314 | return CP_ACCESS_TRAP_EL2; |
315 | } | |
316 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
317 | return CP_ACCESS_TRAP_EL3; | |
318 | } | |
319 | return CP_ACCESS_OK; | |
320 | } | |
321 | ||
84929218 | 322 | /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ |
6d482423 RH |
323 | CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, |
324 | bool isread) | |
84929218 RH |
325 | { |
326 | if (arm_current_el(env) == 1) { | |
327 | uint64_t trap = isread ? HCR_TRVM : HCR_TVM; | |
328 | if (arm_hcr_el2_eff(env) & trap) { | |
329 | return CP_ACCESS_TRAP_EL2; | |
330 | } | |
331 | } | |
332 | return CP_ACCESS_OK; | |
333 | } | |
334 | ||
1803d271 RH |
335 | /* Check for traps from EL1 due to HCR_EL2.TSW. */ |
336 | static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri, | |
337 | bool isread) | |
338 | { | |
339 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) { | |
340 | return CP_ACCESS_TRAP_EL2; | |
341 | } | |
342 | return CP_ACCESS_OK; | |
343 | } | |
344 | ||
99602377 RH |
345 | /* Check for traps from EL1 due to HCR_EL2.TACR. */ |
346 | static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri, | |
347 | bool isread) | |
348 | { | |
349 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TACR)) { | |
350 | return CP_ACCESS_TRAP_EL2; | |
351 | } | |
352 | return CP_ACCESS_OK; | |
353 | } | |
354 | ||
30881b73 RH |
355 | /* Check for traps from EL1 due to HCR_EL2.TTLB. */ |
356 | static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri, | |
357 | bool isread) | |
358 | { | |
359 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TTLB)) { | |
360 | return CP_ACCESS_TRAP_EL2; | |
361 | } | |
362 | return CP_ACCESS_OK; | |
363 | } | |
364 | ||
0f66d223 PM |
365 | /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */ |
366 | static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri, | |
367 | bool isread) | |
368 | { | |
369 | if (arm_current_el(env) == 1 && | |
370 | (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBIS))) { | |
371 | return CP_ACCESS_TRAP_EL2; | |
372 | } | |
373 | return CP_ACCESS_OK; | |
374 | } | |
375 | ||
fe3ca86c PM |
376 | #ifdef TARGET_AARCH64 |
377 | /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */ | |
378 | static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri, | |
379 | bool isread) | |
380 | { | |
381 | if (arm_current_el(env) == 1 && | |
382 | (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBOS))) { | |
383 | return CP_ACCESS_TRAP_EL2; | |
384 | } | |
385 | return CP_ACCESS_OK; | |
386 | } | |
387 | #endif | |
388 | ||
c4241c7d | 389 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
c983fe6c | 390 | { |
2fc0cc0e | 391 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 392 | |
8d5c773e | 393 | raw_write(env, ri, value); |
d10eb08f | 394 | tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ |
c983fe6c PM |
395 | } |
396 | ||
c4241c7d | 397 | static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
08de207b | 398 | { |
2fc0cc0e | 399 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 400 | |
8d5c773e | 401 | if (raw_read(env, ri) != value) { |
9b37a28c FR |
402 | /* |
403 | * Unlike real hardware the qemu TLB uses virtual addresses, | |
08de207b PM |
404 | * not modified virtual addresses, so this causes a TLB flush. |
405 | */ | |
d10eb08f | 406 | tlb_flush(CPU(cpu)); |
8d5c773e | 407 | raw_write(env, ri, value); |
08de207b | 408 | } |
08de207b | 409 | } |
c4241c7d PM |
410 | |
411 | static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
412 | uint64_t value) | |
08de207b | 413 | { |
2fc0cc0e | 414 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 415 | |
452a0955 | 416 | if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) |
014406b5 | 417 | && !extended_addresses_enabled(env)) { |
9b37a28c FR |
418 | /* |
419 | * For VMSA (when not using the LPAE long descriptor page table | |
08de207b PM |
420 | * format) this register includes the ASID, so do a TLB flush. |
421 | * For PMSA it is purely a process ID and no action is needed. | |
422 | */ | |
d10eb08f | 423 | tlb_flush(CPU(cpu)); |
08de207b | 424 | } |
8d5c773e | 425 | raw_write(env, ri, value); |
08de207b PM |
426 | } |
427 | ||
575a94af RH |
428 | static int alle1_tlbmask(CPUARMState *env) |
429 | { | |
430 | /* | |
431 | * Note that the 'ALL' scope must invalidate both stage 1 and | |
432 | * stage 2 translations, whereas most other scopes only invalidate | |
433 | * stage 1 translations. | |
434 | */ | |
435 | return (ARMMMUIdxBit_E10_1 | | |
436 | ARMMMUIdxBit_E10_1_PAN | | |
437 | ARMMMUIdxBit_E10_0 | | |
438 | ARMMMUIdxBit_Stage2 | | |
439 | ARMMMUIdxBit_Stage2_S); | |
440 | } | |
441 | ||
442 | ||
b4ab8ce9 PM |
443 | /* IS variants of TLB operations must affect all cores */ |
444 | static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
445 | uint64_t value) | |
446 | { | |
29a0af61 | 447 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
448 | |
449 | tlb_flush_all_cpus_synced(cs); | |
450 | } | |
451 | ||
452 | static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
453 | uint64_t value) | |
454 | { | |
29a0af61 | 455 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
456 | |
457 | tlb_flush_all_cpus_synced(cs); | |
458 | } | |
459 | ||
460 | static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
461 | uint64_t value) | |
462 | { | |
29a0af61 | 463 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
464 | |
465 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
466 | } | |
467 | ||
468 | static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
469 | uint64_t value) | |
470 | { | |
29a0af61 | 471 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
472 | |
473 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
474 | } | |
475 | ||
476 | /* | |
477 | * Non-IS variants of TLB operations are upgraded to | |
373e7ffd | 478 | * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to |
b4ab8ce9 PM |
479 | * force broadcast of these operations. |
480 | */ | |
481 | static bool tlb_force_broadcast(CPUARMState *env) | |
482 | { | |
373e7ffd | 483 | return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB); |
b4ab8ce9 PM |
484 | } |
485 | ||
c4241c7d PM |
486 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
487 | uint64_t value) | |
d929823f PM |
488 | { |
489 | /* Invalidate all (TLBIALL) */ | |
527db2be | 490 | CPUState *cs = env_cpu(env); |
00c8cb0a | 491 | |
b4ab8ce9 | 492 | if (tlb_force_broadcast(env)) { |
527db2be RH |
493 | tlb_flush_all_cpus_synced(cs); |
494 | } else { | |
495 | tlb_flush(cs); | |
b4ab8ce9 | 496 | } |
d929823f PM |
497 | } |
498 | ||
c4241c7d PM |
499 | static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
500 | uint64_t value) | |
d929823f PM |
501 | { |
502 | /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ | |
527db2be | 503 | CPUState *cs = env_cpu(env); |
31b030d4 | 504 | |
527db2be | 505 | value &= TARGET_PAGE_MASK; |
b4ab8ce9 | 506 | if (tlb_force_broadcast(env)) { |
527db2be RH |
507 | tlb_flush_page_all_cpus_synced(cs, value); |
508 | } else { | |
509 | tlb_flush_page(cs, value); | |
b4ab8ce9 | 510 | } |
d929823f PM |
511 | } |
512 | ||
c4241c7d PM |
513 | static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
514 | uint64_t value) | |
d929823f PM |
515 | { |
516 | /* Invalidate by ASID (TLBIASID) */ | |
527db2be | 517 | CPUState *cs = env_cpu(env); |
00c8cb0a | 518 | |
b4ab8ce9 | 519 | if (tlb_force_broadcast(env)) { |
527db2be RH |
520 | tlb_flush_all_cpus_synced(cs); |
521 | } else { | |
522 | tlb_flush(cs); | |
b4ab8ce9 | 523 | } |
d929823f PM |
524 | } |
525 | ||
c4241c7d PM |
526 | static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
527 | uint64_t value) | |
d929823f PM |
528 | { |
529 | /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ | |
527db2be | 530 | CPUState *cs = env_cpu(env); |
31b030d4 | 531 | |
527db2be | 532 | value &= TARGET_PAGE_MASK; |
b4ab8ce9 | 533 | if (tlb_force_broadcast(env)) { |
527db2be RH |
534 | tlb_flush_page_all_cpus_synced(cs, value); |
535 | } else { | |
536 | tlb_flush_page(cs, value); | |
b4ab8ce9 | 537 | } |
fa439fc5 PM |
538 | } |
539 | ||
541ef8c2 SS |
540 | static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, |
541 | uint64_t value) | |
542 | { | |
29a0af61 | 543 | CPUState *cs = env_cpu(env); |
541ef8c2 | 544 | |
575a94af | 545 | tlb_flush_by_mmuidx(cs, alle1_tlbmask(env)); |
541ef8c2 SS |
546 | } |
547 | ||
548 | static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
549 | uint64_t value) | |
550 | { | |
29a0af61 | 551 | CPUState *cs = env_cpu(env); |
541ef8c2 | 552 | |
575a94af | 553 | tlb_flush_by_mmuidx_all_cpus_synced(cs, alle1_tlbmask(env)); |
541ef8c2 SS |
554 | } |
555 | ||
541ef8c2 SS |
556 | |
557 | static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
558 | uint64_t value) | |
559 | { | |
29a0af61 | 560 | CPUState *cs = env_cpu(env); |
541ef8c2 | 561 | |
e013b741 | 562 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); |
541ef8c2 SS |
563 | } |
564 | ||
565 | static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
566 | uint64_t value) | |
567 | { | |
29a0af61 | 568 | CPUState *cs = env_cpu(env); |
541ef8c2 | 569 | |
e013b741 | 570 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); |
541ef8c2 SS |
571 | } |
572 | ||
573 | static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
574 | uint64_t value) | |
575 | { | |
29a0af61 | 576 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
577 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
578 | ||
e013b741 | 579 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); |
541ef8c2 SS |
580 | } |
581 | ||
582 | static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
583 | uint64_t value) | |
584 | { | |
29a0af61 | 585 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
586 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
587 | ||
a67cf277 | 588 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
e013b741 | 589 | ARMMMUIdxBit_E2); |
541ef8c2 SS |
590 | } |
591 | ||
575a94af RH |
592 | static void tlbiipas2_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, |
593 | uint64_t value) | |
594 | { | |
595 | CPUState *cs = env_cpu(env); | |
596 | uint64_t pageaddr = (value & MAKE_64BIT_MASK(0, 28)) << 12; | |
597 | ||
598 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2); | |
599 | } | |
600 | ||
601 | static void tlbiipas2is_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
602 | uint64_t value) | |
603 | { | |
604 | CPUState *cs = env_cpu(env); | |
605 | uint64_t pageaddr = (value & MAKE_64BIT_MASK(0, 28)) << 12; | |
606 | ||
607 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, ARMMMUIdxBit_Stage2); | |
608 | } | |
609 | ||
e9aa6c21 | 610 | static const ARMCPRegInfo cp_reginfo[] = { |
9b37a28c FR |
611 | /* |
612 | * Define the secure and non-secure FCSE identifier CP registers | |
54bf36ed FA |
613 | * separately because there is no secure bank in V8 (no _EL3). This allows |
614 | * the secure register to be properly reset and migrated. There is also no | |
615 | * v8 EL1 version of the register so the non-secure instance stands alone. | |
616 | */ | |
9c513e78 | 617 | { .name = "FCSEIDR", |
54bf36ed FA |
618 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
619 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, | |
620 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), | |
621 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, | |
9c513e78 | 622 | { .name = "FCSEIDR_S", |
54bf36ed FA |
623 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
624 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
625 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), | |
d4e6df63 | 626 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, |
9b37a28c FR |
627 | /* |
628 | * Define the secure and non-secure context identifier CP registers | |
54bf36ed FA |
629 | * separately because there is no secure bank in V8 (no _EL3). This allows |
630 | * the secure register to be properly reset and migrated. In the | |
631 | * non-secure case, the 32-bit register will have reset and migration | |
632 | * disabled during registration as it is handled by the 64-bit instance. | |
633 | */ | |
634 | { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
014406b5 | 635 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
84929218 | 636 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
158c276c | 637 | .fgt = FGT_CONTEXTIDR_EL1, |
84929218 | 638 | .secure = ARM_CP_SECSTATE_NS, |
54bf36ed FA |
639 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), |
640 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, | |
9c513e78 | 641 | { .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32, |
54bf36ed | 642 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
84929218 RH |
643 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
644 | .secure = ARM_CP_SECSTATE_S, | |
54bf36ed | 645 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), |
d4e6df63 | 646 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, |
9449fdf6 PM |
647 | }; |
648 | ||
649 | static const ARMCPRegInfo not_v8_cp_reginfo[] = { | |
9b37a28c FR |
650 | /* |
651 | * NB: Some of these registers exist in v8 but with more precise | |
9449fdf6 PM |
652 | * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). |
653 | */ | |
654 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
655 | { .name = "DACR", |
656 | .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, | |
84929218 | 657 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
0c17d68c FA |
658 | .writefn = dacr_write, .raw_writefn = raw_write, |
659 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
660 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
9b37a28c FR |
661 | /* |
662 | * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. | |
a903c449 | 663 | * For v6 and v5, these mappings are overly broad. |
4fdd17dd | 664 | */ |
a903c449 EI |
665 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0, |
666 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
667 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1, | |
668 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
669 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4, | |
670 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
671 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8, | |
4fdd17dd | 672 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, |
c4804214 PM |
673 | /* Cache maintenance ops; some of this space may be overridden later. */ |
674 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | |
675 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | |
676 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | |
e9aa6c21 PM |
677 | }; |
678 | ||
7d57f408 | 679 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
9b37a28c FR |
680 | /* |
681 | * Not all pre-v6 cores implemented this WFI, so this is slightly | |
7d57f408 PM |
682 | * over-broad. |
683 | */ | |
684 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | |
685 | .access = PL1_W, .type = ARM_CP_WFI }, | |
7d57f408 PM |
686 | }; |
687 | ||
688 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | |
9b37a28c FR |
689 | /* |
690 | * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which | |
7d57f408 PM |
691 | * is UNPREDICTABLE; we choose to NOP as most implementations do). |
692 | */ | |
693 | { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
694 | .access = PL1_W, .type = ARM_CP_WFI }, | |
9b37a28c FR |
695 | /* |
696 | * L1 cache lockdown. Not architectural in v6 and earlier but in practice | |
34f90529 PM |
697 | * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and |
698 | * OMAPCP will override this space. | |
699 | */ | |
700 | { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, | |
701 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), | |
702 | .resetvalue = 0 }, | |
703 | { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, | |
704 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), | |
705 | .resetvalue = 0 }, | |
776d4e5c PM |
706 | /* v6 doesn't have the cache ID registers but Linux reads them anyway */ |
707 | { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, | |
7a0e58fa | 708 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 709 | .resetvalue = 0 }, |
9b37a28c FR |
710 | /* |
711 | * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; | |
50300698 PM |
712 | * implementing it as RAZ means the "debug architecture version" bits |
713 | * will read as a reserved value, which should cause Linux to not try | |
714 | * to use the debug hardware. | |
715 | */ | |
716 | { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
717 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
9b37a28c FR |
718 | /* |
719 | * MMU TLB control. Note that the wildcarding means we cover not just | |
995939a6 PM |
720 | * the unified TLB ops but also the dside/iside/inner-shareable variants. |
721 | */ | |
722 | { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, | |
723 | .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, | |
7a0e58fa | 724 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
725 | { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, |
726 | .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, | |
7a0e58fa | 727 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
728 | { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, |
729 | .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, | |
7a0e58fa | 730 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
731 | { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, |
732 | .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, | |
7a0e58fa | 733 | .type = ARM_CP_NO_RAW }, |
a903c449 EI |
734 | { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2, |
735 | .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, | |
736 | { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, | |
737 | .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, | |
7d57f408 PM |
738 | }; |
739 | ||
c4241c7d PM |
740 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
741 | uint64_t value) | |
2771db27 | 742 | { |
f0aff255 FA |
743 | uint32_t mask = 0; |
744 | ||
745 | /* In ARMv8 most bits of CPACR_EL1 are RES0. */ | |
746 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
9b37a28c FR |
747 | /* |
748 | * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. | |
f0aff255 FA |
749 | * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. |
750 | * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. | |
751 | */ | |
7fbc6a40 | 752 | if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { |
f0aff255 | 753 | /* VFP coprocessor: cp10 & cp11 [23:20] */ |
fab8ad39 RH |
754 | mask |= R_CPACR_ASEDIS_MASK | |
755 | R_CPACR_D32DIS_MASK | | |
756 | R_CPACR_CP11_MASK | | |
757 | R_CPACR_CP10_MASK; | |
f0aff255 FA |
758 | |
759 | if (!arm_feature(env, ARM_FEATURE_NEON)) { | |
760 | /* ASEDIS [31] bit is RAO/WI */ | |
fab8ad39 | 761 | value |= R_CPACR_ASEDIS_MASK; |
f0aff255 FA |
762 | } |
763 | ||
9b37a28c FR |
764 | /* |
765 | * VFPv3 and upwards with NEON implement 32 double precision | |
f0aff255 FA |
766 | * registers (D0-D31). |
767 | */ | |
a6627f5f | 768 | if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { |
f0aff255 | 769 | /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ |
fab8ad39 | 770 | value |= R_CPACR_D32DIS_MASK; |
f0aff255 FA |
771 | } |
772 | } | |
773 | value &= mask; | |
2771db27 | 774 | } |
fc1120a7 PM |
775 | |
776 | /* | |
777 | * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 | |
778 | * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. | |
779 | */ | |
780 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
781 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
fab8ad39 RH |
782 | mask = R_CPACR_CP11_MASK | R_CPACR_CP10_MASK; |
783 | value = (value & ~mask) | (env->cp15.cpacr_el1 & mask); | |
fc1120a7 PM |
784 | } |
785 | ||
7ebd5f2e | 786 | env->cp15.cpacr_el1 = value; |
2771db27 PM |
787 | } |
788 | ||
fc1120a7 PM |
789 | static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
790 | { | |
791 | /* | |
792 | * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 | |
793 | * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. | |
794 | */ | |
795 | uint64_t value = env->cp15.cpacr_el1; | |
796 | ||
797 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
798 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
fab8ad39 | 799 | value = ~(R_CPACR_CP11_MASK | R_CPACR_CP10_MASK); |
fc1120a7 PM |
800 | } |
801 | return value; | |
802 | } | |
803 | ||
804 | ||
5deac39c PM |
805 | static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
806 | { | |
9b37a28c FR |
807 | /* |
808 | * Call cpacr_write() so that we reset with the correct RAO bits set | |
5deac39c PM |
809 | * for our CPU features. |
810 | */ | |
811 | cpacr_write(env, ri, 0); | |
812 | } | |
813 | ||
3f208fd7 PM |
814 | static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
815 | bool isread) | |
c6f19164 GB |
816 | { |
817 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
818 | /* Check if CPACR accesses are to be trapped to EL2 */ | |
e6ef0169 | 819 | if (arm_current_el(env) == 1 && arm_is_el2_enabled(env) && |
fab8ad39 | 820 | FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TCPAC)) { |
c6f19164 GB |
821 | return CP_ACCESS_TRAP_EL2; |
822 | /* Check if CPACR accesses are to be trapped to EL3 */ | |
823 | } else if (arm_current_el(env) < 3 && | |
fab8ad39 | 824 | FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { |
c6f19164 GB |
825 | return CP_ACCESS_TRAP_EL3; |
826 | } | |
827 | } | |
828 | ||
829 | return CP_ACCESS_OK; | |
830 | } | |
831 | ||
3f208fd7 PM |
832 | static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
833 | bool isread) | |
c6f19164 GB |
834 | { |
835 | /* Check if CPTR accesses are set to trap to EL3 */ | |
fab8ad39 RH |
836 | if (arm_current_el(env) == 2 && |
837 | FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { | |
c6f19164 GB |
838 | return CP_ACCESS_TRAP_EL3; |
839 | } | |
840 | ||
841 | return CP_ACCESS_OK; | |
842 | } | |
843 | ||
7d57f408 PM |
844 | static const ARMCPRegInfo v6_cp_reginfo[] = { |
845 | /* prefetch by MVA in v6, NOP in v7 */ | |
846 | { .name = "MVA_prefetch", | |
847 | .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, | |
848 | .access = PL1_W, .type = ARM_CP_NOP }, | |
9b37a28c FR |
849 | /* |
850 | * We need to break the TB after ISB to execute self-modifying code | |
6df99dec SS |
851 | * correctly and also to take any pending interrupts immediately. |
852 | * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. | |
853 | */ | |
7d57f408 | 854 | { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, |
6df99dec | 855 | .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, |
091fd17c | 856 | { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
7d57f408 | 857 | .access = PL0_W, .type = ARM_CP_NOP }, |
091fd17c | 858 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
7d57f408 | 859 | .access = PL0_W, .type = ARM_CP_NOP }, |
06d76f31 | 860 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
84929218 | 861 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
b848ce2b FA |
862 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), |
863 | offsetof(CPUARMState, cp15.ifar_ns) }, | |
06d76f31 | 864 | .resetvalue = 0, }, |
9b37a28c FR |
865 | /* |
866 | * Watchpoint Fault Address Register : should actually only be present | |
06d76f31 PM |
867 | * for 1136, 1176, 11MPCore. |
868 | */ | |
869 | { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
870 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, | |
34222fb8 | 871 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, |
c6f19164 | 872 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, |
b19ed03c | 873 | .fgt = FGT_CPACR_EL1, |
7ebd5f2e | 874 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), |
fc1120a7 | 875 | .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read }, |
7d57f408 PM |
876 | }; |
877 | ||
57a4a11b AL |
878 | typedef struct pm_event { |
879 | uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ | |
880 | /* If the event is supported on this CPU (used to generate PMCEID[01]) */ | |
881 | bool (*supported)(CPUARMState *); | |
882 | /* | |
883 | * Retrieve the current count of the underlying event. The programmed | |
884 | * counters hold a difference from the return value from this function | |
885 | */ | |
886 | uint64_t (*get_count)(CPUARMState *); | |
4e7beb0c AL |
887 | /* |
888 | * Return how many nanoseconds it will take (at a minimum) for count events | |
889 | * to occur. A negative value indicates the counter will never overflow, or | |
890 | * that the counter has otherwise arranged for the overflow bit to be set | |
891 | * and the PMU interrupt to be raised on overflow. | |
892 | */ | |
893 | int64_t (*ns_per_count)(uint64_t); | |
57a4a11b AL |
894 | } pm_event; |
895 | ||
b2e23725 AL |
896 | static bool event_always_supported(CPUARMState *env) |
897 | { | |
898 | return true; | |
899 | } | |
900 | ||
0d4bfd7d AL |
901 | static uint64_t swinc_get_count(CPUARMState *env) |
902 | { | |
903 | /* | |
904 | * SW_INCR events are written directly to the pmevcntr's by writes to | |
905 | * PMSWINC, so there is no underlying count maintained by the PMU itself | |
906 | */ | |
907 | return 0; | |
908 | } | |
909 | ||
4e7beb0c AL |
910 | static int64_t swinc_ns_per(uint64_t ignored) |
911 | { | |
912 | return -1; | |
913 | } | |
914 | ||
b2e23725 AL |
915 | /* |
916 | * Return the underlying cycle count for the PMU cycle counters. If we're in | |
917 | * usermode, simply return 0. | |
918 | */ | |
919 | static uint64_t cycles_get_count(CPUARMState *env) | |
920 | { | |
921 | #ifndef CONFIG_USER_ONLY | |
922 | return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
923 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); | |
924 | #else | |
925 | return cpu_get_host_ticks(); | |
926 | #endif | |
927 | } | |
928 | ||
929 | #ifndef CONFIG_USER_ONLY | |
4e7beb0c AL |
930 | static int64_t cycles_ns_per(uint64_t cycles) |
931 | { | |
932 | return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles; | |
933 | } | |
934 | ||
b2e23725 AL |
935 | static bool instructions_supported(CPUARMState *env) |
936 | { | |
740b1759 | 937 | return icount_enabled() == 1; /* Precise instruction counting */ |
b2e23725 AL |
938 | } |
939 | ||
940 | static uint64_t instructions_get_count(CPUARMState *env) | |
941 | { | |
8191d368 | 942 | return (uint64_t)icount_get_raw(); |
b2e23725 | 943 | } |
4e7beb0c AL |
944 | |
945 | static int64_t instructions_ns_per(uint64_t icount) | |
946 | { | |
8191d368 | 947 | return icount_to_ns((int64_t)icount); |
4e7beb0c | 948 | } |
b2e23725 AL |
949 | #endif |
950 | ||
a793bcd0 | 951 | static bool pmuv3p1_events_supported(CPUARMState *env) |
0727f63b PM |
952 | { |
953 | /* For events which are supported in any v8.1 PMU */ | |
a793bcd0 | 954 | return cpu_isar_feature(any_pmuv3p1, env_archcpu(env)); |
0727f63b PM |
955 | } |
956 | ||
a793bcd0 | 957 | static bool pmuv3p4_events_supported(CPUARMState *env) |
15dd1ebd PM |
958 | { |
959 | /* For events which are supported in any v8.1 PMU */ | |
a793bcd0 | 960 | return cpu_isar_feature(any_pmuv3p4, env_archcpu(env)); |
15dd1ebd PM |
961 | } |
962 | ||
0727f63b PM |
963 | static uint64_t zero_event_get_count(CPUARMState *env) |
964 | { | |
965 | /* For events which on QEMU never fire, so their count is always zero */ | |
966 | return 0; | |
967 | } | |
968 | ||
969 | static int64_t zero_event_ns_per(uint64_t cycles) | |
970 | { | |
971 | /* An event which never fires can never overflow */ | |
972 | return -1; | |
973 | } | |
974 | ||
57a4a11b | 975 | static const pm_event pm_events[] = { |
0d4bfd7d AL |
976 | { .number = 0x000, /* SW_INCR */ |
977 | .supported = event_always_supported, | |
978 | .get_count = swinc_get_count, | |
4e7beb0c | 979 | .ns_per_count = swinc_ns_per, |
0d4bfd7d | 980 | }, |
b2e23725 AL |
981 | #ifndef CONFIG_USER_ONLY |
982 | { .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */ | |
983 | .supported = instructions_supported, | |
984 | .get_count = instructions_get_count, | |
4e7beb0c | 985 | .ns_per_count = instructions_ns_per, |
b2e23725 AL |
986 | }, |
987 | { .number = 0x011, /* CPU_CYCLES, Cycle */ | |
988 | .supported = event_always_supported, | |
989 | .get_count = cycles_get_count, | |
4e7beb0c | 990 | .ns_per_count = cycles_ns_per, |
0727f63b | 991 | }, |
b2e23725 | 992 | #endif |
0727f63b | 993 | { .number = 0x023, /* STALL_FRONTEND */ |
a793bcd0 | 994 | .supported = pmuv3p1_events_supported, |
0727f63b PM |
995 | .get_count = zero_event_get_count, |
996 | .ns_per_count = zero_event_ns_per, | |
997 | }, | |
998 | { .number = 0x024, /* STALL_BACKEND */ | |
a793bcd0 | 999 | .supported = pmuv3p1_events_supported, |
0727f63b PM |
1000 | .get_count = zero_event_get_count, |
1001 | .ns_per_count = zero_event_ns_per, | |
1002 | }, | |
15dd1ebd | 1003 | { .number = 0x03c, /* STALL */ |
a793bcd0 | 1004 | .supported = pmuv3p4_events_supported, |
15dd1ebd PM |
1005 | .get_count = zero_event_get_count, |
1006 | .ns_per_count = zero_event_ns_per, | |
1007 | }, | |
57a4a11b AL |
1008 | }; |
1009 | ||
1010 | /* | |
1011 | * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of | |
1012 | * events (i.e. the statistical profiling extension), this implementation | |
1013 | * should first be updated to something sparse instead of the current | |
1014 | * supported_event_map[] array. | |
1015 | */ | |
15dd1ebd | 1016 | #define MAX_EVENT_ID 0x3c |
57a4a11b AL |
1017 | #define UNSUPPORTED_EVENT UINT16_MAX |
1018 | static uint16_t supported_event_map[MAX_EVENT_ID + 1]; | |
1019 | ||
1020 | /* | |
bf8d0969 AL |
1021 | * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map |
1022 | * of ARM event numbers to indices in our pm_events array. | |
57a4a11b AL |
1023 | * |
1024 | * Note: Events in the 0x40XX range are not currently supported. | |
1025 | */ | |
bf8d0969 | 1026 | void pmu_init(ARMCPU *cpu) |
57a4a11b | 1027 | { |
57a4a11b AL |
1028 | unsigned int i; |
1029 | ||
bf8d0969 AL |
1030 | /* |
1031 | * Empty supported_event_map and cpu->pmceid[01] before adding supported | |
1032 | * events to them | |
1033 | */ | |
57a4a11b AL |
1034 | for (i = 0; i < ARRAY_SIZE(supported_event_map); i++) { |
1035 | supported_event_map[i] = UNSUPPORTED_EVENT; | |
1036 | } | |
bf8d0969 AL |
1037 | cpu->pmceid0 = 0; |
1038 | cpu->pmceid1 = 0; | |
57a4a11b AL |
1039 | |
1040 | for (i = 0; i < ARRAY_SIZE(pm_events); i++) { | |
1041 | const pm_event *cnt = &pm_events[i]; | |
1042 | assert(cnt->number <= MAX_EVENT_ID); | |
1043 | /* We do not currently support events in the 0x40xx range */ | |
1044 | assert(cnt->number <= 0x3f); | |
1045 | ||
bf8d0969 | 1046 | if (cnt->supported(&cpu->env)) { |
57a4a11b | 1047 | supported_event_map[cnt->number] = i; |
67da43d6 | 1048 | uint64_t event_mask = 1ULL << (cnt->number & 0x1f); |
bf8d0969 AL |
1049 | if (cnt->number & 0x20) { |
1050 | cpu->pmceid1 |= event_mask; | |
1051 | } else { | |
1052 | cpu->pmceid0 |= event_mask; | |
1053 | } | |
57a4a11b AL |
1054 | } |
1055 | } | |
57a4a11b AL |
1056 | } |
1057 | ||
5ecdd3e4 AL |
1058 | /* |
1059 | * Check at runtime whether a PMU event is supported for the current machine | |
1060 | */ | |
1061 | static bool event_supported(uint16_t number) | |
1062 | { | |
1063 | if (number > MAX_EVENT_ID) { | |
1064 | return false; | |
1065 | } | |
1066 | return supported_event_map[number] != UNSUPPORTED_EVENT; | |
1067 | } | |
1068 | ||
3f208fd7 PM |
1069 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1070 | bool isread) | |
200ac0ef | 1071 | { |
9b37a28c FR |
1072 | /* |
1073 | * Performance monitor registers user accessibility is controlled | |
1fce1ba9 PM |
1074 | * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable |
1075 | * trapping to EL2 or EL3 for other accesses. | |
200ac0ef | 1076 | */ |
1fce1ba9 | 1077 | int el = arm_current_el(env); |
59dd089c | 1078 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
1fce1ba9 | 1079 | |
6ecd0b6b | 1080 | if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { |
fcd25206 | 1081 | return CP_ACCESS_TRAP; |
200ac0ef | 1082 | } |
59dd089c | 1083 | if (el < 2 && (mdcr_el2 & MDCR_TPM)) { |
1fce1ba9 PM |
1084 | return CP_ACCESS_TRAP_EL2; |
1085 | } | |
1086 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
1087 | return CP_ACCESS_TRAP_EL3; | |
1088 | } | |
1089 | ||
fcd25206 | 1090 | return CP_ACCESS_OK; |
200ac0ef PM |
1091 | } |
1092 | ||
6ecd0b6b AB |
1093 | static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, |
1094 | const ARMCPRegInfo *ri, | |
1095 | bool isread) | |
1096 | { | |
1097 | /* ER: event counter read trap control */ | |
1098 | if (arm_feature(env, ARM_FEATURE_V8) | |
1099 | && arm_current_el(env) == 0 | |
1100 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 | |
1101 | && isread) { | |
1102 | return CP_ACCESS_OK; | |
1103 | } | |
1104 | ||
1105 | return pmreg_access(env, ri, isread); | |
1106 | } | |
1107 | ||
1108 | static CPAccessResult pmreg_access_swinc(CPUARMState *env, | |
1109 | const ARMCPRegInfo *ri, | |
1110 | bool isread) | |
1111 | { | |
1112 | /* SW: software increment write trap control */ | |
1113 | if (arm_feature(env, ARM_FEATURE_V8) | |
1114 | && arm_current_el(env) == 0 | |
1115 | && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 | |
1116 | && !isread) { | |
1117 | return CP_ACCESS_OK; | |
1118 | } | |
1119 | ||
1120 | return pmreg_access(env, ri, isread); | |
1121 | } | |
1122 | ||
6ecd0b6b AB |
1123 | static CPAccessResult pmreg_access_selr(CPUARMState *env, |
1124 | const ARMCPRegInfo *ri, | |
1125 | bool isread) | |
1126 | { | |
1127 | /* ER: event counter read trap control */ | |
1128 | if (arm_feature(env, ARM_FEATURE_V8) | |
1129 | && arm_current_el(env) == 0 | |
1130 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { | |
1131 | return CP_ACCESS_OK; | |
1132 | } | |
1133 | ||
1134 | return pmreg_access(env, ri, isread); | |
1135 | } | |
1136 | ||
1137 | static CPAccessResult pmreg_access_ccntr(CPUARMState *env, | |
1138 | const ARMCPRegInfo *ri, | |
1139 | bool isread) | |
1140 | { | |
1141 | /* CR: cycle counter read trap control */ | |
1142 | if (arm_feature(env, ARM_FEATURE_V8) | |
1143 | && arm_current_el(env) == 0 | |
1144 | && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 | |
1145 | && isread) { | |
1146 | return CP_ACCESS_OK; | |
1147 | } | |
1148 | ||
1149 | return pmreg_access(env, ri, isread); | |
1150 | } | |
1151 | ||
01765386 PM |
1152 | /* |
1153 | * Bits in MDCR_EL2 and MDCR_EL3 which pmu_counter_enabled() looks at. | |
1154 | * We use these to decide whether we need to wrap a write to MDCR_EL2 | |
1155 | * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls. | |
1156 | */ | |
47b385da PM |
1157 | #define MDCR_EL2_PMU_ENABLE_BITS \ |
1158 | (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP) | |
0b42f4fa | 1159 | #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD) |
01765386 | 1160 | |
9b37a28c FR |
1161 | /* |
1162 | * Returns true if the counter (pass 31 for PMCCNTR) should count events using | |
033614c4 AL |
1163 | * the current EL, security state, and register configuration. |
1164 | */ | |
1165 | static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) | |
87124fde | 1166 | { |
033614c4 AL |
1167 | uint64_t filter; |
1168 | bool e, p, u, nsk, nsu, nsh, m; | |
872d2034 | 1169 | bool enabled, prohibited = false, filtered; |
033614c4 AL |
1170 | bool secure = arm_is_secure(env); |
1171 | int el = arm_current_el(env); | |
59dd089c RDC |
1172 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
1173 | uint8_t hpmn = mdcr_el2 & MDCR_HPMN; | |
87124fde | 1174 | |
cbbb3041 AJ |
1175 | if (!arm_feature(env, ARM_FEATURE_PMU)) { |
1176 | return false; | |
1177 | } | |
1178 | ||
033614c4 AL |
1179 | if (!arm_feature(env, ARM_FEATURE_EL2) || |
1180 | (counter < hpmn || counter == 31)) { | |
1181 | e = env->cp15.c9_pmcr & PMCRE; | |
1182 | } else { | |
59dd089c | 1183 | e = mdcr_el2 & MDCR_HPME; |
87124fde | 1184 | } |
033614c4 | 1185 | enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); |
87124fde | 1186 | |
872d2034 PM |
1187 | /* Is event counting prohibited? */ |
1188 | if (el == 2 && (counter < hpmn || counter == 31)) { | |
1189 | prohibited = mdcr_el2 & MDCR_HPMD; | |
1190 | } | |
1191 | if (secure) { | |
1192 | prohibited = prohibited || !(env->cp15.mdcr_el3 & MDCR_SPME); | |
033614c4 AL |
1193 | } |
1194 | ||
0b42f4fa PM |
1195 | if (counter == 31) { |
1196 | /* | |
1197 | * The cycle counter defaults to running. PMCR.DP says "disable | |
1198 | * the cycle counter when event counting is prohibited". | |
1199 | * Some MDCR bits disable the cycle counter specifically. | |
1200 | */ | |
1201 | prohibited = prohibited && env->cp15.c9_pmcr & PMCRDP; | |
1202 | if (cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { | |
1203 | if (secure) { | |
1204 | prohibited = prohibited || (env->cp15.mdcr_el3 & MDCR_SCCD); | |
1205 | } | |
1206 | if (el == 2) { | |
1207 | prohibited = prohibited || (mdcr_el2 & MDCR_HCCD); | |
1208 | } | |
1209 | } | |
033614c4 AL |
1210 | } |
1211 | ||
5ecdd3e4 AL |
1212 | if (counter == 31) { |
1213 | filter = env->cp15.pmccfiltr_el0; | |
1214 | } else { | |
1215 | filter = env->cp15.c14_pmevtyper[counter]; | |
1216 | } | |
033614c4 AL |
1217 | |
1218 | p = filter & PMXEVTYPER_P; | |
1219 | u = filter & PMXEVTYPER_U; | |
1220 | nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); | |
1221 | nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); | |
1222 | nsh = arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); | |
1223 | m = arm_el_is_aa64(env, 1) && | |
1224 | arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); | |
1225 | ||
1226 | if (el == 0) { | |
1227 | filtered = secure ? u : u != nsu; | |
1228 | } else if (el == 1) { | |
1229 | filtered = secure ? p : p != nsk; | |
1230 | } else if (el == 2) { | |
1231 | filtered = !nsh; | |
1232 | } else { /* EL3 */ | |
1233 | filtered = m != p; | |
1234 | } | |
1235 | ||
5ecdd3e4 AL |
1236 | if (counter != 31) { |
1237 | /* | |
1238 | * If not checking PMCCNTR, ensure the counter is setup to an event we | |
1239 | * support | |
1240 | */ | |
1241 | uint16_t event = filter & PMXEVTYPER_EVTCOUNT; | |
1242 | if (!event_supported(event)) { | |
1243 | return false; | |
1244 | } | |
1245 | } | |
1246 | ||
033614c4 | 1247 | return enabled && !prohibited && !filtered; |
87124fde | 1248 | } |
033614c4 | 1249 | |
f4efb4b2 AL |
1250 | static void pmu_update_irq(CPUARMState *env) |
1251 | { | |
2fc0cc0e | 1252 | ARMCPU *cpu = env_archcpu(env); |
f4efb4b2 AL |
1253 | qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && |
1254 | (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); | |
1255 | } | |
1256 | ||
b57aa7bd PM |
1257 | static bool pmccntr_clockdiv_enabled(CPUARMState *env) |
1258 | { | |
1259 | /* | |
1260 | * Return true if the clock divider is enabled and the cycle counter | |
1261 | * is supposed to tick only once every 64 clock cycles. This is | |
1262 | * controlled by PMCR.D, but if PMCR.LC is set to enable the long | |
1263 | * (64-bit) cycle counter PMCR.D has no effect. | |
1264 | */ | |
1265 | return (env->cp15.c9_pmcr & (PMCRD | PMCRLC)) == PMCRD; | |
1266 | } | |
1267 | ||
47b385da PM |
1268 | static bool pmevcntr_is_64_bit(CPUARMState *env, int counter) |
1269 | { | |
1270 | /* Return true if the specified event counter is configured to be 64 bit */ | |
1271 | ||
1272 | /* This isn't intended to be used with the cycle counter */ | |
1273 | assert(counter < 31); | |
1274 | ||
1275 | if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { | |
1276 | return false; | |
1277 | } | |
1278 | ||
1279 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
1280 | /* | |
1281 | * MDCR_EL2.HLP still applies even when EL2 is disabled in the | |
1282 | * current security state, so we don't use arm_mdcr_el2_eff() here. | |
1283 | */ | |
1284 | bool hlp = env->cp15.mdcr_el2 & MDCR_HLP; | |
1285 | int hpmn = env->cp15.mdcr_el2 & MDCR_HPMN; | |
1286 | ||
3d80bbf1 | 1287 | if (counter >= hpmn) { |
47b385da PM |
1288 | return hlp; |
1289 | } | |
1290 | } | |
1291 | return env->cp15.c9_pmcr & PMCRLP; | |
1292 | } | |
1293 | ||
5d05b9d4 AL |
1294 | /* |
1295 | * Ensure c15_ccnt is the guest-visible count so that operations such as | |
1296 | * enabling/disabling the counter or filtering, modifying the count itself, | |
1297 | * etc. can be done logically. This is essentially a no-op if the counter is | |
1298 | * not enabled at the time of the call. | |
1299 | */ | |
f2b2f53f | 1300 | static void pmccntr_op_start(CPUARMState *env) |
ec7b4ce4 | 1301 | { |
b2e23725 | 1302 | uint64_t cycles = cycles_get_count(env); |
ec7b4ce4 | 1303 | |
033614c4 | 1304 | if (pmu_counter_enabled(env, 31)) { |
5d05b9d4 | 1305 | uint64_t eff_cycles = cycles; |
b57aa7bd | 1306 | if (pmccntr_clockdiv_enabled(env)) { |
5d05b9d4 AL |
1307 | eff_cycles /= 64; |
1308 | } | |
1309 | ||
f4efb4b2 AL |
1310 | uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta; |
1311 | ||
1312 | uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \ | |
1313 | 1ull << 63 : 1ull << 31; | |
1314 | if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { | |
76e25d41 | 1315 | env->cp15.c9_pmovsr |= (1ULL << 31); |
f4efb4b2 AL |
1316 | pmu_update_irq(env); |
1317 | } | |
1318 | ||
1319 | env->cp15.c15_ccnt = new_pmccntr; | |
ec7b4ce4 | 1320 | } |
5d05b9d4 AL |
1321 | env->cp15.c15_ccnt_delta = cycles; |
1322 | } | |
ec7b4ce4 | 1323 | |
5d05b9d4 AL |
1324 | /* |
1325 | * If PMCCNTR is enabled, recalculate the delta between the clock and the | |
1326 | * guest-visible count. A call to pmccntr_op_finish should follow every call to | |
1327 | * pmccntr_op_start. | |
1328 | */ | |
f2b2f53f | 1329 | static void pmccntr_op_finish(CPUARMState *env) |
5d05b9d4 | 1330 | { |
033614c4 | 1331 | if (pmu_counter_enabled(env, 31)) { |
4e7beb0c AL |
1332 | #ifndef CONFIG_USER_ONLY |
1333 | /* Calculate when the counter will next overflow */ | |
1334 | uint64_t remaining_cycles = -env->cp15.c15_ccnt; | |
1335 | if (!(env->cp15.c9_pmcr & PMCRLC)) { | |
1336 | remaining_cycles = (uint32_t)remaining_cycles; | |
1337 | } | |
1338 | int64_t overflow_in = cycles_ns_per(remaining_cycles); | |
1339 | ||
1340 | if (overflow_in > 0) { | |
f1dd2506 PM |
1341 | int64_t overflow_at; |
1342 | ||
1343 | if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
1344 | overflow_in, &overflow_at)) { | |
1345 | ARMCPU *cpu = env_archcpu(env); | |
1346 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); | |
1347 | } | |
4e7beb0c AL |
1348 | } |
1349 | #endif | |
5d05b9d4 | 1350 | |
4e7beb0c | 1351 | uint64_t prev_cycles = env->cp15.c15_ccnt_delta; |
b57aa7bd | 1352 | if (pmccntr_clockdiv_enabled(env)) { |
5d05b9d4 AL |
1353 | prev_cycles /= 64; |
1354 | } | |
5d05b9d4 | 1355 | env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt; |
ec7b4ce4 AF |
1356 | } |
1357 | } | |
1358 | ||
5ecdd3e4 AL |
1359 | static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) |
1360 | { | |
1361 | ||
1362 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; | |
1363 | uint64_t count = 0; | |
1364 | if (event_supported(event)) { | |
1365 | uint16_t event_idx = supported_event_map[event]; | |
1366 | count = pm_events[event_idx].get_count(env); | |
1367 | } | |
1368 | ||
1369 | if (pmu_counter_enabled(env, counter)) { | |
47b385da PM |
1370 | uint64_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter]; |
1371 | uint64_t overflow_mask = pmevcntr_is_64_bit(env, counter) ? | |
1372 | 1ULL << 63 : 1ULL << 31; | |
f4efb4b2 | 1373 | |
47b385da | 1374 | if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & overflow_mask) { |
f4efb4b2 AL |
1375 | env->cp15.c9_pmovsr |= (1 << counter); |
1376 | pmu_update_irq(env); | |
1377 | } | |
1378 | env->cp15.c14_pmevcntr[counter] = new_pmevcntr; | |
5ecdd3e4 AL |
1379 | } |
1380 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1381 | } | |
1382 | ||
1383 | static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) | |
1384 | { | |
1385 | if (pmu_counter_enabled(env, counter)) { | |
4e7beb0c AL |
1386 | #ifndef CONFIG_USER_ONLY |
1387 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; | |
1388 | uint16_t event_idx = supported_event_map[event]; | |
47b385da PM |
1389 | uint64_t delta = -(env->cp15.c14_pmevcntr[counter] + 1); |
1390 | int64_t overflow_in; | |
1391 | ||
1392 | if (!pmevcntr_is_64_bit(env, counter)) { | |
1393 | delta = (uint32_t)delta; | |
1394 | } | |
1395 | overflow_in = pm_events[event_idx].ns_per_count(delta); | |
4e7beb0c AL |
1396 | |
1397 | if (overflow_in > 0) { | |
f1dd2506 PM |
1398 | int64_t overflow_at; |
1399 | ||
1400 | if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
1401 | overflow_in, &overflow_at)) { | |
1402 | ARMCPU *cpu = env_archcpu(env); | |
1403 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); | |
1404 | } | |
4e7beb0c AL |
1405 | } |
1406 | #endif | |
1407 | ||
5ecdd3e4 AL |
1408 | env->cp15.c14_pmevcntr_delta[counter] -= |
1409 | env->cp15.c14_pmevcntr[counter]; | |
1410 | } | |
1411 | } | |
1412 | ||
5d05b9d4 AL |
1413 | void pmu_op_start(CPUARMState *env) |
1414 | { | |
5ecdd3e4 | 1415 | unsigned int i; |
5d05b9d4 | 1416 | pmccntr_op_start(env); |
5ecdd3e4 AL |
1417 | for (i = 0; i < pmu_num_counters(env); i++) { |
1418 | pmevcntr_op_start(env, i); | |
1419 | } | |
5d05b9d4 AL |
1420 | } |
1421 | ||
1422 | void pmu_op_finish(CPUARMState *env) | |
1423 | { | |
5ecdd3e4 | 1424 | unsigned int i; |
5d05b9d4 | 1425 | pmccntr_op_finish(env); |
5ecdd3e4 AL |
1426 | for (i = 0; i < pmu_num_counters(env); i++) { |
1427 | pmevcntr_op_finish(env, i); | |
1428 | } | |
5d05b9d4 AL |
1429 | } |
1430 | ||
033614c4 AL |
1431 | void pmu_pre_el_change(ARMCPU *cpu, void *ignored) |
1432 | { | |
1433 | pmu_op_start(&cpu->env); | |
1434 | } | |
1435 | ||
1436 | void pmu_post_el_change(ARMCPU *cpu, void *ignored) | |
1437 | { | |
1438 | pmu_op_finish(&cpu->env); | |
1439 | } | |
1440 | ||
4e7beb0c AL |
1441 | void arm_pmu_timer_cb(void *opaque) |
1442 | { | |
1443 | ARMCPU *cpu = opaque; | |
1444 | ||
1445 | /* | |
1446 | * Update all the counter values based on the current underlying counts, | |
1447 | * triggering interrupts to be raised, if necessary. pmu_op_finish() also | |
1448 | * has the effect of setting the cpu->pmu_timer to the next earliest time a | |
1449 | * counter may expire. | |
1450 | */ | |
1451 | pmu_op_start(&cpu->env); | |
1452 | pmu_op_finish(&cpu->env); | |
1453 | } | |
1454 | ||
c4241c7d PM |
1455 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1456 | uint64_t value) | |
200ac0ef | 1457 | { |
5d05b9d4 | 1458 | pmu_op_start(env); |
7c2cb42b AF |
1459 | |
1460 | if (value & PMCRC) { | |
1461 | /* The counter has been reset */ | |
1462 | env->cp15.c15_ccnt = 0; | |
1463 | } | |
1464 | ||
5ecdd3e4 AL |
1465 | if (value & PMCRP) { |
1466 | unsigned int i; | |
1467 | for (i = 0; i < pmu_num_counters(env); i++) { | |
1468 | env->cp15.c14_pmevcntr[i] = 0; | |
1469 | } | |
1470 | } | |
1471 | ||
9323e79f PM |
1472 | env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; |
1473 | env->cp15.c9_pmcr |= (value & PMCR_WRITABLE_MASK); | |
7c2cb42b | 1474 | |
5d05b9d4 | 1475 | pmu_op_finish(env); |
7c2cb42b AF |
1476 | } |
1477 | ||
0d4bfd7d AL |
1478 | static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1479 | uint64_t value) | |
1480 | { | |
1481 | unsigned int i; | |
47b385da PM |
1482 | uint64_t overflow_mask, new_pmswinc; |
1483 | ||
0d4bfd7d AL |
1484 | for (i = 0; i < pmu_num_counters(env); i++) { |
1485 | /* Increment a counter's count iff: */ | |
1486 | if ((value & (1 << i)) && /* counter's bit is set */ | |
1487 | /* counter is enabled and not filtered */ | |
1488 | pmu_counter_enabled(env, i) && | |
1489 | /* counter is SW_INCR */ | |
1490 | (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { | |
1491 | pmevcntr_op_start(env, i); | |
f4efb4b2 AL |
1492 | |
1493 | /* | |
1494 | * Detect if this write causes an overflow since we can't predict | |
1495 | * PMSWINC overflows like we can for other events | |
1496 | */ | |
47b385da PM |
1497 | new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; |
1498 | ||
1499 | overflow_mask = pmevcntr_is_64_bit(env, i) ? | |
1500 | 1ULL << 63 : 1ULL << 31; | |
f4efb4b2 | 1501 | |
47b385da | 1502 | if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & overflow_mask) { |
f4efb4b2 AL |
1503 | env->cp15.c9_pmovsr |= (1 << i); |
1504 | pmu_update_irq(env); | |
1505 | } | |
1506 | ||
1507 | env->cp15.c14_pmevcntr[i] = new_pmswinc; | |
1508 | ||
0d4bfd7d AL |
1509 | pmevcntr_op_finish(env, i); |
1510 | } | |
1511 | } | |
1512 | } | |
1513 | ||
7c2cb42b AF |
1514 | static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1515 | { | |
5d05b9d4 AL |
1516 | uint64_t ret; |
1517 | pmccntr_op_start(env); | |
1518 | ret = env->cp15.c15_ccnt; | |
1519 | pmccntr_op_finish(env); | |
1520 | return ret; | |
7c2cb42b AF |
1521 | } |
1522 | ||
6b040780 WH |
1523 | static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1524 | uint64_t value) | |
1525 | { | |
9b37a28c FR |
1526 | /* |
1527 | * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and | |
6b040780 WH |
1528 | * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the |
1529 | * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are | |
1530 | * accessed. | |
1531 | */ | |
1532 | env->cp15.c9_pmselr = value & 0x1f; | |
1533 | } | |
1534 | ||
7c2cb42b AF |
1535 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1536 | uint64_t value) | |
1537 | { | |
5d05b9d4 AL |
1538 | pmccntr_op_start(env); |
1539 | env->cp15.c15_ccnt = value; | |
1540 | pmccntr_op_finish(env); | |
200ac0ef | 1541 | } |
421c7ebd PC |
1542 | |
1543 | static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1544 | uint64_t value) | |
1545 | { | |
1546 | uint64_t cur_val = pmccntr_read(env, NULL); | |
1547 | ||
1548 | pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); | |
1549 | } | |
1550 | ||
0614601c AF |
1551 | static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1552 | uint64_t value) | |
1553 | { | |
5d05b9d4 | 1554 | pmccntr_op_start(env); |
4b8afa1f AL |
1555 | env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0; |
1556 | pmccntr_op_finish(env); | |
1557 | } | |
1558 | ||
1559 | static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1560 | uint64_t value) | |
1561 | { | |
1562 | pmccntr_op_start(env); | |
1563 | /* M is not accessible from AArch32 */ | |
1564 | env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | | |
1565 | (value & PMCCFILTR); | |
5d05b9d4 | 1566 | pmccntr_op_finish(env); |
0614601c AF |
1567 | } |
1568 | ||
4b8afa1f AL |
1569 | static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri) |
1570 | { | |
1571 | /* M is not visible in AArch32 */ | |
1572 | return env->cp15.pmccfiltr_el0 & PMCCFILTR; | |
1573 | } | |
1574 | ||
c4241c7d | 1575 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1576 | uint64_t value) |
1577 | { | |
01765386 | 1578 | pmu_op_start(env); |
7ece99b1 | 1579 | value &= pmu_counter_mask(env); |
200ac0ef | 1580 | env->cp15.c9_pmcnten |= value; |
01765386 | 1581 | pmu_op_finish(env); |
200ac0ef PM |
1582 | } |
1583 | ||
c4241c7d PM |
1584 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1585 | uint64_t value) | |
200ac0ef | 1586 | { |
01765386 | 1587 | pmu_op_start(env); |
7ece99b1 | 1588 | value &= pmu_counter_mask(env); |
200ac0ef | 1589 | env->cp15.c9_pmcnten &= ~value; |
01765386 | 1590 | pmu_op_finish(env); |
200ac0ef PM |
1591 | } |
1592 | ||
c4241c7d PM |
1593 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1594 | uint64_t value) | |
200ac0ef | 1595 | { |
599b71e2 | 1596 | value &= pmu_counter_mask(env); |
200ac0ef | 1597 | env->cp15.c9_pmovsr &= ~value; |
f4efb4b2 | 1598 | pmu_update_irq(env); |
200ac0ef PM |
1599 | } |
1600 | ||
327dd510 AL |
1601 | static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1602 | uint64_t value) | |
1603 | { | |
1604 | value &= pmu_counter_mask(env); | |
1605 | env->cp15.c9_pmovsr |= value; | |
f4efb4b2 | 1606 | pmu_update_irq(env); |
327dd510 AL |
1607 | } |
1608 | ||
5ecdd3e4 AL |
1609 | static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1610 | uint64_t value, const uint8_t counter) | |
200ac0ef | 1611 | { |
5ecdd3e4 AL |
1612 | if (counter == 31) { |
1613 | pmccfiltr_write(env, ri, value); | |
1614 | } else if (counter < pmu_num_counters(env)) { | |
1615 | pmevcntr_op_start(env, counter); | |
1616 | ||
1617 | /* | |
1618 | * If this counter's event type is changing, store the current | |
1619 | * underlying count for the new type in c14_pmevcntr_delta[counter] so | |
1620 | * pmevcntr_op_finish has the correct baseline when it converts back to | |
1621 | * a delta. | |
1622 | */ | |
1623 | uint16_t old_event = env->cp15.c14_pmevtyper[counter] & | |
1624 | PMXEVTYPER_EVTCOUNT; | |
1625 | uint16_t new_event = value & PMXEVTYPER_EVTCOUNT; | |
1626 | if (old_event != new_event) { | |
1627 | uint64_t count = 0; | |
1628 | if (event_supported(new_event)) { | |
1629 | uint16_t event_idx = supported_event_map[new_event]; | |
1630 | count = pm_events[event_idx].get_count(env); | |
1631 | } | |
1632 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1633 | } | |
1634 | ||
1635 | env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK; | |
1636 | pmevcntr_op_finish(env, counter); | |
1637 | } | |
9b37a28c FR |
1638 | /* |
1639 | * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when | |
fdb86656 WH |
1640 | * PMSELR value is equal to or greater than the number of implemented |
1641 | * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. | |
1642 | */ | |
5ecdd3e4 AL |
1643 | } |
1644 | ||
1645 | static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1646 | const uint8_t counter) | |
1647 | { | |
1648 | if (counter == 31) { | |
1649 | return env->cp15.pmccfiltr_el0; | |
1650 | } else if (counter < pmu_num_counters(env)) { | |
1651 | return env->cp15.c14_pmevtyper[counter]; | |
1652 | } else { | |
1653 | /* | |
1654 | * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER | |
1655 | * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). | |
1656 | */ | |
1657 | return 0; | |
1658 | } | |
1659 | } | |
1660 | ||
1661 | static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, | |
1662 | uint64_t value) | |
1663 | { | |
1664 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1665 | pmevtyper_write(env, ri, value, counter); | |
1666 | } | |
1667 | ||
1668 | static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1669 | uint64_t value) | |
1670 | { | |
1671 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1672 | env->cp15.c14_pmevtyper[counter] = value; | |
1673 | ||
1674 | /* | |
1675 | * pmevtyper_rawwrite is called between a pair of pmu_op_start and | |
1676 | * pmu_op_finish calls when loading saved state for a migration. Because | |
1677 | * we're potentially updating the type of event here, the value written to | |
673d8215 | 1678 | * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a |
5ecdd3e4 AL |
1679 | * different counter type. Therefore, we need to set this value to the |
1680 | * current count for the counter type we're writing so that pmu_op_finish | |
1681 | * has the correct count for its calculation. | |
1682 | */ | |
1683 | uint16_t event = value & PMXEVTYPER_EVTCOUNT; | |
1684 | if (event_supported(event)) { | |
1685 | uint16_t event_idx = supported_event_map[event]; | |
1686 | env->cp15.c14_pmevcntr_delta[counter] = | |
1687 | pm_events[event_idx].get_count(env); | |
fdb86656 WH |
1688 | } |
1689 | } | |
1690 | ||
5ecdd3e4 AL |
1691 | static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) |
1692 | { | |
1693 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1694 | return pmevtyper_read(env, ri, counter); | |
1695 | } | |
1696 | ||
1697 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1698 | uint64_t value) | |
1699 | { | |
1700 | pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1701 | } | |
1702 | ||
fdb86656 WH |
1703 | static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1704 | { | |
5ecdd3e4 AL |
1705 | return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); |
1706 | } | |
1707 | ||
1708 | static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1709 | uint64_t value, uint8_t counter) | |
1710 | { | |
47b385da PM |
1711 | if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { |
1712 | /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */ | |
1713 | value &= MAKE_64BIT_MASK(0, 32); | |
1714 | } | |
5ecdd3e4 AL |
1715 | if (counter < pmu_num_counters(env)) { |
1716 | pmevcntr_op_start(env, counter); | |
1717 | env->cp15.c14_pmevcntr[counter] = value; | |
1718 | pmevcntr_op_finish(env, counter); | |
1719 | } | |
1720 | /* | |
1721 | * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR | |
1722 | * are CONSTRAINED UNPREDICTABLE. | |
fdb86656 | 1723 | */ |
5ecdd3e4 AL |
1724 | } |
1725 | ||
1726 | static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1727 | uint8_t counter) | |
1728 | { | |
1729 | if (counter < pmu_num_counters(env)) { | |
1730 | uint64_t ret; | |
1731 | pmevcntr_op_start(env, counter); | |
1732 | ret = env->cp15.c14_pmevcntr[counter]; | |
1733 | pmevcntr_op_finish(env, counter); | |
47b385da PM |
1734 | if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { |
1735 | /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */ | |
1736 | ret &= MAKE_64BIT_MASK(0, 32); | |
1737 | } | |
5ecdd3e4 | 1738 | return ret; |
fdb86656 | 1739 | } else { |
9b37a28c FR |
1740 | /* |
1741 | * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR | |
1742 | * are CONSTRAINED UNPREDICTABLE. | |
1743 | */ | |
fdb86656 WH |
1744 | return 0; |
1745 | } | |
200ac0ef PM |
1746 | } |
1747 | ||
5ecdd3e4 AL |
1748 | static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, |
1749 | uint64_t value) | |
1750 | { | |
1751 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1752 | pmevcntr_write(env, ri, value, counter); | |
1753 | } | |
1754 | ||
1755 | static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) | |
1756 | { | |
1757 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1758 | return pmevcntr_read(env, ri, counter); | |
1759 | } | |
1760 | ||
1761 | static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1762 | uint64_t value) | |
1763 | { | |
1764 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1765 | assert(counter < pmu_num_counters(env)); | |
1766 | env->cp15.c14_pmevcntr[counter] = value; | |
1767 | pmevcntr_write(env, ri, value, counter); | |
1768 | } | |
1769 | ||
1770 | static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri) | |
1771 | { | |
1772 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1773 | assert(counter < pmu_num_counters(env)); | |
1774 | return env->cp15.c14_pmevcntr[counter]; | |
1775 | } | |
1776 | ||
1777 | static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1778 | uint64_t value) | |
1779 | { | |
1780 | pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1781 | } | |
1782 | ||
1783 | static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1784 | { | |
1785 | return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); | |
1786 | } | |
1787 | ||
c4241c7d | 1788 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1789 | uint64_t value) |
1790 | { | |
6ecd0b6b AB |
1791 | if (arm_feature(env, ARM_FEATURE_V8)) { |
1792 | env->cp15.c9_pmuserenr = value & 0xf; | |
1793 | } else { | |
1794 | env->cp15.c9_pmuserenr = value & 1; | |
1795 | } | |
200ac0ef PM |
1796 | } |
1797 | ||
c4241c7d PM |
1798 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1799 | uint64_t value) | |
200ac0ef PM |
1800 | { |
1801 | /* We have no event counters so only the C bit can be changed */ | |
7ece99b1 | 1802 | value &= pmu_counter_mask(env); |
200ac0ef | 1803 | env->cp15.c9_pminten |= value; |
f4efb4b2 | 1804 | pmu_update_irq(env); |
200ac0ef PM |
1805 | } |
1806 | ||
c4241c7d PM |
1807 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1808 | uint64_t value) | |
200ac0ef | 1809 | { |
7ece99b1 | 1810 | value &= pmu_counter_mask(env); |
200ac0ef | 1811 | env->cp15.c9_pminten &= ~value; |
f4efb4b2 | 1812 | pmu_update_irq(env); |
200ac0ef PM |
1813 | } |
1814 | ||
c4241c7d PM |
1815 | static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1816 | uint64_t value) | |
8641136c | 1817 | { |
9b37a28c FR |
1818 | /* |
1819 | * Note that even though the AArch64 view of this register has bits | |
a505d7fe PM |
1820 | * [10:0] all RES0 we can only mask the bottom 5, to comply with the |
1821 | * architectural requirements for bits which are RES0 only in some | |
1822 | * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 | |
1823 | * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) | |
1824 | */ | |
855ea66d | 1825 | raw_write(env, ri, value & ~0x1FULL); |
8641136c NR |
1826 | } |
1827 | ||
64e0e2de EI |
1828 | static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
1829 | { | |
ea22747c | 1830 | /* Begin with base v8.0 state. */ |
06f2adcc | 1831 | uint64_t valid_mask = 0x3fff; |
2fc0cc0e | 1832 | ARMCPU *cpu = env_archcpu(env); |
d902ae75 | 1833 | uint64_t changed; |
ea22747c | 1834 | |
bfe43e3d RH |
1835 | /* |
1836 | * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always | |
1837 | * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64. | |
1838 | * Instead, choose the format based on the mode of EL3. | |
1839 | */ | |
1840 | if (arm_el_is_aa64(env, 3)) { | |
1841 | value |= SCR_FW | SCR_AW; /* RES1 */ | |
1842 | valid_mask &= ~SCR_NET; /* RES0 */ | |
252e8c69 | 1843 | |
6bcbb07a RH |
1844 | if (!cpu_isar_feature(aa64_aa32_el1, cpu) && |
1845 | !cpu_isar_feature(aa64_aa32_el2, cpu)) { | |
1846 | value |= SCR_RW; /* RAO/WI */ | |
1847 | } | |
da3d8b13 RH |
1848 | if (cpu_isar_feature(aa64_ras, cpu)) { |
1849 | valid_mask |= SCR_TERR; | |
1850 | } | |
252e8c69 RH |
1851 | if (cpu_isar_feature(aa64_lor, cpu)) { |
1852 | valid_mask |= SCR_TLOR; | |
1853 | } | |
1854 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
1855 | valid_mask |= SCR_API | SCR_APK; | |
1856 | } | |
926c1b97 RDC |
1857 | if (cpu_isar_feature(aa64_sel2, cpu)) { |
1858 | valid_mask |= SCR_EEL2; | |
87bfbfe7 RH |
1859 | } else if (cpu_isar_feature(aa64_rme, cpu)) { |
1860 | /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */ | |
1861 | value |= SCR_NS; | |
926c1b97 | 1862 | } |
8ddb300b RH |
1863 | if (cpu_isar_feature(aa64_mte, cpu)) { |
1864 | valid_mask |= SCR_ATA; | |
1865 | } | |
7cb1e618 RH |
1866 | if (cpu_isar_feature(aa64_scxtnum, cpu)) { |
1867 | valid_mask |= SCR_ENSCXT; | |
1868 | } | |
7ac61020 PM |
1869 | if (cpu_isar_feature(aa64_doublefault, cpu)) { |
1870 | valid_mask |= SCR_EASE | SCR_NMEA; | |
1871 | } | |
06f2adcc JF |
1872 | if (cpu_isar_feature(aa64_sme, cpu)) { |
1873 | valid_mask |= SCR_ENTP2; | |
1874 | } | |
08899b5c EI |
1875 | if (cpu_isar_feature(aa64_hcx, cpu)) { |
1876 | valid_mask |= SCR_HXEN; | |
1877 | } | |
15126d9c PM |
1878 | if (cpu_isar_feature(aa64_fgt, cpu)) { |
1879 | valid_mask |= SCR_FGTEN; | |
1880 | } | |
aa3cc42c RH |
1881 | if (cpu_isar_feature(aa64_rme, cpu)) { |
1882 | valid_mask |= SCR_NSE | SCR_GPF; | |
1883 | } | |
ea22747c RH |
1884 | } else { |
1885 | valid_mask &= ~(SCR_RW | SCR_ST); | |
da3d8b13 RH |
1886 | if (cpu_isar_feature(aa32_ras, cpu)) { |
1887 | valid_mask |= SCR_TERR; | |
1888 | } | |
ea22747c | 1889 | } |
64e0e2de EI |
1890 | |
1891 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | |
1892 | valid_mask &= ~SCR_HCE; | |
1893 | ||
9b37a28c FR |
1894 | /* |
1895 | * On ARMv7, SMD (or SCD as it is called in v7) is only | |
64e0e2de EI |
1896 | * supported if EL2 exists. The bit is UNK/SBZP when |
1897 | * EL2 is unavailable. In QEMU ARMv7, we force it to always zero | |
1898 | * when EL2 is unavailable. | |
4eb27640 | 1899 | * On ARMv8, this bit is always available. |
64e0e2de | 1900 | */ |
4eb27640 GB |
1901 | if (arm_feature(env, ARM_FEATURE_V7) && |
1902 | !arm_feature(env, ARM_FEATURE_V8)) { | |
64e0e2de EI |
1903 | valid_mask &= ~SCR_SMD; |
1904 | } | |
1905 | } | |
1906 | ||
1907 | /* Clear all-context RES0 bits. */ | |
1908 | value &= valid_mask; | |
d902ae75 RH |
1909 | changed = env->cp15.scr_el3 ^ value; |
1910 | env->cp15.scr_el3 = value; | |
1911 | ||
1912 | /* | |
aa3cc42c | 1913 | * If SCR_EL3.{NS,NSE} changes, i.e. change of security state, |
d902ae75 RH |
1914 | * we must invalidate all TLBs below EL3. |
1915 | */ | |
aa3cc42c | 1916 | if (changed & (SCR_NS | SCR_NSE)) { |
d902ae75 RH |
1917 | tlb_flush_by_mmuidx(env_cpu(env), (ARMMMUIdxBit_E10_0 | |
1918 | ARMMMUIdxBit_E20_0 | | |
1919 | ARMMMUIdxBit_E10_1 | | |
1920 | ARMMMUIdxBit_E20_2 | | |
1921 | ARMMMUIdxBit_E10_1_PAN | | |
1922 | ARMMMUIdxBit_E20_2_PAN | | |
1923 | ARMMMUIdxBit_E2)); | |
1924 | } | |
64e0e2de EI |
1925 | } |
1926 | ||
10d0ef3e MN |
1927 | static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1928 | { | |
1929 | /* | |
1930 | * scr_write will set the RES1 bits on an AArch64-only CPU. | |
1931 | * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise. | |
1932 | */ | |
1933 | scr_write(env, ri, 0); | |
1934 | } | |
1935 | ||
e2ce5fcd PM |
1936 | static CPAccessResult access_tid4(CPUARMState *env, |
1937 | const ARMCPRegInfo *ri, | |
1938 | bool isread) | |
630fcd4d | 1939 | { |
e2ce5fcd PM |
1940 | if (arm_current_el(env) == 1 && |
1941 | (arm_hcr_el2_eff(env) & (HCR_TID2 | HCR_TID4))) { | |
630fcd4d MZ |
1942 | return CP_ACCESS_TRAP_EL2; |
1943 | } | |
1944 | ||
1945 | return CP_ACCESS_OK; | |
1946 | } | |
1947 | ||
c4241c7d | 1948 | static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
776d4e5c | 1949 | { |
2fc0cc0e | 1950 | ARMCPU *cpu = env_archcpu(env); |
b85a1fd6 | 1951 | |
9b37a28c FR |
1952 | /* |
1953 | * Acquire the CSSELR index from the bank corresponding to the CCSIDR | |
b85a1fd6 FA |
1954 | * bank |
1955 | */ | |
1956 | uint32_t index = A32_BANKED_REG_GET(env, csselr, | |
1957 | ri->secure & ARM_CP_SECSTATE_S); | |
1958 | ||
1959 | return cpu->ccsidr[index]; | |
776d4e5c PM |
1960 | } |
1961 | ||
c4241c7d PM |
1962 | static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1963 | uint64_t value) | |
776d4e5c | 1964 | { |
8d5c773e | 1965 | raw_write(env, ri, value & 0xf); |
776d4e5c PM |
1966 | } |
1967 | ||
1090b9c6 PM |
1968 | static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1969 | { | |
29a0af61 | 1970 | CPUState *cs = env_cpu(env); |
cc974d5c RDC |
1971 | bool el1 = arm_current_el(env) == 1; |
1972 | uint64_t hcr_el2 = el1 ? arm_hcr_el2_eff(env) : 0; | |
1090b9c6 PM |
1973 | uint64_t ret = 0; |
1974 | ||
cc974d5c | 1975 | if (hcr_el2 & HCR_IMO) { |
636540e9 PM |
1976 | if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { |
1977 | ret |= CPSR_I; | |
1978 | } | |
1979 | } else { | |
1980 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { | |
1981 | ret |= CPSR_I; | |
1982 | } | |
1090b9c6 | 1983 | } |
636540e9 | 1984 | |
cc974d5c | 1985 | if (hcr_el2 & HCR_FMO) { |
636540e9 PM |
1986 | if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { |
1987 | ret |= CPSR_F; | |
1988 | } | |
1989 | } else { | |
1990 | if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { | |
1991 | ret |= CPSR_F; | |
1992 | } | |
1090b9c6 | 1993 | } |
636540e9 | 1994 | |
3c29632f RH |
1995 | if (hcr_el2 & HCR_AMO) { |
1996 | if (cs->interrupt_request & CPU_INTERRUPT_VSERR) { | |
1997 | ret |= CPSR_A; | |
1998 | } | |
1999 | } | |
2000 | ||
1090b9c6 PM |
2001 | return ret; |
2002 | } | |
2003 | ||
93fbc983 MZ |
2004 | static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInfo *ri, |
2005 | bool isread) | |
2006 | { | |
2007 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID1)) { | |
2008 | return CP_ACCESS_TRAP_EL2; | |
2009 | } | |
2010 | ||
2011 | return CP_ACCESS_OK; | |
2012 | } | |
2013 | ||
2014 | static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInfo *ri, | |
2015 | bool isread) | |
2016 | { | |
2017 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
2018 | return access_aa64_tid1(env, ri, isread); | |
2019 | } | |
2020 | ||
2021 | return CP_ACCESS_OK; | |
2022 | } | |
2023 | ||
e9aa6c21 | 2024 | static const ARMCPRegInfo v7_cp_reginfo[] = { |
7d57f408 PM |
2025 | /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ |
2026 | { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
2027 | .access = PL1_W, .type = ARM_CP_NOP }, | |
9b37a28c FR |
2028 | /* |
2029 | * Performance monitors are implementation defined in v7, | |
200ac0ef | 2030 | * but with an ARM recommended set of registers, which we |
ac689a2e | 2031 | * follow. |
200ac0ef PM |
2032 | * |
2033 | * Performance registers fall into three categories: | |
2034 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) | |
2035 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) | |
2036 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) | |
2037 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW | |
2038 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. | |
2039 | */ | |
2040 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, | |
7f4fbfb5 | 2041 | .access = PL0_RW, .type = ARM_CP_ALIAS | ARM_CP_IO, |
8521466b | 2042 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), |
fcd25206 PM |
2043 | .writefn = pmcntenset_write, |
2044 | .accessfn = pmreg_access, | |
dc780233 | 2045 | .fgt = FGT_PMCNTEN, |
fcd25206 | 2046 | .raw_writefn = raw_write }, |
7f4fbfb5 | 2047 | { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO, |
8521466b AF |
2048 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, |
2049 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 2050 | .fgt = FGT_PMCNTEN, |
8521466b AF |
2051 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, |
2052 | .writefn = pmcntenset_write, .raw_writefn = raw_write }, | |
200ac0ef | 2053 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
8521466b AF |
2054 | .access = PL0_RW, |
2055 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 | 2056 | .accessfn = pmreg_access, |
dc780233 | 2057 | .fgt = FGT_PMCNTEN, |
fcd25206 | 2058 | .writefn = pmcntenclr_write, |
7f4fbfb5 | 2059 | .type = ARM_CP_ALIAS | ARM_CP_IO }, |
8521466b AF |
2060 | { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, |
2061 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, | |
2062 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 2063 | .fgt = FGT_PMCNTEN, |
7f4fbfb5 | 2064 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
8521466b AF |
2065 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), |
2066 | .writefn = pmcntenclr_write }, | |
200ac0ef | 2067 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
f4efb4b2 | 2068 | .access = PL0_RW, .type = ARM_CP_IO, |
e4e91a21 | 2069 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
fcd25206 | 2070 | .accessfn = pmreg_access, |
dc780233 | 2071 | .fgt = FGT_PMOVS, |
fcd25206 PM |
2072 | .writefn = pmovsr_write, |
2073 | .raw_writefn = raw_write }, | |
978364f1 AF |
2074 | { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, |
2075 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, | |
2076 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 2077 | .fgt = FGT_PMOVS, |
f4efb4b2 | 2078 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
978364f1 AF |
2079 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
2080 | .writefn = pmovsr_write, | |
2081 | .raw_writefn = raw_write }, | |
200ac0ef | 2082 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
f4efb4b2 | 2083 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
dc780233 | 2084 | .fgt = FGT_PMSWINC_EL0, |
f4efb4b2 | 2085 | .type = ARM_CP_NO_RAW | ARM_CP_IO, |
0d4bfd7d AL |
2086 | .writefn = pmswinc_write }, |
2087 | { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64, | |
2088 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4, | |
f4efb4b2 | 2089 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
dc780233 | 2090 | .fgt = FGT_PMSWINC_EL0, |
f4efb4b2 | 2091 | .type = ARM_CP_NO_RAW | ARM_CP_IO, |
0d4bfd7d | 2092 | .writefn = pmswinc_write }, |
6b040780 WH |
2093 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, |
2094 | .access = PL0_RW, .type = ARM_CP_ALIAS, | |
dc780233 | 2095 | .fgt = FGT_PMSELR_EL0, |
6b040780 | 2096 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), |
6ecd0b6b | 2097 | .accessfn = pmreg_access_selr, .writefn = pmselr_write, |
6b040780 WH |
2098 | .raw_writefn = raw_write}, |
2099 | { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, | |
2100 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, | |
6ecd0b6b | 2101 | .access = PL0_RW, .accessfn = pmreg_access_selr, |
dc780233 | 2102 | .fgt = FGT_PMSELR_EL0, |
6b040780 WH |
2103 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), |
2104 | .writefn = pmselr_write, .raw_writefn = raw_write, }, | |
200ac0ef | 2105 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
169c8938 | 2106 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO, |
dc780233 | 2107 | .fgt = FGT_PMCCNTR_EL0, |
421c7ebd | 2108 | .readfn = pmccntr_read, .writefn = pmccntr_write32, |
6ecd0b6b | 2109 | .accessfn = pmreg_access_ccntr }, |
8521466b AF |
2110 | { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, |
2111 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, | |
6ecd0b6b | 2112 | .access = PL0_RW, .accessfn = pmreg_access_ccntr, |
dc780233 | 2113 | .fgt = FGT_PMCCNTR_EL0, |
8521466b | 2114 | .type = ARM_CP_IO, |
980ebe87 AL |
2115 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt), |
2116 | .readfn = pmccntr_read, .writefn = pmccntr_write, | |
2117 | .raw_readfn = raw_read, .raw_writefn = raw_write, }, | |
4b8afa1f AL |
2118 | { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7, |
2119 | .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32, | |
2120 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 2121 | .fgt = FGT_PMCCFILTR_EL0, |
4b8afa1f AL |
2122 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
2123 | .resetvalue = 0, }, | |
8521466b AF |
2124 | { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, |
2125 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, | |
980ebe87 | 2126 | .writefn = pmccfiltr_write, .raw_writefn = raw_write, |
8521466b | 2127 | .access = PL0_RW, .accessfn = pmreg_access, |
dc780233 | 2128 | .fgt = FGT_PMCCFILTR_EL0, |
8521466b AF |
2129 | .type = ARM_CP_IO, |
2130 | .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), | |
2131 | .resetvalue = 0, }, | |
200ac0ef | 2132 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
5ecdd3e4 AL |
2133 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
2134 | .accessfn = pmreg_access, | |
dc780233 | 2135 | .fgt = FGT_PMEVTYPERN_EL0, |
fdb86656 WH |
2136 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
2137 | { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, | |
2138 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, | |
5ecdd3e4 AL |
2139 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
2140 | .accessfn = pmreg_access, | |
dc780233 | 2141 | .fgt = FGT_PMEVTYPERN_EL0, |
fdb86656 | 2142 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
200ac0ef | 2143 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
5ecdd3e4 AL |
2144 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
2145 | .accessfn = pmreg_access_xevcntr, | |
dc780233 | 2146 | .fgt = FGT_PMEVCNTRN_EL0, |
5ecdd3e4 AL |
2147 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, |
2148 | { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64, | |
2149 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2, | |
2150 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
2151 | .accessfn = pmreg_access_xevcntr, | |
dc780233 | 2152 | .fgt = FGT_PMEVCNTRN_EL0, |
5ecdd3e4 | 2153 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, |
200ac0ef | 2154 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
1fce1ba9 | 2155 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, |
e4e91a21 | 2156 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr), |
200ac0ef | 2157 | .resetvalue = 0, |
d4e6df63 | 2158 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
8a83ffc2 AF |
2159 | { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, |
2160 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, | |
1fce1ba9 | 2161 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, |
8a83ffc2 AF |
2162 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), |
2163 | .resetvalue = 0, | |
2164 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, | |
200ac0ef | 2165 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
1fce1ba9 | 2166 | .access = PL1_RW, .accessfn = access_tpm, |
dc780233 | 2167 | .fgt = FGT_PMINTEN, |
b7d793ad | 2168 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
e6ec5457 | 2169 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), |
200ac0ef | 2170 | .resetvalue = 0, |
d4e6df63 | 2171 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
e6ec5457 WH |
2172 | { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, |
2173 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, | |
2174 | .access = PL1_RW, .accessfn = access_tpm, | |
dc780233 | 2175 | .fgt = FGT_PMINTEN, |
e6ec5457 WH |
2176 | .type = ARM_CP_IO, |
2177 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
2178 | .writefn = pmintenset_write, .raw_writefn = raw_write, | |
2179 | .resetvalue = 0x0 }, | |
200ac0ef | 2180 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
fc5f6856 | 2181 | .access = PL1_RW, .accessfn = access_tpm, |
dc780233 | 2182 | .fgt = FGT_PMINTEN, |
887c0f15 | 2183 | .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, |
200ac0ef | 2184 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
b061a82b | 2185 | .writefn = pmintenclr_write, }, |
978364f1 AF |
2186 | { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, |
2187 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, | |
fc5f6856 | 2188 | .access = PL1_RW, .accessfn = access_tpm, |
dc780233 | 2189 | .fgt = FGT_PMINTEN, |
887c0f15 | 2190 | .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, |
978364f1 AF |
2191 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
2192 | .writefn = pmintenclr_write }, | |
7da845b0 PM |
2193 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, |
2194 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | |
630fcd4d | 2195 | .access = PL1_R, |
e2ce5fcd | 2196 | .accessfn = access_tid4, |
158c276c | 2197 | .fgt = FGT_CCSIDR_EL1, |
630fcd4d | 2198 | .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, |
7da845b0 PM |
2199 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, |
2200 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | |
630fcd4d | 2201 | .access = PL1_RW, |
e2ce5fcd | 2202 | .accessfn = access_tid4, |
b19ed03c | 2203 | .fgt = FGT_CSSELR_EL1, |
630fcd4d | 2204 | .writefn = csselr_write, .resetvalue = 0, |
b85a1fd6 FA |
2205 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), |
2206 | offsetof(CPUARMState, cp15.csselr_ns) } }, | |
9b37a28c FR |
2207 | /* |
2208 | * Auxiliary ID register: this actually has an IMPDEF value but for now | |
776d4e5c PM |
2209 | * just RAZ for all cores: |
2210 | */ | |
0ff644a7 PM |
2211 | { .name = "AIDR", .state = ARM_CP_STATE_BOTH, |
2212 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, | |
93fbc983 MZ |
2213 | .access = PL1_R, .type = ARM_CP_CONST, |
2214 | .accessfn = access_aa64_tid1, | |
158c276c | 2215 | .fgt = FGT_AIDR_EL1, |
93fbc983 | 2216 | .resetvalue = 0 }, |
9b37a28c FR |
2217 | /* |
2218 | * Auxiliary fault status registers: these also are IMPDEF, and we | |
f32cdad5 PM |
2219 | * choose to RAZ/WI for all cores. |
2220 | */ | |
2221 | { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, | |
2222 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, | |
84929218 | 2223 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
158c276c | 2224 | .fgt = FGT_AFSR0_EL1, |
84929218 | 2225 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
f32cdad5 PM |
2226 | { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, |
2227 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, | |
84929218 | 2228 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
158c276c | 2229 | .fgt = FGT_AFSR1_EL1, |
84929218 | 2230 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
9b37a28c FR |
2231 | /* |
2232 | * MAIR can just read-as-written because we don't implement caches | |
b0fe2427 PM |
2233 | * and so don't need to care about memory attributes. |
2234 | */ | |
2235 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | |
2236 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | |
84929218 | 2237 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
67dd8030 | 2238 | .fgt = FGT_MAIR_EL1, |
84929218 | 2239 | .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), |
b0fe2427 | 2240 | .resetvalue = 0 }, |
4cfb8ad8 PM |
2241 | { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, |
2242 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, | |
2243 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), | |
2244 | .resetvalue = 0 }, | |
9b37a28c FR |
2245 | /* |
2246 | * For non-long-descriptor page tables these are PRRR and NMRR; | |
b0fe2427 | 2247 | * regardless they still act as reads-as-written for QEMU. |
b0fe2427 | 2248 | */ |
9b37a28c FR |
2249 | /* |
2250 | * MAIR0/1 are defined separately from their 64-bit counterpart which | |
be693c87 GB |
2251 | * allows them to assign the correct fieldoffset based on the endianness |
2252 | * handled in the field definitions. | |
2253 | */ | |
a903c449 | 2254 | { .name = "MAIR0", .state = ARM_CP_STATE_AA32, |
84929218 RH |
2255 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, |
2256 | .access = PL1_RW, .accessfn = access_tvm_trvm, | |
be693c87 GB |
2257 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), |
2258 | offsetof(CPUARMState, cp15.mair0_ns) }, | |
b0fe2427 | 2259 | .resetfn = arm_cp_reset_ignore }, |
a903c449 | 2260 | { .name = "MAIR1", .state = ARM_CP_STATE_AA32, |
84929218 RH |
2261 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, |
2262 | .access = PL1_RW, .accessfn = access_tvm_trvm, | |
be693c87 GB |
2263 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), |
2264 | offsetof(CPUARMState, cp15.mair1_ns) }, | |
b0fe2427 | 2265 | .resetfn = arm_cp_reset_ignore }, |
1090b9c6 PM |
2266 | { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, |
2267 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, | |
b19ed03c | 2268 | .fgt = FGT_ISR_EL1, |
7a0e58fa | 2269 | .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, |
995939a6 PM |
2270 | /* 32 bit ITLB invalidates */ |
2271 | { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, | |
30881b73 RH |
2272 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2273 | .writefn = tlbiall_write }, | |
995939a6 | 2274 | { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, |
30881b73 RH |
2275 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2276 | .writefn = tlbimva_write }, | |
995939a6 | 2277 | { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, |
30881b73 RH |
2278 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2279 | .writefn = tlbiasid_write }, | |
995939a6 PM |
2280 | /* 32 bit DTLB invalidates */ |
2281 | { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, | |
30881b73 RH |
2282 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2283 | .writefn = tlbiall_write }, | |
995939a6 | 2284 | { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, |
30881b73 RH |
2285 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2286 | .writefn = tlbimva_write }, | |
995939a6 | 2287 | { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, |
30881b73 RH |
2288 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2289 | .writefn = tlbiasid_write }, | |
995939a6 PM |
2290 | /* 32 bit TLB invalidates */ |
2291 | { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | |
30881b73 RH |
2292 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2293 | .writefn = tlbiall_write }, | |
995939a6 | 2294 | { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
30881b73 RH |
2295 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2296 | .writefn = tlbimva_write }, | |
995939a6 | 2297 | { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
30881b73 RH |
2298 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2299 | .writefn = tlbiasid_write }, | |
995939a6 | 2300 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
30881b73 RH |
2301 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2302 | .writefn = tlbimvaa_write }, | |
995939a6 PM |
2303 | }; |
2304 | ||
2305 | static const ARMCPRegInfo v7mp_cp_reginfo[] = { | |
2306 | /* 32 bit TLB invalidates, Inner Shareable */ | |
2307 | { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | |
0f66d223 | 2308 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, |
30881b73 | 2309 | .writefn = tlbiall_is_write }, |
995939a6 | 2310 | { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
0f66d223 | 2311 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, |
30881b73 | 2312 | .writefn = tlbimva_is_write }, |
995939a6 | 2313 | { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
0f66d223 | 2314 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, |
fa439fc5 | 2315 | .writefn = tlbiasid_is_write }, |
995939a6 | 2316 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
0f66d223 | 2317 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, |
fa439fc5 | 2318 | .writefn = tlbimvaa_is_write }, |
e9aa6c21 PM |
2319 | }; |
2320 | ||
327dd510 AL |
2321 | static const ARMCPRegInfo pmovsset_cp_reginfo[] = { |
2322 | /* PMOVSSET is not implemented in v7 before v7ve */ | |
2323 | { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3, | |
2324 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 2325 | .fgt = FGT_PMOVS, |
f4efb4b2 | 2326 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
327dd510 AL |
2327 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
2328 | .writefn = pmovsset_write, | |
2329 | .raw_writefn = raw_write }, | |
2330 | { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64, | |
2331 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3, | |
2332 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 2333 | .fgt = FGT_PMOVS, |
f4efb4b2 | 2334 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
327dd510 AL |
2335 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
2336 | .writefn = pmovsset_write, | |
2337 | .raw_writefn = raw_write }, | |
327dd510 AL |
2338 | }; |
2339 | ||
c4241c7d PM |
2340 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2341 | uint64_t value) | |
c326b979 PM |
2342 | { |
2343 | value &= 1; | |
2344 | env->teecr = value; | |
c326b979 PM |
2345 | } |
2346 | ||
cc7613bf PM |
2347 | static CPAccessResult teecr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2348 | bool isread) | |
2349 | { | |
2350 | /* | |
2351 | * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE | |
2352 | * at all, so we don't need to check whether we're v8A. | |
2353 | */ | |
2354 | if (arm_current_el(env) < 2 && !arm_is_secure_below_el3(env) && | |
2355 | (env->cp15.hstr_el2 & HSTR_TTEE)) { | |
2356 | return CP_ACCESS_TRAP_EL2; | |
2357 | } | |
2358 | return CP_ACCESS_OK; | |
2359 | } | |
2360 | ||
3f208fd7 PM |
2361 | static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2362 | bool isread) | |
c326b979 | 2363 | { |
dcbff19b | 2364 | if (arm_current_el(env) == 0 && (env->teecr & 1)) { |
92611c00 | 2365 | return CP_ACCESS_TRAP; |
c326b979 | 2366 | } |
cc7613bf | 2367 | return teecr_access(env, ri, isread); |
c326b979 PM |
2368 | } |
2369 | ||
2370 | static const ARMCPRegInfo t2ee_cp_reginfo[] = { | |
2371 | { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, | |
2372 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), | |
2373 | .resetvalue = 0, | |
cc7613bf | 2374 | .writefn = teecr_write, .accessfn = teecr_access }, |
c326b979 PM |
2375 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, |
2376 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | |
92611c00 | 2377 | .accessfn = teehbr_access, .resetvalue = 0 }, |
c326b979 PM |
2378 | }; |
2379 | ||
4d31c596 | 2380 | static const ARMCPRegInfo v6k_cp_reginfo[] = { |
e4fe830b PM |
2381 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, |
2382 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | |
2383 | .access = PL0_RW, | |
67dd8030 | 2384 | .fgt = FGT_TPIDR_EL0, |
54bf36ed | 2385 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, |
4d31c596 PM |
2386 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
2387 | .access = PL0_RW, | |
67dd8030 | 2388 | .fgt = FGT_TPIDR_EL0, |
54bf36ed FA |
2389 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), |
2390 | offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, | |
e4fe830b PM |
2391 | .resetfn = arm_cp_reset_ignore }, |
2392 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | |
2393 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | |
04215eb1 | 2394 | .access = PL0_R | PL1_W, |
67dd8030 | 2395 | .fgt = FGT_TPIDRRO_EL0, |
54bf36ed FA |
2396 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), |
2397 | .resetvalue = 0}, | |
4d31c596 | 2398 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
04215eb1 | 2399 | .access = PL0_R | PL1_W, |
67dd8030 | 2400 | .fgt = FGT_TPIDRRO_EL0, |
54bf36ed FA |
2401 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), |
2402 | offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, | |
e4fe830b | 2403 | .resetfn = arm_cp_reset_ignore }, |
54bf36ed | 2404 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, |
e4fe830b | 2405 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, |
4d31c596 | 2406 | .access = PL1_RW, |
67dd8030 | 2407 | .fgt = FGT_TPIDR_EL1, |
54bf36ed FA |
2408 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, |
2409 | { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, | |
2410 | .access = PL1_RW, | |
2411 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), | |
2412 | offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, | |
2413 | .resetvalue = 0 }, | |
4d31c596 PM |
2414 | }; |
2415 | ||
55d284af PM |
2416 | #ifndef CONFIG_USER_ONLY |
2417 | ||
3f208fd7 PM |
2418 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2419 | bool isread) | |
00108f2d | 2420 | { |
9b37a28c FR |
2421 | /* |
2422 | * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. | |
75502672 PM |
2423 | * Writable only at the highest implemented exception level. |
2424 | */ | |
2425 | int el = arm_current_el(env); | |
5bc84371 RH |
2426 | uint64_t hcr; |
2427 | uint32_t cntkctl; | |
75502672 PM |
2428 | |
2429 | switch (el) { | |
2430 | case 0: | |
5bc84371 RH |
2431 | hcr = arm_hcr_el2_eff(env); |
2432 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2433 | cntkctl = env->cp15.cnthctl_el2; | |
2434 | } else { | |
2435 | cntkctl = env->cp15.c14_cntkctl; | |
2436 | } | |
2437 | if (!extract32(cntkctl, 0, 2)) { | |
75502672 PM |
2438 | return CP_ACCESS_TRAP; |
2439 | } | |
2440 | break; | |
2441 | case 1: | |
2442 | if (!isread && ri->state == ARM_CP_STATE_AA32 && | |
2443 | arm_is_secure_below_el3(env)) { | |
2444 | /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ | |
2445 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2446 | } | |
2447 | break; | |
2448 | case 2: | |
2449 | case 3: | |
2450 | break; | |
00108f2d | 2451 | } |
75502672 PM |
2452 | |
2453 | if (!isread && el < arm_highest_el(env)) { | |
2454 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2455 | } | |
2456 | ||
00108f2d PM |
2457 | return CP_ACCESS_OK; |
2458 | } | |
2459 | ||
3f208fd7 PM |
2460 | static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, |
2461 | bool isread) | |
00108f2d | 2462 | { |
0b6440af | 2463 | unsigned int cur_el = arm_current_el(env); |
e6ef0169 | 2464 | bool has_el2 = arm_is_el2_enabled(env); |
5bc84371 | 2465 | uint64_t hcr = arm_hcr_el2_eff(env); |
0b6440af | 2466 | |
5bc84371 RH |
2467 | switch (cur_el) { |
2468 | case 0: | |
2469 | /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */ | |
2470 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2471 | return (extract32(env->cp15.cnthctl_el2, timeridx, 1) | |
2472 | ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); | |
2473 | } | |
0b6440af | 2474 | |
5bc84371 RH |
2475 | /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */ |
2476 | if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) { | |
2477 | return CP_ACCESS_TRAP; | |
2478 | } | |
d01448c7 | 2479 | /* fall through */ |
5bc84371 RH |
2480 | case 1: |
2481 | /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */ | |
e6ef0169 | 2482 | if (has_el2 && timeridx == GTIMER_PHYS && |
5bc84371 RH |
2483 | (hcr & HCR_E2H |
2484 | ? !extract32(env->cp15.cnthctl_el2, 10, 1) | |
2485 | : !extract32(env->cp15.cnthctl_el2, 0, 1))) { | |
2486 | return CP_ACCESS_TRAP_EL2; | |
2487 | } | |
2488 | break; | |
0b6440af | 2489 | } |
00108f2d PM |
2490 | return CP_ACCESS_OK; |
2491 | } | |
2492 | ||
3f208fd7 PM |
2493 | static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, |
2494 | bool isread) | |
00108f2d | 2495 | { |
0b6440af | 2496 | unsigned int cur_el = arm_current_el(env); |
e6ef0169 | 2497 | bool has_el2 = arm_is_el2_enabled(env); |
5bc84371 | 2498 | uint64_t hcr = arm_hcr_el2_eff(env); |
0b6440af | 2499 | |
5bc84371 RH |
2500 | switch (cur_el) { |
2501 | case 0: | |
2502 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2503 | /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */ | |
2504 | return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1) | |
2505 | ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); | |
2506 | } | |
0b6440af | 2507 | |
5bc84371 RH |
2508 | /* |
2509 | * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from | |
2510 | * EL0 if EL0[PV]TEN is zero. | |
2511 | */ | |
2512 | if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { | |
2513 | return CP_ACCESS_TRAP; | |
2514 | } | |
2515 | /* fall through */ | |
2516 | ||
2517 | case 1: | |
e6ef0169 | 2518 | if (has_el2 && timeridx == GTIMER_PHYS) { |
5bc84371 RH |
2519 | if (hcr & HCR_E2H) { |
2520 | /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */ | |
2521 | if (!extract32(env->cp15.cnthctl_el2, 11, 1)) { | |
2522 | return CP_ACCESS_TRAP_EL2; | |
2523 | } | |
2524 | } else { | |
2525 | /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */ | |
2526 | if (!extract32(env->cp15.cnthctl_el2, 1, 1)) { | |
2527 | return CP_ACCESS_TRAP_EL2; | |
2528 | } | |
2529 | } | |
2530 | } | |
2531 | break; | |
0b6440af | 2532 | } |
00108f2d PM |
2533 | return CP_ACCESS_OK; |
2534 | } | |
2535 | ||
2536 | static CPAccessResult gt_pct_access(CPUARMState *env, | |
3f208fd7 PM |
2537 | const ARMCPRegInfo *ri, |
2538 | bool isread) | |
00108f2d | 2539 | { |
3f208fd7 | 2540 | return gt_counter_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2541 | } |
2542 | ||
2543 | static CPAccessResult gt_vct_access(CPUARMState *env, | |
3f208fd7 PM |
2544 | const ARMCPRegInfo *ri, |
2545 | bool isread) | |
00108f2d | 2546 | { |
3f208fd7 | 2547 | return gt_counter_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2548 | } |
2549 | ||
3f208fd7 PM |
2550 | static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2551 | bool isread) | |
00108f2d | 2552 | { |
3f208fd7 | 2553 | return gt_timer_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2554 | } |
2555 | ||
3f208fd7 PM |
2556 | static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2557 | bool isread) | |
00108f2d | 2558 | { |
3f208fd7 | 2559 | return gt_timer_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2560 | } |
2561 | ||
b4d3978c | 2562 | static CPAccessResult gt_stimer_access(CPUARMState *env, |
3f208fd7 PM |
2563 | const ARMCPRegInfo *ri, |
2564 | bool isread) | |
b4d3978c | 2565 | { |
9b37a28c FR |
2566 | /* |
2567 | * The AArch64 register view of the secure physical timer is | |
b4d3978c PM |
2568 | * always accessible from EL3, and configurably accessible from |
2569 | * Secure EL1. | |
2570 | */ | |
2571 | switch (arm_current_el(env)) { | |
2572 | case 1: | |
2573 | if (!arm_is_secure(env)) { | |
2574 | return CP_ACCESS_TRAP; | |
2575 | } | |
2576 | if (!(env->cp15.scr_el3 & SCR_ST)) { | |
2577 | return CP_ACCESS_TRAP_EL3; | |
2578 | } | |
2579 | return CP_ACCESS_OK; | |
2580 | case 0: | |
2581 | case 2: | |
2582 | return CP_ACCESS_TRAP; | |
2583 | case 3: | |
2584 | return CP_ACCESS_OK; | |
2585 | default: | |
2586 | g_assert_not_reached(); | |
2587 | } | |
2588 | } | |
2589 | ||
55d284af PM |
2590 | static uint64_t gt_get_countervalue(CPUARMState *env) |
2591 | { | |
7def8754 AJ |
2592 | ARMCPU *cpu = env_archcpu(env); |
2593 | ||
2594 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu); | |
55d284af PM |
2595 | } |
2596 | ||
f6fc36de JPB |
2597 | static void gt_update_irq(ARMCPU *cpu, int timeridx) |
2598 | { | |
2599 | CPUARMState *env = &cpu->env; | |
2600 | uint64_t cnthctl = env->cp15.cnthctl_el2; | |
2601 | ARMSecuritySpace ss = arm_security_space(env); | |
2602 | /* ISTATUS && !IMASK */ | |
2603 | int irqstate = (env->cp15.c14_timer[timeridx].ctl & 6) == 4; | |
2604 | ||
2605 | /* | |
2606 | * If bit CNTHCTL_EL2.CNT[VP]MASK is set, it overrides IMASK. | |
2607 | * It is RES0 in Secure and NonSecure state. | |
2608 | */ | |
2609 | if ((ss == ARMSS_Root || ss == ARMSS_Realm) && | |
2610 | ((timeridx == GTIMER_VIRT && (cnthctl & CNTHCTL_CNTVMASK)) || | |
2611 | (timeridx == GTIMER_PHYS && (cnthctl & CNTHCTL_CNTPMASK)))) { | |
2612 | irqstate = 0; | |
2613 | } | |
2614 | ||
2615 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
2616 | trace_arm_gt_update_irq(timeridx, irqstate); | |
2617 | } | |
2618 | ||
2619 | void gt_rme_post_el_change(ARMCPU *cpu, void *ignored) | |
2620 | { | |
2621 | /* | |
2622 | * Changing security state between Root and Secure/NonSecure, which may | |
2623 | * happen when switching EL, can change the effective value of CNTHCTL_EL2 | |
2624 | * mask bits. Update the IRQ state accordingly. | |
2625 | */ | |
2626 | gt_update_irq(cpu, GTIMER_VIRT); | |
2627 | gt_update_irq(cpu, GTIMER_PHYS); | |
2628 | } | |
2629 | ||
55d284af PM |
2630 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) |
2631 | { | |
2632 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; | |
2633 | ||
2634 | if (gt->ctl & 1) { | |
9b37a28c FR |
2635 | /* |
2636 | * Timer enabled: calculate and set current ISTATUS, irq, and | |
55d284af PM |
2637 | * reset timer to when ISTATUS next has to change |
2638 | */ | |
edac4d8a EI |
2639 | uint64_t offset = timeridx == GTIMER_VIRT ? |
2640 | cpu->env.cp15.cntvoff_el2 : 0; | |
55d284af PM |
2641 | uint64_t count = gt_get_countervalue(&cpu->env); |
2642 | /* Note that this must be unsigned 64 bit arithmetic: */ | |
edac4d8a | 2643 | int istatus = count - offset >= gt->cval; |
55d284af PM |
2644 | uint64_t nexttick; |
2645 | ||
2646 | gt->ctl = deposit32(gt->ctl, 2, 1, istatus); | |
194cbc49 | 2647 | |
55d284af | 2648 | if (istatus) { |
8d37a142 PM |
2649 | /* |
2650 | * Next transition is when (count - offset) rolls back over to 0. | |
2651 | * If offset > count then this is when count == offset; | |
2652 | * if offset <= count then this is when count == offset + 2^64 | |
2653 | * For the latter case we set nexttick to an "as far in future | |
2654 | * as possible" value and let the code below handle it. | |
2655 | */ | |
2656 | if (offset > count) { | |
2657 | nexttick = offset; | |
2658 | } else { | |
2659 | nexttick = UINT64_MAX; | |
2660 | } | |
55d284af | 2661 | } else { |
8d37a142 PM |
2662 | /* |
2663 | * Next transition is when (count - offset) == cval, i.e. | |
2664 | * when count == (cval + offset). | |
2665 | * If that would overflow, then again we set up the next interrupt | |
2666 | * for "as far in the future as possible" for the code below. | |
2667 | */ | |
2668 | if (uadd64_overflow(gt->cval, offset, &nexttick)) { | |
2669 | nexttick = UINT64_MAX; | |
2670 | } | |
55d284af | 2671 | } |
9b37a28c FR |
2672 | /* |
2673 | * Note that the desired next expiry time might be beyond the | |
55d284af PM |
2674 | * signed-64-bit range of a QEMUTimer -- in this case we just |
2675 | * set the timer for as far in the future as possible. When the | |
2676 | * timer expires we will reset the timer for any remaining period. | |
2677 | */ | |
7def8754 | 2678 | if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { |
4a0245b6 AJ |
2679 | timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX); |
2680 | } else { | |
2681 | timer_mod(cpu->gt_timer[timeridx], nexttick); | |
55d284af | 2682 | } |
f6fc36de | 2683 | trace_arm_gt_recalc(timeridx, nexttick); |
55d284af PM |
2684 | } else { |
2685 | /* Timer disabled: ISTATUS and timer output always clear */ | |
2686 | gt->ctl &= ~4; | |
bc72ad67 | 2687 | timer_del(cpu->gt_timer[timeridx]); |
194cbc49 | 2688 | trace_arm_gt_recalc_disabled(timeridx); |
55d284af | 2689 | } |
f6fc36de | 2690 | gt_update_irq(cpu, timeridx); |
55d284af PM |
2691 | } |
2692 | ||
0e3eca4c EI |
2693 | static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, |
2694 | int timeridx) | |
55d284af | 2695 | { |
2fc0cc0e | 2696 | ARMCPU *cpu = env_archcpu(env); |
55d284af | 2697 | |
bc72ad67 | 2698 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
2699 | } |
2700 | ||
c4241c7d | 2701 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
55d284af | 2702 | { |
c4241c7d | 2703 | return gt_get_countervalue(env); |
55d284af PM |
2704 | } |
2705 | ||
53d1f856 RH |
2706 | static uint64_t gt_virt_cnt_offset(CPUARMState *env) |
2707 | { | |
2708 | uint64_t hcr; | |
2709 | ||
2710 | switch (arm_current_el(env)) { | |
2711 | case 2: | |
2712 | hcr = arm_hcr_el2_eff(env); | |
2713 | if (hcr & HCR_E2H) { | |
2714 | return 0; | |
2715 | } | |
2716 | break; | |
2717 | case 0: | |
2718 | hcr = arm_hcr_el2_eff(env); | |
2719 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2720 | return 0; | |
2721 | } | |
2722 | break; | |
2723 | } | |
2724 | ||
2725 | return env->cp15.cntvoff_el2; | |
2726 | } | |
2727 | ||
edac4d8a EI |
2728 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2729 | { | |
53d1f856 | 2730 | return gt_get_countervalue(env) - gt_virt_cnt_offset(env); |
edac4d8a EI |
2731 | } |
2732 | ||
c4241c7d | 2733 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2734 | int timeridx, |
c4241c7d | 2735 | uint64_t value) |
55d284af | 2736 | { |
194cbc49 | 2737 | trace_arm_gt_cval_write(timeridx, value); |
55d284af | 2738 | env->cp15.c14_timer[timeridx].cval = value; |
2fc0cc0e | 2739 | gt_recalc_timer(env_archcpu(env), timeridx); |
55d284af | 2740 | } |
c4241c7d | 2741 | |
0e3eca4c EI |
2742 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, |
2743 | int timeridx) | |
55d284af | 2744 | { |
53d1f856 RH |
2745 | uint64_t offset = 0; |
2746 | ||
2747 | switch (timeridx) { | |
2748 | case GTIMER_VIRT: | |
8c94b071 | 2749 | case GTIMER_HYPVIRT: |
53d1f856 RH |
2750 | offset = gt_virt_cnt_offset(env); |
2751 | break; | |
2752 | } | |
55d284af | 2753 | |
c4241c7d | 2754 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - |
edac4d8a | 2755 | (gt_get_countervalue(env) - offset)); |
55d284af PM |
2756 | } |
2757 | ||
c4241c7d | 2758 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2759 | int timeridx, |
c4241c7d | 2760 | uint64_t value) |
55d284af | 2761 | { |
53d1f856 RH |
2762 | uint64_t offset = 0; |
2763 | ||
2764 | switch (timeridx) { | |
2765 | case GTIMER_VIRT: | |
8c94b071 | 2766 | case GTIMER_HYPVIRT: |
53d1f856 RH |
2767 | offset = gt_virt_cnt_offset(env); |
2768 | break; | |
2769 | } | |
55d284af | 2770 | |
194cbc49 | 2771 | trace_arm_gt_tval_write(timeridx, value); |
edac4d8a | 2772 | env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + |
18084b2f | 2773 | sextract64(value, 0, 32); |
2fc0cc0e | 2774 | gt_recalc_timer(env_archcpu(env), timeridx); |
55d284af PM |
2775 | } |
2776 | ||
c4241c7d | 2777 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2778 | int timeridx, |
c4241c7d | 2779 | uint64_t value) |
55d284af | 2780 | { |
2fc0cc0e | 2781 | ARMCPU *cpu = env_archcpu(env); |
55d284af PM |
2782 | uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; |
2783 | ||
194cbc49 | 2784 | trace_arm_gt_ctl_write(timeridx, value); |
d3afacc7 | 2785 | env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); |
55d284af PM |
2786 | if ((oldval ^ value) & 1) { |
2787 | /* Enable toggled */ | |
2788 | gt_recalc_timer(cpu, timeridx); | |
d3afacc7 | 2789 | } else if ((oldval ^ value) & 2) { |
9b37a28c FR |
2790 | /* |
2791 | * IMASK toggled: don't need to recalculate, | |
55d284af PM |
2792 | * just set the interrupt line based on ISTATUS |
2793 | */ | |
f6fc36de JPB |
2794 | trace_arm_gt_imask_toggle(timeridx); |
2795 | gt_update_irq(cpu, timeridx); | |
55d284af | 2796 | } |
55d284af PM |
2797 | } |
2798 | ||
0e3eca4c EI |
2799 | static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2800 | { | |
2801 | gt_timer_reset(env, ri, GTIMER_PHYS); | |
2802 | } | |
2803 | ||
2804 | static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2805 | uint64_t value) | |
2806 | { | |
2807 | gt_cval_write(env, ri, GTIMER_PHYS, value); | |
2808 | } | |
2809 | ||
2810 | static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2811 | { | |
2812 | return gt_tval_read(env, ri, GTIMER_PHYS); | |
2813 | } | |
2814 | ||
2815 | static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2816 | uint64_t value) | |
2817 | { | |
2818 | gt_tval_write(env, ri, GTIMER_PHYS, value); | |
2819 | } | |
2820 | ||
2821 | static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2822 | uint64_t value) | |
2823 | { | |
2824 | gt_ctl_write(env, ri, GTIMER_PHYS, value); | |
2825 | } | |
2826 | ||
bb5972e4 RH |
2827 | static int gt_phys_redir_timeridx(CPUARMState *env) |
2828 | { | |
2829 | switch (arm_mmu_idx(env)) { | |
2830 | case ARMMMUIdx_E20_0: | |
2831 | case ARMMMUIdx_E20_2: | |
452ef8cb | 2832 | case ARMMMUIdx_E20_2_PAN: |
bb5972e4 RH |
2833 | return GTIMER_HYP; |
2834 | default: | |
2835 | return GTIMER_PHYS; | |
2836 | } | |
2837 | } | |
2838 | ||
2839 | static int gt_virt_redir_timeridx(CPUARMState *env) | |
2840 | { | |
2841 | switch (arm_mmu_idx(env)) { | |
2842 | case ARMMMUIdx_E20_0: | |
2843 | case ARMMMUIdx_E20_2: | |
452ef8cb | 2844 | case ARMMMUIdx_E20_2_PAN: |
bb5972e4 RH |
2845 | return GTIMER_HYPVIRT; |
2846 | default: | |
2847 | return GTIMER_VIRT; | |
2848 | } | |
2849 | } | |
2850 | ||
2851 | static uint64_t gt_phys_redir_cval_read(CPUARMState *env, | |
2852 | const ARMCPRegInfo *ri) | |
2853 | { | |
2854 | int timeridx = gt_phys_redir_timeridx(env); | |
2855 | return env->cp15.c14_timer[timeridx].cval; | |
2856 | } | |
2857 | ||
2858 | static void gt_phys_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2859 | uint64_t value) | |
2860 | { | |
2861 | int timeridx = gt_phys_redir_timeridx(env); | |
2862 | gt_cval_write(env, ri, timeridx, value); | |
2863 | } | |
2864 | ||
2865 | static uint64_t gt_phys_redir_tval_read(CPUARMState *env, | |
2866 | const ARMCPRegInfo *ri) | |
2867 | { | |
2868 | int timeridx = gt_phys_redir_timeridx(env); | |
2869 | return gt_tval_read(env, ri, timeridx); | |
2870 | } | |
2871 | ||
2872 | static void gt_phys_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2873 | uint64_t value) | |
2874 | { | |
2875 | int timeridx = gt_phys_redir_timeridx(env); | |
2876 | gt_tval_write(env, ri, timeridx, value); | |
2877 | } | |
2878 | ||
2879 | static uint64_t gt_phys_redir_ctl_read(CPUARMState *env, | |
2880 | const ARMCPRegInfo *ri) | |
2881 | { | |
2882 | int timeridx = gt_phys_redir_timeridx(env); | |
2883 | return env->cp15.c14_timer[timeridx].ctl; | |
2884 | } | |
2885 | ||
2886 | static void gt_phys_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2887 | uint64_t value) | |
2888 | { | |
2889 | int timeridx = gt_phys_redir_timeridx(env); | |
2890 | gt_ctl_write(env, ri, timeridx, value); | |
2891 | } | |
2892 | ||
0e3eca4c EI |
2893 | static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2894 | { | |
2895 | gt_timer_reset(env, ri, GTIMER_VIRT); | |
2896 | } | |
2897 | ||
2898 | static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2899 | uint64_t value) | |
2900 | { | |
2901 | gt_cval_write(env, ri, GTIMER_VIRT, value); | |
2902 | } | |
2903 | ||
2904 | static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2905 | { | |
2906 | return gt_tval_read(env, ri, GTIMER_VIRT); | |
2907 | } | |
2908 | ||
2909 | static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2910 | uint64_t value) | |
2911 | { | |
2912 | gt_tval_write(env, ri, GTIMER_VIRT, value); | |
2913 | } | |
2914 | ||
2915 | static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2916 | uint64_t value) | |
2917 | { | |
2918 | gt_ctl_write(env, ri, GTIMER_VIRT, value); | |
2919 | } | |
2920 | ||
f6fc36de JPB |
2921 | static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2922 | uint64_t value) | |
2923 | { | |
2924 | ARMCPU *cpu = env_archcpu(env); | |
2925 | uint32_t oldval = env->cp15.cnthctl_el2; | |
2926 | ||
2927 | raw_write(env, ri, value); | |
2928 | ||
2929 | if ((oldval ^ value) & CNTHCTL_CNTVMASK) { | |
2930 | gt_update_irq(cpu, GTIMER_VIRT); | |
2931 | } else if ((oldval ^ value) & CNTHCTL_CNTPMASK) { | |
2932 | gt_update_irq(cpu, GTIMER_PHYS); | |
2933 | } | |
2934 | } | |
2935 | ||
edac4d8a EI |
2936 | static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2937 | uint64_t value) | |
2938 | { | |
2fc0cc0e | 2939 | ARMCPU *cpu = env_archcpu(env); |
edac4d8a | 2940 | |
194cbc49 | 2941 | trace_arm_gt_cntvoff_write(value); |
edac4d8a EI |
2942 | raw_write(env, ri, value); |
2943 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
2944 | } | |
2945 | ||
bb5972e4 RH |
2946 | static uint64_t gt_virt_redir_cval_read(CPUARMState *env, |
2947 | const ARMCPRegInfo *ri) | |
2948 | { | |
2949 | int timeridx = gt_virt_redir_timeridx(env); | |
2950 | return env->cp15.c14_timer[timeridx].cval; | |
2951 | } | |
2952 | ||
2953 | static void gt_virt_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2954 | uint64_t value) | |
2955 | { | |
2956 | int timeridx = gt_virt_redir_timeridx(env); | |
2957 | gt_cval_write(env, ri, timeridx, value); | |
2958 | } | |
2959 | ||
2960 | static uint64_t gt_virt_redir_tval_read(CPUARMState *env, | |
2961 | const ARMCPRegInfo *ri) | |
2962 | { | |
2963 | int timeridx = gt_virt_redir_timeridx(env); | |
2964 | return gt_tval_read(env, ri, timeridx); | |
2965 | } | |
2966 | ||
2967 | static void gt_virt_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2968 | uint64_t value) | |
2969 | { | |
2970 | int timeridx = gt_virt_redir_timeridx(env); | |
2971 | gt_tval_write(env, ri, timeridx, value); | |
2972 | } | |
2973 | ||
2974 | static uint64_t gt_virt_redir_ctl_read(CPUARMState *env, | |
2975 | const ARMCPRegInfo *ri) | |
2976 | { | |
2977 | int timeridx = gt_virt_redir_timeridx(env); | |
2978 | return env->cp15.c14_timer[timeridx].ctl; | |
2979 | } | |
2980 | ||
2981 | static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2982 | uint64_t value) | |
2983 | { | |
2984 | int timeridx = gt_virt_redir_timeridx(env); | |
2985 | gt_ctl_write(env, ri, timeridx, value); | |
2986 | } | |
2987 | ||
b0e66d95 EI |
2988 | static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2989 | { | |
2990 | gt_timer_reset(env, ri, GTIMER_HYP); | |
2991 | } | |
2992 | ||
2993 | static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2994 | uint64_t value) | |
2995 | { | |
2996 | gt_cval_write(env, ri, GTIMER_HYP, value); | |
2997 | } | |
2998 | ||
2999 | static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3000 | { | |
3001 | return gt_tval_read(env, ri, GTIMER_HYP); | |
3002 | } | |
3003 | ||
3004 | static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3005 | uint64_t value) | |
3006 | { | |
3007 | gt_tval_write(env, ri, GTIMER_HYP, value); | |
3008 | } | |
3009 | ||
3010 | static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3011 | uint64_t value) | |
3012 | { | |
3013 | gt_ctl_write(env, ri, GTIMER_HYP, value); | |
3014 | } | |
3015 | ||
b4d3978c PM |
3016 | static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
3017 | { | |
3018 | gt_timer_reset(env, ri, GTIMER_SEC); | |
3019 | } | |
3020 | ||
3021 | static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3022 | uint64_t value) | |
3023 | { | |
3024 | gt_cval_write(env, ri, GTIMER_SEC, value); | |
3025 | } | |
3026 | ||
3027 | static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3028 | { | |
3029 | return gt_tval_read(env, ri, GTIMER_SEC); | |
3030 | } | |
3031 | ||
3032 | static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3033 | uint64_t value) | |
3034 | { | |
3035 | gt_tval_write(env, ri, GTIMER_SEC, value); | |
3036 | } | |
3037 | ||
3038 | static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3039 | uint64_t value) | |
3040 | { | |
3041 | gt_ctl_write(env, ri, GTIMER_SEC, value); | |
3042 | } | |
3043 | ||
8c94b071 RH |
3044 | static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
3045 | { | |
3046 | gt_timer_reset(env, ri, GTIMER_HYPVIRT); | |
3047 | } | |
3048 | ||
3049 | static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3050 | uint64_t value) | |
3051 | { | |
3052 | gt_cval_write(env, ri, GTIMER_HYPVIRT, value); | |
3053 | } | |
3054 | ||
3055 | static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3056 | { | |
3057 | return gt_tval_read(env, ri, GTIMER_HYPVIRT); | |
3058 | } | |
3059 | ||
3060 | static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3061 | uint64_t value) | |
3062 | { | |
3063 | gt_tval_write(env, ri, GTIMER_HYPVIRT, value); | |
3064 | } | |
3065 | ||
3066 | static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3067 | uint64_t value) | |
3068 | { | |
3069 | gt_ctl_write(env, ri, GTIMER_HYPVIRT, value); | |
3070 | } | |
3071 | ||
55d284af PM |
3072 | void arm_gt_ptimer_cb(void *opaque) |
3073 | { | |
3074 | ARMCPU *cpu = opaque; | |
3075 | ||
3076 | gt_recalc_timer(cpu, GTIMER_PHYS); | |
3077 | } | |
3078 | ||
3079 | void arm_gt_vtimer_cb(void *opaque) | |
3080 | { | |
3081 | ARMCPU *cpu = opaque; | |
3082 | ||
3083 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
3084 | } | |
3085 | ||
b0e66d95 EI |
3086 | void arm_gt_htimer_cb(void *opaque) |
3087 | { | |
3088 | ARMCPU *cpu = opaque; | |
3089 | ||
3090 | gt_recalc_timer(cpu, GTIMER_HYP); | |
3091 | } | |
3092 | ||
b4d3978c PM |
3093 | void arm_gt_stimer_cb(void *opaque) |
3094 | { | |
3095 | ARMCPU *cpu = opaque; | |
3096 | ||
3097 | gt_recalc_timer(cpu, GTIMER_SEC); | |
3098 | } | |
3099 | ||
8c94b071 RH |
3100 | void arm_gt_hvtimer_cb(void *opaque) |
3101 | { | |
3102 | ARMCPU *cpu = opaque; | |
3103 | ||
3104 | gt_recalc_timer(cpu, GTIMER_HYPVIRT); | |
3105 | } | |
3106 | ||
96eec6b2 AJ |
3107 | static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque) |
3108 | { | |
3109 | ARMCPU *cpu = env_archcpu(env); | |
3110 | ||
3111 | cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz; | |
3112 | } | |
3113 | ||
55d284af | 3114 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
9b37a28c FR |
3115 | /* |
3116 | * Note that CNTFRQ is purely reads-as-written for the benefit | |
55d284af PM |
3117 | * of software; writing it doesn't actually change the timer frequency. |
3118 | * Our reset value matches the fixed frequency we implement the timer at. | |
3119 | */ | |
3120 | { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 3121 | .type = ARM_CP_ALIAS, |
a7adc4b7 PM |
3122 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, |
3123 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), | |
a7adc4b7 PM |
3124 | }, |
3125 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, | |
3126 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
3127 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
55d284af | 3128 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), |
96eec6b2 | 3129 | .resetfn = arm_gt_cntfrq_reset, |
55d284af PM |
3130 | }, |
3131 | /* overall control: mostly access permissions */ | |
a7adc4b7 PM |
3132 | { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, |
3133 | .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, | |
55d284af PM |
3134 | .access = PL1_RW, |
3135 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), | |
3136 | .resetvalue = 0, | |
3137 | }, | |
3138 | /* per-timer control */ | |
3139 | { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
9ff9dd3c | 3140 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 3141 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
a7adc4b7 PM |
3142 | .accessfn = gt_ptimer_access, |
3143 | .fieldoffset = offsetoflow32(CPUARMState, | |
3144 | cp15.c14_timer[GTIMER_PHYS].ctl), | |
bb5972e4 RH |
3145 | .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read, |
3146 | .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write, | |
a7adc4b7 | 3147 | }, |
9c513e78 | 3148 | { .name = "CNTP_CTL_S", |
9ff9dd3c PM |
3149 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, |
3150 | .secure = ARM_CP_SECSTATE_S, | |
daf1dc5f | 3151 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
9ff9dd3c PM |
3152 | .accessfn = gt_ptimer_access, |
3153 | .fieldoffset = offsetoflow32(CPUARMState, | |
3154 | cp15.c14_timer[GTIMER_SEC].ctl), | |
3155 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
3156 | }, | |
a7adc4b7 PM |
3157 | { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, |
3158 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, | |
daf1dc5f | 3159 | .type = ARM_CP_IO, .access = PL0_RW, |
a7adc4b7 | 3160 | .accessfn = gt_ptimer_access, |
55d284af PM |
3161 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), |
3162 | .resetvalue = 0, | |
bb5972e4 RH |
3163 | .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read, |
3164 | .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write, | |
55d284af PM |
3165 | }, |
3166 | { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, | |
daf1dc5f | 3167 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
a7adc4b7 PM |
3168 | .accessfn = gt_vtimer_access, |
3169 | .fieldoffset = offsetoflow32(CPUARMState, | |
3170 | cp15.c14_timer[GTIMER_VIRT].ctl), | |
bb5972e4 RH |
3171 | .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read, |
3172 | .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write, | |
a7adc4b7 PM |
3173 | }, |
3174 | { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
3175 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, | |
daf1dc5f | 3176 | .type = ARM_CP_IO, .access = PL0_RW, |
a7adc4b7 | 3177 | .accessfn = gt_vtimer_access, |
55d284af PM |
3178 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), |
3179 | .resetvalue = 0, | |
bb5972e4 RH |
3180 | .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read, |
3181 | .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write, | |
55d284af PM |
3182 | }, |
3183 | /* TimerValue views: a 32 bit downcounting view of the underlying state */ | |
3184 | { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
9ff9dd3c | 3185 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 3186 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
00108f2d | 3187 | .accessfn = gt_ptimer_access, |
bb5972e4 | 3188 | .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write, |
55d284af | 3189 | }, |
9c513e78 | 3190 | { .name = "CNTP_TVAL_S", |
9ff9dd3c PM |
3191 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, |
3192 | .secure = ARM_CP_SECSTATE_S, | |
daf1dc5f | 3193 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
9ff9dd3c PM |
3194 | .accessfn = gt_ptimer_access, |
3195 | .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, | |
3196 | }, | |
a7adc4b7 PM |
3197 | { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
3198 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, | |
daf1dc5f | 3199 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
0e3eca4c | 3200 | .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, |
bb5972e4 | 3201 | .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write, |
a7adc4b7 | 3202 | }, |
55d284af | 3203 | { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, |
daf1dc5f | 3204 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
00108f2d | 3205 | .accessfn = gt_vtimer_access, |
bb5972e4 | 3206 | .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write, |
55d284af | 3207 | }, |
a7adc4b7 PM |
3208 | { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
3209 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, | |
daf1dc5f | 3210 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
0e3eca4c | 3211 | .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, |
bb5972e4 | 3212 | .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write, |
a7adc4b7 | 3213 | }, |
55d284af PM |
3214 | /* The counter itself */ |
3215 | { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, | |
7a0e58fa | 3216 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 3217 | .accessfn = gt_pct_access, |
a7adc4b7 PM |
3218 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
3219 | }, | |
3220 | { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, | |
3221 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, | |
7a0e58fa | 3222 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 3223 | .accessfn = gt_pct_access, .readfn = gt_cnt_read, |
55d284af PM |
3224 | }, |
3225 | { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, | |
7a0e58fa | 3226 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 3227 | .accessfn = gt_vct_access, |
edac4d8a | 3228 | .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, |
a7adc4b7 PM |
3229 | }, |
3230 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
3231 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
7a0e58fa | 3232 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 3233 | .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, |
55d284af PM |
3234 | }, |
3235 | /* Comparison value, indicating when the timer goes off */ | |
3236 | { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, | |
9ff9dd3c | 3237 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 3238 | .access = PL0_RW, |
7a0e58fa | 3239 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 3240 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), |
b061a82b | 3241 | .accessfn = gt_ptimer_access, |
bb5972e4 RH |
3242 | .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read, |
3243 | .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write, | |
a7adc4b7 | 3244 | }, |
9c513e78 | 3245 | { .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2, |
9ff9dd3c | 3246 | .secure = ARM_CP_SECSTATE_S, |
daf1dc5f | 3247 | .access = PL0_RW, |
9ff9dd3c PM |
3248 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
3249 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
3250 | .accessfn = gt_ptimer_access, | |
3251 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
3252 | }, | |
a7adc4b7 PM |
3253 | { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, |
3254 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, | |
daf1dc5f | 3255 | .access = PL0_RW, |
a7adc4b7 PM |
3256 | .type = ARM_CP_IO, |
3257 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
12cde08a | 3258 | .resetvalue = 0, .accessfn = gt_ptimer_access, |
bb5972e4 RH |
3259 | .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read, |
3260 | .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write, | |
55d284af PM |
3261 | }, |
3262 | { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, | |
daf1dc5f | 3263 | .access = PL0_RW, |
7a0e58fa | 3264 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 3265 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), |
b061a82b | 3266 | .accessfn = gt_vtimer_access, |
bb5972e4 RH |
3267 | .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read, |
3268 | .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write, | |
a7adc4b7 PM |
3269 | }, |
3270 | { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
3271 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, | |
daf1dc5f | 3272 | .access = PL0_RW, |
a7adc4b7 PM |
3273 | .type = ARM_CP_IO, |
3274 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
3275 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
bb5972e4 RH |
3276 | .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read, |
3277 | .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write, | |
55d284af | 3278 | }, |
9b37a28c FR |
3279 | /* |
3280 | * Secure timer -- this is actually restricted to only EL3 | |
b4d3978c PM |
3281 | * and configurably Secure-EL1 via the accessfn. |
3282 | */ | |
3283 | { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, | |
3284 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, | |
3285 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, | |
3286 | .accessfn = gt_stimer_access, | |
3287 | .readfn = gt_sec_tval_read, | |
3288 | .writefn = gt_sec_tval_write, | |
3289 | .resetfn = gt_sec_timer_reset, | |
3290 | }, | |
3291 | { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64, | |
3292 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1, | |
3293 | .type = ARM_CP_IO, .access = PL1_RW, | |
3294 | .accessfn = gt_stimer_access, | |
3295 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), | |
3296 | .resetvalue = 0, | |
3297 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
3298 | }, | |
3299 | { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, | |
3300 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, | |
3301 | .type = ARM_CP_IO, .access = PL1_RW, | |
3302 | .accessfn = gt_stimer_access, | |
3303 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
3304 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
3305 | }, | |
55d284af PM |
3306 | }; |
3307 | ||
bb5972e4 RH |
3308 | static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3309 | bool isread) | |
3310 | { | |
3311 | if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { | |
3312 | return CP_ACCESS_TRAP; | |
3313 | } | |
3314 | return CP_ACCESS_OK; | |
3315 | } | |
3316 | ||
55d284af | 3317 | #else |
26c4a83b | 3318 | |
9b37a28c FR |
3319 | /* |
3320 | * In user-mode most of the generic timer registers are inaccessible | |
26c4a83b | 3321 | * however modern kernels (4.12+) allow access to cntvct_el0 |
55d284af | 3322 | */ |
26c4a83b AB |
3323 | |
3324 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3325 | { | |
7def8754 AJ |
3326 | ARMCPU *cpu = env_archcpu(env); |
3327 | ||
9b37a28c FR |
3328 | /* |
3329 | * Currently we have no support for QEMUTimer in linux-user so we | |
26c4a83b AB |
3330 | * can't call gt_get_countervalue(env), instead we directly |
3331 | * call the lower level functions. | |
3332 | */ | |
7def8754 | 3333 | return cpu_get_clock() / gt_cntfrq_period_ns(cpu); |
26c4a83b AB |
3334 | } |
3335 | ||
6cc7a3ae | 3336 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
26c4a83b AB |
3337 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, |
3338 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
3339 | .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */, | |
3340 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), | |
3341 | .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE, | |
3342 | }, | |
3343 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
3344 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
3345 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
3346 | .readfn = gt_virt_cnt_read, | |
3347 | }, | |
6cc7a3ae PM |
3348 | }; |
3349 | ||
55d284af PM |
3350 | #endif |
3351 | ||
c4241c7d | 3352 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 3353 | { |
891a2fe7 | 3354 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8d5c773e | 3355 | raw_write(env, ri, value); |
891a2fe7 | 3356 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8d5c773e | 3357 | raw_write(env, ri, value & 0xfffff6ff); |
4a501606 | 3358 | } else { |
8d5c773e | 3359 | raw_write(env, ri, value & 0xfffff1ff); |
4a501606 | 3360 | } |
4a501606 PM |
3361 | } |
3362 | ||
3363 | #ifndef CONFIG_USER_ONLY | |
3364 | /* get_phys_addr() isn't present for user-mode-only targets */ | |
702a9357 | 3365 | |
3f208fd7 PM |
3366 | static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3367 | bool isread) | |
92611c00 PM |
3368 | { |
3369 | if (ri->opc2 & 4) { | |
9b37a28c FR |
3370 | /* |
3371 | * The ATS12NSO* operations must trap to EL3 or EL2 if executed in | |
87562e4f PM |
3372 | * Secure EL1 (which can only happen if EL3 is AArch64). |
3373 | * They are simply UNDEF if executed from NS EL1. | |
3374 | * They function normally from EL2 or EL3. | |
92611c00 | 3375 | */ |
87562e4f PM |
3376 | if (arm_current_el(env) == 1) { |
3377 | if (arm_is_secure_below_el3(env)) { | |
926c1b97 | 3378 | if (env->cp15.scr_el3 & SCR_EEL2) { |
ce9a8863 | 3379 | return CP_ACCESS_TRAP_EL2; |
926c1b97 | 3380 | } |
ce9a8863 | 3381 | return CP_ACCESS_TRAP_EL3; |
87562e4f PM |
3382 | } |
3383 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
3384 | } | |
92611c00 PM |
3385 | } |
3386 | return CP_ACCESS_OK; | |
3387 | } | |
3388 | ||
9fb005b0 | 3389 | #ifdef CONFIG_TCG |
b17d86eb PM |
3390 | static int par_el1_shareability(GetPhysAddrResult *res) |
3391 | { | |
3392 | /* | |
3393 | * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC | |
3394 | * memory -- see pseudocode PAREncodeShareability(). | |
3395 | */ | |
3396 | if (((res->cacheattrs.attrs & 0xf0) == 0) || | |
3397 | res->cacheattrs.attrs == 0x44 || res->cacheattrs.attrs == 0x40) { | |
3398 | return 2; | |
3399 | } | |
3400 | return res->cacheattrs.shareability; | |
3401 | } | |
3402 | ||
060e8a48 | 3403 | static uint64_t do_ats_write(CPUARMState *env, uint64_t value, |
7aee3cb9 | 3404 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
e1ee56ec | 3405 | ARMSecuritySpace ss) |
4a501606 | 3406 | { |
b7cc4e82 | 3407 | bool ret; |
01c097f7 | 3408 | uint64_t par64; |
1313e2d7 | 3409 | bool format64 = false; |
e14b5a23 | 3410 | ARMMMUFaultInfo fi = {}; |
de05a709 | 3411 | GetPhysAddrResult res = {}; |
4a501606 | 3412 | |
f1269a98 JPB |
3413 | /* |
3414 | * I_MXTJT: Granule protection checks are not performed on the final address | |
3415 | * of a successful translation. | |
3416 | */ | |
e1ee56ec JPB |
3417 | ret = get_phys_addr_with_space_nogpc(env, value, access_type, mmu_idx, ss, |
3418 | &res, &fi); | |
1313e2d7 | 3419 | |
9f225e60 PM |
3420 | /* |
3421 | * ATS operations only do S1 or S1+S2 translations, so we never | |
3422 | * have to deal with the ARMCacheAttrs format for S2 only. | |
3423 | */ | |
de05a709 | 3424 | assert(!res.cacheattrs.is_s2_format); |
9f225e60 | 3425 | |
0710b2fa PM |
3426 | if (ret) { |
3427 | /* | |
3428 | * Some kinds of translation fault must cause exceptions rather | |
3429 | * than being reported in the PAR. | |
3430 | */ | |
3431 | int current_el = arm_current_el(env); | |
3432 | int target_el; | |
3433 | uint32_t syn, fsr, fsc; | |
3434 | bool take_exc = false; | |
3435 | ||
b1a10c86 | 3436 | if (fi.s1ptw && current_el == 1 |
fee7aa46 | 3437 | && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { |
0710b2fa PM |
3438 | /* |
3439 | * Synchronous stage 2 fault on an access made as part of the | |
3440 | * translation table walk for AT S1E0* or AT S1E1* insn | |
3441 | * executed from NS EL1. If this is a synchronous external abort | |
3442 | * and SCR_EL3.EA == 1, then we take a synchronous external abort | |
3443 | * to EL3. Otherwise the fault is taken as an exception to EL2, | |
3444 | * and HPFAR_EL2 holds the faulting IPA. | |
3445 | */ | |
3446 | if (fi.type == ARMFault_SyncExternalOnWalk && | |
3447 | (env->cp15.scr_el3 & SCR_EA)) { | |
3448 | target_el = 3; | |
3449 | } else { | |
3450 | env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; | |
9861248f RDC |
3451 | if (arm_is_secure_below_el3(env) && fi.s1ns) { |
3452 | env->cp15.hpfar_el2 |= HPFAR_NS; | |
3453 | } | |
0710b2fa PM |
3454 | target_el = 2; |
3455 | } | |
3456 | take_exc = true; | |
3457 | } else if (fi.type == ARMFault_SyncExternalOnWalk) { | |
3458 | /* | |
3459 | * Synchronous external aborts during a translation table walk | |
3460 | * are taken as Data Abort exceptions. | |
3461 | */ | |
3462 | if (fi.stage2) { | |
3463 | if (current_el == 3) { | |
3464 | target_el = 3; | |
3465 | } else { | |
3466 | target_el = 2; | |
3467 | } | |
3468 | } else { | |
3469 | target_el = exception_target_el(env); | |
3470 | } | |
3471 | take_exc = true; | |
3472 | } | |
3473 | ||
3474 | if (take_exc) { | |
3475 | /* Construct FSR and FSC using same logic as arm_deliver_fault() */ | |
3476 | if (target_el == 2 || arm_el_is_aa64(env, target_el) || | |
3477 | arm_s1_regime_using_lpae_format(env, mmu_idx)) { | |
3478 | fsr = arm_fi_to_lfsc(&fi); | |
3479 | fsc = extract32(fsr, 0, 6); | |
3480 | } else { | |
3481 | fsr = arm_fi_to_sfsc(&fi); | |
3482 | fsc = 0x3f; | |
3483 | } | |
3484 | /* | |
3485 | * Report exception with ESR indicating a fault due to a | |
3486 | * translation table walk for a cache maintenance instruction. | |
3487 | */ | |
e24fd076 | 3488 | syn = syn_data_abort_no_iss(current_el == target_el, 0, |
0710b2fa PM |
3489 | fi.ea, 1, fi.s1ptw, 1, fsc); |
3490 | env->exception.vaddress = value; | |
3491 | env->exception.fsr = fsr; | |
3492 | raise_exception(env, EXCP_DATA_ABORT, syn, target_el); | |
3493 | } | |
3494 | } | |
3495 | ||
1313e2d7 EI |
3496 | if (is_a64(env)) { |
3497 | format64 = true; | |
3498 | } else if (arm_feature(env, ARM_FEATURE_LPAE)) { | |
3499 | /* | |
3500 | * ATS1Cxx: | |
3501 | * * TTBCR.EAE determines whether the result is returned using the | |
3502 | * 32-bit or the 64-bit PAR format | |
3503 | * * Instructions executed in Hyp mode always use the 64bit format | |
3504 | * | |
3505 | * ATS1S2NSOxx uses the 64bit format if any of the following is true: | |
3506 | * * The Non-secure TTBCR.EAE bit is set to 1 | |
3507 | * * The implementation includes EL2, and the value of HCR.VM is 1 | |
3508 | * | |
9d1bab33 PM |
3509 | * (Note that HCR.DC makes HCR.VM behave as if it is 1.) |
3510 | * | |
23463e0e | 3511 | * ATS1Hx always uses the 64bit format. |
1313e2d7 EI |
3512 | */ |
3513 | format64 = arm_s1_regime_using_lpae_format(env, mmu_idx); | |
3514 | ||
3515 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
452ef8cb RH |
3516 | if (mmu_idx == ARMMMUIdx_E10_0 || |
3517 | mmu_idx == ARMMMUIdx_E10_1 || | |
3518 | mmu_idx == ARMMMUIdx_E10_1_PAN) { | |
9d1bab33 | 3519 | format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC); |
1313e2d7 EI |
3520 | } else { |
3521 | format64 |= arm_current_el(env) == 2; | |
3522 | } | |
3523 | } | |
3524 | } | |
3525 | ||
3526 | if (format64) { | |
5efe9ed4 | 3527 | /* Create a 64-bit PAR */ |
01c097f7 | 3528 | par64 = (1 << 11); /* LPAE bit always set */ |
b7cc4e82 | 3529 | if (!ret) { |
7fa7ea8f RH |
3530 | par64 |= res.f.phys_addr & ~0xfffULL; |
3531 | if (!res.f.attrs.secure) { | |
8bf5b6a9 PM |
3532 | par64 |= (1 << 9); /* NS */ |
3533 | } | |
de05a709 | 3534 | par64 |= (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */ |
b17d86eb | 3535 | par64 |= par_el1_shareability(&res) << 7; /* SH */ |
4a501606 | 3536 | } else { |
5efe9ed4 PM |
3537 | uint32_t fsr = arm_fi_to_lfsc(&fi); |
3538 | ||
702a9357 | 3539 | par64 |= 1; /* F */ |
b7cc4e82 | 3540 | par64 |= (fsr & 0x3f) << 1; /* FS */ |
0f7b791b PM |
3541 | if (fi.stage2) { |
3542 | par64 |= (1 << 9); /* S */ | |
3543 | } | |
3544 | if (fi.s1ptw) { | |
3545 | par64 |= (1 << 8); /* PTW */ | |
3546 | } | |
4a501606 PM |
3547 | } |
3548 | } else { | |
9b37a28c FR |
3549 | /* |
3550 | * fsr is a DFSR/IFSR value for the short descriptor | |
702a9357 PM |
3551 | * translation table format (with WnR always clear). |
3552 | * Convert it to a 32-bit PAR. | |
3553 | */ | |
b7cc4e82 | 3554 | if (!ret) { |
702a9357 | 3555 | /* We do not set any attribute bits in the PAR */ |
7fa7ea8f | 3556 | if (res.f.lg_page_size == 24 |
702a9357 | 3557 | && arm_feature(env, ARM_FEATURE_V7)) { |
7fa7ea8f | 3558 | par64 = (res.f.phys_addr & 0xff000000) | (1 << 1); |
702a9357 | 3559 | } else { |
7fa7ea8f | 3560 | par64 = res.f.phys_addr & 0xfffff000; |
702a9357 | 3561 | } |
7fa7ea8f | 3562 | if (!res.f.attrs.secure) { |
8bf5b6a9 PM |
3563 | par64 |= (1 << 9); /* NS */ |
3564 | } | |
702a9357 | 3565 | } else { |
5efe9ed4 PM |
3566 | uint32_t fsr = arm_fi_to_sfsc(&fi); |
3567 | ||
b7cc4e82 PC |
3568 | par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | |
3569 | ((fsr & 0xf) << 1) | 1; | |
702a9357 | 3570 | } |
4a501606 | 3571 | } |
060e8a48 PM |
3572 | return par64; |
3573 | } | |
9fb005b0 | 3574 | #endif /* CONFIG_TCG */ |
060e8a48 PM |
3575 | |
3576 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | |
3577 | { | |
9fb005b0 | 3578 | #ifdef CONFIG_TCG |
03ae85f8 | 3579 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
060e8a48 | 3580 | uint64_t par64; |
d3649702 PM |
3581 | ARMMMUIdx mmu_idx; |
3582 | int el = arm_current_el(env); | |
e1ee56ec | 3583 | ARMSecuritySpace ss = arm_security_space(env); |
060e8a48 | 3584 | |
d3649702 PM |
3585 | switch (ri->opc2 & 6) { |
3586 | case 0: | |
04b07d29 | 3587 | /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */ |
d3649702 PM |
3588 | switch (el) { |
3589 | case 3: | |
d902ae75 | 3590 | mmu_idx = ARMMMUIdx_E3; |
d3649702 PM |
3591 | break; |
3592 | case 2: | |
e1ee56ec | 3593 | g_assert(ss != ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit only */ |
04b07d29 | 3594 | /* fall through */ |
d3649702 | 3595 | case 1: |
04b07d29 | 3596 | if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) { |
d902ae75 | 3597 | mmu_idx = ARMMMUIdx_Stage1_E1_PAN; |
04b07d29 | 3598 | } else { |
d902ae75 | 3599 | mmu_idx = ARMMMUIdx_Stage1_E1; |
04b07d29 | 3600 | } |
d3649702 PM |
3601 | break; |
3602 | default: | |
3603 | g_assert_not_reached(); | |
3604 | } | |
3605 | break; | |
3606 | case 2: | |
3607 | /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ | |
3608 | switch (el) { | |
3609 | case 3: | |
d902ae75 | 3610 | mmu_idx = ARMMMUIdx_E10_0; |
d3649702 PM |
3611 | break; |
3612 | case 2: | |
e1ee56ec | 3613 | g_assert(ss != ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit only */ |
2859d7b5 | 3614 | mmu_idx = ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3615 | break; |
3616 | case 1: | |
d902ae75 | 3617 | mmu_idx = ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3618 | break; |
3619 | default: | |
3620 | g_assert_not_reached(); | |
3621 | } | |
3622 | break; | |
3623 | case 4: | |
3624 | /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ | |
01b98b68 | 3625 | mmu_idx = ARMMMUIdx_E10_1; |
e1ee56ec | 3626 | ss = ARMSS_NonSecure; |
d3649702 PM |
3627 | break; |
3628 | case 6: | |
3629 | /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ | |
01b98b68 | 3630 | mmu_idx = ARMMMUIdx_E10_0; |
e1ee56ec | 3631 | ss = ARMSS_NonSecure; |
d3649702 PM |
3632 | break; |
3633 | default: | |
3634 | g_assert_not_reached(); | |
3635 | } | |
3636 | ||
e1ee56ec | 3637 | par64 = do_ats_write(env, value, access_type, mmu_idx, ss); |
01c097f7 FA |
3638 | |
3639 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
9fb005b0 PMD |
3640 | #else |
3641 | /* Handled by hardware accelerator. */ | |
3642 | g_assert_not_reached(); | |
3643 | #endif /* CONFIG_TCG */ | |
4a501606 | 3644 | } |
060e8a48 | 3645 | |
14db7fe0 PM |
3646 | static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3647 | uint64_t value) | |
3648 | { | |
9fb005b0 | 3649 | #ifdef CONFIG_TCG |
03ae85f8 | 3650 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
14db7fe0 PM |
3651 | uint64_t par64; |
3652 | ||
7aee3cb9 | 3653 | /* There is no SecureEL2 for AArch32. */ |
e1ee56ec JPB |
3654 | par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2, |
3655 | ARMSS_NonSecure); | |
14db7fe0 PM |
3656 | |
3657 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
9fb005b0 PMD |
3658 | #else |
3659 | /* Handled by hardware accelerator. */ | |
3660 | g_assert_not_reached(); | |
3661 | #endif /* CONFIG_TCG */ | |
14db7fe0 PM |
3662 | } |
3663 | ||
1acd00ef JPB |
3664 | static CPAccessResult at_e012_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3665 | bool isread) | |
3666 | { | |
3667 | /* | |
3668 | * R_NYXTL: instruction is UNDEFINED if it applies to an Exception level | |
3669 | * lower than EL3 and the combination SCR_EL3.{NSE,NS} is reserved. This can | |
3670 | * only happen when executing at EL3 because that combination also causes an | |
3671 | * illegal exception return. We don't need to check FEAT_RME either, because | |
3672 | * scr_write() ensures that the NSE bit is not set otherwise. | |
3673 | */ | |
3674 | if ((env->cp15.scr_el3 & (SCR_NSE | SCR_NS)) == SCR_NSE) { | |
3675 | return CP_ACCESS_TRAP; | |
3676 | } | |
3677 | return CP_ACCESS_OK; | |
3678 | } | |
3679 | ||
3f208fd7 PM |
3680 | static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3681 | bool isread) | |
2a47df95 | 3682 | { |
926c1b97 RDC |
3683 | if (arm_current_el(env) == 3 && |
3684 | !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) { | |
2a47df95 PM |
3685 | return CP_ACCESS_TRAP; |
3686 | } | |
1acd00ef | 3687 | return at_e012_access(env, ri, isread); |
2a47df95 PM |
3688 | } |
3689 | ||
060e8a48 PM |
3690 | static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, |
3691 | uint64_t value) | |
3692 | { | |
9fb005b0 | 3693 | #ifdef CONFIG_TCG |
03ae85f8 | 3694 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
d3649702 | 3695 | ARMMMUIdx mmu_idx; |
638d5dbd AK |
3696 | uint64_t hcr_el2 = arm_hcr_el2_eff(env); |
3697 | bool regime_e20 = (hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE); | |
d3649702 PM |
3698 | |
3699 | switch (ri->opc2 & 6) { | |
3700 | case 0: | |
3701 | switch (ri->opc1) { | |
04b07d29 RH |
3702 | case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ |
3703 | if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) { | |
638d5dbd AK |
3704 | mmu_idx = regime_e20 ? |
3705 | ARMMMUIdx_E20_2_PAN : ARMMMUIdx_Stage1_E1_PAN; | |
04b07d29 | 3706 | } else { |
638d5dbd | 3707 | mmu_idx = regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_Stage1_E1; |
04b07d29 | 3708 | } |
d3649702 PM |
3709 | break; |
3710 | case 4: /* AT S1E2R, AT S1E2W */ | |
638d5dbd | 3711 | mmu_idx = hcr_el2 & HCR_E2H ? ARMMMUIdx_E20_2 : ARMMMUIdx_E2; |
d3649702 PM |
3712 | break; |
3713 | case 6: /* AT S1E3R, AT S1E3W */ | |
d902ae75 | 3714 | mmu_idx = ARMMMUIdx_E3; |
d3649702 PM |
3715 | break; |
3716 | default: | |
3717 | g_assert_not_reached(); | |
3718 | } | |
3719 | break; | |
3720 | case 2: /* AT S1E0R, AT S1E0W */ | |
638d5dbd | 3721 | mmu_idx = regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3722 | break; |
3723 | case 4: /* AT S12E1R, AT S12E1W */ | |
638d5dbd | 3724 | mmu_idx = regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_E10_1; |
d3649702 PM |
3725 | break; |
3726 | case 6: /* AT S12E0R, AT S12E0W */ | |
638d5dbd | 3727 | mmu_idx = regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_E10_0; |
d3649702 PM |
3728 | break; |
3729 | default: | |
3730 | g_assert_not_reached(); | |
3731 | } | |
060e8a48 | 3732 | |
7aee3cb9 | 3733 | env->cp15.par_el[1] = do_ats_write(env, value, access_type, |
e1ee56ec | 3734 | mmu_idx, arm_security_space(env)); |
9fb005b0 PMD |
3735 | #else |
3736 | /* Handled by hardware accelerator. */ | |
3737 | g_assert_not_reached(); | |
3738 | #endif /* CONFIG_TCG */ | |
060e8a48 | 3739 | } |
4a501606 PM |
3740 | #endif |
3741 | ||
18032bec PM |
3742 | /* Return basic MPU access permission bits. */ |
3743 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
3744 | { | |
3745 | uint32_t ret; | |
3746 | uint32_t mask; | |
3747 | int i; | |
3748 | ret = 0; | |
3749 | mask = 3; | |
3750 | for (i = 0; i < 16; i += 2) { | |
3751 | ret |= (val >> i) & mask; | |
3752 | mask <<= 2; | |
3753 | } | |
3754 | return ret; | |
3755 | } | |
3756 | ||
3757 | /* Pad basic MPU access permission bits to extended format. */ | |
3758 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
3759 | { | |
3760 | uint32_t ret; | |
3761 | uint32_t mask; | |
3762 | int i; | |
3763 | ret = 0; | |
3764 | mask = 3; | |
3765 | for (i = 0; i < 16; i += 2) { | |
3766 | ret |= (val & mask) << i; | |
3767 | mask <<= 2; | |
3768 | } | |
3769 | return ret; | |
3770 | } | |
3771 | ||
c4241c7d PM |
3772 | static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3773 | uint64_t value) | |
18032bec | 3774 | { |
7e09797c | 3775 | env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3776 | } |
3777 | ||
c4241c7d | 3778 | static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3779 | { |
7e09797c | 3780 | return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); |
18032bec PM |
3781 | } |
3782 | ||
c4241c7d PM |
3783 | static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3784 | uint64_t value) | |
18032bec | 3785 | { |
7e09797c | 3786 | env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3787 | } |
3788 | ||
c4241c7d | 3789 | static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3790 | { |
7e09797c | 3791 | return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); |
18032bec PM |
3792 | } |
3793 | ||
6cb0b013 PC |
3794 | static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) |
3795 | { | |
3796 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); | |
3797 | ||
3798 | if (!u32p) { | |
3799 | return 0; | |
3800 | } | |
3801 | ||
1bc04a88 | 3802 | u32p += env->pmsav7.rnr[M_REG_NS]; |
6cb0b013 PC |
3803 | return *u32p; |
3804 | } | |
3805 | ||
3806 | static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3807 | uint64_t value) | |
3808 | { | |
2fc0cc0e | 3809 | ARMCPU *cpu = env_archcpu(env); |
6cb0b013 PC |
3810 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); |
3811 | ||
3812 | if (!u32p) { | |
3813 | return; | |
3814 | } | |
3815 | ||
1bc04a88 | 3816 | u32p += env->pmsav7.rnr[M_REG_NS]; |
d10eb08f | 3817 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ |
6cb0b013 PC |
3818 | *u32p = value; |
3819 | } | |
3820 | ||
6cb0b013 PC |
3821 | static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3822 | uint64_t value) | |
3823 | { | |
2fc0cc0e | 3824 | ARMCPU *cpu = env_archcpu(env); |
6cb0b013 PC |
3825 | uint32_t nrgs = cpu->pmsav7_dregion; |
3826 | ||
3827 | if (value >= nrgs) { | |
3828 | qemu_log_mask(LOG_GUEST_ERROR, | |
3829 | "PMSAv7 RGNR write >= # supported regions, %" PRIu32 | |
3830 | " > %" PRIu32 "\n", (uint32_t)value, nrgs); | |
3831 | return; | |
3832 | } | |
3833 | ||
3834 | raw_write(env, ri, value); | |
3835 | } | |
3836 | ||
761c4642 TR |
3837 | static void prbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3838 | uint64_t value) | |
3839 | { | |
3840 | ARMCPU *cpu = env_archcpu(env); | |
3841 | ||
3842 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | |
3843 | env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value; | |
3844 | } | |
3845 | ||
3846 | static uint64_t prbar_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3847 | { | |
3848 | return env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; | |
3849 | } | |
3850 | ||
3851 | static void prlar_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3852 | uint64_t value) | |
3853 | { | |
3854 | ARMCPU *cpu = env_archcpu(env); | |
3855 | ||
3856 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | |
3857 | env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value; | |
3858 | } | |
3859 | ||
3860 | static uint64_t prlar_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3861 | { | |
3862 | return env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; | |
3863 | } | |
3864 | ||
3865 | static void prselr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3866 | uint64_t value) | |
3867 | { | |
3868 | ARMCPU *cpu = env_archcpu(env); | |
3869 | ||
3870 | /* | |
3871 | * Ignore writes that would select not implemented region. | |
3872 | * This is architecturally UNPREDICTABLE. | |
3873 | */ | |
3874 | if (value >= cpu->pmsav7_dregion) { | |
3875 | return; | |
3876 | } | |
3877 | ||
3878 | env->pmsav7.rnr[M_REG_NS] = value; | |
3879 | } | |
3880 | ||
3881 | static void hprbar_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3882 | uint64_t value) | |
3883 | { | |
3884 | ARMCPU *cpu = env_archcpu(env); | |
3885 | ||
3886 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | |
3887 | env->pmsav8.hprbar[env->pmsav8.hprselr] = value; | |
3888 | } | |
3889 | ||
3890 | static uint64_t hprbar_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3891 | { | |
3892 | return env->pmsav8.hprbar[env->pmsav8.hprselr]; | |
3893 | } | |
3894 | ||
3895 | static void hprlar_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3896 | uint64_t value) | |
3897 | { | |
3898 | ARMCPU *cpu = env_archcpu(env); | |
3899 | ||
3900 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | |
3901 | env->pmsav8.hprlar[env->pmsav8.hprselr] = value; | |
3902 | } | |
3903 | ||
3904 | static uint64_t hprlar_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3905 | { | |
3906 | return env->pmsav8.hprlar[env->pmsav8.hprselr]; | |
3907 | } | |
3908 | ||
3909 | static void hprenr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3910 | uint64_t value) | |
3911 | { | |
3912 | uint32_t n; | |
3913 | uint32_t bit; | |
3914 | ARMCPU *cpu = env_archcpu(env); | |
3915 | ||
3916 | /* Ignore writes to unimplemented regions */ | |
3917 | int rmax = MIN(cpu->pmsav8r_hdregion, 32); | |
3918 | value &= MAKE_64BIT_MASK(0, rmax); | |
3919 | ||
3920 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | |
3921 | ||
3922 | /* Register alias is only valid for first 32 indexes */ | |
3923 | for (n = 0; n < rmax; ++n) { | |
3924 | bit = extract32(value, n, 1); | |
3925 | env->pmsav8.hprlar[n] = deposit32( | |
3926 | env->pmsav8.hprlar[n], 0, 1, bit); | |
3927 | } | |
3928 | } | |
3929 | ||
3930 | static uint64_t hprenr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3931 | { | |
3932 | uint32_t n; | |
3933 | uint32_t result = 0x0; | |
3934 | ARMCPU *cpu = env_archcpu(env); | |
3935 | ||
3936 | /* Register alias is only valid for first 32 indexes */ | |
3937 | for (n = 0; n < MIN(cpu->pmsav8r_hdregion, 32); ++n) { | |
3938 | if (env->pmsav8.hprlar[n] & 0x1) { | |
3939 | result |= (0x1 << n); | |
3940 | } | |
3941 | } | |
3942 | return result; | |
3943 | } | |
3944 | ||
3945 | static void hprselr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3946 | uint64_t value) | |
3947 | { | |
3948 | ARMCPU *cpu = env_archcpu(env); | |
3949 | ||
3950 | /* | |
3951 | * Ignore writes that would select not implemented region. | |
3952 | * This is architecturally UNPREDICTABLE. | |
3953 | */ | |
3954 | if (value >= cpu->pmsav8r_hdregion) { | |
3955 | return; | |
3956 | } | |
3957 | ||
3958 | env->pmsav8.hprselr = value; | |
3959 | } | |
3960 | ||
3961 | static void pmsav8r_regn_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3962 | uint64_t value) | |
3963 | { | |
3964 | ARMCPU *cpu = env_archcpu(env); | |
3965 | uint8_t index = (extract32(ri->opc0, 0, 1) << 4) | | |
3966 | (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1); | |
3967 | ||
3968 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | |
3969 | ||
3970 | if (ri->opc1 & 4) { | |
3971 | if (index >= cpu->pmsav8r_hdregion) { | |
3972 | return; | |
3973 | } | |
3974 | if (ri->opc2 & 0x1) { | |
3975 | env->pmsav8.hprlar[index] = value; | |
3976 | } else { | |
3977 | env->pmsav8.hprbar[index] = value; | |
3978 | } | |
3979 | } else { | |
3980 | if (index >= cpu->pmsav7_dregion) { | |
3981 | return; | |
3982 | } | |
3983 | if (ri->opc2 & 0x1) { | |
3984 | env->pmsav8.rlar[M_REG_NS][index] = value; | |
3985 | } else { | |
3986 | env->pmsav8.rbar[M_REG_NS][index] = value; | |
3987 | } | |
3988 | } | |
3989 | } | |
3990 | ||
3991 | static uint64_t pmsav8r_regn_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3992 | { | |
3993 | ARMCPU *cpu = env_archcpu(env); | |
3994 | uint8_t index = (extract32(ri->opc0, 0, 1) << 4) | | |
3995 | (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1); | |
3996 | ||
3997 | if (ri->opc1 & 4) { | |
3998 | if (index >= cpu->pmsav8r_hdregion) { | |
3999 | return 0x0; | |
4000 | } | |
4001 | if (ri->opc2 & 0x1) { | |
4002 | return env->pmsav8.hprlar[index]; | |
4003 | } else { | |
4004 | return env->pmsav8.hprbar[index]; | |
4005 | } | |
4006 | } else { | |
4007 | if (index >= cpu->pmsav7_dregion) { | |
4008 | return 0x0; | |
4009 | } | |
4010 | if (ri->opc2 & 0x1) { | |
4011 | return env->pmsav8.rlar[M_REG_NS][index]; | |
4012 | } else { | |
4013 | return env->pmsav8.rbar[M_REG_NS][index]; | |
4014 | } | |
4015 | } | |
4016 | } | |
4017 | ||
4018 | static const ARMCPRegInfo pmsav8r_cp_reginfo[] = { | |
4019 | { .name = "PRBAR", | |
4020 | .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 0, | |
4021 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
4022 | .accessfn = access_tvm_trvm, | |
4023 | .readfn = prbar_read, .writefn = prbar_write }, | |
4024 | { .name = "PRLAR", | |
4025 | .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 1, | |
4026 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
4027 | .accessfn = access_tvm_trvm, | |
4028 | .readfn = prlar_read, .writefn = prlar_write }, | |
4029 | { .name = "PRSELR", .resetvalue = 0, | |
4030 | .cp = 15, .opc1 = 0, .crn = 6, .crm = 2, .opc2 = 1, | |
4031 | .access = PL1_RW, .accessfn = access_tvm_trvm, | |
4032 | .writefn = prselr_write, | |
4033 | .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]) }, | |
4034 | { .name = "HPRBAR", .resetvalue = 0, | |
4035 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 0, | |
4036 | .access = PL2_RW, .type = ARM_CP_NO_RAW, | |
4037 | .readfn = hprbar_read, .writefn = hprbar_write }, | |
4038 | { .name = "HPRLAR", | |
4039 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 1, | |
4040 | .access = PL2_RW, .type = ARM_CP_NO_RAW, | |
4041 | .readfn = hprlar_read, .writefn = hprlar_write }, | |
4042 | { .name = "HPRSELR", .resetvalue = 0, | |
4043 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 2, .opc2 = 1, | |
4044 | .access = PL2_RW, | |
4045 | .writefn = hprselr_write, | |
4046 | .fieldoffset = offsetof(CPUARMState, pmsav8.hprselr) }, | |
4047 | { .name = "HPRENR", | |
4048 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 1, .opc2 = 1, | |
4049 | .access = PL2_RW, .type = ARM_CP_NO_RAW, | |
4050 | .readfn = hprenr_read, .writefn = hprenr_write }, | |
4051 | }; | |
4052 | ||
6cb0b013 | 4053 | static const ARMCPRegInfo pmsav7_cp_reginfo[] = { |
9b37a28c FR |
4054 | /* |
4055 | * Reset for all these registers is handled in arm_cpu_reset(), | |
69ceea64 PM |
4056 | * because the PMSAv7 is also used by M-profile CPUs, which do |
4057 | * not register cpregs but still need the state to be reset. | |
4058 | */ | |
6cb0b013 PC |
4059 | { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, |
4060 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
4061 | .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), | |
69ceea64 PM |
4062 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
4063 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
4064 | { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, |
4065 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
4066 | .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), | |
69ceea64 PM |
4067 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
4068 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
4069 | { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, |
4070 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
4071 | .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), | |
69ceea64 PM |
4072 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
4073 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
4074 | { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, |
4075 | .access = PL1_RW, | |
1bc04a88 | 4076 | .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), |
69ceea64 PM |
4077 | .writefn = pmsav7_rgnr_write, |
4078 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
4079 | }; |
4080 | ||
18032bec PM |
4081 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { |
4082 | { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 4083 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 4084 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
18032bec PM |
4085 | .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, |
4086 | { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 4087 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 4088 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
18032bec PM |
4089 | .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, |
4090 | { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, | |
4091 | .access = PL1_RW, | |
7e09797c PM |
4092 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
4093 | .resetvalue = 0, }, | |
18032bec PM |
4094 | { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, |
4095 | .access = PL1_RW, | |
7e09797c PM |
4096 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
4097 | .resetvalue = 0, }, | |
ecce5c3c PM |
4098 | { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
4099 | .access = PL1_RW, | |
4100 | .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, | |
4101 | { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
4102 | .access = PL1_RW, | |
4103 | .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, | |
06d76f31 | 4104 | /* Protection region base and size registers */ |
e508a92b PM |
4105 | { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, |
4106 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4107 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, | |
4108 | { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, | |
4109 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4110 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, | |
4111 | { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, | |
4112 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4113 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, | |
4114 | { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, | |
4115 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4116 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, | |
4117 | { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, | |
4118 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4119 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, | |
4120 | { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, | |
4121 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4122 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, | |
4123 | { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, | |
4124 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4125 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, | |
4126 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | |
4127 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4128 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | |
18032bec PM |
4129 | }; |
4130 | ||
cb4a0a34 PM |
4131 | static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4132 | uint64_t value) | |
ecce5c3c | 4133 | { |
cb4a0a34 | 4134 | ARMCPU *cpu = env_archcpu(env); |
2ebcebe2 | 4135 | |
e389be16 FA |
4136 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
4137 | if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { | |
cb4a0a34 PM |
4138 | /* |
4139 | * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when | |
4140 | * using Long-descriptor translation table format | |
4141 | */ | |
e389be16 FA |
4142 | value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); |
4143 | } else if (arm_feature(env, ARM_FEATURE_EL3)) { | |
cb4a0a34 PM |
4144 | /* |
4145 | * In an implementation that includes the Security Extensions | |
e389be16 FA |
4146 | * TTBCR has additional fields PD0 [4] and PD1 [5] for |
4147 | * Short-descriptor translation table format. | |
4148 | */ | |
4149 | value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; | |
4150 | } else { | |
4151 | value &= TTBCR_N; | |
4152 | } | |
e42c4db3 | 4153 | } |
e389be16 | 4154 | |
d4e6df63 | 4155 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
9b37a28c FR |
4156 | /* |
4157 | * With LPAE the TTBCR could result in a change of ASID | |
d4e6df63 PM |
4158 | * via the TTBCR.A1 bit, so do a TLB flush. |
4159 | */ | |
d10eb08f | 4160 | tlb_flush(CPU(cpu)); |
d4e6df63 | 4161 | } |
cb4a0a34 | 4162 | raw_write(env, ri, value); |
ecce5c3c PM |
4163 | } |
4164 | ||
d06dc933 | 4165 | static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, |
cb2e37df PM |
4166 | uint64_t value) |
4167 | { | |
2fc0cc0e | 4168 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 4169 | |
cb2e37df | 4170 | /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ |
d10eb08f | 4171 | tlb_flush(CPU(cpu)); |
cb4a0a34 | 4172 | raw_write(env, ri, value); |
cb2e37df PM |
4173 | } |
4174 | ||
327ed10f PM |
4175 | static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4176 | uint64_t value) | |
4177 | { | |
93f379b0 RH |
4178 | /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ |
4179 | if (cpreg_field_is_64bit(ri) && | |
4180 | extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { | |
2fc0cc0e | 4181 | ARMCPU *cpu = env_archcpu(env); |
d10eb08f | 4182 | tlb_flush(CPU(cpu)); |
327ed10f PM |
4183 | } |
4184 | raw_write(env, ri, value); | |
4185 | } | |
4186 | ||
ed30da8e RH |
4187 | static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4188 | uint64_t value) | |
4189 | { | |
d06dc933 RH |
4190 | /* |
4191 | * If we are running with E2&0 regime, then an ASID is active. | |
4192 | * Flush if that might be changing. Note we're not checking | |
4193 | * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that | |
4194 | * holds the active ASID, only checking the field that might. | |
4195 | */ | |
4196 | if (extract64(raw_read(env, ri) ^ value, 48, 16) && | |
4197 | (arm_hcr_el2_eff(env) & HCR_E2H)) { | |
b6ad6062 RDC |
4198 | uint16_t mask = ARMMMUIdxBit_E20_2 | |
4199 | ARMMMUIdxBit_E20_2_PAN | | |
4200 | ARMMMUIdxBit_E20_0; | |
b6ad6062 | 4201 | tlb_flush_by_mmuidx(env_cpu(env), mask); |
d06dc933 | 4202 | } |
ed30da8e RH |
4203 | raw_write(env, ri, value); |
4204 | } | |
4205 | ||
b698e9cf EI |
4206 | static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4207 | uint64_t value) | |
4208 | { | |
2fc0cc0e | 4209 | ARMCPU *cpu = env_archcpu(env); |
b698e9cf EI |
4210 | CPUState *cs = CPU(cpu); |
4211 | ||
97fa9350 RH |
4212 | /* |
4213 | * A change in VMID to the stage2 page table (Stage2) invalidates | |
575a94af | 4214 | * the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0). |
97fa9350 | 4215 | */ |
00b20ee4 | 4216 | if (extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { |
575a94af | 4217 | tlb_flush_by_mmuidx(cs, alle1_tlbmask(env)); |
b698e9cf | 4218 | } |
00b20ee4 | 4219 | raw_write(env, ri, value); |
b698e9cf EI |
4220 | } |
4221 | ||
8e5d75c9 | 4222 | static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { |
18032bec | 4223 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, |
84929218 | 4224 | .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS, |
4a7e2d73 | 4225 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), |
b061a82b | 4226 | offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, |
18032bec | 4227 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, |
84929218 | 4228 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
88ca1c2d FA |
4229 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), |
4230 | offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, | |
8e5d75c9 | 4231 | { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, |
84929218 | 4232 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
8e5d75c9 PC |
4233 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), |
4234 | offsetof(CPUARMState, cp15.dfar_ns) } }, | |
4235 | { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, | |
4236 | .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, | |
84929218 | 4237 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
b19ed03c | 4238 | .fgt = FGT_FAR_EL1, |
84929218 | 4239 | .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), |
8e5d75c9 | 4240 | .resetvalue = 0, }, |
8e5d75c9 PC |
4241 | }; |
4242 | ||
4243 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { | |
6cd8a264 RH |
4244 | { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, |
4245 | .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, | |
84929218 | 4246 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
b19ed03c | 4247 | .fgt = FGT_ESR_EL1, |
d81c519c | 4248 | .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, |
327ed10f | 4249 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af | 4250 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, |
84929218 | 4251 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
bd8db7d9 | 4252 | .fgt = FGT_TTBR0_EL1, |
587f8b33 | 4253 | .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write, |
7dd8c9af FA |
4254 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
4255 | offsetof(CPUARMState, cp15.ttbr0_ns) } }, | |
327ed10f | 4256 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af | 4257 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, |
84929218 | 4258 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
bd8db7d9 | 4259 | .fgt = FGT_TTBR1_EL1, |
587f8b33 | 4260 | .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write, |
7dd8c9af FA |
4261 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
4262 | offsetof(CPUARMState, cp15.ttbr1_ns) } }, | |
cb2e37df PM |
4263 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, |
4264 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | |
84929218 | 4265 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
67dd8030 | 4266 | .fgt = FGT_TCR_EL1, |
84929218 | 4267 | .writefn = vmsa_tcr_el12_write, |
cb4a0a34 PM |
4268 | .raw_writefn = raw_write, |
4269 | .resetvalue = 0, | |
11f136ee | 4270 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, |
cb2e37df | 4271 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
84929218 RH |
4272 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4273 | .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, | |
cb4a0a34 PM |
4274 | .raw_writefn = raw_write, |
4275 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), | |
4276 | offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, | |
18032bec PM |
4277 | }; |
4278 | ||
9b37a28c FR |
4279 | /* |
4280 | * Note that unlike TTBCR, writing to TTBCR2 does not require flushing | |
ab638a32 RH |
4281 | * qemu tlbs nor adjusting cached masks. |
4282 | */ | |
4283 | static const ARMCPRegInfo ttbcr2_reginfo = { | |
4284 | .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3, | |
84929218 RH |
4285 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4286 | .type = ARM_CP_ALIAS, | |
d102058e | 4287 | .bank_fieldoffsets = { |
cb4a0a34 PM |
4288 | offsetofhigh32(CPUARMState, cp15.tcr_el[3]), |
4289 | offsetofhigh32(CPUARMState, cp15.tcr_el[1]), | |
d102058e | 4290 | }, |
ab638a32 RH |
4291 | }; |
4292 | ||
c4241c7d PM |
4293 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4294 | uint64_t value) | |
1047b9d7 PM |
4295 | { |
4296 | env->cp15.c15_ticonfig = value & 0xe7; | |
4297 | /* The OS_TYPE bit in this register changes the reported CPUID! */ | |
4298 | env->cp15.c0_cpuid = (value & (1 << 5)) ? | |
4299 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1047b9d7 PM |
4300 | } |
4301 | ||
c4241c7d PM |
4302 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4303 | uint64_t value) | |
1047b9d7 PM |
4304 | { |
4305 | env->cp15.c15_threadid = value & 0xffff; | |
1047b9d7 PM |
4306 | } |
4307 | ||
c4241c7d PM |
4308 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4309 | uint64_t value) | |
1047b9d7 PM |
4310 | { |
4311 | /* Wait-for-interrupt (deprecated) */ | |
2fc0cc0e | 4312 | cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); |
1047b9d7 PM |
4313 | } |
4314 | ||
c4241c7d PM |
4315 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4316 | uint64_t value) | |
c4804214 | 4317 | { |
9b37a28c FR |
4318 | /* |
4319 | * On OMAP there are registers indicating the max/min index of dcache lines | |
c4804214 PM |
4320 | * containing a dirty line; cache flush operations have to reset these. |
4321 | */ | |
4322 | env->cp15.c15_i_max = 0x000; | |
4323 | env->cp15.c15_i_min = 0xff0; | |
c4804214 PM |
4324 | } |
4325 | ||
18032bec PM |
4326 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
4327 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, | |
4328 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, | |
d81c519c | 4329 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 4330 | .resetvalue = 0, }, |
1047b9d7 PM |
4331 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
4332 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
4333 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
4334 | .access = PL1_RW, | |
4335 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, | |
4336 | .writefn = omap_ticonfig_write }, | |
4337 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, | |
4338 | .access = PL1_RW, | |
4339 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, | |
4340 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, | |
4341 | .access = PL1_RW, .resetvalue = 0xff0, | |
4342 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, | |
4343 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, | |
4344 | .access = PL1_RW, | |
4345 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, | |
4346 | .writefn = omap_threadid_write }, | |
4347 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, | |
4348 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
7a0e58fa | 4349 | .type = ARM_CP_NO_RAW, |
1047b9d7 | 4350 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
9b37a28c FR |
4351 | /* |
4352 | * TODO: Peripheral port remap register: | |
1047b9d7 PM |
4353 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller |
4354 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), | |
4355 | * when MMU is off. | |
4356 | */ | |
c4804214 | 4357 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
d4e6df63 | 4358 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
7a0e58fa | 4359 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, |
c4804214 | 4360 | .writefn = omap_cachemaint_write }, |
34f90529 PM |
4361 | { .name = "C9", .cp = 15, .crn = 9, |
4362 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | |
4363 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | |
1047b9d7 PM |
4364 | }; |
4365 | ||
c4241c7d PM |
4366 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4367 | uint64_t value) | |
1047b9d7 | 4368 | { |
c0f4af17 | 4369 | env->cp15.c15_cpar = value & 0x3fff; |
1047b9d7 PM |
4370 | } |
4371 | ||
4372 | static const ARMCPRegInfo xscale_cp_reginfo[] = { | |
4373 | { .name = "XSCALE_CPAR", | |
4374 | .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
4375 | .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, | |
4376 | .writefn = xscale_cpar_write, }, | |
2771db27 PM |
4377 | { .name = "XSCALE_AUXCR", |
4378 | .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, | |
4379 | .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), | |
4380 | .resetvalue = 0, }, | |
9b37a28c FR |
4381 | /* |
4382 | * XScale specific cache-lockdown: since we have no cache we NOP these | |
3b771579 PM |
4383 | * and hope the guest does not really rely on cache behaviour. |
4384 | */ | |
4385 | { .name = "XSCALE_LOCK_ICACHE_LINE", | |
4386 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
4387 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4388 | { .name = "XSCALE_UNLOCK_ICACHE", | |
4389 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
4390 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4391 | { .name = "XSCALE_DCACHE_LOCK", | |
4392 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, | |
4393 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
4394 | { .name = "XSCALE_UNLOCK_DCACHE", | |
4395 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, | |
4396 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1047b9d7 PM |
4397 | }; |
4398 | ||
4399 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | |
9b37a28c FR |
4400 | /* |
4401 | * RAZ/WI the whole crn=15 space, when we don't have a more specific | |
1047b9d7 PM |
4402 | * implementation of this implementation-defined space. |
4403 | * Ideally this should eventually disappear in favour of actually | |
4404 | * implementing the correct behaviour for all cores. | |
4405 | */ | |
4406 | { .name = "C15_IMPDEF", .cp = 15, .crn = 15, | |
4407 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
3671cd87 | 4408 | .access = PL1_RW, |
7a0e58fa | 4409 | .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, |
d4e6df63 | 4410 | .resetvalue = 0 }, |
18032bec PM |
4411 | }; |
4412 | ||
c4804214 PM |
4413 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
4414 | /* Cache status: RAZ because we have no cache so it's always clean */ | |
4415 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | |
7a0e58fa | 4416 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4417 | .resetvalue = 0 }, |
c4804214 PM |
4418 | }; |
4419 | ||
4420 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | |
a07d9df0 | 4421 | /* We never have a block transfer operation in progress */ |
c4804214 | 4422 | { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, |
7a0e58fa | 4423 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4424 | .resetvalue = 0 }, |
30b05bba PM |
4425 | /* The cache ops themselves: these all NOP for QEMU */ |
4426 | { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, | |
04215eb1 | 4427 | .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, |
30b05bba | 4428 | { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, |
04215eb1 | 4429 | .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, |
30b05bba | 4430 | { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, |
04215eb1 | 4431 | .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, |
30b05bba | 4432 | { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, |
04215eb1 | 4433 | .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, |
30b05bba | 4434 | { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, |
04215eb1 | 4435 | .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, |
30b05bba | 4436 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, |
04215eb1 | 4437 | .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, |
c4804214 PM |
4438 | }; |
4439 | ||
4440 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | |
9b37a28c FR |
4441 | /* |
4442 | * The cache test-and-clean instructions always return (1 << 30) | |
c4804214 PM |
4443 | * to indicate that there are no dirty cache lines. |
4444 | */ | |
4445 | { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, | |
7a0e58fa | 4446 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4447 | .resetvalue = (1 << 30) }, |
c4804214 | 4448 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
7a0e58fa | 4449 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4450 | .resetvalue = (1 << 30) }, |
c4804214 PM |
4451 | }; |
4452 | ||
34f90529 PM |
4453 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
4454 | /* Ignore ReadBuffer accesses */ | |
4455 | { .name = "C9_READBUFFER", .cp = 15, .crn = 9, | |
4456 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
d4e6df63 | 4457 | .access = PL1_RW, .resetvalue = 0, |
7a0e58fa | 4458 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, |
34f90529 PM |
4459 | }; |
4460 | ||
731de9e6 EI |
4461 | static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4462 | { | |
731de9e6 | 4463 | unsigned int cur_el = arm_current_el(env); |
731de9e6 | 4464 | |
e6ef0169 | 4465 | if (arm_is_el2_enabled(env) && cur_el == 1) { |
731de9e6 EI |
4466 | return env->cp15.vpidr_el2; |
4467 | } | |
4468 | return raw_read(env, ri); | |
4469 | } | |
4470 | ||
06a7e647 | 4471 | static uint64_t mpidr_read_val(CPUARMState *env) |
81bdde9d | 4472 | { |
2fc0cc0e | 4473 | ARMCPU *cpu = env_archcpu(env); |
eb5e1d3c PF |
4474 | uint64_t mpidr = cpu->mp_affinity; |
4475 | ||
81bdde9d | 4476 | if (arm_feature(env, ARM_FEATURE_V7MP)) { |
78dbbbe4 | 4477 | mpidr |= (1U << 31); |
9b37a28c FR |
4478 | /* |
4479 | * Cores which are uniprocessor (non-coherent) | |
81bdde9d | 4480 | * but still implement the MP extensions set |
a8e81b31 | 4481 | * bit 30. (For instance, Cortex-R5). |
81bdde9d | 4482 | */ |
a8e81b31 PC |
4483 | if (cpu->mp_is_up) { |
4484 | mpidr |= (1u << 30); | |
4485 | } | |
81bdde9d | 4486 | } |
c4241c7d | 4487 | return mpidr; |
81bdde9d PM |
4488 | } |
4489 | ||
06a7e647 EI |
4490 | static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4491 | { | |
f0d574d6 | 4492 | unsigned int cur_el = arm_current_el(env); |
f0d574d6 | 4493 | |
e6ef0169 | 4494 | if (arm_is_el2_enabled(env) && cur_el == 1) { |
f0d574d6 EI |
4495 | return env->cp15.vmpidr_el2; |
4496 | } | |
06a7e647 EI |
4497 | return mpidr_read_val(env); |
4498 | } | |
4499 | ||
7ac681cf | 4500 | static const ARMCPRegInfo lpae_cp_reginfo[] = { |
a903c449 | 4501 | /* NOP AMAIR0/1 */ |
b0fe2427 PM |
4502 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, |
4503 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | |
84929218 | 4504 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
158c276c | 4505 | .fgt = FGT_AMAIR_EL1, |
84929218 | 4506 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
b0fe2427 | 4507 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ |
7ac681cf | 4508 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
84929218 RH |
4509 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4510 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
891a2fe7 | 4511 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
01c097f7 FA |
4512 | .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, |
4513 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), | |
4514 | offsetof(CPUARMState, cp15.par_ns)} }, | |
891a2fe7 | 4515 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, |
84929218 RH |
4516 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4517 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
7dd8c9af FA |
4518 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
4519 | offsetof(CPUARMState, cp15.ttbr0_ns) }, | |
587f8b33 | 4520 | .writefn = vmsa_ttbr_write, .raw_writefn = raw_write }, |
891a2fe7 | 4521 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
84929218 RH |
4522 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4523 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
7dd8c9af FA |
4524 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
4525 | offsetof(CPUARMState, cp15.ttbr1_ns) }, | |
587f8b33 | 4526 | .writefn = vmsa_ttbr_write, .raw_writefn = raw_write }, |
7ac681cf PM |
4527 | }; |
4528 | ||
c4241c7d | 4529 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 4530 | { |
c4241c7d | 4531 | return vfp_get_fpcr(env); |
b0d2b7d0 PM |
4532 | } |
4533 | ||
c4241c7d PM |
4534 | static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4535 | uint64_t value) | |
b0d2b7d0 PM |
4536 | { |
4537 | vfp_set_fpcr(env, value); | |
b0d2b7d0 PM |
4538 | } |
4539 | ||
c4241c7d | 4540 | static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 4541 | { |
c4241c7d | 4542 | return vfp_get_fpsr(env); |
b0d2b7d0 PM |
4543 | } |
4544 | ||
c4241c7d PM |
4545 | static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4546 | uint64_t value) | |
b0d2b7d0 PM |
4547 | { |
4548 | vfp_set_fpsr(env, value); | |
b0d2b7d0 PM |
4549 | } |
4550 | ||
3f208fd7 PM |
4551 | static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4552 | bool isread) | |
c2b820fe | 4553 | { |
aaec1432 | 4554 | if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { |
c2b820fe PM |
4555 | return CP_ACCESS_TRAP; |
4556 | } | |
4557 | return CP_ACCESS_OK; | |
4558 | } | |
4559 | ||
4560 | static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4561 | uint64_t value) | |
4562 | { | |
4563 | env->daif = value & PSTATE_DAIF; | |
4564 | } | |
4565 | ||
220f508f RH |
4566 | static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4567 | { | |
4568 | return env->pstate & PSTATE_PAN; | |
4569 | } | |
4570 | ||
4571 | static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4572 | uint64_t value) | |
4573 | { | |
4574 | env->pstate = (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN); | |
4575 | } | |
4576 | ||
4577 | static const ARMCPRegInfo pan_reginfo = { | |
4578 | .name = "PAN", .state = ARM_CP_STATE_AA64, | |
4579 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 3, | |
4580 | .type = ARM_CP_NO_RAW, .access = PL1_RW, | |
4581 | .readfn = aa64_pan_read, .writefn = aa64_pan_write | |
4582 | }; | |
4583 | ||
9eeb7a1c RH |
4584 | static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4585 | { | |
4586 | return env->pstate & PSTATE_UAO; | |
4587 | } | |
4588 | ||
4589 | static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4590 | uint64_t value) | |
4591 | { | |
4592 | env->pstate = (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO); | |
4593 | } | |
4594 | ||
4595 | static const ARMCPRegInfo uao_reginfo = { | |
4596 | .name = "UAO", .state = ARM_CP_STATE_AA64, | |
4597 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4, | |
4598 | .type = ARM_CP_NO_RAW, .access = PL1_RW, | |
4599 | .readfn = aa64_uao_read, .writefn = aa64_uao_write | |
4600 | }; | |
4601 | ||
dc8b1853 RC |
4602 | static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4603 | { | |
4604 | return env->pstate & PSTATE_DIT; | |
4605 | } | |
4606 | ||
4607 | static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4608 | uint64_t value) | |
4609 | { | |
4610 | env->pstate = (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT); | |
4611 | } | |
4612 | ||
4613 | static const ARMCPRegInfo dit_reginfo = { | |
4614 | .name = "DIT", .state = ARM_CP_STATE_AA64, | |
4615 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 5, | |
4616 | .type = ARM_CP_NO_RAW, .access = PL0_RW, | |
4617 | .readfn = aa64_dit_read, .writefn = aa64_dit_write | |
4618 | }; | |
4619 | ||
f2f68a78 RC |
4620 | static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4621 | { | |
4622 | return env->pstate & PSTATE_SSBS; | |
4623 | } | |
4624 | ||
4625 | static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4626 | uint64_t value) | |
4627 | { | |
4628 | env->pstate = (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS); | |
4629 | } | |
4630 | ||
4631 | static const ARMCPRegInfo ssbs_reginfo = { | |
4632 | .name = "SSBS", .state = ARM_CP_STATE_AA64, | |
4633 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 6, | |
4634 | .type = ARM_CP_NO_RAW, .access = PL0_RW, | |
4635 | .readfn = aa64_ssbs_read, .writefn = aa64_ssbs_write | |
4636 | }; | |
4637 | ||
38262d8a RH |
4638 | static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, |
4639 | const ARMCPRegInfo *ri, | |
4640 | bool isread) | |
8af35c37 | 4641 | { |
38262d8a RH |
4642 | /* Cache invalidate/clean to Point of Coherency or Persistence... */ |
4643 | switch (arm_current_el(env)) { | |
4644 | case 0: | |
4645 | /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ | |
4646 | if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { | |
4647 | return CP_ACCESS_TRAP; | |
4648 | } | |
4649 | /* fall through */ | |
4650 | case 1: | |
4651 | /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */ | |
4652 | if (arm_hcr_el2_eff(env) & HCR_TPCP) { | |
4653 | return CP_ACCESS_TRAP_EL2; | |
4654 | } | |
4655 | break; | |
8af35c37 PM |
4656 | } |
4657 | return CP_ACCESS_OK; | |
4658 | } | |
4659 | ||
2d3ce4c6 | 4660 | static CPAccessResult do_cacheop_pou_access(CPUARMState *env, uint64_t hcrflags) |
1bed4d2e | 4661 | { |
38262d8a | 4662 | /* Cache invalidate/clean to Point of Unification... */ |
1bed4d2e RH |
4663 | switch (arm_current_el(env)) { |
4664 | case 0: | |
4665 | /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ | |
4666 | if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { | |
4667 | return CP_ACCESS_TRAP; | |
4668 | } | |
4669 | /* fall through */ | |
4670 | case 1: | |
2d3ce4c6 PM |
4671 | /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */ |
4672 | if (arm_hcr_el2_eff(env) & hcrflags) { | |
1bed4d2e RH |
4673 | return CP_ACCESS_TRAP_EL2; |
4674 | } | |
4675 | break; | |
4676 | } | |
4677 | return CP_ACCESS_OK; | |
4678 | } | |
4679 | ||
2d3ce4c6 PM |
4680 | static CPAccessResult access_ticab(CPUARMState *env, const ARMCPRegInfo *ri, |
4681 | bool isread) | |
4682 | { | |
4683 | return do_cacheop_pou_access(env, HCR_TICAB | HCR_TPU); | |
4684 | } | |
4685 | ||
4686 | static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri, | |
4687 | bool isread) | |
4688 | { | |
4689 | return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU); | |
4690 | } | |
4691 | ||
9b37a28c FR |
4692 | /* |
4693 | * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions | |
dbb1fb27 AB |
4694 | * Page D4-1736 (DDI0487A.b) |
4695 | */ | |
4696 | ||
b7e0730d RH |
4697 | static int vae1_tlbmask(CPUARMState *env) |
4698 | { | |
e04a5752 | 4699 | uint64_t hcr = arm_hcr_el2_eff(env); |
bc944d3a | 4700 | uint16_t mask; |
e04a5752 RDC |
4701 | |
4702 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
bc944d3a RDC |
4703 | mask = ARMMMUIdxBit_E20_2 | |
4704 | ARMMMUIdxBit_E20_2_PAN | | |
4705 | ARMMMUIdxBit_E20_0; | |
b7e0730d | 4706 | } else { |
bc944d3a | 4707 | mask = ARMMMUIdxBit_E10_1 | |
452ef8cb RH |
4708 | ARMMMUIdxBit_E10_1_PAN | |
4709 | ARMMMUIdxBit_E10_0; | |
b7e0730d | 4710 | } |
bc944d3a | 4711 | return mask; |
b7e0730d RH |
4712 | } |
4713 | ||
ceaa9746 JPB |
4714 | static int vae2_tlbmask(CPUARMState *env) |
4715 | { | |
4716 | uint64_t hcr = arm_hcr_el2_eff(env); | |
4717 | uint16_t mask; | |
4718 | ||
4719 | if (hcr & HCR_E2H) { | |
4720 | mask = ARMMMUIdxBit_E20_2 | | |
4721 | ARMMMUIdxBit_E20_2_PAN | | |
4722 | ARMMMUIdxBit_E20_0; | |
4723 | } else { | |
4724 | mask = ARMMMUIdxBit_E2; | |
4725 | } | |
4726 | return mask; | |
4727 | } | |
4728 | ||
ea04dce7 RH |
4729 | /* Return 56 if TBI is enabled, 64 otherwise. */ |
4730 | static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, | |
4731 | uint64_t addr) | |
4732 | { | |
c1547bba | 4733 | uint64_t tcr = regime_tcr(env, mmu_idx); |
ea04dce7 RH |
4734 | int tbi = aa64_va_parameter_tbi(tcr, mmu_idx); |
4735 | int select = extract64(addr, 55, 1); | |
4736 | ||
4737 | return (tbi >> select) & 1 ? 56 : 64; | |
4738 | } | |
4739 | ||
4740 | static int vae1_tlbbits(CPUARMState *env, uint64_t addr) | |
4741 | { | |
b6ad6062 | 4742 | uint64_t hcr = arm_hcr_el2_eff(env); |
ea04dce7 RH |
4743 | ARMMMUIdx mmu_idx; |
4744 | ||
4745 | /* Only the regime of the mmu_idx below is significant. */ | |
b6ad6062 | 4746 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { |
ea04dce7 RH |
4747 | mmu_idx = ARMMMUIdx_E20_0; |
4748 | } else { | |
4749 | mmu_idx = ARMMMUIdx_E10_0; | |
4750 | } | |
b6ad6062 | 4751 | |
ea04dce7 RH |
4752 | return tlbbits_for_regime(env, mmu_idx, addr); |
4753 | } | |
4754 | ||
ceaa9746 JPB |
4755 | static int vae2_tlbbits(CPUARMState *env, uint64_t addr) |
4756 | { | |
4757 | uint64_t hcr = arm_hcr_el2_eff(env); | |
4758 | ARMMMUIdx mmu_idx; | |
4759 | ||
4760 | /* | |
4761 | * Only the regime of the mmu_idx below is significant. | |
4762 | * Regime EL2&0 has two ranges with separate TBI configuration, while EL2 | |
4763 | * only has one. | |
4764 | */ | |
4765 | if (hcr & HCR_E2H) { | |
4766 | mmu_idx = ARMMMUIdx_E20_2; | |
4767 | } else { | |
4768 | mmu_idx = ARMMMUIdx_E2; | |
4769 | } | |
4770 | ||
4771 | return tlbbits_for_regime(env, mmu_idx, addr); | |
4772 | } | |
4773 | ||
fd3ed969 PM |
4774 | static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4775 | uint64_t value) | |
168aa23b | 4776 | { |
29a0af61 | 4777 | CPUState *cs = env_cpu(env); |
b7e0730d | 4778 | int mask = vae1_tlbmask(env); |
dbb1fb27 | 4779 | |
b7e0730d | 4780 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
168aa23b PM |
4781 | } |
4782 | ||
b4ab8ce9 PM |
4783 | static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4784 | uint64_t value) | |
4785 | { | |
29a0af61 | 4786 | CPUState *cs = env_cpu(env); |
b7e0730d | 4787 | int mask = vae1_tlbmask(env); |
b4ab8ce9 PM |
4788 | |
4789 | if (tlb_force_broadcast(env)) { | |
527db2be RH |
4790 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
4791 | } else { | |
4792 | tlb_flush_by_mmuidx(cs, mask); | |
b4ab8ce9 | 4793 | } |
b4ab8ce9 PM |
4794 | } |
4795 | ||
85d0dc9f RH |
4796 | static int e2_tlbmask(CPUARMState *env) |
4797 | { | |
d902ae75 RH |
4798 | return (ARMMMUIdxBit_E20_0 | |
4799 | ARMMMUIdxBit_E20_2 | | |
4800 | ARMMMUIdxBit_E20_2_PAN | | |
4801 | ARMMMUIdxBit_E2); | |
85d0dc9f RH |
4802 | } |
4803 | ||
90c19cdf RH |
4804 | static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4805 | uint64_t value) | |
4806 | { | |
4807 | CPUState *cs = env_cpu(env); | |
4808 | int mask = alle1_tlbmask(env); | |
4809 | ||
4810 | tlb_flush_by_mmuidx(cs, mask); | |
4811 | } | |
4812 | ||
fd3ed969 | 4813 | static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
fa439fc5 PM |
4814 | uint64_t value) |
4815 | { | |
85d0dc9f RH |
4816 | CPUState *cs = env_cpu(env); |
4817 | int mask = e2_tlbmask(env); | |
fd3ed969 | 4818 | |
85d0dc9f | 4819 | tlb_flush_by_mmuidx(cs, mask); |
fd3ed969 PM |
4820 | } |
4821 | ||
43efaa33 PM |
4822 | static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4823 | uint64_t value) | |
4824 | { | |
2fc0cc0e | 4825 | ARMCPU *cpu = env_archcpu(env); |
43efaa33 PM |
4826 | CPUState *cs = CPU(cpu); |
4827 | ||
d902ae75 | 4828 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E3); |
43efaa33 PM |
4829 | } |
4830 | ||
fd3ed969 PM |
4831 | static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4832 | uint64_t value) | |
4833 | { | |
29a0af61 | 4834 | CPUState *cs = env_cpu(env); |
90c19cdf RH |
4835 | int mask = alle1_tlbmask(env); |
4836 | ||
4837 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); | |
fa439fc5 PM |
4838 | } |
4839 | ||
2bfb9d75 PM |
4840 | static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4841 | uint64_t value) | |
4842 | { | |
29a0af61 | 4843 | CPUState *cs = env_cpu(env); |
85d0dc9f | 4844 | int mask = e2_tlbmask(env); |
2bfb9d75 | 4845 | |
85d0dc9f | 4846 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
2bfb9d75 PM |
4847 | } |
4848 | ||
43efaa33 PM |
4849 | static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4850 | uint64_t value) | |
4851 | { | |
29a0af61 | 4852 | CPUState *cs = env_cpu(env); |
43efaa33 | 4853 | |
d902ae75 | 4854 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E3); |
43efaa33 PM |
4855 | } |
4856 | ||
fd3ed969 PM |
4857 | static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4858 | uint64_t value) | |
fa439fc5 | 4859 | { |
9b37a28c FR |
4860 | /* |
4861 | * Invalidate by VA, EL2 | |
fd3ed969 PM |
4862 | * Currently handles both VAE2 and VALE2, since we don't support |
4863 | * flush-last-level-only. | |
4864 | */ | |
85d0dc9f | 4865 | CPUState *cs = env_cpu(env); |
ceaa9746 | 4866 | int mask = vae2_tlbmask(env); |
fd3ed969 | 4867 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ceaa9746 | 4868 | int bits = vae2_tlbbits(env, pageaddr); |
fd3ed969 | 4869 | |
ceaa9746 | 4870 | tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits); |
fd3ed969 PM |
4871 | } |
4872 | ||
43efaa33 PM |
4873 | static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4874 | uint64_t value) | |
4875 | { | |
9b37a28c FR |
4876 | /* |
4877 | * Invalidate by VA, EL3 | |
43efaa33 PM |
4878 | * Currently handles both VAE3 and VALE3, since we don't support |
4879 | * flush-last-level-only. | |
4880 | */ | |
2fc0cc0e | 4881 | ARMCPU *cpu = env_archcpu(env); |
43efaa33 PM |
4882 | CPUState *cs = CPU(cpu); |
4883 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
4884 | ||
d902ae75 | 4885 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E3); |
43efaa33 PM |
4886 | } |
4887 | ||
fd3ed969 PM |
4888 | static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4889 | uint64_t value) | |
4890 | { | |
90c19cdf RH |
4891 | CPUState *cs = env_cpu(env); |
4892 | int mask = vae1_tlbmask(env); | |
fa439fc5 | 4893 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ea04dce7 | 4894 | int bits = vae1_tlbbits(env, pageaddr); |
fa439fc5 | 4895 | |
ea04dce7 | 4896 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); |
fa439fc5 PM |
4897 | } |
4898 | ||
b4ab8ce9 PM |
4899 | static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4900 | uint64_t value) | |
4901 | { | |
9b37a28c FR |
4902 | /* |
4903 | * Invalidate by VA, EL1&0 (AArch64 version). | |
b4ab8ce9 PM |
4904 | * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, |
4905 | * since we don't support flush-for-specific-ASID-only or | |
4906 | * flush-last-level-only. | |
4907 | */ | |
90c19cdf RH |
4908 | CPUState *cs = env_cpu(env); |
4909 | int mask = vae1_tlbmask(env); | |
b4ab8ce9 | 4910 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ea04dce7 | 4911 | int bits = vae1_tlbbits(env, pageaddr); |
b4ab8ce9 PM |
4912 | |
4913 | if (tlb_force_broadcast(env)) { | |
ea04dce7 | 4914 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); |
527db2be | 4915 | } else { |
ea04dce7 | 4916 | tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits); |
b4ab8ce9 | 4917 | } |
b4ab8ce9 PM |
4918 | } |
4919 | ||
fd3ed969 PM |
4920 | static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4921 | uint64_t value) | |
fa439fc5 | 4922 | { |
29a0af61 | 4923 | CPUState *cs = env_cpu(env); |
ceaa9746 | 4924 | int mask = vae2_tlbmask(env); |
fd3ed969 | 4925 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ceaa9746 | 4926 | int bits = vae2_tlbbits(env, pageaddr); |
fa439fc5 | 4927 | |
ceaa9746 | 4928 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); |
fa439fc5 PM |
4929 | } |
4930 | ||
43efaa33 PM |
4931 | static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4932 | uint64_t value) | |
4933 | { | |
29a0af61 | 4934 | CPUState *cs = env_cpu(env); |
43efaa33 | 4935 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
d902ae75 | 4936 | int bits = tlbbits_for_regime(env, ARMMMUIdx_E3, pageaddr); |
43efaa33 | 4937 | |
ea04dce7 | 4938 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, |
d902ae75 | 4939 | ARMMMUIdxBit_E3, bits); |
43efaa33 PM |
4940 | } |
4941 | ||
575a94af RH |
4942 | static int ipas2e1_tlbmask(CPUARMState *env, int64_t value) |
4943 | { | |
4944 | /* | |
4945 | * The MSB of value is the NS field, which only applies if SEL2 | |
4946 | * is implemented and SCR_EL3.NS is not set (i.e. in secure mode). | |
4947 | */ | |
4948 | return (value >= 0 | |
4949 | && cpu_isar_feature(aa64_sel2, env_archcpu(env)) | |
4950 | && arm_is_secure_below_el3(env) | |
4951 | ? ARMMMUIdxBit_Stage2_S | |
4952 | : ARMMMUIdxBit_Stage2); | |
4953 | } | |
4954 | ||
4955 | static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4956 | uint64_t value) | |
4957 | { | |
4958 | CPUState *cs = env_cpu(env); | |
4959 | int mask = ipas2e1_tlbmask(env, value); | |
4960 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
4961 | ||
4962 | if (tlb_force_broadcast(env)) { | |
4963 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); | |
4964 | } else { | |
4965 | tlb_flush_page_by_mmuidx(cs, pageaddr, mask); | |
4966 | } | |
4967 | } | |
4968 | ||
4969 | static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4970 | uint64_t value) | |
4971 | { | |
4972 | CPUState *cs = env_cpu(env); | |
4973 | int mask = ipas2e1_tlbmask(env, value); | |
4974 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
4975 | ||
4976 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); | |
4977 | } | |
4978 | ||
84940ed8 | 4979 | #ifdef TARGET_AARCH64 |
ab1cdb47 RH |
4980 | typedef struct { |
4981 | uint64_t base; | |
84940ed8 | 4982 | uint64_t length; |
ab1cdb47 RH |
4983 | } TLBIRange; |
4984 | ||
3c003f70 PM |
4985 | static ARMGranuleSize tlbi_range_tg_to_gran_size(int tg) |
4986 | { | |
4987 | /* | |
4988 | * Note that the TLBI range TG field encoding differs from both | |
4989 | * TG0 and TG1 encodings. | |
4990 | */ | |
4991 | switch (tg) { | |
4992 | case 1: | |
4993 | return Gran4K; | |
4994 | case 2: | |
4995 | return Gran16K; | |
4996 | case 3: | |
4997 | return Gran64K; | |
4998 | default: | |
4999 | return GranInvalid; | |
5000 | } | |
5001 | } | |
5002 | ||
ab1cdb47 RH |
5003 | static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, |
5004 | uint64_t value) | |
5005 | { | |
5006 | unsigned int page_size_granule, page_shift, num, scale, exponent; | |
3974ff93 RH |
5007 | /* Extract one bit to represent the va selector in use. */ |
5008 | uint64_t select = sextract64(value, 36, 1); | |
478dccbb | 5009 | ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true, false); |
ab1cdb47 | 5010 | TLBIRange ret = { }; |
3c003f70 | 5011 | ARMGranuleSize gran; |
84940ed8 | 5012 | |
84940ed8 | 5013 | page_size_granule = extract64(value, 46, 2); |
3c003f70 | 5014 | gran = tlbi_range_tg_to_gran_size(page_size_granule); |
84940ed8 | 5015 | |
3974ff93 | 5016 | /* The granule encoded in value must match the granule in use. */ |
3c003f70 | 5017 | if (gran != param.gran) { |
3974ff93 | 5018 | qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\n", |
84940ed8 | 5019 | page_size_granule); |
ab1cdb47 | 5020 | return ret; |
84940ed8 RC |
5021 | } |
5022 | ||
3c003f70 | 5023 | page_shift = arm_granule_bits(gran); |
ab1cdb47 RH |
5024 | num = extract64(value, 39, 5); |
5025 | scale = extract64(value, 44, 2); | |
84940ed8 | 5026 | exponent = (5 * scale) + 1; |
84940ed8 | 5027 | |
ab1cdb47 | 5028 | ret.length = (num + 1) << (exponent + page_shift); |
84940ed8 | 5029 | |
3974ff93 | 5030 | if (param.select) { |
d976de21 | 5031 | ret.base = sextract64(value, 0, 37); |
84940ed8 | 5032 | } else { |
d976de21 | 5033 | ret.base = extract64(value, 0, 37); |
84940ed8 | 5034 | } |
ef56c242 RH |
5035 | if (param.ds) { |
5036 | /* | |
5037 | * With DS=1, BaseADDR is always shifted 16 so that it is able | |
5038 | * to address all 52 va bits. The input address is perforce | |
5039 | * aligned on a 64k boundary regardless of translation granule. | |
5040 | */ | |
5041 | page_shift = 16; | |
5042 | } | |
d976de21 | 5043 | ret.base <<= page_shift; |
84940ed8 | 5044 | |
ab1cdb47 | 5045 | return ret; |
84940ed8 RC |
5046 | } |
5047 | ||
5048 | static void do_rvae_write(CPUARMState *env, uint64_t value, | |
5049 | int idxmap, bool synced) | |
5050 | { | |
5051 | ARMMMUIdx one_idx = ARM_MMU_IDX_A | ctz32(idxmap); | |
ab1cdb47 | 5052 | TLBIRange range; |
84940ed8 RC |
5053 | int bits; |
5054 | ||
ab1cdb47 RH |
5055 | range = tlbi_aa64_get_range(env, one_idx, value); |
5056 | bits = tlbbits_for_regime(env, one_idx, range.base); | |
84940ed8 RC |
5057 | |
5058 | if (synced) { | |
5059 | tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env), | |
ab1cdb47 RH |
5060 | range.base, |
5061 | range.length, | |
84940ed8 RC |
5062 | idxmap, |
5063 | bits); | |
5064 | } else { | |
ab1cdb47 RH |
5065 | tlb_flush_range_by_mmuidx(env_cpu(env), range.base, |
5066 | range.length, idxmap, bits); | |
84940ed8 RC |
5067 | } |
5068 | } | |
5069 | ||
5070 | static void tlbi_aa64_rvae1_write(CPUARMState *env, | |
5071 | const ARMCPRegInfo *ri, | |
5072 | uint64_t value) | |
5073 | { | |
5074 | /* | |
5075 | * Invalidate by VA range, EL1&0. | |
5076 | * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1, | |
5077 | * since we don't support flush-for-specific-ASID-only or | |
5078 | * flush-last-level-only. | |
5079 | */ | |
5080 | ||
5081 | do_rvae_write(env, value, vae1_tlbmask(env), | |
5082 | tlb_force_broadcast(env)); | |
5083 | } | |
5084 | ||
5085 | static void tlbi_aa64_rvae1is_write(CPUARMState *env, | |
5086 | const ARMCPRegInfo *ri, | |
5087 | uint64_t value) | |
5088 | { | |
5089 | /* | |
5090 | * Invalidate by VA range, Inner/Outer Shareable EL1&0. | |
5091 | * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS, | |
5092 | * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support | |
5093 | * flush-for-specific-ASID-only, flush-last-level-only or inner/outer | |
5094 | * shareable specific flushes. | |
5095 | */ | |
5096 | ||
5097 | do_rvae_write(env, value, vae1_tlbmask(env), true); | |
5098 | } | |
5099 | ||
84940ed8 RC |
5100 | static void tlbi_aa64_rvae2_write(CPUARMState *env, |
5101 | const ARMCPRegInfo *ri, | |
5102 | uint64_t value) | |
5103 | { | |
5104 | /* | |
5105 | * Invalidate by VA range, EL2. | |
5106 | * Currently handles all of RVAE2 and RVALE2, | |
5107 | * since we don't support flush-for-specific-ASID-only or | |
5108 | * flush-last-level-only. | |
5109 | */ | |
5110 | ||
5111 | do_rvae_write(env, value, vae2_tlbmask(env), | |
5112 | tlb_force_broadcast(env)); | |
5113 | ||
5114 | ||
5115 | } | |
5116 | ||
5117 | static void tlbi_aa64_rvae2is_write(CPUARMState *env, | |
5118 | const ARMCPRegInfo *ri, | |
5119 | uint64_t value) | |
5120 | { | |
5121 | /* | |
5122 | * Invalidate by VA range, Inner/Outer Shareable, EL2. | |
5123 | * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS, | |
5124 | * since we don't support flush-for-specific-ASID-only, | |
5125 | * flush-last-level-only or inner/outer shareable specific flushes. | |
5126 | */ | |
5127 | ||
5128 | do_rvae_write(env, value, vae2_tlbmask(env), true); | |
5129 | ||
5130 | } | |
5131 | ||
5132 | static void tlbi_aa64_rvae3_write(CPUARMState *env, | |
5133 | const ARMCPRegInfo *ri, | |
5134 | uint64_t value) | |
5135 | { | |
5136 | /* | |
5137 | * Invalidate by VA range, EL3. | |
5138 | * Currently handles all of RVAE3 and RVALE3, | |
5139 | * since we don't support flush-for-specific-ASID-only or | |
5140 | * flush-last-level-only. | |
5141 | */ | |
5142 | ||
d902ae75 | 5143 | do_rvae_write(env, value, ARMMMUIdxBit_E3, tlb_force_broadcast(env)); |
84940ed8 RC |
5144 | } |
5145 | ||
5146 | static void tlbi_aa64_rvae3is_write(CPUARMState *env, | |
5147 | const ARMCPRegInfo *ri, | |
5148 | uint64_t value) | |
5149 | { | |
5150 | /* | |
5151 | * Invalidate by VA range, EL3, Inner/Outer Shareable. | |
5152 | * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS, | |
5153 | * since we don't support flush-for-specific-ASID-only, | |
5154 | * flush-last-level-only or inner/outer specific flushes. | |
5155 | */ | |
5156 | ||
d902ae75 | 5157 | do_rvae_write(env, value, ARMMMUIdxBit_E3, true); |
84940ed8 | 5158 | } |
575a94af RH |
5159 | |
5160 | static void tlbi_aa64_ripas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5161 | uint64_t value) | |
5162 | { | |
5163 | do_rvae_write(env, value, ipas2e1_tlbmask(env, value), | |
5164 | tlb_force_broadcast(env)); | |
5165 | } | |
5166 | ||
5167 | static void tlbi_aa64_ripas2e1is_write(CPUARMState *env, | |
5168 | const ARMCPRegInfo *ri, | |
5169 | uint64_t value) | |
5170 | { | |
5171 | do_rvae_write(env, value, ipas2e1_tlbmask(env, value), true); | |
5172 | } | |
84940ed8 RC |
5173 | #endif |
5174 | ||
3f208fd7 PM |
5175 | static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5176 | bool isread) | |
aca3f40b | 5177 | { |
4351cb72 RH |
5178 | int cur_el = arm_current_el(env); |
5179 | ||
5180 | if (cur_el < 2) { | |
5181 | uint64_t hcr = arm_hcr_el2_eff(env); | |
5182 | ||
5183 | if (cur_el == 0) { | |
5184 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
5185 | if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) { | |
5186 | return CP_ACCESS_TRAP_EL2; | |
5187 | } | |
5188 | } else { | |
5189 | if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) { | |
5190 | return CP_ACCESS_TRAP; | |
5191 | } | |
5192 | if (hcr & HCR_TDZ) { | |
5193 | return CP_ACCESS_TRAP_EL2; | |
5194 | } | |
5195 | } | |
5196 | } else if (hcr & HCR_TDZ) { | |
5197 | return CP_ACCESS_TRAP_EL2; | |
5198 | } | |
aca3f40b PM |
5199 | } |
5200 | return CP_ACCESS_OK; | |
5201 | } | |
5202 | ||
5203 | static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5204 | { | |
2fc0cc0e | 5205 | ARMCPU *cpu = env_archcpu(env); |
aca3f40b PM |
5206 | int dzp_bit = 1 << 4; |
5207 | ||
5208 | /* DZP indicates whether DC ZVA access is allowed */ | |
3f208fd7 | 5209 | if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) { |
aca3f40b PM |
5210 | dzp_bit = 0; |
5211 | } | |
5212 | return cpu->dcz_blocksize | dzp_bit; | |
5213 | } | |
5214 | ||
3f208fd7 PM |
5215 | static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5216 | bool isread) | |
f502cfc2 | 5217 | { |
cdcf1405 | 5218 | if (!(env->pstate & PSTATE_SP)) { |
9b37a28c FR |
5219 | /* |
5220 | * Access to SP_EL0 is undefined if it's being used as | |
f502cfc2 PM |
5221 | * the stack pointer. |
5222 | */ | |
5223 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
5224 | } | |
5225 | return CP_ACCESS_OK; | |
5226 | } | |
5227 | ||
5228 | static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5229 | { | |
5230 | return env->pstate & PSTATE_SP; | |
5231 | } | |
5232 | ||
5233 | static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
5234 | { | |
5235 | update_spsel(env, val); | |
5236 | } | |
5237 | ||
137feaa9 FA |
5238 | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5239 | uint64_t value) | |
5240 | { | |
2fc0cc0e | 5241 | ARMCPU *cpu = env_archcpu(env); |
137feaa9 | 5242 | |
f00faf13 RH |
5243 | if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { |
5244 | /* M bit is RAZ/WI for PMSA with no MPU implemented */ | |
5245 | value &= ~SCTLR_M; | |
5246 | } | |
5247 | ||
5248 | /* ??? Lots of these bits are not implemented. */ | |
5249 | ||
5250 | if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) { | |
5251 | if (ri->opc1 == 6) { /* SCTLR_EL3 */ | |
5252 | value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); | |
5253 | } else { | |
5254 | value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | | |
5255 | SCTLR_ATA0 | SCTLR_ATA); | |
5256 | } | |
5257 | } | |
5258 | ||
137feaa9 | 5259 | if (raw_read(env, ri) == value) { |
9b37a28c FR |
5260 | /* |
5261 | * Skip the TLB flush if nothing actually changed; Linux likes | |
137feaa9 FA |
5262 | * to do a lot of pointless SCTLR writes. |
5263 | */ | |
5264 | return; | |
5265 | } | |
5266 | ||
5267 | raw_write(env, ri, value); | |
f00faf13 | 5268 | |
137feaa9 | 5269 | /* This may enable/disable the MMU, so do a TLB flush. */ |
d10eb08f | 5270 | tlb_flush(CPU(cpu)); |
2e5dcf36 | 5271 | |
2b77ad4d | 5272 | if (tcg_enabled() && ri->type & ARM_CP_SUPPRESS_TB_END) { |
2e5dcf36 RH |
5273 | /* |
5274 | * Normally we would always end the TB on an SCTLR write; see the | |
5275 | * comment in ARMCPRegInfo sctlr initialization below for why Xscale | |
5276 | * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild | |
5277 | * of hflags from the translator, so do it here. | |
5278 | */ | |
5279 | arm_rebuild_hflags(env); | |
5280 | } | |
137feaa9 FA |
5281 | } |
5282 | ||
80d2b43b PM |
5283 | static void mdcr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5284 | uint64_t value) | |
a8d64e73 | 5285 | { |
01765386 PM |
5286 | /* |
5287 | * Some MDCR_EL3 bits affect whether PMU counters are running: | |
5288 | * if we are trying to change any of those then we must | |
5289 | * bracket this update with PMU start/finish calls. | |
5290 | */ | |
5291 | bool pmu_op = (env->cp15.mdcr_el3 ^ value) & MDCR_EL3_PMU_ENABLE_BITS; | |
5292 | ||
5293 | if (pmu_op) { | |
5294 | pmu_op_start(env); | |
5295 | } | |
80d2b43b | 5296 | env->cp15.mdcr_el3 = value; |
01765386 PM |
5297 | if (pmu_op) { |
5298 | pmu_op_finish(env); | |
5299 | } | |
5300 | } | |
5301 | ||
80d2b43b PM |
5302 | static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5303 | uint64_t value) | |
5304 | { | |
5305 | /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */ | |
5306 | mdcr_el3_write(env, ri, value & SDCR_VALID_MASK); | |
5307 | } | |
5308 | ||
01765386 PM |
5309 | static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5310 | uint64_t value) | |
5311 | { | |
5312 | /* | |
5313 | * Some MDCR_EL2 bits affect whether PMU counters are running: | |
5314 | * if we are trying to change any of those then we must | |
5315 | * bracket this update with PMU start/finish calls. | |
5316 | */ | |
5317 | bool pmu_op = (env->cp15.mdcr_el2 ^ value) & MDCR_EL2_PMU_ENABLE_BITS; | |
5318 | ||
5319 | if (pmu_op) { | |
5320 | pmu_op_start(env); | |
5321 | } | |
5322 | env->cp15.mdcr_el2 = value; | |
5323 | if (pmu_op) { | |
5324 | pmu_op_finish(env); | |
5325 | } | |
a8d64e73 PM |
5326 | } |
5327 | ||
9719f125 JH |
5328 | #ifdef CONFIG_USER_ONLY |
5329 | /* | |
5330 | * `IC IVAU` is handled to improve compatibility with JITs that dual-map their | |
5331 | * code to get around W^X restrictions, where one region is writable and the | |
5332 | * other is executable. | |
5333 | * | |
5334 | * Since the executable region is never written to we cannot detect code | |
5335 | * changes when running in user mode, and rely on the emulated JIT telling us | |
5336 | * that the code has changed by executing this instruction. | |
5337 | */ | |
5338 | static void ic_ivau_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5339 | uint64_t value) | |
5340 | { | |
5341 | uint64_t icache_line_mask, start_address, end_address; | |
5342 | const ARMCPU *cpu; | |
5343 | ||
5344 | cpu = env_archcpu(env); | |
5345 | ||
5346 | icache_line_mask = (4 << extract32(cpu->ctr, 0, 4)) - 1; | |
5347 | start_address = value & ~icache_line_mask; | |
5348 | end_address = value | icache_line_mask; | |
5349 | ||
5350 | mmap_lock(); | |
5351 | ||
5352 | tb_invalidate_phys_range(start_address, end_address); | |
5353 | ||
5354 | mmap_unlock(); | |
5355 | } | |
5356 | #endif | |
5357 | ||
b0d2b7d0 | 5358 | static const ARMCPRegInfo v8_cp_reginfo[] = { |
9b37a28c FR |
5359 | /* |
5360 | * Minimal set of EL0-visible registers. This will need to be expanded | |
b0d2b7d0 PM |
5361 | * significantly for system emulation of AArch64 CPUs. |
5362 | */ | |
5363 | { .name = "NZCV", .state = ARM_CP_STATE_AA64, | |
5364 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, | |
5365 | .access = PL0_RW, .type = ARM_CP_NZCV }, | |
c2b820fe PM |
5366 | { .name = "DAIF", .state = ARM_CP_STATE_AA64, |
5367 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, | |
7a0e58fa | 5368 | .type = ARM_CP_NO_RAW, |
c2b820fe PM |
5369 | .access = PL0_RW, .accessfn = aa64_daif_access, |
5370 | .fieldoffset = offsetof(CPUARMState, daif), | |
5371 | .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, | |
b0d2b7d0 PM |
5372 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, |
5373 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | |
b916c9c3 | 5374 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 5375 | .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, |
b0d2b7d0 PM |
5376 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, |
5377 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | |
b916c9c3 | 5378 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 5379 | .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, |
b0d2b7d0 PM |
5380 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, |
5381 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | |
7a0e58fa | 5382 | .access = PL0_R, .type = ARM_CP_NO_RAW, |
b19ed03c | 5383 | .fgt = FGT_DCZID_EL0, |
aca3f40b PM |
5384 | .readfn = aa64_dczid_read }, |
5385 | { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, | |
5386 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, | |
5387 | .access = PL0_W, .type = ARM_CP_DC_ZVA, | |
5388 | #ifndef CONFIG_USER_ONLY | |
5389 | /* Avoid overhead of an access check that always passes in user-mode */ | |
5390 | .accessfn = aa64_zva_access, | |
dd345653 | 5391 | .fgt = FGT_DCZVA, |
aca3f40b PM |
5392 | #endif |
5393 | }, | |
0eef9d98 PM |
5394 | { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, |
5395 | .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, | |
5396 | .access = PL1_R, .type = ARM_CP_CURRENTEL }, | |
9719f125 JH |
5397 | /* |
5398 | * Instruction cache ops. All of these except `IC IVAU` NOP because we | |
5399 | * don't emulate caches. | |
5400 | */ | |
8af35c37 PM |
5401 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, |
5402 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
38262d8a | 5403 | .access = PL1_W, .type = ARM_CP_NOP, |
dd345653 | 5404 | .fgt = FGT_ICIALLUIS, |
2d3ce4c6 | 5405 | .accessfn = access_ticab }, |
8af35c37 PM |
5406 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, |
5407 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
38262d8a | 5408 | .access = PL1_W, .type = ARM_CP_NOP, |
dd345653 | 5409 | .fgt = FGT_ICIALLU, |
2d3ce4c6 | 5410 | .accessfn = access_tocu }, |
8af35c37 PM |
5411 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, |
5412 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | |
9719f125 | 5413 | .access = PL0_W, |
dd345653 | 5414 | .fgt = FGT_ICIVAU, |
9719f125 JH |
5415 | .accessfn = access_tocu, |
5416 | #ifdef CONFIG_USER_ONLY | |
5417 | .type = ARM_CP_NO_RAW, | |
5418 | .writefn = ic_ivau_write | |
5419 | #else | |
5420 | .type = ARM_CP_NOP | |
5421 | #endif | |
5422 | }, | |
5423 | /* Cache ops: all NOPs since we don't emulate caches */ | |
8af35c37 PM |
5424 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, |
5425 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
1bed4d2e | 5426 | .access = PL1_W, .accessfn = aa64_cacheop_poc_access, |
dd345653 | 5427 | .fgt = FGT_DCIVAC, |
1bed4d2e | 5428 | .type = ARM_CP_NOP }, |
8af35c37 PM |
5429 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, |
5430 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
dd345653 | 5431 | .fgt = FGT_DCISW, |
1803d271 | 5432 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
8af35c37 PM |
5433 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, |
5434 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | |
5435 | .access = PL0_W, .type = ARM_CP_NOP, | |
950037e2 | 5436 | .fgt = FGT_DCCVAC, |
1bed4d2e | 5437 | .accessfn = aa64_cacheop_poc_access }, |
8af35c37 PM |
5438 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, |
5439 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
dd345653 | 5440 | .fgt = FGT_DCCSW, |
1803d271 | 5441 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
8af35c37 PM |
5442 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, |
5443 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | |
5444 | .access = PL0_W, .type = ARM_CP_NOP, | |
dd345653 | 5445 | .fgt = FGT_DCCVAU, |
2d3ce4c6 | 5446 | .accessfn = access_tocu }, |
8af35c37 PM |
5447 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, |
5448 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | |
5449 | .access = PL0_W, .type = ARM_CP_NOP, | |
dd345653 | 5450 | .fgt = FGT_DCCIVAC, |
1bed4d2e | 5451 | .accessfn = aa64_cacheop_poc_access }, |
8af35c37 PM |
5452 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, |
5453 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
dd345653 | 5454 | .fgt = FGT_DCCISW, |
1803d271 | 5455 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
168aa23b PM |
5456 | /* TLBI operations */ |
5457 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 5458 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, |
0f66d223 | 5459 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5460 | .fgt = FGT_TLBIVMALLE1IS, |
fd3ed969 | 5461 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 5462 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5463 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
0f66d223 | 5464 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5465 | .fgt = FGT_TLBIVAE1IS, |
fd3ed969 | 5466 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 5467 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5468 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
0f66d223 | 5469 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5470 | .fgt = FGT_TLBIASIDE1IS, |
fd3ed969 | 5471 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 5472 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5473 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
0f66d223 | 5474 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5475 | .fgt = FGT_TLBIVAAE1IS, |
fd3ed969 | 5476 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 5477 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5478 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
0f66d223 | 5479 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5480 | .fgt = FGT_TLBIVALE1IS, |
fd3ed969 | 5481 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 5482 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5483 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
0f66d223 | 5484 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5485 | .fgt = FGT_TLBIVAALE1IS, |
fd3ed969 | 5486 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 5487 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5488 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, |
30881b73 | 5489 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5490 | .fgt = FGT_TLBIVMALLE1, |
fd3ed969 | 5491 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 5492 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5493 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
30881b73 | 5494 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5495 | .fgt = FGT_TLBIVAE1, |
fd3ed969 | 5496 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 5497 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5498 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
30881b73 | 5499 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5500 | .fgt = FGT_TLBIASIDE1, |
fd3ed969 | 5501 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 5502 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5503 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
30881b73 | 5504 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5505 | .fgt = FGT_TLBIVAAE1, |
fd3ed969 | 5506 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 5507 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5508 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
30881b73 | 5509 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5510 | .fgt = FGT_TLBIVALE1, |
fd3ed969 | 5511 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 5512 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5513 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
30881b73 | 5514 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5515 | .fgt = FGT_TLBIVAALE1, |
fd3ed969 | 5516 | .writefn = tlbi_aa64_vae1_write }, |
cea66e91 PM |
5517 | { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, |
5518 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
575a94af RH |
5519 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
5520 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
cea66e91 PM |
5521 | { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, |
5522 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
575a94af RH |
5523 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
5524 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
83ddf975 PM |
5525 | { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, |
5526 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
5527 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 5528 | .writefn = tlbi_aa64_alle1is_write }, |
43efaa33 PM |
5529 | { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, |
5530 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, | |
5531 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
5532 | .writefn = tlbi_aa64_alle1is_write }, | |
cea66e91 PM |
5533 | { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, |
5534 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
575a94af RH |
5535 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
5536 | .writefn = tlbi_aa64_ipas2e1_write }, | |
cea66e91 PM |
5537 | { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, |
5538 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
575a94af RH |
5539 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
5540 | .writefn = tlbi_aa64_ipas2e1_write }, | |
83ddf975 PM |
5541 | { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, |
5542 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
5543 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 5544 | .writefn = tlbi_aa64_alle1_write }, |
43efaa33 PM |
5545 | { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, |
5546 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, | |
5547 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
5548 | .writefn = tlbi_aa64_alle1is_write }, | |
19525524 PM |
5549 | #ifndef CONFIG_USER_ONLY |
5550 | /* 64 bit address translation operations */ | |
5551 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
5552 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, | |
0710b2fa | 5553 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
132c98cd | 5554 | .fgt = FGT_ATS1E1R, |
1acd00ef | 5555 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
19525524 PM |
5556 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, |
5557 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, | |
0710b2fa | 5558 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
132c98cd | 5559 | .fgt = FGT_ATS1E1W, |
1acd00ef | 5560 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
19525524 PM |
5561 | { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, |
5562 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, | |
0710b2fa | 5563 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
132c98cd | 5564 | .fgt = FGT_ATS1E0R, |
1acd00ef | 5565 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
19525524 PM |
5566 | { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, |
5567 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, | |
0710b2fa | 5568 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
132c98cd | 5569 | .fgt = FGT_ATS1E0W, |
1acd00ef | 5570 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
2a47df95 | 5571 | { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 5572 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, |
0710b2fa | 5573 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
1acd00ef | 5574 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
2a47df95 | 5575 | { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, |
7a379c7e | 5576 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, |
0710b2fa | 5577 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
1acd00ef | 5578 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
2a47df95 | 5579 | { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 5580 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, |
0710b2fa | 5581 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
1acd00ef | 5582 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
2a47df95 | 5583 | { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, |
7a379c7e | 5584 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, |
0710b2fa | 5585 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
1acd00ef | 5586 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
2a47df95 PM |
5587 | /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ |
5588 | { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, | |
5589 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, | |
0710b2fa PM |
5590 | .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
5591 | .writefn = ats_write64 }, | |
2a47df95 PM |
5592 | { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, |
5593 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, | |
0710b2fa PM |
5594 | .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
5595 | .writefn = ats_write64 }, | |
c96fc9b5 EI |
5596 | { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, |
5597 | .type = ARM_CP_ALIAS, | |
5598 | .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, | |
5599 | .access = PL1_RW, .resetvalue = 0, | |
67dd8030 | 5600 | .fgt = FGT_PAR_EL1, |
c96fc9b5 EI |
5601 | .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), |
5602 | .writefn = par_write }, | |
19525524 | 5603 | #endif |
995939a6 | 5604 | /* TLB invalidate last level of translation table walk */ |
9449fdf6 | 5605 | { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
0f66d223 | 5606 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, |
30881b73 | 5607 | .writefn = tlbimva_is_write }, |
9449fdf6 | 5608 | { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
0f66d223 | 5609 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, |
fa439fc5 | 5610 | .writefn = tlbimvaa_is_write }, |
9449fdf6 | 5611 | { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
30881b73 RH |
5612 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
5613 | .writefn = tlbimva_write }, | |
9449fdf6 | 5614 | { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
30881b73 RH |
5615 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
5616 | .writefn = tlbimvaa_write }, | |
541ef8c2 SS |
5617 | { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, |
5618 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5619 | .writefn = tlbimva_hyp_write }, | |
5620 | { .name = "TLBIMVALHIS", | |
5621 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
5622 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5623 | .writefn = tlbimva_hyp_is_write }, | |
5624 | { .name = "TLBIIPAS2", | |
5625 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
575a94af RH |
5626 | .type = ARM_CP_NO_RAW, .access = PL2_W, |
5627 | .writefn = tlbiipas2_hyp_write }, | |
541ef8c2 SS |
5628 | { .name = "TLBIIPAS2IS", |
5629 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
575a94af RH |
5630 | .type = ARM_CP_NO_RAW, .access = PL2_W, |
5631 | .writefn = tlbiipas2is_hyp_write }, | |
541ef8c2 SS |
5632 | { .name = "TLBIIPAS2L", |
5633 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
575a94af RH |
5634 | .type = ARM_CP_NO_RAW, .access = PL2_W, |
5635 | .writefn = tlbiipas2_hyp_write }, | |
541ef8c2 SS |
5636 | { .name = "TLBIIPAS2LIS", |
5637 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
575a94af RH |
5638 | .type = ARM_CP_NO_RAW, .access = PL2_W, |
5639 | .writefn = tlbiipas2is_hyp_write }, | |
9449fdf6 PM |
5640 | /* 32 bit cache operations */ |
5641 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
2d3ce4c6 | 5642 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_ticab }, |
9449fdf6 PM |
5643 | { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, |
5644 | .type = ARM_CP_NOP, .access = PL1_W }, | |
5645 | { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
2d3ce4c6 | 5646 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu }, |
9449fdf6 | 5647 | { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, |
2d3ce4c6 | 5648 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu }, |
9449fdf6 PM |
5649 | { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, |
5650 | .type = ARM_CP_NOP, .access = PL1_W }, | |
5651 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | |
5652 | .type = ARM_CP_NOP, .access = PL1_W }, | |
5653 | { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
1bed4d2e | 5654 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 5655 | { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, |
1803d271 | 5656 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 5657 | { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, |
1bed4d2e | 5658 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 5659 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, |
1803d271 | 5660 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 5661 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, |
2d3ce4c6 | 5662 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu }, |
9449fdf6 | 5663 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, |
1bed4d2e | 5664 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 5665 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, |
1803d271 | 5666 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 5667 | /* MMU Domain access control / MPU write buffer control */ |
0c17d68c | 5668 | { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, |
84929218 | 5669 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
0c17d68c FA |
5670 | .writefn = dacr_write, .raw_writefn = raw_write, |
5671 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
5672 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a0618a19 | 5673 | { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5674 | .type = ARM_CP_ALIAS, |
a0618a19 | 5675 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, |
6947f059 EI |
5676 | .access = PL1_RW, |
5677 | .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, | |
a65f1de9 | 5678 | { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5679 | .type = ARM_CP_ALIAS, |
a65f1de9 | 5680 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
5681 | .access = PL1_RW, |
5682 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, | |
9b37a28c FR |
5683 | /* |
5684 | * We rely on the access checks not allowing the guest to write to the | |
f502cfc2 PM |
5685 | * state field when SPSel indicates that it's being used as the stack |
5686 | * pointer. | |
5687 | */ | |
5688 | { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, | |
5689 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, | |
5690 | .access = PL1_RW, .accessfn = sp_el0_access, | |
7a0e58fa | 5691 | .type = ARM_CP_ALIAS, |
f502cfc2 | 5692 | .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, |
884b4dee GB |
5693 | { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, |
5694 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, | |
beeec926 | 5695 | .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_KEEP, |
884b4dee | 5696 | .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, |
f502cfc2 PM |
5697 | { .name = "SPSel", .state = ARM_CP_STATE_AA64, |
5698 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, | |
7a0e58fa | 5699 | .type = ARM_CP_NO_RAW, |
f502cfc2 | 5700 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, |
6a43e0b6 PM |
5701 | { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, |
5702 | .type = ARM_CP_ALIAS, | |
5703 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, | |
5704 | .access = PL2_RW, | |
5705 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, | |
5706 | { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, | |
5707 | .type = ARM_CP_ALIAS, | |
5708 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, | |
5709 | .access = PL2_RW, | |
5710 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, | |
5711 | { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, | |
5712 | .type = ARM_CP_ALIAS, | |
5713 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, | |
5714 | .access = PL2_RW, | |
5715 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, | |
5716 | { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, | |
5717 | .type = ARM_CP_ALIAS, | |
5718 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, | |
5719 | .access = PL2_RW, | |
5720 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, | |
a8d64e73 | 5721 | { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, |
80d2b43b | 5722 | .type = ARM_CP_IO, |
a8d64e73 PM |
5723 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, |
5724 | .resetvalue = 0, | |
80d2b43b PM |
5725 | .access = PL3_RW, |
5726 | .writefn = mdcr_el3_write, | |
5727 | .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) }, | |
7f4fbfb5 | 5728 | { .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO, |
a8d64e73 PM |
5729 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1, |
5730 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, | |
5731 | .writefn = sdcr_write, | |
5732 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, | |
b0d2b7d0 PM |
5733 | }; |
5734 | ||
c36a0d57 PM |
5735 | /* These are present only when EL1 supports AArch32 */ |
5736 | static const ARMCPRegInfo v8_aa32_el1_reginfo[] = { | |
5737 | { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, | |
5738 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, | |
5739 | .access = PL2_RW, | |
5740 | .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, | |
5741 | .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, | |
5742 | { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, | |
5743 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, | |
5744 | .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, | |
5745 | .writefn = dacr_write, .raw_writefn = raw_write, | |
5746 | .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, | |
5747 | { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, | |
5748 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, | |
5749 | .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, | |
5750 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, | |
5751 | }; | |
5752 | ||
d1fb4da2 | 5753 | static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) |
f149e3e8 | 5754 | { |
2fc0cc0e | 5755 | ARMCPU *cpu = env_archcpu(env); |
d1fb4da2 RH |
5756 | |
5757 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
5758 | valid_mask |= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */ | |
5759 | } else { | |
5760 | valid_mask |= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */ | |
5761 | } | |
f149e3e8 EI |
5762 | |
5763 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
5764 | valid_mask &= ~HCR_HCD; | |
77077a83 | 5765 | } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { |
9b37a28c FR |
5766 | /* |
5767 | * Architecturally HCR.TSC is RES0 if EL3 is not implemented. | |
77077a83 JK |
5768 | * However, if we're using the SMC PSCI conduit then QEMU is |
5769 | * effectively acting like EL3 firmware and so the guest at | |
5770 | * EL2 should retain the ability to prevent EL1 from being | |
5771 | * able to make SMC calls into the ersatz firmware, so in | |
5772 | * that case HCR.TSC should be read/write. | |
5773 | */ | |
f149e3e8 EI |
5774 | valid_mask &= ~HCR_TSC; |
5775 | } | |
d1fb4da2 RH |
5776 | |
5777 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
5778 | if (cpu_isar_feature(aa64_vh, cpu)) { | |
5779 | valid_mask |= HCR_E2H; | |
5780 | } | |
da3d8b13 RH |
5781 | if (cpu_isar_feature(aa64_ras, cpu)) { |
5782 | valid_mask |= HCR_TERR | HCR_TEA; | |
5783 | } | |
d1fb4da2 RH |
5784 | if (cpu_isar_feature(aa64_lor, cpu)) { |
5785 | valid_mask |= HCR_TLOR; | |
5786 | } | |
5787 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
5788 | valid_mask |= HCR_API | HCR_APK; | |
5789 | } | |
8ddb300b RH |
5790 | if (cpu_isar_feature(aa64_mte, cpu)) { |
5791 | valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5; | |
5792 | } | |
7cb1e618 RH |
5793 | if (cpu_isar_feature(aa64_scxtnum, cpu)) { |
5794 | valid_mask |= HCR_ENSCXT; | |
5795 | } | |
8c7e17ef PM |
5796 | if (cpu_isar_feature(aa64_fwb, cpu)) { |
5797 | valid_mask |= HCR_FWB; | |
5798 | } | |
aa3cc42c RH |
5799 | if (cpu_isar_feature(aa64_rme, cpu)) { |
5800 | valid_mask |= HCR_GPF; | |
5801 | } | |
ef682cdb | 5802 | } |
f149e3e8 | 5803 | |
d2fd9313 PM |
5804 | if (cpu_isar_feature(any_evt, cpu)) { |
5805 | valid_mask |= HCR_TTLBIS | HCR_TTLBOS | HCR_TICAB | HCR_TOCU | HCR_TID4; | |
5806 | } else if (cpu_isar_feature(any_half_evt, cpu)) { | |
5807 | valid_mask |= HCR_TICAB | HCR_TOCU | HCR_TID4; | |
5808 | } | |
5809 | ||
f149e3e8 EI |
5810 | /* Clear RES0 bits. */ |
5811 | value &= valid_mask; | |
5812 | ||
8ddb300b RH |
5813 | /* |
5814 | * These bits change the MMU setup: | |
f149e3e8 EI |
5815 | * HCR_VM enables stage 2 translation |
5816 | * HCR_PTW forbids certain page-table setups | |
8ddb300b RH |
5817 | * HCR_DC disables stage1 and enables stage2 translation |
5818 | * HCR_DCT enables tagging on (disabled) stage1 translation | |
8c7e17ef | 5819 | * HCR_FWB changes the interpretation of stage2 descriptor bits |
f149e3e8 | 5820 | */ |
8c7e17ef PM |
5821 | if ((env->cp15.hcr_el2 ^ value) & |
5822 | (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT | HCR_FWB)) { | |
d10eb08f | 5823 | tlb_flush(CPU(cpu)); |
f149e3e8 | 5824 | } |
ce4afed8 | 5825 | env->cp15.hcr_el2 = value; |
89430fc6 PM |
5826 | |
5827 | /* | |
5828 | * Updates to VI and VF require us to update the status of | |
5829 | * virtual interrupts, which are the logical OR of these bits | |
5830 | * and the state of the input lines from the GIC. (This requires | |
5831 | * that we have the iothread lock, which is done by marking the | |
5832 | * reginfo structs as ARM_CP_IO.) | |
5833 | * Note that if a write to HCR pends a VIRQ or VFIQ it is never | |
5834 | * possible for it to be taken immediately, because VIRQ and | |
5835 | * VFIQ are masked unless running at EL0 or EL1, and HCR | |
5836 | * can only be written at EL2. | |
5837 | */ | |
5838 | g_assert(qemu_mutex_iothread_locked()); | |
5839 | arm_cpu_update_virq(cpu); | |
5840 | arm_cpu_update_vfiq(cpu); | |
3c29632f | 5841 | arm_cpu_update_vserr(cpu); |
ce4afed8 PM |
5842 | } |
5843 | ||
d1fb4da2 RH |
5844 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
5845 | { | |
5846 | do_hcr_write(env, value, 0); | |
5847 | } | |
5848 | ||
ce4afed8 PM |
5849 | static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, |
5850 | uint64_t value) | |
5851 | { | |
5852 | /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */ | |
5853 | value = deposit64(env->cp15.hcr_el2, 32, 32, value); | |
d1fb4da2 | 5854 | do_hcr_write(env, value, MAKE_64BIT_MASK(0, 32)); |
ce4afed8 PM |
5855 | } |
5856 | ||
5857 | static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, | |
5858 | uint64_t value) | |
5859 | { | |
5860 | /* Handle HCR write, i.e. write to low half of HCR_EL2 */ | |
5861 | value = deposit64(env->cp15.hcr_el2, 0, 32, value); | |
d1fb4da2 | 5862 | do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32)); |
f149e3e8 EI |
5863 | } |
5864 | ||
f7778444 | 5865 | /* |
b74c0443 | 5866 | * Return the effective value of HCR_EL2, at the given security state. |
f7778444 RH |
5867 | * Bits that are not included here: |
5868 | * RW (read from SCR_EL3.RW as needed) | |
5869 | */ | |
2d12bb96 | 5870 | uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space) |
f7778444 RH |
5871 | { |
5872 | uint64_t ret = env->cp15.hcr_el2; | |
5873 | ||
2d12bb96 PM |
5874 | assert(space != ARMSS_Root); |
5875 | ||
4477020d | 5876 | if (!arm_is_el2_enabled_secstate(env, space)) { |
f7778444 RH |
5877 | /* |
5878 | * "This register has no effect if EL2 is not enabled in the | |
5879 | * current Security state". This is ARMv8.4-SecEL2 speak for | |
5880 | * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1). | |
5881 | * | |
5882 | * Prior to that, the language was "In an implementation that | |
5883 | * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves | |
5884 | * as if this field is 0 for all purposes other than a direct | |
5885 | * read or write access of HCR_EL2". With lots of enumeration | |
5886 | * on a per-field basis. In current QEMU, this is condition | |
5887 | * is arm_is_secure_below_el3. | |
5888 | * | |
5889 | * Since the v8.4 language applies to the entire register, and | |
5890 | * appears to be backward compatible, use that. | |
5891 | */ | |
4990e1d3 RH |
5892 | return 0; |
5893 | } | |
5894 | ||
5895 | /* | |
5896 | * For a cpu that supports both aarch64 and aarch32, we can set bits | |
5897 | * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32. | |
5898 | * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32. | |
5899 | */ | |
5900 | if (!arm_el_is_aa64(env, 2)) { | |
5901 | uint64_t aa32_valid; | |
5902 | ||
5903 | /* | |
5904 | * These bits are up-to-date as of ARMv8.6. | |
5905 | * For HCR, it's easiest to list just the 2 bits that are invalid. | |
5906 | * For HCR2, list those that are valid. | |
5907 | */ | |
5908 | aa32_valid = MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ); | |
5909 | aa32_valid |= (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNCE | | |
5910 | HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS); | |
5911 | ret &= aa32_valid; | |
5912 | } | |
5913 | ||
5914 | if (ret & HCR_TGE) { | |
5915 | /* These bits are up-to-date as of ARMv8.6. */ | |
f7778444 RH |
5916 | if (ret & HCR_E2H) { |
5917 | ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | | |
5918 | HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | | |
5919 | HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | | |
4990e1d3 RH |
5920 | HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE | |
5921 | HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT | | |
5922 | HCR_TTLBIS | HCR_TTLBOS | HCR_TID5); | |
f7778444 RH |
5923 | } else { |
5924 | ret |= HCR_FMO | HCR_IMO | HCR_AMO; | |
5925 | } | |
5926 | ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | | |
5927 | HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | | |
5928 | HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | | |
5929 | HCR_TLOR); | |
5930 | } | |
5931 | ||
5932 | return ret; | |
5933 | } | |
5934 | ||
b74c0443 RH |
5935 | uint64_t arm_hcr_el2_eff(CPUARMState *env) |
5936 | { | |
a0262ba6 RH |
5937 | if (arm_feature(env, ARM_FEATURE_M)) { |
5938 | return 0; | |
5939 | } | |
2d12bb96 | 5940 | return arm_hcr_el2_eff_secstate(env, arm_security_space_below_el3(env)); |
b74c0443 RH |
5941 | } |
5942 | ||
19668718 RH |
5943 | /* |
5944 | * Corresponds to ARM pseudocode function ELIsInHost(). | |
5945 | */ | |
5946 | bool el_is_in_host(CPUARMState *env, int el) | |
5947 | { | |
5948 | uint64_t mask; | |
5949 | ||
5950 | /* | |
5951 | * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff(). | |
5952 | * Perform the simplest bit tests first, and validate EL2 afterward. | |
5953 | */ | |
5954 | if (el & 1) { | |
5955 | return false; /* EL1 or EL3 */ | |
5956 | } | |
5957 | ||
5958 | /* | |
5959 | * Note that hcr_write() checks isar_feature_aa64_vh(), | |
5960 | * aka HaveVirtHostExt(), in allowing HCR_E2H to be set. | |
5961 | */ | |
5962 | mask = el ? HCR_E2H : HCR_E2H | HCR_TGE; | |
5963 | if ((env->cp15.hcr_el2 & mask) != mask) { | |
5964 | return false; | |
5965 | } | |
5966 | ||
5967 | /* TGE and/or E2H set: double check those bits are currently legal. */ | |
5968 | return arm_is_el2_enabled(env) && arm_el_is_aa64(env, 2); | |
5969 | } | |
5970 | ||
5814d587 RH |
5971 | static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5972 | uint64_t value) | |
5973 | { | |
5974 | uint64_t valid_mask = 0; | |
5975 | ||
dbc678f9 PM |
5976 | /* FEAT_MOPS adds MSCEn and MCE2 */ |
5977 | if (cpu_isar_feature(aa64_mops, env_archcpu(env))) { | |
5978 | valid_mask |= HCRX_MSCEN | HCRX_MCE2; | |
5979 | } | |
5814d587 RH |
5980 | |
5981 | /* Clear RES0 bits. */ | |
5982 | env->cp15.hcrx_el2 = value & valid_mask; | |
5983 | } | |
5984 | ||
5985 | static CPAccessResult access_hxen(CPUARMState *env, const ARMCPRegInfo *ri, | |
5986 | bool isread) | |
5987 | { | |
5988 | if (arm_current_el(env) < 3 | |
5989 | && arm_feature(env, ARM_FEATURE_EL3) | |
5990 | && !(env->cp15.scr_el3 & SCR_HXEN)) { | |
5991 | return CP_ACCESS_TRAP_EL3; | |
5992 | } | |
5993 | return CP_ACCESS_OK; | |
5994 | } | |
5995 | ||
5996 | static const ARMCPRegInfo hcrx_el2_reginfo = { | |
5997 | .name = "HCRX_EL2", .state = ARM_CP_STATE_AA64, | |
5998 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 2, | |
5999 | .access = PL2_RW, .writefn = hcrx_write, .accessfn = access_hxen, | |
6000 | .fieldoffset = offsetof(CPUARMState, cp15.hcrx_el2), | |
6001 | }; | |
6002 | ||
6003 | /* Return the effective value of HCRX_EL2. */ | |
6004 | uint64_t arm_hcrx_el2_eff(CPUARMState *env) | |
6005 | { | |
6006 | /* | |
6007 | * The bits in this register behave as 0 for all purposes other than | |
dbc678f9 PM |
6008 | * direct reads of the register if SCR_EL3.HXEn is 0. |
6009 | * If EL2 is not enabled in the current security state, then the | |
6010 | * bit may behave as if 0, or as if 1, depending on the bit. | |
6011 | * For the moment, we treat the EL2-disabled case as taking | |
6012 | * priority over the HXEn-disabled case. This is true for the only | |
6013 | * bit for a feature which we implement where the answer is different | |
6014 | * for the two cases (MSCEn for FEAT_MOPS). | |
6015 | * This may need to be revisited for future bits. | |
5814d587 | 6016 | */ |
dbc678f9 PM |
6017 | if (!arm_is_el2_enabled(env)) { |
6018 | uint64_t hcrx = 0; | |
6019 | if (cpu_isar_feature(aa64_mops, env_archcpu(env))) { | |
6020 | /* MSCEn behaves as 1 if EL2 is not enabled */ | |
6021 | hcrx |= HCRX_MSCEN; | |
6022 | } | |
6023 | return hcrx; | |
6024 | } | |
6025 | if (arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_HXEN)) { | |
5814d587 RH |
6026 | return 0; |
6027 | } | |
6028 | return env->cp15.hcrx_el2; | |
6029 | } | |
6030 | ||
fc1120a7 PM |
6031 | static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
6032 | uint64_t value) | |
6033 | { | |
6034 | /* | |
6035 | * For A-profile AArch32 EL3, if NSACR.CP10 | |
6036 | * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. | |
6037 | */ | |
6038 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
6039 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
fab8ad39 RH |
6040 | uint64_t mask = R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; |
6041 | value = (value & ~mask) | (env->cp15.cptr_el[2] & mask); | |
fc1120a7 PM |
6042 | } |
6043 | env->cp15.cptr_el[2] = value; | |
6044 | } | |
6045 | ||
6046 | static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
6047 | { | |
6048 | /* | |
6049 | * For A-profile AArch32 EL3, if NSACR.CP10 | |
6050 | * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. | |
6051 | */ | |
6052 | uint64_t value = env->cp15.cptr_el[2]; | |
6053 | ||
6054 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
6055 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
fab8ad39 | 6056 | value |= R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; |
fc1120a7 PM |
6057 | } |
6058 | return value; | |
6059 | } | |
6060 | ||
4771cd01 | 6061 | static const ARMCPRegInfo el2_cp_reginfo[] = { |
f149e3e8 | 6062 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
89430fc6 | 6063 | .type = ARM_CP_IO, |
f149e3e8 EI |
6064 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
6065 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
587f8b33 | 6066 | .writefn = hcr_write, .raw_writefn = raw_write }, |
ce4afed8 | 6067 | { .name = "HCR", .state = ARM_CP_STATE_AA32, |
89430fc6 | 6068 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
6069 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
6070 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
c624ea0f | 6071 | .writefn = hcr_writelow }, |
831a2fca PM |
6072 | { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, |
6073 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, | |
6074 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3b685ba7 | 6075 | { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 6076 | .type = ARM_CP_ALIAS, |
3b685ba7 EI |
6077 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, |
6078 | .access = PL2_RW, | |
6079 | .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, | |
68e78e33 | 6080 | { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, |
f2c30f42 EI |
6081 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, |
6082 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, | |
cba517c3 | 6083 | { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, |
63b60551 EI |
6084 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, |
6085 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, | |
cba517c3 PM |
6086 | { .name = "HIFAR", .state = ARM_CP_STATE_AA32, |
6087 | .type = ARM_CP_ALIAS, | |
6088 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | |
6089 | .access = PL2_RW, | |
6090 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) }, | |
3b685ba7 | 6091 | { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 6092 | .type = ARM_CP_ALIAS, |
3b685ba7 | 6093 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
6094 | .access = PL2_RW, |
6095 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, | |
d79e0c06 | 6096 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, |
d42e3c26 EI |
6097 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, |
6098 | .access = PL2_RW, .writefn = vbar_write, | |
6099 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), | |
6100 | .resetvalue = 0 }, | |
884b4dee GB |
6101 | { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, |
6102 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 6103 | .access = PL3_RW, .type = ARM_CP_ALIAS, |
884b4dee | 6104 | .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, |
c6f19164 GB |
6105 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
6106 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
6107 | .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, | |
fc1120a7 PM |
6108 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]), |
6109 | .readfn = cptr_el2_read, .writefn = cptr_el2_write }, | |
95f949ac EI |
6110 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
6111 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
6112 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), | |
6113 | .resetvalue = 0 }, | |
6114 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
b5ede85b | 6115 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, |
95f949ac EI |
6116 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
6117 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, | |
2179ef95 PM |
6118 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
6119 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
6120 | .access = PL2_RW, .type = ARM_CP_CONST, | |
6121 | .resetvalue = 0 }, | |
6122 | /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ | |
55b53c71 | 6123 | { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, |
b5ede85b | 6124 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, |
2179ef95 PM |
6125 | .access = PL2_RW, .type = ARM_CP_CONST, |
6126 | .resetvalue = 0 }, | |
37cd6c24 PM |
6127 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
6128 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
6129 | .access = PL2_RW, .type = ARM_CP_CONST, | |
6130 | .resetvalue = 0 }, | |
6131 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
6132 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
6133 | .access = PL2_RW, .type = ARM_CP_CONST, | |
6134 | .resetvalue = 0 }, | |
06ec4c8c EI |
6135 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
6136 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
d06dc933 | 6137 | .access = PL2_RW, .writefn = vmsa_tcr_el12_write, |
587f8b33 | 6138 | .raw_writefn = raw_write, |
06ec4c8c | 6139 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, |
68e9c2fe EI |
6140 | { .name = "VTCR", .state = ARM_CP_STATE_AA32, |
6141 | .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 | 6142 | .type = ARM_CP_ALIAS, |
68e9c2fe | 6143 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
afbb181c | 6144 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vtcr_el2) }, |
68e9c2fe EI |
6145 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, |
6146 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 | 6147 | .access = PL2_RW, |
988cc190 | 6148 | /* no .writefn needed as this can't cause an ASID change */ |
68e9c2fe | 6149 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, |
b698e9cf EI |
6150 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
6151 | .cp = 15, .opc1 = 6, .crm = 2, | |
6152 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
6153 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
6154 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), | |
587f8b33 | 6155 | .writefn = vttbr_write, .raw_writefn = raw_write }, |
b698e9cf EI |
6156 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, |
6157 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
587f8b33 | 6158 | .access = PL2_RW, .writefn = vttbr_write, .raw_writefn = raw_write, |
b698e9cf | 6159 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, |
b9cb5323 EI |
6160 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
6161 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
6162 | .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, | |
6163 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, | |
ff05f37b EI |
6164 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
6165 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
6166 | .access = PL2_RW, .resetvalue = 0, | |
6167 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, | |
a57633c0 EI |
6168 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
6169 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
587f8b33 EA |
6170 | .access = PL2_RW, .resetvalue = 0, |
6171 | .writefn = vmsa_tcr_ttbr_el2_write, .raw_writefn = raw_write, | |
a57633c0 EI |
6172 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
6173 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
6174 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
a57633c0 | 6175 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
541ef8c2 SS |
6176 | { .name = "TLBIALLNSNH", |
6177 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
6178 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
6179 | .writefn = tlbiall_nsnh_write }, | |
6180 | { .name = "TLBIALLNSNHIS", | |
6181 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
6182 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
6183 | .writefn = tlbiall_nsnh_is_write }, | |
6184 | { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
6185 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
6186 | .writefn = tlbiall_hyp_write }, | |
6187 | { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
6188 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
6189 | .writefn = tlbiall_hyp_is_write }, | |
6190 | { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
6191 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
6192 | .writefn = tlbimva_hyp_write }, | |
6193 | { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
6194 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
6195 | .writefn = tlbimva_hyp_is_write }, | |
51da9014 EI |
6196 | { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, |
6197 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
696ba377 | 6198 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
fd3ed969 | 6199 | .writefn = tlbi_aa64_alle2_write }, |
8742d49d EI |
6200 | { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, |
6201 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
696ba377 | 6202 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
fd3ed969 | 6203 | .writefn = tlbi_aa64_vae2_write }, |
2bfb9d75 PM |
6204 | { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, |
6205 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, | |
696ba377 | 6206 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
2bfb9d75 PM |
6207 | .writefn = tlbi_aa64_vae2_write }, |
6208 | { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, | |
6209 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
696ba377 | 6210 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
2bfb9d75 | 6211 | .writefn = tlbi_aa64_alle2is_write }, |
8742d49d EI |
6212 | { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, |
6213 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
696ba377 | 6214 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
fd3ed969 | 6215 | .writefn = tlbi_aa64_vae2is_write }, |
2bfb9d75 PM |
6216 | { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, |
6217 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
696ba377 | 6218 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
2bfb9d75 | 6219 | .writefn = tlbi_aa64_vae2is_write }, |
edac4d8a | 6220 | #ifndef CONFIG_USER_ONLY |
9b37a28c FR |
6221 | /* |
6222 | * Unlike the other EL2-related AT operations, these must | |
2a47df95 PM |
6223 | * UNDEF from EL3 if EL2 is not implemented, which is why we |
6224 | * define them here rather than with the rest of the AT ops. | |
6225 | */ | |
6226 | { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, | |
6227 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
6228 | .access = PL2_W, .accessfn = at_s1e2_access, | |
696ba377 RH |
6229 | .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, |
6230 | .writefn = ats_write64 }, | |
2a47df95 PM |
6231 | { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, |
6232 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | |
6233 | .access = PL2_W, .accessfn = at_s1e2_access, | |
696ba377 RH |
6234 | .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, |
6235 | .writefn = ats_write64 }, | |
9b37a28c FR |
6236 | /* |
6237 | * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE | |
14db7fe0 PM |
6238 | * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 |
6239 | * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose | |
6240 | * to behave as if SCR.NS was 1. | |
6241 | */ | |
6242 | { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
6243 | .access = PL2_W, | |
0710b2fa | 6244 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
14db7fe0 PM |
6245 | { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, |
6246 | .access = PL2_W, | |
0710b2fa | 6247 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
0b6440af EI |
6248 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
6249 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
9b37a28c FR |
6250 | /* |
6251 | * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the | |
0b6440af EI |
6252 | * reset values as IMPDEF. We choose to reset to 3 to comply with |
6253 | * both ARMv7 and ARMv8. | |
6254 | */ | |
f6fc36de JPB |
6255 | .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 3, |
6256 | .writefn = gt_cnthctl_write, .raw_writefn = raw_write, | |
0b6440af | 6257 | .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, |
edac4d8a EI |
6258 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
6259 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
6260 | .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, | |
6261 | .writefn = gt_cntvoff_write, | |
6262 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
6263 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
6264 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, | |
6265 | .writefn = gt_cntvoff_write, | |
6266 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
b0e66d95 EI |
6267 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
6268 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
6269 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
6270 | .type = ARM_CP_IO, .access = PL2_RW, | |
6271 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
6272 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
6273 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
6274 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO, | |
6275 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
6276 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
6277 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
d44ec156 | 6278 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, |
b0e66d95 EI |
6279 | .resetfn = gt_hyp_timer_reset, |
6280 | .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, | |
6281 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
6282 | .type = ARM_CP_IO, | |
6283 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
6284 | .access = PL2_RW, | |
6285 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), | |
6286 | .resetvalue = 0, | |
6287 | .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, | |
edac4d8a | 6288 | #endif |
59e05530 EI |
6289 | { .name = "HPFAR", .state = ARM_CP_STATE_AA32, |
6290 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
6291 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
6292 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
6293 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, | |
6294 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
6295 | .access = PL2_RW, | |
6296 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
2a5a9abd AF |
6297 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
6298 | .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
6299 | .access = PL2_RW, | |
6300 | .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, | |
3b685ba7 EI |
6301 | }; |
6302 | ||
ce4afed8 PM |
6303 | static const ARMCPRegInfo el2_v8_cp_reginfo[] = { |
6304 | { .name = "HCR2", .state = ARM_CP_STATE_AA32, | |
89430fc6 | 6305 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
6306 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, |
6307 | .access = PL2_RW, | |
6308 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2), | |
6309 | .writefn = hcr_writehigh }, | |
ce4afed8 PM |
6310 | }; |
6311 | ||
e9152ee9 RDC |
6312 | static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, |
6313 | bool isread) | |
6314 | { | |
6315 | if (arm_current_el(env) == 3 || arm_is_secure_below_el3(env)) { | |
6316 | return CP_ACCESS_OK; | |
6317 | } | |
6318 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
6319 | } | |
6320 | ||
6321 | static const ARMCPRegInfo el2_sec_cp_reginfo[] = { | |
6322 | { .name = "VSTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
6323 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 0, | |
6324 | .access = PL2_RW, .accessfn = sel2_access, | |
6325 | .fieldoffset = offsetof(CPUARMState, cp15.vsttbr_el2) }, | |
6326 | { .name = "VSTCR_EL2", .state = ARM_CP_STATE_AA64, | |
6327 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2, | |
6328 | .access = PL2_RW, .accessfn = sel2_access, | |
6329 | .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) }, | |
e9152ee9 RDC |
6330 | }; |
6331 | ||
2f027fc5 PM |
6332 | static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
6333 | bool isread) | |
6334 | { | |
9b37a28c FR |
6335 | /* |
6336 | * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. | |
926c1b97 | 6337 | * At Secure EL1 it traps to EL3 or EL2. |
2f027fc5 PM |
6338 | */ |
6339 | if (arm_current_el(env) == 3) { | |
6340 | return CP_ACCESS_OK; | |
6341 | } | |
6342 | if (arm_is_secure_below_el3(env)) { | |
926c1b97 RDC |
6343 | if (env->cp15.scr_el3 & SCR_EEL2) { |
6344 | return CP_ACCESS_TRAP_EL2; | |
6345 | } | |
2f027fc5 PM |
6346 | return CP_ACCESS_TRAP_EL3; |
6347 | } | |
6348 | /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ | |
6349 | if (isread) { | |
6350 | return CP_ACCESS_OK; | |
6351 | } | |
6352 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
6353 | } | |
6354 | ||
60fb1a87 GB |
6355 | static const ARMCPRegInfo el3_cp_reginfo[] = { |
6356 | { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, | |
6357 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, | |
6358 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), | |
587f8b33 | 6359 | .resetfn = scr_reset, .writefn = scr_write, .raw_writefn = raw_write }, |
f80741d1 | 6360 | { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL, |
60fb1a87 | 6361 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, |
efe4a274 PM |
6362 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
6363 | .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), | |
587f8b33 | 6364 | .writefn = scr_write, .raw_writefn = raw_write }, |
60fb1a87 GB |
6365 | { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, |
6366 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, | |
6367 | .access = PL3_RW, .resetvalue = 0, | |
6368 | .fieldoffset = offsetof(CPUARMState, cp15.sder) }, | |
6369 | { .name = "SDER", | |
6370 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, | |
6371 | .access = PL3_RW, .resetvalue = 0, | |
6372 | .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, | |
60fb1a87 | 6373 | { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, |
efe4a274 PM |
6374 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
6375 | .writefn = vbar_write, .resetvalue = 0, | |
60fb1a87 | 6376 | .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, |
7dd8c9af FA |
6377 | { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, |
6378 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, | |
f478847f | 6379 | .access = PL3_RW, .resetvalue = 0, |
7dd8c9af | 6380 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, |
11f136ee FA |
6381 | { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, |
6382 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, | |
6459b94c | 6383 | .access = PL3_RW, |
cb4a0a34 PM |
6384 | /* no .writefn needed as this can't cause an ASID change */ |
6385 | .resetvalue = 0, | |
11f136ee | 6386 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, |
81547d66 | 6387 | { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 6388 | .type = ARM_CP_ALIAS, |
81547d66 EI |
6389 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, |
6390 | .access = PL3_RW, | |
6391 | .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, | |
f2c30f42 | 6392 | { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, |
f2c30f42 EI |
6393 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, |
6394 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, | |
63b60551 EI |
6395 | { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, |
6396 | .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, | |
6397 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, | |
81547d66 | 6398 | { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 6399 | .type = ARM_CP_ALIAS, |
81547d66 | 6400 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
6401 | .access = PL3_RW, |
6402 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) }, | |
a1ba125c EI |
6403 | { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, |
6404 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, | |
6405 | .access = PL3_RW, .writefn = vbar_write, | |
6406 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), | |
6407 | .resetvalue = 0 }, | |
c6f19164 GB |
6408 | { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, |
6409 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, | |
6410 | .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, | |
6411 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, | |
4cfb8ad8 PM |
6412 | { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, |
6413 | .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, | |
6414 | .access = PL3_RW, .resetvalue = 0, | |
6415 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, | |
2179ef95 PM |
6416 | { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64, |
6417 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, | |
6418 | .access = PL3_RW, .type = ARM_CP_CONST, | |
6419 | .resetvalue = 0 }, | |
37cd6c24 PM |
6420 | { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, |
6421 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, | |
6422 | .access = PL3_RW, .type = ARM_CP_CONST, | |
6423 | .resetvalue = 0 }, | |
6424 | { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, | |
6425 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, | |
6426 | .access = PL3_RW, .type = ARM_CP_CONST, | |
6427 | .resetvalue = 0 }, | |
43efaa33 PM |
6428 | { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, |
6429 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, | |
6430 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6431 | .writefn = tlbi_aa64_alle3is_write }, | |
6432 | { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, | |
6433 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, | |
6434 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6435 | .writefn = tlbi_aa64_vae3is_write }, | |
6436 | { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, | |
6437 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, | |
6438 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6439 | .writefn = tlbi_aa64_vae3is_write }, | |
6440 | { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, | |
6441 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, | |
6442 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6443 | .writefn = tlbi_aa64_alle3_write }, | |
6444 | { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, | |
6445 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, | |
6446 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6447 | .writefn = tlbi_aa64_vae3_write }, | |
6448 | { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, | |
6449 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, | |
6450 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6451 | .writefn = tlbi_aa64_vae3_write }, | |
0f1a3b24 FA |
6452 | }; |
6453 | ||
e2cce18f RH |
6454 | #ifndef CONFIG_USER_ONLY |
6455 | /* Test if system register redirection is to occur in the current state. */ | |
6456 | static bool redirect_for_e2h(CPUARMState *env) | |
6457 | { | |
6458 | return arm_current_el(env) == 2 && (arm_hcr_el2_eff(env) & HCR_E2H); | |
6459 | } | |
6460 | ||
6461 | static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
6462 | { | |
6463 | CPReadFn *readfn; | |
6464 | ||
6465 | if (redirect_for_e2h(env)) { | |
6466 | /* Switch to the saved EL2 version of the register. */ | |
6467 | ri = ri->opaque; | |
6468 | readfn = ri->readfn; | |
6469 | } else { | |
6470 | readfn = ri->orig_readfn; | |
6471 | } | |
6472 | if (readfn == NULL) { | |
6473 | readfn = raw_read; | |
6474 | } | |
6475 | return readfn(env, ri); | |
6476 | } | |
6477 | ||
6478 | static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6479 | uint64_t value) | |
6480 | { | |
6481 | CPWriteFn *writefn; | |
6482 | ||
6483 | if (redirect_for_e2h(env)) { | |
6484 | /* Switch to the saved EL2 version of the register. */ | |
6485 | ri = ri->opaque; | |
6486 | writefn = ri->writefn; | |
6487 | } else { | |
6488 | writefn = ri->orig_writefn; | |
6489 | } | |
6490 | if (writefn == NULL) { | |
6491 | writefn = raw_write; | |
6492 | } | |
6493 | writefn(env, ri, value); | |
6494 | } | |
6495 | ||
6496 | static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) | |
6497 | { | |
6498 | struct E2HAlias { | |
6499 | uint32_t src_key, dst_key, new_key; | |
6500 | const char *src_name, *dst_name, *new_name; | |
6501 | bool (*feature)(const ARMISARegisters *id); | |
6502 | }; | |
6503 | ||
6504 | #define K(op0, op1, crn, crm, op2) \ | |
6505 | ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) | |
6506 | ||
6507 | static const struct E2HAlias aliases[] = { | |
6508 | { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), | |
6509 | "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, | |
6510 | { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), | |
6511 | "CPACR", "CPTR_EL2", "CPACR_EL12" }, | |
6512 | { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), | |
6513 | "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, | |
6514 | { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), | |
6515 | "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, | |
6516 | { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), | |
6517 | "TCR_EL1", "TCR_EL2", "TCR_EL12" }, | |
6518 | { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), | |
6519 | "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, | |
6520 | { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), | |
6521 | "ELR_EL1", "ELR_EL2", "ELR_EL12" }, | |
6522 | { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0), | |
6523 | "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" }, | |
6524 | { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1), | |
6525 | "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" }, | |
6526 | { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0), | |
6527 | "ESR_EL1", "ESR_EL2", "ESR_EL12" }, | |
6528 | { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0), | |
6529 | "FAR_EL1", "FAR_EL2", "FAR_EL12" }, | |
6530 | { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), | |
6531 | "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, | |
6532 | { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), | |
6533 | "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" }, | |
6534 | { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), | |
6535 | "VBAR", "VBAR_EL2", "VBAR_EL12" }, | |
6536 | { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), | |
6537 | "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, | |
6538 | { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), | |
6539 | "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" }, | |
6540 | ||
6541 | /* | |
6542 | * Note that redirection of ZCR is mentioned in the description | |
6543 | * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but | |
6544 | * not in the summary table. | |
6545 | */ | |
6546 | { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), | |
6547 | "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, | |
de561988 RH |
6548 | { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6), |
6549 | "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme }, | |
e2cce18f | 6550 | |
4b779ceb RH |
6551 | { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), |
6552 | "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, | |
6553 | ||
7cb1e618 RH |
6554 | { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), |
6555 | "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", | |
6556 | isar_feature_aa64_scxtnum }, | |
6557 | ||
e2cce18f RH |
6558 | /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ |
6559 | /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ | |
6560 | }; | |
6561 | #undef K | |
6562 | ||
6563 | size_t i; | |
6564 | ||
6565 | for (i = 0; i < ARRAY_SIZE(aliases); i++) { | |
6566 | const struct E2HAlias *a = &aliases[i]; | |
9da35a40 | 6567 | ARMCPRegInfo *src_reg, *dst_reg, *new_reg; |
9da35a40 | 6568 | bool ok; |
e2cce18f RH |
6569 | |
6570 | if (a->feature && !a->feature(&cpu->isar)) { | |
6571 | continue; | |
6572 | } | |
6573 | ||
5860362d RH |
6574 | src_reg = g_hash_table_lookup(cpu->cp_regs, |
6575 | (gpointer)(uintptr_t)a->src_key); | |
6576 | dst_reg = g_hash_table_lookup(cpu->cp_regs, | |
6577 | (gpointer)(uintptr_t)a->dst_key); | |
e2cce18f RH |
6578 | g_assert(src_reg != NULL); |
6579 | g_assert(dst_reg != NULL); | |
6580 | ||
6581 | /* Cross-compare names to detect typos in the keys. */ | |
6582 | g_assert(strcmp(src_reg->name, a->src_name) == 0); | |
6583 | g_assert(strcmp(dst_reg->name, a->dst_name) == 0); | |
6584 | ||
6585 | /* None of the core system registers use opaque; we will. */ | |
6586 | g_assert(src_reg->opaque == NULL); | |
6587 | ||
6588 | /* Create alias before redirection so we dup the right data. */ | |
9da35a40 | 6589 | new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo)); |
9da35a40 RH |
6590 | |
6591 | new_reg->name = a->new_name; | |
6592 | new_reg->type |= ARM_CP_ALIAS; | |
6593 | /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ | |
6594 | new_reg->access &= PL2_RW | PL3_RW; | |
6595 | ||
5860362d RH |
6596 | ok = g_hash_table_insert(cpu->cp_regs, |
6597 | (gpointer)(uintptr_t)a->new_key, new_reg); | |
9da35a40 | 6598 | g_assert(ok); |
e2cce18f RH |
6599 | |
6600 | src_reg->opaque = dst_reg; | |
6601 | src_reg->orig_readfn = src_reg->readfn ?: raw_read; | |
6602 | src_reg->orig_writefn = src_reg->writefn ?: raw_write; | |
6603 | if (!src_reg->raw_readfn) { | |
6604 | src_reg->raw_readfn = raw_read; | |
6605 | } | |
6606 | if (!src_reg->raw_writefn) { | |
6607 | src_reg->raw_writefn = raw_write; | |
6608 | } | |
6609 | src_reg->readfn = el2_e2h_read; | |
6610 | src_reg->writefn = el2_e2h_write; | |
6611 | } | |
6612 | } | |
6613 | #endif | |
6614 | ||
3f208fd7 PM |
6615 | static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
6616 | bool isread) | |
7da845b0 | 6617 | { |
97475a89 RH |
6618 | int cur_el = arm_current_el(env); |
6619 | ||
6620 | if (cur_el < 2) { | |
6621 | uint64_t hcr = arm_hcr_el2_eff(env); | |
6622 | ||
6623 | if (cur_el == 0) { | |
6624 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
6625 | if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) { | |
6626 | return CP_ACCESS_TRAP_EL2; | |
6627 | } | |
6628 | } else { | |
6629 | if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) { | |
6630 | return CP_ACCESS_TRAP; | |
6631 | } | |
6632 | if (hcr & HCR_TID2) { | |
6633 | return CP_ACCESS_TRAP_EL2; | |
6634 | } | |
6635 | } | |
6636 | } else if (hcr & HCR_TID2) { | |
6637 | return CP_ACCESS_TRAP_EL2; | |
6638 | } | |
7da845b0 | 6639 | } |
630fcd4d MZ |
6640 | |
6641 | if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) { | |
6642 | return CP_ACCESS_TRAP_EL2; | |
6643 | } | |
6644 | ||
7da845b0 PM |
6645 | return CP_ACCESS_OK; |
6646 | } | |
6647 | ||
58e93b48 RH |
6648 | /* |
6649 | * Check for traps to RAS registers, which are controlled | |
6650 | * by HCR_EL2.TERR and SCR_EL3.TERR. | |
6651 | */ | |
6652 | static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri, | |
6653 | bool isread) | |
6654 | { | |
6655 | int el = arm_current_el(env); | |
6656 | ||
6657 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) { | |
6658 | return CP_ACCESS_TRAP_EL2; | |
6659 | } | |
6660 | if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) { | |
6661 | return CP_ACCESS_TRAP_EL3; | |
6662 | } | |
6663 | return CP_ACCESS_OK; | |
6664 | } | |
6665 | ||
6666 | static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
6667 | { | |
6668 | int el = arm_current_el(env); | |
6669 | ||
6670 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { | |
6671 | return env->cp15.vdisr_el2; | |
6672 | } | |
6673 | if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { | |
6674 | return 0; /* RAZ/WI */ | |
6675 | } | |
6676 | return env->cp15.disr_el1; | |
6677 | } | |
6678 | ||
6679 | static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
6680 | { | |
6681 | int el = arm_current_el(env); | |
6682 | ||
6683 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { | |
6684 | env->cp15.vdisr_el2 = val; | |
6685 | return; | |
6686 | } | |
6687 | if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { | |
6688 | return; /* RAZ/WI */ | |
6689 | } | |
6690 | env->cp15.disr_el1 = val; | |
6691 | } | |
6692 | ||
6693 | /* | |
6694 | * Minimal RAS implementation with no Error Records. | |
6695 | * Which means that all of the Error Record registers: | |
6696 | * ERXADDR_EL1 | |
6697 | * ERXCTLR_EL1 | |
6698 | * ERXFR_EL1 | |
6699 | * ERXMISC0_EL1 | |
6700 | * ERXMISC1_EL1 | |
6701 | * ERXMISC2_EL1 | |
6702 | * ERXMISC3_EL1 | |
6703 | * ERXPFGCDN_EL1 (RASv1p1) | |
6704 | * ERXPFGCTL_EL1 (RASv1p1) | |
6705 | * ERXPFGF_EL1 (RASv1p1) | |
6706 | * ERXSTATUS_EL1 | |
6707 | * and | |
6708 | * ERRSELR_EL1 | |
6709 | * may generate UNDEFINED, which is the effect we get by not | |
6710 | * listing them at all. | |
bd8db7d9 PM |
6711 | * |
6712 | * These registers have fine-grained trap bits, but UNDEF-to-EL1 | |
6713 | * is higher priority than FGT-to-EL2 so we do not need to list them | |
6714 | * in order to check for an FGT. | |
58e93b48 RH |
6715 | */ |
6716 | static const ARMCPRegInfo minimal_ras_reginfo[] = { | |
6717 | { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH, | |
6718 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1, | |
6719 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1), | |
6720 | .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write }, | |
6721 | { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
6722 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0, | |
6723 | .access = PL1_R, .accessfn = access_terr, | |
bd8db7d9 | 6724 | .fgt = FGT_ERRIDR_EL1, |
58e93b48 RH |
6725 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
6726 | { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH, | |
6727 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1, | |
6728 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) }, | |
6729 | { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH, | |
6730 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3, | |
6731 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) }, | |
6732 | }; | |
6733 | ||
397d922c RH |
6734 | /* |
6735 | * Return the exception level to which exceptions should be taken | |
6736 | * via SVEAccessTrap. This excludes the check for whether the exception | |
6737 | * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily | |
6738 | * be found by testing 0 < fp_exception_el < sve_exception_el. | |
6739 | * | |
6740 | * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the | |
6741 | * pseudocode does *not* separate out the FP trap checks, but has them | |
6742 | * all in one function. | |
5be5e8ed | 6743 | */ |
ced31551 | 6744 | int sve_exception_el(CPUARMState *env, int el) |
5be5e8ed RH |
6745 | { |
6746 | #ifndef CONFIG_USER_ONLY | |
aa4451b6 | 6747 | if (el <= 1 && !el_is_in_host(env, el)) { |
fab8ad39 | 6748 | switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, ZEN)) { |
7701cee5 RH |
6749 | case 1: |
6750 | if (el != 0) { | |
6751 | break; | |
6752 | } | |
6753 | /* fall through */ | |
6754 | case 0: | |
6755 | case 2: | |
61a8c23a | 6756 | return 1; |
5be5e8ed | 6757 | } |
5be5e8ed RH |
6758 | } |
6759 | ||
7d38cb92 RH |
6760 | if (el <= 2 && arm_is_el2_enabled(env)) { |
6761 | /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */ | |
6762 | if (env->cp15.hcr_el2 & HCR_E2H) { | |
fab8ad39 | 6763 | switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, ZEN)) { |
d5a6fa2d | 6764 | case 1: |
7d38cb92 | 6765 | if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) { |
d5a6fa2d RH |
6766 | break; |
6767 | } | |
6768 | /* fall through */ | |
6769 | case 0: | |
6770 | case 2: | |
6771 | return 2; | |
6772 | } | |
7d38cb92 | 6773 | } else { |
fab8ad39 | 6774 | if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) { |
d5a6fa2d RH |
6775 | return 2; |
6776 | } | |
60eed086 | 6777 | } |
5be5e8ed RH |
6778 | } |
6779 | ||
60eed086 RH |
6780 | /* CPTR_EL3. Since EZ is negative we must check for EL3. */ |
6781 | if (arm_feature(env, ARM_FEATURE_EL3) | |
fab8ad39 | 6782 | && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, EZ)) { |
5be5e8ed RH |
6783 | return 3; |
6784 | } | |
6785 | #endif | |
6786 | return 0; | |
6787 | } | |
6788 | ||
6b2ca83e RH |
6789 | /* |
6790 | * Return the exception level to which exceptions should be taken for SME. | |
6791 | * C.f. the ARM pseudocode function CheckSMEAccess. | |
6792 | */ | |
6793 | int sme_exception_el(CPUARMState *env, int el) | |
6794 | { | |
6795 | #ifndef CONFIG_USER_ONLY | |
6796 | if (el <= 1 && !el_is_in_host(env, el)) { | |
6797 | switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, SMEN)) { | |
6798 | case 1: | |
6799 | if (el != 0) { | |
6800 | break; | |
6801 | } | |
6802 | /* fall through */ | |
6803 | case 0: | |
6804 | case 2: | |
6805 | return 1; | |
6806 | } | |
6807 | } | |
6808 | ||
6809 | if (el <= 2 && arm_is_el2_enabled(env)) { | |
6810 | /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */ | |
6811 | if (env->cp15.hcr_el2 & HCR_E2H) { | |
6812 | switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, SMEN)) { | |
6813 | case 1: | |
6814 | if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) { | |
6815 | break; | |
6816 | } | |
6817 | /* fall through */ | |
6818 | case 0: | |
6819 | case 2: | |
6820 | return 2; | |
6821 | } | |
6822 | } else { | |
6823 | if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TSM)) { | |
6824 | return 2; | |
6825 | } | |
6826 | } | |
6827 | } | |
6828 | ||
6829 | /* CPTR_EL3. Since ESM is negative we must check for EL3. */ | |
6830 | if (arm_feature(env, ARM_FEATURE_EL3) | |
6831 | && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { | |
6832 | return 3; | |
6833 | } | |
6834 | #endif | |
6835 | return 0; | |
6836 | } | |
6837 | ||
0ab5953b RH |
6838 | /* |
6839 | * Given that SVE is enabled, return the vector length for EL. | |
6840 | */ | |
6ca54aa9 | 6841 | uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm) |
0ab5953b | 6842 | { |
2fc0cc0e | 6843 | ARMCPU *cpu = env_archcpu(env); |
6ca54aa9 RH |
6844 | uint64_t *cr = env->vfp.zcr_el; |
6845 | uint32_t map = cpu->sve_vq.map; | |
6846 | uint32_t len = ARM_MAX_VQ - 1; | |
6847 | ||
6848 | if (sm) { | |
6849 | cr = env->vfp.smcr_el; | |
6850 | map = cpu->sme_vq.map; | |
6851 | } | |
0ab5953b | 6852 | |
c6225beb | 6853 | if (el <= 1 && !el_is_in_host(env, el)) { |
6ca54aa9 | 6854 | len = MIN(len, 0xf & (uint32_t)cr[1]); |
0ab5953b | 6855 | } |
6a02a732 | 6856 | if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) { |
6ca54aa9 | 6857 | len = MIN(len, 0xf & (uint32_t)cr[2]); |
0ab5953b | 6858 | } |
6a02a732 | 6859 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
6ca54aa9 RH |
6860 | len = MIN(len, 0xf & (uint32_t)cr[3]); |
6861 | } | |
6862 | ||
6863 | map &= MAKE_64BIT_MASK(0, len + 1); | |
6864 | if (map != 0) { | |
6865 | return 31 - clz32(map); | |
0ab5953b | 6866 | } |
0df9142d | 6867 | |
6ca54aa9 RH |
6868 | /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */ |
6869 | assert(sm); | |
6870 | return ctz32(cpu->sme_vq.map); | |
6871 | } | |
6872 | ||
6873 | uint32_t sve_vqm1_for_el(CPUARMState *env, int el) | |
6874 | { | |
6875 | return sve_vqm1_for_el_sm(env, el, FIELD_EX64(env->svcr, SVCR, SM)); | |
0ab5953b RH |
6876 | } |
6877 | ||
5be5e8ed RH |
6878 | static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
6879 | uint64_t value) | |
6880 | { | |
0ab5953b | 6881 | int cur_el = arm_current_el(env); |
5ef3cc56 | 6882 | int old_len = sve_vqm1_for_el(env, cur_el); |
0ab5953b RH |
6883 | int new_len; |
6884 | ||
5be5e8ed | 6885 | /* Bits other than [3:0] are RAZ/WI. */ |
7b351d98 | 6886 | QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16); |
5be5e8ed | 6887 | raw_write(env, ri, value & 0xf); |
0ab5953b RH |
6888 | |
6889 | /* | |
6890 | * Because we arrived here, we know both FP and SVE are enabled; | |
6891 | * otherwise we would have trapped access to the ZCR_ELn register. | |
6892 | */ | |
5ef3cc56 | 6893 | new_len = sve_vqm1_for_el(env, cur_el); |
0ab5953b RH |
6894 | if (new_len < old_len) { |
6895 | aarch64_sve_narrow_vq(env, new_len + 1); | |
6896 | } | |
5be5e8ed RH |
6897 | } |
6898 | ||
60360d82 RH |
6899 | static const ARMCPRegInfo zcr_reginfo[] = { |
6900 | { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | |
6901 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | |
6902 | .access = PL1_RW, .type = ARM_CP_SVE, | |
6903 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), | |
6904 | .writefn = zcr_write, .raw_writefn = raw_write }, | |
6905 | { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | |
6906 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | |
6907 | .access = PL2_RW, .type = ARM_CP_SVE, | |
6908 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), | |
6909 | .writefn = zcr_write, .raw_writefn = raw_write }, | |
6910 | { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | |
6911 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | |
6912 | .access = PL3_RW, .type = ARM_CP_SVE, | |
6913 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), | |
6914 | .writefn = zcr_write, .raw_writefn = raw_write }, | |
5be5e8ed RH |
6915 | }; |
6916 | ||
9e5ec745 RH |
6917 | #ifdef TARGET_AARCH64 |
6918 | static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri, | |
6919 | bool isread) | |
6920 | { | |
6921 | int el = arm_current_el(env); | |
6922 | ||
6923 | if (el == 0) { | |
6924 | uint64_t sctlr = arm_sctlr(env, el); | |
6925 | if (!(sctlr & SCTLR_EnTP2)) { | |
6926 | return CP_ACCESS_TRAP; | |
6927 | } | |
6928 | } | |
6929 | /* TODO: FEAT_FGT */ | |
6930 | if (el < 3 | |
6931 | && arm_feature(env, ARM_FEATURE_EL3) | |
6932 | && !(env->cp15.scr_el3 & SCR_ENTP2)) { | |
6933 | return CP_ACCESS_TRAP_EL3; | |
6934 | } | |
6935 | return CP_ACCESS_OK; | |
6936 | } | |
6937 | ||
d5b1223a RH |
6938 | static CPAccessResult access_esm(CPUARMState *env, const ARMCPRegInfo *ri, |
6939 | bool isread) | |
6940 | { | |
6941 | /* TODO: FEAT_FGT for SMPRI_EL1 but not SMPRIMAP_EL2 */ | |
6942 | if (arm_current_el(env) < 3 | |
6943 | && arm_feature(env, ARM_FEATURE_EL3) | |
6944 | && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { | |
6945 | return CP_ACCESS_TRAP_EL3; | |
6946 | } | |
6947 | return CP_ACCESS_OK; | |
6948 | } | |
6949 | ||
7f2a01e7 RH |
6950 | /* ResetSVEState */ |
6951 | static void arm_reset_sve_state(CPUARMState *env) | |
6952 | { | |
6953 | memset(env->vfp.zregs, 0, sizeof(env->vfp.zregs)); | |
6954 | /* Recall that FFR is stored as pregs[16]. */ | |
6955 | memset(env->vfp.pregs, 0, sizeof(env->vfp.pregs)); | |
6956 | vfp_set_fpcr(env, 0x0800009f); | |
6957 | } | |
6958 | ||
2a8af382 RH |
6959 | void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask) |
6960 | { | |
6961 | uint64_t change = (env->svcr ^ new) & mask; | |
6962 | ||
f4318557 RH |
6963 | if (change == 0) { |
6964 | return; | |
6965 | } | |
2a8af382 | 6966 | env->svcr ^= change; |
7f2a01e7 RH |
6967 | |
6968 | if (change & R_SVCR_SM_MASK) { | |
6969 | arm_reset_sve_state(env); | |
6970 | } | |
fccb4918 RH |
6971 | |
6972 | /* | |
6973 | * ResetSMEState. | |
6974 | * | |
6975 | * SetPSTATE_ZA zeros on enable and disable. We can zero this only | |
6976 | * on enable: while disabled, the storage is inaccessible and the | |
6977 | * value does not matter. We're not saving the storage in vmstate | |
6978 | * when disabled either. | |
6979 | */ | |
6980 | if (change & new & R_SVCR_ZA_MASK) { | |
6981 | memset(env->zarray, 0, sizeof(env->zarray)); | |
6982 | } | |
f4318557 | 6983 | |
2b77ad4d FR |
6984 | if (tcg_enabled()) { |
6985 | arm_rebuild_hflags(env); | |
6986 | } | |
2a8af382 RH |
6987 | } |
6988 | ||
c37e6ac9 RH |
6989 | static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
6990 | uint64_t value) | |
6991 | { | |
2a8af382 | 6992 | aarch64_set_svcr(env, value, -1); |
c37e6ac9 RH |
6993 | } |
6994 | ||
de561988 RH |
6995 | static void smcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
6996 | uint64_t value) | |
6997 | { | |
6998 | int cur_el = arm_current_el(env); | |
6999 | int old_len = sve_vqm1_for_el(env, cur_el); | |
7000 | int new_len; | |
7001 | ||
7002 | QEMU_BUILD_BUG_ON(ARM_MAX_VQ > R_SMCR_LEN_MASK + 1); | |
7003 | value &= R_SMCR_LEN_MASK | R_SMCR_FA64_MASK; | |
7004 | raw_write(env, ri, value); | |
7005 | ||
7006 | /* | |
7007 | * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage | |
7008 | * when SVL is widened (old values kept, or zeros). Choose to keep the | |
7009 | * current values for simplicity. But for QEMU internals, we must still | |
7010 | * apply the narrower SVL to the Zregs and Pregs -- see the comment | |
7011 | * above aarch64_sve_narrow_vq. | |
7012 | */ | |
7013 | new_len = sve_vqm1_for_el(env, cur_el); | |
7014 | if (new_len < old_len) { | |
7015 | aarch64_sve_narrow_vq(env, new_len + 1); | |
7016 | } | |
7017 | } | |
7018 | ||
9e5ec745 RH |
7019 | static const ARMCPRegInfo sme_reginfo[] = { |
7020 | { .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64, | |
7021 | .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5, | |
7022 | .access = PL0_RW, .accessfn = access_tpidr2, | |
bd8db7d9 | 7023 | .fgt = FGT_NTPIDR2_EL0, |
9e5ec745 | 7024 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) }, |
c37e6ac9 RH |
7025 | { .name = "SVCR", .state = ARM_CP_STATE_AA64, |
7026 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 2, | |
7027 | .access = PL0_RW, .type = ARM_CP_SME, | |
7028 | .fieldoffset = offsetof(CPUARMState, svcr), | |
7029 | .writefn = svcr_write, .raw_writefn = raw_write }, | |
de561988 RH |
7030 | { .name = "SMCR_EL1", .state = ARM_CP_STATE_AA64, |
7031 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 6, | |
7032 | .access = PL1_RW, .type = ARM_CP_SME, | |
7033 | .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[1]), | |
7034 | .writefn = smcr_write, .raw_writefn = raw_write }, | |
7035 | { .name = "SMCR_EL2", .state = ARM_CP_STATE_AA64, | |
7036 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 6, | |
7037 | .access = PL2_RW, .type = ARM_CP_SME, | |
7038 | .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[2]), | |
7039 | .writefn = smcr_write, .raw_writefn = raw_write }, | |
7040 | { .name = "SMCR_EL3", .state = ARM_CP_STATE_AA64, | |
7041 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 6, | |
7042 | .access = PL3_RW, .type = ARM_CP_SME, | |
7043 | .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[3]), | |
7044 | .writefn = smcr_write, .raw_writefn = raw_write }, | |
d5b1223a RH |
7045 | { .name = "SMIDR_EL1", .state = ARM_CP_STATE_AA64, |
7046 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 6, | |
7047 | .access = PL1_R, .accessfn = access_aa64_tid1, | |
7048 | /* | |
7049 | * IMPLEMENTOR = 0 (software) | |
7050 | * REVISION = 0 (implementation defined) | |
7051 | * SMPS = 0 (no streaming execution priority in QEMU) | |
7052 | * AFFINITY = 0 (streaming sve mode not shared with other PEs) | |
7053 | */ | |
7054 | .type = ARM_CP_CONST, .resetvalue = 0, }, | |
7055 | /* | |
7056 | * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0. | |
7057 | */ | |
7058 | { .name = "SMPRI_EL1", .state = ARM_CP_STATE_AA64, | |
7059 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 4, | |
7060 | .access = PL1_RW, .accessfn = access_esm, | |
bd8db7d9 | 7061 | .fgt = FGT_NSMPRI_EL1, |
d5b1223a RH |
7062 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
7063 | { .name = "SMPRIMAP_EL2", .state = ARM_CP_STATE_AA64, | |
7064 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 5, | |
7065 | .access = PL2_RW, .accessfn = access_esm, | |
7066 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
9e5ec745 | 7067 | }; |
ef1febe7 RH |
7068 | |
7069 | static void tlbi_aa64_paall_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
7070 | uint64_t value) | |
7071 | { | |
7072 | CPUState *cs = env_cpu(env); | |
7073 | ||
7074 | tlb_flush(cs); | |
7075 | } | |
7076 | ||
7077 | static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
7078 | uint64_t value) | |
7079 | { | |
7080 | /* L0GPTSZ is RO; other bits not mentioned are RES0. */ | |
7081 | uint64_t rw_mask = R_GPCCR_PPS_MASK | R_GPCCR_IRGN_MASK | | |
7082 | R_GPCCR_ORGN_MASK | R_GPCCR_SH_MASK | R_GPCCR_PGS_MASK | | |
7083 | R_GPCCR_GPC_MASK | R_GPCCR_GPCP_MASK; | |
7084 | ||
7085 | env->cp15.gpccr_el3 = (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw_mask); | |
7086 | } | |
7087 | ||
7088 | static void gpccr_reset(CPUARMState *env, const ARMCPRegInfo *ri) | |
7089 | { | |
7090 | env->cp15.gpccr_el3 = FIELD_DP64(0, GPCCR, L0GPTSZ, | |
7091 | env_archcpu(env)->reset_l0gptsz); | |
7092 | } | |
7093 | ||
7094 | static void tlbi_aa64_paallos_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
7095 | uint64_t value) | |
7096 | { | |
7097 | CPUState *cs = env_cpu(env); | |
7098 | ||
7099 | tlb_flush_all_cpus_synced(cs); | |
7100 | } | |
7101 | ||
7102 | static const ARMCPRegInfo rme_reginfo[] = { | |
7103 | { .name = "GPCCR_EL3", .state = ARM_CP_STATE_AA64, | |
7104 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 6, | |
7105 | .access = PL3_RW, .writefn = gpccr_write, .resetfn = gpccr_reset, | |
7106 | .fieldoffset = offsetof(CPUARMState, cp15.gpccr_el3) }, | |
7107 | { .name = "GPTBR_EL3", .state = ARM_CP_STATE_AA64, | |
7108 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 4, | |
7109 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.gptbr_el3) }, | |
7110 | { .name = "MFAR_EL3", .state = ARM_CP_STATE_AA64, | |
7111 | .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 5, | |
7112 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mfar_el3) }, | |
7113 | { .name = "TLBI_PAALL", .state = ARM_CP_STATE_AA64, | |
7114 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 4, | |
7115 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7116 | .writefn = tlbi_aa64_paall_write }, | |
7117 | { .name = "TLBI_PAALLOS", .state = ARM_CP_STATE_AA64, | |
7118 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 4, | |
7119 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7120 | .writefn = tlbi_aa64_paallos_write }, | |
7121 | /* | |
7122 | * QEMU does not have a way to invalidate by physical address, thus | |
7123 | * invalidating a range of physical addresses is accomplished by | |
673d8215 | 7124 | * flushing all tlb entries in the outer shareable domain, |
ef1febe7 RH |
7125 | * just like PAALLOS. |
7126 | */ | |
7127 | { .name = "TLBI_RPALOS", .state = ARM_CP_STATE_AA64, | |
7128 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 7, | |
7129 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7130 | .writefn = tlbi_aa64_paallos_write }, | |
7131 | { .name = "TLBI_RPAOS", .state = ARM_CP_STATE_AA64, | |
7132 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 3, | |
7133 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7134 | .writefn = tlbi_aa64_paallos_write }, | |
7135 | { .name = "DC_CIPAPA", .state = ARM_CP_STATE_AA64, | |
7136 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 1, | |
7137 | .access = PL3_W, .type = ARM_CP_NOP }, | |
7138 | }; | |
7139 | ||
7140 | static const ARMCPRegInfo rme_mte_reginfo[] = { | |
7141 | { .name = "DC_CIGDPAPA", .state = ARM_CP_STATE_AA64, | |
7142 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 5, | |
7143 | .access = PL3_W, .type = ARM_CP_NOP }, | |
7144 | }; | |
9e5ec745 RH |
7145 | #endif /* TARGET_AARCH64 */ |
7146 | ||
24183fb6 PM |
7147 | static void define_pmu_regs(ARMCPU *cpu) |
7148 | { | |
7149 | /* | |
7150 | * v7 performance monitor control register: same implementor | |
7151 | * field as main ID register, and we implement four counters in | |
7152 | * addition to the cycle count register. | |
7153 | */ | |
24526bb9 | 7154 | unsigned int i, pmcrn = pmu_num_counters(&cpu->env); |
24183fb6 PM |
7155 | ARMCPRegInfo pmcr = { |
7156 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | |
7157 | .access = PL0_RW, | |
dc780233 | 7158 | .fgt = FGT_PMCR_EL0, |
24183fb6 PM |
7159 | .type = ARM_CP_IO | ARM_CP_ALIAS, |
7160 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), | |
7161 | .accessfn = pmreg_access, .writefn = pmcr_write, | |
7162 | .raw_writefn = raw_write, | |
7163 | }; | |
7164 | ARMCPRegInfo pmcr64 = { | |
7165 | .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, | |
7166 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, | |
7167 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 7168 | .fgt = FGT_PMCR_EL0, |
24183fb6 PM |
7169 | .type = ARM_CP_IO, |
7170 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), | |
24526bb9 | 7171 | .resetvalue = cpu->isar.reset_pmcr_el0, |
24183fb6 PM |
7172 | .writefn = pmcr_write, .raw_writefn = raw_write, |
7173 | }; | |
24526bb9 | 7174 | |
24183fb6 PM |
7175 | define_one_arm_cp_reg(cpu, &pmcr); |
7176 | define_one_arm_cp_reg(cpu, &pmcr64); | |
7177 | for (i = 0; i < pmcrn; i++) { | |
7178 | char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i); | |
7179 | char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i); | |
7180 | char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i); | |
7181 | char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i); | |
7182 | ARMCPRegInfo pmev_regs[] = { | |
7183 | { .name = pmevcntr_name, .cp = 15, .crn = 14, | |
7184 | .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, | |
7185 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
dc780233 | 7186 | .fgt = FGT_PMEVCNTRN_EL0, |
24183fb6 | 7187 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, |
99a50d1a | 7188 | .accessfn = pmreg_access_xevcntr }, |
24183fb6 PM |
7189 | { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64, |
7190 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)), | |
99a50d1a | 7191 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr, |
24183fb6 | 7192 | .type = ARM_CP_IO, |
dc780233 | 7193 | .fgt = FGT_PMEVCNTRN_EL0, |
24183fb6 PM |
7194 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, |
7195 | .raw_readfn = pmevcntr_rawread, | |
7196 | .raw_writefn = pmevcntr_rawwrite }, | |
7197 | { .name = pmevtyper_name, .cp = 15, .crn = 14, | |
7198 | .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, | |
7199 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
dc780233 | 7200 | .fgt = FGT_PMEVTYPERN_EL0, |
24183fb6 PM |
7201 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, |
7202 | .accessfn = pmreg_access }, | |
7203 | { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64, | |
7204 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)), | |
7205 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 7206 | .fgt = FGT_PMEVTYPERN_EL0, |
24183fb6 PM |
7207 | .type = ARM_CP_IO, |
7208 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | |
7209 | .raw_writefn = pmevtyper_rawwrite }, | |
24183fb6 PM |
7210 | }; |
7211 | define_arm_cp_regs(cpu, pmev_regs); | |
7212 | g_free(pmevcntr_name); | |
7213 | g_free(pmevcntr_el0_name); | |
7214 | g_free(pmevtyper_name); | |
7215 | g_free(pmevtyper_el0_name); | |
7216 | } | |
a793bcd0 | 7217 | if (cpu_isar_feature(aa32_pmuv3p1, cpu)) { |
24183fb6 PM |
7218 | ARMCPRegInfo v81_pmu_regs[] = { |
7219 | { .name = "PMCEID2", .state = ARM_CP_STATE_AA32, | |
7220 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4, | |
7221 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 7222 | .fgt = FGT_PMCEIDN_EL0, |
24183fb6 PM |
7223 | .resetvalue = extract64(cpu->pmceid0, 32, 32) }, |
7224 | { .name = "PMCEID3", .state = ARM_CP_STATE_AA32, | |
7225 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5, | |
7226 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 7227 | .fgt = FGT_PMCEIDN_EL0, |
24183fb6 | 7228 | .resetvalue = extract64(cpu->pmceid1, 32, 32) }, |
24183fb6 PM |
7229 | }; |
7230 | define_arm_cp_regs(cpu, v81_pmu_regs); | |
7231 | } | |
a793bcd0 | 7232 | if (cpu_isar_feature(any_pmuv3p4, cpu)) { |
15dd1ebd PM |
7233 | static const ARMCPRegInfo v84_pmmir = { |
7234 | .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH, | |
7235 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6, | |
7236 | .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 7237 | .fgt = FGT_PMMIR_EL1, |
15dd1ebd PM |
7238 | .resetvalue = 0 |
7239 | }; | |
7240 | define_one_arm_cp_reg(cpu, &v84_pmmir); | |
7241 | } | |
24183fb6 PM |
7242 | } |
7243 | ||
0f150c84 | 7244 | #ifndef CONFIG_USER_ONLY |
9b37a28c FR |
7245 | /* |
7246 | * We don't know until after realize whether there's a GICv3 | |
96a8b92e PM |
7247 | * attached, and that is what registers the gicv3 sysregs. |
7248 | * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1 | |
7249 | * at runtime. | |
7250 | */ | |
7251 | static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
7252 | { | |
2fc0cc0e | 7253 | ARMCPU *cpu = env_archcpu(env); |
8a130a7b | 7254 | uint64_t pfr1 = cpu->isar.id_pfr1; |
96a8b92e PM |
7255 | |
7256 | if (env->gicv3state) { | |
7257 | pfr1 |= 1 << 28; | |
7258 | } | |
7259 | return pfr1; | |
7260 | } | |
7261 | ||
7262 | static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
7263 | { | |
2fc0cc0e | 7264 | ARMCPU *cpu = env_archcpu(env); |
47576b94 | 7265 | uint64_t pfr0 = cpu->isar.id_aa64pfr0; |
96a8b92e PM |
7266 | |
7267 | if (env->gicv3state) { | |
7268 | pfr0 |= 1 << 24; | |
7269 | } | |
7270 | return pfr0; | |
7271 | } | |
976b99b6 | 7272 | #endif |
96a8b92e | 7273 | |
9b37a28c FR |
7274 | /* |
7275 | * Shared logic between LORID and the rest of the LOR* registers. | |
9bd268ba | 7276 | * Secure state exclusion has already been dealt with. |
2d7137c1 | 7277 | */ |
9bd268ba RDC |
7278 | static CPAccessResult access_lor_ns(CPUARMState *env, |
7279 | const ARMCPRegInfo *ri, bool isread) | |
2d7137c1 RH |
7280 | { |
7281 | int el = arm_current_el(env); | |
7282 | ||
7283 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) { | |
7284 | return CP_ACCESS_TRAP_EL2; | |
7285 | } | |
7286 | if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { | |
7287 | return CP_ACCESS_TRAP_EL3; | |
7288 | } | |
7289 | return CP_ACCESS_OK; | |
7290 | } | |
7291 | ||
2d7137c1 RH |
7292 | static CPAccessResult access_lor_other(CPUARMState *env, |
7293 | const ARMCPRegInfo *ri, bool isread) | |
7294 | { | |
7295 | if (arm_is_secure_below_el3(env)) { | |
7296 | /* Access denied in secure mode. */ | |
7297 | return CP_ACCESS_TRAP; | |
7298 | } | |
9bd268ba | 7299 | return access_lor_ns(env, ri, isread); |
2d7137c1 RH |
7300 | } |
7301 | ||
d8564ee4 RH |
7302 | /* |
7303 | * A trivial implementation of ARMv8.1-LOR leaves all of these | |
7304 | * registers fixed at 0, which indicates that there are zero | |
7305 | * supported Limited Ordering regions. | |
7306 | */ | |
7307 | static const ARMCPRegInfo lor_reginfo[] = { | |
7308 | { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, | |
7309 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, | |
7310 | .access = PL1_RW, .accessfn = access_lor_other, | |
b19ed03c | 7311 | .fgt = FGT_LORSA_EL1, |
d8564ee4 RH |
7312 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
7313 | { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, | |
7314 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, | |
7315 | .access = PL1_RW, .accessfn = access_lor_other, | |
b19ed03c | 7316 | .fgt = FGT_LOREA_EL1, |
d8564ee4 RH |
7317 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
7318 | { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, | |
7319 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, | |
7320 | .access = PL1_RW, .accessfn = access_lor_other, | |
b19ed03c | 7321 | .fgt = FGT_LORN_EL1, |
d8564ee4 RH |
7322 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
7323 | { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, | |
7324 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, | |
7325 | .access = PL1_RW, .accessfn = access_lor_other, | |
b19ed03c | 7326 | .fgt = FGT_LORC_EL1, |
d8564ee4 RH |
7327 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
7328 | { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, | |
7329 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, | |
9bd268ba | 7330 | .access = PL1_R, .accessfn = access_lor_ns, |
b19ed03c | 7331 | .fgt = FGT_LORID_EL1, |
d8564ee4 | 7332 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
d8564ee4 RH |
7333 | }; |
7334 | ||
967aa94f RH |
7335 | #ifdef TARGET_AARCH64 |
7336 | static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, | |
7337 | bool isread) | |
7338 | { | |
7339 | int el = arm_current_el(env); | |
7340 | ||
7341 | if (el < 2 && | |
07b034ea | 7342 | arm_is_el2_enabled(env) && |
967aa94f RH |
7343 | !(arm_hcr_el2_eff(env) & HCR_APK)) { |
7344 | return CP_ACCESS_TRAP_EL2; | |
7345 | } | |
7346 | if (el < 3 && | |
7347 | arm_feature(env, ARM_FEATURE_EL3) && | |
7348 | !(env->cp15.scr_el3 & SCR_APK)) { | |
7349 | return CP_ACCESS_TRAP_EL3; | |
7350 | } | |
7351 | return CP_ACCESS_OK; | |
7352 | } | |
7353 | ||
7354 | static const ARMCPRegInfo pauth_reginfo[] = { | |
7355 | { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64, | |
7356 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0, | |
7357 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7358 | .fgt = FGT_APDAKEY, |
108b3ba8 | 7359 | .fieldoffset = offsetof(CPUARMState, keys.apda.lo) }, |
967aa94f RH |
7360 | { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
7361 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1, | |
7362 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7363 | .fgt = FGT_APDAKEY, |
108b3ba8 | 7364 | .fieldoffset = offsetof(CPUARMState, keys.apda.hi) }, |
967aa94f RH |
7365 | { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
7366 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2, | |
7367 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7368 | .fgt = FGT_APDBKEY, |
108b3ba8 | 7369 | .fieldoffset = offsetof(CPUARMState, keys.apdb.lo) }, |
967aa94f RH |
7370 | { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
7371 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3, | |
7372 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7373 | .fgt = FGT_APDBKEY, |
108b3ba8 | 7374 | .fieldoffset = offsetof(CPUARMState, keys.apdb.hi) }, |
967aa94f RH |
7375 | { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
7376 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0, | |
7377 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7378 | .fgt = FGT_APGAKEY, |
108b3ba8 | 7379 | .fieldoffset = offsetof(CPUARMState, keys.apga.lo) }, |
967aa94f RH |
7380 | { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
7381 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1, | |
7382 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7383 | .fgt = FGT_APGAKEY, |
108b3ba8 | 7384 | .fieldoffset = offsetof(CPUARMState, keys.apga.hi) }, |
967aa94f RH |
7385 | { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
7386 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0, | |
7387 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7388 | .fgt = FGT_APIAKEY, |
108b3ba8 | 7389 | .fieldoffset = offsetof(CPUARMState, keys.apia.lo) }, |
967aa94f RH |
7390 | { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
7391 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1, | |
7392 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7393 | .fgt = FGT_APIAKEY, |
108b3ba8 | 7394 | .fieldoffset = offsetof(CPUARMState, keys.apia.hi) }, |
967aa94f RH |
7395 | { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
7396 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2, | |
7397 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7398 | .fgt = FGT_APIBKEY, |
108b3ba8 | 7399 | .fieldoffset = offsetof(CPUARMState, keys.apib.lo) }, |
967aa94f RH |
7400 | { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
7401 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3, | |
7402 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7403 | .fgt = FGT_APIBKEY, |
108b3ba8 | 7404 | .fieldoffset = offsetof(CPUARMState, keys.apib.hi) }, |
967aa94f | 7405 | }; |
de390645 | 7406 | |
84940ed8 RC |
7407 | static const ARMCPRegInfo tlbirange_reginfo[] = { |
7408 | { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64, | |
7409 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1, | |
0f66d223 | 7410 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7411 | .fgt = FGT_TLBIRVAE1IS, |
84940ed8 RC |
7412 | .writefn = tlbi_aa64_rvae1is_write }, |
7413 | { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64, | |
7414 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3, | |
0f66d223 | 7415 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7416 | .fgt = FGT_TLBIRVAAE1IS, |
84940ed8 RC |
7417 | .writefn = tlbi_aa64_rvae1is_write }, |
7418 | { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64, | |
7419 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5, | |
0f66d223 | 7420 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7421 | .fgt = FGT_TLBIRVALE1IS, |
84940ed8 RC |
7422 | .writefn = tlbi_aa64_rvae1is_write }, |
7423 | { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64, | |
7424 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7, | |
0f66d223 | 7425 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7426 | .fgt = FGT_TLBIRVAALE1IS, |
84940ed8 RC |
7427 | .writefn = tlbi_aa64_rvae1is_write }, |
7428 | { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64, | |
7429 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, | |
fe3ca86c | 7430 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7431 | .fgt = FGT_TLBIRVAE1OS, |
84940ed8 RC |
7432 | .writefn = tlbi_aa64_rvae1is_write }, |
7433 | { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64, | |
7434 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3, | |
fe3ca86c | 7435 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7436 | .fgt = FGT_TLBIRVAAE1OS, |
84940ed8 RC |
7437 | .writefn = tlbi_aa64_rvae1is_write }, |
7438 | { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64, | |
7439 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5, | |
fe3ca86c | 7440 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7441 | .fgt = FGT_TLBIRVALE1OS, |
84940ed8 RC |
7442 | .writefn = tlbi_aa64_rvae1is_write }, |
7443 | { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64, | |
7444 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7, | |
fe3ca86c | 7445 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7446 | .fgt = FGT_TLBIRVAALE1OS, |
84940ed8 RC |
7447 | .writefn = tlbi_aa64_rvae1is_write }, |
7448 | { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64, | |
7449 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, | |
4870f38b | 7450 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7451 | .fgt = FGT_TLBIRVAE1, |
84940ed8 RC |
7452 | .writefn = tlbi_aa64_rvae1_write }, |
7453 | { .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64, | |
7454 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3, | |
4870f38b | 7455 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7456 | .fgt = FGT_TLBIRVAAE1, |
84940ed8 RC |
7457 | .writefn = tlbi_aa64_rvae1_write }, |
7458 | { .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64, | |
7459 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5, | |
4870f38b | 7460 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7461 | .fgt = FGT_TLBIRVALE1, |
84940ed8 RC |
7462 | .writefn = tlbi_aa64_rvae1_write }, |
7463 | { .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64, | |
7464 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7, | |
4870f38b | 7465 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7466 | .fgt = FGT_TLBIRVAALE1, |
84940ed8 RC |
7467 | .writefn = tlbi_aa64_rvae1_write }, |
7468 | { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64, | |
7469 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2, | |
575a94af RH |
7470 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
7471 | .writefn = tlbi_aa64_ripas2e1is_write }, | |
84940ed8 RC |
7472 | { .name = "TLBI_RIPAS2LE1IS", .state = ARM_CP_STATE_AA64, |
7473 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 6, | |
575a94af RH |
7474 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
7475 | .writefn = tlbi_aa64_ripas2e1is_write }, | |
84940ed8 RC |
7476 | { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64, |
7477 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1, | |
696ba377 | 7478 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
7479 | .writefn = tlbi_aa64_rvae2is_write }, |
7480 | { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64, | |
7481 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5, | |
696ba377 | 7482 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
7483 | .writefn = tlbi_aa64_rvae2is_write }, |
7484 | { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64, | |
7485 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2, | |
575a94af RH |
7486 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
7487 | .writefn = tlbi_aa64_ripas2e1_write }, | |
7488 | { .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64, | |
84940ed8 | 7489 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 6, |
575a94af RH |
7490 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
7491 | .writefn = tlbi_aa64_ripas2e1_write }, | |
84940ed8 RC |
7492 | { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64, |
7493 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1, | |
696ba377 | 7494 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
7495 | .writefn = tlbi_aa64_rvae2is_write }, |
7496 | { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64, | |
7497 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5, | |
696ba377 | 7498 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
7499 | .writefn = tlbi_aa64_rvae2is_write }, |
7500 | { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64, | |
7501 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1, | |
696ba377 | 7502 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
7503 | .writefn = tlbi_aa64_rvae2_write }, |
7504 | { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64, | |
7505 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5, | |
696ba377 | 7506 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
7507 | .writefn = tlbi_aa64_rvae2_write }, |
7508 | { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64, | |
7509 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1, | |
7510 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7511 | .writefn = tlbi_aa64_rvae3is_write }, | |
7512 | { .name = "TLBI_RVALE3IS", .state = ARM_CP_STATE_AA64, | |
7513 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 5, | |
7514 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7515 | .writefn = tlbi_aa64_rvae3is_write }, | |
7516 | { .name = "TLBI_RVAE3OS", .state = ARM_CP_STATE_AA64, | |
7517 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 1, | |
7518 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7519 | .writefn = tlbi_aa64_rvae3is_write }, | |
7520 | { .name = "TLBI_RVALE3OS", .state = ARM_CP_STATE_AA64, | |
7521 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 5, | |
7522 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7523 | .writefn = tlbi_aa64_rvae3is_write }, | |
7524 | { .name = "TLBI_RVAE3", .state = ARM_CP_STATE_AA64, | |
7525 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 1, | |
7526 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7527 | .writefn = tlbi_aa64_rvae3_write }, | |
7528 | { .name = "TLBI_RVALE3", .state = ARM_CP_STATE_AA64, | |
7529 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5, | |
7530 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7531 | .writefn = tlbi_aa64_rvae3_write }, | |
84940ed8 RC |
7532 | }; |
7533 | ||
7113d618 RC |
7534 | static const ARMCPRegInfo tlbios_reginfo[] = { |
7535 | { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64, | |
7536 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0, | |
fe3ca86c | 7537 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7538 | .fgt = FGT_TLBIVMALLE1OS, |
7113d618 | 7539 | .writefn = tlbi_aa64_vmalle1is_write }, |
b7469ef9 IH |
7540 | { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64, |
7541 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1, | |
bf2f0625 | 7542 | .fgt = FGT_TLBIVAE1OS, |
fe3ca86c | 7543 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
b7469ef9 | 7544 | .writefn = tlbi_aa64_vae1is_write }, |
7113d618 RC |
7545 | { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64, |
7546 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2, | |
fe3ca86c | 7547 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7548 | .fgt = FGT_TLBIASIDE1OS, |
7113d618 | 7549 | .writefn = tlbi_aa64_vmalle1is_write }, |
b7469ef9 IH |
7550 | { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64, |
7551 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3, | |
fe3ca86c | 7552 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7553 | .fgt = FGT_TLBIVAAE1OS, |
b7469ef9 IH |
7554 | .writefn = tlbi_aa64_vae1is_write }, |
7555 | { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64, | |
7556 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5, | |
fe3ca86c | 7557 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7558 | .fgt = FGT_TLBIVALE1OS, |
b7469ef9 IH |
7559 | .writefn = tlbi_aa64_vae1is_write }, |
7560 | { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64, | |
7561 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7, | |
fe3ca86c | 7562 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7563 | .fgt = FGT_TLBIVAALE1OS, |
b7469ef9 | 7564 | .writefn = tlbi_aa64_vae1is_write }, |
7113d618 RC |
7565 | { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64, |
7566 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0, | |
696ba377 | 7567 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
7113d618 | 7568 | .writefn = tlbi_aa64_alle2is_write }, |
b7469ef9 IH |
7569 | { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64, |
7570 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1, | |
696ba377 | 7571 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
b7469ef9 | 7572 | .writefn = tlbi_aa64_vae2is_write }, |
7113d618 RC |
7573 | { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64, |
7574 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4, | |
7575 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
7576 | .writefn = tlbi_aa64_alle1is_write }, | |
b7469ef9 IH |
7577 | { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64, |
7578 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5, | |
696ba377 | 7579 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
b7469ef9 | 7580 | .writefn = tlbi_aa64_vae2is_write }, |
7113d618 RC |
7581 | { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64, |
7582 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6, | |
7583 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
7584 | .writefn = tlbi_aa64_alle1is_write }, | |
7585 | { .name = "TLBI_IPAS2E1OS", .state = ARM_CP_STATE_AA64, | |
7586 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 0, | |
7587 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7588 | { .name = "TLBI_RIPAS2E1OS", .state = ARM_CP_STATE_AA64, | |
7589 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 3, | |
7590 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7591 | { .name = "TLBI_IPAS2LE1OS", .state = ARM_CP_STATE_AA64, | |
7592 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 4, | |
7593 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7594 | { .name = "TLBI_RIPAS2LE1OS", .state = ARM_CP_STATE_AA64, | |
7595 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 7, | |
7596 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7597 | { .name = "TLBI_ALLE3OS", .state = ARM_CP_STATE_AA64, | |
7598 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 0, | |
7599 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7600 | .writefn = tlbi_aa64_alle3is_write }, | |
b7469ef9 IH |
7601 | { .name = "TLBI_VAE3OS", .state = ARM_CP_STATE_AA64, |
7602 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 1, | |
7603 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7604 | .writefn = tlbi_aa64_vae3is_write }, | |
7605 | { .name = "TLBI_VALE3OS", .state = ARM_CP_STATE_AA64, | |
7606 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5, | |
7607 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7608 | .writefn = tlbi_aa64_vae3is_write }, | |
7113d618 RC |
7609 | }; |
7610 | ||
de390645 RH |
7611 | static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) |
7612 | { | |
7613 | Error *err = NULL; | |
7614 | uint64_t ret; | |
7615 | ||
7616 | /* Success sets NZCV = 0000. */ | |
7617 | env->NF = env->CF = env->VF = 0, env->ZF = 1; | |
7618 | ||
7619 | if (qemu_guest_getrandom(&ret, sizeof(ret), &err) < 0) { | |
7620 | /* | |
7621 | * ??? Failed, for unknown reasons in the crypto subsystem. | |
7622 | * The best we can do is log the reason and return the | |
7623 | * timed-out indication to the guest. There is no reason | |
7624 | * we know to expect this failure to be transitory, so the | |
7625 | * guest may well hang retrying the operation. | |
7626 | */ | |
7627 | qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", | |
7628 | ri->name, error_get_pretty(err)); | |
7629 | error_free(err); | |
7630 | ||
7631 | env->ZF = 0; /* NZCF = 0100 */ | |
7632 | return 0; | |
7633 | } | |
7634 | return ret; | |
7635 | } | |
7636 | ||
7637 | /* We do not support re-seeding, so the two registers operate the same. */ | |
7638 | static const ARMCPRegInfo rndr_reginfo[] = { | |
7639 | { .name = "RNDR", .state = ARM_CP_STATE_AA64, | |
7640 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | |
7641 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 0, | |
7642 | .access = PL0_R, .readfn = rndr_readfn }, | |
7643 | { .name = "RNDRRS", .state = ARM_CP_STATE_AA64, | |
7644 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | |
7645 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1, | |
7646 | .access = PL0_R, .readfn = rndr_readfn }, | |
de390645 | 7647 | }; |
0d57b499 | 7648 | |
0d57b499 BM |
7649 | static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, |
7650 | uint64_t value) | |
7651 | { | |
7a3014a9 | 7652 | #ifdef CONFIG_TCG |
0d57b499 BM |
7653 | ARMCPU *cpu = env_archcpu(env); |
7654 | /* CTR_EL0 System register -> DminLine, bits [19:16] */ | |
7655 | uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF); | |
7656 | uint64_t vaddr_in = (uint64_t) value; | |
7657 | uint64_t vaddr = vaddr_in & ~(dline_size - 1); | |
7658 | void *haddr; | |
7659 | int mem_idx = cpu_mmu_index(env, false); | |
7660 | ||
7661 | /* This won't be crossing page boundaries */ | |
7662 | haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC()); | |
7663 | if (haddr) { | |
cd4a47f9 | 7664 | #ifndef CONFIG_USER_ONLY |
0d57b499 BM |
7665 | |
7666 | ram_addr_t offset; | |
7667 | MemoryRegion *mr; | |
7668 | ||
7669 | /* RCU lock is already being held */ | |
7670 | mr = memory_region_from_host(haddr, &offset); | |
7671 | ||
7672 | if (mr) { | |
4dfe59d1 | 7673 | memory_region_writeback(mr, offset, dline_size); |
0d57b499 | 7674 | } |
cd4a47f9 | 7675 | #endif /*CONFIG_USER_ONLY*/ |
0d57b499 | 7676 | } |
7a3014a9 PMD |
7677 | #else |
7678 | /* Handled by hardware accelerator. */ | |
7679 | g_assert_not_reached(); | |
7680 | #endif /* CONFIG_TCG */ | |
0d57b499 BM |
7681 | } |
7682 | ||
7683 | static const ARMCPRegInfo dcpop_reg[] = { | |
7684 | { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64, | |
7685 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1, | |
7686 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | |
dd345653 | 7687 | .fgt = FGT_DCCVAP, |
1bed4d2e | 7688 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, |
0d57b499 BM |
7689 | }; |
7690 | ||
7691 | static const ARMCPRegInfo dcpodp_reg[] = { | |
7692 | { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64, | |
7693 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1, | |
7694 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | |
dd345653 | 7695 | .fgt = FGT_DCCVADP, |
1bed4d2e | 7696 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, |
0d57b499 | 7697 | }; |
0d57b499 | 7698 | |
4b779ceb RH |
7699 | static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInfo *ri, |
7700 | bool isread) | |
7701 | { | |
7702 | if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID5)) { | |
7703 | return CP_ACCESS_TRAP_EL2; | |
7704 | } | |
7705 | ||
7706 | return CP_ACCESS_OK; | |
7707 | } | |
7708 | ||
7709 | static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri, | |
7710 | bool isread) | |
7711 | { | |
7712 | int el = arm_current_el(env); | |
7713 | ||
0da067f2 | 7714 | if (el < 2 && arm_is_el2_enabled(env)) { |
4301acd7 RH |
7715 | uint64_t hcr = arm_hcr_el2_eff(env); |
7716 | if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { | |
7717 | return CP_ACCESS_TRAP_EL2; | |
7718 | } | |
4b779ceb RH |
7719 | } |
7720 | if (el < 3 && | |
7721 | arm_feature(env, ARM_FEATURE_EL3) && | |
7722 | !(env->cp15.scr_el3 & SCR_ATA)) { | |
7723 | return CP_ACCESS_TRAP_EL3; | |
7724 | } | |
7725 | return CP_ACCESS_OK; | |
7726 | } | |
7727 | ||
7728 | static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
7729 | { | |
7730 | return env->pstate & PSTATE_TCO; | |
7731 | } | |
7732 | ||
7733 | static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
7734 | { | |
7735 | env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); | |
7736 | } | |
7737 | ||
7738 | static const ARMCPRegInfo mte_reginfo[] = { | |
7739 | { .name = "TFSRE0_EL1", .state = ARM_CP_STATE_AA64, | |
7740 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 1, | |
7741 | .access = PL1_RW, .accessfn = access_mte, | |
7742 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) }, | |
7743 | { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64, | |
7744 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 0, | |
7745 | .access = PL1_RW, .accessfn = access_mte, | |
7746 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) }, | |
7747 | { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64, | |
7748 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 6, .opc2 = 0, | |
7749 | .access = PL2_RW, .accessfn = access_mte, | |
7750 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) }, | |
7751 | { .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64, | |
7752 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 6, .opc2 = 0, | |
7753 | .access = PL3_RW, | |
7754 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) }, | |
7755 | { .name = "RGSR_EL1", .state = ARM_CP_STATE_AA64, | |
7756 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5, | |
7757 | .access = PL1_RW, .accessfn = access_mte, | |
7758 | .fieldoffset = offsetof(CPUARMState, cp15.rgsr_el1) }, | |
7759 | { .name = "GCR_EL1", .state = ARM_CP_STATE_AA64, | |
7760 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6, | |
7761 | .access = PL1_RW, .accessfn = access_mte, | |
7762 | .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, | |
4b779ceb RH |
7763 | { .name = "TCO", .state = ARM_CP_STATE_AA64, |
7764 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | |
7765 | .type = ARM_CP_NO_RAW, | |
7766 | .access = PL0_RW, .readfn = tco_read, .writefn = tco_write }, | |
5463df16 RH |
7767 | { .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64, |
7768 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3, | |
7769 | .type = ARM_CP_NOP, .access = PL1_W, | |
dd345653 | 7770 | .fgt = FGT_DCIVAC, |
5463df16 RH |
7771 | .accessfn = aa64_cacheop_poc_access }, |
7772 | { .name = "DC_IGSW", .state = ARM_CP_STATE_AA64, | |
7773 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4, | |
dd345653 | 7774 | .fgt = FGT_DCISW, |
5463df16 RH |
7775 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
7776 | { .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64, | |
7777 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5, | |
7778 | .type = ARM_CP_NOP, .access = PL1_W, | |
dd345653 | 7779 | .fgt = FGT_DCIVAC, |
5463df16 RH |
7780 | .accessfn = aa64_cacheop_poc_access }, |
7781 | { .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64, | |
7782 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6, | |
dd345653 | 7783 | .fgt = FGT_DCISW, |
5463df16 RH |
7784 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
7785 | { .name = "DC_CGSW", .state = ARM_CP_STATE_AA64, | |
7786 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4, | |
dd345653 | 7787 | .fgt = FGT_DCCSW, |
5463df16 RH |
7788 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
7789 | { .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64, | |
7790 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6, | |
dd345653 | 7791 | .fgt = FGT_DCCSW, |
5463df16 RH |
7792 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
7793 | { .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64, | |
7794 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4, | |
dd345653 | 7795 | .fgt = FGT_DCCISW, |
5463df16 RH |
7796 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
7797 | { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64, | |
7798 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6, | |
dd345653 | 7799 | .fgt = FGT_DCCISW, |
5463df16 | 7800 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
4b779ceb RH |
7801 | }; |
7802 | ||
7803 | static const ARMCPRegInfo mte_tco_ro_reginfo[] = { | |
7804 | { .name = "TCO", .state = ARM_CP_STATE_AA64, | |
7805 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | |
7806 | .type = ARM_CP_CONST, .access = PL0_RW, }, | |
4b779ceb | 7807 | }; |
5463df16 RH |
7808 | |
7809 | static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | |
7810 | { .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64, | |
7811 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3, | |
7812 | .type = ARM_CP_NOP, .access = PL0_W, | |
950037e2 | 7813 | .fgt = FGT_DCCVAC, |
5463df16 RH |
7814 | .accessfn = aa64_cacheop_poc_access }, |
7815 | { .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64, | |
7816 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5, | |
7817 | .type = ARM_CP_NOP, .access = PL0_W, | |
950037e2 | 7818 | .fgt = FGT_DCCVAC, |
5463df16 RH |
7819 | .accessfn = aa64_cacheop_poc_access }, |
7820 | { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64, | |
7821 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3, | |
7822 | .type = ARM_CP_NOP, .access = PL0_W, | |
dd345653 | 7823 | .fgt = FGT_DCCVAP, |
5463df16 RH |
7824 | .accessfn = aa64_cacheop_poc_access }, |
7825 | { .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64, | |
7826 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5, | |
7827 | .type = ARM_CP_NOP, .access = PL0_W, | |
dd345653 | 7828 | .fgt = FGT_DCCVAP, |
5463df16 RH |
7829 | .accessfn = aa64_cacheop_poc_access }, |
7830 | { .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64, | |
7831 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3, | |
7832 | .type = ARM_CP_NOP, .access = PL0_W, | |
dd345653 | 7833 | .fgt = FGT_DCCVADP, |
5463df16 RH |
7834 | .accessfn = aa64_cacheop_poc_access }, |
7835 | { .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64, | |
7836 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5, | |
7837 | .type = ARM_CP_NOP, .access = PL0_W, | |
dd345653 | 7838 | .fgt = FGT_DCCVADP, |
5463df16 RH |
7839 | .accessfn = aa64_cacheop_poc_access }, |
7840 | { .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64, | |
7841 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3, | |
7842 | .type = ARM_CP_NOP, .access = PL0_W, | |
dd345653 | 7843 | .fgt = FGT_DCCIVAC, |
5463df16 RH |
7844 | .accessfn = aa64_cacheop_poc_access }, |
7845 | { .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64, | |
7846 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, | |
7847 | .type = ARM_CP_NOP, .access = PL0_W, | |
dd345653 | 7848 | .fgt = FGT_DCCIVAC, |
5463df16 | 7849 | .accessfn = aa64_cacheop_poc_access }, |
eb821168 RH |
7850 | { .name = "DC_GVA", .state = ARM_CP_STATE_AA64, |
7851 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3, | |
7852 | .access = PL0_W, .type = ARM_CP_DC_GVA, | |
7853 | #ifndef CONFIG_USER_ONLY | |
7854 | /* Avoid overhead of an access check that always passes in user-mode */ | |
7855 | .accessfn = aa64_zva_access, | |
dd345653 | 7856 | .fgt = FGT_DCZVA, |
eb821168 RH |
7857 | #endif |
7858 | }, | |
7859 | { .name = "DC_GZVA", .state = ARM_CP_STATE_AA64, | |
7860 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 4, | |
7861 | .access = PL0_W, .type = ARM_CP_DC_GZVA, | |
7862 | #ifndef CONFIG_USER_ONLY | |
7863 | /* Avoid overhead of an access check that always passes in user-mode */ | |
7864 | .accessfn = aa64_zva_access, | |
dd345653 | 7865 | .fgt = FGT_DCZVA, |
eb821168 RH |
7866 | #endif |
7867 | }, | |
5463df16 RH |
7868 | }; |
7869 | ||
7cb1e618 RH |
7870 | static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri, |
7871 | bool isread) | |
7872 | { | |
7873 | uint64_t hcr = arm_hcr_el2_eff(env); | |
7874 | int el = arm_current_el(env); | |
7875 | ||
7876 | if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) { | |
7877 | if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { | |
7878 | if (hcr & HCR_TGE) { | |
7879 | return CP_ACCESS_TRAP_EL2; | |
7880 | } | |
7881 | return CP_ACCESS_TRAP; | |
7882 | } | |
7883 | } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { | |
7884 | return CP_ACCESS_TRAP_EL2; | |
7885 | } | |
7886 | if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) { | |
7887 | return CP_ACCESS_TRAP_EL2; | |
7888 | } | |
7889 | if (el < 3 | |
7890 | && arm_feature(env, ARM_FEATURE_EL3) | |
7891 | && !(env->cp15.scr_el3 & SCR_ENSCXT)) { | |
7892 | return CP_ACCESS_TRAP_EL3; | |
7893 | } | |
7894 | return CP_ACCESS_OK; | |
7895 | } | |
7896 | ||
7897 | static const ARMCPRegInfo scxtnum_reginfo[] = { | |
7898 | { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64, | |
7899 | .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7, | |
7900 | .access = PL0_RW, .accessfn = access_scxtnum, | |
67dd8030 | 7901 | .fgt = FGT_SCXTNUM_EL0, |
7cb1e618 RH |
7902 | .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) }, |
7903 | { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64, | |
7904 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7, | |
7905 | .access = PL1_RW, .accessfn = access_scxtnum, | |
67dd8030 | 7906 | .fgt = FGT_SCXTNUM_EL1, |
7cb1e618 RH |
7907 | .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) }, |
7908 | { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64, | |
7909 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7, | |
7910 | .access = PL2_RW, .accessfn = access_scxtnum, | |
7911 | .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) }, | |
7912 | { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64, | |
7913 | .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7, | |
7914 | .access = PL3_RW, | |
7915 | .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) }, | |
7916 | }; | |
15126d9c PM |
7917 | |
7918 | static CPAccessResult access_fgt(CPUARMState *env, const ARMCPRegInfo *ri, | |
7919 | bool isread) | |
7920 | { | |
7921 | if (arm_current_el(env) == 2 && | |
7922 | arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_FGTEN)) { | |
7923 | return CP_ACCESS_TRAP_EL3; | |
7924 | } | |
7925 | return CP_ACCESS_OK; | |
7926 | } | |
7927 | ||
7928 | static const ARMCPRegInfo fgt_reginfo[] = { | |
7929 | { .name = "HFGRTR_EL2", .state = ARM_CP_STATE_AA64, | |
7930 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, | |
7931 | .access = PL2_RW, .accessfn = access_fgt, | |
7932 | .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HFGRTR]) }, | |
7933 | { .name = "HFGWTR_EL2", .state = ARM_CP_STATE_AA64, | |
7934 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 5, | |
7935 | .access = PL2_RW, .accessfn = access_fgt, | |
7936 | .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HFGWTR]) }, | |
7937 | { .name = "HDFGRTR_EL2", .state = ARM_CP_STATE_AA64, | |
7938 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 4, | |
7939 | .access = PL2_RW, .accessfn = access_fgt, | |
7940 | .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HDFGRTR]) }, | |
7941 | { .name = "HDFGWTR_EL2", .state = ARM_CP_STATE_AA64, | |
7942 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 5, | |
7943 | .access = PL2_RW, .accessfn = access_fgt, | |
7944 | .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HDFGWTR]) }, | |
7945 | { .name = "HFGITR_EL2", .state = ARM_CP_STATE_AA64, | |
7946 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 6, | |
7947 | .access = PL2_RW, .accessfn = access_fgt, | |
7948 | .fieldoffset = offsetof(CPUARMState, cp15.fgt_exec[FGTREG_HFGITR]) }, | |
7949 | }; | |
7cb1e618 | 7950 | #endif /* TARGET_AARCH64 */ |
967aa94f | 7951 | |
cb570bd3 RH |
7952 | static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, |
7953 | bool isread) | |
7954 | { | |
7955 | int el = arm_current_el(env); | |
7956 | ||
7957 | if (el == 0) { | |
7958 | uint64_t sctlr = arm_sctlr(env, el); | |
7959 | if (!(sctlr & SCTLR_EnRCTX)) { | |
7960 | return CP_ACCESS_TRAP; | |
7961 | } | |
7962 | } else if (el == 1) { | |
7963 | uint64_t hcr = arm_hcr_el2_eff(env); | |
7964 | if (hcr & HCR_NV) { | |
7965 | return CP_ACCESS_TRAP_EL2; | |
7966 | } | |
7967 | } | |
7968 | return CP_ACCESS_OK; | |
7969 | } | |
7970 | ||
7971 | static const ARMCPRegInfo predinv_reginfo[] = { | |
7972 | { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64, | |
7973 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4, | |
950037e2 | 7974 | .fgt = FGT_CFPRCTX, |
cb570bd3 RH |
7975 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, |
7976 | { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64, | |
7977 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5, | |
950037e2 | 7978 | .fgt = FGT_DVPRCTX, |
cb570bd3 RH |
7979 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, |
7980 | { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64, | |
7981 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7, | |
950037e2 | 7982 | .fgt = FGT_CPPRCTX, |
cb570bd3 RH |
7983 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, |
7984 | /* | |
7985 | * Note the AArch32 opcodes have a different OPC1. | |
7986 | */ | |
7987 | { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32, | |
7988 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4, | |
950037e2 | 7989 | .fgt = FGT_CFPRCTX, |
cb570bd3 RH |
7990 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, |
7991 | { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32, | |
7992 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5, | |
950037e2 | 7993 | .fgt = FGT_DVPRCTX, |
cb570bd3 RH |
7994 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, |
7995 | { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32, | |
7996 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7, | |
950037e2 | 7997 | .fgt = FGT_CPPRCTX, |
cb570bd3 | 7998 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, |
cb570bd3 RH |
7999 | }; |
8000 | ||
957e6155 PM |
8001 | static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri) |
8002 | { | |
8003 | /* Read the high 32 bits of the current CCSIDR */ | |
8004 | return extract64(ccsidr_read(env, ri), 32, 32); | |
8005 | } | |
8006 | ||
8007 | static const ARMCPRegInfo ccsidr2_reginfo[] = { | |
8008 | { .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH, | |
8009 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2, | |
8010 | .access = PL1_R, | |
e2ce5fcd | 8011 | .accessfn = access_tid4, |
957e6155 | 8012 | .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW }, |
957e6155 PM |
8013 | }; |
8014 | ||
6a4ef4e5 MZ |
8015 | static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri, |
8016 | bool isread) | |
8017 | { | |
8018 | if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) { | |
8019 | return CP_ACCESS_TRAP_EL2; | |
8020 | } | |
8021 | ||
8022 | return CP_ACCESS_OK; | |
8023 | } | |
8024 | ||
8025 | static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri, | |
8026 | bool isread) | |
8027 | { | |
8028 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
8029 | return access_aa64_tid3(env, ri, isread); | |
8030 | } | |
8031 | ||
8032 | return CP_ACCESS_OK; | |
8033 | } | |
8034 | ||
f96f3d5f MZ |
8035 | static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri, |
8036 | bool isread) | |
8037 | { | |
8038 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID0)) { | |
8039 | return CP_ACCESS_TRAP_EL2; | |
8040 | } | |
8041 | ||
8042 | return CP_ACCESS_OK; | |
8043 | } | |
8044 | ||
8e228c9e PM |
8045 | static CPAccessResult access_joscr_jmcr(CPUARMState *env, |
8046 | const ARMCPRegInfo *ri, bool isread) | |
8047 | { | |
8048 | /* | |
8049 | * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only | |
8050 | * in v7A, not in v8A. | |
8051 | */ | |
8052 | if (!arm_feature(env, ARM_FEATURE_V8) && | |
8053 | arm_current_el(env) < 2 && !arm_is_secure_below_el3(env) && | |
8054 | (env->cp15.hstr_el2 & HSTR_TJDBX)) { | |
8055 | return CP_ACCESS_TRAP_EL2; | |
8056 | } | |
8057 | return CP_ACCESS_OK; | |
8058 | } | |
8059 | ||
f96f3d5f MZ |
8060 | static const ARMCPRegInfo jazelle_regs[] = { |
8061 | { .name = "JIDR", | |
8062 | .cp = 14, .crn = 0, .crm = 0, .opc1 = 7, .opc2 = 0, | |
8063 | .access = PL1_R, .accessfn = access_jazelle, | |
8064 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8065 | { .name = "JOSCR", | |
8066 | .cp = 14, .crn = 1, .crm = 0, .opc1 = 7, .opc2 = 0, | |
8e228c9e | 8067 | .accessfn = access_joscr_jmcr, |
f96f3d5f MZ |
8068 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
8069 | { .name = "JMCR", | |
8070 | .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0, | |
8e228c9e | 8071 | .accessfn = access_joscr_jmcr, |
f96f3d5f | 8072 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f96f3d5f MZ |
8073 | }; |
8074 | ||
52d18727 RH |
8075 | static const ARMCPRegInfo contextidr_el2 = { |
8076 | .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, | |
8077 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, | |
8078 | .access = PL2_RW, | |
8079 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) | |
8080 | }; | |
8081 | ||
e2a1a461 | 8082 | static const ARMCPRegInfo vhe_reginfo[] = { |
ed30da8e RH |
8083 | { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, |
8084 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, | |
8085 | .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, | |
587f8b33 | 8086 | .raw_writefn = raw_write, |
ed30da8e | 8087 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) }, |
8c94b071 RH |
8088 | #ifndef CONFIG_USER_ONLY |
8089 | { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64, | |
8090 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 2, | |
8091 | .fieldoffset = | |
8092 | offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval), | |
8093 | .type = ARM_CP_IO, .access = PL2_RW, | |
8094 | .writefn = gt_hv_cval_write, .raw_writefn = raw_write }, | |
8095 | { .name = "CNTHV_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
8096 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 0, | |
8097 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, | |
8098 | .resetfn = gt_hv_timer_reset, | |
8099 | .readfn = gt_hv_tval_read, .writefn = gt_hv_tval_write }, | |
8100 | { .name = "CNTHV_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
8101 | .type = ARM_CP_IO, | |
8102 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 1, | |
8103 | .access = PL2_RW, | |
8104 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].ctl), | |
8105 | .writefn = gt_hv_ctl_write, .raw_writefn = raw_write }, | |
bb5972e4 RH |
8106 | { .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64, |
8107 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1, | |
8108 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
8109 | .access = PL2_RW, .accessfn = e2h_access, | |
8110 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), | |
8111 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write }, | |
8112 | { .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64, | |
8113 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1, | |
8114 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
8115 | .access = PL2_RW, .accessfn = e2h_access, | |
8116 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), | |
8117 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write }, | |
8118 | { .name = "CNTP_TVAL_EL02", .state = ARM_CP_STATE_AA64, | |
8119 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 0, | |
8120 | .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, | |
8121 | .access = PL2_RW, .accessfn = e2h_access, | |
8122 | .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write }, | |
8123 | { .name = "CNTV_TVAL_EL02", .state = ARM_CP_STATE_AA64, | |
8124 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 0, | |
8125 | .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, | |
8126 | .access = PL2_RW, .accessfn = e2h_access, | |
8127 | .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write }, | |
8128 | { .name = "CNTP_CVAL_EL02", .state = ARM_CP_STATE_AA64, | |
8129 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 2, | |
8130 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
8131 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
8132 | .access = PL2_RW, .accessfn = e2h_access, | |
8133 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write }, | |
8134 | { .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64, | |
8135 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2, | |
8136 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
8137 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
8138 | .access = PL2_RW, .accessfn = e2h_access, | |
8139 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write }, | |
8c94b071 | 8140 | #endif |
e2a1a461 RH |
8141 | }; |
8142 | ||
04b07d29 RH |
8143 | #ifndef CONFIG_USER_ONLY |
8144 | static const ARMCPRegInfo ats1e1_reginfo[] = { | |
3999d2d2 | 8145 | { .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64, |
04b07d29 RH |
8146 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, |
8147 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
132c98cd | 8148 | .fgt = FGT_ATS1E1RP, |
1acd00ef | 8149 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
3999d2d2 | 8150 | { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64, |
04b07d29 RH |
8151 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, |
8152 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
132c98cd | 8153 | .fgt = FGT_ATS1E1WP, |
1acd00ef | 8154 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
04b07d29 RH |
8155 | }; |
8156 | ||
8157 | static const ARMCPRegInfo ats1cp_reginfo[] = { | |
8158 | { .name = "ATS1CPRP", | |
8159 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, | |
8160 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
8161 | .writefn = ats_write }, | |
8162 | { .name = "ATS1CPWP", | |
8163 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, | |
8164 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
8165 | .writefn = ats_write }, | |
04b07d29 RH |
8166 | }; |
8167 | #endif | |
8168 | ||
f6287c24 PM |
8169 | /* |
8170 | * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and | |
8171 | * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field | |
8172 | * is non-zero, which is never for ARMv7, optionally in ARMv8 | |
8173 | * and mandatorily for ARMv8.2 and up. | |
8174 | * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's | |
8175 | * implementation is RAZ/WI we can ignore this detail, as we | |
8176 | * do for ACTLR. | |
8177 | */ | |
8178 | static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = { | |
8179 | { .name = "ACTLR2", .state = ARM_CP_STATE_AA32, | |
8180 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 3, | |
99602377 RH |
8181 | .access = PL1_RW, .accessfn = access_tacr, |
8182 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
f6287c24 PM |
8183 | { .name = "HACTLR2", .state = ARM_CP_STATE_AA32, |
8184 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3, | |
8185 | .access = PL2_RW, .type = ARM_CP_CONST, | |
8186 | .resetvalue = 0 }, | |
f6287c24 PM |
8187 | }; |
8188 | ||
2ceb98c0 PM |
8189 | void register_cp_regs_for_features(ARMCPU *cpu) |
8190 | { | |
8191 | /* Register all the coprocessor registers based on feature bits */ | |
8192 | CPUARMState *env = &cpu->env; | |
8193 | if (arm_feature(env, ARM_FEATURE_M)) { | |
8194 | /* M profile has no coprocessor registers */ | |
8195 | return; | |
8196 | } | |
8197 | ||
e9aa6c21 | 8198 | define_arm_cp_regs(cpu, cp_reginfo); |
9449fdf6 | 8199 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
9b37a28c FR |
8200 | /* |
8201 | * Must go early as it is full of wildcards that may be | |
9449fdf6 PM |
8202 | * overridden by later definitions. |
8203 | */ | |
8204 | define_arm_cp_regs(cpu, not_v8_cp_reginfo); | |
8205 | } | |
8206 | ||
7d57f408 | 8207 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8515a092 PM |
8208 | /* The ID registers all have impdef reset values */ |
8209 | ARMCPRegInfo v6_idregs[] = { | |
0ff644a7 PM |
8210 | { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, |
8211 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
8212 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8213 | .accessfn = access_aa32_tid3, |
8a130a7b | 8214 | .resetvalue = cpu->isar.id_pfr0 }, |
9b37a28c FR |
8215 | /* |
8216 | * ID_PFR1 is not a plain ARM_CP_CONST because we don't know | |
96a8b92e PM |
8217 | * the value of the GIC field until after we define these regs. |
8218 | */ | |
0ff644a7 PM |
8219 | { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, |
8220 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | |
96a8b92e | 8221 | .access = PL1_R, .type = ARM_CP_NO_RAW, |
6a4ef4e5 | 8222 | .accessfn = access_aa32_tid3, |
0f150c84 PMD |
8223 | #ifdef CONFIG_USER_ONLY |
8224 | .type = ARM_CP_CONST, | |
8225 | .resetvalue = cpu->isar.id_pfr1, | |
8226 | #else | |
8227 | .type = ARM_CP_NO_RAW, | |
8228 | .accessfn = access_aa32_tid3, | |
96a8b92e | 8229 | .readfn = id_pfr1_read, |
0f150c84 PMD |
8230 | .writefn = arm_cp_write_ignore |
8231 | #endif | |
8232 | }, | |
0ff644a7 PM |
8233 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, |
8234 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | |
8235 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8236 | .accessfn = access_aa32_tid3, |
a6179538 | 8237 | .resetvalue = cpu->isar.id_dfr0 }, |
0ff644a7 PM |
8238 | { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, |
8239 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, | |
8240 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8241 | .accessfn = access_aa32_tid3, |
8515a092 | 8242 | .resetvalue = cpu->id_afr0 }, |
0ff644a7 PM |
8243 | { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, |
8244 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, | |
8245 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8246 | .accessfn = access_aa32_tid3, |
10054016 | 8247 | .resetvalue = cpu->isar.id_mmfr0 }, |
0ff644a7 PM |
8248 | { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, |
8249 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, | |
8250 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8251 | .accessfn = access_aa32_tid3, |
10054016 | 8252 | .resetvalue = cpu->isar.id_mmfr1 }, |
0ff644a7 PM |
8253 | { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, |
8254 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, | |
8255 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8256 | .accessfn = access_aa32_tid3, |
10054016 | 8257 | .resetvalue = cpu->isar.id_mmfr2 }, |
0ff644a7 PM |
8258 | { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, |
8259 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, | |
8260 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8261 | .accessfn = access_aa32_tid3, |
10054016 | 8262 | .resetvalue = cpu->isar.id_mmfr3 }, |
0ff644a7 PM |
8263 | { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, |
8264 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
8265 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8266 | .accessfn = access_aa32_tid3, |
47576b94 | 8267 | .resetvalue = cpu->isar.id_isar0 }, |
0ff644a7 PM |
8268 | { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, |
8269 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, | |
8270 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8271 | .accessfn = access_aa32_tid3, |
47576b94 | 8272 | .resetvalue = cpu->isar.id_isar1 }, |
0ff644a7 PM |
8273 | { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, |
8274 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
8275 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8276 | .accessfn = access_aa32_tid3, |
47576b94 | 8277 | .resetvalue = cpu->isar.id_isar2 }, |
0ff644a7 PM |
8278 | { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, |
8279 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, | |
8280 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8281 | .accessfn = access_aa32_tid3, |
47576b94 | 8282 | .resetvalue = cpu->isar.id_isar3 }, |
0ff644a7 PM |
8283 | { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, |
8284 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, | |
8285 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8286 | .accessfn = access_aa32_tid3, |
47576b94 | 8287 | .resetvalue = cpu->isar.id_isar4 }, |
0ff644a7 PM |
8288 | { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, |
8289 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, | |
8290 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8291 | .accessfn = access_aa32_tid3, |
47576b94 | 8292 | .resetvalue = cpu->isar.id_isar5 }, |
e20d84c1 PM |
8293 | { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, |
8294 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, | |
8295 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8296 | .accessfn = access_aa32_tid3, |
10054016 | 8297 | .resetvalue = cpu->isar.id_mmfr4 }, |
802abf40 | 8298 | { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
8299 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, |
8300 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8301 | .accessfn = access_aa32_tid3, |
47576b94 | 8302 | .resetvalue = cpu->isar.id_isar6 }, |
8515a092 PM |
8303 | }; |
8304 | define_arm_cp_regs(cpu, v6_idregs); | |
7d57f408 PM |
8305 | define_arm_cp_regs(cpu, v6_cp_reginfo); |
8306 | } else { | |
8307 | define_arm_cp_regs(cpu, not_v6_cp_reginfo); | |
8308 | } | |
4d31c596 PM |
8309 | if (arm_feature(env, ARM_FEATURE_V6K)) { |
8310 | define_arm_cp_regs(cpu, v6k_cp_reginfo); | |
8311 | } | |
5e5cf9e3 | 8312 | if (arm_feature(env, ARM_FEATURE_V7MP) && |
452a0955 | 8313 | !arm_feature(env, ARM_FEATURE_PMSA)) { |
995939a6 PM |
8314 | define_arm_cp_regs(cpu, v7mp_cp_reginfo); |
8315 | } | |
327dd510 AL |
8316 | if (arm_feature(env, ARM_FEATURE_V7VE)) { |
8317 | define_arm_cp_regs(cpu, pmovsset_cp_reginfo); | |
8318 | } | |
e9aa6c21 | 8319 | if (arm_feature(env, ARM_FEATURE_V7)) { |
776d4e5c | 8320 | ARMCPRegInfo clidr = { |
7da845b0 PM |
8321 | .name = "CLIDR", .state = ARM_CP_STATE_BOTH, |
8322 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | |
630fcd4d | 8323 | .access = PL1_R, .type = ARM_CP_CONST, |
e2ce5fcd | 8324 | .accessfn = access_tid4, |
158c276c | 8325 | .fgt = FGT_CLIDR_EL1, |
630fcd4d | 8326 | .resetvalue = cpu->clidr |
776d4e5c | 8327 | }; |
776d4e5c | 8328 | define_one_arm_cp_reg(cpu, &clidr); |
e9aa6c21 | 8329 | define_arm_cp_regs(cpu, v7_cp_reginfo); |
50300698 | 8330 | define_debug_regs(cpu); |
24183fb6 | 8331 | define_pmu_regs(cpu); |
7d57f408 PM |
8332 | } else { |
8333 | define_arm_cp_regs(cpu, not_v7_cp_reginfo); | |
e9aa6c21 | 8334 | } |
b0d2b7d0 | 8335 | if (arm_feature(env, ARM_FEATURE_V8)) { |
dde4d028 PM |
8336 | /* |
8337 | * v8 ID registers, which all have impdef reset values. | |
e20d84c1 PM |
8338 | * Note that within the ID register ranges the unused slots |
8339 | * must all RAZ, not UNDEF; future architecture versions may | |
8340 | * define new registers here. | |
dde4d028 PM |
8341 | * ID registers which are AArch64 views of the AArch32 ID registers |
8342 | * which already existed in v6 and v7 are handled elsewhere, | |
8343 | * in v6_idregs[]. | |
e20d84c1 | 8344 | */ |
dde4d028 | 8345 | int i; |
e60cef86 | 8346 | ARMCPRegInfo v8_idregs[] = { |
976b99b6 AB |
8347 | /* |
8348 | * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system | |
8349 | * emulation because we don't know the right value for the | |
8350 | * GIC field until after we define these regs. | |
96a8b92e | 8351 | */ |
e60cef86 PM |
8352 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, |
8353 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | |
976b99b6 AB |
8354 | .access = PL1_R, |
8355 | #ifdef CONFIG_USER_ONLY | |
8356 | .type = ARM_CP_CONST, | |
8357 | .resetvalue = cpu->isar.id_aa64pfr0 | |
8358 | #else | |
8359 | .type = ARM_CP_NO_RAW, | |
6a4ef4e5 | 8360 | .accessfn = access_aa64_tid3, |
96a8b92e | 8361 | .readfn = id_aa64pfr0_read, |
976b99b6 AB |
8362 | .writefn = arm_cp_write_ignore |
8363 | #endif | |
8364 | }, | |
e60cef86 PM |
8365 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, |
8366 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | |
8367 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8368 | .accessfn = access_aa64_tid3, |
47576b94 | 8369 | .resetvalue = cpu->isar.id_aa64pfr1}, |
e20d84c1 PM |
8370 | { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
8371 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, | |
8372 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8373 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8374 | .resetvalue = 0 }, |
8375 | { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8376 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, | |
8377 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8378 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8379 | .resetvalue = 0 }, |
9516d772 | 8380 | { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
8381 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, |
8382 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8383 | .accessfn = access_aa64_tid3, |
2dc10fa2 | 8384 | .resetvalue = cpu->isar.id_aa64zfr0 }, |
414c54d5 | 8385 | { .name = "ID_AA64SMFR0_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
8386 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, |
8387 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8388 | .accessfn = access_aa64_tid3, |
414c54d5 | 8389 | .resetvalue = cpu->isar.id_aa64smfr0 }, |
e20d84c1 PM |
8390 | { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
8391 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, | |
8392 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8393 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8394 | .resetvalue = 0 }, |
8395 | { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8396 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, | |
8397 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8398 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8399 | .resetvalue = 0 }, |
e60cef86 PM |
8400 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, |
8401 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | |
8402 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8403 | .accessfn = access_aa64_tid3, |
2a609df8 | 8404 | .resetvalue = cpu->isar.id_aa64dfr0 }, |
e60cef86 PM |
8405 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, |
8406 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | |
8407 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8408 | .accessfn = access_aa64_tid3, |
2a609df8 | 8409 | .resetvalue = cpu->isar.id_aa64dfr1 }, |
e20d84c1 PM |
8410 | { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
8411 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, | |
8412 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8413 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8414 | .resetvalue = 0 }, |
8415 | { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8416 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, | |
8417 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8418 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8419 | .resetvalue = 0 }, |
e60cef86 PM |
8420 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, |
8421 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | |
8422 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8423 | .accessfn = access_aa64_tid3, |
e60cef86 PM |
8424 | .resetvalue = cpu->id_aa64afr0 }, |
8425 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | |
8426 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | |
8427 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8428 | .accessfn = access_aa64_tid3, |
e60cef86 | 8429 | .resetvalue = cpu->id_aa64afr1 }, |
e20d84c1 PM |
8430 | { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
8431 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, | |
8432 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8433 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8434 | .resetvalue = 0 }, |
8435 | { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8436 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, | |
8437 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8438 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8439 | .resetvalue = 0 }, |
e60cef86 PM |
8440 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, |
8441 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | |
8442 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8443 | .accessfn = access_aa64_tid3, |
47576b94 | 8444 | .resetvalue = cpu->isar.id_aa64isar0 }, |
e60cef86 PM |
8445 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, |
8446 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | |
8447 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8448 | .accessfn = access_aa64_tid3, |
47576b94 | 8449 | .resetvalue = cpu->isar.id_aa64isar1 }, |
a969fe97 | 8450 | { .name = "ID_AA64ISAR2_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
8451 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, |
8452 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8453 | .accessfn = access_aa64_tid3, |
a969fe97 | 8454 | .resetvalue = cpu->isar.id_aa64isar2 }, |
e20d84c1 PM |
8455 | { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
8456 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, | |
8457 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8458 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8459 | .resetvalue = 0 }, |
8460 | { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8461 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, | |
8462 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8463 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8464 | .resetvalue = 0 }, |
8465 | { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8466 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, | |
8467 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8468 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8469 | .resetvalue = 0 }, |
8470 | { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8471 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, | |
8472 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8473 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8474 | .resetvalue = 0 }, |
8475 | { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8476 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, | |
8477 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8478 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8479 | .resetvalue = 0 }, |
e60cef86 PM |
8480 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, |
8481 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
8482 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8483 | .accessfn = access_aa64_tid3, |
3dc91ddb | 8484 | .resetvalue = cpu->isar.id_aa64mmfr0 }, |
e60cef86 PM |
8485 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, |
8486 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | |
8487 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8488 | .accessfn = access_aa64_tid3, |
3dc91ddb | 8489 | .resetvalue = cpu->isar.id_aa64mmfr1 }, |
64761e10 | 8490 | { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
8491 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, |
8492 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8493 | .accessfn = access_aa64_tid3, |
64761e10 | 8494 | .resetvalue = cpu->isar.id_aa64mmfr2 }, |
e20d84c1 PM |
8495 | { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
8496 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, | |
8497 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8498 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8499 | .resetvalue = 0 }, |
8500 | { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8501 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, | |
8502 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8503 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8504 | .resetvalue = 0 }, |
8505 | { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8506 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, | |
8507 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8508 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8509 | .resetvalue = 0 }, |
8510 | { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8511 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, | |
8512 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8513 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8514 | .resetvalue = 0 }, |
8515 | { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8516 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, | |
8517 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8518 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8519 | .resetvalue = 0 }, |
a50c0f51 PM |
8520 | { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, |
8521 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
8522 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8523 | .accessfn = access_aa64_tid3, |
47576b94 | 8524 | .resetvalue = cpu->isar.mvfr0 }, |
a50c0f51 PM |
8525 | { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, |
8526 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
8527 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8528 | .accessfn = access_aa64_tid3, |
47576b94 | 8529 | .resetvalue = cpu->isar.mvfr1 }, |
a50c0f51 PM |
8530 | { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, |
8531 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
8532 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8533 | .accessfn = access_aa64_tid3, |
47576b94 | 8534 | .resetvalue = cpu->isar.mvfr2 }, |
dde4d028 PM |
8535 | /* |
8536 | * "0, c0, c3, {0,1,2}" are the encodings corresponding to | |
8537 | * AArch64 MVFR[012]_EL1. Define the STATE_AA32 encoding | |
8538 | * as RAZ, since it is in the "reserved for future ID | |
8539 | * registers, RAZ" part of the AArch32 encoding space. | |
8540 | */ | |
8541 | { .name = "RES_0_C0_C3_0", .state = ARM_CP_STATE_AA32, | |
8542 | .cp = 15, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
8543 | .access = PL1_R, .type = ARM_CP_CONST, | |
8544 | .accessfn = access_aa64_tid3, | |
8545 | .resetvalue = 0 }, | |
8546 | { .name = "RES_0_C0_C3_1", .state = ARM_CP_STATE_AA32, | |
8547 | .cp = 15, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
8548 | .access = PL1_R, .type = ARM_CP_CONST, | |
8549 | .accessfn = access_aa64_tid3, | |
8550 | .resetvalue = 0 }, | |
8551 | { .name = "RES_0_C0_C3_2", .state = ARM_CP_STATE_AA32, | |
8552 | .cp = 15, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
8553 | .access = PL1_R, .type = ARM_CP_CONST, | |
8554 | .accessfn = access_aa64_tid3, | |
8555 | .resetvalue = 0 }, | |
8556 | /* | |
8557 | * Other encodings in "0, c0, c3, ..." are STATE_BOTH because | |
8558 | * they're also RAZ for AArch64, and in v8 are gradually | |
8559 | * being filled with AArch64-view-of-AArch32-ID-register | |
8560 | * for new ID registers. | |
8561 | */ | |
8562 | { .name = "RES_0_C0_C3_3", .state = ARM_CP_STATE_BOTH, | |
e20d84c1 PM |
8563 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, |
8564 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8565 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8566 | .resetvalue = 0 }, |
1d51bc96 | 8567 | { .name = "ID_PFR2", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
8568 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, |
8569 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8570 | .accessfn = access_aa64_tid3, |
1d51bc96 | 8571 | .resetvalue = cpu->isar.id_pfr2 }, |
d22c5649 | 8572 | { .name = "ID_DFR1", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
8573 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, |
8574 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8575 | .accessfn = access_aa64_tid3, |
d22c5649 | 8576 | .resetvalue = cpu->isar.id_dfr1 }, |
32957aad | 8577 | { .name = "ID_MMFR5", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
8578 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, |
8579 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8580 | .accessfn = access_aa64_tid3, |
32957aad | 8581 | .resetvalue = cpu->isar.id_mmfr5 }, |
dde4d028 | 8582 | { .name = "RES_0_C0_C3_7", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
8583 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, |
8584 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8585 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8586 | .resetvalue = 0 }, |
4054bfa9 AF |
8587 | { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, |
8588 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, | |
8589 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 8590 | .fgt = FGT_PMCEIDN_EL0, |
cad86737 | 8591 | .resetvalue = extract64(cpu->pmceid0, 0, 32) }, |
4054bfa9 AF |
8592 | { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, |
8593 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, | |
8594 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 8595 | .fgt = FGT_PMCEIDN_EL0, |
4054bfa9 AF |
8596 | .resetvalue = cpu->pmceid0 }, |
8597 | { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, | |
8598 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, | |
8599 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 8600 | .fgt = FGT_PMCEIDN_EL0, |
cad86737 | 8601 | .resetvalue = extract64(cpu->pmceid1, 0, 32) }, |
4054bfa9 AF |
8602 | { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, |
8603 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, | |
8604 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 8605 | .fgt = FGT_PMCEIDN_EL0, |
4054bfa9 | 8606 | .resetvalue = cpu->pmceid1 }, |
e60cef86 | 8607 | }; |
6c5c0fec | 8608 | #ifdef CONFIG_USER_ONLY |
10b0220e | 8609 | static const ARMCPRegUserSpaceInfo v8_user_idregs[] = { |
6c5c0fec | 8610 | { .name = "ID_AA64PFR0_EL1", |
bc6bd20e ZS |
8611 | .exported_bits = R_ID_AA64PFR0_FP_MASK | |
8612 | R_ID_AA64PFR0_ADVSIMD_MASK | | |
8613 | R_ID_AA64PFR0_SVE_MASK | | |
8614 | R_ID_AA64PFR0_DIT_MASK, | |
8615 | .fixed_bits = (0x1u << R_ID_AA64PFR0_EL0_SHIFT) | | |
8616 | (0x1u << R_ID_AA64PFR0_EL1_SHIFT) }, | |
6c5c0fec | 8617 | { .name = "ID_AA64PFR1_EL1", |
bc6bd20e ZS |
8618 | .exported_bits = R_ID_AA64PFR1_BT_MASK | |
8619 | R_ID_AA64PFR1_SSBS_MASK | | |
8620 | R_ID_AA64PFR1_MTE_MASK | | |
8621 | R_ID_AA64PFR1_SME_MASK }, | |
d040242e | 8622 | { .name = "ID_AA64PFR*_EL1_RESERVED", |
bc6bd20e ZS |
8623 | .is_glob = true }, |
8624 | { .name = "ID_AA64ZFR0_EL1", | |
8625 | .exported_bits = R_ID_AA64ZFR0_SVEVER_MASK | | |
8626 | R_ID_AA64ZFR0_AES_MASK | | |
8627 | R_ID_AA64ZFR0_BITPERM_MASK | | |
8628 | R_ID_AA64ZFR0_BFLOAT16_MASK | | |
8629 | R_ID_AA64ZFR0_SHA3_MASK | | |
8630 | R_ID_AA64ZFR0_SM4_MASK | | |
8631 | R_ID_AA64ZFR0_I8MM_MASK | | |
8632 | R_ID_AA64ZFR0_F32MM_MASK | | |
8633 | R_ID_AA64ZFR0_F64MM_MASK }, | |
8634 | { .name = "ID_AA64SMFR0_EL1", | |
8635 | .exported_bits = R_ID_AA64SMFR0_F32F32_MASK | | |
5f7b71fb | 8636 | R_ID_AA64SMFR0_BI32I32_MASK | |
bc6bd20e ZS |
8637 | R_ID_AA64SMFR0_B16F32_MASK | |
8638 | R_ID_AA64SMFR0_F16F32_MASK | | |
8639 | R_ID_AA64SMFR0_I8I32_MASK | | |
5f7b71fb PM |
8640 | R_ID_AA64SMFR0_F16F16_MASK | |
8641 | R_ID_AA64SMFR0_B16B16_MASK | | |
8642 | R_ID_AA64SMFR0_I16I32_MASK | | |
bc6bd20e ZS |
8643 | R_ID_AA64SMFR0_F64F64_MASK | |
8644 | R_ID_AA64SMFR0_I16I64_MASK | | |
5f7b71fb | 8645 | R_ID_AA64SMFR0_SMEVER_MASK | |
bc6bd20e | 8646 | R_ID_AA64SMFR0_FA64_MASK }, |
6c5c0fec | 8647 | { .name = "ID_AA64MMFR0_EL1", |
bc6bd20e ZS |
8648 | .exported_bits = R_ID_AA64MMFR0_ECV_MASK, |
8649 | .fixed_bits = (0xfu << R_ID_AA64MMFR0_TGRAN64_SHIFT) | | |
8650 | (0xfu << R_ID_AA64MMFR0_TGRAN4_SHIFT) }, | |
8651 | { .name = "ID_AA64MMFR1_EL1", | |
8652 | .exported_bits = R_ID_AA64MMFR1_AFP_MASK }, | |
8653 | { .name = "ID_AA64MMFR2_EL1", | |
8654 | .exported_bits = R_ID_AA64MMFR2_AT_MASK }, | |
d040242e | 8655 | { .name = "ID_AA64MMFR*_EL1_RESERVED", |
bc6bd20e | 8656 | .is_glob = true }, |
6c5c0fec | 8657 | { .name = "ID_AA64DFR0_EL1", |
bc6bd20e ZS |
8658 | .fixed_bits = (0x6u << R_ID_AA64DFR0_DEBUGVER_SHIFT) }, |
8659 | { .name = "ID_AA64DFR1_EL1" }, | |
d040242e | 8660 | { .name = "ID_AA64DFR*_EL1_RESERVED", |
bc6bd20e | 8661 | .is_glob = true }, |
d040242e | 8662 | { .name = "ID_AA64AFR*", |
bc6bd20e | 8663 | .is_glob = true }, |
6c5c0fec | 8664 | { .name = "ID_AA64ISAR0_EL1", |
bc6bd20e ZS |
8665 | .exported_bits = R_ID_AA64ISAR0_AES_MASK | |
8666 | R_ID_AA64ISAR0_SHA1_MASK | | |
8667 | R_ID_AA64ISAR0_SHA2_MASK | | |
8668 | R_ID_AA64ISAR0_CRC32_MASK | | |
8669 | R_ID_AA64ISAR0_ATOMIC_MASK | | |
8670 | R_ID_AA64ISAR0_RDM_MASK | | |
8671 | R_ID_AA64ISAR0_SHA3_MASK | | |
8672 | R_ID_AA64ISAR0_SM3_MASK | | |
8673 | R_ID_AA64ISAR0_SM4_MASK | | |
8674 | R_ID_AA64ISAR0_DP_MASK | | |
8675 | R_ID_AA64ISAR0_FHM_MASK | | |
8676 | R_ID_AA64ISAR0_TS_MASK | | |
8677 | R_ID_AA64ISAR0_RNDR_MASK }, | |
6c5c0fec | 8678 | { .name = "ID_AA64ISAR1_EL1", |
bc6bd20e ZS |
8679 | .exported_bits = R_ID_AA64ISAR1_DPB_MASK | |
8680 | R_ID_AA64ISAR1_APA_MASK | | |
8681 | R_ID_AA64ISAR1_API_MASK | | |
8682 | R_ID_AA64ISAR1_JSCVT_MASK | | |
8683 | R_ID_AA64ISAR1_FCMA_MASK | | |
8684 | R_ID_AA64ISAR1_LRCPC_MASK | | |
8685 | R_ID_AA64ISAR1_GPA_MASK | | |
8686 | R_ID_AA64ISAR1_GPI_MASK | | |
8687 | R_ID_AA64ISAR1_FRINTTS_MASK | | |
8688 | R_ID_AA64ISAR1_SB_MASK | | |
8689 | R_ID_AA64ISAR1_BF16_MASK | | |
8690 | R_ID_AA64ISAR1_DGH_MASK | | |
8691 | R_ID_AA64ISAR1_I8MM_MASK }, | |
8692 | { .name = "ID_AA64ISAR2_EL1", | |
8693 | .exported_bits = R_ID_AA64ISAR2_WFXT_MASK | | |
8694 | R_ID_AA64ISAR2_RPRES_MASK | | |
8695 | R_ID_AA64ISAR2_GPA3_MASK | | |
5f7b71fb PM |
8696 | R_ID_AA64ISAR2_APA3_MASK | |
8697 | R_ID_AA64ISAR2_MOPS_MASK | | |
8698 | R_ID_AA64ISAR2_BC_MASK | | |
8699 | R_ID_AA64ISAR2_RPRFM_MASK | | |
8700 | R_ID_AA64ISAR2_CSSC_MASK }, | |
d040242e | 8701 | { .name = "ID_AA64ISAR*_EL1_RESERVED", |
bc6bd20e | 8702 | .is_glob = true }, |
6c5c0fec AB |
8703 | }; |
8704 | modify_arm_cp_regs(v8_idregs, v8_user_idregs); | |
8705 | #endif | |
97198a7d RH |
8706 | /* |
8707 | * RVBAR_EL1 and RMR_EL1 only implemented if EL1 is the highest EL. | |
8708 | * TODO: For RMR, a write with bit 1 set should do something with | |
8709 | * cpu_reset(). In the meantime, "the bit is strictly a request", | |
8710 | * so we are in spec just ignoring writes. | |
8711 | */ | |
be8e8128 GB |
8712 | if (!arm_feature(env, ARM_FEATURE_EL3) && |
8713 | !arm_feature(env, ARM_FEATURE_EL2)) { | |
97198a7d RH |
8714 | ARMCPRegInfo el1_reset_regs[] = { |
8715 | { .name = "RVBAR_EL1", .state = ARM_CP_STATE_BOTH, | |
8716 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, | |
8717 | .access = PL1_R, | |
8718 | .fieldoffset = offsetof(CPUARMState, cp15.rvbar) }, | |
8719 | { .name = "RMR_EL1", .state = ARM_CP_STATE_BOTH, | |
8720 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2, | |
8721 | .access = PL1_RW, .type = ARM_CP_CONST, | |
8722 | .resetvalue = arm_feature(env, ARM_FEATURE_AARCH64) } | |
be8e8128 | 8723 | }; |
97198a7d | 8724 | define_arm_cp_regs(cpu, el1_reset_regs); |
be8e8128 | 8725 | } |
e60cef86 | 8726 | define_arm_cp_regs(cpu, v8_idregs); |
b0d2b7d0 | 8727 | define_arm_cp_regs(cpu, v8_cp_reginfo); |
c36a0d57 PM |
8728 | if (cpu_isar_feature(aa64_aa32_el1, cpu)) { |
8729 | define_arm_cp_regs(cpu, v8_aa32_el1_reginfo); | |
8730 | } | |
dde4d028 PM |
8731 | |
8732 | for (i = 4; i < 16; i++) { | |
8733 | /* | |
8734 | * Encodings in "0, c0, {c4-c7}, {0-7}" are RAZ for AArch32. | |
8735 | * For pre-v8 cores there are RAZ patterns for these in | |
8736 | * id_pre_v8_midr_cp_reginfo[]; for v8 we do that here. | |
8737 | * v8 extends the "must RAZ" part of the ID register space | |
8738 | * to also cover c0, 0, c{8-15}, {0-7}. | |
8739 | * These are STATE_AA32 because in the AArch64 sysreg space | |
8740 | * c4-c7 is where the AArch64 ID registers live (and we've | |
8741 | * already defined those in v8_idregs[]), and c8-c15 are not | |
8742 | * "must RAZ" for AArch64. | |
8743 | */ | |
8744 | g_autofree char *name = g_strdup_printf("RES_0_C0_C%d_X", i); | |
8745 | ARMCPRegInfo v8_aa32_raz_idregs = { | |
8746 | .name = name, | |
8747 | .state = ARM_CP_STATE_AA32, | |
8748 | .cp = 15, .opc1 = 0, .crn = 0, .crm = i, .opc2 = CP_ANY, | |
8749 | .access = PL1_R, .type = ARM_CP_CONST, | |
8750 | .accessfn = access_aa64_tid3, | |
8751 | .resetvalue = 0 }; | |
8752 | define_one_arm_cp_reg(cpu, &v8_aa32_raz_idregs); | |
8753 | } | |
b0d2b7d0 | 8754 | } |
99a90811 RH |
8755 | |
8756 | /* | |
8757 | * Register the base EL2 cpregs. | |
8758 | * Pre v8, these registers are implemented only as part of the | |
8759 | * Virtualization Extensions (EL2 present). Beginning with v8, | |
8760 | * if EL2 is missing but EL3 is enabled, mostly these become | |
8761 | * RES0 from EL3, with some specific exceptions. | |
8762 | */ | |
8763 | if (arm_feature(env, ARM_FEATURE_EL2) | |
8764 | || (arm_feature(env, ARM_FEATURE_EL3) | |
8765 | && arm_feature(env, ARM_FEATURE_V8))) { | |
f0d574d6 | 8766 | uint64_t vmpidr_def = mpidr_read_val(env); |
731de9e6 EI |
8767 | ARMCPRegInfo vpidr_regs[] = { |
8768 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | |
8769 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
8770 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
696ba377 RH |
8771 | .resetvalue = cpu->midr, |
8772 | .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, | |
36476562 | 8773 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) }, |
731de9e6 EI |
8774 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, |
8775 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
8776 | .access = PL2_RW, .resetvalue = cpu->midr, | |
696ba377 | 8777 | .type = ARM_CP_EL3_NO_EL2_C_NZ, |
731de9e6 | 8778 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, |
f0d574d6 EI |
8779 | { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, |
8780 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
8781 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
696ba377 RH |
8782 | .resetvalue = vmpidr_def, |
8783 | .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, | |
36476562 | 8784 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) }, |
f0d574d6 EI |
8785 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, |
8786 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
696ba377 RH |
8787 | .access = PL2_RW, .resetvalue = vmpidr_def, |
8788 | .type = ARM_CP_EL3_NO_EL2_C_NZ, | |
f0d574d6 | 8789 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, |
731de9e6 | 8790 | }; |
24526bb9 PM |
8791 | /* |
8792 | * The only field of MDCR_EL2 that has a defined architectural reset | |
8793 | * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N. | |
8794 | */ | |
8795 | ARMCPRegInfo mdcr_el2 = { | |
7f4fbfb5 | 8796 | .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, .type = ARM_CP_IO, |
24526bb9 | 8797 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, |
01765386 | 8798 | .writefn = mdcr_el2_write, |
24526bb9 PM |
8799 | .access = PL2_RW, .resetvalue = pmu_num_counters(env), |
8800 | .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), | |
8801 | }; | |
8802 | define_one_arm_cp_reg(cpu, &mdcr_el2); | |
731de9e6 | 8803 | define_arm_cp_regs(cpu, vpidr_regs); |
4771cd01 | 8804 | define_arm_cp_regs(cpu, el2_cp_reginfo); |
ce4afed8 PM |
8805 | if (arm_feature(env, ARM_FEATURE_V8)) { |
8806 | define_arm_cp_regs(cpu, el2_v8_cp_reginfo); | |
8807 | } | |
e9152ee9 RDC |
8808 | if (cpu_isar_feature(aa64_sel2, cpu)) { |
8809 | define_arm_cp_regs(cpu, el2_sec_cp_reginfo); | |
8810 | } | |
97198a7d RH |
8811 | /* |
8812 | * RVBAR_EL2 and RMR_EL2 only implemented if EL2 is the highest EL. | |
8813 | * See commentary near RMR_EL1. | |
8814 | */ | |
be8e8128 | 8815 | if (!arm_feature(env, ARM_FEATURE_EL3)) { |
97198a7d RH |
8816 | static const ARMCPRegInfo el2_reset_regs[] = { |
8817 | { .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, | |
8818 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, | |
8819 | .access = PL2_R, | |
8820 | .fieldoffset = offsetof(CPUARMState, cp15.rvbar) }, | |
8821 | { .name = "RVBAR", .type = ARM_CP_ALIAS, | |
8822 | .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, | |
8823 | .access = PL2_R, | |
8824 | .fieldoffset = offsetof(CPUARMState, cp15.rvbar) }, | |
8825 | { .name = "RMR_EL2", .state = ARM_CP_STATE_AA64, | |
8826 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 2, | |
8827 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 1 }, | |
be8e8128 | 8828 | }; |
97198a7d | 8829 | define_arm_cp_regs(cpu, el2_reset_regs); |
be8e8128 | 8830 | } |
3b685ba7 | 8831 | } |
99a90811 RH |
8832 | |
8833 | /* Register the base EL3 cpregs. */ | |
81547d66 | 8834 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0f1a3b24 | 8835 | define_arm_cp_regs(cpu, el3_cp_reginfo); |
e24fdd23 PM |
8836 | ARMCPRegInfo el3_regs[] = { |
8837 | { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, | |
8838 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, | |
4a7319b7 | 8839 | .access = PL3_R, |
97198a7d RH |
8840 | .fieldoffset = offsetof(CPUARMState, cp15.rvbar), }, |
8841 | { .name = "RMR_EL3", .state = ARM_CP_STATE_AA64, | |
8842 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 2, | |
8843 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 1 }, | |
8844 | { .name = "RMR", .state = ARM_CP_STATE_AA32, | |
8845 | .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2, | |
8846 | .access = PL3_RW, .type = ARM_CP_CONST, | |
8847 | .resetvalue = arm_feature(env, ARM_FEATURE_AARCH64) }, | |
e24fdd23 PM |
8848 | { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, |
8849 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, | |
8850 | .access = PL3_RW, | |
8851 | .raw_writefn = raw_write, .writefn = sctlr_write, | |
8852 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), | |
8853 | .resetvalue = cpu->reset_sctlr }, | |
be8e8128 | 8854 | }; |
e24fdd23 PM |
8855 | |
8856 | define_arm_cp_regs(cpu, el3_regs); | |
81547d66 | 8857 | } |
9b37a28c FR |
8858 | /* |
8859 | * The behaviour of NSACR is sufficiently various that we don't | |
2f027fc5 PM |
8860 | * try to describe it in a single reginfo: |
8861 | * if EL3 is 64 bit, then trap to EL3 from S EL1, | |
8862 | * reads as constant 0xc00 from NS EL1 and NS EL2 | |
8863 | * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 | |
8864 | * if v7 without EL3, register doesn't exist | |
8865 | * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 | |
8866 | */ | |
8867 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
8868 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
10b0220e | 8869 | static const ARMCPRegInfo nsacr = { |
2f027fc5 PM |
8870 | .name = "NSACR", .type = ARM_CP_CONST, |
8871 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
8872 | .access = PL1_RW, .accessfn = nsacr_access, | |
8873 | .resetvalue = 0xc00 | |
8874 | }; | |
8875 | define_one_arm_cp_reg(cpu, &nsacr); | |
8876 | } else { | |
10b0220e | 8877 | static const ARMCPRegInfo nsacr = { |
2f027fc5 PM |
8878 | .name = "NSACR", |
8879 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
8880 | .access = PL3_RW | PL1_R, | |
8881 | .resetvalue = 0, | |
8882 | .fieldoffset = offsetof(CPUARMState, cp15.nsacr) | |
8883 | }; | |
8884 | define_one_arm_cp_reg(cpu, &nsacr); | |
8885 | } | |
8886 | } else { | |
8887 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
10b0220e | 8888 | static const ARMCPRegInfo nsacr = { |
2f027fc5 PM |
8889 | .name = "NSACR", .type = ARM_CP_CONST, |
8890 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
8891 | .access = PL1_R, | |
8892 | .resetvalue = 0xc00 | |
8893 | }; | |
8894 | define_one_arm_cp_reg(cpu, &nsacr); | |
8895 | } | |
8896 | } | |
8897 | ||
452a0955 | 8898 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
6cb0b013 PC |
8899 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8900 | /* PMSAv6 not implemented */ | |
8901 | assert(arm_feature(env, ARM_FEATURE_V7)); | |
8902 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); | |
8903 | define_arm_cp_regs(cpu, pmsav7_cp_reginfo); | |
8904 | } else { | |
8905 | define_arm_cp_regs(cpu, pmsav5_cp_reginfo); | |
8906 | } | |
18032bec | 8907 | } else { |
8e5d75c9 | 8908 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); |
18032bec | 8909 | define_arm_cp_regs(cpu, vmsa_cp_reginfo); |
4036b7d1 PM |
8910 | /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */ |
8911 | if (cpu_isar_feature(aa32_hpd, cpu)) { | |
ab638a32 RH |
8912 | define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); |
8913 | } | |
18032bec | 8914 | } |
c326b979 PM |
8915 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
8916 | define_arm_cp_regs(cpu, t2ee_cp_reginfo); | |
8917 | } | |
6cc7a3ae PM |
8918 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
8919 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); | |
8920 | } | |
4a501606 | 8921 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
8ce4d441 AB |
8922 | ARMCPRegInfo vapa_cp_reginfo[] = { |
8923 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, | |
8924 | .access = PL1_RW, .resetvalue = 0, | |
8925 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), | |
8926 | offsetoflow32(CPUARMState, cp15.par_ns) }, | |
8927 | .writefn = par_write}, | |
8928 | #ifndef CONFIG_USER_ONLY | |
8929 | /* This underdecoding is safe because the reginfo is NO_RAW. */ | |
8930 | { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, | |
8931 | .access = PL1_W, .accessfn = ats_access, | |
8932 | .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, | |
8933 | #endif | |
8934 | }; | |
8935 | ||
8936 | /* | |
8937 | * When LPAE exists this 32-bit PAR register is an alias of the | |
8938 | * 64-bit AArch32 PAR register defined in lpae_cp_reginfo[] | |
8939 | */ | |
8940 | if (arm_feature(env, ARM_FEATURE_LPAE)) { | |
8941 | vapa_cp_reginfo[0].type = ARM_CP_ALIAS | ARM_CP_NO_GDB; | |
8942 | } | |
4a501606 PM |
8943 | define_arm_cp_regs(cpu, vapa_cp_reginfo); |
8944 | } | |
c4804214 PM |
8945 | if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { |
8946 | define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); | |
8947 | } | |
8948 | if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { | |
8949 | define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); | |
8950 | } | |
8951 | if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { | |
8952 | define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); | |
8953 | } | |
18032bec PM |
8954 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
8955 | define_arm_cp_regs(cpu, omap_cp_reginfo); | |
8956 | } | |
34f90529 PM |
8957 | if (arm_feature(env, ARM_FEATURE_STRONGARM)) { |
8958 | define_arm_cp_regs(cpu, strongarm_cp_reginfo); | |
8959 | } | |
1047b9d7 PM |
8960 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
8961 | define_arm_cp_regs(cpu, xscale_cp_reginfo); | |
8962 | } | |
8963 | if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { | |
8964 | define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); | |
8965 | } | |
7ac681cf PM |
8966 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8967 | define_arm_cp_regs(cpu, lpae_cp_reginfo); | |
8968 | } | |
873b73c0 | 8969 | if (cpu_isar_feature(aa32_jazelle, cpu)) { |
f96f3d5f MZ |
8970 | define_arm_cp_regs(cpu, jazelle_regs); |
8971 | } | |
9b37a28c FR |
8972 | /* |
8973 | * Slightly awkwardly, the OMAP and StrongARM cores need all of | |
7884849c PM |
8974 | * cp15 crn=0 to be writes-ignored, whereas for other cores they should |
8975 | * be read-only (ie write causes UNDEF exception). | |
8976 | */ | |
8977 | { | |
00a29f3d | 8978 | ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { |
9b37a28c FR |
8979 | /* |
8980 | * Pre-v8 MIDR space. | |
00a29f3d | 8981 | * Note that the MIDR isn't a simple constant register because |
7884849c PM |
8982 | * of the TI925 behaviour where writes to another register can |
8983 | * cause the MIDR value to change. | |
97ce8d61 PC |
8984 | * |
8985 | * Unimplemented registers in the c15 0 0 0 space default to | |
8986 | * MIDR. Define MIDR first as this entire space, then CTR, TCMTR | |
8987 | * and friends override accordingly. | |
7884849c PM |
8988 | */ |
8989 | { .name = "MIDR", | |
97ce8d61 | 8990 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, |
7884849c | 8991 | .access = PL1_R, .resetvalue = cpu->midr, |
d4e6df63 | 8992 | .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, |
731de9e6 | 8993 | .readfn = midr_read, |
97ce8d61 PC |
8994 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
8995 | .type = ARM_CP_OVERRIDE }, | |
7884849c PM |
8996 | /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ |
8997 | { .name = "DUMMY", | |
8998 | .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, | |
8999 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
9000 | { .name = "DUMMY", | |
9001 | .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, | |
9002 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
9003 | { .name = "DUMMY", | |
9004 | .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, | |
9005 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
9006 | { .name = "DUMMY", | |
9007 | .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, | |
9008 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
9009 | { .name = "DUMMY", | |
9010 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | |
9011 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
7884849c | 9012 | }; |
00a29f3d | 9013 | ARMCPRegInfo id_v8_midr_cp_reginfo[] = { |
00a29f3d PM |
9014 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, |
9015 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, | |
731de9e6 | 9016 | .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, |
67dd8030 | 9017 | .fgt = FGT_MIDR_EL1, |
731de9e6 EI |
9018 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
9019 | .readfn = midr_read }, | |
c7f786ab | 9020 | /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */ |
ac00c79f SF |
9021 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, |
9022 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, | |
9023 | .access = PL1_R, .resetvalue = cpu->midr }, | |
00a29f3d PM |
9024 | { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, |
9025 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, | |
93fbc983 MZ |
9026 | .access = PL1_R, |
9027 | .accessfn = access_aa64_tid1, | |
67dd8030 | 9028 | .fgt = FGT_REVIDR_EL1, |
93fbc983 | 9029 | .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, |
00a29f3d | 9030 | }; |
c7f786ab | 9031 | ARMCPRegInfo id_v8_midr_alias_cp_reginfo = { |
acd8e83a | 9032 | .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST | ARM_CP_NO_GDB, |
c7f786ab TR |
9033 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, |
9034 | .access = PL1_R, .resetvalue = cpu->midr | |
9035 | }; | |
00a29f3d PM |
9036 | ARMCPRegInfo id_cp_reginfo[] = { |
9037 | /* These are common to v8 and pre-v8 */ | |
9038 | { .name = "CTR", | |
9039 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, | |
630fcd4d MZ |
9040 | .access = PL1_R, .accessfn = ctr_el0_access, |
9041 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
00a29f3d PM |
9042 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, |
9043 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, | |
9044 | .access = PL0_R, .accessfn = ctr_el0_access, | |
b19ed03c | 9045 | .fgt = FGT_CTR_EL0, |
00a29f3d PM |
9046 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, |
9047 | /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ | |
9048 | { .name = "TCMTR", | |
9049 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, | |
93fbc983 MZ |
9050 | .access = PL1_R, |
9051 | .accessfn = access_aa32_tid1, | |
9052 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
00a29f3d | 9053 | }; |
8085ce63 PC |
9054 | /* TLBTR is specific to VMSA */ |
9055 | ARMCPRegInfo id_tlbtr_reginfo = { | |
9056 | .name = "TLBTR", | |
9057 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, | |
93fbc983 MZ |
9058 | .access = PL1_R, |
9059 | .accessfn = access_aa32_tid1, | |
9060 | .type = ARM_CP_CONST, .resetvalue = 0, | |
8085ce63 | 9061 | }; |
3281af81 PC |
9062 | /* MPUIR is specific to PMSA V6+ */ |
9063 | ARMCPRegInfo id_mpuir_reginfo = { | |
9064 | .name = "MPUIR", | |
9065 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
9066 | .access = PL1_R, .type = ARM_CP_CONST, | |
9067 | .resetvalue = cpu->pmsav7_dregion << 8 | |
9068 | }; | |
761c4642 TR |
9069 | /* HMPUIR is specific to PMSA V8 */ |
9070 | ARMCPRegInfo id_hmpuir_reginfo = { | |
9071 | .name = "HMPUIR", | |
9072 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 4, | |
9073 | .access = PL2_R, .type = ARM_CP_CONST, | |
9074 | .resetvalue = cpu->pmsav8r_hdregion | |
9075 | }; | |
10b0220e | 9076 | static const ARMCPRegInfo crn0_wi_reginfo = { |
7884849c PM |
9077 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, |
9078 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | |
9079 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | |
9080 | }; | |
6c5c0fec | 9081 | #ifdef CONFIG_USER_ONLY |
10b0220e | 9082 | static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = { |
6c5c0fec | 9083 | { .name = "MIDR_EL1", |
bc6bd20e ZS |
9084 | .exported_bits = R_MIDR_EL1_REVISION_MASK | |
9085 | R_MIDR_EL1_PARTNUM_MASK | | |
9086 | R_MIDR_EL1_ARCHITECTURE_MASK | | |
9087 | R_MIDR_EL1_VARIANT_MASK | | |
9088 | R_MIDR_EL1_IMPLEMENTER_MASK }, | |
9089 | { .name = "REVIDR_EL1" }, | |
6c5c0fec AB |
9090 | }; |
9091 | modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo); | |
9092 | #endif | |
7884849c PM |
9093 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || |
9094 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | |
5809ac57 | 9095 | size_t i; |
9b37a28c FR |
9096 | /* |
9097 | * Register the blanket "writes ignored" value first to cover the | |
a703eda1 PC |
9098 | * whole space. Then update the specific ID registers to allow write |
9099 | * access, so that they ignore writes rather than causing them to | |
9100 | * UNDEF. | |
7884849c PM |
9101 | */ |
9102 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | |
5809ac57 RH |
9103 | for (i = 0; i < ARRAY_SIZE(id_pre_v8_midr_cp_reginfo); ++i) { |
9104 | id_pre_v8_midr_cp_reginfo[i].access = PL1_RW; | |
00a29f3d | 9105 | } |
5809ac57 RH |
9106 | for (i = 0; i < ARRAY_SIZE(id_cp_reginfo); ++i) { |
9107 | id_cp_reginfo[i].access = PL1_RW; | |
7884849c | 9108 | } |
10006112 | 9109 | id_mpuir_reginfo.access = PL1_RW; |
3281af81 | 9110 | id_tlbtr_reginfo.access = PL1_RW; |
7884849c | 9111 | } |
00a29f3d PM |
9112 | if (arm_feature(env, ARM_FEATURE_V8)) { |
9113 | define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); | |
c7f786ab TR |
9114 | if (!arm_feature(env, ARM_FEATURE_PMSA)) { |
9115 | define_one_arm_cp_reg(cpu, &id_v8_midr_alias_cp_reginfo); | |
9116 | } | |
00a29f3d PM |
9117 | } else { |
9118 | define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); | |
9119 | } | |
a703eda1 | 9120 | define_arm_cp_regs(cpu, id_cp_reginfo); |
452a0955 | 9121 | if (!arm_feature(env, ARM_FEATURE_PMSA)) { |
8085ce63 | 9122 | define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); |
761c4642 TR |
9123 | } else if (arm_feature(env, ARM_FEATURE_PMSA) && |
9124 | arm_feature(env, ARM_FEATURE_V8)) { | |
9125 | uint32_t i = 0; | |
9126 | char *tmp_string; | |
9127 | ||
9128 | define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); | |
9129 | define_one_arm_cp_reg(cpu, &id_hmpuir_reginfo); | |
9130 | define_arm_cp_regs(cpu, pmsav8r_cp_reginfo); | |
9131 | ||
9132 | /* Register alias is only valid for first 32 indexes */ | |
9133 | for (i = 0; i < MIN(cpu->pmsav7_dregion, 32); ++i) { | |
9134 | uint8_t crm = 0b1000 | extract32(i, 1, 3); | |
9135 | uint8_t opc1 = extract32(i, 4, 1); | |
9136 | uint8_t opc2 = extract32(i, 0, 1) << 2; | |
9137 | ||
9138 | tmp_string = g_strdup_printf("PRBAR%u", i); | |
9139 | ARMCPRegInfo tmp_prbarn_reginfo = { | |
9140 | .name = tmp_string, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW, | |
9141 | .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, | |
9142 | .access = PL1_RW, .resetvalue = 0, | |
9143 | .accessfn = access_tvm_trvm, | |
9144 | .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read | |
9145 | }; | |
9146 | define_one_arm_cp_reg(cpu, &tmp_prbarn_reginfo); | |
9147 | g_free(tmp_string); | |
9148 | ||
9149 | opc2 = extract32(i, 0, 1) << 2 | 0x1; | |
9150 | tmp_string = g_strdup_printf("PRLAR%u", i); | |
9151 | ARMCPRegInfo tmp_prlarn_reginfo = { | |
9152 | .name = tmp_string, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW, | |
9153 | .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, | |
9154 | .access = PL1_RW, .resetvalue = 0, | |
9155 | .accessfn = access_tvm_trvm, | |
9156 | .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read | |
9157 | }; | |
9158 | define_one_arm_cp_reg(cpu, &tmp_prlarn_reginfo); | |
9159 | g_free(tmp_string); | |
9160 | } | |
9161 | ||
9162 | /* Register alias is only valid for first 32 indexes */ | |
9163 | for (i = 0; i < MIN(cpu->pmsav8r_hdregion, 32); ++i) { | |
9164 | uint8_t crm = 0b1000 | extract32(i, 1, 3); | |
9165 | uint8_t opc1 = 0b100 | extract32(i, 4, 1); | |
9166 | uint8_t opc2 = extract32(i, 0, 1) << 2; | |
9167 | ||
9168 | tmp_string = g_strdup_printf("HPRBAR%u", i); | |
9169 | ARMCPRegInfo tmp_hprbarn_reginfo = { | |
9170 | .name = tmp_string, | |
9171 | .type = ARM_CP_NO_RAW, | |
9172 | .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, | |
9173 | .access = PL2_RW, .resetvalue = 0, | |
9174 | .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read | |
9175 | }; | |
9176 | define_one_arm_cp_reg(cpu, &tmp_hprbarn_reginfo); | |
9177 | g_free(tmp_string); | |
9178 | ||
9179 | opc2 = extract32(i, 0, 1) << 2 | 0x1; | |
9180 | tmp_string = g_strdup_printf("HPRLAR%u", i); | |
9181 | ARMCPRegInfo tmp_hprlarn_reginfo = { | |
9182 | .name = tmp_string, | |
9183 | .type = ARM_CP_NO_RAW, | |
9184 | .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, | |
9185 | .access = PL2_RW, .resetvalue = 0, | |
9186 | .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read | |
9187 | }; | |
9188 | define_one_arm_cp_reg(cpu, &tmp_hprlarn_reginfo); | |
9189 | g_free(tmp_string); | |
9190 | } | |
3281af81 PC |
9191 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
9192 | define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); | |
8085ce63 | 9193 | } |
7884849c PM |
9194 | } |
9195 | ||
97ce8d61 | 9196 | if (arm_feature(env, ARM_FEATURE_MPIDR)) { |
52264166 AB |
9197 | ARMCPRegInfo mpidr_cp_reginfo[] = { |
9198 | { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
9199 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | |
67dd8030 | 9200 | .fgt = FGT_MPIDR_EL1, |
52264166 | 9201 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, |
52264166 AB |
9202 | }; |
9203 | #ifdef CONFIG_USER_ONLY | |
10b0220e | 9204 | static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = { |
52264166 AB |
9205 | { .name = "MPIDR_EL1", |
9206 | .fixed_bits = 0x0000000080000000 }, | |
52264166 AB |
9207 | }; |
9208 | modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); | |
9209 | #endif | |
97ce8d61 PC |
9210 | define_arm_cp_regs(cpu, mpidr_cp_reginfo); |
9211 | } | |
9212 | ||
2771db27 | 9213 | if (arm_feature(env, ARM_FEATURE_AUXCR)) { |
834a6c69 PM |
9214 | ARMCPRegInfo auxcr_reginfo[] = { |
9215 | { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, | |
9216 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, | |
99602377 RH |
9217 | .access = PL1_RW, .accessfn = access_tacr, |
9218 | .type = ARM_CP_CONST, .resetvalue = cpu->reset_auxcr }, | |
834a6c69 PM |
9219 | { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, |
9220 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, | |
9221 | .access = PL2_RW, .type = ARM_CP_CONST, | |
9222 | .resetvalue = 0 }, | |
9223 | { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, | |
9224 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, | |
9225 | .access = PL3_RW, .type = ARM_CP_CONST, | |
9226 | .resetvalue = 0 }, | |
2771db27 | 9227 | }; |
834a6c69 | 9228 | define_arm_cp_regs(cpu, auxcr_reginfo); |
f6287c24 PM |
9229 | if (cpu_isar_feature(aa32_ac2, cpu)) { |
9230 | define_arm_cp_regs(cpu, actlr2_hactlr2_reginfo); | |
0e0456ab | 9231 | } |
2771db27 PM |
9232 | } |
9233 | ||
d8ba780b | 9234 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
d56974af LM |
9235 | /* |
9236 | * CBAR is IMPDEF, but common on Arm Cortex-A implementations. | |
9237 | * There are two flavours: | |
9238 | * (1) older 32-bit only cores have a simple 32-bit CBAR | |
9239 | * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a | |
9240 | * 32-bit register visible to AArch32 at a different encoding | |
9241 | * to the "flavour 1" register and with the bits rearranged to | |
9242 | * be able to squash a 64-bit address into the 32-bit view. | |
9243 | * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but | |
9244 | * in future if we support AArch32-only configs of some of the | |
9245 | * AArch64 cores we might need to add a specific feature flag | |
9246 | * to indicate cores with "flavour 2" CBAR. | |
9247 | */ | |
f318cec6 PM |
9248 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
9249 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | |
9250 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | |
9251 | | extract64(cpu->reset_cbar, 32, 12); | |
9252 | ARMCPRegInfo cbar_reginfo[] = { | |
9253 | { .name = "CBAR", | |
9254 | .type = ARM_CP_CONST, | |
d56974af LM |
9255 | .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0, |
9256 | .access = PL1_R, .resetvalue = cbar32 }, | |
f318cec6 PM |
9257 | { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, |
9258 | .type = ARM_CP_CONST, | |
9259 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | |
d56974af | 9260 | .access = PL1_R, .resetvalue = cpu->reset_cbar }, |
f318cec6 PM |
9261 | }; |
9262 | /* We don't implement a r/w 64 bit CBAR currently */ | |
9263 | assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); | |
9264 | define_arm_cp_regs(cpu, cbar_reginfo); | |
9265 | } else { | |
9266 | ARMCPRegInfo cbar = { | |
9267 | .name = "CBAR", | |
9268 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
04215eb1 | 9269 | .access = PL1_R | PL3_W, .resetvalue = cpu->reset_cbar, |
f318cec6 PM |
9270 | .fieldoffset = offsetof(CPUARMState, |
9271 | cp15.c15_config_base_address) | |
9272 | }; | |
9273 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | |
9274 | cbar.access = PL1_R; | |
9275 | cbar.fieldoffset = 0; | |
9276 | cbar.type = ARM_CP_CONST; | |
9277 | } | |
9278 | define_one_arm_cp_reg(cpu, &cbar); | |
9279 | } | |
d8ba780b PC |
9280 | } |
9281 | ||
91db4642 | 9282 | if (arm_feature(env, ARM_FEATURE_VBAR)) { |
10b0220e | 9283 | static const ARMCPRegInfo vbar_cp_reginfo[] = { |
91db4642 CLG |
9284 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, |
9285 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | |
9286 | .access = PL1_RW, .writefn = vbar_write, | |
bd8db7d9 | 9287 | .fgt = FGT_VBAR_EL1, |
91db4642 CLG |
9288 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), |
9289 | offsetof(CPUARMState, cp15.vbar_ns) }, | |
9290 | .resetvalue = 0 }, | |
91db4642 CLG |
9291 | }; |
9292 | define_arm_cp_regs(cpu, vbar_cp_reginfo); | |
9293 | } | |
9294 | ||
2771db27 PM |
9295 | /* Generic registers whose values depend on the implementation */ |
9296 | { | |
9297 | ARMCPRegInfo sctlr = { | |
5ebafdf3 | 9298 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, |
137feaa9 | 9299 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, |
84929218 | 9300 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
67dd8030 | 9301 | .fgt = FGT_SCTLR_EL1, |
137feaa9 FA |
9302 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), |
9303 | offsetof(CPUARMState, cp15.sctlr_ns) }, | |
d4e6df63 PM |
9304 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, |
9305 | .raw_writefn = raw_write, | |
2771db27 PM |
9306 | }; |
9307 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
9b37a28c FR |
9308 | /* |
9309 | * Normally we would always end the TB on an SCTLR write, but Linux | |
2771db27 PM |
9310 | * arch/arm/mach-pxa/sleep.S expects two instructions following |
9311 | * an MMU enable to execute from cache. Imitate this behaviour. | |
9312 | */ | |
9313 | sctlr.type |= ARM_CP_SUPPRESS_TB_END; | |
9314 | } | |
9315 | define_one_arm_cp_reg(cpu, &sctlr); | |
761c4642 TR |
9316 | |
9317 | if (arm_feature(env, ARM_FEATURE_PMSA) && | |
9318 | arm_feature(env, ARM_FEATURE_V8)) { | |
9319 | ARMCPRegInfo vsctlr = { | |
9320 | .name = "VSCTLR", .state = ARM_CP_STATE_AA32, | |
9321 | .cp = 15, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
9322 | .access = PL2_RW, .resetvalue = 0x0, | |
9323 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vsctlr), | |
9324 | }; | |
9325 | define_one_arm_cp_reg(cpu, &vsctlr); | |
9326 | } | |
2771db27 | 9327 | } |
5be5e8ed | 9328 | |
2d7137c1 | 9329 | if (cpu_isar_feature(aa64_lor, cpu)) { |
2d7137c1 RH |
9330 | define_arm_cp_regs(cpu, lor_reginfo); |
9331 | } | |
220f508f RH |
9332 | if (cpu_isar_feature(aa64_pan, cpu)) { |
9333 | define_one_arm_cp_reg(cpu, &pan_reginfo); | |
9334 | } | |
04b07d29 RH |
9335 | #ifndef CONFIG_USER_ONLY |
9336 | if (cpu_isar_feature(aa64_ats1e1, cpu)) { | |
9337 | define_arm_cp_regs(cpu, ats1e1_reginfo); | |
9338 | } | |
9339 | if (cpu_isar_feature(aa32_ats1e1, cpu)) { | |
9340 | define_arm_cp_regs(cpu, ats1cp_reginfo); | |
9341 | } | |
9342 | #endif | |
9eeb7a1c RH |
9343 | if (cpu_isar_feature(aa64_uao, cpu)) { |
9344 | define_one_arm_cp_reg(cpu, &uao_reginfo); | |
9345 | } | |
2d7137c1 | 9346 | |
dc8b1853 RC |
9347 | if (cpu_isar_feature(aa64_dit, cpu)) { |
9348 | define_one_arm_cp_reg(cpu, &dit_reginfo); | |
9349 | } | |
f2f68a78 RC |
9350 | if (cpu_isar_feature(aa64_ssbs, cpu)) { |
9351 | define_one_arm_cp_reg(cpu, &ssbs_reginfo); | |
9352 | } | |
58e93b48 RH |
9353 | if (cpu_isar_feature(any_ras, cpu)) { |
9354 | define_arm_cp_regs(cpu, minimal_ras_reginfo); | |
9355 | } | |
dc8b1853 | 9356 | |
52d18727 RH |
9357 | if (cpu_isar_feature(aa64_vh, cpu) || |
9358 | cpu_isar_feature(aa64_debugv8p2, cpu)) { | |
9359 | define_one_arm_cp_reg(cpu, &contextidr_el2); | |
9360 | } | |
e2a1a461 RH |
9361 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { |
9362 | define_arm_cp_regs(cpu, vhe_reginfo); | |
9363 | } | |
9364 | ||
cd208a1c | 9365 | if (cpu_isar_feature(aa64_sve, cpu)) { |
60360d82 | 9366 | define_arm_cp_regs(cpu, zcr_reginfo); |
5be5e8ed | 9367 | } |
967aa94f | 9368 | |
5814d587 RH |
9369 | if (cpu_isar_feature(aa64_hcx, cpu)) { |
9370 | define_one_arm_cp_reg(cpu, &hcrx_el2_reginfo); | |
9371 | } | |
9372 | ||
967aa94f | 9373 | #ifdef TARGET_AARCH64 |
9e5ec745 RH |
9374 | if (cpu_isar_feature(aa64_sme, cpu)) { |
9375 | define_arm_cp_regs(cpu, sme_reginfo); | |
9376 | } | |
967aa94f RH |
9377 | if (cpu_isar_feature(aa64_pauth, cpu)) { |
9378 | define_arm_cp_regs(cpu, pauth_reginfo); | |
9379 | } | |
de390645 RH |
9380 | if (cpu_isar_feature(aa64_rndr, cpu)) { |
9381 | define_arm_cp_regs(cpu, rndr_reginfo); | |
9382 | } | |
84940ed8 RC |
9383 | if (cpu_isar_feature(aa64_tlbirange, cpu)) { |
9384 | define_arm_cp_regs(cpu, tlbirange_reginfo); | |
9385 | } | |
7113d618 RC |
9386 | if (cpu_isar_feature(aa64_tlbios, cpu)) { |
9387 | define_arm_cp_regs(cpu, tlbios_reginfo); | |
9388 | } | |
0d57b499 BM |
9389 | /* Data Cache clean instructions up to PoP */ |
9390 | if (cpu_isar_feature(aa64_dcpop, cpu)) { | |
9391 | define_one_arm_cp_reg(cpu, dcpop_reg); | |
9392 | ||
9393 | if (cpu_isar_feature(aa64_dcpodp, cpu)) { | |
9394 | define_one_arm_cp_reg(cpu, dcpodp_reg); | |
9395 | } | |
9396 | } | |
4b779ceb RH |
9397 | |
9398 | /* | |
9399 | * If full MTE is enabled, add all of the system registers. | |
9400 | * If only "instructions available at EL0" are enabled, | |
9401 | * then define only a RAZ/WI version of PSTATE.TCO. | |
9402 | */ | |
9403 | if (cpu_isar_feature(aa64_mte, cpu)) { | |
851ec6eb RH |
9404 | ARMCPRegInfo gmid_reginfo = { |
9405 | .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, | |
9406 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, | |
9407 | .access = PL1_R, .accessfn = access_aa64_tid5, | |
9408 | .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize, | |
9409 | }; | |
9410 | define_one_arm_cp_reg(cpu, &gmid_reginfo); | |
4b779ceb | 9411 | define_arm_cp_regs(cpu, mte_reginfo); |
5463df16 | 9412 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); |
4b779ceb RH |
9413 | } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { |
9414 | define_arm_cp_regs(cpu, mte_tco_ro_reginfo); | |
5463df16 | 9415 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); |
4b779ceb | 9416 | } |
7cb1e618 RH |
9417 | |
9418 | if (cpu_isar_feature(aa64_scxtnum, cpu)) { | |
9419 | define_arm_cp_regs(cpu, scxtnum_reginfo); | |
9420 | } | |
15126d9c PM |
9421 | |
9422 | if (cpu_isar_feature(aa64_fgt, cpu)) { | |
9423 | define_arm_cp_regs(cpu, fgt_reginfo); | |
9424 | } | |
ef1febe7 RH |
9425 | |
9426 | if (cpu_isar_feature(aa64_rme, cpu)) { | |
9427 | define_arm_cp_regs(cpu, rme_reginfo); | |
9428 | if (cpu_isar_feature(aa64_mte, cpu)) { | |
9429 | define_arm_cp_regs(cpu, rme_mte_reginfo); | |
9430 | } | |
9431 | } | |
967aa94f | 9432 | #endif |
cb570bd3 | 9433 | |
22e57073 | 9434 | if (cpu_isar_feature(any_predinv, cpu)) { |
cb570bd3 RH |
9435 | define_arm_cp_regs(cpu, predinv_reginfo); |
9436 | } | |
e2cce18f | 9437 | |
957e6155 PM |
9438 | if (cpu_isar_feature(any_ccidx, cpu)) { |
9439 | define_arm_cp_regs(cpu, ccsidr2_reginfo); | |
9440 | } | |
9441 | ||
e2cce18f RH |
9442 | #ifndef CONFIG_USER_ONLY |
9443 | /* | |
9444 | * Register redirections and aliases must be done last, | |
9445 | * after the registers from the other extensions have been defined. | |
9446 | */ | |
9447 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { | |
9448 | define_arm_vh_e2h_redirects_aliases(cpu); | |
9449 | } | |
9450 | #endif | |
2ceb98c0 PM |
9451 | } |
9452 | ||
777dc784 PM |
9453 | /* Sort alphabetically by type name, except for "any". */ |
9454 | static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) | |
5adb4839 | 9455 | { |
777dc784 PM |
9456 | ObjectClass *class_a = (ObjectClass *)a; |
9457 | ObjectClass *class_b = (ObjectClass *)b; | |
9458 | const char *name_a, *name_b; | |
5adb4839 | 9459 | |
777dc784 PM |
9460 | name_a = object_class_get_name(class_a); |
9461 | name_b = object_class_get_name(class_b); | |
51492fd1 | 9462 | if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 | 9463 | return 1; |
51492fd1 | 9464 | } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 PM |
9465 | return -1; |
9466 | } else { | |
9467 | return strcmp(name_a, name_b); | |
5adb4839 PB |
9468 | } |
9469 | } | |
9470 | ||
777dc784 | 9471 | static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
40f137e1 | 9472 | { |
777dc784 | 9473 | ObjectClass *oc = data; |
977c33ba | 9474 | CPUClass *cc = CPU_CLASS(oc); |
51492fd1 AF |
9475 | const char *typename; |
9476 | char *name; | |
3371d272 | 9477 | |
51492fd1 AF |
9478 | typename = object_class_get_name(oc); |
9479 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
977c33ba DB |
9480 | if (cc->deprecation_note) { |
9481 | qemu_printf(" %s (deprecated)\n", name); | |
9482 | } else { | |
9483 | qemu_printf(" %s\n", name); | |
9484 | } | |
51492fd1 | 9485 | g_free(name); |
777dc784 PM |
9486 | } |
9487 | ||
0442428a | 9488 | void arm_cpu_list(void) |
777dc784 | 9489 | { |
777dc784 PM |
9490 | GSList *list; |
9491 | ||
9492 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
9493 | list = g_slist_sort(list, arm_cpu_list_compare); | |
0442428a MA |
9494 | qemu_printf("Available CPUs:\n"); |
9495 | g_slist_foreach(list, arm_cpu_list_entry, NULL); | |
777dc784 | 9496 | g_slist_free(list); |
40f137e1 PB |
9497 | } |
9498 | ||
1859f8c3 RH |
9499 | /* |
9500 | * Private utility function for define_one_arm_cp_reg_with_opaque(): | |
9501 | * add a single reginfo struct to the hash table. | |
9502 | */ | |
6e6efd61 | 9503 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
cbe64585 RH |
9504 | void *opaque, CPState state, |
9505 | CPSecureState secstate, | |
9c513e78 AB |
9506 | int crm, int opc1, int opc2, |
9507 | const char *name) | |
6e6efd61 | 9508 | { |
696ba377 | 9509 | CPUARMState *env = &cpu->env; |
5860362d | 9510 | uint32_t key; |
c27f5d3a | 9511 | ARMCPRegInfo *r2; |
4c8c4541 RH |
9512 | bool is64 = r->type & ARM_CP_64BIT; |
9513 | bool ns = secstate & ARM_CP_SECSTATE_NS; | |
cac65299 | 9514 | int cp = r->cp; |
c27f5d3a | 9515 | size_t name_len; |
696ba377 | 9516 | bool make_const; |
c27f5d3a | 9517 | |
cac65299 RH |
9518 | switch (state) { |
9519 | case ARM_CP_STATE_AA32: | |
9520 | /* We assume it is a cp15 register if the .cp field is left unset. */ | |
9521 | if (cp == 0 && r->state == ARM_CP_STATE_BOTH) { | |
9522 | cp = 15; | |
9523 | } | |
9524 | key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2); | |
9525 | break; | |
9526 | case ARM_CP_STATE_AA64: | |
9527 | /* | |
9528 | * To allow abbreviation of ARMCPRegInfo definitions, we treat | |
9529 | * cp == 0 as equivalent to the value for "standard guest-visible | |
9530 | * sysreg". STATE_BOTH definitions are also always "standard sysreg" | |
9531 | * in their AArch64 view (the .cp value may be non-zero for the | |
9532 | * benefit of the AArch32 view). | |
9533 | */ | |
9534 | if (cp == 0 || r->state == ARM_CP_STATE_BOTH) { | |
9535 | cp = CP_REG_ARM64_SYSREG_CP; | |
9536 | } | |
9537 | key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2); | |
9538 | break; | |
9539 | default: | |
9540 | g_assert_not_reached(); | |
9541 | } | |
9542 | ||
dc44545b RH |
9543 | /* Overriding of an existing definition must be explicitly requested. */ |
9544 | if (!(r->type & ARM_CP_OVERRIDE)) { | |
9545 | const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key); | |
9546 | if (oldreg) { | |
9547 | assert(oldreg->type & ARM_CP_OVERRIDE); | |
9548 | } | |
9549 | } | |
9550 | ||
696ba377 RH |
9551 | /* |
9552 | * Eliminate registers that are not present because the EL is missing. | |
9553 | * Doing this here makes it easier to put all registers for a given | |
9554 | * feature into the same ARMCPRegInfo array and define them all at once. | |
9555 | */ | |
9556 | make_const = false; | |
9557 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
9558 | /* | |
9559 | * An EL2 register without EL2 but with EL3 is (usually) RES0. | |
9560 | * See rule RJFFP in section D1.1.3 of DDI0487H.a. | |
9561 | */ | |
9562 | int min_el = ctz32(r->access) / 2; | |
9563 | if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) { | |
9564 | if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { | |
9565 | return; | |
9566 | } | |
9567 | make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP); | |
9568 | } | |
9569 | } else { | |
9570 | CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2) | |
9571 | ? PL2_RW : PL1_RW); | |
9572 | if ((r->access & max_el) == 0) { | |
9573 | return; | |
9574 | } | |
9575 | } | |
9576 | ||
c27f5d3a RH |
9577 | /* Combine cpreg and name into one allocation. */ |
9578 | name_len = strlen(name) + 1; | |
9579 | r2 = g_malloc(sizeof(*r2) + name_len); | |
9580 | *r2 = *r; | |
9581 | r2->name = memcpy(r2 + 1, name, name_len); | |
3f3c82a5 | 9582 | |
cc946d96 RH |
9583 | /* |
9584 | * Update fields to match the instantiation, overwiting wildcards | |
9585 | * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH. | |
3f3c82a5 | 9586 | */ |
cc946d96 RH |
9587 | r2->cp = cp; |
9588 | r2->crm = crm; | |
9589 | r2->opc1 = opc1; | |
9590 | r2->opc2 = opc2; | |
9591 | r2->state = state; | |
3f3c82a5 | 9592 | r2->secure = secstate; |
cc946d96 RH |
9593 | if (opaque) { |
9594 | r2->opaque = opaque; | |
9595 | } | |
3f3c82a5 | 9596 | |
696ba377 RH |
9597 | if (make_const) { |
9598 | /* This should not have been a very special register to begin. */ | |
9599 | int old_special = r2->type & ARM_CP_SPECIAL_MASK; | |
9600 | assert(old_special == 0 || old_special == ARM_CP_NOP); | |
1859f8c3 | 9601 | /* |
696ba377 RH |
9602 | * Set the special function to CONST, retaining the other flags. |
9603 | * This is important for e.g. ARM_CP_SVE so that we still | |
9604 | * take the SVE trap if CPTR_EL3.EZ == 0. | |
f5a0a5a5 | 9605 | */ |
696ba377 RH |
9606 | r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST; |
9607 | /* | |
9608 | * Usually, these registers become RES0, but there are a few | |
9609 | * special cases like VPIDR_EL2 which have a constant non-zero | |
9610 | * value with writes ignored. | |
9611 | */ | |
9612 | if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { | |
9613 | r2->resetvalue = 0; | |
9614 | } | |
9615 | /* | |
9616 | * ARM_CP_CONST has precedence, so removing the callbacks and | |
9617 | * offsets are not strictly necessary, but it is potentially | |
9618 | * less confusing to debug later. | |
9619 | */ | |
9620 | r2->readfn = NULL; | |
9621 | r2->writefn = NULL; | |
9622 | r2->raw_readfn = NULL; | |
9623 | r2->raw_writefn = NULL; | |
9624 | r2->resetfn = NULL; | |
9625 | r2->fieldoffset = 0; | |
9626 | r2->bank_fieldoffsets[0] = 0; | |
9627 | r2->bank_fieldoffsets[1] = 0; | |
9628 | } else { | |
9629 | bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; | |
3f3c82a5 | 9630 | |
10748a96 | 9631 | if (isbanked) { |
1859f8c3 | 9632 | /* |
696ba377 RH |
9633 | * Register is banked (using both entries in array). |
9634 | * Overwriting fieldoffset as the array is only used to define | |
9635 | * banked registers but later only fieldoffset is used. | |
3f3c82a5 | 9636 | */ |
696ba377 RH |
9637 | r2->fieldoffset = r->bank_fieldoffsets[ns]; |
9638 | } | |
9639 | if (state == ARM_CP_STATE_AA32) { | |
9640 | if (isbanked) { | |
9641 | /* | |
9642 | * If the register is banked then we don't need to migrate or | |
9643 | * reset the 32-bit instance in certain cases: | |
9644 | * | |
9645 | * 1) If the register has both 32-bit and 64-bit instances | |
9646 | * then we can count on the 64-bit instance taking care | |
9647 | * of the non-secure bank. | |
9648 | * 2) If ARMv8 is enabled then we can count on a 64-bit | |
9649 | * version taking care of the secure bank. This requires | |
9650 | * that separate 32 and 64-bit definitions are provided. | |
9651 | */ | |
9652 | if ((r->state == ARM_CP_STATE_BOTH && ns) || | |
9653 | (arm_feature(env, ARM_FEATURE_V8) && !ns)) { | |
9654 | r2->type |= ARM_CP_ALIAS; | |
9655 | } | |
9656 | } else if ((secstate != r->secure) && !ns) { | |
9657 | /* | |
9658 | * The register is not banked so we only want to allow | |
9659 | * migration of the non-secure instance. | |
9660 | */ | |
7a0e58fa | 9661 | r2->type |= ARM_CP_ALIAS; |
3f3c82a5 | 9662 | } |
3f3c82a5 | 9663 | |
696ba377 RH |
9664 | if (HOST_BIG_ENDIAN && |
9665 | r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) { | |
9666 | r2->fieldoffset += sizeof(uint32_t); | |
9667 | } | |
3f3c82a5 | 9668 | } |
f5a0a5a5 | 9669 | } |
cc946d96 | 9670 | |
1859f8c3 RH |
9671 | /* |
9672 | * By convention, for wildcarded registers only the first | |
6e6efd61 | 9673 | * entry is used for migration; the others are marked as |
7a0e58fa | 9674 | * ALIAS so we don't try to transfer the register |
6e6efd61 | 9675 | * multiple times. Special registers (ie NOP/WFI) are |
7a0e58fa | 9676 | * never migratable and not even raw-accessible. |
6e6efd61 | 9677 | */ |
696ba377 | 9678 | if (r2->type & ARM_CP_SPECIAL_MASK) { |
7a0e58fa PM |
9679 | r2->type |= ARM_CP_NO_RAW; |
9680 | } | |
9681 | if (((r->crm == CP_ANY) && crm != 0) || | |
6e6efd61 PM |
9682 | ((r->opc1 == CP_ANY) && opc1 != 0) || |
9683 | ((r->opc2 == CP_ANY) && opc2 != 0)) { | |
1f163787 | 9684 | r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB; |
6e6efd61 PM |
9685 | } |
9686 | ||
1859f8c3 RH |
9687 | /* |
9688 | * Check that raw accesses are either forbidden or handled. Note that | |
375421cc PM |
9689 | * we can't assert this earlier because the setup of fieldoffset for |
9690 | * banked registers has to be done first. | |
9691 | */ | |
9692 | if (!(r2->type & ARM_CP_NO_RAW)) { | |
9693 | assert(!raw_accessors_invalid(r2)); | |
9694 | } | |
9695 | ||
5860362d | 9696 | g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); |
6e6efd61 PM |
9697 | } |
9698 | ||
9699 | ||
4b6a83fb PM |
9700 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
9701 | const ARMCPRegInfo *r, void *opaque) | |
9702 | { | |
9b37a28c FR |
9703 | /* |
9704 | * Define implementations of coprocessor registers. | |
4b6a83fb PM |
9705 | * We store these in a hashtable because typically |
9706 | * there are less than 150 registers in a space which | |
9707 | * is 16*16*16*8*8 = 262144 in size. | |
9708 | * Wildcarding is supported for the crm, opc1 and opc2 fields. | |
9709 | * If a register is defined twice then the second definition is | |
9710 | * used, so this can be used to define some generic registers and | |
9711 | * then override them with implementation specific variations. | |
9712 | * At least one of the original and the second definition should | |
9713 | * include ARM_CP_OVERRIDE in its type bits -- this is just a guard | |
9714 | * against accidental use. | |
f5a0a5a5 PM |
9715 | * |
9716 | * The state field defines whether the register is to be | |
9717 | * visible in the AArch32 or AArch64 execution state. If the | |
9718 | * state is set to ARM_CP_STATE_BOTH then we synthesise a | |
9719 | * reginfo structure for the AArch32 view, which sees the lower | |
9720 | * 32 bits of the 64 bit register. | |
9721 | * | |
9722 | * Only registers visible in AArch64 may set r->opc0; opc0 cannot | |
9723 | * be wildcarded. AArch64 registers are always considered to be 64 | |
9724 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | |
9725 | * the register, if any. | |
4b6a83fb | 9726 | */ |
d95101d6 | 9727 | int crm, opc1, opc2; |
4b6a83fb PM |
9728 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
9729 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | |
9730 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | |
9731 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | |
9732 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | |
9733 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | |
d95101d6 RH |
9734 | CPState state; |
9735 | ||
4b6a83fb PM |
9736 | /* 64 bit registers have only CRm and Opc1 fields */ |
9737 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | |
f5a0a5a5 PM |
9738 | /* op0 only exists in the AArch64 encodings */ |
9739 | assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); | |
9740 | /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ | |
9741 | assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); | |
cd8be50e PM |
9742 | /* |
9743 | * This API is only for Arm's system coprocessors (14 and 15) or | |
9744 | * (M-profile or v7A-and-earlier only) for implementation defined | |
9745 | * coprocessors in the range 0..7. Our decode assumes this, since | |
9746 | * 8..13 can be used for other insns including VFP and Neon. See | |
9747 | * valid_cp() in translate.c. Assert here that we haven't tried | |
9748 | * to use an invalid coprocessor number. | |
9749 | */ | |
9750 | switch (r->state) { | |
9751 | case ARM_CP_STATE_BOTH: | |
9752 | /* 0 has a special meaning, but otherwise the same rules as AA32. */ | |
9753 | if (r->cp == 0) { | |
9754 | break; | |
9755 | } | |
9756 | /* fall through */ | |
9757 | case ARM_CP_STATE_AA32: | |
9758 | if (arm_feature(&cpu->env, ARM_FEATURE_V8) && | |
9759 | !arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
9760 | assert(r->cp >= 14 && r->cp <= 15); | |
9761 | } else { | |
9762 | assert(r->cp < 8 || (r->cp >= 14 && r->cp <= 15)); | |
9763 | } | |
9764 | break; | |
9765 | case ARM_CP_STATE_AA64: | |
9766 | assert(r->cp == 0 || r->cp == CP_REG_ARM64_SYSREG_CP); | |
9767 | break; | |
9768 | default: | |
9769 | g_assert_not_reached(); | |
9770 | } | |
9b37a28c FR |
9771 | /* |
9772 | * The AArch64 pseudocode CheckSystemAccess() specifies that op1 | |
f5a0a5a5 PM |
9773 | * encodes a minimum access level for the register. We roll this |
9774 | * runtime check into our general permission check code, so check | |
9775 | * here that the reginfo's specified permissions are strict enough | |
9776 | * to encompass the generic architectural permission check. | |
9777 | */ | |
9778 | if (r->state != ARM_CP_STATE_AA32) { | |
39107337 | 9779 | CPAccessRights mask; |
f5a0a5a5 | 9780 | switch (r->opc1) { |
b5bd7440 AB |
9781 | case 0: |
9782 | /* min_EL EL1, but some accessible to EL0 via kernel ABI */ | |
9783 | mask = PL0U_R | PL1_RW; | |
9784 | break; | |
9785 | case 1: case 2: | |
f5a0a5a5 PM |
9786 | /* min_EL EL1 */ |
9787 | mask = PL1_RW; | |
9788 | break; | |
9789 | case 3: | |
9790 | /* min_EL EL0 */ | |
9791 | mask = PL0_RW; | |
9792 | break; | |
9793 | case 4: | |
b4ecf60f | 9794 | case 5: |
f5a0a5a5 PM |
9795 | /* min_EL EL2 */ |
9796 | mask = PL2_RW; | |
9797 | break; | |
f5a0a5a5 PM |
9798 | case 6: |
9799 | /* min_EL EL3 */ | |
9800 | mask = PL3_RW; | |
9801 | break; | |
9802 | case 7: | |
9803 | /* min_EL EL1, secure mode only (we don't check the latter) */ | |
9804 | mask = PL1_RW; | |
9805 | break; | |
9806 | default: | |
9807 | /* broken reginfo with out-of-range opc1 */ | |
d385a605 | 9808 | g_assert_not_reached(); |
f5a0a5a5 PM |
9809 | } |
9810 | /* assert our permissions are not too lax (stricter is fine) */ | |
9811 | assert((r->access & ~mask) == 0); | |
9812 | } | |
9813 | ||
9b37a28c FR |
9814 | /* |
9815 | * Check that the register definition has enough info to handle | |
4b6a83fb PM |
9816 | * reads and writes if they are permitted. |
9817 | */ | |
87c3f0f2 | 9818 | if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) { |
4b6a83fb | 9819 | if (r->access & PL3_R) { |
3f3c82a5 FA |
9820 | assert((r->fieldoffset || |
9821 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
9822 | r->readfn); | |
4b6a83fb PM |
9823 | } |
9824 | if (r->access & PL3_W) { | |
3f3c82a5 FA |
9825 | assert((r->fieldoffset || |
9826 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
9827 | r->writefn); | |
4b6a83fb PM |
9828 | } |
9829 | } | |
5809ac57 | 9830 | |
4b6a83fb PM |
9831 | for (crm = crmmin; crm <= crmmax; crm++) { |
9832 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | |
9833 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | |
f5a0a5a5 PM |
9834 | for (state = ARM_CP_STATE_AA32; |
9835 | state <= ARM_CP_STATE_AA64; state++) { | |
9836 | if (r->state != state && r->state != ARM_CP_STATE_BOTH) { | |
9837 | continue; | |
9838 | } | |
3f3c82a5 | 9839 | if (state == ARM_CP_STATE_AA32) { |
9b37a28c FR |
9840 | /* |
9841 | * Under AArch32 CP registers can be common | |
3f3c82a5 FA |
9842 | * (same for secure and non-secure world) or banked. |
9843 | */ | |
9c513e78 AB |
9844 | char *name; |
9845 | ||
3f3c82a5 FA |
9846 | switch (r->secure) { |
9847 | case ARM_CP_SECSTATE_S: | |
9848 | case ARM_CP_SECSTATE_NS: | |
9849 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
9c513e78 AB |
9850 | r->secure, crm, opc1, opc2, |
9851 | r->name); | |
3f3c82a5 | 9852 | break; |
cbe64585 | 9853 | case ARM_CP_SECSTATE_BOTH: |
9c513e78 | 9854 | name = g_strdup_printf("%s_S", r->name); |
3f3c82a5 FA |
9855 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
9856 | ARM_CP_SECSTATE_S, | |
9c513e78 AB |
9857 | crm, opc1, opc2, name); |
9858 | g_free(name); | |
3f3c82a5 FA |
9859 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
9860 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 9861 | crm, opc1, opc2, r->name); |
3f3c82a5 | 9862 | break; |
cbe64585 RH |
9863 | default: |
9864 | g_assert_not_reached(); | |
3f3c82a5 FA |
9865 | } |
9866 | } else { | |
9b37a28c FR |
9867 | /* |
9868 | * AArch64 registers get mapped to non-secure instance | |
9869 | * of AArch32 | |
9870 | */ | |
3f3c82a5 FA |
9871 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
9872 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 9873 | crm, opc1, opc2, r->name); |
3f3c82a5 | 9874 | } |
f5a0a5a5 | 9875 | } |
4b6a83fb PM |
9876 | } |
9877 | } | |
9878 | } | |
9879 | } | |
9880 | ||
5809ac57 RH |
9881 | /* Define a whole list of registers */ |
9882 | void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs, | |
9883 | void *opaque, size_t len) | |
4b6a83fb | 9884 | { |
5809ac57 RH |
9885 | size_t i; |
9886 | for (i = 0; i < len; ++i) { | |
9887 | define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque); | |
4b6a83fb PM |
9888 | } |
9889 | } | |
9890 | ||
6c5c0fec AB |
9891 | /* |
9892 | * Modify ARMCPRegInfo for access from userspace. | |
9893 | * | |
9894 | * This is a data driven modification directed by | |
9895 | * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as | |
9896 | * user-space cannot alter any values and dynamic values pertaining to | |
9897 | * execution state are hidden from user space view anyway. | |
9898 | */ | |
5809ac57 RH |
9899 | void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, |
9900 | const ARMCPRegUserSpaceInfo *mods, | |
9901 | size_t mods_len) | |
6c5c0fec | 9902 | { |
5809ac57 RH |
9903 | for (size_t mi = 0; mi < mods_len; ++mi) { |
9904 | const ARMCPRegUserSpaceInfo *m = mods + mi; | |
d040242e | 9905 | GPatternSpec *pat = NULL; |
5809ac57 | 9906 | |
d040242e AB |
9907 | if (m->is_glob) { |
9908 | pat = g_pattern_spec_new(m->name); | |
9909 | } | |
5809ac57 RH |
9910 | for (size_t ri = 0; ri < regs_len; ++ri) { |
9911 | ARMCPRegInfo *r = regs + ri; | |
9912 | ||
d040242e AB |
9913 | if (pat && g_pattern_match_string(pat, r->name)) { |
9914 | r->type = ARM_CP_CONST; | |
9915 | r->access = PL0U_R; | |
9916 | r->resetvalue = 0; | |
9917 | /* continue */ | |
9918 | } else if (strcmp(r->name, m->name) == 0) { | |
6c5c0fec AB |
9919 | r->type = ARM_CP_CONST; |
9920 | r->access = PL0U_R; | |
9921 | r->resetvalue &= m->exported_bits; | |
9922 | r->resetvalue |= m->fixed_bits; | |
9923 | break; | |
9924 | } | |
9925 | } | |
d040242e AB |
9926 | if (pat) { |
9927 | g_pattern_spec_free(pat); | |
9928 | } | |
6c5c0fec AB |
9929 | } |
9930 | } | |
9931 | ||
60322b39 | 9932 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) |
4b6a83fb | 9933 | { |
5860362d | 9934 | return g_hash_table_lookup(cpregs, (gpointer)(uintptr_t)encoded_cp); |
4b6a83fb PM |
9935 | } |
9936 | ||
c4241c7d PM |
9937 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
9938 | uint64_t value) | |
4b6a83fb PM |
9939 | { |
9940 | /* Helper coprocessor write function for write-ignore registers */ | |
4b6a83fb PM |
9941 | } |
9942 | ||
c4241c7d | 9943 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) |
4b6a83fb PM |
9944 | { |
9945 | /* Helper coprocessor write function for read-as-zero registers */ | |
4b6a83fb PM |
9946 | return 0; |
9947 | } | |
9948 | ||
f5a0a5a5 PM |
9949 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) |
9950 | { | |
9951 | /* Helper coprocessor reset function for do-nothing-on-reset registers */ | |
9952 | } | |
9953 | ||
af393ffc | 9954 | static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) |
37064a8b | 9955 | { |
9b37a28c FR |
9956 | /* |
9957 | * Return true if it is not valid for us to switch to | |
37064a8b PM |
9958 | * this CPU mode (ie all the UNPREDICTABLE cases in |
9959 | * the ARM ARM CPSRWriteByInstr pseudocode). | |
9960 | */ | |
af393ffc PM |
9961 | |
9962 | /* Changes to or from Hyp via MSR and CPS are illegal. */ | |
9963 | if (write_type == CPSRWriteByInstr && | |
9964 | ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || | |
9965 | mode == ARM_CPU_MODE_HYP)) { | |
9966 | return 1; | |
9967 | } | |
9968 | ||
37064a8b PM |
9969 | switch (mode) { |
9970 | case ARM_CPU_MODE_USR: | |
10eacda7 | 9971 | return 0; |
37064a8b PM |
9972 | case ARM_CPU_MODE_SYS: |
9973 | case ARM_CPU_MODE_SVC: | |
9974 | case ARM_CPU_MODE_ABT: | |
9975 | case ARM_CPU_MODE_UND: | |
9976 | case ARM_CPU_MODE_IRQ: | |
9977 | case ARM_CPU_MODE_FIQ: | |
9b37a28c FR |
9978 | /* |
9979 | * Note that we don't implement the IMPDEF NSACR.RFR which in v7 | |
52ff951b PM |
9980 | * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) |
9981 | */ | |
9b37a28c FR |
9982 | /* |
9983 | * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR | |
10eacda7 PM |
9984 | * and CPS are treated as illegal mode changes. |
9985 | */ | |
9986 | if (write_type == CPSRWriteByInstr && | |
10eacda7 | 9987 | (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && |
7c208e0f | 9988 | (arm_hcr_el2_eff(env) & HCR_TGE)) { |
10eacda7 PM |
9989 | return 1; |
9990 | } | |
37064a8b | 9991 | return 0; |
e6c8fc07 | 9992 | case ARM_CPU_MODE_HYP: |
e6ef0169 | 9993 | return !arm_is_el2_enabled(env) || arm_current_el(env) < 2; |
027fc527 | 9994 | case ARM_CPU_MODE_MON: |
58ae2d1f | 9995 | return arm_current_el(env) < 3; |
37064a8b PM |
9996 | default: |
9997 | return 1; | |
9998 | } | |
9999 | } | |
10000 | ||
2f4a40e5 AZ |
10001 | uint32_t cpsr_read(CPUARMState *env) |
10002 | { | |
10003 | int ZF; | |
6fbe23d5 PB |
10004 | ZF = (env->ZF == 0); |
10005 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
10006 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
10007 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
10008 | | ((env->condexec_bits & 0xfc) << 8) | |
af519934 | 10009 | | (env->GE << 16) | (env->daif & CPSR_AIF); |
2f4a40e5 AZ |
10010 | } |
10011 | ||
50866ba5 PM |
10012 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, |
10013 | CPSRWriteType write_type) | |
2f4a40e5 | 10014 | { |
6e8801f9 | 10015 | uint32_t changed_daif; |
e784807c PM |
10016 | bool rebuild_hflags = (write_type != CPSRWriteRaw) && |
10017 | (mask & (CPSR_M | CPSR_E | CPSR_IL)); | |
6e8801f9 | 10018 | |
2f4a40e5 | 10019 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
10020 | env->ZF = (~val) & CPSR_Z; |
10021 | env->NF = val; | |
2f4a40e5 AZ |
10022 | env->CF = (val >> 29) & 1; |
10023 | env->VF = (val << 3) & 0x80000000; | |
10024 | } | |
f927dbda | 10025 | if (mask & CPSR_Q) { |
2f4a40e5 | 10026 | env->QF = ((val & CPSR_Q) != 0); |
f927dbda FR |
10027 | } |
10028 | if (mask & CPSR_T) { | |
2f4a40e5 | 10029 | env->thumb = ((val & CPSR_T) != 0); |
f927dbda | 10030 | } |
2f4a40e5 AZ |
10031 | if (mask & CPSR_IT_0_1) { |
10032 | env->condexec_bits &= ~3; | |
10033 | env->condexec_bits |= (val >> 25) & 3; | |
10034 | } | |
10035 | if (mask & CPSR_IT_2_7) { | |
10036 | env->condexec_bits &= 3; | |
10037 | env->condexec_bits |= (val >> 8) & 0xfc; | |
10038 | } | |
10039 | if (mask & CPSR_GE) { | |
10040 | env->GE = (val >> 16) & 0xf; | |
10041 | } | |
10042 | ||
9b37a28c FR |
10043 | /* |
10044 | * In a V7 implementation that includes the security extensions but does | |
6e8801f9 FA |
10045 | * not include Virtualization Extensions the SCR.FW and SCR.AW bits control |
10046 | * whether non-secure software is allowed to change the CPSR_F and CPSR_A | |
10047 | * bits respectively. | |
10048 | * | |
10049 | * In a V8 implementation, it is permitted for privileged software to | |
10050 | * change the CPSR A/F bits regardless of the SCR.AW/FW bits. | |
10051 | */ | |
f8c88bbc | 10052 | if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && |
6e8801f9 FA |
10053 | arm_feature(env, ARM_FEATURE_EL3) && |
10054 | !arm_feature(env, ARM_FEATURE_EL2) && | |
10055 | !arm_is_secure(env)) { | |
10056 | ||
10057 | changed_daif = (env->daif ^ val) & mask; | |
10058 | ||
10059 | if (changed_daif & CPSR_A) { | |
9b37a28c FR |
10060 | /* |
10061 | * Check to see if we are allowed to change the masking of async | |
6e8801f9 FA |
10062 | * abort exceptions from a non-secure state. |
10063 | */ | |
10064 | if (!(env->cp15.scr_el3 & SCR_AW)) { | |
10065 | qemu_log_mask(LOG_GUEST_ERROR, | |
10066 | "Ignoring attempt to switch CPSR_A flag from " | |
10067 | "non-secure world with SCR.AW bit clear\n"); | |
10068 | mask &= ~CPSR_A; | |
10069 | } | |
10070 | } | |
10071 | ||
10072 | if (changed_daif & CPSR_F) { | |
9b37a28c FR |
10073 | /* |
10074 | * Check to see if we are allowed to change the masking of FIQ | |
6e8801f9 FA |
10075 | * exceptions from a non-secure state. |
10076 | */ | |
10077 | if (!(env->cp15.scr_el3 & SCR_FW)) { | |
10078 | qemu_log_mask(LOG_GUEST_ERROR, | |
10079 | "Ignoring attempt to switch CPSR_F flag from " | |
10080 | "non-secure world with SCR.FW bit clear\n"); | |
10081 | mask &= ~CPSR_F; | |
10082 | } | |
10083 | ||
9b37a28c FR |
10084 | /* |
10085 | * Check whether non-maskable FIQ (NMFI) support is enabled. | |
6e8801f9 FA |
10086 | * If this bit is set software is not allowed to mask |
10087 | * FIQs, but is allowed to set CPSR_F to 0. | |
10088 | */ | |
10089 | if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && | |
10090 | (val & CPSR_F)) { | |
10091 | qemu_log_mask(LOG_GUEST_ERROR, | |
10092 | "Ignoring attempt to enable CPSR_F flag " | |
10093 | "(non-maskable FIQ [NMFI] support enabled)\n"); | |
10094 | mask &= ~CPSR_F; | |
10095 | } | |
10096 | } | |
10097 | } | |
10098 | ||
4cc35614 PM |
10099 | env->daif &= ~(CPSR_AIF & mask); |
10100 | env->daif |= val & CPSR_AIF & mask; | |
10101 | ||
f8c88bbc PM |
10102 | if (write_type != CPSRWriteRaw && |
10103 | ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { | |
8c4f0eb9 | 10104 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { |
9b37a28c FR |
10105 | /* |
10106 | * Note that we can only get here in USR mode if this is a | |
8c4f0eb9 PM |
10107 | * gdb stub write; for this case we follow the architectural |
10108 | * behaviour for guest writes in USR mode of ignoring an attempt | |
10109 | * to switch mode. (Those are caught by translate.c for writes | |
10110 | * triggered by guest instructions.) | |
10111 | */ | |
10112 | mask &= ~CPSR_M; | |
10113 | } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { | |
9b37a28c FR |
10114 | /* |
10115 | * Attempt to switch to an invalid mode: this is UNPREDICTABLE in | |
81907a58 PM |
10116 | * v7, and has defined behaviour in v8: |
10117 | * + leave CPSR.M untouched | |
10118 | * + allow changes to the other CPSR fields | |
10119 | * + set PSTATE.IL | |
10120 | * For user changes via the GDB stub, we don't set PSTATE.IL, | |
10121 | * as this would be unnecessarily harsh for a user error. | |
37064a8b PM |
10122 | */ |
10123 | mask &= ~CPSR_M; | |
81907a58 PM |
10124 | if (write_type != CPSRWriteByGDBStub && |
10125 | arm_feature(env, ARM_FEATURE_V8)) { | |
10126 | mask |= CPSR_IL; | |
10127 | val |= CPSR_IL; | |
10128 | } | |
81e37284 PM |
10129 | qemu_log_mask(LOG_GUEST_ERROR, |
10130 | "Illegal AArch32 mode switch attempt from %s to %s\n", | |
10131 | aarch32_mode_name(env->uncached_cpsr), | |
10132 | aarch32_mode_name(val)); | |
37064a8b | 10133 | } else { |
81e37284 PM |
10134 | qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n", |
10135 | write_type == CPSRWriteExceptionReturn ? | |
10136 | "Exception return from AArch32" : | |
10137 | "AArch32 mode switch from", | |
10138 | aarch32_mode_name(env->uncached_cpsr), | |
10139 | aarch32_mode_name(val), env->regs[15]); | |
37064a8b PM |
10140 | switch_mode(env, val & CPSR_M); |
10141 | } | |
2f4a40e5 AZ |
10142 | } |
10143 | mask &= ~CACHED_CPSR_BITS; | |
10144 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
2b77ad4d | 10145 | if (tcg_enabled() && rebuild_hflags) { |
e784807c PM |
10146 | arm_rebuild_hflags(env); |
10147 | } | |
2f4a40e5 AZ |
10148 | } |
10149 | ||
c47eaf9f | 10150 | #ifdef CONFIG_USER_ONLY |
b5ff1b31 | 10151 | |
affdb64d | 10152 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 | 10153 | { |
2fc0cc0e | 10154 | ARMCPU *cpu = env_archcpu(env); |
a47dddd7 AF |
10155 | |
10156 | if (mode != ARM_CPU_MODE_USR) { | |
10157 | cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); | |
10158 | } | |
b5ff1b31 FB |
10159 | } |
10160 | ||
012a906b GB |
10161 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
10162 | uint32_t cur_el, bool secure) | |
9e729b57 EI |
10163 | { |
10164 | return 1; | |
10165 | } | |
10166 | ||
ce02049d GB |
10167 | void aarch64_sync_64_to_32(CPUARMState *env) |
10168 | { | |
10169 | g_assert_not_reached(); | |
10170 | } | |
10171 | ||
b5ff1b31 FB |
10172 | #else |
10173 | ||
affdb64d | 10174 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
10175 | { |
10176 | int old_mode; | |
10177 | int i; | |
10178 | ||
10179 | old_mode = env->uncached_cpsr & CPSR_M; | |
f927dbda | 10180 | if (mode == old_mode) { |
b5ff1b31 | 10181 | return; |
f927dbda | 10182 | } |
b5ff1b31 FB |
10183 | |
10184 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
04215eb1 FR |
10185 | memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); |
10186 | memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); | |
b5ff1b31 | 10187 | } else if (mode == ARM_CPU_MODE_FIQ) { |
04215eb1 FR |
10188 | memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); |
10189 | memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); | |
b5ff1b31 FB |
10190 | } |
10191 | ||
f5206413 | 10192 | i = bank_number(old_mode); |
b5ff1b31 | 10193 | env->banked_r13[i] = env->regs[13]; |
b5ff1b31 FB |
10194 | env->banked_spsr[i] = env->spsr; |
10195 | ||
f5206413 | 10196 | i = bank_number(mode); |
b5ff1b31 | 10197 | env->regs[13] = env->banked_r13[i]; |
b5ff1b31 | 10198 | env->spsr = env->banked_spsr[i]; |
593cfa2b PM |
10199 | |
10200 | env->banked_r14[r14_bank_number(old_mode)] = env->regs[14]; | |
10201 | env->regs[14] = env->banked_r14[r14_bank_number(mode)]; | |
b5ff1b31 FB |
10202 | } |
10203 | ||
9b37a28c FR |
10204 | /* |
10205 | * Physical Interrupt Target EL Lookup Table | |
0eeb17d6 GB |
10206 | * |
10207 | * [ From ARM ARM section G1.13.4 (Table G1-15) ] | |
10208 | * | |
10209 | * The below multi-dimensional table is used for looking up the target | |
10210 | * exception level given numerous condition criteria. Specifically, the | |
10211 | * target EL is based on SCR and HCR routing controls as well as the | |
10212 | * currently executing EL and secure state. | |
10213 | * | |
10214 | * Dimensions: | |
10215 | * target_el_table[2][2][2][2][2][4] | |
10216 | * | | | | | +--- Current EL | |
10217 | * | | | | +------ Non-secure(0)/Secure(1) | |
10218 | * | | | +--------- HCR mask override | |
10219 | * | | +------------ SCR exec state control | |
10220 | * | +--------------- SCR mask override | |
10221 | * +------------------ 32-bit(0)/64-bit(1) EL3 | |
10222 | * | |
10223 | * The table values are as such: | |
10224 | * 0-3 = EL0-EL3 | |
10225 | * -1 = Cannot occur | |
10226 | * | |
10227 | * The ARM ARM target EL table includes entries indicating that an "exception | |
10228 | * is not taken". The two cases where this is applicable are: | |
10229 | * 1) An exception is taken from EL3 but the SCR does not have the exception | |
10230 | * routed to EL3. | |
10231 | * 2) An exception is taken from EL2 but the HCR does not have the exception | |
10232 | * routed to EL2. | |
10233 | * In these two cases, the below table contain a target of EL1. This value is | |
10234 | * returned as it is expected that the consumer of the table data will check | |
10235 | * for "target EL >= current EL" to ensure the exception is not taken. | |
10236 | * | |
10237 | * SCR HCR | |
10238 | * 64 EA AMO From | |
10239 | * BIT IRQ IMO Non-secure Secure | |
10240 | * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 | |
10241 | */ | |
82c39f6a | 10242 | static const int8_t target_el_table[2][2][2][2][2][4] = { |
0eeb17d6 GB |
10243 | {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, |
10244 | {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, | |
10245 | {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, | |
10246 | {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, | |
10247 | {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
10248 | {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, | |
10249 | {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
10250 | {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, | |
10251 | {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, | |
6c85f906 RDC |
10252 | {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},}, |
10253 | {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },}, | |
10254 | {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},}, | |
0eeb17d6 GB |
10255 | {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, |
10256 | {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, | |
6c85f906 RDC |
10257 | {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },}, |
10258 | {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},}, | |
0eeb17d6 GB |
10259 | }; |
10260 | ||
10261 | /* | |
10262 | * Determine the target EL for physical exceptions | |
10263 | */ | |
012a906b GB |
10264 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
10265 | uint32_t cur_el, bool secure) | |
0eeb17d6 | 10266 | { |
b77af26e | 10267 | CPUARMState *env = cpu_env(cs); |
f7778444 RH |
10268 | bool rw; |
10269 | bool scr; | |
10270 | bool hcr; | |
0eeb17d6 | 10271 | int target_el; |
2cde031f | 10272 | /* Is the highest EL AArch64? */ |
f7778444 RH |
10273 | bool is64 = arm_feature(env, ARM_FEATURE_AARCH64); |
10274 | uint64_t hcr_el2; | |
2cde031f SS |
10275 | |
10276 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
10277 | rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); | |
10278 | } else { | |
9b37a28c FR |
10279 | /* |
10280 | * Either EL2 is the highest EL (and so the EL2 register width | |
2cde031f SS |
10281 | * is given by is64); or there is no EL2 or EL3, in which case |
10282 | * the value of 'rw' does not affect the table lookup anyway. | |
10283 | */ | |
10284 | rw = is64; | |
10285 | } | |
0eeb17d6 | 10286 | |
f7778444 | 10287 | hcr_el2 = arm_hcr_el2_eff(env); |
0eeb17d6 GB |
10288 | switch (excp_idx) { |
10289 | case EXCP_IRQ: | |
10290 | scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); | |
f7778444 | 10291 | hcr = hcr_el2 & HCR_IMO; |
0eeb17d6 GB |
10292 | break; |
10293 | case EXCP_FIQ: | |
10294 | scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); | |
f7778444 | 10295 | hcr = hcr_el2 & HCR_FMO; |
0eeb17d6 GB |
10296 | break; |
10297 | default: | |
10298 | scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); | |
f7778444 | 10299 | hcr = hcr_el2 & HCR_AMO; |
0eeb17d6 GB |
10300 | break; |
10301 | }; | |
10302 | ||
d1b31428 RH |
10303 | /* |
10304 | * For these purposes, TGE and AMO/IMO/FMO both force the | |
10305 | * interrupt to EL2. Fold TGE into the bit extracted above. | |
10306 | */ | |
10307 | hcr |= (hcr_el2 & HCR_TGE) != 0; | |
10308 | ||
0eeb17d6 GB |
10309 | /* Perform a table-lookup for the target EL given the current state */ |
10310 | target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; | |
10311 | ||
10312 | assert(target_el > 0); | |
10313 | ||
10314 | return target_el; | |
10315 | } | |
10316 | ||
fc6177af | 10317 | void arm_log_exception(CPUState *cs) |
b59f479b | 10318 | { |
fc6177af PM |
10319 | int idx = cs->exception_index; |
10320 | ||
b59f479b PMD |
10321 | if (qemu_loglevel_mask(CPU_LOG_INT)) { |
10322 | const char *exc = NULL; | |
10323 | static const char * const excnames[] = { | |
10324 | [EXCP_UDEF] = "Undefined Instruction", | |
10325 | [EXCP_SWI] = "SVC", | |
10326 | [EXCP_PREFETCH_ABORT] = "Prefetch Abort", | |
10327 | [EXCP_DATA_ABORT] = "Data Abort", | |
10328 | [EXCP_IRQ] = "IRQ", | |
10329 | [EXCP_FIQ] = "FIQ", | |
10330 | [EXCP_BKPT] = "Breakpoint", | |
10331 | [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", | |
10332 | [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", | |
10333 | [EXCP_HVC] = "Hypervisor Call", | |
10334 | [EXCP_HYP_TRAP] = "Hypervisor Trap", | |
10335 | [EXCP_SMC] = "Secure Monitor Call", | |
10336 | [EXCP_VIRQ] = "Virtual IRQ", | |
10337 | [EXCP_VFIQ] = "Virtual FIQ", | |
10338 | [EXCP_SEMIHOST] = "Semihosting call", | |
10339 | [EXCP_NOCP] = "v7M NOCP UsageFault", | |
10340 | [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", | |
10341 | [EXCP_STKOF] = "v8M STKOF UsageFault", | |
10342 | [EXCP_LAZYFP] = "v7M exception during lazy FP stacking", | |
10343 | [EXCP_LSERR] = "v8M LSERR UsageFault", | |
10344 | [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", | |
e5346292 | 10345 | [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault", |
3c29632f | 10346 | [EXCP_VSERR] = "Virtual SERR", |
11b76fda | 10347 | [EXCP_GPC] = "Granule Protection Check", |
b59f479b PMD |
10348 | }; |
10349 | ||
10350 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | |
10351 | exc = excnames[idx]; | |
10352 | } | |
10353 | if (!exc) { | |
10354 | exc = "unknown"; | |
10355 | } | |
fc6177af PM |
10356 | qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s] on CPU %d\n", |
10357 | idx, exc, cs->cpu_index); | |
b59f479b PMD |
10358 | } |
10359 | } | |
10360 | ||
a356dacf | 10361 | /* |
7aab5a8c PMD |
10362 | * Function used to synchronize QEMU's AArch64 register set with AArch32 |
10363 | * register set. This is necessary when switching between AArch32 and AArch64 | |
10364 | * execution state. | |
a356dacf | 10365 | */ |
7aab5a8c | 10366 | void aarch64_sync_32_to_64(CPUARMState *env) |
9ee6e8bb | 10367 | { |
7aab5a8c PMD |
10368 | int i; |
10369 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
10370 | ||
10371 | /* We can blanket copy R[0:7] to X[0:7] */ | |
10372 | for (i = 0; i < 8; i++) { | |
10373 | env->xregs[i] = env->regs[i]; | |
fd592d89 | 10374 | } |
70d74660 | 10375 | |
9a223097 | 10376 | /* |
7aab5a8c PMD |
10377 | * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. |
10378 | * Otherwise, they come from the banked user regs. | |
fd592d89 | 10379 | */ |
7aab5a8c PMD |
10380 | if (mode == ARM_CPU_MODE_FIQ) { |
10381 | for (i = 8; i < 13; i++) { | |
10382 | env->xregs[i] = env->usr_regs[i - 8]; | |
10383 | } | |
10384 | } else { | |
10385 | for (i = 8; i < 13; i++) { | |
10386 | env->xregs[i] = env->regs[i]; | |
10387 | } | |
fd592d89 | 10388 | } |
9ee6e8bb | 10389 | |
7aab5a8c PMD |
10390 | /* |
10391 | * Registers x13-x23 are the various mode SP and FP registers. Registers | |
10392 | * r13 and r14 are only copied if we are in that mode, otherwise we copy | |
10393 | * from the mode banked register. | |
10394 | */ | |
10395 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { | |
10396 | env->xregs[13] = env->regs[13]; | |
10397 | env->xregs[14] = env->regs[14]; | |
10398 | } else { | |
10399 | env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; | |
10400 | /* HYP is an exception in that it is copied from r14 */ | |
10401 | if (mode == ARM_CPU_MODE_HYP) { | |
10402 | env->xregs[14] = env->regs[14]; | |
95695eff | 10403 | } else { |
7aab5a8c | 10404 | env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)]; |
95695eff | 10405 | } |
95695eff PM |
10406 | } |
10407 | ||
7aab5a8c PMD |
10408 | if (mode == ARM_CPU_MODE_HYP) { |
10409 | env->xregs[15] = env->regs[13]; | |
10410 | } else { | |
10411 | env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; | |
95695eff PM |
10412 | } |
10413 | ||
7aab5a8c PMD |
10414 | if (mode == ARM_CPU_MODE_IRQ) { |
10415 | env->xregs[16] = env->regs[14]; | |
10416 | env->xregs[17] = env->regs[13]; | |
10417 | } else { | |
10418 | env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)]; | |
10419 | env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; | |
10420 | } | |
95695eff | 10421 | |
7aab5a8c PMD |
10422 | if (mode == ARM_CPU_MODE_SVC) { |
10423 | env->xregs[18] = env->regs[14]; | |
10424 | env->xregs[19] = env->regs[13]; | |
10425 | } else { | |
10426 | env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)]; | |
10427 | env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; | |
10428 | } | |
95695eff | 10429 | |
7aab5a8c PMD |
10430 | if (mode == ARM_CPU_MODE_ABT) { |
10431 | env->xregs[20] = env->regs[14]; | |
10432 | env->xregs[21] = env->regs[13]; | |
10433 | } else { | |
10434 | env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)]; | |
10435 | env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; | |
10436 | } | |
e33cf0f8 | 10437 | |
7aab5a8c PMD |
10438 | if (mode == ARM_CPU_MODE_UND) { |
10439 | env->xregs[22] = env->regs[14]; | |
10440 | env->xregs[23] = env->regs[13]; | |
10441 | } else { | |
10442 | env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)]; | |
10443 | env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; | |
e33cf0f8 PM |
10444 | } |
10445 | ||
10446 | /* | |
7aab5a8c PMD |
10447 | * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ |
10448 | * mode, then we can copy from r8-r14. Otherwise, we copy from the | |
10449 | * FIQ bank for r8-r14. | |
e33cf0f8 | 10450 | */ |
7aab5a8c PMD |
10451 | if (mode == ARM_CPU_MODE_FIQ) { |
10452 | for (i = 24; i < 31; i++) { | |
10453 | env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ | |
10454 | } | |
10455 | } else { | |
10456 | for (i = 24; i < 29; i++) { | |
10457 | env->xregs[i] = env->fiq_regs[i - 24]; | |
e33cf0f8 | 10458 | } |
7aab5a8c PMD |
10459 | env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; |
10460 | env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)]; | |
e33cf0f8 | 10461 | } |
7aab5a8c PMD |
10462 | |
10463 | env->pc = env->regs[15]; | |
e33cf0f8 PM |
10464 | } |
10465 | ||
9a223097 | 10466 | /* |
7aab5a8c PMD |
10467 | * Function used to synchronize QEMU's AArch32 register set with AArch64 |
10468 | * register set. This is necessary when switching between AArch32 and AArch64 | |
10469 | * execution state. | |
de2db7ec | 10470 | */ |
7aab5a8c | 10471 | void aarch64_sync_64_to_32(CPUARMState *env) |
9ee6e8bb | 10472 | { |
7aab5a8c PMD |
10473 | int i; |
10474 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
abc24d86 | 10475 | |
7aab5a8c PMD |
10476 | /* We can blanket copy X[0:7] to R[0:7] */ |
10477 | for (i = 0; i < 8; i++) { | |
10478 | env->regs[i] = env->xregs[i]; | |
de2db7ec | 10479 | } |
3f0cddee | 10480 | |
9a223097 | 10481 | /* |
7aab5a8c PMD |
10482 | * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. |
10483 | * Otherwise, we copy x8-x12 into the banked user regs. | |
de2db7ec | 10484 | */ |
7aab5a8c PMD |
10485 | if (mode == ARM_CPU_MODE_FIQ) { |
10486 | for (i = 8; i < 13; i++) { | |
10487 | env->usr_regs[i - 8] = env->xregs[i]; | |
10488 | } | |
10489 | } else { | |
10490 | for (i = 8; i < 13; i++) { | |
10491 | env->regs[i] = env->xregs[i]; | |
10492 | } | |
fb602cb7 PM |
10493 | } |
10494 | ||
9a223097 | 10495 | /* |
7aab5a8c PMD |
10496 | * Registers r13 & r14 depend on the current mode. |
10497 | * If we are in a given mode, we copy the corresponding x registers to r13 | |
10498 | * and r14. Otherwise, we copy the x register to the banked r13 and r14 | |
10499 | * for the mode. | |
fb602cb7 | 10500 | */ |
7aab5a8c PMD |
10501 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { |
10502 | env->regs[13] = env->xregs[13]; | |
10503 | env->regs[14] = env->xregs[14]; | |
fb602cb7 | 10504 | } else { |
7aab5a8c | 10505 | env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; |
fb602cb7 | 10506 | |
7aab5a8c PMD |
10507 | /* |
10508 | * HYP is an exception in that it does not have its own banked r14 but | |
10509 | * shares the USR r14 | |
10510 | */ | |
10511 | if (mode == ARM_CPU_MODE_HYP) { | |
10512 | env->regs[14] = env->xregs[14]; | |
10513 | } else { | |
10514 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; | |
10515 | } | |
10516 | } | |
fb602cb7 | 10517 | |
7aab5a8c PMD |
10518 | if (mode == ARM_CPU_MODE_HYP) { |
10519 | env->regs[13] = env->xregs[15]; | |
fb602cb7 | 10520 | } else { |
7aab5a8c | 10521 | env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; |
fb602cb7 | 10522 | } |
d02a8698 | 10523 | |
7aab5a8c PMD |
10524 | if (mode == ARM_CPU_MODE_IRQ) { |
10525 | env->regs[14] = env->xregs[16]; | |
10526 | env->regs[13] = env->xregs[17]; | |
d02a8698 | 10527 | } else { |
7aab5a8c PMD |
10528 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; |
10529 | env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; | |
d02a8698 PM |
10530 | } |
10531 | ||
7aab5a8c PMD |
10532 | if (mode == ARM_CPU_MODE_SVC) { |
10533 | env->regs[14] = env->xregs[18]; | |
10534 | env->regs[13] = env->xregs[19]; | |
10535 | } else { | |
10536 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; | |
10537 | env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; | |
fb602cb7 PM |
10538 | } |
10539 | ||
7aab5a8c PMD |
10540 | if (mode == ARM_CPU_MODE_ABT) { |
10541 | env->regs[14] = env->xregs[20]; | |
10542 | env->regs[13] = env->xregs[21]; | |
10543 | } else { | |
10544 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; | |
10545 | env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; | |
ce02049d GB |
10546 | } |
10547 | ||
10548 | if (mode == ARM_CPU_MODE_UND) { | |
3a9148d0 SS |
10549 | env->regs[14] = env->xregs[22]; |
10550 | env->regs[13] = env->xregs[23]; | |
ce02049d | 10551 | } else { |
593cfa2b | 10552 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; |
3a9148d0 | 10553 | env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; |
ce02049d GB |
10554 | } |
10555 | ||
9b37a28c FR |
10556 | /* |
10557 | * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ | |
ce02049d GB |
10558 | * mode, then we can copy to r8-r14. Otherwise, we copy to the |
10559 | * FIQ bank for r8-r14. | |
10560 | */ | |
10561 | if (mode == ARM_CPU_MODE_FIQ) { | |
10562 | for (i = 24; i < 31; i++) { | |
10563 | env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ | |
10564 | } | |
10565 | } else { | |
10566 | for (i = 24; i < 29; i++) { | |
10567 | env->fiq_regs[i - 24] = env->xregs[i]; | |
10568 | } | |
10569 | env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; | |
593cfa2b | 10570 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; |
ce02049d GB |
10571 | } |
10572 | ||
10573 | env->regs[15] = env->pc; | |
10574 | } | |
10575 | ||
dea8378b PM |
10576 | static void take_aarch32_exception(CPUARMState *env, int new_mode, |
10577 | uint32_t mask, uint32_t offset, | |
10578 | uint32_t newpc) | |
10579 | { | |
4a2696c0 RH |
10580 | int new_el; |
10581 | ||
dea8378b PM |
10582 | /* Change the CPU state so as to actually take the exception. */ |
10583 | switch_mode(env, new_mode); | |
4a2696c0 | 10584 | |
dea8378b PM |
10585 | /* |
10586 | * For exceptions taken to AArch32 we must clear the SS bit in both | |
10587 | * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. | |
10588 | */ | |
f944a854 | 10589 | env->pstate &= ~PSTATE_SS; |
dea8378b PM |
10590 | env->spsr = cpsr_read(env); |
10591 | /* Clear IT bits. */ | |
10592 | env->condexec_bits = 0; | |
10593 | /* Switch to the new mode, and to the correct instruction set. */ | |
10594 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; | |
88828bf1 CD |
10595 | |
10596 | /* This must be after mode switching. */ | |
10597 | new_el = arm_current_el(env); | |
10598 | ||
dea8378b PM |
10599 | /* Set new mode endianness */ |
10600 | env->uncached_cpsr &= ~CPSR_E; | |
4a2696c0 | 10601 | if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { |
dea8378b PM |
10602 | env->uncached_cpsr |= CPSR_E; |
10603 | } | |
829f9fd3 PM |
10604 | /* J and IL must always be cleared for exception entry */ |
10605 | env->uncached_cpsr &= ~(CPSR_IL | CPSR_J); | |
dea8378b PM |
10606 | env->daif |= mask; |
10607 | ||
f2f68a78 RC |
10608 | if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) { |
10609 | if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) { | |
10610 | env->uncached_cpsr |= CPSR_SSBS; | |
10611 | } else { | |
10612 | env->uncached_cpsr &= ~CPSR_SSBS; | |
10613 | } | |
10614 | } | |
10615 | ||
dea8378b PM |
10616 | if (new_mode == ARM_CPU_MODE_HYP) { |
10617 | env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0; | |
10618 | env->elr_el[2] = env->regs[15]; | |
10619 | } else { | |
4a2696c0 | 10620 | /* CPSR.PAN is normally preserved preserved unless... */ |
f8af1143 | 10621 | if (cpu_isar_feature(aa32_pan, env_archcpu(env))) { |
4a2696c0 RH |
10622 | switch (new_el) { |
10623 | case 3: | |
10624 | if (!arm_is_secure_below_el3(env)) { | |
10625 | /* ... the target is EL3, from non-secure state. */ | |
10626 | env->uncached_cpsr &= ~CPSR_PAN; | |
10627 | break; | |
10628 | } | |
10629 | /* ... the target is EL3, from secure state ... */ | |
10630 | /* fall through */ | |
10631 | case 1: | |
10632 | /* ... the target is EL1 and SCTLR.SPAN is 0. */ | |
10633 | if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { | |
10634 | env->uncached_cpsr |= CPSR_PAN; | |
10635 | } | |
10636 | break; | |
10637 | } | |
10638 | } | |
dea8378b PM |
10639 | /* |
10640 | * this is a lie, as there was no c1_sys on V4T/V5, but who cares | |
10641 | * and we should just guard the thumb mode on V4 | |
10642 | */ | |
10643 | if (arm_feature(env, ARM_FEATURE_V4T)) { | |
10644 | env->thumb = | |
10645 | (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; | |
10646 | } | |
10647 | env->regs[14] = env->regs[15] + offset; | |
10648 | } | |
10649 | env->regs[15] = newpc; | |
2b77ad4d FR |
10650 | |
10651 | if (tcg_enabled()) { | |
10652 | arm_rebuild_hflags(env); | |
10653 | } | |
dea8378b PM |
10654 | } |
10655 | ||
b9bc21ff PM |
10656 | static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) |
10657 | { | |
10658 | /* | |
10659 | * Handle exception entry to Hyp mode; this is sufficiently | |
10660 | * different to entry to other AArch32 modes that we handle it | |
10661 | * separately here. | |
10662 | * | |
10663 | * The vector table entry used is always the 0x14 Hyp mode entry point, | |
2c023d36 | 10664 | * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp. |
b9bc21ff PM |
10665 | * The offset applied to the preferred return address is always zero |
10666 | * (see DDI0487C.a section G1.12.3). | |
10667 | * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. | |
10668 | */ | |
10669 | uint32_t addr, mask; | |
10670 | ARMCPU *cpu = ARM_CPU(cs); | |
10671 | CPUARMState *env = &cpu->env; | |
10672 | ||
10673 | switch (cs->exception_index) { | |
10674 | case EXCP_UDEF: | |
10675 | addr = 0x04; | |
10676 | break; | |
10677 | case EXCP_SWI: | |
2c023d36 | 10678 | addr = 0x08; |
b9bc21ff PM |
10679 | break; |
10680 | case EXCP_BKPT: | |
10681 | /* Fall through to prefetch abort. */ | |
10682 | case EXCP_PREFETCH_ABORT: | |
10683 | env->cp15.ifar_s = env->exception.vaddress; | |
10684 | qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n", | |
10685 | (uint32_t)env->exception.vaddress); | |
10686 | addr = 0x0c; | |
10687 | break; | |
10688 | case EXCP_DATA_ABORT: | |
10689 | env->cp15.dfar_s = env->exception.vaddress; | |
10690 | qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n", | |
10691 | (uint32_t)env->exception.vaddress); | |
10692 | addr = 0x10; | |
10693 | break; | |
10694 | case EXCP_IRQ: | |
10695 | addr = 0x18; | |
10696 | break; | |
10697 | case EXCP_FIQ: | |
10698 | addr = 0x1c; | |
10699 | break; | |
10700 | case EXCP_HVC: | |
10701 | addr = 0x08; | |
10702 | break; | |
10703 | case EXCP_HYP_TRAP: | |
10704 | addr = 0x14; | |
9bbb4ef9 | 10705 | break; |
b9bc21ff PM |
10706 | default: |
10707 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
10708 | } | |
10709 | ||
10710 | if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) { | |
2ed08180 PM |
10711 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
10712 | /* | |
10713 | * QEMU syndrome values are v8-style. v7 has the IL bit | |
10714 | * UNK/SBZP for "field not valid" cases, where v8 uses RES1. | |
10715 | * If this is a v7 CPU, squash the IL bit in those cases. | |
10716 | */ | |
10717 | if (cs->exception_index == EXCP_PREFETCH_ABORT || | |
10718 | (cs->exception_index == EXCP_DATA_ABORT && | |
10719 | !(env->exception.syndrome & ARM_EL_ISV)) || | |
10720 | syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) { | |
10721 | env->exception.syndrome &= ~ARM_EL_IL; | |
10722 | } | |
10723 | } | |
b9bc21ff PM |
10724 | env->cp15.esr_el[2] = env->exception.syndrome; |
10725 | } | |
10726 | ||
10727 | if (arm_current_el(env) != 2 && addr < 0x14) { | |
10728 | addr = 0x14; | |
10729 | } | |
10730 | ||
10731 | mask = 0; | |
10732 | if (!(env->cp15.scr_el3 & SCR_EA)) { | |
10733 | mask |= CPSR_A; | |
10734 | } | |
10735 | if (!(env->cp15.scr_el3 & SCR_IRQ)) { | |
10736 | mask |= CPSR_I; | |
10737 | } | |
10738 | if (!(env->cp15.scr_el3 & SCR_FIQ)) { | |
10739 | mask |= CPSR_F; | |
10740 | } | |
10741 | ||
10742 | addr += env->cp15.hvbar; | |
10743 | ||
10744 | take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr); | |
10745 | } | |
10746 | ||
966f758c | 10747 | static void arm_cpu_do_interrupt_aarch32(CPUState *cs) |
b5ff1b31 | 10748 | { |
97a8ea5a AF |
10749 | ARMCPU *cpu = ARM_CPU(cs); |
10750 | CPUARMState *env = &cpu->env; | |
b5ff1b31 FB |
10751 | uint32_t addr; |
10752 | uint32_t mask; | |
10753 | int new_mode; | |
10754 | uint32_t offset; | |
16a906fd | 10755 | uint32_t moe; |
b5ff1b31 | 10756 | |
16a906fd | 10757 | /* If this is a debug exception we must update the DBGDSCR.MOE bits */ |
64b91e3f | 10758 | switch (syn_get_ec(env->exception.syndrome)) { |
16a906fd PM |
10759 | case EC_BREAKPOINT: |
10760 | case EC_BREAKPOINT_SAME_EL: | |
10761 | moe = 1; | |
10762 | break; | |
10763 | case EC_WATCHPOINT: | |
10764 | case EC_WATCHPOINT_SAME_EL: | |
10765 | moe = 10; | |
10766 | break; | |
10767 | case EC_AA32_BKPT: | |
10768 | moe = 3; | |
10769 | break; | |
10770 | case EC_VECTORCATCH: | |
10771 | moe = 5; | |
10772 | break; | |
10773 | default: | |
10774 | moe = 0; | |
10775 | break; | |
10776 | } | |
10777 | ||
10778 | if (moe) { | |
10779 | env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); | |
10780 | } | |
10781 | ||
b9bc21ff PM |
10782 | if (env->exception.target_el == 2) { |
10783 | arm_cpu_do_interrupt_aarch32_hyp(cs); | |
10784 | return; | |
10785 | } | |
10786 | ||
27103424 | 10787 | switch (cs->exception_index) { |
b5ff1b31 FB |
10788 | case EXCP_UDEF: |
10789 | new_mode = ARM_CPU_MODE_UND; | |
10790 | addr = 0x04; | |
10791 | mask = CPSR_I; | |
f927dbda | 10792 | if (env->thumb) { |
b5ff1b31 | 10793 | offset = 2; |
f927dbda | 10794 | } else { |
b5ff1b31 | 10795 | offset = 4; |
f927dbda | 10796 | } |
b5ff1b31 FB |
10797 | break; |
10798 | case EXCP_SWI: | |
10799 | new_mode = ARM_CPU_MODE_SVC; | |
10800 | addr = 0x08; | |
10801 | mask = CPSR_I; | |
601d70b9 | 10802 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
10803 | offset = 0; |
10804 | break; | |
06c949e6 | 10805 | case EXCP_BKPT: |
9ee6e8bb PB |
10806 | /* Fall through to prefetch abort. */ |
10807 | case EXCP_PREFETCH_ABORT: | |
88ca1c2d | 10808 | A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); |
b848ce2b | 10809 | A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); |
3f1beaca | 10810 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", |
88ca1c2d | 10811 | env->exception.fsr, (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
10812 | new_mode = ARM_CPU_MODE_ABT; |
10813 | addr = 0x0c; | |
10814 | mask = CPSR_A | CPSR_I; | |
10815 | offset = 4; | |
10816 | break; | |
10817 | case EXCP_DATA_ABORT: | |
4a7e2d73 | 10818 | A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); |
b848ce2b | 10819 | A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); |
3f1beaca | 10820 | qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", |
4a7e2d73 | 10821 | env->exception.fsr, |
6cd8a264 | 10822 | (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
10823 | new_mode = ARM_CPU_MODE_ABT; |
10824 | addr = 0x10; | |
10825 | mask = CPSR_A | CPSR_I; | |
10826 | offset = 8; | |
10827 | break; | |
10828 | case EXCP_IRQ: | |
10829 | new_mode = ARM_CPU_MODE_IRQ; | |
10830 | addr = 0x18; | |
10831 | /* Disable IRQ and imprecise data aborts. */ | |
10832 | mask = CPSR_A | CPSR_I; | |
10833 | offset = 4; | |
de38d23b FA |
10834 | if (env->cp15.scr_el3 & SCR_IRQ) { |
10835 | /* IRQ routed to monitor mode */ | |
10836 | new_mode = ARM_CPU_MODE_MON; | |
10837 | mask |= CPSR_F; | |
10838 | } | |
b5ff1b31 FB |
10839 | break; |
10840 | case EXCP_FIQ: | |
10841 | new_mode = ARM_CPU_MODE_FIQ; | |
10842 | addr = 0x1c; | |
10843 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
10844 | mask = CPSR_A | CPSR_I | CPSR_F; | |
de38d23b FA |
10845 | if (env->cp15.scr_el3 & SCR_FIQ) { |
10846 | /* FIQ routed to monitor mode */ | |
10847 | new_mode = ARM_CPU_MODE_MON; | |
10848 | } | |
b5ff1b31 FB |
10849 | offset = 4; |
10850 | break; | |
87a4b270 PM |
10851 | case EXCP_VIRQ: |
10852 | new_mode = ARM_CPU_MODE_IRQ; | |
10853 | addr = 0x18; | |
10854 | /* Disable IRQ and imprecise data aborts. */ | |
10855 | mask = CPSR_A | CPSR_I; | |
10856 | offset = 4; | |
10857 | break; | |
10858 | case EXCP_VFIQ: | |
10859 | new_mode = ARM_CPU_MODE_FIQ; | |
10860 | addr = 0x1c; | |
10861 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
10862 | mask = CPSR_A | CPSR_I | CPSR_F; | |
10863 | offset = 4; | |
10864 | break; | |
3c29632f RH |
10865 | case EXCP_VSERR: |
10866 | { | |
10867 | /* | |
10868 | * Note that this is reported as a data abort, but the DFAR | |
10869 | * has an UNKNOWN value. Construct the SError syndrome from | |
10870 | * AET and ExT fields. | |
10871 | */ | |
10872 | ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, }; | |
10873 | ||
10874 | if (extended_addresses_enabled(env)) { | |
10875 | env->exception.fsr = arm_fi_to_lfsc(&fi); | |
10876 | } else { | |
10877 | env->exception.fsr = arm_fi_to_sfsc(&fi); | |
10878 | } | |
10879 | env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000; | |
10880 | A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); | |
10881 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n", | |
10882 | env->exception.fsr); | |
10883 | ||
10884 | new_mode = ARM_CPU_MODE_ABT; | |
10885 | addr = 0x10; | |
10886 | mask = CPSR_A | CPSR_I; | |
10887 | offset = 8; | |
10888 | } | |
10889 | break; | |
dbe9d163 FA |
10890 | case EXCP_SMC: |
10891 | new_mode = ARM_CPU_MODE_MON; | |
10892 | addr = 0x08; | |
10893 | mask = CPSR_A | CPSR_I | CPSR_F; | |
10894 | offset = 0; | |
10895 | break; | |
b5ff1b31 | 10896 | default: |
a47dddd7 | 10897 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
b5ff1b31 FB |
10898 | return; /* Never happens. Keep compiler happy. */ |
10899 | } | |
e89e51a1 FA |
10900 | |
10901 | if (new_mode == ARM_CPU_MODE_MON) { | |
10902 | addr += env->cp15.mvbar; | |
137feaa9 | 10903 | } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { |
e89e51a1 | 10904 | /* High vectors. When enabled, base address cannot be remapped. */ |
b5ff1b31 | 10905 | addr += 0xffff0000; |
8641136c | 10906 | } else { |
9b37a28c FR |
10907 | /* |
10908 | * ARM v7 architectures provide a vector base address register to remap | |
8641136c | 10909 | * the interrupt vector table. |
e89e51a1 | 10910 | * This register is only followed in non-monitor mode, and is banked. |
8641136c NR |
10911 | * Note: only bits 31:5 are valid. |
10912 | */ | |
fb6c91ba | 10913 | addr += A32_BANKED_CURRENT_REG_GET(env, vbar); |
b5ff1b31 | 10914 | } |
dbe9d163 FA |
10915 | |
10916 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
10917 | env->cp15.scr_el3 &= ~SCR_NS; | |
10918 | } | |
10919 | ||
dea8378b | 10920 | take_aarch32_exception(env, new_mode, mask, offset, addr); |
b5ff1b31 FB |
10921 | } |
10922 | ||
a65dabf7 PM |
10923 | static int aarch64_regnum(CPUARMState *env, int aarch32_reg) |
10924 | { | |
10925 | /* | |
10926 | * Return the register number of the AArch64 view of the AArch32 | |
10927 | * register @aarch32_reg. The CPUARMState CPSR is assumed to still | |
10928 | * be that of the AArch32 mode the exception came from. | |
10929 | */ | |
10930 | int mode = env->uncached_cpsr & CPSR_M; | |
10931 | ||
10932 | switch (aarch32_reg) { | |
10933 | case 0 ... 7: | |
10934 | return aarch32_reg; | |
10935 | case 8 ... 12: | |
10936 | return mode == ARM_CPU_MODE_FIQ ? aarch32_reg + 16 : aarch32_reg; | |
10937 | case 13: | |
10938 | switch (mode) { | |
10939 | case ARM_CPU_MODE_USR: | |
10940 | case ARM_CPU_MODE_SYS: | |
10941 | return 13; | |
10942 | case ARM_CPU_MODE_HYP: | |
10943 | return 15; | |
10944 | case ARM_CPU_MODE_IRQ: | |
10945 | return 17; | |
10946 | case ARM_CPU_MODE_SVC: | |
10947 | return 19; | |
10948 | case ARM_CPU_MODE_ABT: | |
10949 | return 21; | |
10950 | case ARM_CPU_MODE_UND: | |
10951 | return 23; | |
10952 | case ARM_CPU_MODE_FIQ: | |
10953 | return 29; | |
10954 | default: | |
10955 | g_assert_not_reached(); | |
10956 | } | |
10957 | case 14: | |
10958 | switch (mode) { | |
10959 | case ARM_CPU_MODE_USR: | |
10960 | case ARM_CPU_MODE_SYS: | |
10961 | case ARM_CPU_MODE_HYP: | |
10962 | return 14; | |
10963 | case ARM_CPU_MODE_IRQ: | |
10964 | return 16; | |
10965 | case ARM_CPU_MODE_SVC: | |
10966 | return 18; | |
10967 | case ARM_CPU_MODE_ABT: | |
10968 | return 20; | |
10969 | case ARM_CPU_MODE_UND: | |
10970 | return 22; | |
10971 | case ARM_CPU_MODE_FIQ: | |
10972 | return 30; | |
10973 | default: | |
10974 | g_assert_not_reached(); | |
10975 | } | |
10976 | case 15: | |
10977 | return 31; | |
10978 | default: | |
10979 | g_assert_not_reached(); | |
10980 | } | |
10981 | } | |
10982 | ||
f944a854 RC |
10983 | static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env) |
10984 | { | |
10985 | uint32_t ret = cpsr_read(env); | |
10986 | ||
10987 | /* Move DIT to the correct location for SPSR_ELx */ | |
10988 | if (ret & CPSR_DIT) { | |
10989 | ret &= ~CPSR_DIT; | |
10990 | ret |= PSTATE_DIT; | |
10991 | } | |
10992 | /* Merge PSTATE.SS into SPSR_ELx */ | |
10993 | ret |= env->pstate & PSTATE_SS; | |
10994 | ||
10995 | return ret; | |
10996 | } | |
10997 | ||
7ac61020 PM |
10998 | static bool syndrome_is_sync_extabt(uint32_t syndrome) |
10999 | { | |
11000 | /* Return true if this syndrome value is a synchronous external abort */ | |
11001 | switch (syn_get_ec(syndrome)) { | |
11002 | case EC_INSNABORT: | |
11003 | case EC_INSNABORT_SAME_EL: | |
11004 | case EC_DATAABORT: | |
11005 | case EC_DATAABORT_SAME_EL: | |
11006 | /* Look at fault status code for all the synchronous ext abort cases */ | |
11007 | switch (syndrome & 0x3f) { | |
11008 | case 0x10: | |
11009 | case 0x13: | |
11010 | case 0x14: | |
11011 | case 0x15: | |
11012 | case 0x16: | |
11013 | case 0x17: | |
11014 | return true; | |
11015 | default: | |
11016 | return false; | |
11017 | } | |
11018 | default: | |
11019 | return false; | |
11020 | } | |
11021 | } | |
11022 | ||
966f758c PM |
11023 | /* Handle exception entry to a target EL which is using AArch64 */ |
11024 | static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | |
f3a9b694 PM |
11025 | { |
11026 | ARMCPU *cpu = ARM_CPU(cs); | |
11027 | CPUARMState *env = &cpu->env; | |
11028 | unsigned int new_el = env->exception.target_el; | |
11029 | target_ulong addr = env->cp15.vbar_el[new_el]; | |
11030 | unsigned int new_mode = aarch64_pstate_mode(new_el, true); | |
4a2696c0 | 11031 | unsigned int old_mode; |
0ab5953b | 11032 | unsigned int cur_el = arm_current_el(env); |
a65dabf7 | 11033 | int rt; |
0ab5953b | 11034 | |
d55b2a2a CF |
11035 | if (tcg_enabled()) { |
11036 | /* | |
11037 | * Note that new_el can never be 0. If cur_el is 0, then | |
11038 | * el0_a64 is is_a64(), else el0_a64 is ignored. | |
11039 | */ | |
11040 | aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); | |
11041 | } | |
f3a9b694 | 11042 | |
0ab5953b | 11043 | if (cur_el < new_el) { |
9b37a28c FR |
11044 | /* |
11045 | * Entry vector offset depends on whether the implemented EL | |
3d6f7617 PM |
11046 | * immediately lower than the target level is using AArch32 or AArch64 |
11047 | */ | |
11048 | bool is_aa64; | |
cb092fbb | 11049 | uint64_t hcr; |
3d6f7617 PM |
11050 | |
11051 | switch (new_el) { | |
11052 | case 3: | |
11053 | is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; | |
11054 | break; | |
11055 | case 2: | |
cb092fbb RH |
11056 | hcr = arm_hcr_el2_eff(env); |
11057 | if ((hcr & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { | |
11058 | is_aa64 = (hcr & HCR_RW) != 0; | |
11059 | break; | |
11060 | } | |
11061 | /* fall through */ | |
3d6f7617 PM |
11062 | case 1: |
11063 | is_aa64 = is_a64(env); | |
11064 | break; | |
11065 | default: | |
11066 | g_assert_not_reached(); | |
11067 | } | |
11068 | ||
11069 | if (is_aa64) { | |
f3a9b694 PM |
11070 | addr += 0x400; |
11071 | } else { | |
11072 | addr += 0x600; | |
11073 | } | |
11074 | } else if (pstate_read(env) & PSTATE_SP) { | |
11075 | addr += 0x200; | |
11076 | } | |
11077 | ||
f3a9b694 | 11078 | switch (cs->exception_index) { |
11b76fda RH |
11079 | case EXCP_GPC: |
11080 | qemu_log_mask(CPU_LOG_INT, "...with MFAR 0x%" PRIx64 "\n", | |
11081 | env->cp15.mfar_el3); | |
11082 | /* fall through */ | |
f3a9b694 PM |
11083 | case EXCP_PREFETCH_ABORT: |
11084 | case EXCP_DATA_ABORT: | |
7ac61020 PM |
11085 | /* |
11086 | * FEAT_DoubleFault allows synchronous external aborts taken to EL3 | |
11087 | * to be taken to the SError vector entrypoint. | |
11088 | */ | |
11089 | if (new_el == 3 && (env->cp15.scr_el3 & SCR_EASE) && | |
11090 | syndrome_is_sync_extabt(env->exception.syndrome)) { | |
11091 | addr += 0x180; | |
11092 | } | |
f3a9b694 PM |
11093 | env->cp15.far_el[new_el] = env->exception.vaddress; |
11094 | qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", | |
11095 | env->cp15.far_el[new_el]); | |
11096 | /* fall through */ | |
11097 | case EXCP_BKPT: | |
11098 | case EXCP_UDEF: | |
11099 | case EXCP_SWI: | |
11100 | case EXCP_HVC: | |
11101 | case EXCP_HYP_TRAP: | |
11102 | case EXCP_SMC: | |
a65dabf7 PM |
11103 | switch (syn_get_ec(env->exception.syndrome)) { |
11104 | case EC_ADVSIMDFPACCESSTRAP: | |
4be42f40 PM |
11105 | /* |
11106 | * QEMU internal FP/SIMD syndromes from AArch32 include the | |
11107 | * TA and coproc fields which are only exposed if the exception | |
11108 | * is taken to AArch32 Hyp mode. Mask them out to get a valid | |
11109 | * AArch64 format syndrome. | |
11110 | */ | |
11111 | env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20); | |
a65dabf7 PM |
11112 | break; |
11113 | case EC_CP14RTTRAP: | |
11114 | case EC_CP15RTTRAP: | |
11115 | case EC_CP14DTTRAP: | |
11116 | /* | |
11117 | * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently | |
11118 | * the raw register field from the insn; when taking this to | |
11119 | * AArch64 we must convert it to the AArch64 view of the register | |
11120 | * number. Notice that we read a 4-bit AArch32 register number and | |
11121 | * write back a 5-bit AArch64 one. | |
11122 | */ | |
11123 | rt = extract32(env->exception.syndrome, 5, 4); | |
11124 | rt = aarch64_regnum(env, rt); | |
11125 | env->exception.syndrome = deposit32(env->exception.syndrome, | |
11126 | 5, 5, rt); | |
11127 | break; | |
11128 | case EC_CP15RRTTRAP: | |
11129 | case EC_CP14RRTTRAP: | |
11130 | /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */ | |
11131 | rt = extract32(env->exception.syndrome, 5, 4); | |
11132 | rt = aarch64_regnum(env, rt); | |
11133 | env->exception.syndrome = deposit32(env->exception.syndrome, | |
11134 | 5, 5, rt); | |
11135 | rt = extract32(env->exception.syndrome, 10, 4); | |
11136 | rt = aarch64_regnum(env, rt); | |
11137 | env->exception.syndrome = deposit32(env->exception.syndrome, | |
11138 | 10, 5, rt); | |
11139 | break; | |
4be42f40 | 11140 | } |
f3a9b694 PM |
11141 | env->cp15.esr_el[new_el] = env->exception.syndrome; |
11142 | break; | |
11143 | case EXCP_IRQ: | |
11144 | case EXCP_VIRQ: | |
11145 | addr += 0x80; | |
11146 | break; | |
11147 | case EXCP_FIQ: | |
11148 | case EXCP_VFIQ: | |
11149 | addr += 0x100; | |
11150 | break; | |
3c29632f RH |
11151 | case EXCP_VSERR: |
11152 | addr += 0x180; | |
11153 | /* Construct the SError syndrome from IDS and ISS fields. */ | |
11154 | env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff); | |
11155 | env->cp15.esr_el[new_el] = env->exception.syndrome; | |
11156 | break; | |
f3a9b694 PM |
11157 | default: |
11158 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
11159 | } | |
11160 | ||
11161 | if (is_a64(env)) { | |
4a2696c0 | 11162 | old_mode = pstate_read(env); |
f3a9b694 PM |
11163 | aarch64_save_sp(env, arm_current_el(env)); |
11164 | env->elr_el[new_el] = env->pc; | |
11165 | } else { | |
f944a854 | 11166 | old_mode = cpsr_read_for_spsr_elx(env); |
f3a9b694 PM |
11167 | env->elr_el[new_el] = env->regs[15]; |
11168 | ||
11169 | aarch64_sync_32_to_64(env); | |
11170 | ||
11171 | env->condexec_bits = 0; | |
11172 | } | |
4a2696c0 RH |
11173 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode; |
11174 | ||
f3a9b694 PM |
11175 | qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", |
11176 | env->elr_el[new_el]); | |
11177 | ||
4a2696c0 RH |
11178 | if (cpu_isar_feature(aa64_pan, cpu)) { |
11179 | /* The value of PSTATE.PAN is normally preserved, except when ... */ | |
11180 | new_mode |= old_mode & PSTATE_PAN; | |
11181 | switch (new_el) { | |
11182 | case 2: | |
11183 | /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */ | |
11184 | if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) | |
11185 | != (HCR_E2H | HCR_TGE)) { | |
11186 | break; | |
11187 | } | |
11188 | /* fall through */ | |
11189 | case 1: | |
11190 | /* ... the target is EL1 ... */ | |
11191 | /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */ | |
11192 | if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) == 0) { | |
11193 | new_mode |= PSTATE_PAN; | |
11194 | } | |
11195 | break; | |
11196 | } | |
11197 | } | |
34669338 RH |
11198 | if (cpu_isar_feature(aa64_mte, cpu)) { |
11199 | new_mode |= PSTATE_TCO; | |
11200 | } | |
4a2696c0 | 11201 | |
f2f68a78 RC |
11202 | if (cpu_isar_feature(aa64_ssbs, cpu)) { |
11203 | if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) { | |
11204 | new_mode |= PSTATE_SSBS; | |
11205 | } else { | |
11206 | new_mode &= ~PSTATE_SSBS; | |
11207 | } | |
11208 | } | |
11209 | ||
f3a9b694 | 11210 | pstate_write(env, PSTATE_DAIF | new_mode); |
53221552 | 11211 | env->aarch64 = true; |
f3a9b694 | 11212 | aarch64_restore_sp(env, new_el); |
2b77ad4d FR |
11213 | |
11214 | if (tcg_enabled()) { | |
11215 | helper_rebuild_hflags_a64(env, new_el); | |
11216 | } | |
f3a9b694 PM |
11217 | |
11218 | env->pc = addr; | |
11219 | ||
11220 | qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", | |
11221 | new_el, env->pc, pstate_read(env)); | |
966f758c PM |
11222 | } |
11223 | ||
ed6e6ba9 AB |
11224 | /* |
11225 | * Do semihosting call and set the appropriate return value. All the | |
11226 | * permission and validity checks have been done at translate time. | |
11227 | * | |
11228 | * We only see semihosting exceptions in TCG only as they are not | |
11229 | * trapped to the hypervisor in KVM. | |
11230 | */ | |
91f78c58 | 11231 | #ifdef CONFIG_TCG |
a06e3a68 | 11232 | static void tcg_handle_semihosting(CPUState *cs) |
ed6e6ba9 | 11233 | { |
904c04de PM |
11234 | ARMCPU *cpu = ARM_CPU(cs); |
11235 | CPUARMState *env = &cpu->env; | |
11236 | ||
11237 | if (is_a64(env)) { | |
ed6e6ba9 AB |
11238 | qemu_log_mask(CPU_LOG_INT, |
11239 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
11240 | env->xregs[0]); | |
ed3a06b1 | 11241 | do_common_semihosting(cs); |
4ff5ef9e | 11242 | env->pc += 4; |
904c04de | 11243 | } else { |
904c04de PM |
11244 | qemu_log_mask(CPU_LOG_INT, |
11245 | "...handling as semihosting call 0x%x\n", | |
11246 | env->regs[0]); | |
ed3a06b1 | 11247 | do_common_semihosting(cs); |
4ff5ef9e | 11248 | env->regs[15] += env->thumb ? 2 : 4; |
904c04de PM |
11249 | } |
11250 | } | |
ed6e6ba9 | 11251 | #endif |
904c04de | 11252 | |
9b37a28c FR |
11253 | /* |
11254 | * Handle a CPU exception for A and R profile CPUs. | |
966f758c PM |
11255 | * Do any appropriate logging, handle PSCI calls, and then hand off |
11256 | * to the AArch64-entry or AArch32-entry function depending on the | |
11257 | * target exception level's register width. | |
853bfef4 CF |
11258 | * |
11259 | * Note: this is used for both TCG (as the do_interrupt tcg op), | |
11260 | * and KVM to re-inject guest debug exceptions, and to | |
11261 | * inject a Synchronous-External-Abort. | |
966f758c PM |
11262 | */ |
11263 | void arm_cpu_do_interrupt(CPUState *cs) | |
11264 | { | |
11265 | ARMCPU *cpu = ARM_CPU(cs); | |
11266 | CPUARMState *env = &cpu->env; | |
11267 | unsigned int new_el = env->exception.target_el; | |
11268 | ||
531c60a9 | 11269 | assert(!arm_feature(env, ARM_FEATURE_M)); |
966f758c | 11270 | |
fc6177af | 11271 | arm_log_exception(cs); |
966f758c PM |
11272 | qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), |
11273 | new_el); | |
11274 | if (qemu_loglevel_mask(CPU_LOG_INT) | |
11275 | && !excp_is_internal(cs->exception_index)) { | |
6568da45 | 11276 | qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", |
64b91e3f | 11277 | syn_get_ec(env->exception.syndrome), |
966f758c PM |
11278 | env->exception.syndrome); |
11279 | } | |
11280 | ||
0c1aaa66 | 11281 | if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) { |
966f758c PM |
11282 | arm_handle_psci_call(cpu); |
11283 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | |
11284 | return; | |
11285 | } | |
11286 | ||
ed6e6ba9 AB |
11287 | /* |
11288 | * Semihosting semantics depend on the register width of the code | |
11289 | * that caused the exception, not the target exception level, so | |
11290 | * must be handled here. | |
966f758c | 11291 | */ |
ed6e6ba9 AB |
11292 | #ifdef CONFIG_TCG |
11293 | if (cs->exception_index == EXCP_SEMIHOST) { | |
a06e3a68 | 11294 | tcg_handle_semihosting(cs); |
904c04de PM |
11295 | return; |
11296 | } | |
ed6e6ba9 | 11297 | #endif |
904c04de | 11298 | |
9b37a28c FR |
11299 | /* |
11300 | * Hooks may change global state so BQL should be held, also the | |
b5c53d1b AL |
11301 | * BQL needs to be held for any modification of |
11302 | * cs->interrupt_request. | |
11303 | */ | |
11304 | g_assert(qemu_mutex_iothread_locked()); | |
11305 | ||
11306 | arm_call_pre_el_change_hook(cpu); | |
11307 | ||
904c04de PM |
11308 | assert(!excp_is_internal(cs->exception_index)); |
11309 | if (arm_el_is_aa64(env, new_el)) { | |
966f758c PM |
11310 | arm_cpu_do_interrupt_aarch64(cs); |
11311 | } else { | |
11312 | arm_cpu_do_interrupt_aarch32(cs); | |
11313 | } | |
f3a9b694 | 11314 | |
bd7d00fc PM |
11315 | arm_call_el_change_hook(cpu); |
11316 | ||
f3a9b694 PM |
11317 | if (!kvm_enabled()) { |
11318 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
11319 | } | |
11320 | } | |
c47eaf9f | 11321 | #endif /* !CONFIG_USER_ONLY */ |
0480f69a | 11322 | |
aaec1432 RH |
11323 | uint64_t arm_sctlr(CPUARMState *env, int el) |
11324 | { | |
11325 | /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ | |
11326 | if (el == 0) { | |
11327 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0); | |
d902ae75 | 11328 | el = mmu_idx == ARMMMUIdx_E20_0 ? 2 : 1; |
aaec1432 RH |
11329 | } |
11330 | return env->cp15.sctlr_el[el]; | |
11331 | } | |
c47eaf9f | 11332 | |
8ae08860 | 11333 | int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) |
b830a5ee RH |
11334 | { |
11335 | if (regime_has_2_ranges(mmu_idx)) { | |
11336 | return extract64(tcr, 37, 2); | |
edc05dd4 | 11337 | } else if (regime_is_stage2(mmu_idx)) { |
b830a5ee RH |
11338 | return 0; /* VTCR_EL2 */ |
11339 | } else { | |
3e270f67 RH |
11340 | /* Replicate the single TBI bit so we always have 2 bits. */ |
11341 | return extract32(tcr, 20, 1) * 3; | |
b830a5ee RH |
11342 | } |
11343 | } | |
11344 | ||
8ae08860 | 11345 | int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) |
b830a5ee RH |
11346 | { |
11347 | if (regime_has_2_ranges(mmu_idx)) { | |
11348 | return extract64(tcr, 51, 2); | |
edc05dd4 | 11349 | } else if (regime_is_stage2(mmu_idx)) { |
b830a5ee RH |
11350 | return 0; /* VTCR_EL2 */ |
11351 | } else { | |
3e270f67 RH |
11352 | /* Replicate the single TBID bit so we always have 2 bits. */ |
11353 | return extract32(tcr, 29, 1) * 3; | |
b830a5ee RH |
11354 | } |
11355 | } | |
11356 | ||
671efad1 | 11357 | int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx) |
81ae05fa RH |
11358 | { |
11359 | if (regime_has_2_ranges(mmu_idx)) { | |
11360 | return extract64(tcr, 57, 2); | |
11361 | } else { | |
11362 | /* Replicate the single TCMA bit so we always have 2 bits. */ | |
11363 | return extract32(tcr, 30, 1) * 3; | |
11364 | } | |
11365 | } | |
11366 | ||
104f703d PM |
11367 | static ARMGranuleSize tg0_to_gran_size(int tg) |
11368 | { | |
11369 | switch (tg) { | |
11370 | case 0: | |
11371 | return Gran4K; | |
11372 | case 1: | |
11373 | return Gran64K; | |
11374 | case 2: | |
11375 | return Gran16K; | |
11376 | default: | |
11377 | return GranInvalid; | |
11378 | } | |
11379 | } | |
11380 | ||
11381 | static ARMGranuleSize tg1_to_gran_size(int tg) | |
11382 | { | |
11383 | switch (tg) { | |
11384 | case 1: | |
11385 | return Gran16K; | |
11386 | case 2: | |
11387 | return Gran4K; | |
11388 | case 3: | |
11389 | return Gran64K; | |
11390 | default: | |
11391 | return GranInvalid; | |
11392 | } | |
11393 | } | |
11394 | ||
11395 | static inline bool have4k(ARMCPU *cpu, bool stage2) | |
11396 | { | |
11397 | return stage2 ? cpu_isar_feature(aa64_tgran4_2, cpu) | |
11398 | : cpu_isar_feature(aa64_tgran4, cpu); | |
11399 | } | |
11400 | ||
11401 | static inline bool have16k(ARMCPU *cpu, bool stage2) | |
11402 | { | |
11403 | return stage2 ? cpu_isar_feature(aa64_tgran16_2, cpu) | |
11404 | : cpu_isar_feature(aa64_tgran16, cpu); | |
11405 | } | |
11406 | ||
11407 | static inline bool have64k(ARMCPU *cpu, bool stage2) | |
11408 | { | |
11409 | return stage2 ? cpu_isar_feature(aa64_tgran64_2, cpu) | |
11410 | : cpu_isar_feature(aa64_tgran64, cpu); | |
11411 | } | |
11412 | ||
11413 | static ARMGranuleSize sanitize_gran_size(ARMCPU *cpu, ARMGranuleSize gran, | |
11414 | bool stage2) | |
11415 | { | |
11416 | switch (gran) { | |
11417 | case Gran4K: | |
11418 | if (have4k(cpu, stage2)) { | |
11419 | return gran; | |
11420 | } | |
11421 | break; | |
11422 | case Gran16K: | |
11423 | if (have16k(cpu, stage2)) { | |
11424 | return gran; | |
11425 | } | |
11426 | break; | |
11427 | case Gran64K: | |
11428 | if (have64k(cpu, stage2)) { | |
11429 | return gran; | |
11430 | } | |
11431 | break; | |
11432 | case GranInvalid: | |
11433 | break; | |
11434 | } | |
11435 | /* | |
11436 | * If the guest selects a granule size that isn't implemented, | |
11437 | * the architecture requires that we behave as if it selected one | |
11438 | * that is (with an IMPDEF choice of which one to pick). We choose | |
11439 | * to implement the smallest supported granule size. | |
11440 | */ | |
11441 | if (have4k(cpu, stage2)) { | |
11442 | return Gran4K; | |
11443 | } | |
11444 | if (have16k(cpu, stage2)) { | |
11445 | return Gran16K; | |
11446 | } | |
11447 | assert(have64k(cpu, stage2)); | |
11448 | return Gran64K; | |
11449 | } | |
11450 | ||
b830a5ee | 11451 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, |
478dccbb PM |
11452 | ARMMMUIdx mmu_idx, bool data, |
11453 | bool el1_is_aa32) | |
ba97be9f | 11454 | { |
c1547bba | 11455 | uint64_t tcr = regime_tcr(env, mmu_idx); |
89739227 | 11456 | bool epd, hpd, tsz_oob, ds, ha, hd; |
ef56c242 | 11457 | int select, tsz, tbi, max_tsz, min_tsz, ps, sh; |
104f703d | 11458 | ARMGranuleSize gran; |
ef56c242 | 11459 | ARMCPU *cpu = env_archcpu(env); |
edc05dd4 | 11460 | bool stage2 = regime_is_stage2(mmu_idx); |
ba97be9f | 11461 | |
339370b9 | 11462 | if (!regime_has_2_ranges(mmu_idx)) { |
71d18164 | 11463 | select = 0; |
ba97be9f | 11464 | tsz = extract32(tcr, 0, 6); |
104f703d PM |
11465 | gran = tg0_to_gran_size(extract32(tcr, 14, 2)); |
11466 | if (stage2) { | |
ba97be9f | 11467 | /* VTCR_EL2 */ |
b830a5ee | 11468 | hpd = false; |
ba97be9f | 11469 | } else { |
ba97be9f RH |
11470 | hpd = extract32(tcr, 24, 1); |
11471 | } | |
11472 | epd = false; | |
ef56c242 | 11473 | sh = extract32(tcr, 12, 2); |
f4ecc015 | 11474 | ps = extract32(tcr, 16, 3); |
89739227 RH |
11475 | ha = extract32(tcr, 21, 1) && cpu_isar_feature(aa64_hafs, cpu); |
11476 | hd = extract32(tcr, 22, 1) && cpu_isar_feature(aa64_hdbs, cpu); | |
ef56c242 | 11477 | ds = extract64(tcr, 32, 1); |
ba97be9f | 11478 | } else { |
e4c93e44 PM |
11479 | bool e0pd; |
11480 | ||
71d18164 RH |
11481 | /* |
11482 | * Bit 55 is always between the two regions, and is canonical for | |
11483 | * determining if address tagging is enabled. | |
11484 | */ | |
11485 | select = extract64(va, 55, 1); | |
11486 | if (!select) { | |
11487 | tsz = extract32(tcr, 0, 6); | |
104f703d | 11488 | gran = tg0_to_gran_size(extract32(tcr, 14, 2)); |
71d18164 | 11489 | epd = extract32(tcr, 7, 1); |
ef56c242 | 11490 | sh = extract32(tcr, 12, 2); |
71d18164 | 11491 | hpd = extract64(tcr, 41, 1); |
e4c93e44 | 11492 | e0pd = extract64(tcr, 55, 1); |
71d18164 | 11493 | } else { |
71d18164 | 11494 | tsz = extract32(tcr, 16, 6); |
104f703d | 11495 | gran = tg1_to_gran_size(extract32(tcr, 30, 2)); |
71d18164 | 11496 | epd = extract32(tcr, 23, 1); |
ef56c242 | 11497 | sh = extract32(tcr, 28, 2); |
71d18164 | 11498 | hpd = extract64(tcr, 42, 1); |
e4c93e44 | 11499 | e0pd = extract64(tcr, 56, 1); |
71d18164 | 11500 | } |
f4ecc015 | 11501 | ps = extract64(tcr, 32, 3); |
89739227 RH |
11502 | ha = extract64(tcr, 39, 1) && cpu_isar_feature(aa64_hafs, cpu); |
11503 | hd = extract64(tcr, 40, 1) && cpu_isar_feature(aa64_hdbs, cpu); | |
ef56c242 | 11504 | ds = extract64(tcr, 59, 1); |
e4c93e44 PM |
11505 | |
11506 | if (e0pd && cpu_isar_feature(aa64_e0pd, cpu) && | |
11507 | regime_is_user(env, mmu_idx)) { | |
11508 | epd = true; | |
11509 | } | |
ba97be9f | 11510 | } |
c36c65ea | 11511 | |
104f703d | 11512 | gran = sanitize_gran_size(cpu, gran, stage2); |
104f703d | 11513 | |
ef56c242 | 11514 | if (cpu_isar_feature(aa64_st, cpu)) { |
3c003f70 | 11515 | max_tsz = 48 - (gran == Gran64K); |
c36c65ea RDC |
11516 | } else { |
11517 | max_tsz = 39; | |
11518 | } | |
0af312b6 | 11519 | |
ef56c242 RH |
11520 | /* |
11521 | * DS is RES0 unless FEAT_LPA2 is supported for the given page size; | |
11522 | * adjust the effective value of DS, as documented. | |
11523 | */ | |
0af312b6 | 11524 | min_tsz = 16; |
3c003f70 | 11525 | if (gran == Gran64K) { |
ef56c242 RH |
11526 | if (cpu_isar_feature(aa64_lva, cpu)) { |
11527 | min_tsz = 12; | |
11528 | } | |
11529 | ds = false; | |
11530 | } else if (ds) { | |
edc05dd4 | 11531 | if (regime_is_stage2(mmu_idx)) { |
3c003f70 | 11532 | if (gran == Gran16K) { |
ef56c242 RH |
11533 | ds = cpu_isar_feature(aa64_tgran16_2_lpa2, cpu); |
11534 | } else { | |
11535 | ds = cpu_isar_feature(aa64_tgran4_2_lpa2, cpu); | |
11536 | } | |
edc05dd4 | 11537 | } else { |
3c003f70 | 11538 | if (gran == Gran16K) { |
ef56c242 RH |
11539 | ds = cpu_isar_feature(aa64_tgran16_lpa2, cpu); |
11540 | } else { | |
11541 | ds = cpu_isar_feature(aa64_tgran4_lpa2, cpu); | |
11542 | } | |
ef56c242 RH |
11543 | } |
11544 | if (ds) { | |
0af312b6 RH |
11545 | min_tsz = 12; |
11546 | } | |
11547 | } | |
c36c65ea | 11548 | |
478dccbb PM |
11549 | if (stage2 && el1_is_aa32) { |
11550 | /* | |
11551 | * For AArch32 EL1 the min txsz (and thus max IPA size) requirements | |
11552 | * are loosened: a configured IPA of 40 bits is permitted even if | |
11553 | * the implemented PA is less than that (and so a 40 bit IPA would | |
11554 | * fault for an AArch64 EL1). See R_DTLMN. | |
11555 | */ | |
11556 | min_tsz = MIN(min_tsz, 24); | |
11557 | } | |
11558 | ||
ebf93ce7 RH |
11559 | if (tsz > max_tsz) { |
11560 | tsz = max_tsz; | |
11561 | tsz_oob = true; | |
11562 | } else if (tsz < min_tsz) { | |
11563 | tsz = min_tsz; | |
11564 | tsz_oob = true; | |
11565 | } else { | |
11566 | tsz_oob = false; | |
11567 | } | |
ba97be9f | 11568 | |
b830a5ee RH |
11569 | /* Present TBI as a composite with TBID. */ |
11570 | tbi = aa64_va_parameter_tbi(tcr, mmu_idx); | |
11571 | if (!data) { | |
11572 | tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); | |
11573 | } | |
11574 | tbi = (tbi >> select) & 1; | |
11575 | ||
ba97be9f RH |
11576 | return (ARMVAParameters) { |
11577 | .tsz = tsz, | |
f4ecc015 | 11578 | .ps = ps, |
ef56c242 | 11579 | .sh = sh, |
ba97be9f RH |
11580 | .select = select, |
11581 | .tbi = tbi, | |
11582 | .epd = epd, | |
11583 | .hpd = hpd, | |
ebf93ce7 | 11584 | .tsz_oob = tsz_oob, |
ef56c242 | 11585 | .ds = ds, |
89739227 RH |
11586 | .ha = ha, |
11587 | .hd = ha && hd, | |
3c003f70 | 11588 | .gran = gran, |
ba97be9f RH |
11589 | }; |
11590 | } | |
11591 | ||
9b37a28c FR |
11592 | /* |
11593 | * Note that signed overflow is undefined in C. The following routines are | |
11594 | * careful to use unsigned types where modulo arithmetic is required. | |
11595 | * Failure to do so _will_ break on newer gcc. | |
11596 | */ | |
6ddbc6e4 PB |
11597 | |
11598 | /* Signed saturating arithmetic. */ | |
11599 | ||
1654b2d6 | 11600 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
11601 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
11602 | { | |
11603 | uint16_t res; | |
11604 | ||
11605 | res = a + b; | |
11606 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
f927dbda | 11607 | if (a & 0x8000) { |
6ddbc6e4 | 11608 | res = 0x8000; |
f927dbda | 11609 | } else { |
6ddbc6e4 | 11610 | res = 0x7fff; |
f927dbda | 11611 | } |
6ddbc6e4 PB |
11612 | } |
11613 | return res; | |
11614 | } | |
11615 | ||
1654b2d6 | 11616 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
11617 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
11618 | { | |
11619 | uint8_t res; | |
11620 | ||
11621 | res = a + b; | |
11622 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
f927dbda | 11623 | if (a & 0x80) { |
6ddbc6e4 | 11624 | res = 0x80; |
f927dbda | 11625 | } else { |
6ddbc6e4 | 11626 | res = 0x7f; |
f927dbda | 11627 | } |
6ddbc6e4 PB |
11628 | } |
11629 | return res; | |
11630 | } | |
11631 | ||
1654b2d6 | 11632 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
11633 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
11634 | { | |
11635 | uint16_t res; | |
11636 | ||
11637 | res = a - b; | |
11638 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
f927dbda | 11639 | if (a & 0x8000) { |
6ddbc6e4 | 11640 | res = 0x8000; |
f927dbda | 11641 | } else { |
6ddbc6e4 | 11642 | res = 0x7fff; |
f927dbda | 11643 | } |
6ddbc6e4 PB |
11644 | } |
11645 | return res; | |
11646 | } | |
11647 | ||
1654b2d6 | 11648 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
11649 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
11650 | { | |
11651 | uint8_t res; | |
11652 | ||
11653 | res = a - b; | |
11654 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
f927dbda | 11655 | if (a & 0x80) { |
6ddbc6e4 | 11656 | res = 0x80; |
f927dbda | 11657 | } else { |
6ddbc6e4 | 11658 | res = 0x7f; |
f927dbda | 11659 | } |
6ddbc6e4 PB |
11660 | } |
11661 | return res; | |
11662 | } | |
11663 | ||
11664 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
11665 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
11666 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
11667 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
11668 | #define PFX q | |
11669 | ||
11670 | #include "op_addsub.h" | |
11671 | ||
11672 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 11673 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
11674 | { |
11675 | uint16_t res; | |
11676 | res = a + b; | |
f927dbda | 11677 | if (res < a) { |
6ddbc6e4 | 11678 | res = 0xffff; |
f927dbda | 11679 | } |
6ddbc6e4 PB |
11680 | return res; |
11681 | } | |
11682 | ||
460a09c1 | 11683 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 | 11684 | { |
f927dbda | 11685 | if (a > b) { |
6ddbc6e4 | 11686 | return a - b; |
f927dbda | 11687 | } else { |
6ddbc6e4 | 11688 | return 0; |
f927dbda | 11689 | } |
6ddbc6e4 PB |
11690 | } |
11691 | ||
11692 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
11693 | { | |
11694 | uint8_t res; | |
11695 | res = a + b; | |
f927dbda | 11696 | if (res < a) { |
6ddbc6e4 | 11697 | res = 0xff; |
f927dbda | 11698 | } |
6ddbc6e4 PB |
11699 | return res; |
11700 | } | |
11701 | ||
11702 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
11703 | { | |
f927dbda | 11704 | if (a > b) { |
6ddbc6e4 | 11705 | return a - b; |
f927dbda | 11706 | } else { |
6ddbc6e4 | 11707 | return 0; |
f927dbda | 11708 | } |
6ddbc6e4 PB |
11709 | } |
11710 | ||
11711 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
11712 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
11713 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
11714 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
11715 | #define PFX uq | |
11716 | ||
11717 | #include "op_addsub.h" | |
11718 | ||
11719 | /* Signed modulo arithmetic. */ | |
11720 | #define SARITH16(a, b, n, op) do { \ | |
11721 | int32_t sum; \ | |
db6e2e65 | 11722 | sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
6ddbc6e4 PB |
11723 | RESULT(sum, n, 16); \ |
11724 | if (sum >= 0) \ | |
11725 | ge |= 3 << (n * 2); \ | |
04215eb1 | 11726 | } while (0) |
6ddbc6e4 PB |
11727 | |
11728 | #define SARITH8(a, b, n, op) do { \ | |
11729 | int32_t sum; \ | |
db6e2e65 | 11730 | sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
6ddbc6e4 PB |
11731 | RESULT(sum, n, 8); \ |
11732 | if (sum >= 0) \ | |
11733 | ge |= 1 << n; \ | |
04215eb1 | 11734 | } while (0) |
6ddbc6e4 PB |
11735 | |
11736 | ||
11737 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
11738 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
11739 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
11740 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
11741 | #define PFX s | |
11742 | #define ARITH_GE | |
11743 | ||
11744 | #include "op_addsub.h" | |
11745 | ||
11746 | /* Unsigned modulo arithmetic. */ | |
11747 | #define ADD16(a, b, n) do { \ | |
11748 | uint32_t sum; \ | |
11749 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
11750 | RESULT(sum, n, 16); \ | |
a87aa10b | 11751 | if ((sum >> 16) == 1) \ |
6ddbc6e4 | 11752 | ge |= 3 << (n * 2); \ |
04215eb1 | 11753 | } while (0) |
6ddbc6e4 PB |
11754 | |
11755 | #define ADD8(a, b, n) do { \ | |
11756 | uint32_t sum; \ | |
11757 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
11758 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
11759 | if ((sum >> 8) == 1) \ |
11760 | ge |= 1 << n; \ | |
04215eb1 | 11761 | } while (0) |
6ddbc6e4 PB |
11762 | |
11763 | #define SUB16(a, b, n) do { \ | |
11764 | uint32_t sum; \ | |
11765 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
11766 | RESULT(sum, n, 16); \ | |
11767 | if ((sum >> 16) == 0) \ | |
11768 | ge |= 3 << (n * 2); \ | |
04215eb1 | 11769 | } while (0) |
6ddbc6e4 PB |
11770 | |
11771 | #define SUB8(a, b, n) do { \ | |
11772 | uint32_t sum; \ | |
11773 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
11774 | RESULT(sum, n, 8); \ | |
11775 | if ((sum >> 8) == 0) \ | |
a87aa10b | 11776 | ge |= 1 << n; \ |
04215eb1 | 11777 | } while (0) |
6ddbc6e4 PB |
11778 | |
11779 | #define PFX u | |
11780 | #define ARITH_GE | |
11781 | ||
11782 | #include "op_addsub.h" | |
11783 | ||
11784 | /* Halved signed arithmetic. */ | |
11785 | #define ADD16(a, b, n) \ | |
11786 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
11787 | #define SUB16(a, b, n) \ | |
11788 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
11789 | #define ADD8(a, b, n) \ | |
11790 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
11791 | #define SUB8(a, b, n) \ | |
11792 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
11793 | #define PFX sh | |
11794 | ||
11795 | #include "op_addsub.h" | |
11796 | ||
11797 | /* Halved unsigned arithmetic. */ | |
11798 | #define ADD16(a, b, n) \ | |
11799 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
11800 | #define SUB16(a, b, n) \ | |
11801 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
11802 | #define ADD8(a, b, n) \ | |
11803 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
11804 | #define SUB8(a, b, n) \ | |
11805 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
11806 | #define PFX uh | |
11807 | ||
11808 | #include "op_addsub.h" | |
11809 | ||
11810 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
11811 | { | |
f927dbda | 11812 | if (a > b) { |
6ddbc6e4 | 11813 | return a - b; |
f927dbda | 11814 | } else { |
6ddbc6e4 | 11815 | return b - a; |
f927dbda | 11816 | } |
6ddbc6e4 PB |
11817 | } |
11818 | ||
11819 | /* Unsigned sum of absolute byte differences. */ | |
11820 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
11821 | { | |
11822 | uint32_t sum; | |
11823 | sum = do_usad(a, b); | |
11824 | sum += do_usad(a >> 8, b >> 8); | |
bdc3b6f5 | 11825 | sum += do_usad(a >> 16, b >> 16); |
6ddbc6e4 PB |
11826 | sum += do_usad(a >> 24, b >> 24); |
11827 | return sum; | |
11828 | } | |
11829 | ||
11830 | /* For ARMv6 SEL instruction. */ | |
11831 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
11832 | { | |
11833 | uint32_t mask; | |
11834 | ||
11835 | mask = 0; | |
f927dbda | 11836 | if (flags & 1) { |
6ddbc6e4 | 11837 | mask |= 0xff; |
f927dbda FR |
11838 | } |
11839 | if (flags & 2) { | |
6ddbc6e4 | 11840 | mask |= 0xff00; |
f927dbda FR |
11841 | } |
11842 | if (flags & 4) { | |
6ddbc6e4 | 11843 | mask |= 0xff0000; |
f927dbda FR |
11844 | } |
11845 | if (flags & 8) { | |
6ddbc6e4 | 11846 | mask |= 0xff000000; |
f927dbda | 11847 | } |
6ddbc6e4 PB |
11848 | return (a & mask) | (b & ~mask); |
11849 | } | |
11850 | ||
9b37a28c FR |
11851 | /* |
11852 | * CRC helpers. | |
aa633469 PM |
11853 | * The upper bytes of val (above the number specified by 'bytes') must have |
11854 | * been zeroed out by the caller. | |
11855 | */ | |
eb0ecd5a WN |
11856 | uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) |
11857 | { | |
11858 | uint8_t buf[4]; | |
11859 | ||
aa633469 | 11860 | stl_le_p(buf, val); |
eb0ecd5a WN |
11861 | |
11862 | /* zlib crc32 converts the accumulator and output to one's complement. */ | |
11863 | return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | |
11864 | } | |
11865 | ||
11866 | uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | |
11867 | { | |
11868 | uint8_t buf[4]; | |
11869 | ||
aa633469 | 11870 | stl_le_p(buf, val); |
eb0ecd5a WN |
11871 | |
11872 | /* Linux crc32c converts the output to one's complement. */ | |
11873 | return crc32c(acc, buf, bytes) ^ 0xffffffff; | |
11874 | } | |
a9e01311 | 11875 | |
9b37a28c FR |
11876 | /* |
11877 | * Return the exception level to which FP-disabled exceptions should | |
a9e01311 RH |
11878 | * be taken, or 0 if FP is enabled. |
11879 | */ | |
ced31551 | 11880 | int fp_exception_el(CPUARMState *env, int cur_el) |
a9e01311 | 11881 | { |
55faa212 | 11882 | #ifndef CONFIG_USER_ONLY |
d5a6fa2d RH |
11883 | uint64_t hcr_el2; |
11884 | ||
9b37a28c FR |
11885 | /* |
11886 | * CPACR and the CPTR registers don't exist before v6, so FP is | |
a9e01311 RH |
11887 | * always accessible |
11888 | */ | |
11889 | if (!arm_feature(env, ARM_FEATURE_V6)) { | |
11890 | return 0; | |
11891 | } | |
11892 | ||
d87513c0 PM |
11893 | if (arm_feature(env, ARM_FEATURE_M)) { |
11894 | /* CPACR can cause a NOCP UsageFault taken to current security state */ | |
11895 | if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) { | |
11896 | return 1; | |
11897 | } | |
11898 | ||
11899 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) { | |
11900 | if (!extract32(env->v7m.nsacr, 10, 1)) { | |
11901 | /* FP insns cause a NOCP UsageFault taken to Secure */ | |
11902 | return 3; | |
11903 | } | |
11904 | } | |
11905 | ||
11906 | return 0; | |
11907 | } | |
11908 | ||
d5a6fa2d RH |
11909 | hcr_el2 = arm_hcr_el2_eff(env); |
11910 | ||
9b37a28c FR |
11911 | /* |
11912 | * The CPACR controls traps to EL1, or PL1 if we're 32 bit: | |
a9e01311 RH |
11913 | * 0, 2 : trap EL0 and EL1/PL1 accesses |
11914 | * 1 : trap only EL0 accesses | |
11915 | * 3 : trap no accesses | |
c2ddb7cf | 11916 | * This register is ignored if E2H+TGE are both set. |
a9e01311 | 11917 | */ |
d5a6fa2d | 11918 | if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { |
fab8ad39 | 11919 | int fpen = FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN); |
c2ddb7cf RH |
11920 | |
11921 | switch (fpen) { | |
02e1de14 RH |
11922 | case 1: |
11923 | if (cur_el != 0) { | |
11924 | break; | |
11925 | } | |
11926 | /* fall through */ | |
c2ddb7cf RH |
11927 | case 0: |
11928 | case 2: | |
02e1de14 RH |
11929 | /* Trap from Secure PL0 or PL1 to Secure PL1. */ |
11930 | if (!arm_el_is_aa64(env, 3) | |
11931 | && (cur_el == 3 || arm_is_secure_below_el3(env))) { | |
a9e01311 RH |
11932 | return 3; |
11933 | } | |
02e1de14 | 11934 | if (cur_el <= 1) { |
c2ddb7cf RH |
11935 | return 1; |
11936 | } | |
11937 | break; | |
a9e01311 | 11938 | } |
a9e01311 RH |
11939 | } |
11940 | ||
fc1120a7 PM |
11941 | /* |
11942 | * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode | |
11943 | * to control non-secure access to the FPU. It doesn't have any | |
11944 | * effect if EL3 is AArch64 or if EL3 doesn't exist at all. | |
11945 | */ | |
11946 | if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
11947 | cur_el <= 2 && !arm_is_secure_below_el3(env))) { | |
11948 | if (!extract32(env->cp15.nsacr, 10, 1)) { | |
11949 | /* FP insns act as UNDEF */ | |
11950 | return cur_el == 2 ? 2 : 1; | |
11951 | } | |
11952 | } | |
11953 | ||
d5a6fa2d RH |
11954 | /* |
11955 | * CPTR_EL2 is present in v7VE or v8, and changes format | |
11956 | * with HCR_EL2.E2H (regardless of TGE). | |
a9e01311 | 11957 | */ |
d5a6fa2d RH |
11958 | if (cur_el <= 2) { |
11959 | if (hcr_el2 & HCR_E2H) { | |
fab8ad39 | 11960 | switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) { |
d5a6fa2d RH |
11961 | case 1: |
11962 | if (cur_el != 0 || !(hcr_el2 & HCR_TGE)) { | |
11963 | break; | |
11964 | } | |
11965 | /* fall through */ | |
11966 | case 0: | |
11967 | case 2: | |
11968 | return 2; | |
11969 | } | |
11970 | } else if (arm_is_el2_enabled(env)) { | |
fab8ad39 | 11971 | if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) { |
d5a6fa2d RH |
11972 | return 2; |
11973 | } | |
11974 | } | |
a9e01311 RH |
11975 | } |
11976 | ||
11977 | /* CPTR_EL3 : present in v8 */ | |
fab8ad39 | 11978 | if (FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TFP)) { |
a9e01311 RH |
11979 | /* Trap all FP ops to EL3 */ |
11980 | return 3; | |
11981 | } | |
55faa212 | 11982 | #endif |
a9e01311 RH |
11983 | return 0; |
11984 | } | |
11985 | ||
b9f6033c RH |
11986 | /* Return the exception level we're running at if this is our mmu_idx */ |
11987 | int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) | |
11988 | { | |
11989 | if (mmu_idx & ARM_MMU_IDX_M) { | |
11990 | return mmu_idx & ARM_MMU_IDX_M_PRIV; | |
11991 | } | |
11992 | ||
11993 | switch (mmu_idx) { | |
11994 | case ARMMMUIdx_E10_0: | |
11995 | case ARMMMUIdx_E20_0: | |
b9f6033c RH |
11996 | return 0; |
11997 | case ARMMMUIdx_E10_1: | |
452ef8cb | 11998 | case ARMMMUIdx_E10_1_PAN: |
b9f6033c RH |
11999 | return 1; |
12000 | case ARMMMUIdx_E2: | |
12001 | case ARMMMUIdx_E20_2: | |
452ef8cb | 12002 | case ARMMMUIdx_E20_2_PAN: |
b9f6033c | 12003 | return 2; |
d902ae75 | 12004 | case ARMMMUIdx_E3: |
b9f6033c RH |
12005 | return 3; |
12006 | default: | |
12007 | g_assert_not_reached(); | |
12008 | } | |
12009 | } | |
12010 | ||
7aab5a8c | 12011 | #ifndef CONFIG_TCG |
65e4655c RH |
12012 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
12013 | { | |
7aab5a8c | 12014 | g_assert_not_reached(); |
65e4655c | 12015 | } |
7aab5a8c | 12016 | #endif |
65e4655c | 12017 | |
6f2d9d74 TK |
12018 | static bool arm_pan_enabled(CPUARMState *env) |
12019 | { | |
12020 | if (is_a64(env)) { | |
12021 | return env->pstate & PSTATE_PAN; | |
12022 | } else { | |
12023 | return env->uncached_cpsr & CPSR_PAN; | |
12024 | } | |
12025 | } | |
12026 | ||
164690b2 | 12027 | ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) |
65e4655c | 12028 | { |
b6ad6062 RDC |
12029 | ARMMMUIdx idx; |
12030 | uint64_t hcr; | |
12031 | ||
65e4655c | 12032 | if (arm_feature(env, ARM_FEATURE_M)) { |
50494a27 | 12033 | return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); |
65e4655c RH |
12034 | } |
12035 | ||
6003d980 | 12036 | /* See ARM pseudo-function ELIsInHost. */ |
b9f6033c RH |
12037 | switch (el) { |
12038 | case 0: | |
b6ad6062 RDC |
12039 | hcr = arm_hcr_el2_eff(env); |
12040 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
12041 | idx = ARMMMUIdx_E20_0; | |
12042 | } else { | |
12043 | idx = ARMMMUIdx_E10_0; | |
6003d980 | 12044 | } |
b6ad6062 | 12045 | break; |
b9f6033c | 12046 | case 1: |
6f2d9d74 | 12047 | if (arm_pan_enabled(env)) { |
b6ad6062 RDC |
12048 | idx = ARMMMUIdx_E10_1_PAN; |
12049 | } else { | |
12050 | idx = ARMMMUIdx_E10_1; | |
66412260 | 12051 | } |
b6ad6062 | 12052 | break; |
b9f6033c | 12053 | case 2: |
6003d980 | 12054 | /* Note that TGE does not apply at EL2. */ |
b6ad6062 | 12055 | if (arm_hcr_el2_eff(env) & HCR_E2H) { |
6f2d9d74 | 12056 | if (arm_pan_enabled(env)) { |
b6ad6062 RDC |
12057 | idx = ARMMMUIdx_E20_2_PAN; |
12058 | } else { | |
12059 | idx = ARMMMUIdx_E20_2; | |
66412260 | 12060 | } |
b6ad6062 RDC |
12061 | } else { |
12062 | idx = ARMMMUIdx_E2; | |
6003d980 | 12063 | } |
b6ad6062 | 12064 | break; |
b9f6033c | 12065 | case 3: |
d902ae75 | 12066 | return ARMMMUIdx_E3; |
b9f6033c RH |
12067 | default: |
12068 | g_assert_not_reached(); | |
65e4655c | 12069 | } |
b6ad6062 | 12070 | |
b6ad6062 | 12071 | return idx; |
50494a27 RH |
12072 | } |
12073 | ||
164690b2 RH |
12074 | ARMMMUIdx arm_mmu_idx(CPUARMState *env) |
12075 | { | |
12076 | return arm_mmu_idx_el(env, arm_current_el(env)); | |
12077 | } | |
12078 | ||
26702213 PM |
12079 | static bool mve_no_pred(CPUARMState *env) |
12080 | { | |
12081 | /* | |
12082 | * Return true if there is definitely no predication of MVE | |
12083 | * instructions by VPR or LTPSIZE. (Returning false even if there | |
12084 | * isn't any predication is OK; generated code will just be | |
12085 | * a little worse.) | |
12086 | * If the CPU does not implement MVE then this TB flag is always 0. | |
12087 | * | |
12088 | * NOTE: if you change this logic, the "recalculate s->mve_no_pred" | |
12089 | * logic in gen_update_fp_context() needs to be updated to match. | |
12090 | * | |
12091 | * We do not include the effect of the ECI bits here -- they are | |
12092 | * tracked in other TB flags. This simplifies the logic for | |
12093 | * "when did we emit code that changes the MVE_NO_PRED TB flag | |
12094 | * and thus need to end the TB?". | |
12095 | */ | |
12096 | if (cpu_isar_feature(aa32_mve, env_archcpu(env))) { | |
12097 | return false; | |
12098 | } | |
12099 | if (env->v7m.vpr) { | |
12100 | return false; | |
12101 | } | |
12102 | if (env->v7m.ltpsize < 4) { | |
12103 | return false; | |
12104 | } | |
12105 | return true; | |
12106 | } | |
12107 | ||
bb5de525 AJ |
12108 | void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, |
12109 | uint64_t *cs_base, uint32_t *pflags) | |
d4d7503a | 12110 | { |
3902bfc6 | 12111 | CPUARMTBFlags flags; |
d4d7503a | 12112 | |
0ee8b24a | 12113 | assert_hflags_rebuild_correctly(env); |
3902bfc6 | 12114 | flags = env->hflags; |
3d74e2e9 | 12115 | |
a729a46b | 12116 | if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { |
d4d7503a | 12117 | *pc = env->pc; |
d4d7503a | 12118 | if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { |
a729a46b | 12119 | DP_TBFLAG_A64(flags, BTYPE, env->btype); |
08f1434a | 12120 | } |
a9e01311 RH |
12121 | } else { |
12122 | *pc = env->regs[15]; | |
6e33ced5 RH |
12123 | |
12124 | if (arm_feature(env, ARM_FEATURE_M)) { | |
9550d1bd RH |
12125 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && |
12126 | FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) | |
12127 | != env->v7m.secure) { | |
a729a46b | 12128 | DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1); |
9550d1bd RH |
12129 | } |
12130 | ||
12131 | if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && | |
12132 | (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || | |
12133 | (env->v7m.secure && | |
12134 | !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { | |
12135 | /* | |
12136 | * ASPEN is set, but FPCA/SFPA indicate that there is no | |
12137 | * active FP context; we must create a new FP context before | |
12138 | * executing any FP insn. | |
12139 | */ | |
a729a46b | 12140 | DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1); |
9550d1bd RH |
12141 | } |
12142 | ||
12143 | bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; | |
12144 | if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { | |
a729a46b | 12145 | DP_TBFLAG_M32(flags, LSPACT, 1); |
9550d1bd | 12146 | } |
26702213 PM |
12147 | |
12148 | if (mve_no_pred(env)) { | |
12149 | DP_TBFLAG_M32(flags, MVE_NO_PRED, 1); | |
12150 | } | |
6e33ced5 | 12151 | } else { |
bbad7c62 RH |
12152 | /* |
12153 | * Note that XSCALE_CPAR shares bits with VECSTRIDE. | |
12154 | * Note that VECLEN+VECSTRIDE are RES0 for M-profile. | |
12155 | */ | |
12156 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
a729a46b | 12157 | DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); |
bbad7c62 | 12158 | } else { |
a729a46b RH |
12159 | DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); |
12160 | DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); | |
bbad7c62 | 12161 | } |
0a54d68e | 12162 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { |
a729a46b | 12163 | DP_TBFLAG_A32(flags, VFPEN, 1); |
0a54d68e | 12164 | } |
6e33ced5 RH |
12165 | } |
12166 | ||
a729a46b RH |
12167 | DP_TBFLAG_AM32(flags, THUMB, env->thumb); |
12168 | DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits); | |
d4d7503a | 12169 | } |
a9e01311 | 12170 | |
60e12c37 RH |
12171 | /* |
12172 | * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine | |
a9e01311 RH |
12173 | * states defined in the ARM ARM for software singlestep: |
12174 | * SS_ACTIVE PSTATE.SS State | |
12175 | * 0 x Inactive (the TB flag for SS is always 0) | |
12176 | * 1 0 Active-pending | |
12177 | * 1 1 Active-not-pending | |
ae6eb1e9 | 12178 | * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. |
a9e01311 | 12179 | */ |
a729a46b RH |
12180 | if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { |
12181 | DP_TBFLAG_ANY(flags, PSTATE__SS, 1); | |
a9e01311 | 12182 | } |
a9e01311 | 12183 | |
3902bfc6 | 12184 | *pflags = flags.flags; |
a378206a | 12185 | *cs_base = flags.flags2; |
a9e01311 | 12186 | } |
0ab5953b RH |
12187 | |
12188 | #ifdef TARGET_AARCH64 | |
12189 | /* | |
12190 | * The manual says that when SVE is enabled and VQ is widened the | |
12191 | * implementation is allowed to zero the previously inaccessible | |
12192 | * portion of the registers. The corollary to that is that when | |
12193 | * SVE is enabled and VQ is narrowed we are also allowed to zero | |
12194 | * the now inaccessible portion of the registers. | |
12195 | * | |
12196 | * The intent of this is that no predicate bit beyond VQ is ever set. | |
12197 | * Which means that some operations on predicate registers themselves | |
12198 | * may operate on full uint64_t or even unrolled across the maximum | |
12199 | * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally | |
12200 | * may well be cheaper than conditionals to restrict the operation | |
12201 | * to the relevant portion of a uint16_t[16]. | |
12202 | */ | |
12203 | void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) | |
12204 | { | |
12205 | int i, j; | |
12206 | uint64_t pmask; | |
12207 | ||
12208 | assert(vq >= 1 && vq <= ARM_MAX_VQ); | |
2fc0cc0e | 12209 | assert(vq <= env_archcpu(env)->sve_max_vq); |
0ab5953b RH |
12210 | |
12211 | /* Zap the high bits of the zregs. */ | |
12212 | for (i = 0; i < 32; i++) { | |
12213 | memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)); | |
12214 | } | |
12215 | ||
12216 | /* Zap the high bits of the pregs and ffr. */ | |
12217 | pmask = 0; | |
12218 | if (vq & 3) { | |
12219 | pmask = ~(-1ULL << (16 * (vq & 3))); | |
12220 | } | |
12221 | for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) { | |
12222 | for (i = 0; i < 17; ++i) { | |
12223 | env->vfp.pregs[i].p[j] &= pmask; | |
12224 | } | |
12225 | pmask = 0; | |
12226 | } | |
12227 | } | |
12228 | ||
6a775fd6 RH |
12229 | static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState *env, int el, bool sm) |
12230 | { | |
12231 | int exc_el; | |
12232 | ||
12233 | if (sm) { | |
12234 | exc_el = sme_exception_el(env, el); | |
12235 | } else { | |
12236 | exc_el = sve_exception_el(env, el); | |
12237 | } | |
12238 | if (exc_el) { | |
12239 | return 0; /* disabled */ | |
12240 | } | |
12241 | return sve_vqm1_for_el_sm(env, el, sm); | |
12242 | } | |
12243 | ||
0ab5953b RH |
12244 | /* |
12245 | * Notice a change in SVE vector size when changing EL. | |
12246 | */ | |
9a05f7b6 RH |
12247 | void aarch64_sve_change_el(CPUARMState *env, int old_el, |
12248 | int new_el, bool el0_a64) | |
0ab5953b | 12249 | { |
2fc0cc0e | 12250 | ARMCPU *cpu = env_archcpu(env); |
0ab5953b | 12251 | int old_len, new_len; |
6a775fd6 | 12252 | bool old_a64, new_a64, sm; |
0ab5953b RH |
12253 | |
12254 | /* Nothing to do if no SVE. */ | |
cd208a1c | 12255 | if (!cpu_isar_feature(aa64_sve, cpu)) { |
0ab5953b RH |
12256 | return; |
12257 | } | |
12258 | ||
12259 | /* Nothing to do if FP is disabled in either EL. */ | |
12260 | if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) { | |
12261 | return; | |
12262 | } | |
12263 | ||
04fbce76 RH |
12264 | old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; |
12265 | new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; | |
12266 | ||
12267 | /* | |
12268 | * Both AArch64.TakeException and AArch64.ExceptionReturn | |
12269 | * invoke ResetSVEState when taking an exception from, or | |
12270 | * returning to, AArch32 state when PSTATE.SM is enabled. | |
12271 | */ | |
6a775fd6 RH |
12272 | sm = FIELD_EX64(env->svcr, SVCR, SM); |
12273 | if (old_a64 != new_a64 && sm) { | |
04fbce76 RH |
12274 | arm_reset_sve_state(env); |
12275 | return; | |
12276 | } | |
12277 | ||
0ab5953b RH |
12278 | /* |
12279 | * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped | |
12280 | * at ELx, or not available because the EL is in AArch32 state, then | |
12281 | * for all purposes other than a direct read, the ZCR_ELx.LEN field | |
12282 | * has an effective value of 0". | |
12283 | * | |
12284 | * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0). | |
12285 | * If we ignore aa32 state, we would fail to see the vq4->vq0 transition | |
12286 | * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that | |
12287 | * we already have the correct register contents when encountering the | |
12288 | * vq0->vq0 transition between EL0->EL1. | |
12289 | */ | |
6a775fd6 RH |
12290 | old_len = new_len = 0; |
12291 | if (old_a64) { | |
12292 | old_len = sve_vqm1_for_el_sm_ena(env, old_el, sm); | |
12293 | } | |
12294 | if (new_a64) { | |
12295 | new_len = sve_vqm1_for_el_sm_ena(env, new_el, sm); | |
12296 | } | |
0ab5953b RH |
12297 | |
12298 | /* When changing vector length, clear inaccessible state. */ | |
12299 | if (new_len < old_len) { | |
12300 | aarch64_sve_narrow_vq(env, new_len + 1); | |
12301 | } | |
12302 | } | |
12303 | #endif | |
5d28ac0c RH |
12304 | |
12305 | #ifndef CONFIG_USER_ONLY | |
12306 | ARMSecuritySpace arm_security_space(CPUARMState *env) | |
12307 | { | |
12308 | if (arm_feature(env, ARM_FEATURE_M)) { | |
12309 | return arm_secure_to_space(env->v7m.secure); | |
12310 | } | |
12311 | ||
12312 | /* | |
12313 | * If EL3 is not supported then the secure state is implementation | |
12314 | * defined, in which case QEMU defaults to non-secure. | |
12315 | */ | |
12316 | if (!arm_feature(env, ARM_FEATURE_EL3)) { | |
12317 | return ARMSS_NonSecure; | |
12318 | } | |
12319 | ||
12320 | /* Check for AArch64 EL3 or AArch32 Mon. */ | |
12321 | if (is_a64(env)) { | |
12322 | if (extract32(env->pstate, 2, 2) == 3) { | |
12323 | if (cpu_isar_feature(aa64_rme, env_archcpu(env))) { | |
12324 | return ARMSS_Root; | |
12325 | } else { | |
12326 | return ARMSS_Secure; | |
12327 | } | |
12328 | } | |
12329 | } else { | |
12330 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
12331 | return ARMSS_Secure; | |
12332 | } | |
12333 | } | |
12334 | ||
12335 | return arm_security_space_below_el3(env); | |
12336 | } | |
12337 | ||
12338 | ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) | |
12339 | { | |
12340 | assert(!arm_feature(env, ARM_FEATURE_M)); | |
12341 | ||
12342 | /* | |
12343 | * If EL3 is not supported then the secure state is implementation | |
12344 | * defined, in which case QEMU defaults to non-secure. | |
12345 | */ | |
12346 | if (!arm_feature(env, ARM_FEATURE_EL3)) { | |
12347 | return ARMSS_NonSecure; | |
12348 | } | |
12349 | ||
12350 | /* | |
12351 | * Note NSE cannot be set without RME, and NSE & !NS is Reserved. | |
12352 | * Ignoring NSE when !NS retains consistency without having to | |
12353 | * modify other predicates. | |
12354 | */ | |
12355 | if (!(env->cp15.scr_el3 & SCR_NS)) { | |
12356 | return ARMSS_Secure; | |
12357 | } else if (env->cp15.scr_el3 & SCR_NSE) { | |
12358 | return ARMSS_Realm; | |
12359 | } else { | |
12360 | return ARMSS_NonSecure; | |
12361 | } | |
12362 | } | |
12363 | #endif /* !CONFIG_USER_ONLY */ |