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Commit | Line | Data |
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ed3baad1 PMD |
1 | /* |
2 | * ARM generic helpers. | |
3 | * | |
4 | * This code is licensed under the GNU GPL v2 or later. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0-or-later | |
7 | */ | |
db725815 | 8 | |
74c21bd0 | 9 | #include "qemu/osdep.h" |
63159601 | 10 | #include "qemu/units.h" |
181962fd | 11 | #include "target/arm/idau.h" |
194cbc49 | 12 | #include "trace.h" |
b5ff1b31 | 13 | #include "cpu.h" |
ccd38087 | 14 | #include "internals.h" |
022c62cb | 15 | #include "exec/gdbstub.h" |
2ef6175a | 16 | #include "exec/helper-proto.h" |
1de7afc9 | 17 | #include "qemu/host-utils.h" |
db725815 | 18 | #include "qemu/main-loop.h" |
1de7afc9 | 19 | #include "qemu/bitops.h" |
eb0ecd5a | 20 | #include "qemu/crc32c.h" |
0442428a | 21 | #include "qemu/qemu-print.h" |
63c91552 | 22 | #include "exec/exec-all.h" |
eb0ecd5a | 23 | #include <zlib.h> /* For crc32 */ |
64552b6b | 24 | #include "hw/irq.h" |
f1672e6f | 25 | #include "hw/semihosting/semihost.h" |
b2e23725 | 26 | #include "sysemu/cpus.h" |
f3a9b694 | 27 | #include "sysemu/kvm.h" |
9d2b5a58 | 28 | #include "qemu/range.h" |
7f7b4e7a | 29 | #include "qapi/qapi-commands-machine-target.h" |
de390645 RH |
30 | #include "qapi/error.h" |
31 | #include "qemu/guest-random.h" | |
91f78c58 PMD |
32 | #ifdef CONFIG_TCG |
33 | #include "arm_ldst.h" | |
7aab5a8c | 34 | #include "exec/cpu_ldst.h" |
91f78c58 | 35 | #endif |
0b03bdfc | 36 | |
352c98e5 LV |
37 | #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ |
38 | ||
4a501606 | 39 | #ifndef CONFIG_USER_ONLY |
7c2cb42b | 40 | |
37785977 | 41 | static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
03ae85f8 | 42 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
37785977 | 43 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, |
da909b2c | 44 | target_ulong *page_size_ptr, |
5b2d261d | 45 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); |
4a501606 PM |
46 | #endif |
47 | ||
affdb64d PM |
48 | static void switch_mode(CPUARMState *env, int mode); |
49 | ||
0ecb72a5 | 50 | static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
51 | { |
52 | int nregs; | |
53 | ||
54 | /* VFP data registers are always little-endian. */ | |
55 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
56 | if (reg < nregs) { | |
9a2b5256 | 57 | stq_le_p(buf, *aa32_vfp_dreg(env, reg)); |
56aebc89 PB |
58 | return 8; |
59 | } | |
60 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
61 | /* Aliases for Q regs. */ | |
62 | nregs += 16; | |
63 | if (reg < nregs) { | |
9a2b5256 RH |
64 | uint64_t *q = aa32_vfp_qreg(env, reg - 32); |
65 | stq_le_p(buf, q[0]); | |
66 | stq_le_p(buf + 8, q[1]); | |
56aebc89 PB |
67 | return 16; |
68 | } | |
69 | } | |
70 | switch (reg - nregs) { | |
71 | case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; | |
b0a909a4 | 72 | case 1: stl_p(buf, vfp_get_fpscr(env)); return 4; |
56aebc89 PB |
73 | case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; |
74 | } | |
75 | return 0; | |
76 | } | |
77 | ||
0ecb72a5 | 78 | static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
79 | { |
80 | int nregs; | |
81 | ||
82 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
83 | if (reg < nregs) { | |
9a2b5256 | 84 | *aa32_vfp_dreg(env, reg) = ldq_le_p(buf); |
56aebc89 PB |
85 | return 8; |
86 | } | |
87 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
88 | nregs += 16; | |
89 | if (reg < nregs) { | |
9a2b5256 RH |
90 | uint64_t *q = aa32_vfp_qreg(env, reg - 32); |
91 | q[0] = ldq_le_p(buf); | |
92 | q[1] = ldq_le_p(buf + 8); | |
56aebc89 PB |
93 | return 16; |
94 | } | |
95 | } | |
96 | switch (reg - nregs) { | |
97 | case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; | |
b0a909a4 | 98 | case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4; |
71b3c3de | 99 | case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
56aebc89 PB |
100 | } |
101 | return 0; | |
102 | } | |
103 | ||
6a669427 PM |
104 | static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
105 | { | |
106 | switch (reg) { | |
107 | case 0 ... 31: | |
108 | /* 128 bit FP register */ | |
9a2b5256 RH |
109 | { |
110 | uint64_t *q = aa64_vfp_qreg(env, reg); | |
111 | stq_le_p(buf, q[0]); | |
112 | stq_le_p(buf + 8, q[1]); | |
113 | return 16; | |
114 | } | |
6a669427 PM |
115 | case 32: |
116 | /* FPSR */ | |
117 | stl_p(buf, vfp_get_fpsr(env)); | |
118 | return 4; | |
119 | case 33: | |
120 | /* FPCR */ | |
121 | stl_p(buf, vfp_get_fpcr(env)); | |
122 | return 4; | |
123 | default: | |
124 | return 0; | |
125 | } | |
126 | } | |
127 | ||
128 | static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) | |
129 | { | |
130 | switch (reg) { | |
131 | case 0 ... 31: | |
132 | /* 128 bit FP register */ | |
9a2b5256 RH |
133 | { |
134 | uint64_t *q = aa64_vfp_qreg(env, reg); | |
135 | q[0] = ldq_le_p(buf); | |
136 | q[1] = ldq_le_p(buf + 8); | |
137 | return 16; | |
138 | } | |
6a669427 PM |
139 | case 32: |
140 | /* FPSR */ | |
141 | vfp_set_fpsr(env, ldl_p(buf)); | |
142 | return 4; | |
143 | case 33: | |
144 | /* FPCR */ | |
145 | vfp_set_fpcr(env, ldl_p(buf)); | |
146 | return 4; | |
147 | default: | |
148 | return 0; | |
149 | } | |
150 | } | |
151 | ||
c4241c7d | 152 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) |
d4e6df63 | 153 | { |
375421cc | 154 | assert(ri->fieldoffset); |
67ed771d | 155 | if (cpreg_field_is_64bit(ri)) { |
c4241c7d | 156 | return CPREG_FIELD64(env, ri); |
22d9e1a9 | 157 | } else { |
c4241c7d | 158 | return CPREG_FIELD32(env, ri); |
22d9e1a9 | 159 | } |
d4e6df63 PM |
160 | } |
161 | ||
c4241c7d PM |
162 | static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
163 | uint64_t value) | |
d4e6df63 | 164 | { |
375421cc | 165 | assert(ri->fieldoffset); |
67ed771d | 166 | if (cpreg_field_is_64bit(ri)) { |
22d9e1a9 PM |
167 | CPREG_FIELD64(env, ri) = value; |
168 | } else { | |
169 | CPREG_FIELD32(env, ri) = value; | |
170 | } | |
d4e6df63 PM |
171 | } |
172 | ||
11f136ee FA |
173 | static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) |
174 | { | |
175 | return (char *)env + ri->fieldoffset; | |
176 | } | |
177 | ||
49a66191 | 178 | uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) |
721fae12 | 179 | { |
59a1c327 | 180 | /* Raw read of a coprocessor register (as needed for migration, etc). */ |
721fae12 | 181 | if (ri->type & ARM_CP_CONST) { |
59a1c327 | 182 | return ri->resetvalue; |
721fae12 | 183 | } else if (ri->raw_readfn) { |
59a1c327 | 184 | return ri->raw_readfn(env, ri); |
721fae12 | 185 | } else if (ri->readfn) { |
59a1c327 | 186 | return ri->readfn(env, ri); |
721fae12 | 187 | } else { |
59a1c327 | 188 | return raw_read(env, ri); |
721fae12 | 189 | } |
721fae12 PM |
190 | } |
191 | ||
59a1c327 | 192 | static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, |
7900e9f1 | 193 | uint64_t v) |
721fae12 PM |
194 | { |
195 | /* Raw write of a coprocessor register (as needed for migration, etc). | |
721fae12 PM |
196 | * Note that constant registers are treated as write-ignored; the |
197 | * caller should check for success by whether a readback gives the | |
198 | * value written. | |
199 | */ | |
200 | if (ri->type & ARM_CP_CONST) { | |
59a1c327 | 201 | return; |
721fae12 | 202 | } else if (ri->raw_writefn) { |
c4241c7d | 203 | ri->raw_writefn(env, ri, v); |
721fae12 | 204 | } else if (ri->writefn) { |
c4241c7d | 205 | ri->writefn(env, ri, v); |
721fae12 | 206 | } else { |
afb2530f | 207 | raw_write(env, ri, v); |
721fae12 | 208 | } |
721fae12 PM |
209 | } |
210 | ||
200bf5b7 AB |
211 | static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg) |
212 | { | |
2fc0cc0e | 213 | ARMCPU *cpu = env_archcpu(env); |
200bf5b7 AB |
214 | const ARMCPRegInfo *ri; |
215 | uint32_t key; | |
216 | ||
217 | key = cpu->dyn_xml.cpregs_keys[reg]; | |
218 | ri = get_arm_cp_reginfo(cpu->cp_regs, key); | |
219 | if (ri) { | |
220 | if (cpreg_field_is_64bit(ri)) { | |
221 | return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); | |
222 | } else { | |
223 | return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); | |
224 | } | |
225 | } | |
226 | return 0; | |
227 | } | |
228 | ||
229 | static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) | |
230 | { | |
231 | return 0; | |
232 | } | |
233 | ||
375421cc PM |
234 | static bool raw_accessors_invalid(const ARMCPRegInfo *ri) |
235 | { | |
236 | /* Return true if the regdef would cause an assertion if you called | |
237 | * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a | |
238 | * program bug for it not to have the NO_RAW flag). | |
239 | * NB that returning false here doesn't necessarily mean that calling | |
240 | * read/write_raw_cp_reg() is safe, because we can't distinguish "has | |
241 | * read/write access functions which are safe for raw use" from "has | |
242 | * read/write access functions which have side effects but has forgotten | |
243 | * to provide raw access functions". | |
244 | * The tests here line up with the conditions in read/write_raw_cp_reg() | |
245 | * and assertions in raw_read()/raw_write(). | |
246 | */ | |
247 | if ((ri->type & ARM_CP_CONST) || | |
248 | ri->fieldoffset || | |
249 | ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { | |
250 | return false; | |
251 | } | |
252 | return true; | |
253 | } | |
254 | ||
b698e4ee | 255 | bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync) |
721fae12 PM |
256 | { |
257 | /* Write the coprocessor state from cpu->env to the (index,value) list. */ | |
258 | int i; | |
259 | bool ok = true; | |
260 | ||
261 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
262 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
263 | const ARMCPRegInfo *ri; | |
b698e4ee | 264 | uint64_t newval; |
59a1c327 | 265 | |
60322b39 | 266 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
267 | if (!ri) { |
268 | ok = false; | |
269 | continue; | |
270 | } | |
7a0e58fa | 271 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
272 | continue; |
273 | } | |
b698e4ee PM |
274 | |
275 | newval = read_raw_cp_reg(&cpu->env, ri); | |
276 | if (kvm_sync) { | |
277 | /* | |
278 | * Only sync if the previous list->cpustate sync succeeded. | |
279 | * Rather than tracking the success/failure state for every | |
280 | * item in the list, we just recheck "does the raw write we must | |
281 | * have made in write_list_to_cpustate() read back OK" here. | |
282 | */ | |
283 | uint64_t oldval = cpu->cpreg_values[i]; | |
284 | ||
285 | if (oldval == newval) { | |
286 | continue; | |
287 | } | |
288 | ||
289 | write_raw_cp_reg(&cpu->env, ri, oldval); | |
290 | if (read_raw_cp_reg(&cpu->env, ri) != oldval) { | |
291 | continue; | |
292 | } | |
293 | ||
294 | write_raw_cp_reg(&cpu->env, ri, newval); | |
295 | } | |
296 | cpu->cpreg_values[i] = newval; | |
721fae12 PM |
297 | } |
298 | return ok; | |
299 | } | |
300 | ||
301 | bool write_list_to_cpustate(ARMCPU *cpu) | |
302 | { | |
303 | int i; | |
304 | bool ok = true; | |
305 | ||
306 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
307 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
308 | uint64_t v = cpu->cpreg_values[i]; | |
721fae12 PM |
309 | const ARMCPRegInfo *ri; |
310 | ||
60322b39 | 311 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
312 | if (!ri) { |
313 | ok = false; | |
314 | continue; | |
315 | } | |
7a0e58fa | 316 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
317 | continue; |
318 | } | |
319 | /* Write value and confirm it reads back as written | |
320 | * (to catch read-only registers and partially read-only | |
321 | * registers where the incoming migration value doesn't match) | |
322 | */ | |
59a1c327 PM |
323 | write_raw_cp_reg(&cpu->env, ri, v); |
324 | if (read_raw_cp_reg(&cpu->env, ri) != v) { | |
721fae12 PM |
325 | ok = false; |
326 | } | |
327 | } | |
328 | return ok; | |
329 | } | |
330 | ||
331 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | |
332 | { | |
333 | ARMCPU *cpu = opaque; | |
334 | uint64_t regidx; | |
335 | const ARMCPRegInfo *ri; | |
336 | ||
337 | regidx = *(uint32_t *)key; | |
60322b39 | 338 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 | 339 | |
7a0e58fa | 340 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
341 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); |
342 | /* The value array need not be initialized at this point */ | |
343 | cpu->cpreg_array_len++; | |
344 | } | |
345 | } | |
346 | ||
347 | static void count_cpreg(gpointer key, gpointer opaque) | |
348 | { | |
349 | ARMCPU *cpu = opaque; | |
350 | uint64_t regidx; | |
351 | const ARMCPRegInfo *ri; | |
352 | ||
353 | regidx = *(uint32_t *)key; | |
60322b39 | 354 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 | 355 | |
7a0e58fa | 356 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
357 | cpu->cpreg_array_len++; |
358 | } | |
359 | } | |
360 | ||
361 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | |
362 | { | |
cbf239b7 AR |
363 | uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); |
364 | uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); | |
721fae12 | 365 | |
cbf239b7 AR |
366 | if (aidx > bidx) { |
367 | return 1; | |
368 | } | |
369 | if (aidx < bidx) { | |
370 | return -1; | |
371 | } | |
372 | return 0; | |
721fae12 PM |
373 | } |
374 | ||
375 | void init_cpreg_list(ARMCPU *cpu) | |
376 | { | |
377 | /* Initialise the cpreg_tuples[] array based on the cp_regs hash. | |
378 | * Note that we require cpreg_tuples[] to be sorted by key ID. | |
379 | */ | |
57b6d95e | 380 | GList *keys; |
721fae12 PM |
381 | int arraylen; |
382 | ||
57b6d95e | 383 | keys = g_hash_table_get_keys(cpu->cp_regs); |
721fae12 PM |
384 | keys = g_list_sort(keys, cpreg_key_compare); |
385 | ||
386 | cpu->cpreg_array_len = 0; | |
387 | ||
388 | g_list_foreach(keys, count_cpreg, cpu); | |
389 | ||
390 | arraylen = cpu->cpreg_array_len; | |
391 | cpu->cpreg_indexes = g_new(uint64_t, arraylen); | |
392 | cpu->cpreg_values = g_new(uint64_t, arraylen); | |
393 | cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); | |
394 | cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); | |
395 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; | |
396 | cpu->cpreg_array_len = 0; | |
397 | ||
398 | g_list_foreach(keys, add_cpreg_to_list, cpu); | |
399 | ||
400 | assert(cpu->cpreg_array_len == arraylen); | |
401 | ||
402 | g_list_free(keys); | |
403 | } | |
404 | ||
68e9c2fe EI |
405 | /* |
406 | * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but | |
407 | * they are accessible when EL3 is using AArch64 regardless of EL3.NS. | |
408 | * | |
409 | * access_el3_aa32ns: Used to check AArch32 register views. | |
410 | * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views. | |
411 | */ | |
412 | static CPAccessResult access_el3_aa32ns(CPUARMState *env, | |
3f208fd7 PM |
413 | const ARMCPRegInfo *ri, |
414 | bool isread) | |
68e9c2fe EI |
415 | { |
416 | bool secure = arm_is_secure_below_el3(env); | |
417 | ||
418 | assert(!arm_el_is_aa64(env, 3)); | |
419 | if (secure) { | |
420 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
421 | } | |
422 | return CP_ACCESS_OK; | |
423 | } | |
424 | ||
425 | static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env, | |
3f208fd7 PM |
426 | const ARMCPRegInfo *ri, |
427 | bool isread) | |
68e9c2fe EI |
428 | { |
429 | if (!arm_el_is_aa64(env, 3)) { | |
3f208fd7 | 430 | return access_el3_aa32ns(env, ri, isread); |
68e9c2fe EI |
431 | } |
432 | return CP_ACCESS_OK; | |
433 | } | |
434 | ||
5513c3ab PM |
435 | /* Some secure-only AArch32 registers trap to EL3 if used from |
436 | * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). | |
437 | * Note that an access from Secure EL1 can only happen if EL3 is AArch64. | |
438 | * We assume that the .access field is set to PL1_RW. | |
439 | */ | |
440 | static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, | |
3f208fd7 PM |
441 | const ARMCPRegInfo *ri, |
442 | bool isread) | |
5513c3ab PM |
443 | { |
444 | if (arm_current_el(env) == 3) { | |
445 | return CP_ACCESS_OK; | |
446 | } | |
447 | if (arm_is_secure_below_el3(env)) { | |
448 | return CP_ACCESS_TRAP_EL3; | |
449 | } | |
450 | /* This will be EL1 NS and EL2 NS, which just UNDEF */ | |
451 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
452 | } | |
453 | ||
187f678d PM |
454 | /* Check for traps to "powerdown debug" registers, which are controlled |
455 | * by MDCR.TDOSA | |
456 | */ | |
457 | static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, | |
458 | bool isread) | |
459 | { | |
460 | int el = arm_current_el(env); | |
30ac6339 PM |
461 | bool mdcr_el2_tdosa = (env->cp15.mdcr_el2 & MDCR_TDOSA) || |
462 | (env->cp15.mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 463 | (arm_hcr_el2_eff(env) & HCR_TGE); |
187f678d | 464 | |
30ac6339 | 465 | if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) { |
187f678d PM |
466 | return CP_ACCESS_TRAP_EL2; |
467 | } | |
468 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { | |
469 | return CP_ACCESS_TRAP_EL3; | |
470 | } | |
471 | return CP_ACCESS_OK; | |
472 | } | |
473 | ||
91b0a238 PM |
474 | /* Check for traps to "debug ROM" registers, which are controlled |
475 | * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. | |
476 | */ | |
477 | static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, | |
478 | bool isread) | |
479 | { | |
480 | int el = arm_current_el(env); | |
30ac6339 PM |
481 | bool mdcr_el2_tdra = (env->cp15.mdcr_el2 & MDCR_TDRA) || |
482 | (env->cp15.mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 483 | (arm_hcr_el2_eff(env) & HCR_TGE); |
91b0a238 | 484 | |
30ac6339 | 485 | if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) { |
91b0a238 PM |
486 | return CP_ACCESS_TRAP_EL2; |
487 | } | |
488 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
489 | return CP_ACCESS_TRAP_EL3; | |
490 | } | |
491 | return CP_ACCESS_OK; | |
492 | } | |
493 | ||
d6c8cf81 PM |
494 | /* Check for traps to general debug registers, which are controlled |
495 | * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. | |
496 | */ | |
497 | static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, | |
498 | bool isread) | |
499 | { | |
500 | int el = arm_current_el(env); | |
30ac6339 PM |
501 | bool mdcr_el2_tda = (env->cp15.mdcr_el2 & MDCR_TDA) || |
502 | (env->cp15.mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 503 | (arm_hcr_el2_eff(env) & HCR_TGE); |
d6c8cf81 | 504 | |
30ac6339 | 505 | if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) { |
d6c8cf81 PM |
506 | return CP_ACCESS_TRAP_EL2; |
507 | } | |
508 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
509 | return CP_ACCESS_TRAP_EL3; | |
510 | } | |
511 | return CP_ACCESS_OK; | |
512 | } | |
513 | ||
1fce1ba9 PM |
514 | /* Check for traps to performance monitor registers, which are controlled |
515 | * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. | |
516 | */ | |
517 | static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, | |
518 | bool isread) | |
519 | { | |
520 | int el = arm_current_el(env); | |
521 | ||
522 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) | |
523 | && !arm_is_secure_below_el3(env)) { | |
524 | return CP_ACCESS_TRAP_EL2; | |
525 | } | |
526 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
527 | return CP_ACCESS_TRAP_EL3; | |
528 | } | |
529 | return CP_ACCESS_OK; | |
530 | } | |
531 | ||
c4241c7d | 532 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
c983fe6c | 533 | { |
2fc0cc0e | 534 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 535 | |
8d5c773e | 536 | raw_write(env, ri, value); |
d10eb08f | 537 | tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ |
c983fe6c PM |
538 | } |
539 | ||
c4241c7d | 540 | static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
08de207b | 541 | { |
2fc0cc0e | 542 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 543 | |
8d5c773e | 544 | if (raw_read(env, ri) != value) { |
08de207b PM |
545 | /* Unlike real hardware the qemu TLB uses virtual addresses, |
546 | * not modified virtual addresses, so this causes a TLB flush. | |
547 | */ | |
d10eb08f | 548 | tlb_flush(CPU(cpu)); |
8d5c773e | 549 | raw_write(env, ri, value); |
08de207b | 550 | } |
08de207b | 551 | } |
c4241c7d PM |
552 | |
553 | static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
554 | uint64_t value) | |
08de207b | 555 | { |
2fc0cc0e | 556 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 557 | |
452a0955 | 558 | if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) |
014406b5 | 559 | && !extended_addresses_enabled(env)) { |
08de207b PM |
560 | /* For VMSA (when not using the LPAE long descriptor page table |
561 | * format) this register includes the ASID, so do a TLB flush. | |
562 | * For PMSA it is purely a process ID and no action is needed. | |
563 | */ | |
d10eb08f | 564 | tlb_flush(CPU(cpu)); |
08de207b | 565 | } |
8d5c773e | 566 | raw_write(env, ri, value); |
08de207b PM |
567 | } |
568 | ||
b4ab8ce9 PM |
569 | /* IS variants of TLB operations must affect all cores */ |
570 | static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
571 | uint64_t value) | |
572 | { | |
29a0af61 | 573 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
574 | |
575 | tlb_flush_all_cpus_synced(cs); | |
576 | } | |
577 | ||
578 | static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
579 | uint64_t value) | |
580 | { | |
29a0af61 | 581 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
582 | |
583 | tlb_flush_all_cpus_synced(cs); | |
584 | } | |
585 | ||
586 | static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
587 | uint64_t value) | |
588 | { | |
29a0af61 | 589 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
590 | |
591 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
592 | } | |
593 | ||
594 | static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
595 | uint64_t value) | |
596 | { | |
29a0af61 | 597 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
598 | |
599 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
600 | } | |
601 | ||
602 | /* | |
603 | * Non-IS variants of TLB operations are upgraded to | |
604 | * IS versions if we are at NS EL1 and HCR_EL2.FB is set to | |
605 | * force broadcast of these operations. | |
606 | */ | |
607 | static bool tlb_force_broadcast(CPUARMState *env) | |
608 | { | |
609 | return (env->cp15.hcr_el2 & HCR_FB) && | |
610 | arm_current_el(env) == 1 && arm_is_secure_below_el3(env); | |
611 | } | |
612 | ||
c4241c7d PM |
613 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
614 | uint64_t value) | |
d929823f PM |
615 | { |
616 | /* Invalidate all (TLBIALL) */ | |
2fc0cc0e | 617 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 618 | |
b4ab8ce9 PM |
619 | if (tlb_force_broadcast(env)) { |
620 | tlbiall_is_write(env, NULL, value); | |
621 | return; | |
622 | } | |
623 | ||
d10eb08f | 624 | tlb_flush(CPU(cpu)); |
d929823f PM |
625 | } |
626 | ||
c4241c7d PM |
627 | static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
628 | uint64_t value) | |
d929823f PM |
629 | { |
630 | /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ | |
2fc0cc0e | 631 | ARMCPU *cpu = env_archcpu(env); |
31b030d4 | 632 | |
b4ab8ce9 PM |
633 | if (tlb_force_broadcast(env)) { |
634 | tlbimva_is_write(env, NULL, value); | |
635 | return; | |
636 | } | |
637 | ||
31b030d4 | 638 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); |
d929823f PM |
639 | } |
640 | ||
c4241c7d PM |
641 | static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
642 | uint64_t value) | |
d929823f PM |
643 | { |
644 | /* Invalidate by ASID (TLBIASID) */ | |
2fc0cc0e | 645 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 646 | |
b4ab8ce9 PM |
647 | if (tlb_force_broadcast(env)) { |
648 | tlbiasid_is_write(env, NULL, value); | |
649 | return; | |
650 | } | |
651 | ||
d10eb08f | 652 | tlb_flush(CPU(cpu)); |
d929823f PM |
653 | } |
654 | ||
c4241c7d PM |
655 | static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
656 | uint64_t value) | |
d929823f PM |
657 | { |
658 | /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ | |
2fc0cc0e | 659 | ARMCPU *cpu = env_archcpu(env); |
31b030d4 | 660 | |
b4ab8ce9 PM |
661 | if (tlb_force_broadcast(env)) { |
662 | tlbimvaa_is_write(env, NULL, value); | |
663 | return; | |
664 | } | |
fa439fc5 | 665 | |
b4ab8ce9 | 666 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); |
fa439fc5 PM |
667 | } |
668 | ||
541ef8c2 SS |
669 | static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, |
670 | uint64_t value) | |
671 | { | |
29a0af61 | 672 | CPUState *cs = env_cpu(env); |
541ef8c2 | 673 | |
0336cbf8 | 674 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
675 | ARMMMUIdxBit_S12NSE1 | |
676 | ARMMMUIdxBit_S12NSE0 | | |
677 | ARMMMUIdxBit_S2NS); | |
541ef8c2 SS |
678 | } |
679 | ||
680 | static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
681 | uint64_t value) | |
682 | { | |
29a0af61 | 683 | CPUState *cs = env_cpu(env); |
541ef8c2 | 684 | |
a67cf277 | 685 | tlb_flush_by_mmuidx_all_cpus_synced(cs, |
8bd5c820 PM |
686 | ARMMMUIdxBit_S12NSE1 | |
687 | ARMMMUIdxBit_S12NSE0 | | |
688 | ARMMMUIdxBit_S2NS); | |
541ef8c2 SS |
689 | } |
690 | ||
691 | static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
692 | uint64_t value) | |
693 | { | |
694 | /* Invalidate by IPA. This has to invalidate any structures that | |
695 | * contain only stage 2 translation information, but does not need | |
696 | * to apply to structures that contain combined stage 1 and stage 2 | |
697 | * translation information. | |
698 | * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. | |
699 | */ | |
29a0af61 | 700 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
701 | uint64_t pageaddr; |
702 | ||
703 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
704 | return; | |
705 | } | |
706 | ||
707 | pageaddr = sextract64(value << 12, 0, 40); | |
708 | ||
8bd5c820 | 709 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); |
541ef8c2 SS |
710 | } |
711 | ||
712 | static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
713 | uint64_t value) | |
714 | { | |
29a0af61 | 715 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
716 | uint64_t pageaddr; |
717 | ||
718 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
719 | return; | |
720 | } | |
721 | ||
722 | pageaddr = sextract64(value << 12, 0, 40); | |
723 | ||
a67cf277 | 724 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 725 | ARMMMUIdxBit_S2NS); |
541ef8c2 SS |
726 | } |
727 | ||
728 | static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
729 | uint64_t value) | |
730 | { | |
29a0af61 | 731 | CPUState *cs = env_cpu(env); |
541ef8c2 | 732 | |
8bd5c820 | 733 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
734 | } |
735 | ||
736 | static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
737 | uint64_t value) | |
738 | { | |
29a0af61 | 739 | CPUState *cs = env_cpu(env); |
541ef8c2 | 740 | |
8bd5c820 | 741 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
742 | } |
743 | ||
744 | static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
745 | uint64_t value) | |
746 | { | |
29a0af61 | 747 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
748 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
749 | ||
8bd5c820 | 750 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
751 | } |
752 | ||
753 | static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
754 | uint64_t value) | |
755 | { | |
29a0af61 | 756 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
757 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
758 | ||
a67cf277 | 759 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 760 | ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
761 | } |
762 | ||
e9aa6c21 | 763 | static const ARMCPRegInfo cp_reginfo[] = { |
54bf36ed FA |
764 | /* Define the secure and non-secure FCSE identifier CP registers |
765 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
766 | * the secure register to be properly reset and migrated. There is also no | |
767 | * v8 EL1 version of the register so the non-secure instance stands alone. | |
768 | */ | |
9c513e78 | 769 | { .name = "FCSEIDR", |
54bf36ed FA |
770 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
771 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, | |
772 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), | |
773 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, | |
9c513e78 | 774 | { .name = "FCSEIDR_S", |
54bf36ed FA |
775 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
776 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
777 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), | |
d4e6df63 | 778 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, |
54bf36ed FA |
779 | /* Define the secure and non-secure context identifier CP registers |
780 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
781 | * the secure register to be properly reset and migrated. In the | |
782 | * non-secure case, the 32-bit register will have reset and migration | |
783 | * disabled during registration as it is handled by the 64-bit instance. | |
784 | */ | |
785 | { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
014406b5 | 786 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
54bf36ed FA |
787 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, |
788 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), | |
789 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, | |
9c513e78 | 790 | { .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32, |
54bf36ed FA |
791 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
792 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
793 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), | |
d4e6df63 | 794 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, |
9449fdf6 PM |
795 | REGINFO_SENTINEL |
796 | }; | |
797 | ||
798 | static const ARMCPRegInfo not_v8_cp_reginfo[] = { | |
799 | /* NB: Some of these registers exist in v8 but with more precise | |
800 | * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). | |
801 | */ | |
802 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
803 | { .name = "DACR", |
804 | .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, | |
805 | .access = PL1_RW, .resetvalue = 0, | |
806 | .writefn = dacr_write, .raw_writefn = raw_write, | |
807 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
808 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a903c449 EI |
809 | /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. |
810 | * For v6 and v5, these mappings are overly broad. | |
4fdd17dd | 811 | */ |
a903c449 EI |
812 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0, |
813 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
814 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1, | |
815 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
816 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4, | |
817 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
818 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8, | |
4fdd17dd | 819 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, |
c4804214 PM |
820 | /* Cache maintenance ops; some of this space may be overridden later. */ |
821 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | |
822 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | |
823 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | |
e9aa6c21 PM |
824 | REGINFO_SENTINEL |
825 | }; | |
826 | ||
7d57f408 PM |
827 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
828 | /* Not all pre-v6 cores implemented this WFI, so this is slightly | |
829 | * over-broad. | |
830 | */ | |
831 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | |
832 | .access = PL1_W, .type = ARM_CP_WFI }, | |
833 | REGINFO_SENTINEL | |
834 | }; | |
835 | ||
836 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | |
837 | /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which | |
838 | * is UNPREDICTABLE; we choose to NOP as most implementations do). | |
839 | */ | |
840 | { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
841 | .access = PL1_W, .type = ARM_CP_WFI }, | |
34f90529 PM |
842 | /* L1 cache lockdown. Not architectural in v6 and earlier but in practice |
843 | * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and | |
844 | * OMAPCP will override this space. | |
845 | */ | |
846 | { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, | |
847 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), | |
848 | .resetvalue = 0 }, | |
849 | { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, | |
850 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), | |
851 | .resetvalue = 0 }, | |
776d4e5c PM |
852 | /* v6 doesn't have the cache ID registers but Linux reads them anyway */ |
853 | { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, | |
7a0e58fa | 854 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 855 | .resetvalue = 0 }, |
50300698 PM |
856 | /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; |
857 | * implementing it as RAZ means the "debug architecture version" bits | |
858 | * will read as a reserved value, which should cause Linux to not try | |
859 | * to use the debug hardware. | |
860 | */ | |
861 | { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
862 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
995939a6 PM |
863 | /* MMU TLB control. Note that the wildcarding means we cover not just |
864 | * the unified TLB ops but also the dside/iside/inner-shareable variants. | |
865 | */ | |
866 | { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, | |
867 | .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, | |
7a0e58fa | 868 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
869 | { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, |
870 | .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, | |
7a0e58fa | 871 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
872 | { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, |
873 | .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, | |
7a0e58fa | 874 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
875 | { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, |
876 | .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, | |
7a0e58fa | 877 | .type = ARM_CP_NO_RAW }, |
a903c449 EI |
878 | { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2, |
879 | .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, | |
880 | { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, | |
881 | .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, | |
7d57f408 PM |
882 | REGINFO_SENTINEL |
883 | }; | |
884 | ||
c4241c7d PM |
885 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
886 | uint64_t value) | |
2771db27 | 887 | { |
f0aff255 FA |
888 | uint32_t mask = 0; |
889 | ||
890 | /* In ARMv8 most bits of CPACR_EL1 are RES0. */ | |
891 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
892 | /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. | |
893 | * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. | |
894 | * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. | |
895 | */ | |
896 | if (arm_feature(env, ARM_FEATURE_VFP)) { | |
897 | /* VFP coprocessor: cp10 & cp11 [23:20] */ | |
898 | mask |= (1 << 31) | (1 << 30) | (0xf << 20); | |
899 | ||
900 | if (!arm_feature(env, ARM_FEATURE_NEON)) { | |
901 | /* ASEDIS [31] bit is RAO/WI */ | |
902 | value |= (1 << 31); | |
903 | } | |
904 | ||
905 | /* VFPv3 and upwards with NEON implement 32 double precision | |
906 | * registers (D0-D31). | |
907 | */ | |
908 | if (!arm_feature(env, ARM_FEATURE_NEON) || | |
909 | !arm_feature(env, ARM_FEATURE_VFP3)) { | |
910 | /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ | |
911 | value |= (1 << 30); | |
912 | } | |
913 | } | |
914 | value &= mask; | |
2771db27 | 915 | } |
fc1120a7 PM |
916 | |
917 | /* | |
918 | * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 | |
919 | * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. | |
920 | */ | |
921 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
922 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
923 | value &= ~(0xf << 20); | |
924 | value |= env->cp15.cpacr_el1 & (0xf << 20); | |
925 | } | |
926 | ||
7ebd5f2e | 927 | env->cp15.cpacr_el1 = value; |
2771db27 PM |
928 | } |
929 | ||
fc1120a7 PM |
930 | static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
931 | { | |
932 | /* | |
933 | * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 | |
934 | * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. | |
935 | */ | |
936 | uint64_t value = env->cp15.cpacr_el1; | |
937 | ||
938 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
939 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
940 | value &= ~(0xf << 20); | |
941 | } | |
942 | return value; | |
943 | } | |
944 | ||
945 | ||
5deac39c PM |
946 | static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
947 | { | |
948 | /* Call cpacr_write() so that we reset with the correct RAO bits set | |
949 | * for our CPU features. | |
950 | */ | |
951 | cpacr_write(env, ri, 0); | |
952 | } | |
953 | ||
3f208fd7 PM |
954 | static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
955 | bool isread) | |
c6f19164 GB |
956 | { |
957 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
958 | /* Check if CPACR accesses are to be trapped to EL2 */ | |
959 | if (arm_current_el(env) == 1 && | |
960 | (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) { | |
961 | return CP_ACCESS_TRAP_EL2; | |
962 | /* Check if CPACR accesses are to be trapped to EL3 */ | |
963 | } else if (arm_current_el(env) < 3 && | |
964 | (env->cp15.cptr_el[3] & CPTR_TCPAC)) { | |
965 | return CP_ACCESS_TRAP_EL3; | |
966 | } | |
967 | } | |
968 | ||
969 | return CP_ACCESS_OK; | |
970 | } | |
971 | ||
3f208fd7 PM |
972 | static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
973 | bool isread) | |
c6f19164 GB |
974 | { |
975 | /* Check if CPTR accesses are set to trap to EL3 */ | |
976 | if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) { | |
977 | return CP_ACCESS_TRAP_EL3; | |
978 | } | |
979 | ||
980 | return CP_ACCESS_OK; | |
981 | } | |
982 | ||
7d57f408 PM |
983 | static const ARMCPRegInfo v6_cp_reginfo[] = { |
984 | /* prefetch by MVA in v6, NOP in v7 */ | |
985 | { .name = "MVA_prefetch", | |
986 | .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, | |
987 | .access = PL1_W, .type = ARM_CP_NOP }, | |
6df99dec SS |
988 | /* We need to break the TB after ISB to execute self-modifying code |
989 | * correctly and also to take any pending interrupts immediately. | |
990 | * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. | |
991 | */ | |
7d57f408 | 992 | { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, |
6df99dec | 993 | .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, |
091fd17c | 994 | { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
7d57f408 | 995 | .access = PL0_W, .type = ARM_CP_NOP }, |
091fd17c | 996 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
7d57f408 | 997 | .access = PL0_W, .type = ARM_CP_NOP }, |
06d76f31 | 998 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
6cd8a264 | 999 | .access = PL1_RW, |
b848ce2b FA |
1000 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), |
1001 | offsetof(CPUARMState, cp15.ifar_ns) }, | |
06d76f31 PM |
1002 | .resetvalue = 0, }, |
1003 | /* Watchpoint Fault Address Register : should actually only be present | |
1004 | * for 1136, 1176, 11MPCore. | |
1005 | */ | |
1006 | { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1007 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, | |
34222fb8 | 1008 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, |
c6f19164 | 1009 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, |
7ebd5f2e | 1010 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), |
fc1120a7 | 1011 | .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read }, |
7d57f408 PM |
1012 | REGINFO_SENTINEL |
1013 | }; | |
1014 | ||
7ece99b1 AL |
1015 | /* Definitions for the PMU registers */ |
1016 | #define PMCRN_MASK 0xf800 | |
1017 | #define PMCRN_SHIFT 11 | |
f4efb4b2 | 1018 | #define PMCRLC 0x40 |
033614c4 | 1019 | #define PMCRDP 0x10 |
7ece99b1 AL |
1020 | #define PMCRD 0x8 |
1021 | #define PMCRC 0x4 | |
5ecdd3e4 | 1022 | #define PMCRP 0x2 |
7ece99b1 AL |
1023 | #define PMCRE 0x1 |
1024 | ||
033614c4 AL |
1025 | #define PMXEVTYPER_P 0x80000000 |
1026 | #define PMXEVTYPER_U 0x40000000 | |
1027 | #define PMXEVTYPER_NSK 0x20000000 | |
1028 | #define PMXEVTYPER_NSU 0x10000000 | |
1029 | #define PMXEVTYPER_NSH 0x08000000 | |
1030 | #define PMXEVTYPER_M 0x04000000 | |
1031 | #define PMXEVTYPER_MT 0x02000000 | |
1032 | #define PMXEVTYPER_EVTCOUNT 0x0000ffff | |
1033 | #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \ | |
1034 | PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ | |
1035 | PMXEVTYPER_M | PMXEVTYPER_MT | \ | |
1036 | PMXEVTYPER_EVTCOUNT) | |
1037 | ||
4b8afa1f AL |
1038 | #define PMCCFILTR 0xf8000000 |
1039 | #define PMCCFILTR_M PMXEVTYPER_M | |
1040 | #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) | |
1041 | ||
7ece99b1 AL |
1042 | static inline uint32_t pmu_num_counters(CPUARMState *env) |
1043 | { | |
1044 | return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; | |
1045 | } | |
1046 | ||
1047 | /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ | |
1048 | static inline uint64_t pmu_counter_mask(CPUARMState *env) | |
1049 | { | |
1050 | return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); | |
1051 | } | |
1052 | ||
57a4a11b AL |
1053 | typedef struct pm_event { |
1054 | uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ | |
1055 | /* If the event is supported on this CPU (used to generate PMCEID[01]) */ | |
1056 | bool (*supported)(CPUARMState *); | |
1057 | /* | |
1058 | * Retrieve the current count of the underlying event. The programmed | |
1059 | * counters hold a difference from the return value from this function | |
1060 | */ | |
1061 | uint64_t (*get_count)(CPUARMState *); | |
4e7beb0c AL |
1062 | /* |
1063 | * Return how many nanoseconds it will take (at a minimum) for count events | |
1064 | * to occur. A negative value indicates the counter will never overflow, or | |
1065 | * that the counter has otherwise arranged for the overflow bit to be set | |
1066 | * and the PMU interrupt to be raised on overflow. | |
1067 | */ | |
1068 | int64_t (*ns_per_count)(uint64_t); | |
57a4a11b AL |
1069 | } pm_event; |
1070 | ||
b2e23725 AL |
1071 | static bool event_always_supported(CPUARMState *env) |
1072 | { | |
1073 | return true; | |
1074 | } | |
1075 | ||
0d4bfd7d AL |
1076 | static uint64_t swinc_get_count(CPUARMState *env) |
1077 | { | |
1078 | /* | |
1079 | * SW_INCR events are written directly to the pmevcntr's by writes to | |
1080 | * PMSWINC, so there is no underlying count maintained by the PMU itself | |
1081 | */ | |
1082 | return 0; | |
1083 | } | |
1084 | ||
4e7beb0c AL |
1085 | static int64_t swinc_ns_per(uint64_t ignored) |
1086 | { | |
1087 | return -1; | |
1088 | } | |
1089 | ||
b2e23725 AL |
1090 | /* |
1091 | * Return the underlying cycle count for the PMU cycle counters. If we're in | |
1092 | * usermode, simply return 0. | |
1093 | */ | |
1094 | static uint64_t cycles_get_count(CPUARMState *env) | |
1095 | { | |
1096 | #ifndef CONFIG_USER_ONLY | |
1097 | return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
1098 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); | |
1099 | #else | |
1100 | return cpu_get_host_ticks(); | |
1101 | #endif | |
1102 | } | |
1103 | ||
1104 | #ifndef CONFIG_USER_ONLY | |
4e7beb0c AL |
1105 | static int64_t cycles_ns_per(uint64_t cycles) |
1106 | { | |
1107 | return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles; | |
1108 | } | |
1109 | ||
b2e23725 AL |
1110 | static bool instructions_supported(CPUARMState *env) |
1111 | { | |
1112 | return use_icount == 1 /* Precise instruction counting */; | |
1113 | } | |
1114 | ||
1115 | static uint64_t instructions_get_count(CPUARMState *env) | |
1116 | { | |
1117 | return (uint64_t)cpu_get_icount_raw(); | |
1118 | } | |
4e7beb0c AL |
1119 | |
1120 | static int64_t instructions_ns_per(uint64_t icount) | |
1121 | { | |
1122 | return cpu_icount_to_ns((int64_t)icount); | |
1123 | } | |
b2e23725 AL |
1124 | #endif |
1125 | ||
57a4a11b | 1126 | static const pm_event pm_events[] = { |
0d4bfd7d AL |
1127 | { .number = 0x000, /* SW_INCR */ |
1128 | .supported = event_always_supported, | |
1129 | .get_count = swinc_get_count, | |
4e7beb0c | 1130 | .ns_per_count = swinc_ns_per, |
0d4bfd7d | 1131 | }, |
b2e23725 AL |
1132 | #ifndef CONFIG_USER_ONLY |
1133 | { .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */ | |
1134 | .supported = instructions_supported, | |
1135 | .get_count = instructions_get_count, | |
4e7beb0c | 1136 | .ns_per_count = instructions_ns_per, |
b2e23725 AL |
1137 | }, |
1138 | { .number = 0x011, /* CPU_CYCLES, Cycle */ | |
1139 | .supported = event_always_supported, | |
1140 | .get_count = cycles_get_count, | |
4e7beb0c | 1141 | .ns_per_count = cycles_ns_per, |
b2e23725 AL |
1142 | } |
1143 | #endif | |
57a4a11b AL |
1144 | }; |
1145 | ||
1146 | /* | |
1147 | * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of | |
1148 | * events (i.e. the statistical profiling extension), this implementation | |
1149 | * should first be updated to something sparse instead of the current | |
1150 | * supported_event_map[] array. | |
1151 | */ | |
b2e23725 | 1152 | #define MAX_EVENT_ID 0x11 |
57a4a11b AL |
1153 | #define UNSUPPORTED_EVENT UINT16_MAX |
1154 | static uint16_t supported_event_map[MAX_EVENT_ID + 1]; | |
1155 | ||
1156 | /* | |
bf8d0969 AL |
1157 | * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map |
1158 | * of ARM event numbers to indices in our pm_events array. | |
57a4a11b AL |
1159 | * |
1160 | * Note: Events in the 0x40XX range are not currently supported. | |
1161 | */ | |
bf8d0969 | 1162 | void pmu_init(ARMCPU *cpu) |
57a4a11b | 1163 | { |
57a4a11b AL |
1164 | unsigned int i; |
1165 | ||
bf8d0969 AL |
1166 | /* |
1167 | * Empty supported_event_map and cpu->pmceid[01] before adding supported | |
1168 | * events to them | |
1169 | */ | |
57a4a11b AL |
1170 | for (i = 0; i < ARRAY_SIZE(supported_event_map); i++) { |
1171 | supported_event_map[i] = UNSUPPORTED_EVENT; | |
1172 | } | |
bf8d0969 AL |
1173 | cpu->pmceid0 = 0; |
1174 | cpu->pmceid1 = 0; | |
57a4a11b AL |
1175 | |
1176 | for (i = 0; i < ARRAY_SIZE(pm_events); i++) { | |
1177 | const pm_event *cnt = &pm_events[i]; | |
1178 | assert(cnt->number <= MAX_EVENT_ID); | |
1179 | /* We do not currently support events in the 0x40xx range */ | |
1180 | assert(cnt->number <= 0x3f); | |
1181 | ||
bf8d0969 | 1182 | if (cnt->supported(&cpu->env)) { |
57a4a11b | 1183 | supported_event_map[cnt->number] = i; |
67da43d6 | 1184 | uint64_t event_mask = 1ULL << (cnt->number & 0x1f); |
bf8d0969 AL |
1185 | if (cnt->number & 0x20) { |
1186 | cpu->pmceid1 |= event_mask; | |
1187 | } else { | |
1188 | cpu->pmceid0 |= event_mask; | |
1189 | } | |
57a4a11b AL |
1190 | } |
1191 | } | |
57a4a11b AL |
1192 | } |
1193 | ||
5ecdd3e4 AL |
1194 | /* |
1195 | * Check at runtime whether a PMU event is supported for the current machine | |
1196 | */ | |
1197 | static bool event_supported(uint16_t number) | |
1198 | { | |
1199 | if (number > MAX_EVENT_ID) { | |
1200 | return false; | |
1201 | } | |
1202 | return supported_event_map[number] != UNSUPPORTED_EVENT; | |
1203 | } | |
1204 | ||
3f208fd7 PM |
1205 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1206 | bool isread) | |
200ac0ef | 1207 | { |
3b163b01 | 1208 | /* Performance monitor registers user accessibility is controlled |
1fce1ba9 PM |
1209 | * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable |
1210 | * trapping to EL2 or EL3 for other accesses. | |
200ac0ef | 1211 | */ |
1fce1ba9 PM |
1212 | int el = arm_current_el(env); |
1213 | ||
6ecd0b6b | 1214 | if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { |
fcd25206 | 1215 | return CP_ACCESS_TRAP; |
200ac0ef | 1216 | } |
1fce1ba9 PM |
1217 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) |
1218 | && !arm_is_secure_below_el3(env)) { | |
1219 | return CP_ACCESS_TRAP_EL2; | |
1220 | } | |
1221 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
1222 | return CP_ACCESS_TRAP_EL3; | |
1223 | } | |
1224 | ||
fcd25206 | 1225 | return CP_ACCESS_OK; |
200ac0ef PM |
1226 | } |
1227 | ||
6ecd0b6b AB |
1228 | static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, |
1229 | const ARMCPRegInfo *ri, | |
1230 | bool isread) | |
1231 | { | |
1232 | /* ER: event counter read trap control */ | |
1233 | if (arm_feature(env, ARM_FEATURE_V8) | |
1234 | && arm_current_el(env) == 0 | |
1235 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 | |
1236 | && isread) { | |
1237 | return CP_ACCESS_OK; | |
1238 | } | |
1239 | ||
1240 | return pmreg_access(env, ri, isread); | |
1241 | } | |
1242 | ||
1243 | static CPAccessResult pmreg_access_swinc(CPUARMState *env, | |
1244 | const ARMCPRegInfo *ri, | |
1245 | bool isread) | |
1246 | { | |
1247 | /* SW: software increment write trap control */ | |
1248 | if (arm_feature(env, ARM_FEATURE_V8) | |
1249 | && arm_current_el(env) == 0 | |
1250 | && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 | |
1251 | && !isread) { | |
1252 | return CP_ACCESS_OK; | |
1253 | } | |
1254 | ||
1255 | return pmreg_access(env, ri, isread); | |
1256 | } | |
1257 | ||
6ecd0b6b AB |
1258 | static CPAccessResult pmreg_access_selr(CPUARMState *env, |
1259 | const ARMCPRegInfo *ri, | |
1260 | bool isread) | |
1261 | { | |
1262 | /* ER: event counter read trap control */ | |
1263 | if (arm_feature(env, ARM_FEATURE_V8) | |
1264 | && arm_current_el(env) == 0 | |
1265 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { | |
1266 | return CP_ACCESS_OK; | |
1267 | } | |
1268 | ||
1269 | return pmreg_access(env, ri, isread); | |
1270 | } | |
1271 | ||
1272 | static CPAccessResult pmreg_access_ccntr(CPUARMState *env, | |
1273 | const ARMCPRegInfo *ri, | |
1274 | bool isread) | |
1275 | { | |
1276 | /* CR: cycle counter read trap control */ | |
1277 | if (arm_feature(env, ARM_FEATURE_V8) | |
1278 | && arm_current_el(env) == 0 | |
1279 | && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 | |
1280 | && isread) { | |
1281 | return CP_ACCESS_OK; | |
1282 | } | |
1283 | ||
1284 | return pmreg_access(env, ri, isread); | |
1285 | } | |
1286 | ||
033614c4 AL |
1287 | /* Returns true if the counter (pass 31 for PMCCNTR) should count events using |
1288 | * the current EL, security state, and register configuration. | |
1289 | */ | |
1290 | static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) | |
87124fde | 1291 | { |
033614c4 AL |
1292 | uint64_t filter; |
1293 | bool e, p, u, nsk, nsu, nsh, m; | |
1294 | bool enabled, prohibited, filtered; | |
1295 | bool secure = arm_is_secure(env); | |
1296 | int el = arm_current_el(env); | |
1297 | uint8_t hpmn = env->cp15.mdcr_el2 & MDCR_HPMN; | |
87124fde | 1298 | |
cbbb3041 AJ |
1299 | if (!arm_feature(env, ARM_FEATURE_PMU)) { |
1300 | return false; | |
1301 | } | |
1302 | ||
033614c4 AL |
1303 | if (!arm_feature(env, ARM_FEATURE_EL2) || |
1304 | (counter < hpmn || counter == 31)) { | |
1305 | e = env->cp15.c9_pmcr & PMCRE; | |
1306 | } else { | |
1307 | e = env->cp15.mdcr_el2 & MDCR_HPME; | |
87124fde | 1308 | } |
033614c4 | 1309 | enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); |
87124fde | 1310 | |
033614c4 AL |
1311 | if (!secure) { |
1312 | if (el == 2 && (counter < hpmn || counter == 31)) { | |
1313 | prohibited = env->cp15.mdcr_el2 & MDCR_HPMD; | |
1314 | } else { | |
1315 | prohibited = false; | |
1316 | } | |
1317 | } else { | |
1318 | prohibited = arm_feature(env, ARM_FEATURE_EL3) && | |
1319 | (env->cp15.mdcr_el3 & MDCR_SPME); | |
1320 | } | |
1321 | ||
1322 | if (prohibited && counter == 31) { | |
1323 | prohibited = env->cp15.c9_pmcr & PMCRDP; | |
1324 | } | |
1325 | ||
5ecdd3e4 AL |
1326 | if (counter == 31) { |
1327 | filter = env->cp15.pmccfiltr_el0; | |
1328 | } else { | |
1329 | filter = env->cp15.c14_pmevtyper[counter]; | |
1330 | } | |
033614c4 AL |
1331 | |
1332 | p = filter & PMXEVTYPER_P; | |
1333 | u = filter & PMXEVTYPER_U; | |
1334 | nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); | |
1335 | nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); | |
1336 | nsh = arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); | |
1337 | m = arm_el_is_aa64(env, 1) && | |
1338 | arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); | |
1339 | ||
1340 | if (el == 0) { | |
1341 | filtered = secure ? u : u != nsu; | |
1342 | } else if (el == 1) { | |
1343 | filtered = secure ? p : p != nsk; | |
1344 | } else if (el == 2) { | |
1345 | filtered = !nsh; | |
1346 | } else { /* EL3 */ | |
1347 | filtered = m != p; | |
1348 | } | |
1349 | ||
5ecdd3e4 AL |
1350 | if (counter != 31) { |
1351 | /* | |
1352 | * If not checking PMCCNTR, ensure the counter is setup to an event we | |
1353 | * support | |
1354 | */ | |
1355 | uint16_t event = filter & PMXEVTYPER_EVTCOUNT; | |
1356 | if (!event_supported(event)) { | |
1357 | return false; | |
1358 | } | |
1359 | } | |
1360 | ||
033614c4 | 1361 | return enabled && !prohibited && !filtered; |
87124fde | 1362 | } |
033614c4 | 1363 | |
f4efb4b2 AL |
1364 | static void pmu_update_irq(CPUARMState *env) |
1365 | { | |
2fc0cc0e | 1366 | ARMCPU *cpu = env_archcpu(env); |
f4efb4b2 AL |
1367 | qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && |
1368 | (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); | |
1369 | } | |
1370 | ||
5d05b9d4 AL |
1371 | /* |
1372 | * Ensure c15_ccnt is the guest-visible count so that operations such as | |
1373 | * enabling/disabling the counter or filtering, modifying the count itself, | |
1374 | * etc. can be done logically. This is essentially a no-op if the counter is | |
1375 | * not enabled at the time of the call. | |
1376 | */ | |
f2b2f53f | 1377 | static void pmccntr_op_start(CPUARMState *env) |
ec7b4ce4 | 1378 | { |
b2e23725 | 1379 | uint64_t cycles = cycles_get_count(env); |
ec7b4ce4 | 1380 | |
033614c4 | 1381 | if (pmu_counter_enabled(env, 31)) { |
5d05b9d4 AL |
1382 | uint64_t eff_cycles = cycles; |
1383 | if (env->cp15.c9_pmcr & PMCRD) { | |
1384 | /* Increment once every 64 processor clock cycles */ | |
1385 | eff_cycles /= 64; | |
1386 | } | |
1387 | ||
f4efb4b2 AL |
1388 | uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta; |
1389 | ||
1390 | uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \ | |
1391 | 1ull << 63 : 1ull << 31; | |
1392 | if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { | |
1393 | env->cp15.c9_pmovsr |= (1 << 31); | |
1394 | pmu_update_irq(env); | |
1395 | } | |
1396 | ||
1397 | env->cp15.c15_ccnt = new_pmccntr; | |
ec7b4ce4 | 1398 | } |
5d05b9d4 AL |
1399 | env->cp15.c15_ccnt_delta = cycles; |
1400 | } | |
ec7b4ce4 | 1401 | |
5d05b9d4 AL |
1402 | /* |
1403 | * If PMCCNTR is enabled, recalculate the delta between the clock and the | |
1404 | * guest-visible count. A call to pmccntr_op_finish should follow every call to | |
1405 | * pmccntr_op_start. | |
1406 | */ | |
f2b2f53f | 1407 | static void pmccntr_op_finish(CPUARMState *env) |
5d05b9d4 | 1408 | { |
033614c4 | 1409 | if (pmu_counter_enabled(env, 31)) { |
4e7beb0c AL |
1410 | #ifndef CONFIG_USER_ONLY |
1411 | /* Calculate when the counter will next overflow */ | |
1412 | uint64_t remaining_cycles = -env->cp15.c15_ccnt; | |
1413 | if (!(env->cp15.c9_pmcr & PMCRLC)) { | |
1414 | remaining_cycles = (uint32_t)remaining_cycles; | |
1415 | } | |
1416 | int64_t overflow_in = cycles_ns_per(remaining_cycles); | |
1417 | ||
1418 | if (overflow_in > 0) { | |
1419 | int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
1420 | overflow_in; | |
2fc0cc0e | 1421 | ARMCPU *cpu = env_archcpu(env); |
4e7beb0c AL |
1422 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); |
1423 | } | |
1424 | #endif | |
5d05b9d4 | 1425 | |
4e7beb0c | 1426 | uint64_t prev_cycles = env->cp15.c15_ccnt_delta; |
5d05b9d4 AL |
1427 | if (env->cp15.c9_pmcr & PMCRD) { |
1428 | /* Increment once every 64 processor clock cycles */ | |
1429 | prev_cycles /= 64; | |
1430 | } | |
5d05b9d4 | 1431 | env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt; |
ec7b4ce4 AF |
1432 | } |
1433 | } | |
1434 | ||
5ecdd3e4 AL |
1435 | static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) |
1436 | { | |
1437 | ||
1438 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; | |
1439 | uint64_t count = 0; | |
1440 | if (event_supported(event)) { | |
1441 | uint16_t event_idx = supported_event_map[event]; | |
1442 | count = pm_events[event_idx].get_count(env); | |
1443 | } | |
1444 | ||
1445 | if (pmu_counter_enabled(env, counter)) { | |
f4efb4b2 AL |
1446 | uint32_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter]; |
1447 | ||
1448 | if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & INT32_MIN) { | |
1449 | env->cp15.c9_pmovsr |= (1 << counter); | |
1450 | pmu_update_irq(env); | |
1451 | } | |
1452 | env->cp15.c14_pmevcntr[counter] = new_pmevcntr; | |
5ecdd3e4 AL |
1453 | } |
1454 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1455 | } | |
1456 | ||
1457 | static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) | |
1458 | { | |
1459 | if (pmu_counter_enabled(env, counter)) { | |
4e7beb0c AL |
1460 | #ifndef CONFIG_USER_ONLY |
1461 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; | |
1462 | uint16_t event_idx = supported_event_map[event]; | |
1463 | uint64_t delta = UINT32_MAX - | |
1464 | (uint32_t)env->cp15.c14_pmevcntr[counter] + 1; | |
1465 | int64_t overflow_in = pm_events[event_idx].ns_per_count(delta); | |
1466 | ||
1467 | if (overflow_in > 0) { | |
1468 | int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
1469 | overflow_in; | |
2fc0cc0e | 1470 | ARMCPU *cpu = env_archcpu(env); |
4e7beb0c AL |
1471 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); |
1472 | } | |
1473 | #endif | |
1474 | ||
5ecdd3e4 AL |
1475 | env->cp15.c14_pmevcntr_delta[counter] -= |
1476 | env->cp15.c14_pmevcntr[counter]; | |
1477 | } | |
1478 | } | |
1479 | ||
5d05b9d4 AL |
1480 | void pmu_op_start(CPUARMState *env) |
1481 | { | |
5ecdd3e4 | 1482 | unsigned int i; |
5d05b9d4 | 1483 | pmccntr_op_start(env); |
5ecdd3e4 AL |
1484 | for (i = 0; i < pmu_num_counters(env); i++) { |
1485 | pmevcntr_op_start(env, i); | |
1486 | } | |
5d05b9d4 AL |
1487 | } |
1488 | ||
1489 | void pmu_op_finish(CPUARMState *env) | |
1490 | { | |
5ecdd3e4 | 1491 | unsigned int i; |
5d05b9d4 | 1492 | pmccntr_op_finish(env); |
5ecdd3e4 AL |
1493 | for (i = 0; i < pmu_num_counters(env); i++) { |
1494 | pmevcntr_op_finish(env, i); | |
1495 | } | |
5d05b9d4 AL |
1496 | } |
1497 | ||
033614c4 AL |
1498 | void pmu_pre_el_change(ARMCPU *cpu, void *ignored) |
1499 | { | |
1500 | pmu_op_start(&cpu->env); | |
1501 | } | |
1502 | ||
1503 | void pmu_post_el_change(ARMCPU *cpu, void *ignored) | |
1504 | { | |
1505 | pmu_op_finish(&cpu->env); | |
1506 | } | |
1507 | ||
4e7beb0c AL |
1508 | void arm_pmu_timer_cb(void *opaque) |
1509 | { | |
1510 | ARMCPU *cpu = opaque; | |
1511 | ||
1512 | /* | |
1513 | * Update all the counter values based on the current underlying counts, | |
1514 | * triggering interrupts to be raised, if necessary. pmu_op_finish() also | |
1515 | * has the effect of setting the cpu->pmu_timer to the next earliest time a | |
1516 | * counter may expire. | |
1517 | */ | |
1518 | pmu_op_start(&cpu->env); | |
1519 | pmu_op_finish(&cpu->env); | |
1520 | } | |
1521 | ||
c4241c7d PM |
1522 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1523 | uint64_t value) | |
200ac0ef | 1524 | { |
5d05b9d4 | 1525 | pmu_op_start(env); |
7c2cb42b AF |
1526 | |
1527 | if (value & PMCRC) { | |
1528 | /* The counter has been reset */ | |
1529 | env->cp15.c15_ccnt = 0; | |
1530 | } | |
1531 | ||
5ecdd3e4 AL |
1532 | if (value & PMCRP) { |
1533 | unsigned int i; | |
1534 | for (i = 0; i < pmu_num_counters(env); i++) { | |
1535 | env->cp15.c14_pmevcntr[i] = 0; | |
1536 | } | |
1537 | } | |
1538 | ||
200ac0ef PM |
1539 | /* only the DP, X, D and E bits are writable */ |
1540 | env->cp15.c9_pmcr &= ~0x39; | |
1541 | env->cp15.c9_pmcr |= (value & 0x39); | |
7c2cb42b | 1542 | |
5d05b9d4 | 1543 | pmu_op_finish(env); |
7c2cb42b AF |
1544 | } |
1545 | ||
0d4bfd7d AL |
1546 | static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1547 | uint64_t value) | |
1548 | { | |
1549 | unsigned int i; | |
1550 | for (i = 0; i < pmu_num_counters(env); i++) { | |
1551 | /* Increment a counter's count iff: */ | |
1552 | if ((value & (1 << i)) && /* counter's bit is set */ | |
1553 | /* counter is enabled and not filtered */ | |
1554 | pmu_counter_enabled(env, i) && | |
1555 | /* counter is SW_INCR */ | |
1556 | (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { | |
1557 | pmevcntr_op_start(env, i); | |
f4efb4b2 AL |
1558 | |
1559 | /* | |
1560 | * Detect if this write causes an overflow since we can't predict | |
1561 | * PMSWINC overflows like we can for other events | |
1562 | */ | |
1563 | uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; | |
1564 | ||
1565 | if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { | |
1566 | env->cp15.c9_pmovsr |= (1 << i); | |
1567 | pmu_update_irq(env); | |
1568 | } | |
1569 | ||
1570 | env->cp15.c14_pmevcntr[i] = new_pmswinc; | |
1571 | ||
0d4bfd7d AL |
1572 | pmevcntr_op_finish(env, i); |
1573 | } | |
1574 | } | |
1575 | } | |
1576 | ||
7c2cb42b AF |
1577 | static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1578 | { | |
5d05b9d4 AL |
1579 | uint64_t ret; |
1580 | pmccntr_op_start(env); | |
1581 | ret = env->cp15.c15_ccnt; | |
1582 | pmccntr_op_finish(env); | |
1583 | return ret; | |
7c2cb42b AF |
1584 | } |
1585 | ||
6b040780 WH |
1586 | static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1587 | uint64_t value) | |
1588 | { | |
1589 | /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and | |
1590 | * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the | |
1591 | * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are | |
1592 | * accessed. | |
1593 | */ | |
1594 | env->cp15.c9_pmselr = value & 0x1f; | |
1595 | } | |
1596 | ||
7c2cb42b AF |
1597 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1598 | uint64_t value) | |
1599 | { | |
5d05b9d4 AL |
1600 | pmccntr_op_start(env); |
1601 | env->cp15.c15_ccnt = value; | |
1602 | pmccntr_op_finish(env); | |
200ac0ef | 1603 | } |
421c7ebd PC |
1604 | |
1605 | static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1606 | uint64_t value) | |
1607 | { | |
1608 | uint64_t cur_val = pmccntr_read(env, NULL); | |
1609 | ||
1610 | pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); | |
1611 | } | |
1612 | ||
0614601c AF |
1613 | static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1614 | uint64_t value) | |
1615 | { | |
5d05b9d4 | 1616 | pmccntr_op_start(env); |
4b8afa1f AL |
1617 | env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0; |
1618 | pmccntr_op_finish(env); | |
1619 | } | |
1620 | ||
1621 | static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1622 | uint64_t value) | |
1623 | { | |
1624 | pmccntr_op_start(env); | |
1625 | /* M is not accessible from AArch32 */ | |
1626 | env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | | |
1627 | (value & PMCCFILTR); | |
5d05b9d4 | 1628 | pmccntr_op_finish(env); |
0614601c AF |
1629 | } |
1630 | ||
4b8afa1f AL |
1631 | static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri) |
1632 | { | |
1633 | /* M is not visible in AArch32 */ | |
1634 | return env->cp15.pmccfiltr_el0 & PMCCFILTR; | |
1635 | } | |
1636 | ||
c4241c7d | 1637 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1638 | uint64_t value) |
1639 | { | |
7ece99b1 | 1640 | value &= pmu_counter_mask(env); |
200ac0ef | 1641 | env->cp15.c9_pmcnten |= value; |
200ac0ef PM |
1642 | } |
1643 | ||
c4241c7d PM |
1644 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1645 | uint64_t value) | |
200ac0ef | 1646 | { |
7ece99b1 | 1647 | value &= pmu_counter_mask(env); |
200ac0ef | 1648 | env->cp15.c9_pmcnten &= ~value; |
200ac0ef PM |
1649 | } |
1650 | ||
c4241c7d PM |
1651 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1652 | uint64_t value) | |
200ac0ef | 1653 | { |
599b71e2 | 1654 | value &= pmu_counter_mask(env); |
200ac0ef | 1655 | env->cp15.c9_pmovsr &= ~value; |
f4efb4b2 | 1656 | pmu_update_irq(env); |
200ac0ef PM |
1657 | } |
1658 | ||
327dd510 AL |
1659 | static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1660 | uint64_t value) | |
1661 | { | |
1662 | value &= pmu_counter_mask(env); | |
1663 | env->cp15.c9_pmovsr |= value; | |
f4efb4b2 | 1664 | pmu_update_irq(env); |
327dd510 AL |
1665 | } |
1666 | ||
5ecdd3e4 AL |
1667 | static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1668 | uint64_t value, const uint8_t counter) | |
200ac0ef | 1669 | { |
5ecdd3e4 AL |
1670 | if (counter == 31) { |
1671 | pmccfiltr_write(env, ri, value); | |
1672 | } else if (counter < pmu_num_counters(env)) { | |
1673 | pmevcntr_op_start(env, counter); | |
1674 | ||
1675 | /* | |
1676 | * If this counter's event type is changing, store the current | |
1677 | * underlying count for the new type in c14_pmevcntr_delta[counter] so | |
1678 | * pmevcntr_op_finish has the correct baseline when it converts back to | |
1679 | * a delta. | |
1680 | */ | |
1681 | uint16_t old_event = env->cp15.c14_pmevtyper[counter] & | |
1682 | PMXEVTYPER_EVTCOUNT; | |
1683 | uint16_t new_event = value & PMXEVTYPER_EVTCOUNT; | |
1684 | if (old_event != new_event) { | |
1685 | uint64_t count = 0; | |
1686 | if (event_supported(new_event)) { | |
1687 | uint16_t event_idx = supported_event_map[new_event]; | |
1688 | count = pm_events[event_idx].get_count(env); | |
1689 | } | |
1690 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1691 | } | |
1692 | ||
1693 | env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK; | |
1694 | pmevcntr_op_finish(env, counter); | |
1695 | } | |
fdb86656 WH |
1696 | /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when |
1697 | * PMSELR value is equal to or greater than the number of implemented | |
1698 | * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. | |
1699 | */ | |
5ecdd3e4 AL |
1700 | } |
1701 | ||
1702 | static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1703 | const uint8_t counter) | |
1704 | { | |
1705 | if (counter == 31) { | |
1706 | return env->cp15.pmccfiltr_el0; | |
1707 | } else if (counter < pmu_num_counters(env)) { | |
1708 | return env->cp15.c14_pmevtyper[counter]; | |
1709 | } else { | |
1710 | /* | |
1711 | * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER | |
1712 | * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). | |
1713 | */ | |
1714 | return 0; | |
1715 | } | |
1716 | } | |
1717 | ||
1718 | static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, | |
1719 | uint64_t value) | |
1720 | { | |
1721 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1722 | pmevtyper_write(env, ri, value, counter); | |
1723 | } | |
1724 | ||
1725 | static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1726 | uint64_t value) | |
1727 | { | |
1728 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1729 | env->cp15.c14_pmevtyper[counter] = value; | |
1730 | ||
1731 | /* | |
1732 | * pmevtyper_rawwrite is called between a pair of pmu_op_start and | |
1733 | * pmu_op_finish calls when loading saved state for a migration. Because | |
1734 | * we're potentially updating the type of event here, the value written to | |
1735 | * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a | |
1736 | * different counter type. Therefore, we need to set this value to the | |
1737 | * current count for the counter type we're writing so that pmu_op_finish | |
1738 | * has the correct count for its calculation. | |
1739 | */ | |
1740 | uint16_t event = value & PMXEVTYPER_EVTCOUNT; | |
1741 | if (event_supported(event)) { | |
1742 | uint16_t event_idx = supported_event_map[event]; | |
1743 | env->cp15.c14_pmevcntr_delta[counter] = | |
1744 | pm_events[event_idx].get_count(env); | |
fdb86656 WH |
1745 | } |
1746 | } | |
1747 | ||
5ecdd3e4 AL |
1748 | static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) |
1749 | { | |
1750 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1751 | return pmevtyper_read(env, ri, counter); | |
1752 | } | |
1753 | ||
1754 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1755 | uint64_t value) | |
1756 | { | |
1757 | pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1758 | } | |
1759 | ||
fdb86656 WH |
1760 | static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1761 | { | |
5ecdd3e4 AL |
1762 | return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); |
1763 | } | |
1764 | ||
1765 | static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1766 | uint64_t value, uint8_t counter) | |
1767 | { | |
1768 | if (counter < pmu_num_counters(env)) { | |
1769 | pmevcntr_op_start(env, counter); | |
1770 | env->cp15.c14_pmevcntr[counter] = value; | |
1771 | pmevcntr_op_finish(env, counter); | |
1772 | } | |
1773 | /* | |
1774 | * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR | |
1775 | * are CONSTRAINED UNPREDICTABLE. | |
fdb86656 | 1776 | */ |
5ecdd3e4 AL |
1777 | } |
1778 | ||
1779 | static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1780 | uint8_t counter) | |
1781 | { | |
1782 | if (counter < pmu_num_counters(env)) { | |
1783 | uint64_t ret; | |
1784 | pmevcntr_op_start(env, counter); | |
1785 | ret = env->cp15.c14_pmevcntr[counter]; | |
1786 | pmevcntr_op_finish(env, counter); | |
1787 | return ret; | |
fdb86656 | 1788 | } else { |
5ecdd3e4 AL |
1789 | /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR |
1790 | * are CONSTRAINED UNPREDICTABLE. */ | |
fdb86656 WH |
1791 | return 0; |
1792 | } | |
200ac0ef PM |
1793 | } |
1794 | ||
5ecdd3e4 AL |
1795 | static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, |
1796 | uint64_t value) | |
1797 | { | |
1798 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1799 | pmevcntr_write(env, ri, value, counter); | |
1800 | } | |
1801 | ||
1802 | static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) | |
1803 | { | |
1804 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1805 | return pmevcntr_read(env, ri, counter); | |
1806 | } | |
1807 | ||
1808 | static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1809 | uint64_t value) | |
1810 | { | |
1811 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1812 | assert(counter < pmu_num_counters(env)); | |
1813 | env->cp15.c14_pmevcntr[counter] = value; | |
1814 | pmevcntr_write(env, ri, value, counter); | |
1815 | } | |
1816 | ||
1817 | static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri) | |
1818 | { | |
1819 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1820 | assert(counter < pmu_num_counters(env)); | |
1821 | return env->cp15.c14_pmevcntr[counter]; | |
1822 | } | |
1823 | ||
1824 | static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1825 | uint64_t value) | |
1826 | { | |
1827 | pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1828 | } | |
1829 | ||
1830 | static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1831 | { | |
1832 | return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); | |
1833 | } | |
1834 | ||
c4241c7d | 1835 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1836 | uint64_t value) |
1837 | { | |
6ecd0b6b AB |
1838 | if (arm_feature(env, ARM_FEATURE_V8)) { |
1839 | env->cp15.c9_pmuserenr = value & 0xf; | |
1840 | } else { | |
1841 | env->cp15.c9_pmuserenr = value & 1; | |
1842 | } | |
200ac0ef PM |
1843 | } |
1844 | ||
c4241c7d PM |
1845 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1846 | uint64_t value) | |
200ac0ef PM |
1847 | { |
1848 | /* We have no event counters so only the C bit can be changed */ | |
7ece99b1 | 1849 | value &= pmu_counter_mask(env); |
200ac0ef | 1850 | env->cp15.c9_pminten |= value; |
f4efb4b2 | 1851 | pmu_update_irq(env); |
200ac0ef PM |
1852 | } |
1853 | ||
c4241c7d PM |
1854 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1855 | uint64_t value) | |
200ac0ef | 1856 | { |
7ece99b1 | 1857 | value &= pmu_counter_mask(env); |
200ac0ef | 1858 | env->cp15.c9_pminten &= ~value; |
f4efb4b2 | 1859 | pmu_update_irq(env); |
200ac0ef PM |
1860 | } |
1861 | ||
c4241c7d PM |
1862 | static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1863 | uint64_t value) | |
8641136c | 1864 | { |
a505d7fe PM |
1865 | /* Note that even though the AArch64 view of this register has bits |
1866 | * [10:0] all RES0 we can only mask the bottom 5, to comply with the | |
1867 | * architectural requirements for bits which are RES0 only in some | |
1868 | * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 | |
1869 | * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) | |
1870 | */ | |
855ea66d | 1871 | raw_write(env, ri, value & ~0x1FULL); |
8641136c NR |
1872 | } |
1873 | ||
64e0e2de EI |
1874 | static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
1875 | { | |
ea22747c RH |
1876 | /* Begin with base v8.0 state. */ |
1877 | uint32_t valid_mask = 0x3fff; | |
2fc0cc0e | 1878 | ARMCPU *cpu = env_archcpu(env); |
ea22747c RH |
1879 | |
1880 | if (arm_el_is_aa64(env, 3)) { | |
1881 | value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ | |
1882 | valid_mask &= ~SCR_NET; | |
1883 | } else { | |
1884 | valid_mask &= ~(SCR_RW | SCR_ST); | |
1885 | } | |
64e0e2de EI |
1886 | |
1887 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | |
1888 | valid_mask &= ~SCR_HCE; | |
1889 | ||
1890 | /* On ARMv7, SMD (or SCD as it is called in v7) is only | |
1891 | * supported if EL2 exists. The bit is UNK/SBZP when | |
1892 | * EL2 is unavailable. In QEMU ARMv7, we force it to always zero | |
1893 | * when EL2 is unavailable. | |
4eb27640 | 1894 | * On ARMv8, this bit is always available. |
64e0e2de | 1895 | */ |
4eb27640 GB |
1896 | if (arm_feature(env, ARM_FEATURE_V7) && |
1897 | !arm_feature(env, ARM_FEATURE_V8)) { | |
64e0e2de EI |
1898 | valid_mask &= ~SCR_SMD; |
1899 | } | |
1900 | } | |
2d7137c1 RH |
1901 | if (cpu_isar_feature(aa64_lor, cpu)) { |
1902 | valid_mask |= SCR_TLOR; | |
1903 | } | |
ef682cdb RH |
1904 | if (cpu_isar_feature(aa64_pauth, cpu)) { |
1905 | valid_mask |= SCR_API | SCR_APK; | |
1906 | } | |
64e0e2de EI |
1907 | |
1908 | /* Clear all-context RES0 bits. */ | |
1909 | value &= valid_mask; | |
1910 | raw_write(env, ri, value); | |
1911 | } | |
1912 | ||
630fcd4d MZ |
1913 | static CPAccessResult access_aa64_tid2(CPUARMState *env, |
1914 | const ARMCPRegInfo *ri, | |
1915 | bool isread) | |
1916 | { | |
1917 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) { | |
1918 | return CP_ACCESS_TRAP_EL2; | |
1919 | } | |
1920 | ||
1921 | return CP_ACCESS_OK; | |
1922 | } | |
1923 | ||
c4241c7d | 1924 | static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
776d4e5c | 1925 | { |
2fc0cc0e | 1926 | ARMCPU *cpu = env_archcpu(env); |
b85a1fd6 FA |
1927 | |
1928 | /* Acquire the CSSELR index from the bank corresponding to the CCSIDR | |
1929 | * bank | |
1930 | */ | |
1931 | uint32_t index = A32_BANKED_REG_GET(env, csselr, | |
1932 | ri->secure & ARM_CP_SECSTATE_S); | |
1933 | ||
1934 | return cpu->ccsidr[index]; | |
776d4e5c PM |
1935 | } |
1936 | ||
c4241c7d PM |
1937 | static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1938 | uint64_t value) | |
776d4e5c | 1939 | { |
8d5c773e | 1940 | raw_write(env, ri, value & 0xf); |
776d4e5c PM |
1941 | } |
1942 | ||
1090b9c6 PM |
1943 | static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1944 | { | |
29a0af61 | 1945 | CPUState *cs = env_cpu(env); |
f7778444 | 1946 | uint64_t hcr_el2 = arm_hcr_el2_eff(env); |
1090b9c6 | 1947 | uint64_t ret = 0; |
7cf95aed MZ |
1948 | bool allow_virt = (arm_current_el(env) == 1 && |
1949 | (!arm_is_secure_below_el3(env) || | |
1950 | (env->cp15.scr_el3 & SCR_EEL2))); | |
1090b9c6 | 1951 | |
7cf95aed | 1952 | if (allow_virt && (hcr_el2 & HCR_IMO)) { |
636540e9 PM |
1953 | if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { |
1954 | ret |= CPSR_I; | |
1955 | } | |
1956 | } else { | |
1957 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { | |
1958 | ret |= CPSR_I; | |
1959 | } | |
1090b9c6 | 1960 | } |
636540e9 | 1961 | |
7cf95aed | 1962 | if (allow_virt && (hcr_el2 & HCR_FMO)) { |
636540e9 PM |
1963 | if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { |
1964 | ret |= CPSR_F; | |
1965 | } | |
1966 | } else { | |
1967 | if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { | |
1968 | ret |= CPSR_F; | |
1969 | } | |
1090b9c6 | 1970 | } |
636540e9 | 1971 | |
1090b9c6 PM |
1972 | /* External aborts are not possible in QEMU so A bit is always clear */ |
1973 | return ret; | |
1974 | } | |
1975 | ||
93fbc983 MZ |
1976 | static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInfo *ri, |
1977 | bool isread) | |
1978 | { | |
1979 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID1)) { | |
1980 | return CP_ACCESS_TRAP_EL2; | |
1981 | } | |
1982 | ||
1983 | return CP_ACCESS_OK; | |
1984 | } | |
1985 | ||
1986 | static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInfo *ri, | |
1987 | bool isread) | |
1988 | { | |
1989 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
1990 | return access_aa64_tid1(env, ri, isread); | |
1991 | } | |
1992 | ||
1993 | return CP_ACCESS_OK; | |
1994 | } | |
1995 | ||
e9aa6c21 | 1996 | static const ARMCPRegInfo v7_cp_reginfo[] = { |
7d57f408 PM |
1997 | /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ |
1998 | { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
1999 | .access = PL1_W, .type = ARM_CP_NOP }, | |
200ac0ef PM |
2000 | /* Performance monitors are implementation defined in v7, |
2001 | * but with an ARM recommended set of registers, which we | |
ac689a2e | 2002 | * follow. |
200ac0ef PM |
2003 | * |
2004 | * Performance registers fall into three categories: | |
2005 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) | |
2006 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) | |
2007 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) | |
2008 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW | |
2009 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. | |
2010 | */ | |
2011 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 2012 | .access = PL0_RW, .type = ARM_CP_ALIAS, |
8521466b | 2013 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), |
fcd25206 PM |
2014 | .writefn = pmcntenset_write, |
2015 | .accessfn = pmreg_access, | |
2016 | .raw_writefn = raw_write }, | |
8521466b AF |
2017 | { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, |
2018 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, | |
2019 | .access = PL0_RW, .accessfn = pmreg_access, | |
2020 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, | |
2021 | .writefn = pmcntenset_write, .raw_writefn = raw_write }, | |
200ac0ef | 2022 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
8521466b AF |
2023 | .access = PL0_RW, |
2024 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
2025 | .accessfn = pmreg_access, |
2026 | .writefn = pmcntenclr_write, | |
7a0e58fa | 2027 | .type = ARM_CP_ALIAS }, |
8521466b AF |
2028 | { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, |
2029 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, | |
2030 | .access = PL0_RW, .accessfn = pmreg_access, | |
7a0e58fa | 2031 | .type = ARM_CP_ALIAS, |
8521466b AF |
2032 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), |
2033 | .writefn = pmcntenclr_write }, | |
200ac0ef | 2034 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
f4efb4b2 | 2035 | .access = PL0_RW, .type = ARM_CP_IO, |
e4e91a21 | 2036 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
fcd25206 PM |
2037 | .accessfn = pmreg_access, |
2038 | .writefn = pmovsr_write, | |
2039 | .raw_writefn = raw_write }, | |
978364f1 AF |
2040 | { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, |
2041 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, | |
2042 | .access = PL0_RW, .accessfn = pmreg_access, | |
f4efb4b2 | 2043 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
978364f1 AF |
2044 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
2045 | .writefn = pmovsr_write, | |
2046 | .raw_writefn = raw_write }, | |
200ac0ef | 2047 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
f4efb4b2 AL |
2048 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
2049 | .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
0d4bfd7d AL |
2050 | .writefn = pmswinc_write }, |
2051 | { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64, | |
2052 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4, | |
f4efb4b2 AL |
2053 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
2054 | .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
0d4bfd7d | 2055 | .writefn = pmswinc_write }, |
6b040780 WH |
2056 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, |
2057 | .access = PL0_RW, .type = ARM_CP_ALIAS, | |
2058 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), | |
6ecd0b6b | 2059 | .accessfn = pmreg_access_selr, .writefn = pmselr_write, |
6b040780 WH |
2060 | .raw_writefn = raw_write}, |
2061 | { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, | |
2062 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, | |
6ecd0b6b | 2063 | .access = PL0_RW, .accessfn = pmreg_access_selr, |
6b040780 WH |
2064 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), |
2065 | .writefn = pmselr_write, .raw_writefn = raw_write, }, | |
200ac0ef | 2066 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
169c8938 | 2067 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO, |
421c7ebd | 2068 | .readfn = pmccntr_read, .writefn = pmccntr_write32, |
6ecd0b6b | 2069 | .accessfn = pmreg_access_ccntr }, |
8521466b AF |
2070 | { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, |
2071 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, | |
6ecd0b6b | 2072 | .access = PL0_RW, .accessfn = pmreg_access_ccntr, |
8521466b | 2073 | .type = ARM_CP_IO, |
980ebe87 AL |
2074 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt), |
2075 | .readfn = pmccntr_read, .writefn = pmccntr_write, | |
2076 | .raw_readfn = raw_read, .raw_writefn = raw_write, }, | |
4b8afa1f AL |
2077 | { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7, |
2078 | .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32, | |
2079 | .access = PL0_RW, .accessfn = pmreg_access, | |
2080 | .type = ARM_CP_ALIAS | ARM_CP_IO, | |
2081 | .resetvalue = 0, }, | |
8521466b AF |
2082 | { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, |
2083 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, | |
980ebe87 | 2084 | .writefn = pmccfiltr_write, .raw_writefn = raw_write, |
8521466b AF |
2085 | .access = PL0_RW, .accessfn = pmreg_access, |
2086 | .type = ARM_CP_IO, | |
2087 | .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), | |
2088 | .resetvalue = 0, }, | |
200ac0ef | 2089 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
5ecdd3e4 AL |
2090 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
2091 | .accessfn = pmreg_access, | |
fdb86656 WH |
2092 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
2093 | { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, | |
2094 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, | |
5ecdd3e4 AL |
2095 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
2096 | .accessfn = pmreg_access, | |
fdb86656 | 2097 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
200ac0ef | 2098 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
5ecdd3e4 AL |
2099 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
2100 | .accessfn = pmreg_access_xevcntr, | |
2101 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, | |
2102 | { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64, | |
2103 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2, | |
2104 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
2105 | .accessfn = pmreg_access_xevcntr, | |
2106 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, | |
200ac0ef | 2107 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
1fce1ba9 | 2108 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, |
e4e91a21 | 2109 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr), |
200ac0ef | 2110 | .resetvalue = 0, |
d4e6df63 | 2111 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
8a83ffc2 AF |
2112 | { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, |
2113 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, | |
1fce1ba9 | 2114 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, |
8a83ffc2 AF |
2115 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), |
2116 | .resetvalue = 0, | |
2117 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, | |
200ac0ef | 2118 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
1fce1ba9 | 2119 | .access = PL1_RW, .accessfn = access_tpm, |
b7d793ad | 2120 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
e6ec5457 | 2121 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), |
200ac0ef | 2122 | .resetvalue = 0, |
d4e6df63 | 2123 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
e6ec5457 WH |
2124 | { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, |
2125 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, | |
2126 | .access = PL1_RW, .accessfn = access_tpm, | |
2127 | .type = ARM_CP_IO, | |
2128 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
2129 | .writefn = pmintenset_write, .raw_writefn = raw_write, | |
2130 | .resetvalue = 0x0 }, | |
200ac0ef | 2131 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
fc5f6856 AL |
2132 | .access = PL1_RW, .accessfn = access_tpm, |
2133 | .type = ARM_CP_ALIAS | ARM_CP_IO, | |
200ac0ef | 2134 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
b061a82b | 2135 | .writefn = pmintenclr_write, }, |
978364f1 AF |
2136 | { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, |
2137 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, | |
fc5f6856 AL |
2138 | .access = PL1_RW, .accessfn = access_tpm, |
2139 | .type = ARM_CP_ALIAS | ARM_CP_IO, | |
978364f1 AF |
2140 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
2141 | .writefn = pmintenclr_write }, | |
7da845b0 PM |
2142 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, |
2143 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | |
630fcd4d MZ |
2144 | .access = PL1_R, |
2145 | .accessfn = access_aa64_tid2, | |
2146 | .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, | |
7da845b0 PM |
2147 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, |
2148 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | |
630fcd4d MZ |
2149 | .access = PL1_RW, |
2150 | .accessfn = access_aa64_tid2, | |
2151 | .writefn = csselr_write, .resetvalue = 0, | |
b85a1fd6 FA |
2152 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), |
2153 | offsetof(CPUARMState, cp15.csselr_ns) } }, | |
776d4e5c PM |
2154 | /* Auxiliary ID register: this actually has an IMPDEF value but for now |
2155 | * just RAZ for all cores: | |
2156 | */ | |
0ff644a7 PM |
2157 | { .name = "AIDR", .state = ARM_CP_STATE_BOTH, |
2158 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, | |
93fbc983 MZ |
2159 | .access = PL1_R, .type = ARM_CP_CONST, |
2160 | .accessfn = access_aa64_tid1, | |
2161 | .resetvalue = 0 }, | |
f32cdad5 PM |
2162 | /* Auxiliary fault status registers: these also are IMPDEF, and we |
2163 | * choose to RAZ/WI for all cores. | |
2164 | */ | |
2165 | { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, | |
2166 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, | |
2167 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2168 | { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, | |
2169 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, | |
2170 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b0fe2427 PM |
2171 | /* MAIR can just read-as-written because we don't implement caches |
2172 | * and so don't need to care about memory attributes. | |
2173 | */ | |
2174 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | |
2175 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | |
be693c87 | 2176 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), |
b0fe2427 | 2177 | .resetvalue = 0 }, |
4cfb8ad8 PM |
2178 | { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, |
2179 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, | |
2180 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), | |
2181 | .resetvalue = 0 }, | |
b0fe2427 PM |
2182 | /* For non-long-descriptor page tables these are PRRR and NMRR; |
2183 | * regardless they still act as reads-as-written for QEMU. | |
b0fe2427 | 2184 | */ |
1281f8e3 | 2185 | /* MAIR0/1 are defined separately from their 64-bit counterpart which |
be693c87 GB |
2186 | * allows them to assign the correct fieldoffset based on the endianness |
2187 | * handled in the field definitions. | |
2188 | */ | |
a903c449 | 2189 | { .name = "MAIR0", .state = ARM_CP_STATE_AA32, |
b0fe2427 | 2190 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, |
be693c87 GB |
2191 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), |
2192 | offsetof(CPUARMState, cp15.mair0_ns) }, | |
b0fe2427 | 2193 | .resetfn = arm_cp_reset_ignore }, |
a903c449 | 2194 | { .name = "MAIR1", .state = ARM_CP_STATE_AA32, |
b0fe2427 | 2195 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, |
be693c87 GB |
2196 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), |
2197 | offsetof(CPUARMState, cp15.mair1_ns) }, | |
b0fe2427 | 2198 | .resetfn = arm_cp_reset_ignore }, |
1090b9c6 PM |
2199 | { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, |
2200 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, | |
7a0e58fa | 2201 | .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, |
995939a6 PM |
2202 | /* 32 bit ITLB invalidates */ |
2203 | { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, | |
7a0e58fa | 2204 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 2205 | { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, |
7a0e58fa | 2206 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 2207 | { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, |
7a0e58fa | 2208 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 PM |
2209 | /* 32 bit DTLB invalidates */ |
2210 | { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, | |
7a0e58fa | 2211 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 2212 | { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, |
7a0e58fa | 2213 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 2214 | { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, |
7a0e58fa | 2215 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 PM |
2216 | /* 32 bit TLB invalidates */ |
2217 | { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | |
7a0e58fa | 2218 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 2219 | { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
7a0e58fa | 2220 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 2221 | { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
7a0e58fa | 2222 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 | 2223 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
7a0e58fa | 2224 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, |
995939a6 PM |
2225 | REGINFO_SENTINEL |
2226 | }; | |
2227 | ||
2228 | static const ARMCPRegInfo v7mp_cp_reginfo[] = { | |
2229 | /* 32 bit TLB invalidates, Inner Shareable */ | |
2230 | { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | |
7a0e58fa | 2231 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write }, |
995939a6 | 2232 | { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
7a0e58fa | 2233 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, |
995939a6 | 2234 | { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
7a0e58fa | 2235 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 2236 | .writefn = tlbiasid_is_write }, |
995939a6 | 2237 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
7a0e58fa | 2238 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 2239 | .writefn = tlbimvaa_is_write }, |
e9aa6c21 PM |
2240 | REGINFO_SENTINEL |
2241 | }; | |
2242 | ||
327dd510 AL |
2243 | static const ARMCPRegInfo pmovsset_cp_reginfo[] = { |
2244 | /* PMOVSSET is not implemented in v7 before v7ve */ | |
2245 | { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3, | |
2246 | .access = PL0_RW, .accessfn = pmreg_access, | |
f4efb4b2 | 2247 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
327dd510 AL |
2248 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
2249 | .writefn = pmovsset_write, | |
2250 | .raw_writefn = raw_write }, | |
2251 | { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64, | |
2252 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3, | |
2253 | .access = PL0_RW, .accessfn = pmreg_access, | |
f4efb4b2 | 2254 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
327dd510 AL |
2255 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
2256 | .writefn = pmovsset_write, | |
2257 | .raw_writefn = raw_write }, | |
2258 | REGINFO_SENTINEL | |
2259 | }; | |
2260 | ||
c4241c7d PM |
2261 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2262 | uint64_t value) | |
c326b979 PM |
2263 | { |
2264 | value &= 1; | |
2265 | env->teecr = value; | |
c326b979 PM |
2266 | } |
2267 | ||
3f208fd7 PM |
2268 | static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2269 | bool isread) | |
c326b979 | 2270 | { |
dcbff19b | 2271 | if (arm_current_el(env) == 0 && (env->teecr & 1)) { |
92611c00 | 2272 | return CP_ACCESS_TRAP; |
c326b979 | 2273 | } |
92611c00 | 2274 | return CP_ACCESS_OK; |
c326b979 PM |
2275 | } |
2276 | ||
2277 | static const ARMCPRegInfo t2ee_cp_reginfo[] = { | |
2278 | { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, | |
2279 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), | |
2280 | .resetvalue = 0, | |
2281 | .writefn = teecr_write }, | |
2282 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, | |
2283 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | |
92611c00 | 2284 | .accessfn = teehbr_access, .resetvalue = 0 }, |
c326b979 PM |
2285 | REGINFO_SENTINEL |
2286 | }; | |
2287 | ||
4d31c596 | 2288 | static const ARMCPRegInfo v6k_cp_reginfo[] = { |
e4fe830b PM |
2289 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, |
2290 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | |
2291 | .access = PL0_RW, | |
54bf36ed | 2292 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, |
4d31c596 PM |
2293 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
2294 | .access = PL0_RW, | |
54bf36ed FA |
2295 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), |
2296 | offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, | |
e4fe830b PM |
2297 | .resetfn = arm_cp_reset_ignore }, |
2298 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | |
2299 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | |
2300 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
2301 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), |
2302 | .resetvalue = 0}, | |
4d31c596 PM |
2303 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
2304 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
2305 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), |
2306 | offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, | |
e4fe830b | 2307 | .resetfn = arm_cp_reset_ignore }, |
54bf36ed | 2308 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, |
e4fe830b | 2309 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, |
4d31c596 | 2310 | .access = PL1_RW, |
54bf36ed FA |
2311 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, |
2312 | { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, | |
2313 | .access = PL1_RW, | |
2314 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), | |
2315 | offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, | |
2316 | .resetvalue = 0 }, | |
4d31c596 PM |
2317 | REGINFO_SENTINEL |
2318 | }; | |
2319 | ||
55d284af PM |
2320 | #ifndef CONFIG_USER_ONLY |
2321 | ||
3f208fd7 PM |
2322 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2323 | bool isread) | |
00108f2d | 2324 | { |
75502672 PM |
2325 | /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. |
2326 | * Writable only at the highest implemented exception level. | |
2327 | */ | |
2328 | int el = arm_current_el(env); | |
2329 | ||
2330 | switch (el) { | |
2331 | case 0: | |
2332 | if (!extract32(env->cp15.c14_cntkctl, 0, 2)) { | |
2333 | return CP_ACCESS_TRAP; | |
2334 | } | |
2335 | break; | |
2336 | case 1: | |
2337 | if (!isread && ri->state == ARM_CP_STATE_AA32 && | |
2338 | arm_is_secure_below_el3(env)) { | |
2339 | /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ | |
2340 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2341 | } | |
2342 | break; | |
2343 | case 2: | |
2344 | case 3: | |
2345 | break; | |
00108f2d | 2346 | } |
75502672 PM |
2347 | |
2348 | if (!isread && el < arm_highest_el(env)) { | |
2349 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2350 | } | |
2351 | ||
00108f2d PM |
2352 | return CP_ACCESS_OK; |
2353 | } | |
2354 | ||
3f208fd7 PM |
2355 | static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, |
2356 | bool isread) | |
00108f2d | 2357 | { |
0b6440af EI |
2358 | unsigned int cur_el = arm_current_el(env); |
2359 | bool secure = arm_is_secure(env); | |
2360 | ||
00108f2d | 2361 | /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ |
0b6440af | 2362 | if (cur_el == 0 && |
00108f2d PM |
2363 | !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { |
2364 | return CP_ACCESS_TRAP; | |
2365 | } | |
0b6440af EI |
2366 | |
2367 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
2368 | timeridx == GTIMER_PHYS && !secure && cur_el < 2 && | |
2369 | !extract32(env->cp15.cnthctl_el2, 0, 1)) { | |
2370 | return CP_ACCESS_TRAP_EL2; | |
2371 | } | |
00108f2d PM |
2372 | return CP_ACCESS_OK; |
2373 | } | |
2374 | ||
3f208fd7 PM |
2375 | static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, |
2376 | bool isread) | |
00108f2d | 2377 | { |
0b6440af EI |
2378 | unsigned int cur_el = arm_current_el(env); |
2379 | bool secure = arm_is_secure(env); | |
2380 | ||
00108f2d PM |
2381 | /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if |
2382 | * EL0[PV]TEN is zero. | |
2383 | */ | |
0b6440af | 2384 | if (cur_el == 0 && |
00108f2d PM |
2385 | !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { |
2386 | return CP_ACCESS_TRAP; | |
2387 | } | |
0b6440af EI |
2388 | |
2389 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
2390 | timeridx == GTIMER_PHYS && !secure && cur_el < 2 && | |
2391 | !extract32(env->cp15.cnthctl_el2, 1, 1)) { | |
2392 | return CP_ACCESS_TRAP_EL2; | |
2393 | } | |
00108f2d PM |
2394 | return CP_ACCESS_OK; |
2395 | } | |
2396 | ||
2397 | static CPAccessResult gt_pct_access(CPUARMState *env, | |
3f208fd7 PM |
2398 | const ARMCPRegInfo *ri, |
2399 | bool isread) | |
00108f2d | 2400 | { |
3f208fd7 | 2401 | return gt_counter_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2402 | } |
2403 | ||
2404 | static CPAccessResult gt_vct_access(CPUARMState *env, | |
3f208fd7 PM |
2405 | const ARMCPRegInfo *ri, |
2406 | bool isread) | |
00108f2d | 2407 | { |
3f208fd7 | 2408 | return gt_counter_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2409 | } |
2410 | ||
3f208fd7 PM |
2411 | static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2412 | bool isread) | |
00108f2d | 2413 | { |
3f208fd7 | 2414 | return gt_timer_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2415 | } |
2416 | ||
3f208fd7 PM |
2417 | static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2418 | bool isread) | |
00108f2d | 2419 | { |
3f208fd7 | 2420 | return gt_timer_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2421 | } |
2422 | ||
b4d3978c | 2423 | static CPAccessResult gt_stimer_access(CPUARMState *env, |
3f208fd7 PM |
2424 | const ARMCPRegInfo *ri, |
2425 | bool isread) | |
b4d3978c PM |
2426 | { |
2427 | /* The AArch64 register view of the secure physical timer is | |
2428 | * always accessible from EL3, and configurably accessible from | |
2429 | * Secure EL1. | |
2430 | */ | |
2431 | switch (arm_current_el(env)) { | |
2432 | case 1: | |
2433 | if (!arm_is_secure(env)) { | |
2434 | return CP_ACCESS_TRAP; | |
2435 | } | |
2436 | if (!(env->cp15.scr_el3 & SCR_ST)) { | |
2437 | return CP_ACCESS_TRAP_EL3; | |
2438 | } | |
2439 | return CP_ACCESS_OK; | |
2440 | case 0: | |
2441 | case 2: | |
2442 | return CP_ACCESS_TRAP; | |
2443 | case 3: | |
2444 | return CP_ACCESS_OK; | |
2445 | default: | |
2446 | g_assert_not_reached(); | |
2447 | } | |
2448 | } | |
2449 | ||
55d284af PM |
2450 | static uint64_t gt_get_countervalue(CPUARMState *env) |
2451 | { | |
bc72ad67 | 2452 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; |
55d284af PM |
2453 | } |
2454 | ||
2455 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) | |
2456 | { | |
2457 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; | |
2458 | ||
2459 | if (gt->ctl & 1) { | |
2460 | /* Timer enabled: calculate and set current ISTATUS, irq, and | |
2461 | * reset timer to when ISTATUS next has to change | |
2462 | */ | |
edac4d8a EI |
2463 | uint64_t offset = timeridx == GTIMER_VIRT ? |
2464 | cpu->env.cp15.cntvoff_el2 : 0; | |
55d284af PM |
2465 | uint64_t count = gt_get_countervalue(&cpu->env); |
2466 | /* Note that this must be unsigned 64 bit arithmetic: */ | |
edac4d8a | 2467 | int istatus = count - offset >= gt->cval; |
55d284af | 2468 | uint64_t nexttick; |
194cbc49 | 2469 | int irqstate; |
55d284af PM |
2470 | |
2471 | gt->ctl = deposit32(gt->ctl, 2, 1, istatus); | |
194cbc49 PM |
2472 | |
2473 | irqstate = (istatus && !(gt->ctl & 2)); | |
2474 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
2475 | ||
55d284af PM |
2476 | if (istatus) { |
2477 | /* Next transition is when count rolls back over to zero */ | |
2478 | nexttick = UINT64_MAX; | |
2479 | } else { | |
2480 | /* Next transition is when we hit cval */ | |
edac4d8a | 2481 | nexttick = gt->cval + offset; |
55d284af PM |
2482 | } |
2483 | /* Note that the desired next expiry time might be beyond the | |
2484 | * signed-64-bit range of a QEMUTimer -- in this case we just | |
2485 | * set the timer for as far in the future as possible. When the | |
2486 | * timer expires we will reset the timer for any remaining period. | |
2487 | */ | |
2488 | if (nexttick > INT64_MAX / GTIMER_SCALE) { | |
2489 | nexttick = INT64_MAX / GTIMER_SCALE; | |
2490 | } | |
bc72ad67 | 2491 | timer_mod(cpu->gt_timer[timeridx], nexttick); |
194cbc49 | 2492 | trace_arm_gt_recalc(timeridx, irqstate, nexttick); |
55d284af PM |
2493 | } else { |
2494 | /* Timer disabled: ISTATUS and timer output always clear */ | |
2495 | gt->ctl &= ~4; | |
2496 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); | |
bc72ad67 | 2497 | timer_del(cpu->gt_timer[timeridx]); |
194cbc49 | 2498 | trace_arm_gt_recalc_disabled(timeridx); |
55d284af PM |
2499 | } |
2500 | } | |
2501 | ||
0e3eca4c EI |
2502 | static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, |
2503 | int timeridx) | |
55d284af | 2504 | { |
2fc0cc0e | 2505 | ARMCPU *cpu = env_archcpu(env); |
55d284af | 2506 | |
bc72ad67 | 2507 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
2508 | } |
2509 | ||
c4241c7d | 2510 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
55d284af | 2511 | { |
c4241c7d | 2512 | return gt_get_countervalue(env); |
55d284af PM |
2513 | } |
2514 | ||
edac4d8a EI |
2515 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2516 | { | |
2517 | return gt_get_countervalue(env) - env->cp15.cntvoff_el2; | |
2518 | } | |
2519 | ||
c4241c7d | 2520 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2521 | int timeridx, |
c4241c7d | 2522 | uint64_t value) |
55d284af | 2523 | { |
194cbc49 | 2524 | trace_arm_gt_cval_write(timeridx, value); |
55d284af | 2525 | env->cp15.c14_timer[timeridx].cval = value; |
2fc0cc0e | 2526 | gt_recalc_timer(env_archcpu(env), timeridx); |
55d284af | 2527 | } |
c4241c7d | 2528 | |
0e3eca4c EI |
2529 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, |
2530 | int timeridx) | |
55d284af | 2531 | { |
edac4d8a | 2532 | uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; |
55d284af | 2533 | |
c4241c7d | 2534 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - |
edac4d8a | 2535 | (gt_get_countervalue(env) - offset)); |
55d284af PM |
2536 | } |
2537 | ||
c4241c7d | 2538 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2539 | int timeridx, |
c4241c7d | 2540 | uint64_t value) |
55d284af | 2541 | { |
edac4d8a | 2542 | uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; |
55d284af | 2543 | |
194cbc49 | 2544 | trace_arm_gt_tval_write(timeridx, value); |
edac4d8a | 2545 | env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + |
18084b2f | 2546 | sextract64(value, 0, 32); |
2fc0cc0e | 2547 | gt_recalc_timer(env_archcpu(env), timeridx); |
55d284af PM |
2548 | } |
2549 | ||
c4241c7d | 2550 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2551 | int timeridx, |
c4241c7d | 2552 | uint64_t value) |
55d284af | 2553 | { |
2fc0cc0e | 2554 | ARMCPU *cpu = env_archcpu(env); |
55d284af PM |
2555 | uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; |
2556 | ||
194cbc49 | 2557 | trace_arm_gt_ctl_write(timeridx, value); |
d3afacc7 | 2558 | env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); |
55d284af PM |
2559 | if ((oldval ^ value) & 1) { |
2560 | /* Enable toggled */ | |
2561 | gt_recalc_timer(cpu, timeridx); | |
d3afacc7 | 2562 | } else if ((oldval ^ value) & 2) { |
55d284af PM |
2563 | /* IMASK toggled: don't need to recalculate, |
2564 | * just set the interrupt line based on ISTATUS | |
2565 | */ | |
194cbc49 PM |
2566 | int irqstate = (oldval & 4) && !(value & 2); |
2567 | ||
2568 | trace_arm_gt_imask_toggle(timeridx, irqstate); | |
2569 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
55d284af | 2570 | } |
55d284af PM |
2571 | } |
2572 | ||
0e3eca4c EI |
2573 | static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2574 | { | |
2575 | gt_timer_reset(env, ri, GTIMER_PHYS); | |
2576 | } | |
2577 | ||
2578 | static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2579 | uint64_t value) | |
2580 | { | |
2581 | gt_cval_write(env, ri, GTIMER_PHYS, value); | |
2582 | } | |
2583 | ||
2584 | static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2585 | { | |
2586 | return gt_tval_read(env, ri, GTIMER_PHYS); | |
2587 | } | |
2588 | ||
2589 | static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2590 | uint64_t value) | |
2591 | { | |
2592 | gt_tval_write(env, ri, GTIMER_PHYS, value); | |
2593 | } | |
2594 | ||
2595 | static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2596 | uint64_t value) | |
2597 | { | |
2598 | gt_ctl_write(env, ri, GTIMER_PHYS, value); | |
2599 | } | |
2600 | ||
2601 | static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) | |
2602 | { | |
2603 | gt_timer_reset(env, ri, GTIMER_VIRT); | |
2604 | } | |
2605 | ||
2606 | static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2607 | uint64_t value) | |
2608 | { | |
2609 | gt_cval_write(env, ri, GTIMER_VIRT, value); | |
2610 | } | |
2611 | ||
2612 | static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2613 | { | |
2614 | return gt_tval_read(env, ri, GTIMER_VIRT); | |
2615 | } | |
2616 | ||
2617 | static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2618 | uint64_t value) | |
2619 | { | |
2620 | gt_tval_write(env, ri, GTIMER_VIRT, value); | |
2621 | } | |
2622 | ||
2623 | static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2624 | uint64_t value) | |
2625 | { | |
2626 | gt_ctl_write(env, ri, GTIMER_VIRT, value); | |
2627 | } | |
2628 | ||
edac4d8a EI |
2629 | static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2630 | uint64_t value) | |
2631 | { | |
2fc0cc0e | 2632 | ARMCPU *cpu = env_archcpu(env); |
edac4d8a | 2633 | |
194cbc49 | 2634 | trace_arm_gt_cntvoff_write(value); |
edac4d8a EI |
2635 | raw_write(env, ri, value); |
2636 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
2637 | } | |
2638 | ||
b0e66d95 EI |
2639 | static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2640 | { | |
2641 | gt_timer_reset(env, ri, GTIMER_HYP); | |
2642 | } | |
2643 | ||
2644 | static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2645 | uint64_t value) | |
2646 | { | |
2647 | gt_cval_write(env, ri, GTIMER_HYP, value); | |
2648 | } | |
2649 | ||
2650 | static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2651 | { | |
2652 | return gt_tval_read(env, ri, GTIMER_HYP); | |
2653 | } | |
2654 | ||
2655 | static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2656 | uint64_t value) | |
2657 | { | |
2658 | gt_tval_write(env, ri, GTIMER_HYP, value); | |
2659 | } | |
2660 | ||
2661 | static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2662 | uint64_t value) | |
2663 | { | |
2664 | gt_ctl_write(env, ri, GTIMER_HYP, value); | |
2665 | } | |
2666 | ||
b4d3978c PM |
2667 | static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2668 | { | |
2669 | gt_timer_reset(env, ri, GTIMER_SEC); | |
2670 | } | |
2671 | ||
2672 | static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2673 | uint64_t value) | |
2674 | { | |
2675 | gt_cval_write(env, ri, GTIMER_SEC, value); | |
2676 | } | |
2677 | ||
2678 | static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2679 | { | |
2680 | return gt_tval_read(env, ri, GTIMER_SEC); | |
2681 | } | |
2682 | ||
2683 | static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2684 | uint64_t value) | |
2685 | { | |
2686 | gt_tval_write(env, ri, GTIMER_SEC, value); | |
2687 | } | |
2688 | ||
2689 | static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2690 | uint64_t value) | |
2691 | { | |
2692 | gt_ctl_write(env, ri, GTIMER_SEC, value); | |
2693 | } | |
2694 | ||
55d284af PM |
2695 | void arm_gt_ptimer_cb(void *opaque) |
2696 | { | |
2697 | ARMCPU *cpu = opaque; | |
2698 | ||
2699 | gt_recalc_timer(cpu, GTIMER_PHYS); | |
2700 | } | |
2701 | ||
2702 | void arm_gt_vtimer_cb(void *opaque) | |
2703 | { | |
2704 | ARMCPU *cpu = opaque; | |
2705 | ||
2706 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
2707 | } | |
2708 | ||
b0e66d95 EI |
2709 | void arm_gt_htimer_cb(void *opaque) |
2710 | { | |
2711 | ARMCPU *cpu = opaque; | |
2712 | ||
2713 | gt_recalc_timer(cpu, GTIMER_HYP); | |
2714 | } | |
2715 | ||
b4d3978c PM |
2716 | void arm_gt_stimer_cb(void *opaque) |
2717 | { | |
2718 | ARMCPU *cpu = opaque; | |
2719 | ||
2720 | gt_recalc_timer(cpu, GTIMER_SEC); | |
2721 | } | |
2722 | ||
55d284af PM |
2723 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
2724 | /* Note that CNTFRQ is purely reads-as-written for the benefit | |
2725 | * of software; writing it doesn't actually change the timer frequency. | |
2726 | * Our reset value matches the fixed frequency we implement the timer at. | |
2727 | */ | |
2728 | { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 2729 | .type = ARM_CP_ALIAS, |
a7adc4b7 PM |
2730 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, |
2731 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), | |
a7adc4b7 PM |
2732 | }, |
2733 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, | |
2734 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
2735 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
55d284af PM |
2736 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), |
2737 | .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE, | |
55d284af PM |
2738 | }, |
2739 | /* overall control: mostly access permissions */ | |
a7adc4b7 PM |
2740 | { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, |
2741 | .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, | |
55d284af PM |
2742 | .access = PL1_RW, |
2743 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), | |
2744 | .resetvalue = 0, | |
2745 | }, | |
2746 | /* per-timer control */ | |
2747 | { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
9ff9dd3c | 2748 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 2749 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
a7adc4b7 PM |
2750 | .accessfn = gt_ptimer_access, |
2751 | .fieldoffset = offsetoflow32(CPUARMState, | |
2752 | cp15.c14_timer[GTIMER_PHYS].ctl), | |
0e3eca4c | 2753 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, |
a7adc4b7 | 2754 | }, |
9c513e78 | 2755 | { .name = "CNTP_CTL_S", |
9ff9dd3c PM |
2756 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, |
2757 | .secure = ARM_CP_SECSTATE_S, | |
daf1dc5f | 2758 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
9ff9dd3c PM |
2759 | .accessfn = gt_ptimer_access, |
2760 | .fieldoffset = offsetoflow32(CPUARMState, | |
2761 | cp15.c14_timer[GTIMER_SEC].ctl), | |
2762 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
2763 | }, | |
a7adc4b7 PM |
2764 | { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, |
2765 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, | |
daf1dc5f | 2766 | .type = ARM_CP_IO, .access = PL0_RW, |
a7adc4b7 | 2767 | .accessfn = gt_ptimer_access, |
55d284af PM |
2768 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), |
2769 | .resetvalue = 0, | |
0e3eca4c | 2770 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
2771 | }, |
2772 | { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, | |
daf1dc5f | 2773 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
a7adc4b7 PM |
2774 | .accessfn = gt_vtimer_access, |
2775 | .fieldoffset = offsetoflow32(CPUARMState, | |
2776 | cp15.c14_timer[GTIMER_VIRT].ctl), | |
0e3eca4c | 2777 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, |
a7adc4b7 PM |
2778 | }, |
2779 | { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
2780 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, | |
daf1dc5f | 2781 | .type = ARM_CP_IO, .access = PL0_RW, |
a7adc4b7 | 2782 | .accessfn = gt_vtimer_access, |
55d284af PM |
2783 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), |
2784 | .resetvalue = 0, | |
0e3eca4c | 2785 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
2786 | }, |
2787 | /* TimerValue views: a 32 bit downcounting view of the underlying state */ | |
2788 | { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
9ff9dd3c | 2789 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 2790 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
00108f2d | 2791 | .accessfn = gt_ptimer_access, |
0e3eca4c | 2792 | .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, |
55d284af | 2793 | }, |
9c513e78 | 2794 | { .name = "CNTP_TVAL_S", |
9ff9dd3c PM |
2795 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, |
2796 | .secure = ARM_CP_SECSTATE_S, | |
daf1dc5f | 2797 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
9ff9dd3c PM |
2798 | .accessfn = gt_ptimer_access, |
2799 | .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, | |
2800 | }, | |
a7adc4b7 PM |
2801 | { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
2802 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, | |
daf1dc5f | 2803 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
0e3eca4c EI |
2804 | .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, |
2805 | .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, | |
a7adc4b7 | 2806 | }, |
55d284af | 2807 | { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, |
daf1dc5f | 2808 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
00108f2d | 2809 | .accessfn = gt_vtimer_access, |
0e3eca4c | 2810 | .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, |
55d284af | 2811 | }, |
a7adc4b7 PM |
2812 | { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
2813 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, | |
daf1dc5f | 2814 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
0e3eca4c EI |
2815 | .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, |
2816 | .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, | |
a7adc4b7 | 2817 | }, |
55d284af PM |
2818 | /* The counter itself */ |
2819 | { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, | |
7a0e58fa | 2820 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 2821 | .accessfn = gt_pct_access, |
a7adc4b7 PM |
2822 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
2823 | }, | |
2824 | { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, | |
2825 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, | |
7a0e58fa | 2826 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 2827 | .accessfn = gt_pct_access, .readfn = gt_cnt_read, |
55d284af PM |
2828 | }, |
2829 | { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, | |
7a0e58fa | 2830 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 2831 | .accessfn = gt_vct_access, |
edac4d8a | 2832 | .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, |
a7adc4b7 PM |
2833 | }, |
2834 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
2835 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
7a0e58fa | 2836 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 2837 | .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, |
55d284af PM |
2838 | }, |
2839 | /* Comparison value, indicating when the timer goes off */ | |
2840 | { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, | |
9ff9dd3c | 2841 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 2842 | .access = PL0_RW, |
7a0e58fa | 2843 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 2844 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), |
b061a82b | 2845 | .accessfn = gt_ptimer_access, |
0e3eca4c | 2846 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write, |
a7adc4b7 | 2847 | }, |
9c513e78 | 2848 | { .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2, |
9ff9dd3c | 2849 | .secure = ARM_CP_SECSTATE_S, |
daf1dc5f | 2850 | .access = PL0_RW, |
9ff9dd3c PM |
2851 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
2852 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
2853 | .accessfn = gt_ptimer_access, | |
2854 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
2855 | }, | |
a7adc4b7 PM |
2856 | { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, |
2857 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, | |
daf1dc5f | 2858 | .access = PL0_RW, |
a7adc4b7 PM |
2859 | .type = ARM_CP_IO, |
2860 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
12cde08a | 2861 | .resetvalue = 0, .accessfn = gt_ptimer_access, |
0e3eca4c | 2862 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write, |
55d284af PM |
2863 | }, |
2864 | { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, | |
daf1dc5f | 2865 | .access = PL0_RW, |
7a0e58fa | 2866 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 2867 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), |
b061a82b | 2868 | .accessfn = gt_vtimer_access, |
0e3eca4c | 2869 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write, |
a7adc4b7 PM |
2870 | }, |
2871 | { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
2872 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, | |
daf1dc5f | 2873 | .access = PL0_RW, |
a7adc4b7 PM |
2874 | .type = ARM_CP_IO, |
2875 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
2876 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
0e3eca4c | 2877 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write, |
55d284af | 2878 | }, |
b4d3978c PM |
2879 | /* Secure timer -- this is actually restricted to only EL3 |
2880 | * and configurably Secure-EL1 via the accessfn. | |
2881 | */ | |
2882 | { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, | |
2883 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, | |
2884 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, | |
2885 | .accessfn = gt_stimer_access, | |
2886 | .readfn = gt_sec_tval_read, | |
2887 | .writefn = gt_sec_tval_write, | |
2888 | .resetfn = gt_sec_timer_reset, | |
2889 | }, | |
2890 | { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64, | |
2891 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1, | |
2892 | .type = ARM_CP_IO, .access = PL1_RW, | |
2893 | .accessfn = gt_stimer_access, | |
2894 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), | |
2895 | .resetvalue = 0, | |
2896 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
2897 | }, | |
2898 | { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, | |
2899 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, | |
2900 | .type = ARM_CP_IO, .access = PL1_RW, | |
2901 | .accessfn = gt_stimer_access, | |
2902 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
2903 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
2904 | }, | |
55d284af PM |
2905 | REGINFO_SENTINEL |
2906 | }; | |
2907 | ||
2908 | #else | |
26c4a83b AB |
2909 | |
2910 | /* In user-mode most of the generic timer registers are inaccessible | |
2911 | * however modern kernels (4.12+) allow access to cntvct_el0 | |
55d284af | 2912 | */ |
26c4a83b AB |
2913 | |
2914 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2915 | { | |
2916 | /* Currently we have no support for QEMUTimer in linux-user so we | |
2917 | * can't call gt_get_countervalue(env), instead we directly | |
2918 | * call the lower level functions. | |
2919 | */ | |
2920 | return cpu_get_clock() / GTIMER_SCALE; | |
2921 | } | |
2922 | ||
6cc7a3ae | 2923 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
26c4a83b AB |
2924 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, |
2925 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
2926 | .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */, | |
2927 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), | |
2928 | .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE, | |
2929 | }, | |
2930 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
2931 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
2932 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
2933 | .readfn = gt_virt_cnt_read, | |
2934 | }, | |
6cc7a3ae PM |
2935 | REGINFO_SENTINEL |
2936 | }; | |
2937 | ||
55d284af PM |
2938 | #endif |
2939 | ||
c4241c7d | 2940 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 2941 | { |
891a2fe7 | 2942 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8d5c773e | 2943 | raw_write(env, ri, value); |
891a2fe7 | 2944 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8d5c773e | 2945 | raw_write(env, ri, value & 0xfffff6ff); |
4a501606 | 2946 | } else { |
8d5c773e | 2947 | raw_write(env, ri, value & 0xfffff1ff); |
4a501606 | 2948 | } |
4a501606 PM |
2949 | } |
2950 | ||
2951 | #ifndef CONFIG_USER_ONLY | |
2952 | /* get_phys_addr() isn't present for user-mode-only targets */ | |
702a9357 | 2953 | |
3f208fd7 PM |
2954 | static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2955 | bool isread) | |
92611c00 PM |
2956 | { |
2957 | if (ri->opc2 & 4) { | |
87562e4f PM |
2958 | /* The ATS12NSO* operations must trap to EL3 if executed in |
2959 | * Secure EL1 (which can only happen if EL3 is AArch64). | |
2960 | * They are simply UNDEF if executed from NS EL1. | |
2961 | * They function normally from EL2 or EL3. | |
92611c00 | 2962 | */ |
87562e4f PM |
2963 | if (arm_current_el(env) == 1) { |
2964 | if (arm_is_secure_below_el3(env)) { | |
2965 | return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; | |
2966 | } | |
2967 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2968 | } | |
92611c00 PM |
2969 | } |
2970 | return CP_ACCESS_OK; | |
2971 | } | |
2972 | ||
060e8a48 | 2973 | static uint64_t do_ats_write(CPUARMState *env, uint64_t value, |
03ae85f8 | 2974 | MMUAccessType access_type, ARMMMUIdx mmu_idx) |
4a501606 | 2975 | { |
a8170e5e | 2976 | hwaddr phys_addr; |
4a501606 PM |
2977 | target_ulong page_size; |
2978 | int prot; | |
b7cc4e82 | 2979 | bool ret; |
01c097f7 | 2980 | uint64_t par64; |
1313e2d7 | 2981 | bool format64 = false; |
8bf5b6a9 | 2982 | MemTxAttrs attrs = {}; |
e14b5a23 | 2983 | ARMMMUFaultInfo fi = {}; |
5b2d261d | 2984 | ARMCacheAttrs cacheattrs = {}; |
4a501606 | 2985 | |
5b2d261d | 2986 | ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, |
bc52bfeb | 2987 | &prot, &page_size, &fi, &cacheattrs); |
1313e2d7 | 2988 | |
0710b2fa PM |
2989 | if (ret) { |
2990 | /* | |
2991 | * Some kinds of translation fault must cause exceptions rather | |
2992 | * than being reported in the PAR. | |
2993 | */ | |
2994 | int current_el = arm_current_el(env); | |
2995 | int target_el; | |
2996 | uint32_t syn, fsr, fsc; | |
2997 | bool take_exc = false; | |
2998 | ||
2999 | if (fi.s1ptw && current_el == 1 && !arm_is_secure(env) | |
3000 | && (mmu_idx == ARMMMUIdx_S1NSE1 || mmu_idx == ARMMMUIdx_S1NSE0)) { | |
3001 | /* | |
3002 | * Synchronous stage 2 fault on an access made as part of the | |
3003 | * translation table walk for AT S1E0* or AT S1E1* insn | |
3004 | * executed from NS EL1. If this is a synchronous external abort | |
3005 | * and SCR_EL3.EA == 1, then we take a synchronous external abort | |
3006 | * to EL3. Otherwise the fault is taken as an exception to EL2, | |
3007 | * and HPFAR_EL2 holds the faulting IPA. | |
3008 | */ | |
3009 | if (fi.type == ARMFault_SyncExternalOnWalk && | |
3010 | (env->cp15.scr_el3 & SCR_EA)) { | |
3011 | target_el = 3; | |
3012 | } else { | |
3013 | env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; | |
3014 | target_el = 2; | |
3015 | } | |
3016 | take_exc = true; | |
3017 | } else if (fi.type == ARMFault_SyncExternalOnWalk) { | |
3018 | /* | |
3019 | * Synchronous external aborts during a translation table walk | |
3020 | * are taken as Data Abort exceptions. | |
3021 | */ | |
3022 | if (fi.stage2) { | |
3023 | if (current_el == 3) { | |
3024 | target_el = 3; | |
3025 | } else { | |
3026 | target_el = 2; | |
3027 | } | |
3028 | } else { | |
3029 | target_el = exception_target_el(env); | |
3030 | } | |
3031 | take_exc = true; | |
3032 | } | |
3033 | ||
3034 | if (take_exc) { | |
3035 | /* Construct FSR and FSC using same logic as arm_deliver_fault() */ | |
3036 | if (target_el == 2 || arm_el_is_aa64(env, target_el) || | |
3037 | arm_s1_regime_using_lpae_format(env, mmu_idx)) { | |
3038 | fsr = arm_fi_to_lfsc(&fi); | |
3039 | fsc = extract32(fsr, 0, 6); | |
3040 | } else { | |
3041 | fsr = arm_fi_to_sfsc(&fi); | |
3042 | fsc = 0x3f; | |
3043 | } | |
3044 | /* | |
3045 | * Report exception with ESR indicating a fault due to a | |
3046 | * translation table walk for a cache maintenance instruction. | |
3047 | */ | |
3048 | syn = syn_data_abort_no_iss(current_el == target_el, | |
3049 | fi.ea, 1, fi.s1ptw, 1, fsc); | |
3050 | env->exception.vaddress = value; | |
3051 | env->exception.fsr = fsr; | |
3052 | raise_exception(env, EXCP_DATA_ABORT, syn, target_el); | |
3053 | } | |
3054 | } | |
3055 | ||
1313e2d7 EI |
3056 | if (is_a64(env)) { |
3057 | format64 = true; | |
3058 | } else if (arm_feature(env, ARM_FEATURE_LPAE)) { | |
3059 | /* | |
3060 | * ATS1Cxx: | |
3061 | * * TTBCR.EAE determines whether the result is returned using the | |
3062 | * 32-bit or the 64-bit PAR format | |
3063 | * * Instructions executed in Hyp mode always use the 64bit format | |
3064 | * | |
3065 | * ATS1S2NSOxx uses the 64bit format if any of the following is true: | |
3066 | * * The Non-secure TTBCR.EAE bit is set to 1 | |
3067 | * * The implementation includes EL2, and the value of HCR.VM is 1 | |
3068 | * | |
9d1bab33 PM |
3069 | * (Note that HCR.DC makes HCR.VM behave as if it is 1.) |
3070 | * | |
23463e0e | 3071 | * ATS1Hx always uses the 64bit format. |
1313e2d7 EI |
3072 | */ |
3073 | format64 = arm_s1_regime_using_lpae_format(env, mmu_idx); | |
3074 | ||
3075 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
3076 | if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { | |
9d1bab33 | 3077 | format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC); |
1313e2d7 EI |
3078 | } else { |
3079 | format64 |= arm_current_el(env) == 2; | |
3080 | } | |
3081 | } | |
3082 | } | |
3083 | ||
3084 | if (format64) { | |
5efe9ed4 | 3085 | /* Create a 64-bit PAR */ |
01c097f7 | 3086 | par64 = (1 << 11); /* LPAE bit always set */ |
b7cc4e82 | 3087 | if (!ret) { |
702a9357 | 3088 | par64 |= phys_addr & ~0xfffULL; |
8bf5b6a9 PM |
3089 | if (!attrs.secure) { |
3090 | par64 |= (1 << 9); /* NS */ | |
3091 | } | |
5b2d261d AB |
3092 | par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */ |
3093 | par64 |= cacheattrs.shareability << 7; /* SH */ | |
4a501606 | 3094 | } else { |
5efe9ed4 PM |
3095 | uint32_t fsr = arm_fi_to_lfsc(&fi); |
3096 | ||
702a9357 | 3097 | par64 |= 1; /* F */ |
b7cc4e82 | 3098 | par64 |= (fsr & 0x3f) << 1; /* FS */ |
0f7b791b PM |
3099 | if (fi.stage2) { |
3100 | par64 |= (1 << 9); /* S */ | |
3101 | } | |
3102 | if (fi.s1ptw) { | |
3103 | par64 |= (1 << 8); /* PTW */ | |
3104 | } | |
4a501606 PM |
3105 | } |
3106 | } else { | |
b7cc4e82 | 3107 | /* fsr is a DFSR/IFSR value for the short descriptor |
702a9357 PM |
3108 | * translation table format (with WnR always clear). |
3109 | * Convert it to a 32-bit PAR. | |
3110 | */ | |
b7cc4e82 | 3111 | if (!ret) { |
702a9357 PM |
3112 | /* We do not set any attribute bits in the PAR */ |
3113 | if (page_size == (1 << 24) | |
3114 | && arm_feature(env, ARM_FEATURE_V7)) { | |
01c097f7 | 3115 | par64 = (phys_addr & 0xff000000) | (1 << 1); |
702a9357 | 3116 | } else { |
01c097f7 | 3117 | par64 = phys_addr & 0xfffff000; |
702a9357 | 3118 | } |
8bf5b6a9 PM |
3119 | if (!attrs.secure) { |
3120 | par64 |= (1 << 9); /* NS */ | |
3121 | } | |
702a9357 | 3122 | } else { |
5efe9ed4 PM |
3123 | uint32_t fsr = arm_fi_to_sfsc(&fi); |
3124 | ||
b7cc4e82 PC |
3125 | par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | |
3126 | ((fsr & 0xf) << 1) | 1; | |
702a9357 | 3127 | } |
4a501606 | 3128 | } |
060e8a48 PM |
3129 | return par64; |
3130 | } | |
3131 | ||
3132 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | |
3133 | { | |
03ae85f8 | 3134 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
060e8a48 | 3135 | uint64_t par64; |
d3649702 PM |
3136 | ARMMMUIdx mmu_idx; |
3137 | int el = arm_current_el(env); | |
3138 | bool secure = arm_is_secure_below_el3(env); | |
060e8a48 | 3139 | |
d3649702 PM |
3140 | switch (ri->opc2 & 6) { |
3141 | case 0: | |
3142 | /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ | |
3143 | switch (el) { | |
3144 | case 3: | |
3145 | mmu_idx = ARMMMUIdx_S1E3; | |
3146 | break; | |
3147 | case 2: | |
3148 | mmu_idx = ARMMMUIdx_S1NSE1; | |
3149 | break; | |
3150 | case 1: | |
3151 | mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; | |
3152 | break; | |
3153 | default: | |
3154 | g_assert_not_reached(); | |
3155 | } | |
3156 | break; | |
3157 | case 2: | |
3158 | /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ | |
3159 | switch (el) { | |
3160 | case 3: | |
3161 | mmu_idx = ARMMMUIdx_S1SE0; | |
3162 | break; | |
3163 | case 2: | |
3164 | mmu_idx = ARMMMUIdx_S1NSE0; | |
3165 | break; | |
3166 | case 1: | |
3167 | mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; | |
3168 | break; | |
3169 | default: | |
3170 | g_assert_not_reached(); | |
3171 | } | |
3172 | break; | |
3173 | case 4: | |
3174 | /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ | |
3175 | mmu_idx = ARMMMUIdx_S12NSE1; | |
3176 | break; | |
3177 | case 6: | |
3178 | /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ | |
3179 | mmu_idx = ARMMMUIdx_S12NSE0; | |
3180 | break; | |
3181 | default: | |
3182 | g_assert_not_reached(); | |
3183 | } | |
3184 | ||
3185 | par64 = do_ats_write(env, value, access_type, mmu_idx); | |
01c097f7 FA |
3186 | |
3187 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
4a501606 | 3188 | } |
060e8a48 | 3189 | |
14db7fe0 PM |
3190 | static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3191 | uint64_t value) | |
3192 | { | |
03ae85f8 | 3193 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
14db7fe0 PM |
3194 | uint64_t par64; |
3195 | ||
23463e0e | 3196 | par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S1E2); |
14db7fe0 PM |
3197 | |
3198 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
3199 | } | |
3200 | ||
3f208fd7 PM |
3201 | static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3202 | bool isread) | |
2a47df95 PM |
3203 | { |
3204 | if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) { | |
3205 | return CP_ACCESS_TRAP; | |
3206 | } | |
3207 | return CP_ACCESS_OK; | |
3208 | } | |
3209 | ||
060e8a48 PM |
3210 | static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, |
3211 | uint64_t value) | |
3212 | { | |
03ae85f8 | 3213 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
d3649702 PM |
3214 | ARMMMUIdx mmu_idx; |
3215 | int secure = arm_is_secure_below_el3(env); | |
3216 | ||
3217 | switch (ri->opc2 & 6) { | |
3218 | case 0: | |
3219 | switch (ri->opc1) { | |
3220 | case 0: /* AT S1E1R, AT S1E1W */ | |
3221 | mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; | |
3222 | break; | |
3223 | case 4: /* AT S1E2R, AT S1E2W */ | |
3224 | mmu_idx = ARMMMUIdx_S1E2; | |
3225 | break; | |
3226 | case 6: /* AT S1E3R, AT S1E3W */ | |
3227 | mmu_idx = ARMMMUIdx_S1E3; | |
3228 | break; | |
3229 | default: | |
3230 | g_assert_not_reached(); | |
3231 | } | |
3232 | break; | |
3233 | case 2: /* AT S1E0R, AT S1E0W */ | |
3234 | mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; | |
3235 | break; | |
3236 | case 4: /* AT S12E1R, AT S12E1W */ | |
2a47df95 | 3237 | mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1; |
d3649702 PM |
3238 | break; |
3239 | case 6: /* AT S12E0R, AT S12E0W */ | |
2a47df95 | 3240 | mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0; |
d3649702 PM |
3241 | break; |
3242 | default: | |
3243 | g_assert_not_reached(); | |
3244 | } | |
060e8a48 | 3245 | |
d3649702 | 3246 | env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); |
060e8a48 | 3247 | } |
4a501606 PM |
3248 | #endif |
3249 | ||
3250 | static const ARMCPRegInfo vapa_cp_reginfo[] = { | |
3251 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, | |
3252 | .access = PL1_RW, .resetvalue = 0, | |
01c097f7 FA |
3253 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), |
3254 | offsetoflow32(CPUARMState, cp15.par_ns) }, | |
4a501606 PM |
3255 | .writefn = par_write }, |
3256 | #ifndef CONFIG_USER_ONLY | |
87562e4f | 3257 | /* This underdecoding is safe because the reginfo is NO_RAW. */ |
4a501606 | 3258 | { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, |
92611c00 | 3259 | .access = PL1_W, .accessfn = ats_access, |
0710b2fa | 3260 | .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
4a501606 PM |
3261 | #endif |
3262 | REGINFO_SENTINEL | |
3263 | }; | |
3264 | ||
18032bec PM |
3265 | /* Return basic MPU access permission bits. */ |
3266 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
3267 | { | |
3268 | uint32_t ret; | |
3269 | uint32_t mask; | |
3270 | int i; | |
3271 | ret = 0; | |
3272 | mask = 3; | |
3273 | for (i = 0; i < 16; i += 2) { | |
3274 | ret |= (val >> i) & mask; | |
3275 | mask <<= 2; | |
3276 | } | |
3277 | return ret; | |
3278 | } | |
3279 | ||
3280 | /* Pad basic MPU access permission bits to extended format. */ | |
3281 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
3282 | { | |
3283 | uint32_t ret; | |
3284 | uint32_t mask; | |
3285 | int i; | |
3286 | ret = 0; | |
3287 | mask = 3; | |
3288 | for (i = 0; i < 16; i += 2) { | |
3289 | ret |= (val & mask) << i; | |
3290 | mask <<= 2; | |
3291 | } | |
3292 | return ret; | |
3293 | } | |
3294 | ||
c4241c7d PM |
3295 | static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3296 | uint64_t value) | |
18032bec | 3297 | { |
7e09797c | 3298 | env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3299 | } |
3300 | ||
c4241c7d | 3301 | static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3302 | { |
7e09797c | 3303 | return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); |
18032bec PM |
3304 | } |
3305 | ||
c4241c7d PM |
3306 | static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3307 | uint64_t value) | |
18032bec | 3308 | { |
7e09797c | 3309 | env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3310 | } |
3311 | ||
c4241c7d | 3312 | static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3313 | { |
7e09797c | 3314 | return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); |
18032bec PM |
3315 | } |
3316 | ||
6cb0b013 PC |
3317 | static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) |
3318 | { | |
3319 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); | |
3320 | ||
3321 | if (!u32p) { | |
3322 | return 0; | |
3323 | } | |
3324 | ||
1bc04a88 | 3325 | u32p += env->pmsav7.rnr[M_REG_NS]; |
6cb0b013 PC |
3326 | return *u32p; |
3327 | } | |
3328 | ||
3329 | static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3330 | uint64_t value) | |
3331 | { | |
2fc0cc0e | 3332 | ARMCPU *cpu = env_archcpu(env); |
6cb0b013 PC |
3333 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); |
3334 | ||
3335 | if (!u32p) { | |
3336 | return; | |
3337 | } | |
3338 | ||
1bc04a88 | 3339 | u32p += env->pmsav7.rnr[M_REG_NS]; |
d10eb08f | 3340 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ |
6cb0b013 PC |
3341 | *u32p = value; |
3342 | } | |
3343 | ||
6cb0b013 PC |
3344 | static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3345 | uint64_t value) | |
3346 | { | |
2fc0cc0e | 3347 | ARMCPU *cpu = env_archcpu(env); |
6cb0b013 PC |
3348 | uint32_t nrgs = cpu->pmsav7_dregion; |
3349 | ||
3350 | if (value >= nrgs) { | |
3351 | qemu_log_mask(LOG_GUEST_ERROR, | |
3352 | "PMSAv7 RGNR write >= # supported regions, %" PRIu32 | |
3353 | " > %" PRIu32 "\n", (uint32_t)value, nrgs); | |
3354 | return; | |
3355 | } | |
3356 | ||
3357 | raw_write(env, ri, value); | |
3358 | } | |
3359 | ||
3360 | static const ARMCPRegInfo pmsav7_cp_reginfo[] = { | |
69ceea64 PM |
3361 | /* Reset for all these registers is handled in arm_cpu_reset(), |
3362 | * because the PMSAv7 is also used by M-profile CPUs, which do | |
3363 | * not register cpregs but still need the state to be reset. | |
3364 | */ | |
6cb0b013 PC |
3365 | { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, |
3366 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3367 | .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), | |
69ceea64 PM |
3368 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3369 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3370 | { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, |
3371 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3372 | .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), | |
69ceea64 PM |
3373 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3374 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3375 | { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, |
3376 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3377 | .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), | |
69ceea64 PM |
3378 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3379 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3380 | { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, |
3381 | .access = PL1_RW, | |
1bc04a88 | 3382 | .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), |
69ceea64 PM |
3383 | .writefn = pmsav7_rgnr_write, |
3384 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3385 | REGINFO_SENTINEL |
3386 | }; | |
3387 | ||
18032bec PM |
3388 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { |
3389 | { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 3390 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 3391 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
18032bec PM |
3392 | .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, |
3393 | { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 3394 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 3395 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
18032bec PM |
3396 | .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, |
3397 | { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, | |
3398 | .access = PL1_RW, | |
7e09797c PM |
3399 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
3400 | .resetvalue = 0, }, | |
18032bec PM |
3401 | { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, |
3402 | .access = PL1_RW, | |
7e09797c PM |
3403 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
3404 | .resetvalue = 0, }, | |
ecce5c3c PM |
3405 | { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
3406 | .access = PL1_RW, | |
3407 | .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, | |
3408 | { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
3409 | .access = PL1_RW, | |
3410 | .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, | |
06d76f31 | 3411 | /* Protection region base and size registers */ |
e508a92b PM |
3412 | { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, |
3413 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3414 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, | |
3415 | { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, | |
3416 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3417 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, | |
3418 | { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, | |
3419 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3420 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, | |
3421 | { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, | |
3422 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3423 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, | |
3424 | { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, | |
3425 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3426 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, | |
3427 | { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, | |
3428 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3429 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, | |
3430 | { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, | |
3431 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3432 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, | |
3433 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | |
3434 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3435 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | |
18032bec PM |
3436 | REGINFO_SENTINEL |
3437 | }; | |
3438 | ||
c4241c7d PM |
3439 | static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3440 | uint64_t value) | |
ecce5c3c | 3441 | { |
11f136ee | 3442 | TCR *tcr = raw_ptr(env, ri); |
2ebcebe2 PM |
3443 | int maskshift = extract32(value, 0, 3); |
3444 | ||
e389be16 FA |
3445 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
3446 | if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { | |
3447 | /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when | |
3448 | * using Long-desciptor translation table format */ | |
3449 | value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); | |
3450 | } else if (arm_feature(env, ARM_FEATURE_EL3)) { | |
3451 | /* In an implementation that includes the Security Extensions | |
3452 | * TTBCR has additional fields PD0 [4] and PD1 [5] for | |
3453 | * Short-descriptor translation table format. | |
3454 | */ | |
3455 | value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; | |
3456 | } else { | |
3457 | value &= TTBCR_N; | |
3458 | } | |
e42c4db3 | 3459 | } |
e389be16 | 3460 | |
b6af0975 | 3461 | /* Update the masks corresponding to the TCR bank being written |
11f136ee | 3462 | * Note that we always calculate mask and base_mask, but |
e42c4db3 | 3463 | * they are only used for short-descriptor tables (ie if EAE is 0); |
11f136ee FA |
3464 | * for long-descriptor tables the TCR fields are used differently |
3465 | * and the mask and base_mask values are meaningless. | |
e42c4db3 | 3466 | */ |
11f136ee FA |
3467 | tcr->raw_tcr = value; |
3468 | tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift); | |
3469 | tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift); | |
ecce5c3c PM |
3470 | } |
3471 | ||
c4241c7d PM |
3472 | static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3473 | uint64_t value) | |
d4e6df63 | 3474 | { |
2fc0cc0e | 3475 | ARMCPU *cpu = env_archcpu(env); |
ab638a32 | 3476 | TCR *tcr = raw_ptr(env, ri); |
00c8cb0a | 3477 | |
d4e6df63 PM |
3478 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
3479 | /* With LPAE the TTBCR could result in a change of ASID | |
3480 | * via the TTBCR.A1 bit, so do a TLB flush. | |
3481 | */ | |
d10eb08f | 3482 | tlb_flush(CPU(cpu)); |
d4e6df63 | 3483 | } |
ab638a32 RH |
3484 | /* Preserve the high half of TCR_EL1, set via TTBCR2. */ |
3485 | value = deposit64(tcr->raw_tcr, 0, 32, value); | |
c4241c7d | 3486 | vmsa_ttbcr_raw_write(env, ri, value); |
d4e6df63 PM |
3487 | } |
3488 | ||
ecce5c3c PM |
3489 | static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
3490 | { | |
11f136ee FA |
3491 | TCR *tcr = raw_ptr(env, ri); |
3492 | ||
3493 | /* Reset both the TCR as well as the masks corresponding to the bank of | |
3494 | * the TCR being reset. | |
3495 | */ | |
3496 | tcr->raw_tcr = 0; | |
3497 | tcr->mask = 0; | |
3498 | tcr->base_mask = 0xffffc000u; | |
ecce5c3c PM |
3499 | } |
3500 | ||
cb2e37df PM |
3501 | static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3502 | uint64_t value) | |
3503 | { | |
2fc0cc0e | 3504 | ARMCPU *cpu = env_archcpu(env); |
11f136ee | 3505 | TCR *tcr = raw_ptr(env, ri); |
00c8cb0a | 3506 | |
cb2e37df | 3507 | /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ |
d10eb08f | 3508 | tlb_flush(CPU(cpu)); |
11f136ee | 3509 | tcr->raw_tcr = value; |
cb2e37df PM |
3510 | } |
3511 | ||
327ed10f PM |
3512 | static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3513 | uint64_t value) | |
3514 | { | |
93f379b0 RH |
3515 | /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ |
3516 | if (cpreg_field_is_64bit(ri) && | |
3517 | extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { | |
2fc0cc0e | 3518 | ARMCPU *cpu = env_archcpu(env); |
d10eb08f | 3519 | tlb_flush(CPU(cpu)); |
327ed10f PM |
3520 | } |
3521 | raw_write(env, ri, value); | |
3522 | } | |
3523 | ||
b698e9cf EI |
3524 | static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3525 | uint64_t value) | |
3526 | { | |
2fc0cc0e | 3527 | ARMCPU *cpu = env_archcpu(env); |
b698e9cf EI |
3528 | CPUState *cs = CPU(cpu); |
3529 | ||
3530 | /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ | |
3531 | if (raw_read(env, ri) != value) { | |
0336cbf8 | 3532 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
3533 | ARMMMUIdxBit_S12NSE1 | |
3534 | ARMMMUIdxBit_S12NSE0 | | |
3535 | ARMMMUIdxBit_S2NS); | |
b698e9cf EI |
3536 | raw_write(env, ri, value); |
3537 | } | |
3538 | } | |
3539 | ||
8e5d75c9 | 3540 | static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { |
18032bec | 3541 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, |
7a0e58fa | 3542 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
4a7e2d73 | 3543 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), |
b061a82b | 3544 | offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, |
18032bec | 3545 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, |
88ca1c2d FA |
3546 | .access = PL1_RW, .resetvalue = 0, |
3547 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), | |
3548 | offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, | |
8e5d75c9 PC |
3549 | { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, |
3550 | .access = PL1_RW, .resetvalue = 0, | |
3551 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), | |
3552 | offsetof(CPUARMState, cp15.dfar_ns) } }, | |
3553 | { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, | |
3554 | .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, | |
3555 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), | |
3556 | .resetvalue = 0, }, | |
3557 | REGINFO_SENTINEL | |
3558 | }; | |
3559 | ||
3560 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { | |
6cd8a264 RH |
3561 | { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, |
3562 | .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, | |
3563 | .access = PL1_RW, | |
d81c519c | 3564 | .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, |
327ed10f | 3565 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af FA |
3566 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, |
3567 | .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
3568 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), | |
3569 | offsetof(CPUARMState, cp15.ttbr0_ns) } }, | |
327ed10f | 3570 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af FA |
3571 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, |
3572 | .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
3573 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), | |
3574 | offsetof(CPUARMState, cp15.ttbr1_ns) } }, | |
cb2e37df PM |
3575 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, |
3576 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | |
3577 | .access = PL1_RW, .writefn = vmsa_tcr_el1_write, | |
3578 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, | |
11f136ee | 3579 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, |
cb2e37df | 3580 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
7a0e58fa | 3581 | .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, |
b061a82b | 3582 | .raw_writefn = vmsa_ttbcr_raw_write, |
11f136ee FA |
3583 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), |
3584 | offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, | |
18032bec PM |
3585 | REGINFO_SENTINEL |
3586 | }; | |
3587 | ||
ab638a32 RH |
3588 | /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing |
3589 | * qemu tlbs nor adjusting cached masks. | |
3590 | */ | |
3591 | static const ARMCPRegInfo ttbcr2_reginfo = { | |
3592 | .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3, | |
3593 | .access = PL1_RW, .type = ARM_CP_ALIAS, | |
3594 | .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), | |
3595 | offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, | |
3596 | }; | |
3597 | ||
c4241c7d PM |
3598 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3599 | uint64_t value) | |
1047b9d7 PM |
3600 | { |
3601 | env->cp15.c15_ticonfig = value & 0xe7; | |
3602 | /* The OS_TYPE bit in this register changes the reported CPUID! */ | |
3603 | env->cp15.c0_cpuid = (value & (1 << 5)) ? | |
3604 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1047b9d7 PM |
3605 | } |
3606 | ||
c4241c7d PM |
3607 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3608 | uint64_t value) | |
1047b9d7 PM |
3609 | { |
3610 | env->cp15.c15_threadid = value & 0xffff; | |
1047b9d7 PM |
3611 | } |
3612 | ||
c4241c7d PM |
3613 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3614 | uint64_t value) | |
1047b9d7 PM |
3615 | { |
3616 | /* Wait-for-interrupt (deprecated) */ | |
2fc0cc0e | 3617 | cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); |
1047b9d7 PM |
3618 | } |
3619 | ||
c4241c7d PM |
3620 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3621 | uint64_t value) | |
c4804214 PM |
3622 | { |
3623 | /* On OMAP there are registers indicating the max/min index of dcache lines | |
3624 | * containing a dirty line; cache flush operations have to reset these. | |
3625 | */ | |
3626 | env->cp15.c15_i_max = 0x000; | |
3627 | env->cp15.c15_i_min = 0xff0; | |
c4804214 PM |
3628 | } |
3629 | ||
18032bec PM |
3630 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
3631 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, | |
3632 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, | |
d81c519c | 3633 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 3634 | .resetvalue = 0, }, |
1047b9d7 PM |
3635 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
3636 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
3637 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
3638 | .access = PL1_RW, | |
3639 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, | |
3640 | .writefn = omap_ticonfig_write }, | |
3641 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, | |
3642 | .access = PL1_RW, | |
3643 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, | |
3644 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, | |
3645 | .access = PL1_RW, .resetvalue = 0xff0, | |
3646 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, | |
3647 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, | |
3648 | .access = PL1_RW, | |
3649 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, | |
3650 | .writefn = omap_threadid_write }, | |
3651 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, | |
3652 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
7a0e58fa | 3653 | .type = ARM_CP_NO_RAW, |
1047b9d7 PM |
3654 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
3655 | /* TODO: Peripheral port remap register: | |
3656 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller | |
3657 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), | |
3658 | * when MMU is off. | |
3659 | */ | |
c4804214 | 3660 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
d4e6df63 | 3661 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
7a0e58fa | 3662 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, |
c4804214 | 3663 | .writefn = omap_cachemaint_write }, |
34f90529 PM |
3664 | { .name = "C9", .cp = 15, .crn = 9, |
3665 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | |
3666 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | |
1047b9d7 PM |
3667 | REGINFO_SENTINEL |
3668 | }; | |
3669 | ||
c4241c7d PM |
3670 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3671 | uint64_t value) | |
1047b9d7 | 3672 | { |
c0f4af17 | 3673 | env->cp15.c15_cpar = value & 0x3fff; |
1047b9d7 PM |
3674 | } |
3675 | ||
3676 | static const ARMCPRegInfo xscale_cp_reginfo[] = { | |
3677 | { .name = "XSCALE_CPAR", | |
3678 | .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
3679 | .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, | |
3680 | .writefn = xscale_cpar_write, }, | |
2771db27 PM |
3681 | { .name = "XSCALE_AUXCR", |
3682 | .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, | |
3683 | .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), | |
3684 | .resetvalue = 0, }, | |
3b771579 PM |
3685 | /* XScale specific cache-lockdown: since we have no cache we NOP these |
3686 | * and hope the guest does not really rely on cache behaviour. | |
3687 | */ | |
3688 | { .name = "XSCALE_LOCK_ICACHE_LINE", | |
3689 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
3690 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3691 | { .name = "XSCALE_UNLOCK_ICACHE", | |
3692 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
3693 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3694 | { .name = "XSCALE_DCACHE_LOCK", | |
3695 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, | |
3696 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
3697 | { .name = "XSCALE_UNLOCK_DCACHE", | |
3698 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, | |
3699 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1047b9d7 PM |
3700 | REGINFO_SENTINEL |
3701 | }; | |
3702 | ||
3703 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | |
3704 | /* RAZ/WI the whole crn=15 space, when we don't have a more specific | |
3705 | * implementation of this implementation-defined space. | |
3706 | * Ideally this should eventually disappear in favour of actually | |
3707 | * implementing the correct behaviour for all cores. | |
3708 | */ | |
3709 | { .name = "C15_IMPDEF", .cp = 15, .crn = 15, | |
3710 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
3671cd87 | 3711 | .access = PL1_RW, |
7a0e58fa | 3712 | .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, |
d4e6df63 | 3713 | .resetvalue = 0 }, |
18032bec PM |
3714 | REGINFO_SENTINEL |
3715 | }; | |
3716 | ||
c4804214 PM |
3717 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
3718 | /* Cache status: RAZ because we have no cache so it's always clean */ | |
3719 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | |
7a0e58fa | 3720 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 3721 | .resetvalue = 0 }, |
c4804214 PM |
3722 | REGINFO_SENTINEL |
3723 | }; | |
3724 | ||
3725 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | |
3726 | /* We never have a a block transfer operation in progress */ | |
3727 | { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, | |
7a0e58fa | 3728 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 3729 | .resetvalue = 0 }, |
30b05bba PM |
3730 | /* The cache ops themselves: these all NOP for QEMU */ |
3731 | { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, | |
3732 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3733 | { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, | |
3734 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3735 | { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, | |
3736 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3737 | { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, | |
3738 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3739 | { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, | |
3740 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3741 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, | |
3742 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
c4804214 PM |
3743 | REGINFO_SENTINEL |
3744 | }; | |
3745 | ||
3746 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | |
3747 | /* The cache test-and-clean instructions always return (1 << 30) | |
3748 | * to indicate that there are no dirty cache lines. | |
3749 | */ | |
3750 | { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, | |
7a0e58fa | 3751 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 3752 | .resetvalue = (1 << 30) }, |
c4804214 | 3753 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
7a0e58fa | 3754 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 3755 | .resetvalue = (1 << 30) }, |
c4804214 PM |
3756 | REGINFO_SENTINEL |
3757 | }; | |
3758 | ||
34f90529 PM |
3759 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
3760 | /* Ignore ReadBuffer accesses */ | |
3761 | { .name = "C9_READBUFFER", .cp = 15, .crn = 9, | |
3762 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
d4e6df63 | 3763 | .access = PL1_RW, .resetvalue = 0, |
7a0e58fa | 3764 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, |
34f90529 PM |
3765 | REGINFO_SENTINEL |
3766 | }; | |
3767 | ||
731de9e6 EI |
3768 | static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
3769 | { | |
2fc0cc0e | 3770 | ARMCPU *cpu = env_archcpu(env); |
731de9e6 EI |
3771 | unsigned int cur_el = arm_current_el(env); |
3772 | bool secure = arm_is_secure(env); | |
3773 | ||
3774 | if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { | |
3775 | return env->cp15.vpidr_el2; | |
3776 | } | |
3777 | return raw_read(env, ri); | |
3778 | } | |
3779 | ||
06a7e647 | 3780 | static uint64_t mpidr_read_val(CPUARMState *env) |
81bdde9d | 3781 | { |
2fc0cc0e | 3782 | ARMCPU *cpu = env_archcpu(env); |
eb5e1d3c PF |
3783 | uint64_t mpidr = cpu->mp_affinity; |
3784 | ||
81bdde9d | 3785 | if (arm_feature(env, ARM_FEATURE_V7MP)) { |
78dbbbe4 | 3786 | mpidr |= (1U << 31); |
81bdde9d PM |
3787 | /* Cores which are uniprocessor (non-coherent) |
3788 | * but still implement the MP extensions set | |
a8e81b31 | 3789 | * bit 30. (For instance, Cortex-R5). |
81bdde9d | 3790 | */ |
a8e81b31 PC |
3791 | if (cpu->mp_is_up) { |
3792 | mpidr |= (1u << 30); | |
3793 | } | |
81bdde9d | 3794 | } |
c4241c7d | 3795 | return mpidr; |
81bdde9d PM |
3796 | } |
3797 | ||
06a7e647 EI |
3798 | static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
3799 | { | |
f0d574d6 EI |
3800 | unsigned int cur_el = arm_current_el(env); |
3801 | bool secure = arm_is_secure(env); | |
3802 | ||
3803 | if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { | |
3804 | return env->cp15.vmpidr_el2; | |
3805 | } | |
06a7e647 EI |
3806 | return mpidr_read_val(env); |
3807 | } | |
3808 | ||
7ac681cf | 3809 | static const ARMCPRegInfo lpae_cp_reginfo[] = { |
a903c449 | 3810 | /* NOP AMAIR0/1 */ |
b0fe2427 PM |
3811 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, |
3812 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | |
a903c449 | 3813 | .access = PL1_RW, .type = ARM_CP_CONST, |
7ac681cf | 3814 | .resetvalue = 0 }, |
b0fe2427 | 3815 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ |
7ac681cf | 3816 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
a903c449 | 3817 | .access = PL1_RW, .type = ARM_CP_CONST, |
7ac681cf | 3818 | .resetvalue = 0 }, |
891a2fe7 | 3819 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
01c097f7 FA |
3820 | .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, |
3821 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), | |
3822 | offsetof(CPUARMState, cp15.par_ns)} }, | |
891a2fe7 | 3823 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, |
7a0e58fa | 3824 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, |
7dd8c9af FA |
3825 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
3826 | offsetof(CPUARMState, cp15.ttbr0_ns) }, | |
b061a82b | 3827 | .writefn = vmsa_ttbr_write, }, |
891a2fe7 | 3828 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
7a0e58fa | 3829 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, |
7dd8c9af FA |
3830 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
3831 | offsetof(CPUARMState, cp15.ttbr1_ns) }, | |
b061a82b | 3832 | .writefn = vmsa_ttbr_write, }, |
7ac681cf PM |
3833 | REGINFO_SENTINEL |
3834 | }; | |
3835 | ||
c4241c7d | 3836 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 3837 | { |
c4241c7d | 3838 | return vfp_get_fpcr(env); |
b0d2b7d0 PM |
3839 | } |
3840 | ||
c4241c7d PM |
3841 | static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3842 | uint64_t value) | |
b0d2b7d0 PM |
3843 | { |
3844 | vfp_set_fpcr(env, value); | |
b0d2b7d0 PM |
3845 | } |
3846 | ||
c4241c7d | 3847 | static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 3848 | { |
c4241c7d | 3849 | return vfp_get_fpsr(env); |
b0d2b7d0 PM |
3850 | } |
3851 | ||
c4241c7d PM |
3852 | static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3853 | uint64_t value) | |
b0d2b7d0 PM |
3854 | { |
3855 | vfp_set_fpsr(env, value); | |
b0d2b7d0 PM |
3856 | } |
3857 | ||
3f208fd7 PM |
3858 | static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3859 | bool isread) | |
c2b820fe | 3860 | { |
137feaa9 | 3861 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { |
c2b820fe PM |
3862 | return CP_ACCESS_TRAP; |
3863 | } | |
3864 | return CP_ACCESS_OK; | |
3865 | } | |
3866 | ||
3867 | static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3868 | uint64_t value) | |
3869 | { | |
3870 | env->daif = value & PSTATE_DAIF; | |
3871 | } | |
3872 | ||
8af35c37 | 3873 | static CPAccessResult aa64_cacheop_access(CPUARMState *env, |
3f208fd7 PM |
3874 | const ARMCPRegInfo *ri, |
3875 | bool isread) | |
8af35c37 PM |
3876 | { |
3877 | /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless | |
3878 | * SCTLR_EL1.UCI is set. | |
3879 | */ | |
137feaa9 | 3880 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) { |
8af35c37 PM |
3881 | return CP_ACCESS_TRAP; |
3882 | } | |
3883 | return CP_ACCESS_OK; | |
3884 | } | |
3885 | ||
dbb1fb27 AB |
3886 | /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions |
3887 | * Page D4-1736 (DDI0487A.b) | |
3888 | */ | |
3889 | ||
fd3ed969 PM |
3890 | static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3891 | uint64_t value) | |
168aa23b | 3892 | { |
29a0af61 | 3893 | CPUState *cs = env_cpu(env); |
fd3ed969 | 3894 | bool sec = arm_is_secure_below_el3(env); |
dbb1fb27 | 3895 | |
a67cf277 AB |
3896 | if (sec) { |
3897 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3898 | ARMMMUIdxBit_S1SE1 | |
3899 | ARMMMUIdxBit_S1SE0); | |
a67cf277 AB |
3900 | } else { |
3901 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3902 | ARMMMUIdxBit_S12NSE1 | |
3903 | ARMMMUIdxBit_S12NSE0); | |
fd3ed969 | 3904 | } |
168aa23b PM |
3905 | } |
3906 | ||
b4ab8ce9 PM |
3907 | static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3908 | uint64_t value) | |
3909 | { | |
29a0af61 | 3910 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
3911 | |
3912 | if (tlb_force_broadcast(env)) { | |
09a86dfa | 3913 | tlbi_aa64_vmalle1is_write(env, NULL, value); |
b4ab8ce9 PM |
3914 | return; |
3915 | } | |
3916 | ||
3917 | if (arm_is_secure_below_el3(env)) { | |
3918 | tlb_flush_by_mmuidx(cs, | |
3919 | ARMMMUIdxBit_S1SE1 | | |
3920 | ARMMMUIdxBit_S1SE0); | |
3921 | } else { | |
3922 | tlb_flush_by_mmuidx(cs, | |
3923 | ARMMMUIdxBit_S12NSE1 | | |
3924 | ARMMMUIdxBit_S12NSE0); | |
3925 | } | |
3926 | } | |
3927 | ||
fd3ed969 PM |
3928 | static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3929 | uint64_t value) | |
168aa23b | 3930 | { |
fd3ed969 PM |
3931 | /* Note that the 'ALL' scope must invalidate both stage 1 and |
3932 | * stage 2 translations, whereas most other scopes only invalidate | |
3933 | * stage 1 translations. | |
3934 | */ | |
2fc0cc0e | 3935 | ARMCPU *cpu = env_archcpu(env); |
fd3ed969 PM |
3936 | CPUState *cs = CPU(cpu); |
3937 | ||
3938 | if (arm_is_secure_below_el3(env)) { | |
0336cbf8 | 3939 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
3940 | ARMMMUIdxBit_S1SE1 | |
3941 | ARMMMUIdxBit_S1SE0); | |
fd3ed969 PM |
3942 | } else { |
3943 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
0336cbf8 | 3944 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
3945 | ARMMMUIdxBit_S12NSE1 | |
3946 | ARMMMUIdxBit_S12NSE0 | | |
3947 | ARMMMUIdxBit_S2NS); | |
fd3ed969 | 3948 | } else { |
0336cbf8 | 3949 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
3950 | ARMMMUIdxBit_S12NSE1 | |
3951 | ARMMMUIdxBit_S12NSE0); | |
fd3ed969 PM |
3952 | } |
3953 | } | |
168aa23b PM |
3954 | } |
3955 | ||
fd3ed969 | 3956 | static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
fa439fc5 PM |
3957 | uint64_t value) |
3958 | { | |
2fc0cc0e | 3959 | ARMCPU *cpu = env_archcpu(env); |
fd3ed969 PM |
3960 | CPUState *cs = CPU(cpu); |
3961 | ||
8bd5c820 | 3962 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); |
fd3ed969 PM |
3963 | } |
3964 | ||
43efaa33 PM |
3965 | static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3966 | uint64_t value) | |
3967 | { | |
2fc0cc0e | 3968 | ARMCPU *cpu = env_archcpu(env); |
43efaa33 PM |
3969 | CPUState *cs = CPU(cpu); |
3970 | ||
8bd5c820 | 3971 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3); |
43efaa33 PM |
3972 | } |
3973 | ||
fd3ed969 PM |
3974 | static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3975 | uint64_t value) | |
3976 | { | |
3977 | /* Note that the 'ALL' scope must invalidate both stage 1 and | |
3978 | * stage 2 translations, whereas most other scopes only invalidate | |
3979 | * stage 1 translations. | |
3980 | */ | |
29a0af61 | 3981 | CPUState *cs = env_cpu(env); |
fd3ed969 PM |
3982 | bool sec = arm_is_secure_below_el3(env); |
3983 | bool has_el2 = arm_feature(env, ARM_FEATURE_EL2); | |
a67cf277 AB |
3984 | |
3985 | if (sec) { | |
3986 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3987 | ARMMMUIdxBit_S1SE1 | |
3988 | ARMMMUIdxBit_S1SE0); | |
a67cf277 AB |
3989 | } else if (has_el2) { |
3990 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3991 | ARMMMUIdxBit_S12NSE1 | |
3992 | ARMMMUIdxBit_S12NSE0 | | |
3993 | ARMMMUIdxBit_S2NS); | |
a67cf277 AB |
3994 | } else { |
3995 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3996 | ARMMMUIdxBit_S12NSE1 | |
3997 | ARMMMUIdxBit_S12NSE0); | |
fa439fc5 PM |
3998 | } |
3999 | } | |
4000 | ||
2bfb9d75 PM |
4001 | static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4002 | uint64_t value) | |
4003 | { | |
29a0af61 | 4004 | CPUState *cs = env_cpu(env); |
2bfb9d75 | 4005 | |
8bd5c820 | 4006 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); |
2bfb9d75 PM |
4007 | } |
4008 | ||
43efaa33 PM |
4009 | static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4010 | uint64_t value) | |
4011 | { | |
29a0af61 | 4012 | CPUState *cs = env_cpu(env); |
43efaa33 | 4013 | |
8bd5c820 | 4014 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3); |
43efaa33 PM |
4015 | } |
4016 | ||
fd3ed969 PM |
4017 | static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4018 | uint64_t value) | |
fa439fc5 | 4019 | { |
fd3ed969 PM |
4020 | /* Invalidate by VA, EL2 |
4021 | * Currently handles both VAE2 and VALE2, since we don't support | |
4022 | * flush-last-level-only. | |
4023 | */ | |
2fc0cc0e | 4024 | ARMCPU *cpu = env_archcpu(env); |
fd3ed969 PM |
4025 | CPUState *cs = CPU(cpu); |
4026 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
4027 | ||
8bd5c820 | 4028 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); |
fd3ed969 PM |
4029 | } |
4030 | ||
43efaa33 PM |
4031 | static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4032 | uint64_t value) | |
4033 | { | |
4034 | /* Invalidate by VA, EL3 | |
4035 | * Currently handles both VAE3 and VALE3, since we don't support | |
4036 | * flush-last-level-only. | |
4037 | */ | |
2fc0cc0e | 4038 | ARMCPU *cpu = env_archcpu(env); |
43efaa33 PM |
4039 | CPUState *cs = CPU(cpu); |
4040 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
4041 | ||
8bd5c820 | 4042 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3); |
43efaa33 PM |
4043 | } |
4044 | ||
fd3ed969 PM |
4045 | static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4046 | uint64_t value) | |
4047 | { | |
2fc0cc0e | 4048 | ARMCPU *cpu = env_archcpu(env); |
a67cf277 | 4049 | CPUState *cs = CPU(cpu); |
fd3ed969 | 4050 | bool sec = arm_is_secure_below_el3(env); |
fa439fc5 PM |
4051 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
4052 | ||
a67cf277 AB |
4053 | if (sec) { |
4054 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, | |
8bd5c820 PM |
4055 | ARMMMUIdxBit_S1SE1 | |
4056 | ARMMMUIdxBit_S1SE0); | |
a67cf277 AB |
4057 | } else { |
4058 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, | |
8bd5c820 PM |
4059 | ARMMMUIdxBit_S12NSE1 | |
4060 | ARMMMUIdxBit_S12NSE0); | |
fa439fc5 PM |
4061 | } |
4062 | } | |
4063 | ||
b4ab8ce9 PM |
4064 | static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4065 | uint64_t value) | |
4066 | { | |
4067 | /* Invalidate by VA, EL1&0 (AArch64 version). | |
4068 | * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, | |
4069 | * since we don't support flush-for-specific-ASID-only or | |
4070 | * flush-last-level-only. | |
4071 | */ | |
2fc0cc0e | 4072 | ARMCPU *cpu = env_archcpu(env); |
b4ab8ce9 PM |
4073 | CPUState *cs = CPU(cpu); |
4074 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
4075 | ||
4076 | if (tlb_force_broadcast(env)) { | |
4077 | tlbi_aa64_vae1is_write(env, NULL, value); | |
4078 | return; | |
4079 | } | |
4080 | ||
4081 | if (arm_is_secure_below_el3(env)) { | |
4082 | tlb_flush_page_by_mmuidx(cs, pageaddr, | |
4083 | ARMMMUIdxBit_S1SE1 | | |
4084 | ARMMMUIdxBit_S1SE0); | |
4085 | } else { | |
4086 | tlb_flush_page_by_mmuidx(cs, pageaddr, | |
4087 | ARMMMUIdxBit_S12NSE1 | | |
4088 | ARMMMUIdxBit_S12NSE0); | |
4089 | } | |
4090 | } | |
4091 | ||
fd3ed969 PM |
4092 | static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4093 | uint64_t value) | |
fa439fc5 | 4094 | { |
29a0af61 | 4095 | CPUState *cs = env_cpu(env); |
fd3ed969 | 4096 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
fa439fc5 | 4097 | |
a67cf277 | 4098 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 4099 | ARMMMUIdxBit_S1E2); |
fa439fc5 PM |
4100 | } |
4101 | ||
43efaa33 PM |
4102 | static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4103 | uint64_t value) | |
4104 | { | |
29a0af61 | 4105 | CPUState *cs = env_cpu(env); |
43efaa33 PM |
4106 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
4107 | ||
a67cf277 | 4108 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 4109 | ARMMMUIdxBit_S1E3); |
43efaa33 PM |
4110 | } |
4111 | ||
cea66e91 PM |
4112 | static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4113 | uint64_t value) | |
4114 | { | |
4115 | /* Invalidate by IPA. This has to invalidate any structures that | |
4116 | * contain only stage 2 translation information, but does not need | |
4117 | * to apply to structures that contain combined stage 1 and stage 2 | |
4118 | * translation information. | |
4119 | * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. | |
4120 | */ | |
2fc0cc0e | 4121 | ARMCPU *cpu = env_archcpu(env); |
cea66e91 PM |
4122 | CPUState *cs = CPU(cpu); |
4123 | uint64_t pageaddr; | |
4124 | ||
4125 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
4126 | return; | |
4127 | } | |
4128 | ||
4129 | pageaddr = sextract64(value << 12, 0, 48); | |
4130 | ||
8bd5c820 | 4131 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); |
cea66e91 PM |
4132 | } |
4133 | ||
4134 | static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4135 | uint64_t value) | |
4136 | { | |
29a0af61 | 4137 | CPUState *cs = env_cpu(env); |
cea66e91 PM |
4138 | uint64_t pageaddr; |
4139 | ||
4140 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
4141 | return; | |
4142 | } | |
4143 | ||
4144 | pageaddr = sextract64(value << 12, 0, 48); | |
4145 | ||
a67cf277 | 4146 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 4147 | ARMMMUIdxBit_S2NS); |
cea66e91 PM |
4148 | } |
4149 | ||
3f208fd7 PM |
4150 | static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4151 | bool isread) | |
aca3f40b PM |
4152 | { |
4153 | /* We don't implement EL2, so the only control on DC ZVA is the | |
4154 | * bit in the SCTLR which can prohibit access for EL0. | |
4155 | */ | |
137feaa9 | 4156 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) { |
aca3f40b PM |
4157 | return CP_ACCESS_TRAP; |
4158 | } | |
4159 | return CP_ACCESS_OK; | |
4160 | } | |
4161 | ||
4162 | static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
4163 | { | |
2fc0cc0e | 4164 | ARMCPU *cpu = env_archcpu(env); |
aca3f40b PM |
4165 | int dzp_bit = 1 << 4; |
4166 | ||
4167 | /* DZP indicates whether DC ZVA access is allowed */ | |
3f208fd7 | 4168 | if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) { |
aca3f40b PM |
4169 | dzp_bit = 0; |
4170 | } | |
4171 | return cpu->dcz_blocksize | dzp_bit; | |
4172 | } | |
4173 | ||
3f208fd7 PM |
4174 | static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4175 | bool isread) | |
f502cfc2 | 4176 | { |
cdcf1405 | 4177 | if (!(env->pstate & PSTATE_SP)) { |
f502cfc2 PM |
4178 | /* Access to SP_EL0 is undefined if it's being used as |
4179 | * the stack pointer. | |
4180 | */ | |
4181 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
4182 | } | |
4183 | return CP_ACCESS_OK; | |
4184 | } | |
4185 | ||
4186 | static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
4187 | { | |
4188 | return env->pstate & PSTATE_SP; | |
4189 | } | |
4190 | ||
4191 | static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
4192 | { | |
4193 | update_spsel(env, val); | |
4194 | } | |
4195 | ||
137feaa9 FA |
4196 | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4197 | uint64_t value) | |
4198 | { | |
2fc0cc0e | 4199 | ARMCPU *cpu = env_archcpu(env); |
137feaa9 FA |
4200 | |
4201 | if (raw_read(env, ri) == value) { | |
4202 | /* Skip the TLB flush if nothing actually changed; Linux likes | |
4203 | * to do a lot of pointless SCTLR writes. | |
4204 | */ | |
4205 | return; | |
4206 | } | |
4207 | ||
06312feb PM |
4208 | if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { |
4209 | /* M bit is RAZ/WI for PMSA with no MPU implemented */ | |
4210 | value &= ~SCTLR_M; | |
4211 | } | |
4212 | ||
137feaa9 FA |
4213 | raw_write(env, ri, value); |
4214 | /* ??? Lots of these bits are not implemented. */ | |
4215 | /* This may enable/disable the MMU, so do a TLB flush. */ | |
d10eb08f | 4216 | tlb_flush(CPU(cpu)); |
2e5dcf36 RH |
4217 | |
4218 | if (ri->type & ARM_CP_SUPPRESS_TB_END) { | |
4219 | /* | |
4220 | * Normally we would always end the TB on an SCTLR write; see the | |
4221 | * comment in ARMCPRegInfo sctlr initialization below for why Xscale | |
4222 | * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild | |
4223 | * of hflags from the translator, so do it here. | |
4224 | */ | |
4225 | arm_rebuild_hflags(env); | |
4226 | } | |
137feaa9 FA |
4227 | } |
4228 | ||
3f208fd7 PM |
4229 | static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4230 | bool isread) | |
03fbf20f PM |
4231 | { |
4232 | if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { | |
f2cae609 | 4233 | return CP_ACCESS_TRAP_FP_EL2; |
03fbf20f PM |
4234 | } |
4235 | if (env->cp15.cptr_el[3] & CPTR_TFP) { | |
f2cae609 | 4236 | return CP_ACCESS_TRAP_FP_EL3; |
03fbf20f PM |
4237 | } |
4238 | return CP_ACCESS_OK; | |
4239 | } | |
4240 | ||
a8d64e73 PM |
4241 | static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4242 | uint64_t value) | |
4243 | { | |
4244 | env->cp15.mdcr_el3 = value & SDCR_VALID_MASK; | |
4245 | } | |
4246 | ||
b0d2b7d0 PM |
4247 | static const ARMCPRegInfo v8_cp_reginfo[] = { |
4248 | /* Minimal set of EL0-visible registers. This will need to be expanded | |
4249 | * significantly for system emulation of AArch64 CPUs. | |
4250 | */ | |
4251 | { .name = "NZCV", .state = ARM_CP_STATE_AA64, | |
4252 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, | |
4253 | .access = PL0_RW, .type = ARM_CP_NZCV }, | |
c2b820fe PM |
4254 | { .name = "DAIF", .state = ARM_CP_STATE_AA64, |
4255 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, | |
7a0e58fa | 4256 | .type = ARM_CP_NO_RAW, |
c2b820fe PM |
4257 | .access = PL0_RW, .accessfn = aa64_daif_access, |
4258 | .fieldoffset = offsetof(CPUARMState, daif), | |
4259 | .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, | |
b0d2b7d0 PM |
4260 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, |
4261 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | |
b916c9c3 | 4262 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 4263 | .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, |
b0d2b7d0 PM |
4264 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, |
4265 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | |
b916c9c3 | 4266 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 4267 | .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, |
b0d2b7d0 PM |
4268 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, |
4269 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | |
7a0e58fa | 4270 | .access = PL0_R, .type = ARM_CP_NO_RAW, |
aca3f40b PM |
4271 | .readfn = aa64_dczid_read }, |
4272 | { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, | |
4273 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, | |
4274 | .access = PL0_W, .type = ARM_CP_DC_ZVA, | |
4275 | #ifndef CONFIG_USER_ONLY | |
4276 | /* Avoid overhead of an access check that always passes in user-mode */ | |
4277 | .accessfn = aa64_zva_access, | |
4278 | #endif | |
4279 | }, | |
0eef9d98 PM |
4280 | { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, |
4281 | .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, | |
4282 | .access = PL1_R, .type = ARM_CP_CURRENTEL }, | |
8af35c37 PM |
4283 | /* Cache ops: all NOPs since we don't emulate caches */ |
4284 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, | |
4285 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
4286 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4287 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, | |
4288 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
4289 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4290 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, | |
4291 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | |
4292 | .access = PL0_W, .type = ARM_CP_NOP, | |
4293 | .accessfn = aa64_cacheop_access }, | |
4294 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, | |
4295 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
4296 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4297 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, | |
4298 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
4299 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4300 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, | |
4301 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | |
4302 | .access = PL0_W, .type = ARM_CP_NOP, | |
4303 | .accessfn = aa64_cacheop_access }, | |
4304 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, | |
4305 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
4306 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4307 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, | |
4308 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | |
4309 | .access = PL0_W, .type = ARM_CP_NOP, | |
4310 | .accessfn = aa64_cacheop_access }, | |
4311 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, | |
4312 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | |
4313 | .access = PL0_W, .type = ARM_CP_NOP, | |
4314 | .accessfn = aa64_cacheop_access }, | |
4315 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, | |
4316 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
4317 | .access = PL1_W, .type = ARM_CP_NOP }, | |
168aa23b PM |
4318 | /* TLBI operations */ |
4319 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 4320 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, |
7a0e58fa | 4321 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4322 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 4323 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4324 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
7a0e58fa | 4325 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4326 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4327 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4328 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
7a0e58fa | 4329 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4330 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 4331 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4332 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
7a0e58fa | 4333 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4334 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4335 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4336 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
7a0e58fa | 4337 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4338 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4339 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4340 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
7a0e58fa | 4341 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4342 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4343 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4344 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, |
7a0e58fa | 4345 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4346 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 4347 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4348 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
7a0e58fa | 4349 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4350 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4351 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4352 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
7a0e58fa | 4353 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4354 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 4355 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4356 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
7a0e58fa | 4357 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4358 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4359 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4360 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
7a0e58fa | 4361 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4362 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4363 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4364 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
7a0e58fa | 4365 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4366 | .writefn = tlbi_aa64_vae1_write }, |
cea66e91 PM |
4367 | { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, |
4368 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
4369 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4370 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
4371 | { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, | |
4372 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
4373 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4374 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
83ddf975 PM |
4375 | { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, |
4376 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
4377 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 4378 | .writefn = tlbi_aa64_alle1is_write }, |
43efaa33 PM |
4379 | { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, |
4380 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, | |
4381 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4382 | .writefn = tlbi_aa64_alle1is_write }, | |
cea66e91 PM |
4383 | { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, |
4384 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
4385 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4386 | .writefn = tlbi_aa64_ipas2e1_write }, | |
4387 | { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, | |
4388 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
4389 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4390 | .writefn = tlbi_aa64_ipas2e1_write }, | |
83ddf975 PM |
4391 | { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, |
4392 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
4393 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 4394 | .writefn = tlbi_aa64_alle1_write }, |
43efaa33 PM |
4395 | { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, |
4396 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, | |
4397 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4398 | .writefn = tlbi_aa64_alle1is_write }, | |
19525524 PM |
4399 | #ifndef CONFIG_USER_ONLY |
4400 | /* 64 bit address translation operations */ | |
4401 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
4402 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, | |
0710b2fa PM |
4403 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4404 | .writefn = ats_write64 }, | |
19525524 PM |
4405 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, |
4406 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, | |
0710b2fa PM |
4407 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4408 | .writefn = ats_write64 }, | |
19525524 PM |
4409 | { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, |
4410 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, | |
0710b2fa PM |
4411 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4412 | .writefn = ats_write64 }, | |
19525524 PM |
4413 | { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, |
4414 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, | |
0710b2fa PM |
4415 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4416 | .writefn = ats_write64 }, | |
2a47df95 | 4417 | { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4418 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, |
0710b2fa PM |
4419 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4420 | .writefn = ats_write64 }, | |
2a47df95 | 4421 | { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4422 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, |
0710b2fa PM |
4423 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4424 | .writefn = ats_write64 }, | |
2a47df95 | 4425 | { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4426 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, |
0710b2fa PM |
4427 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4428 | .writefn = ats_write64 }, | |
2a47df95 | 4429 | { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4430 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, |
0710b2fa PM |
4431 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4432 | .writefn = ats_write64 }, | |
2a47df95 PM |
4433 | /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ |
4434 | { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, | |
4435 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, | |
0710b2fa PM |
4436 | .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4437 | .writefn = ats_write64 }, | |
2a47df95 PM |
4438 | { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, |
4439 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, | |
0710b2fa PM |
4440 | .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4441 | .writefn = ats_write64 }, | |
c96fc9b5 EI |
4442 | { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, |
4443 | .type = ARM_CP_ALIAS, | |
4444 | .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, | |
4445 | .access = PL1_RW, .resetvalue = 0, | |
4446 | .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), | |
4447 | .writefn = par_write }, | |
19525524 | 4448 | #endif |
995939a6 | 4449 | /* TLB invalidate last level of translation table walk */ |
9449fdf6 | 4450 | { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
7a0e58fa | 4451 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, |
9449fdf6 | 4452 | { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
7a0e58fa | 4453 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 4454 | .writefn = tlbimvaa_is_write }, |
9449fdf6 | 4455 | { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
7a0e58fa | 4456 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
9449fdf6 | 4457 | { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
7a0e58fa | 4458 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, |
541ef8c2 SS |
4459 | { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, |
4460 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4461 | .writefn = tlbimva_hyp_write }, | |
4462 | { .name = "TLBIMVALHIS", | |
4463 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
4464 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4465 | .writefn = tlbimva_hyp_is_write }, | |
4466 | { .name = "TLBIIPAS2", | |
4467 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
4468 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4469 | .writefn = tlbiipas2_write }, | |
4470 | { .name = "TLBIIPAS2IS", | |
4471 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
4472 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4473 | .writefn = tlbiipas2_is_write }, | |
4474 | { .name = "TLBIIPAS2L", | |
4475 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
4476 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4477 | .writefn = tlbiipas2_write }, | |
4478 | { .name = "TLBIIPAS2LIS", | |
4479 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
4480 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4481 | .writefn = tlbiipas2_is_write }, | |
9449fdf6 PM |
4482 | /* 32 bit cache operations */ |
4483 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
4484 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4485 | { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, | |
4486 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4487 | { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
4488 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4489 | { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, | |
4490 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4491 | { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, | |
4492 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4493 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | |
4494 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4495 | { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
4496 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4497 | { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
4498 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4499 | { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, | |
4500 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4501 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
4502 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4503 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, | |
4504 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4505 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, | |
4506 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4507 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
4508 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4509 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
4510 | { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, |
4511 | .access = PL1_RW, .resetvalue = 0, | |
4512 | .writefn = dacr_write, .raw_writefn = raw_write, | |
4513 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
4514 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a0618a19 | 4515 | { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4516 | .type = ARM_CP_ALIAS, |
a0618a19 | 4517 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, |
6947f059 EI |
4518 | .access = PL1_RW, |
4519 | .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, | |
a65f1de9 | 4520 | { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4521 | .type = ARM_CP_ALIAS, |
a65f1de9 | 4522 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
4523 | .access = PL1_RW, |
4524 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, | |
f502cfc2 PM |
4525 | /* We rely on the access checks not allowing the guest to write to the |
4526 | * state field when SPSel indicates that it's being used as the stack | |
4527 | * pointer. | |
4528 | */ | |
4529 | { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, | |
4530 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, | |
4531 | .access = PL1_RW, .accessfn = sp_el0_access, | |
7a0e58fa | 4532 | .type = ARM_CP_ALIAS, |
f502cfc2 | 4533 | .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, |
884b4dee GB |
4534 | { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, |
4535 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 4536 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
884b4dee | 4537 | .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, |
f502cfc2 PM |
4538 | { .name = "SPSel", .state = ARM_CP_STATE_AA64, |
4539 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, | |
7a0e58fa | 4540 | .type = ARM_CP_NO_RAW, |
f502cfc2 | 4541 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, |
03fbf20f PM |
4542 | { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, |
4543 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, | |
4544 | .type = ARM_CP_ALIAS, | |
4545 | .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), | |
4546 | .access = PL2_RW, .accessfn = fpexc32_access }, | |
6a43e0b6 PM |
4547 | { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, |
4548 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, | |
4549 | .access = PL2_RW, .resetvalue = 0, | |
4550 | .writefn = dacr_write, .raw_writefn = raw_write, | |
4551 | .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, | |
4552 | { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, | |
4553 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, | |
4554 | .access = PL2_RW, .resetvalue = 0, | |
4555 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, | |
4556 | { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, | |
4557 | .type = ARM_CP_ALIAS, | |
4558 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, | |
4559 | .access = PL2_RW, | |
4560 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, | |
4561 | { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, | |
4562 | .type = ARM_CP_ALIAS, | |
4563 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, | |
4564 | .access = PL2_RW, | |
4565 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, | |
4566 | { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, | |
4567 | .type = ARM_CP_ALIAS, | |
4568 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, | |
4569 | .access = PL2_RW, | |
4570 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, | |
4571 | { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, | |
4572 | .type = ARM_CP_ALIAS, | |
4573 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, | |
4574 | .access = PL2_RW, | |
4575 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, | |
a8d64e73 PM |
4576 | { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, |
4577 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, | |
4578 | .resetvalue = 0, | |
4579 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) }, | |
4580 | { .name = "SDCR", .type = ARM_CP_ALIAS, | |
4581 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1, | |
4582 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, | |
4583 | .writefn = sdcr_write, | |
4584 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, | |
b0d2b7d0 PM |
4585 | REGINFO_SENTINEL |
4586 | }; | |
4587 | ||
d42e3c26 | 4588 | /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ |
4771cd01 | 4589 | static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { |
d79e0c06 | 4590 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, |
d42e3c26 EI |
4591 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, |
4592 | .access = PL2_RW, | |
4593 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | |
ce4afed8 | 4594 | { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH, |
7a0e58fa | 4595 | .type = ARM_CP_NO_RAW, |
f149e3e8 EI |
4596 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
4597 | .access = PL2_RW, | |
ce4afed8 | 4598 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
831a2fca PM |
4599 | { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, |
4600 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, | |
4601 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
68e78e33 PM |
4602 | { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, |
4603 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, | |
4604 | .access = PL2_RW, | |
4605 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
c6f19164 GB |
4606 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
4607 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
4608 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
95f949ac EI |
4609 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
4610 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
4611 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4612 | .resetvalue = 0 }, | |
4613 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
b5ede85b | 4614 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, |
95f949ac | 4615 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
2179ef95 PM |
4616 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
4617 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
4618 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4619 | .resetvalue = 0 }, | |
55b53c71 | 4620 | { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, |
b5ede85b | 4621 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, |
2179ef95 PM |
4622 | .access = PL2_RW, .type = ARM_CP_CONST, |
4623 | .resetvalue = 0 }, | |
37cd6c24 PM |
4624 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
4625 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
4626 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4627 | .resetvalue = 0 }, | |
4628 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
4629 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
4630 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4631 | .resetvalue = 0 }, | |
06ec4c8c EI |
4632 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
4633 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
4634 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
68e9c2fe EI |
4635 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH, |
4636 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
4637 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
4638 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b698e9cf EI |
4639 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
4640 | .cp = 15, .opc1 = 6, .crm = 2, | |
4641 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
4642 | .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | |
4643 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
4644 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
4645 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b9cb5323 EI |
4646 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
4647 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
4648 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
ff05f37b EI |
4649 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
4650 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
4651 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
a57633c0 EI |
4652 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
4653 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
4654 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4655 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
4656 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
4657 | .resetvalue = 0 }, | |
0b6440af EI |
4658 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
4659 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
4660 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
edac4d8a EI |
4661 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
4662 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
4663 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4664 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
4665 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
4666 | .resetvalue = 0 }, | |
b0e66d95 EI |
4667 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
4668 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
4669 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4670 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
4671 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
4672 | .resetvalue = 0 }, | |
4673 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
4674 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
4675 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4676 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
4677 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
4678 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
14cc7b54 SF |
4679 | { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, |
4680 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | |
d6c8cf81 PM |
4681 | .access = PL2_RW, .accessfn = access_tda, |
4682 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
59e05530 EI |
4683 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, |
4684 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
4685 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
4686 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2a5a9abd AF |
4687 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
4688 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
4689 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
cba517c3 PM |
4690 | { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, |
4691 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, | |
4692 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4693 | { .name = "HIFAR", .state = ARM_CP_STATE_AA32, | |
4694 | .type = ARM_CP_CONST, | |
4695 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | |
4696 | .access = PL2_RW, .resetvalue = 0 }, | |
d42e3c26 EI |
4697 | REGINFO_SENTINEL |
4698 | }; | |
4699 | ||
ce4afed8 PM |
4700 | /* Ditto, but for registers which exist in ARMv8 but not v7 */ |
4701 | static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { | |
4702 | { .name = "HCR2", .state = ARM_CP_STATE_AA32, | |
4703 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, | |
4704 | .access = PL2_RW, | |
4705 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4706 | REGINFO_SENTINEL | |
4707 | }; | |
4708 | ||
f149e3e8 EI |
4709 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4710 | { | |
2fc0cc0e | 4711 | ARMCPU *cpu = env_archcpu(env); |
f149e3e8 EI |
4712 | uint64_t valid_mask = HCR_MASK; |
4713 | ||
4714 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
4715 | valid_mask &= ~HCR_HCD; | |
77077a83 JK |
4716 | } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { |
4717 | /* Architecturally HCR.TSC is RES0 if EL3 is not implemented. | |
4718 | * However, if we're using the SMC PSCI conduit then QEMU is | |
4719 | * effectively acting like EL3 firmware and so the guest at | |
4720 | * EL2 should retain the ability to prevent EL1 from being | |
4721 | * able to make SMC calls into the ersatz firmware, so in | |
4722 | * that case HCR.TSC should be read/write. | |
4723 | */ | |
f149e3e8 EI |
4724 | valid_mask &= ~HCR_TSC; |
4725 | } | |
2d7137c1 RH |
4726 | if (cpu_isar_feature(aa64_lor, cpu)) { |
4727 | valid_mask |= HCR_TLOR; | |
4728 | } | |
ef682cdb RH |
4729 | if (cpu_isar_feature(aa64_pauth, cpu)) { |
4730 | valid_mask |= HCR_API | HCR_APK; | |
4731 | } | |
f149e3e8 EI |
4732 | |
4733 | /* Clear RES0 bits. */ | |
4734 | value &= valid_mask; | |
4735 | ||
4736 | /* These bits change the MMU setup: | |
4737 | * HCR_VM enables stage 2 translation | |
4738 | * HCR_PTW forbids certain page-table setups | |
4739 | * HCR_DC Disables stage1 and enables stage2 translation | |
4740 | */ | |
ce4afed8 | 4741 | if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { |
d10eb08f | 4742 | tlb_flush(CPU(cpu)); |
f149e3e8 | 4743 | } |
ce4afed8 | 4744 | env->cp15.hcr_el2 = value; |
89430fc6 PM |
4745 | |
4746 | /* | |
4747 | * Updates to VI and VF require us to update the status of | |
4748 | * virtual interrupts, which are the logical OR of these bits | |
4749 | * and the state of the input lines from the GIC. (This requires | |
4750 | * that we have the iothread lock, which is done by marking the | |
4751 | * reginfo structs as ARM_CP_IO.) | |
4752 | * Note that if a write to HCR pends a VIRQ or VFIQ it is never | |
4753 | * possible for it to be taken immediately, because VIRQ and | |
4754 | * VFIQ are masked unless running at EL0 or EL1, and HCR | |
4755 | * can only be written at EL2. | |
4756 | */ | |
4757 | g_assert(qemu_mutex_iothread_locked()); | |
4758 | arm_cpu_update_virq(cpu); | |
4759 | arm_cpu_update_vfiq(cpu); | |
ce4afed8 PM |
4760 | } |
4761 | ||
4762 | static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, | |
4763 | uint64_t value) | |
4764 | { | |
4765 | /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */ | |
4766 | value = deposit64(env->cp15.hcr_el2, 32, 32, value); | |
4767 | hcr_write(env, NULL, value); | |
4768 | } | |
4769 | ||
4770 | static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, | |
4771 | uint64_t value) | |
4772 | { | |
4773 | /* Handle HCR write, i.e. write to low half of HCR_EL2 */ | |
4774 | value = deposit64(env->cp15.hcr_el2, 0, 32, value); | |
4775 | hcr_write(env, NULL, value); | |
f149e3e8 EI |
4776 | } |
4777 | ||
f7778444 RH |
4778 | /* |
4779 | * Return the effective value of HCR_EL2. | |
4780 | * Bits that are not included here: | |
4781 | * RW (read from SCR_EL3.RW as needed) | |
4782 | */ | |
4783 | uint64_t arm_hcr_el2_eff(CPUARMState *env) | |
4784 | { | |
4785 | uint64_t ret = env->cp15.hcr_el2; | |
4786 | ||
4787 | if (arm_is_secure_below_el3(env)) { | |
4788 | /* | |
4789 | * "This register has no effect if EL2 is not enabled in the | |
4790 | * current Security state". This is ARMv8.4-SecEL2 speak for | |
4791 | * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1). | |
4792 | * | |
4793 | * Prior to that, the language was "In an implementation that | |
4794 | * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves | |
4795 | * as if this field is 0 for all purposes other than a direct | |
4796 | * read or write access of HCR_EL2". With lots of enumeration | |
4797 | * on a per-field basis. In current QEMU, this is condition | |
4798 | * is arm_is_secure_below_el3. | |
4799 | * | |
4800 | * Since the v8.4 language applies to the entire register, and | |
4801 | * appears to be backward compatible, use that. | |
4802 | */ | |
4803 | ret = 0; | |
4804 | } else if (ret & HCR_TGE) { | |
4805 | /* These bits are up-to-date as of ARMv8.4. */ | |
4806 | if (ret & HCR_E2H) { | |
4807 | ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | | |
4808 | HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | | |
4809 | HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | | |
4810 | HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE); | |
4811 | } else { | |
4812 | ret |= HCR_FMO | HCR_IMO | HCR_AMO; | |
4813 | } | |
4814 | ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | | |
4815 | HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | | |
4816 | HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | | |
4817 | HCR_TLOR); | |
4818 | } | |
4819 | ||
4820 | return ret; | |
4821 | } | |
4822 | ||
fc1120a7 PM |
4823 | static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4824 | uint64_t value) | |
4825 | { | |
4826 | /* | |
4827 | * For A-profile AArch32 EL3, if NSACR.CP10 | |
4828 | * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. | |
4829 | */ | |
4830 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
4831 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
4832 | value &= ~(0x3 << 10); | |
4833 | value |= env->cp15.cptr_el[2] & (0x3 << 10); | |
4834 | } | |
4835 | env->cp15.cptr_el[2] = value; | |
4836 | } | |
4837 | ||
4838 | static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
4839 | { | |
4840 | /* | |
4841 | * For A-profile AArch32 EL3, if NSACR.CP10 | |
4842 | * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. | |
4843 | */ | |
4844 | uint64_t value = env->cp15.cptr_el[2]; | |
4845 | ||
4846 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
4847 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
4848 | value |= 0x3 << 10; | |
4849 | } | |
4850 | return value; | |
4851 | } | |
4852 | ||
4771cd01 | 4853 | static const ARMCPRegInfo el2_cp_reginfo[] = { |
f149e3e8 | 4854 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
89430fc6 | 4855 | .type = ARM_CP_IO, |
f149e3e8 EI |
4856 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
4857 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
c624ea0f | 4858 | .writefn = hcr_write }, |
ce4afed8 | 4859 | { .name = "HCR", .state = ARM_CP_STATE_AA32, |
89430fc6 | 4860 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
4861 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
4862 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
c624ea0f | 4863 | .writefn = hcr_writelow }, |
831a2fca PM |
4864 | { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, |
4865 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, | |
4866 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3b685ba7 | 4867 | { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4868 | .type = ARM_CP_ALIAS, |
3b685ba7 EI |
4869 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, |
4870 | .access = PL2_RW, | |
4871 | .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, | |
68e78e33 | 4872 | { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, |
f2c30f42 EI |
4873 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, |
4874 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, | |
cba517c3 | 4875 | { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, |
63b60551 EI |
4876 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, |
4877 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, | |
cba517c3 PM |
4878 | { .name = "HIFAR", .state = ARM_CP_STATE_AA32, |
4879 | .type = ARM_CP_ALIAS, | |
4880 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | |
4881 | .access = PL2_RW, | |
4882 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) }, | |
3b685ba7 | 4883 | { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4884 | .type = ARM_CP_ALIAS, |
3b685ba7 | 4885 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
4886 | .access = PL2_RW, |
4887 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, | |
d79e0c06 | 4888 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, |
d42e3c26 EI |
4889 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, |
4890 | .access = PL2_RW, .writefn = vbar_write, | |
4891 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), | |
4892 | .resetvalue = 0 }, | |
884b4dee GB |
4893 | { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, |
4894 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 4895 | .access = PL3_RW, .type = ARM_CP_ALIAS, |
884b4dee | 4896 | .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, |
c6f19164 GB |
4897 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
4898 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
4899 | .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, | |
fc1120a7 PM |
4900 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]), |
4901 | .readfn = cptr_el2_read, .writefn = cptr_el2_write }, | |
95f949ac EI |
4902 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
4903 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
4904 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), | |
4905 | .resetvalue = 0 }, | |
4906 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
b5ede85b | 4907 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, |
95f949ac EI |
4908 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
4909 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, | |
2179ef95 PM |
4910 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
4911 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
4912 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4913 | .resetvalue = 0 }, | |
4914 | /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ | |
55b53c71 | 4915 | { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, |
b5ede85b | 4916 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, |
2179ef95 PM |
4917 | .access = PL2_RW, .type = ARM_CP_CONST, |
4918 | .resetvalue = 0 }, | |
37cd6c24 PM |
4919 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
4920 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
4921 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4922 | .resetvalue = 0 }, | |
4923 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
4924 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
4925 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4926 | .resetvalue = 0 }, | |
06ec4c8c EI |
4927 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
4928 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
6459b94c PM |
4929 | .access = PL2_RW, |
4930 | /* no .writefn needed as this can't cause an ASID change; | |
4931 | * no .raw_writefn or .resetfn needed as we never use mask/base_mask | |
4932 | */ | |
06ec4c8c | 4933 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, |
68e9c2fe EI |
4934 | { .name = "VTCR", .state = ARM_CP_STATE_AA32, |
4935 | .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 | 4936 | .type = ARM_CP_ALIAS, |
68e9c2fe EI |
4937 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
4938 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, | |
4939 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, | |
4940 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 PM |
4941 | .access = PL2_RW, |
4942 | /* no .writefn needed as this can't cause an ASID change; | |
4943 | * no .raw_writefn or .resetfn needed as we never use mask/base_mask | |
4944 | */ | |
68e9c2fe | 4945 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, |
b698e9cf EI |
4946 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
4947 | .cp = 15, .opc1 = 6, .crm = 2, | |
4948 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
4949 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
4950 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), | |
4951 | .writefn = vttbr_write }, | |
4952 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
4953 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
4954 | .access = PL2_RW, .writefn = vttbr_write, | |
4955 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, | |
b9cb5323 EI |
4956 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
4957 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
4958 | .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, | |
4959 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, | |
ff05f37b EI |
4960 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
4961 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
4962 | .access = PL2_RW, .resetvalue = 0, | |
4963 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, | |
a57633c0 EI |
4964 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
4965 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
4966 | .access = PL2_RW, .resetvalue = 0, | |
4967 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, | |
4968 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
4969 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
a57633c0 | 4970 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
541ef8c2 SS |
4971 | { .name = "TLBIALLNSNH", |
4972 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
4973 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4974 | .writefn = tlbiall_nsnh_write }, | |
4975 | { .name = "TLBIALLNSNHIS", | |
4976 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
4977 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4978 | .writefn = tlbiall_nsnh_is_write }, | |
4979 | { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
4980 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4981 | .writefn = tlbiall_hyp_write }, | |
4982 | { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
4983 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4984 | .writefn = tlbiall_hyp_is_write }, | |
4985 | { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
4986 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4987 | .writefn = tlbimva_hyp_write }, | |
4988 | { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
4989 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4990 | .writefn = tlbimva_hyp_is_write }, | |
51da9014 EI |
4991 | { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, |
4992 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
4993 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 4994 | .writefn = tlbi_aa64_alle2_write }, |
8742d49d EI |
4995 | { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, |
4996 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
4997 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 4998 | .writefn = tlbi_aa64_vae2_write }, |
2bfb9d75 PM |
4999 | { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, |
5000 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, | |
5001 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
5002 | .writefn = tlbi_aa64_vae2_write }, | |
5003 | { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, | |
5004 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
5005 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
5006 | .writefn = tlbi_aa64_alle2is_write }, | |
8742d49d EI |
5007 | { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, |
5008 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
5009 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 5010 | .writefn = tlbi_aa64_vae2is_write }, |
2bfb9d75 PM |
5011 | { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, |
5012 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
5013 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
5014 | .writefn = tlbi_aa64_vae2is_write }, | |
edac4d8a | 5015 | #ifndef CONFIG_USER_ONLY |
2a47df95 PM |
5016 | /* Unlike the other EL2-related AT operations, these must |
5017 | * UNDEF from EL3 if EL2 is not implemented, which is why we | |
5018 | * define them here rather than with the rest of the AT ops. | |
5019 | */ | |
5020 | { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, | |
5021 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
5022 | .access = PL2_W, .accessfn = at_s1e2_access, | |
0710b2fa | 5023 | .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, |
2a47df95 PM |
5024 | { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, |
5025 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | |
5026 | .access = PL2_W, .accessfn = at_s1e2_access, | |
0710b2fa | 5027 | .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, |
14db7fe0 PM |
5028 | /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE |
5029 | * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 | |
5030 | * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose | |
5031 | * to behave as if SCR.NS was 1. | |
5032 | */ | |
5033 | { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
5034 | .access = PL2_W, | |
0710b2fa | 5035 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
14db7fe0 PM |
5036 | { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, |
5037 | .access = PL2_W, | |
0710b2fa | 5038 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
0b6440af EI |
5039 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
5040 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
5041 | /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the | |
5042 | * reset values as IMPDEF. We choose to reset to 3 to comply with | |
5043 | * both ARMv7 and ARMv8. | |
5044 | */ | |
5045 | .access = PL2_RW, .resetvalue = 3, | |
5046 | .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, | |
edac4d8a EI |
5047 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
5048 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
5049 | .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, | |
5050 | .writefn = gt_cntvoff_write, | |
5051 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
5052 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
5053 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, | |
5054 | .writefn = gt_cntvoff_write, | |
5055 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
b0e66d95 EI |
5056 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
5057 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
5058 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
5059 | .type = ARM_CP_IO, .access = PL2_RW, | |
5060 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
5061 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
5062 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
5063 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO, | |
5064 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
5065 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
5066 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
d44ec156 | 5067 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, |
b0e66d95 EI |
5068 | .resetfn = gt_hyp_timer_reset, |
5069 | .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, | |
5070 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
5071 | .type = ARM_CP_IO, | |
5072 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
5073 | .access = PL2_RW, | |
5074 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), | |
5075 | .resetvalue = 0, | |
5076 | .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, | |
edac4d8a | 5077 | #endif |
14cc7b54 SF |
5078 | /* The only field of MDCR_EL2 that has a defined architectural reset value |
5079 | * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we | |
5ecdd3e4 | 5080 | * don't implement any PMU event counters, so using zero as a reset |
14cc7b54 SF |
5081 | * value for MDCR_EL2 is okay |
5082 | */ | |
5083 | { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, | |
5084 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | |
5085 | .access = PL2_RW, .resetvalue = 0, | |
5086 | .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), }, | |
59e05530 EI |
5087 | { .name = "HPFAR", .state = ARM_CP_STATE_AA32, |
5088 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
5089 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
5090 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
5091 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, | |
5092 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
5093 | .access = PL2_RW, | |
5094 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
2a5a9abd AF |
5095 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
5096 | .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
5097 | .access = PL2_RW, | |
5098 | .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, | |
3b685ba7 EI |
5099 | REGINFO_SENTINEL |
5100 | }; | |
5101 | ||
ce4afed8 PM |
5102 | static const ARMCPRegInfo el2_v8_cp_reginfo[] = { |
5103 | { .name = "HCR2", .state = ARM_CP_STATE_AA32, | |
89430fc6 | 5104 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
5105 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, |
5106 | .access = PL2_RW, | |
5107 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2), | |
5108 | .writefn = hcr_writehigh }, | |
5109 | REGINFO_SENTINEL | |
5110 | }; | |
5111 | ||
2f027fc5 PM |
5112 | static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5113 | bool isread) | |
5114 | { | |
5115 | /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. | |
5116 | * At Secure EL1 it traps to EL3. | |
5117 | */ | |
5118 | if (arm_current_el(env) == 3) { | |
5119 | return CP_ACCESS_OK; | |
5120 | } | |
5121 | if (arm_is_secure_below_el3(env)) { | |
5122 | return CP_ACCESS_TRAP_EL3; | |
5123 | } | |
5124 | /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ | |
5125 | if (isread) { | |
5126 | return CP_ACCESS_OK; | |
5127 | } | |
5128 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
5129 | } | |
5130 | ||
60fb1a87 GB |
5131 | static const ARMCPRegInfo el3_cp_reginfo[] = { |
5132 | { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, | |
5133 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, | |
5134 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), | |
5135 | .resetvalue = 0, .writefn = scr_write }, | |
7a0e58fa | 5136 | { .name = "SCR", .type = ARM_CP_ALIAS, |
60fb1a87 | 5137 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, |
efe4a274 PM |
5138 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
5139 | .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), | |
b061a82b | 5140 | .writefn = scr_write }, |
60fb1a87 GB |
5141 | { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, |
5142 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, | |
5143 | .access = PL3_RW, .resetvalue = 0, | |
5144 | .fieldoffset = offsetof(CPUARMState, cp15.sder) }, | |
5145 | { .name = "SDER", | |
5146 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, | |
5147 | .access = PL3_RW, .resetvalue = 0, | |
5148 | .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, | |
60fb1a87 | 5149 | { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, |
efe4a274 PM |
5150 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
5151 | .writefn = vbar_write, .resetvalue = 0, | |
60fb1a87 | 5152 | .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, |
7dd8c9af FA |
5153 | { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, |
5154 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, | |
f478847f | 5155 | .access = PL3_RW, .resetvalue = 0, |
7dd8c9af | 5156 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, |
11f136ee FA |
5157 | { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, |
5158 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, | |
6459b94c PM |
5159 | .access = PL3_RW, |
5160 | /* no .writefn needed as this can't cause an ASID change; | |
811595a2 PM |
5161 | * we must provide a .raw_writefn and .resetfn because we handle |
5162 | * reset and migration for the AArch32 TTBCR(S), which might be | |
5163 | * using mask and base_mask. | |
6459b94c | 5164 | */ |
811595a2 | 5165 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, |
11f136ee | 5166 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, |
81547d66 | 5167 | { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5168 | .type = ARM_CP_ALIAS, |
81547d66 EI |
5169 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, |
5170 | .access = PL3_RW, | |
5171 | .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, | |
f2c30f42 | 5172 | { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, |
f2c30f42 EI |
5173 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, |
5174 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, | |
63b60551 EI |
5175 | { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, |
5176 | .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, | |
5177 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, | |
81547d66 | 5178 | { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5179 | .type = ARM_CP_ALIAS, |
81547d66 | 5180 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
5181 | .access = PL3_RW, |
5182 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) }, | |
a1ba125c EI |
5183 | { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, |
5184 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, | |
5185 | .access = PL3_RW, .writefn = vbar_write, | |
5186 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), | |
5187 | .resetvalue = 0 }, | |
c6f19164 GB |
5188 | { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, |
5189 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, | |
5190 | .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, | |
5191 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, | |
4cfb8ad8 PM |
5192 | { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, |
5193 | .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, | |
5194 | .access = PL3_RW, .resetvalue = 0, | |
5195 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, | |
2179ef95 PM |
5196 | { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64, |
5197 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, | |
5198 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5199 | .resetvalue = 0 }, | |
37cd6c24 PM |
5200 | { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, |
5201 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, | |
5202 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5203 | .resetvalue = 0 }, | |
5204 | { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, | |
5205 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, | |
5206 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5207 | .resetvalue = 0 }, | |
43efaa33 PM |
5208 | { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, |
5209 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, | |
5210 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5211 | .writefn = tlbi_aa64_alle3is_write }, | |
5212 | { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, | |
5213 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, | |
5214 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5215 | .writefn = tlbi_aa64_vae3is_write }, | |
5216 | { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, | |
5217 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, | |
5218 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5219 | .writefn = tlbi_aa64_vae3is_write }, | |
5220 | { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, | |
5221 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, | |
5222 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5223 | .writefn = tlbi_aa64_alle3_write }, | |
5224 | { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, | |
5225 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, | |
5226 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5227 | .writefn = tlbi_aa64_vae3_write }, | |
5228 | { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, | |
5229 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, | |
5230 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5231 | .writefn = tlbi_aa64_vae3_write }, | |
0f1a3b24 FA |
5232 | REGINFO_SENTINEL |
5233 | }; | |
5234 | ||
3f208fd7 PM |
5235 | static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5236 | bool isread) | |
7da845b0 PM |
5237 | { |
5238 | /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, | |
5239 | * but the AArch32 CTR has its own reginfo struct) | |
5240 | */ | |
137feaa9 | 5241 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) { |
7da845b0 PM |
5242 | return CP_ACCESS_TRAP; |
5243 | } | |
630fcd4d MZ |
5244 | |
5245 | if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) { | |
5246 | return CP_ACCESS_TRAP_EL2; | |
5247 | } | |
5248 | ||
7da845b0 PM |
5249 | return CP_ACCESS_OK; |
5250 | } | |
5251 | ||
1424ca8d DM |
5252 | static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5253 | uint64_t value) | |
5254 | { | |
5255 | /* Writes to OSLAR_EL1 may update the OS lock status, which can be | |
5256 | * read via a bit in OSLSR_EL1. | |
5257 | */ | |
5258 | int oslock; | |
5259 | ||
5260 | if (ri->state == ARM_CP_STATE_AA32) { | |
5261 | oslock = (value == 0xC5ACCE55); | |
5262 | } else { | |
5263 | oslock = value & 1; | |
5264 | } | |
5265 | ||
5266 | env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); | |
5267 | } | |
5268 | ||
50300698 | 5269 | static const ARMCPRegInfo debug_cp_reginfo[] = { |
50300698 | 5270 | /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped |
10aae104 PM |
5271 | * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; |
5272 | * unlike DBGDRAR it is never accessible from EL0. | |
5273 | * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 | |
5274 | * accessor. | |
50300698 PM |
5275 | */ |
5276 | { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
91b0a238 PM |
5277 | .access = PL0_R, .accessfn = access_tdra, |
5278 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
10aae104 PM |
5279 | { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, |
5280 | .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, | |
91b0a238 PM |
5281 | .access = PL1_R, .accessfn = access_tdra, |
5282 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
50300698 | 5283 | { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
91b0a238 PM |
5284 | .access = PL0_R, .accessfn = access_tdra, |
5285 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
17a9eb53 | 5286 | /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ |
10aae104 PM |
5287 | { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, |
5288 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
d6c8cf81 | 5289 | .access = PL1_RW, .accessfn = access_tda, |
0e5e8935 PM |
5290 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), |
5291 | .resetvalue = 0 }, | |
5e8b12ff PM |
5292 | /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. |
5293 | * We don't implement the configurable EL0 access. | |
5294 | */ | |
5295 | { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH, | |
5296 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
7a0e58fa | 5297 | .type = ARM_CP_ALIAS, |
d6c8cf81 | 5298 | .access = PL1_R, .accessfn = access_tda, |
b061a82b | 5299 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, |
10aae104 PM |
5300 | { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, |
5301 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, | |
1424ca8d | 5302 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
187f678d | 5303 | .accessfn = access_tdosa, |
1424ca8d DM |
5304 | .writefn = oslar_write }, |
5305 | { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, | |
5306 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, | |
5307 | .access = PL1_R, .resetvalue = 10, | |
187f678d | 5308 | .accessfn = access_tdosa, |
1424ca8d | 5309 | .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, |
5e8b12ff PM |
5310 | /* Dummy OSDLR_EL1: 32-bit Linux will read this */ |
5311 | { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, | |
5312 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, | |
187f678d PM |
5313 | .access = PL1_RW, .accessfn = access_tdosa, |
5314 | .type = ARM_CP_NOP }, | |
5e8b12ff PM |
5315 | /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't |
5316 | * implement vector catch debug events yet. | |
5317 | */ | |
5318 | { .name = "DBGVCR", | |
5319 | .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
d6c8cf81 PM |
5320 | .access = PL1_RW, .accessfn = access_tda, |
5321 | .type = ARM_CP_NOP }, | |
4d2ec4da PM |
5322 | /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor |
5323 | * to save and restore a 32-bit guest's DBGVCR) | |
5324 | */ | |
5325 | { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, | |
5326 | .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, | |
5327 | .access = PL2_RW, .accessfn = access_tda, | |
5328 | .type = ARM_CP_NOP }, | |
5dbdc434 PM |
5329 | /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications |
5330 | * Channel but Linux may try to access this register. The 32-bit | |
5331 | * alias is DBGDCCINT. | |
5332 | */ | |
5333 | { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, | |
5334 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
5335 | .access = PL1_RW, .accessfn = access_tda, | |
5336 | .type = ARM_CP_NOP }, | |
50300698 PM |
5337 | REGINFO_SENTINEL |
5338 | }; | |
5339 | ||
5340 | static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | |
5341 | /* 64 bit access versions of the (dummy) debug registers */ | |
5342 | { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, | |
5343 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
5344 | { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | |
5345 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
5346 | REGINFO_SENTINEL | |
5347 | }; | |
5348 | ||
60eed086 RH |
5349 | /* Return the exception level to which exceptions should be taken |
5350 | * via SVEAccessTrap. If an exception should be routed through | |
5351 | * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should | |
5352 | * take care of raising that exception. | |
5353 | * C.f. the ARM pseudocode function CheckSVEEnabled. | |
5be5e8ed | 5354 | */ |
ced31551 | 5355 | int sve_exception_el(CPUARMState *env, int el) |
5be5e8ed RH |
5356 | { |
5357 | #ifndef CONFIG_USER_ONLY | |
2de7ace2 | 5358 | if (el <= 1) { |
60eed086 RH |
5359 | bool disabled = false; |
5360 | ||
5361 | /* The CPACR.ZEN controls traps to EL1: | |
5362 | * 0, 2 : trap EL0 and EL1 accesses | |
5363 | * 1 : trap only EL0 accesses | |
5364 | * 3 : trap no accesses | |
5365 | */ | |
5366 | if (!extract32(env->cp15.cpacr_el1, 16, 1)) { | |
5367 | disabled = true; | |
5368 | } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) { | |
2de7ace2 | 5369 | disabled = el == 0; |
5be5e8ed | 5370 | } |
60eed086 RH |
5371 | if (disabled) { |
5372 | /* route_to_el2 */ | |
5373 | return (arm_feature(env, ARM_FEATURE_EL2) | |
7c208e0f | 5374 | && (arm_hcr_el2_eff(env) & HCR_TGE) ? 2 : 1); |
5be5e8ed | 5375 | } |
5be5e8ed | 5376 | |
60eed086 RH |
5377 | /* Check CPACR.FPEN. */ |
5378 | if (!extract32(env->cp15.cpacr_el1, 20, 1)) { | |
5379 | disabled = true; | |
5380 | } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) { | |
2de7ace2 | 5381 | disabled = el == 0; |
5be5e8ed | 5382 | } |
60eed086 RH |
5383 | if (disabled) { |
5384 | return 0; | |
5be5e8ed | 5385 | } |
5be5e8ed RH |
5386 | } |
5387 | ||
60eed086 RH |
5388 | /* CPTR_EL2. Since TZ and TFP are positive, |
5389 | * they will be zero when EL2 is not present. | |
5390 | */ | |
2de7ace2 | 5391 | if (el <= 2 && !arm_is_secure_below_el3(env)) { |
60eed086 RH |
5392 | if (env->cp15.cptr_el[2] & CPTR_TZ) { |
5393 | return 2; | |
5394 | } | |
5395 | if (env->cp15.cptr_el[2] & CPTR_TFP) { | |
5396 | return 0; | |
5397 | } | |
5be5e8ed RH |
5398 | } |
5399 | ||
60eed086 RH |
5400 | /* CPTR_EL3. Since EZ is negative we must check for EL3. */ |
5401 | if (arm_feature(env, ARM_FEATURE_EL3) | |
5402 | && !(env->cp15.cptr_el[3] & CPTR_EZ)) { | |
5be5e8ed RH |
5403 | return 3; |
5404 | } | |
5405 | #endif | |
5406 | return 0; | |
5407 | } | |
5408 | ||
0df9142d AJ |
5409 | static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) |
5410 | { | |
6e553f2a | 5411 | uint32_t end_len; |
0df9142d | 5412 | |
6e553f2a RH |
5413 | end_len = start_len &= 0xf; |
5414 | if (!test_bit(start_len, cpu->sve_vq_map)) { | |
5415 | end_len = find_last_bit(cpu->sve_vq_map, start_len); | |
5416 | assert(end_len < start_len); | |
5417 | } | |
5418 | return end_len; | |
0df9142d AJ |
5419 | } |
5420 | ||
0ab5953b RH |
5421 | /* |
5422 | * Given that SVE is enabled, return the vector length for EL. | |
5423 | */ | |
ced31551 | 5424 | uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) |
0ab5953b | 5425 | { |
2fc0cc0e | 5426 | ARMCPU *cpu = env_archcpu(env); |
0ab5953b RH |
5427 | uint32_t zcr_len = cpu->sve_max_vq - 1; |
5428 | ||
5429 | if (el <= 1) { | |
5430 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); | |
5431 | } | |
6a02a732 | 5432 | if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) { |
0ab5953b RH |
5433 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); |
5434 | } | |
6a02a732 | 5435 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0ab5953b RH |
5436 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); |
5437 | } | |
0df9142d AJ |
5438 | |
5439 | return sve_zcr_get_valid_len(cpu, zcr_len); | |
0ab5953b RH |
5440 | } |
5441 | ||
5be5e8ed RH |
5442 | static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5443 | uint64_t value) | |
5444 | { | |
0ab5953b RH |
5445 | int cur_el = arm_current_el(env); |
5446 | int old_len = sve_zcr_len_for_el(env, cur_el); | |
5447 | int new_len; | |
5448 | ||
5be5e8ed | 5449 | /* Bits other than [3:0] are RAZ/WI. */ |
7b351d98 | 5450 | QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16); |
5be5e8ed | 5451 | raw_write(env, ri, value & 0xf); |
0ab5953b RH |
5452 | |
5453 | /* | |
5454 | * Because we arrived here, we know both FP and SVE are enabled; | |
5455 | * otherwise we would have trapped access to the ZCR_ELn register. | |
5456 | */ | |
5457 | new_len = sve_zcr_len_for_el(env, cur_el); | |
5458 | if (new_len < old_len) { | |
5459 | aarch64_sve_narrow_vq(env, new_len + 1); | |
5460 | } | |
5be5e8ed RH |
5461 | } |
5462 | ||
5463 | static const ARMCPRegInfo zcr_el1_reginfo = { | |
5464 | .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | |
5465 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 5466 | .access = PL1_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
5467 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), |
5468 | .writefn = zcr_write, .raw_writefn = raw_write | |
5469 | }; | |
5470 | ||
5471 | static const ARMCPRegInfo zcr_el2_reginfo = { | |
5472 | .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | |
5473 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 5474 | .access = PL2_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
5475 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), |
5476 | .writefn = zcr_write, .raw_writefn = raw_write | |
5477 | }; | |
5478 | ||
5479 | static const ARMCPRegInfo zcr_no_el2_reginfo = { | |
5480 | .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | |
5481 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 5482 | .access = PL2_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
5483 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore |
5484 | }; | |
5485 | ||
5486 | static const ARMCPRegInfo zcr_el3_reginfo = { | |
5487 | .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | |
5488 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 5489 | .access = PL3_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
5490 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), |
5491 | .writefn = zcr_write, .raw_writefn = raw_write | |
5492 | }; | |
5493 | ||
9ee98ce8 PM |
5494 | void hw_watchpoint_update(ARMCPU *cpu, int n) |
5495 | { | |
5496 | CPUARMState *env = &cpu->env; | |
5497 | vaddr len = 0; | |
5498 | vaddr wvr = env->cp15.dbgwvr[n]; | |
5499 | uint64_t wcr = env->cp15.dbgwcr[n]; | |
5500 | int mask; | |
5501 | int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; | |
5502 | ||
5503 | if (env->cpu_watchpoint[n]) { | |
5504 | cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); | |
5505 | env->cpu_watchpoint[n] = NULL; | |
5506 | } | |
5507 | ||
5508 | if (!extract64(wcr, 0, 1)) { | |
5509 | /* E bit clear : watchpoint disabled */ | |
5510 | return; | |
5511 | } | |
5512 | ||
5513 | switch (extract64(wcr, 3, 2)) { | |
5514 | case 0: | |
5515 | /* LSC 00 is reserved and must behave as if the wp is disabled */ | |
5516 | return; | |
5517 | case 1: | |
5518 | flags |= BP_MEM_READ; | |
5519 | break; | |
5520 | case 2: | |
5521 | flags |= BP_MEM_WRITE; | |
5522 | break; | |
5523 | case 3: | |
5524 | flags |= BP_MEM_ACCESS; | |
5525 | break; | |
5526 | } | |
5527 | ||
5528 | /* Attempts to use both MASK and BAS fields simultaneously are | |
5529 | * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, | |
5530 | * thus generating a watchpoint for every byte in the masked region. | |
5531 | */ | |
5532 | mask = extract64(wcr, 24, 4); | |
5533 | if (mask == 1 || mask == 2) { | |
5534 | /* Reserved values of MASK; we must act as if the mask value was | |
5535 | * some non-reserved value, or as if the watchpoint were disabled. | |
5536 | * We choose the latter. | |
5537 | */ | |
5538 | return; | |
5539 | } else if (mask) { | |
5540 | /* Watchpoint covers an aligned area up to 2GB in size */ | |
5541 | len = 1ULL << mask; | |
5542 | /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE | |
5543 | * whether the watchpoint fires when the unmasked bits match; we opt | |
5544 | * to generate the exceptions. | |
5545 | */ | |
5546 | wvr &= ~(len - 1); | |
5547 | } else { | |
5548 | /* Watchpoint covers bytes defined by the byte address select bits */ | |
5549 | int bas = extract64(wcr, 5, 8); | |
5550 | int basstart; | |
5551 | ||
5552 | if (bas == 0) { | |
5553 | /* This must act as if the watchpoint is disabled */ | |
5554 | return; | |
5555 | } | |
5556 | ||
5557 | if (extract64(wvr, 2, 1)) { | |
5558 | /* Deprecated case of an only 4-aligned address. BAS[7:4] are | |
5559 | * ignored, and BAS[3:0] define which bytes to watch. | |
5560 | */ | |
5561 | bas &= 0xf; | |
5562 | } | |
5563 | /* The BAS bits are supposed to be programmed to indicate a contiguous | |
5564 | * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether | |
5565 | * we fire for each byte in the word/doubleword addressed by the WVR. | |
5566 | * We choose to ignore any non-zero bits after the first range of 1s. | |
5567 | */ | |
5568 | basstart = ctz32(bas); | |
5569 | len = cto32(bas >> basstart); | |
5570 | wvr += basstart; | |
5571 | } | |
5572 | ||
5573 | cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, | |
5574 | &env->cpu_watchpoint[n]); | |
5575 | } | |
5576 | ||
5577 | void hw_watchpoint_update_all(ARMCPU *cpu) | |
5578 | { | |
5579 | int i; | |
5580 | CPUARMState *env = &cpu->env; | |
5581 | ||
5582 | /* Completely clear out existing QEMU watchpoints and our array, to | |
5583 | * avoid possible stale entries following migration load. | |
5584 | */ | |
5585 | cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); | |
5586 | memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); | |
5587 | ||
5588 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { | |
5589 | hw_watchpoint_update(cpu, i); | |
5590 | } | |
5591 | } | |
5592 | ||
5593 | static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5594 | uint64_t value) | |
5595 | { | |
2fc0cc0e | 5596 | ARMCPU *cpu = env_archcpu(env); |
9ee98ce8 PM |
5597 | int i = ri->crm; |
5598 | ||
5599 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, the | |
5600 | * register reads and behaves as if values written are sign extended. | |
5601 | * Bits [1:0] are RES0. | |
5602 | */ | |
5603 | value = sextract64(value, 0, 49) & ~3ULL; | |
5604 | ||
5605 | raw_write(env, ri, value); | |
5606 | hw_watchpoint_update(cpu, i); | |
5607 | } | |
5608 | ||
5609 | static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5610 | uint64_t value) | |
5611 | { | |
2fc0cc0e | 5612 | ARMCPU *cpu = env_archcpu(env); |
9ee98ce8 PM |
5613 | int i = ri->crm; |
5614 | ||
5615 | raw_write(env, ri, value); | |
5616 | hw_watchpoint_update(cpu, i); | |
5617 | } | |
5618 | ||
46747d15 PM |
5619 | void hw_breakpoint_update(ARMCPU *cpu, int n) |
5620 | { | |
5621 | CPUARMState *env = &cpu->env; | |
5622 | uint64_t bvr = env->cp15.dbgbvr[n]; | |
5623 | uint64_t bcr = env->cp15.dbgbcr[n]; | |
5624 | vaddr addr; | |
5625 | int bt; | |
5626 | int flags = BP_CPU; | |
5627 | ||
5628 | if (env->cpu_breakpoint[n]) { | |
5629 | cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); | |
5630 | env->cpu_breakpoint[n] = NULL; | |
5631 | } | |
5632 | ||
5633 | if (!extract64(bcr, 0, 1)) { | |
5634 | /* E bit clear : watchpoint disabled */ | |
5635 | return; | |
5636 | } | |
5637 | ||
5638 | bt = extract64(bcr, 20, 4); | |
5639 | ||
5640 | switch (bt) { | |
5641 | case 4: /* unlinked address mismatch (reserved if AArch64) */ | |
5642 | case 5: /* linked address mismatch (reserved if AArch64) */ | |
5643 | qemu_log_mask(LOG_UNIMP, | |
0221c8fd | 5644 | "arm: address mismatch breakpoint types not implemented\n"); |
46747d15 PM |
5645 | return; |
5646 | case 0: /* unlinked address match */ | |
5647 | case 1: /* linked address match */ | |
5648 | { | |
5649 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, | |
5650 | * we behave as if the register was sign extended. Bits [1:0] are | |
5651 | * RES0. The BAS field is used to allow setting breakpoints on 16 | |
5652 | * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether | |
5653 | * a bp will fire if the addresses covered by the bp and the addresses | |
5654 | * covered by the insn overlap but the insn doesn't start at the | |
5655 | * start of the bp address range. We choose to require the insn and | |
5656 | * the bp to have the same address. The constraints on writing to | |
5657 | * BAS enforced in dbgbcr_write mean we have only four cases: | |
5658 | * 0b0000 => no breakpoint | |
5659 | * 0b0011 => breakpoint on addr | |
5660 | * 0b1100 => breakpoint on addr + 2 | |
5661 | * 0b1111 => breakpoint on addr | |
5662 | * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). | |
5663 | */ | |
5664 | int bas = extract64(bcr, 5, 4); | |
5665 | addr = sextract64(bvr, 0, 49) & ~3ULL; | |
5666 | if (bas == 0) { | |
5667 | return; | |
5668 | } | |
5669 | if (bas == 0xc) { | |
5670 | addr += 2; | |
5671 | } | |
5672 | break; | |
5673 | } | |
5674 | case 2: /* unlinked context ID match */ | |
5675 | case 8: /* unlinked VMID match (reserved if no EL2) */ | |
5676 | case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ | |
5677 | qemu_log_mask(LOG_UNIMP, | |
0221c8fd | 5678 | "arm: unlinked context breakpoint types not implemented\n"); |
46747d15 PM |
5679 | return; |
5680 | case 9: /* linked VMID match (reserved if no EL2) */ | |
5681 | case 11: /* linked context ID and VMID match (reserved if no EL2) */ | |
5682 | case 3: /* linked context ID match */ | |
5683 | default: | |
5684 | /* We must generate no events for Linked context matches (unless | |
5685 | * they are linked to by some other bp/wp, which is handled in | |
5686 | * updates for the linking bp/wp). We choose to also generate no events | |
5687 | * for reserved values. | |
5688 | */ | |
5689 | return; | |
5690 | } | |
5691 | ||
5692 | cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); | |
5693 | } | |
5694 | ||
5695 | void hw_breakpoint_update_all(ARMCPU *cpu) | |
5696 | { | |
5697 | int i; | |
5698 | CPUARMState *env = &cpu->env; | |
5699 | ||
5700 | /* Completely clear out existing QEMU breakpoints and our array, to | |
5701 | * avoid possible stale entries following migration load. | |
5702 | */ | |
5703 | cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); | |
5704 | memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); | |
5705 | ||
5706 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { | |
5707 | hw_breakpoint_update(cpu, i); | |
5708 | } | |
5709 | } | |
5710 | ||
5711 | static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5712 | uint64_t value) | |
5713 | { | |
2fc0cc0e | 5714 | ARMCPU *cpu = env_archcpu(env); |
46747d15 PM |
5715 | int i = ri->crm; |
5716 | ||
5717 | raw_write(env, ri, value); | |
5718 | hw_breakpoint_update(cpu, i); | |
5719 | } | |
5720 | ||
5721 | static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5722 | uint64_t value) | |
5723 | { | |
2fc0cc0e | 5724 | ARMCPU *cpu = env_archcpu(env); |
46747d15 PM |
5725 | int i = ri->crm; |
5726 | ||
5727 | /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only | |
5728 | * copy of BAS[0]. | |
5729 | */ | |
5730 | value = deposit64(value, 6, 1, extract64(value, 5, 1)); | |
5731 | value = deposit64(value, 8, 1, extract64(value, 7, 1)); | |
5732 | ||
5733 | raw_write(env, ri, value); | |
5734 | hw_breakpoint_update(cpu, i); | |
5735 | } | |
5736 | ||
50300698 | 5737 | static void define_debug_regs(ARMCPU *cpu) |
0b45451e | 5738 | { |
50300698 PM |
5739 | /* Define v7 and v8 architectural debug registers. |
5740 | * These are just dummy implementations for now. | |
0b45451e PM |
5741 | */ |
5742 | int i; | |
3ff6fc91 | 5743 | int wrps, brps, ctx_cmps; |
48eb3ae6 PM |
5744 | ARMCPRegInfo dbgdidr = { |
5745 | .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
d6c8cf81 PM |
5746 | .access = PL0_R, .accessfn = access_tda, |
5747 | .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr, | |
48eb3ae6 PM |
5748 | }; |
5749 | ||
3ff6fc91 | 5750 | /* Note that all these register fields hold "number of Xs minus 1". */ |
48eb3ae6 PM |
5751 | brps = extract32(cpu->dbgdidr, 24, 4); |
5752 | wrps = extract32(cpu->dbgdidr, 28, 4); | |
3ff6fc91 PM |
5753 | ctx_cmps = extract32(cpu->dbgdidr, 20, 4); |
5754 | ||
5755 | assert(ctx_cmps <= brps); | |
48eb3ae6 PM |
5756 | |
5757 | /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties | |
5758 | * of the debug registers such as number of breakpoints; | |
5759 | * check that if they both exist then they agree. | |
5760 | */ | |
5761 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
5762 | assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps); | |
5763 | assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps); | |
3ff6fc91 | 5764 | assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps); |
48eb3ae6 | 5765 | } |
0b45451e | 5766 | |
48eb3ae6 | 5767 | define_one_arm_cp_reg(cpu, &dbgdidr); |
50300698 PM |
5768 | define_arm_cp_regs(cpu, debug_cp_reginfo); |
5769 | ||
5770 | if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { | |
5771 | define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); | |
5772 | } | |
5773 | ||
48eb3ae6 | 5774 | for (i = 0; i < brps + 1; i++) { |
0b45451e | 5775 | ARMCPRegInfo dbgregs[] = { |
10aae104 PM |
5776 | { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH, |
5777 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, | |
d6c8cf81 | 5778 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
5779 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), |
5780 | .writefn = dbgbvr_write, .raw_writefn = raw_write | |
5781 | }, | |
10aae104 PM |
5782 | { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH, |
5783 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, | |
d6c8cf81 | 5784 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
5785 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), |
5786 | .writefn = dbgbcr_write, .raw_writefn = raw_write | |
5787 | }, | |
48eb3ae6 PM |
5788 | REGINFO_SENTINEL |
5789 | }; | |
5790 | define_arm_cp_regs(cpu, dbgregs); | |
5791 | } | |
5792 | ||
5793 | for (i = 0; i < wrps + 1; i++) { | |
5794 | ARMCPRegInfo dbgregs[] = { | |
10aae104 PM |
5795 | { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH, |
5796 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, | |
d6c8cf81 | 5797 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
5798 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), |
5799 | .writefn = dbgwvr_write, .raw_writefn = raw_write | |
5800 | }, | |
10aae104 PM |
5801 | { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH, |
5802 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, | |
d6c8cf81 | 5803 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
5804 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), |
5805 | .writefn = dbgwcr_write, .raw_writefn = raw_write | |
5806 | }, | |
5807 | REGINFO_SENTINEL | |
0b45451e PM |
5808 | }; |
5809 | define_arm_cp_regs(cpu, dbgregs); | |
5810 | } | |
5811 | } | |
5812 | ||
96a8b92e PM |
5813 | /* We don't know until after realize whether there's a GICv3 |
5814 | * attached, and that is what registers the gicv3 sysregs. | |
5815 | * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1 | |
5816 | * at runtime. | |
5817 | */ | |
5818 | static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5819 | { | |
2fc0cc0e | 5820 | ARMCPU *cpu = env_archcpu(env); |
96a8b92e PM |
5821 | uint64_t pfr1 = cpu->id_pfr1; |
5822 | ||
5823 | if (env->gicv3state) { | |
5824 | pfr1 |= 1 << 28; | |
5825 | } | |
5826 | return pfr1; | |
5827 | } | |
5828 | ||
5829 | static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5830 | { | |
2fc0cc0e | 5831 | ARMCPU *cpu = env_archcpu(env); |
47576b94 | 5832 | uint64_t pfr0 = cpu->isar.id_aa64pfr0; |
96a8b92e PM |
5833 | |
5834 | if (env->gicv3state) { | |
5835 | pfr0 |= 1 << 24; | |
5836 | } | |
5837 | return pfr0; | |
5838 | } | |
5839 | ||
2d7137c1 RH |
5840 | /* Shared logic between LORID and the rest of the LOR* registers. |
5841 | * Secure state has already been delt with. | |
5842 | */ | |
5843 | static CPAccessResult access_lor_ns(CPUARMState *env) | |
5844 | { | |
5845 | int el = arm_current_el(env); | |
5846 | ||
5847 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) { | |
5848 | return CP_ACCESS_TRAP_EL2; | |
5849 | } | |
5850 | if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { | |
5851 | return CP_ACCESS_TRAP_EL3; | |
5852 | } | |
5853 | return CP_ACCESS_OK; | |
5854 | } | |
5855 | ||
5856 | static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri, | |
5857 | bool isread) | |
5858 | { | |
5859 | if (arm_is_secure_below_el3(env)) { | |
5860 | /* Access ok in secure mode. */ | |
5861 | return CP_ACCESS_OK; | |
5862 | } | |
5863 | return access_lor_ns(env); | |
5864 | } | |
5865 | ||
5866 | static CPAccessResult access_lor_other(CPUARMState *env, | |
5867 | const ARMCPRegInfo *ri, bool isread) | |
5868 | { | |
5869 | if (arm_is_secure_below_el3(env)) { | |
5870 | /* Access denied in secure mode. */ | |
5871 | return CP_ACCESS_TRAP; | |
5872 | } | |
5873 | return access_lor_ns(env); | |
5874 | } | |
5875 | ||
967aa94f RH |
5876 | #ifdef TARGET_AARCH64 |
5877 | static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, | |
5878 | bool isread) | |
5879 | { | |
5880 | int el = arm_current_el(env); | |
5881 | ||
5882 | if (el < 2 && | |
5883 | arm_feature(env, ARM_FEATURE_EL2) && | |
5884 | !(arm_hcr_el2_eff(env) & HCR_APK)) { | |
5885 | return CP_ACCESS_TRAP_EL2; | |
5886 | } | |
5887 | if (el < 3 && | |
5888 | arm_feature(env, ARM_FEATURE_EL3) && | |
5889 | !(env->cp15.scr_el3 & SCR_APK)) { | |
5890 | return CP_ACCESS_TRAP_EL3; | |
5891 | } | |
5892 | return CP_ACCESS_OK; | |
5893 | } | |
5894 | ||
5895 | static const ARMCPRegInfo pauth_reginfo[] = { | |
5896 | { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64, | |
5897 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0, | |
5898 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5899 | .fieldoffset = offsetof(CPUARMState, keys.apda.lo) }, |
967aa94f RH |
5900 | { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
5901 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1, | |
5902 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5903 | .fieldoffset = offsetof(CPUARMState, keys.apda.hi) }, |
967aa94f RH |
5904 | { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
5905 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2, | |
5906 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5907 | .fieldoffset = offsetof(CPUARMState, keys.apdb.lo) }, |
967aa94f RH |
5908 | { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
5909 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3, | |
5910 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5911 | .fieldoffset = offsetof(CPUARMState, keys.apdb.hi) }, |
967aa94f RH |
5912 | { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
5913 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0, | |
5914 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5915 | .fieldoffset = offsetof(CPUARMState, keys.apga.lo) }, |
967aa94f RH |
5916 | { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
5917 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1, | |
5918 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5919 | .fieldoffset = offsetof(CPUARMState, keys.apga.hi) }, |
967aa94f RH |
5920 | { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
5921 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0, | |
5922 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5923 | .fieldoffset = offsetof(CPUARMState, keys.apia.lo) }, |
967aa94f RH |
5924 | { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
5925 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1, | |
5926 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5927 | .fieldoffset = offsetof(CPUARMState, keys.apia.hi) }, |
967aa94f RH |
5928 | { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
5929 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2, | |
5930 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5931 | .fieldoffset = offsetof(CPUARMState, keys.apib.lo) }, |
967aa94f RH |
5932 | { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
5933 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3, | |
5934 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5935 | .fieldoffset = offsetof(CPUARMState, keys.apib.hi) }, |
967aa94f RH |
5936 | REGINFO_SENTINEL |
5937 | }; | |
de390645 RH |
5938 | |
5939 | static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) | |
5940 | { | |
5941 | Error *err = NULL; | |
5942 | uint64_t ret; | |
5943 | ||
5944 | /* Success sets NZCV = 0000. */ | |
5945 | env->NF = env->CF = env->VF = 0, env->ZF = 1; | |
5946 | ||
5947 | if (qemu_guest_getrandom(&ret, sizeof(ret), &err) < 0) { | |
5948 | /* | |
5949 | * ??? Failed, for unknown reasons in the crypto subsystem. | |
5950 | * The best we can do is log the reason and return the | |
5951 | * timed-out indication to the guest. There is no reason | |
5952 | * we know to expect this failure to be transitory, so the | |
5953 | * guest may well hang retrying the operation. | |
5954 | */ | |
5955 | qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", | |
5956 | ri->name, error_get_pretty(err)); | |
5957 | error_free(err); | |
5958 | ||
5959 | env->ZF = 0; /* NZCF = 0100 */ | |
5960 | return 0; | |
5961 | } | |
5962 | return ret; | |
5963 | } | |
5964 | ||
5965 | /* We do not support re-seeding, so the two registers operate the same. */ | |
5966 | static const ARMCPRegInfo rndr_reginfo[] = { | |
5967 | { .name = "RNDR", .state = ARM_CP_STATE_AA64, | |
5968 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | |
5969 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 0, | |
5970 | .access = PL0_R, .readfn = rndr_readfn }, | |
5971 | { .name = "RNDRRS", .state = ARM_CP_STATE_AA64, | |
5972 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | |
5973 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1, | |
5974 | .access = PL0_R, .readfn = rndr_readfn }, | |
5975 | REGINFO_SENTINEL | |
5976 | }; | |
967aa94f RH |
5977 | #endif |
5978 | ||
cb570bd3 RH |
5979 | static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, |
5980 | bool isread) | |
5981 | { | |
5982 | int el = arm_current_el(env); | |
5983 | ||
5984 | if (el == 0) { | |
5985 | uint64_t sctlr = arm_sctlr(env, el); | |
5986 | if (!(sctlr & SCTLR_EnRCTX)) { | |
5987 | return CP_ACCESS_TRAP; | |
5988 | } | |
5989 | } else if (el == 1) { | |
5990 | uint64_t hcr = arm_hcr_el2_eff(env); | |
5991 | if (hcr & HCR_NV) { | |
5992 | return CP_ACCESS_TRAP_EL2; | |
5993 | } | |
5994 | } | |
5995 | return CP_ACCESS_OK; | |
5996 | } | |
5997 | ||
5998 | static const ARMCPRegInfo predinv_reginfo[] = { | |
5999 | { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64, | |
6000 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4, | |
6001 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
6002 | { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64, | |
6003 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5, | |
6004 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
6005 | { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64, | |
6006 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7, | |
6007 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
6008 | /* | |
6009 | * Note the AArch32 opcodes have a different OPC1. | |
6010 | */ | |
6011 | { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32, | |
6012 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4, | |
6013 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
6014 | { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32, | |
6015 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5, | |
6016 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
6017 | { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32, | |
6018 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7, | |
6019 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
6020 | REGINFO_SENTINEL | |
6021 | }; | |
6022 | ||
6a4ef4e5 MZ |
6023 | static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri, |
6024 | bool isread) | |
6025 | { | |
6026 | if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) { | |
6027 | return CP_ACCESS_TRAP_EL2; | |
6028 | } | |
6029 | ||
6030 | return CP_ACCESS_OK; | |
6031 | } | |
6032 | ||
6033 | static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri, | |
6034 | bool isread) | |
6035 | { | |
6036 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
6037 | return access_aa64_tid3(env, ri, isread); | |
6038 | } | |
6039 | ||
6040 | return CP_ACCESS_OK; | |
6041 | } | |
6042 | ||
2ceb98c0 PM |
6043 | void register_cp_regs_for_features(ARMCPU *cpu) |
6044 | { | |
6045 | /* Register all the coprocessor registers based on feature bits */ | |
6046 | CPUARMState *env = &cpu->env; | |
6047 | if (arm_feature(env, ARM_FEATURE_M)) { | |
6048 | /* M profile has no coprocessor registers */ | |
6049 | return; | |
6050 | } | |
6051 | ||
e9aa6c21 | 6052 | define_arm_cp_regs(cpu, cp_reginfo); |
9449fdf6 PM |
6053 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
6054 | /* Must go early as it is full of wildcards that may be | |
6055 | * overridden by later definitions. | |
6056 | */ | |
6057 | define_arm_cp_regs(cpu, not_v8_cp_reginfo); | |
6058 | } | |
6059 | ||
7d57f408 | 6060 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8515a092 PM |
6061 | /* The ID registers all have impdef reset values */ |
6062 | ARMCPRegInfo v6_idregs[] = { | |
0ff644a7 PM |
6063 | { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, |
6064 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
6065 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6066 | .accessfn = access_aa32_tid3, |
8515a092 | 6067 | .resetvalue = cpu->id_pfr0 }, |
96a8b92e PM |
6068 | /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know |
6069 | * the value of the GIC field until after we define these regs. | |
6070 | */ | |
0ff644a7 PM |
6071 | { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, |
6072 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | |
96a8b92e | 6073 | .access = PL1_R, .type = ARM_CP_NO_RAW, |
6a4ef4e5 | 6074 | .accessfn = access_aa32_tid3, |
96a8b92e PM |
6075 | .readfn = id_pfr1_read, |
6076 | .writefn = arm_cp_write_ignore }, | |
0ff644a7 PM |
6077 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, |
6078 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | |
6079 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6080 | .accessfn = access_aa32_tid3, |
8515a092 | 6081 | .resetvalue = cpu->id_dfr0 }, |
0ff644a7 PM |
6082 | { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, |
6083 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, | |
6084 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6085 | .accessfn = access_aa32_tid3, |
8515a092 | 6086 | .resetvalue = cpu->id_afr0 }, |
0ff644a7 PM |
6087 | { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, |
6088 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, | |
6089 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6090 | .accessfn = access_aa32_tid3, |
8515a092 | 6091 | .resetvalue = cpu->id_mmfr0 }, |
0ff644a7 PM |
6092 | { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, |
6093 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, | |
6094 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6095 | .accessfn = access_aa32_tid3, |
8515a092 | 6096 | .resetvalue = cpu->id_mmfr1 }, |
0ff644a7 PM |
6097 | { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, |
6098 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, | |
6099 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6100 | .accessfn = access_aa32_tid3, |
8515a092 | 6101 | .resetvalue = cpu->id_mmfr2 }, |
0ff644a7 PM |
6102 | { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, |
6103 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, | |
6104 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6105 | .accessfn = access_aa32_tid3, |
8515a092 | 6106 | .resetvalue = cpu->id_mmfr3 }, |
0ff644a7 PM |
6107 | { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, |
6108 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
6109 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6110 | .accessfn = access_aa32_tid3, |
47576b94 | 6111 | .resetvalue = cpu->isar.id_isar0 }, |
0ff644a7 PM |
6112 | { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, |
6113 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, | |
6114 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6115 | .accessfn = access_aa32_tid3, |
47576b94 | 6116 | .resetvalue = cpu->isar.id_isar1 }, |
0ff644a7 PM |
6117 | { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, |
6118 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
6119 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6120 | .accessfn = access_aa32_tid3, |
47576b94 | 6121 | .resetvalue = cpu->isar.id_isar2 }, |
0ff644a7 PM |
6122 | { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, |
6123 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, | |
6124 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6125 | .accessfn = access_aa32_tid3, |
47576b94 | 6126 | .resetvalue = cpu->isar.id_isar3 }, |
0ff644a7 PM |
6127 | { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, |
6128 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, | |
6129 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6130 | .accessfn = access_aa32_tid3, |
47576b94 | 6131 | .resetvalue = cpu->isar.id_isar4 }, |
0ff644a7 PM |
6132 | { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, |
6133 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, | |
6134 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6135 | .accessfn = access_aa32_tid3, |
47576b94 | 6136 | .resetvalue = cpu->isar.id_isar5 }, |
e20d84c1 PM |
6137 | { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, |
6138 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, | |
6139 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6140 | .accessfn = access_aa32_tid3, |
e20d84c1 | 6141 | .resetvalue = cpu->id_mmfr4 }, |
802abf40 | 6142 | { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
6143 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, |
6144 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6145 | .accessfn = access_aa32_tid3, |
47576b94 | 6146 | .resetvalue = cpu->isar.id_isar6 }, |
8515a092 PM |
6147 | REGINFO_SENTINEL |
6148 | }; | |
6149 | define_arm_cp_regs(cpu, v6_idregs); | |
7d57f408 PM |
6150 | define_arm_cp_regs(cpu, v6_cp_reginfo); |
6151 | } else { | |
6152 | define_arm_cp_regs(cpu, not_v6_cp_reginfo); | |
6153 | } | |
4d31c596 PM |
6154 | if (arm_feature(env, ARM_FEATURE_V6K)) { |
6155 | define_arm_cp_regs(cpu, v6k_cp_reginfo); | |
6156 | } | |
5e5cf9e3 | 6157 | if (arm_feature(env, ARM_FEATURE_V7MP) && |
452a0955 | 6158 | !arm_feature(env, ARM_FEATURE_PMSA)) { |
995939a6 PM |
6159 | define_arm_cp_regs(cpu, v7mp_cp_reginfo); |
6160 | } | |
327dd510 AL |
6161 | if (arm_feature(env, ARM_FEATURE_V7VE)) { |
6162 | define_arm_cp_regs(cpu, pmovsset_cp_reginfo); | |
6163 | } | |
e9aa6c21 | 6164 | if (arm_feature(env, ARM_FEATURE_V7)) { |
200ac0ef | 6165 | /* v7 performance monitor control register: same implementor |
ac689a2e AL |
6166 | * field as main ID register, and we implement four counters in |
6167 | * addition to the cycle count register. | |
200ac0ef | 6168 | */ |
ac689a2e | 6169 | unsigned int i, pmcrn = 4; |
200ac0ef PM |
6170 | ARMCPRegInfo pmcr = { |
6171 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | |
8521466b | 6172 | .access = PL0_RW, |
7a0e58fa | 6173 | .type = ARM_CP_IO | ARM_CP_ALIAS, |
8521466b | 6174 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), |
fcd25206 PM |
6175 | .accessfn = pmreg_access, .writefn = pmcr_write, |
6176 | .raw_writefn = raw_write, | |
200ac0ef | 6177 | }; |
8521466b AF |
6178 | ARMCPRegInfo pmcr64 = { |
6179 | .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, | |
6180 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, | |
6181 | .access = PL0_RW, .accessfn = pmreg_access, | |
6182 | .type = ARM_CP_IO, | |
6183 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), | |
ac689a2e | 6184 | .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT), |
8521466b AF |
6185 | .writefn = pmcr_write, .raw_writefn = raw_write, |
6186 | }; | |
7c2cb42b | 6187 | define_one_arm_cp_reg(cpu, &pmcr); |
8521466b | 6188 | define_one_arm_cp_reg(cpu, &pmcr64); |
5ecdd3e4 AL |
6189 | for (i = 0; i < pmcrn; i++) { |
6190 | char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i); | |
6191 | char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i); | |
6192 | char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i); | |
6193 | char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i); | |
6194 | ARMCPRegInfo pmev_regs[] = { | |
62c7ec34 | 6195 | { .name = pmevcntr_name, .cp = 15, .crn = 14, |
5ecdd3e4 AL |
6196 | .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, |
6197 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6198 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, | |
6199 | .accessfn = pmreg_access }, | |
6200 | { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64, | |
62c7ec34 | 6201 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)), |
5ecdd3e4 AL |
6202 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, |
6203 | .type = ARM_CP_IO, | |
6204 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, | |
6205 | .raw_readfn = pmevcntr_rawread, | |
6206 | .raw_writefn = pmevcntr_rawwrite }, | |
62c7ec34 | 6207 | { .name = pmevtyper_name, .cp = 15, .crn = 14, |
5ecdd3e4 AL |
6208 | .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, |
6209 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6210 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | |
6211 | .accessfn = pmreg_access }, | |
6212 | { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64, | |
62c7ec34 | 6213 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)), |
5ecdd3e4 AL |
6214 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, |
6215 | .type = ARM_CP_IO, | |
6216 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | |
6217 | .raw_writefn = pmevtyper_rawwrite }, | |
6218 | REGINFO_SENTINEL | |
6219 | }; | |
6220 | define_arm_cp_regs(cpu, pmev_regs); | |
6221 | g_free(pmevcntr_name); | |
6222 | g_free(pmevcntr_el0_name); | |
6223 | g_free(pmevtyper_name); | |
6224 | g_free(pmevtyper_el0_name); | |
6225 | } | |
776d4e5c | 6226 | ARMCPRegInfo clidr = { |
7da845b0 PM |
6227 | .name = "CLIDR", .state = ARM_CP_STATE_BOTH, |
6228 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | |
630fcd4d MZ |
6229 | .access = PL1_R, .type = ARM_CP_CONST, |
6230 | .accessfn = access_aa64_tid2, | |
6231 | .resetvalue = cpu->clidr | |
776d4e5c | 6232 | }; |
776d4e5c | 6233 | define_one_arm_cp_reg(cpu, &clidr); |
e9aa6c21 | 6234 | define_arm_cp_regs(cpu, v7_cp_reginfo); |
50300698 | 6235 | define_debug_regs(cpu); |
7d57f408 PM |
6236 | } else { |
6237 | define_arm_cp_regs(cpu, not_v7_cp_reginfo); | |
e9aa6c21 | 6238 | } |
cad86737 AL |
6239 | if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 && |
6240 | FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) { | |
6241 | ARMCPRegInfo v81_pmu_regs[] = { | |
6242 | { .name = "PMCEID2", .state = ARM_CP_STATE_AA32, | |
6243 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4, | |
6244 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6245 | .resetvalue = extract64(cpu->pmceid0, 32, 32) }, | |
6246 | { .name = "PMCEID3", .state = ARM_CP_STATE_AA32, | |
6247 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5, | |
6248 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6249 | .resetvalue = extract64(cpu->pmceid1, 32, 32) }, | |
6250 | REGINFO_SENTINEL | |
6251 | }; | |
6252 | define_arm_cp_regs(cpu, v81_pmu_regs); | |
6253 | } | |
b0d2b7d0 | 6254 | if (arm_feature(env, ARM_FEATURE_V8)) { |
e20d84c1 PM |
6255 | /* AArch64 ID registers, which all have impdef reset values. |
6256 | * Note that within the ID register ranges the unused slots | |
6257 | * must all RAZ, not UNDEF; future architecture versions may | |
6258 | * define new registers here. | |
6259 | */ | |
e60cef86 | 6260 | ARMCPRegInfo v8_idregs[] = { |
96a8b92e PM |
6261 | /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't |
6262 | * know the right value for the GIC field until after we | |
6263 | * define these regs. | |
6264 | */ | |
e60cef86 PM |
6265 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, |
6266 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | |
96a8b92e | 6267 | .access = PL1_R, .type = ARM_CP_NO_RAW, |
6a4ef4e5 | 6268 | .accessfn = access_aa64_tid3, |
96a8b92e PM |
6269 | .readfn = id_aa64pfr0_read, |
6270 | .writefn = arm_cp_write_ignore }, | |
e60cef86 PM |
6271 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, |
6272 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | |
6273 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6274 | .accessfn = access_aa64_tid3, |
47576b94 | 6275 | .resetvalue = cpu->isar.id_aa64pfr1}, |
e20d84c1 PM |
6276 | { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
6277 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, | |
6278 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6279 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
6280 | .resetvalue = 0 }, |
6281 | { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6282 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, | |
6283 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6284 | .accessfn = access_aa64_tid3, |
e20d84c1 | 6285 | .resetvalue = 0 }, |
9516d772 | 6286 | { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
6287 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, |
6288 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6289 | .accessfn = access_aa64_tid3, |
9516d772 | 6290 | /* At present, only SVEver == 0 is defined anyway. */ |
e20d84c1 PM |
6291 | .resetvalue = 0 }, |
6292 | { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6293 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, | |
6294 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6295 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
6296 | .resetvalue = 0 }, |
6297 | { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6298 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, | |
6299 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6300 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
6301 | .resetvalue = 0 }, |
6302 | { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6303 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, | |
6304 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6305 | .accessfn = access_aa64_tid3, |
e20d84c1 | 6306 | .resetvalue = 0 }, |
e60cef86 PM |
6307 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, |
6308 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | |
6309 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6310 | .accessfn = access_aa64_tid3, |
d6f02ce3 | 6311 | .resetvalue = cpu->id_aa64dfr0 }, |
e60cef86 PM |
6312 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, |
6313 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | |
6314 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6315 | .accessfn = access_aa64_tid3, |
e60cef86 | 6316 | .resetvalue = cpu->id_aa64dfr1 }, |
e20d84c1 PM |
6317 | { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
6318 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, | |
6319 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6320 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
6321 | .resetvalue = 0 }, |
6322 | { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6323 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, | |
6324 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6325 | .accessfn = access_aa64_tid3, |
e20d84c1 | 6326 | .resetvalue = 0 }, |
e60cef86 PM |
6327 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, |
6328 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | |
6329 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6330 | .accessfn = access_aa64_tid3, |
e60cef86 PM |
6331 | .resetvalue = cpu->id_aa64afr0 }, |
6332 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | |
6333 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | |
6334 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6335 | .accessfn = access_aa64_tid3, |
e60cef86 | 6336 | .resetvalue = cpu->id_aa64afr1 }, |
e20d84c1 PM |
6337 | { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
6338 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, | |
6339 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6340 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
6341 | .resetvalue = 0 }, |
6342 | { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6343 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, | |
6344 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6345 | .accessfn = access_aa64_tid3, |
e20d84c1 | 6346 | .resetvalue = 0 }, |
e60cef86 PM |
6347 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, |
6348 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | |
6349 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6350 | .accessfn = access_aa64_tid3, |
47576b94 | 6351 | .resetvalue = cpu->isar.id_aa64isar0 }, |
e60cef86 PM |
6352 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, |
6353 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | |
6354 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6355 | .accessfn = access_aa64_tid3, |
47576b94 | 6356 | .resetvalue = cpu->isar.id_aa64isar1 }, |
e20d84c1 PM |
6357 | { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
6358 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, | |
6359 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6360 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
6361 | .resetvalue = 0 }, |
6362 | { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6363 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, | |
6364 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6365 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
6366 | .resetvalue = 0 }, |
6367 | { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6368 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, | |
6369 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6370 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
6371 | .resetvalue = 0 }, |
6372 | { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6373 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, | |
6374 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6375 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
6376 | .resetvalue = 0 }, |
6377 | { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6378 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, | |
6379 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6380 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
6381 | .resetvalue = 0 }, |
6382 | { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6383 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, | |
6384 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6385 | .accessfn = access_aa64_tid3, |
e20d84c1 | 6386 | .resetvalue = 0 }, |
e60cef86 PM |
6387 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, |
6388 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
6389 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6390 | .accessfn = access_aa64_tid3, |
3dc91ddb | 6391 | .resetvalue = cpu->isar.id_aa64mmfr0 }, |
e60cef86 PM |
6392 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, |
6393 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | |
6394 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6395 | .accessfn = access_aa64_tid3, |
3dc91ddb | 6396 | .resetvalue = cpu->isar.id_aa64mmfr1 }, |
e20d84c1 PM |
6397 | { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
6398 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, | |
6399 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6400 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
6401 | .resetvalue = 0 }, |
6402 | { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6403 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, | |
6404 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6405 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
6406 | .resetvalue = 0 }, |
6407 | { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6408 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, | |
6409 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6410 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
6411 | .resetvalue = 0 }, |
6412 | { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6413 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, | |
6414 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6415 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
6416 | .resetvalue = 0 }, |
6417 | { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6418 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, | |
6419 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6420 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
6421 | .resetvalue = 0 }, |
6422 | { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6423 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, | |
6424 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6425 | .accessfn = access_aa64_tid3, |
e20d84c1 | 6426 | .resetvalue = 0 }, |
a50c0f51 PM |
6427 | { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, |
6428 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
6429 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6430 | .accessfn = access_aa64_tid3, |
47576b94 | 6431 | .resetvalue = cpu->isar.mvfr0 }, |
a50c0f51 PM |
6432 | { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, |
6433 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
6434 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6435 | .accessfn = access_aa64_tid3, |
47576b94 | 6436 | .resetvalue = cpu->isar.mvfr1 }, |
a50c0f51 PM |
6437 | { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, |
6438 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
6439 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6440 | .accessfn = access_aa64_tid3, |
47576b94 | 6441 | .resetvalue = cpu->isar.mvfr2 }, |
e20d84c1 PM |
6442 | { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
6443 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, | |
6444 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6445 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
6446 | .resetvalue = 0 }, |
6447 | { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6448 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, | |
6449 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6450 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
6451 | .resetvalue = 0 }, |
6452 | { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6453 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, | |
6454 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6455 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
6456 | .resetvalue = 0 }, |
6457 | { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6458 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, | |
6459 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6460 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
6461 | .resetvalue = 0 }, |
6462 | { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6463 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, | |
6464 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 6465 | .accessfn = access_aa64_tid3, |
e20d84c1 | 6466 | .resetvalue = 0 }, |
4054bfa9 AF |
6467 | { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, |
6468 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, | |
6469 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
cad86737 | 6470 | .resetvalue = extract64(cpu->pmceid0, 0, 32) }, |
4054bfa9 AF |
6471 | { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, |
6472 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, | |
6473 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6474 | .resetvalue = cpu->pmceid0 }, | |
6475 | { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, | |
6476 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, | |
6477 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
cad86737 | 6478 | .resetvalue = extract64(cpu->pmceid1, 0, 32) }, |
4054bfa9 AF |
6479 | { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, |
6480 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, | |
6481 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6482 | .resetvalue = cpu->pmceid1 }, | |
e60cef86 PM |
6483 | REGINFO_SENTINEL |
6484 | }; | |
6c5c0fec AB |
6485 | #ifdef CONFIG_USER_ONLY |
6486 | ARMCPRegUserSpaceInfo v8_user_idregs[] = { | |
6487 | { .name = "ID_AA64PFR0_EL1", | |
6488 | .exported_bits = 0x000f000f00ff0000, | |
6489 | .fixed_bits = 0x0000000000000011 }, | |
6490 | { .name = "ID_AA64PFR1_EL1", | |
6491 | .exported_bits = 0x00000000000000f0 }, | |
d040242e AB |
6492 | { .name = "ID_AA64PFR*_EL1_RESERVED", |
6493 | .is_glob = true }, | |
6c5c0fec AB |
6494 | { .name = "ID_AA64ZFR0_EL1" }, |
6495 | { .name = "ID_AA64MMFR0_EL1", | |
6496 | .fixed_bits = 0x00000000ff000000 }, | |
6497 | { .name = "ID_AA64MMFR1_EL1" }, | |
d040242e AB |
6498 | { .name = "ID_AA64MMFR*_EL1_RESERVED", |
6499 | .is_glob = true }, | |
6c5c0fec AB |
6500 | { .name = "ID_AA64DFR0_EL1", |
6501 | .fixed_bits = 0x0000000000000006 }, | |
6502 | { .name = "ID_AA64DFR1_EL1" }, | |
d040242e AB |
6503 | { .name = "ID_AA64DFR*_EL1_RESERVED", |
6504 | .is_glob = true }, | |
6505 | { .name = "ID_AA64AFR*", | |
6506 | .is_glob = true }, | |
6c5c0fec AB |
6507 | { .name = "ID_AA64ISAR0_EL1", |
6508 | .exported_bits = 0x00fffffff0fffff0 }, | |
6509 | { .name = "ID_AA64ISAR1_EL1", | |
6510 | .exported_bits = 0x000000f0ffffffff }, | |
d040242e AB |
6511 | { .name = "ID_AA64ISAR*_EL1_RESERVED", |
6512 | .is_glob = true }, | |
6c5c0fec AB |
6513 | REGUSERINFO_SENTINEL |
6514 | }; | |
6515 | modify_arm_cp_regs(v8_idregs, v8_user_idregs); | |
6516 | #endif | |
be8e8128 GB |
6517 | /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ |
6518 | if (!arm_feature(env, ARM_FEATURE_EL3) && | |
6519 | !arm_feature(env, ARM_FEATURE_EL2)) { | |
6520 | ARMCPRegInfo rvbar = { | |
6521 | .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, | |
6522 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, | |
6523 | .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar | |
6524 | }; | |
6525 | define_one_arm_cp_reg(cpu, &rvbar); | |
6526 | } | |
e60cef86 | 6527 | define_arm_cp_regs(cpu, v8_idregs); |
b0d2b7d0 PM |
6528 | define_arm_cp_regs(cpu, v8_cp_reginfo); |
6529 | } | |
3b685ba7 | 6530 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
f0d574d6 | 6531 | uint64_t vmpidr_def = mpidr_read_val(env); |
731de9e6 EI |
6532 | ARMCPRegInfo vpidr_regs[] = { |
6533 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | |
6534 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
6535 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
36476562 PM |
6536 | .resetvalue = cpu->midr, .type = ARM_CP_ALIAS, |
6537 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) }, | |
731de9e6 EI |
6538 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, |
6539 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
6540 | .access = PL2_RW, .resetvalue = cpu->midr, | |
6541 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
f0d574d6 EI |
6542 | { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, |
6543 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
6544 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
36476562 PM |
6545 | .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS, |
6546 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) }, | |
f0d574d6 EI |
6547 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, |
6548 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
6549 | .access = PL2_RW, | |
6550 | .resetvalue = vmpidr_def, | |
6551 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | |
731de9e6 EI |
6552 | REGINFO_SENTINEL |
6553 | }; | |
6554 | define_arm_cp_regs(cpu, vpidr_regs); | |
4771cd01 | 6555 | define_arm_cp_regs(cpu, el2_cp_reginfo); |
ce4afed8 PM |
6556 | if (arm_feature(env, ARM_FEATURE_V8)) { |
6557 | define_arm_cp_regs(cpu, el2_v8_cp_reginfo); | |
6558 | } | |
be8e8128 GB |
6559 | /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ |
6560 | if (!arm_feature(env, ARM_FEATURE_EL3)) { | |
6561 | ARMCPRegInfo rvbar = { | |
6562 | .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, | |
6563 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, | |
6564 | .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar | |
6565 | }; | |
6566 | define_one_arm_cp_reg(cpu, &rvbar); | |
6567 | } | |
d42e3c26 EI |
6568 | } else { |
6569 | /* If EL2 is missing but higher ELs are enabled, we need to | |
6570 | * register the no_el2 reginfos. | |
6571 | */ | |
6572 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
f0d574d6 EI |
6573 | /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value |
6574 | * of MIDR_EL1 and MPIDR_EL1. | |
731de9e6 EI |
6575 | */ |
6576 | ARMCPRegInfo vpidr_regs[] = { | |
6577 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH, | |
6578 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
6579 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
6580 | .type = ARM_CP_CONST, .resetvalue = cpu->midr, | |
6581 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
f0d574d6 EI |
6582 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
6583 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
6584 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
6585 | .type = ARM_CP_NO_RAW, | |
6586 | .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, | |
731de9e6 EI |
6587 | REGINFO_SENTINEL |
6588 | }; | |
6589 | define_arm_cp_regs(cpu, vpidr_regs); | |
4771cd01 | 6590 | define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); |
ce4afed8 PM |
6591 | if (arm_feature(env, ARM_FEATURE_V8)) { |
6592 | define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo); | |
6593 | } | |
d42e3c26 | 6594 | } |
3b685ba7 | 6595 | } |
81547d66 | 6596 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0f1a3b24 | 6597 | define_arm_cp_regs(cpu, el3_cp_reginfo); |
e24fdd23 PM |
6598 | ARMCPRegInfo el3_regs[] = { |
6599 | { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, | |
6600 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, | |
6601 | .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, | |
6602 | { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, | |
6603 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, | |
6604 | .access = PL3_RW, | |
6605 | .raw_writefn = raw_write, .writefn = sctlr_write, | |
6606 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), | |
6607 | .resetvalue = cpu->reset_sctlr }, | |
6608 | REGINFO_SENTINEL | |
be8e8128 | 6609 | }; |
e24fdd23 PM |
6610 | |
6611 | define_arm_cp_regs(cpu, el3_regs); | |
81547d66 | 6612 | } |
2f027fc5 PM |
6613 | /* The behaviour of NSACR is sufficiently various that we don't |
6614 | * try to describe it in a single reginfo: | |
6615 | * if EL3 is 64 bit, then trap to EL3 from S EL1, | |
6616 | * reads as constant 0xc00 from NS EL1 and NS EL2 | |
6617 | * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 | |
6618 | * if v7 without EL3, register doesn't exist | |
6619 | * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 | |
6620 | */ | |
6621 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
6622 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
6623 | ARMCPRegInfo nsacr = { | |
6624 | .name = "NSACR", .type = ARM_CP_CONST, | |
6625 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
6626 | .access = PL1_RW, .accessfn = nsacr_access, | |
6627 | .resetvalue = 0xc00 | |
6628 | }; | |
6629 | define_one_arm_cp_reg(cpu, &nsacr); | |
6630 | } else { | |
6631 | ARMCPRegInfo nsacr = { | |
6632 | .name = "NSACR", | |
6633 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
6634 | .access = PL3_RW | PL1_R, | |
6635 | .resetvalue = 0, | |
6636 | .fieldoffset = offsetof(CPUARMState, cp15.nsacr) | |
6637 | }; | |
6638 | define_one_arm_cp_reg(cpu, &nsacr); | |
6639 | } | |
6640 | } else { | |
6641 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
6642 | ARMCPRegInfo nsacr = { | |
6643 | .name = "NSACR", .type = ARM_CP_CONST, | |
6644 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
6645 | .access = PL1_R, | |
6646 | .resetvalue = 0xc00 | |
6647 | }; | |
6648 | define_one_arm_cp_reg(cpu, &nsacr); | |
6649 | } | |
6650 | } | |
6651 | ||
452a0955 | 6652 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
6cb0b013 PC |
6653 | if (arm_feature(env, ARM_FEATURE_V6)) { |
6654 | /* PMSAv6 not implemented */ | |
6655 | assert(arm_feature(env, ARM_FEATURE_V7)); | |
6656 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); | |
6657 | define_arm_cp_regs(cpu, pmsav7_cp_reginfo); | |
6658 | } else { | |
6659 | define_arm_cp_regs(cpu, pmsav5_cp_reginfo); | |
6660 | } | |
18032bec | 6661 | } else { |
8e5d75c9 | 6662 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); |
18032bec | 6663 | define_arm_cp_regs(cpu, vmsa_cp_reginfo); |
ab638a32 RH |
6664 | /* TTCBR2 is introduced with ARMv8.2-A32HPD. */ |
6665 | if (FIELD_EX32(cpu->id_mmfr4, ID_MMFR4, HPDS) != 0) { | |
6666 | define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); | |
6667 | } | |
18032bec | 6668 | } |
c326b979 PM |
6669 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
6670 | define_arm_cp_regs(cpu, t2ee_cp_reginfo); | |
6671 | } | |
6cc7a3ae PM |
6672 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
6673 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); | |
6674 | } | |
4a501606 PM |
6675 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
6676 | define_arm_cp_regs(cpu, vapa_cp_reginfo); | |
6677 | } | |
c4804214 PM |
6678 | if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { |
6679 | define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); | |
6680 | } | |
6681 | if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { | |
6682 | define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); | |
6683 | } | |
6684 | if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { | |
6685 | define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); | |
6686 | } | |
18032bec PM |
6687 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
6688 | define_arm_cp_regs(cpu, omap_cp_reginfo); | |
6689 | } | |
34f90529 PM |
6690 | if (arm_feature(env, ARM_FEATURE_STRONGARM)) { |
6691 | define_arm_cp_regs(cpu, strongarm_cp_reginfo); | |
6692 | } | |
1047b9d7 PM |
6693 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
6694 | define_arm_cp_regs(cpu, xscale_cp_reginfo); | |
6695 | } | |
6696 | if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { | |
6697 | define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); | |
6698 | } | |
7ac681cf PM |
6699 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
6700 | define_arm_cp_regs(cpu, lpae_cp_reginfo); | |
6701 | } | |
7884849c PM |
6702 | /* Slightly awkwardly, the OMAP and StrongARM cores need all of |
6703 | * cp15 crn=0 to be writes-ignored, whereas for other cores they should | |
6704 | * be read-only (ie write causes UNDEF exception). | |
6705 | */ | |
6706 | { | |
00a29f3d PM |
6707 | ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { |
6708 | /* Pre-v8 MIDR space. | |
6709 | * Note that the MIDR isn't a simple constant register because | |
7884849c PM |
6710 | * of the TI925 behaviour where writes to another register can |
6711 | * cause the MIDR value to change. | |
97ce8d61 PC |
6712 | * |
6713 | * Unimplemented registers in the c15 0 0 0 space default to | |
6714 | * MIDR. Define MIDR first as this entire space, then CTR, TCMTR | |
6715 | * and friends override accordingly. | |
7884849c PM |
6716 | */ |
6717 | { .name = "MIDR", | |
97ce8d61 | 6718 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, |
7884849c | 6719 | .access = PL1_R, .resetvalue = cpu->midr, |
d4e6df63 | 6720 | .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, |
731de9e6 | 6721 | .readfn = midr_read, |
97ce8d61 PC |
6722 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
6723 | .type = ARM_CP_OVERRIDE }, | |
7884849c PM |
6724 | /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ |
6725 | { .name = "DUMMY", | |
6726 | .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, | |
6727 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6728 | { .name = "DUMMY", | |
6729 | .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, | |
6730 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6731 | { .name = "DUMMY", | |
6732 | .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, | |
6733 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6734 | { .name = "DUMMY", | |
6735 | .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, | |
6736 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6737 | { .name = "DUMMY", | |
6738 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | |
6739 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6740 | REGINFO_SENTINEL | |
6741 | }; | |
00a29f3d | 6742 | ARMCPRegInfo id_v8_midr_cp_reginfo[] = { |
00a29f3d PM |
6743 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, |
6744 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, | |
731de9e6 EI |
6745 | .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, |
6746 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), | |
6747 | .readfn = midr_read }, | |
ac00c79f SF |
6748 | /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ |
6749 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
6750 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
6751 | .access = PL1_R, .resetvalue = cpu->midr }, | |
6752 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
6753 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, | |
6754 | .access = PL1_R, .resetvalue = cpu->midr }, | |
00a29f3d PM |
6755 | { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, |
6756 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, | |
93fbc983 MZ |
6757 | .access = PL1_R, |
6758 | .accessfn = access_aa64_tid1, | |
6759 | .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, | |
00a29f3d PM |
6760 | REGINFO_SENTINEL |
6761 | }; | |
6762 | ARMCPRegInfo id_cp_reginfo[] = { | |
6763 | /* These are common to v8 and pre-v8 */ | |
6764 | { .name = "CTR", | |
6765 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, | |
630fcd4d MZ |
6766 | .access = PL1_R, .accessfn = ctr_el0_access, |
6767 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
00a29f3d PM |
6768 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, |
6769 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, | |
6770 | .access = PL0_R, .accessfn = ctr_el0_access, | |
6771 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
6772 | /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ | |
6773 | { .name = "TCMTR", | |
6774 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, | |
93fbc983 MZ |
6775 | .access = PL1_R, |
6776 | .accessfn = access_aa32_tid1, | |
6777 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
00a29f3d PM |
6778 | REGINFO_SENTINEL |
6779 | }; | |
8085ce63 PC |
6780 | /* TLBTR is specific to VMSA */ |
6781 | ARMCPRegInfo id_tlbtr_reginfo = { | |
6782 | .name = "TLBTR", | |
6783 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, | |
93fbc983 MZ |
6784 | .access = PL1_R, |
6785 | .accessfn = access_aa32_tid1, | |
6786 | .type = ARM_CP_CONST, .resetvalue = 0, | |
8085ce63 | 6787 | }; |
3281af81 PC |
6788 | /* MPUIR is specific to PMSA V6+ */ |
6789 | ARMCPRegInfo id_mpuir_reginfo = { | |
6790 | .name = "MPUIR", | |
6791 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
6792 | .access = PL1_R, .type = ARM_CP_CONST, | |
6793 | .resetvalue = cpu->pmsav7_dregion << 8 | |
6794 | }; | |
7884849c PM |
6795 | ARMCPRegInfo crn0_wi_reginfo = { |
6796 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, | |
6797 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | |
6798 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | |
6799 | }; | |
6c5c0fec AB |
6800 | #ifdef CONFIG_USER_ONLY |
6801 | ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = { | |
6802 | { .name = "MIDR_EL1", | |
6803 | .exported_bits = 0x00000000ffffffff }, | |
6804 | { .name = "REVIDR_EL1" }, | |
6805 | REGUSERINFO_SENTINEL | |
6806 | }; | |
6807 | modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo); | |
6808 | #endif | |
7884849c PM |
6809 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || |
6810 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | |
6811 | ARMCPRegInfo *r; | |
6812 | /* Register the blanket "writes ignored" value first to cover the | |
a703eda1 PC |
6813 | * whole space. Then update the specific ID registers to allow write |
6814 | * access, so that they ignore writes rather than causing them to | |
6815 | * UNDEF. | |
7884849c PM |
6816 | */ |
6817 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | |
00a29f3d PM |
6818 | for (r = id_pre_v8_midr_cp_reginfo; |
6819 | r->type != ARM_CP_SENTINEL; r++) { | |
6820 | r->access = PL1_RW; | |
6821 | } | |
7884849c PM |
6822 | for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { |
6823 | r->access = PL1_RW; | |
7884849c | 6824 | } |
10006112 | 6825 | id_mpuir_reginfo.access = PL1_RW; |
3281af81 | 6826 | id_tlbtr_reginfo.access = PL1_RW; |
7884849c | 6827 | } |
00a29f3d PM |
6828 | if (arm_feature(env, ARM_FEATURE_V8)) { |
6829 | define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); | |
6830 | } else { | |
6831 | define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); | |
6832 | } | |
a703eda1 | 6833 | define_arm_cp_regs(cpu, id_cp_reginfo); |
452a0955 | 6834 | if (!arm_feature(env, ARM_FEATURE_PMSA)) { |
8085ce63 | 6835 | define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); |
3281af81 PC |
6836 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
6837 | define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); | |
8085ce63 | 6838 | } |
7884849c PM |
6839 | } |
6840 | ||
97ce8d61 | 6841 | if (arm_feature(env, ARM_FEATURE_MPIDR)) { |
52264166 AB |
6842 | ARMCPRegInfo mpidr_cp_reginfo[] = { |
6843 | { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
6844 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | |
6845 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, | |
6846 | REGINFO_SENTINEL | |
6847 | }; | |
6848 | #ifdef CONFIG_USER_ONLY | |
6849 | ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = { | |
6850 | { .name = "MPIDR_EL1", | |
6851 | .fixed_bits = 0x0000000080000000 }, | |
6852 | REGUSERINFO_SENTINEL | |
6853 | }; | |
6854 | modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); | |
6855 | #endif | |
97ce8d61 PC |
6856 | define_arm_cp_regs(cpu, mpidr_cp_reginfo); |
6857 | } | |
6858 | ||
2771db27 | 6859 | if (arm_feature(env, ARM_FEATURE_AUXCR)) { |
834a6c69 PM |
6860 | ARMCPRegInfo auxcr_reginfo[] = { |
6861 | { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, | |
6862 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, | |
6863 | .access = PL1_RW, .type = ARM_CP_CONST, | |
6864 | .resetvalue = cpu->reset_auxcr }, | |
6865 | { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, | |
6866 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, | |
6867 | .access = PL2_RW, .type = ARM_CP_CONST, | |
6868 | .resetvalue = 0 }, | |
6869 | { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, | |
6870 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, | |
6871 | .access = PL3_RW, .type = ARM_CP_CONST, | |
6872 | .resetvalue = 0 }, | |
6873 | REGINFO_SENTINEL | |
2771db27 | 6874 | }; |
834a6c69 | 6875 | define_arm_cp_regs(cpu, auxcr_reginfo); |
0e0456ab PM |
6876 | if (arm_feature(env, ARM_FEATURE_V8)) { |
6877 | /* HACTLR2 maps to ACTLR_EL2[63:32] and is not in ARMv7 */ | |
6878 | ARMCPRegInfo hactlr2_reginfo = { | |
6879 | .name = "HACTLR2", .state = ARM_CP_STATE_AA32, | |
6880 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3, | |
6881 | .access = PL2_RW, .type = ARM_CP_CONST, | |
6882 | .resetvalue = 0 | |
6883 | }; | |
6884 | define_one_arm_cp_reg(cpu, &hactlr2_reginfo); | |
6885 | } | |
2771db27 PM |
6886 | } |
6887 | ||
d8ba780b | 6888 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
d56974af LM |
6889 | /* |
6890 | * CBAR is IMPDEF, but common on Arm Cortex-A implementations. | |
6891 | * There are two flavours: | |
6892 | * (1) older 32-bit only cores have a simple 32-bit CBAR | |
6893 | * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a | |
6894 | * 32-bit register visible to AArch32 at a different encoding | |
6895 | * to the "flavour 1" register and with the bits rearranged to | |
6896 | * be able to squash a 64-bit address into the 32-bit view. | |
6897 | * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but | |
6898 | * in future if we support AArch32-only configs of some of the | |
6899 | * AArch64 cores we might need to add a specific feature flag | |
6900 | * to indicate cores with "flavour 2" CBAR. | |
6901 | */ | |
f318cec6 PM |
6902 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
6903 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | |
6904 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | |
6905 | | extract64(cpu->reset_cbar, 32, 12); | |
6906 | ARMCPRegInfo cbar_reginfo[] = { | |
6907 | { .name = "CBAR", | |
6908 | .type = ARM_CP_CONST, | |
d56974af LM |
6909 | .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0, |
6910 | .access = PL1_R, .resetvalue = cbar32 }, | |
f318cec6 PM |
6911 | { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, |
6912 | .type = ARM_CP_CONST, | |
6913 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | |
d56974af | 6914 | .access = PL1_R, .resetvalue = cpu->reset_cbar }, |
f318cec6 PM |
6915 | REGINFO_SENTINEL |
6916 | }; | |
6917 | /* We don't implement a r/w 64 bit CBAR currently */ | |
6918 | assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); | |
6919 | define_arm_cp_regs(cpu, cbar_reginfo); | |
6920 | } else { | |
6921 | ARMCPRegInfo cbar = { | |
6922 | .name = "CBAR", | |
6923 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
6924 | .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, | |
6925 | .fieldoffset = offsetof(CPUARMState, | |
6926 | cp15.c15_config_base_address) | |
6927 | }; | |
6928 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | |
6929 | cbar.access = PL1_R; | |
6930 | cbar.fieldoffset = 0; | |
6931 | cbar.type = ARM_CP_CONST; | |
6932 | } | |
6933 | define_one_arm_cp_reg(cpu, &cbar); | |
6934 | } | |
d8ba780b PC |
6935 | } |
6936 | ||
91db4642 CLG |
6937 | if (arm_feature(env, ARM_FEATURE_VBAR)) { |
6938 | ARMCPRegInfo vbar_cp_reginfo[] = { | |
6939 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, | |
6940 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | |
6941 | .access = PL1_RW, .writefn = vbar_write, | |
6942 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), | |
6943 | offsetof(CPUARMState, cp15.vbar_ns) }, | |
6944 | .resetvalue = 0 }, | |
6945 | REGINFO_SENTINEL | |
6946 | }; | |
6947 | define_arm_cp_regs(cpu, vbar_cp_reginfo); | |
6948 | } | |
6949 | ||
2771db27 PM |
6950 | /* Generic registers whose values depend on the implementation */ |
6951 | { | |
6952 | ARMCPRegInfo sctlr = { | |
5ebafdf3 | 6953 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, |
137feaa9 FA |
6954 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, |
6955 | .access = PL1_RW, | |
6956 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), | |
6957 | offsetof(CPUARMState, cp15.sctlr_ns) }, | |
d4e6df63 PM |
6958 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, |
6959 | .raw_writefn = raw_write, | |
2771db27 PM |
6960 | }; |
6961 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
6962 | /* Normally we would always end the TB on an SCTLR write, but Linux | |
6963 | * arch/arm/mach-pxa/sleep.S expects two instructions following | |
6964 | * an MMU enable to execute from cache. Imitate this behaviour. | |
6965 | */ | |
6966 | sctlr.type |= ARM_CP_SUPPRESS_TB_END; | |
6967 | } | |
6968 | define_one_arm_cp_reg(cpu, &sctlr); | |
6969 | } | |
5be5e8ed | 6970 | |
2d7137c1 RH |
6971 | if (cpu_isar_feature(aa64_lor, cpu)) { |
6972 | /* | |
6973 | * A trivial implementation of ARMv8.1-LOR leaves all of these | |
6974 | * registers fixed at 0, which indicates that there are zero | |
6975 | * supported Limited Ordering regions. | |
6976 | */ | |
6977 | static const ARMCPRegInfo lor_reginfo[] = { | |
6978 | { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, | |
6979 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, | |
6980 | .access = PL1_RW, .accessfn = access_lor_other, | |
6981 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6982 | { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, | |
6983 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, | |
6984 | .access = PL1_RW, .accessfn = access_lor_other, | |
6985 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6986 | { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, | |
6987 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, | |
6988 | .access = PL1_RW, .accessfn = access_lor_other, | |
6989 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6990 | { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, | |
6991 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, | |
6992 | .access = PL1_RW, .accessfn = access_lor_other, | |
6993 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6994 | { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, | |
6995 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, | |
6996 | .access = PL1_R, .accessfn = access_lorid, | |
6997 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6998 | REGINFO_SENTINEL | |
6999 | }; | |
7000 | define_arm_cp_regs(cpu, lor_reginfo); | |
7001 | } | |
7002 | ||
cd208a1c | 7003 | if (cpu_isar_feature(aa64_sve, cpu)) { |
5be5e8ed RH |
7004 | define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); |
7005 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
7006 | define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); | |
7007 | } else { | |
7008 | define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo); | |
7009 | } | |
7010 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
7011 | define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); | |
7012 | } | |
7013 | } | |
967aa94f RH |
7014 | |
7015 | #ifdef TARGET_AARCH64 | |
7016 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
7017 | define_arm_cp_regs(cpu, pauth_reginfo); | |
7018 | } | |
de390645 RH |
7019 | if (cpu_isar_feature(aa64_rndr, cpu)) { |
7020 | define_arm_cp_regs(cpu, rndr_reginfo); | |
7021 | } | |
967aa94f | 7022 | #endif |
cb570bd3 RH |
7023 | |
7024 | /* | |
7025 | * While all v8.0 cpus support aarch64, QEMU does have configurations | |
7026 | * that do not set ID_AA64ISAR1, e.g. user-only qemu-arm -cpu max, | |
7027 | * which will set ID_ISAR6. | |
7028 | */ | |
7029 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) | |
7030 | ? cpu_isar_feature(aa64_predinv, cpu) | |
7031 | : cpu_isar_feature(aa32_predinv, cpu)) { | |
7032 | define_arm_cp_regs(cpu, predinv_reginfo); | |
7033 | } | |
2ceb98c0 PM |
7034 | } |
7035 | ||
14969266 AF |
7036 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) |
7037 | { | |
22169d41 | 7038 | CPUState *cs = CPU(cpu); |
14969266 AF |
7039 | CPUARMState *env = &cpu->env; |
7040 | ||
6a669427 PM |
7041 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
7042 | gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, | |
7043 | aarch64_fpu_gdb_set_reg, | |
7044 | 34, "aarch64-fpu.xml", 0); | |
7045 | } else if (arm_feature(env, ARM_FEATURE_NEON)) { | |
22169d41 | 7046 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
7047 | 51, "arm-neon.xml", 0); |
7048 | } else if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
22169d41 | 7049 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
7050 | 35, "arm-vfp3.xml", 0); |
7051 | } else if (arm_feature(env, ARM_FEATURE_VFP)) { | |
22169d41 | 7052 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
7053 | 19, "arm-vfp.xml", 0); |
7054 | } | |
200bf5b7 AB |
7055 | gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, |
7056 | arm_gen_dynamic_xml(cs), | |
7057 | "system-registers.xml", 0); | |
40f137e1 PB |
7058 | } |
7059 | ||
777dc784 PM |
7060 | /* Sort alphabetically by type name, except for "any". */ |
7061 | static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) | |
5adb4839 | 7062 | { |
777dc784 PM |
7063 | ObjectClass *class_a = (ObjectClass *)a; |
7064 | ObjectClass *class_b = (ObjectClass *)b; | |
7065 | const char *name_a, *name_b; | |
5adb4839 | 7066 | |
777dc784 PM |
7067 | name_a = object_class_get_name(class_a); |
7068 | name_b = object_class_get_name(class_b); | |
51492fd1 | 7069 | if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 | 7070 | return 1; |
51492fd1 | 7071 | } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 PM |
7072 | return -1; |
7073 | } else { | |
7074 | return strcmp(name_a, name_b); | |
5adb4839 PB |
7075 | } |
7076 | } | |
7077 | ||
777dc784 | 7078 | static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
40f137e1 | 7079 | { |
777dc784 | 7080 | ObjectClass *oc = data; |
51492fd1 AF |
7081 | const char *typename; |
7082 | char *name; | |
3371d272 | 7083 | |
51492fd1 AF |
7084 | typename = object_class_get_name(oc); |
7085 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
0442428a | 7086 | qemu_printf(" %s\n", name); |
51492fd1 | 7087 | g_free(name); |
777dc784 PM |
7088 | } |
7089 | ||
0442428a | 7090 | void arm_cpu_list(void) |
777dc784 | 7091 | { |
777dc784 PM |
7092 | GSList *list; |
7093 | ||
7094 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
7095 | list = g_slist_sort(list, arm_cpu_list_compare); | |
0442428a MA |
7096 | qemu_printf("Available CPUs:\n"); |
7097 | g_slist_foreach(list, arm_cpu_list_entry, NULL); | |
777dc784 | 7098 | g_slist_free(list); |
40f137e1 PB |
7099 | } |
7100 | ||
78027bb6 CR |
7101 | static void arm_cpu_add_definition(gpointer data, gpointer user_data) |
7102 | { | |
7103 | ObjectClass *oc = data; | |
7104 | CpuDefinitionInfoList **cpu_list = user_data; | |
7105 | CpuDefinitionInfoList *entry; | |
7106 | CpuDefinitionInfo *info; | |
7107 | const char *typename; | |
7108 | ||
7109 | typename = object_class_get_name(oc); | |
7110 | info = g_malloc0(sizeof(*info)); | |
7111 | info->name = g_strndup(typename, | |
7112 | strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
8ed877b7 | 7113 | info->q_typename = g_strdup(typename); |
78027bb6 CR |
7114 | |
7115 | entry = g_malloc0(sizeof(*entry)); | |
7116 | entry->value = info; | |
7117 | entry->next = *cpu_list; | |
7118 | *cpu_list = entry; | |
7119 | } | |
7120 | ||
25a9d6ca | 7121 | CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) |
78027bb6 CR |
7122 | { |
7123 | CpuDefinitionInfoList *cpu_list = NULL; | |
7124 | GSList *list; | |
7125 | ||
7126 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
7127 | g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); | |
7128 | g_slist_free(list); | |
7129 | ||
7130 | return cpu_list; | |
7131 | } | |
7132 | ||
6e6efd61 | 7133 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
51a79b03 | 7134 | void *opaque, int state, int secstate, |
9c513e78 AB |
7135 | int crm, int opc1, int opc2, |
7136 | const char *name) | |
6e6efd61 PM |
7137 | { |
7138 | /* Private utility function for define_one_arm_cp_reg_with_opaque(): | |
7139 | * add a single reginfo struct to the hash table. | |
7140 | */ | |
7141 | uint32_t *key = g_new(uint32_t, 1); | |
7142 | ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); | |
7143 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | |
3f3c82a5 FA |
7144 | int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; |
7145 | ||
9c513e78 | 7146 | r2->name = g_strdup(name); |
3f3c82a5 FA |
7147 | /* Reset the secure state to the specific incoming state. This is |
7148 | * necessary as the register may have been defined with both states. | |
7149 | */ | |
7150 | r2->secure = secstate; | |
7151 | ||
7152 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
7153 | /* Register is banked (using both entries in array). | |
7154 | * Overwriting fieldoffset as the array is only used to define | |
7155 | * banked registers but later only fieldoffset is used. | |
f5a0a5a5 | 7156 | */ |
3f3c82a5 FA |
7157 | r2->fieldoffset = r->bank_fieldoffsets[ns]; |
7158 | } | |
7159 | ||
7160 | if (state == ARM_CP_STATE_AA32) { | |
7161 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
7162 | /* If the register is banked then we don't need to migrate or | |
7163 | * reset the 32-bit instance in certain cases: | |
7164 | * | |
7165 | * 1) If the register has both 32-bit and 64-bit instances then we | |
7166 | * can count on the 64-bit instance taking care of the | |
7167 | * non-secure bank. | |
7168 | * 2) If ARMv8 is enabled then we can count on a 64-bit version | |
7169 | * taking care of the secure bank. This requires that separate | |
7170 | * 32 and 64-bit definitions are provided. | |
7171 | */ | |
7172 | if ((r->state == ARM_CP_STATE_BOTH && ns) || | |
7173 | (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { | |
7a0e58fa | 7174 | r2->type |= ARM_CP_ALIAS; |
3f3c82a5 FA |
7175 | } |
7176 | } else if ((secstate != r->secure) && !ns) { | |
7177 | /* The register is not banked so we only want to allow migration of | |
7178 | * the non-secure instance. | |
7179 | */ | |
7a0e58fa | 7180 | r2->type |= ARM_CP_ALIAS; |
58a1d8ce | 7181 | } |
3f3c82a5 FA |
7182 | |
7183 | if (r->state == ARM_CP_STATE_BOTH) { | |
7184 | /* We assume it is a cp15 register if the .cp field is left unset. | |
7185 | */ | |
7186 | if (r2->cp == 0) { | |
7187 | r2->cp = 15; | |
7188 | } | |
7189 | ||
f5a0a5a5 | 7190 | #ifdef HOST_WORDS_BIGENDIAN |
3f3c82a5 FA |
7191 | if (r2->fieldoffset) { |
7192 | r2->fieldoffset += sizeof(uint32_t); | |
7193 | } | |
f5a0a5a5 | 7194 | #endif |
3f3c82a5 | 7195 | } |
f5a0a5a5 PM |
7196 | } |
7197 | if (state == ARM_CP_STATE_AA64) { | |
7198 | /* To allow abbreviation of ARMCPRegInfo | |
7199 | * definitions, we treat cp == 0 as equivalent to | |
7200 | * the value for "standard guest-visible sysreg". | |
58a1d8ce PM |
7201 | * STATE_BOTH definitions are also always "standard |
7202 | * sysreg" in their AArch64 view (the .cp value may | |
7203 | * be non-zero for the benefit of the AArch32 view). | |
f5a0a5a5 | 7204 | */ |
58a1d8ce | 7205 | if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { |
f5a0a5a5 PM |
7206 | r2->cp = CP_REG_ARM64_SYSREG_CP; |
7207 | } | |
7208 | *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | |
7209 | r2->opc0, opc1, opc2); | |
7210 | } else { | |
51a79b03 | 7211 | *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); |
f5a0a5a5 | 7212 | } |
6e6efd61 PM |
7213 | if (opaque) { |
7214 | r2->opaque = opaque; | |
7215 | } | |
67ed771d PM |
7216 | /* reginfo passed to helpers is correct for the actual access, |
7217 | * and is never ARM_CP_STATE_BOTH: | |
7218 | */ | |
7219 | r2->state = state; | |
6e6efd61 PM |
7220 | /* Make sure reginfo passed to helpers for wildcarded regs |
7221 | * has the correct crm/opc1/opc2 for this reg, not CP_ANY: | |
7222 | */ | |
7223 | r2->crm = crm; | |
7224 | r2->opc1 = opc1; | |
7225 | r2->opc2 = opc2; | |
7226 | /* By convention, for wildcarded registers only the first | |
7227 | * entry is used for migration; the others are marked as | |
7a0e58fa | 7228 | * ALIAS so we don't try to transfer the register |
6e6efd61 | 7229 | * multiple times. Special registers (ie NOP/WFI) are |
7a0e58fa | 7230 | * never migratable and not even raw-accessible. |
6e6efd61 | 7231 | */ |
7a0e58fa PM |
7232 | if ((r->type & ARM_CP_SPECIAL)) { |
7233 | r2->type |= ARM_CP_NO_RAW; | |
7234 | } | |
7235 | if (((r->crm == CP_ANY) && crm != 0) || | |
6e6efd61 PM |
7236 | ((r->opc1 == CP_ANY) && opc1 != 0) || |
7237 | ((r->opc2 == CP_ANY) && opc2 != 0)) { | |
1f163787 | 7238 | r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB; |
6e6efd61 PM |
7239 | } |
7240 | ||
375421cc PM |
7241 | /* Check that raw accesses are either forbidden or handled. Note that |
7242 | * we can't assert this earlier because the setup of fieldoffset for | |
7243 | * banked registers has to be done first. | |
7244 | */ | |
7245 | if (!(r2->type & ARM_CP_NO_RAW)) { | |
7246 | assert(!raw_accessors_invalid(r2)); | |
7247 | } | |
7248 | ||
6e6efd61 PM |
7249 | /* Overriding of an existing definition must be explicitly |
7250 | * requested. | |
7251 | */ | |
7252 | if (!(r->type & ARM_CP_OVERRIDE)) { | |
7253 | ARMCPRegInfo *oldreg; | |
7254 | oldreg = g_hash_table_lookup(cpu->cp_regs, key); | |
7255 | if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { | |
7256 | fprintf(stderr, "Register redefined: cp=%d %d bit " | |
7257 | "crn=%d crm=%d opc1=%d opc2=%d, " | |
7258 | "was %s, now %s\n", r2->cp, 32 + 32 * is64, | |
7259 | r2->crn, r2->crm, r2->opc1, r2->opc2, | |
7260 | oldreg->name, r2->name); | |
7261 | g_assert_not_reached(); | |
7262 | } | |
7263 | } | |
7264 | g_hash_table_insert(cpu->cp_regs, key, r2); | |
7265 | } | |
7266 | ||
7267 | ||
4b6a83fb PM |
7268 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
7269 | const ARMCPRegInfo *r, void *opaque) | |
7270 | { | |
7271 | /* Define implementations of coprocessor registers. | |
7272 | * We store these in a hashtable because typically | |
7273 | * there are less than 150 registers in a space which | |
7274 | * is 16*16*16*8*8 = 262144 in size. | |
7275 | * Wildcarding is supported for the crm, opc1 and opc2 fields. | |
7276 | * If a register is defined twice then the second definition is | |
7277 | * used, so this can be used to define some generic registers and | |
7278 | * then override them with implementation specific variations. | |
7279 | * At least one of the original and the second definition should | |
7280 | * include ARM_CP_OVERRIDE in its type bits -- this is just a guard | |
7281 | * against accidental use. | |
f5a0a5a5 PM |
7282 | * |
7283 | * The state field defines whether the register is to be | |
7284 | * visible in the AArch32 or AArch64 execution state. If the | |
7285 | * state is set to ARM_CP_STATE_BOTH then we synthesise a | |
7286 | * reginfo structure for the AArch32 view, which sees the lower | |
7287 | * 32 bits of the 64 bit register. | |
7288 | * | |
7289 | * Only registers visible in AArch64 may set r->opc0; opc0 cannot | |
7290 | * be wildcarded. AArch64 registers are always considered to be 64 | |
7291 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | |
7292 | * the register, if any. | |
4b6a83fb | 7293 | */ |
f5a0a5a5 | 7294 | int crm, opc1, opc2, state; |
4b6a83fb PM |
7295 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
7296 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | |
7297 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | |
7298 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | |
7299 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | |
7300 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | |
7301 | /* 64 bit registers have only CRm and Opc1 fields */ | |
7302 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | |
f5a0a5a5 PM |
7303 | /* op0 only exists in the AArch64 encodings */ |
7304 | assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); | |
7305 | /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ | |
7306 | assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); | |
7307 | /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 | |
7308 | * encodes a minimum access level for the register. We roll this | |
7309 | * runtime check into our general permission check code, so check | |
7310 | * here that the reginfo's specified permissions are strict enough | |
7311 | * to encompass the generic architectural permission check. | |
7312 | */ | |
7313 | if (r->state != ARM_CP_STATE_AA32) { | |
7314 | int mask = 0; | |
7315 | switch (r->opc1) { | |
b5bd7440 AB |
7316 | case 0: |
7317 | /* min_EL EL1, but some accessible to EL0 via kernel ABI */ | |
7318 | mask = PL0U_R | PL1_RW; | |
7319 | break; | |
7320 | case 1: case 2: | |
f5a0a5a5 PM |
7321 | /* min_EL EL1 */ |
7322 | mask = PL1_RW; | |
7323 | break; | |
7324 | case 3: | |
7325 | /* min_EL EL0 */ | |
7326 | mask = PL0_RW; | |
7327 | break; | |
7328 | case 4: | |
7329 | /* min_EL EL2 */ | |
7330 | mask = PL2_RW; | |
7331 | break; | |
7332 | case 5: | |
7333 | /* unallocated encoding, so not possible */ | |
7334 | assert(false); | |
7335 | break; | |
7336 | case 6: | |
7337 | /* min_EL EL3 */ | |
7338 | mask = PL3_RW; | |
7339 | break; | |
7340 | case 7: | |
7341 | /* min_EL EL1, secure mode only (we don't check the latter) */ | |
7342 | mask = PL1_RW; | |
7343 | break; | |
7344 | default: | |
7345 | /* broken reginfo with out-of-range opc1 */ | |
7346 | assert(false); | |
7347 | break; | |
7348 | } | |
7349 | /* assert our permissions are not too lax (stricter is fine) */ | |
7350 | assert((r->access & ~mask) == 0); | |
7351 | } | |
7352 | ||
4b6a83fb PM |
7353 | /* Check that the register definition has enough info to handle |
7354 | * reads and writes if they are permitted. | |
7355 | */ | |
7356 | if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { | |
7357 | if (r->access & PL3_R) { | |
3f3c82a5 FA |
7358 | assert((r->fieldoffset || |
7359 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
7360 | r->readfn); | |
4b6a83fb PM |
7361 | } |
7362 | if (r->access & PL3_W) { | |
3f3c82a5 FA |
7363 | assert((r->fieldoffset || |
7364 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
7365 | r->writefn); | |
4b6a83fb PM |
7366 | } |
7367 | } | |
7368 | /* Bad type field probably means missing sentinel at end of reg list */ | |
7369 | assert(cptype_valid(r->type)); | |
7370 | for (crm = crmmin; crm <= crmmax; crm++) { | |
7371 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | |
7372 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | |
f5a0a5a5 PM |
7373 | for (state = ARM_CP_STATE_AA32; |
7374 | state <= ARM_CP_STATE_AA64; state++) { | |
7375 | if (r->state != state && r->state != ARM_CP_STATE_BOTH) { | |
7376 | continue; | |
7377 | } | |
3f3c82a5 FA |
7378 | if (state == ARM_CP_STATE_AA32) { |
7379 | /* Under AArch32 CP registers can be common | |
7380 | * (same for secure and non-secure world) or banked. | |
7381 | */ | |
9c513e78 AB |
7382 | char *name; |
7383 | ||
3f3c82a5 FA |
7384 | switch (r->secure) { |
7385 | case ARM_CP_SECSTATE_S: | |
7386 | case ARM_CP_SECSTATE_NS: | |
7387 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
9c513e78 AB |
7388 | r->secure, crm, opc1, opc2, |
7389 | r->name); | |
3f3c82a5 FA |
7390 | break; |
7391 | default: | |
9c513e78 | 7392 | name = g_strdup_printf("%s_S", r->name); |
3f3c82a5 FA |
7393 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
7394 | ARM_CP_SECSTATE_S, | |
9c513e78 AB |
7395 | crm, opc1, opc2, name); |
7396 | g_free(name); | |
3f3c82a5 FA |
7397 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
7398 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 7399 | crm, opc1, opc2, r->name); |
3f3c82a5 FA |
7400 | break; |
7401 | } | |
7402 | } else { | |
7403 | /* AArch64 registers get mapped to non-secure instance | |
7404 | * of AArch32 */ | |
7405 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
7406 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 7407 | crm, opc1, opc2, r->name); |
3f3c82a5 | 7408 | } |
f5a0a5a5 | 7409 | } |
4b6a83fb PM |
7410 | } |
7411 | } | |
7412 | } | |
7413 | } | |
7414 | ||
7415 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
7416 | const ARMCPRegInfo *regs, void *opaque) | |
7417 | { | |
7418 | /* Define a whole list of registers */ | |
7419 | const ARMCPRegInfo *r; | |
7420 | for (r = regs; r->type != ARM_CP_SENTINEL; r++) { | |
7421 | define_one_arm_cp_reg_with_opaque(cpu, r, opaque); | |
7422 | } | |
7423 | } | |
7424 | ||
6c5c0fec AB |
7425 | /* |
7426 | * Modify ARMCPRegInfo for access from userspace. | |
7427 | * | |
7428 | * This is a data driven modification directed by | |
7429 | * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as | |
7430 | * user-space cannot alter any values and dynamic values pertaining to | |
7431 | * execution state are hidden from user space view anyway. | |
7432 | */ | |
7433 | void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods) | |
7434 | { | |
7435 | const ARMCPRegUserSpaceInfo *m; | |
7436 | ARMCPRegInfo *r; | |
7437 | ||
7438 | for (m = mods; m->name; m++) { | |
d040242e AB |
7439 | GPatternSpec *pat = NULL; |
7440 | if (m->is_glob) { | |
7441 | pat = g_pattern_spec_new(m->name); | |
7442 | } | |
6c5c0fec | 7443 | for (r = regs; r->type != ARM_CP_SENTINEL; r++) { |
d040242e AB |
7444 | if (pat && g_pattern_match_string(pat, r->name)) { |
7445 | r->type = ARM_CP_CONST; | |
7446 | r->access = PL0U_R; | |
7447 | r->resetvalue = 0; | |
7448 | /* continue */ | |
7449 | } else if (strcmp(r->name, m->name) == 0) { | |
6c5c0fec AB |
7450 | r->type = ARM_CP_CONST; |
7451 | r->access = PL0U_R; | |
7452 | r->resetvalue &= m->exported_bits; | |
7453 | r->resetvalue |= m->fixed_bits; | |
7454 | break; | |
7455 | } | |
7456 | } | |
d040242e AB |
7457 | if (pat) { |
7458 | g_pattern_spec_free(pat); | |
7459 | } | |
6c5c0fec AB |
7460 | } |
7461 | } | |
7462 | ||
60322b39 | 7463 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) |
4b6a83fb | 7464 | { |
60322b39 | 7465 | return g_hash_table_lookup(cpregs, &encoded_cp); |
4b6a83fb PM |
7466 | } |
7467 | ||
c4241c7d PM |
7468 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
7469 | uint64_t value) | |
4b6a83fb PM |
7470 | { |
7471 | /* Helper coprocessor write function for write-ignore registers */ | |
4b6a83fb PM |
7472 | } |
7473 | ||
c4241c7d | 7474 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) |
4b6a83fb PM |
7475 | { |
7476 | /* Helper coprocessor write function for read-as-zero registers */ | |
4b6a83fb PM |
7477 | return 0; |
7478 | } | |
7479 | ||
f5a0a5a5 PM |
7480 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) |
7481 | { | |
7482 | /* Helper coprocessor reset function for do-nothing-on-reset registers */ | |
7483 | } | |
7484 | ||
af393ffc | 7485 | static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) |
37064a8b PM |
7486 | { |
7487 | /* Return true if it is not valid for us to switch to | |
7488 | * this CPU mode (ie all the UNPREDICTABLE cases in | |
7489 | * the ARM ARM CPSRWriteByInstr pseudocode). | |
7490 | */ | |
af393ffc PM |
7491 | |
7492 | /* Changes to or from Hyp via MSR and CPS are illegal. */ | |
7493 | if (write_type == CPSRWriteByInstr && | |
7494 | ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || | |
7495 | mode == ARM_CPU_MODE_HYP)) { | |
7496 | return 1; | |
7497 | } | |
7498 | ||
37064a8b PM |
7499 | switch (mode) { |
7500 | case ARM_CPU_MODE_USR: | |
10eacda7 | 7501 | return 0; |
37064a8b PM |
7502 | case ARM_CPU_MODE_SYS: |
7503 | case ARM_CPU_MODE_SVC: | |
7504 | case ARM_CPU_MODE_ABT: | |
7505 | case ARM_CPU_MODE_UND: | |
7506 | case ARM_CPU_MODE_IRQ: | |
7507 | case ARM_CPU_MODE_FIQ: | |
52ff951b PM |
7508 | /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 |
7509 | * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) | |
7510 | */ | |
10eacda7 PM |
7511 | /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR |
7512 | * and CPS are treated as illegal mode changes. | |
7513 | */ | |
7514 | if (write_type == CPSRWriteByInstr && | |
10eacda7 | 7515 | (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && |
7c208e0f | 7516 | (arm_hcr_el2_eff(env) & HCR_TGE)) { |
10eacda7 PM |
7517 | return 1; |
7518 | } | |
37064a8b | 7519 | return 0; |
e6c8fc07 PM |
7520 | case ARM_CPU_MODE_HYP: |
7521 | return !arm_feature(env, ARM_FEATURE_EL2) | |
2d2a4549 | 7522 | || arm_current_el(env) < 2 || arm_is_secure_below_el3(env); |
027fc527 | 7523 | case ARM_CPU_MODE_MON: |
58ae2d1f | 7524 | return arm_current_el(env) < 3; |
37064a8b PM |
7525 | default: |
7526 | return 1; | |
7527 | } | |
7528 | } | |
7529 | ||
2f4a40e5 AZ |
7530 | uint32_t cpsr_read(CPUARMState *env) |
7531 | { | |
7532 | int ZF; | |
6fbe23d5 PB |
7533 | ZF = (env->ZF == 0); |
7534 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
7535 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
7536 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
7537 | | ((env->condexec_bits & 0xfc) << 8) | |
af519934 | 7538 | | (env->GE << 16) | (env->daif & CPSR_AIF); |
2f4a40e5 AZ |
7539 | } |
7540 | ||
50866ba5 PM |
7541 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, |
7542 | CPSRWriteType write_type) | |
2f4a40e5 | 7543 | { |
6e8801f9 FA |
7544 | uint32_t changed_daif; |
7545 | ||
2f4a40e5 | 7546 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
7547 | env->ZF = (~val) & CPSR_Z; |
7548 | env->NF = val; | |
2f4a40e5 AZ |
7549 | env->CF = (val >> 29) & 1; |
7550 | env->VF = (val << 3) & 0x80000000; | |
7551 | } | |
7552 | if (mask & CPSR_Q) | |
7553 | env->QF = ((val & CPSR_Q) != 0); | |
7554 | if (mask & CPSR_T) | |
7555 | env->thumb = ((val & CPSR_T) != 0); | |
7556 | if (mask & CPSR_IT_0_1) { | |
7557 | env->condexec_bits &= ~3; | |
7558 | env->condexec_bits |= (val >> 25) & 3; | |
7559 | } | |
7560 | if (mask & CPSR_IT_2_7) { | |
7561 | env->condexec_bits &= 3; | |
7562 | env->condexec_bits |= (val >> 8) & 0xfc; | |
7563 | } | |
7564 | if (mask & CPSR_GE) { | |
7565 | env->GE = (val >> 16) & 0xf; | |
7566 | } | |
7567 | ||
6e8801f9 FA |
7568 | /* In a V7 implementation that includes the security extensions but does |
7569 | * not include Virtualization Extensions the SCR.FW and SCR.AW bits control | |
7570 | * whether non-secure software is allowed to change the CPSR_F and CPSR_A | |
7571 | * bits respectively. | |
7572 | * | |
7573 | * In a V8 implementation, it is permitted for privileged software to | |
7574 | * change the CPSR A/F bits regardless of the SCR.AW/FW bits. | |
7575 | */ | |
f8c88bbc | 7576 | if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && |
6e8801f9 FA |
7577 | arm_feature(env, ARM_FEATURE_EL3) && |
7578 | !arm_feature(env, ARM_FEATURE_EL2) && | |
7579 | !arm_is_secure(env)) { | |
7580 | ||
7581 | changed_daif = (env->daif ^ val) & mask; | |
7582 | ||
7583 | if (changed_daif & CPSR_A) { | |
7584 | /* Check to see if we are allowed to change the masking of async | |
7585 | * abort exceptions from a non-secure state. | |
7586 | */ | |
7587 | if (!(env->cp15.scr_el3 & SCR_AW)) { | |
7588 | qemu_log_mask(LOG_GUEST_ERROR, | |
7589 | "Ignoring attempt to switch CPSR_A flag from " | |
7590 | "non-secure world with SCR.AW bit clear\n"); | |
7591 | mask &= ~CPSR_A; | |
7592 | } | |
7593 | } | |
7594 | ||
7595 | if (changed_daif & CPSR_F) { | |
7596 | /* Check to see if we are allowed to change the masking of FIQ | |
7597 | * exceptions from a non-secure state. | |
7598 | */ | |
7599 | if (!(env->cp15.scr_el3 & SCR_FW)) { | |
7600 | qemu_log_mask(LOG_GUEST_ERROR, | |
7601 | "Ignoring attempt to switch CPSR_F flag from " | |
7602 | "non-secure world with SCR.FW bit clear\n"); | |
7603 | mask &= ~CPSR_F; | |
7604 | } | |
7605 | ||
7606 | /* Check whether non-maskable FIQ (NMFI) support is enabled. | |
7607 | * If this bit is set software is not allowed to mask | |
7608 | * FIQs, but is allowed to set CPSR_F to 0. | |
7609 | */ | |
7610 | if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && | |
7611 | (val & CPSR_F)) { | |
7612 | qemu_log_mask(LOG_GUEST_ERROR, | |
7613 | "Ignoring attempt to enable CPSR_F flag " | |
7614 | "(non-maskable FIQ [NMFI] support enabled)\n"); | |
7615 | mask &= ~CPSR_F; | |
7616 | } | |
7617 | } | |
7618 | } | |
7619 | ||
4cc35614 PM |
7620 | env->daif &= ~(CPSR_AIF & mask); |
7621 | env->daif |= val & CPSR_AIF & mask; | |
7622 | ||
f8c88bbc PM |
7623 | if (write_type != CPSRWriteRaw && |
7624 | ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { | |
8c4f0eb9 PM |
7625 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { |
7626 | /* Note that we can only get here in USR mode if this is a | |
7627 | * gdb stub write; for this case we follow the architectural | |
7628 | * behaviour for guest writes in USR mode of ignoring an attempt | |
7629 | * to switch mode. (Those are caught by translate.c for writes | |
7630 | * triggered by guest instructions.) | |
7631 | */ | |
7632 | mask &= ~CPSR_M; | |
7633 | } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { | |
81907a58 PM |
7634 | /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in |
7635 | * v7, and has defined behaviour in v8: | |
7636 | * + leave CPSR.M untouched | |
7637 | * + allow changes to the other CPSR fields | |
7638 | * + set PSTATE.IL | |
7639 | * For user changes via the GDB stub, we don't set PSTATE.IL, | |
7640 | * as this would be unnecessarily harsh for a user error. | |
37064a8b PM |
7641 | */ |
7642 | mask &= ~CPSR_M; | |
81907a58 PM |
7643 | if (write_type != CPSRWriteByGDBStub && |
7644 | arm_feature(env, ARM_FEATURE_V8)) { | |
7645 | mask |= CPSR_IL; | |
7646 | val |= CPSR_IL; | |
7647 | } | |
81e37284 PM |
7648 | qemu_log_mask(LOG_GUEST_ERROR, |
7649 | "Illegal AArch32 mode switch attempt from %s to %s\n", | |
7650 | aarch32_mode_name(env->uncached_cpsr), | |
7651 | aarch32_mode_name(val)); | |
37064a8b | 7652 | } else { |
81e37284 PM |
7653 | qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n", |
7654 | write_type == CPSRWriteExceptionReturn ? | |
7655 | "Exception return from AArch32" : | |
7656 | "AArch32 mode switch from", | |
7657 | aarch32_mode_name(env->uncached_cpsr), | |
7658 | aarch32_mode_name(val), env->regs[15]); | |
37064a8b PM |
7659 | switch_mode(env, val & CPSR_M); |
7660 | } | |
2f4a40e5 AZ |
7661 | } |
7662 | mask &= ~CACHED_CPSR_BITS; | |
7663 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
7664 | } | |
7665 | ||
b26eefb6 PB |
7666 | /* Sign/zero extend */ |
7667 | uint32_t HELPER(sxtb16)(uint32_t x) | |
7668 | { | |
7669 | uint32_t res; | |
7670 | res = (uint16_t)(int8_t)x; | |
7671 | res |= (uint32_t)(int8_t)(x >> 16) << 16; | |
7672 | return res; | |
7673 | } | |
7674 | ||
7675 | uint32_t HELPER(uxtb16)(uint32_t x) | |
7676 | { | |
7677 | uint32_t res; | |
7678 | res = (uint16_t)(uint8_t)x; | |
7679 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; | |
7680 | return res; | |
7681 | } | |
7682 | ||
3670669c PB |
7683 | int32_t HELPER(sdiv)(int32_t num, int32_t den) |
7684 | { | |
7685 | if (den == 0) | |
7686 | return 0; | |
686eeb93 AJ |
7687 | if (num == INT_MIN && den == -1) |
7688 | return INT_MIN; | |
3670669c PB |
7689 | return num / den; |
7690 | } | |
7691 | ||
7692 | uint32_t HELPER(udiv)(uint32_t num, uint32_t den) | |
7693 | { | |
7694 | if (den == 0) | |
7695 | return 0; | |
7696 | return num / den; | |
7697 | } | |
7698 | ||
7699 | uint32_t HELPER(rbit)(uint32_t x) | |
7700 | { | |
42fedbca | 7701 | return revbit32(x); |
3670669c PB |
7702 | } |
7703 | ||
c47eaf9f | 7704 | #ifdef CONFIG_USER_ONLY |
b5ff1b31 | 7705 | |
affdb64d | 7706 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 | 7707 | { |
2fc0cc0e | 7708 | ARMCPU *cpu = env_archcpu(env); |
a47dddd7 AF |
7709 | |
7710 | if (mode != ARM_CPU_MODE_USR) { | |
7711 | cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); | |
7712 | } | |
b5ff1b31 FB |
7713 | } |
7714 | ||
012a906b GB |
7715 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
7716 | uint32_t cur_el, bool secure) | |
9e729b57 EI |
7717 | { |
7718 | return 1; | |
7719 | } | |
7720 | ||
ce02049d GB |
7721 | void aarch64_sync_64_to_32(CPUARMState *env) |
7722 | { | |
7723 | g_assert_not_reached(); | |
7724 | } | |
7725 | ||
b5ff1b31 FB |
7726 | #else |
7727 | ||
affdb64d | 7728 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
7729 | { |
7730 | int old_mode; | |
7731 | int i; | |
7732 | ||
7733 | old_mode = env->uncached_cpsr & CPSR_M; | |
7734 | if (mode == old_mode) | |
7735 | return; | |
7736 | ||
7737 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
7738 | memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 7739 | memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
7740 | } else if (mode == ARM_CPU_MODE_FIQ) { |
7741 | memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 7742 | memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
7743 | } |
7744 | ||
f5206413 | 7745 | i = bank_number(old_mode); |
b5ff1b31 | 7746 | env->banked_r13[i] = env->regs[13]; |
b5ff1b31 FB |
7747 | env->banked_spsr[i] = env->spsr; |
7748 | ||
f5206413 | 7749 | i = bank_number(mode); |
b5ff1b31 | 7750 | env->regs[13] = env->banked_r13[i]; |
b5ff1b31 | 7751 | env->spsr = env->banked_spsr[i]; |
593cfa2b PM |
7752 | |
7753 | env->banked_r14[r14_bank_number(old_mode)] = env->regs[14]; | |
7754 | env->regs[14] = env->banked_r14[r14_bank_number(mode)]; | |
b5ff1b31 FB |
7755 | } |
7756 | ||
0eeb17d6 GB |
7757 | /* Physical Interrupt Target EL Lookup Table |
7758 | * | |
7759 | * [ From ARM ARM section G1.13.4 (Table G1-15) ] | |
7760 | * | |
7761 | * The below multi-dimensional table is used for looking up the target | |
7762 | * exception level given numerous condition criteria. Specifically, the | |
7763 | * target EL is based on SCR and HCR routing controls as well as the | |
7764 | * currently executing EL and secure state. | |
7765 | * | |
7766 | * Dimensions: | |
7767 | * target_el_table[2][2][2][2][2][4] | |
7768 | * | | | | | +--- Current EL | |
7769 | * | | | | +------ Non-secure(0)/Secure(1) | |
7770 | * | | | +--------- HCR mask override | |
7771 | * | | +------------ SCR exec state control | |
7772 | * | +--------------- SCR mask override | |
7773 | * +------------------ 32-bit(0)/64-bit(1) EL3 | |
7774 | * | |
7775 | * The table values are as such: | |
7776 | * 0-3 = EL0-EL3 | |
7777 | * -1 = Cannot occur | |
7778 | * | |
7779 | * The ARM ARM target EL table includes entries indicating that an "exception | |
7780 | * is not taken". The two cases where this is applicable are: | |
7781 | * 1) An exception is taken from EL3 but the SCR does not have the exception | |
7782 | * routed to EL3. | |
7783 | * 2) An exception is taken from EL2 but the HCR does not have the exception | |
7784 | * routed to EL2. | |
7785 | * In these two cases, the below table contain a target of EL1. This value is | |
7786 | * returned as it is expected that the consumer of the table data will check | |
7787 | * for "target EL >= current EL" to ensure the exception is not taken. | |
7788 | * | |
7789 | * SCR HCR | |
7790 | * 64 EA AMO From | |
7791 | * BIT IRQ IMO Non-secure Secure | |
7792 | * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 | |
7793 | */ | |
82c39f6a | 7794 | static const int8_t target_el_table[2][2][2][2][2][4] = { |
0eeb17d6 GB |
7795 | {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, |
7796 | {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, | |
7797 | {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, | |
7798 | {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, | |
7799 | {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
7800 | {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, | |
7801 | {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
7802 | {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, | |
7803 | {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, | |
7804 | {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},}, | |
7805 | {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },}, | |
7806 | {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},}, | |
7807 | {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, | |
7808 | {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, | |
7809 | {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, | |
7810 | {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},}, | |
7811 | }; | |
7812 | ||
7813 | /* | |
7814 | * Determine the target EL for physical exceptions | |
7815 | */ | |
012a906b GB |
7816 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
7817 | uint32_t cur_el, bool secure) | |
0eeb17d6 GB |
7818 | { |
7819 | CPUARMState *env = cs->env_ptr; | |
f7778444 RH |
7820 | bool rw; |
7821 | bool scr; | |
7822 | bool hcr; | |
0eeb17d6 | 7823 | int target_el; |
2cde031f | 7824 | /* Is the highest EL AArch64? */ |
f7778444 RH |
7825 | bool is64 = arm_feature(env, ARM_FEATURE_AARCH64); |
7826 | uint64_t hcr_el2; | |
2cde031f SS |
7827 | |
7828 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
7829 | rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); | |
7830 | } else { | |
7831 | /* Either EL2 is the highest EL (and so the EL2 register width | |
7832 | * is given by is64); or there is no EL2 or EL3, in which case | |
7833 | * the value of 'rw' does not affect the table lookup anyway. | |
7834 | */ | |
7835 | rw = is64; | |
7836 | } | |
0eeb17d6 | 7837 | |
f7778444 | 7838 | hcr_el2 = arm_hcr_el2_eff(env); |
0eeb17d6 GB |
7839 | switch (excp_idx) { |
7840 | case EXCP_IRQ: | |
7841 | scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); | |
f7778444 | 7842 | hcr = hcr_el2 & HCR_IMO; |
0eeb17d6 GB |
7843 | break; |
7844 | case EXCP_FIQ: | |
7845 | scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); | |
f7778444 | 7846 | hcr = hcr_el2 & HCR_FMO; |
0eeb17d6 GB |
7847 | break; |
7848 | default: | |
7849 | scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); | |
f7778444 | 7850 | hcr = hcr_el2 & HCR_AMO; |
0eeb17d6 GB |
7851 | break; |
7852 | }; | |
7853 | ||
0eeb17d6 GB |
7854 | /* Perform a table-lookup for the target EL given the current state */ |
7855 | target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; | |
7856 | ||
7857 | assert(target_el > 0); | |
7858 | ||
7859 | return target_el; | |
7860 | } | |
7861 | ||
b59f479b PMD |
7862 | void arm_log_exception(int idx) |
7863 | { | |
7864 | if (qemu_loglevel_mask(CPU_LOG_INT)) { | |
7865 | const char *exc = NULL; | |
7866 | static const char * const excnames[] = { | |
7867 | [EXCP_UDEF] = "Undefined Instruction", | |
7868 | [EXCP_SWI] = "SVC", | |
7869 | [EXCP_PREFETCH_ABORT] = "Prefetch Abort", | |
7870 | [EXCP_DATA_ABORT] = "Data Abort", | |
7871 | [EXCP_IRQ] = "IRQ", | |
7872 | [EXCP_FIQ] = "FIQ", | |
7873 | [EXCP_BKPT] = "Breakpoint", | |
7874 | [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", | |
7875 | [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", | |
7876 | [EXCP_HVC] = "Hypervisor Call", | |
7877 | [EXCP_HYP_TRAP] = "Hypervisor Trap", | |
7878 | [EXCP_SMC] = "Secure Monitor Call", | |
7879 | [EXCP_VIRQ] = "Virtual IRQ", | |
7880 | [EXCP_VFIQ] = "Virtual FIQ", | |
7881 | [EXCP_SEMIHOST] = "Semihosting call", | |
7882 | [EXCP_NOCP] = "v7M NOCP UsageFault", | |
7883 | [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", | |
7884 | [EXCP_STKOF] = "v8M STKOF UsageFault", | |
7885 | [EXCP_LAZYFP] = "v7M exception during lazy FP stacking", | |
7886 | [EXCP_LSERR] = "v8M LSERR UsageFault", | |
7887 | [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", | |
7888 | }; | |
7889 | ||
7890 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | |
7891 | exc = excnames[idx]; | |
7892 | } | |
7893 | if (!exc) { | |
7894 | exc = "unknown"; | |
7895 | } | |
7896 | qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); | |
7897 | } | |
7898 | } | |
7899 | ||
a356dacf | 7900 | /* |
7aab5a8c PMD |
7901 | * Function used to synchronize QEMU's AArch64 register set with AArch32 |
7902 | * register set. This is necessary when switching between AArch32 and AArch64 | |
7903 | * execution state. | |
a356dacf | 7904 | */ |
7aab5a8c | 7905 | void aarch64_sync_32_to_64(CPUARMState *env) |
9ee6e8bb | 7906 | { |
7aab5a8c PMD |
7907 | int i; |
7908 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
7909 | ||
7910 | /* We can blanket copy R[0:7] to X[0:7] */ | |
7911 | for (i = 0; i < 8; i++) { | |
7912 | env->xregs[i] = env->regs[i]; | |
fd592d89 | 7913 | } |
70d74660 | 7914 | |
9a223097 | 7915 | /* |
7aab5a8c PMD |
7916 | * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. |
7917 | * Otherwise, they come from the banked user regs. | |
fd592d89 | 7918 | */ |
7aab5a8c PMD |
7919 | if (mode == ARM_CPU_MODE_FIQ) { |
7920 | for (i = 8; i < 13; i++) { | |
7921 | env->xregs[i] = env->usr_regs[i - 8]; | |
7922 | } | |
7923 | } else { | |
7924 | for (i = 8; i < 13; i++) { | |
7925 | env->xregs[i] = env->regs[i]; | |
7926 | } | |
fd592d89 | 7927 | } |
9ee6e8bb | 7928 | |
7aab5a8c PMD |
7929 | /* |
7930 | * Registers x13-x23 are the various mode SP and FP registers. Registers | |
7931 | * r13 and r14 are only copied if we are in that mode, otherwise we copy | |
7932 | * from the mode banked register. | |
7933 | */ | |
7934 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { | |
7935 | env->xregs[13] = env->regs[13]; | |
7936 | env->xregs[14] = env->regs[14]; | |
7937 | } else { | |
7938 | env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; | |
7939 | /* HYP is an exception in that it is copied from r14 */ | |
7940 | if (mode == ARM_CPU_MODE_HYP) { | |
7941 | env->xregs[14] = env->regs[14]; | |
95695eff | 7942 | } else { |
7aab5a8c | 7943 | env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)]; |
95695eff | 7944 | } |
95695eff PM |
7945 | } |
7946 | ||
7aab5a8c PMD |
7947 | if (mode == ARM_CPU_MODE_HYP) { |
7948 | env->xregs[15] = env->regs[13]; | |
7949 | } else { | |
7950 | env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; | |
95695eff PM |
7951 | } |
7952 | ||
7aab5a8c PMD |
7953 | if (mode == ARM_CPU_MODE_IRQ) { |
7954 | env->xregs[16] = env->regs[14]; | |
7955 | env->xregs[17] = env->regs[13]; | |
7956 | } else { | |
7957 | env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)]; | |
7958 | env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; | |
7959 | } | |
95695eff | 7960 | |
7aab5a8c PMD |
7961 | if (mode == ARM_CPU_MODE_SVC) { |
7962 | env->xregs[18] = env->regs[14]; | |
7963 | env->xregs[19] = env->regs[13]; | |
7964 | } else { | |
7965 | env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)]; | |
7966 | env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; | |
7967 | } | |
95695eff | 7968 | |
7aab5a8c PMD |
7969 | if (mode == ARM_CPU_MODE_ABT) { |
7970 | env->xregs[20] = env->regs[14]; | |
7971 | env->xregs[21] = env->regs[13]; | |
7972 | } else { | |
7973 | env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)]; | |
7974 | env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; | |
7975 | } | |
e33cf0f8 | 7976 | |
7aab5a8c PMD |
7977 | if (mode == ARM_CPU_MODE_UND) { |
7978 | env->xregs[22] = env->regs[14]; | |
7979 | env->xregs[23] = env->regs[13]; | |
7980 | } else { | |
7981 | env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)]; | |
7982 | env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; | |
e33cf0f8 PM |
7983 | } |
7984 | ||
7985 | /* | |
7aab5a8c PMD |
7986 | * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ |
7987 | * mode, then we can copy from r8-r14. Otherwise, we copy from the | |
7988 | * FIQ bank for r8-r14. | |
e33cf0f8 | 7989 | */ |
7aab5a8c PMD |
7990 | if (mode == ARM_CPU_MODE_FIQ) { |
7991 | for (i = 24; i < 31; i++) { | |
7992 | env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ | |
7993 | } | |
7994 | } else { | |
7995 | for (i = 24; i < 29; i++) { | |
7996 | env->xregs[i] = env->fiq_regs[i - 24]; | |
e33cf0f8 | 7997 | } |
7aab5a8c PMD |
7998 | env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; |
7999 | env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)]; | |
e33cf0f8 | 8000 | } |
7aab5a8c PMD |
8001 | |
8002 | env->pc = env->regs[15]; | |
e33cf0f8 PM |
8003 | } |
8004 | ||
9a223097 | 8005 | /* |
7aab5a8c PMD |
8006 | * Function used to synchronize QEMU's AArch32 register set with AArch64 |
8007 | * register set. This is necessary when switching between AArch32 and AArch64 | |
8008 | * execution state. | |
de2db7ec | 8009 | */ |
7aab5a8c | 8010 | void aarch64_sync_64_to_32(CPUARMState *env) |
9ee6e8bb | 8011 | { |
7aab5a8c PMD |
8012 | int i; |
8013 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
abc24d86 | 8014 | |
7aab5a8c PMD |
8015 | /* We can blanket copy X[0:7] to R[0:7] */ |
8016 | for (i = 0; i < 8; i++) { | |
8017 | env->regs[i] = env->xregs[i]; | |
de2db7ec | 8018 | } |
3f0cddee | 8019 | |
9a223097 | 8020 | /* |
7aab5a8c PMD |
8021 | * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. |
8022 | * Otherwise, we copy x8-x12 into the banked user regs. | |
de2db7ec | 8023 | */ |
7aab5a8c PMD |
8024 | if (mode == ARM_CPU_MODE_FIQ) { |
8025 | for (i = 8; i < 13; i++) { | |
8026 | env->usr_regs[i - 8] = env->xregs[i]; | |
8027 | } | |
8028 | } else { | |
8029 | for (i = 8; i < 13; i++) { | |
8030 | env->regs[i] = env->xregs[i]; | |
8031 | } | |
fb602cb7 PM |
8032 | } |
8033 | ||
9a223097 | 8034 | /* |
7aab5a8c PMD |
8035 | * Registers r13 & r14 depend on the current mode. |
8036 | * If we are in a given mode, we copy the corresponding x registers to r13 | |
8037 | * and r14. Otherwise, we copy the x register to the banked r13 and r14 | |
8038 | * for the mode. | |
fb602cb7 | 8039 | */ |
7aab5a8c PMD |
8040 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { |
8041 | env->regs[13] = env->xregs[13]; | |
8042 | env->regs[14] = env->xregs[14]; | |
fb602cb7 | 8043 | } else { |
7aab5a8c | 8044 | env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; |
fb602cb7 | 8045 | |
7aab5a8c PMD |
8046 | /* |
8047 | * HYP is an exception in that it does not have its own banked r14 but | |
8048 | * shares the USR r14 | |
8049 | */ | |
8050 | if (mode == ARM_CPU_MODE_HYP) { | |
8051 | env->regs[14] = env->xregs[14]; | |
8052 | } else { | |
8053 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; | |
8054 | } | |
8055 | } | |
fb602cb7 | 8056 | |
7aab5a8c PMD |
8057 | if (mode == ARM_CPU_MODE_HYP) { |
8058 | env->regs[13] = env->xregs[15]; | |
fb602cb7 | 8059 | } else { |
7aab5a8c | 8060 | env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; |
fb602cb7 | 8061 | } |
d02a8698 | 8062 | |
7aab5a8c PMD |
8063 | if (mode == ARM_CPU_MODE_IRQ) { |
8064 | env->regs[14] = env->xregs[16]; | |
8065 | env->regs[13] = env->xregs[17]; | |
d02a8698 | 8066 | } else { |
7aab5a8c PMD |
8067 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; |
8068 | env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; | |
d02a8698 PM |
8069 | } |
8070 | ||
7aab5a8c PMD |
8071 | if (mode == ARM_CPU_MODE_SVC) { |
8072 | env->regs[14] = env->xregs[18]; | |
8073 | env->regs[13] = env->xregs[19]; | |
8074 | } else { | |
8075 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; | |
8076 | env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; | |
fb602cb7 PM |
8077 | } |
8078 | ||
7aab5a8c PMD |
8079 | if (mode == ARM_CPU_MODE_ABT) { |
8080 | env->regs[14] = env->xregs[20]; | |
8081 | env->regs[13] = env->xregs[21]; | |
8082 | } else { | |
8083 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; | |
8084 | env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; | |
ce02049d GB |
8085 | } |
8086 | ||
8087 | if (mode == ARM_CPU_MODE_UND) { | |
3a9148d0 SS |
8088 | env->regs[14] = env->xregs[22]; |
8089 | env->regs[13] = env->xregs[23]; | |
ce02049d | 8090 | } else { |
593cfa2b | 8091 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; |
3a9148d0 | 8092 | env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; |
ce02049d GB |
8093 | } |
8094 | ||
8095 | /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ | |
8096 | * mode, then we can copy to r8-r14. Otherwise, we copy to the | |
8097 | * FIQ bank for r8-r14. | |
8098 | */ | |
8099 | if (mode == ARM_CPU_MODE_FIQ) { | |
8100 | for (i = 24; i < 31; i++) { | |
8101 | env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ | |
8102 | } | |
8103 | } else { | |
8104 | for (i = 24; i < 29; i++) { | |
8105 | env->fiq_regs[i - 24] = env->xregs[i]; | |
8106 | } | |
8107 | env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; | |
593cfa2b | 8108 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; |
ce02049d GB |
8109 | } |
8110 | ||
8111 | env->regs[15] = env->pc; | |
8112 | } | |
8113 | ||
dea8378b PM |
8114 | static void take_aarch32_exception(CPUARMState *env, int new_mode, |
8115 | uint32_t mask, uint32_t offset, | |
8116 | uint32_t newpc) | |
8117 | { | |
8118 | /* Change the CPU state so as to actually take the exception. */ | |
8119 | switch_mode(env, new_mode); | |
8120 | /* | |
8121 | * For exceptions taken to AArch32 we must clear the SS bit in both | |
8122 | * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. | |
8123 | */ | |
8124 | env->uncached_cpsr &= ~PSTATE_SS; | |
8125 | env->spsr = cpsr_read(env); | |
8126 | /* Clear IT bits. */ | |
8127 | env->condexec_bits = 0; | |
8128 | /* Switch to the new mode, and to the correct instruction set. */ | |
8129 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; | |
8130 | /* Set new mode endianness */ | |
8131 | env->uncached_cpsr &= ~CPSR_E; | |
8132 | if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { | |
8133 | env->uncached_cpsr |= CPSR_E; | |
8134 | } | |
829f9fd3 PM |
8135 | /* J and IL must always be cleared for exception entry */ |
8136 | env->uncached_cpsr &= ~(CPSR_IL | CPSR_J); | |
dea8378b PM |
8137 | env->daif |= mask; |
8138 | ||
8139 | if (new_mode == ARM_CPU_MODE_HYP) { | |
8140 | env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0; | |
8141 | env->elr_el[2] = env->regs[15]; | |
8142 | } else { | |
8143 | /* | |
8144 | * this is a lie, as there was no c1_sys on V4T/V5, but who cares | |
8145 | * and we should just guard the thumb mode on V4 | |
8146 | */ | |
8147 | if (arm_feature(env, ARM_FEATURE_V4T)) { | |
8148 | env->thumb = | |
8149 | (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; | |
8150 | } | |
8151 | env->regs[14] = env->regs[15] + offset; | |
8152 | } | |
8153 | env->regs[15] = newpc; | |
a8a79c7a | 8154 | arm_rebuild_hflags(env); |
dea8378b PM |
8155 | } |
8156 | ||
b9bc21ff PM |
8157 | static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) |
8158 | { | |
8159 | /* | |
8160 | * Handle exception entry to Hyp mode; this is sufficiently | |
8161 | * different to entry to other AArch32 modes that we handle it | |
8162 | * separately here. | |
8163 | * | |
8164 | * The vector table entry used is always the 0x14 Hyp mode entry point, | |
8165 | * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp. | |
8166 | * The offset applied to the preferred return address is always zero | |
8167 | * (see DDI0487C.a section G1.12.3). | |
8168 | * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. | |
8169 | */ | |
8170 | uint32_t addr, mask; | |
8171 | ARMCPU *cpu = ARM_CPU(cs); | |
8172 | CPUARMState *env = &cpu->env; | |
8173 | ||
8174 | switch (cs->exception_index) { | |
8175 | case EXCP_UDEF: | |
8176 | addr = 0x04; | |
8177 | break; | |
8178 | case EXCP_SWI: | |
8179 | addr = 0x14; | |
8180 | break; | |
8181 | case EXCP_BKPT: | |
8182 | /* Fall through to prefetch abort. */ | |
8183 | case EXCP_PREFETCH_ABORT: | |
8184 | env->cp15.ifar_s = env->exception.vaddress; | |
8185 | qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n", | |
8186 | (uint32_t)env->exception.vaddress); | |
8187 | addr = 0x0c; | |
8188 | break; | |
8189 | case EXCP_DATA_ABORT: | |
8190 | env->cp15.dfar_s = env->exception.vaddress; | |
8191 | qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n", | |
8192 | (uint32_t)env->exception.vaddress); | |
8193 | addr = 0x10; | |
8194 | break; | |
8195 | case EXCP_IRQ: | |
8196 | addr = 0x18; | |
8197 | break; | |
8198 | case EXCP_FIQ: | |
8199 | addr = 0x1c; | |
8200 | break; | |
8201 | case EXCP_HVC: | |
8202 | addr = 0x08; | |
8203 | break; | |
8204 | case EXCP_HYP_TRAP: | |
8205 | addr = 0x14; | |
9bbb4ef9 | 8206 | break; |
b9bc21ff PM |
8207 | default: |
8208 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
8209 | } | |
8210 | ||
8211 | if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) { | |
2ed08180 PM |
8212 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
8213 | /* | |
8214 | * QEMU syndrome values are v8-style. v7 has the IL bit | |
8215 | * UNK/SBZP for "field not valid" cases, where v8 uses RES1. | |
8216 | * If this is a v7 CPU, squash the IL bit in those cases. | |
8217 | */ | |
8218 | if (cs->exception_index == EXCP_PREFETCH_ABORT || | |
8219 | (cs->exception_index == EXCP_DATA_ABORT && | |
8220 | !(env->exception.syndrome & ARM_EL_ISV)) || | |
8221 | syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) { | |
8222 | env->exception.syndrome &= ~ARM_EL_IL; | |
8223 | } | |
8224 | } | |
b9bc21ff PM |
8225 | env->cp15.esr_el[2] = env->exception.syndrome; |
8226 | } | |
8227 | ||
8228 | if (arm_current_el(env) != 2 && addr < 0x14) { | |
8229 | addr = 0x14; | |
8230 | } | |
8231 | ||
8232 | mask = 0; | |
8233 | if (!(env->cp15.scr_el3 & SCR_EA)) { | |
8234 | mask |= CPSR_A; | |
8235 | } | |
8236 | if (!(env->cp15.scr_el3 & SCR_IRQ)) { | |
8237 | mask |= CPSR_I; | |
8238 | } | |
8239 | if (!(env->cp15.scr_el3 & SCR_FIQ)) { | |
8240 | mask |= CPSR_F; | |
8241 | } | |
8242 | ||
8243 | addr += env->cp15.hvbar; | |
8244 | ||
8245 | take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr); | |
8246 | } | |
8247 | ||
966f758c | 8248 | static void arm_cpu_do_interrupt_aarch32(CPUState *cs) |
b5ff1b31 | 8249 | { |
97a8ea5a AF |
8250 | ARMCPU *cpu = ARM_CPU(cs); |
8251 | CPUARMState *env = &cpu->env; | |
b5ff1b31 FB |
8252 | uint32_t addr; |
8253 | uint32_t mask; | |
8254 | int new_mode; | |
8255 | uint32_t offset; | |
16a906fd | 8256 | uint32_t moe; |
b5ff1b31 | 8257 | |
16a906fd | 8258 | /* If this is a debug exception we must update the DBGDSCR.MOE bits */ |
64b91e3f | 8259 | switch (syn_get_ec(env->exception.syndrome)) { |
16a906fd PM |
8260 | case EC_BREAKPOINT: |
8261 | case EC_BREAKPOINT_SAME_EL: | |
8262 | moe = 1; | |
8263 | break; | |
8264 | case EC_WATCHPOINT: | |
8265 | case EC_WATCHPOINT_SAME_EL: | |
8266 | moe = 10; | |
8267 | break; | |
8268 | case EC_AA32_BKPT: | |
8269 | moe = 3; | |
8270 | break; | |
8271 | case EC_VECTORCATCH: | |
8272 | moe = 5; | |
8273 | break; | |
8274 | default: | |
8275 | moe = 0; | |
8276 | break; | |
8277 | } | |
8278 | ||
8279 | if (moe) { | |
8280 | env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); | |
8281 | } | |
8282 | ||
b9bc21ff PM |
8283 | if (env->exception.target_el == 2) { |
8284 | arm_cpu_do_interrupt_aarch32_hyp(cs); | |
8285 | return; | |
8286 | } | |
8287 | ||
27103424 | 8288 | switch (cs->exception_index) { |
b5ff1b31 FB |
8289 | case EXCP_UDEF: |
8290 | new_mode = ARM_CPU_MODE_UND; | |
8291 | addr = 0x04; | |
8292 | mask = CPSR_I; | |
8293 | if (env->thumb) | |
8294 | offset = 2; | |
8295 | else | |
8296 | offset = 4; | |
8297 | break; | |
8298 | case EXCP_SWI: | |
8299 | new_mode = ARM_CPU_MODE_SVC; | |
8300 | addr = 0x08; | |
8301 | mask = CPSR_I; | |
601d70b9 | 8302 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
8303 | offset = 0; |
8304 | break; | |
06c949e6 | 8305 | case EXCP_BKPT: |
9ee6e8bb PB |
8306 | /* Fall through to prefetch abort. */ |
8307 | case EXCP_PREFETCH_ABORT: | |
88ca1c2d | 8308 | A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); |
b848ce2b | 8309 | A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); |
3f1beaca | 8310 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", |
88ca1c2d | 8311 | env->exception.fsr, (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
8312 | new_mode = ARM_CPU_MODE_ABT; |
8313 | addr = 0x0c; | |
8314 | mask = CPSR_A | CPSR_I; | |
8315 | offset = 4; | |
8316 | break; | |
8317 | case EXCP_DATA_ABORT: | |
4a7e2d73 | 8318 | A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); |
b848ce2b | 8319 | A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); |
3f1beaca | 8320 | qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", |
4a7e2d73 | 8321 | env->exception.fsr, |
6cd8a264 | 8322 | (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
8323 | new_mode = ARM_CPU_MODE_ABT; |
8324 | addr = 0x10; | |
8325 | mask = CPSR_A | CPSR_I; | |
8326 | offset = 8; | |
8327 | break; | |
8328 | case EXCP_IRQ: | |
8329 | new_mode = ARM_CPU_MODE_IRQ; | |
8330 | addr = 0x18; | |
8331 | /* Disable IRQ and imprecise data aborts. */ | |
8332 | mask = CPSR_A | CPSR_I; | |
8333 | offset = 4; | |
de38d23b FA |
8334 | if (env->cp15.scr_el3 & SCR_IRQ) { |
8335 | /* IRQ routed to monitor mode */ | |
8336 | new_mode = ARM_CPU_MODE_MON; | |
8337 | mask |= CPSR_F; | |
8338 | } | |
b5ff1b31 FB |
8339 | break; |
8340 | case EXCP_FIQ: | |
8341 | new_mode = ARM_CPU_MODE_FIQ; | |
8342 | addr = 0x1c; | |
8343 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
8344 | mask = CPSR_A | CPSR_I | CPSR_F; | |
de38d23b FA |
8345 | if (env->cp15.scr_el3 & SCR_FIQ) { |
8346 | /* FIQ routed to monitor mode */ | |
8347 | new_mode = ARM_CPU_MODE_MON; | |
8348 | } | |
b5ff1b31 FB |
8349 | offset = 4; |
8350 | break; | |
87a4b270 PM |
8351 | case EXCP_VIRQ: |
8352 | new_mode = ARM_CPU_MODE_IRQ; | |
8353 | addr = 0x18; | |
8354 | /* Disable IRQ and imprecise data aborts. */ | |
8355 | mask = CPSR_A | CPSR_I; | |
8356 | offset = 4; | |
8357 | break; | |
8358 | case EXCP_VFIQ: | |
8359 | new_mode = ARM_CPU_MODE_FIQ; | |
8360 | addr = 0x1c; | |
8361 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
8362 | mask = CPSR_A | CPSR_I | CPSR_F; | |
8363 | offset = 4; | |
8364 | break; | |
dbe9d163 FA |
8365 | case EXCP_SMC: |
8366 | new_mode = ARM_CPU_MODE_MON; | |
8367 | addr = 0x08; | |
8368 | mask = CPSR_A | CPSR_I | CPSR_F; | |
8369 | offset = 0; | |
8370 | break; | |
b5ff1b31 | 8371 | default: |
a47dddd7 | 8372 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
b5ff1b31 FB |
8373 | return; /* Never happens. Keep compiler happy. */ |
8374 | } | |
e89e51a1 FA |
8375 | |
8376 | if (new_mode == ARM_CPU_MODE_MON) { | |
8377 | addr += env->cp15.mvbar; | |
137feaa9 | 8378 | } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { |
e89e51a1 | 8379 | /* High vectors. When enabled, base address cannot be remapped. */ |
b5ff1b31 | 8380 | addr += 0xffff0000; |
8641136c NR |
8381 | } else { |
8382 | /* ARM v7 architectures provide a vector base address register to remap | |
8383 | * the interrupt vector table. | |
e89e51a1 | 8384 | * This register is only followed in non-monitor mode, and is banked. |
8641136c NR |
8385 | * Note: only bits 31:5 are valid. |
8386 | */ | |
fb6c91ba | 8387 | addr += A32_BANKED_CURRENT_REG_GET(env, vbar); |
b5ff1b31 | 8388 | } |
dbe9d163 FA |
8389 | |
8390 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
8391 | env->cp15.scr_el3 &= ~SCR_NS; | |
8392 | } | |
8393 | ||
dea8378b | 8394 | take_aarch32_exception(env, new_mode, mask, offset, addr); |
b5ff1b31 FB |
8395 | } |
8396 | ||
966f758c PM |
8397 | /* Handle exception entry to a target EL which is using AArch64 */ |
8398 | static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | |
f3a9b694 PM |
8399 | { |
8400 | ARMCPU *cpu = ARM_CPU(cs); | |
8401 | CPUARMState *env = &cpu->env; | |
8402 | unsigned int new_el = env->exception.target_el; | |
8403 | target_ulong addr = env->cp15.vbar_el[new_el]; | |
8404 | unsigned int new_mode = aarch64_pstate_mode(new_el, true); | |
0ab5953b RH |
8405 | unsigned int cur_el = arm_current_el(env); |
8406 | ||
9a05f7b6 RH |
8407 | /* |
8408 | * Note that new_el can never be 0. If cur_el is 0, then | |
8409 | * el0_a64 is is_a64(), else el0_a64 is ignored. | |
8410 | */ | |
8411 | aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); | |
f3a9b694 | 8412 | |
0ab5953b | 8413 | if (cur_el < new_el) { |
3d6f7617 PM |
8414 | /* Entry vector offset depends on whether the implemented EL |
8415 | * immediately lower than the target level is using AArch32 or AArch64 | |
8416 | */ | |
8417 | bool is_aa64; | |
8418 | ||
8419 | switch (new_el) { | |
8420 | case 3: | |
8421 | is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; | |
8422 | break; | |
8423 | case 2: | |
8424 | is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0; | |
8425 | break; | |
8426 | case 1: | |
8427 | is_aa64 = is_a64(env); | |
8428 | break; | |
8429 | default: | |
8430 | g_assert_not_reached(); | |
8431 | } | |
8432 | ||
8433 | if (is_aa64) { | |
f3a9b694 PM |
8434 | addr += 0x400; |
8435 | } else { | |
8436 | addr += 0x600; | |
8437 | } | |
8438 | } else if (pstate_read(env) & PSTATE_SP) { | |
8439 | addr += 0x200; | |
8440 | } | |
8441 | ||
f3a9b694 PM |
8442 | switch (cs->exception_index) { |
8443 | case EXCP_PREFETCH_ABORT: | |
8444 | case EXCP_DATA_ABORT: | |
8445 | env->cp15.far_el[new_el] = env->exception.vaddress; | |
8446 | qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", | |
8447 | env->cp15.far_el[new_el]); | |
8448 | /* fall through */ | |
8449 | case EXCP_BKPT: | |
8450 | case EXCP_UDEF: | |
8451 | case EXCP_SWI: | |
8452 | case EXCP_HVC: | |
8453 | case EXCP_HYP_TRAP: | |
8454 | case EXCP_SMC: | |
4be42f40 PM |
8455 | if (syn_get_ec(env->exception.syndrome) == EC_ADVSIMDFPACCESSTRAP) { |
8456 | /* | |
8457 | * QEMU internal FP/SIMD syndromes from AArch32 include the | |
8458 | * TA and coproc fields which are only exposed if the exception | |
8459 | * is taken to AArch32 Hyp mode. Mask them out to get a valid | |
8460 | * AArch64 format syndrome. | |
8461 | */ | |
8462 | env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20); | |
8463 | } | |
f3a9b694 PM |
8464 | env->cp15.esr_el[new_el] = env->exception.syndrome; |
8465 | break; | |
8466 | case EXCP_IRQ: | |
8467 | case EXCP_VIRQ: | |
8468 | addr += 0x80; | |
8469 | break; | |
8470 | case EXCP_FIQ: | |
8471 | case EXCP_VFIQ: | |
8472 | addr += 0x100; | |
8473 | break; | |
8474 | case EXCP_SEMIHOST: | |
8475 | qemu_log_mask(CPU_LOG_INT, | |
8476 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
8477 | env->xregs[0]); | |
8478 | env->xregs[0] = do_arm_semihosting(env); | |
8479 | return; | |
8480 | default: | |
8481 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
8482 | } | |
8483 | ||
8484 | if (is_a64(env)) { | |
8485 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env); | |
8486 | aarch64_save_sp(env, arm_current_el(env)); | |
8487 | env->elr_el[new_el] = env->pc; | |
8488 | } else { | |
8489 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env); | |
f3a9b694 PM |
8490 | env->elr_el[new_el] = env->regs[15]; |
8491 | ||
8492 | aarch64_sync_32_to_64(env); | |
8493 | ||
8494 | env->condexec_bits = 0; | |
8495 | } | |
8496 | qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", | |
8497 | env->elr_el[new_el]); | |
8498 | ||
8499 | pstate_write(env, PSTATE_DAIF | new_mode); | |
8500 | env->aarch64 = 1; | |
8501 | aarch64_restore_sp(env, new_el); | |
a8a79c7a | 8502 | helper_rebuild_hflags_a64(env, new_el); |
f3a9b694 PM |
8503 | |
8504 | env->pc = addr; | |
8505 | ||
8506 | qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", | |
8507 | new_el, env->pc, pstate_read(env)); | |
966f758c PM |
8508 | } |
8509 | ||
ed6e6ba9 AB |
8510 | /* |
8511 | * Do semihosting call and set the appropriate return value. All the | |
8512 | * permission and validity checks have been done at translate time. | |
8513 | * | |
8514 | * We only see semihosting exceptions in TCG only as they are not | |
8515 | * trapped to the hypervisor in KVM. | |
8516 | */ | |
91f78c58 | 8517 | #ifdef CONFIG_TCG |
ed6e6ba9 AB |
8518 | static void handle_semihosting(CPUState *cs) |
8519 | { | |
904c04de PM |
8520 | ARMCPU *cpu = ARM_CPU(cs); |
8521 | CPUARMState *env = &cpu->env; | |
8522 | ||
8523 | if (is_a64(env)) { | |
ed6e6ba9 AB |
8524 | qemu_log_mask(CPU_LOG_INT, |
8525 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
8526 | env->xregs[0]); | |
8527 | env->xregs[0] = do_arm_semihosting(env); | |
904c04de | 8528 | } else { |
904c04de PM |
8529 | qemu_log_mask(CPU_LOG_INT, |
8530 | "...handling as semihosting call 0x%x\n", | |
8531 | env->regs[0]); | |
8532 | env->regs[0] = do_arm_semihosting(env); | |
904c04de PM |
8533 | } |
8534 | } | |
ed6e6ba9 | 8535 | #endif |
904c04de | 8536 | |
966f758c PM |
8537 | /* Handle a CPU exception for A and R profile CPUs. |
8538 | * Do any appropriate logging, handle PSCI calls, and then hand off | |
8539 | * to the AArch64-entry or AArch32-entry function depending on the | |
8540 | * target exception level's register width. | |
8541 | */ | |
8542 | void arm_cpu_do_interrupt(CPUState *cs) | |
8543 | { | |
8544 | ARMCPU *cpu = ARM_CPU(cs); | |
8545 | CPUARMState *env = &cpu->env; | |
8546 | unsigned int new_el = env->exception.target_el; | |
8547 | ||
531c60a9 | 8548 | assert(!arm_feature(env, ARM_FEATURE_M)); |
966f758c PM |
8549 | |
8550 | arm_log_exception(cs->exception_index); | |
8551 | qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), | |
8552 | new_el); | |
8553 | if (qemu_loglevel_mask(CPU_LOG_INT) | |
8554 | && !excp_is_internal(cs->exception_index)) { | |
6568da45 | 8555 | qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", |
64b91e3f | 8556 | syn_get_ec(env->exception.syndrome), |
966f758c PM |
8557 | env->exception.syndrome); |
8558 | } | |
8559 | ||
8560 | if (arm_is_psci_call(cpu, cs->exception_index)) { | |
8561 | arm_handle_psci_call(cpu); | |
8562 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | |
8563 | return; | |
8564 | } | |
8565 | ||
ed6e6ba9 AB |
8566 | /* |
8567 | * Semihosting semantics depend on the register width of the code | |
8568 | * that caused the exception, not the target exception level, so | |
8569 | * must be handled here. | |
966f758c | 8570 | */ |
ed6e6ba9 AB |
8571 | #ifdef CONFIG_TCG |
8572 | if (cs->exception_index == EXCP_SEMIHOST) { | |
8573 | handle_semihosting(cs); | |
904c04de PM |
8574 | return; |
8575 | } | |
ed6e6ba9 | 8576 | #endif |
904c04de | 8577 | |
b5c53d1b AL |
8578 | /* Hooks may change global state so BQL should be held, also the |
8579 | * BQL needs to be held for any modification of | |
8580 | * cs->interrupt_request. | |
8581 | */ | |
8582 | g_assert(qemu_mutex_iothread_locked()); | |
8583 | ||
8584 | arm_call_pre_el_change_hook(cpu); | |
8585 | ||
904c04de PM |
8586 | assert(!excp_is_internal(cs->exception_index)); |
8587 | if (arm_el_is_aa64(env, new_el)) { | |
966f758c PM |
8588 | arm_cpu_do_interrupt_aarch64(cs); |
8589 | } else { | |
8590 | arm_cpu_do_interrupt_aarch32(cs); | |
8591 | } | |
f3a9b694 | 8592 | |
bd7d00fc PM |
8593 | arm_call_el_change_hook(cpu); |
8594 | ||
f3a9b694 PM |
8595 | if (!kvm_enabled()) { |
8596 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
8597 | } | |
8598 | } | |
c47eaf9f | 8599 | #endif /* !CONFIG_USER_ONLY */ |
0480f69a PM |
8600 | |
8601 | /* Return the exception level which controls this address translation regime */ | |
8602 | static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) | |
8603 | { | |
8604 | switch (mmu_idx) { | |
8605 | case ARMMMUIdx_S2NS: | |
8606 | case ARMMMUIdx_S1E2: | |
8607 | return 2; | |
8608 | case ARMMMUIdx_S1E3: | |
8609 | return 3; | |
8610 | case ARMMMUIdx_S1SE0: | |
8611 | return arm_el_is_aa64(env, 3) ? 1 : 3; | |
8612 | case ARMMMUIdx_S1SE1: | |
8613 | case ARMMMUIdx_S1NSE0: | |
8614 | case ARMMMUIdx_S1NSE1: | |
62593718 PM |
8615 | case ARMMMUIdx_MPrivNegPri: |
8616 | case ARMMMUIdx_MUserNegPri: | |
e7b921c2 PM |
8617 | case ARMMMUIdx_MPriv: |
8618 | case ARMMMUIdx_MUser: | |
62593718 PM |
8619 | case ARMMMUIdx_MSPrivNegPri: |
8620 | case ARMMMUIdx_MSUserNegPri: | |
66787c78 | 8621 | case ARMMMUIdx_MSPriv: |
66787c78 | 8622 | case ARMMMUIdx_MSUser: |
0480f69a PM |
8623 | return 1; |
8624 | default: | |
8625 | g_assert_not_reached(); | |
8626 | } | |
8627 | } | |
8628 | ||
c47eaf9f PM |
8629 | #ifndef CONFIG_USER_ONLY |
8630 | ||
0480f69a PM |
8631 | /* Return the SCTLR value which controls this address translation regime */ |
8632 | static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) | |
8633 | { | |
8634 | return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; | |
8635 | } | |
8636 | ||
8637 | /* Return true if the specified stage of address translation is disabled */ | |
8638 | static inline bool regime_translation_disabled(CPUARMState *env, | |
8639 | ARMMMUIdx mmu_idx) | |
8640 | { | |
29c483a5 | 8641 | if (arm_feature(env, ARM_FEATURE_M)) { |
ecf5e8ea | 8642 | switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & |
3bef7012 PM |
8643 | (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { |
8644 | case R_V7M_MPU_CTRL_ENABLE_MASK: | |
8645 | /* Enabled, but not for HardFault and NMI */ | |
62593718 | 8646 | return mmu_idx & ARM_MMU_IDX_M_NEGPRI; |
3bef7012 PM |
8647 | case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: |
8648 | /* Enabled for all cases */ | |
8649 | return false; | |
8650 | case 0: | |
8651 | default: | |
8652 | /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but | |
8653 | * we warned about that in armv7m_nvic.c when the guest set it. | |
8654 | */ | |
8655 | return true; | |
8656 | } | |
29c483a5 MD |
8657 | } |
8658 | ||
0480f69a | 8659 | if (mmu_idx == ARMMMUIdx_S2NS) { |
9d1bab33 PM |
8660 | /* HCR.DC means HCR.VM behaves as 1 */ |
8661 | return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) == 0; | |
0480f69a | 8662 | } |
3d0e3080 PM |
8663 | |
8664 | if (env->cp15.hcr_el2 & HCR_TGE) { | |
8665 | /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ | |
8666 | if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) { | |
8667 | return true; | |
8668 | } | |
8669 | } | |
8670 | ||
9d1bab33 PM |
8671 | if ((env->cp15.hcr_el2 & HCR_DC) && |
8672 | (mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1)) { | |
8673 | /* HCR.DC means SCTLR_EL1.M behaves as 0 */ | |
8674 | return true; | |
8675 | } | |
8676 | ||
0480f69a PM |
8677 | return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; |
8678 | } | |
8679 | ||
73462ddd PC |
8680 | static inline bool regime_translation_big_endian(CPUARMState *env, |
8681 | ARMMMUIdx mmu_idx) | |
8682 | { | |
8683 | return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; | |
8684 | } | |
8685 | ||
c47eaf9f PM |
8686 | /* Return the TTBR associated with this translation regime */ |
8687 | static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, | |
8688 | int ttbrn) | |
8689 | { | |
8690 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
8691 | return env->cp15.vttbr_el2; | |
8692 | } | |
8693 | if (ttbrn == 0) { | |
8694 | return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; | |
8695 | } else { | |
8696 | return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; | |
8697 | } | |
8698 | } | |
8699 | ||
8700 | #endif /* !CONFIG_USER_ONLY */ | |
8701 | ||
0480f69a PM |
8702 | /* Return the TCR controlling this translation regime */ |
8703 | static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) | |
8704 | { | |
8705 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
68e9c2fe | 8706 | return &env->cp15.vtcr_el2; |
0480f69a PM |
8707 | } |
8708 | return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; | |
8709 | } | |
8710 | ||
8bd5c820 PM |
8711 | /* Convert a possible stage1+2 MMU index into the appropriate |
8712 | * stage 1 MMU index | |
8713 | */ | |
8714 | static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) | |
8715 | { | |
8716 | if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { | |
8717 | mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0); | |
8718 | } | |
8719 | return mmu_idx; | |
8720 | } | |
8721 | ||
0480f69a PM |
8722 | /* Return true if the translation regime is using LPAE format page tables */ |
8723 | static inline bool regime_using_lpae_format(CPUARMState *env, | |
8724 | ARMMMUIdx mmu_idx) | |
8725 | { | |
8726 | int el = regime_el(env, mmu_idx); | |
8727 | if (el == 2 || arm_el_is_aa64(env, el)) { | |
8728 | return true; | |
8729 | } | |
8730 | if (arm_feature(env, ARM_FEATURE_LPAE) | |
8731 | && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { | |
8732 | return true; | |
8733 | } | |
8734 | return false; | |
8735 | } | |
8736 | ||
deb2db99 AR |
8737 | /* Returns true if the stage 1 translation regime is using LPAE format page |
8738 | * tables. Used when raising alignment exceptions, whose FSR changes depending | |
8739 | * on whether the long or short descriptor format is in use. */ | |
8740 | bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) | |
30901475 | 8741 | { |
8bd5c820 | 8742 | mmu_idx = stage_1_mmu_idx(mmu_idx); |
deb2db99 | 8743 | |
30901475 AB |
8744 | return regime_using_lpae_format(env, mmu_idx); |
8745 | } | |
8746 | ||
c47eaf9f | 8747 | #ifndef CONFIG_USER_ONLY |
0480f69a PM |
8748 | static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) |
8749 | { | |
8750 | switch (mmu_idx) { | |
8751 | case ARMMMUIdx_S1SE0: | |
8752 | case ARMMMUIdx_S1NSE0: | |
e7b921c2 | 8753 | case ARMMMUIdx_MUser: |
871bec7c | 8754 | case ARMMMUIdx_MSUser: |
62593718 PM |
8755 | case ARMMMUIdx_MUserNegPri: |
8756 | case ARMMMUIdx_MSUserNegPri: | |
0480f69a PM |
8757 | return true; |
8758 | default: | |
8759 | return false; | |
8760 | case ARMMMUIdx_S12NSE0: | |
8761 | case ARMMMUIdx_S12NSE1: | |
8762 | g_assert_not_reached(); | |
8763 | } | |
8764 | } | |
8765 | ||
0fbf5238 AJ |
8766 | /* Translate section/page access permissions to page |
8767 | * R/W protection flags | |
d76951b6 AJ |
8768 | * |
8769 | * @env: CPUARMState | |
8770 | * @mmu_idx: MMU index indicating required translation regime | |
8771 | * @ap: The 3-bit access permissions (AP[2:0]) | |
8772 | * @domain_prot: The 2-bit domain access permissions | |
0fbf5238 AJ |
8773 | */ |
8774 | static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, | |
8775 | int ap, int domain_prot) | |
8776 | { | |
554b0b09 PM |
8777 | bool is_user = regime_is_user(env, mmu_idx); |
8778 | ||
8779 | if (domain_prot == 3) { | |
8780 | return PAGE_READ | PAGE_WRITE; | |
8781 | } | |
8782 | ||
554b0b09 PM |
8783 | switch (ap) { |
8784 | case 0: | |
8785 | if (arm_feature(env, ARM_FEATURE_V7)) { | |
8786 | return 0; | |
8787 | } | |
554b0b09 PM |
8788 | switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) { |
8789 | case SCTLR_S: | |
8790 | return is_user ? 0 : PAGE_READ; | |
8791 | case SCTLR_R: | |
8792 | return PAGE_READ; | |
8793 | default: | |
8794 | return 0; | |
8795 | } | |
8796 | case 1: | |
8797 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
8798 | case 2: | |
87c3d486 | 8799 | if (is_user) { |
0fbf5238 | 8800 | return PAGE_READ; |
87c3d486 | 8801 | } else { |
554b0b09 | 8802 | return PAGE_READ | PAGE_WRITE; |
87c3d486 | 8803 | } |
554b0b09 PM |
8804 | case 3: |
8805 | return PAGE_READ | PAGE_WRITE; | |
8806 | case 4: /* Reserved. */ | |
8807 | return 0; | |
8808 | case 5: | |
0fbf5238 | 8809 | return is_user ? 0 : PAGE_READ; |
554b0b09 | 8810 | case 6: |
0fbf5238 | 8811 | return PAGE_READ; |
554b0b09 | 8812 | case 7: |
87c3d486 | 8813 | if (!arm_feature(env, ARM_FEATURE_V6K)) { |
554b0b09 | 8814 | return 0; |
87c3d486 | 8815 | } |
0fbf5238 | 8816 | return PAGE_READ; |
554b0b09 | 8817 | default: |
0fbf5238 | 8818 | g_assert_not_reached(); |
554b0b09 | 8819 | } |
b5ff1b31 FB |
8820 | } |
8821 | ||
d76951b6 AJ |
8822 | /* Translate section/page access permissions to page |
8823 | * R/W protection flags. | |
8824 | * | |
d76951b6 | 8825 | * @ap: The 2-bit simple AP (AP[2:1]) |
d8e052b3 | 8826 | * @is_user: TRUE if accessing from PL0 |
d76951b6 | 8827 | */ |
d8e052b3 | 8828 | static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user) |
d76951b6 | 8829 | { |
d76951b6 AJ |
8830 | switch (ap) { |
8831 | case 0: | |
8832 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
8833 | case 1: | |
8834 | return PAGE_READ | PAGE_WRITE; | |
8835 | case 2: | |
8836 | return is_user ? 0 : PAGE_READ; | |
8837 | case 3: | |
8838 | return PAGE_READ; | |
8839 | default: | |
8840 | g_assert_not_reached(); | |
8841 | } | |
8842 | } | |
8843 | ||
d8e052b3 AJ |
8844 | static inline int |
8845 | simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) | |
8846 | { | |
8847 | return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); | |
8848 | } | |
8849 | ||
6ab1a5ee EI |
8850 | /* Translate S2 section/page access permissions to protection flags |
8851 | * | |
8852 | * @env: CPUARMState | |
8853 | * @s2ap: The 2-bit stage2 access permissions (S2AP) | |
8854 | * @xn: XN (execute-never) bit | |
8855 | */ | |
8856 | static int get_S2prot(CPUARMState *env, int s2ap, int xn) | |
8857 | { | |
8858 | int prot = 0; | |
8859 | ||
8860 | if (s2ap & 1) { | |
8861 | prot |= PAGE_READ; | |
8862 | } | |
8863 | if (s2ap & 2) { | |
8864 | prot |= PAGE_WRITE; | |
8865 | } | |
8866 | if (!xn) { | |
dfda6837 SS |
8867 | if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { |
8868 | prot |= PAGE_EXEC; | |
8869 | } | |
6ab1a5ee EI |
8870 | } |
8871 | return prot; | |
8872 | } | |
8873 | ||
d8e052b3 AJ |
8874 | /* Translate section/page access permissions to protection flags |
8875 | * | |
8876 | * @env: CPUARMState | |
8877 | * @mmu_idx: MMU index indicating required translation regime | |
8878 | * @is_aa64: TRUE if AArch64 | |
8879 | * @ap: The 2-bit simple AP (AP[2:1]) | |
8880 | * @ns: NS (non-secure) bit | |
8881 | * @xn: XN (execute-never) bit | |
8882 | * @pxn: PXN (privileged execute-never) bit | |
8883 | */ | |
8884 | static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, | |
8885 | int ap, int ns, int xn, int pxn) | |
8886 | { | |
8887 | bool is_user = regime_is_user(env, mmu_idx); | |
8888 | int prot_rw, user_rw; | |
8889 | bool have_wxn; | |
8890 | int wxn = 0; | |
8891 | ||
8892 | assert(mmu_idx != ARMMMUIdx_S2NS); | |
8893 | ||
8894 | user_rw = simple_ap_to_rw_prot_is_user(ap, true); | |
8895 | if (is_user) { | |
8896 | prot_rw = user_rw; | |
8897 | } else { | |
8898 | prot_rw = simple_ap_to_rw_prot_is_user(ap, false); | |
8899 | } | |
8900 | ||
8901 | if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { | |
8902 | return prot_rw; | |
8903 | } | |
8904 | ||
8905 | /* TODO have_wxn should be replaced with | |
8906 | * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) | |
8907 | * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE | |
8908 | * compatible processors have EL2, which is required for [U]WXN. | |
8909 | */ | |
8910 | have_wxn = arm_feature(env, ARM_FEATURE_LPAE); | |
8911 | ||
8912 | if (have_wxn) { | |
8913 | wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN; | |
8914 | } | |
8915 | ||
8916 | if (is_aa64) { | |
8917 | switch (regime_el(env, mmu_idx)) { | |
8918 | case 1: | |
8919 | if (!is_user) { | |
8920 | xn = pxn || (user_rw & PAGE_WRITE); | |
8921 | } | |
8922 | break; | |
8923 | case 2: | |
8924 | case 3: | |
8925 | break; | |
8926 | } | |
8927 | } else if (arm_feature(env, ARM_FEATURE_V7)) { | |
8928 | switch (regime_el(env, mmu_idx)) { | |
8929 | case 1: | |
8930 | case 3: | |
8931 | if (is_user) { | |
8932 | xn = xn || !(user_rw & PAGE_READ); | |
8933 | } else { | |
8934 | int uwxn = 0; | |
8935 | if (have_wxn) { | |
8936 | uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN; | |
8937 | } | |
8938 | xn = xn || !(prot_rw & PAGE_READ) || pxn || | |
8939 | (uwxn && (user_rw & PAGE_WRITE)); | |
8940 | } | |
8941 | break; | |
8942 | case 2: | |
8943 | break; | |
8944 | } | |
8945 | } else { | |
8946 | xn = wxn = 0; | |
8947 | } | |
8948 | ||
8949 | if (xn || (wxn && (prot_rw & PAGE_WRITE))) { | |
8950 | return prot_rw; | |
8951 | } | |
8952 | return prot_rw | PAGE_EXEC; | |
8953 | } | |
8954 | ||
0480f69a PM |
8955 | static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, |
8956 | uint32_t *table, uint32_t address) | |
b2fa1797 | 8957 | { |
0480f69a | 8958 | /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ |
0480f69a | 8959 | TCR *tcr = regime_tcr(env, mmu_idx); |
11f136ee | 8960 | |
11f136ee FA |
8961 | if (address & tcr->mask) { |
8962 | if (tcr->raw_tcr & TTBCR_PD1) { | |
e389be16 FA |
8963 | /* Translation table walk disabled for TTBR1 */ |
8964 | return false; | |
8965 | } | |
aef878be | 8966 | *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; |
e389be16 | 8967 | } else { |
11f136ee | 8968 | if (tcr->raw_tcr & TTBCR_PD0) { |
e389be16 FA |
8969 | /* Translation table walk disabled for TTBR0 */ |
8970 | return false; | |
8971 | } | |
aef878be | 8972 | *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; |
e389be16 FA |
8973 | } |
8974 | *table |= (address >> 18) & 0x3ffc; | |
8975 | return true; | |
b2fa1797 PB |
8976 | } |
8977 | ||
37785977 EI |
8978 | /* Translate a S1 pagetable walk through S2 if needed. */ |
8979 | static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, | |
8980 | hwaddr addr, MemTxAttrs txattrs, | |
37785977 EI |
8981 | ARMMMUFaultInfo *fi) |
8982 | { | |
8983 | if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) && | |
8984 | !regime_translation_disabled(env, ARMMMUIdx_S2NS)) { | |
8985 | target_ulong s2size; | |
8986 | hwaddr s2pa; | |
8987 | int s2prot; | |
8988 | int ret; | |
eadb2feb PM |
8989 | ARMCacheAttrs cacheattrs = {}; |
8990 | ARMCacheAttrs *pcacheattrs = NULL; | |
8991 | ||
8992 | if (env->cp15.hcr_el2 & HCR_PTW) { | |
8993 | /* | |
8994 | * PTW means we must fault if this S1 walk touches S2 Device | |
8995 | * memory; otherwise we don't care about the attributes and can | |
8996 | * save the S2 translation the effort of computing them. | |
8997 | */ | |
8998 | pcacheattrs = &cacheattrs; | |
8999 | } | |
37785977 EI |
9000 | |
9001 | ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, | |
eadb2feb | 9002 | &txattrs, &s2prot, &s2size, fi, pcacheattrs); |
37785977 | 9003 | if (ret) { |
3b39d734 | 9004 | assert(fi->type != ARMFault_None); |
37785977 EI |
9005 | fi->s2addr = addr; |
9006 | fi->stage2 = true; | |
9007 | fi->s1ptw = true; | |
9008 | return ~0; | |
9009 | } | |
eadb2feb PM |
9010 | if (pcacheattrs && (pcacheattrs->attrs & 0xf0) == 0) { |
9011 | /* Access was to Device memory: generate Permission fault */ | |
9012 | fi->type = ARMFault_Permission; | |
9013 | fi->s2addr = addr; | |
9014 | fi->stage2 = true; | |
9015 | fi->s1ptw = true; | |
9016 | return ~0; | |
9017 | } | |
37785977 EI |
9018 | addr = s2pa; |
9019 | } | |
9020 | return addr; | |
9021 | } | |
9022 | ||
14577270 | 9023 | /* All loads done in the course of a page table walk go through here. */ |
a614e698 | 9024 | static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, |
3795a6de | 9025 | ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) |
ebca90e4 | 9026 | { |
a614e698 EI |
9027 | ARMCPU *cpu = ARM_CPU(cs); |
9028 | CPUARMState *env = &cpu->env; | |
ebca90e4 | 9029 | MemTxAttrs attrs = {}; |
3b39d734 | 9030 | MemTxResult result = MEMTX_OK; |
5ce4ff65 | 9031 | AddressSpace *as; |
3b39d734 | 9032 | uint32_t data; |
ebca90e4 PM |
9033 | |
9034 | attrs.secure = is_secure; | |
5ce4ff65 | 9035 | as = arm_addressspace(cs, attrs); |
3795a6de | 9036 | addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi); |
a614e698 EI |
9037 | if (fi->s1ptw) { |
9038 | return 0; | |
9039 | } | |
73462ddd | 9040 | if (regime_translation_big_endian(env, mmu_idx)) { |
3b39d734 | 9041 | data = address_space_ldl_be(as, addr, attrs, &result); |
73462ddd | 9042 | } else { |
3b39d734 | 9043 | data = address_space_ldl_le(as, addr, attrs, &result); |
73462ddd | 9044 | } |
3b39d734 PM |
9045 | if (result == MEMTX_OK) { |
9046 | return data; | |
9047 | } | |
9048 | fi->type = ARMFault_SyncExternalOnWalk; | |
9049 | fi->ea = arm_extabort_type(result); | |
9050 | return 0; | |
ebca90e4 PM |
9051 | } |
9052 | ||
37785977 | 9053 | static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, |
3795a6de | 9054 | ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) |
ebca90e4 | 9055 | { |
37785977 EI |
9056 | ARMCPU *cpu = ARM_CPU(cs); |
9057 | CPUARMState *env = &cpu->env; | |
ebca90e4 | 9058 | MemTxAttrs attrs = {}; |
3b39d734 | 9059 | MemTxResult result = MEMTX_OK; |
5ce4ff65 | 9060 | AddressSpace *as; |
9aea1ea3 | 9061 | uint64_t data; |
ebca90e4 PM |
9062 | |
9063 | attrs.secure = is_secure; | |
5ce4ff65 | 9064 | as = arm_addressspace(cs, attrs); |
3795a6de | 9065 | addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi); |
37785977 EI |
9066 | if (fi->s1ptw) { |
9067 | return 0; | |
9068 | } | |
73462ddd | 9069 | if (regime_translation_big_endian(env, mmu_idx)) { |
3b39d734 | 9070 | data = address_space_ldq_be(as, addr, attrs, &result); |
73462ddd | 9071 | } else { |
3b39d734 PM |
9072 | data = address_space_ldq_le(as, addr, attrs, &result); |
9073 | } | |
9074 | if (result == MEMTX_OK) { | |
9075 | return data; | |
73462ddd | 9076 | } |
3b39d734 PM |
9077 | fi->type = ARMFault_SyncExternalOnWalk; |
9078 | fi->ea = arm_extabort_type(result); | |
9079 | return 0; | |
ebca90e4 PM |
9080 | } |
9081 | ||
b7cc4e82 | 9082 | static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, |
03ae85f8 | 9083 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
b7cc4e82 | 9084 | hwaddr *phys_ptr, int *prot, |
f989983e | 9085 | target_ulong *page_size, |
e14b5a23 | 9086 | ARMMMUFaultInfo *fi) |
b5ff1b31 | 9087 | { |
2fc0cc0e | 9088 | CPUState *cs = env_cpu(env); |
f989983e | 9089 | int level = 1; |
b5ff1b31 FB |
9090 | uint32_t table; |
9091 | uint32_t desc; | |
9092 | int type; | |
9093 | int ap; | |
e389be16 | 9094 | int domain = 0; |
dd4ebc2e | 9095 | int domain_prot; |
a8170e5e | 9096 | hwaddr phys_addr; |
0480f69a | 9097 | uint32_t dacr; |
b5ff1b31 | 9098 | |
9ee6e8bb PB |
9099 | /* Pagetable walk. */ |
9100 | /* Lookup l1 descriptor. */ | |
0480f69a | 9101 | if (!get_level1_table_address(env, mmu_idx, &table, address)) { |
e389be16 | 9102 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ |
f989983e | 9103 | fi->type = ARMFault_Translation; |
e389be16 FA |
9104 | goto do_fault; |
9105 | } | |
a614e698 | 9106 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 9107 | mmu_idx, fi); |
3b39d734 PM |
9108 | if (fi->type != ARMFault_None) { |
9109 | goto do_fault; | |
9110 | } | |
9ee6e8bb | 9111 | type = (desc & 3); |
dd4ebc2e | 9112 | domain = (desc >> 5) & 0x0f; |
0480f69a PM |
9113 | if (regime_el(env, mmu_idx) == 1) { |
9114 | dacr = env->cp15.dacr_ns; | |
9115 | } else { | |
9116 | dacr = env->cp15.dacr_s; | |
9117 | } | |
9118 | domain_prot = (dacr >> (domain * 2)) & 3; | |
9ee6e8bb | 9119 | if (type == 0) { |
601d70b9 | 9120 | /* Section translation fault. */ |
f989983e | 9121 | fi->type = ARMFault_Translation; |
9ee6e8bb PB |
9122 | goto do_fault; |
9123 | } | |
f989983e PM |
9124 | if (type != 2) { |
9125 | level = 2; | |
9126 | } | |
dd4ebc2e | 9127 | if (domain_prot == 0 || domain_prot == 2) { |
f989983e | 9128 | fi->type = ARMFault_Domain; |
9ee6e8bb PB |
9129 | goto do_fault; |
9130 | } | |
9131 | if (type == 2) { | |
9132 | /* 1Mb section. */ | |
9133 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
9134 | ap = (desc >> 10) & 3; | |
d4c430a8 | 9135 | *page_size = 1024 * 1024; |
9ee6e8bb PB |
9136 | } else { |
9137 | /* Lookup l2 entry. */ | |
554b0b09 PM |
9138 | if (type == 1) { |
9139 | /* Coarse pagetable. */ | |
9140 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
9141 | } else { | |
9142 | /* Fine pagetable. */ | |
9143 | table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); | |
9144 | } | |
a614e698 | 9145 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 9146 | mmu_idx, fi); |
3b39d734 PM |
9147 | if (fi->type != ARMFault_None) { |
9148 | goto do_fault; | |
9149 | } | |
9ee6e8bb PB |
9150 | switch (desc & 3) { |
9151 | case 0: /* Page translation fault. */ | |
f989983e | 9152 | fi->type = ARMFault_Translation; |
9ee6e8bb PB |
9153 | goto do_fault; |
9154 | case 1: /* 64k page. */ | |
9155 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
9156 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
d4c430a8 | 9157 | *page_size = 0x10000; |
ce819861 | 9158 | break; |
9ee6e8bb PB |
9159 | case 2: /* 4k page. */ |
9160 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
c10f7fc3 | 9161 | ap = (desc >> (4 + ((address >> 9) & 6))) & 3; |
d4c430a8 | 9162 | *page_size = 0x1000; |
ce819861 | 9163 | break; |
fc1891c7 | 9164 | case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ |
554b0b09 | 9165 | if (type == 1) { |
fc1891c7 PM |
9166 | /* ARMv6/XScale extended small page format */ |
9167 | if (arm_feature(env, ARM_FEATURE_XSCALE) | |
9168 | || arm_feature(env, ARM_FEATURE_V6)) { | |
554b0b09 | 9169 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
fc1891c7 | 9170 | *page_size = 0x1000; |
554b0b09 | 9171 | } else { |
fc1891c7 PM |
9172 | /* UNPREDICTABLE in ARMv5; we choose to take a |
9173 | * page translation fault. | |
9174 | */ | |
f989983e | 9175 | fi->type = ARMFault_Translation; |
554b0b09 PM |
9176 | goto do_fault; |
9177 | } | |
9178 | } else { | |
9179 | phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); | |
fc1891c7 | 9180 | *page_size = 0x400; |
554b0b09 | 9181 | } |
9ee6e8bb | 9182 | ap = (desc >> 4) & 3; |
ce819861 PB |
9183 | break; |
9184 | default: | |
9ee6e8bb PB |
9185 | /* Never happens, but compiler isn't smart enough to tell. */ |
9186 | abort(); | |
ce819861 | 9187 | } |
9ee6e8bb | 9188 | } |
0fbf5238 AJ |
9189 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); |
9190 | *prot |= *prot ? PAGE_EXEC : 0; | |
9191 | if (!(*prot & (1 << access_type))) { | |
9ee6e8bb | 9192 | /* Access permission fault. */ |
f989983e | 9193 | fi->type = ARMFault_Permission; |
9ee6e8bb PB |
9194 | goto do_fault; |
9195 | } | |
9196 | *phys_ptr = phys_addr; | |
b7cc4e82 | 9197 | return false; |
9ee6e8bb | 9198 | do_fault: |
f989983e PM |
9199 | fi->domain = domain; |
9200 | fi->level = level; | |
b7cc4e82 | 9201 | return true; |
9ee6e8bb PB |
9202 | } |
9203 | ||
b7cc4e82 | 9204 | static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, |
03ae85f8 | 9205 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
b7cc4e82 | 9206 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, |
f06cf243 | 9207 | target_ulong *page_size, ARMMMUFaultInfo *fi) |
9ee6e8bb | 9208 | { |
2fc0cc0e | 9209 | CPUState *cs = env_cpu(env); |
f06cf243 | 9210 | int level = 1; |
9ee6e8bb PB |
9211 | uint32_t table; |
9212 | uint32_t desc; | |
9213 | uint32_t xn; | |
de9b05b8 | 9214 | uint32_t pxn = 0; |
9ee6e8bb PB |
9215 | int type; |
9216 | int ap; | |
de9b05b8 | 9217 | int domain = 0; |
dd4ebc2e | 9218 | int domain_prot; |
a8170e5e | 9219 | hwaddr phys_addr; |
0480f69a | 9220 | uint32_t dacr; |
8bf5b6a9 | 9221 | bool ns; |
9ee6e8bb PB |
9222 | |
9223 | /* Pagetable walk. */ | |
9224 | /* Lookup l1 descriptor. */ | |
0480f69a | 9225 | if (!get_level1_table_address(env, mmu_idx, &table, address)) { |
e389be16 | 9226 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ |
f06cf243 | 9227 | fi->type = ARMFault_Translation; |
e389be16 FA |
9228 | goto do_fault; |
9229 | } | |
a614e698 | 9230 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 9231 | mmu_idx, fi); |
3b39d734 PM |
9232 | if (fi->type != ARMFault_None) { |
9233 | goto do_fault; | |
9234 | } | |
9ee6e8bb | 9235 | type = (desc & 3); |
de9b05b8 PM |
9236 | if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { |
9237 | /* Section translation fault, or attempt to use the encoding | |
9238 | * which is Reserved on implementations without PXN. | |
9239 | */ | |
f06cf243 | 9240 | fi->type = ARMFault_Translation; |
9ee6e8bb | 9241 | goto do_fault; |
de9b05b8 PM |
9242 | } |
9243 | if ((type == 1) || !(desc & (1 << 18))) { | |
9244 | /* Page or Section. */ | |
dd4ebc2e | 9245 | domain = (desc >> 5) & 0x0f; |
9ee6e8bb | 9246 | } |
0480f69a PM |
9247 | if (regime_el(env, mmu_idx) == 1) { |
9248 | dacr = env->cp15.dacr_ns; | |
9249 | } else { | |
9250 | dacr = env->cp15.dacr_s; | |
9251 | } | |
f06cf243 PM |
9252 | if (type == 1) { |
9253 | level = 2; | |
9254 | } | |
0480f69a | 9255 | domain_prot = (dacr >> (domain * 2)) & 3; |
dd4ebc2e | 9256 | if (domain_prot == 0 || domain_prot == 2) { |
f06cf243 PM |
9257 | /* Section or Page domain fault */ |
9258 | fi->type = ARMFault_Domain; | |
9ee6e8bb PB |
9259 | goto do_fault; |
9260 | } | |
de9b05b8 | 9261 | if (type != 1) { |
9ee6e8bb PB |
9262 | if (desc & (1 << 18)) { |
9263 | /* Supersection. */ | |
9264 | phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); | |
4e42a6ca SF |
9265 | phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32; |
9266 | phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36; | |
d4c430a8 | 9267 | *page_size = 0x1000000; |
b5ff1b31 | 9268 | } else { |
9ee6e8bb PB |
9269 | /* Section. */ |
9270 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
d4c430a8 | 9271 | *page_size = 0x100000; |
b5ff1b31 | 9272 | } |
9ee6e8bb PB |
9273 | ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
9274 | xn = desc & (1 << 4); | |
de9b05b8 | 9275 | pxn = desc & 1; |
8bf5b6a9 | 9276 | ns = extract32(desc, 19, 1); |
9ee6e8bb | 9277 | } else { |
de9b05b8 PM |
9278 | if (arm_feature(env, ARM_FEATURE_PXN)) { |
9279 | pxn = (desc >> 2) & 1; | |
9280 | } | |
8bf5b6a9 | 9281 | ns = extract32(desc, 3, 1); |
9ee6e8bb PB |
9282 | /* Lookup l2 entry. */ |
9283 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
a614e698 | 9284 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 9285 | mmu_idx, fi); |
3b39d734 PM |
9286 | if (fi->type != ARMFault_None) { |
9287 | goto do_fault; | |
9288 | } | |
9ee6e8bb PB |
9289 | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
9290 | switch (desc & 3) { | |
9291 | case 0: /* Page translation fault. */ | |
f06cf243 | 9292 | fi->type = ARMFault_Translation; |
b5ff1b31 | 9293 | goto do_fault; |
9ee6e8bb PB |
9294 | case 1: /* 64k page. */ |
9295 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
9296 | xn = desc & (1 << 15); | |
d4c430a8 | 9297 | *page_size = 0x10000; |
9ee6e8bb PB |
9298 | break; |
9299 | case 2: case 3: /* 4k page. */ | |
9300 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
9301 | xn = desc & 1; | |
d4c430a8 | 9302 | *page_size = 0x1000; |
9ee6e8bb PB |
9303 | break; |
9304 | default: | |
9305 | /* Never happens, but compiler isn't smart enough to tell. */ | |
9306 | abort(); | |
b5ff1b31 | 9307 | } |
9ee6e8bb | 9308 | } |
dd4ebc2e | 9309 | if (domain_prot == 3) { |
c0034328 JR |
9310 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
9311 | } else { | |
0480f69a | 9312 | if (pxn && !regime_is_user(env, mmu_idx)) { |
de9b05b8 PM |
9313 | xn = 1; |
9314 | } | |
f06cf243 PM |
9315 | if (xn && access_type == MMU_INST_FETCH) { |
9316 | fi->type = ARMFault_Permission; | |
c0034328 | 9317 | goto do_fault; |
f06cf243 | 9318 | } |
9ee6e8bb | 9319 | |
d76951b6 AJ |
9320 | if (arm_feature(env, ARM_FEATURE_V6K) && |
9321 | (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { | |
9322 | /* The simplified model uses AP[0] as an access control bit. */ | |
9323 | if ((ap & 1) == 0) { | |
9324 | /* Access flag fault. */ | |
f06cf243 | 9325 | fi->type = ARMFault_AccessFlag; |
d76951b6 AJ |
9326 | goto do_fault; |
9327 | } | |
9328 | *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); | |
9329 | } else { | |
9330 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); | |
c0034328 | 9331 | } |
0fbf5238 AJ |
9332 | if (*prot && !xn) { |
9333 | *prot |= PAGE_EXEC; | |
9334 | } | |
9335 | if (!(*prot & (1 << access_type))) { | |
c0034328 | 9336 | /* Access permission fault. */ |
f06cf243 | 9337 | fi->type = ARMFault_Permission; |
c0034328 JR |
9338 | goto do_fault; |
9339 | } | |
3ad493fc | 9340 | } |
8bf5b6a9 PM |
9341 | if (ns) { |
9342 | /* The NS bit will (as required by the architecture) have no effect if | |
9343 | * the CPU doesn't support TZ or this is a non-secure translation | |
9344 | * regime, because the attribute will already be non-secure. | |
9345 | */ | |
9346 | attrs->secure = false; | |
9347 | } | |
9ee6e8bb | 9348 | *phys_ptr = phys_addr; |
b7cc4e82 | 9349 | return false; |
b5ff1b31 | 9350 | do_fault: |
f06cf243 PM |
9351 | fi->domain = domain; |
9352 | fi->level = level; | |
b7cc4e82 | 9353 | return true; |
b5ff1b31 FB |
9354 | } |
9355 | ||
1853d5a9 | 9356 | /* |
a0e966c9 | 9357 | * check_s2_mmu_setup |
1853d5a9 EI |
9358 | * @cpu: ARMCPU |
9359 | * @is_aa64: True if the translation regime is in AArch64 state | |
9360 | * @startlevel: Suggested starting level | |
9361 | * @inputsize: Bitsize of IPAs | |
9362 | * @stride: Page-table stride (See the ARM ARM) | |
9363 | * | |
a0e966c9 EI |
9364 | * Returns true if the suggested S2 translation parameters are OK and |
9365 | * false otherwise. | |
1853d5a9 | 9366 | */ |
a0e966c9 EI |
9367 | static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, |
9368 | int inputsize, int stride) | |
1853d5a9 | 9369 | { |
98d68ec2 EI |
9370 | const int grainsize = stride + 3; |
9371 | int startsizecheck; | |
9372 | ||
1853d5a9 EI |
9373 | /* Negative levels are never allowed. */ |
9374 | if (level < 0) { | |
9375 | return false; | |
9376 | } | |
9377 | ||
98d68ec2 EI |
9378 | startsizecheck = inputsize - ((3 - level) * stride + grainsize); |
9379 | if (startsizecheck < 1 || startsizecheck > stride + 4) { | |
9380 | return false; | |
9381 | } | |
9382 | ||
1853d5a9 | 9383 | if (is_aa64) { |
3526423e | 9384 | CPUARMState *env = &cpu->env; |
1853d5a9 EI |
9385 | unsigned int pamax = arm_pamax(cpu); |
9386 | ||
9387 | switch (stride) { | |
9388 | case 13: /* 64KB Pages. */ | |
9389 | if (level == 0 || (level == 1 && pamax <= 42)) { | |
9390 | return false; | |
9391 | } | |
9392 | break; | |
9393 | case 11: /* 16KB Pages. */ | |
9394 | if (level == 0 || (level == 1 && pamax <= 40)) { | |
9395 | return false; | |
9396 | } | |
9397 | break; | |
9398 | case 9: /* 4KB Pages. */ | |
9399 | if (level == 0 && pamax <= 42) { | |
9400 | return false; | |
9401 | } | |
9402 | break; | |
9403 | default: | |
9404 | g_assert_not_reached(); | |
9405 | } | |
3526423e EI |
9406 | |
9407 | /* Inputsize checks. */ | |
9408 | if (inputsize > pamax && | |
9409 | (arm_el_is_aa64(env, 1) || inputsize > 40)) { | |
9410 | /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ | |
9411 | return false; | |
9412 | } | |
1853d5a9 | 9413 | } else { |
1853d5a9 EI |
9414 | /* AArch32 only supports 4KB pages. Assert on that. */ |
9415 | assert(stride == 9); | |
9416 | ||
9417 | if (level == 0) { | |
9418 | return false; | |
9419 | } | |
1853d5a9 EI |
9420 | } |
9421 | return true; | |
9422 | } | |
9423 | ||
5b2d261d AB |
9424 | /* Translate from the 4-bit stage 2 representation of |
9425 | * memory attributes (without cache-allocation hints) to | |
9426 | * the 8-bit representation of the stage 1 MAIR registers | |
9427 | * (which includes allocation hints). | |
9428 | * | |
9429 | * ref: shared/translation/attrs/S2AttrDecode() | |
9430 | * .../S2ConvertAttrsHints() | |
9431 | */ | |
9432 | static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) | |
9433 | { | |
9434 | uint8_t hiattr = extract32(s2attrs, 2, 2); | |
9435 | uint8_t loattr = extract32(s2attrs, 0, 2); | |
9436 | uint8_t hihint = 0, lohint = 0; | |
9437 | ||
9438 | if (hiattr != 0) { /* normal memory */ | |
9439 | if ((env->cp15.hcr_el2 & HCR_CD) != 0) { /* cache disabled */ | |
9440 | hiattr = loattr = 1; /* non-cacheable */ | |
9441 | } else { | |
9442 | if (hiattr != 1) { /* Write-through or write-back */ | |
9443 | hihint = 3; /* RW allocate */ | |
9444 | } | |
9445 | if (loattr != 1) { /* Write-through or write-back */ | |
9446 | lohint = 3; /* RW allocate */ | |
9447 | } | |
9448 | } | |
9449 | } | |
9450 | ||
9451 | return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; | |
9452 | } | |
c47eaf9f | 9453 | #endif /* !CONFIG_USER_ONLY */ |
5b2d261d | 9454 | |
e737ed2a RH |
9455 | ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, |
9456 | ARMMMUIdx mmu_idx) | |
ba97be9f RH |
9457 | { |
9458 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | |
9459 | uint32_t el = regime_el(env, mmu_idx); | |
8220af7e | 9460 | bool tbi, tbid, epd, hpd, using16k, using64k; |
ba97be9f RH |
9461 | int select, tsz; |
9462 | ||
9463 | /* | |
9464 | * Bit 55 is always between the two regions, and is canonical for | |
9465 | * determining if address tagging is enabled. | |
9466 | */ | |
9467 | select = extract64(va, 55, 1); | |
9468 | ||
9469 | if (el > 1) { | |
9470 | tsz = extract32(tcr, 0, 6); | |
9471 | using64k = extract32(tcr, 14, 1); | |
9472 | using16k = extract32(tcr, 15, 1); | |
9473 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
9474 | /* VTCR_EL2 */ | |
8220af7e | 9475 | tbi = tbid = hpd = false; |
ba97be9f RH |
9476 | } else { |
9477 | tbi = extract32(tcr, 20, 1); | |
9478 | hpd = extract32(tcr, 24, 1); | |
8220af7e | 9479 | tbid = extract32(tcr, 29, 1); |
ba97be9f RH |
9480 | } |
9481 | epd = false; | |
9482 | } else if (!select) { | |
9483 | tsz = extract32(tcr, 0, 6); | |
9484 | epd = extract32(tcr, 7, 1); | |
9485 | using64k = extract32(tcr, 14, 1); | |
9486 | using16k = extract32(tcr, 15, 1); | |
9487 | tbi = extract64(tcr, 37, 1); | |
9488 | hpd = extract64(tcr, 41, 1); | |
8220af7e | 9489 | tbid = extract64(tcr, 51, 1); |
ba97be9f RH |
9490 | } else { |
9491 | int tg = extract32(tcr, 30, 2); | |
9492 | using16k = tg == 1; | |
9493 | using64k = tg == 3; | |
9494 | tsz = extract32(tcr, 16, 6); | |
9495 | epd = extract32(tcr, 23, 1); | |
9496 | tbi = extract64(tcr, 38, 1); | |
9497 | hpd = extract64(tcr, 42, 1); | |
8220af7e | 9498 | tbid = extract64(tcr, 52, 1); |
ba97be9f RH |
9499 | } |
9500 | tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ | |
9501 | tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ | |
9502 | ||
9503 | return (ARMVAParameters) { | |
9504 | .tsz = tsz, | |
9505 | .select = select, | |
9506 | .tbi = tbi, | |
8220af7e | 9507 | .tbid = tbid, |
ba97be9f RH |
9508 | .epd = epd, |
9509 | .hpd = hpd, | |
9510 | .using16k = using16k, | |
9511 | .using64k = using64k, | |
9512 | }; | |
9513 | } | |
9514 | ||
e737ed2a RH |
9515 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, |
9516 | ARMMMUIdx mmu_idx, bool data) | |
9517 | { | |
8220af7e RH |
9518 | ARMVAParameters ret = aa64_va_parameters_both(env, va, mmu_idx); |
9519 | ||
9520 | /* Present TBI as a composite with TBID. */ | |
9521 | ret.tbi &= (data || !ret.tbid); | |
9522 | return ret; | |
e737ed2a RH |
9523 | } |
9524 | ||
c47eaf9f | 9525 | #ifndef CONFIG_USER_ONLY |
ba97be9f RH |
9526 | static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, |
9527 | ARMMMUIdx mmu_idx) | |
9528 | { | |
9529 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | |
9530 | uint32_t el = regime_el(env, mmu_idx); | |
9531 | int select, tsz; | |
9532 | bool epd, hpd; | |
9533 | ||
9534 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
9535 | /* VTCR */ | |
9536 | bool sext = extract32(tcr, 4, 1); | |
9537 | bool sign = extract32(tcr, 3, 1); | |
9538 | ||
9539 | /* | |
9540 | * If the sign-extend bit is not the same as t0sz[3], the result | |
9541 | * is unpredictable. Flag this as a guest error. | |
9542 | */ | |
9543 | if (sign != sext) { | |
9544 | qemu_log_mask(LOG_GUEST_ERROR, | |
9545 | "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); | |
9546 | } | |
9547 | tsz = sextract32(tcr, 0, 4) + 8; | |
9548 | select = 0; | |
9549 | hpd = false; | |
9550 | epd = false; | |
9551 | } else if (el == 2) { | |
9552 | /* HTCR */ | |
9553 | tsz = extract32(tcr, 0, 3); | |
9554 | select = 0; | |
9555 | hpd = extract64(tcr, 24, 1); | |
9556 | epd = false; | |
9557 | } else { | |
9558 | int t0sz = extract32(tcr, 0, 3); | |
9559 | int t1sz = extract32(tcr, 16, 3); | |
9560 | ||
9561 | if (t1sz == 0) { | |
9562 | select = va > (0xffffffffu >> t0sz); | |
9563 | } else { | |
9564 | /* Note that we will detect errors later. */ | |
9565 | select = va >= ~(0xffffffffu >> t1sz); | |
9566 | } | |
9567 | if (!select) { | |
9568 | tsz = t0sz; | |
9569 | epd = extract32(tcr, 7, 1); | |
9570 | hpd = extract64(tcr, 41, 1); | |
9571 | } else { | |
9572 | tsz = t1sz; | |
9573 | epd = extract32(tcr, 23, 1); | |
9574 | hpd = extract64(tcr, 42, 1); | |
9575 | } | |
9576 | /* For aarch32, hpd0 is not enabled without t2e as well. */ | |
9577 | hpd &= extract32(tcr, 6, 1); | |
9578 | } | |
9579 | ||
9580 | return (ARMVAParameters) { | |
9581 | .tsz = tsz, | |
9582 | .select = select, | |
9583 | .epd = epd, | |
9584 | .hpd = hpd, | |
9585 | }; | |
9586 | } | |
9587 | ||
b7cc4e82 | 9588 | static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
03ae85f8 | 9589 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
b7cc4e82 | 9590 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, |
da909b2c | 9591 | target_ulong *page_size_ptr, |
5b2d261d | 9592 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) |
3dde962f | 9593 | { |
2fc0cc0e | 9594 | ARMCPU *cpu = env_archcpu(env); |
1853d5a9 | 9595 | CPUState *cs = CPU(cpu); |
3dde962f | 9596 | /* Read an LPAE long-descriptor translation table. */ |
da909b2c | 9597 | ARMFaultType fault_type = ARMFault_Translation; |
1b4093ea | 9598 | uint32_t level; |
ba97be9f | 9599 | ARMVAParameters param; |
3dde962f | 9600 | uint64_t ttbr; |
dddb5223 | 9601 | hwaddr descaddr, indexmask, indexmask_grainsize; |
3dde962f | 9602 | uint32_t tableattrs; |
36d820af | 9603 | target_ulong page_size; |
3dde962f | 9604 | uint32_t attrs; |
ba97be9f RH |
9605 | int32_t stride; |
9606 | int addrsize, inputsize; | |
0480f69a | 9607 | TCR *tcr = regime_tcr(env, mmu_idx); |
d8e052b3 | 9608 | int ap, ns, xn, pxn; |
88e8add8 | 9609 | uint32_t el = regime_el(env, mmu_idx); |
ba97be9f | 9610 | bool ttbr1_valid; |
6109769a | 9611 | uint64_t descaddrmask; |
6e99f762 | 9612 | bool aarch64 = arm_el_is_aa64(env, el); |
1bafc2ba | 9613 | bool guarded = false; |
0480f69a PM |
9614 | |
9615 | /* TODO: | |
88e8add8 GB |
9616 | * This code does not handle the different format TCR for VTCR_EL2. |
9617 | * This code also does not support shareability levels. | |
9618 | * Attribute and permission bit handling should also be checked when adding | |
9619 | * support for those page table walks. | |
0480f69a | 9620 | */ |
6e99f762 | 9621 | if (aarch64) { |
ba97be9f RH |
9622 | param = aa64_va_parameters(env, address, mmu_idx, |
9623 | access_type != MMU_INST_FETCH); | |
1b4093ea | 9624 | level = 0; |
88e8add8 GB |
9625 | /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it |
9626 | * invalid. | |
9627 | */ | |
ba97be9f RH |
9628 | ttbr1_valid = (el < 2); |
9629 | addrsize = 64 - 8 * param.tbi; | |
9630 | inputsize = 64 - param.tsz; | |
d0a2cbce | 9631 | } else { |
ba97be9f | 9632 | param = aa32_va_parameters(env, address, mmu_idx); |
1b4093ea | 9633 | level = 1; |
d0a2cbce | 9634 | /* There is no TTBR1 for EL2 */ |
ba97be9f RH |
9635 | ttbr1_valid = (el != 2); |
9636 | addrsize = (mmu_idx == ARMMMUIdx_S2NS ? 40 : 32); | |
9637 | inputsize = addrsize - param.tsz; | |
2c8dd318 | 9638 | } |
3dde962f | 9639 | |
ba97be9f RH |
9640 | /* |
9641 | * We determined the region when collecting the parameters, but we | |
9642 | * have not yet validated that the address is valid for the region. | |
9643 | * Extract the top bits and verify that they all match select. | |
36d820af RH |
9644 | * |
9645 | * For aa32, if inputsize == addrsize, then we have selected the | |
9646 | * region by exclusion in aa32_va_parameters and there is no more | |
9647 | * validation to do here. | |
9648 | */ | |
9649 | if (inputsize < addrsize) { | |
9650 | target_ulong top_bits = sextract64(address, inputsize, | |
9651 | addrsize - inputsize); | |
9652 | if (-top_bits != param.select || (param.select && !ttbr1_valid)) { | |
9653 | /* The gap between the two regions is a Translation fault */ | |
9654 | fault_type = ARMFault_Translation; | |
9655 | goto do_fault; | |
9656 | } | |
3dde962f PM |
9657 | } |
9658 | ||
ba97be9f RH |
9659 | if (param.using64k) { |
9660 | stride = 13; | |
9661 | } else if (param.using16k) { | |
9662 | stride = 11; | |
9663 | } else { | |
9664 | stride = 9; | |
9665 | } | |
9666 | ||
3dde962f PM |
9667 | /* Note that QEMU ignores shareability and cacheability attributes, |
9668 | * so we don't need to do anything with the SH, ORGN, IRGN fields | |
9669 | * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the | |
9670 | * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently | |
9671 | * implement any ASID-like capability so we can ignore it (instead | |
9672 | * we will always flush the TLB any time the ASID is changed). | |
9673 | */ | |
ba97be9f | 9674 | ttbr = regime_ttbr(env, mmu_idx, param.select); |
3dde962f | 9675 | |
0480f69a | 9676 | /* Here we should have set up all the parameters for the translation: |
6e99f762 | 9677 | * inputsize, ttbr, epd, stride, tbi |
0480f69a PM |
9678 | */ |
9679 | ||
ba97be9f | 9680 | if (param.epd) { |
88e8add8 GB |
9681 | /* Translation table walk disabled => Translation fault on TLB miss |
9682 | * Note: This is always 0 on 64-bit EL2 and EL3. | |
9683 | */ | |
3dde962f PM |
9684 | goto do_fault; |
9685 | } | |
9686 | ||
1853d5a9 EI |
9687 | if (mmu_idx != ARMMMUIdx_S2NS) { |
9688 | /* The starting level depends on the virtual address size (which can | |
9689 | * be up to 48 bits) and the translation granule size. It indicates | |
9690 | * the number of strides (stride bits at a time) needed to | |
9691 | * consume the bits of the input address. In the pseudocode this is: | |
9692 | * level = 4 - RoundUp((inputsize - grainsize) / stride) | |
9693 | * where their 'inputsize' is our 'inputsize', 'grainsize' is | |
9694 | * our 'stride + 3' and 'stride' is our 'stride'. | |
9695 | * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: | |
9696 | * = 4 - (inputsize - stride - 3 + stride - 1) / stride | |
9697 | * = 4 - (inputsize - 4) / stride; | |
9698 | */ | |
9699 | level = 4 - (inputsize - 4) / stride; | |
9700 | } else { | |
9701 | /* For stage 2 translations the starting level is specified by the | |
9702 | * VTCR_EL2.SL0 field (whose interpretation depends on the page size) | |
9703 | */ | |
1b4093ea SS |
9704 | uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); |
9705 | uint32_t startlevel; | |
1853d5a9 EI |
9706 | bool ok; |
9707 | ||
6e99f762 | 9708 | if (!aarch64 || stride == 9) { |
1853d5a9 | 9709 | /* AArch32 or 4KB pages */ |
1b4093ea | 9710 | startlevel = 2 - sl0; |
1853d5a9 EI |
9711 | } else { |
9712 | /* 16KB or 64KB pages */ | |
1b4093ea | 9713 | startlevel = 3 - sl0; |
1853d5a9 EI |
9714 | } |
9715 | ||
9716 | /* Check that the starting level is valid. */ | |
6e99f762 | 9717 | ok = check_s2_mmu_setup(cpu, aarch64, startlevel, |
1b4093ea | 9718 | inputsize, stride); |
1853d5a9 | 9719 | if (!ok) { |
da909b2c | 9720 | fault_type = ARMFault_Translation; |
1853d5a9 EI |
9721 | goto do_fault; |
9722 | } | |
1b4093ea | 9723 | level = startlevel; |
1853d5a9 | 9724 | } |
3dde962f | 9725 | |
dddb5223 SS |
9726 | indexmask_grainsize = (1ULL << (stride + 3)) - 1; |
9727 | indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; | |
3dde962f PM |
9728 | |
9729 | /* Now we can extract the actual base address from the TTBR */ | |
2c8dd318 | 9730 | descaddr = extract64(ttbr, 0, 48); |
dddb5223 | 9731 | descaddr &= ~indexmask; |
3dde962f | 9732 | |
6109769a | 9733 | /* The address field in the descriptor goes up to bit 39 for ARMv7 |
dddb5223 SS |
9734 | * but up to bit 47 for ARMv8, but we use the descaddrmask |
9735 | * up to bit 39 for AArch32, because we don't need other bits in that case | |
9736 | * to construct next descriptor address (anyway they should be all zeroes). | |
6109769a | 9737 | */ |
6e99f762 | 9738 | descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) & |
dddb5223 | 9739 | ~indexmask_grainsize; |
6109769a | 9740 | |
ebca90e4 PM |
9741 | /* Secure accesses start with the page table in secure memory and |
9742 | * can be downgraded to non-secure at any step. Non-secure accesses | |
9743 | * remain non-secure. We implement this by just ORing in the NSTable/NS | |
9744 | * bits at each step. | |
9745 | */ | |
9746 | tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); | |
3dde962f PM |
9747 | for (;;) { |
9748 | uint64_t descriptor; | |
ebca90e4 | 9749 | bool nstable; |
3dde962f | 9750 | |
dddb5223 | 9751 | descaddr |= (address >> (stride * (4 - level))) & indexmask; |
2c8dd318 | 9752 | descaddr &= ~7ULL; |
ebca90e4 | 9753 | nstable = extract32(tableattrs, 4, 1); |
3795a6de | 9754 | descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi); |
3b39d734 | 9755 | if (fi->type != ARMFault_None) { |
37785977 EI |
9756 | goto do_fault; |
9757 | } | |
9758 | ||
3dde962f PM |
9759 | if (!(descriptor & 1) || |
9760 | (!(descriptor & 2) && (level == 3))) { | |
9761 | /* Invalid, or the Reserved level 3 encoding */ | |
9762 | goto do_fault; | |
9763 | } | |
6109769a | 9764 | descaddr = descriptor & descaddrmask; |
3dde962f PM |
9765 | |
9766 | if ((descriptor & 2) && (level < 3)) { | |
037c13c5 | 9767 | /* Table entry. The top five bits are attributes which may |
3dde962f PM |
9768 | * propagate down through lower levels of the table (and |
9769 | * which are all arranged so that 0 means "no effect", so | |
9770 | * we can gather them up by ORing in the bits at each level). | |
9771 | */ | |
9772 | tableattrs |= extract64(descriptor, 59, 5); | |
9773 | level++; | |
dddb5223 | 9774 | indexmask = indexmask_grainsize; |
3dde962f PM |
9775 | continue; |
9776 | } | |
9777 | /* Block entry at level 1 or 2, or page entry at level 3. | |
9778 | * These are basically the same thing, although the number | |
9779 | * of bits we pull in from the vaddr varies. | |
9780 | */ | |
973a5434 | 9781 | page_size = (1ULL << ((stride * (4 - level)) + 3)); |
3dde962f | 9782 | descaddr |= (address & (page_size - 1)); |
6ab1a5ee | 9783 | /* Extract attributes from the descriptor */ |
d615efac IC |
9784 | attrs = extract64(descriptor, 2, 10) |
9785 | | (extract64(descriptor, 52, 12) << 10); | |
6ab1a5ee EI |
9786 | |
9787 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
9788 | /* Stage 2 table descriptors do not include any attribute fields */ | |
9789 | break; | |
9790 | } | |
9791 | /* Merge in attributes from table descriptors */ | |
037c13c5 | 9792 | attrs |= nstable << 3; /* NS */ |
1bafc2ba | 9793 | guarded = extract64(descriptor, 50, 1); /* GP */ |
ba97be9f | 9794 | if (param.hpd) { |
037c13c5 RH |
9795 | /* HPD disables all the table attributes except NSTable. */ |
9796 | break; | |
9797 | } | |
9798 | attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ | |
3dde962f PM |
9799 | /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 |
9800 | * means "force PL1 access only", which means forcing AP[1] to 0. | |
9801 | */ | |
037c13c5 RH |
9802 | attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */ |
9803 | attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */ | |
3dde962f PM |
9804 | break; |
9805 | } | |
9806 | /* Here descaddr is the final physical address, and attributes | |
9807 | * are all in attrs. | |
9808 | */ | |
da909b2c | 9809 | fault_type = ARMFault_AccessFlag; |
3dde962f PM |
9810 | if ((attrs & (1 << 8)) == 0) { |
9811 | /* Access flag */ | |
9812 | goto do_fault; | |
9813 | } | |
d8e052b3 AJ |
9814 | |
9815 | ap = extract32(attrs, 4, 2); | |
d8e052b3 | 9816 | xn = extract32(attrs, 12, 1); |
d8e052b3 | 9817 | |
6ab1a5ee EI |
9818 | if (mmu_idx == ARMMMUIdx_S2NS) { |
9819 | ns = true; | |
9820 | *prot = get_S2prot(env, ap, xn); | |
9821 | } else { | |
9822 | ns = extract32(attrs, 3, 1); | |
9823 | pxn = extract32(attrs, 11, 1); | |
6e99f762 | 9824 | *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); |
6ab1a5ee | 9825 | } |
d8e052b3 | 9826 | |
da909b2c | 9827 | fault_type = ARMFault_Permission; |
d8e052b3 | 9828 | if (!(*prot & (1 << access_type))) { |
3dde962f PM |
9829 | goto do_fault; |
9830 | } | |
3dde962f | 9831 | |
8bf5b6a9 PM |
9832 | if (ns) { |
9833 | /* The NS bit will (as required by the architecture) have no effect if | |
9834 | * the CPU doesn't support TZ or this is a non-secure translation | |
9835 | * regime, because the attribute will already be non-secure. | |
9836 | */ | |
9837 | txattrs->secure = false; | |
9838 | } | |
1bafc2ba RH |
9839 | /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */ |
9840 | if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { | |
9841 | txattrs->target_tlb_bit0 = true; | |
9842 | } | |
5b2d261d AB |
9843 | |
9844 | if (cacheattrs != NULL) { | |
9845 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
9846 | cacheattrs->attrs = convert_stage2_attrs(env, | |
9847 | extract32(attrs, 0, 4)); | |
9848 | } else { | |
9849 | /* Index into MAIR registers for cache attributes */ | |
9850 | uint8_t attrindx = extract32(attrs, 0, 3); | |
9851 | uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; | |
9852 | assert(attrindx <= 7); | |
9853 | cacheattrs->attrs = extract64(mair, attrindx * 8, 8); | |
9854 | } | |
9855 | cacheattrs->shareability = extract32(attrs, 6, 2); | |
9856 | } | |
9857 | ||
3dde962f PM |
9858 | *phys_ptr = descaddr; |
9859 | *page_size_ptr = page_size; | |
b7cc4e82 | 9860 | return false; |
3dde962f PM |
9861 | |
9862 | do_fault: | |
da909b2c PM |
9863 | fi->type = fault_type; |
9864 | fi->level = level; | |
37785977 EI |
9865 | /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ |
9866 | fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS); | |
b7cc4e82 | 9867 | return true; |
3dde962f PM |
9868 | } |
9869 | ||
f6bda88f PC |
9870 | static inline void get_phys_addr_pmsav7_default(CPUARMState *env, |
9871 | ARMMMUIdx mmu_idx, | |
9872 | int32_t address, int *prot) | |
9873 | { | |
3a00d560 MD |
9874 | if (!arm_feature(env, ARM_FEATURE_M)) { |
9875 | *prot = PAGE_READ | PAGE_WRITE; | |
9876 | switch (address) { | |
9877 | case 0xF0000000 ... 0xFFFFFFFF: | |
9878 | if (regime_sctlr(env, mmu_idx) & SCTLR_V) { | |
9879 | /* hivecs execing is ok */ | |
9880 | *prot |= PAGE_EXEC; | |
9881 | } | |
9882 | break; | |
9883 | case 0x00000000 ... 0x7FFFFFFF: | |
f6bda88f | 9884 | *prot |= PAGE_EXEC; |
3a00d560 MD |
9885 | break; |
9886 | } | |
9887 | } else { | |
9888 | /* Default system address map for M profile cores. | |
9889 | * The architecture specifies which regions are execute-never; | |
9890 | * at the MPU level no other checks are defined. | |
9891 | */ | |
9892 | switch (address) { | |
9893 | case 0x00000000 ... 0x1fffffff: /* ROM */ | |
9894 | case 0x20000000 ... 0x3fffffff: /* SRAM */ | |
9895 | case 0x60000000 ... 0x7fffffff: /* RAM */ | |
9896 | case 0x80000000 ... 0x9fffffff: /* RAM */ | |
9897 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
9898 | break; | |
9899 | case 0x40000000 ... 0x5fffffff: /* Peripheral */ | |
9900 | case 0xa0000000 ... 0xbfffffff: /* Device */ | |
9901 | case 0xc0000000 ... 0xdfffffff: /* Device */ | |
9902 | case 0xe0000000 ... 0xffffffff: /* System */ | |
9903 | *prot = PAGE_READ | PAGE_WRITE; | |
9904 | break; | |
9905 | default: | |
9906 | g_assert_not_reached(); | |
f6bda88f | 9907 | } |
f6bda88f | 9908 | } |
f6bda88f PC |
9909 | } |
9910 | ||
29c483a5 MD |
9911 | static bool pmsav7_use_background_region(ARMCPU *cpu, |
9912 | ARMMMUIdx mmu_idx, bool is_user) | |
9913 | { | |
9914 | /* Return true if we should use the default memory map as a | |
9915 | * "background" region if there are no hits against any MPU regions. | |
9916 | */ | |
9917 | CPUARMState *env = &cpu->env; | |
9918 | ||
9919 | if (is_user) { | |
9920 | return false; | |
9921 | } | |
9922 | ||
9923 | if (arm_feature(env, ARM_FEATURE_M)) { | |
ecf5e8ea PM |
9924 | return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] |
9925 | & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; | |
29c483a5 MD |
9926 | } else { |
9927 | return regime_sctlr(env, mmu_idx) & SCTLR_BR; | |
9928 | } | |
9929 | } | |
9930 | ||
38aaa60c PM |
9931 | static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address) |
9932 | { | |
9933 | /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */ | |
9934 | return arm_feature(env, ARM_FEATURE_M) && | |
9935 | extract32(address, 20, 12) == 0xe00; | |
9936 | } | |
9937 | ||
bf446a11 PM |
9938 | static inline bool m_is_system_region(CPUARMState *env, uint32_t address) |
9939 | { | |
9940 | /* True if address is in the M profile system region | |
9941 | * 0xe0000000 - 0xffffffff | |
9942 | */ | |
9943 | return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7; | |
9944 | } | |
9945 | ||
f6bda88f | 9946 | static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, |
03ae85f8 | 9947 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
9375ad15 | 9948 | hwaddr *phys_ptr, int *prot, |
e5e40999 | 9949 | target_ulong *page_size, |
9375ad15 | 9950 | ARMMMUFaultInfo *fi) |
f6bda88f | 9951 | { |
2fc0cc0e | 9952 | ARMCPU *cpu = env_archcpu(env); |
f6bda88f PC |
9953 | int n; |
9954 | bool is_user = regime_is_user(env, mmu_idx); | |
9955 | ||
9956 | *phys_ptr = address; | |
e5e40999 | 9957 | *page_size = TARGET_PAGE_SIZE; |
f6bda88f PC |
9958 | *prot = 0; |
9959 | ||
38aaa60c PM |
9960 | if (regime_translation_disabled(env, mmu_idx) || |
9961 | m_is_ppb_region(env, address)) { | |
9962 | /* MPU disabled or M profile PPB access: use default memory map. | |
9963 | * The other case which uses the default memory map in the | |
9964 | * v7M ARM ARM pseudocode is exception vector reads from the vector | |
9965 | * table. In QEMU those accesses are done in arm_v7m_load_vector(), | |
9966 | * which always does a direct read using address_space_ldl(), rather | |
9967 | * than going via this function, so we don't need to check that here. | |
9968 | */ | |
f6bda88f PC |
9969 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); |
9970 | } else { /* MPU enabled */ | |
9971 | for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { | |
9972 | /* region search */ | |
9973 | uint32_t base = env->pmsav7.drbar[n]; | |
9974 | uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5); | |
9975 | uint32_t rmask; | |
9976 | bool srdis = false; | |
9977 | ||
9978 | if (!(env->pmsav7.drsr[n] & 0x1)) { | |
9979 | continue; | |
9980 | } | |
9981 | ||
9982 | if (!rsize) { | |
c9f9f124 MD |
9983 | qemu_log_mask(LOG_GUEST_ERROR, |
9984 | "DRSR[%d]: Rsize field cannot be 0\n", n); | |
f6bda88f PC |
9985 | continue; |
9986 | } | |
9987 | rsize++; | |
9988 | rmask = (1ull << rsize) - 1; | |
9989 | ||
9990 | if (base & rmask) { | |
c9f9f124 MD |
9991 | qemu_log_mask(LOG_GUEST_ERROR, |
9992 | "DRBAR[%d]: 0x%" PRIx32 " misaligned " | |
9993 | "to DRSR region size, mask = 0x%" PRIx32 "\n", | |
9994 | n, base, rmask); | |
f6bda88f PC |
9995 | continue; |
9996 | } | |
9997 | ||
9998 | if (address < base || address > base + rmask) { | |
9d2b5a58 PM |
9999 | /* |
10000 | * Address not in this region. We must check whether the | |
10001 | * region covers addresses in the same page as our address. | |
10002 | * In that case we must not report a size that covers the | |
10003 | * whole page for a subsequent hit against a different MPU | |
10004 | * region or the background region, because it would result in | |
10005 | * incorrect TLB hits for subsequent accesses to addresses that | |
10006 | * are in this MPU region. | |
10007 | */ | |
10008 | if (ranges_overlap(base, rmask, | |
10009 | address & TARGET_PAGE_MASK, | |
10010 | TARGET_PAGE_SIZE)) { | |
10011 | *page_size = 1; | |
10012 | } | |
f6bda88f PC |
10013 | continue; |
10014 | } | |
10015 | ||
10016 | /* Region matched */ | |
10017 | ||
10018 | if (rsize >= 8) { /* no subregions for regions < 256 bytes */ | |
10019 | int i, snd; | |
10020 | uint32_t srdis_mask; | |
10021 | ||
10022 | rsize -= 3; /* sub region size (power of 2) */ | |
10023 | snd = ((address - base) >> rsize) & 0x7; | |
10024 | srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1); | |
10025 | ||
10026 | srdis_mask = srdis ? 0x3 : 0x0; | |
10027 | for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) { | |
10028 | /* This will check in groups of 2, 4 and then 8, whether | |
10029 | * the subregion bits are consistent. rsize is incremented | |
10030 | * back up to give the region size, considering consistent | |
10031 | * adjacent subregions as one region. Stop testing if rsize | |
10032 | * is already big enough for an entire QEMU page. | |
10033 | */ | |
10034 | int snd_rounded = snd & ~(i - 1); | |
10035 | uint32_t srdis_multi = extract32(env->pmsav7.drsr[n], | |
10036 | snd_rounded + 8, i); | |
10037 | if (srdis_mask ^ srdis_multi) { | |
10038 | break; | |
10039 | } | |
10040 | srdis_mask = (srdis_mask << i) | srdis_mask; | |
10041 | rsize++; | |
10042 | } | |
10043 | } | |
f6bda88f PC |
10044 | if (srdis) { |
10045 | continue; | |
10046 | } | |
e5e40999 PM |
10047 | if (rsize < TARGET_PAGE_BITS) { |
10048 | *page_size = 1 << rsize; | |
10049 | } | |
f6bda88f PC |
10050 | break; |
10051 | } | |
10052 | ||
10053 | if (n == -1) { /* no hits */ | |
29c483a5 | 10054 | if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { |
f6bda88f | 10055 | /* background fault */ |
9375ad15 | 10056 | fi->type = ARMFault_Background; |
f6bda88f PC |
10057 | return true; |
10058 | } | |
10059 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | |
10060 | } else { /* a MPU hit! */ | |
10061 | uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); | |
bf446a11 PM |
10062 | uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1); |
10063 | ||
10064 | if (m_is_system_region(env, address)) { | |
10065 | /* System space is always execute never */ | |
10066 | xn = 1; | |
10067 | } | |
f6bda88f PC |
10068 | |
10069 | if (is_user) { /* User mode AP bit decoding */ | |
10070 | switch (ap) { | |
10071 | case 0: | |
10072 | case 1: | |
10073 | case 5: | |
10074 | break; /* no access */ | |
10075 | case 3: | |
10076 | *prot |= PAGE_WRITE; | |
10077 | /* fall through */ | |
10078 | case 2: | |
10079 | case 6: | |
10080 | *prot |= PAGE_READ | PAGE_EXEC; | |
10081 | break; | |
8638f1ad PM |
10082 | case 7: |
10083 | /* for v7M, same as 6; for R profile a reserved value */ | |
10084 | if (arm_feature(env, ARM_FEATURE_M)) { | |
10085 | *prot |= PAGE_READ | PAGE_EXEC; | |
10086 | break; | |
10087 | } | |
10088 | /* fall through */ | |
f6bda88f PC |
10089 | default: |
10090 | qemu_log_mask(LOG_GUEST_ERROR, | |
c9f9f124 MD |
10091 | "DRACR[%d]: Bad value for AP bits: 0x%" |
10092 | PRIx32 "\n", n, ap); | |
f6bda88f PC |
10093 | } |
10094 | } else { /* Priv. mode AP bits decoding */ | |
10095 | switch (ap) { | |
10096 | case 0: | |
10097 | break; /* no access */ | |
10098 | case 1: | |
10099 | case 2: | |
10100 | case 3: | |
10101 | *prot |= PAGE_WRITE; | |
10102 | /* fall through */ | |
10103 | case 5: | |
10104 | case 6: | |
10105 | *prot |= PAGE_READ | PAGE_EXEC; | |
10106 | break; | |
8638f1ad PM |
10107 | case 7: |
10108 | /* for v7M, same as 6; for R profile a reserved value */ | |
10109 | if (arm_feature(env, ARM_FEATURE_M)) { | |
10110 | *prot |= PAGE_READ | PAGE_EXEC; | |
10111 | break; | |
10112 | } | |
10113 | /* fall through */ | |
f6bda88f PC |
10114 | default: |
10115 | qemu_log_mask(LOG_GUEST_ERROR, | |
c9f9f124 MD |
10116 | "DRACR[%d]: Bad value for AP bits: 0x%" |
10117 | PRIx32 "\n", n, ap); | |
f6bda88f PC |
10118 | } |
10119 | } | |
10120 | ||
10121 | /* execute never */ | |
bf446a11 | 10122 | if (xn) { |
f6bda88f PC |
10123 | *prot &= ~PAGE_EXEC; |
10124 | } | |
10125 | } | |
10126 | } | |
10127 | ||
9375ad15 PM |
10128 | fi->type = ARMFault_Permission; |
10129 | fi->level = 1; | |
f6bda88f PC |
10130 | return !(*prot & (1 << access_type)); |
10131 | } | |
10132 | ||
35337cc3 PM |
10133 | static bool v8m_is_sau_exempt(CPUARMState *env, |
10134 | uint32_t address, MMUAccessType access_type) | |
10135 | { | |
10136 | /* The architecture specifies that certain address ranges are | |
10137 | * exempt from v8M SAU/IDAU checks. | |
10138 | */ | |
10139 | return | |
10140 | (access_type == MMU_INST_FETCH && m_is_system_region(env, address)) || | |
10141 | (address >= 0xe0000000 && address <= 0xe0002fff) || | |
10142 | (address >= 0xe000e000 && address <= 0xe000efff) || | |
10143 | (address >= 0xe002e000 && address <= 0xe002efff) || | |
10144 | (address >= 0xe0040000 && address <= 0xe0041fff) || | |
10145 | (address >= 0xe00ff000 && address <= 0xe00fffff); | |
10146 | } | |
10147 | ||
787a7e76 | 10148 | void v8m_security_lookup(CPUARMState *env, uint32_t address, |
35337cc3 PM |
10149 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
10150 | V8M_SAttributes *sattrs) | |
10151 | { | |
10152 | /* Look up the security attributes for this address. Compare the | |
10153 | * pseudocode SecurityCheck() function. | |
10154 | * We assume the caller has zero-initialized *sattrs. | |
10155 | */ | |
2fc0cc0e | 10156 | ARMCPU *cpu = env_archcpu(env); |
35337cc3 | 10157 | int r; |
181962fd PM |
10158 | bool idau_exempt = false, idau_ns = true, idau_nsc = true; |
10159 | int idau_region = IREGION_NOTVALID; | |
72042435 PM |
10160 | uint32_t addr_page_base = address & TARGET_PAGE_MASK; |
10161 | uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); | |
35337cc3 | 10162 | |
181962fd PM |
10163 | if (cpu->idau) { |
10164 | IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau); | |
10165 | IDAUInterface *ii = IDAU_INTERFACE(cpu->idau); | |
10166 | ||
10167 | iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns, | |
10168 | &idau_nsc); | |
10169 | } | |
35337cc3 PM |
10170 | |
10171 | if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) { | |
10172 | /* 0xf0000000..0xffffffff is always S for insn fetches */ | |
10173 | return; | |
10174 | } | |
10175 | ||
181962fd | 10176 | if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) { |
35337cc3 PM |
10177 | sattrs->ns = !regime_is_secure(env, mmu_idx); |
10178 | return; | |
10179 | } | |
10180 | ||
181962fd PM |
10181 | if (idau_region != IREGION_NOTVALID) { |
10182 | sattrs->irvalid = true; | |
10183 | sattrs->iregion = idau_region; | |
10184 | } | |
10185 | ||
35337cc3 PM |
10186 | switch (env->sau.ctrl & 3) { |
10187 | case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */ | |
10188 | break; | |
10189 | case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */ | |
10190 | sattrs->ns = true; | |
10191 | break; | |
10192 | default: /* SAU.ENABLE == 1 */ | |
10193 | for (r = 0; r < cpu->sau_sregion; r++) { | |
10194 | if (env->sau.rlar[r] & 1) { | |
10195 | uint32_t base = env->sau.rbar[r] & ~0x1f; | |
10196 | uint32_t limit = env->sau.rlar[r] | 0x1f; | |
10197 | ||
10198 | if (base <= address && limit >= address) { | |
72042435 PM |
10199 | if (base > addr_page_base || limit < addr_page_limit) { |
10200 | sattrs->subpage = true; | |
10201 | } | |
35337cc3 PM |
10202 | if (sattrs->srvalid) { |
10203 | /* If we hit in more than one region then we must report | |
10204 | * as Secure, not NS-Callable, with no valid region | |
10205 | * number info. | |
10206 | */ | |
10207 | sattrs->ns = false; | |
10208 | sattrs->nsc = false; | |
10209 | sattrs->sregion = 0; | |
10210 | sattrs->srvalid = false; | |
10211 | break; | |
10212 | } else { | |
10213 | if (env->sau.rlar[r] & 2) { | |
10214 | sattrs->nsc = true; | |
10215 | } else { | |
10216 | sattrs->ns = true; | |
10217 | } | |
10218 | sattrs->srvalid = true; | |
10219 | sattrs->sregion = r; | |
10220 | } | |
9d2b5a58 PM |
10221 | } else { |
10222 | /* | |
10223 | * Address not in this region. We must check whether the | |
10224 | * region covers addresses in the same page as our address. | |
10225 | * In that case we must not report a size that covers the | |
10226 | * whole page for a subsequent hit against a different MPU | |
10227 | * region or the background region, because it would result | |
10228 | * in incorrect TLB hits for subsequent accesses to | |
10229 | * addresses that are in this MPU region. | |
10230 | */ | |
10231 | if (limit >= base && | |
10232 | ranges_overlap(base, limit - base + 1, | |
10233 | addr_page_base, | |
10234 | TARGET_PAGE_SIZE)) { | |
10235 | sattrs->subpage = true; | |
10236 | } | |
35337cc3 PM |
10237 | } |
10238 | } | |
10239 | } | |
7e3f1223 TR |
10240 | break; |
10241 | } | |
35337cc3 | 10242 | |
7e3f1223 TR |
10243 | /* |
10244 | * The IDAU will override the SAU lookup results if it specifies | |
10245 | * higher security than the SAU does. | |
10246 | */ | |
10247 | if (!idau_ns) { | |
10248 | if (sattrs->ns || (!idau_nsc && sattrs->nsc)) { | |
10249 | sattrs->ns = false; | |
10250 | sattrs->nsc = idau_nsc; | |
181962fd | 10251 | } |
35337cc3 PM |
10252 | } |
10253 | } | |
10254 | ||
787a7e76 | 10255 | bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, |
54317c0f PM |
10256 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
10257 | hwaddr *phys_ptr, MemTxAttrs *txattrs, | |
72042435 PM |
10258 | int *prot, bool *is_subpage, |
10259 | ARMMMUFaultInfo *fi, uint32_t *mregion) | |
54317c0f PM |
10260 | { |
10261 | /* Perform a PMSAv8 MPU lookup (without also doing the SAU check | |
10262 | * that a full phys-to-virt translation does). | |
10263 | * mregion is (if not NULL) set to the region number which matched, | |
10264 | * or -1 if no region number is returned (MPU off, address did not | |
10265 | * hit a region, address hit in multiple regions). | |
72042435 PM |
10266 | * We set is_subpage to true if the region hit doesn't cover the |
10267 | * entire TARGET_PAGE the address is within. | |
54317c0f | 10268 | */ |
2fc0cc0e | 10269 | ARMCPU *cpu = env_archcpu(env); |
504e3cc3 | 10270 | bool is_user = regime_is_user(env, mmu_idx); |
62c58ee0 | 10271 | uint32_t secure = regime_is_secure(env, mmu_idx); |
504e3cc3 PM |
10272 | int n; |
10273 | int matchregion = -1; | |
10274 | bool hit = false; | |
72042435 PM |
10275 | uint32_t addr_page_base = address & TARGET_PAGE_MASK; |
10276 | uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); | |
504e3cc3 | 10277 | |
72042435 | 10278 | *is_subpage = false; |
504e3cc3 PM |
10279 | *phys_ptr = address; |
10280 | *prot = 0; | |
54317c0f PM |
10281 | if (mregion) { |
10282 | *mregion = -1; | |
35337cc3 PM |
10283 | } |
10284 | ||
504e3cc3 PM |
10285 | /* Unlike the ARM ARM pseudocode, we don't need to check whether this |
10286 | * was an exception vector read from the vector table (which is always | |
10287 | * done using the default system address map), because those accesses | |
10288 | * are done in arm_v7m_load_vector(), which always does a direct | |
10289 | * read using address_space_ldl(), rather than going via this function. | |
10290 | */ | |
10291 | if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ | |
10292 | hit = true; | |
10293 | } else if (m_is_ppb_region(env, address)) { | |
10294 | hit = true; | |
504e3cc3 | 10295 | } else { |
cff21316 PM |
10296 | if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) { |
10297 | hit = true; | |
10298 | } | |
10299 | ||
504e3cc3 PM |
10300 | for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { |
10301 | /* region search */ | |
10302 | /* Note that the base address is bits [31:5] from the register | |
10303 | * with bits [4:0] all zeroes, but the limit address is bits | |
10304 | * [31:5] from the register with bits [4:0] all ones. | |
10305 | */ | |
62c58ee0 PM |
10306 | uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f; |
10307 | uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f; | |
504e3cc3 | 10308 | |
62c58ee0 | 10309 | if (!(env->pmsav8.rlar[secure][n] & 0x1)) { |
504e3cc3 PM |
10310 | /* Region disabled */ |
10311 | continue; | |
10312 | } | |
10313 | ||
10314 | if (address < base || address > limit) { | |
9d2b5a58 PM |
10315 | /* |
10316 | * Address not in this region. We must check whether the | |
10317 | * region covers addresses in the same page as our address. | |
10318 | * In that case we must not report a size that covers the | |
10319 | * whole page for a subsequent hit against a different MPU | |
10320 | * region or the background region, because it would result in | |
10321 | * incorrect TLB hits for subsequent accesses to addresses that | |
10322 | * are in this MPU region. | |
10323 | */ | |
10324 | if (limit >= base && | |
10325 | ranges_overlap(base, limit - base + 1, | |
10326 | addr_page_base, | |
10327 | TARGET_PAGE_SIZE)) { | |
10328 | *is_subpage = true; | |
10329 | } | |
504e3cc3 PM |
10330 | continue; |
10331 | } | |
10332 | ||
72042435 PM |
10333 | if (base > addr_page_base || limit < addr_page_limit) { |
10334 | *is_subpage = true; | |
10335 | } | |
10336 | ||
cff21316 | 10337 | if (matchregion != -1) { |
504e3cc3 PM |
10338 | /* Multiple regions match -- always a failure (unlike |
10339 | * PMSAv7 where highest-numbered-region wins) | |
10340 | */ | |
3f551b5b PM |
10341 | fi->type = ARMFault_Permission; |
10342 | fi->level = 1; | |
504e3cc3 PM |
10343 | return true; |
10344 | } | |
10345 | ||
10346 | matchregion = n; | |
10347 | hit = true; | |
504e3cc3 PM |
10348 | } |
10349 | } | |
10350 | ||
10351 | if (!hit) { | |
10352 | /* background fault */ | |
3f551b5b | 10353 | fi->type = ARMFault_Background; |
504e3cc3 PM |
10354 | return true; |
10355 | } | |
10356 | ||
10357 | if (matchregion == -1) { | |
10358 | /* hit using the background region */ | |
10359 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | |
10360 | } else { | |
62c58ee0 PM |
10361 | uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2); |
10362 | uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1); | |
504e3cc3 PM |
10363 | |
10364 | if (m_is_system_region(env, address)) { | |
10365 | /* System space is always execute never */ | |
10366 | xn = 1; | |
10367 | } | |
10368 | ||
10369 | *prot = simple_ap_to_rw_prot(env, mmu_idx, ap); | |
10370 | if (*prot && !xn) { | |
10371 | *prot |= PAGE_EXEC; | |
10372 | } | |
10373 | /* We don't need to look the attribute up in the MAIR0/MAIR1 | |
10374 | * registers because that only tells us about cacheability. | |
10375 | */ | |
54317c0f PM |
10376 | if (mregion) { |
10377 | *mregion = matchregion; | |
10378 | } | |
504e3cc3 PM |
10379 | } |
10380 | ||
3f551b5b PM |
10381 | fi->type = ARMFault_Permission; |
10382 | fi->level = 1; | |
504e3cc3 PM |
10383 | return !(*prot & (1 << access_type)); |
10384 | } | |
10385 | ||
54317c0f PM |
10386 | |
10387 | static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, | |
10388 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
10389 | hwaddr *phys_ptr, MemTxAttrs *txattrs, | |
72042435 PM |
10390 | int *prot, target_ulong *page_size, |
10391 | ARMMMUFaultInfo *fi) | |
54317c0f PM |
10392 | { |
10393 | uint32_t secure = regime_is_secure(env, mmu_idx); | |
10394 | V8M_SAttributes sattrs = {}; | |
72042435 PM |
10395 | bool ret; |
10396 | bool mpu_is_subpage; | |
54317c0f PM |
10397 | |
10398 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
10399 | v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs); | |
10400 | if (access_type == MMU_INST_FETCH) { | |
10401 | /* Instruction fetches always use the MMU bank and the | |
10402 | * transaction attribute determined by the fetch address, | |
10403 | * regardless of CPU state. This is painful for QEMU | |
10404 | * to handle, because it would mean we need to encode | |
10405 | * into the mmu_idx not just the (user, negpri) information | |
10406 | * for the current security state but also that for the | |
10407 | * other security state, which would balloon the number | |
10408 | * of mmu_idx values needed alarmingly. | |
10409 | * Fortunately we can avoid this because it's not actually | |
10410 | * possible to arbitrarily execute code from memory with | |
10411 | * the wrong security attribute: it will always generate | |
10412 | * an exception of some kind or another, apart from the | |
10413 | * special case of an NS CPU executing an SG instruction | |
10414 | * in S&NSC memory. So we always just fail the translation | |
10415 | * here and sort things out in the exception handler | |
10416 | * (including possibly emulating an SG instruction). | |
10417 | */ | |
10418 | if (sattrs.ns != !secure) { | |
3f551b5b PM |
10419 | if (sattrs.nsc) { |
10420 | fi->type = ARMFault_QEMU_NSCExec; | |
10421 | } else { | |
10422 | fi->type = ARMFault_QEMU_SFault; | |
10423 | } | |
72042435 | 10424 | *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; |
54317c0f PM |
10425 | *phys_ptr = address; |
10426 | *prot = 0; | |
10427 | return true; | |
10428 | } | |
10429 | } else { | |
10430 | /* For data accesses we always use the MMU bank indicated | |
10431 | * by the current CPU state, but the security attributes | |
10432 | * might downgrade a secure access to nonsecure. | |
10433 | */ | |
10434 | if (sattrs.ns) { | |
10435 | txattrs->secure = false; | |
10436 | } else if (!secure) { | |
10437 | /* NS access to S memory must fault. | |
10438 | * Architecturally we should first check whether the | |
10439 | * MPU information for this address indicates that we | |
10440 | * are doing an unaligned access to Device memory, which | |
10441 | * should generate a UsageFault instead. QEMU does not | |
10442 | * currently check for that kind of unaligned access though. | |
10443 | * If we added it we would need to do so as a special case | |
10444 | * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). | |
10445 | */ | |
3f551b5b | 10446 | fi->type = ARMFault_QEMU_SFault; |
72042435 | 10447 | *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; |
54317c0f PM |
10448 | *phys_ptr = address; |
10449 | *prot = 0; | |
10450 | return true; | |
10451 | } | |
10452 | } | |
10453 | } | |
10454 | ||
72042435 PM |
10455 | ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, |
10456 | txattrs, prot, &mpu_is_subpage, fi, NULL); | |
72042435 PM |
10457 | *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; |
10458 | return ret; | |
54317c0f PM |
10459 | } |
10460 | ||
13689d43 | 10461 | static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, |
03ae85f8 | 10462 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
53a4e5c5 PM |
10463 | hwaddr *phys_ptr, int *prot, |
10464 | ARMMMUFaultInfo *fi) | |
9ee6e8bb PB |
10465 | { |
10466 | int n; | |
10467 | uint32_t mask; | |
10468 | uint32_t base; | |
0480f69a | 10469 | bool is_user = regime_is_user(env, mmu_idx); |
9ee6e8bb | 10470 | |
3279adb9 PM |
10471 | if (regime_translation_disabled(env, mmu_idx)) { |
10472 | /* MPU disabled. */ | |
10473 | *phys_ptr = address; | |
10474 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
10475 | return false; | |
10476 | } | |
10477 | ||
9ee6e8bb PB |
10478 | *phys_ptr = address; |
10479 | for (n = 7; n >= 0; n--) { | |
554b0b09 | 10480 | base = env->cp15.c6_region[n]; |
87c3d486 | 10481 | if ((base & 1) == 0) { |
554b0b09 | 10482 | continue; |
87c3d486 | 10483 | } |
554b0b09 PM |
10484 | mask = 1 << ((base >> 1) & 0x1f); |
10485 | /* Keep this shift separate from the above to avoid an | |
10486 | (undefined) << 32. */ | |
10487 | mask = (mask << 1) - 1; | |
87c3d486 | 10488 | if (((base ^ address) & ~mask) == 0) { |
554b0b09 | 10489 | break; |
87c3d486 | 10490 | } |
9ee6e8bb | 10491 | } |
87c3d486 | 10492 | if (n < 0) { |
53a4e5c5 | 10493 | fi->type = ARMFault_Background; |
b7cc4e82 | 10494 | return true; |
87c3d486 | 10495 | } |
9ee6e8bb | 10496 | |
03ae85f8 | 10497 | if (access_type == MMU_INST_FETCH) { |
7e09797c | 10498 | mask = env->cp15.pmsav5_insn_ap; |
9ee6e8bb | 10499 | } else { |
7e09797c | 10500 | mask = env->cp15.pmsav5_data_ap; |
9ee6e8bb PB |
10501 | } |
10502 | mask = (mask >> (n * 4)) & 0xf; | |
10503 | switch (mask) { | |
10504 | case 0: | |
53a4e5c5 PM |
10505 | fi->type = ARMFault_Permission; |
10506 | fi->level = 1; | |
b7cc4e82 | 10507 | return true; |
9ee6e8bb | 10508 | case 1: |
87c3d486 | 10509 | if (is_user) { |
53a4e5c5 PM |
10510 | fi->type = ARMFault_Permission; |
10511 | fi->level = 1; | |
b7cc4e82 | 10512 | return true; |
87c3d486 | 10513 | } |
554b0b09 PM |
10514 | *prot = PAGE_READ | PAGE_WRITE; |
10515 | break; | |
9ee6e8bb | 10516 | case 2: |
554b0b09 | 10517 | *prot = PAGE_READ; |
87c3d486 | 10518 | if (!is_user) { |
554b0b09 | 10519 | *prot |= PAGE_WRITE; |
87c3d486 | 10520 | } |
554b0b09 | 10521 | break; |
9ee6e8bb | 10522 | case 3: |
554b0b09 PM |
10523 | *prot = PAGE_READ | PAGE_WRITE; |
10524 | break; | |
9ee6e8bb | 10525 | case 5: |
87c3d486 | 10526 | if (is_user) { |
53a4e5c5 PM |
10527 | fi->type = ARMFault_Permission; |
10528 | fi->level = 1; | |
b7cc4e82 | 10529 | return true; |
87c3d486 | 10530 | } |
554b0b09 PM |
10531 | *prot = PAGE_READ; |
10532 | break; | |
9ee6e8bb | 10533 | case 6: |
554b0b09 PM |
10534 | *prot = PAGE_READ; |
10535 | break; | |
9ee6e8bb | 10536 | default: |
554b0b09 | 10537 | /* Bad permission. */ |
53a4e5c5 PM |
10538 | fi->type = ARMFault_Permission; |
10539 | fi->level = 1; | |
b7cc4e82 | 10540 | return true; |
9ee6e8bb | 10541 | } |
3ad493fc | 10542 | *prot |= PAGE_EXEC; |
b7cc4e82 | 10543 | return false; |
9ee6e8bb PB |
10544 | } |
10545 | ||
5b2d261d AB |
10546 | /* Combine either inner or outer cacheability attributes for normal |
10547 | * memory, according to table D4-42 and pseudocode procedure | |
10548 | * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). | |
10549 | * | |
10550 | * NB: only stage 1 includes allocation hints (RW bits), leading to | |
10551 | * some asymmetry. | |
10552 | */ | |
10553 | static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2) | |
10554 | { | |
10555 | if (s1 == 4 || s2 == 4) { | |
10556 | /* non-cacheable has precedence */ | |
10557 | return 4; | |
10558 | } else if (extract32(s1, 2, 2) == 0 || extract32(s1, 2, 2) == 2) { | |
10559 | /* stage 1 write-through takes precedence */ | |
10560 | return s1; | |
10561 | } else if (extract32(s2, 2, 2) == 2) { | |
10562 | /* stage 2 write-through takes precedence, but the allocation hint | |
10563 | * is still taken from stage 1 | |
10564 | */ | |
10565 | return (2 << 2) | extract32(s1, 0, 2); | |
10566 | } else { /* write-back */ | |
10567 | return s1; | |
10568 | } | |
10569 | } | |
10570 | ||
10571 | /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 | |
10572 | * and CombineS1S2Desc() | |
10573 | * | |
10574 | * @s1: Attributes from stage 1 walk | |
10575 | * @s2: Attributes from stage 2 walk | |
10576 | */ | |
10577 | static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) | |
10578 | { | |
10579 | uint8_t s1lo = extract32(s1.attrs, 0, 4), s2lo = extract32(s2.attrs, 0, 4); | |
10580 | uint8_t s1hi = extract32(s1.attrs, 4, 4), s2hi = extract32(s2.attrs, 4, 4); | |
10581 | ARMCacheAttrs ret; | |
10582 | ||
10583 | /* Combine shareability attributes (table D4-43) */ | |
10584 | if (s1.shareability == 2 || s2.shareability == 2) { | |
10585 | /* if either are outer-shareable, the result is outer-shareable */ | |
10586 | ret.shareability = 2; | |
10587 | } else if (s1.shareability == 3 || s2.shareability == 3) { | |
10588 | /* if either are inner-shareable, the result is inner-shareable */ | |
10589 | ret.shareability = 3; | |
10590 | } else { | |
10591 | /* both non-shareable */ | |
10592 | ret.shareability = 0; | |
10593 | } | |
10594 | ||
10595 | /* Combine memory type and cacheability attributes */ | |
10596 | if (s1hi == 0 || s2hi == 0) { | |
10597 | /* Device has precedence over normal */ | |
10598 | if (s1lo == 0 || s2lo == 0) { | |
10599 | /* nGnRnE has precedence over anything */ | |
10600 | ret.attrs = 0; | |
10601 | } else if (s1lo == 4 || s2lo == 4) { | |
10602 | /* non-Reordering has precedence over Reordering */ | |
10603 | ret.attrs = 4; /* nGnRE */ | |
10604 | } else if (s1lo == 8 || s2lo == 8) { | |
10605 | /* non-Gathering has precedence over Gathering */ | |
10606 | ret.attrs = 8; /* nGRE */ | |
10607 | } else { | |
10608 | ret.attrs = 0xc; /* GRE */ | |
10609 | } | |
10610 | ||
10611 | /* Any location for which the resultant memory type is any | |
10612 | * type of Device memory is always treated as Outer Shareable. | |
10613 | */ | |
10614 | ret.shareability = 2; | |
10615 | } else { /* Normal memory */ | |
10616 | /* Outer/inner cacheability combine independently */ | |
10617 | ret.attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4 | |
10618 | | combine_cacheattr_nibble(s1lo, s2lo); | |
10619 | ||
10620 | if (ret.attrs == 0x44) { | |
10621 | /* Any location for which the resultant memory type is Normal | |
10622 | * Inner Non-cacheable, Outer Non-cacheable is always treated | |
10623 | * as Outer Shareable. | |
10624 | */ | |
10625 | ret.shareability = 2; | |
10626 | } | |
10627 | } | |
10628 | ||
10629 | return ret; | |
10630 | } | |
10631 | ||
10632 | ||
702a9357 PM |
10633 | /* get_phys_addr - get the physical address for this virtual address |
10634 | * | |
10635 | * Find the physical address corresponding to the given virtual address, | |
10636 | * by doing a translation table walk on MMU based systems or using the | |
10637 | * MPU state on MPU based systems. | |
10638 | * | |
b7cc4e82 PC |
10639 | * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, |
10640 | * prot and page_size may not be filled in, and the populated fsr value provides | |
702a9357 PM |
10641 | * information on why the translation aborted, in the format of a |
10642 | * DFSR/IFSR fault register, with the following caveats: | |
10643 | * * we honour the short vs long DFSR format differences. | |
10644 | * * the WnR bit is never set (the caller must do this). | |
f6bda88f | 10645 | * * for PSMAv5 based systems we don't bother to return a full FSR format |
702a9357 PM |
10646 | * value. |
10647 | * | |
10648 | * @env: CPUARMState | |
10649 | * @address: virtual address to get physical address for | |
10650 | * @access_type: 0 for read, 1 for write, 2 for execute | |
d3649702 | 10651 | * @mmu_idx: MMU index indicating required translation regime |
702a9357 | 10652 | * @phys_ptr: set to the physical address corresponding to the virtual address |
8bf5b6a9 | 10653 | * @attrs: set to the memory transaction attributes to use |
702a9357 PM |
10654 | * @prot: set to the permissions for the page containing phys_ptr |
10655 | * @page_size: set to the size of the page containing phys_ptr | |
5b2d261d AB |
10656 | * @fi: set to fault info if the translation fails |
10657 | * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes | |
702a9357 | 10658 | */ |
ebae861f PMD |
10659 | bool get_phys_addr(CPUARMState *env, target_ulong address, |
10660 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
10661 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, | |
10662 | target_ulong *page_size, | |
10663 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) | |
9ee6e8bb | 10664 | { |
0480f69a | 10665 | if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { |
9b539263 EI |
10666 | /* Call ourselves recursively to do the stage 1 and then stage 2 |
10667 | * translations. | |
0480f69a | 10668 | */ |
9b539263 EI |
10669 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
10670 | hwaddr ipa; | |
10671 | int s2_prot; | |
10672 | int ret; | |
5b2d261d | 10673 | ARMCacheAttrs cacheattrs2 = {}; |
9b539263 EI |
10674 | |
10675 | ret = get_phys_addr(env, address, access_type, | |
8bd5c820 | 10676 | stage_1_mmu_idx(mmu_idx), &ipa, attrs, |
bc52bfeb | 10677 | prot, page_size, fi, cacheattrs); |
9b539263 EI |
10678 | |
10679 | /* If S1 fails or S2 is disabled, return early. */ | |
10680 | if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { | |
10681 | *phys_ptr = ipa; | |
10682 | return ret; | |
10683 | } | |
10684 | ||
10685 | /* S1 is done. Now do S2 translation. */ | |
10686 | ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS, | |
10687 | phys_ptr, attrs, &s2_prot, | |
da909b2c | 10688 | page_size, fi, |
5b2d261d | 10689 | cacheattrs != NULL ? &cacheattrs2 : NULL); |
9b539263 EI |
10690 | fi->s2addr = ipa; |
10691 | /* Combine the S1 and S2 perms. */ | |
10692 | *prot &= s2_prot; | |
5b2d261d AB |
10693 | |
10694 | /* Combine the S1 and S2 cache attributes, if needed */ | |
10695 | if (!ret && cacheattrs != NULL) { | |
9d1bab33 PM |
10696 | if (env->cp15.hcr_el2 & HCR_DC) { |
10697 | /* | |
10698 | * HCR.DC forces the first stage attributes to | |
10699 | * Normal Non-Shareable, | |
10700 | * Inner Write-Back Read-Allocate Write-Allocate, | |
10701 | * Outer Write-Back Read-Allocate Write-Allocate. | |
10702 | */ | |
10703 | cacheattrs->attrs = 0xff; | |
10704 | cacheattrs->shareability = 0; | |
10705 | } | |
5b2d261d AB |
10706 | *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2); |
10707 | } | |
10708 | ||
9b539263 EI |
10709 | return ret; |
10710 | } else { | |
10711 | /* | |
10712 | * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. | |
10713 | */ | |
8bd5c820 | 10714 | mmu_idx = stage_1_mmu_idx(mmu_idx); |
9b539263 | 10715 | } |
0480f69a | 10716 | } |
d3649702 | 10717 | |
8bf5b6a9 PM |
10718 | /* The page table entries may downgrade secure to non-secure, but |
10719 | * cannot upgrade an non-secure translation regime's attributes | |
10720 | * to secure. | |
10721 | */ | |
10722 | attrs->secure = regime_is_secure(env, mmu_idx); | |
0995bf8c | 10723 | attrs->user = regime_is_user(env, mmu_idx); |
8bf5b6a9 | 10724 | |
0480f69a PM |
10725 | /* Fast Context Switch Extension. This doesn't exist at all in v8. |
10726 | * In v7 and earlier it affects all stage 1 translations. | |
10727 | */ | |
10728 | if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS | |
10729 | && !arm_feature(env, ARM_FEATURE_V8)) { | |
10730 | if (regime_el(env, mmu_idx) == 3) { | |
10731 | address += env->cp15.fcseidr_s; | |
10732 | } else { | |
10733 | address += env->cp15.fcseidr_ns; | |
10734 | } | |
54bf36ed | 10735 | } |
9ee6e8bb | 10736 | |
3279adb9 | 10737 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
c9f9f124 | 10738 | bool ret; |
f6bda88f | 10739 | *page_size = TARGET_PAGE_SIZE; |
3279adb9 | 10740 | |
504e3cc3 PM |
10741 | if (arm_feature(env, ARM_FEATURE_V8)) { |
10742 | /* PMSAv8 */ | |
10743 | ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, | |
72042435 | 10744 | phys_ptr, attrs, prot, page_size, fi); |
504e3cc3 | 10745 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
3279adb9 PM |
10746 | /* PMSAv7 */ |
10747 | ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, | |
e5e40999 | 10748 | phys_ptr, prot, page_size, fi); |
3279adb9 PM |
10749 | } else { |
10750 | /* Pre-v7 MPU */ | |
10751 | ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, | |
53a4e5c5 | 10752 | phys_ptr, prot, fi); |
3279adb9 PM |
10753 | } |
10754 | qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 | |
c9f9f124 | 10755 | " mmu_idx %u -> %s (prot %c%c%c)\n", |
709e4407 PM |
10756 | access_type == MMU_DATA_LOAD ? "reading" : |
10757 | (access_type == MMU_DATA_STORE ? "writing" : "execute"), | |
c9f9f124 MD |
10758 | (uint32_t)address, mmu_idx, |
10759 | ret ? "Miss" : "Hit", | |
10760 | *prot & PAGE_READ ? 'r' : '-', | |
10761 | *prot & PAGE_WRITE ? 'w' : '-', | |
10762 | *prot & PAGE_EXEC ? 'x' : '-'); | |
10763 | ||
10764 | return ret; | |
f6bda88f PC |
10765 | } |
10766 | ||
3279adb9 PM |
10767 | /* Definitely a real MMU, not an MPU */ |
10768 | ||
0480f69a | 10769 | if (regime_translation_disabled(env, mmu_idx)) { |
3279adb9 | 10770 | /* MMU disabled. */ |
9ee6e8bb | 10771 | *phys_ptr = address; |
3ad493fc | 10772 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
d4c430a8 | 10773 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb | 10774 | return 0; |
0480f69a PM |
10775 | } |
10776 | ||
0480f69a | 10777 | if (regime_using_lpae_format(env, mmu_idx)) { |
bc52bfeb PM |
10778 | return get_phys_addr_lpae(env, address, access_type, mmu_idx, |
10779 | phys_ptr, attrs, prot, page_size, | |
10780 | fi, cacheattrs); | |
0480f69a | 10781 | } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { |
bc52bfeb PM |
10782 | return get_phys_addr_v6(env, address, access_type, mmu_idx, |
10783 | phys_ptr, attrs, prot, page_size, fi); | |
9ee6e8bb | 10784 | } else { |
bc52bfeb | 10785 | return get_phys_addr_v5(env, address, access_type, mmu_idx, |
f989983e | 10786 | phys_ptr, prot, page_size, fi); |
9ee6e8bb PB |
10787 | } |
10788 | } | |
10789 | ||
0faea0c7 PM |
10790 | hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, |
10791 | MemTxAttrs *attrs) | |
b5ff1b31 | 10792 | { |
00b941e5 | 10793 | ARMCPU *cpu = ARM_CPU(cs); |
d3649702 | 10794 | CPUARMState *env = &cpu->env; |
a8170e5e | 10795 | hwaddr phys_addr; |
d4c430a8 | 10796 | target_ulong page_size; |
b5ff1b31 | 10797 | int prot; |
b7cc4e82 | 10798 | bool ret; |
e14b5a23 | 10799 | ARMMMUFaultInfo fi = {}; |
50494a27 | 10800 | ARMMMUIdx mmu_idx = arm_mmu_idx(env); |
b5ff1b31 | 10801 | |
0faea0c7 PM |
10802 | *attrs = (MemTxAttrs) {}; |
10803 | ||
8bd5c820 | 10804 | ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr, |
bc52bfeb | 10805 | attrs, &prot, &page_size, &fi, NULL); |
b5ff1b31 | 10806 | |
b7cc4e82 | 10807 | if (ret) { |
b5ff1b31 | 10808 | return -1; |
00b941e5 | 10809 | } |
b5ff1b31 FB |
10810 | return phys_addr; |
10811 | } | |
10812 | ||
b5ff1b31 | 10813 | #endif |
6ddbc6e4 PB |
10814 | |
10815 | /* Note that signed overflow is undefined in C. The following routines are | |
10816 | careful to use unsigned types where modulo arithmetic is required. | |
10817 | Failure to do so _will_ break on newer gcc. */ | |
10818 | ||
10819 | /* Signed saturating arithmetic. */ | |
10820 | ||
1654b2d6 | 10821 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
10822 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
10823 | { | |
10824 | uint16_t res; | |
10825 | ||
10826 | res = a + b; | |
10827 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
10828 | if (a & 0x8000) | |
10829 | res = 0x8000; | |
10830 | else | |
10831 | res = 0x7fff; | |
10832 | } | |
10833 | return res; | |
10834 | } | |
10835 | ||
1654b2d6 | 10836 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
10837 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
10838 | { | |
10839 | uint8_t res; | |
10840 | ||
10841 | res = a + b; | |
10842 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
10843 | if (a & 0x80) | |
10844 | res = 0x80; | |
10845 | else | |
10846 | res = 0x7f; | |
10847 | } | |
10848 | return res; | |
10849 | } | |
10850 | ||
1654b2d6 | 10851 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
10852 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
10853 | { | |
10854 | uint16_t res; | |
10855 | ||
10856 | res = a - b; | |
10857 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
10858 | if (a & 0x8000) | |
10859 | res = 0x8000; | |
10860 | else | |
10861 | res = 0x7fff; | |
10862 | } | |
10863 | return res; | |
10864 | } | |
10865 | ||
1654b2d6 | 10866 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
10867 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
10868 | { | |
10869 | uint8_t res; | |
10870 | ||
10871 | res = a - b; | |
10872 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
10873 | if (a & 0x80) | |
10874 | res = 0x80; | |
10875 | else | |
10876 | res = 0x7f; | |
10877 | } | |
10878 | return res; | |
10879 | } | |
10880 | ||
10881 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
10882 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
10883 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
10884 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
10885 | #define PFX q | |
10886 | ||
10887 | #include "op_addsub.h" | |
10888 | ||
10889 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 10890 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
10891 | { |
10892 | uint16_t res; | |
10893 | res = a + b; | |
10894 | if (res < a) | |
10895 | res = 0xffff; | |
10896 | return res; | |
10897 | } | |
10898 | ||
460a09c1 | 10899 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 | 10900 | { |
4c4fd3f8 | 10901 | if (a > b) |
6ddbc6e4 PB |
10902 | return a - b; |
10903 | else | |
10904 | return 0; | |
10905 | } | |
10906 | ||
10907 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
10908 | { | |
10909 | uint8_t res; | |
10910 | res = a + b; | |
10911 | if (res < a) | |
10912 | res = 0xff; | |
10913 | return res; | |
10914 | } | |
10915 | ||
10916 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
10917 | { | |
4c4fd3f8 | 10918 | if (a > b) |
6ddbc6e4 PB |
10919 | return a - b; |
10920 | else | |
10921 | return 0; | |
10922 | } | |
10923 | ||
10924 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
10925 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
10926 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
10927 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
10928 | #define PFX uq | |
10929 | ||
10930 | #include "op_addsub.h" | |
10931 | ||
10932 | /* Signed modulo arithmetic. */ | |
10933 | #define SARITH16(a, b, n, op) do { \ | |
10934 | int32_t sum; \ | |
db6e2e65 | 10935 | sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
6ddbc6e4 PB |
10936 | RESULT(sum, n, 16); \ |
10937 | if (sum >= 0) \ | |
10938 | ge |= 3 << (n * 2); \ | |
10939 | } while(0) | |
10940 | ||
10941 | #define SARITH8(a, b, n, op) do { \ | |
10942 | int32_t sum; \ | |
db6e2e65 | 10943 | sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
6ddbc6e4 PB |
10944 | RESULT(sum, n, 8); \ |
10945 | if (sum >= 0) \ | |
10946 | ge |= 1 << n; \ | |
10947 | } while(0) | |
10948 | ||
10949 | ||
10950 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
10951 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
10952 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
10953 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
10954 | #define PFX s | |
10955 | #define ARITH_GE | |
10956 | ||
10957 | #include "op_addsub.h" | |
10958 | ||
10959 | /* Unsigned modulo arithmetic. */ | |
10960 | #define ADD16(a, b, n) do { \ | |
10961 | uint32_t sum; \ | |
10962 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
10963 | RESULT(sum, n, 16); \ | |
a87aa10b | 10964 | if ((sum >> 16) == 1) \ |
6ddbc6e4 PB |
10965 | ge |= 3 << (n * 2); \ |
10966 | } while(0) | |
10967 | ||
10968 | #define ADD8(a, b, n) do { \ | |
10969 | uint32_t sum; \ | |
10970 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
10971 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
10972 | if ((sum >> 8) == 1) \ |
10973 | ge |= 1 << n; \ | |
6ddbc6e4 PB |
10974 | } while(0) |
10975 | ||
10976 | #define SUB16(a, b, n) do { \ | |
10977 | uint32_t sum; \ | |
10978 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
10979 | RESULT(sum, n, 16); \ | |
10980 | if ((sum >> 16) == 0) \ | |
10981 | ge |= 3 << (n * 2); \ | |
10982 | } while(0) | |
10983 | ||
10984 | #define SUB8(a, b, n) do { \ | |
10985 | uint32_t sum; \ | |
10986 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
10987 | RESULT(sum, n, 8); \ | |
10988 | if ((sum >> 8) == 0) \ | |
a87aa10b | 10989 | ge |= 1 << n; \ |
6ddbc6e4 PB |
10990 | } while(0) |
10991 | ||
10992 | #define PFX u | |
10993 | #define ARITH_GE | |
10994 | ||
10995 | #include "op_addsub.h" | |
10996 | ||
10997 | /* Halved signed arithmetic. */ | |
10998 | #define ADD16(a, b, n) \ | |
10999 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
11000 | #define SUB16(a, b, n) \ | |
11001 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
11002 | #define ADD8(a, b, n) \ | |
11003 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
11004 | #define SUB8(a, b, n) \ | |
11005 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
11006 | #define PFX sh | |
11007 | ||
11008 | #include "op_addsub.h" | |
11009 | ||
11010 | /* Halved unsigned arithmetic. */ | |
11011 | #define ADD16(a, b, n) \ | |
11012 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
11013 | #define SUB16(a, b, n) \ | |
11014 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
11015 | #define ADD8(a, b, n) \ | |
11016 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
11017 | #define SUB8(a, b, n) \ | |
11018 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
11019 | #define PFX uh | |
11020 | ||
11021 | #include "op_addsub.h" | |
11022 | ||
11023 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
11024 | { | |
11025 | if (a > b) | |
11026 | return a - b; | |
11027 | else | |
11028 | return b - a; | |
11029 | } | |
11030 | ||
11031 | /* Unsigned sum of absolute byte differences. */ | |
11032 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
11033 | { | |
11034 | uint32_t sum; | |
11035 | sum = do_usad(a, b); | |
11036 | sum += do_usad(a >> 8, b >> 8); | |
11037 | sum += do_usad(a >> 16, b >>16); | |
11038 | sum += do_usad(a >> 24, b >> 24); | |
11039 | return sum; | |
11040 | } | |
11041 | ||
11042 | /* For ARMv6 SEL instruction. */ | |
11043 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
11044 | { | |
11045 | uint32_t mask; | |
11046 | ||
11047 | mask = 0; | |
11048 | if (flags & 1) | |
11049 | mask |= 0xff; | |
11050 | if (flags & 2) | |
11051 | mask |= 0xff00; | |
11052 | if (flags & 4) | |
11053 | mask |= 0xff0000; | |
11054 | if (flags & 8) | |
11055 | mask |= 0xff000000; | |
11056 | return (a & mask) | (b & ~mask); | |
11057 | } | |
11058 | ||
aa633469 PM |
11059 | /* CRC helpers. |
11060 | * The upper bytes of val (above the number specified by 'bytes') must have | |
11061 | * been zeroed out by the caller. | |
11062 | */ | |
eb0ecd5a WN |
11063 | uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) |
11064 | { | |
11065 | uint8_t buf[4]; | |
11066 | ||
aa633469 | 11067 | stl_le_p(buf, val); |
eb0ecd5a WN |
11068 | |
11069 | /* zlib crc32 converts the accumulator and output to one's complement. */ | |
11070 | return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | |
11071 | } | |
11072 | ||
11073 | uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | |
11074 | { | |
11075 | uint8_t buf[4]; | |
11076 | ||
aa633469 | 11077 | stl_le_p(buf, val); |
eb0ecd5a WN |
11078 | |
11079 | /* Linux crc32c converts the output to one's complement. */ | |
11080 | return crc32c(acc, buf, bytes) ^ 0xffffffff; | |
11081 | } | |
a9e01311 RH |
11082 | |
11083 | /* Return the exception level to which FP-disabled exceptions should | |
11084 | * be taken, or 0 if FP is enabled. | |
11085 | */ | |
ced31551 | 11086 | int fp_exception_el(CPUARMState *env, int cur_el) |
a9e01311 | 11087 | { |
55faa212 | 11088 | #ifndef CONFIG_USER_ONLY |
a9e01311 | 11089 | int fpen; |
a9e01311 RH |
11090 | |
11091 | /* CPACR and the CPTR registers don't exist before v6, so FP is | |
11092 | * always accessible | |
11093 | */ | |
11094 | if (!arm_feature(env, ARM_FEATURE_V6)) { | |
11095 | return 0; | |
11096 | } | |
11097 | ||
d87513c0 PM |
11098 | if (arm_feature(env, ARM_FEATURE_M)) { |
11099 | /* CPACR can cause a NOCP UsageFault taken to current security state */ | |
11100 | if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) { | |
11101 | return 1; | |
11102 | } | |
11103 | ||
11104 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) { | |
11105 | if (!extract32(env->v7m.nsacr, 10, 1)) { | |
11106 | /* FP insns cause a NOCP UsageFault taken to Secure */ | |
11107 | return 3; | |
11108 | } | |
11109 | } | |
11110 | ||
11111 | return 0; | |
11112 | } | |
11113 | ||
a9e01311 RH |
11114 | /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: |
11115 | * 0, 2 : trap EL0 and EL1/PL1 accesses | |
11116 | * 1 : trap only EL0 accesses | |
11117 | * 3 : trap no accesses | |
11118 | */ | |
11119 | fpen = extract32(env->cp15.cpacr_el1, 20, 2); | |
11120 | switch (fpen) { | |
11121 | case 0: | |
11122 | case 2: | |
11123 | if (cur_el == 0 || cur_el == 1) { | |
11124 | /* Trap to PL1, which might be EL1 or EL3 */ | |
11125 | if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { | |
11126 | return 3; | |
11127 | } | |
11128 | return 1; | |
11129 | } | |
11130 | if (cur_el == 3 && !is_a64(env)) { | |
11131 | /* Secure PL1 running at EL3 */ | |
11132 | return 3; | |
11133 | } | |
11134 | break; | |
11135 | case 1: | |
11136 | if (cur_el == 0) { | |
11137 | return 1; | |
11138 | } | |
11139 | break; | |
11140 | case 3: | |
11141 | break; | |
11142 | } | |
11143 | ||
fc1120a7 PM |
11144 | /* |
11145 | * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode | |
11146 | * to control non-secure access to the FPU. It doesn't have any | |
11147 | * effect if EL3 is AArch64 or if EL3 doesn't exist at all. | |
11148 | */ | |
11149 | if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
11150 | cur_el <= 2 && !arm_is_secure_below_el3(env))) { | |
11151 | if (!extract32(env->cp15.nsacr, 10, 1)) { | |
11152 | /* FP insns act as UNDEF */ | |
11153 | return cur_el == 2 ? 2 : 1; | |
11154 | } | |
11155 | } | |
11156 | ||
a9e01311 RH |
11157 | /* For the CPTR registers we don't need to guard with an ARM_FEATURE |
11158 | * check because zero bits in the registers mean "don't trap". | |
11159 | */ | |
11160 | ||
11161 | /* CPTR_EL2 : present in v7VE or v8 */ | |
11162 | if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1) | |
11163 | && !arm_is_secure_below_el3(env)) { | |
11164 | /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ | |
11165 | return 2; | |
11166 | } | |
11167 | ||
11168 | /* CPTR_EL3 : present in v8 */ | |
11169 | if (extract32(env->cp15.cptr_el[3], 10, 1)) { | |
11170 | /* Trap all FP ops to EL3 */ | |
11171 | return 3; | |
11172 | } | |
55faa212 | 11173 | #endif |
a9e01311 RH |
11174 | return 0; |
11175 | } | |
11176 | ||
7aab5a8c | 11177 | #ifndef CONFIG_TCG |
65e4655c RH |
11178 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
11179 | { | |
7aab5a8c | 11180 | g_assert_not_reached(); |
65e4655c | 11181 | } |
7aab5a8c | 11182 | #endif |
65e4655c | 11183 | |
164690b2 | 11184 | ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) |
65e4655c | 11185 | { |
65e4655c | 11186 | if (arm_feature(env, ARM_FEATURE_M)) { |
50494a27 | 11187 | return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); |
65e4655c RH |
11188 | } |
11189 | ||
11190 | if (el < 2 && arm_is_secure_below_el3(env)) { | |
50494a27 RH |
11191 | return ARMMMUIdx_S1SE0 + el; |
11192 | } else { | |
11193 | return ARMMMUIdx_S12NSE0 + el; | |
65e4655c | 11194 | } |
50494a27 RH |
11195 | } |
11196 | ||
164690b2 RH |
11197 | ARMMMUIdx arm_mmu_idx(CPUARMState *env) |
11198 | { | |
11199 | return arm_mmu_idx_el(env, arm_current_el(env)); | |
11200 | } | |
11201 | ||
50494a27 RH |
11202 | int cpu_mmu_index(CPUARMState *env, bool ifetch) |
11203 | { | |
11204 | return arm_to_core_mmu_idx(arm_mmu_idx(env)); | |
65e4655c RH |
11205 | } |
11206 | ||
64be86ab RH |
11207 | #ifndef CONFIG_USER_ONLY |
11208 | ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) | |
11209 | { | |
11210 | return stage_1_mmu_idx(arm_mmu_idx(env)); | |
11211 | } | |
11212 | #endif | |
11213 | ||
fdd1b228 RH |
11214 | static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el, |
11215 | ARMMMUIdx mmu_idx, uint32_t flags) | |
11216 | { | |
11217 | flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); | |
11218 | flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, | |
11219 | arm_to_core_mmu_idx(mmu_idx)); | |
11220 | ||
fdd1b228 RH |
11221 | if (arm_singlestep_active(env)) { |
11222 | flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); | |
11223 | } | |
11224 | return flags; | |
11225 | } | |
11226 | ||
43eccfb6 RH |
11227 | static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el, |
11228 | ARMMMUIdx mmu_idx, uint32_t flags) | |
11229 | { | |
8061a649 RH |
11230 | bool sctlr_b = arm_sctlr_b(env); |
11231 | ||
11232 | if (sctlr_b) { | |
11233 | flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, 1); | |
11234 | } | |
11235 | if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { | |
11236 | flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); | |
11237 | } | |
43eccfb6 RH |
11238 | flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); |
11239 | ||
11240 | return rebuild_hflags_common(env, fp_el, mmu_idx, flags); | |
11241 | } | |
11242 | ||
6e33ced5 RH |
11243 | static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el, |
11244 | ARMMMUIdx mmu_idx) | |
11245 | { | |
11246 | uint32_t flags = 0; | |
11247 | ||
0a54d68e RH |
11248 | /* v8M always enables the fpu. */ |
11249 | flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); | |
11250 | ||
6e33ced5 RH |
11251 | if (arm_v7m_is_handler_mode(env)) { |
11252 | flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); | |
11253 | } | |
11254 | ||
11255 | /* | |
11256 | * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN | |
11257 | * is suppressing them because the requested execution priority | |
11258 | * is less than 0. | |
11259 | */ | |
11260 | if (arm_feature(env, ARM_FEATURE_V8) && | |
11261 | !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && | |
11262 | (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { | |
11263 | flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); | |
11264 | } | |
11265 | ||
11266 | return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); | |
11267 | } | |
11268 | ||
83f4baef RH |
11269 | static uint32_t rebuild_hflags_aprofile(CPUARMState *env) |
11270 | { | |
11271 | int flags = 0; | |
11272 | ||
11273 | flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, | |
11274 | arm_debug_target_el(env)); | |
11275 | return flags; | |
11276 | } | |
11277 | ||
c747224c RH |
11278 | static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el, |
11279 | ARMMMUIdx mmu_idx) | |
11280 | { | |
83f4baef | 11281 | uint32_t flags = rebuild_hflags_aprofile(env); |
0a54d68e RH |
11282 | |
11283 | if (arm_el_is_aa64(env, 1)) { | |
11284 | flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); | |
11285 | } | |
5bb0a20b MZ |
11286 | |
11287 | if (arm_current_el(env) < 2 && env->cp15.hstr_el2 && | |
11288 | (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { | |
11289 | flags = FIELD_DP32(flags, TBFLAG_A32, HSTR_ACTIVE, 1); | |
11290 | } | |
11291 | ||
83f4baef | 11292 | return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); |
c747224c RH |
11293 | } |
11294 | ||
d4d7503a RH |
11295 | static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, |
11296 | ARMMMUIdx mmu_idx) | |
a9e01311 | 11297 | { |
83f4baef | 11298 | uint32_t flags = rebuild_hflags_aprofile(env); |
d4d7503a RH |
11299 | ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); |
11300 | ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); | |
d4d7503a RH |
11301 | uint64_t sctlr; |
11302 | int tbii, tbid; | |
b9adaa70 | 11303 | |
d4d7503a | 11304 | flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); |
cd208a1c | 11305 | |
d4d7503a RH |
11306 | /* FIXME: ARMv8.1-VHE S2 translation regime. */ |
11307 | if (regime_el(env, stage1) < 2) { | |
11308 | ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); | |
11309 | tbid = (p1.tbi << 1) | p0.tbi; | |
11310 | tbii = tbid & ~((p1.tbid << 1) | p0.tbid); | |
11311 | } else { | |
11312 | tbid = p0.tbi; | |
11313 | tbii = tbid & !p0.tbid; | |
11314 | } | |
5d8634f5 | 11315 | |
d4d7503a RH |
11316 | flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); |
11317 | flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); | |
11318 | ||
11319 | if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { | |
11320 | int sve_el = sve_exception_el(env, el); | |
11321 | uint32_t zcr_len; | |
5d8634f5 | 11322 | |
d4d7503a RH |
11323 | /* |
11324 | * If SVE is disabled, but FP is enabled, | |
11325 | * then the effective len is 0. | |
11326 | */ | |
11327 | if (sve_el != 0 && fp_el == 0) { | |
11328 | zcr_len = 0; | |
11329 | } else { | |
11330 | zcr_len = sve_zcr_len_for_el(env, el); | |
5d8634f5 | 11331 | } |
d4d7503a RH |
11332 | flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); |
11333 | flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); | |
11334 | } | |
1db5e96c | 11335 | |
d4d7503a | 11336 | sctlr = arm_sctlr(env, el); |
1db5e96c | 11337 | |
8061a649 RH |
11338 | if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { |
11339 | flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); | |
11340 | } | |
11341 | ||
d4d7503a RH |
11342 | if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { |
11343 | /* | |
11344 | * In order to save space in flags, we record only whether | |
11345 | * pauth is "inactive", meaning all insns are implemented as | |
11346 | * a nop, or "active" when some action must be performed. | |
11347 | * The decision of which action to take is left to a helper. | |
11348 | */ | |
11349 | if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { | |
11350 | flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); | |
1db5e96c | 11351 | } |
d4d7503a | 11352 | } |
0816ef1b | 11353 | |
d4d7503a RH |
11354 | if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { |
11355 | /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ | |
11356 | if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { | |
11357 | flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); | |
0816ef1b | 11358 | } |
d4d7503a | 11359 | } |
08f1434a | 11360 | |
d4d7503a RH |
11361 | return rebuild_hflags_common(env, fp_el, mmu_idx, flags); |
11362 | } | |
11363 | ||
3d74e2e9 RH |
11364 | static uint32_t rebuild_hflags_internal(CPUARMState *env) |
11365 | { | |
11366 | int el = arm_current_el(env); | |
11367 | int fp_el = fp_exception_el(env, el); | |
164690b2 | 11368 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); |
3d74e2e9 RH |
11369 | |
11370 | if (is_a64(env)) { | |
11371 | return rebuild_hflags_a64(env, el, fp_el, mmu_idx); | |
11372 | } else if (arm_feature(env, ARM_FEATURE_M)) { | |
11373 | return rebuild_hflags_m32(env, fp_el, mmu_idx); | |
11374 | } else { | |
11375 | return rebuild_hflags_a32(env, fp_el, mmu_idx); | |
11376 | } | |
11377 | } | |
11378 | ||
11379 | void arm_rebuild_hflags(CPUARMState *env) | |
11380 | { | |
11381 | env->hflags = rebuild_hflags_internal(env); | |
11382 | } | |
11383 | ||
14f3c588 RH |
11384 | void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) |
11385 | { | |
11386 | int fp_el = fp_exception_el(env, el); | |
11387 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
11388 | ||
11389 | env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); | |
11390 | } | |
11391 | ||
11392 | void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) | |
11393 | { | |
11394 | int fp_el = fp_exception_el(env, el); | |
11395 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
11396 | ||
11397 | env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); | |
11398 | } | |
11399 | ||
11400 | void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) | |
11401 | { | |
11402 | int fp_el = fp_exception_el(env, el); | |
11403 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | |
11404 | ||
11405 | env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx); | |
11406 | } | |
11407 | ||
d4d7503a RH |
11408 | void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, |
11409 | target_ulong *cs_base, uint32_t *pflags) | |
11410 | { | |
e979972a RH |
11411 | uint32_t flags = env->hflags; |
11412 | uint32_t pstate_for_ss; | |
d4d7503a | 11413 | |
9b253fe5 | 11414 | *cs_base = 0; |
e979972a RH |
11415 | #ifdef CONFIG_DEBUG_TCG |
11416 | assert(flags == rebuild_hflags_internal(env)); | |
11417 | #endif | |
3d74e2e9 | 11418 | |
e979972a | 11419 | if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) { |
d4d7503a | 11420 | *pc = env->pc; |
d4d7503a | 11421 | if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { |
08f1434a RH |
11422 | flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); |
11423 | } | |
60e12c37 | 11424 | pstate_for_ss = env->pstate; |
a9e01311 RH |
11425 | } else { |
11426 | *pc = env->regs[15]; | |
6e33ced5 RH |
11427 | |
11428 | if (arm_feature(env, ARM_FEATURE_M)) { | |
9550d1bd RH |
11429 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && |
11430 | FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) | |
11431 | != env->v7m.secure) { | |
11432 | flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); | |
11433 | } | |
11434 | ||
11435 | if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && | |
11436 | (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || | |
11437 | (env->v7m.secure && | |
11438 | !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { | |
11439 | /* | |
11440 | * ASPEN is set, but FPCA/SFPA indicate that there is no | |
11441 | * active FP context; we must create a new FP context before | |
11442 | * executing any FP insn. | |
11443 | */ | |
11444 | flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1); | |
11445 | } | |
11446 | ||
11447 | bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; | |
11448 | if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { | |
11449 | flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); | |
11450 | } | |
6e33ced5 | 11451 | } else { |
bbad7c62 RH |
11452 | /* |
11453 | * Note that XSCALE_CPAR shares bits with VECSTRIDE. | |
11454 | * Note that VECLEN+VECSTRIDE are RES0 for M-profile. | |
11455 | */ | |
11456 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
11457 | flags = FIELD_DP32(flags, TBFLAG_A32, | |
11458 | XSCALE_CPAR, env->cp15.c15_cpar); | |
11459 | } else { | |
11460 | flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, | |
11461 | env->vfp.vec_len); | |
11462 | flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, | |
11463 | env->vfp.vec_stride); | |
11464 | } | |
0a54d68e RH |
11465 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { |
11466 | flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); | |
11467 | } | |
6e33ced5 RH |
11468 | } |
11469 | ||
aad821ac | 11470 | flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); |
aad821ac | 11471 | flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); |
60e12c37 | 11472 | pstate_for_ss = env->uncached_cpsr; |
d4d7503a | 11473 | } |
a9e01311 | 11474 | |
60e12c37 RH |
11475 | /* |
11476 | * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine | |
a9e01311 RH |
11477 | * states defined in the ARM ARM for software singlestep: |
11478 | * SS_ACTIVE PSTATE.SS State | |
11479 | * 0 x Inactive (the TB flag for SS is always 0) | |
11480 | * 1 0 Active-pending | |
11481 | * 1 1 Active-not-pending | |
fdd1b228 | 11482 | * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. |
a9e01311 | 11483 | */ |
60e12c37 RH |
11484 | if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) && |
11485 | (pstate_for_ss & PSTATE_SS)) { | |
11486 | flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); | |
a9e01311 | 11487 | } |
a9e01311 | 11488 | |
b9adaa70 | 11489 | *pflags = flags; |
a9e01311 | 11490 | } |
0ab5953b RH |
11491 | |
11492 | #ifdef TARGET_AARCH64 | |
11493 | /* | |
11494 | * The manual says that when SVE is enabled and VQ is widened the | |
11495 | * implementation is allowed to zero the previously inaccessible | |
11496 | * portion of the registers. The corollary to that is that when | |
11497 | * SVE is enabled and VQ is narrowed we are also allowed to zero | |
11498 | * the now inaccessible portion of the registers. | |
11499 | * | |
11500 | * The intent of this is that no predicate bit beyond VQ is ever set. | |
11501 | * Which means that some operations on predicate registers themselves | |
11502 | * may operate on full uint64_t or even unrolled across the maximum | |
11503 | * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally | |
11504 | * may well be cheaper than conditionals to restrict the operation | |
11505 | * to the relevant portion of a uint16_t[16]. | |
11506 | */ | |
11507 | void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) | |
11508 | { | |
11509 | int i, j; | |
11510 | uint64_t pmask; | |
11511 | ||
11512 | assert(vq >= 1 && vq <= ARM_MAX_VQ); | |
2fc0cc0e | 11513 | assert(vq <= env_archcpu(env)->sve_max_vq); |
0ab5953b RH |
11514 | |
11515 | /* Zap the high bits of the zregs. */ | |
11516 | for (i = 0; i < 32; i++) { | |
11517 | memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)); | |
11518 | } | |
11519 | ||
11520 | /* Zap the high bits of the pregs and ffr. */ | |
11521 | pmask = 0; | |
11522 | if (vq & 3) { | |
11523 | pmask = ~(-1ULL << (16 * (vq & 3))); | |
11524 | } | |
11525 | for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) { | |
11526 | for (i = 0; i < 17; ++i) { | |
11527 | env->vfp.pregs[i].p[j] &= pmask; | |
11528 | } | |
11529 | pmask = 0; | |
11530 | } | |
11531 | } | |
11532 | ||
11533 | /* | |
11534 | * Notice a change in SVE vector size when changing EL. | |
11535 | */ | |
9a05f7b6 RH |
11536 | void aarch64_sve_change_el(CPUARMState *env, int old_el, |
11537 | int new_el, bool el0_a64) | |
0ab5953b | 11538 | { |
2fc0cc0e | 11539 | ARMCPU *cpu = env_archcpu(env); |
0ab5953b | 11540 | int old_len, new_len; |
9a05f7b6 | 11541 | bool old_a64, new_a64; |
0ab5953b RH |
11542 | |
11543 | /* Nothing to do if no SVE. */ | |
cd208a1c | 11544 | if (!cpu_isar_feature(aa64_sve, cpu)) { |
0ab5953b RH |
11545 | return; |
11546 | } | |
11547 | ||
11548 | /* Nothing to do if FP is disabled in either EL. */ | |
11549 | if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) { | |
11550 | return; | |
11551 | } | |
11552 | ||
11553 | /* | |
11554 | * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped | |
11555 | * at ELx, or not available because the EL is in AArch32 state, then | |
11556 | * for all purposes other than a direct read, the ZCR_ELx.LEN field | |
11557 | * has an effective value of 0". | |
11558 | * | |
11559 | * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0). | |
11560 | * If we ignore aa32 state, we would fail to see the vq4->vq0 transition | |
11561 | * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that | |
11562 | * we already have the correct register contents when encountering the | |
11563 | * vq0->vq0 transition between EL0->EL1. | |
11564 | */ | |
9a05f7b6 RH |
11565 | old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; |
11566 | old_len = (old_a64 && !sve_exception_el(env, old_el) | |
0ab5953b | 11567 | ? sve_zcr_len_for_el(env, old_el) : 0); |
9a05f7b6 RH |
11568 | new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; |
11569 | new_len = (new_a64 && !sve_exception_el(env, new_el) | |
0ab5953b RH |
11570 | ? sve_zcr_len_for_el(env, new_el) : 0); |
11571 | ||
11572 | /* When changing vector length, clear inaccessible state. */ | |
11573 | if (new_len < old_len) { | |
11574 | aarch64_sve_narrow_vq(env, new_len + 1); | |
11575 | } | |
11576 | } | |
11577 | #endif |