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Commit | Line | Data |
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74c21bd0 | 1 | #include "qemu/osdep.h" |
194cbc49 | 2 | #include "trace.h" |
b5ff1b31 | 3 | #include "cpu.h" |
ccd38087 | 4 | #include "internals.h" |
022c62cb | 5 | #include "exec/gdbstub.h" |
2ef6175a | 6 | #include "exec/helper-proto.h" |
1de7afc9 | 7 | #include "qemu/host-utils.h" |
78027bb6 | 8 | #include "sysemu/arch_init.h" |
9c17d615 | 9 | #include "sysemu/sysemu.h" |
1de7afc9 | 10 | #include "qemu/bitops.h" |
eb0ecd5a | 11 | #include "qemu/crc32c.h" |
63c91552 | 12 | #include "exec/exec-all.h" |
f08b6170 | 13 | #include "exec/cpu_ldst.h" |
1d854765 | 14 | #include "arm_ldst.h" |
eb0ecd5a | 15 | #include <zlib.h> /* For crc32 */ |
cfe67cef | 16 | #include "exec/semihost.h" |
f3a9b694 | 17 | #include "sysemu/kvm.h" |
0b03bdfc | 18 | |
352c98e5 LV |
19 | #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ |
20 | ||
4a501606 | 21 | #ifndef CONFIG_USER_ONLY |
af51f566 EI |
22 | static bool get_phys_addr(CPUARMState *env, target_ulong address, |
23 | int access_type, ARMMMUIdx mmu_idx, | |
24 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, | |
e14b5a23 EI |
25 | target_ulong *page_size, uint32_t *fsr, |
26 | ARMMMUFaultInfo *fi); | |
7c2cb42b | 27 | |
37785977 EI |
28 | static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
29 | int access_type, ARMMMUIdx mmu_idx, | |
30 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, | |
31 | target_ulong *page_size_ptr, uint32_t *fsr, | |
32 | ARMMMUFaultInfo *fi); | |
33 | ||
7c2cb42b AF |
34 | /* Definitions for the PMCCNTR and PMCR registers */ |
35 | #define PMCRD 0x8 | |
36 | #define PMCRC 0x4 | |
37 | #define PMCRE 0x1 | |
4a501606 PM |
38 | #endif |
39 | ||
0ecb72a5 | 40 | static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
41 | { |
42 | int nregs; | |
43 | ||
44 | /* VFP data registers are always little-endian. */ | |
45 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
46 | if (reg < nregs) { | |
47 | stfq_le_p(buf, env->vfp.regs[reg]); | |
48 | return 8; | |
49 | } | |
50 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
51 | /* Aliases for Q regs. */ | |
52 | nregs += 16; | |
53 | if (reg < nregs) { | |
54 | stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); | |
55 | stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); | |
56 | return 16; | |
57 | } | |
58 | } | |
59 | switch (reg - nregs) { | |
60 | case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; | |
61 | case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; | |
62 | case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; | |
63 | } | |
64 | return 0; | |
65 | } | |
66 | ||
0ecb72a5 | 67 | static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
68 | { |
69 | int nregs; | |
70 | ||
71 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
72 | if (reg < nregs) { | |
73 | env->vfp.regs[reg] = ldfq_le_p(buf); | |
74 | return 8; | |
75 | } | |
76 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
77 | nregs += 16; | |
78 | if (reg < nregs) { | |
79 | env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); | |
80 | env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); | |
81 | return 16; | |
82 | } | |
83 | } | |
84 | switch (reg - nregs) { | |
85 | case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; | |
86 | case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; | |
71b3c3de | 87 | case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
56aebc89 PB |
88 | } |
89 | return 0; | |
90 | } | |
91 | ||
6a669427 PM |
92 | static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
93 | { | |
94 | switch (reg) { | |
95 | case 0 ... 31: | |
96 | /* 128 bit FP register */ | |
97 | stfq_le_p(buf, env->vfp.regs[reg * 2]); | |
98 | stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); | |
99 | return 16; | |
100 | case 32: | |
101 | /* FPSR */ | |
102 | stl_p(buf, vfp_get_fpsr(env)); | |
103 | return 4; | |
104 | case 33: | |
105 | /* FPCR */ | |
106 | stl_p(buf, vfp_get_fpcr(env)); | |
107 | return 4; | |
108 | default: | |
109 | return 0; | |
110 | } | |
111 | } | |
112 | ||
113 | static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) | |
114 | { | |
115 | switch (reg) { | |
116 | case 0 ... 31: | |
117 | /* 128 bit FP register */ | |
118 | env->vfp.regs[reg * 2] = ldfq_le_p(buf); | |
119 | env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8); | |
120 | return 16; | |
121 | case 32: | |
122 | /* FPSR */ | |
123 | vfp_set_fpsr(env, ldl_p(buf)); | |
124 | return 4; | |
125 | case 33: | |
126 | /* FPCR */ | |
127 | vfp_set_fpcr(env, ldl_p(buf)); | |
128 | return 4; | |
129 | default: | |
130 | return 0; | |
131 | } | |
132 | } | |
133 | ||
c4241c7d | 134 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) |
d4e6df63 | 135 | { |
375421cc | 136 | assert(ri->fieldoffset); |
67ed771d | 137 | if (cpreg_field_is_64bit(ri)) { |
c4241c7d | 138 | return CPREG_FIELD64(env, ri); |
22d9e1a9 | 139 | } else { |
c4241c7d | 140 | return CPREG_FIELD32(env, ri); |
22d9e1a9 | 141 | } |
d4e6df63 PM |
142 | } |
143 | ||
c4241c7d PM |
144 | static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
145 | uint64_t value) | |
d4e6df63 | 146 | { |
375421cc | 147 | assert(ri->fieldoffset); |
67ed771d | 148 | if (cpreg_field_is_64bit(ri)) { |
22d9e1a9 PM |
149 | CPREG_FIELD64(env, ri) = value; |
150 | } else { | |
151 | CPREG_FIELD32(env, ri) = value; | |
152 | } | |
d4e6df63 PM |
153 | } |
154 | ||
11f136ee FA |
155 | static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) |
156 | { | |
157 | return (char *)env + ri->fieldoffset; | |
158 | } | |
159 | ||
49a66191 | 160 | uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) |
721fae12 | 161 | { |
59a1c327 | 162 | /* Raw read of a coprocessor register (as needed for migration, etc). */ |
721fae12 | 163 | if (ri->type & ARM_CP_CONST) { |
59a1c327 | 164 | return ri->resetvalue; |
721fae12 | 165 | } else if (ri->raw_readfn) { |
59a1c327 | 166 | return ri->raw_readfn(env, ri); |
721fae12 | 167 | } else if (ri->readfn) { |
59a1c327 | 168 | return ri->readfn(env, ri); |
721fae12 | 169 | } else { |
59a1c327 | 170 | return raw_read(env, ri); |
721fae12 | 171 | } |
721fae12 PM |
172 | } |
173 | ||
59a1c327 | 174 | static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, |
7900e9f1 | 175 | uint64_t v) |
721fae12 PM |
176 | { |
177 | /* Raw write of a coprocessor register (as needed for migration, etc). | |
721fae12 PM |
178 | * Note that constant registers are treated as write-ignored; the |
179 | * caller should check for success by whether a readback gives the | |
180 | * value written. | |
181 | */ | |
182 | if (ri->type & ARM_CP_CONST) { | |
59a1c327 | 183 | return; |
721fae12 | 184 | } else if (ri->raw_writefn) { |
c4241c7d | 185 | ri->raw_writefn(env, ri, v); |
721fae12 | 186 | } else if (ri->writefn) { |
c4241c7d | 187 | ri->writefn(env, ri, v); |
721fae12 | 188 | } else { |
afb2530f | 189 | raw_write(env, ri, v); |
721fae12 | 190 | } |
721fae12 PM |
191 | } |
192 | ||
375421cc PM |
193 | static bool raw_accessors_invalid(const ARMCPRegInfo *ri) |
194 | { | |
195 | /* Return true if the regdef would cause an assertion if you called | |
196 | * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a | |
197 | * program bug for it not to have the NO_RAW flag). | |
198 | * NB that returning false here doesn't necessarily mean that calling | |
199 | * read/write_raw_cp_reg() is safe, because we can't distinguish "has | |
200 | * read/write access functions which are safe for raw use" from "has | |
201 | * read/write access functions which have side effects but has forgotten | |
202 | * to provide raw access functions". | |
203 | * The tests here line up with the conditions in read/write_raw_cp_reg() | |
204 | * and assertions in raw_read()/raw_write(). | |
205 | */ | |
206 | if ((ri->type & ARM_CP_CONST) || | |
207 | ri->fieldoffset || | |
208 | ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { | |
209 | return false; | |
210 | } | |
211 | return true; | |
212 | } | |
213 | ||
721fae12 PM |
214 | bool write_cpustate_to_list(ARMCPU *cpu) |
215 | { | |
216 | /* Write the coprocessor state from cpu->env to the (index,value) list. */ | |
217 | int i; | |
218 | bool ok = true; | |
219 | ||
220 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
221 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
222 | const ARMCPRegInfo *ri; | |
59a1c327 | 223 | |
60322b39 | 224 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
225 | if (!ri) { |
226 | ok = false; | |
227 | continue; | |
228 | } | |
7a0e58fa | 229 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
230 | continue; |
231 | } | |
59a1c327 | 232 | cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri); |
721fae12 PM |
233 | } |
234 | return ok; | |
235 | } | |
236 | ||
237 | bool write_list_to_cpustate(ARMCPU *cpu) | |
238 | { | |
239 | int i; | |
240 | bool ok = true; | |
241 | ||
242 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
243 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
244 | uint64_t v = cpu->cpreg_values[i]; | |
721fae12 PM |
245 | const ARMCPRegInfo *ri; |
246 | ||
60322b39 | 247 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
248 | if (!ri) { |
249 | ok = false; | |
250 | continue; | |
251 | } | |
7a0e58fa | 252 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
253 | continue; |
254 | } | |
255 | /* Write value and confirm it reads back as written | |
256 | * (to catch read-only registers and partially read-only | |
257 | * registers where the incoming migration value doesn't match) | |
258 | */ | |
59a1c327 PM |
259 | write_raw_cp_reg(&cpu->env, ri, v); |
260 | if (read_raw_cp_reg(&cpu->env, ri) != v) { | |
721fae12 PM |
261 | ok = false; |
262 | } | |
263 | } | |
264 | return ok; | |
265 | } | |
266 | ||
267 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | |
268 | { | |
269 | ARMCPU *cpu = opaque; | |
270 | uint64_t regidx; | |
271 | const ARMCPRegInfo *ri; | |
272 | ||
273 | regidx = *(uint32_t *)key; | |
60322b39 | 274 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 | 275 | |
7a0e58fa | 276 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
277 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); |
278 | /* The value array need not be initialized at this point */ | |
279 | cpu->cpreg_array_len++; | |
280 | } | |
281 | } | |
282 | ||
283 | static void count_cpreg(gpointer key, gpointer opaque) | |
284 | { | |
285 | ARMCPU *cpu = opaque; | |
286 | uint64_t regidx; | |
287 | const ARMCPRegInfo *ri; | |
288 | ||
289 | regidx = *(uint32_t *)key; | |
60322b39 | 290 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 | 291 | |
7a0e58fa | 292 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
293 | cpu->cpreg_array_len++; |
294 | } | |
295 | } | |
296 | ||
297 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | |
298 | { | |
cbf239b7 AR |
299 | uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); |
300 | uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); | |
721fae12 | 301 | |
cbf239b7 AR |
302 | if (aidx > bidx) { |
303 | return 1; | |
304 | } | |
305 | if (aidx < bidx) { | |
306 | return -1; | |
307 | } | |
308 | return 0; | |
721fae12 PM |
309 | } |
310 | ||
311 | void init_cpreg_list(ARMCPU *cpu) | |
312 | { | |
313 | /* Initialise the cpreg_tuples[] array based on the cp_regs hash. | |
314 | * Note that we require cpreg_tuples[] to be sorted by key ID. | |
315 | */ | |
57b6d95e | 316 | GList *keys; |
721fae12 PM |
317 | int arraylen; |
318 | ||
57b6d95e | 319 | keys = g_hash_table_get_keys(cpu->cp_regs); |
721fae12 PM |
320 | keys = g_list_sort(keys, cpreg_key_compare); |
321 | ||
322 | cpu->cpreg_array_len = 0; | |
323 | ||
324 | g_list_foreach(keys, count_cpreg, cpu); | |
325 | ||
326 | arraylen = cpu->cpreg_array_len; | |
327 | cpu->cpreg_indexes = g_new(uint64_t, arraylen); | |
328 | cpu->cpreg_values = g_new(uint64_t, arraylen); | |
329 | cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); | |
330 | cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); | |
331 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; | |
332 | cpu->cpreg_array_len = 0; | |
333 | ||
334 | g_list_foreach(keys, add_cpreg_to_list, cpu); | |
335 | ||
336 | assert(cpu->cpreg_array_len == arraylen); | |
337 | ||
338 | g_list_free(keys); | |
339 | } | |
340 | ||
68e9c2fe EI |
341 | /* |
342 | * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but | |
343 | * they are accessible when EL3 is using AArch64 regardless of EL3.NS. | |
344 | * | |
345 | * access_el3_aa32ns: Used to check AArch32 register views. | |
346 | * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views. | |
347 | */ | |
348 | static CPAccessResult access_el3_aa32ns(CPUARMState *env, | |
3f208fd7 PM |
349 | const ARMCPRegInfo *ri, |
350 | bool isread) | |
68e9c2fe EI |
351 | { |
352 | bool secure = arm_is_secure_below_el3(env); | |
353 | ||
354 | assert(!arm_el_is_aa64(env, 3)); | |
355 | if (secure) { | |
356 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
357 | } | |
358 | return CP_ACCESS_OK; | |
359 | } | |
360 | ||
361 | static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env, | |
3f208fd7 PM |
362 | const ARMCPRegInfo *ri, |
363 | bool isread) | |
68e9c2fe EI |
364 | { |
365 | if (!arm_el_is_aa64(env, 3)) { | |
3f208fd7 | 366 | return access_el3_aa32ns(env, ri, isread); |
68e9c2fe EI |
367 | } |
368 | return CP_ACCESS_OK; | |
369 | } | |
370 | ||
5513c3ab PM |
371 | /* Some secure-only AArch32 registers trap to EL3 if used from |
372 | * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). | |
373 | * Note that an access from Secure EL1 can only happen if EL3 is AArch64. | |
374 | * We assume that the .access field is set to PL1_RW. | |
375 | */ | |
376 | static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, | |
3f208fd7 PM |
377 | const ARMCPRegInfo *ri, |
378 | bool isread) | |
5513c3ab PM |
379 | { |
380 | if (arm_current_el(env) == 3) { | |
381 | return CP_ACCESS_OK; | |
382 | } | |
383 | if (arm_is_secure_below_el3(env)) { | |
384 | return CP_ACCESS_TRAP_EL3; | |
385 | } | |
386 | /* This will be EL1 NS and EL2 NS, which just UNDEF */ | |
387 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
388 | } | |
389 | ||
187f678d PM |
390 | /* Check for traps to "powerdown debug" registers, which are controlled |
391 | * by MDCR.TDOSA | |
392 | */ | |
393 | static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, | |
394 | bool isread) | |
395 | { | |
396 | int el = arm_current_el(env); | |
397 | ||
398 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA) | |
399 | && !arm_is_secure_below_el3(env)) { | |
400 | return CP_ACCESS_TRAP_EL2; | |
401 | } | |
402 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { | |
403 | return CP_ACCESS_TRAP_EL3; | |
404 | } | |
405 | return CP_ACCESS_OK; | |
406 | } | |
407 | ||
91b0a238 PM |
408 | /* Check for traps to "debug ROM" registers, which are controlled |
409 | * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. | |
410 | */ | |
411 | static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, | |
412 | bool isread) | |
413 | { | |
414 | int el = arm_current_el(env); | |
415 | ||
416 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA) | |
417 | && !arm_is_secure_below_el3(env)) { | |
418 | return CP_ACCESS_TRAP_EL2; | |
419 | } | |
420 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
421 | return CP_ACCESS_TRAP_EL3; | |
422 | } | |
423 | return CP_ACCESS_OK; | |
424 | } | |
425 | ||
d6c8cf81 PM |
426 | /* Check for traps to general debug registers, which are controlled |
427 | * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. | |
428 | */ | |
429 | static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, | |
430 | bool isread) | |
431 | { | |
432 | int el = arm_current_el(env); | |
433 | ||
434 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA) | |
435 | && !arm_is_secure_below_el3(env)) { | |
436 | return CP_ACCESS_TRAP_EL2; | |
437 | } | |
438 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
439 | return CP_ACCESS_TRAP_EL3; | |
440 | } | |
441 | return CP_ACCESS_OK; | |
442 | } | |
443 | ||
1fce1ba9 PM |
444 | /* Check for traps to performance monitor registers, which are controlled |
445 | * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. | |
446 | */ | |
447 | static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, | |
448 | bool isread) | |
449 | { | |
450 | int el = arm_current_el(env); | |
451 | ||
452 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) | |
453 | && !arm_is_secure_below_el3(env)) { | |
454 | return CP_ACCESS_TRAP_EL2; | |
455 | } | |
456 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
457 | return CP_ACCESS_TRAP_EL3; | |
458 | } | |
459 | return CP_ACCESS_OK; | |
460 | } | |
461 | ||
c4241c7d | 462 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
c983fe6c | 463 | { |
00c8cb0a AF |
464 | ARMCPU *cpu = arm_env_get_cpu(env); |
465 | ||
8d5c773e | 466 | raw_write(env, ri, value); |
d10eb08f | 467 | tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ |
c983fe6c PM |
468 | } |
469 | ||
c4241c7d | 470 | static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
08de207b | 471 | { |
00c8cb0a AF |
472 | ARMCPU *cpu = arm_env_get_cpu(env); |
473 | ||
8d5c773e | 474 | if (raw_read(env, ri) != value) { |
08de207b PM |
475 | /* Unlike real hardware the qemu TLB uses virtual addresses, |
476 | * not modified virtual addresses, so this causes a TLB flush. | |
477 | */ | |
d10eb08f | 478 | tlb_flush(CPU(cpu)); |
8d5c773e | 479 | raw_write(env, ri, value); |
08de207b | 480 | } |
08de207b | 481 | } |
c4241c7d PM |
482 | |
483 | static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
484 | uint64_t value) | |
08de207b | 485 | { |
00c8cb0a AF |
486 | ARMCPU *cpu = arm_env_get_cpu(env); |
487 | ||
452a0955 | 488 | if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) |
014406b5 | 489 | && !extended_addresses_enabled(env)) { |
08de207b PM |
490 | /* For VMSA (when not using the LPAE long descriptor page table |
491 | * format) this register includes the ASID, so do a TLB flush. | |
492 | * For PMSA it is purely a process ID and no action is needed. | |
493 | */ | |
d10eb08f | 494 | tlb_flush(CPU(cpu)); |
08de207b | 495 | } |
8d5c773e | 496 | raw_write(env, ri, value); |
08de207b PM |
497 | } |
498 | ||
c4241c7d PM |
499 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
500 | uint64_t value) | |
d929823f PM |
501 | { |
502 | /* Invalidate all (TLBIALL) */ | |
00c8cb0a AF |
503 | ARMCPU *cpu = arm_env_get_cpu(env); |
504 | ||
d10eb08f | 505 | tlb_flush(CPU(cpu)); |
d929823f PM |
506 | } |
507 | ||
c4241c7d PM |
508 | static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
509 | uint64_t value) | |
d929823f PM |
510 | { |
511 | /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ | |
31b030d4 AF |
512 | ARMCPU *cpu = arm_env_get_cpu(env); |
513 | ||
514 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); | |
d929823f PM |
515 | } |
516 | ||
c4241c7d PM |
517 | static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
518 | uint64_t value) | |
d929823f PM |
519 | { |
520 | /* Invalidate by ASID (TLBIASID) */ | |
00c8cb0a AF |
521 | ARMCPU *cpu = arm_env_get_cpu(env); |
522 | ||
d10eb08f | 523 | tlb_flush(CPU(cpu)); |
d929823f PM |
524 | } |
525 | ||
c4241c7d PM |
526 | static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
527 | uint64_t value) | |
d929823f PM |
528 | { |
529 | /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ | |
31b030d4 AF |
530 | ARMCPU *cpu = arm_env_get_cpu(env); |
531 | ||
532 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); | |
d929823f PM |
533 | } |
534 | ||
fa439fc5 PM |
535 | /* IS variants of TLB operations must affect all cores */ |
536 | static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
537 | uint64_t value) | |
538 | { | |
a67cf277 | 539 | CPUState *cs = ENV_GET_CPU(env); |
fa439fc5 | 540 | |
a67cf277 | 541 | tlb_flush_all_cpus_synced(cs); |
fa439fc5 PM |
542 | } |
543 | ||
544 | static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
545 | uint64_t value) | |
546 | { | |
a67cf277 | 547 | CPUState *cs = ENV_GET_CPU(env); |
fa439fc5 | 548 | |
a67cf277 | 549 | tlb_flush_all_cpus_synced(cs); |
fa439fc5 PM |
550 | } |
551 | ||
552 | static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
553 | uint64_t value) | |
554 | { | |
a67cf277 | 555 | CPUState *cs = ENV_GET_CPU(env); |
fa439fc5 | 556 | |
a67cf277 | 557 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); |
fa439fc5 PM |
558 | } |
559 | ||
560 | static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
561 | uint64_t value) | |
562 | { | |
a67cf277 | 563 | CPUState *cs = ENV_GET_CPU(env); |
fa439fc5 | 564 | |
a67cf277 | 565 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); |
fa439fc5 PM |
566 | } |
567 | ||
541ef8c2 SS |
568 | static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, |
569 | uint64_t value) | |
570 | { | |
571 | CPUState *cs = ENV_GET_CPU(env); | |
572 | ||
0336cbf8 | 573 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
574 | ARMMMUIdxBit_S12NSE1 | |
575 | ARMMMUIdxBit_S12NSE0 | | |
576 | ARMMMUIdxBit_S2NS); | |
541ef8c2 SS |
577 | } |
578 | ||
579 | static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
580 | uint64_t value) | |
581 | { | |
a67cf277 | 582 | CPUState *cs = ENV_GET_CPU(env); |
541ef8c2 | 583 | |
a67cf277 | 584 | tlb_flush_by_mmuidx_all_cpus_synced(cs, |
8bd5c820 PM |
585 | ARMMMUIdxBit_S12NSE1 | |
586 | ARMMMUIdxBit_S12NSE0 | | |
587 | ARMMMUIdxBit_S2NS); | |
541ef8c2 SS |
588 | } |
589 | ||
590 | static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
591 | uint64_t value) | |
592 | { | |
593 | /* Invalidate by IPA. This has to invalidate any structures that | |
594 | * contain only stage 2 translation information, but does not need | |
595 | * to apply to structures that contain combined stage 1 and stage 2 | |
596 | * translation information. | |
597 | * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. | |
598 | */ | |
599 | CPUState *cs = ENV_GET_CPU(env); | |
600 | uint64_t pageaddr; | |
601 | ||
602 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
603 | return; | |
604 | } | |
605 | ||
606 | pageaddr = sextract64(value << 12, 0, 40); | |
607 | ||
8bd5c820 | 608 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); |
541ef8c2 SS |
609 | } |
610 | ||
611 | static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
612 | uint64_t value) | |
613 | { | |
a67cf277 | 614 | CPUState *cs = ENV_GET_CPU(env); |
541ef8c2 SS |
615 | uint64_t pageaddr; |
616 | ||
617 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
618 | return; | |
619 | } | |
620 | ||
621 | pageaddr = sextract64(value << 12, 0, 40); | |
622 | ||
a67cf277 | 623 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 624 | ARMMMUIdxBit_S2NS); |
541ef8c2 SS |
625 | } |
626 | ||
627 | static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
628 | uint64_t value) | |
629 | { | |
630 | CPUState *cs = ENV_GET_CPU(env); | |
631 | ||
8bd5c820 | 632 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
633 | } |
634 | ||
635 | static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
636 | uint64_t value) | |
637 | { | |
a67cf277 | 638 | CPUState *cs = ENV_GET_CPU(env); |
541ef8c2 | 639 | |
8bd5c820 | 640 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
641 | } |
642 | ||
643 | static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
644 | uint64_t value) | |
645 | { | |
646 | CPUState *cs = ENV_GET_CPU(env); | |
647 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); | |
648 | ||
8bd5c820 | 649 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
650 | } |
651 | ||
652 | static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
653 | uint64_t value) | |
654 | { | |
a67cf277 | 655 | CPUState *cs = ENV_GET_CPU(env); |
541ef8c2 SS |
656 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
657 | ||
a67cf277 | 658 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 659 | ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
660 | } |
661 | ||
e9aa6c21 | 662 | static const ARMCPRegInfo cp_reginfo[] = { |
54bf36ed FA |
663 | /* Define the secure and non-secure FCSE identifier CP registers |
664 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
665 | * the secure register to be properly reset and migrated. There is also no | |
666 | * v8 EL1 version of the register so the non-secure instance stands alone. | |
667 | */ | |
668 | { .name = "FCSEIDR(NS)", | |
669 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, | |
670 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, | |
671 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), | |
672 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, | |
673 | { .name = "FCSEIDR(S)", | |
674 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, | |
675 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
676 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), | |
d4e6df63 | 677 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, |
54bf36ed FA |
678 | /* Define the secure and non-secure context identifier CP registers |
679 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
680 | * the secure register to be properly reset and migrated. In the | |
681 | * non-secure case, the 32-bit register will have reset and migration | |
682 | * disabled during registration as it is handled by the 64-bit instance. | |
683 | */ | |
684 | { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
014406b5 | 685 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
54bf36ed FA |
686 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, |
687 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), | |
688 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, | |
689 | { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32, | |
690 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, | |
691 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
692 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), | |
d4e6df63 | 693 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, |
9449fdf6 PM |
694 | REGINFO_SENTINEL |
695 | }; | |
696 | ||
697 | static const ARMCPRegInfo not_v8_cp_reginfo[] = { | |
698 | /* NB: Some of these registers exist in v8 but with more precise | |
699 | * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). | |
700 | */ | |
701 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
702 | { .name = "DACR", |
703 | .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, | |
704 | .access = PL1_RW, .resetvalue = 0, | |
705 | .writefn = dacr_write, .raw_writefn = raw_write, | |
706 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
707 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a903c449 EI |
708 | /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. |
709 | * For v6 and v5, these mappings are overly broad. | |
4fdd17dd | 710 | */ |
a903c449 EI |
711 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0, |
712 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
713 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1, | |
714 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
715 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4, | |
716 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
717 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8, | |
4fdd17dd | 718 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, |
c4804214 PM |
719 | /* Cache maintenance ops; some of this space may be overridden later. */ |
720 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | |
721 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | |
722 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | |
e9aa6c21 PM |
723 | REGINFO_SENTINEL |
724 | }; | |
725 | ||
7d57f408 PM |
726 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
727 | /* Not all pre-v6 cores implemented this WFI, so this is slightly | |
728 | * over-broad. | |
729 | */ | |
730 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | |
731 | .access = PL1_W, .type = ARM_CP_WFI }, | |
732 | REGINFO_SENTINEL | |
733 | }; | |
734 | ||
735 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | |
736 | /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which | |
737 | * is UNPREDICTABLE; we choose to NOP as most implementations do). | |
738 | */ | |
739 | { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
740 | .access = PL1_W, .type = ARM_CP_WFI }, | |
34f90529 PM |
741 | /* L1 cache lockdown. Not architectural in v6 and earlier but in practice |
742 | * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and | |
743 | * OMAPCP will override this space. | |
744 | */ | |
745 | { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, | |
746 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), | |
747 | .resetvalue = 0 }, | |
748 | { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, | |
749 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), | |
750 | .resetvalue = 0 }, | |
776d4e5c PM |
751 | /* v6 doesn't have the cache ID registers but Linux reads them anyway */ |
752 | { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, | |
7a0e58fa | 753 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 754 | .resetvalue = 0 }, |
50300698 PM |
755 | /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; |
756 | * implementing it as RAZ means the "debug architecture version" bits | |
757 | * will read as a reserved value, which should cause Linux to not try | |
758 | * to use the debug hardware. | |
759 | */ | |
760 | { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
761 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
995939a6 PM |
762 | /* MMU TLB control. Note that the wildcarding means we cover not just |
763 | * the unified TLB ops but also the dside/iside/inner-shareable variants. | |
764 | */ | |
765 | { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, | |
766 | .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, | |
7a0e58fa | 767 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
768 | { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, |
769 | .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, | |
7a0e58fa | 770 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
771 | { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, |
772 | .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, | |
7a0e58fa | 773 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
774 | { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, |
775 | .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, | |
7a0e58fa | 776 | .type = ARM_CP_NO_RAW }, |
a903c449 EI |
777 | { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2, |
778 | .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, | |
779 | { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, | |
780 | .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, | |
7d57f408 PM |
781 | REGINFO_SENTINEL |
782 | }; | |
783 | ||
c4241c7d PM |
784 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
785 | uint64_t value) | |
2771db27 | 786 | { |
f0aff255 FA |
787 | uint32_t mask = 0; |
788 | ||
789 | /* In ARMv8 most bits of CPACR_EL1 are RES0. */ | |
790 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
791 | /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. | |
792 | * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. | |
793 | * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. | |
794 | */ | |
795 | if (arm_feature(env, ARM_FEATURE_VFP)) { | |
796 | /* VFP coprocessor: cp10 & cp11 [23:20] */ | |
797 | mask |= (1 << 31) | (1 << 30) | (0xf << 20); | |
798 | ||
799 | if (!arm_feature(env, ARM_FEATURE_NEON)) { | |
800 | /* ASEDIS [31] bit is RAO/WI */ | |
801 | value |= (1 << 31); | |
802 | } | |
803 | ||
804 | /* VFPv3 and upwards with NEON implement 32 double precision | |
805 | * registers (D0-D31). | |
806 | */ | |
807 | if (!arm_feature(env, ARM_FEATURE_NEON) || | |
808 | !arm_feature(env, ARM_FEATURE_VFP3)) { | |
809 | /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ | |
810 | value |= (1 << 30); | |
811 | } | |
812 | } | |
813 | value &= mask; | |
2771db27 | 814 | } |
7ebd5f2e | 815 | env->cp15.cpacr_el1 = value; |
2771db27 PM |
816 | } |
817 | ||
3f208fd7 PM |
818 | static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
819 | bool isread) | |
c6f19164 GB |
820 | { |
821 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
822 | /* Check if CPACR accesses are to be trapped to EL2 */ | |
823 | if (arm_current_el(env) == 1 && | |
824 | (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) { | |
825 | return CP_ACCESS_TRAP_EL2; | |
826 | /* Check if CPACR accesses are to be trapped to EL3 */ | |
827 | } else if (arm_current_el(env) < 3 && | |
828 | (env->cp15.cptr_el[3] & CPTR_TCPAC)) { | |
829 | return CP_ACCESS_TRAP_EL3; | |
830 | } | |
831 | } | |
832 | ||
833 | return CP_ACCESS_OK; | |
834 | } | |
835 | ||
3f208fd7 PM |
836 | static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
837 | bool isread) | |
c6f19164 GB |
838 | { |
839 | /* Check if CPTR accesses are set to trap to EL3 */ | |
840 | if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) { | |
841 | return CP_ACCESS_TRAP_EL3; | |
842 | } | |
843 | ||
844 | return CP_ACCESS_OK; | |
845 | } | |
846 | ||
7d57f408 PM |
847 | static const ARMCPRegInfo v6_cp_reginfo[] = { |
848 | /* prefetch by MVA in v6, NOP in v7 */ | |
849 | { .name = "MVA_prefetch", | |
850 | .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, | |
851 | .access = PL1_W, .type = ARM_CP_NOP }, | |
6df99dec SS |
852 | /* We need to break the TB after ISB to execute self-modifying code |
853 | * correctly and also to take any pending interrupts immediately. | |
854 | * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. | |
855 | */ | |
7d57f408 | 856 | { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, |
6df99dec | 857 | .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, |
091fd17c | 858 | { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
7d57f408 | 859 | .access = PL0_W, .type = ARM_CP_NOP }, |
091fd17c | 860 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
7d57f408 | 861 | .access = PL0_W, .type = ARM_CP_NOP }, |
06d76f31 | 862 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
6cd8a264 | 863 | .access = PL1_RW, |
b848ce2b FA |
864 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), |
865 | offsetof(CPUARMState, cp15.ifar_ns) }, | |
06d76f31 PM |
866 | .resetvalue = 0, }, |
867 | /* Watchpoint Fault Address Register : should actually only be present | |
868 | * for 1136, 1176, 11MPCore. | |
869 | */ | |
870 | { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
871 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, | |
34222fb8 | 872 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, |
c6f19164 | 873 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, |
7ebd5f2e | 874 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), |
2771db27 | 875 | .resetvalue = 0, .writefn = cpacr_write }, |
7d57f408 PM |
876 | REGINFO_SENTINEL |
877 | }; | |
878 | ||
3f208fd7 PM |
879 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, |
880 | bool isread) | |
200ac0ef | 881 | { |
3b163b01 | 882 | /* Performance monitor registers user accessibility is controlled |
1fce1ba9 PM |
883 | * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable |
884 | * trapping to EL2 or EL3 for other accesses. | |
200ac0ef | 885 | */ |
1fce1ba9 PM |
886 | int el = arm_current_el(env); |
887 | ||
6ecd0b6b | 888 | if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { |
fcd25206 | 889 | return CP_ACCESS_TRAP; |
200ac0ef | 890 | } |
1fce1ba9 PM |
891 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) |
892 | && !arm_is_secure_below_el3(env)) { | |
893 | return CP_ACCESS_TRAP_EL2; | |
894 | } | |
895 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
896 | return CP_ACCESS_TRAP_EL3; | |
897 | } | |
898 | ||
fcd25206 | 899 | return CP_ACCESS_OK; |
200ac0ef PM |
900 | } |
901 | ||
6ecd0b6b AB |
902 | static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, |
903 | const ARMCPRegInfo *ri, | |
904 | bool isread) | |
905 | { | |
906 | /* ER: event counter read trap control */ | |
907 | if (arm_feature(env, ARM_FEATURE_V8) | |
908 | && arm_current_el(env) == 0 | |
909 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 | |
910 | && isread) { | |
911 | return CP_ACCESS_OK; | |
912 | } | |
913 | ||
914 | return pmreg_access(env, ri, isread); | |
915 | } | |
916 | ||
917 | static CPAccessResult pmreg_access_swinc(CPUARMState *env, | |
918 | const ARMCPRegInfo *ri, | |
919 | bool isread) | |
920 | { | |
921 | /* SW: software increment write trap control */ | |
922 | if (arm_feature(env, ARM_FEATURE_V8) | |
923 | && arm_current_el(env) == 0 | |
924 | && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 | |
925 | && !isread) { | |
926 | return CP_ACCESS_OK; | |
927 | } | |
928 | ||
929 | return pmreg_access(env, ri, isread); | |
930 | } | |
931 | ||
7c2cb42b | 932 | #ifndef CONFIG_USER_ONLY |
87124fde | 933 | |
6ecd0b6b AB |
934 | static CPAccessResult pmreg_access_selr(CPUARMState *env, |
935 | const ARMCPRegInfo *ri, | |
936 | bool isread) | |
937 | { | |
938 | /* ER: event counter read trap control */ | |
939 | if (arm_feature(env, ARM_FEATURE_V8) | |
940 | && arm_current_el(env) == 0 | |
941 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { | |
942 | return CP_ACCESS_OK; | |
943 | } | |
944 | ||
945 | return pmreg_access(env, ri, isread); | |
946 | } | |
947 | ||
948 | static CPAccessResult pmreg_access_ccntr(CPUARMState *env, | |
949 | const ARMCPRegInfo *ri, | |
950 | bool isread) | |
951 | { | |
952 | /* CR: cycle counter read trap control */ | |
953 | if (arm_feature(env, ARM_FEATURE_V8) | |
954 | && arm_current_el(env) == 0 | |
955 | && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 | |
956 | && isread) { | |
957 | return CP_ACCESS_OK; | |
958 | } | |
959 | ||
960 | return pmreg_access(env, ri, isread); | |
961 | } | |
962 | ||
87124fde AF |
963 | static inline bool arm_ccnt_enabled(CPUARMState *env) |
964 | { | |
965 | /* This does not support checking PMCCFILTR_EL0 register */ | |
966 | ||
967 | if (!(env->cp15.c9_pmcr & PMCRE)) { | |
968 | return false; | |
969 | } | |
970 | ||
971 | return true; | |
972 | } | |
973 | ||
ec7b4ce4 AF |
974 | void pmccntr_sync(CPUARMState *env) |
975 | { | |
976 | uint64_t temp_ticks; | |
977 | ||
352c98e5 LV |
978 | temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
979 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); | |
ec7b4ce4 AF |
980 | |
981 | if (env->cp15.c9_pmcr & PMCRD) { | |
982 | /* Increment once every 64 processor clock cycles */ | |
983 | temp_ticks /= 64; | |
984 | } | |
985 | ||
986 | if (arm_ccnt_enabled(env)) { | |
987 | env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; | |
988 | } | |
989 | } | |
990 | ||
c4241c7d PM |
991 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
992 | uint64_t value) | |
200ac0ef | 993 | { |
942a155b | 994 | pmccntr_sync(env); |
7c2cb42b AF |
995 | |
996 | if (value & PMCRC) { | |
997 | /* The counter has been reset */ | |
998 | env->cp15.c15_ccnt = 0; | |
999 | } | |
1000 | ||
200ac0ef PM |
1001 | /* only the DP, X, D and E bits are writable */ |
1002 | env->cp15.c9_pmcr &= ~0x39; | |
1003 | env->cp15.c9_pmcr |= (value & 0x39); | |
7c2cb42b | 1004 | |
942a155b | 1005 | pmccntr_sync(env); |
7c2cb42b AF |
1006 | } |
1007 | ||
1008 | static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1009 | { | |
c92c0687 | 1010 | uint64_t total_ticks; |
7c2cb42b | 1011 | |
942a155b | 1012 | if (!arm_ccnt_enabled(env)) { |
7c2cb42b AF |
1013 | /* Counter is disabled, do not change value */ |
1014 | return env->cp15.c15_ccnt; | |
1015 | } | |
1016 | ||
352c98e5 LV |
1017 | total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
1018 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); | |
7c2cb42b AF |
1019 | |
1020 | if (env->cp15.c9_pmcr & PMCRD) { | |
1021 | /* Increment once every 64 processor clock cycles */ | |
1022 | total_ticks /= 64; | |
1023 | } | |
1024 | return total_ticks - env->cp15.c15_ccnt; | |
1025 | } | |
1026 | ||
6b040780 WH |
1027 | static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1028 | uint64_t value) | |
1029 | { | |
1030 | /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and | |
1031 | * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the | |
1032 | * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are | |
1033 | * accessed. | |
1034 | */ | |
1035 | env->cp15.c9_pmselr = value & 0x1f; | |
1036 | } | |
1037 | ||
7c2cb42b AF |
1038 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1039 | uint64_t value) | |
1040 | { | |
c92c0687 | 1041 | uint64_t total_ticks; |
7c2cb42b | 1042 | |
942a155b | 1043 | if (!arm_ccnt_enabled(env)) { |
7c2cb42b AF |
1044 | /* Counter is disabled, set the absolute value */ |
1045 | env->cp15.c15_ccnt = value; | |
1046 | return; | |
1047 | } | |
1048 | ||
352c98e5 LV |
1049 | total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
1050 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); | |
7c2cb42b AF |
1051 | |
1052 | if (env->cp15.c9_pmcr & PMCRD) { | |
1053 | /* Increment once every 64 processor clock cycles */ | |
1054 | total_ticks /= 64; | |
1055 | } | |
1056 | env->cp15.c15_ccnt = total_ticks - value; | |
200ac0ef | 1057 | } |
421c7ebd PC |
1058 | |
1059 | static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1060 | uint64_t value) | |
1061 | { | |
1062 | uint64_t cur_val = pmccntr_read(env, NULL); | |
1063 | ||
1064 | pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); | |
1065 | } | |
1066 | ||
ec7b4ce4 AF |
1067 | #else /* CONFIG_USER_ONLY */ |
1068 | ||
1069 | void pmccntr_sync(CPUARMState *env) | |
1070 | { | |
1071 | } | |
1072 | ||
7c2cb42b | 1073 | #endif |
200ac0ef | 1074 | |
0614601c AF |
1075 | static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1076 | uint64_t value) | |
1077 | { | |
1078 | pmccntr_sync(env); | |
1079 | env->cp15.pmccfiltr_el0 = value & 0x7E000000; | |
1080 | pmccntr_sync(env); | |
1081 | } | |
1082 | ||
c4241c7d | 1083 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1084 | uint64_t value) |
1085 | { | |
200ac0ef PM |
1086 | value &= (1 << 31); |
1087 | env->cp15.c9_pmcnten |= value; | |
200ac0ef PM |
1088 | } |
1089 | ||
c4241c7d PM |
1090 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1091 | uint64_t value) | |
200ac0ef | 1092 | { |
200ac0ef PM |
1093 | value &= (1 << 31); |
1094 | env->cp15.c9_pmcnten &= ~value; | |
200ac0ef PM |
1095 | } |
1096 | ||
c4241c7d PM |
1097 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1098 | uint64_t value) | |
200ac0ef | 1099 | { |
200ac0ef | 1100 | env->cp15.c9_pmovsr &= ~value; |
200ac0ef PM |
1101 | } |
1102 | ||
c4241c7d PM |
1103 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1104 | uint64_t value) | |
200ac0ef | 1105 | { |
fdb86656 WH |
1106 | /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when |
1107 | * PMSELR value is equal to or greater than the number of implemented | |
1108 | * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. | |
1109 | */ | |
1110 | if (env->cp15.c9_pmselr == 0x1f) { | |
1111 | pmccfiltr_write(env, ri, value); | |
1112 | } | |
1113 | } | |
1114 | ||
1115 | static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1116 | { | |
1117 | /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER | |
1118 | * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write(). | |
1119 | */ | |
1120 | if (env->cp15.c9_pmselr == 0x1f) { | |
1121 | return env->cp15.pmccfiltr_el0; | |
1122 | } else { | |
1123 | return 0; | |
1124 | } | |
200ac0ef PM |
1125 | } |
1126 | ||
c4241c7d | 1127 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1128 | uint64_t value) |
1129 | { | |
6ecd0b6b AB |
1130 | if (arm_feature(env, ARM_FEATURE_V8)) { |
1131 | env->cp15.c9_pmuserenr = value & 0xf; | |
1132 | } else { | |
1133 | env->cp15.c9_pmuserenr = value & 1; | |
1134 | } | |
200ac0ef PM |
1135 | } |
1136 | ||
c4241c7d PM |
1137 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1138 | uint64_t value) | |
200ac0ef PM |
1139 | { |
1140 | /* We have no event counters so only the C bit can be changed */ | |
1141 | value &= (1 << 31); | |
1142 | env->cp15.c9_pminten |= value; | |
200ac0ef PM |
1143 | } |
1144 | ||
c4241c7d PM |
1145 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1146 | uint64_t value) | |
200ac0ef PM |
1147 | { |
1148 | value &= (1 << 31); | |
1149 | env->cp15.c9_pminten &= ~value; | |
200ac0ef PM |
1150 | } |
1151 | ||
c4241c7d PM |
1152 | static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1153 | uint64_t value) | |
8641136c | 1154 | { |
a505d7fe PM |
1155 | /* Note that even though the AArch64 view of this register has bits |
1156 | * [10:0] all RES0 we can only mask the bottom 5, to comply with the | |
1157 | * architectural requirements for bits which are RES0 only in some | |
1158 | * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 | |
1159 | * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) | |
1160 | */ | |
855ea66d | 1161 | raw_write(env, ri, value & ~0x1FULL); |
8641136c NR |
1162 | } |
1163 | ||
64e0e2de EI |
1164 | static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
1165 | { | |
1166 | /* We only mask off bits that are RES0 both for AArch64 and AArch32. | |
1167 | * For bits that vary between AArch32/64, code needs to check the | |
1168 | * current execution mode before directly using the feature bit. | |
1169 | */ | |
1170 | uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK; | |
1171 | ||
1172 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | |
1173 | valid_mask &= ~SCR_HCE; | |
1174 | ||
1175 | /* On ARMv7, SMD (or SCD as it is called in v7) is only | |
1176 | * supported if EL2 exists. The bit is UNK/SBZP when | |
1177 | * EL2 is unavailable. In QEMU ARMv7, we force it to always zero | |
1178 | * when EL2 is unavailable. | |
4eb27640 | 1179 | * On ARMv8, this bit is always available. |
64e0e2de | 1180 | */ |
4eb27640 GB |
1181 | if (arm_feature(env, ARM_FEATURE_V7) && |
1182 | !arm_feature(env, ARM_FEATURE_V8)) { | |
64e0e2de EI |
1183 | valid_mask &= ~SCR_SMD; |
1184 | } | |
1185 | } | |
1186 | ||
1187 | /* Clear all-context RES0 bits. */ | |
1188 | value &= valid_mask; | |
1189 | raw_write(env, ri, value); | |
1190 | } | |
1191 | ||
c4241c7d | 1192 | static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
776d4e5c PM |
1193 | { |
1194 | ARMCPU *cpu = arm_env_get_cpu(env); | |
b85a1fd6 FA |
1195 | |
1196 | /* Acquire the CSSELR index from the bank corresponding to the CCSIDR | |
1197 | * bank | |
1198 | */ | |
1199 | uint32_t index = A32_BANKED_REG_GET(env, csselr, | |
1200 | ri->secure & ARM_CP_SECSTATE_S); | |
1201 | ||
1202 | return cpu->ccsidr[index]; | |
776d4e5c PM |
1203 | } |
1204 | ||
c4241c7d PM |
1205 | static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1206 | uint64_t value) | |
776d4e5c | 1207 | { |
8d5c773e | 1208 | raw_write(env, ri, value & 0xf); |
776d4e5c PM |
1209 | } |
1210 | ||
1090b9c6 PM |
1211 | static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1212 | { | |
1213 | CPUState *cs = ENV_GET_CPU(env); | |
1214 | uint64_t ret = 0; | |
1215 | ||
1216 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { | |
1217 | ret |= CPSR_I; | |
1218 | } | |
1219 | if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { | |
1220 | ret |= CPSR_F; | |
1221 | } | |
1222 | /* External aborts are not possible in QEMU so A bit is always clear */ | |
1223 | return ret; | |
1224 | } | |
1225 | ||
e9aa6c21 | 1226 | static const ARMCPRegInfo v7_cp_reginfo[] = { |
7d57f408 PM |
1227 | /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ |
1228 | { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
1229 | .access = PL1_W, .type = ARM_CP_NOP }, | |
200ac0ef PM |
1230 | /* Performance monitors are implementation defined in v7, |
1231 | * but with an ARM recommended set of registers, which we | |
1232 | * follow (although we don't actually implement any counters) | |
1233 | * | |
1234 | * Performance registers fall into three categories: | |
1235 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) | |
1236 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) | |
1237 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) | |
1238 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW | |
1239 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. | |
1240 | */ | |
1241 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 1242 | .access = PL0_RW, .type = ARM_CP_ALIAS, |
8521466b | 1243 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), |
fcd25206 PM |
1244 | .writefn = pmcntenset_write, |
1245 | .accessfn = pmreg_access, | |
1246 | .raw_writefn = raw_write }, | |
8521466b AF |
1247 | { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, |
1248 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, | |
1249 | .access = PL0_RW, .accessfn = pmreg_access, | |
1250 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, | |
1251 | .writefn = pmcntenset_write, .raw_writefn = raw_write }, | |
200ac0ef | 1252 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
8521466b AF |
1253 | .access = PL0_RW, |
1254 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
1255 | .accessfn = pmreg_access, |
1256 | .writefn = pmcntenclr_write, | |
7a0e58fa | 1257 | .type = ARM_CP_ALIAS }, |
8521466b AF |
1258 | { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, |
1259 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, | |
1260 | .access = PL0_RW, .accessfn = pmreg_access, | |
7a0e58fa | 1261 | .type = ARM_CP_ALIAS, |
8521466b AF |
1262 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), |
1263 | .writefn = pmcntenclr_write }, | |
200ac0ef PM |
1264 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
1265 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), | |
fcd25206 PM |
1266 | .accessfn = pmreg_access, |
1267 | .writefn = pmovsr_write, | |
1268 | .raw_writefn = raw_write }, | |
978364f1 AF |
1269 | { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, |
1270 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, | |
1271 | .access = PL0_RW, .accessfn = pmreg_access, | |
1272 | .type = ARM_CP_ALIAS, | |
1273 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), | |
1274 | .writefn = pmovsr_write, | |
1275 | .raw_writefn = raw_write }, | |
fcd25206 | 1276 | /* Unimplemented so WI. */ |
200ac0ef | 1277 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
6ecd0b6b | 1278 | .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP }, |
7c2cb42b | 1279 | #ifndef CONFIG_USER_ONLY |
6b040780 WH |
1280 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, |
1281 | .access = PL0_RW, .type = ARM_CP_ALIAS, | |
1282 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), | |
6ecd0b6b | 1283 | .accessfn = pmreg_access_selr, .writefn = pmselr_write, |
6b040780 WH |
1284 | .raw_writefn = raw_write}, |
1285 | { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, | |
1286 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, | |
6ecd0b6b | 1287 | .access = PL0_RW, .accessfn = pmreg_access_selr, |
6b040780 WH |
1288 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), |
1289 | .writefn = pmselr_write, .raw_writefn = raw_write, }, | |
200ac0ef | 1290 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
7c2cb42b | 1291 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, |
421c7ebd | 1292 | .readfn = pmccntr_read, .writefn = pmccntr_write32, |
6ecd0b6b | 1293 | .accessfn = pmreg_access_ccntr }, |
8521466b AF |
1294 | { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, |
1295 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, | |
6ecd0b6b | 1296 | .access = PL0_RW, .accessfn = pmreg_access_ccntr, |
8521466b AF |
1297 | .type = ARM_CP_IO, |
1298 | .readfn = pmccntr_read, .writefn = pmccntr_write, }, | |
7c2cb42b | 1299 | #endif |
8521466b AF |
1300 | { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, |
1301 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, | |
0614601c | 1302 | .writefn = pmccfiltr_write, |
8521466b AF |
1303 | .access = PL0_RW, .accessfn = pmreg_access, |
1304 | .type = ARM_CP_IO, | |
1305 | .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), | |
1306 | .resetvalue = 0, }, | |
200ac0ef | 1307 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
fdb86656 WH |
1308 | .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access, |
1309 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, | |
1310 | { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, | |
1311 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, | |
1312 | .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access, | |
1313 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, | |
fcd25206 | 1314 | /* Unimplemented, RAZ/WI. */ |
200ac0ef | 1315 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
fcd25206 | 1316 | .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
6ecd0b6b | 1317 | .accessfn = pmreg_access_xevcntr }, |
200ac0ef | 1318 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
1fce1ba9 | 1319 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, |
200ac0ef PM |
1320 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), |
1321 | .resetvalue = 0, | |
d4e6df63 | 1322 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
8a83ffc2 AF |
1323 | { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, |
1324 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, | |
1fce1ba9 | 1325 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, |
8a83ffc2 AF |
1326 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), |
1327 | .resetvalue = 0, | |
1328 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, | |
200ac0ef | 1329 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
1fce1ba9 | 1330 | .access = PL1_RW, .accessfn = access_tpm, |
e6ec5457 WH |
1331 | .type = ARM_CP_ALIAS, |
1332 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), | |
200ac0ef | 1333 | .resetvalue = 0, |
d4e6df63 | 1334 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
e6ec5457 WH |
1335 | { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, |
1336 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, | |
1337 | .access = PL1_RW, .accessfn = access_tpm, | |
1338 | .type = ARM_CP_IO, | |
1339 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
1340 | .writefn = pmintenset_write, .raw_writefn = raw_write, | |
1341 | .resetvalue = 0x0 }, | |
200ac0ef | 1342 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
1fce1ba9 | 1343 | .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, |
200ac0ef | 1344 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
b061a82b | 1345 | .writefn = pmintenclr_write, }, |
978364f1 AF |
1346 | { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, |
1347 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, | |
1fce1ba9 | 1348 | .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, |
978364f1 AF |
1349 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
1350 | .writefn = pmintenclr_write }, | |
7da845b0 PM |
1351 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, |
1352 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | |
7a0e58fa | 1353 | .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, |
7da845b0 PM |
1354 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, |
1355 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | |
b85a1fd6 FA |
1356 | .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, |
1357 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), | |
1358 | offsetof(CPUARMState, cp15.csselr_ns) } }, | |
776d4e5c PM |
1359 | /* Auxiliary ID register: this actually has an IMPDEF value but for now |
1360 | * just RAZ for all cores: | |
1361 | */ | |
0ff644a7 PM |
1362 | { .name = "AIDR", .state = ARM_CP_STATE_BOTH, |
1363 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, | |
776d4e5c | 1364 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f32cdad5 PM |
1365 | /* Auxiliary fault status registers: these also are IMPDEF, and we |
1366 | * choose to RAZ/WI for all cores. | |
1367 | */ | |
1368 | { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, | |
1369 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, | |
1370 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1371 | { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, | |
1372 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, | |
1373 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b0fe2427 PM |
1374 | /* MAIR can just read-as-written because we don't implement caches |
1375 | * and so don't need to care about memory attributes. | |
1376 | */ | |
1377 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | |
1378 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | |
be693c87 | 1379 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), |
b0fe2427 | 1380 | .resetvalue = 0 }, |
4cfb8ad8 PM |
1381 | { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, |
1382 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, | |
1383 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), | |
1384 | .resetvalue = 0 }, | |
b0fe2427 PM |
1385 | /* For non-long-descriptor page tables these are PRRR and NMRR; |
1386 | * regardless they still act as reads-as-written for QEMU. | |
b0fe2427 | 1387 | */ |
1281f8e3 | 1388 | /* MAIR0/1 are defined separately from their 64-bit counterpart which |
be693c87 GB |
1389 | * allows them to assign the correct fieldoffset based on the endianness |
1390 | * handled in the field definitions. | |
1391 | */ | |
a903c449 | 1392 | { .name = "MAIR0", .state = ARM_CP_STATE_AA32, |
b0fe2427 | 1393 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, |
be693c87 GB |
1394 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), |
1395 | offsetof(CPUARMState, cp15.mair0_ns) }, | |
b0fe2427 | 1396 | .resetfn = arm_cp_reset_ignore }, |
a903c449 | 1397 | { .name = "MAIR1", .state = ARM_CP_STATE_AA32, |
b0fe2427 | 1398 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, |
be693c87 GB |
1399 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), |
1400 | offsetof(CPUARMState, cp15.mair1_ns) }, | |
b0fe2427 | 1401 | .resetfn = arm_cp_reset_ignore }, |
1090b9c6 PM |
1402 | { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, |
1403 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, | |
7a0e58fa | 1404 | .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, |
995939a6 PM |
1405 | /* 32 bit ITLB invalidates */ |
1406 | { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, | |
7a0e58fa | 1407 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 1408 | { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, |
7a0e58fa | 1409 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 1410 | { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, |
7a0e58fa | 1411 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 PM |
1412 | /* 32 bit DTLB invalidates */ |
1413 | { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, | |
7a0e58fa | 1414 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 1415 | { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, |
7a0e58fa | 1416 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 1417 | { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, |
7a0e58fa | 1418 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 PM |
1419 | /* 32 bit TLB invalidates */ |
1420 | { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | |
7a0e58fa | 1421 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 1422 | { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
7a0e58fa | 1423 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 1424 | { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
7a0e58fa | 1425 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 | 1426 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
7a0e58fa | 1427 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, |
995939a6 PM |
1428 | REGINFO_SENTINEL |
1429 | }; | |
1430 | ||
1431 | static const ARMCPRegInfo v7mp_cp_reginfo[] = { | |
1432 | /* 32 bit TLB invalidates, Inner Shareable */ | |
1433 | { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | |
7a0e58fa | 1434 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write }, |
995939a6 | 1435 | { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
7a0e58fa | 1436 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, |
995939a6 | 1437 | { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
7a0e58fa | 1438 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 1439 | .writefn = tlbiasid_is_write }, |
995939a6 | 1440 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
7a0e58fa | 1441 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 1442 | .writefn = tlbimvaa_is_write }, |
e9aa6c21 PM |
1443 | REGINFO_SENTINEL |
1444 | }; | |
1445 | ||
c4241c7d PM |
1446 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1447 | uint64_t value) | |
c326b979 PM |
1448 | { |
1449 | value &= 1; | |
1450 | env->teecr = value; | |
c326b979 PM |
1451 | } |
1452 | ||
3f208fd7 PM |
1453 | static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1454 | bool isread) | |
c326b979 | 1455 | { |
dcbff19b | 1456 | if (arm_current_el(env) == 0 && (env->teecr & 1)) { |
92611c00 | 1457 | return CP_ACCESS_TRAP; |
c326b979 | 1458 | } |
92611c00 | 1459 | return CP_ACCESS_OK; |
c326b979 PM |
1460 | } |
1461 | ||
1462 | static const ARMCPRegInfo t2ee_cp_reginfo[] = { | |
1463 | { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, | |
1464 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), | |
1465 | .resetvalue = 0, | |
1466 | .writefn = teecr_write }, | |
1467 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, | |
1468 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | |
92611c00 | 1469 | .accessfn = teehbr_access, .resetvalue = 0 }, |
c326b979 PM |
1470 | REGINFO_SENTINEL |
1471 | }; | |
1472 | ||
4d31c596 | 1473 | static const ARMCPRegInfo v6k_cp_reginfo[] = { |
e4fe830b PM |
1474 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, |
1475 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | |
1476 | .access = PL0_RW, | |
54bf36ed | 1477 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, |
4d31c596 PM |
1478 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
1479 | .access = PL0_RW, | |
54bf36ed FA |
1480 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), |
1481 | offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, | |
e4fe830b PM |
1482 | .resetfn = arm_cp_reset_ignore }, |
1483 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | |
1484 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | |
1485 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
1486 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), |
1487 | .resetvalue = 0}, | |
4d31c596 PM |
1488 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
1489 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
1490 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), |
1491 | offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, | |
e4fe830b | 1492 | .resetfn = arm_cp_reset_ignore }, |
54bf36ed | 1493 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, |
e4fe830b | 1494 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, |
4d31c596 | 1495 | .access = PL1_RW, |
54bf36ed FA |
1496 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, |
1497 | { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, | |
1498 | .access = PL1_RW, | |
1499 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), | |
1500 | offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, | |
1501 | .resetvalue = 0 }, | |
4d31c596 PM |
1502 | REGINFO_SENTINEL |
1503 | }; | |
1504 | ||
55d284af PM |
1505 | #ifndef CONFIG_USER_ONLY |
1506 | ||
3f208fd7 PM |
1507 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1508 | bool isread) | |
00108f2d | 1509 | { |
75502672 PM |
1510 | /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. |
1511 | * Writable only at the highest implemented exception level. | |
1512 | */ | |
1513 | int el = arm_current_el(env); | |
1514 | ||
1515 | switch (el) { | |
1516 | case 0: | |
1517 | if (!extract32(env->cp15.c14_cntkctl, 0, 2)) { | |
1518 | return CP_ACCESS_TRAP; | |
1519 | } | |
1520 | break; | |
1521 | case 1: | |
1522 | if (!isread && ri->state == ARM_CP_STATE_AA32 && | |
1523 | arm_is_secure_below_el3(env)) { | |
1524 | /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ | |
1525 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
1526 | } | |
1527 | break; | |
1528 | case 2: | |
1529 | case 3: | |
1530 | break; | |
00108f2d | 1531 | } |
75502672 PM |
1532 | |
1533 | if (!isread && el < arm_highest_el(env)) { | |
1534 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
1535 | } | |
1536 | ||
00108f2d PM |
1537 | return CP_ACCESS_OK; |
1538 | } | |
1539 | ||
3f208fd7 PM |
1540 | static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, |
1541 | bool isread) | |
00108f2d | 1542 | { |
0b6440af EI |
1543 | unsigned int cur_el = arm_current_el(env); |
1544 | bool secure = arm_is_secure(env); | |
1545 | ||
00108f2d | 1546 | /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ |
0b6440af | 1547 | if (cur_el == 0 && |
00108f2d PM |
1548 | !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { |
1549 | return CP_ACCESS_TRAP; | |
1550 | } | |
0b6440af EI |
1551 | |
1552 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
1553 | timeridx == GTIMER_PHYS && !secure && cur_el < 2 && | |
1554 | !extract32(env->cp15.cnthctl_el2, 0, 1)) { | |
1555 | return CP_ACCESS_TRAP_EL2; | |
1556 | } | |
00108f2d PM |
1557 | return CP_ACCESS_OK; |
1558 | } | |
1559 | ||
3f208fd7 PM |
1560 | static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, |
1561 | bool isread) | |
00108f2d | 1562 | { |
0b6440af EI |
1563 | unsigned int cur_el = arm_current_el(env); |
1564 | bool secure = arm_is_secure(env); | |
1565 | ||
00108f2d PM |
1566 | /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if |
1567 | * EL0[PV]TEN is zero. | |
1568 | */ | |
0b6440af | 1569 | if (cur_el == 0 && |
00108f2d PM |
1570 | !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { |
1571 | return CP_ACCESS_TRAP; | |
1572 | } | |
0b6440af EI |
1573 | |
1574 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
1575 | timeridx == GTIMER_PHYS && !secure && cur_el < 2 && | |
1576 | !extract32(env->cp15.cnthctl_el2, 1, 1)) { | |
1577 | return CP_ACCESS_TRAP_EL2; | |
1578 | } | |
00108f2d PM |
1579 | return CP_ACCESS_OK; |
1580 | } | |
1581 | ||
1582 | static CPAccessResult gt_pct_access(CPUARMState *env, | |
3f208fd7 PM |
1583 | const ARMCPRegInfo *ri, |
1584 | bool isread) | |
00108f2d | 1585 | { |
3f208fd7 | 1586 | return gt_counter_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
1587 | } |
1588 | ||
1589 | static CPAccessResult gt_vct_access(CPUARMState *env, | |
3f208fd7 PM |
1590 | const ARMCPRegInfo *ri, |
1591 | bool isread) | |
00108f2d | 1592 | { |
3f208fd7 | 1593 | return gt_counter_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
1594 | } |
1595 | ||
3f208fd7 PM |
1596 | static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1597 | bool isread) | |
00108f2d | 1598 | { |
3f208fd7 | 1599 | return gt_timer_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
1600 | } |
1601 | ||
3f208fd7 PM |
1602 | static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1603 | bool isread) | |
00108f2d | 1604 | { |
3f208fd7 | 1605 | return gt_timer_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
1606 | } |
1607 | ||
b4d3978c | 1608 | static CPAccessResult gt_stimer_access(CPUARMState *env, |
3f208fd7 PM |
1609 | const ARMCPRegInfo *ri, |
1610 | bool isread) | |
b4d3978c PM |
1611 | { |
1612 | /* The AArch64 register view of the secure physical timer is | |
1613 | * always accessible from EL3, and configurably accessible from | |
1614 | * Secure EL1. | |
1615 | */ | |
1616 | switch (arm_current_el(env)) { | |
1617 | case 1: | |
1618 | if (!arm_is_secure(env)) { | |
1619 | return CP_ACCESS_TRAP; | |
1620 | } | |
1621 | if (!(env->cp15.scr_el3 & SCR_ST)) { | |
1622 | return CP_ACCESS_TRAP_EL3; | |
1623 | } | |
1624 | return CP_ACCESS_OK; | |
1625 | case 0: | |
1626 | case 2: | |
1627 | return CP_ACCESS_TRAP; | |
1628 | case 3: | |
1629 | return CP_ACCESS_OK; | |
1630 | default: | |
1631 | g_assert_not_reached(); | |
1632 | } | |
1633 | } | |
1634 | ||
55d284af PM |
1635 | static uint64_t gt_get_countervalue(CPUARMState *env) |
1636 | { | |
bc72ad67 | 1637 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; |
55d284af PM |
1638 | } |
1639 | ||
1640 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) | |
1641 | { | |
1642 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; | |
1643 | ||
1644 | if (gt->ctl & 1) { | |
1645 | /* Timer enabled: calculate and set current ISTATUS, irq, and | |
1646 | * reset timer to when ISTATUS next has to change | |
1647 | */ | |
edac4d8a EI |
1648 | uint64_t offset = timeridx == GTIMER_VIRT ? |
1649 | cpu->env.cp15.cntvoff_el2 : 0; | |
55d284af PM |
1650 | uint64_t count = gt_get_countervalue(&cpu->env); |
1651 | /* Note that this must be unsigned 64 bit arithmetic: */ | |
edac4d8a | 1652 | int istatus = count - offset >= gt->cval; |
55d284af | 1653 | uint64_t nexttick; |
194cbc49 | 1654 | int irqstate; |
55d284af PM |
1655 | |
1656 | gt->ctl = deposit32(gt->ctl, 2, 1, istatus); | |
194cbc49 PM |
1657 | |
1658 | irqstate = (istatus && !(gt->ctl & 2)); | |
1659 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
1660 | ||
55d284af PM |
1661 | if (istatus) { |
1662 | /* Next transition is when count rolls back over to zero */ | |
1663 | nexttick = UINT64_MAX; | |
1664 | } else { | |
1665 | /* Next transition is when we hit cval */ | |
edac4d8a | 1666 | nexttick = gt->cval + offset; |
55d284af PM |
1667 | } |
1668 | /* Note that the desired next expiry time might be beyond the | |
1669 | * signed-64-bit range of a QEMUTimer -- in this case we just | |
1670 | * set the timer for as far in the future as possible. When the | |
1671 | * timer expires we will reset the timer for any remaining period. | |
1672 | */ | |
1673 | if (nexttick > INT64_MAX / GTIMER_SCALE) { | |
1674 | nexttick = INT64_MAX / GTIMER_SCALE; | |
1675 | } | |
bc72ad67 | 1676 | timer_mod(cpu->gt_timer[timeridx], nexttick); |
194cbc49 | 1677 | trace_arm_gt_recalc(timeridx, irqstate, nexttick); |
55d284af PM |
1678 | } else { |
1679 | /* Timer disabled: ISTATUS and timer output always clear */ | |
1680 | gt->ctl &= ~4; | |
1681 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); | |
bc72ad67 | 1682 | timer_del(cpu->gt_timer[timeridx]); |
194cbc49 | 1683 | trace_arm_gt_recalc_disabled(timeridx); |
55d284af PM |
1684 | } |
1685 | } | |
1686 | ||
0e3eca4c EI |
1687 | static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, |
1688 | int timeridx) | |
55d284af PM |
1689 | { |
1690 | ARMCPU *cpu = arm_env_get_cpu(env); | |
55d284af | 1691 | |
bc72ad67 | 1692 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
1693 | } |
1694 | ||
c4241c7d | 1695 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
55d284af | 1696 | { |
c4241c7d | 1697 | return gt_get_countervalue(env); |
55d284af PM |
1698 | } |
1699 | ||
edac4d8a EI |
1700 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1701 | { | |
1702 | return gt_get_countervalue(env) - env->cp15.cntvoff_el2; | |
1703 | } | |
1704 | ||
c4241c7d | 1705 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 1706 | int timeridx, |
c4241c7d | 1707 | uint64_t value) |
55d284af | 1708 | { |
194cbc49 | 1709 | trace_arm_gt_cval_write(timeridx, value); |
55d284af PM |
1710 | env->cp15.c14_timer[timeridx].cval = value; |
1711 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); | |
55d284af | 1712 | } |
c4241c7d | 1713 | |
0e3eca4c EI |
1714 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, |
1715 | int timeridx) | |
55d284af | 1716 | { |
edac4d8a | 1717 | uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; |
55d284af | 1718 | |
c4241c7d | 1719 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - |
edac4d8a | 1720 | (gt_get_countervalue(env) - offset)); |
55d284af PM |
1721 | } |
1722 | ||
c4241c7d | 1723 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 1724 | int timeridx, |
c4241c7d | 1725 | uint64_t value) |
55d284af | 1726 | { |
edac4d8a | 1727 | uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; |
55d284af | 1728 | |
194cbc49 | 1729 | trace_arm_gt_tval_write(timeridx, value); |
edac4d8a | 1730 | env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + |
18084b2f | 1731 | sextract64(value, 0, 32); |
55d284af | 1732 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); |
55d284af PM |
1733 | } |
1734 | ||
c4241c7d | 1735 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 1736 | int timeridx, |
c4241c7d | 1737 | uint64_t value) |
55d284af PM |
1738 | { |
1739 | ARMCPU *cpu = arm_env_get_cpu(env); | |
55d284af PM |
1740 | uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; |
1741 | ||
194cbc49 | 1742 | trace_arm_gt_ctl_write(timeridx, value); |
d3afacc7 | 1743 | env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); |
55d284af PM |
1744 | if ((oldval ^ value) & 1) { |
1745 | /* Enable toggled */ | |
1746 | gt_recalc_timer(cpu, timeridx); | |
d3afacc7 | 1747 | } else if ((oldval ^ value) & 2) { |
55d284af PM |
1748 | /* IMASK toggled: don't need to recalculate, |
1749 | * just set the interrupt line based on ISTATUS | |
1750 | */ | |
194cbc49 PM |
1751 | int irqstate = (oldval & 4) && !(value & 2); |
1752 | ||
1753 | trace_arm_gt_imask_toggle(timeridx, irqstate); | |
1754 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
55d284af | 1755 | } |
55d284af PM |
1756 | } |
1757 | ||
0e3eca4c EI |
1758 | static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1759 | { | |
1760 | gt_timer_reset(env, ri, GTIMER_PHYS); | |
1761 | } | |
1762 | ||
1763 | static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1764 | uint64_t value) | |
1765 | { | |
1766 | gt_cval_write(env, ri, GTIMER_PHYS, value); | |
1767 | } | |
1768 | ||
1769 | static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1770 | { | |
1771 | return gt_tval_read(env, ri, GTIMER_PHYS); | |
1772 | } | |
1773 | ||
1774 | static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1775 | uint64_t value) | |
1776 | { | |
1777 | gt_tval_write(env, ri, GTIMER_PHYS, value); | |
1778 | } | |
1779 | ||
1780 | static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1781 | uint64_t value) | |
1782 | { | |
1783 | gt_ctl_write(env, ri, GTIMER_PHYS, value); | |
1784 | } | |
1785 | ||
1786 | static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) | |
1787 | { | |
1788 | gt_timer_reset(env, ri, GTIMER_VIRT); | |
1789 | } | |
1790 | ||
1791 | static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1792 | uint64_t value) | |
1793 | { | |
1794 | gt_cval_write(env, ri, GTIMER_VIRT, value); | |
1795 | } | |
1796 | ||
1797 | static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1798 | { | |
1799 | return gt_tval_read(env, ri, GTIMER_VIRT); | |
1800 | } | |
1801 | ||
1802 | static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1803 | uint64_t value) | |
1804 | { | |
1805 | gt_tval_write(env, ri, GTIMER_VIRT, value); | |
1806 | } | |
1807 | ||
1808 | static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1809 | uint64_t value) | |
1810 | { | |
1811 | gt_ctl_write(env, ri, GTIMER_VIRT, value); | |
1812 | } | |
1813 | ||
edac4d8a EI |
1814 | static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1815 | uint64_t value) | |
1816 | { | |
1817 | ARMCPU *cpu = arm_env_get_cpu(env); | |
1818 | ||
194cbc49 | 1819 | trace_arm_gt_cntvoff_write(value); |
edac4d8a EI |
1820 | raw_write(env, ri, value); |
1821 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
1822 | } | |
1823 | ||
b0e66d95 EI |
1824 | static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1825 | { | |
1826 | gt_timer_reset(env, ri, GTIMER_HYP); | |
1827 | } | |
1828 | ||
1829 | static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1830 | uint64_t value) | |
1831 | { | |
1832 | gt_cval_write(env, ri, GTIMER_HYP, value); | |
1833 | } | |
1834 | ||
1835 | static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1836 | { | |
1837 | return gt_tval_read(env, ri, GTIMER_HYP); | |
1838 | } | |
1839 | ||
1840 | static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1841 | uint64_t value) | |
1842 | { | |
1843 | gt_tval_write(env, ri, GTIMER_HYP, value); | |
1844 | } | |
1845 | ||
1846 | static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1847 | uint64_t value) | |
1848 | { | |
1849 | gt_ctl_write(env, ri, GTIMER_HYP, value); | |
1850 | } | |
1851 | ||
b4d3978c PM |
1852 | static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1853 | { | |
1854 | gt_timer_reset(env, ri, GTIMER_SEC); | |
1855 | } | |
1856 | ||
1857 | static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1858 | uint64_t value) | |
1859 | { | |
1860 | gt_cval_write(env, ri, GTIMER_SEC, value); | |
1861 | } | |
1862 | ||
1863 | static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1864 | { | |
1865 | return gt_tval_read(env, ri, GTIMER_SEC); | |
1866 | } | |
1867 | ||
1868 | static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1869 | uint64_t value) | |
1870 | { | |
1871 | gt_tval_write(env, ri, GTIMER_SEC, value); | |
1872 | } | |
1873 | ||
1874 | static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1875 | uint64_t value) | |
1876 | { | |
1877 | gt_ctl_write(env, ri, GTIMER_SEC, value); | |
1878 | } | |
1879 | ||
55d284af PM |
1880 | void arm_gt_ptimer_cb(void *opaque) |
1881 | { | |
1882 | ARMCPU *cpu = opaque; | |
1883 | ||
1884 | gt_recalc_timer(cpu, GTIMER_PHYS); | |
1885 | } | |
1886 | ||
1887 | void arm_gt_vtimer_cb(void *opaque) | |
1888 | { | |
1889 | ARMCPU *cpu = opaque; | |
1890 | ||
1891 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
1892 | } | |
1893 | ||
b0e66d95 EI |
1894 | void arm_gt_htimer_cb(void *opaque) |
1895 | { | |
1896 | ARMCPU *cpu = opaque; | |
1897 | ||
1898 | gt_recalc_timer(cpu, GTIMER_HYP); | |
1899 | } | |
1900 | ||
b4d3978c PM |
1901 | void arm_gt_stimer_cb(void *opaque) |
1902 | { | |
1903 | ARMCPU *cpu = opaque; | |
1904 | ||
1905 | gt_recalc_timer(cpu, GTIMER_SEC); | |
1906 | } | |
1907 | ||
55d284af PM |
1908 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
1909 | /* Note that CNTFRQ is purely reads-as-written for the benefit | |
1910 | * of software; writing it doesn't actually change the timer frequency. | |
1911 | * Our reset value matches the fixed frequency we implement the timer at. | |
1912 | */ | |
1913 | { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 1914 | .type = ARM_CP_ALIAS, |
a7adc4b7 PM |
1915 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, |
1916 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), | |
a7adc4b7 PM |
1917 | }, |
1918 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, | |
1919 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
1920 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
55d284af PM |
1921 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), |
1922 | .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE, | |
55d284af PM |
1923 | }, |
1924 | /* overall control: mostly access permissions */ | |
a7adc4b7 PM |
1925 | { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, |
1926 | .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, | |
55d284af PM |
1927 | .access = PL1_RW, |
1928 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), | |
1929 | .resetvalue = 0, | |
1930 | }, | |
1931 | /* per-timer control */ | |
1932 | { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
9ff9dd3c | 1933 | .secure = ARM_CP_SECSTATE_NS, |
7a0e58fa | 1934 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, |
a7adc4b7 PM |
1935 | .accessfn = gt_ptimer_access, |
1936 | .fieldoffset = offsetoflow32(CPUARMState, | |
1937 | cp15.c14_timer[GTIMER_PHYS].ctl), | |
0e3eca4c | 1938 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, |
a7adc4b7 | 1939 | }, |
9ff9dd3c PM |
1940 | { .name = "CNTP_CTL(S)", |
1941 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
1942 | .secure = ARM_CP_SECSTATE_S, | |
1943 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, | |
1944 | .accessfn = gt_ptimer_access, | |
1945 | .fieldoffset = offsetoflow32(CPUARMState, | |
1946 | cp15.c14_timer[GTIMER_SEC].ctl), | |
1947 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
1948 | }, | |
a7adc4b7 PM |
1949 | { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, |
1950 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, | |
55d284af | 1951 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, |
a7adc4b7 | 1952 | .accessfn = gt_ptimer_access, |
55d284af PM |
1953 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), |
1954 | .resetvalue = 0, | |
0e3eca4c | 1955 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
1956 | }, |
1957 | { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 1958 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, |
a7adc4b7 PM |
1959 | .accessfn = gt_vtimer_access, |
1960 | .fieldoffset = offsetoflow32(CPUARMState, | |
1961 | cp15.c14_timer[GTIMER_VIRT].ctl), | |
0e3eca4c | 1962 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, |
a7adc4b7 PM |
1963 | }, |
1964 | { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
1965 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, | |
55d284af | 1966 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, |
a7adc4b7 | 1967 | .accessfn = gt_vtimer_access, |
55d284af PM |
1968 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), |
1969 | .resetvalue = 0, | |
0e3eca4c | 1970 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
1971 | }, |
1972 | /* TimerValue views: a 32 bit downcounting view of the underlying state */ | |
1973 | { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
9ff9dd3c | 1974 | .secure = ARM_CP_SECSTATE_NS, |
7a0e58fa | 1975 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, |
00108f2d | 1976 | .accessfn = gt_ptimer_access, |
0e3eca4c | 1977 | .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, |
55d284af | 1978 | }, |
9ff9dd3c PM |
1979 | { .name = "CNTP_TVAL(S)", |
1980 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
1981 | .secure = ARM_CP_SECSTATE_S, | |
1982 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
1983 | .accessfn = gt_ptimer_access, | |
1984 | .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, | |
1985 | }, | |
a7adc4b7 PM |
1986 | { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
1987 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, | |
7a0e58fa | 1988 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, |
0e3eca4c EI |
1989 | .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, |
1990 | .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, | |
a7adc4b7 | 1991 | }, |
55d284af | 1992 | { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, |
7a0e58fa | 1993 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, |
00108f2d | 1994 | .accessfn = gt_vtimer_access, |
0e3eca4c | 1995 | .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, |
55d284af | 1996 | }, |
a7adc4b7 PM |
1997 | { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
1998 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, | |
7a0e58fa | 1999 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, |
0e3eca4c EI |
2000 | .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, |
2001 | .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, | |
a7adc4b7 | 2002 | }, |
55d284af PM |
2003 | /* The counter itself */ |
2004 | { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, | |
7a0e58fa | 2005 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 2006 | .accessfn = gt_pct_access, |
a7adc4b7 PM |
2007 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
2008 | }, | |
2009 | { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, | |
2010 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, | |
7a0e58fa | 2011 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 2012 | .accessfn = gt_pct_access, .readfn = gt_cnt_read, |
55d284af PM |
2013 | }, |
2014 | { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, | |
7a0e58fa | 2015 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 2016 | .accessfn = gt_vct_access, |
edac4d8a | 2017 | .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, |
a7adc4b7 PM |
2018 | }, |
2019 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
2020 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
7a0e58fa | 2021 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 2022 | .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, |
55d284af PM |
2023 | }, |
2024 | /* Comparison value, indicating when the timer goes off */ | |
2025 | { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, | |
9ff9dd3c | 2026 | .secure = ARM_CP_SECSTATE_NS, |
55d284af | 2027 | .access = PL1_RW | PL0_R, |
7a0e58fa | 2028 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 2029 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), |
b061a82b | 2030 | .accessfn = gt_ptimer_access, |
0e3eca4c | 2031 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write, |
a7adc4b7 | 2032 | }, |
9ff9dd3c PM |
2033 | { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2, |
2034 | .secure = ARM_CP_SECSTATE_S, | |
2035 | .access = PL1_RW | PL0_R, | |
2036 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, | |
2037 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
2038 | .accessfn = gt_ptimer_access, | |
2039 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
2040 | }, | |
a7adc4b7 PM |
2041 | { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, |
2042 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, | |
2043 | .access = PL1_RW | PL0_R, | |
2044 | .type = ARM_CP_IO, | |
2045 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
12cde08a | 2046 | .resetvalue = 0, .accessfn = gt_ptimer_access, |
0e3eca4c | 2047 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write, |
55d284af PM |
2048 | }, |
2049 | { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, | |
2050 | .access = PL1_RW | PL0_R, | |
7a0e58fa | 2051 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 2052 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), |
b061a82b | 2053 | .accessfn = gt_vtimer_access, |
0e3eca4c | 2054 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write, |
a7adc4b7 PM |
2055 | }, |
2056 | { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
2057 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, | |
2058 | .access = PL1_RW | PL0_R, | |
2059 | .type = ARM_CP_IO, | |
2060 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
2061 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
0e3eca4c | 2062 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write, |
55d284af | 2063 | }, |
b4d3978c PM |
2064 | /* Secure timer -- this is actually restricted to only EL3 |
2065 | * and configurably Secure-EL1 via the accessfn. | |
2066 | */ | |
2067 | { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, | |
2068 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, | |
2069 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, | |
2070 | .accessfn = gt_stimer_access, | |
2071 | .readfn = gt_sec_tval_read, | |
2072 | .writefn = gt_sec_tval_write, | |
2073 | .resetfn = gt_sec_timer_reset, | |
2074 | }, | |
2075 | { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64, | |
2076 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1, | |
2077 | .type = ARM_CP_IO, .access = PL1_RW, | |
2078 | .accessfn = gt_stimer_access, | |
2079 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), | |
2080 | .resetvalue = 0, | |
2081 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
2082 | }, | |
2083 | { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, | |
2084 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, | |
2085 | .type = ARM_CP_IO, .access = PL1_RW, | |
2086 | .accessfn = gt_stimer_access, | |
2087 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
2088 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
2089 | }, | |
55d284af PM |
2090 | REGINFO_SENTINEL |
2091 | }; | |
2092 | ||
2093 | #else | |
2094 | /* In user-mode none of the generic timer registers are accessible, | |
bc72ad67 | 2095 | * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs, |
55d284af PM |
2096 | * so instead just don't register any of them. |
2097 | */ | |
6cc7a3ae | 2098 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
6cc7a3ae PM |
2099 | REGINFO_SENTINEL |
2100 | }; | |
2101 | ||
55d284af PM |
2102 | #endif |
2103 | ||
c4241c7d | 2104 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 2105 | { |
891a2fe7 | 2106 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8d5c773e | 2107 | raw_write(env, ri, value); |
891a2fe7 | 2108 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8d5c773e | 2109 | raw_write(env, ri, value & 0xfffff6ff); |
4a501606 | 2110 | } else { |
8d5c773e | 2111 | raw_write(env, ri, value & 0xfffff1ff); |
4a501606 | 2112 | } |
4a501606 PM |
2113 | } |
2114 | ||
2115 | #ifndef CONFIG_USER_ONLY | |
2116 | /* get_phys_addr() isn't present for user-mode-only targets */ | |
702a9357 | 2117 | |
3f208fd7 PM |
2118 | static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2119 | bool isread) | |
92611c00 PM |
2120 | { |
2121 | if (ri->opc2 & 4) { | |
87562e4f PM |
2122 | /* The ATS12NSO* operations must trap to EL3 if executed in |
2123 | * Secure EL1 (which can only happen if EL3 is AArch64). | |
2124 | * They are simply UNDEF if executed from NS EL1. | |
2125 | * They function normally from EL2 or EL3. | |
92611c00 | 2126 | */ |
87562e4f PM |
2127 | if (arm_current_el(env) == 1) { |
2128 | if (arm_is_secure_below_el3(env)) { | |
2129 | return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; | |
2130 | } | |
2131 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2132 | } | |
92611c00 PM |
2133 | } |
2134 | return CP_ACCESS_OK; | |
2135 | } | |
2136 | ||
060e8a48 | 2137 | static uint64_t do_ats_write(CPUARMState *env, uint64_t value, |
d3649702 | 2138 | int access_type, ARMMMUIdx mmu_idx) |
4a501606 | 2139 | { |
a8170e5e | 2140 | hwaddr phys_addr; |
4a501606 PM |
2141 | target_ulong page_size; |
2142 | int prot; | |
b7cc4e82 PC |
2143 | uint32_t fsr; |
2144 | bool ret; | |
01c097f7 | 2145 | uint64_t par64; |
8bf5b6a9 | 2146 | MemTxAttrs attrs = {}; |
e14b5a23 | 2147 | ARMMMUFaultInfo fi = {}; |
4a501606 | 2148 | |
d3649702 | 2149 | ret = get_phys_addr(env, value, access_type, mmu_idx, |
e14b5a23 | 2150 | &phys_addr, &attrs, &prot, &page_size, &fsr, &fi); |
702a9357 | 2151 | if (extended_addresses_enabled(env)) { |
b7cc4e82 | 2152 | /* fsr is a DFSR/IFSR value for the long descriptor |
702a9357 PM |
2153 | * translation table format, but with WnR always clear. |
2154 | * Convert it to a 64-bit PAR. | |
2155 | */ | |
01c097f7 | 2156 | par64 = (1 << 11); /* LPAE bit always set */ |
b7cc4e82 | 2157 | if (!ret) { |
702a9357 | 2158 | par64 |= phys_addr & ~0xfffULL; |
8bf5b6a9 PM |
2159 | if (!attrs.secure) { |
2160 | par64 |= (1 << 9); /* NS */ | |
2161 | } | |
702a9357 | 2162 | /* We don't set the ATTR or SH fields in the PAR. */ |
4a501606 | 2163 | } else { |
702a9357 | 2164 | par64 |= 1; /* F */ |
b7cc4e82 | 2165 | par64 |= (fsr & 0x3f) << 1; /* FS */ |
702a9357 PM |
2166 | /* Note that S2WLK and FSTAGE are always zero, because we don't |
2167 | * implement virtualization and therefore there can't be a stage 2 | |
2168 | * fault. | |
2169 | */ | |
4a501606 PM |
2170 | } |
2171 | } else { | |
b7cc4e82 | 2172 | /* fsr is a DFSR/IFSR value for the short descriptor |
702a9357 PM |
2173 | * translation table format (with WnR always clear). |
2174 | * Convert it to a 32-bit PAR. | |
2175 | */ | |
b7cc4e82 | 2176 | if (!ret) { |
702a9357 PM |
2177 | /* We do not set any attribute bits in the PAR */ |
2178 | if (page_size == (1 << 24) | |
2179 | && arm_feature(env, ARM_FEATURE_V7)) { | |
01c097f7 | 2180 | par64 = (phys_addr & 0xff000000) | (1 << 1); |
702a9357 | 2181 | } else { |
01c097f7 | 2182 | par64 = phys_addr & 0xfffff000; |
702a9357 | 2183 | } |
8bf5b6a9 PM |
2184 | if (!attrs.secure) { |
2185 | par64 |= (1 << 9); /* NS */ | |
2186 | } | |
702a9357 | 2187 | } else { |
b7cc4e82 PC |
2188 | par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | |
2189 | ((fsr & 0xf) << 1) | 1; | |
702a9357 | 2190 | } |
4a501606 | 2191 | } |
060e8a48 PM |
2192 | return par64; |
2193 | } | |
2194 | ||
2195 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | |
2196 | { | |
060e8a48 PM |
2197 | int access_type = ri->opc2 & 1; |
2198 | uint64_t par64; | |
d3649702 PM |
2199 | ARMMMUIdx mmu_idx; |
2200 | int el = arm_current_el(env); | |
2201 | bool secure = arm_is_secure_below_el3(env); | |
060e8a48 | 2202 | |
d3649702 PM |
2203 | switch (ri->opc2 & 6) { |
2204 | case 0: | |
2205 | /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ | |
2206 | switch (el) { | |
2207 | case 3: | |
2208 | mmu_idx = ARMMMUIdx_S1E3; | |
2209 | break; | |
2210 | case 2: | |
2211 | mmu_idx = ARMMMUIdx_S1NSE1; | |
2212 | break; | |
2213 | case 1: | |
2214 | mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; | |
2215 | break; | |
2216 | default: | |
2217 | g_assert_not_reached(); | |
2218 | } | |
2219 | break; | |
2220 | case 2: | |
2221 | /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ | |
2222 | switch (el) { | |
2223 | case 3: | |
2224 | mmu_idx = ARMMMUIdx_S1SE0; | |
2225 | break; | |
2226 | case 2: | |
2227 | mmu_idx = ARMMMUIdx_S1NSE0; | |
2228 | break; | |
2229 | case 1: | |
2230 | mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; | |
2231 | break; | |
2232 | default: | |
2233 | g_assert_not_reached(); | |
2234 | } | |
2235 | break; | |
2236 | case 4: | |
2237 | /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ | |
2238 | mmu_idx = ARMMMUIdx_S12NSE1; | |
2239 | break; | |
2240 | case 6: | |
2241 | /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ | |
2242 | mmu_idx = ARMMMUIdx_S12NSE0; | |
2243 | break; | |
2244 | default: | |
2245 | g_assert_not_reached(); | |
2246 | } | |
2247 | ||
2248 | par64 = do_ats_write(env, value, access_type, mmu_idx); | |
01c097f7 FA |
2249 | |
2250 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
4a501606 | 2251 | } |
060e8a48 | 2252 | |
14db7fe0 PM |
2253 | static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2254 | uint64_t value) | |
2255 | { | |
2256 | int access_type = ri->opc2 & 1; | |
2257 | uint64_t par64; | |
2258 | ||
2259 | par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS); | |
2260 | ||
2261 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
2262 | } | |
2263 | ||
3f208fd7 PM |
2264 | static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2265 | bool isread) | |
2a47df95 PM |
2266 | { |
2267 | if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) { | |
2268 | return CP_ACCESS_TRAP; | |
2269 | } | |
2270 | return CP_ACCESS_OK; | |
2271 | } | |
2272 | ||
060e8a48 PM |
2273 | static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, |
2274 | uint64_t value) | |
2275 | { | |
060e8a48 | 2276 | int access_type = ri->opc2 & 1; |
d3649702 PM |
2277 | ARMMMUIdx mmu_idx; |
2278 | int secure = arm_is_secure_below_el3(env); | |
2279 | ||
2280 | switch (ri->opc2 & 6) { | |
2281 | case 0: | |
2282 | switch (ri->opc1) { | |
2283 | case 0: /* AT S1E1R, AT S1E1W */ | |
2284 | mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; | |
2285 | break; | |
2286 | case 4: /* AT S1E2R, AT S1E2W */ | |
2287 | mmu_idx = ARMMMUIdx_S1E2; | |
2288 | break; | |
2289 | case 6: /* AT S1E3R, AT S1E3W */ | |
2290 | mmu_idx = ARMMMUIdx_S1E3; | |
2291 | break; | |
2292 | default: | |
2293 | g_assert_not_reached(); | |
2294 | } | |
2295 | break; | |
2296 | case 2: /* AT S1E0R, AT S1E0W */ | |
2297 | mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; | |
2298 | break; | |
2299 | case 4: /* AT S12E1R, AT S12E1W */ | |
2a47df95 | 2300 | mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1; |
d3649702 PM |
2301 | break; |
2302 | case 6: /* AT S12E0R, AT S12E0W */ | |
2a47df95 | 2303 | mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0; |
d3649702 PM |
2304 | break; |
2305 | default: | |
2306 | g_assert_not_reached(); | |
2307 | } | |
060e8a48 | 2308 | |
d3649702 | 2309 | env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); |
060e8a48 | 2310 | } |
4a501606 PM |
2311 | #endif |
2312 | ||
2313 | static const ARMCPRegInfo vapa_cp_reginfo[] = { | |
2314 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, | |
2315 | .access = PL1_RW, .resetvalue = 0, | |
01c097f7 FA |
2316 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), |
2317 | offsetoflow32(CPUARMState, cp15.par_ns) }, | |
4a501606 PM |
2318 | .writefn = par_write }, |
2319 | #ifndef CONFIG_USER_ONLY | |
87562e4f | 2320 | /* This underdecoding is safe because the reginfo is NO_RAW. */ |
4a501606 | 2321 | { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, |
92611c00 | 2322 | .access = PL1_W, .accessfn = ats_access, |
7a0e58fa | 2323 | .writefn = ats_write, .type = ARM_CP_NO_RAW }, |
4a501606 PM |
2324 | #endif |
2325 | REGINFO_SENTINEL | |
2326 | }; | |
2327 | ||
18032bec PM |
2328 | /* Return basic MPU access permission bits. */ |
2329 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
2330 | { | |
2331 | uint32_t ret; | |
2332 | uint32_t mask; | |
2333 | int i; | |
2334 | ret = 0; | |
2335 | mask = 3; | |
2336 | for (i = 0; i < 16; i += 2) { | |
2337 | ret |= (val >> i) & mask; | |
2338 | mask <<= 2; | |
2339 | } | |
2340 | return ret; | |
2341 | } | |
2342 | ||
2343 | /* Pad basic MPU access permission bits to extended format. */ | |
2344 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
2345 | { | |
2346 | uint32_t ret; | |
2347 | uint32_t mask; | |
2348 | int i; | |
2349 | ret = 0; | |
2350 | mask = 3; | |
2351 | for (i = 0; i < 16; i += 2) { | |
2352 | ret |= (val & mask) << i; | |
2353 | mask <<= 2; | |
2354 | } | |
2355 | return ret; | |
2356 | } | |
2357 | ||
c4241c7d PM |
2358 | static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2359 | uint64_t value) | |
18032bec | 2360 | { |
7e09797c | 2361 | env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); |
18032bec PM |
2362 | } |
2363 | ||
c4241c7d | 2364 | static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 2365 | { |
7e09797c | 2366 | return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); |
18032bec PM |
2367 | } |
2368 | ||
c4241c7d PM |
2369 | static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2370 | uint64_t value) | |
18032bec | 2371 | { |
7e09797c | 2372 | env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); |
18032bec PM |
2373 | } |
2374 | ||
c4241c7d | 2375 | static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 2376 | { |
7e09797c | 2377 | return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); |
18032bec PM |
2378 | } |
2379 | ||
6cb0b013 PC |
2380 | static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2381 | { | |
2382 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); | |
2383 | ||
2384 | if (!u32p) { | |
2385 | return 0; | |
2386 | } | |
2387 | ||
2388 | u32p += env->cp15.c6_rgnr; | |
2389 | return *u32p; | |
2390 | } | |
2391 | ||
2392 | static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2393 | uint64_t value) | |
2394 | { | |
2395 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2396 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); | |
2397 | ||
2398 | if (!u32p) { | |
2399 | return; | |
2400 | } | |
2401 | ||
2402 | u32p += env->cp15.c6_rgnr; | |
d10eb08f | 2403 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ |
6cb0b013 PC |
2404 | *u32p = value; |
2405 | } | |
2406 | ||
2407 | static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri) | |
2408 | { | |
2409 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2410 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); | |
2411 | ||
2412 | if (!u32p) { | |
2413 | return; | |
2414 | } | |
2415 | ||
2416 | memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion); | |
2417 | } | |
2418 | ||
2419 | static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2420 | uint64_t value) | |
2421 | { | |
2422 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2423 | uint32_t nrgs = cpu->pmsav7_dregion; | |
2424 | ||
2425 | if (value >= nrgs) { | |
2426 | qemu_log_mask(LOG_GUEST_ERROR, | |
2427 | "PMSAv7 RGNR write >= # supported regions, %" PRIu32 | |
2428 | " > %" PRIu32 "\n", (uint32_t)value, nrgs); | |
2429 | return; | |
2430 | } | |
2431 | ||
2432 | raw_write(env, ri, value); | |
2433 | } | |
2434 | ||
2435 | static const ARMCPRegInfo pmsav7_cp_reginfo[] = { | |
2436 | { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, | |
2437 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
2438 | .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), | |
2439 | .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, | |
2440 | { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, | |
2441 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
2442 | .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), | |
2443 | .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, | |
2444 | { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, | |
2445 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
2446 | .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), | |
2447 | .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset }, | |
2448 | { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, | |
2449 | .access = PL1_RW, | |
2450 | .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr), | |
2451 | .writefn = pmsav7_rgnr_write }, | |
2452 | REGINFO_SENTINEL | |
2453 | }; | |
2454 | ||
18032bec PM |
2455 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { |
2456 | { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 2457 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 2458 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
18032bec PM |
2459 | .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, |
2460 | { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 2461 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 2462 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
18032bec PM |
2463 | .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, |
2464 | { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, | |
2465 | .access = PL1_RW, | |
7e09797c PM |
2466 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
2467 | .resetvalue = 0, }, | |
18032bec PM |
2468 | { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, |
2469 | .access = PL1_RW, | |
7e09797c PM |
2470 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
2471 | .resetvalue = 0, }, | |
ecce5c3c PM |
2472 | { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
2473 | .access = PL1_RW, | |
2474 | .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, | |
2475 | { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
2476 | .access = PL1_RW, | |
2477 | .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, | |
06d76f31 | 2478 | /* Protection region base and size registers */ |
e508a92b PM |
2479 | { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, |
2480 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2481 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, | |
2482 | { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, | |
2483 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2484 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, | |
2485 | { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, | |
2486 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2487 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, | |
2488 | { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, | |
2489 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2490 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, | |
2491 | { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, | |
2492 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2493 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, | |
2494 | { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, | |
2495 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2496 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, | |
2497 | { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, | |
2498 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2499 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, | |
2500 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | |
2501 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2502 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | |
18032bec PM |
2503 | REGINFO_SENTINEL |
2504 | }; | |
2505 | ||
c4241c7d PM |
2506 | static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2507 | uint64_t value) | |
ecce5c3c | 2508 | { |
11f136ee | 2509 | TCR *tcr = raw_ptr(env, ri); |
2ebcebe2 PM |
2510 | int maskshift = extract32(value, 0, 3); |
2511 | ||
e389be16 FA |
2512 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
2513 | if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { | |
2514 | /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when | |
2515 | * using Long-desciptor translation table format */ | |
2516 | value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); | |
2517 | } else if (arm_feature(env, ARM_FEATURE_EL3)) { | |
2518 | /* In an implementation that includes the Security Extensions | |
2519 | * TTBCR has additional fields PD0 [4] and PD1 [5] for | |
2520 | * Short-descriptor translation table format. | |
2521 | */ | |
2522 | value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; | |
2523 | } else { | |
2524 | value &= TTBCR_N; | |
2525 | } | |
e42c4db3 | 2526 | } |
e389be16 | 2527 | |
b6af0975 | 2528 | /* Update the masks corresponding to the TCR bank being written |
11f136ee | 2529 | * Note that we always calculate mask and base_mask, but |
e42c4db3 | 2530 | * they are only used for short-descriptor tables (ie if EAE is 0); |
11f136ee FA |
2531 | * for long-descriptor tables the TCR fields are used differently |
2532 | * and the mask and base_mask values are meaningless. | |
e42c4db3 | 2533 | */ |
11f136ee FA |
2534 | tcr->raw_tcr = value; |
2535 | tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift); | |
2536 | tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift); | |
ecce5c3c PM |
2537 | } |
2538 | ||
c4241c7d PM |
2539 | static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2540 | uint64_t value) | |
d4e6df63 | 2541 | { |
00c8cb0a AF |
2542 | ARMCPU *cpu = arm_env_get_cpu(env); |
2543 | ||
d4e6df63 PM |
2544 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
2545 | /* With LPAE the TTBCR could result in a change of ASID | |
2546 | * via the TTBCR.A1 bit, so do a TLB flush. | |
2547 | */ | |
d10eb08f | 2548 | tlb_flush(CPU(cpu)); |
d4e6df63 | 2549 | } |
c4241c7d | 2550 | vmsa_ttbcr_raw_write(env, ri, value); |
d4e6df63 PM |
2551 | } |
2552 | ||
ecce5c3c PM |
2553 | static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2554 | { | |
11f136ee FA |
2555 | TCR *tcr = raw_ptr(env, ri); |
2556 | ||
2557 | /* Reset both the TCR as well as the masks corresponding to the bank of | |
2558 | * the TCR being reset. | |
2559 | */ | |
2560 | tcr->raw_tcr = 0; | |
2561 | tcr->mask = 0; | |
2562 | tcr->base_mask = 0xffffc000u; | |
ecce5c3c PM |
2563 | } |
2564 | ||
cb2e37df PM |
2565 | static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2566 | uint64_t value) | |
2567 | { | |
00c8cb0a | 2568 | ARMCPU *cpu = arm_env_get_cpu(env); |
11f136ee | 2569 | TCR *tcr = raw_ptr(env, ri); |
00c8cb0a | 2570 | |
cb2e37df | 2571 | /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ |
d10eb08f | 2572 | tlb_flush(CPU(cpu)); |
11f136ee | 2573 | tcr->raw_tcr = value; |
cb2e37df PM |
2574 | } |
2575 | ||
327ed10f PM |
2576 | static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2577 | uint64_t value) | |
2578 | { | |
2579 | /* 64 bit accesses to the TTBRs can change the ASID and so we | |
2580 | * must flush the TLB. | |
2581 | */ | |
2582 | if (cpreg_field_is_64bit(ri)) { | |
00c8cb0a AF |
2583 | ARMCPU *cpu = arm_env_get_cpu(env); |
2584 | ||
d10eb08f | 2585 | tlb_flush(CPU(cpu)); |
327ed10f PM |
2586 | } |
2587 | raw_write(env, ri, value); | |
2588 | } | |
2589 | ||
b698e9cf EI |
2590 | static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2591 | uint64_t value) | |
2592 | { | |
2593 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2594 | CPUState *cs = CPU(cpu); | |
2595 | ||
2596 | /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ | |
2597 | if (raw_read(env, ri) != value) { | |
0336cbf8 | 2598 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
2599 | ARMMMUIdxBit_S12NSE1 | |
2600 | ARMMMUIdxBit_S12NSE0 | | |
2601 | ARMMMUIdxBit_S2NS); | |
b698e9cf EI |
2602 | raw_write(env, ri, value); |
2603 | } | |
2604 | } | |
2605 | ||
8e5d75c9 | 2606 | static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { |
18032bec | 2607 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, |
7a0e58fa | 2608 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
4a7e2d73 | 2609 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), |
b061a82b | 2610 | offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, |
18032bec | 2611 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, |
88ca1c2d FA |
2612 | .access = PL1_RW, .resetvalue = 0, |
2613 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), | |
2614 | offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, | |
8e5d75c9 PC |
2615 | { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, |
2616 | .access = PL1_RW, .resetvalue = 0, | |
2617 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), | |
2618 | offsetof(CPUARMState, cp15.dfar_ns) } }, | |
2619 | { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, | |
2620 | .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, | |
2621 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), | |
2622 | .resetvalue = 0, }, | |
2623 | REGINFO_SENTINEL | |
2624 | }; | |
2625 | ||
2626 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { | |
6cd8a264 RH |
2627 | { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, |
2628 | .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, | |
2629 | .access = PL1_RW, | |
d81c519c | 2630 | .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, |
327ed10f | 2631 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af FA |
2632 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, |
2633 | .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
2634 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), | |
2635 | offsetof(CPUARMState, cp15.ttbr0_ns) } }, | |
327ed10f | 2636 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af FA |
2637 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, |
2638 | .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
2639 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), | |
2640 | offsetof(CPUARMState, cp15.ttbr1_ns) } }, | |
cb2e37df PM |
2641 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, |
2642 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | |
2643 | .access = PL1_RW, .writefn = vmsa_tcr_el1_write, | |
2644 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, | |
11f136ee | 2645 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, |
cb2e37df | 2646 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
7a0e58fa | 2647 | .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, |
b061a82b | 2648 | .raw_writefn = vmsa_ttbcr_raw_write, |
11f136ee FA |
2649 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), |
2650 | offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, | |
18032bec PM |
2651 | REGINFO_SENTINEL |
2652 | }; | |
2653 | ||
c4241c7d PM |
2654 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2655 | uint64_t value) | |
1047b9d7 PM |
2656 | { |
2657 | env->cp15.c15_ticonfig = value & 0xe7; | |
2658 | /* The OS_TYPE bit in this register changes the reported CPUID! */ | |
2659 | env->cp15.c0_cpuid = (value & (1 << 5)) ? | |
2660 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1047b9d7 PM |
2661 | } |
2662 | ||
c4241c7d PM |
2663 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2664 | uint64_t value) | |
1047b9d7 PM |
2665 | { |
2666 | env->cp15.c15_threadid = value & 0xffff; | |
1047b9d7 PM |
2667 | } |
2668 | ||
c4241c7d PM |
2669 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2670 | uint64_t value) | |
1047b9d7 PM |
2671 | { |
2672 | /* Wait-for-interrupt (deprecated) */ | |
c3affe56 | 2673 | cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); |
1047b9d7 PM |
2674 | } |
2675 | ||
c4241c7d PM |
2676 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2677 | uint64_t value) | |
c4804214 PM |
2678 | { |
2679 | /* On OMAP there are registers indicating the max/min index of dcache lines | |
2680 | * containing a dirty line; cache flush operations have to reset these. | |
2681 | */ | |
2682 | env->cp15.c15_i_max = 0x000; | |
2683 | env->cp15.c15_i_min = 0xff0; | |
c4804214 PM |
2684 | } |
2685 | ||
18032bec PM |
2686 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
2687 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, | |
2688 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, | |
d81c519c | 2689 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 2690 | .resetvalue = 0, }, |
1047b9d7 PM |
2691 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
2692 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
2693 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
2694 | .access = PL1_RW, | |
2695 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, | |
2696 | .writefn = omap_ticonfig_write }, | |
2697 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, | |
2698 | .access = PL1_RW, | |
2699 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, | |
2700 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, | |
2701 | .access = PL1_RW, .resetvalue = 0xff0, | |
2702 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, | |
2703 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, | |
2704 | .access = PL1_RW, | |
2705 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, | |
2706 | .writefn = omap_threadid_write }, | |
2707 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, | |
2708 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
7a0e58fa | 2709 | .type = ARM_CP_NO_RAW, |
1047b9d7 PM |
2710 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
2711 | /* TODO: Peripheral port remap register: | |
2712 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller | |
2713 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), | |
2714 | * when MMU is off. | |
2715 | */ | |
c4804214 | 2716 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
d4e6df63 | 2717 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
7a0e58fa | 2718 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, |
c4804214 | 2719 | .writefn = omap_cachemaint_write }, |
34f90529 PM |
2720 | { .name = "C9", .cp = 15, .crn = 9, |
2721 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | |
2722 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | |
1047b9d7 PM |
2723 | REGINFO_SENTINEL |
2724 | }; | |
2725 | ||
c4241c7d PM |
2726 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2727 | uint64_t value) | |
1047b9d7 | 2728 | { |
c0f4af17 | 2729 | env->cp15.c15_cpar = value & 0x3fff; |
1047b9d7 PM |
2730 | } |
2731 | ||
2732 | static const ARMCPRegInfo xscale_cp_reginfo[] = { | |
2733 | { .name = "XSCALE_CPAR", | |
2734 | .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
2735 | .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, | |
2736 | .writefn = xscale_cpar_write, }, | |
2771db27 PM |
2737 | { .name = "XSCALE_AUXCR", |
2738 | .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, | |
2739 | .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), | |
2740 | .resetvalue = 0, }, | |
3b771579 PM |
2741 | /* XScale specific cache-lockdown: since we have no cache we NOP these |
2742 | * and hope the guest does not really rely on cache behaviour. | |
2743 | */ | |
2744 | { .name = "XSCALE_LOCK_ICACHE_LINE", | |
2745 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
2746 | .access = PL1_W, .type = ARM_CP_NOP }, | |
2747 | { .name = "XSCALE_UNLOCK_ICACHE", | |
2748 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
2749 | .access = PL1_W, .type = ARM_CP_NOP }, | |
2750 | { .name = "XSCALE_DCACHE_LOCK", | |
2751 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, | |
2752 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
2753 | { .name = "XSCALE_UNLOCK_DCACHE", | |
2754 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, | |
2755 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1047b9d7 PM |
2756 | REGINFO_SENTINEL |
2757 | }; | |
2758 | ||
2759 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | |
2760 | /* RAZ/WI the whole crn=15 space, when we don't have a more specific | |
2761 | * implementation of this implementation-defined space. | |
2762 | * Ideally this should eventually disappear in favour of actually | |
2763 | * implementing the correct behaviour for all cores. | |
2764 | */ | |
2765 | { .name = "C15_IMPDEF", .cp = 15, .crn = 15, | |
2766 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
3671cd87 | 2767 | .access = PL1_RW, |
7a0e58fa | 2768 | .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, |
d4e6df63 | 2769 | .resetvalue = 0 }, |
18032bec PM |
2770 | REGINFO_SENTINEL |
2771 | }; | |
2772 | ||
c4804214 PM |
2773 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
2774 | /* Cache status: RAZ because we have no cache so it's always clean */ | |
2775 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | |
7a0e58fa | 2776 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 2777 | .resetvalue = 0 }, |
c4804214 PM |
2778 | REGINFO_SENTINEL |
2779 | }; | |
2780 | ||
2781 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | |
2782 | /* We never have a a block transfer operation in progress */ | |
2783 | { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, | |
7a0e58fa | 2784 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 2785 | .resetvalue = 0 }, |
30b05bba PM |
2786 | /* The cache ops themselves: these all NOP for QEMU */ |
2787 | { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, | |
2788 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
2789 | { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, | |
2790 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
2791 | { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, | |
2792 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
2793 | { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, | |
2794 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
2795 | { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, | |
2796 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
2797 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, | |
2798 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
c4804214 PM |
2799 | REGINFO_SENTINEL |
2800 | }; | |
2801 | ||
2802 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | |
2803 | /* The cache test-and-clean instructions always return (1 << 30) | |
2804 | * to indicate that there are no dirty cache lines. | |
2805 | */ | |
2806 | { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, | |
7a0e58fa | 2807 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 2808 | .resetvalue = (1 << 30) }, |
c4804214 | 2809 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
7a0e58fa | 2810 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 2811 | .resetvalue = (1 << 30) }, |
c4804214 PM |
2812 | REGINFO_SENTINEL |
2813 | }; | |
2814 | ||
34f90529 PM |
2815 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
2816 | /* Ignore ReadBuffer accesses */ | |
2817 | { .name = "C9_READBUFFER", .cp = 15, .crn = 9, | |
2818 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
d4e6df63 | 2819 | .access = PL1_RW, .resetvalue = 0, |
7a0e58fa | 2820 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, |
34f90529 PM |
2821 | REGINFO_SENTINEL |
2822 | }; | |
2823 | ||
731de9e6 EI |
2824 | static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2825 | { | |
2826 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2827 | unsigned int cur_el = arm_current_el(env); | |
2828 | bool secure = arm_is_secure(env); | |
2829 | ||
2830 | if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { | |
2831 | return env->cp15.vpidr_el2; | |
2832 | } | |
2833 | return raw_read(env, ri); | |
2834 | } | |
2835 | ||
06a7e647 | 2836 | static uint64_t mpidr_read_val(CPUARMState *env) |
81bdde9d | 2837 | { |
eb5e1d3c PF |
2838 | ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env)); |
2839 | uint64_t mpidr = cpu->mp_affinity; | |
2840 | ||
81bdde9d | 2841 | if (arm_feature(env, ARM_FEATURE_V7MP)) { |
78dbbbe4 | 2842 | mpidr |= (1U << 31); |
81bdde9d PM |
2843 | /* Cores which are uniprocessor (non-coherent) |
2844 | * but still implement the MP extensions set | |
a8e81b31 | 2845 | * bit 30. (For instance, Cortex-R5). |
81bdde9d | 2846 | */ |
a8e81b31 PC |
2847 | if (cpu->mp_is_up) { |
2848 | mpidr |= (1u << 30); | |
2849 | } | |
81bdde9d | 2850 | } |
c4241c7d | 2851 | return mpidr; |
81bdde9d PM |
2852 | } |
2853 | ||
06a7e647 EI |
2854 | static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2855 | { | |
f0d574d6 EI |
2856 | unsigned int cur_el = arm_current_el(env); |
2857 | bool secure = arm_is_secure(env); | |
2858 | ||
2859 | if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { | |
2860 | return env->cp15.vmpidr_el2; | |
2861 | } | |
06a7e647 EI |
2862 | return mpidr_read_val(env); |
2863 | } | |
2864 | ||
81bdde9d | 2865 | static const ARMCPRegInfo mpidr_cp_reginfo[] = { |
4b7fff2f PM |
2866 | { .name = "MPIDR", .state = ARM_CP_STATE_BOTH, |
2867 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | |
7a0e58fa | 2868 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, |
81bdde9d PM |
2869 | REGINFO_SENTINEL |
2870 | }; | |
2871 | ||
7ac681cf | 2872 | static const ARMCPRegInfo lpae_cp_reginfo[] = { |
a903c449 | 2873 | /* NOP AMAIR0/1 */ |
b0fe2427 PM |
2874 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, |
2875 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | |
a903c449 | 2876 | .access = PL1_RW, .type = ARM_CP_CONST, |
7ac681cf | 2877 | .resetvalue = 0 }, |
b0fe2427 | 2878 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ |
7ac681cf | 2879 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
a903c449 | 2880 | .access = PL1_RW, .type = ARM_CP_CONST, |
7ac681cf | 2881 | .resetvalue = 0 }, |
891a2fe7 | 2882 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
01c097f7 FA |
2883 | .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, |
2884 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), | |
2885 | offsetof(CPUARMState, cp15.par_ns)} }, | |
891a2fe7 | 2886 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, |
7a0e58fa | 2887 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, |
7dd8c9af FA |
2888 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
2889 | offsetof(CPUARMState, cp15.ttbr0_ns) }, | |
b061a82b | 2890 | .writefn = vmsa_ttbr_write, }, |
891a2fe7 | 2891 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
7a0e58fa | 2892 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, |
7dd8c9af FA |
2893 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
2894 | offsetof(CPUARMState, cp15.ttbr1_ns) }, | |
b061a82b | 2895 | .writefn = vmsa_ttbr_write, }, |
7ac681cf PM |
2896 | REGINFO_SENTINEL |
2897 | }; | |
2898 | ||
c4241c7d | 2899 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 2900 | { |
c4241c7d | 2901 | return vfp_get_fpcr(env); |
b0d2b7d0 PM |
2902 | } |
2903 | ||
c4241c7d PM |
2904 | static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2905 | uint64_t value) | |
b0d2b7d0 PM |
2906 | { |
2907 | vfp_set_fpcr(env, value); | |
b0d2b7d0 PM |
2908 | } |
2909 | ||
c4241c7d | 2910 | static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 2911 | { |
c4241c7d | 2912 | return vfp_get_fpsr(env); |
b0d2b7d0 PM |
2913 | } |
2914 | ||
c4241c7d PM |
2915 | static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2916 | uint64_t value) | |
b0d2b7d0 PM |
2917 | { |
2918 | vfp_set_fpsr(env, value); | |
b0d2b7d0 PM |
2919 | } |
2920 | ||
3f208fd7 PM |
2921 | static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2922 | bool isread) | |
c2b820fe | 2923 | { |
137feaa9 | 2924 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { |
c2b820fe PM |
2925 | return CP_ACCESS_TRAP; |
2926 | } | |
2927 | return CP_ACCESS_OK; | |
2928 | } | |
2929 | ||
2930 | static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2931 | uint64_t value) | |
2932 | { | |
2933 | env->daif = value & PSTATE_DAIF; | |
2934 | } | |
2935 | ||
8af35c37 | 2936 | static CPAccessResult aa64_cacheop_access(CPUARMState *env, |
3f208fd7 PM |
2937 | const ARMCPRegInfo *ri, |
2938 | bool isread) | |
8af35c37 PM |
2939 | { |
2940 | /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless | |
2941 | * SCTLR_EL1.UCI is set. | |
2942 | */ | |
137feaa9 | 2943 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) { |
8af35c37 PM |
2944 | return CP_ACCESS_TRAP; |
2945 | } | |
2946 | return CP_ACCESS_OK; | |
2947 | } | |
2948 | ||
dbb1fb27 AB |
2949 | /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions |
2950 | * Page D4-1736 (DDI0487A.b) | |
2951 | */ | |
2952 | ||
fd3ed969 PM |
2953 | static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2954 | uint64_t value) | |
168aa23b | 2955 | { |
a67cf277 | 2956 | CPUState *cs = ENV_GET_CPU(env); |
dbb1fb27 | 2957 | |
fd3ed969 | 2958 | if (arm_is_secure_below_el3(env)) { |
0336cbf8 | 2959 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
2960 | ARMMMUIdxBit_S1SE1 | |
2961 | ARMMMUIdxBit_S1SE0); | |
fd3ed969 | 2962 | } else { |
0336cbf8 | 2963 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
2964 | ARMMMUIdxBit_S12NSE1 | |
2965 | ARMMMUIdxBit_S12NSE0); | |
fd3ed969 | 2966 | } |
168aa23b PM |
2967 | } |
2968 | ||
fd3ed969 PM |
2969 | static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2970 | uint64_t value) | |
168aa23b | 2971 | { |
a67cf277 | 2972 | CPUState *cs = ENV_GET_CPU(env); |
fd3ed969 | 2973 | bool sec = arm_is_secure_below_el3(env); |
dbb1fb27 | 2974 | |
a67cf277 AB |
2975 | if (sec) { |
2976 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
2977 | ARMMMUIdxBit_S1SE1 | |
2978 | ARMMMUIdxBit_S1SE0); | |
a67cf277 AB |
2979 | } else { |
2980 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
2981 | ARMMMUIdxBit_S12NSE1 | |
2982 | ARMMMUIdxBit_S12NSE0); | |
fd3ed969 | 2983 | } |
168aa23b PM |
2984 | } |
2985 | ||
fd3ed969 PM |
2986 | static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2987 | uint64_t value) | |
168aa23b | 2988 | { |
fd3ed969 PM |
2989 | /* Note that the 'ALL' scope must invalidate both stage 1 and |
2990 | * stage 2 translations, whereas most other scopes only invalidate | |
2991 | * stage 1 translations. | |
2992 | */ | |
00c8cb0a | 2993 | ARMCPU *cpu = arm_env_get_cpu(env); |
fd3ed969 PM |
2994 | CPUState *cs = CPU(cpu); |
2995 | ||
2996 | if (arm_is_secure_below_el3(env)) { | |
0336cbf8 | 2997 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
2998 | ARMMMUIdxBit_S1SE1 | |
2999 | ARMMMUIdxBit_S1SE0); | |
fd3ed969 PM |
3000 | } else { |
3001 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
0336cbf8 | 3002 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
3003 | ARMMMUIdxBit_S12NSE1 | |
3004 | ARMMMUIdxBit_S12NSE0 | | |
3005 | ARMMMUIdxBit_S2NS); | |
fd3ed969 | 3006 | } else { |
0336cbf8 | 3007 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
3008 | ARMMMUIdxBit_S12NSE1 | |
3009 | ARMMMUIdxBit_S12NSE0); | |
fd3ed969 PM |
3010 | } |
3011 | } | |
168aa23b PM |
3012 | } |
3013 | ||
fd3ed969 | 3014 | static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
fa439fc5 PM |
3015 | uint64_t value) |
3016 | { | |
fd3ed969 PM |
3017 | ARMCPU *cpu = arm_env_get_cpu(env); |
3018 | CPUState *cs = CPU(cpu); | |
3019 | ||
8bd5c820 | 3020 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); |
fd3ed969 PM |
3021 | } |
3022 | ||
43efaa33 PM |
3023 | static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3024 | uint64_t value) | |
3025 | { | |
3026 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3027 | CPUState *cs = CPU(cpu); | |
3028 | ||
8bd5c820 | 3029 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3); |
43efaa33 PM |
3030 | } |
3031 | ||
fd3ed969 PM |
3032 | static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3033 | uint64_t value) | |
3034 | { | |
3035 | /* Note that the 'ALL' scope must invalidate both stage 1 and | |
3036 | * stage 2 translations, whereas most other scopes only invalidate | |
3037 | * stage 1 translations. | |
3038 | */ | |
a67cf277 | 3039 | CPUState *cs = ENV_GET_CPU(env); |
fd3ed969 PM |
3040 | bool sec = arm_is_secure_below_el3(env); |
3041 | bool has_el2 = arm_feature(env, ARM_FEATURE_EL2); | |
a67cf277 AB |
3042 | |
3043 | if (sec) { | |
3044 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3045 | ARMMMUIdxBit_S1SE1 | |
3046 | ARMMMUIdxBit_S1SE0); | |
a67cf277 AB |
3047 | } else if (has_el2) { |
3048 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3049 | ARMMMUIdxBit_S12NSE1 | |
3050 | ARMMMUIdxBit_S12NSE0 | | |
3051 | ARMMMUIdxBit_S2NS); | |
a67cf277 AB |
3052 | } else { |
3053 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3054 | ARMMMUIdxBit_S12NSE1 | |
3055 | ARMMMUIdxBit_S12NSE0); | |
fa439fc5 PM |
3056 | } |
3057 | } | |
3058 | ||
2bfb9d75 PM |
3059 | static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3060 | uint64_t value) | |
3061 | { | |
a67cf277 | 3062 | CPUState *cs = ENV_GET_CPU(env); |
2bfb9d75 | 3063 | |
8bd5c820 | 3064 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); |
2bfb9d75 PM |
3065 | } |
3066 | ||
43efaa33 PM |
3067 | static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3068 | uint64_t value) | |
3069 | { | |
a67cf277 | 3070 | CPUState *cs = ENV_GET_CPU(env); |
43efaa33 | 3071 | |
8bd5c820 | 3072 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3); |
43efaa33 PM |
3073 | } |
3074 | ||
fd3ed969 PM |
3075 | static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3076 | uint64_t value) | |
3077 | { | |
3078 | /* Invalidate by VA, EL1&0 (AArch64 version). | |
3079 | * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, | |
3080 | * since we don't support flush-for-specific-ASID-only or | |
3081 | * flush-last-level-only. | |
3082 | */ | |
3083 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3084 | CPUState *cs = CPU(cpu); | |
3085 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
3086 | ||
3087 | if (arm_is_secure_below_el3(env)) { | |
0336cbf8 | 3088 | tlb_flush_page_by_mmuidx(cs, pageaddr, |
8bd5c820 PM |
3089 | ARMMMUIdxBit_S1SE1 | |
3090 | ARMMMUIdxBit_S1SE0); | |
fd3ed969 | 3091 | } else { |
0336cbf8 | 3092 | tlb_flush_page_by_mmuidx(cs, pageaddr, |
8bd5c820 PM |
3093 | ARMMMUIdxBit_S12NSE1 | |
3094 | ARMMMUIdxBit_S12NSE0); | |
fd3ed969 PM |
3095 | } |
3096 | } | |
3097 | ||
3098 | static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3099 | uint64_t value) | |
fa439fc5 | 3100 | { |
fd3ed969 PM |
3101 | /* Invalidate by VA, EL2 |
3102 | * Currently handles both VAE2 and VALE2, since we don't support | |
3103 | * flush-last-level-only. | |
3104 | */ | |
3105 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3106 | CPUState *cs = CPU(cpu); | |
3107 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
3108 | ||
8bd5c820 | 3109 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); |
fd3ed969 PM |
3110 | } |
3111 | ||
43efaa33 PM |
3112 | static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3113 | uint64_t value) | |
3114 | { | |
3115 | /* Invalidate by VA, EL3 | |
3116 | * Currently handles both VAE3 and VALE3, since we don't support | |
3117 | * flush-last-level-only. | |
3118 | */ | |
3119 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3120 | CPUState *cs = CPU(cpu); | |
3121 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
3122 | ||
8bd5c820 | 3123 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3); |
43efaa33 PM |
3124 | } |
3125 | ||
fd3ed969 PM |
3126 | static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3127 | uint64_t value) | |
3128 | { | |
a67cf277 AB |
3129 | ARMCPU *cpu = arm_env_get_cpu(env); |
3130 | CPUState *cs = CPU(cpu); | |
fd3ed969 | 3131 | bool sec = arm_is_secure_below_el3(env); |
fa439fc5 PM |
3132 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
3133 | ||
a67cf277 AB |
3134 | if (sec) { |
3135 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, | |
8bd5c820 PM |
3136 | ARMMMUIdxBit_S1SE1 | |
3137 | ARMMMUIdxBit_S1SE0); | |
a67cf277 AB |
3138 | } else { |
3139 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, | |
8bd5c820 PM |
3140 | ARMMMUIdxBit_S12NSE1 | |
3141 | ARMMMUIdxBit_S12NSE0); | |
fa439fc5 PM |
3142 | } |
3143 | } | |
3144 | ||
fd3ed969 PM |
3145 | static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3146 | uint64_t value) | |
fa439fc5 | 3147 | { |
a67cf277 | 3148 | CPUState *cs = ENV_GET_CPU(env); |
fd3ed969 | 3149 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
fa439fc5 | 3150 | |
a67cf277 | 3151 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 3152 | ARMMMUIdxBit_S1E2); |
fa439fc5 PM |
3153 | } |
3154 | ||
43efaa33 PM |
3155 | static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3156 | uint64_t value) | |
3157 | { | |
a67cf277 | 3158 | CPUState *cs = ENV_GET_CPU(env); |
43efaa33 PM |
3159 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
3160 | ||
a67cf277 | 3161 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 3162 | ARMMMUIdxBit_S1E3); |
43efaa33 PM |
3163 | } |
3164 | ||
cea66e91 PM |
3165 | static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3166 | uint64_t value) | |
3167 | { | |
3168 | /* Invalidate by IPA. This has to invalidate any structures that | |
3169 | * contain only stage 2 translation information, but does not need | |
3170 | * to apply to structures that contain combined stage 1 and stage 2 | |
3171 | * translation information. | |
3172 | * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. | |
3173 | */ | |
3174 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3175 | CPUState *cs = CPU(cpu); | |
3176 | uint64_t pageaddr; | |
3177 | ||
3178 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
3179 | return; | |
3180 | } | |
3181 | ||
3182 | pageaddr = sextract64(value << 12, 0, 48); | |
3183 | ||
8bd5c820 | 3184 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); |
cea66e91 PM |
3185 | } |
3186 | ||
3187 | static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3188 | uint64_t value) | |
3189 | { | |
a67cf277 | 3190 | CPUState *cs = ENV_GET_CPU(env); |
cea66e91 PM |
3191 | uint64_t pageaddr; |
3192 | ||
3193 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
3194 | return; | |
3195 | } | |
3196 | ||
3197 | pageaddr = sextract64(value << 12, 0, 48); | |
3198 | ||
a67cf277 | 3199 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 3200 | ARMMMUIdxBit_S2NS); |
cea66e91 PM |
3201 | } |
3202 | ||
3f208fd7 PM |
3203 | static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3204 | bool isread) | |
aca3f40b PM |
3205 | { |
3206 | /* We don't implement EL2, so the only control on DC ZVA is the | |
3207 | * bit in the SCTLR which can prohibit access for EL0. | |
3208 | */ | |
137feaa9 | 3209 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) { |
aca3f40b PM |
3210 | return CP_ACCESS_TRAP; |
3211 | } | |
3212 | return CP_ACCESS_OK; | |
3213 | } | |
3214 | ||
3215 | static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3216 | { | |
3217 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3218 | int dzp_bit = 1 << 4; | |
3219 | ||
3220 | /* DZP indicates whether DC ZVA access is allowed */ | |
3f208fd7 | 3221 | if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) { |
aca3f40b PM |
3222 | dzp_bit = 0; |
3223 | } | |
3224 | return cpu->dcz_blocksize | dzp_bit; | |
3225 | } | |
3226 | ||
3f208fd7 PM |
3227 | static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3228 | bool isread) | |
f502cfc2 | 3229 | { |
cdcf1405 | 3230 | if (!(env->pstate & PSTATE_SP)) { |
f502cfc2 PM |
3231 | /* Access to SP_EL0 is undefined if it's being used as |
3232 | * the stack pointer. | |
3233 | */ | |
3234 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
3235 | } | |
3236 | return CP_ACCESS_OK; | |
3237 | } | |
3238 | ||
3239 | static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3240 | { | |
3241 | return env->pstate & PSTATE_SP; | |
3242 | } | |
3243 | ||
3244 | static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
3245 | { | |
3246 | update_spsel(env, val); | |
3247 | } | |
3248 | ||
137feaa9 FA |
3249 | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3250 | uint64_t value) | |
3251 | { | |
3252 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3253 | ||
3254 | if (raw_read(env, ri) == value) { | |
3255 | /* Skip the TLB flush if nothing actually changed; Linux likes | |
3256 | * to do a lot of pointless SCTLR writes. | |
3257 | */ | |
3258 | return; | |
3259 | } | |
3260 | ||
06312feb PM |
3261 | if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { |
3262 | /* M bit is RAZ/WI for PMSA with no MPU implemented */ | |
3263 | value &= ~SCTLR_M; | |
3264 | } | |
3265 | ||
137feaa9 FA |
3266 | raw_write(env, ri, value); |
3267 | /* ??? Lots of these bits are not implemented. */ | |
3268 | /* This may enable/disable the MMU, so do a TLB flush. */ | |
d10eb08f | 3269 | tlb_flush(CPU(cpu)); |
137feaa9 FA |
3270 | } |
3271 | ||
3f208fd7 PM |
3272 | static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3273 | bool isread) | |
03fbf20f PM |
3274 | { |
3275 | if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { | |
f2cae609 | 3276 | return CP_ACCESS_TRAP_FP_EL2; |
03fbf20f PM |
3277 | } |
3278 | if (env->cp15.cptr_el[3] & CPTR_TFP) { | |
f2cae609 | 3279 | return CP_ACCESS_TRAP_FP_EL3; |
03fbf20f PM |
3280 | } |
3281 | return CP_ACCESS_OK; | |
3282 | } | |
3283 | ||
a8d64e73 PM |
3284 | static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3285 | uint64_t value) | |
3286 | { | |
3287 | env->cp15.mdcr_el3 = value & SDCR_VALID_MASK; | |
3288 | } | |
3289 | ||
b0d2b7d0 PM |
3290 | static const ARMCPRegInfo v8_cp_reginfo[] = { |
3291 | /* Minimal set of EL0-visible registers. This will need to be expanded | |
3292 | * significantly for system emulation of AArch64 CPUs. | |
3293 | */ | |
3294 | { .name = "NZCV", .state = ARM_CP_STATE_AA64, | |
3295 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, | |
3296 | .access = PL0_RW, .type = ARM_CP_NZCV }, | |
c2b820fe PM |
3297 | { .name = "DAIF", .state = ARM_CP_STATE_AA64, |
3298 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, | |
7a0e58fa | 3299 | .type = ARM_CP_NO_RAW, |
c2b820fe PM |
3300 | .access = PL0_RW, .accessfn = aa64_daif_access, |
3301 | .fieldoffset = offsetof(CPUARMState, daif), | |
3302 | .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, | |
b0d2b7d0 PM |
3303 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, |
3304 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | |
3305 | .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, | |
3306 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, | |
3307 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | |
3308 | .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, | |
b0d2b7d0 PM |
3309 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, |
3310 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | |
7a0e58fa | 3311 | .access = PL0_R, .type = ARM_CP_NO_RAW, |
aca3f40b PM |
3312 | .readfn = aa64_dczid_read }, |
3313 | { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, | |
3314 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, | |
3315 | .access = PL0_W, .type = ARM_CP_DC_ZVA, | |
3316 | #ifndef CONFIG_USER_ONLY | |
3317 | /* Avoid overhead of an access check that always passes in user-mode */ | |
3318 | .accessfn = aa64_zva_access, | |
3319 | #endif | |
3320 | }, | |
0eef9d98 PM |
3321 | { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, |
3322 | .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, | |
3323 | .access = PL1_R, .type = ARM_CP_CURRENTEL }, | |
8af35c37 PM |
3324 | /* Cache ops: all NOPs since we don't emulate caches */ |
3325 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, | |
3326 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
3327 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3328 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, | |
3329 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
3330 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3331 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, | |
3332 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | |
3333 | .access = PL0_W, .type = ARM_CP_NOP, | |
3334 | .accessfn = aa64_cacheop_access }, | |
3335 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, | |
3336 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
3337 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3338 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, | |
3339 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
3340 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3341 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, | |
3342 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | |
3343 | .access = PL0_W, .type = ARM_CP_NOP, | |
3344 | .accessfn = aa64_cacheop_access }, | |
3345 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, | |
3346 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
3347 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3348 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, | |
3349 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | |
3350 | .access = PL0_W, .type = ARM_CP_NOP, | |
3351 | .accessfn = aa64_cacheop_access }, | |
3352 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, | |
3353 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | |
3354 | .access = PL0_W, .type = ARM_CP_NOP, | |
3355 | .accessfn = aa64_cacheop_access }, | |
3356 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, | |
3357 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
3358 | .access = PL1_W, .type = ARM_CP_NOP }, | |
168aa23b PM |
3359 | /* TLBI operations */ |
3360 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 3361 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, |
7a0e58fa | 3362 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3363 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 3364 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3365 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
7a0e58fa | 3366 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3367 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 3368 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3369 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
7a0e58fa | 3370 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3371 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 3372 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3373 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
7a0e58fa | 3374 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3375 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 3376 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3377 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
7a0e58fa | 3378 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3379 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 3380 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3381 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
7a0e58fa | 3382 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3383 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 3384 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3385 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, |
7a0e58fa | 3386 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3387 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 3388 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3389 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
7a0e58fa | 3390 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3391 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 3392 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3393 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
7a0e58fa | 3394 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3395 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 3396 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3397 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
7a0e58fa | 3398 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3399 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 3400 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3401 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
7a0e58fa | 3402 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3403 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 3404 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3405 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
7a0e58fa | 3406 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3407 | .writefn = tlbi_aa64_vae1_write }, |
cea66e91 PM |
3408 | { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, |
3409 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
3410 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3411 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
3412 | { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, | |
3413 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
3414 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3415 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
83ddf975 PM |
3416 | { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, |
3417 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
3418 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 3419 | .writefn = tlbi_aa64_alle1is_write }, |
43efaa33 PM |
3420 | { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, |
3421 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, | |
3422 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3423 | .writefn = tlbi_aa64_alle1is_write }, | |
cea66e91 PM |
3424 | { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, |
3425 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
3426 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3427 | .writefn = tlbi_aa64_ipas2e1_write }, | |
3428 | { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, | |
3429 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
3430 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3431 | .writefn = tlbi_aa64_ipas2e1_write }, | |
83ddf975 PM |
3432 | { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, |
3433 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
3434 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 3435 | .writefn = tlbi_aa64_alle1_write }, |
43efaa33 PM |
3436 | { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, |
3437 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, | |
3438 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3439 | .writefn = tlbi_aa64_alle1is_write }, | |
19525524 PM |
3440 | #ifndef CONFIG_USER_ONLY |
3441 | /* 64 bit address translation operations */ | |
3442 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
3443 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, | |
060e8a48 | 3444 | .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
19525524 PM |
3445 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, |
3446 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, | |
060e8a48 | 3447 | .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
19525524 PM |
3448 | { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, |
3449 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, | |
060e8a48 | 3450 | .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
19525524 PM |
3451 | { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, |
3452 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, | |
060e8a48 | 3453 | .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
2a47df95 | 3454 | { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 3455 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, |
2a47df95 PM |
3456 | .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
3457 | { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, | |
7a379c7e | 3458 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, |
2a47df95 PM |
3459 | .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
3460 | { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, | |
7a379c7e | 3461 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, |
2a47df95 PM |
3462 | .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
3463 | { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, | |
7a379c7e | 3464 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, |
2a47df95 PM |
3465 | .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
3466 | /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ | |
3467 | { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, | |
3468 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, | |
3469 | .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, | |
3470 | { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, | |
3471 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, | |
3472 | .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, | |
c96fc9b5 EI |
3473 | { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, |
3474 | .type = ARM_CP_ALIAS, | |
3475 | .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, | |
3476 | .access = PL1_RW, .resetvalue = 0, | |
3477 | .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), | |
3478 | .writefn = par_write }, | |
19525524 | 3479 | #endif |
995939a6 | 3480 | /* TLB invalidate last level of translation table walk */ |
9449fdf6 | 3481 | { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
7a0e58fa | 3482 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, |
9449fdf6 | 3483 | { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
7a0e58fa | 3484 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 3485 | .writefn = tlbimvaa_is_write }, |
9449fdf6 | 3486 | { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
7a0e58fa | 3487 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
9449fdf6 | 3488 | { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
7a0e58fa | 3489 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, |
541ef8c2 SS |
3490 | { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, |
3491 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3492 | .writefn = tlbimva_hyp_write }, | |
3493 | { .name = "TLBIMVALHIS", | |
3494 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
3495 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3496 | .writefn = tlbimva_hyp_is_write }, | |
3497 | { .name = "TLBIIPAS2", | |
3498 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
3499 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3500 | .writefn = tlbiipas2_write }, | |
3501 | { .name = "TLBIIPAS2IS", | |
3502 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
3503 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3504 | .writefn = tlbiipas2_is_write }, | |
3505 | { .name = "TLBIIPAS2L", | |
3506 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
3507 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3508 | .writefn = tlbiipas2_write }, | |
3509 | { .name = "TLBIIPAS2LIS", | |
3510 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
3511 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3512 | .writefn = tlbiipas2_is_write }, | |
9449fdf6 PM |
3513 | /* 32 bit cache operations */ |
3514 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
3515 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3516 | { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, | |
3517 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3518 | { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
3519 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3520 | { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, | |
3521 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3522 | { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, | |
3523 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3524 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | |
3525 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3526 | { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
3527 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3528 | { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
3529 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3530 | { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, | |
3531 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3532 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
3533 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3534 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, | |
3535 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3536 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, | |
3537 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3538 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
3539 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3540 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
3541 | { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, |
3542 | .access = PL1_RW, .resetvalue = 0, | |
3543 | .writefn = dacr_write, .raw_writefn = raw_write, | |
3544 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
3545 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a0618a19 | 3546 | { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 3547 | .type = ARM_CP_ALIAS, |
a0618a19 | 3548 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, |
6947f059 EI |
3549 | .access = PL1_RW, |
3550 | .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, | |
a65f1de9 | 3551 | { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 3552 | .type = ARM_CP_ALIAS, |
a65f1de9 | 3553 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
3554 | .access = PL1_RW, |
3555 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, | |
f502cfc2 PM |
3556 | /* We rely on the access checks not allowing the guest to write to the |
3557 | * state field when SPSel indicates that it's being used as the stack | |
3558 | * pointer. | |
3559 | */ | |
3560 | { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, | |
3561 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, | |
3562 | .access = PL1_RW, .accessfn = sp_el0_access, | |
7a0e58fa | 3563 | .type = ARM_CP_ALIAS, |
f502cfc2 | 3564 | .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, |
884b4dee GB |
3565 | { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, |
3566 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 3567 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
884b4dee | 3568 | .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, |
f502cfc2 PM |
3569 | { .name = "SPSel", .state = ARM_CP_STATE_AA64, |
3570 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, | |
7a0e58fa | 3571 | .type = ARM_CP_NO_RAW, |
f502cfc2 | 3572 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, |
03fbf20f PM |
3573 | { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, |
3574 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, | |
3575 | .type = ARM_CP_ALIAS, | |
3576 | .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), | |
3577 | .access = PL2_RW, .accessfn = fpexc32_access }, | |
6a43e0b6 PM |
3578 | { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, |
3579 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, | |
3580 | .access = PL2_RW, .resetvalue = 0, | |
3581 | .writefn = dacr_write, .raw_writefn = raw_write, | |
3582 | .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, | |
3583 | { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, | |
3584 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, | |
3585 | .access = PL2_RW, .resetvalue = 0, | |
3586 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, | |
3587 | { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, | |
3588 | .type = ARM_CP_ALIAS, | |
3589 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, | |
3590 | .access = PL2_RW, | |
3591 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, | |
3592 | { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, | |
3593 | .type = ARM_CP_ALIAS, | |
3594 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, | |
3595 | .access = PL2_RW, | |
3596 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, | |
3597 | { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, | |
3598 | .type = ARM_CP_ALIAS, | |
3599 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, | |
3600 | .access = PL2_RW, | |
3601 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, | |
3602 | { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, | |
3603 | .type = ARM_CP_ALIAS, | |
3604 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, | |
3605 | .access = PL2_RW, | |
3606 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, | |
a8d64e73 PM |
3607 | { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, |
3608 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, | |
3609 | .resetvalue = 0, | |
3610 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) }, | |
3611 | { .name = "SDCR", .type = ARM_CP_ALIAS, | |
3612 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1, | |
3613 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, | |
3614 | .writefn = sdcr_write, | |
3615 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, | |
b0d2b7d0 PM |
3616 | REGINFO_SENTINEL |
3617 | }; | |
3618 | ||
d42e3c26 | 3619 | /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ |
4771cd01 | 3620 | static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { |
d42e3c26 EI |
3621 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, |
3622 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | |
3623 | .access = PL2_RW, | |
3624 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | |
f149e3e8 | 3625 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 3626 | .type = ARM_CP_NO_RAW, |
f149e3e8 EI |
3627 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
3628 | .access = PL2_RW, | |
3629 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | |
c6f19164 GB |
3630 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
3631 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
3632 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
95f949ac EI |
3633 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
3634 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
3635 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3636 | .resetvalue = 0 }, | |
3637 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
3638 | .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, | |
3639 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2179ef95 PM |
3640 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
3641 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
3642 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3643 | .resetvalue = 0 }, | |
3644 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
3645 | .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, | |
3646 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3647 | .resetvalue = 0 }, | |
37cd6c24 PM |
3648 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
3649 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
3650 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3651 | .resetvalue = 0 }, | |
3652 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
3653 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
3654 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3655 | .resetvalue = 0 }, | |
06ec4c8c EI |
3656 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
3657 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
3658 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
68e9c2fe EI |
3659 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH, |
3660 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
3661 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
3662 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b698e9cf EI |
3663 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
3664 | .cp = 15, .opc1 = 6, .crm = 2, | |
3665 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
3666 | .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | |
3667 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
3668 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
3669 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b9cb5323 EI |
3670 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
3671 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
3672 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
ff05f37b EI |
3673 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
3674 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
3675 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
a57633c0 EI |
3676 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
3677 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
3678 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3679 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
3680 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
3681 | .resetvalue = 0 }, | |
0b6440af EI |
3682 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
3683 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
3684 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
edac4d8a EI |
3685 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
3686 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
3687 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3688 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
3689 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
3690 | .resetvalue = 0 }, | |
b0e66d95 EI |
3691 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
3692 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
3693 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3694 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
3695 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
3696 | .resetvalue = 0 }, | |
3697 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
3698 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
3699 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3700 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
3701 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
3702 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
14cc7b54 SF |
3703 | { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, |
3704 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | |
d6c8cf81 PM |
3705 | .access = PL2_RW, .accessfn = access_tda, |
3706 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
59e05530 EI |
3707 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, |
3708 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
3709 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
3710 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2a5a9abd AF |
3711 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
3712 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
3713 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
d42e3c26 EI |
3714 | REGINFO_SENTINEL |
3715 | }; | |
3716 | ||
f149e3e8 EI |
3717 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
3718 | { | |
3719 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3720 | uint64_t valid_mask = HCR_MASK; | |
3721 | ||
3722 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
3723 | valid_mask &= ~HCR_HCD; | |
3724 | } else { | |
3725 | valid_mask &= ~HCR_TSC; | |
3726 | } | |
3727 | ||
3728 | /* Clear RES0 bits. */ | |
3729 | value &= valid_mask; | |
3730 | ||
3731 | /* These bits change the MMU setup: | |
3732 | * HCR_VM enables stage 2 translation | |
3733 | * HCR_PTW forbids certain page-table setups | |
3734 | * HCR_DC Disables stage1 and enables stage2 translation | |
3735 | */ | |
3736 | if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { | |
d10eb08f | 3737 | tlb_flush(CPU(cpu)); |
f149e3e8 EI |
3738 | } |
3739 | raw_write(env, ri, value); | |
3740 | } | |
3741 | ||
4771cd01 | 3742 | static const ARMCPRegInfo el2_cp_reginfo[] = { |
f149e3e8 EI |
3743 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
3744 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, | |
3745 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
3746 | .writefn = hcr_write }, | |
3b685ba7 | 3747 | { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 3748 | .type = ARM_CP_ALIAS, |
3b685ba7 EI |
3749 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, |
3750 | .access = PL2_RW, | |
3751 | .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, | |
f2c30f42 | 3752 | { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, |
f2c30f42 EI |
3753 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, |
3754 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, | |
63b60551 EI |
3755 | { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, |
3756 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, | |
3757 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, | |
3b685ba7 | 3758 | { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 3759 | .type = ARM_CP_ALIAS, |
3b685ba7 | 3760 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
3761 | .access = PL2_RW, |
3762 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, | |
d42e3c26 EI |
3763 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, |
3764 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | |
3765 | .access = PL2_RW, .writefn = vbar_write, | |
3766 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), | |
3767 | .resetvalue = 0 }, | |
884b4dee GB |
3768 | { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, |
3769 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 3770 | .access = PL3_RW, .type = ARM_CP_ALIAS, |
884b4dee | 3771 | .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, |
c6f19164 GB |
3772 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
3773 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
3774 | .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, | |
3775 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) }, | |
95f949ac EI |
3776 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
3777 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
3778 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), | |
3779 | .resetvalue = 0 }, | |
3780 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
3781 | .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, | |
3782 | .access = PL2_RW, .type = ARM_CP_ALIAS, | |
3783 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, | |
2179ef95 PM |
3784 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
3785 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
3786 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3787 | .resetvalue = 0 }, | |
3788 | /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ | |
3789 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
3790 | .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, | |
3791 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3792 | .resetvalue = 0 }, | |
37cd6c24 PM |
3793 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
3794 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
3795 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3796 | .resetvalue = 0 }, | |
3797 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
3798 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
3799 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3800 | .resetvalue = 0 }, | |
06ec4c8c EI |
3801 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
3802 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
6459b94c PM |
3803 | .access = PL2_RW, |
3804 | /* no .writefn needed as this can't cause an ASID change; | |
3805 | * no .raw_writefn or .resetfn needed as we never use mask/base_mask | |
3806 | */ | |
06ec4c8c | 3807 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, |
68e9c2fe EI |
3808 | { .name = "VTCR", .state = ARM_CP_STATE_AA32, |
3809 | .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 | 3810 | .type = ARM_CP_ALIAS, |
68e9c2fe EI |
3811 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
3812 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, | |
3813 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, | |
3814 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 PM |
3815 | .access = PL2_RW, |
3816 | /* no .writefn needed as this can't cause an ASID change; | |
3817 | * no .raw_writefn or .resetfn needed as we never use mask/base_mask | |
3818 | */ | |
68e9c2fe | 3819 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, |
b698e9cf EI |
3820 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
3821 | .cp = 15, .opc1 = 6, .crm = 2, | |
3822 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
3823 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
3824 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), | |
3825 | .writefn = vttbr_write }, | |
3826 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
3827 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
3828 | .access = PL2_RW, .writefn = vttbr_write, | |
3829 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, | |
b9cb5323 EI |
3830 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
3831 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
3832 | .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, | |
3833 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, | |
ff05f37b EI |
3834 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
3835 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
3836 | .access = PL2_RW, .resetvalue = 0, | |
3837 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, | |
a57633c0 EI |
3838 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
3839 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
3840 | .access = PL2_RW, .resetvalue = 0, | |
3841 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, | |
3842 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
3843 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
a57633c0 | 3844 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
541ef8c2 SS |
3845 | { .name = "TLBIALLNSNH", |
3846 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
3847 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3848 | .writefn = tlbiall_nsnh_write }, | |
3849 | { .name = "TLBIALLNSNHIS", | |
3850 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
3851 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3852 | .writefn = tlbiall_nsnh_is_write }, | |
3853 | { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
3854 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3855 | .writefn = tlbiall_hyp_write }, | |
3856 | { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
3857 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3858 | .writefn = tlbiall_hyp_is_write }, | |
3859 | { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
3860 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3861 | .writefn = tlbimva_hyp_write }, | |
3862 | { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
3863 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3864 | .writefn = tlbimva_hyp_is_write }, | |
51da9014 EI |
3865 | { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, |
3866 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
3867 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 3868 | .writefn = tlbi_aa64_alle2_write }, |
8742d49d EI |
3869 | { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, |
3870 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
3871 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 3872 | .writefn = tlbi_aa64_vae2_write }, |
2bfb9d75 PM |
3873 | { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, |
3874 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, | |
3875 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3876 | .writefn = tlbi_aa64_vae2_write }, | |
3877 | { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, | |
3878 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
3879 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3880 | .writefn = tlbi_aa64_alle2is_write }, | |
8742d49d EI |
3881 | { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, |
3882 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
3883 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 3884 | .writefn = tlbi_aa64_vae2is_write }, |
2bfb9d75 PM |
3885 | { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, |
3886 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
3887 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3888 | .writefn = tlbi_aa64_vae2is_write }, | |
edac4d8a | 3889 | #ifndef CONFIG_USER_ONLY |
2a47df95 PM |
3890 | /* Unlike the other EL2-related AT operations, these must |
3891 | * UNDEF from EL3 if EL2 is not implemented, which is why we | |
3892 | * define them here rather than with the rest of the AT ops. | |
3893 | */ | |
3894 | { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, | |
3895 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
3896 | .access = PL2_W, .accessfn = at_s1e2_access, | |
3897 | .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, | |
3898 | { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, | |
3899 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | |
3900 | .access = PL2_W, .accessfn = at_s1e2_access, | |
3901 | .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, | |
14db7fe0 PM |
3902 | /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE |
3903 | * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 | |
3904 | * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose | |
3905 | * to behave as if SCR.NS was 1. | |
3906 | */ | |
3907 | { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
3908 | .access = PL2_W, | |
3909 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, | |
3910 | { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | |
3911 | .access = PL2_W, | |
3912 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, | |
0b6440af EI |
3913 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
3914 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
3915 | /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the | |
3916 | * reset values as IMPDEF. We choose to reset to 3 to comply with | |
3917 | * both ARMv7 and ARMv8. | |
3918 | */ | |
3919 | .access = PL2_RW, .resetvalue = 3, | |
3920 | .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, | |
edac4d8a EI |
3921 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
3922 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
3923 | .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, | |
3924 | .writefn = gt_cntvoff_write, | |
3925 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
3926 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
3927 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, | |
3928 | .writefn = gt_cntvoff_write, | |
3929 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
b0e66d95 EI |
3930 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
3931 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
3932 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
3933 | .type = ARM_CP_IO, .access = PL2_RW, | |
3934 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
3935 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
3936 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
3937 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO, | |
3938 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
3939 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
3940 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
d44ec156 | 3941 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, |
b0e66d95 EI |
3942 | .resetfn = gt_hyp_timer_reset, |
3943 | .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, | |
3944 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
3945 | .type = ARM_CP_IO, | |
3946 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
3947 | .access = PL2_RW, | |
3948 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), | |
3949 | .resetvalue = 0, | |
3950 | .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, | |
edac4d8a | 3951 | #endif |
14cc7b54 SF |
3952 | /* The only field of MDCR_EL2 that has a defined architectural reset value |
3953 | * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we | |
3954 | * don't impelment any PMU event counters, so using zero as a reset | |
3955 | * value for MDCR_EL2 is okay | |
3956 | */ | |
3957 | { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, | |
3958 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | |
3959 | .access = PL2_RW, .resetvalue = 0, | |
3960 | .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), }, | |
59e05530 EI |
3961 | { .name = "HPFAR", .state = ARM_CP_STATE_AA32, |
3962 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
3963 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
3964 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
3965 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, | |
3966 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
3967 | .access = PL2_RW, | |
3968 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
2a5a9abd AF |
3969 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
3970 | .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
3971 | .access = PL2_RW, | |
3972 | .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, | |
3b685ba7 EI |
3973 | REGINFO_SENTINEL |
3974 | }; | |
3975 | ||
2f027fc5 PM |
3976 | static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3977 | bool isread) | |
3978 | { | |
3979 | /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. | |
3980 | * At Secure EL1 it traps to EL3. | |
3981 | */ | |
3982 | if (arm_current_el(env) == 3) { | |
3983 | return CP_ACCESS_OK; | |
3984 | } | |
3985 | if (arm_is_secure_below_el3(env)) { | |
3986 | return CP_ACCESS_TRAP_EL3; | |
3987 | } | |
3988 | /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ | |
3989 | if (isread) { | |
3990 | return CP_ACCESS_OK; | |
3991 | } | |
3992 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
3993 | } | |
3994 | ||
60fb1a87 GB |
3995 | static const ARMCPRegInfo el3_cp_reginfo[] = { |
3996 | { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, | |
3997 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, | |
3998 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), | |
3999 | .resetvalue = 0, .writefn = scr_write }, | |
7a0e58fa | 4000 | { .name = "SCR", .type = ARM_CP_ALIAS, |
60fb1a87 | 4001 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, |
efe4a274 PM |
4002 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
4003 | .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), | |
b061a82b | 4004 | .writefn = scr_write }, |
60fb1a87 GB |
4005 | { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, |
4006 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, | |
4007 | .access = PL3_RW, .resetvalue = 0, | |
4008 | .fieldoffset = offsetof(CPUARMState, cp15.sder) }, | |
4009 | { .name = "SDER", | |
4010 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, | |
4011 | .access = PL3_RW, .resetvalue = 0, | |
4012 | .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, | |
60fb1a87 | 4013 | { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, |
efe4a274 PM |
4014 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
4015 | .writefn = vbar_write, .resetvalue = 0, | |
60fb1a87 | 4016 | .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, |
7dd8c9af FA |
4017 | { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, |
4018 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, | |
4019 | .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
4020 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, | |
11f136ee FA |
4021 | { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, |
4022 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, | |
6459b94c PM |
4023 | .access = PL3_RW, |
4024 | /* no .writefn needed as this can't cause an ASID change; | |
811595a2 PM |
4025 | * we must provide a .raw_writefn and .resetfn because we handle |
4026 | * reset and migration for the AArch32 TTBCR(S), which might be | |
4027 | * using mask and base_mask. | |
6459b94c | 4028 | */ |
811595a2 | 4029 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, |
11f136ee | 4030 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, |
81547d66 | 4031 | { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4032 | .type = ARM_CP_ALIAS, |
81547d66 EI |
4033 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, |
4034 | .access = PL3_RW, | |
4035 | .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, | |
f2c30f42 | 4036 | { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, |
f2c30f42 EI |
4037 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, |
4038 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, | |
63b60551 EI |
4039 | { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, |
4040 | .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, | |
4041 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, | |
81547d66 | 4042 | { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4043 | .type = ARM_CP_ALIAS, |
81547d66 | 4044 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
4045 | .access = PL3_RW, |
4046 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) }, | |
a1ba125c EI |
4047 | { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, |
4048 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, | |
4049 | .access = PL3_RW, .writefn = vbar_write, | |
4050 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), | |
4051 | .resetvalue = 0 }, | |
c6f19164 GB |
4052 | { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, |
4053 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, | |
4054 | .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, | |
4055 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, | |
4cfb8ad8 PM |
4056 | { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, |
4057 | .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, | |
4058 | .access = PL3_RW, .resetvalue = 0, | |
4059 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, | |
2179ef95 PM |
4060 | { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64, |
4061 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, | |
4062 | .access = PL3_RW, .type = ARM_CP_CONST, | |
4063 | .resetvalue = 0 }, | |
37cd6c24 PM |
4064 | { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, |
4065 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, | |
4066 | .access = PL3_RW, .type = ARM_CP_CONST, | |
4067 | .resetvalue = 0 }, | |
4068 | { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, | |
4069 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, | |
4070 | .access = PL3_RW, .type = ARM_CP_CONST, | |
4071 | .resetvalue = 0 }, | |
43efaa33 PM |
4072 | { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, |
4073 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, | |
4074 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
4075 | .writefn = tlbi_aa64_alle3is_write }, | |
4076 | { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, | |
4077 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, | |
4078 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
4079 | .writefn = tlbi_aa64_vae3is_write }, | |
4080 | { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, | |
4081 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, | |
4082 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
4083 | .writefn = tlbi_aa64_vae3is_write }, | |
4084 | { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, | |
4085 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, | |
4086 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
4087 | .writefn = tlbi_aa64_alle3_write }, | |
4088 | { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, | |
4089 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, | |
4090 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
4091 | .writefn = tlbi_aa64_vae3_write }, | |
4092 | { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, | |
4093 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, | |
4094 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
4095 | .writefn = tlbi_aa64_vae3_write }, | |
0f1a3b24 FA |
4096 | REGINFO_SENTINEL |
4097 | }; | |
4098 | ||
3f208fd7 PM |
4099 | static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4100 | bool isread) | |
7da845b0 PM |
4101 | { |
4102 | /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, | |
4103 | * but the AArch32 CTR has its own reginfo struct) | |
4104 | */ | |
137feaa9 | 4105 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) { |
7da845b0 PM |
4106 | return CP_ACCESS_TRAP; |
4107 | } | |
4108 | return CP_ACCESS_OK; | |
4109 | } | |
4110 | ||
1424ca8d DM |
4111 | static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4112 | uint64_t value) | |
4113 | { | |
4114 | /* Writes to OSLAR_EL1 may update the OS lock status, which can be | |
4115 | * read via a bit in OSLSR_EL1. | |
4116 | */ | |
4117 | int oslock; | |
4118 | ||
4119 | if (ri->state == ARM_CP_STATE_AA32) { | |
4120 | oslock = (value == 0xC5ACCE55); | |
4121 | } else { | |
4122 | oslock = value & 1; | |
4123 | } | |
4124 | ||
4125 | env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); | |
4126 | } | |
4127 | ||
50300698 | 4128 | static const ARMCPRegInfo debug_cp_reginfo[] = { |
50300698 | 4129 | /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped |
10aae104 PM |
4130 | * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; |
4131 | * unlike DBGDRAR it is never accessible from EL0. | |
4132 | * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 | |
4133 | * accessor. | |
50300698 PM |
4134 | */ |
4135 | { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
91b0a238 PM |
4136 | .access = PL0_R, .accessfn = access_tdra, |
4137 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
10aae104 PM |
4138 | { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, |
4139 | .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, | |
91b0a238 PM |
4140 | .access = PL1_R, .accessfn = access_tdra, |
4141 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
50300698 | 4142 | { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
91b0a238 PM |
4143 | .access = PL0_R, .accessfn = access_tdra, |
4144 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
17a9eb53 | 4145 | /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ |
10aae104 PM |
4146 | { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, |
4147 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
d6c8cf81 | 4148 | .access = PL1_RW, .accessfn = access_tda, |
0e5e8935 PM |
4149 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), |
4150 | .resetvalue = 0 }, | |
5e8b12ff PM |
4151 | /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. |
4152 | * We don't implement the configurable EL0 access. | |
4153 | */ | |
4154 | { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH, | |
4155 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
7a0e58fa | 4156 | .type = ARM_CP_ALIAS, |
d6c8cf81 | 4157 | .access = PL1_R, .accessfn = access_tda, |
b061a82b | 4158 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, |
10aae104 PM |
4159 | { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, |
4160 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, | |
1424ca8d | 4161 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
187f678d | 4162 | .accessfn = access_tdosa, |
1424ca8d DM |
4163 | .writefn = oslar_write }, |
4164 | { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, | |
4165 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, | |
4166 | .access = PL1_R, .resetvalue = 10, | |
187f678d | 4167 | .accessfn = access_tdosa, |
1424ca8d | 4168 | .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, |
5e8b12ff PM |
4169 | /* Dummy OSDLR_EL1: 32-bit Linux will read this */ |
4170 | { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, | |
4171 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, | |
187f678d PM |
4172 | .access = PL1_RW, .accessfn = access_tdosa, |
4173 | .type = ARM_CP_NOP }, | |
5e8b12ff PM |
4174 | /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't |
4175 | * implement vector catch debug events yet. | |
4176 | */ | |
4177 | { .name = "DBGVCR", | |
4178 | .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
d6c8cf81 PM |
4179 | .access = PL1_RW, .accessfn = access_tda, |
4180 | .type = ARM_CP_NOP }, | |
4d2ec4da PM |
4181 | /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor |
4182 | * to save and restore a 32-bit guest's DBGVCR) | |
4183 | */ | |
4184 | { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, | |
4185 | .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, | |
4186 | .access = PL2_RW, .accessfn = access_tda, | |
4187 | .type = ARM_CP_NOP }, | |
5dbdc434 PM |
4188 | /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications |
4189 | * Channel but Linux may try to access this register. The 32-bit | |
4190 | * alias is DBGDCCINT. | |
4191 | */ | |
4192 | { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, | |
4193 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
4194 | .access = PL1_RW, .accessfn = access_tda, | |
4195 | .type = ARM_CP_NOP }, | |
50300698 PM |
4196 | REGINFO_SENTINEL |
4197 | }; | |
4198 | ||
4199 | static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | |
4200 | /* 64 bit access versions of the (dummy) debug registers */ | |
4201 | { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, | |
4202 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
4203 | { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | |
4204 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
4205 | REGINFO_SENTINEL | |
4206 | }; | |
4207 | ||
9ee98ce8 PM |
4208 | void hw_watchpoint_update(ARMCPU *cpu, int n) |
4209 | { | |
4210 | CPUARMState *env = &cpu->env; | |
4211 | vaddr len = 0; | |
4212 | vaddr wvr = env->cp15.dbgwvr[n]; | |
4213 | uint64_t wcr = env->cp15.dbgwcr[n]; | |
4214 | int mask; | |
4215 | int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; | |
4216 | ||
4217 | if (env->cpu_watchpoint[n]) { | |
4218 | cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); | |
4219 | env->cpu_watchpoint[n] = NULL; | |
4220 | } | |
4221 | ||
4222 | if (!extract64(wcr, 0, 1)) { | |
4223 | /* E bit clear : watchpoint disabled */ | |
4224 | return; | |
4225 | } | |
4226 | ||
4227 | switch (extract64(wcr, 3, 2)) { | |
4228 | case 0: | |
4229 | /* LSC 00 is reserved and must behave as if the wp is disabled */ | |
4230 | return; | |
4231 | case 1: | |
4232 | flags |= BP_MEM_READ; | |
4233 | break; | |
4234 | case 2: | |
4235 | flags |= BP_MEM_WRITE; | |
4236 | break; | |
4237 | case 3: | |
4238 | flags |= BP_MEM_ACCESS; | |
4239 | break; | |
4240 | } | |
4241 | ||
4242 | /* Attempts to use both MASK and BAS fields simultaneously are | |
4243 | * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, | |
4244 | * thus generating a watchpoint for every byte in the masked region. | |
4245 | */ | |
4246 | mask = extract64(wcr, 24, 4); | |
4247 | if (mask == 1 || mask == 2) { | |
4248 | /* Reserved values of MASK; we must act as if the mask value was | |
4249 | * some non-reserved value, or as if the watchpoint were disabled. | |
4250 | * We choose the latter. | |
4251 | */ | |
4252 | return; | |
4253 | } else if (mask) { | |
4254 | /* Watchpoint covers an aligned area up to 2GB in size */ | |
4255 | len = 1ULL << mask; | |
4256 | /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE | |
4257 | * whether the watchpoint fires when the unmasked bits match; we opt | |
4258 | * to generate the exceptions. | |
4259 | */ | |
4260 | wvr &= ~(len - 1); | |
4261 | } else { | |
4262 | /* Watchpoint covers bytes defined by the byte address select bits */ | |
4263 | int bas = extract64(wcr, 5, 8); | |
4264 | int basstart; | |
4265 | ||
4266 | if (bas == 0) { | |
4267 | /* This must act as if the watchpoint is disabled */ | |
4268 | return; | |
4269 | } | |
4270 | ||
4271 | if (extract64(wvr, 2, 1)) { | |
4272 | /* Deprecated case of an only 4-aligned address. BAS[7:4] are | |
4273 | * ignored, and BAS[3:0] define which bytes to watch. | |
4274 | */ | |
4275 | bas &= 0xf; | |
4276 | } | |
4277 | /* The BAS bits are supposed to be programmed to indicate a contiguous | |
4278 | * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether | |
4279 | * we fire for each byte in the word/doubleword addressed by the WVR. | |
4280 | * We choose to ignore any non-zero bits after the first range of 1s. | |
4281 | */ | |
4282 | basstart = ctz32(bas); | |
4283 | len = cto32(bas >> basstart); | |
4284 | wvr += basstart; | |
4285 | } | |
4286 | ||
4287 | cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, | |
4288 | &env->cpu_watchpoint[n]); | |
4289 | } | |
4290 | ||
4291 | void hw_watchpoint_update_all(ARMCPU *cpu) | |
4292 | { | |
4293 | int i; | |
4294 | CPUARMState *env = &cpu->env; | |
4295 | ||
4296 | /* Completely clear out existing QEMU watchpoints and our array, to | |
4297 | * avoid possible stale entries following migration load. | |
4298 | */ | |
4299 | cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); | |
4300 | memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); | |
4301 | ||
4302 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { | |
4303 | hw_watchpoint_update(cpu, i); | |
4304 | } | |
4305 | } | |
4306 | ||
4307 | static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4308 | uint64_t value) | |
4309 | { | |
4310 | ARMCPU *cpu = arm_env_get_cpu(env); | |
4311 | int i = ri->crm; | |
4312 | ||
4313 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, the | |
4314 | * register reads and behaves as if values written are sign extended. | |
4315 | * Bits [1:0] are RES0. | |
4316 | */ | |
4317 | value = sextract64(value, 0, 49) & ~3ULL; | |
4318 | ||
4319 | raw_write(env, ri, value); | |
4320 | hw_watchpoint_update(cpu, i); | |
4321 | } | |
4322 | ||
4323 | static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4324 | uint64_t value) | |
4325 | { | |
4326 | ARMCPU *cpu = arm_env_get_cpu(env); | |
4327 | int i = ri->crm; | |
4328 | ||
4329 | raw_write(env, ri, value); | |
4330 | hw_watchpoint_update(cpu, i); | |
4331 | } | |
4332 | ||
46747d15 PM |
4333 | void hw_breakpoint_update(ARMCPU *cpu, int n) |
4334 | { | |
4335 | CPUARMState *env = &cpu->env; | |
4336 | uint64_t bvr = env->cp15.dbgbvr[n]; | |
4337 | uint64_t bcr = env->cp15.dbgbcr[n]; | |
4338 | vaddr addr; | |
4339 | int bt; | |
4340 | int flags = BP_CPU; | |
4341 | ||
4342 | if (env->cpu_breakpoint[n]) { | |
4343 | cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); | |
4344 | env->cpu_breakpoint[n] = NULL; | |
4345 | } | |
4346 | ||
4347 | if (!extract64(bcr, 0, 1)) { | |
4348 | /* E bit clear : watchpoint disabled */ | |
4349 | return; | |
4350 | } | |
4351 | ||
4352 | bt = extract64(bcr, 20, 4); | |
4353 | ||
4354 | switch (bt) { | |
4355 | case 4: /* unlinked address mismatch (reserved if AArch64) */ | |
4356 | case 5: /* linked address mismatch (reserved if AArch64) */ | |
4357 | qemu_log_mask(LOG_UNIMP, | |
4358 | "arm: address mismatch breakpoint types not implemented"); | |
4359 | return; | |
4360 | case 0: /* unlinked address match */ | |
4361 | case 1: /* linked address match */ | |
4362 | { | |
4363 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, | |
4364 | * we behave as if the register was sign extended. Bits [1:0] are | |
4365 | * RES0. The BAS field is used to allow setting breakpoints on 16 | |
4366 | * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether | |
4367 | * a bp will fire if the addresses covered by the bp and the addresses | |
4368 | * covered by the insn overlap but the insn doesn't start at the | |
4369 | * start of the bp address range. We choose to require the insn and | |
4370 | * the bp to have the same address. The constraints on writing to | |
4371 | * BAS enforced in dbgbcr_write mean we have only four cases: | |
4372 | * 0b0000 => no breakpoint | |
4373 | * 0b0011 => breakpoint on addr | |
4374 | * 0b1100 => breakpoint on addr + 2 | |
4375 | * 0b1111 => breakpoint on addr | |
4376 | * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). | |
4377 | */ | |
4378 | int bas = extract64(bcr, 5, 4); | |
4379 | addr = sextract64(bvr, 0, 49) & ~3ULL; | |
4380 | if (bas == 0) { | |
4381 | return; | |
4382 | } | |
4383 | if (bas == 0xc) { | |
4384 | addr += 2; | |
4385 | } | |
4386 | break; | |
4387 | } | |
4388 | case 2: /* unlinked context ID match */ | |
4389 | case 8: /* unlinked VMID match (reserved if no EL2) */ | |
4390 | case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ | |
4391 | qemu_log_mask(LOG_UNIMP, | |
4392 | "arm: unlinked context breakpoint types not implemented"); | |
4393 | return; | |
4394 | case 9: /* linked VMID match (reserved if no EL2) */ | |
4395 | case 11: /* linked context ID and VMID match (reserved if no EL2) */ | |
4396 | case 3: /* linked context ID match */ | |
4397 | default: | |
4398 | /* We must generate no events for Linked context matches (unless | |
4399 | * they are linked to by some other bp/wp, which is handled in | |
4400 | * updates for the linking bp/wp). We choose to also generate no events | |
4401 | * for reserved values. | |
4402 | */ | |
4403 | return; | |
4404 | } | |
4405 | ||
4406 | cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); | |
4407 | } | |
4408 | ||
4409 | void hw_breakpoint_update_all(ARMCPU *cpu) | |
4410 | { | |
4411 | int i; | |
4412 | CPUARMState *env = &cpu->env; | |
4413 | ||
4414 | /* Completely clear out existing QEMU breakpoints and our array, to | |
4415 | * avoid possible stale entries following migration load. | |
4416 | */ | |
4417 | cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); | |
4418 | memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); | |
4419 | ||
4420 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { | |
4421 | hw_breakpoint_update(cpu, i); | |
4422 | } | |
4423 | } | |
4424 | ||
4425 | static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4426 | uint64_t value) | |
4427 | { | |
4428 | ARMCPU *cpu = arm_env_get_cpu(env); | |
4429 | int i = ri->crm; | |
4430 | ||
4431 | raw_write(env, ri, value); | |
4432 | hw_breakpoint_update(cpu, i); | |
4433 | } | |
4434 | ||
4435 | static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4436 | uint64_t value) | |
4437 | { | |
4438 | ARMCPU *cpu = arm_env_get_cpu(env); | |
4439 | int i = ri->crm; | |
4440 | ||
4441 | /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only | |
4442 | * copy of BAS[0]. | |
4443 | */ | |
4444 | value = deposit64(value, 6, 1, extract64(value, 5, 1)); | |
4445 | value = deposit64(value, 8, 1, extract64(value, 7, 1)); | |
4446 | ||
4447 | raw_write(env, ri, value); | |
4448 | hw_breakpoint_update(cpu, i); | |
4449 | } | |
4450 | ||
50300698 | 4451 | static void define_debug_regs(ARMCPU *cpu) |
0b45451e | 4452 | { |
50300698 PM |
4453 | /* Define v7 and v8 architectural debug registers. |
4454 | * These are just dummy implementations for now. | |
0b45451e PM |
4455 | */ |
4456 | int i; | |
3ff6fc91 | 4457 | int wrps, brps, ctx_cmps; |
48eb3ae6 PM |
4458 | ARMCPRegInfo dbgdidr = { |
4459 | .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
d6c8cf81 PM |
4460 | .access = PL0_R, .accessfn = access_tda, |
4461 | .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr, | |
48eb3ae6 PM |
4462 | }; |
4463 | ||
3ff6fc91 | 4464 | /* Note that all these register fields hold "number of Xs minus 1". */ |
48eb3ae6 PM |
4465 | brps = extract32(cpu->dbgdidr, 24, 4); |
4466 | wrps = extract32(cpu->dbgdidr, 28, 4); | |
3ff6fc91 PM |
4467 | ctx_cmps = extract32(cpu->dbgdidr, 20, 4); |
4468 | ||
4469 | assert(ctx_cmps <= brps); | |
48eb3ae6 PM |
4470 | |
4471 | /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties | |
4472 | * of the debug registers such as number of breakpoints; | |
4473 | * check that if they both exist then they agree. | |
4474 | */ | |
4475 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
4476 | assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps); | |
4477 | assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps); | |
3ff6fc91 | 4478 | assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps); |
48eb3ae6 | 4479 | } |
0b45451e | 4480 | |
48eb3ae6 | 4481 | define_one_arm_cp_reg(cpu, &dbgdidr); |
50300698 PM |
4482 | define_arm_cp_regs(cpu, debug_cp_reginfo); |
4483 | ||
4484 | if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { | |
4485 | define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); | |
4486 | } | |
4487 | ||
48eb3ae6 | 4488 | for (i = 0; i < brps + 1; i++) { |
0b45451e | 4489 | ARMCPRegInfo dbgregs[] = { |
10aae104 PM |
4490 | { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH, |
4491 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, | |
d6c8cf81 | 4492 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
4493 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), |
4494 | .writefn = dbgbvr_write, .raw_writefn = raw_write | |
4495 | }, | |
10aae104 PM |
4496 | { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH, |
4497 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, | |
d6c8cf81 | 4498 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
4499 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), |
4500 | .writefn = dbgbcr_write, .raw_writefn = raw_write | |
4501 | }, | |
48eb3ae6 PM |
4502 | REGINFO_SENTINEL |
4503 | }; | |
4504 | define_arm_cp_regs(cpu, dbgregs); | |
4505 | } | |
4506 | ||
4507 | for (i = 0; i < wrps + 1; i++) { | |
4508 | ARMCPRegInfo dbgregs[] = { | |
10aae104 PM |
4509 | { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH, |
4510 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, | |
d6c8cf81 | 4511 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
4512 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), |
4513 | .writefn = dbgwvr_write, .raw_writefn = raw_write | |
4514 | }, | |
10aae104 PM |
4515 | { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH, |
4516 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, | |
d6c8cf81 | 4517 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
4518 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), |
4519 | .writefn = dbgwcr_write, .raw_writefn = raw_write | |
4520 | }, | |
4521 | REGINFO_SENTINEL | |
0b45451e PM |
4522 | }; |
4523 | define_arm_cp_regs(cpu, dbgregs); | |
4524 | } | |
4525 | } | |
4526 | ||
2ceb98c0 PM |
4527 | void register_cp_regs_for_features(ARMCPU *cpu) |
4528 | { | |
4529 | /* Register all the coprocessor registers based on feature bits */ | |
4530 | CPUARMState *env = &cpu->env; | |
4531 | if (arm_feature(env, ARM_FEATURE_M)) { | |
4532 | /* M profile has no coprocessor registers */ | |
4533 | return; | |
4534 | } | |
4535 | ||
e9aa6c21 | 4536 | define_arm_cp_regs(cpu, cp_reginfo); |
9449fdf6 PM |
4537 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
4538 | /* Must go early as it is full of wildcards that may be | |
4539 | * overridden by later definitions. | |
4540 | */ | |
4541 | define_arm_cp_regs(cpu, not_v8_cp_reginfo); | |
4542 | } | |
4543 | ||
7d57f408 | 4544 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8515a092 PM |
4545 | /* The ID registers all have impdef reset values */ |
4546 | ARMCPRegInfo v6_idregs[] = { | |
0ff644a7 PM |
4547 | { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, |
4548 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
4549 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4550 | .resetvalue = cpu->id_pfr0 }, |
0ff644a7 PM |
4551 | { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, |
4552 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | |
4553 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4554 | .resetvalue = cpu->id_pfr1 }, |
0ff644a7 PM |
4555 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, |
4556 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | |
4557 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4558 | .resetvalue = cpu->id_dfr0 }, |
0ff644a7 PM |
4559 | { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, |
4560 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, | |
4561 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4562 | .resetvalue = cpu->id_afr0 }, |
0ff644a7 PM |
4563 | { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, |
4564 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, | |
4565 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4566 | .resetvalue = cpu->id_mmfr0 }, |
0ff644a7 PM |
4567 | { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, |
4568 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, | |
4569 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4570 | .resetvalue = cpu->id_mmfr1 }, |
0ff644a7 PM |
4571 | { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, |
4572 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, | |
4573 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4574 | .resetvalue = cpu->id_mmfr2 }, |
0ff644a7 PM |
4575 | { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, |
4576 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, | |
4577 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4578 | .resetvalue = cpu->id_mmfr3 }, |
0ff644a7 PM |
4579 | { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, |
4580 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
4581 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4582 | .resetvalue = cpu->id_isar0 }, |
0ff644a7 PM |
4583 | { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, |
4584 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, | |
4585 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4586 | .resetvalue = cpu->id_isar1 }, |
0ff644a7 PM |
4587 | { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, |
4588 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
4589 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4590 | .resetvalue = cpu->id_isar2 }, |
0ff644a7 PM |
4591 | { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, |
4592 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, | |
4593 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4594 | .resetvalue = cpu->id_isar3 }, |
0ff644a7 PM |
4595 | { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, |
4596 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, | |
4597 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4598 | .resetvalue = cpu->id_isar4 }, |
0ff644a7 PM |
4599 | { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, |
4600 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, | |
4601 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4602 | .resetvalue = cpu->id_isar5 }, |
e20d84c1 PM |
4603 | { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, |
4604 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, | |
4605 | .access = PL1_R, .type = ARM_CP_CONST, | |
4606 | .resetvalue = cpu->id_mmfr4 }, | |
4607 | /* 7 is as yet unallocated and must RAZ */ | |
4608 | { .name = "ID_ISAR7_RESERVED", .state = ARM_CP_STATE_BOTH, | |
4609 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, | |
4610 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 PM |
4611 | .resetvalue = 0 }, |
4612 | REGINFO_SENTINEL | |
4613 | }; | |
4614 | define_arm_cp_regs(cpu, v6_idregs); | |
7d57f408 PM |
4615 | define_arm_cp_regs(cpu, v6_cp_reginfo); |
4616 | } else { | |
4617 | define_arm_cp_regs(cpu, not_v6_cp_reginfo); | |
4618 | } | |
4d31c596 PM |
4619 | if (arm_feature(env, ARM_FEATURE_V6K)) { |
4620 | define_arm_cp_regs(cpu, v6k_cp_reginfo); | |
4621 | } | |
5e5cf9e3 | 4622 | if (arm_feature(env, ARM_FEATURE_V7MP) && |
452a0955 | 4623 | !arm_feature(env, ARM_FEATURE_PMSA)) { |
995939a6 PM |
4624 | define_arm_cp_regs(cpu, v7mp_cp_reginfo); |
4625 | } | |
e9aa6c21 | 4626 | if (arm_feature(env, ARM_FEATURE_V7)) { |
200ac0ef | 4627 | /* v7 performance monitor control register: same implementor |
7c2cb42b AF |
4628 | * field as main ID register, and we implement only the cycle |
4629 | * count register. | |
200ac0ef | 4630 | */ |
7c2cb42b | 4631 | #ifndef CONFIG_USER_ONLY |
200ac0ef PM |
4632 | ARMCPRegInfo pmcr = { |
4633 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | |
8521466b | 4634 | .access = PL0_RW, |
7a0e58fa | 4635 | .type = ARM_CP_IO | ARM_CP_ALIAS, |
8521466b | 4636 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), |
fcd25206 PM |
4637 | .accessfn = pmreg_access, .writefn = pmcr_write, |
4638 | .raw_writefn = raw_write, | |
200ac0ef | 4639 | }; |
8521466b AF |
4640 | ARMCPRegInfo pmcr64 = { |
4641 | .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, | |
4642 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, | |
4643 | .access = PL0_RW, .accessfn = pmreg_access, | |
4644 | .type = ARM_CP_IO, | |
4645 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), | |
4646 | .resetvalue = cpu->midr & 0xff000000, | |
4647 | .writefn = pmcr_write, .raw_writefn = raw_write, | |
4648 | }; | |
7c2cb42b | 4649 | define_one_arm_cp_reg(cpu, &pmcr); |
8521466b | 4650 | define_one_arm_cp_reg(cpu, &pmcr64); |
7c2cb42b | 4651 | #endif |
776d4e5c | 4652 | ARMCPRegInfo clidr = { |
7da845b0 PM |
4653 | .name = "CLIDR", .state = ARM_CP_STATE_BOTH, |
4654 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | |
776d4e5c PM |
4655 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr |
4656 | }; | |
776d4e5c | 4657 | define_one_arm_cp_reg(cpu, &clidr); |
e9aa6c21 | 4658 | define_arm_cp_regs(cpu, v7_cp_reginfo); |
50300698 | 4659 | define_debug_regs(cpu); |
7d57f408 PM |
4660 | } else { |
4661 | define_arm_cp_regs(cpu, not_v7_cp_reginfo); | |
e9aa6c21 | 4662 | } |
b0d2b7d0 | 4663 | if (arm_feature(env, ARM_FEATURE_V8)) { |
e20d84c1 PM |
4664 | /* AArch64 ID registers, which all have impdef reset values. |
4665 | * Note that within the ID register ranges the unused slots | |
4666 | * must all RAZ, not UNDEF; future architecture versions may | |
4667 | * define new registers here. | |
4668 | */ | |
e60cef86 PM |
4669 | ARMCPRegInfo v8_idregs[] = { |
4670 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, | |
4671 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | |
4672 | .access = PL1_R, .type = ARM_CP_CONST, | |
4673 | .resetvalue = cpu->id_aa64pfr0 }, | |
4674 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, | |
4675 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | |
4676 | .access = PL1_R, .type = ARM_CP_CONST, | |
4677 | .resetvalue = cpu->id_aa64pfr1}, | |
e20d84c1 PM |
4678 | { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
4679 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, | |
4680 | .access = PL1_R, .type = ARM_CP_CONST, | |
4681 | .resetvalue = 0 }, | |
4682 | { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4683 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, | |
4684 | .access = PL1_R, .type = ARM_CP_CONST, | |
4685 | .resetvalue = 0 }, | |
4686 | { .name = "ID_AA64PFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4687 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, | |
4688 | .access = PL1_R, .type = ARM_CP_CONST, | |
4689 | .resetvalue = 0 }, | |
4690 | { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4691 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, | |
4692 | .access = PL1_R, .type = ARM_CP_CONST, | |
4693 | .resetvalue = 0 }, | |
4694 | { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4695 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, | |
4696 | .access = PL1_R, .type = ARM_CP_CONST, | |
4697 | .resetvalue = 0 }, | |
4698 | { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4699 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, | |
4700 | .access = PL1_R, .type = ARM_CP_CONST, | |
4701 | .resetvalue = 0 }, | |
e60cef86 PM |
4702 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, |
4703 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | |
4704 | .access = PL1_R, .type = ARM_CP_CONST, | |
d6f02ce3 | 4705 | .resetvalue = cpu->id_aa64dfr0 }, |
e60cef86 PM |
4706 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, |
4707 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | |
4708 | .access = PL1_R, .type = ARM_CP_CONST, | |
4709 | .resetvalue = cpu->id_aa64dfr1 }, | |
e20d84c1 PM |
4710 | { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
4711 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, | |
4712 | .access = PL1_R, .type = ARM_CP_CONST, | |
4713 | .resetvalue = 0 }, | |
4714 | { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4715 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, | |
4716 | .access = PL1_R, .type = ARM_CP_CONST, | |
4717 | .resetvalue = 0 }, | |
e60cef86 PM |
4718 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, |
4719 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | |
4720 | .access = PL1_R, .type = ARM_CP_CONST, | |
4721 | .resetvalue = cpu->id_aa64afr0 }, | |
4722 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | |
4723 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | |
4724 | .access = PL1_R, .type = ARM_CP_CONST, | |
4725 | .resetvalue = cpu->id_aa64afr1 }, | |
e20d84c1 PM |
4726 | { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
4727 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, | |
4728 | .access = PL1_R, .type = ARM_CP_CONST, | |
4729 | .resetvalue = 0 }, | |
4730 | { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4731 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, | |
4732 | .access = PL1_R, .type = ARM_CP_CONST, | |
4733 | .resetvalue = 0 }, | |
e60cef86 PM |
4734 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, |
4735 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | |
4736 | .access = PL1_R, .type = ARM_CP_CONST, | |
4737 | .resetvalue = cpu->id_aa64isar0 }, | |
4738 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, | |
4739 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | |
4740 | .access = PL1_R, .type = ARM_CP_CONST, | |
4741 | .resetvalue = cpu->id_aa64isar1 }, | |
e20d84c1 PM |
4742 | { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
4743 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, | |
4744 | .access = PL1_R, .type = ARM_CP_CONST, | |
4745 | .resetvalue = 0 }, | |
4746 | { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4747 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, | |
4748 | .access = PL1_R, .type = ARM_CP_CONST, | |
4749 | .resetvalue = 0 }, | |
4750 | { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4751 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, | |
4752 | .access = PL1_R, .type = ARM_CP_CONST, | |
4753 | .resetvalue = 0 }, | |
4754 | { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4755 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, | |
4756 | .access = PL1_R, .type = ARM_CP_CONST, | |
4757 | .resetvalue = 0 }, | |
4758 | { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4759 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, | |
4760 | .access = PL1_R, .type = ARM_CP_CONST, | |
4761 | .resetvalue = 0 }, | |
4762 | { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4763 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, | |
4764 | .access = PL1_R, .type = ARM_CP_CONST, | |
4765 | .resetvalue = 0 }, | |
e60cef86 PM |
4766 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, |
4767 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
4768 | .access = PL1_R, .type = ARM_CP_CONST, | |
4769 | .resetvalue = cpu->id_aa64mmfr0 }, | |
4770 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, | |
4771 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | |
4772 | .access = PL1_R, .type = ARM_CP_CONST, | |
4773 | .resetvalue = cpu->id_aa64mmfr1 }, | |
e20d84c1 PM |
4774 | { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
4775 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, | |
4776 | .access = PL1_R, .type = ARM_CP_CONST, | |
4777 | .resetvalue = 0 }, | |
4778 | { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4779 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, | |
4780 | .access = PL1_R, .type = ARM_CP_CONST, | |
4781 | .resetvalue = 0 }, | |
4782 | { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4783 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, | |
4784 | .access = PL1_R, .type = ARM_CP_CONST, | |
4785 | .resetvalue = 0 }, | |
4786 | { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4787 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, | |
4788 | .access = PL1_R, .type = ARM_CP_CONST, | |
4789 | .resetvalue = 0 }, | |
4790 | { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4791 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, | |
4792 | .access = PL1_R, .type = ARM_CP_CONST, | |
4793 | .resetvalue = 0 }, | |
4794 | { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4795 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, | |
4796 | .access = PL1_R, .type = ARM_CP_CONST, | |
4797 | .resetvalue = 0 }, | |
a50c0f51 PM |
4798 | { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, |
4799 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
4800 | .access = PL1_R, .type = ARM_CP_CONST, | |
4801 | .resetvalue = cpu->mvfr0 }, | |
4802 | { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, | |
4803 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
4804 | .access = PL1_R, .type = ARM_CP_CONST, | |
4805 | .resetvalue = cpu->mvfr1 }, | |
4806 | { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, | |
4807 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
4808 | .access = PL1_R, .type = ARM_CP_CONST, | |
4809 | .resetvalue = cpu->mvfr2 }, | |
e20d84c1 PM |
4810 | { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
4811 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, | |
4812 | .access = PL1_R, .type = ARM_CP_CONST, | |
4813 | .resetvalue = 0 }, | |
4814 | { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4815 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, | |
4816 | .access = PL1_R, .type = ARM_CP_CONST, | |
4817 | .resetvalue = 0 }, | |
4818 | { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4819 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, | |
4820 | .access = PL1_R, .type = ARM_CP_CONST, | |
4821 | .resetvalue = 0 }, | |
4822 | { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4823 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, | |
4824 | .access = PL1_R, .type = ARM_CP_CONST, | |
4825 | .resetvalue = 0 }, | |
4826 | { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4827 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, | |
4828 | .access = PL1_R, .type = ARM_CP_CONST, | |
4829 | .resetvalue = 0 }, | |
4054bfa9 AF |
4830 | { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, |
4831 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, | |
4832 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
4833 | .resetvalue = cpu->pmceid0 }, | |
4834 | { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, | |
4835 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, | |
4836 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
4837 | .resetvalue = cpu->pmceid0 }, | |
4838 | { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, | |
4839 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, | |
4840 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
4841 | .resetvalue = cpu->pmceid1 }, | |
4842 | { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, | |
4843 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, | |
4844 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
4845 | .resetvalue = cpu->pmceid1 }, | |
e60cef86 PM |
4846 | REGINFO_SENTINEL |
4847 | }; | |
be8e8128 GB |
4848 | /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ |
4849 | if (!arm_feature(env, ARM_FEATURE_EL3) && | |
4850 | !arm_feature(env, ARM_FEATURE_EL2)) { | |
4851 | ARMCPRegInfo rvbar = { | |
4852 | .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, | |
4853 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, | |
4854 | .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar | |
4855 | }; | |
4856 | define_one_arm_cp_reg(cpu, &rvbar); | |
4857 | } | |
e60cef86 | 4858 | define_arm_cp_regs(cpu, v8_idregs); |
b0d2b7d0 PM |
4859 | define_arm_cp_regs(cpu, v8_cp_reginfo); |
4860 | } | |
3b685ba7 | 4861 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
f0d574d6 | 4862 | uint64_t vmpidr_def = mpidr_read_val(env); |
731de9e6 EI |
4863 | ARMCPRegInfo vpidr_regs[] = { |
4864 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | |
4865 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
4866 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
4867 | .resetvalue = cpu->midr, | |
4868 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
4869 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, | |
4870 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
4871 | .access = PL2_RW, .resetvalue = cpu->midr, | |
4872 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
f0d574d6 EI |
4873 | { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, |
4874 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
4875 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
4876 | .resetvalue = vmpidr_def, | |
4877 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | |
4878 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, | |
4879 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
4880 | .access = PL2_RW, | |
4881 | .resetvalue = vmpidr_def, | |
4882 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | |
731de9e6 EI |
4883 | REGINFO_SENTINEL |
4884 | }; | |
4885 | define_arm_cp_regs(cpu, vpidr_regs); | |
4771cd01 | 4886 | define_arm_cp_regs(cpu, el2_cp_reginfo); |
be8e8128 GB |
4887 | /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ |
4888 | if (!arm_feature(env, ARM_FEATURE_EL3)) { | |
4889 | ARMCPRegInfo rvbar = { | |
4890 | .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, | |
4891 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, | |
4892 | .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar | |
4893 | }; | |
4894 | define_one_arm_cp_reg(cpu, &rvbar); | |
4895 | } | |
d42e3c26 EI |
4896 | } else { |
4897 | /* If EL2 is missing but higher ELs are enabled, we need to | |
4898 | * register the no_el2 reginfos. | |
4899 | */ | |
4900 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
f0d574d6 EI |
4901 | /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value |
4902 | * of MIDR_EL1 and MPIDR_EL1. | |
731de9e6 EI |
4903 | */ |
4904 | ARMCPRegInfo vpidr_regs[] = { | |
4905 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH, | |
4906 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
4907 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
4908 | .type = ARM_CP_CONST, .resetvalue = cpu->midr, | |
4909 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
f0d574d6 EI |
4910 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
4911 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
4912 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
4913 | .type = ARM_CP_NO_RAW, | |
4914 | .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, | |
731de9e6 EI |
4915 | REGINFO_SENTINEL |
4916 | }; | |
4917 | define_arm_cp_regs(cpu, vpidr_regs); | |
4771cd01 | 4918 | define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); |
d42e3c26 | 4919 | } |
3b685ba7 | 4920 | } |
81547d66 | 4921 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0f1a3b24 | 4922 | define_arm_cp_regs(cpu, el3_cp_reginfo); |
e24fdd23 PM |
4923 | ARMCPRegInfo el3_regs[] = { |
4924 | { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, | |
4925 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, | |
4926 | .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, | |
4927 | { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, | |
4928 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, | |
4929 | .access = PL3_RW, | |
4930 | .raw_writefn = raw_write, .writefn = sctlr_write, | |
4931 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), | |
4932 | .resetvalue = cpu->reset_sctlr }, | |
4933 | REGINFO_SENTINEL | |
be8e8128 | 4934 | }; |
e24fdd23 PM |
4935 | |
4936 | define_arm_cp_regs(cpu, el3_regs); | |
81547d66 | 4937 | } |
2f027fc5 PM |
4938 | /* The behaviour of NSACR is sufficiently various that we don't |
4939 | * try to describe it in a single reginfo: | |
4940 | * if EL3 is 64 bit, then trap to EL3 from S EL1, | |
4941 | * reads as constant 0xc00 from NS EL1 and NS EL2 | |
4942 | * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 | |
4943 | * if v7 without EL3, register doesn't exist | |
4944 | * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 | |
4945 | */ | |
4946 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
4947 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
4948 | ARMCPRegInfo nsacr = { | |
4949 | .name = "NSACR", .type = ARM_CP_CONST, | |
4950 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
4951 | .access = PL1_RW, .accessfn = nsacr_access, | |
4952 | .resetvalue = 0xc00 | |
4953 | }; | |
4954 | define_one_arm_cp_reg(cpu, &nsacr); | |
4955 | } else { | |
4956 | ARMCPRegInfo nsacr = { | |
4957 | .name = "NSACR", | |
4958 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
4959 | .access = PL3_RW | PL1_R, | |
4960 | .resetvalue = 0, | |
4961 | .fieldoffset = offsetof(CPUARMState, cp15.nsacr) | |
4962 | }; | |
4963 | define_one_arm_cp_reg(cpu, &nsacr); | |
4964 | } | |
4965 | } else { | |
4966 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
4967 | ARMCPRegInfo nsacr = { | |
4968 | .name = "NSACR", .type = ARM_CP_CONST, | |
4969 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
4970 | .access = PL1_R, | |
4971 | .resetvalue = 0xc00 | |
4972 | }; | |
4973 | define_one_arm_cp_reg(cpu, &nsacr); | |
4974 | } | |
4975 | } | |
4976 | ||
452a0955 | 4977 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
6cb0b013 PC |
4978 | if (arm_feature(env, ARM_FEATURE_V6)) { |
4979 | /* PMSAv6 not implemented */ | |
4980 | assert(arm_feature(env, ARM_FEATURE_V7)); | |
4981 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); | |
4982 | define_arm_cp_regs(cpu, pmsav7_cp_reginfo); | |
4983 | } else { | |
4984 | define_arm_cp_regs(cpu, pmsav5_cp_reginfo); | |
4985 | } | |
18032bec | 4986 | } else { |
8e5d75c9 | 4987 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); |
18032bec PM |
4988 | define_arm_cp_regs(cpu, vmsa_cp_reginfo); |
4989 | } | |
c326b979 PM |
4990 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
4991 | define_arm_cp_regs(cpu, t2ee_cp_reginfo); | |
4992 | } | |
6cc7a3ae PM |
4993 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
4994 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); | |
4995 | } | |
4a501606 PM |
4996 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
4997 | define_arm_cp_regs(cpu, vapa_cp_reginfo); | |
4998 | } | |
c4804214 PM |
4999 | if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { |
5000 | define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); | |
5001 | } | |
5002 | if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { | |
5003 | define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); | |
5004 | } | |
5005 | if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { | |
5006 | define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); | |
5007 | } | |
18032bec PM |
5008 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
5009 | define_arm_cp_regs(cpu, omap_cp_reginfo); | |
5010 | } | |
34f90529 PM |
5011 | if (arm_feature(env, ARM_FEATURE_STRONGARM)) { |
5012 | define_arm_cp_regs(cpu, strongarm_cp_reginfo); | |
5013 | } | |
1047b9d7 PM |
5014 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
5015 | define_arm_cp_regs(cpu, xscale_cp_reginfo); | |
5016 | } | |
5017 | if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { | |
5018 | define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); | |
5019 | } | |
7ac681cf PM |
5020 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
5021 | define_arm_cp_regs(cpu, lpae_cp_reginfo); | |
5022 | } | |
7884849c PM |
5023 | /* Slightly awkwardly, the OMAP and StrongARM cores need all of |
5024 | * cp15 crn=0 to be writes-ignored, whereas for other cores they should | |
5025 | * be read-only (ie write causes UNDEF exception). | |
5026 | */ | |
5027 | { | |
00a29f3d PM |
5028 | ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { |
5029 | /* Pre-v8 MIDR space. | |
5030 | * Note that the MIDR isn't a simple constant register because | |
7884849c PM |
5031 | * of the TI925 behaviour where writes to another register can |
5032 | * cause the MIDR value to change. | |
97ce8d61 PC |
5033 | * |
5034 | * Unimplemented registers in the c15 0 0 0 space default to | |
5035 | * MIDR. Define MIDR first as this entire space, then CTR, TCMTR | |
5036 | * and friends override accordingly. | |
7884849c PM |
5037 | */ |
5038 | { .name = "MIDR", | |
97ce8d61 | 5039 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, |
7884849c | 5040 | .access = PL1_R, .resetvalue = cpu->midr, |
d4e6df63 | 5041 | .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, |
731de9e6 | 5042 | .readfn = midr_read, |
97ce8d61 PC |
5043 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
5044 | .type = ARM_CP_OVERRIDE }, | |
7884849c PM |
5045 | /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ |
5046 | { .name = "DUMMY", | |
5047 | .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, | |
5048 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5049 | { .name = "DUMMY", | |
5050 | .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, | |
5051 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5052 | { .name = "DUMMY", | |
5053 | .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, | |
5054 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5055 | { .name = "DUMMY", | |
5056 | .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, | |
5057 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5058 | { .name = "DUMMY", | |
5059 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | |
5060 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5061 | REGINFO_SENTINEL | |
5062 | }; | |
00a29f3d | 5063 | ARMCPRegInfo id_v8_midr_cp_reginfo[] = { |
00a29f3d PM |
5064 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, |
5065 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, | |
731de9e6 EI |
5066 | .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, |
5067 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), | |
5068 | .readfn = midr_read }, | |
ac00c79f SF |
5069 | /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ |
5070 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
5071 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
5072 | .access = PL1_R, .resetvalue = cpu->midr }, | |
5073 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
5074 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, | |
5075 | .access = PL1_R, .resetvalue = cpu->midr }, | |
00a29f3d PM |
5076 | { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, |
5077 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, | |
13b72b2b | 5078 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, |
00a29f3d PM |
5079 | REGINFO_SENTINEL |
5080 | }; | |
5081 | ARMCPRegInfo id_cp_reginfo[] = { | |
5082 | /* These are common to v8 and pre-v8 */ | |
5083 | { .name = "CTR", | |
5084 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, | |
5085 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
5086 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, | |
5087 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, | |
5088 | .access = PL0_R, .accessfn = ctr_el0_access, | |
5089 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
5090 | /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ | |
5091 | { .name = "TCMTR", | |
5092 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, | |
5093 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
00a29f3d PM |
5094 | REGINFO_SENTINEL |
5095 | }; | |
8085ce63 PC |
5096 | /* TLBTR is specific to VMSA */ |
5097 | ARMCPRegInfo id_tlbtr_reginfo = { | |
5098 | .name = "TLBTR", | |
5099 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, | |
5100 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0, | |
5101 | }; | |
3281af81 PC |
5102 | /* MPUIR is specific to PMSA V6+ */ |
5103 | ARMCPRegInfo id_mpuir_reginfo = { | |
5104 | .name = "MPUIR", | |
5105 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
5106 | .access = PL1_R, .type = ARM_CP_CONST, | |
5107 | .resetvalue = cpu->pmsav7_dregion << 8 | |
5108 | }; | |
7884849c PM |
5109 | ARMCPRegInfo crn0_wi_reginfo = { |
5110 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, | |
5111 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | |
5112 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | |
5113 | }; | |
5114 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || | |
5115 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | |
5116 | ARMCPRegInfo *r; | |
5117 | /* Register the blanket "writes ignored" value first to cover the | |
a703eda1 PC |
5118 | * whole space. Then update the specific ID registers to allow write |
5119 | * access, so that they ignore writes rather than causing them to | |
5120 | * UNDEF. | |
7884849c PM |
5121 | */ |
5122 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | |
00a29f3d PM |
5123 | for (r = id_pre_v8_midr_cp_reginfo; |
5124 | r->type != ARM_CP_SENTINEL; r++) { | |
5125 | r->access = PL1_RW; | |
5126 | } | |
7884849c PM |
5127 | for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { |
5128 | r->access = PL1_RW; | |
7884849c | 5129 | } |
8085ce63 | 5130 | id_tlbtr_reginfo.access = PL1_RW; |
3281af81 | 5131 | id_tlbtr_reginfo.access = PL1_RW; |
7884849c | 5132 | } |
00a29f3d PM |
5133 | if (arm_feature(env, ARM_FEATURE_V8)) { |
5134 | define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); | |
5135 | } else { | |
5136 | define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); | |
5137 | } | |
a703eda1 | 5138 | define_arm_cp_regs(cpu, id_cp_reginfo); |
452a0955 | 5139 | if (!arm_feature(env, ARM_FEATURE_PMSA)) { |
8085ce63 | 5140 | define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); |
3281af81 PC |
5141 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
5142 | define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); | |
8085ce63 | 5143 | } |
7884849c PM |
5144 | } |
5145 | ||
97ce8d61 PC |
5146 | if (arm_feature(env, ARM_FEATURE_MPIDR)) { |
5147 | define_arm_cp_regs(cpu, mpidr_cp_reginfo); | |
5148 | } | |
5149 | ||
2771db27 | 5150 | if (arm_feature(env, ARM_FEATURE_AUXCR)) { |
834a6c69 PM |
5151 | ARMCPRegInfo auxcr_reginfo[] = { |
5152 | { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, | |
5153 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, | |
5154 | .access = PL1_RW, .type = ARM_CP_CONST, | |
5155 | .resetvalue = cpu->reset_auxcr }, | |
5156 | { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, | |
5157 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, | |
5158 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5159 | .resetvalue = 0 }, | |
5160 | { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, | |
5161 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, | |
5162 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5163 | .resetvalue = 0 }, | |
5164 | REGINFO_SENTINEL | |
2771db27 | 5165 | }; |
834a6c69 | 5166 | define_arm_cp_regs(cpu, auxcr_reginfo); |
2771db27 PM |
5167 | } |
5168 | ||
d8ba780b | 5169 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
f318cec6 PM |
5170 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
5171 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | |
5172 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | |
5173 | | extract64(cpu->reset_cbar, 32, 12); | |
5174 | ARMCPRegInfo cbar_reginfo[] = { | |
5175 | { .name = "CBAR", | |
5176 | .type = ARM_CP_CONST, | |
5177 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
5178 | .access = PL1_R, .resetvalue = cpu->reset_cbar }, | |
5179 | { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, | |
5180 | .type = ARM_CP_CONST, | |
5181 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | |
5182 | .access = PL1_R, .resetvalue = cbar32 }, | |
5183 | REGINFO_SENTINEL | |
5184 | }; | |
5185 | /* We don't implement a r/w 64 bit CBAR currently */ | |
5186 | assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); | |
5187 | define_arm_cp_regs(cpu, cbar_reginfo); | |
5188 | } else { | |
5189 | ARMCPRegInfo cbar = { | |
5190 | .name = "CBAR", | |
5191 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
5192 | .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, | |
5193 | .fieldoffset = offsetof(CPUARMState, | |
5194 | cp15.c15_config_base_address) | |
5195 | }; | |
5196 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | |
5197 | cbar.access = PL1_R; | |
5198 | cbar.fieldoffset = 0; | |
5199 | cbar.type = ARM_CP_CONST; | |
5200 | } | |
5201 | define_one_arm_cp_reg(cpu, &cbar); | |
5202 | } | |
d8ba780b PC |
5203 | } |
5204 | ||
91db4642 CLG |
5205 | if (arm_feature(env, ARM_FEATURE_VBAR)) { |
5206 | ARMCPRegInfo vbar_cp_reginfo[] = { | |
5207 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, | |
5208 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | |
5209 | .access = PL1_RW, .writefn = vbar_write, | |
5210 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), | |
5211 | offsetof(CPUARMState, cp15.vbar_ns) }, | |
5212 | .resetvalue = 0 }, | |
5213 | REGINFO_SENTINEL | |
5214 | }; | |
5215 | define_arm_cp_regs(cpu, vbar_cp_reginfo); | |
5216 | } | |
5217 | ||
2771db27 PM |
5218 | /* Generic registers whose values depend on the implementation */ |
5219 | { | |
5220 | ARMCPRegInfo sctlr = { | |
5ebafdf3 | 5221 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, |
137feaa9 FA |
5222 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, |
5223 | .access = PL1_RW, | |
5224 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), | |
5225 | offsetof(CPUARMState, cp15.sctlr_ns) }, | |
d4e6df63 PM |
5226 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, |
5227 | .raw_writefn = raw_write, | |
2771db27 PM |
5228 | }; |
5229 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
5230 | /* Normally we would always end the TB on an SCTLR write, but Linux | |
5231 | * arch/arm/mach-pxa/sleep.S expects two instructions following | |
5232 | * an MMU enable to execute from cache. Imitate this behaviour. | |
5233 | */ | |
5234 | sctlr.type |= ARM_CP_SUPPRESS_TB_END; | |
5235 | } | |
5236 | define_one_arm_cp_reg(cpu, &sctlr); | |
5237 | } | |
2ceb98c0 PM |
5238 | } |
5239 | ||
778c3a06 | 5240 | ARMCPU *cpu_arm_init(const char *cpu_model) |
40f137e1 | 5241 | { |
9262685b | 5242 | return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); |
14969266 AF |
5243 | } |
5244 | ||
5245 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | |
5246 | { | |
22169d41 | 5247 | CPUState *cs = CPU(cpu); |
14969266 AF |
5248 | CPUARMState *env = &cpu->env; |
5249 | ||
6a669427 PM |
5250 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
5251 | gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, | |
5252 | aarch64_fpu_gdb_set_reg, | |
5253 | 34, "aarch64-fpu.xml", 0); | |
5254 | } else if (arm_feature(env, ARM_FEATURE_NEON)) { | |
22169d41 | 5255 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
5256 | 51, "arm-neon.xml", 0); |
5257 | } else if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
22169d41 | 5258 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
5259 | 35, "arm-vfp3.xml", 0); |
5260 | } else if (arm_feature(env, ARM_FEATURE_VFP)) { | |
22169d41 | 5261 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
5262 | 19, "arm-vfp.xml", 0); |
5263 | } | |
40f137e1 PB |
5264 | } |
5265 | ||
777dc784 PM |
5266 | /* Sort alphabetically by type name, except for "any". */ |
5267 | static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) | |
5adb4839 | 5268 | { |
777dc784 PM |
5269 | ObjectClass *class_a = (ObjectClass *)a; |
5270 | ObjectClass *class_b = (ObjectClass *)b; | |
5271 | const char *name_a, *name_b; | |
5adb4839 | 5272 | |
777dc784 PM |
5273 | name_a = object_class_get_name(class_a); |
5274 | name_b = object_class_get_name(class_b); | |
51492fd1 | 5275 | if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 | 5276 | return 1; |
51492fd1 | 5277 | } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 PM |
5278 | return -1; |
5279 | } else { | |
5280 | return strcmp(name_a, name_b); | |
5adb4839 PB |
5281 | } |
5282 | } | |
5283 | ||
777dc784 | 5284 | static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
40f137e1 | 5285 | { |
777dc784 | 5286 | ObjectClass *oc = data; |
92a31361 | 5287 | CPUListState *s = user_data; |
51492fd1 AF |
5288 | const char *typename; |
5289 | char *name; | |
3371d272 | 5290 | |
51492fd1 AF |
5291 | typename = object_class_get_name(oc); |
5292 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
777dc784 | 5293 | (*s->cpu_fprintf)(s->file, " %s\n", |
51492fd1 AF |
5294 | name); |
5295 | g_free(name); | |
777dc784 PM |
5296 | } |
5297 | ||
5298 | void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
5299 | { | |
92a31361 | 5300 | CPUListState s = { |
777dc784 PM |
5301 | .file = f, |
5302 | .cpu_fprintf = cpu_fprintf, | |
5303 | }; | |
5304 | GSList *list; | |
5305 | ||
5306 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
5307 | list = g_slist_sort(list, arm_cpu_list_compare); | |
5308 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
5309 | g_slist_foreach(list, arm_cpu_list_entry, &s); | |
5310 | g_slist_free(list); | |
a96c0514 PM |
5311 | #ifdef CONFIG_KVM |
5312 | /* The 'host' CPU type is dynamically registered only if KVM is | |
5313 | * enabled, so we have to special-case it here: | |
5314 | */ | |
5315 | (*cpu_fprintf)(f, " host (only available in KVM mode)\n"); | |
5316 | #endif | |
40f137e1 PB |
5317 | } |
5318 | ||
78027bb6 CR |
5319 | static void arm_cpu_add_definition(gpointer data, gpointer user_data) |
5320 | { | |
5321 | ObjectClass *oc = data; | |
5322 | CpuDefinitionInfoList **cpu_list = user_data; | |
5323 | CpuDefinitionInfoList *entry; | |
5324 | CpuDefinitionInfo *info; | |
5325 | const char *typename; | |
5326 | ||
5327 | typename = object_class_get_name(oc); | |
5328 | info = g_malloc0(sizeof(*info)); | |
5329 | info->name = g_strndup(typename, | |
5330 | strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
8ed877b7 | 5331 | info->q_typename = g_strdup(typename); |
78027bb6 CR |
5332 | |
5333 | entry = g_malloc0(sizeof(*entry)); | |
5334 | entry->value = info; | |
5335 | entry->next = *cpu_list; | |
5336 | *cpu_list = entry; | |
5337 | } | |
5338 | ||
5339 | CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) | |
5340 | { | |
5341 | CpuDefinitionInfoList *cpu_list = NULL; | |
5342 | GSList *list; | |
5343 | ||
5344 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
5345 | g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); | |
5346 | g_slist_free(list); | |
5347 | ||
5348 | return cpu_list; | |
5349 | } | |
5350 | ||
6e6efd61 | 5351 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
51a79b03 | 5352 | void *opaque, int state, int secstate, |
f5a0a5a5 | 5353 | int crm, int opc1, int opc2) |
6e6efd61 PM |
5354 | { |
5355 | /* Private utility function for define_one_arm_cp_reg_with_opaque(): | |
5356 | * add a single reginfo struct to the hash table. | |
5357 | */ | |
5358 | uint32_t *key = g_new(uint32_t, 1); | |
5359 | ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); | |
5360 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | |
3f3c82a5 FA |
5361 | int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; |
5362 | ||
5363 | /* Reset the secure state to the specific incoming state. This is | |
5364 | * necessary as the register may have been defined with both states. | |
5365 | */ | |
5366 | r2->secure = secstate; | |
5367 | ||
5368 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
5369 | /* Register is banked (using both entries in array). | |
5370 | * Overwriting fieldoffset as the array is only used to define | |
5371 | * banked registers but later only fieldoffset is used. | |
f5a0a5a5 | 5372 | */ |
3f3c82a5 FA |
5373 | r2->fieldoffset = r->bank_fieldoffsets[ns]; |
5374 | } | |
5375 | ||
5376 | if (state == ARM_CP_STATE_AA32) { | |
5377 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
5378 | /* If the register is banked then we don't need to migrate or | |
5379 | * reset the 32-bit instance in certain cases: | |
5380 | * | |
5381 | * 1) If the register has both 32-bit and 64-bit instances then we | |
5382 | * can count on the 64-bit instance taking care of the | |
5383 | * non-secure bank. | |
5384 | * 2) If ARMv8 is enabled then we can count on a 64-bit version | |
5385 | * taking care of the secure bank. This requires that separate | |
5386 | * 32 and 64-bit definitions are provided. | |
5387 | */ | |
5388 | if ((r->state == ARM_CP_STATE_BOTH && ns) || | |
5389 | (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { | |
7a0e58fa | 5390 | r2->type |= ARM_CP_ALIAS; |
3f3c82a5 FA |
5391 | } |
5392 | } else if ((secstate != r->secure) && !ns) { | |
5393 | /* The register is not banked so we only want to allow migration of | |
5394 | * the non-secure instance. | |
5395 | */ | |
7a0e58fa | 5396 | r2->type |= ARM_CP_ALIAS; |
58a1d8ce | 5397 | } |
3f3c82a5 FA |
5398 | |
5399 | if (r->state == ARM_CP_STATE_BOTH) { | |
5400 | /* We assume it is a cp15 register if the .cp field is left unset. | |
5401 | */ | |
5402 | if (r2->cp == 0) { | |
5403 | r2->cp = 15; | |
5404 | } | |
5405 | ||
f5a0a5a5 | 5406 | #ifdef HOST_WORDS_BIGENDIAN |
3f3c82a5 FA |
5407 | if (r2->fieldoffset) { |
5408 | r2->fieldoffset += sizeof(uint32_t); | |
5409 | } | |
f5a0a5a5 | 5410 | #endif |
3f3c82a5 | 5411 | } |
f5a0a5a5 PM |
5412 | } |
5413 | if (state == ARM_CP_STATE_AA64) { | |
5414 | /* To allow abbreviation of ARMCPRegInfo | |
5415 | * definitions, we treat cp == 0 as equivalent to | |
5416 | * the value for "standard guest-visible sysreg". | |
58a1d8ce PM |
5417 | * STATE_BOTH definitions are also always "standard |
5418 | * sysreg" in their AArch64 view (the .cp value may | |
5419 | * be non-zero for the benefit of the AArch32 view). | |
f5a0a5a5 | 5420 | */ |
58a1d8ce | 5421 | if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { |
f5a0a5a5 PM |
5422 | r2->cp = CP_REG_ARM64_SYSREG_CP; |
5423 | } | |
5424 | *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | |
5425 | r2->opc0, opc1, opc2); | |
5426 | } else { | |
51a79b03 | 5427 | *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); |
f5a0a5a5 | 5428 | } |
6e6efd61 PM |
5429 | if (opaque) { |
5430 | r2->opaque = opaque; | |
5431 | } | |
67ed771d PM |
5432 | /* reginfo passed to helpers is correct for the actual access, |
5433 | * and is never ARM_CP_STATE_BOTH: | |
5434 | */ | |
5435 | r2->state = state; | |
6e6efd61 PM |
5436 | /* Make sure reginfo passed to helpers for wildcarded regs |
5437 | * has the correct crm/opc1/opc2 for this reg, not CP_ANY: | |
5438 | */ | |
5439 | r2->crm = crm; | |
5440 | r2->opc1 = opc1; | |
5441 | r2->opc2 = opc2; | |
5442 | /* By convention, for wildcarded registers only the first | |
5443 | * entry is used for migration; the others are marked as | |
7a0e58fa | 5444 | * ALIAS so we don't try to transfer the register |
6e6efd61 | 5445 | * multiple times. Special registers (ie NOP/WFI) are |
7a0e58fa | 5446 | * never migratable and not even raw-accessible. |
6e6efd61 | 5447 | */ |
7a0e58fa PM |
5448 | if ((r->type & ARM_CP_SPECIAL)) { |
5449 | r2->type |= ARM_CP_NO_RAW; | |
5450 | } | |
5451 | if (((r->crm == CP_ANY) && crm != 0) || | |
6e6efd61 PM |
5452 | ((r->opc1 == CP_ANY) && opc1 != 0) || |
5453 | ((r->opc2 == CP_ANY) && opc2 != 0)) { | |
7a0e58fa | 5454 | r2->type |= ARM_CP_ALIAS; |
6e6efd61 PM |
5455 | } |
5456 | ||
375421cc PM |
5457 | /* Check that raw accesses are either forbidden or handled. Note that |
5458 | * we can't assert this earlier because the setup of fieldoffset for | |
5459 | * banked registers has to be done first. | |
5460 | */ | |
5461 | if (!(r2->type & ARM_CP_NO_RAW)) { | |
5462 | assert(!raw_accessors_invalid(r2)); | |
5463 | } | |
5464 | ||
6e6efd61 PM |
5465 | /* Overriding of an existing definition must be explicitly |
5466 | * requested. | |
5467 | */ | |
5468 | if (!(r->type & ARM_CP_OVERRIDE)) { | |
5469 | ARMCPRegInfo *oldreg; | |
5470 | oldreg = g_hash_table_lookup(cpu->cp_regs, key); | |
5471 | if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { | |
5472 | fprintf(stderr, "Register redefined: cp=%d %d bit " | |
5473 | "crn=%d crm=%d opc1=%d opc2=%d, " | |
5474 | "was %s, now %s\n", r2->cp, 32 + 32 * is64, | |
5475 | r2->crn, r2->crm, r2->opc1, r2->opc2, | |
5476 | oldreg->name, r2->name); | |
5477 | g_assert_not_reached(); | |
5478 | } | |
5479 | } | |
5480 | g_hash_table_insert(cpu->cp_regs, key, r2); | |
5481 | } | |
5482 | ||
5483 | ||
4b6a83fb PM |
5484 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
5485 | const ARMCPRegInfo *r, void *opaque) | |
5486 | { | |
5487 | /* Define implementations of coprocessor registers. | |
5488 | * We store these in a hashtable because typically | |
5489 | * there are less than 150 registers in a space which | |
5490 | * is 16*16*16*8*8 = 262144 in size. | |
5491 | * Wildcarding is supported for the crm, opc1 and opc2 fields. | |
5492 | * If a register is defined twice then the second definition is | |
5493 | * used, so this can be used to define some generic registers and | |
5494 | * then override them with implementation specific variations. | |
5495 | * At least one of the original and the second definition should | |
5496 | * include ARM_CP_OVERRIDE in its type bits -- this is just a guard | |
5497 | * against accidental use. | |
f5a0a5a5 PM |
5498 | * |
5499 | * The state field defines whether the register is to be | |
5500 | * visible in the AArch32 or AArch64 execution state. If the | |
5501 | * state is set to ARM_CP_STATE_BOTH then we synthesise a | |
5502 | * reginfo structure for the AArch32 view, which sees the lower | |
5503 | * 32 bits of the 64 bit register. | |
5504 | * | |
5505 | * Only registers visible in AArch64 may set r->opc0; opc0 cannot | |
5506 | * be wildcarded. AArch64 registers are always considered to be 64 | |
5507 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | |
5508 | * the register, if any. | |
4b6a83fb | 5509 | */ |
f5a0a5a5 | 5510 | int crm, opc1, opc2, state; |
4b6a83fb PM |
5511 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
5512 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | |
5513 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | |
5514 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | |
5515 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | |
5516 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | |
5517 | /* 64 bit registers have only CRm and Opc1 fields */ | |
5518 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | |
f5a0a5a5 PM |
5519 | /* op0 only exists in the AArch64 encodings */ |
5520 | assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); | |
5521 | /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ | |
5522 | assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); | |
5523 | /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 | |
5524 | * encodes a minimum access level for the register. We roll this | |
5525 | * runtime check into our general permission check code, so check | |
5526 | * here that the reginfo's specified permissions are strict enough | |
5527 | * to encompass the generic architectural permission check. | |
5528 | */ | |
5529 | if (r->state != ARM_CP_STATE_AA32) { | |
5530 | int mask = 0; | |
5531 | switch (r->opc1) { | |
5532 | case 0: case 1: case 2: | |
5533 | /* min_EL EL1 */ | |
5534 | mask = PL1_RW; | |
5535 | break; | |
5536 | case 3: | |
5537 | /* min_EL EL0 */ | |
5538 | mask = PL0_RW; | |
5539 | break; | |
5540 | case 4: | |
5541 | /* min_EL EL2 */ | |
5542 | mask = PL2_RW; | |
5543 | break; | |
5544 | case 5: | |
5545 | /* unallocated encoding, so not possible */ | |
5546 | assert(false); | |
5547 | break; | |
5548 | case 6: | |
5549 | /* min_EL EL3 */ | |
5550 | mask = PL3_RW; | |
5551 | break; | |
5552 | case 7: | |
5553 | /* min_EL EL1, secure mode only (we don't check the latter) */ | |
5554 | mask = PL1_RW; | |
5555 | break; | |
5556 | default: | |
5557 | /* broken reginfo with out-of-range opc1 */ | |
5558 | assert(false); | |
5559 | break; | |
5560 | } | |
5561 | /* assert our permissions are not too lax (stricter is fine) */ | |
5562 | assert((r->access & ~mask) == 0); | |
5563 | } | |
5564 | ||
4b6a83fb PM |
5565 | /* Check that the register definition has enough info to handle |
5566 | * reads and writes if they are permitted. | |
5567 | */ | |
5568 | if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { | |
5569 | if (r->access & PL3_R) { | |
3f3c82a5 FA |
5570 | assert((r->fieldoffset || |
5571 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
5572 | r->readfn); | |
4b6a83fb PM |
5573 | } |
5574 | if (r->access & PL3_W) { | |
3f3c82a5 FA |
5575 | assert((r->fieldoffset || |
5576 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
5577 | r->writefn); | |
4b6a83fb PM |
5578 | } |
5579 | } | |
5580 | /* Bad type field probably means missing sentinel at end of reg list */ | |
5581 | assert(cptype_valid(r->type)); | |
5582 | for (crm = crmmin; crm <= crmmax; crm++) { | |
5583 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | |
5584 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | |
f5a0a5a5 PM |
5585 | for (state = ARM_CP_STATE_AA32; |
5586 | state <= ARM_CP_STATE_AA64; state++) { | |
5587 | if (r->state != state && r->state != ARM_CP_STATE_BOTH) { | |
5588 | continue; | |
5589 | } | |
3f3c82a5 FA |
5590 | if (state == ARM_CP_STATE_AA32) { |
5591 | /* Under AArch32 CP registers can be common | |
5592 | * (same for secure and non-secure world) or banked. | |
5593 | */ | |
5594 | switch (r->secure) { | |
5595 | case ARM_CP_SECSTATE_S: | |
5596 | case ARM_CP_SECSTATE_NS: | |
5597 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
5598 | r->secure, crm, opc1, opc2); | |
5599 | break; | |
5600 | default: | |
5601 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
5602 | ARM_CP_SECSTATE_S, | |
5603 | crm, opc1, opc2); | |
5604 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
5605 | ARM_CP_SECSTATE_NS, | |
5606 | crm, opc1, opc2); | |
5607 | break; | |
5608 | } | |
5609 | } else { | |
5610 | /* AArch64 registers get mapped to non-secure instance | |
5611 | * of AArch32 */ | |
5612 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
5613 | ARM_CP_SECSTATE_NS, | |
5614 | crm, opc1, opc2); | |
5615 | } | |
f5a0a5a5 | 5616 | } |
4b6a83fb PM |
5617 | } |
5618 | } | |
5619 | } | |
5620 | } | |
5621 | ||
5622 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
5623 | const ARMCPRegInfo *regs, void *opaque) | |
5624 | { | |
5625 | /* Define a whole list of registers */ | |
5626 | const ARMCPRegInfo *r; | |
5627 | for (r = regs; r->type != ARM_CP_SENTINEL; r++) { | |
5628 | define_one_arm_cp_reg_with_opaque(cpu, r, opaque); | |
5629 | } | |
5630 | } | |
5631 | ||
60322b39 | 5632 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) |
4b6a83fb | 5633 | { |
60322b39 | 5634 | return g_hash_table_lookup(cpregs, &encoded_cp); |
4b6a83fb PM |
5635 | } |
5636 | ||
c4241c7d PM |
5637 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
5638 | uint64_t value) | |
4b6a83fb PM |
5639 | { |
5640 | /* Helper coprocessor write function for write-ignore registers */ | |
4b6a83fb PM |
5641 | } |
5642 | ||
c4241c7d | 5643 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) |
4b6a83fb PM |
5644 | { |
5645 | /* Helper coprocessor write function for read-as-zero registers */ | |
4b6a83fb PM |
5646 | return 0; |
5647 | } | |
5648 | ||
f5a0a5a5 PM |
5649 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) |
5650 | { | |
5651 | /* Helper coprocessor reset function for do-nothing-on-reset registers */ | |
5652 | } | |
5653 | ||
af393ffc | 5654 | static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) |
37064a8b PM |
5655 | { |
5656 | /* Return true if it is not valid for us to switch to | |
5657 | * this CPU mode (ie all the UNPREDICTABLE cases in | |
5658 | * the ARM ARM CPSRWriteByInstr pseudocode). | |
5659 | */ | |
af393ffc PM |
5660 | |
5661 | /* Changes to or from Hyp via MSR and CPS are illegal. */ | |
5662 | if (write_type == CPSRWriteByInstr && | |
5663 | ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || | |
5664 | mode == ARM_CPU_MODE_HYP)) { | |
5665 | return 1; | |
5666 | } | |
5667 | ||
37064a8b PM |
5668 | switch (mode) { |
5669 | case ARM_CPU_MODE_USR: | |
10eacda7 | 5670 | return 0; |
37064a8b PM |
5671 | case ARM_CPU_MODE_SYS: |
5672 | case ARM_CPU_MODE_SVC: | |
5673 | case ARM_CPU_MODE_ABT: | |
5674 | case ARM_CPU_MODE_UND: | |
5675 | case ARM_CPU_MODE_IRQ: | |
5676 | case ARM_CPU_MODE_FIQ: | |
52ff951b PM |
5677 | /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 |
5678 | * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) | |
5679 | */ | |
10eacda7 PM |
5680 | /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR |
5681 | * and CPS are treated as illegal mode changes. | |
5682 | */ | |
5683 | if (write_type == CPSRWriteByInstr && | |
5684 | (env->cp15.hcr_el2 & HCR_TGE) && | |
5685 | (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && | |
5686 | !arm_is_secure_below_el3(env)) { | |
5687 | return 1; | |
5688 | } | |
37064a8b | 5689 | return 0; |
e6c8fc07 PM |
5690 | case ARM_CPU_MODE_HYP: |
5691 | return !arm_feature(env, ARM_FEATURE_EL2) | |
5692 | || arm_current_el(env) < 2 || arm_is_secure(env); | |
027fc527 | 5693 | case ARM_CPU_MODE_MON: |
58ae2d1f | 5694 | return arm_current_el(env) < 3; |
37064a8b PM |
5695 | default: |
5696 | return 1; | |
5697 | } | |
5698 | } | |
5699 | ||
2f4a40e5 AZ |
5700 | uint32_t cpsr_read(CPUARMState *env) |
5701 | { | |
5702 | int ZF; | |
6fbe23d5 PB |
5703 | ZF = (env->ZF == 0); |
5704 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
5705 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
5706 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
5707 | | ((env->condexec_bits & 0xfc) << 8) | |
af519934 | 5708 | | (env->GE << 16) | (env->daif & CPSR_AIF); |
2f4a40e5 AZ |
5709 | } |
5710 | ||
50866ba5 PM |
5711 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, |
5712 | CPSRWriteType write_type) | |
2f4a40e5 | 5713 | { |
6e8801f9 FA |
5714 | uint32_t changed_daif; |
5715 | ||
2f4a40e5 | 5716 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
5717 | env->ZF = (~val) & CPSR_Z; |
5718 | env->NF = val; | |
2f4a40e5 AZ |
5719 | env->CF = (val >> 29) & 1; |
5720 | env->VF = (val << 3) & 0x80000000; | |
5721 | } | |
5722 | if (mask & CPSR_Q) | |
5723 | env->QF = ((val & CPSR_Q) != 0); | |
5724 | if (mask & CPSR_T) | |
5725 | env->thumb = ((val & CPSR_T) != 0); | |
5726 | if (mask & CPSR_IT_0_1) { | |
5727 | env->condexec_bits &= ~3; | |
5728 | env->condexec_bits |= (val >> 25) & 3; | |
5729 | } | |
5730 | if (mask & CPSR_IT_2_7) { | |
5731 | env->condexec_bits &= 3; | |
5732 | env->condexec_bits |= (val >> 8) & 0xfc; | |
5733 | } | |
5734 | if (mask & CPSR_GE) { | |
5735 | env->GE = (val >> 16) & 0xf; | |
5736 | } | |
5737 | ||
6e8801f9 FA |
5738 | /* In a V7 implementation that includes the security extensions but does |
5739 | * not include Virtualization Extensions the SCR.FW and SCR.AW bits control | |
5740 | * whether non-secure software is allowed to change the CPSR_F and CPSR_A | |
5741 | * bits respectively. | |
5742 | * | |
5743 | * In a V8 implementation, it is permitted for privileged software to | |
5744 | * change the CPSR A/F bits regardless of the SCR.AW/FW bits. | |
5745 | */ | |
f8c88bbc | 5746 | if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && |
6e8801f9 FA |
5747 | arm_feature(env, ARM_FEATURE_EL3) && |
5748 | !arm_feature(env, ARM_FEATURE_EL2) && | |
5749 | !arm_is_secure(env)) { | |
5750 | ||
5751 | changed_daif = (env->daif ^ val) & mask; | |
5752 | ||
5753 | if (changed_daif & CPSR_A) { | |
5754 | /* Check to see if we are allowed to change the masking of async | |
5755 | * abort exceptions from a non-secure state. | |
5756 | */ | |
5757 | if (!(env->cp15.scr_el3 & SCR_AW)) { | |
5758 | qemu_log_mask(LOG_GUEST_ERROR, | |
5759 | "Ignoring attempt to switch CPSR_A flag from " | |
5760 | "non-secure world with SCR.AW bit clear\n"); | |
5761 | mask &= ~CPSR_A; | |
5762 | } | |
5763 | } | |
5764 | ||
5765 | if (changed_daif & CPSR_F) { | |
5766 | /* Check to see if we are allowed to change the masking of FIQ | |
5767 | * exceptions from a non-secure state. | |
5768 | */ | |
5769 | if (!(env->cp15.scr_el3 & SCR_FW)) { | |
5770 | qemu_log_mask(LOG_GUEST_ERROR, | |
5771 | "Ignoring attempt to switch CPSR_F flag from " | |
5772 | "non-secure world with SCR.FW bit clear\n"); | |
5773 | mask &= ~CPSR_F; | |
5774 | } | |
5775 | ||
5776 | /* Check whether non-maskable FIQ (NMFI) support is enabled. | |
5777 | * If this bit is set software is not allowed to mask | |
5778 | * FIQs, but is allowed to set CPSR_F to 0. | |
5779 | */ | |
5780 | if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && | |
5781 | (val & CPSR_F)) { | |
5782 | qemu_log_mask(LOG_GUEST_ERROR, | |
5783 | "Ignoring attempt to enable CPSR_F flag " | |
5784 | "(non-maskable FIQ [NMFI] support enabled)\n"); | |
5785 | mask &= ~CPSR_F; | |
5786 | } | |
5787 | } | |
5788 | } | |
5789 | ||
4cc35614 PM |
5790 | env->daif &= ~(CPSR_AIF & mask); |
5791 | env->daif |= val & CPSR_AIF & mask; | |
5792 | ||
f8c88bbc PM |
5793 | if (write_type != CPSRWriteRaw && |
5794 | ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { | |
8c4f0eb9 PM |
5795 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { |
5796 | /* Note that we can only get here in USR mode if this is a | |
5797 | * gdb stub write; for this case we follow the architectural | |
5798 | * behaviour for guest writes in USR mode of ignoring an attempt | |
5799 | * to switch mode. (Those are caught by translate.c for writes | |
5800 | * triggered by guest instructions.) | |
5801 | */ | |
5802 | mask &= ~CPSR_M; | |
5803 | } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { | |
81907a58 PM |
5804 | /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in |
5805 | * v7, and has defined behaviour in v8: | |
5806 | * + leave CPSR.M untouched | |
5807 | * + allow changes to the other CPSR fields | |
5808 | * + set PSTATE.IL | |
5809 | * For user changes via the GDB stub, we don't set PSTATE.IL, | |
5810 | * as this would be unnecessarily harsh for a user error. | |
37064a8b PM |
5811 | */ |
5812 | mask &= ~CPSR_M; | |
81907a58 PM |
5813 | if (write_type != CPSRWriteByGDBStub && |
5814 | arm_feature(env, ARM_FEATURE_V8)) { | |
5815 | mask |= CPSR_IL; | |
5816 | val |= CPSR_IL; | |
5817 | } | |
37064a8b PM |
5818 | } else { |
5819 | switch_mode(env, val & CPSR_M); | |
5820 | } | |
2f4a40e5 AZ |
5821 | } |
5822 | mask &= ~CACHED_CPSR_BITS; | |
5823 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
5824 | } | |
5825 | ||
b26eefb6 PB |
5826 | /* Sign/zero extend */ |
5827 | uint32_t HELPER(sxtb16)(uint32_t x) | |
5828 | { | |
5829 | uint32_t res; | |
5830 | res = (uint16_t)(int8_t)x; | |
5831 | res |= (uint32_t)(int8_t)(x >> 16) << 16; | |
5832 | return res; | |
5833 | } | |
5834 | ||
5835 | uint32_t HELPER(uxtb16)(uint32_t x) | |
5836 | { | |
5837 | uint32_t res; | |
5838 | res = (uint16_t)(uint8_t)x; | |
5839 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; | |
5840 | return res; | |
5841 | } | |
5842 | ||
3670669c PB |
5843 | int32_t HELPER(sdiv)(int32_t num, int32_t den) |
5844 | { | |
5845 | if (den == 0) | |
5846 | return 0; | |
686eeb93 AJ |
5847 | if (num == INT_MIN && den == -1) |
5848 | return INT_MIN; | |
3670669c PB |
5849 | return num / den; |
5850 | } | |
5851 | ||
5852 | uint32_t HELPER(udiv)(uint32_t num, uint32_t den) | |
5853 | { | |
5854 | if (den == 0) | |
5855 | return 0; | |
5856 | return num / den; | |
5857 | } | |
5858 | ||
5859 | uint32_t HELPER(rbit)(uint32_t x) | |
5860 | { | |
42fedbca | 5861 | return revbit32(x); |
3670669c PB |
5862 | } |
5863 | ||
5fafdf24 | 5864 | #if defined(CONFIG_USER_ONLY) |
b5ff1b31 | 5865 | |
9ee6e8bb | 5866 | /* These should probably raise undefined insn exceptions. */ |
0ecb72a5 | 5867 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) |
9ee6e8bb | 5868 | { |
a47dddd7 AF |
5869 | ARMCPU *cpu = arm_env_get_cpu(env); |
5870 | ||
5871 | cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); | |
9ee6e8bb PB |
5872 | } |
5873 | ||
0ecb72a5 | 5874 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb | 5875 | { |
a47dddd7 AF |
5876 | ARMCPU *cpu = arm_env_get_cpu(env); |
5877 | ||
5878 | cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); | |
9ee6e8bb PB |
5879 | return 0; |
5880 | } | |
5881 | ||
0ecb72a5 | 5882 | void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 | 5883 | { |
a47dddd7 AF |
5884 | ARMCPU *cpu = arm_env_get_cpu(env); |
5885 | ||
5886 | if (mode != ARM_CPU_MODE_USR) { | |
5887 | cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); | |
5888 | } | |
b5ff1b31 FB |
5889 | } |
5890 | ||
012a906b GB |
5891 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
5892 | uint32_t cur_el, bool secure) | |
9e729b57 EI |
5893 | { |
5894 | return 1; | |
5895 | } | |
5896 | ||
ce02049d GB |
5897 | void aarch64_sync_64_to_32(CPUARMState *env) |
5898 | { | |
5899 | g_assert_not_reached(); | |
5900 | } | |
5901 | ||
b5ff1b31 FB |
5902 | #else |
5903 | ||
0ecb72a5 | 5904 | void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
5905 | { |
5906 | int old_mode; | |
5907 | int i; | |
5908 | ||
5909 | old_mode = env->uncached_cpsr & CPSR_M; | |
5910 | if (mode == old_mode) | |
5911 | return; | |
5912 | ||
5913 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
5914 | memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 5915 | memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
5916 | } else if (mode == ARM_CPU_MODE_FIQ) { |
5917 | memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 5918 | memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
5919 | } |
5920 | ||
f5206413 | 5921 | i = bank_number(old_mode); |
b5ff1b31 FB |
5922 | env->banked_r13[i] = env->regs[13]; |
5923 | env->banked_r14[i] = env->regs[14]; | |
5924 | env->banked_spsr[i] = env->spsr; | |
5925 | ||
f5206413 | 5926 | i = bank_number(mode); |
b5ff1b31 FB |
5927 | env->regs[13] = env->banked_r13[i]; |
5928 | env->regs[14] = env->banked_r14[i]; | |
5929 | env->spsr = env->banked_spsr[i]; | |
5930 | } | |
5931 | ||
0eeb17d6 GB |
5932 | /* Physical Interrupt Target EL Lookup Table |
5933 | * | |
5934 | * [ From ARM ARM section G1.13.4 (Table G1-15) ] | |
5935 | * | |
5936 | * The below multi-dimensional table is used for looking up the target | |
5937 | * exception level given numerous condition criteria. Specifically, the | |
5938 | * target EL is based on SCR and HCR routing controls as well as the | |
5939 | * currently executing EL and secure state. | |
5940 | * | |
5941 | * Dimensions: | |
5942 | * target_el_table[2][2][2][2][2][4] | |
5943 | * | | | | | +--- Current EL | |
5944 | * | | | | +------ Non-secure(0)/Secure(1) | |
5945 | * | | | +--------- HCR mask override | |
5946 | * | | +------------ SCR exec state control | |
5947 | * | +--------------- SCR mask override | |
5948 | * +------------------ 32-bit(0)/64-bit(1) EL3 | |
5949 | * | |
5950 | * The table values are as such: | |
5951 | * 0-3 = EL0-EL3 | |
5952 | * -1 = Cannot occur | |
5953 | * | |
5954 | * The ARM ARM target EL table includes entries indicating that an "exception | |
5955 | * is not taken". The two cases where this is applicable are: | |
5956 | * 1) An exception is taken from EL3 but the SCR does not have the exception | |
5957 | * routed to EL3. | |
5958 | * 2) An exception is taken from EL2 but the HCR does not have the exception | |
5959 | * routed to EL2. | |
5960 | * In these two cases, the below table contain a target of EL1. This value is | |
5961 | * returned as it is expected that the consumer of the table data will check | |
5962 | * for "target EL >= current EL" to ensure the exception is not taken. | |
5963 | * | |
5964 | * SCR HCR | |
5965 | * 64 EA AMO From | |
5966 | * BIT IRQ IMO Non-secure Secure | |
5967 | * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 | |
5968 | */ | |
82c39f6a | 5969 | static const int8_t target_el_table[2][2][2][2][2][4] = { |
0eeb17d6 GB |
5970 | {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, |
5971 | {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, | |
5972 | {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, | |
5973 | {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, | |
5974 | {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
5975 | {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, | |
5976 | {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
5977 | {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, | |
5978 | {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, | |
5979 | {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},}, | |
5980 | {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },}, | |
5981 | {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},}, | |
5982 | {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, | |
5983 | {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, | |
5984 | {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, | |
5985 | {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},}, | |
5986 | }; | |
5987 | ||
5988 | /* | |
5989 | * Determine the target EL for physical exceptions | |
5990 | */ | |
012a906b GB |
5991 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
5992 | uint32_t cur_el, bool secure) | |
0eeb17d6 GB |
5993 | { |
5994 | CPUARMState *env = cs->env_ptr; | |
2cde031f | 5995 | int rw; |
0eeb17d6 GB |
5996 | int scr; |
5997 | int hcr; | |
5998 | int target_el; | |
2cde031f SS |
5999 | /* Is the highest EL AArch64? */ |
6000 | int is64 = arm_feature(env, ARM_FEATURE_AARCH64); | |
6001 | ||
6002 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
6003 | rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); | |
6004 | } else { | |
6005 | /* Either EL2 is the highest EL (and so the EL2 register width | |
6006 | * is given by is64); or there is no EL2 or EL3, in which case | |
6007 | * the value of 'rw' does not affect the table lookup anyway. | |
6008 | */ | |
6009 | rw = is64; | |
6010 | } | |
0eeb17d6 GB |
6011 | |
6012 | switch (excp_idx) { | |
6013 | case EXCP_IRQ: | |
6014 | scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); | |
6015 | hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO); | |
6016 | break; | |
6017 | case EXCP_FIQ: | |
6018 | scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); | |
6019 | hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO); | |
6020 | break; | |
6021 | default: | |
6022 | scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); | |
6023 | hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO); | |
6024 | break; | |
6025 | }; | |
6026 | ||
6027 | /* If HCR.TGE is set then HCR is treated as being 1 */ | |
6028 | hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE); | |
6029 | ||
6030 | /* Perform a table-lookup for the target EL given the current state */ | |
6031 | target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; | |
6032 | ||
6033 | assert(target_el > 0); | |
6034 | ||
6035 | return target_el; | |
6036 | } | |
6037 | ||
9ee6e8bb PB |
6038 | static void v7m_push(CPUARMState *env, uint32_t val) |
6039 | { | |
70d74660 AF |
6040 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
6041 | ||
9ee6e8bb | 6042 | env->regs[13] -= 4; |
ab1da857 | 6043 | stl_phys(cs->as, env->regs[13], val); |
9ee6e8bb PB |
6044 | } |
6045 | ||
6046 | static uint32_t v7m_pop(CPUARMState *env) | |
6047 | { | |
70d74660 | 6048 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
9ee6e8bb | 6049 | uint32_t val; |
70d74660 | 6050 | |
fdfba1a2 | 6051 | val = ldl_phys(cs->as, env->regs[13]); |
9ee6e8bb PB |
6052 | env->regs[13] += 4; |
6053 | return val; | |
6054 | } | |
6055 | ||
6056 | /* Switch to V7M main or process stack pointer. */ | |
abc24d86 | 6057 | static void switch_v7m_sp(CPUARMState *env, bool new_spsel) |
9ee6e8bb PB |
6058 | { |
6059 | uint32_t tmp; | |
abc24d86 MD |
6060 | bool old_spsel = env->v7m.control & R_V7M_CONTROL_SPSEL_MASK; |
6061 | ||
6062 | if (old_spsel != new_spsel) { | |
9ee6e8bb PB |
6063 | tmp = env->v7m.other_sp; |
6064 | env->v7m.other_sp = env->regs[13]; | |
6065 | env->regs[13] = tmp; | |
abc24d86 MD |
6066 | |
6067 | env->v7m.control = deposit32(env->v7m.control, | |
6068 | R_V7M_CONTROL_SPSEL_SHIFT, | |
6069 | R_V7M_CONTROL_SPSEL_LENGTH, new_spsel); | |
9ee6e8bb PB |
6070 | } |
6071 | } | |
6072 | ||
39ae2474 PM |
6073 | static uint32_t arm_v7m_load_vector(ARMCPU *cpu) |
6074 | { | |
6075 | CPUState *cs = CPU(cpu); | |
6076 | CPUARMState *env = &cpu->env; | |
6077 | MemTxResult result; | |
6078 | hwaddr vec = env->v7m.vecbase + env->v7m.exception * 4; | |
6079 | uint32_t addr; | |
6080 | ||
6081 | addr = address_space_ldl(cs->as, vec, | |
6082 | MEMTXATTRS_UNSPECIFIED, &result); | |
6083 | if (result != MEMTX_OK) { | |
6084 | /* Architecturally this should cause a HardFault setting HSFR.VECTTBL, | |
6085 | * which would then be immediately followed by our failing to load | |
6086 | * the entry vector for that HardFault, which is a Lockup case. | |
6087 | * Since we don't model Lockup, we just report this guest error | |
6088 | * via cpu_abort(). | |
6089 | */ | |
6090 | cpu_abort(cs, "Failed to read from exception vector table " | |
6091 | "entry %08x\n", (unsigned)vec); | |
6092 | } | |
6093 | return addr; | |
6094 | } | |
6095 | ||
6096 | static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr) | |
6097 | { | |
6098 | /* Do the "take the exception" parts of exception entry, | |
6099 | * but not the pushing of state to the stack. This is | |
6100 | * similar to the pseudocode ExceptionTaken() function. | |
6101 | */ | |
6102 | CPUARMState *env = &cpu->env; | |
6103 | uint32_t addr; | |
6104 | ||
6105 | armv7m_nvic_acknowledge_irq(env->nvic); | |
6106 | switch_v7m_sp(env, 0); | |
6107 | /* Clear IT bits */ | |
6108 | env->condexec_bits = 0; | |
6109 | env->regs[14] = lr; | |
6110 | addr = arm_v7m_load_vector(cpu); | |
6111 | env->regs[15] = addr & 0xfffffffe; | |
6112 | env->thumb = addr & 1; | |
6113 | } | |
6114 | ||
6115 | static void v7m_push_stack(ARMCPU *cpu) | |
6116 | { | |
6117 | /* Do the "set up stack frame" part of exception entry, | |
6118 | * similar to pseudocode PushStack(). | |
6119 | */ | |
6120 | CPUARMState *env = &cpu->env; | |
6121 | uint32_t xpsr = xpsr_read(env); | |
6122 | ||
6123 | /* Align stack pointer if the guest wants that */ | |
6124 | if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) { | |
6125 | env->regs[13] -= 4; | |
6126 | xpsr |= 0x200; | |
6127 | } | |
6128 | /* Switch to the handler mode. */ | |
6129 | v7m_push(env, xpsr); | |
6130 | v7m_push(env, env->regs[15]); | |
6131 | v7m_push(env, env->regs[14]); | |
6132 | v7m_push(env, env->regs[12]); | |
6133 | v7m_push(env, env->regs[3]); | |
6134 | v7m_push(env, env->regs[2]); | |
6135 | v7m_push(env, env->regs[1]); | |
6136 | v7m_push(env, env->regs[0]); | |
6137 | } | |
6138 | ||
aa488fe3 | 6139 | static void do_v7m_exception_exit(ARMCPU *cpu) |
9ee6e8bb | 6140 | { |
aa488fe3 | 6141 | CPUARMState *env = &cpu->env; |
9ee6e8bb PB |
6142 | uint32_t type; |
6143 | uint32_t xpsr; | |
aa488fe3 PM |
6144 | bool ufault = false; |
6145 | bool return_to_sp_process = false; | |
6146 | bool return_to_handler = false; | |
6147 | bool rettobase = false; | |
6148 | ||
6149 | /* We can only get here from an EXCP_EXCEPTION_EXIT, and | |
6150 | * arm_v7m_do_unassigned_access() enforces the architectural rule | |
6151 | * that jumps to magic addresses don't have magic behaviour unless | |
6152 | * we're in Handler mode (compare pseudocode BXWritePC()). | |
6153 | */ | |
6154 | assert(env->v7m.exception != 0); | |
6155 | ||
6156 | /* In the spec pseudocode ExceptionReturn() is called directly | |
6157 | * from BXWritePC() and gets the full target PC value including | |
6158 | * bit zero. In QEMU's implementation we treat it as a normal | |
6159 | * jump-to-register (which is then caught later on), and so split | |
6160 | * the target value up between env->regs[15] and env->thumb in | |
6161 | * gen_bx(). Reconstitute it. | |
6162 | */ | |
9ee6e8bb | 6163 | type = env->regs[15]; |
aa488fe3 PM |
6164 | if (env->thumb) { |
6165 | type |= 1; | |
6166 | } | |
6167 | ||
6168 | qemu_log_mask(CPU_LOG_INT, "Exception return: magic PC %" PRIx32 | |
6169 | " previous exception %d\n", | |
6170 | type, env->v7m.exception); | |
6171 | ||
6172 | if (extract32(type, 5, 23) != extract32(-1, 5, 23)) { | |
6173 | qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception " | |
6174 | "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", type); | |
6175 | } | |
6176 | ||
a20ee600 MD |
6177 | if (env->v7m.exception != ARMV7M_EXCP_NMI) { |
6178 | /* Auto-clear FAULTMASK on return from other than NMI */ | |
6179 | env->daif &= ~PSTATE_F; | |
6180 | } | |
aa488fe3 PM |
6181 | |
6182 | switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception)) { | |
6183 | case -1: | |
6184 | /* attempt to exit an exception that isn't active */ | |
6185 | ufault = true; | |
6186 | break; | |
6187 | case 0: | |
6188 | /* still an irq active now */ | |
6189 | break; | |
6190 | case 1: | |
6191 | /* we returned to base exception level, no nesting. | |
6192 | * (In the pseudocode this is written using "NestedActivation != 1" | |
6193 | * where we have 'rettobase == false'.) | |
6194 | */ | |
6195 | rettobase = true; | |
6196 | break; | |
6197 | default: | |
6198 | g_assert_not_reached(); | |
6199 | } | |
6200 | ||
6201 | switch (type & 0xf) { | |
6202 | case 1: /* Return to Handler */ | |
6203 | return_to_handler = true; | |
6204 | break; | |
6205 | case 13: /* Return to Thread using Process stack */ | |
6206 | return_to_sp_process = true; | |
6207 | /* fall through */ | |
6208 | case 9: /* Return to Thread using Main stack */ | |
6209 | if (!rettobase && | |
6210 | !(env->v7m.ccr & R_V7M_CCR_NONBASETHRDENA_MASK)) { | |
6211 | ufault = true; | |
6212 | } | |
6213 | break; | |
6214 | default: | |
6215 | ufault = true; | |
6216 | } | |
6217 | ||
6218 | if (ufault) { | |
6219 | /* Bad exception return: instead of popping the exception | |
6220 | * stack, directly take a usage fault on the current stack. | |
6221 | */ | |
6222 | env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK; | |
6223 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); | |
6224 | v7m_exception_taken(cpu, type | 0xf0000000); | |
6225 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " | |
6226 | "stackframe: failed exception return integrity check\n"); | |
6227 | return; | |
a20ee600 | 6228 | } |
9ee6e8bb PB |
6229 | |
6230 | /* Switch to the target stack. */ | |
aa488fe3 | 6231 | switch_v7m_sp(env, return_to_sp_process); |
9ee6e8bb PB |
6232 | /* Pop registers. */ |
6233 | env->regs[0] = v7m_pop(env); | |
6234 | env->regs[1] = v7m_pop(env); | |
6235 | env->regs[2] = v7m_pop(env); | |
6236 | env->regs[3] = v7m_pop(env); | |
6237 | env->regs[12] = v7m_pop(env); | |
6238 | env->regs[14] = v7m_pop(env); | |
6239 | env->regs[15] = v7m_pop(env); | |
fcf83ab1 PM |
6240 | if (env->regs[15] & 1) { |
6241 | qemu_log_mask(LOG_GUEST_ERROR, | |
6242 | "M profile return from interrupt with misaligned " | |
6243 | "PC is UNPREDICTABLE\n"); | |
6244 | /* Actual hardware seems to ignore the lsbit, and there are several | |
6245 | * RTOSes out there which incorrectly assume the r15 in the stack | |
6246 | * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value. | |
6247 | */ | |
6248 | env->regs[15] &= ~1U; | |
6249 | } | |
9ee6e8bb PB |
6250 | xpsr = v7m_pop(env); |
6251 | xpsr_write(env, xpsr, 0xfffffdff); | |
6252 | /* Undo stack alignment. */ | |
6253 | if (xpsr & 0x200) | |
6254 | env->regs[13] |= 4; | |
aa488fe3 PM |
6255 | |
6256 | /* The restored xPSR exception field will be zero if we're | |
6257 | * resuming in Thread mode. If that doesn't match what the | |
6258 | * exception return type specified then this is a UsageFault. | |
6259 | */ | |
6260 | if (return_to_handler == (env->v7m.exception == 0)) { | |
6261 | /* Take an INVPC UsageFault by pushing the stack again. */ | |
6262 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); | |
6263 | env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK; | |
6264 | v7m_push_stack(cpu); | |
6265 | v7m_exception_taken(cpu, type | 0xf0000000); | |
6266 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: " | |
6267 | "failed exception return integrity check\n"); | |
6268 | return; | |
6269 | } | |
6270 | ||
6271 | /* Otherwise, we have a successful exception exit. */ | |
6272 | qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); | |
9ee6e8bb PB |
6273 | } |
6274 | ||
27a7ea8a PB |
6275 | static void arm_log_exception(int idx) |
6276 | { | |
6277 | if (qemu_loglevel_mask(CPU_LOG_INT)) { | |
6278 | const char *exc = NULL; | |
2c4a7cc5 PM |
6279 | static const char * const excnames[] = { |
6280 | [EXCP_UDEF] = "Undefined Instruction", | |
6281 | [EXCP_SWI] = "SVC", | |
6282 | [EXCP_PREFETCH_ABORT] = "Prefetch Abort", | |
6283 | [EXCP_DATA_ABORT] = "Data Abort", | |
6284 | [EXCP_IRQ] = "IRQ", | |
6285 | [EXCP_FIQ] = "FIQ", | |
6286 | [EXCP_BKPT] = "Breakpoint", | |
6287 | [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", | |
6288 | [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", | |
6289 | [EXCP_HVC] = "Hypervisor Call", | |
6290 | [EXCP_HYP_TRAP] = "Hypervisor Trap", | |
6291 | [EXCP_SMC] = "Secure Monitor Call", | |
6292 | [EXCP_VIRQ] = "Virtual IRQ", | |
6293 | [EXCP_VFIQ] = "Virtual FIQ", | |
6294 | [EXCP_SEMIHOST] = "Semihosting call", | |
6295 | [EXCP_NOCP] = "v7M NOCP UsageFault", | |
6296 | [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", | |
6297 | }; | |
27a7ea8a PB |
6298 | |
6299 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | |
6300 | exc = excnames[idx]; | |
6301 | } | |
6302 | if (!exc) { | |
6303 | exc = "unknown"; | |
6304 | } | |
6305 | qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); | |
6306 | } | |
6307 | } | |
6308 | ||
e6f010cc | 6309 | void arm_v7m_cpu_do_interrupt(CPUState *cs) |
9ee6e8bb | 6310 | { |
e6f010cc AF |
6311 | ARMCPU *cpu = ARM_CPU(cs); |
6312 | CPUARMState *env = &cpu->env; | |
9ee6e8bb | 6313 | uint32_t lr; |
9ee6e8bb | 6314 | |
27103424 | 6315 | arm_log_exception(cs->exception_index); |
3f1beaca | 6316 | |
9ee6e8bb | 6317 | lr = 0xfffffff1; |
abc24d86 | 6318 | if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { |
9ee6e8bb | 6319 | lr |= 4; |
abc24d86 | 6320 | } |
9ee6e8bb PB |
6321 | if (env->v7m.exception == 0) |
6322 | lr |= 8; | |
6323 | ||
6324 | /* For exceptions we just mark as pending on the NVIC, and let that | |
6325 | handle it. */ | |
27103424 | 6326 | switch (cs->exception_index) { |
9ee6e8bb | 6327 | case EXCP_UDEF: |
983fe826 | 6328 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); |
81dd9648 | 6329 | env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK; |
a25dc805 | 6330 | break; |
7517748e PM |
6331 | case EXCP_NOCP: |
6332 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); | |
6333 | env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK; | |
a25dc805 | 6334 | break; |
e13886e3 PM |
6335 | case EXCP_INVSTATE: |
6336 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); | |
6337 | env->v7m.cfsr |= R_V7M_CFSR_INVSTATE_MASK; | |
6338 | break; | |
9ee6e8bb | 6339 | case EXCP_SWI: |
314e2296 | 6340 | /* The PC already points to the next instruction. */ |
983fe826 | 6341 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); |
a25dc805 | 6342 | break; |
9ee6e8bb PB |
6343 | case EXCP_PREFETCH_ABORT: |
6344 | case EXCP_DATA_ABORT: | |
abf1172f PM |
6345 | /* TODO: if we implemented the MPU registers, this is where we |
6346 | * should set the MMFAR, etc from exception.fsr and exception.vaddress. | |
6347 | */ | |
983fe826 | 6348 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); |
a25dc805 | 6349 | break; |
9ee6e8bb | 6350 | case EXCP_BKPT: |
cfe67cef | 6351 | if (semihosting_enabled()) { |
2ad207d4 | 6352 | int nr; |
f9fd40eb | 6353 | nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff; |
2ad207d4 PB |
6354 | if (nr == 0xab) { |
6355 | env->regs[15] += 2; | |
205ace55 CC |
6356 | qemu_log_mask(CPU_LOG_INT, |
6357 | "...handling as semihosting call 0x%x\n", | |
6358 | env->regs[0]); | |
2ad207d4 PB |
6359 | env->regs[0] = do_arm_semihosting(env); |
6360 | return; | |
6361 | } | |
6362 | } | |
983fe826 | 6363 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG); |
a25dc805 | 6364 | break; |
9ee6e8bb | 6365 | case EXCP_IRQ: |
9ee6e8bb PB |
6366 | break; |
6367 | case EXCP_EXCEPTION_EXIT: | |
aa488fe3 | 6368 | do_v7m_exception_exit(cpu); |
9ee6e8bb PB |
6369 | return; |
6370 | default: | |
a47dddd7 | 6371 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
9ee6e8bb PB |
6372 | return; /* Never happens. Keep compiler happy. */ |
6373 | } | |
6374 | ||
39ae2474 PM |
6375 | v7m_push_stack(cpu); |
6376 | v7m_exception_taken(cpu, lr); | |
a25dc805 | 6377 | qemu_log_mask(CPU_LOG_INT, "... as %d\n", env->v7m.exception); |
9ee6e8bb PB |
6378 | } |
6379 | ||
ce02049d GB |
6380 | /* Function used to synchronize QEMU's AArch64 register set with AArch32 |
6381 | * register set. This is necessary when switching between AArch32 and AArch64 | |
6382 | * execution state. | |
6383 | */ | |
6384 | void aarch64_sync_32_to_64(CPUARMState *env) | |
6385 | { | |
6386 | int i; | |
6387 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
6388 | ||
6389 | /* We can blanket copy R[0:7] to X[0:7] */ | |
6390 | for (i = 0; i < 8; i++) { | |
6391 | env->xregs[i] = env->regs[i]; | |
6392 | } | |
6393 | ||
6394 | /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. | |
6395 | * Otherwise, they come from the banked user regs. | |
6396 | */ | |
6397 | if (mode == ARM_CPU_MODE_FIQ) { | |
6398 | for (i = 8; i < 13; i++) { | |
6399 | env->xregs[i] = env->usr_regs[i - 8]; | |
6400 | } | |
6401 | } else { | |
6402 | for (i = 8; i < 13; i++) { | |
6403 | env->xregs[i] = env->regs[i]; | |
6404 | } | |
6405 | } | |
6406 | ||
6407 | /* Registers x13-x23 are the various mode SP and FP registers. Registers | |
6408 | * r13 and r14 are only copied if we are in that mode, otherwise we copy | |
6409 | * from the mode banked register. | |
6410 | */ | |
6411 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { | |
6412 | env->xregs[13] = env->regs[13]; | |
6413 | env->xregs[14] = env->regs[14]; | |
6414 | } else { | |
6415 | env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; | |
6416 | /* HYP is an exception in that it is copied from r14 */ | |
6417 | if (mode == ARM_CPU_MODE_HYP) { | |
6418 | env->xregs[14] = env->regs[14]; | |
6419 | } else { | |
6420 | env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)]; | |
6421 | } | |
6422 | } | |
6423 | ||
6424 | if (mode == ARM_CPU_MODE_HYP) { | |
6425 | env->xregs[15] = env->regs[13]; | |
6426 | } else { | |
6427 | env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; | |
6428 | } | |
6429 | ||
6430 | if (mode == ARM_CPU_MODE_IRQ) { | |
3a9148d0 SS |
6431 | env->xregs[16] = env->regs[14]; |
6432 | env->xregs[17] = env->regs[13]; | |
ce02049d | 6433 | } else { |
3a9148d0 SS |
6434 | env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)]; |
6435 | env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; | |
ce02049d GB |
6436 | } |
6437 | ||
6438 | if (mode == ARM_CPU_MODE_SVC) { | |
3a9148d0 SS |
6439 | env->xregs[18] = env->regs[14]; |
6440 | env->xregs[19] = env->regs[13]; | |
ce02049d | 6441 | } else { |
3a9148d0 SS |
6442 | env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)]; |
6443 | env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; | |
ce02049d GB |
6444 | } |
6445 | ||
6446 | if (mode == ARM_CPU_MODE_ABT) { | |
3a9148d0 SS |
6447 | env->xregs[20] = env->regs[14]; |
6448 | env->xregs[21] = env->regs[13]; | |
ce02049d | 6449 | } else { |
3a9148d0 SS |
6450 | env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)]; |
6451 | env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; | |
ce02049d GB |
6452 | } |
6453 | ||
6454 | if (mode == ARM_CPU_MODE_UND) { | |
3a9148d0 SS |
6455 | env->xregs[22] = env->regs[14]; |
6456 | env->xregs[23] = env->regs[13]; | |
ce02049d | 6457 | } else { |
3a9148d0 SS |
6458 | env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)]; |
6459 | env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; | |
ce02049d GB |
6460 | } |
6461 | ||
6462 | /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ | |
6463 | * mode, then we can copy from r8-r14. Otherwise, we copy from the | |
6464 | * FIQ bank for r8-r14. | |
6465 | */ | |
6466 | if (mode == ARM_CPU_MODE_FIQ) { | |
6467 | for (i = 24; i < 31; i++) { | |
6468 | env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ | |
6469 | } | |
6470 | } else { | |
6471 | for (i = 24; i < 29; i++) { | |
6472 | env->xregs[i] = env->fiq_regs[i - 24]; | |
6473 | } | |
6474 | env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; | |
6475 | env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)]; | |
6476 | } | |
6477 | ||
6478 | env->pc = env->regs[15]; | |
6479 | } | |
6480 | ||
6481 | /* Function used to synchronize QEMU's AArch32 register set with AArch64 | |
6482 | * register set. This is necessary when switching between AArch32 and AArch64 | |
6483 | * execution state. | |
6484 | */ | |
6485 | void aarch64_sync_64_to_32(CPUARMState *env) | |
6486 | { | |
6487 | int i; | |
6488 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
6489 | ||
6490 | /* We can blanket copy X[0:7] to R[0:7] */ | |
6491 | for (i = 0; i < 8; i++) { | |
6492 | env->regs[i] = env->xregs[i]; | |
6493 | } | |
6494 | ||
6495 | /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. | |
6496 | * Otherwise, we copy x8-x12 into the banked user regs. | |
6497 | */ | |
6498 | if (mode == ARM_CPU_MODE_FIQ) { | |
6499 | for (i = 8; i < 13; i++) { | |
6500 | env->usr_regs[i - 8] = env->xregs[i]; | |
6501 | } | |
6502 | } else { | |
6503 | for (i = 8; i < 13; i++) { | |
6504 | env->regs[i] = env->xregs[i]; | |
6505 | } | |
6506 | } | |
6507 | ||
6508 | /* Registers r13 & r14 depend on the current mode. | |
6509 | * If we are in a given mode, we copy the corresponding x registers to r13 | |
6510 | * and r14. Otherwise, we copy the x register to the banked r13 and r14 | |
6511 | * for the mode. | |
6512 | */ | |
6513 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { | |
6514 | env->regs[13] = env->xregs[13]; | |
6515 | env->regs[14] = env->xregs[14]; | |
6516 | } else { | |
6517 | env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; | |
6518 | ||
6519 | /* HYP is an exception in that it does not have its own banked r14 but | |
6520 | * shares the USR r14 | |
6521 | */ | |
6522 | if (mode == ARM_CPU_MODE_HYP) { | |
6523 | env->regs[14] = env->xregs[14]; | |
6524 | } else { | |
6525 | env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; | |
6526 | } | |
6527 | } | |
6528 | ||
6529 | if (mode == ARM_CPU_MODE_HYP) { | |
6530 | env->regs[13] = env->xregs[15]; | |
6531 | } else { | |
6532 | env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; | |
6533 | } | |
6534 | ||
6535 | if (mode == ARM_CPU_MODE_IRQ) { | |
3a9148d0 SS |
6536 | env->regs[14] = env->xregs[16]; |
6537 | env->regs[13] = env->xregs[17]; | |
ce02049d | 6538 | } else { |
3a9148d0 SS |
6539 | env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; |
6540 | env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; | |
ce02049d GB |
6541 | } |
6542 | ||
6543 | if (mode == ARM_CPU_MODE_SVC) { | |
3a9148d0 SS |
6544 | env->regs[14] = env->xregs[18]; |
6545 | env->regs[13] = env->xregs[19]; | |
ce02049d | 6546 | } else { |
3a9148d0 SS |
6547 | env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; |
6548 | env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; | |
ce02049d GB |
6549 | } |
6550 | ||
6551 | if (mode == ARM_CPU_MODE_ABT) { | |
3a9148d0 SS |
6552 | env->regs[14] = env->xregs[20]; |
6553 | env->regs[13] = env->xregs[21]; | |
ce02049d | 6554 | } else { |
3a9148d0 SS |
6555 | env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; |
6556 | env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; | |
ce02049d GB |
6557 | } |
6558 | ||
6559 | if (mode == ARM_CPU_MODE_UND) { | |
3a9148d0 SS |
6560 | env->regs[14] = env->xregs[22]; |
6561 | env->regs[13] = env->xregs[23]; | |
ce02049d | 6562 | } else { |
3a9148d0 SS |
6563 | env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; |
6564 | env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; | |
ce02049d GB |
6565 | } |
6566 | ||
6567 | /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ | |
6568 | * mode, then we can copy to r8-r14. Otherwise, we copy to the | |
6569 | * FIQ bank for r8-r14. | |
6570 | */ | |
6571 | if (mode == ARM_CPU_MODE_FIQ) { | |
6572 | for (i = 24; i < 31; i++) { | |
6573 | env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ | |
6574 | } | |
6575 | } else { | |
6576 | for (i = 24; i < 29; i++) { | |
6577 | env->fiq_regs[i - 24] = env->xregs[i]; | |
6578 | } | |
6579 | env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; | |
6580 | env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; | |
6581 | } | |
6582 | ||
6583 | env->regs[15] = env->pc; | |
6584 | } | |
6585 | ||
966f758c | 6586 | static void arm_cpu_do_interrupt_aarch32(CPUState *cs) |
b5ff1b31 | 6587 | { |
97a8ea5a AF |
6588 | ARMCPU *cpu = ARM_CPU(cs); |
6589 | CPUARMState *env = &cpu->env; | |
b5ff1b31 FB |
6590 | uint32_t addr; |
6591 | uint32_t mask; | |
6592 | int new_mode; | |
6593 | uint32_t offset; | |
16a906fd | 6594 | uint32_t moe; |
b5ff1b31 | 6595 | |
16a906fd PM |
6596 | /* If this is a debug exception we must update the DBGDSCR.MOE bits */ |
6597 | switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) { | |
6598 | case EC_BREAKPOINT: | |
6599 | case EC_BREAKPOINT_SAME_EL: | |
6600 | moe = 1; | |
6601 | break; | |
6602 | case EC_WATCHPOINT: | |
6603 | case EC_WATCHPOINT_SAME_EL: | |
6604 | moe = 10; | |
6605 | break; | |
6606 | case EC_AA32_BKPT: | |
6607 | moe = 3; | |
6608 | break; | |
6609 | case EC_VECTORCATCH: | |
6610 | moe = 5; | |
6611 | break; | |
6612 | default: | |
6613 | moe = 0; | |
6614 | break; | |
6615 | } | |
6616 | ||
6617 | if (moe) { | |
6618 | env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); | |
6619 | } | |
6620 | ||
b5ff1b31 | 6621 | /* TODO: Vectored interrupt controller. */ |
27103424 | 6622 | switch (cs->exception_index) { |
b5ff1b31 FB |
6623 | case EXCP_UDEF: |
6624 | new_mode = ARM_CPU_MODE_UND; | |
6625 | addr = 0x04; | |
6626 | mask = CPSR_I; | |
6627 | if (env->thumb) | |
6628 | offset = 2; | |
6629 | else | |
6630 | offset = 4; | |
6631 | break; | |
6632 | case EXCP_SWI: | |
6633 | new_mode = ARM_CPU_MODE_SVC; | |
6634 | addr = 0x08; | |
6635 | mask = CPSR_I; | |
601d70b9 | 6636 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
6637 | offset = 0; |
6638 | break; | |
06c949e6 | 6639 | case EXCP_BKPT: |
abf1172f | 6640 | env->exception.fsr = 2; |
9ee6e8bb PB |
6641 | /* Fall through to prefetch abort. */ |
6642 | case EXCP_PREFETCH_ABORT: | |
88ca1c2d | 6643 | A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); |
b848ce2b | 6644 | A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); |
3f1beaca | 6645 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", |
88ca1c2d | 6646 | env->exception.fsr, (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
6647 | new_mode = ARM_CPU_MODE_ABT; |
6648 | addr = 0x0c; | |
6649 | mask = CPSR_A | CPSR_I; | |
6650 | offset = 4; | |
6651 | break; | |
6652 | case EXCP_DATA_ABORT: | |
4a7e2d73 | 6653 | A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); |
b848ce2b | 6654 | A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); |
3f1beaca | 6655 | qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", |
4a7e2d73 | 6656 | env->exception.fsr, |
6cd8a264 | 6657 | (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
6658 | new_mode = ARM_CPU_MODE_ABT; |
6659 | addr = 0x10; | |
6660 | mask = CPSR_A | CPSR_I; | |
6661 | offset = 8; | |
6662 | break; | |
6663 | case EXCP_IRQ: | |
6664 | new_mode = ARM_CPU_MODE_IRQ; | |
6665 | addr = 0x18; | |
6666 | /* Disable IRQ and imprecise data aborts. */ | |
6667 | mask = CPSR_A | CPSR_I; | |
6668 | offset = 4; | |
de38d23b FA |
6669 | if (env->cp15.scr_el3 & SCR_IRQ) { |
6670 | /* IRQ routed to monitor mode */ | |
6671 | new_mode = ARM_CPU_MODE_MON; | |
6672 | mask |= CPSR_F; | |
6673 | } | |
b5ff1b31 FB |
6674 | break; |
6675 | case EXCP_FIQ: | |
6676 | new_mode = ARM_CPU_MODE_FIQ; | |
6677 | addr = 0x1c; | |
6678 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
6679 | mask = CPSR_A | CPSR_I | CPSR_F; | |
de38d23b FA |
6680 | if (env->cp15.scr_el3 & SCR_FIQ) { |
6681 | /* FIQ routed to monitor mode */ | |
6682 | new_mode = ARM_CPU_MODE_MON; | |
6683 | } | |
b5ff1b31 FB |
6684 | offset = 4; |
6685 | break; | |
87a4b270 PM |
6686 | case EXCP_VIRQ: |
6687 | new_mode = ARM_CPU_MODE_IRQ; | |
6688 | addr = 0x18; | |
6689 | /* Disable IRQ and imprecise data aborts. */ | |
6690 | mask = CPSR_A | CPSR_I; | |
6691 | offset = 4; | |
6692 | break; | |
6693 | case EXCP_VFIQ: | |
6694 | new_mode = ARM_CPU_MODE_FIQ; | |
6695 | addr = 0x1c; | |
6696 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
6697 | mask = CPSR_A | CPSR_I | CPSR_F; | |
6698 | offset = 4; | |
6699 | break; | |
dbe9d163 FA |
6700 | case EXCP_SMC: |
6701 | new_mode = ARM_CPU_MODE_MON; | |
6702 | addr = 0x08; | |
6703 | mask = CPSR_A | CPSR_I | CPSR_F; | |
6704 | offset = 0; | |
6705 | break; | |
b5ff1b31 | 6706 | default: |
a47dddd7 | 6707 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
b5ff1b31 FB |
6708 | return; /* Never happens. Keep compiler happy. */ |
6709 | } | |
e89e51a1 FA |
6710 | |
6711 | if (new_mode == ARM_CPU_MODE_MON) { | |
6712 | addr += env->cp15.mvbar; | |
137feaa9 | 6713 | } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { |
e89e51a1 | 6714 | /* High vectors. When enabled, base address cannot be remapped. */ |
b5ff1b31 | 6715 | addr += 0xffff0000; |
8641136c NR |
6716 | } else { |
6717 | /* ARM v7 architectures provide a vector base address register to remap | |
6718 | * the interrupt vector table. | |
e89e51a1 | 6719 | * This register is only followed in non-monitor mode, and is banked. |
8641136c NR |
6720 | * Note: only bits 31:5 are valid. |
6721 | */ | |
fb6c91ba | 6722 | addr += A32_BANKED_CURRENT_REG_GET(env, vbar); |
b5ff1b31 | 6723 | } |
dbe9d163 FA |
6724 | |
6725 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
6726 | env->cp15.scr_el3 &= ~SCR_NS; | |
6727 | } | |
6728 | ||
b5ff1b31 | 6729 | switch_mode (env, new_mode); |
662cefb7 PM |
6730 | /* For exceptions taken to AArch32 we must clear the SS bit in both |
6731 | * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. | |
6732 | */ | |
6733 | env->uncached_cpsr &= ~PSTATE_SS; | |
b5ff1b31 | 6734 | env->spsr = cpsr_read(env); |
9ee6e8bb PB |
6735 | /* Clear IT bits. */ |
6736 | env->condexec_bits = 0; | |
30a8cac1 | 6737 | /* Switch to the new mode, and to the correct instruction set. */ |
6d7e6326 | 6738 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; |
73462ddd PC |
6739 | /* Set new mode endianness */ |
6740 | env->uncached_cpsr &= ~CPSR_E; | |
6741 | if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { | |
3823b9db | 6742 | env->uncached_cpsr |= CPSR_E; |
73462ddd | 6743 | } |
4cc35614 | 6744 | env->daif |= mask; |
be5e7a76 DES |
6745 | /* this is a lie, as the was no c1_sys on V4T/V5, but who cares |
6746 | * and we should just guard the thumb mode on V4 */ | |
6747 | if (arm_feature(env, ARM_FEATURE_V4T)) { | |
137feaa9 | 6748 | env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; |
be5e7a76 | 6749 | } |
b5ff1b31 FB |
6750 | env->regs[14] = env->regs[15] + offset; |
6751 | env->regs[15] = addr; | |
b5ff1b31 FB |
6752 | } |
6753 | ||
966f758c PM |
6754 | /* Handle exception entry to a target EL which is using AArch64 */ |
6755 | static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | |
f3a9b694 PM |
6756 | { |
6757 | ARMCPU *cpu = ARM_CPU(cs); | |
6758 | CPUARMState *env = &cpu->env; | |
6759 | unsigned int new_el = env->exception.target_el; | |
6760 | target_ulong addr = env->cp15.vbar_el[new_el]; | |
6761 | unsigned int new_mode = aarch64_pstate_mode(new_el, true); | |
6762 | ||
6763 | if (arm_current_el(env) < new_el) { | |
3d6f7617 PM |
6764 | /* Entry vector offset depends on whether the implemented EL |
6765 | * immediately lower than the target level is using AArch32 or AArch64 | |
6766 | */ | |
6767 | bool is_aa64; | |
6768 | ||
6769 | switch (new_el) { | |
6770 | case 3: | |
6771 | is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; | |
6772 | break; | |
6773 | case 2: | |
6774 | is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0; | |
6775 | break; | |
6776 | case 1: | |
6777 | is_aa64 = is_a64(env); | |
6778 | break; | |
6779 | default: | |
6780 | g_assert_not_reached(); | |
6781 | } | |
6782 | ||
6783 | if (is_aa64) { | |
f3a9b694 PM |
6784 | addr += 0x400; |
6785 | } else { | |
6786 | addr += 0x600; | |
6787 | } | |
6788 | } else if (pstate_read(env) & PSTATE_SP) { | |
6789 | addr += 0x200; | |
6790 | } | |
6791 | ||
f3a9b694 PM |
6792 | switch (cs->exception_index) { |
6793 | case EXCP_PREFETCH_ABORT: | |
6794 | case EXCP_DATA_ABORT: | |
6795 | env->cp15.far_el[new_el] = env->exception.vaddress; | |
6796 | qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", | |
6797 | env->cp15.far_el[new_el]); | |
6798 | /* fall through */ | |
6799 | case EXCP_BKPT: | |
6800 | case EXCP_UDEF: | |
6801 | case EXCP_SWI: | |
6802 | case EXCP_HVC: | |
6803 | case EXCP_HYP_TRAP: | |
6804 | case EXCP_SMC: | |
6805 | env->cp15.esr_el[new_el] = env->exception.syndrome; | |
6806 | break; | |
6807 | case EXCP_IRQ: | |
6808 | case EXCP_VIRQ: | |
6809 | addr += 0x80; | |
6810 | break; | |
6811 | case EXCP_FIQ: | |
6812 | case EXCP_VFIQ: | |
6813 | addr += 0x100; | |
6814 | break; | |
6815 | case EXCP_SEMIHOST: | |
6816 | qemu_log_mask(CPU_LOG_INT, | |
6817 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
6818 | env->xregs[0]); | |
6819 | env->xregs[0] = do_arm_semihosting(env); | |
6820 | return; | |
6821 | default: | |
6822 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
6823 | } | |
6824 | ||
6825 | if (is_a64(env)) { | |
6826 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env); | |
6827 | aarch64_save_sp(env, arm_current_el(env)); | |
6828 | env->elr_el[new_el] = env->pc; | |
6829 | } else { | |
6830 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env); | |
f3a9b694 PM |
6831 | env->elr_el[new_el] = env->regs[15]; |
6832 | ||
6833 | aarch64_sync_32_to_64(env); | |
6834 | ||
6835 | env->condexec_bits = 0; | |
6836 | } | |
6837 | qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", | |
6838 | env->elr_el[new_el]); | |
6839 | ||
6840 | pstate_write(env, PSTATE_DAIF | new_mode); | |
6841 | env->aarch64 = 1; | |
6842 | aarch64_restore_sp(env, new_el); | |
6843 | ||
6844 | env->pc = addr; | |
6845 | ||
6846 | qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", | |
6847 | new_el, env->pc, pstate_read(env)); | |
966f758c PM |
6848 | } |
6849 | ||
904c04de PM |
6850 | static inline bool check_for_semihosting(CPUState *cs) |
6851 | { | |
6852 | /* Check whether this exception is a semihosting call; if so | |
6853 | * then handle it and return true; otherwise return false. | |
6854 | */ | |
6855 | ARMCPU *cpu = ARM_CPU(cs); | |
6856 | CPUARMState *env = &cpu->env; | |
6857 | ||
6858 | if (is_a64(env)) { | |
6859 | if (cs->exception_index == EXCP_SEMIHOST) { | |
6860 | /* This is always the 64-bit semihosting exception. | |
6861 | * The "is this usermode" and "is semihosting enabled" | |
6862 | * checks have been done at translate time. | |
6863 | */ | |
6864 | qemu_log_mask(CPU_LOG_INT, | |
6865 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
6866 | env->xregs[0]); | |
6867 | env->xregs[0] = do_arm_semihosting(env); | |
6868 | return true; | |
6869 | } | |
6870 | return false; | |
6871 | } else { | |
6872 | uint32_t imm; | |
6873 | ||
6874 | /* Only intercept calls from privileged modes, to provide some | |
6875 | * semblance of security. | |
6876 | */ | |
19a6e31c PM |
6877 | if (cs->exception_index != EXCP_SEMIHOST && |
6878 | (!semihosting_enabled() || | |
6879 | ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) { | |
904c04de PM |
6880 | return false; |
6881 | } | |
6882 | ||
6883 | switch (cs->exception_index) { | |
19a6e31c PM |
6884 | case EXCP_SEMIHOST: |
6885 | /* This is always a semihosting call; the "is this usermode" | |
6886 | * and "is semihosting enabled" checks have been done at | |
6887 | * translate time. | |
6888 | */ | |
6889 | break; | |
904c04de PM |
6890 | case EXCP_SWI: |
6891 | /* Check for semihosting interrupt. */ | |
6892 | if (env->thumb) { | |
f9fd40eb | 6893 | imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env)) |
904c04de PM |
6894 | & 0xff; |
6895 | if (imm == 0xab) { | |
6896 | break; | |
6897 | } | |
6898 | } else { | |
f9fd40eb | 6899 | imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env)) |
904c04de PM |
6900 | & 0xffffff; |
6901 | if (imm == 0x123456) { | |
6902 | break; | |
6903 | } | |
6904 | } | |
6905 | return false; | |
6906 | case EXCP_BKPT: | |
6907 | /* See if this is a semihosting syscall. */ | |
6908 | if (env->thumb) { | |
f9fd40eb | 6909 | imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) |
904c04de PM |
6910 | & 0xff; |
6911 | if (imm == 0xab) { | |
6912 | env->regs[15] += 2; | |
6913 | break; | |
6914 | } | |
6915 | } | |
6916 | return false; | |
6917 | default: | |
6918 | return false; | |
6919 | } | |
6920 | ||
6921 | qemu_log_mask(CPU_LOG_INT, | |
6922 | "...handling as semihosting call 0x%x\n", | |
6923 | env->regs[0]); | |
6924 | env->regs[0] = do_arm_semihosting(env); | |
6925 | return true; | |
6926 | } | |
6927 | } | |
6928 | ||
966f758c PM |
6929 | /* Handle a CPU exception for A and R profile CPUs. |
6930 | * Do any appropriate logging, handle PSCI calls, and then hand off | |
6931 | * to the AArch64-entry or AArch32-entry function depending on the | |
6932 | * target exception level's register width. | |
6933 | */ | |
6934 | void arm_cpu_do_interrupt(CPUState *cs) | |
6935 | { | |
6936 | ARMCPU *cpu = ARM_CPU(cs); | |
6937 | CPUARMState *env = &cpu->env; | |
6938 | unsigned int new_el = env->exception.target_el; | |
6939 | ||
531c60a9 | 6940 | assert(!arm_feature(env, ARM_FEATURE_M)); |
966f758c PM |
6941 | |
6942 | arm_log_exception(cs->exception_index); | |
6943 | qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), | |
6944 | new_el); | |
6945 | if (qemu_loglevel_mask(CPU_LOG_INT) | |
6946 | && !excp_is_internal(cs->exception_index)) { | |
6568da45 | 6947 | qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", |
966f758c PM |
6948 | env->exception.syndrome >> ARM_EL_EC_SHIFT, |
6949 | env->exception.syndrome); | |
6950 | } | |
6951 | ||
6952 | if (arm_is_psci_call(cpu, cs->exception_index)) { | |
6953 | arm_handle_psci_call(cpu); | |
6954 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | |
6955 | return; | |
6956 | } | |
6957 | ||
904c04de PM |
6958 | /* Semihosting semantics depend on the register width of the |
6959 | * code that caused the exception, not the target exception level, | |
6960 | * so must be handled here. | |
966f758c | 6961 | */ |
904c04de PM |
6962 | if (check_for_semihosting(cs)) { |
6963 | return; | |
6964 | } | |
6965 | ||
6966 | assert(!excp_is_internal(cs->exception_index)); | |
6967 | if (arm_el_is_aa64(env, new_el)) { | |
966f758c PM |
6968 | arm_cpu_do_interrupt_aarch64(cs); |
6969 | } else { | |
6970 | arm_cpu_do_interrupt_aarch32(cs); | |
6971 | } | |
f3a9b694 | 6972 | |
8d04fb55 JK |
6973 | /* Hooks may change global state so BQL should be held, also the |
6974 | * BQL needs to be held for any modification of | |
6975 | * cs->interrupt_request. | |
6976 | */ | |
6977 | g_assert(qemu_mutex_iothread_locked()); | |
6978 | ||
bd7d00fc PM |
6979 | arm_call_el_change_hook(cpu); |
6980 | ||
f3a9b694 PM |
6981 | if (!kvm_enabled()) { |
6982 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
6983 | } | |
6984 | } | |
0480f69a PM |
6985 | |
6986 | /* Return the exception level which controls this address translation regime */ | |
6987 | static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) | |
6988 | { | |
6989 | switch (mmu_idx) { | |
6990 | case ARMMMUIdx_S2NS: | |
6991 | case ARMMMUIdx_S1E2: | |
6992 | return 2; | |
6993 | case ARMMMUIdx_S1E3: | |
6994 | return 3; | |
6995 | case ARMMMUIdx_S1SE0: | |
6996 | return arm_el_is_aa64(env, 3) ? 1 : 3; | |
6997 | case ARMMMUIdx_S1SE1: | |
6998 | case ARMMMUIdx_S1NSE0: | |
6999 | case ARMMMUIdx_S1NSE1: | |
e7b921c2 PM |
7000 | case ARMMMUIdx_MPriv: |
7001 | case ARMMMUIdx_MUser: | |
0480f69a PM |
7002 | return 1; |
7003 | default: | |
7004 | g_assert_not_reached(); | |
7005 | } | |
7006 | } | |
7007 | ||
8bf5b6a9 PM |
7008 | /* Return true if this address translation regime is secure */ |
7009 | static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) | |
7010 | { | |
7011 | switch (mmu_idx) { | |
7012 | case ARMMMUIdx_S12NSE0: | |
7013 | case ARMMMUIdx_S12NSE1: | |
7014 | case ARMMMUIdx_S1NSE0: | |
7015 | case ARMMMUIdx_S1NSE1: | |
7016 | case ARMMMUIdx_S1E2: | |
7017 | case ARMMMUIdx_S2NS: | |
e7b921c2 PM |
7018 | case ARMMMUIdx_MPriv: |
7019 | case ARMMMUIdx_MUser: | |
8bf5b6a9 PM |
7020 | return false; |
7021 | case ARMMMUIdx_S1E3: | |
7022 | case ARMMMUIdx_S1SE0: | |
7023 | case ARMMMUIdx_S1SE1: | |
7024 | return true; | |
7025 | default: | |
7026 | g_assert_not_reached(); | |
7027 | } | |
7028 | } | |
7029 | ||
0480f69a PM |
7030 | /* Return the SCTLR value which controls this address translation regime */ |
7031 | static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) | |
7032 | { | |
7033 | return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; | |
7034 | } | |
7035 | ||
7036 | /* Return true if the specified stage of address translation is disabled */ | |
7037 | static inline bool regime_translation_disabled(CPUARMState *env, | |
7038 | ARMMMUIdx mmu_idx) | |
7039 | { | |
7040 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
7041 | return (env->cp15.hcr_el2 & HCR_VM) == 0; | |
7042 | } | |
7043 | return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; | |
7044 | } | |
7045 | ||
73462ddd PC |
7046 | static inline bool regime_translation_big_endian(CPUARMState *env, |
7047 | ARMMMUIdx mmu_idx) | |
7048 | { | |
7049 | return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; | |
7050 | } | |
7051 | ||
0480f69a PM |
7052 | /* Return the TCR controlling this translation regime */ |
7053 | static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) | |
7054 | { | |
7055 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
68e9c2fe | 7056 | return &env->cp15.vtcr_el2; |
0480f69a PM |
7057 | } |
7058 | return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; | |
7059 | } | |
7060 | ||
8bd5c820 PM |
7061 | /* Convert a possible stage1+2 MMU index into the appropriate |
7062 | * stage 1 MMU index | |
7063 | */ | |
7064 | static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) | |
7065 | { | |
7066 | if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { | |
7067 | mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0); | |
7068 | } | |
7069 | return mmu_idx; | |
7070 | } | |
7071 | ||
86fb3fa4 TH |
7072 | /* Returns TBI0 value for current regime el */ |
7073 | uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) | |
7074 | { | |
7075 | TCR *tcr; | |
7076 | uint32_t el; | |
7077 | ||
7078 | /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert | |
8bd5c820 PM |
7079 | * a stage 1+2 mmu index into the appropriate stage 1 mmu index. |
7080 | */ | |
7081 | mmu_idx = stage_1_mmu_idx(mmu_idx); | |
86fb3fa4 TH |
7082 | |
7083 | tcr = regime_tcr(env, mmu_idx); | |
7084 | el = regime_el(env, mmu_idx); | |
7085 | ||
7086 | if (el > 1) { | |
7087 | return extract64(tcr->raw_tcr, 20, 1); | |
7088 | } else { | |
7089 | return extract64(tcr->raw_tcr, 37, 1); | |
7090 | } | |
7091 | } | |
7092 | ||
7093 | /* Returns TBI1 value for current regime el */ | |
7094 | uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) | |
7095 | { | |
7096 | TCR *tcr; | |
7097 | uint32_t el; | |
7098 | ||
7099 | /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert | |
8bd5c820 PM |
7100 | * a stage 1+2 mmu index into the appropriate stage 1 mmu index. |
7101 | */ | |
7102 | mmu_idx = stage_1_mmu_idx(mmu_idx); | |
86fb3fa4 TH |
7103 | |
7104 | tcr = regime_tcr(env, mmu_idx); | |
7105 | el = regime_el(env, mmu_idx); | |
7106 | ||
7107 | if (el > 1) { | |
7108 | return 0; | |
7109 | } else { | |
7110 | return extract64(tcr->raw_tcr, 38, 1); | |
7111 | } | |
7112 | } | |
7113 | ||
aef878be GB |
7114 | /* Return the TTBR associated with this translation regime */ |
7115 | static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, | |
7116 | int ttbrn) | |
7117 | { | |
7118 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
b698e9cf | 7119 | return env->cp15.vttbr_el2; |
aef878be GB |
7120 | } |
7121 | if (ttbrn == 0) { | |
7122 | return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; | |
7123 | } else { | |
7124 | return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; | |
7125 | } | |
7126 | } | |
7127 | ||
0480f69a PM |
7128 | /* Return true if the translation regime is using LPAE format page tables */ |
7129 | static inline bool regime_using_lpae_format(CPUARMState *env, | |
7130 | ARMMMUIdx mmu_idx) | |
7131 | { | |
7132 | int el = regime_el(env, mmu_idx); | |
7133 | if (el == 2 || arm_el_is_aa64(env, el)) { | |
7134 | return true; | |
7135 | } | |
7136 | if (arm_feature(env, ARM_FEATURE_LPAE) | |
7137 | && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { | |
7138 | return true; | |
7139 | } | |
7140 | return false; | |
7141 | } | |
7142 | ||
deb2db99 AR |
7143 | /* Returns true if the stage 1 translation regime is using LPAE format page |
7144 | * tables. Used when raising alignment exceptions, whose FSR changes depending | |
7145 | * on whether the long or short descriptor format is in use. */ | |
7146 | bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) | |
30901475 | 7147 | { |
8bd5c820 | 7148 | mmu_idx = stage_1_mmu_idx(mmu_idx); |
deb2db99 | 7149 | |
30901475 AB |
7150 | return regime_using_lpae_format(env, mmu_idx); |
7151 | } | |
7152 | ||
0480f69a PM |
7153 | static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) |
7154 | { | |
7155 | switch (mmu_idx) { | |
7156 | case ARMMMUIdx_S1SE0: | |
7157 | case ARMMMUIdx_S1NSE0: | |
e7b921c2 | 7158 | case ARMMMUIdx_MUser: |
0480f69a PM |
7159 | return true; |
7160 | default: | |
7161 | return false; | |
7162 | case ARMMMUIdx_S12NSE0: | |
7163 | case ARMMMUIdx_S12NSE1: | |
7164 | g_assert_not_reached(); | |
7165 | } | |
7166 | } | |
7167 | ||
0fbf5238 AJ |
7168 | /* Translate section/page access permissions to page |
7169 | * R/W protection flags | |
d76951b6 AJ |
7170 | * |
7171 | * @env: CPUARMState | |
7172 | * @mmu_idx: MMU index indicating required translation regime | |
7173 | * @ap: The 3-bit access permissions (AP[2:0]) | |
7174 | * @domain_prot: The 2-bit domain access permissions | |
0fbf5238 AJ |
7175 | */ |
7176 | static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, | |
7177 | int ap, int domain_prot) | |
7178 | { | |
554b0b09 PM |
7179 | bool is_user = regime_is_user(env, mmu_idx); |
7180 | ||
7181 | if (domain_prot == 3) { | |
7182 | return PAGE_READ | PAGE_WRITE; | |
7183 | } | |
7184 | ||
554b0b09 PM |
7185 | switch (ap) { |
7186 | case 0: | |
7187 | if (arm_feature(env, ARM_FEATURE_V7)) { | |
7188 | return 0; | |
7189 | } | |
554b0b09 PM |
7190 | switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) { |
7191 | case SCTLR_S: | |
7192 | return is_user ? 0 : PAGE_READ; | |
7193 | case SCTLR_R: | |
7194 | return PAGE_READ; | |
7195 | default: | |
7196 | return 0; | |
7197 | } | |
7198 | case 1: | |
7199 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
7200 | case 2: | |
87c3d486 | 7201 | if (is_user) { |
0fbf5238 | 7202 | return PAGE_READ; |
87c3d486 | 7203 | } else { |
554b0b09 | 7204 | return PAGE_READ | PAGE_WRITE; |
87c3d486 | 7205 | } |
554b0b09 PM |
7206 | case 3: |
7207 | return PAGE_READ | PAGE_WRITE; | |
7208 | case 4: /* Reserved. */ | |
7209 | return 0; | |
7210 | case 5: | |
0fbf5238 | 7211 | return is_user ? 0 : PAGE_READ; |
554b0b09 | 7212 | case 6: |
0fbf5238 | 7213 | return PAGE_READ; |
554b0b09 | 7214 | case 7: |
87c3d486 | 7215 | if (!arm_feature(env, ARM_FEATURE_V6K)) { |
554b0b09 | 7216 | return 0; |
87c3d486 | 7217 | } |
0fbf5238 | 7218 | return PAGE_READ; |
554b0b09 | 7219 | default: |
0fbf5238 | 7220 | g_assert_not_reached(); |
554b0b09 | 7221 | } |
b5ff1b31 FB |
7222 | } |
7223 | ||
d76951b6 AJ |
7224 | /* Translate section/page access permissions to page |
7225 | * R/W protection flags. | |
7226 | * | |
d76951b6 | 7227 | * @ap: The 2-bit simple AP (AP[2:1]) |
d8e052b3 | 7228 | * @is_user: TRUE if accessing from PL0 |
d76951b6 | 7229 | */ |
d8e052b3 | 7230 | static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user) |
d76951b6 | 7231 | { |
d76951b6 AJ |
7232 | switch (ap) { |
7233 | case 0: | |
7234 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
7235 | case 1: | |
7236 | return PAGE_READ | PAGE_WRITE; | |
7237 | case 2: | |
7238 | return is_user ? 0 : PAGE_READ; | |
7239 | case 3: | |
7240 | return PAGE_READ; | |
7241 | default: | |
7242 | g_assert_not_reached(); | |
7243 | } | |
7244 | } | |
7245 | ||
d8e052b3 AJ |
7246 | static inline int |
7247 | simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) | |
7248 | { | |
7249 | return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); | |
7250 | } | |
7251 | ||
6ab1a5ee EI |
7252 | /* Translate S2 section/page access permissions to protection flags |
7253 | * | |
7254 | * @env: CPUARMState | |
7255 | * @s2ap: The 2-bit stage2 access permissions (S2AP) | |
7256 | * @xn: XN (execute-never) bit | |
7257 | */ | |
7258 | static int get_S2prot(CPUARMState *env, int s2ap, int xn) | |
7259 | { | |
7260 | int prot = 0; | |
7261 | ||
7262 | if (s2ap & 1) { | |
7263 | prot |= PAGE_READ; | |
7264 | } | |
7265 | if (s2ap & 2) { | |
7266 | prot |= PAGE_WRITE; | |
7267 | } | |
7268 | if (!xn) { | |
dfda6837 SS |
7269 | if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { |
7270 | prot |= PAGE_EXEC; | |
7271 | } | |
6ab1a5ee EI |
7272 | } |
7273 | return prot; | |
7274 | } | |
7275 | ||
d8e052b3 AJ |
7276 | /* Translate section/page access permissions to protection flags |
7277 | * | |
7278 | * @env: CPUARMState | |
7279 | * @mmu_idx: MMU index indicating required translation regime | |
7280 | * @is_aa64: TRUE if AArch64 | |
7281 | * @ap: The 2-bit simple AP (AP[2:1]) | |
7282 | * @ns: NS (non-secure) bit | |
7283 | * @xn: XN (execute-never) bit | |
7284 | * @pxn: PXN (privileged execute-never) bit | |
7285 | */ | |
7286 | static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, | |
7287 | int ap, int ns, int xn, int pxn) | |
7288 | { | |
7289 | bool is_user = regime_is_user(env, mmu_idx); | |
7290 | int prot_rw, user_rw; | |
7291 | bool have_wxn; | |
7292 | int wxn = 0; | |
7293 | ||
7294 | assert(mmu_idx != ARMMMUIdx_S2NS); | |
7295 | ||
7296 | user_rw = simple_ap_to_rw_prot_is_user(ap, true); | |
7297 | if (is_user) { | |
7298 | prot_rw = user_rw; | |
7299 | } else { | |
7300 | prot_rw = simple_ap_to_rw_prot_is_user(ap, false); | |
7301 | } | |
7302 | ||
7303 | if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { | |
7304 | return prot_rw; | |
7305 | } | |
7306 | ||
7307 | /* TODO have_wxn should be replaced with | |
7308 | * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) | |
7309 | * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE | |
7310 | * compatible processors have EL2, which is required for [U]WXN. | |
7311 | */ | |
7312 | have_wxn = arm_feature(env, ARM_FEATURE_LPAE); | |
7313 | ||
7314 | if (have_wxn) { | |
7315 | wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN; | |
7316 | } | |
7317 | ||
7318 | if (is_aa64) { | |
7319 | switch (regime_el(env, mmu_idx)) { | |
7320 | case 1: | |
7321 | if (!is_user) { | |
7322 | xn = pxn || (user_rw & PAGE_WRITE); | |
7323 | } | |
7324 | break; | |
7325 | case 2: | |
7326 | case 3: | |
7327 | break; | |
7328 | } | |
7329 | } else if (arm_feature(env, ARM_FEATURE_V7)) { | |
7330 | switch (regime_el(env, mmu_idx)) { | |
7331 | case 1: | |
7332 | case 3: | |
7333 | if (is_user) { | |
7334 | xn = xn || !(user_rw & PAGE_READ); | |
7335 | } else { | |
7336 | int uwxn = 0; | |
7337 | if (have_wxn) { | |
7338 | uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN; | |
7339 | } | |
7340 | xn = xn || !(prot_rw & PAGE_READ) || pxn || | |
7341 | (uwxn && (user_rw & PAGE_WRITE)); | |
7342 | } | |
7343 | break; | |
7344 | case 2: | |
7345 | break; | |
7346 | } | |
7347 | } else { | |
7348 | xn = wxn = 0; | |
7349 | } | |
7350 | ||
7351 | if (xn || (wxn && (prot_rw & PAGE_WRITE))) { | |
7352 | return prot_rw; | |
7353 | } | |
7354 | return prot_rw | PAGE_EXEC; | |
7355 | } | |
7356 | ||
0480f69a PM |
7357 | static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, |
7358 | uint32_t *table, uint32_t address) | |
b2fa1797 | 7359 | { |
0480f69a | 7360 | /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ |
0480f69a | 7361 | TCR *tcr = regime_tcr(env, mmu_idx); |
11f136ee | 7362 | |
11f136ee FA |
7363 | if (address & tcr->mask) { |
7364 | if (tcr->raw_tcr & TTBCR_PD1) { | |
e389be16 FA |
7365 | /* Translation table walk disabled for TTBR1 */ |
7366 | return false; | |
7367 | } | |
aef878be | 7368 | *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; |
e389be16 | 7369 | } else { |
11f136ee | 7370 | if (tcr->raw_tcr & TTBCR_PD0) { |
e389be16 FA |
7371 | /* Translation table walk disabled for TTBR0 */ |
7372 | return false; | |
7373 | } | |
aef878be | 7374 | *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; |
e389be16 FA |
7375 | } |
7376 | *table |= (address >> 18) & 0x3ffc; | |
7377 | return true; | |
b2fa1797 PB |
7378 | } |
7379 | ||
37785977 EI |
7380 | /* Translate a S1 pagetable walk through S2 if needed. */ |
7381 | static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, | |
7382 | hwaddr addr, MemTxAttrs txattrs, | |
7383 | uint32_t *fsr, | |
7384 | ARMMMUFaultInfo *fi) | |
7385 | { | |
7386 | if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) && | |
7387 | !regime_translation_disabled(env, ARMMMUIdx_S2NS)) { | |
7388 | target_ulong s2size; | |
7389 | hwaddr s2pa; | |
7390 | int s2prot; | |
7391 | int ret; | |
7392 | ||
7393 | ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, | |
7394 | &txattrs, &s2prot, &s2size, fsr, fi); | |
7395 | if (ret) { | |
7396 | fi->s2addr = addr; | |
7397 | fi->stage2 = true; | |
7398 | fi->s1ptw = true; | |
7399 | return ~0; | |
7400 | } | |
7401 | addr = s2pa; | |
7402 | } | |
7403 | return addr; | |
7404 | } | |
7405 | ||
ebca90e4 PM |
7406 | /* All loads done in the course of a page table walk go through here. |
7407 | * TODO: rather than ignoring errors from physical memory reads (which | |
7408 | * are external aborts in ARM terminology) we should propagate this | |
7409 | * error out so that we can turn it into a Data Abort if this walk | |
7410 | * was being done for a CPU load/store or an address translation instruction | |
7411 | * (but not if it was for a debug access). | |
7412 | */ | |
a614e698 EI |
7413 | static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, |
7414 | ARMMMUIdx mmu_idx, uint32_t *fsr, | |
7415 | ARMMMUFaultInfo *fi) | |
ebca90e4 | 7416 | { |
a614e698 EI |
7417 | ARMCPU *cpu = ARM_CPU(cs); |
7418 | CPUARMState *env = &cpu->env; | |
ebca90e4 | 7419 | MemTxAttrs attrs = {}; |
5ce4ff65 | 7420 | AddressSpace *as; |
ebca90e4 PM |
7421 | |
7422 | attrs.secure = is_secure; | |
5ce4ff65 | 7423 | as = arm_addressspace(cs, attrs); |
a614e698 EI |
7424 | addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); |
7425 | if (fi->s1ptw) { | |
7426 | return 0; | |
7427 | } | |
73462ddd PC |
7428 | if (regime_translation_big_endian(env, mmu_idx)) { |
7429 | return address_space_ldl_be(as, addr, attrs, NULL); | |
7430 | } else { | |
7431 | return address_space_ldl_le(as, addr, attrs, NULL); | |
7432 | } | |
ebca90e4 PM |
7433 | } |
7434 | ||
37785977 EI |
7435 | static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, |
7436 | ARMMMUIdx mmu_idx, uint32_t *fsr, | |
7437 | ARMMMUFaultInfo *fi) | |
ebca90e4 | 7438 | { |
37785977 EI |
7439 | ARMCPU *cpu = ARM_CPU(cs); |
7440 | CPUARMState *env = &cpu->env; | |
ebca90e4 | 7441 | MemTxAttrs attrs = {}; |
5ce4ff65 | 7442 | AddressSpace *as; |
ebca90e4 PM |
7443 | |
7444 | attrs.secure = is_secure; | |
5ce4ff65 | 7445 | as = arm_addressspace(cs, attrs); |
37785977 EI |
7446 | addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); |
7447 | if (fi->s1ptw) { | |
7448 | return 0; | |
7449 | } | |
73462ddd PC |
7450 | if (regime_translation_big_endian(env, mmu_idx)) { |
7451 | return address_space_ldq_be(as, addr, attrs, NULL); | |
7452 | } else { | |
7453 | return address_space_ldq_le(as, addr, attrs, NULL); | |
7454 | } | |
ebca90e4 PM |
7455 | } |
7456 | ||
b7cc4e82 PC |
7457 | static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, |
7458 | int access_type, ARMMMUIdx mmu_idx, | |
7459 | hwaddr *phys_ptr, int *prot, | |
e14b5a23 EI |
7460 | target_ulong *page_size, uint32_t *fsr, |
7461 | ARMMMUFaultInfo *fi) | |
b5ff1b31 | 7462 | { |
70d74660 | 7463 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
b5ff1b31 FB |
7464 | int code; |
7465 | uint32_t table; | |
7466 | uint32_t desc; | |
7467 | int type; | |
7468 | int ap; | |
e389be16 | 7469 | int domain = 0; |
dd4ebc2e | 7470 | int domain_prot; |
a8170e5e | 7471 | hwaddr phys_addr; |
0480f69a | 7472 | uint32_t dacr; |
b5ff1b31 | 7473 | |
9ee6e8bb PB |
7474 | /* Pagetable walk. */ |
7475 | /* Lookup l1 descriptor. */ | |
0480f69a | 7476 | if (!get_level1_table_address(env, mmu_idx, &table, address)) { |
e389be16 FA |
7477 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ |
7478 | code = 5; | |
7479 | goto do_fault; | |
7480 | } | |
a614e698 EI |
7481 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
7482 | mmu_idx, fsr, fi); | |
9ee6e8bb | 7483 | type = (desc & 3); |
dd4ebc2e | 7484 | domain = (desc >> 5) & 0x0f; |
0480f69a PM |
7485 | if (regime_el(env, mmu_idx) == 1) { |
7486 | dacr = env->cp15.dacr_ns; | |
7487 | } else { | |
7488 | dacr = env->cp15.dacr_s; | |
7489 | } | |
7490 | domain_prot = (dacr >> (domain * 2)) & 3; | |
9ee6e8bb | 7491 | if (type == 0) { |
601d70b9 | 7492 | /* Section translation fault. */ |
9ee6e8bb PB |
7493 | code = 5; |
7494 | goto do_fault; | |
7495 | } | |
dd4ebc2e | 7496 | if (domain_prot == 0 || domain_prot == 2) { |
9ee6e8bb PB |
7497 | if (type == 2) |
7498 | code = 9; /* Section domain fault. */ | |
7499 | else | |
7500 | code = 11; /* Page domain fault. */ | |
7501 | goto do_fault; | |
7502 | } | |
7503 | if (type == 2) { | |
7504 | /* 1Mb section. */ | |
7505 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
7506 | ap = (desc >> 10) & 3; | |
7507 | code = 13; | |
d4c430a8 | 7508 | *page_size = 1024 * 1024; |
9ee6e8bb PB |
7509 | } else { |
7510 | /* Lookup l2 entry. */ | |
554b0b09 PM |
7511 | if (type == 1) { |
7512 | /* Coarse pagetable. */ | |
7513 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
7514 | } else { | |
7515 | /* Fine pagetable. */ | |
7516 | table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); | |
7517 | } | |
a614e698 EI |
7518 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
7519 | mmu_idx, fsr, fi); | |
9ee6e8bb PB |
7520 | switch (desc & 3) { |
7521 | case 0: /* Page translation fault. */ | |
7522 | code = 7; | |
7523 | goto do_fault; | |
7524 | case 1: /* 64k page. */ | |
7525 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
7526 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
d4c430a8 | 7527 | *page_size = 0x10000; |
ce819861 | 7528 | break; |
9ee6e8bb PB |
7529 | case 2: /* 4k page. */ |
7530 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
c10f7fc3 | 7531 | ap = (desc >> (4 + ((address >> 9) & 6))) & 3; |
d4c430a8 | 7532 | *page_size = 0x1000; |
ce819861 | 7533 | break; |
fc1891c7 | 7534 | case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ |
554b0b09 | 7535 | if (type == 1) { |
fc1891c7 PM |
7536 | /* ARMv6/XScale extended small page format */ |
7537 | if (arm_feature(env, ARM_FEATURE_XSCALE) | |
7538 | || arm_feature(env, ARM_FEATURE_V6)) { | |
554b0b09 | 7539 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
fc1891c7 | 7540 | *page_size = 0x1000; |
554b0b09 | 7541 | } else { |
fc1891c7 PM |
7542 | /* UNPREDICTABLE in ARMv5; we choose to take a |
7543 | * page translation fault. | |
7544 | */ | |
554b0b09 PM |
7545 | code = 7; |
7546 | goto do_fault; | |
7547 | } | |
7548 | } else { | |
7549 | phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); | |
fc1891c7 | 7550 | *page_size = 0x400; |
554b0b09 | 7551 | } |
9ee6e8bb | 7552 | ap = (desc >> 4) & 3; |
ce819861 PB |
7553 | break; |
7554 | default: | |
9ee6e8bb PB |
7555 | /* Never happens, but compiler isn't smart enough to tell. */ |
7556 | abort(); | |
ce819861 | 7557 | } |
9ee6e8bb PB |
7558 | code = 15; |
7559 | } | |
0fbf5238 AJ |
7560 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); |
7561 | *prot |= *prot ? PAGE_EXEC : 0; | |
7562 | if (!(*prot & (1 << access_type))) { | |
9ee6e8bb PB |
7563 | /* Access permission fault. */ |
7564 | goto do_fault; | |
7565 | } | |
7566 | *phys_ptr = phys_addr; | |
b7cc4e82 | 7567 | return false; |
9ee6e8bb | 7568 | do_fault: |
b7cc4e82 PC |
7569 | *fsr = code | (domain << 4); |
7570 | return true; | |
9ee6e8bb PB |
7571 | } |
7572 | ||
b7cc4e82 PC |
7573 | static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, |
7574 | int access_type, ARMMMUIdx mmu_idx, | |
7575 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, | |
e14b5a23 EI |
7576 | target_ulong *page_size, uint32_t *fsr, |
7577 | ARMMMUFaultInfo *fi) | |
9ee6e8bb | 7578 | { |
70d74660 | 7579 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
9ee6e8bb PB |
7580 | int code; |
7581 | uint32_t table; | |
7582 | uint32_t desc; | |
7583 | uint32_t xn; | |
de9b05b8 | 7584 | uint32_t pxn = 0; |
9ee6e8bb PB |
7585 | int type; |
7586 | int ap; | |
de9b05b8 | 7587 | int domain = 0; |
dd4ebc2e | 7588 | int domain_prot; |
a8170e5e | 7589 | hwaddr phys_addr; |
0480f69a | 7590 | uint32_t dacr; |
8bf5b6a9 | 7591 | bool ns; |
9ee6e8bb PB |
7592 | |
7593 | /* Pagetable walk. */ | |
7594 | /* Lookup l1 descriptor. */ | |
0480f69a | 7595 | if (!get_level1_table_address(env, mmu_idx, &table, address)) { |
e389be16 FA |
7596 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ |
7597 | code = 5; | |
7598 | goto do_fault; | |
7599 | } | |
a614e698 EI |
7600 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
7601 | mmu_idx, fsr, fi); | |
9ee6e8bb | 7602 | type = (desc & 3); |
de9b05b8 PM |
7603 | if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { |
7604 | /* Section translation fault, or attempt to use the encoding | |
7605 | * which is Reserved on implementations without PXN. | |
7606 | */ | |
9ee6e8bb | 7607 | code = 5; |
9ee6e8bb | 7608 | goto do_fault; |
de9b05b8 PM |
7609 | } |
7610 | if ((type == 1) || !(desc & (1 << 18))) { | |
7611 | /* Page or Section. */ | |
dd4ebc2e | 7612 | domain = (desc >> 5) & 0x0f; |
9ee6e8bb | 7613 | } |
0480f69a PM |
7614 | if (regime_el(env, mmu_idx) == 1) { |
7615 | dacr = env->cp15.dacr_ns; | |
7616 | } else { | |
7617 | dacr = env->cp15.dacr_s; | |
7618 | } | |
7619 | domain_prot = (dacr >> (domain * 2)) & 3; | |
dd4ebc2e | 7620 | if (domain_prot == 0 || domain_prot == 2) { |
de9b05b8 | 7621 | if (type != 1) { |
9ee6e8bb | 7622 | code = 9; /* Section domain fault. */ |
de9b05b8 | 7623 | } else { |
9ee6e8bb | 7624 | code = 11; /* Page domain fault. */ |
de9b05b8 | 7625 | } |
9ee6e8bb PB |
7626 | goto do_fault; |
7627 | } | |
de9b05b8 | 7628 | if (type != 1) { |
9ee6e8bb PB |
7629 | if (desc & (1 << 18)) { |
7630 | /* Supersection. */ | |
7631 | phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); | |
4e42a6ca SF |
7632 | phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32; |
7633 | phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36; | |
d4c430a8 | 7634 | *page_size = 0x1000000; |
b5ff1b31 | 7635 | } else { |
9ee6e8bb PB |
7636 | /* Section. */ |
7637 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
d4c430a8 | 7638 | *page_size = 0x100000; |
b5ff1b31 | 7639 | } |
9ee6e8bb PB |
7640 | ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
7641 | xn = desc & (1 << 4); | |
de9b05b8 | 7642 | pxn = desc & 1; |
9ee6e8bb | 7643 | code = 13; |
8bf5b6a9 | 7644 | ns = extract32(desc, 19, 1); |
9ee6e8bb | 7645 | } else { |
de9b05b8 PM |
7646 | if (arm_feature(env, ARM_FEATURE_PXN)) { |
7647 | pxn = (desc >> 2) & 1; | |
7648 | } | |
8bf5b6a9 | 7649 | ns = extract32(desc, 3, 1); |
9ee6e8bb PB |
7650 | /* Lookup l2 entry. */ |
7651 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
a614e698 EI |
7652 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
7653 | mmu_idx, fsr, fi); | |
9ee6e8bb PB |
7654 | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
7655 | switch (desc & 3) { | |
7656 | case 0: /* Page translation fault. */ | |
7657 | code = 7; | |
b5ff1b31 | 7658 | goto do_fault; |
9ee6e8bb PB |
7659 | case 1: /* 64k page. */ |
7660 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
7661 | xn = desc & (1 << 15); | |
d4c430a8 | 7662 | *page_size = 0x10000; |
9ee6e8bb PB |
7663 | break; |
7664 | case 2: case 3: /* 4k page. */ | |
7665 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
7666 | xn = desc & 1; | |
d4c430a8 | 7667 | *page_size = 0x1000; |
9ee6e8bb PB |
7668 | break; |
7669 | default: | |
7670 | /* Never happens, but compiler isn't smart enough to tell. */ | |
7671 | abort(); | |
b5ff1b31 | 7672 | } |
9ee6e8bb PB |
7673 | code = 15; |
7674 | } | |
dd4ebc2e | 7675 | if (domain_prot == 3) { |
c0034328 JR |
7676 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
7677 | } else { | |
0480f69a | 7678 | if (pxn && !regime_is_user(env, mmu_idx)) { |
de9b05b8 PM |
7679 | xn = 1; |
7680 | } | |
c0034328 JR |
7681 | if (xn && access_type == 2) |
7682 | goto do_fault; | |
9ee6e8bb | 7683 | |
d76951b6 AJ |
7684 | if (arm_feature(env, ARM_FEATURE_V6K) && |
7685 | (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { | |
7686 | /* The simplified model uses AP[0] as an access control bit. */ | |
7687 | if ((ap & 1) == 0) { | |
7688 | /* Access flag fault. */ | |
7689 | code = (code == 15) ? 6 : 3; | |
7690 | goto do_fault; | |
7691 | } | |
7692 | *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); | |
7693 | } else { | |
7694 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); | |
c0034328 | 7695 | } |
0fbf5238 AJ |
7696 | if (*prot && !xn) { |
7697 | *prot |= PAGE_EXEC; | |
7698 | } | |
7699 | if (!(*prot & (1 << access_type))) { | |
c0034328 JR |
7700 | /* Access permission fault. */ |
7701 | goto do_fault; | |
7702 | } | |
3ad493fc | 7703 | } |
8bf5b6a9 PM |
7704 | if (ns) { |
7705 | /* The NS bit will (as required by the architecture) have no effect if | |
7706 | * the CPU doesn't support TZ or this is a non-secure translation | |
7707 | * regime, because the attribute will already be non-secure. | |
7708 | */ | |
7709 | attrs->secure = false; | |
7710 | } | |
9ee6e8bb | 7711 | *phys_ptr = phys_addr; |
b7cc4e82 | 7712 | return false; |
b5ff1b31 | 7713 | do_fault: |
b7cc4e82 PC |
7714 | *fsr = code | (domain << 4); |
7715 | return true; | |
b5ff1b31 FB |
7716 | } |
7717 | ||
3dde962f PM |
7718 | /* Fault type for long-descriptor MMU fault reporting; this corresponds |
7719 | * to bits [5..2] in the STATUS field in long-format DFSR/IFSR. | |
7720 | */ | |
7721 | typedef enum { | |
7722 | translation_fault = 1, | |
7723 | access_fault = 2, | |
7724 | permission_fault = 3, | |
7725 | } MMUFaultType; | |
7726 | ||
1853d5a9 | 7727 | /* |
a0e966c9 | 7728 | * check_s2_mmu_setup |
1853d5a9 EI |
7729 | * @cpu: ARMCPU |
7730 | * @is_aa64: True if the translation regime is in AArch64 state | |
7731 | * @startlevel: Suggested starting level | |
7732 | * @inputsize: Bitsize of IPAs | |
7733 | * @stride: Page-table stride (See the ARM ARM) | |
7734 | * | |
a0e966c9 EI |
7735 | * Returns true if the suggested S2 translation parameters are OK and |
7736 | * false otherwise. | |
1853d5a9 | 7737 | */ |
a0e966c9 EI |
7738 | static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, |
7739 | int inputsize, int stride) | |
1853d5a9 | 7740 | { |
98d68ec2 EI |
7741 | const int grainsize = stride + 3; |
7742 | int startsizecheck; | |
7743 | ||
1853d5a9 EI |
7744 | /* Negative levels are never allowed. */ |
7745 | if (level < 0) { | |
7746 | return false; | |
7747 | } | |
7748 | ||
98d68ec2 EI |
7749 | startsizecheck = inputsize - ((3 - level) * stride + grainsize); |
7750 | if (startsizecheck < 1 || startsizecheck > stride + 4) { | |
7751 | return false; | |
7752 | } | |
7753 | ||
1853d5a9 | 7754 | if (is_aa64) { |
3526423e | 7755 | CPUARMState *env = &cpu->env; |
1853d5a9 EI |
7756 | unsigned int pamax = arm_pamax(cpu); |
7757 | ||
7758 | switch (stride) { | |
7759 | case 13: /* 64KB Pages. */ | |
7760 | if (level == 0 || (level == 1 && pamax <= 42)) { | |
7761 | return false; | |
7762 | } | |
7763 | break; | |
7764 | case 11: /* 16KB Pages. */ | |
7765 | if (level == 0 || (level == 1 && pamax <= 40)) { | |
7766 | return false; | |
7767 | } | |
7768 | break; | |
7769 | case 9: /* 4KB Pages. */ | |
7770 | if (level == 0 && pamax <= 42) { | |
7771 | return false; | |
7772 | } | |
7773 | break; | |
7774 | default: | |
7775 | g_assert_not_reached(); | |
7776 | } | |
3526423e EI |
7777 | |
7778 | /* Inputsize checks. */ | |
7779 | if (inputsize > pamax && | |
7780 | (arm_el_is_aa64(env, 1) || inputsize > 40)) { | |
7781 | /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ | |
7782 | return false; | |
7783 | } | |
1853d5a9 | 7784 | } else { |
1853d5a9 EI |
7785 | /* AArch32 only supports 4KB pages. Assert on that. */ |
7786 | assert(stride == 9); | |
7787 | ||
7788 | if (level == 0) { | |
7789 | return false; | |
7790 | } | |
1853d5a9 EI |
7791 | } |
7792 | return true; | |
7793 | } | |
7794 | ||
b7cc4e82 PC |
7795 | static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
7796 | int access_type, ARMMMUIdx mmu_idx, | |
7797 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, | |
e14b5a23 EI |
7798 | target_ulong *page_size_ptr, uint32_t *fsr, |
7799 | ARMMMUFaultInfo *fi) | |
3dde962f | 7800 | { |
1853d5a9 EI |
7801 | ARMCPU *cpu = arm_env_get_cpu(env); |
7802 | CPUState *cs = CPU(cpu); | |
3dde962f PM |
7803 | /* Read an LPAE long-descriptor translation table. */ |
7804 | MMUFaultType fault_type = translation_fault; | |
1b4093ea | 7805 | uint32_t level; |
0c5fbf3b | 7806 | uint32_t epd = 0; |
1f4c8c18 | 7807 | int32_t t0sz, t1sz; |
2c8dd318 | 7808 | uint32_t tg; |
3dde962f PM |
7809 | uint64_t ttbr; |
7810 | int ttbr_select; | |
dddb5223 | 7811 | hwaddr descaddr, indexmask, indexmask_grainsize; |
3dde962f PM |
7812 | uint32_t tableattrs; |
7813 | target_ulong page_size; | |
7814 | uint32_t attrs; | |
973a5434 | 7815 | int32_t stride = 9; |
6e99f762 | 7816 | int32_t addrsize; |
4ca6a051 | 7817 | int inputsize; |
2c8dd318 | 7818 | int32_t tbi = 0; |
0480f69a | 7819 | TCR *tcr = regime_tcr(env, mmu_idx); |
d8e052b3 | 7820 | int ap, ns, xn, pxn; |
88e8add8 GB |
7821 | uint32_t el = regime_el(env, mmu_idx); |
7822 | bool ttbr1_valid = true; | |
6109769a | 7823 | uint64_t descaddrmask; |
6e99f762 | 7824 | bool aarch64 = arm_el_is_aa64(env, el); |
0480f69a PM |
7825 | |
7826 | /* TODO: | |
88e8add8 GB |
7827 | * This code does not handle the different format TCR for VTCR_EL2. |
7828 | * This code also does not support shareability levels. | |
7829 | * Attribute and permission bit handling should also be checked when adding | |
7830 | * support for those page table walks. | |
0480f69a | 7831 | */ |
6e99f762 | 7832 | if (aarch64) { |
1b4093ea | 7833 | level = 0; |
6e99f762 | 7834 | addrsize = 64; |
88e8add8 | 7835 | if (el > 1) { |
1edee470 EI |
7836 | if (mmu_idx != ARMMMUIdx_S2NS) { |
7837 | tbi = extract64(tcr->raw_tcr, 20, 1); | |
7838 | } | |
88e8add8 GB |
7839 | } else { |
7840 | if (extract64(address, 55, 1)) { | |
7841 | tbi = extract64(tcr->raw_tcr, 38, 1); | |
7842 | } else { | |
7843 | tbi = extract64(tcr->raw_tcr, 37, 1); | |
7844 | } | |
7845 | } | |
2c8dd318 | 7846 | tbi *= 8; |
88e8add8 GB |
7847 | |
7848 | /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it | |
7849 | * invalid. | |
7850 | */ | |
7851 | if (el > 1) { | |
7852 | ttbr1_valid = false; | |
7853 | } | |
d0a2cbce | 7854 | } else { |
1b4093ea | 7855 | level = 1; |
6e99f762 | 7856 | addrsize = 32; |
d0a2cbce PM |
7857 | /* There is no TTBR1 for EL2 */ |
7858 | if (el == 2) { | |
7859 | ttbr1_valid = false; | |
7860 | } | |
2c8dd318 | 7861 | } |
3dde962f PM |
7862 | |
7863 | /* Determine whether this address is in the region controlled by | |
7864 | * TTBR0 or TTBR1 (or if it is in neither region and should fault). | |
7865 | * This is a Non-secure PL0/1 stage 1 translation, so controlled by | |
7866 | * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: | |
7867 | */ | |
6e99f762 | 7868 | if (aarch64) { |
4ee38098 EI |
7869 | /* AArch64 translation. */ |
7870 | t0sz = extract32(tcr->raw_tcr, 0, 6); | |
2c8dd318 RH |
7871 | t0sz = MIN(t0sz, 39); |
7872 | t0sz = MAX(t0sz, 16); | |
4ee38098 EI |
7873 | } else if (mmu_idx != ARMMMUIdx_S2NS) { |
7874 | /* AArch32 stage 1 translation. */ | |
7875 | t0sz = extract32(tcr->raw_tcr, 0, 3); | |
7876 | } else { | |
7877 | /* AArch32 stage 2 translation. */ | |
7878 | bool sext = extract32(tcr->raw_tcr, 4, 1); | |
7879 | bool sign = extract32(tcr->raw_tcr, 3, 1); | |
6e99f762 SS |
7880 | /* Address size is 40-bit for a stage 2 translation, |
7881 | * and t0sz can be negative (from -8 to 7), | |
7882 | * so we need to adjust it to use the TTBR selecting logic below. | |
7883 | */ | |
7884 | addrsize = 40; | |
7885 | t0sz = sextract32(tcr->raw_tcr, 0, 4) + 8; | |
4ee38098 EI |
7886 | |
7887 | /* If the sign-extend bit is not the same as t0sz[3], the result | |
7888 | * is unpredictable. Flag this as a guest error. */ | |
7889 | if (sign != sext) { | |
7890 | qemu_log_mask(LOG_GUEST_ERROR, | |
39cba610 | 7891 | "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); |
4ee38098 | 7892 | } |
2c8dd318 | 7893 | } |
1f4c8c18 | 7894 | t1sz = extract32(tcr->raw_tcr, 16, 6); |
6e99f762 | 7895 | if (aarch64) { |
2c8dd318 RH |
7896 | t1sz = MIN(t1sz, 39); |
7897 | t1sz = MAX(t1sz, 16); | |
7898 | } | |
6e99f762 | 7899 | if (t0sz && !extract64(address, addrsize - t0sz, t0sz - tbi)) { |
3dde962f PM |
7900 | /* there is a ttbr0 region and we are in it (high bits all zero) */ |
7901 | ttbr_select = 0; | |
88e8add8 | 7902 | } else if (ttbr1_valid && t1sz && |
6e99f762 | 7903 | !extract64(~address, addrsize - t1sz, t1sz - tbi)) { |
3dde962f PM |
7904 | /* there is a ttbr1 region and we are in it (high bits all one) */ |
7905 | ttbr_select = 1; | |
7906 | } else if (!t0sz) { | |
7907 | /* ttbr0 region is "everything not in the ttbr1 region" */ | |
7908 | ttbr_select = 0; | |
88e8add8 | 7909 | } else if (!t1sz && ttbr1_valid) { |
3dde962f PM |
7910 | /* ttbr1 region is "everything not in the ttbr0 region" */ |
7911 | ttbr_select = 1; | |
7912 | } else { | |
7913 | /* in the gap between the two regions, this is a Translation fault */ | |
7914 | fault_type = translation_fault; | |
7915 | goto do_fault; | |
7916 | } | |
7917 | ||
7918 | /* Note that QEMU ignores shareability and cacheability attributes, | |
7919 | * so we don't need to do anything with the SH, ORGN, IRGN fields | |
7920 | * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the | |
7921 | * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently | |
7922 | * implement any ASID-like capability so we can ignore it (instead | |
7923 | * we will always flush the TLB any time the ASID is changed). | |
7924 | */ | |
7925 | if (ttbr_select == 0) { | |
aef878be | 7926 | ttbr = regime_ttbr(env, mmu_idx, 0); |
0c5fbf3b EI |
7927 | if (el < 2) { |
7928 | epd = extract32(tcr->raw_tcr, 7, 1); | |
7929 | } | |
6e99f762 | 7930 | inputsize = addrsize - t0sz; |
2c8dd318 | 7931 | |
11f136ee | 7932 | tg = extract32(tcr->raw_tcr, 14, 2); |
2c8dd318 | 7933 | if (tg == 1) { /* 64KB pages */ |
973a5434 | 7934 | stride = 13; |
2c8dd318 RH |
7935 | } |
7936 | if (tg == 2) { /* 16KB pages */ | |
973a5434 | 7937 | stride = 11; |
2c8dd318 | 7938 | } |
3dde962f | 7939 | } else { |
88e8add8 GB |
7940 | /* We should only be here if TTBR1 is valid */ |
7941 | assert(ttbr1_valid); | |
7942 | ||
aef878be | 7943 | ttbr = regime_ttbr(env, mmu_idx, 1); |
11f136ee | 7944 | epd = extract32(tcr->raw_tcr, 23, 1); |
6e99f762 | 7945 | inputsize = addrsize - t1sz; |
2c8dd318 | 7946 | |
11f136ee | 7947 | tg = extract32(tcr->raw_tcr, 30, 2); |
2c8dd318 | 7948 | if (tg == 3) { /* 64KB pages */ |
973a5434 | 7949 | stride = 13; |
2c8dd318 RH |
7950 | } |
7951 | if (tg == 1) { /* 16KB pages */ | |
973a5434 | 7952 | stride = 11; |
2c8dd318 | 7953 | } |
3dde962f PM |
7954 | } |
7955 | ||
0480f69a | 7956 | /* Here we should have set up all the parameters for the translation: |
6e99f762 | 7957 | * inputsize, ttbr, epd, stride, tbi |
0480f69a PM |
7958 | */ |
7959 | ||
3dde962f | 7960 | if (epd) { |
88e8add8 GB |
7961 | /* Translation table walk disabled => Translation fault on TLB miss |
7962 | * Note: This is always 0 on 64-bit EL2 and EL3. | |
7963 | */ | |
3dde962f PM |
7964 | goto do_fault; |
7965 | } | |
7966 | ||
1853d5a9 EI |
7967 | if (mmu_idx != ARMMMUIdx_S2NS) { |
7968 | /* The starting level depends on the virtual address size (which can | |
7969 | * be up to 48 bits) and the translation granule size. It indicates | |
7970 | * the number of strides (stride bits at a time) needed to | |
7971 | * consume the bits of the input address. In the pseudocode this is: | |
7972 | * level = 4 - RoundUp((inputsize - grainsize) / stride) | |
7973 | * where their 'inputsize' is our 'inputsize', 'grainsize' is | |
7974 | * our 'stride + 3' and 'stride' is our 'stride'. | |
7975 | * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: | |
7976 | * = 4 - (inputsize - stride - 3 + stride - 1) / stride | |
7977 | * = 4 - (inputsize - 4) / stride; | |
7978 | */ | |
7979 | level = 4 - (inputsize - 4) / stride; | |
7980 | } else { | |
7981 | /* For stage 2 translations the starting level is specified by the | |
7982 | * VTCR_EL2.SL0 field (whose interpretation depends on the page size) | |
7983 | */ | |
1b4093ea SS |
7984 | uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); |
7985 | uint32_t startlevel; | |
1853d5a9 EI |
7986 | bool ok; |
7987 | ||
6e99f762 | 7988 | if (!aarch64 || stride == 9) { |
1853d5a9 | 7989 | /* AArch32 or 4KB pages */ |
1b4093ea | 7990 | startlevel = 2 - sl0; |
1853d5a9 EI |
7991 | } else { |
7992 | /* 16KB or 64KB pages */ | |
1b4093ea | 7993 | startlevel = 3 - sl0; |
1853d5a9 EI |
7994 | } |
7995 | ||
7996 | /* Check that the starting level is valid. */ | |
6e99f762 | 7997 | ok = check_s2_mmu_setup(cpu, aarch64, startlevel, |
1b4093ea | 7998 | inputsize, stride); |
1853d5a9 | 7999 | if (!ok) { |
1853d5a9 EI |
8000 | fault_type = translation_fault; |
8001 | goto do_fault; | |
8002 | } | |
1b4093ea | 8003 | level = startlevel; |
1853d5a9 | 8004 | } |
3dde962f | 8005 | |
dddb5223 SS |
8006 | indexmask_grainsize = (1ULL << (stride + 3)) - 1; |
8007 | indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; | |
3dde962f PM |
8008 | |
8009 | /* Now we can extract the actual base address from the TTBR */ | |
2c8dd318 | 8010 | descaddr = extract64(ttbr, 0, 48); |
dddb5223 | 8011 | descaddr &= ~indexmask; |
3dde962f | 8012 | |
6109769a | 8013 | /* The address field in the descriptor goes up to bit 39 for ARMv7 |
dddb5223 SS |
8014 | * but up to bit 47 for ARMv8, but we use the descaddrmask |
8015 | * up to bit 39 for AArch32, because we don't need other bits in that case | |
8016 | * to construct next descriptor address (anyway they should be all zeroes). | |
6109769a | 8017 | */ |
6e99f762 | 8018 | descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) & |
dddb5223 | 8019 | ~indexmask_grainsize; |
6109769a | 8020 | |
ebca90e4 PM |
8021 | /* Secure accesses start with the page table in secure memory and |
8022 | * can be downgraded to non-secure at any step. Non-secure accesses | |
8023 | * remain non-secure. We implement this by just ORing in the NSTable/NS | |
8024 | * bits at each step. | |
8025 | */ | |
8026 | tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); | |
3dde962f PM |
8027 | for (;;) { |
8028 | uint64_t descriptor; | |
ebca90e4 | 8029 | bool nstable; |
3dde962f | 8030 | |
dddb5223 | 8031 | descaddr |= (address >> (stride * (4 - level))) & indexmask; |
2c8dd318 | 8032 | descaddr &= ~7ULL; |
ebca90e4 | 8033 | nstable = extract32(tableattrs, 4, 1); |
37785977 EI |
8034 | descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi); |
8035 | if (fi->s1ptw) { | |
8036 | goto do_fault; | |
8037 | } | |
8038 | ||
3dde962f PM |
8039 | if (!(descriptor & 1) || |
8040 | (!(descriptor & 2) && (level == 3))) { | |
8041 | /* Invalid, or the Reserved level 3 encoding */ | |
8042 | goto do_fault; | |
8043 | } | |
6109769a | 8044 | descaddr = descriptor & descaddrmask; |
3dde962f PM |
8045 | |
8046 | if ((descriptor & 2) && (level < 3)) { | |
8047 | /* Table entry. The top five bits are attributes which may | |
8048 | * propagate down through lower levels of the table (and | |
8049 | * which are all arranged so that 0 means "no effect", so | |
8050 | * we can gather them up by ORing in the bits at each level). | |
8051 | */ | |
8052 | tableattrs |= extract64(descriptor, 59, 5); | |
8053 | level++; | |
dddb5223 | 8054 | indexmask = indexmask_grainsize; |
3dde962f PM |
8055 | continue; |
8056 | } | |
8057 | /* Block entry at level 1 or 2, or page entry at level 3. | |
8058 | * These are basically the same thing, although the number | |
8059 | * of bits we pull in from the vaddr varies. | |
8060 | */ | |
973a5434 | 8061 | page_size = (1ULL << ((stride * (4 - level)) + 3)); |
3dde962f | 8062 | descaddr |= (address & (page_size - 1)); |
6ab1a5ee | 8063 | /* Extract attributes from the descriptor */ |
d615efac IC |
8064 | attrs = extract64(descriptor, 2, 10) |
8065 | | (extract64(descriptor, 52, 12) << 10); | |
6ab1a5ee EI |
8066 | |
8067 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
8068 | /* Stage 2 table descriptors do not include any attribute fields */ | |
8069 | break; | |
8070 | } | |
8071 | /* Merge in attributes from table descriptors */ | |
3dde962f PM |
8072 | attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ |
8073 | attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ | |
8074 | /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 | |
8075 | * means "force PL1 access only", which means forcing AP[1] to 0. | |
8076 | */ | |
8077 | if (extract32(tableattrs, 2, 1)) { | |
8078 | attrs &= ~(1 << 4); | |
8079 | } | |
ebca90e4 | 8080 | attrs |= nstable << 3; /* NS */ |
3dde962f PM |
8081 | break; |
8082 | } | |
8083 | /* Here descaddr is the final physical address, and attributes | |
8084 | * are all in attrs. | |
8085 | */ | |
8086 | fault_type = access_fault; | |
8087 | if ((attrs & (1 << 8)) == 0) { | |
8088 | /* Access flag */ | |
8089 | goto do_fault; | |
8090 | } | |
d8e052b3 AJ |
8091 | |
8092 | ap = extract32(attrs, 4, 2); | |
d8e052b3 | 8093 | xn = extract32(attrs, 12, 1); |
d8e052b3 | 8094 | |
6ab1a5ee EI |
8095 | if (mmu_idx == ARMMMUIdx_S2NS) { |
8096 | ns = true; | |
8097 | *prot = get_S2prot(env, ap, xn); | |
8098 | } else { | |
8099 | ns = extract32(attrs, 3, 1); | |
8100 | pxn = extract32(attrs, 11, 1); | |
6e99f762 | 8101 | *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); |
6ab1a5ee | 8102 | } |
d8e052b3 | 8103 | |
3dde962f | 8104 | fault_type = permission_fault; |
d8e052b3 | 8105 | if (!(*prot & (1 << access_type))) { |
3dde962f PM |
8106 | goto do_fault; |
8107 | } | |
3dde962f | 8108 | |
8bf5b6a9 PM |
8109 | if (ns) { |
8110 | /* The NS bit will (as required by the architecture) have no effect if | |
8111 | * the CPU doesn't support TZ or this is a non-secure translation | |
8112 | * regime, because the attribute will already be non-secure. | |
8113 | */ | |
8114 | txattrs->secure = false; | |
8115 | } | |
3dde962f PM |
8116 | *phys_ptr = descaddr; |
8117 | *page_size_ptr = page_size; | |
b7cc4e82 | 8118 | return false; |
3dde962f PM |
8119 | |
8120 | do_fault: | |
8121 | /* Long-descriptor format IFSR/DFSR value */ | |
b7cc4e82 | 8122 | *fsr = (1 << 9) | (fault_type << 2) | level; |
37785977 EI |
8123 | /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ |
8124 | fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS); | |
b7cc4e82 | 8125 | return true; |
3dde962f PM |
8126 | } |
8127 | ||
f6bda88f PC |
8128 | static inline void get_phys_addr_pmsav7_default(CPUARMState *env, |
8129 | ARMMMUIdx mmu_idx, | |
8130 | int32_t address, int *prot) | |
8131 | { | |
3a00d560 MD |
8132 | if (!arm_feature(env, ARM_FEATURE_M)) { |
8133 | *prot = PAGE_READ | PAGE_WRITE; | |
8134 | switch (address) { | |
8135 | case 0xF0000000 ... 0xFFFFFFFF: | |
8136 | if (regime_sctlr(env, mmu_idx) & SCTLR_V) { | |
8137 | /* hivecs execing is ok */ | |
8138 | *prot |= PAGE_EXEC; | |
8139 | } | |
8140 | break; | |
8141 | case 0x00000000 ... 0x7FFFFFFF: | |
f6bda88f | 8142 | *prot |= PAGE_EXEC; |
3a00d560 MD |
8143 | break; |
8144 | } | |
8145 | } else { | |
8146 | /* Default system address map for M profile cores. | |
8147 | * The architecture specifies which regions are execute-never; | |
8148 | * at the MPU level no other checks are defined. | |
8149 | */ | |
8150 | switch (address) { | |
8151 | case 0x00000000 ... 0x1fffffff: /* ROM */ | |
8152 | case 0x20000000 ... 0x3fffffff: /* SRAM */ | |
8153 | case 0x60000000 ... 0x7fffffff: /* RAM */ | |
8154 | case 0x80000000 ... 0x9fffffff: /* RAM */ | |
8155 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
8156 | break; | |
8157 | case 0x40000000 ... 0x5fffffff: /* Peripheral */ | |
8158 | case 0xa0000000 ... 0xbfffffff: /* Device */ | |
8159 | case 0xc0000000 ... 0xdfffffff: /* Device */ | |
8160 | case 0xe0000000 ... 0xffffffff: /* System */ | |
8161 | *prot = PAGE_READ | PAGE_WRITE; | |
8162 | break; | |
8163 | default: | |
8164 | g_assert_not_reached(); | |
f6bda88f | 8165 | } |
f6bda88f | 8166 | } |
f6bda88f PC |
8167 | } |
8168 | ||
8169 | static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, | |
8170 | int access_type, ARMMMUIdx mmu_idx, | |
8171 | hwaddr *phys_ptr, int *prot, uint32_t *fsr) | |
8172 | { | |
8173 | ARMCPU *cpu = arm_env_get_cpu(env); | |
8174 | int n; | |
8175 | bool is_user = regime_is_user(env, mmu_idx); | |
8176 | ||
8177 | *phys_ptr = address; | |
8178 | *prot = 0; | |
8179 | ||
8180 | if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ | |
8181 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | |
8182 | } else { /* MPU enabled */ | |
8183 | for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { | |
8184 | /* region search */ | |
8185 | uint32_t base = env->pmsav7.drbar[n]; | |
8186 | uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5); | |
8187 | uint32_t rmask; | |
8188 | bool srdis = false; | |
8189 | ||
8190 | if (!(env->pmsav7.drsr[n] & 0x1)) { | |
8191 | continue; | |
8192 | } | |
8193 | ||
8194 | if (!rsize) { | |
c9f9f124 MD |
8195 | qemu_log_mask(LOG_GUEST_ERROR, |
8196 | "DRSR[%d]: Rsize field cannot be 0\n", n); | |
f6bda88f PC |
8197 | continue; |
8198 | } | |
8199 | rsize++; | |
8200 | rmask = (1ull << rsize) - 1; | |
8201 | ||
8202 | if (base & rmask) { | |
c9f9f124 MD |
8203 | qemu_log_mask(LOG_GUEST_ERROR, |
8204 | "DRBAR[%d]: 0x%" PRIx32 " misaligned " | |
8205 | "to DRSR region size, mask = 0x%" PRIx32 "\n", | |
8206 | n, base, rmask); | |
f6bda88f PC |
8207 | continue; |
8208 | } | |
8209 | ||
8210 | if (address < base || address > base + rmask) { | |
8211 | continue; | |
8212 | } | |
8213 | ||
8214 | /* Region matched */ | |
8215 | ||
8216 | if (rsize >= 8) { /* no subregions for regions < 256 bytes */ | |
8217 | int i, snd; | |
8218 | uint32_t srdis_mask; | |
8219 | ||
8220 | rsize -= 3; /* sub region size (power of 2) */ | |
8221 | snd = ((address - base) >> rsize) & 0x7; | |
8222 | srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1); | |
8223 | ||
8224 | srdis_mask = srdis ? 0x3 : 0x0; | |
8225 | for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) { | |
8226 | /* This will check in groups of 2, 4 and then 8, whether | |
8227 | * the subregion bits are consistent. rsize is incremented | |
8228 | * back up to give the region size, considering consistent | |
8229 | * adjacent subregions as one region. Stop testing if rsize | |
8230 | * is already big enough for an entire QEMU page. | |
8231 | */ | |
8232 | int snd_rounded = snd & ~(i - 1); | |
8233 | uint32_t srdis_multi = extract32(env->pmsav7.drsr[n], | |
8234 | snd_rounded + 8, i); | |
8235 | if (srdis_mask ^ srdis_multi) { | |
8236 | break; | |
8237 | } | |
8238 | srdis_mask = (srdis_mask << i) | srdis_mask; | |
8239 | rsize++; | |
8240 | } | |
8241 | } | |
8242 | if (rsize < TARGET_PAGE_BITS) { | |
c9f9f124 MD |
8243 | qemu_log_mask(LOG_UNIMP, |
8244 | "DRSR[%d]: No support for MPU (sub)region " | |
f6bda88f | 8245 | "alignment of %" PRIu32 " bits. Minimum is %d\n", |
c9f9f124 | 8246 | n, rsize, TARGET_PAGE_BITS); |
f6bda88f PC |
8247 | continue; |
8248 | } | |
8249 | if (srdis) { | |
8250 | continue; | |
8251 | } | |
8252 | break; | |
8253 | } | |
8254 | ||
8255 | if (n == -1) { /* no hits */ | |
e9235c69 | 8256 | if (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR)) { |
f6bda88f PC |
8257 | /* background fault */ |
8258 | *fsr = 0; | |
8259 | return true; | |
8260 | } | |
8261 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | |
8262 | } else { /* a MPU hit! */ | |
8263 | uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); | |
8264 | ||
8265 | if (is_user) { /* User mode AP bit decoding */ | |
8266 | switch (ap) { | |
8267 | case 0: | |
8268 | case 1: | |
8269 | case 5: | |
8270 | break; /* no access */ | |
8271 | case 3: | |
8272 | *prot |= PAGE_WRITE; | |
8273 | /* fall through */ | |
8274 | case 2: | |
8275 | case 6: | |
8276 | *prot |= PAGE_READ | PAGE_EXEC; | |
8277 | break; | |
8278 | default: | |
8279 | qemu_log_mask(LOG_GUEST_ERROR, | |
c9f9f124 MD |
8280 | "DRACR[%d]: Bad value for AP bits: 0x%" |
8281 | PRIx32 "\n", n, ap); | |
f6bda88f PC |
8282 | } |
8283 | } else { /* Priv. mode AP bits decoding */ | |
8284 | switch (ap) { | |
8285 | case 0: | |
8286 | break; /* no access */ | |
8287 | case 1: | |
8288 | case 2: | |
8289 | case 3: | |
8290 | *prot |= PAGE_WRITE; | |
8291 | /* fall through */ | |
8292 | case 5: | |
8293 | case 6: | |
8294 | *prot |= PAGE_READ | PAGE_EXEC; | |
8295 | break; | |
8296 | default: | |
8297 | qemu_log_mask(LOG_GUEST_ERROR, | |
c9f9f124 MD |
8298 | "DRACR[%d]: Bad value for AP bits: 0x%" |
8299 | PRIx32 "\n", n, ap); | |
f6bda88f PC |
8300 | } |
8301 | } | |
8302 | ||
8303 | /* execute never */ | |
8304 | if (env->pmsav7.dracr[n] & (1 << 12)) { | |
8305 | *prot &= ~PAGE_EXEC; | |
8306 | } | |
8307 | } | |
8308 | } | |
8309 | ||
8310 | *fsr = 0x00d; /* Permission fault */ | |
8311 | return !(*prot & (1 << access_type)); | |
8312 | } | |
8313 | ||
13689d43 PC |
8314 | static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, |
8315 | int access_type, ARMMMUIdx mmu_idx, | |
8316 | hwaddr *phys_ptr, int *prot, uint32_t *fsr) | |
9ee6e8bb PB |
8317 | { |
8318 | int n; | |
8319 | uint32_t mask; | |
8320 | uint32_t base; | |
0480f69a | 8321 | bool is_user = regime_is_user(env, mmu_idx); |
9ee6e8bb PB |
8322 | |
8323 | *phys_ptr = address; | |
8324 | for (n = 7; n >= 0; n--) { | |
554b0b09 | 8325 | base = env->cp15.c6_region[n]; |
87c3d486 | 8326 | if ((base & 1) == 0) { |
554b0b09 | 8327 | continue; |
87c3d486 | 8328 | } |
554b0b09 PM |
8329 | mask = 1 << ((base >> 1) & 0x1f); |
8330 | /* Keep this shift separate from the above to avoid an | |
8331 | (undefined) << 32. */ | |
8332 | mask = (mask << 1) - 1; | |
87c3d486 | 8333 | if (((base ^ address) & ~mask) == 0) { |
554b0b09 | 8334 | break; |
87c3d486 | 8335 | } |
9ee6e8bb | 8336 | } |
87c3d486 | 8337 | if (n < 0) { |
b7cc4e82 PC |
8338 | *fsr = 2; |
8339 | return true; | |
87c3d486 | 8340 | } |
9ee6e8bb PB |
8341 | |
8342 | if (access_type == 2) { | |
7e09797c | 8343 | mask = env->cp15.pmsav5_insn_ap; |
9ee6e8bb | 8344 | } else { |
7e09797c | 8345 | mask = env->cp15.pmsav5_data_ap; |
9ee6e8bb PB |
8346 | } |
8347 | mask = (mask >> (n * 4)) & 0xf; | |
8348 | switch (mask) { | |
8349 | case 0: | |
b7cc4e82 PC |
8350 | *fsr = 1; |
8351 | return true; | |
9ee6e8bb | 8352 | case 1: |
87c3d486 | 8353 | if (is_user) { |
b7cc4e82 PC |
8354 | *fsr = 1; |
8355 | return true; | |
87c3d486 | 8356 | } |
554b0b09 PM |
8357 | *prot = PAGE_READ | PAGE_WRITE; |
8358 | break; | |
9ee6e8bb | 8359 | case 2: |
554b0b09 | 8360 | *prot = PAGE_READ; |
87c3d486 | 8361 | if (!is_user) { |
554b0b09 | 8362 | *prot |= PAGE_WRITE; |
87c3d486 | 8363 | } |
554b0b09 | 8364 | break; |
9ee6e8bb | 8365 | case 3: |
554b0b09 PM |
8366 | *prot = PAGE_READ | PAGE_WRITE; |
8367 | break; | |
9ee6e8bb | 8368 | case 5: |
87c3d486 | 8369 | if (is_user) { |
b7cc4e82 PC |
8370 | *fsr = 1; |
8371 | return true; | |
87c3d486 | 8372 | } |
554b0b09 PM |
8373 | *prot = PAGE_READ; |
8374 | break; | |
9ee6e8bb | 8375 | case 6: |
554b0b09 PM |
8376 | *prot = PAGE_READ; |
8377 | break; | |
9ee6e8bb | 8378 | default: |
554b0b09 | 8379 | /* Bad permission. */ |
b7cc4e82 PC |
8380 | *fsr = 1; |
8381 | return true; | |
9ee6e8bb | 8382 | } |
3ad493fc | 8383 | *prot |= PAGE_EXEC; |
b7cc4e82 | 8384 | return false; |
9ee6e8bb PB |
8385 | } |
8386 | ||
702a9357 PM |
8387 | /* get_phys_addr - get the physical address for this virtual address |
8388 | * | |
8389 | * Find the physical address corresponding to the given virtual address, | |
8390 | * by doing a translation table walk on MMU based systems or using the | |
8391 | * MPU state on MPU based systems. | |
8392 | * | |
b7cc4e82 PC |
8393 | * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, |
8394 | * prot and page_size may not be filled in, and the populated fsr value provides | |
702a9357 PM |
8395 | * information on why the translation aborted, in the format of a |
8396 | * DFSR/IFSR fault register, with the following caveats: | |
8397 | * * we honour the short vs long DFSR format differences. | |
8398 | * * the WnR bit is never set (the caller must do this). | |
f6bda88f | 8399 | * * for PSMAv5 based systems we don't bother to return a full FSR format |
702a9357 PM |
8400 | * value. |
8401 | * | |
8402 | * @env: CPUARMState | |
8403 | * @address: virtual address to get physical address for | |
8404 | * @access_type: 0 for read, 1 for write, 2 for execute | |
d3649702 | 8405 | * @mmu_idx: MMU index indicating required translation regime |
702a9357 | 8406 | * @phys_ptr: set to the physical address corresponding to the virtual address |
8bf5b6a9 | 8407 | * @attrs: set to the memory transaction attributes to use |
702a9357 PM |
8408 | * @prot: set to the permissions for the page containing phys_ptr |
8409 | * @page_size: set to the size of the page containing phys_ptr | |
b7cc4e82 | 8410 | * @fsr: set to the DFSR/IFSR value on failure |
702a9357 | 8411 | */ |
af51f566 EI |
8412 | static bool get_phys_addr(CPUARMState *env, target_ulong address, |
8413 | int access_type, ARMMMUIdx mmu_idx, | |
8414 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, | |
e14b5a23 EI |
8415 | target_ulong *page_size, uint32_t *fsr, |
8416 | ARMMMUFaultInfo *fi) | |
9ee6e8bb | 8417 | { |
0480f69a | 8418 | if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { |
9b539263 EI |
8419 | /* Call ourselves recursively to do the stage 1 and then stage 2 |
8420 | * translations. | |
0480f69a | 8421 | */ |
9b539263 EI |
8422 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
8423 | hwaddr ipa; | |
8424 | int s2_prot; | |
8425 | int ret; | |
8426 | ||
8427 | ret = get_phys_addr(env, address, access_type, | |
8bd5c820 | 8428 | stage_1_mmu_idx(mmu_idx), &ipa, attrs, |
9b539263 EI |
8429 | prot, page_size, fsr, fi); |
8430 | ||
8431 | /* If S1 fails or S2 is disabled, return early. */ | |
8432 | if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { | |
8433 | *phys_ptr = ipa; | |
8434 | return ret; | |
8435 | } | |
8436 | ||
8437 | /* S1 is done. Now do S2 translation. */ | |
8438 | ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS, | |
8439 | phys_ptr, attrs, &s2_prot, | |
8440 | page_size, fsr, fi); | |
8441 | fi->s2addr = ipa; | |
8442 | /* Combine the S1 and S2 perms. */ | |
8443 | *prot &= s2_prot; | |
8444 | return ret; | |
8445 | } else { | |
8446 | /* | |
8447 | * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. | |
8448 | */ | |
8bd5c820 | 8449 | mmu_idx = stage_1_mmu_idx(mmu_idx); |
9b539263 | 8450 | } |
0480f69a | 8451 | } |
d3649702 | 8452 | |
8bf5b6a9 PM |
8453 | /* The page table entries may downgrade secure to non-secure, but |
8454 | * cannot upgrade an non-secure translation regime's attributes | |
8455 | * to secure. | |
8456 | */ | |
8457 | attrs->secure = regime_is_secure(env, mmu_idx); | |
0995bf8c | 8458 | attrs->user = regime_is_user(env, mmu_idx); |
8bf5b6a9 | 8459 | |
0480f69a PM |
8460 | /* Fast Context Switch Extension. This doesn't exist at all in v8. |
8461 | * In v7 and earlier it affects all stage 1 translations. | |
8462 | */ | |
8463 | if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS | |
8464 | && !arm_feature(env, ARM_FEATURE_V8)) { | |
8465 | if (regime_el(env, mmu_idx) == 3) { | |
8466 | address += env->cp15.fcseidr_s; | |
8467 | } else { | |
8468 | address += env->cp15.fcseidr_ns; | |
8469 | } | |
54bf36ed | 8470 | } |
9ee6e8bb | 8471 | |
f6bda88f PC |
8472 | /* pmsav7 has special handling for when MPU is disabled so call it before |
8473 | * the common MMU/MPU disabled check below. | |
8474 | */ | |
452a0955 | 8475 | if (arm_feature(env, ARM_FEATURE_PMSA) && |
f6bda88f | 8476 | arm_feature(env, ARM_FEATURE_V7)) { |
c9f9f124 | 8477 | bool ret; |
f6bda88f | 8478 | *page_size = TARGET_PAGE_SIZE; |
c9f9f124 MD |
8479 | ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, |
8480 | phys_ptr, prot, fsr); | |
8481 | qemu_log_mask(CPU_LOG_MMU, "PMSAv7 MPU lookup for %s at 0x%08" PRIx32 | |
8482 | " mmu_idx %u -> %s (prot %c%c%c)\n", | |
8483 | access_type == 1 ? "reading" : | |
8484 | (access_type == 2 ? "writing" : "execute"), | |
8485 | (uint32_t)address, mmu_idx, | |
8486 | ret ? "Miss" : "Hit", | |
8487 | *prot & PAGE_READ ? 'r' : '-', | |
8488 | *prot & PAGE_WRITE ? 'w' : '-', | |
8489 | *prot & PAGE_EXEC ? 'x' : '-'); | |
8490 | ||
8491 | return ret; | |
f6bda88f PC |
8492 | } |
8493 | ||
0480f69a | 8494 | if (regime_translation_disabled(env, mmu_idx)) { |
9ee6e8bb PB |
8495 | /* MMU/MPU disabled. */ |
8496 | *phys_ptr = address; | |
3ad493fc | 8497 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
d4c430a8 | 8498 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb | 8499 | return 0; |
0480f69a PM |
8500 | } |
8501 | ||
452a0955 | 8502 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
f6bda88f | 8503 | /* Pre-v7 MPU */ |
d4c430a8 | 8504 | *page_size = TARGET_PAGE_SIZE; |
13689d43 PC |
8505 | return get_phys_addr_pmsav5(env, address, access_type, mmu_idx, |
8506 | phys_ptr, prot, fsr); | |
0480f69a PM |
8507 | } |
8508 | ||
8509 | if (regime_using_lpae_format(env, mmu_idx)) { | |
8510 | return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr, | |
e14b5a23 | 8511 | attrs, prot, page_size, fsr, fi); |
0480f69a PM |
8512 | } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { |
8513 | return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr, | |
e14b5a23 | 8514 | attrs, prot, page_size, fsr, fi); |
9ee6e8bb | 8515 | } else { |
0480f69a | 8516 | return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr, |
e14b5a23 | 8517 | prot, page_size, fsr, fi); |
9ee6e8bb PB |
8518 | } |
8519 | } | |
8520 | ||
8c6084bf | 8521 | /* Walk the page table and (if the mapping exists) add the page |
b7cc4e82 PC |
8522 | * to the TLB. Return false on success, or true on failure. Populate |
8523 | * fsr with ARM DFSR/IFSR fault register format value on failure. | |
8c6084bf | 8524 | */ |
b7cc4e82 | 8525 | bool arm_tlb_fill(CPUState *cs, vaddr address, |
e14b5a23 EI |
8526 | int access_type, int mmu_idx, uint32_t *fsr, |
8527 | ARMMMUFaultInfo *fi) | |
b5ff1b31 | 8528 | { |
7510454e AF |
8529 | ARMCPU *cpu = ARM_CPU(cs); |
8530 | CPUARMState *env = &cpu->env; | |
a8170e5e | 8531 | hwaddr phys_addr; |
d4c430a8 | 8532 | target_ulong page_size; |
b5ff1b31 | 8533 | int prot; |
d3649702 | 8534 | int ret; |
8bf5b6a9 | 8535 | MemTxAttrs attrs = {}; |
b5ff1b31 | 8536 | |
8bd5c820 PM |
8537 | ret = get_phys_addr(env, address, access_type, |
8538 | core_to_arm_mmu_idx(env, mmu_idx), &phys_addr, | |
e14b5a23 | 8539 | &attrs, &prot, &page_size, fsr, fi); |
b7cc4e82 | 8540 | if (!ret) { |
b5ff1b31 | 8541 | /* Map a single [sub]page. */ |
dcd82c11 AB |
8542 | phys_addr &= TARGET_PAGE_MASK; |
8543 | address &= TARGET_PAGE_MASK; | |
8bf5b6a9 PM |
8544 | tlb_set_page_with_attrs(cs, address, phys_addr, attrs, |
8545 | prot, mmu_idx, page_size); | |
d4c430a8 | 8546 | return 0; |
b5ff1b31 FB |
8547 | } |
8548 | ||
8c6084bf | 8549 | return ret; |
b5ff1b31 FB |
8550 | } |
8551 | ||
0faea0c7 PM |
8552 | hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, |
8553 | MemTxAttrs *attrs) | |
b5ff1b31 | 8554 | { |
00b941e5 | 8555 | ARMCPU *cpu = ARM_CPU(cs); |
d3649702 | 8556 | CPUARMState *env = &cpu->env; |
a8170e5e | 8557 | hwaddr phys_addr; |
d4c430a8 | 8558 | target_ulong page_size; |
b5ff1b31 | 8559 | int prot; |
b7cc4e82 PC |
8560 | bool ret; |
8561 | uint32_t fsr; | |
e14b5a23 | 8562 | ARMMMUFaultInfo fi = {}; |
8bd5c820 | 8563 | ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); |
b5ff1b31 | 8564 | |
0faea0c7 PM |
8565 | *attrs = (MemTxAttrs) {}; |
8566 | ||
8bd5c820 | 8567 | ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr, |
0faea0c7 | 8568 | attrs, &prot, &page_size, &fsr, &fi); |
b5ff1b31 | 8569 | |
b7cc4e82 | 8570 | if (ret) { |
b5ff1b31 | 8571 | return -1; |
00b941e5 | 8572 | } |
b5ff1b31 FB |
8573 | return phys_addr; |
8574 | } | |
8575 | ||
0ecb72a5 | 8576 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb | 8577 | { |
58117c9b MD |
8578 | uint32_t mask; |
8579 | unsigned el = arm_current_el(env); | |
8580 | ||
8581 | /* First handle registers which unprivileged can read */ | |
8582 | ||
8583 | switch (reg) { | |
8584 | case 0 ... 7: /* xPSR sub-fields */ | |
8585 | mask = 0; | |
8586 | if ((reg & 1) && el) { | |
8587 | mask |= 0x000001ff; /* IPSR (unpriv. reads as zero) */ | |
8588 | } | |
8589 | if (!(reg & 4)) { | |
8590 | mask |= 0xf8000000; /* APSR */ | |
8591 | } | |
8592 | /* EPSR reads as zero */ | |
8593 | return xpsr_read(env) & mask; | |
8594 | break; | |
8595 | case 20: /* CONTROL */ | |
8596 | return env->v7m.control; | |
8597 | } | |
8598 | ||
8599 | if (el == 0) { | |
8600 | return 0; /* unprivileged reads others as zero */ | |
8601 | } | |
a47dddd7 | 8602 | |
9ee6e8bb | 8603 | switch (reg) { |
9ee6e8bb | 8604 | case 8: /* MSP */ |
abc24d86 MD |
8605 | return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? |
8606 | env->v7m.other_sp : env->regs[13]; | |
9ee6e8bb | 8607 | case 9: /* PSP */ |
abc24d86 MD |
8608 | return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? |
8609 | env->regs[13] : env->v7m.other_sp; | |
9ee6e8bb | 8610 | case 16: /* PRIMASK */ |
4cc35614 | 8611 | return (env->daif & PSTATE_I) != 0; |
82845826 SH |
8612 | case 17: /* BASEPRI */ |
8613 | case 18: /* BASEPRI_MAX */ | |
9ee6e8bb | 8614 | return env->v7m.basepri; |
82845826 | 8615 | case 19: /* FAULTMASK */ |
4cc35614 | 8616 | return (env->daif & PSTATE_F) != 0; |
9ee6e8bb | 8617 | default: |
58117c9b MD |
8618 | qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special" |
8619 | " register %d\n", reg); | |
9ee6e8bb PB |
8620 | return 0; |
8621 | } | |
8622 | } | |
8623 | ||
b28b3377 PM |
8624 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) |
8625 | { | |
8626 | /* We're passed bits [11..0] of the instruction; extract | |
8627 | * SYSm and the mask bits. | |
8628 | * Invalid combinations of SYSm and mask are UNPREDICTABLE; | |
8629 | * we choose to treat them as if the mask bits were valid. | |
8630 | * NB that the pseudocode 'mask' variable is bits [11..10], | |
8631 | * whereas ours is [11..8]. | |
8632 | */ | |
8633 | uint32_t mask = extract32(maskreg, 8, 4); | |
8634 | uint32_t reg = extract32(maskreg, 0, 8); | |
8635 | ||
58117c9b MD |
8636 | if (arm_current_el(env) == 0 && reg > 7) { |
8637 | /* only xPSR sub-fields may be written by unprivileged */ | |
8638 | return; | |
8639 | } | |
a47dddd7 | 8640 | |
9ee6e8bb | 8641 | switch (reg) { |
58117c9b MD |
8642 | case 0 ... 7: /* xPSR sub-fields */ |
8643 | /* only APSR is actually writable */ | |
b28b3377 PM |
8644 | if (!(reg & 4)) { |
8645 | uint32_t apsrmask = 0; | |
8646 | ||
8647 | if (mask & 8) { | |
8648 | apsrmask |= 0xf8000000; /* APSR NZCVQ */ | |
8649 | } | |
8650 | if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { | |
8651 | apsrmask |= 0x000f0000; /* APSR GE[3:0] */ | |
8652 | } | |
8653 | xpsr_write(env, val, apsrmask); | |
58117c9b | 8654 | } |
9ee6e8bb PB |
8655 | break; |
8656 | case 8: /* MSP */ | |
abc24d86 | 8657 | if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { |
9ee6e8bb | 8658 | env->v7m.other_sp = val; |
abc24d86 | 8659 | } else { |
9ee6e8bb | 8660 | env->regs[13] = val; |
abc24d86 | 8661 | } |
9ee6e8bb PB |
8662 | break; |
8663 | case 9: /* PSP */ | |
abc24d86 | 8664 | if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { |
9ee6e8bb | 8665 | env->regs[13] = val; |
abc24d86 | 8666 | } else { |
9ee6e8bb | 8667 | env->v7m.other_sp = val; |
abc24d86 | 8668 | } |
9ee6e8bb PB |
8669 | break; |
8670 | case 16: /* PRIMASK */ | |
4cc35614 PM |
8671 | if (val & 1) { |
8672 | env->daif |= PSTATE_I; | |
8673 | } else { | |
8674 | env->daif &= ~PSTATE_I; | |
8675 | } | |
9ee6e8bb | 8676 | break; |
82845826 | 8677 | case 17: /* BASEPRI */ |
9ee6e8bb PB |
8678 | env->v7m.basepri = val & 0xff; |
8679 | break; | |
82845826 | 8680 | case 18: /* BASEPRI_MAX */ |
9ee6e8bb PB |
8681 | val &= 0xff; |
8682 | if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) | |
8683 | env->v7m.basepri = val; | |
8684 | break; | |
82845826 | 8685 | case 19: /* FAULTMASK */ |
4cc35614 PM |
8686 | if (val & 1) { |
8687 | env->daif |= PSTATE_F; | |
8688 | } else { | |
8689 | env->daif &= ~PSTATE_F; | |
8690 | } | |
82845826 | 8691 | break; |
9ee6e8bb | 8692 | case 20: /* CONTROL */ |
abc24d86 MD |
8693 | switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0); |
8694 | env->v7m.control = val & (R_V7M_CONTROL_SPSEL_MASK | | |
8695 | R_V7M_CONTROL_NPRIV_MASK); | |
9ee6e8bb PB |
8696 | break; |
8697 | default: | |
58117c9b MD |
8698 | qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special" |
8699 | " register %d\n", reg); | |
9ee6e8bb PB |
8700 | return; |
8701 | } | |
8702 | } | |
8703 | ||
b5ff1b31 | 8704 | #endif |
6ddbc6e4 | 8705 | |
aca3f40b PM |
8706 | void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) |
8707 | { | |
8708 | /* Implement DC ZVA, which zeroes a fixed-length block of memory. | |
8709 | * Note that we do not implement the (architecturally mandated) | |
8710 | * alignment fault for attempts to use this on Device memory | |
8711 | * (which matches the usual QEMU behaviour of not implementing either | |
8712 | * alignment faults or any memory attribute handling). | |
8713 | */ | |
8714 | ||
8715 | ARMCPU *cpu = arm_env_get_cpu(env); | |
8716 | uint64_t blocklen = 4 << cpu->dcz_blocksize; | |
8717 | uint64_t vaddr = vaddr_in & ~(blocklen - 1); | |
8718 | ||
8719 | #ifndef CONFIG_USER_ONLY | |
8720 | { | |
8721 | /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than | |
8722 | * the block size so we might have to do more than one TLB lookup. | |
8723 | * We know that in fact for any v8 CPU the page size is at least 4K | |
8724 | * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only | |
8725 | * 1K as an artefact of legacy v5 subpage support being present in the | |
8726 | * same QEMU executable. | |
8727 | */ | |
8728 | int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); | |
8729 | void *hostaddr[maxidx]; | |
8730 | int try, i; | |
97ed5ccd | 8731 | unsigned mmu_idx = cpu_mmu_index(env, false); |
3972ef6f | 8732 | TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); |
aca3f40b PM |
8733 | |
8734 | for (try = 0; try < 2; try++) { | |
8735 | ||
8736 | for (i = 0; i < maxidx; i++) { | |
8737 | hostaddr[i] = tlb_vaddr_to_host(env, | |
8738 | vaddr + TARGET_PAGE_SIZE * i, | |
3972ef6f | 8739 | 1, mmu_idx); |
aca3f40b PM |
8740 | if (!hostaddr[i]) { |
8741 | break; | |
8742 | } | |
8743 | } | |
8744 | if (i == maxidx) { | |
8745 | /* If it's all in the TLB it's fair game for just writing to; | |
8746 | * we know we don't need to update dirty status, etc. | |
8747 | */ | |
8748 | for (i = 0; i < maxidx - 1; i++) { | |
8749 | memset(hostaddr[i], 0, TARGET_PAGE_SIZE); | |
8750 | } | |
8751 | memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); | |
8752 | return; | |
8753 | } | |
8754 | /* OK, try a store and see if we can populate the tlb. This | |
8755 | * might cause an exception if the memory isn't writable, | |
8756 | * in which case we will longjmp out of here. We must for | |
8757 | * this purpose use the actual register value passed to us | |
8758 | * so that we get the fault address right. | |
8759 | */ | |
01ecaf43 | 8760 | helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC()); |
aca3f40b PM |
8761 | /* Now we can populate the other TLB entries, if any */ |
8762 | for (i = 0; i < maxidx; i++) { | |
8763 | uint64_t va = vaddr + TARGET_PAGE_SIZE * i; | |
8764 | if (va != (vaddr_in & TARGET_PAGE_MASK)) { | |
01ecaf43 | 8765 | helper_ret_stb_mmu(env, va, 0, oi, GETPC()); |
aca3f40b PM |
8766 | } |
8767 | } | |
8768 | } | |
8769 | ||
8770 | /* Slow path (probably attempt to do this to an I/O device or | |
8771 | * similar, or clearing of a block of code we have translations | |
8772 | * cached for). Just do a series of byte writes as the architecture | |
8773 | * demands. It's not worth trying to use a cpu_physical_memory_map(), | |
8774 | * memset(), unmap() sequence here because: | |
8775 | * + we'd need to account for the blocksize being larger than a page | |
8776 | * + the direct-RAM access case is almost always going to be dealt | |
8777 | * with in the fastpath code above, so there's no speed benefit | |
8778 | * + we would have to deal with the map returning NULL because the | |
8779 | * bounce buffer was in use | |
8780 | */ | |
8781 | for (i = 0; i < blocklen; i++) { | |
01ecaf43 | 8782 | helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC()); |
aca3f40b PM |
8783 | } |
8784 | } | |
8785 | #else | |
8786 | memset(g2h(vaddr), 0, blocklen); | |
8787 | #endif | |
8788 | } | |
8789 | ||
6ddbc6e4 PB |
8790 | /* Note that signed overflow is undefined in C. The following routines are |
8791 | careful to use unsigned types where modulo arithmetic is required. | |
8792 | Failure to do so _will_ break on newer gcc. */ | |
8793 | ||
8794 | /* Signed saturating arithmetic. */ | |
8795 | ||
1654b2d6 | 8796 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
8797 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
8798 | { | |
8799 | uint16_t res; | |
8800 | ||
8801 | res = a + b; | |
8802 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
8803 | if (a & 0x8000) | |
8804 | res = 0x8000; | |
8805 | else | |
8806 | res = 0x7fff; | |
8807 | } | |
8808 | return res; | |
8809 | } | |
8810 | ||
1654b2d6 | 8811 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
8812 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
8813 | { | |
8814 | uint8_t res; | |
8815 | ||
8816 | res = a + b; | |
8817 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
8818 | if (a & 0x80) | |
8819 | res = 0x80; | |
8820 | else | |
8821 | res = 0x7f; | |
8822 | } | |
8823 | return res; | |
8824 | } | |
8825 | ||
1654b2d6 | 8826 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
8827 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
8828 | { | |
8829 | uint16_t res; | |
8830 | ||
8831 | res = a - b; | |
8832 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
8833 | if (a & 0x8000) | |
8834 | res = 0x8000; | |
8835 | else | |
8836 | res = 0x7fff; | |
8837 | } | |
8838 | return res; | |
8839 | } | |
8840 | ||
1654b2d6 | 8841 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
8842 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
8843 | { | |
8844 | uint8_t res; | |
8845 | ||
8846 | res = a - b; | |
8847 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
8848 | if (a & 0x80) | |
8849 | res = 0x80; | |
8850 | else | |
8851 | res = 0x7f; | |
8852 | } | |
8853 | return res; | |
8854 | } | |
8855 | ||
8856 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
8857 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
8858 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
8859 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
8860 | #define PFX q | |
8861 | ||
8862 | #include "op_addsub.h" | |
8863 | ||
8864 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 8865 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
8866 | { |
8867 | uint16_t res; | |
8868 | res = a + b; | |
8869 | if (res < a) | |
8870 | res = 0xffff; | |
8871 | return res; | |
8872 | } | |
8873 | ||
460a09c1 | 8874 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 | 8875 | { |
4c4fd3f8 | 8876 | if (a > b) |
6ddbc6e4 PB |
8877 | return a - b; |
8878 | else | |
8879 | return 0; | |
8880 | } | |
8881 | ||
8882 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
8883 | { | |
8884 | uint8_t res; | |
8885 | res = a + b; | |
8886 | if (res < a) | |
8887 | res = 0xff; | |
8888 | return res; | |
8889 | } | |
8890 | ||
8891 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
8892 | { | |
4c4fd3f8 | 8893 | if (a > b) |
6ddbc6e4 PB |
8894 | return a - b; |
8895 | else | |
8896 | return 0; | |
8897 | } | |
8898 | ||
8899 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
8900 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
8901 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
8902 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
8903 | #define PFX uq | |
8904 | ||
8905 | #include "op_addsub.h" | |
8906 | ||
8907 | /* Signed modulo arithmetic. */ | |
8908 | #define SARITH16(a, b, n, op) do { \ | |
8909 | int32_t sum; \ | |
db6e2e65 | 8910 | sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
6ddbc6e4 PB |
8911 | RESULT(sum, n, 16); \ |
8912 | if (sum >= 0) \ | |
8913 | ge |= 3 << (n * 2); \ | |
8914 | } while(0) | |
8915 | ||
8916 | #define SARITH8(a, b, n, op) do { \ | |
8917 | int32_t sum; \ | |
db6e2e65 | 8918 | sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
6ddbc6e4 PB |
8919 | RESULT(sum, n, 8); \ |
8920 | if (sum >= 0) \ | |
8921 | ge |= 1 << n; \ | |
8922 | } while(0) | |
8923 | ||
8924 | ||
8925 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
8926 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
8927 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
8928 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
8929 | #define PFX s | |
8930 | #define ARITH_GE | |
8931 | ||
8932 | #include "op_addsub.h" | |
8933 | ||
8934 | /* Unsigned modulo arithmetic. */ | |
8935 | #define ADD16(a, b, n) do { \ | |
8936 | uint32_t sum; \ | |
8937 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
8938 | RESULT(sum, n, 16); \ | |
a87aa10b | 8939 | if ((sum >> 16) == 1) \ |
6ddbc6e4 PB |
8940 | ge |= 3 << (n * 2); \ |
8941 | } while(0) | |
8942 | ||
8943 | #define ADD8(a, b, n) do { \ | |
8944 | uint32_t sum; \ | |
8945 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
8946 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
8947 | if ((sum >> 8) == 1) \ |
8948 | ge |= 1 << n; \ | |
6ddbc6e4 PB |
8949 | } while(0) |
8950 | ||
8951 | #define SUB16(a, b, n) do { \ | |
8952 | uint32_t sum; \ | |
8953 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
8954 | RESULT(sum, n, 16); \ | |
8955 | if ((sum >> 16) == 0) \ | |
8956 | ge |= 3 << (n * 2); \ | |
8957 | } while(0) | |
8958 | ||
8959 | #define SUB8(a, b, n) do { \ | |
8960 | uint32_t sum; \ | |
8961 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
8962 | RESULT(sum, n, 8); \ | |
8963 | if ((sum >> 8) == 0) \ | |
a87aa10b | 8964 | ge |= 1 << n; \ |
6ddbc6e4 PB |
8965 | } while(0) |
8966 | ||
8967 | #define PFX u | |
8968 | #define ARITH_GE | |
8969 | ||
8970 | #include "op_addsub.h" | |
8971 | ||
8972 | /* Halved signed arithmetic. */ | |
8973 | #define ADD16(a, b, n) \ | |
8974 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
8975 | #define SUB16(a, b, n) \ | |
8976 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
8977 | #define ADD8(a, b, n) \ | |
8978 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
8979 | #define SUB8(a, b, n) \ | |
8980 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
8981 | #define PFX sh | |
8982 | ||
8983 | #include "op_addsub.h" | |
8984 | ||
8985 | /* Halved unsigned arithmetic. */ | |
8986 | #define ADD16(a, b, n) \ | |
8987 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
8988 | #define SUB16(a, b, n) \ | |
8989 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
8990 | #define ADD8(a, b, n) \ | |
8991 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
8992 | #define SUB8(a, b, n) \ | |
8993 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
8994 | #define PFX uh | |
8995 | ||
8996 | #include "op_addsub.h" | |
8997 | ||
8998 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
8999 | { | |
9000 | if (a > b) | |
9001 | return a - b; | |
9002 | else | |
9003 | return b - a; | |
9004 | } | |
9005 | ||
9006 | /* Unsigned sum of absolute byte differences. */ | |
9007 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
9008 | { | |
9009 | uint32_t sum; | |
9010 | sum = do_usad(a, b); | |
9011 | sum += do_usad(a >> 8, b >> 8); | |
9012 | sum += do_usad(a >> 16, b >>16); | |
9013 | sum += do_usad(a >> 24, b >> 24); | |
9014 | return sum; | |
9015 | } | |
9016 | ||
9017 | /* For ARMv6 SEL instruction. */ | |
9018 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
9019 | { | |
9020 | uint32_t mask; | |
9021 | ||
9022 | mask = 0; | |
9023 | if (flags & 1) | |
9024 | mask |= 0xff; | |
9025 | if (flags & 2) | |
9026 | mask |= 0xff00; | |
9027 | if (flags & 4) | |
9028 | mask |= 0xff0000; | |
9029 | if (flags & 8) | |
9030 | mask |= 0xff000000; | |
9031 | return (a & mask) | (b & ~mask); | |
9032 | } | |
9033 | ||
b90372ad PM |
9034 | /* VFP support. We follow the convention used for VFP instructions: |
9035 | Single precision routines have a "s" suffix, double precision a | |
4373f3ce PB |
9036 | "d" suffix. */ |
9037 | ||
9038 | /* Convert host exception flags to vfp form. */ | |
9039 | static inline int vfp_exceptbits_from_host(int host_bits) | |
9040 | { | |
9041 | int target_bits = 0; | |
9042 | ||
9043 | if (host_bits & float_flag_invalid) | |
9044 | target_bits |= 1; | |
9045 | if (host_bits & float_flag_divbyzero) | |
9046 | target_bits |= 2; | |
9047 | if (host_bits & float_flag_overflow) | |
9048 | target_bits |= 4; | |
36802b6b | 9049 | if (host_bits & (float_flag_underflow | float_flag_output_denormal)) |
4373f3ce PB |
9050 | target_bits |= 8; |
9051 | if (host_bits & float_flag_inexact) | |
9052 | target_bits |= 0x10; | |
cecd8504 PM |
9053 | if (host_bits & float_flag_input_denormal) |
9054 | target_bits |= 0x80; | |
4373f3ce PB |
9055 | return target_bits; |
9056 | } | |
9057 | ||
0ecb72a5 | 9058 | uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) |
4373f3ce PB |
9059 | { |
9060 | int i; | |
9061 | uint32_t fpscr; | |
9062 | ||
9063 | fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) | |
9064 | | (env->vfp.vec_len << 16) | |
9065 | | (env->vfp.vec_stride << 20); | |
9066 | i = get_float_exception_flags(&env->vfp.fp_status); | |
3a492f3a | 9067 | i |= get_float_exception_flags(&env->vfp.standard_fp_status); |
4373f3ce PB |
9068 | fpscr |= vfp_exceptbits_from_host(i); |
9069 | return fpscr; | |
9070 | } | |
9071 | ||
0ecb72a5 | 9072 | uint32_t vfp_get_fpscr(CPUARMState *env) |
01653295 PM |
9073 | { |
9074 | return HELPER(vfp_get_fpscr)(env); | |
9075 | } | |
9076 | ||
4373f3ce PB |
9077 | /* Convert vfp exception flags to target form. */ |
9078 | static inline int vfp_exceptbits_to_host(int target_bits) | |
9079 | { | |
9080 | int host_bits = 0; | |
9081 | ||
9082 | if (target_bits & 1) | |
9083 | host_bits |= float_flag_invalid; | |
9084 | if (target_bits & 2) | |
9085 | host_bits |= float_flag_divbyzero; | |
9086 | if (target_bits & 4) | |
9087 | host_bits |= float_flag_overflow; | |
9088 | if (target_bits & 8) | |
9089 | host_bits |= float_flag_underflow; | |
9090 | if (target_bits & 0x10) | |
9091 | host_bits |= float_flag_inexact; | |
cecd8504 PM |
9092 | if (target_bits & 0x80) |
9093 | host_bits |= float_flag_input_denormal; | |
4373f3ce PB |
9094 | return host_bits; |
9095 | } | |
9096 | ||
0ecb72a5 | 9097 | void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) |
4373f3ce PB |
9098 | { |
9099 | int i; | |
9100 | uint32_t changed; | |
9101 | ||
9102 | changed = env->vfp.xregs[ARM_VFP_FPSCR]; | |
9103 | env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); | |
9104 | env->vfp.vec_len = (val >> 16) & 7; | |
9105 | env->vfp.vec_stride = (val >> 20) & 3; | |
9106 | ||
9107 | changed ^= val; | |
9108 | if (changed & (3 << 22)) { | |
9109 | i = (val >> 22) & 3; | |
9110 | switch (i) { | |
4d3da0f3 | 9111 | case FPROUNDING_TIEEVEN: |
4373f3ce PB |
9112 | i = float_round_nearest_even; |
9113 | break; | |
4d3da0f3 | 9114 | case FPROUNDING_POSINF: |
4373f3ce PB |
9115 | i = float_round_up; |
9116 | break; | |
4d3da0f3 | 9117 | case FPROUNDING_NEGINF: |
4373f3ce PB |
9118 | i = float_round_down; |
9119 | break; | |
4d3da0f3 | 9120 | case FPROUNDING_ZERO: |
4373f3ce PB |
9121 | i = float_round_to_zero; |
9122 | break; | |
9123 | } | |
9124 | set_float_rounding_mode(i, &env->vfp.fp_status); | |
9125 | } | |
cecd8504 | 9126 | if (changed & (1 << 24)) { |
fe76d976 | 9127 | set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
cecd8504 PM |
9128 | set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
9129 | } | |
5c7908ed PB |
9130 | if (changed & (1 << 25)) |
9131 | set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); | |
4373f3ce | 9132 | |
b12c390b | 9133 | i = vfp_exceptbits_to_host(val); |
4373f3ce | 9134 | set_float_exception_flags(i, &env->vfp.fp_status); |
3a492f3a | 9135 | set_float_exception_flags(0, &env->vfp.standard_fp_status); |
4373f3ce PB |
9136 | } |
9137 | ||
0ecb72a5 | 9138 | void vfp_set_fpscr(CPUARMState *env, uint32_t val) |
01653295 PM |
9139 | { |
9140 | HELPER(vfp_set_fpscr)(env, val); | |
9141 | } | |
9142 | ||
4373f3ce PB |
9143 | #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) |
9144 | ||
9145 | #define VFP_BINOP(name) \ | |
ae1857ec | 9146 | float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ |
4373f3ce | 9147 | { \ |
ae1857ec PM |
9148 | float_status *fpst = fpstp; \ |
9149 | return float32_ ## name(a, b, fpst); \ | |
4373f3ce | 9150 | } \ |
ae1857ec | 9151 | float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ |
4373f3ce | 9152 | { \ |
ae1857ec PM |
9153 | float_status *fpst = fpstp; \ |
9154 | return float64_ ## name(a, b, fpst); \ | |
4373f3ce PB |
9155 | } |
9156 | VFP_BINOP(add) | |
9157 | VFP_BINOP(sub) | |
9158 | VFP_BINOP(mul) | |
9159 | VFP_BINOP(div) | |
f71a2ae5 PM |
9160 | VFP_BINOP(min) |
9161 | VFP_BINOP(max) | |
9162 | VFP_BINOP(minnum) | |
9163 | VFP_BINOP(maxnum) | |
4373f3ce PB |
9164 | #undef VFP_BINOP |
9165 | ||
9166 | float32 VFP_HELPER(neg, s)(float32 a) | |
9167 | { | |
9168 | return float32_chs(a); | |
9169 | } | |
9170 | ||
9171 | float64 VFP_HELPER(neg, d)(float64 a) | |
9172 | { | |
66230e0d | 9173 | return float64_chs(a); |
4373f3ce PB |
9174 | } |
9175 | ||
9176 | float32 VFP_HELPER(abs, s)(float32 a) | |
9177 | { | |
9178 | return float32_abs(a); | |
9179 | } | |
9180 | ||
9181 | float64 VFP_HELPER(abs, d)(float64 a) | |
9182 | { | |
66230e0d | 9183 | return float64_abs(a); |
4373f3ce PB |
9184 | } |
9185 | ||
0ecb72a5 | 9186 | float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) |
4373f3ce PB |
9187 | { |
9188 | return float32_sqrt(a, &env->vfp.fp_status); | |
9189 | } | |
9190 | ||
0ecb72a5 | 9191 | float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) |
4373f3ce PB |
9192 | { |
9193 | return float64_sqrt(a, &env->vfp.fp_status); | |
9194 | } | |
9195 | ||
9196 | /* XXX: check quiet/signaling case */ | |
9197 | #define DO_VFP_cmp(p, type) \ | |
0ecb72a5 | 9198 | void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
9199 | { \ |
9200 | uint32_t flags; \ | |
9201 | switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ | |
9202 | case 0: flags = 0x6; break; \ | |
9203 | case -1: flags = 0x8; break; \ | |
9204 | case 1: flags = 0x2; break; \ | |
9205 | default: case 2: flags = 0x3; break; \ | |
9206 | } \ | |
9207 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
9208 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
9209 | } \ | |
0ecb72a5 | 9210 | void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
9211 | { \ |
9212 | uint32_t flags; \ | |
9213 | switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ | |
9214 | case 0: flags = 0x6; break; \ | |
9215 | case -1: flags = 0x8; break; \ | |
9216 | case 1: flags = 0x2; break; \ | |
9217 | default: case 2: flags = 0x3; break; \ | |
9218 | } \ | |
9219 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
9220 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
9221 | } | |
9222 | DO_VFP_cmp(s, float32) | |
9223 | DO_VFP_cmp(d, float64) | |
9224 | #undef DO_VFP_cmp | |
9225 | ||
5500b06c | 9226 | /* Integer to float and float to integer conversions */ |
4373f3ce | 9227 | |
5500b06c PM |
9228 | #define CONV_ITOF(name, fsz, sign) \ |
9229 | float##fsz HELPER(name)(uint32_t x, void *fpstp) \ | |
9230 | { \ | |
9231 | float_status *fpst = fpstp; \ | |
85836979 | 9232 | return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ |
4373f3ce PB |
9233 | } |
9234 | ||
5500b06c PM |
9235 | #define CONV_FTOI(name, fsz, sign, round) \ |
9236 | uint32_t HELPER(name)(float##fsz x, void *fpstp) \ | |
9237 | { \ | |
9238 | float_status *fpst = fpstp; \ | |
9239 | if (float##fsz##_is_any_nan(x)) { \ | |
9240 | float_raise(float_flag_invalid, fpst); \ | |
9241 | return 0; \ | |
9242 | } \ | |
9243 | return float##fsz##_to_##sign##int32##round(x, fpst); \ | |
4373f3ce PB |
9244 | } |
9245 | ||
5500b06c PM |
9246 | #define FLOAT_CONVS(name, p, fsz, sign) \ |
9247 | CONV_ITOF(vfp_##name##to##p, fsz, sign) \ | |
9248 | CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ | |
9249 | CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) | |
4373f3ce | 9250 | |
5500b06c PM |
9251 | FLOAT_CONVS(si, s, 32, ) |
9252 | FLOAT_CONVS(si, d, 64, ) | |
9253 | FLOAT_CONVS(ui, s, 32, u) | |
9254 | FLOAT_CONVS(ui, d, 64, u) | |
4373f3ce | 9255 | |
5500b06c PM |
9256 | #undef CONV_ITOF |
9257 | #undef CONV_FTOI | |
9258 | #undef FLOAT_CONVS | |
4373f3ce PB |
9259 | |
9260 | /* floating point conversion */ | |
0ecb72a5 | 9261 | float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) |
4373f3ce | 9262 | { |
2d627737 PM |
9263 | float64 r = float32_to_float64(x, &env->vfp.fp_status); |
9264 | /* ARM requires that S<->D conversion of any kind of NaN generates | |
9265 | * a quiet NaN by forcing the most significant frac bit to 1. | |
9266 | */ | |
af39bc8c | 9267 | return float64_maybe_silence_nan(r, &env->vfp.fp_status); |
4373f3ce PB |
9268 | } |
9269 | ||
0ecb72a5 | 9270 | float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) |
4373f3ce | 9271 | { |
2d627737 PM |
9272 | float32 r = float64_to_float32(x, &env->vfp.fp_status); |
9273 | /* ARM requires that S<->D conversion of any kind of NaN generates | |
9274 | * a quiet NaN by forcing the most significant frac bit to 1. | |
9275 | */ | |
af39bc8c | 9276 | return float32_maybe_silence_nan(r, &env->vfp.fp_status); |
4373f3ce PB |
9277 | } |
9278 | ||
9279 | /* VFP3 fixed point conversion. */ | |
16d5b3ca | 9280 | #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ |
8ed697e8 WN |
9281 | float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ |
9282 | void *fpstp) \ | |
4373f3ce | 9283 | { \ |
5500b06c | 9284 | float_status *fpst = fpstp; \ |
622465e1 | 9285 | float##fsz tmp; \ |
8ed697e8 | 9286 | tmp = itype##_to_##float##fsz(x, fpst); \ |
5500b06c | 9287 | return float##fsz##_scalbn(tmp, -(int)shift, fpst); \ |
16d5b3ca WN |
9288 | } |
9289 | ||
abe66f70 PM |
9290 | /* Notice that we want only input-denormal exception flags from the |
9291 | * scalbn operation: the other possible flags (overflow+inexact if | |
9292 | * we overflow to infinity, output-denormal) aren't correct for the | |
9293 | * complete scale-and-convert operation. | |
9294 | */ | |
16d5b3ca WN |
9295 | #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \ |
9296 | uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \ | |
9297 | uint32_t shift, \ | |
9298 | void *fpstp) \ | |
4373f3ce | 9299 | { \ |
5500b06c | 9300 | float_status *fpst = fpstp; \ |
abe66f70 | 9301 | int old_exc_flags = get_float_exception_flags(fpst); \ |
622465e1 PM |
9302 | float##fsz tmp; \ |
9303 | if (float##fsz##_is_any_nan(x)) { \ | |
5500b06c | 9304 | float_raise(float_flag_invalid, fpst); \ |
622465e1 | 9305 | return 0; \ |
09d9487f | 9306 | } \ |
5500b06c | 9307 | tmp = float##fsz##_scalbn(x, shift, fpst); \ |
abe66f70 PM |
9308 | old_exc_flags |= get_float_exception_flags(fpst) \ |
9309 | & float_flag_input_denormal; \ | |
9310 | set_float_exception_flags(old_exc_flags, fpst); \ | |
16d5b3ca | 9311 | return float##fsz##_to_##itype##round(tmp, fpst); \ |
622465e1 PM |
9312 | } |
9313 | ||
16d5b3ca WN |
9314 | #define VFP_CONV_FIX(name, p, fsz, isz, itype) \ |
9315 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
3c6a074a WN |
9316 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \ |
9317 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) | |
9318 | ||
9319 | #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \ | |
9320 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
9321 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) | |
16d5b3ca | 9322 | |
8ed697e8 WN |
9323 | VFP_CONV_FIX(sh, d, 64, 64, int16) |
9324 | VFP_CONV_FIX(sl, d, 64, 64, int32) | |
3c6a074a | 9325 | VFP_CONV_FIX_A64(sq, d, 64, 64, int64) |
8ed697e8 WN |
9326 | VFP_CONV_FIX(uh, d, 64, 64, uint16) |
9327 | VFP_CONV_FIX(ul, d, 64, 64, uint32) | |
3c6a074a | 9328 | VFP_CONV_FIX_A64(uq, d, 64, 64, uint64) |
8ed697e8 WN |
9329 | VFP_CONV_FIX(sh, s, 32, 32, int16) |
9330 | VFP_CONV_FIX(sl, s, 32, 32, int32) | |
3c6a074a | 9331 | VFP_CONV_FIX_A64(sq, s, 32, 64, int64) |
8ed697e8 WN |
9332 | VFP_CONV_FIX(uh, s, 32, 32, uint16) |
9333 | VFP_CONV_FIX(ul, s, 32, 32, uint32) | |
3c6a074a | 9334 | VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) |
4373f3ce | 9335 | #undef VFP_CONV_FIX |
16d5b3ca WN |
9336 | #undef VFP_CONV_FIX_FLOAT |
9337 | #undef VFP_CONV_FLOAT_FIX_ROUND | |
4373f3ce | 9338 | |
52a1f6a3 AG |
9339 | /* Set the current fp rounding mode and return the old one. |
9340 | * The argument is a softfloat float_round_ value. | |
9341 | */ | |
9342 | uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env) | |
9343 | { | |
9344 | float_status *fp_status = &env->vfp.fp_status; | |
9345 | ||
9346 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
9347 | set_float_rounding_mode(rmode, fp_status); | |
9348 | ||
9349 | return prev_rmode; | |
9350 | } | |
9351 | ||
43630e58 WN |
9352 | /* Set the current fp rounding mode in the standard fp status and return |
9353 | * the old one. This is for NEON instructions that need to change the | |
9354 | * rounding mode but wish to use the standard FPSCR values for everything | |
9355 | * else. Always set the rounding mode back to the correct value after | |
9356 | * modifying it. | |
9357 | * The argument is a softfloat float_round_ value. | |
9358 | */ | |
9359 | uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) | |
9360 | { | |
9361 | float_status *fp_status = &env->vfp.standard_fp_status; | |
9362 | ||
9363 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
9364 | set_float_rounding_mode(rmode, fp_status); | |
9365 | ||
9366 | return prev_rmode; | |
9367 | } | |
9368 | ||
60011498 | 9369 | /* Half precision conversions. */ |
0ecb72a5 | 9370 | static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s) |
60011498 | 9371 | { |
60011498 | 9372 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
fb91678d PM |
9373 | float32 r = float16_to_float32(make_float16(a), ieee, s); |
9374 | if (ieee) { | |
af39bc8c | 9375 | return float32_maybe_silence_nan(r, s); |
fb91678d PM |
9376 | } |
9377 | return r; | |
60011498 PB |
9378 | } |
9379 | ||
0ecb72a5 | 9380 | static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s) |
60011498 | 9381 | { |
60011498 | 9382 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
fb91678d PM |
9383 | float16 r = float32_to_float16(a, ieee, s); |
9384 | if (ieee) { | |
af39bc8c | 9385 | r = float16_maybe_silence_nan(r, s); |
fb91678d PM |
9386 | } |
9387 | return float16_val(r); | |
60011498 PB |
9388 | } |
9389 | ||
0ecb72a5 | 9390 | float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
2d981da7 PM |
9391 | { |
9392 | return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status); | |
9393 | } | |
9394 | ||
0ecb72a5 | 9395 | uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
2d981da7 PM |
9396 | { |
9397 | return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status); | |
9398 | } | |
9399 | ||
0ecb72a5 | 9400 | float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
2d981da7 PM |
9401 | { |
9402 | return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status); | |
9403 | } | |
9404 | ||
0ecb72a5 | 9405 | uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
2d981da7 PM |
9406 | { |
9407 | return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status); | |
9408 | } | |
9409 | ||
8900aad2 PM |
9410 | float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env) |
9411 | { | |
9412 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
9413 | float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status); | |
9414 | if (ieee) { | |
af39bc8c | 9415 | return float64_maybe_silence_nan(r, &env->vfp.fp_status); |
8900aad2 PM |
9416 | } |
9417 | return r; | |
9418 | } | |
9419 | ||
9420 | uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env) | |
9421 | { | |
9422 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
9423 | float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status); | |
9424 | if (ieee) { | |
af39bc8c | 9425 | r = float16_maybe_silence_nan(r, &env->vfp.fp_status); |
8900aad2 PM |
9426 | } |
9427 | return float16_val(r); | |
9428 | } | |
9429 | ||
dda3ec49 | 9430 | #define float32_two make_float32(0x40000000) |
6aae3df1 PM |
9431 | #define float32_three make_float32(0x40400000) |
9432 | #define float32_one_point_five make_float32(0x3fc00000) | |
dda3ec49 | 9433 | |
0ecb72a5 | 9434 | float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 9435 | { |
dda3ec49 PM |
9436 | float_status *s = &env->vfp.standard_fp_status; |
9437 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
9438 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
9439 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
9440 | float_raise(float_flag_input_denormal, s); | |
9441 | } | |
dda3ec49 PM |
9442 | return float32_two; |
9443 | } | |
9444 | return float32_sub(float32_two, float32_mul(a, b, s), s); | |
4373f3ce PB |
9445 | } |
9446 | ||
0ecb72a5 | 9447 | float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 9448 | { |
71826966 | 9449 | float_status *s = &env->vfp.standard_fp_status; |
9ea62f57 PM |
9450 | float32 product; |
9451 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
9452 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
9453 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
9454 | float_raise(float_flag_input_denormal, s); | |
9455 | } | |
6aae3df1 | 9456 | return float32_one_point_five; |
9ea62f57 | 9457 | } |
6aae3df1 PM |
9458 | product = float32_mul(a, b, s); |
9459 | return float32_div(float32_sub(float32_three, product, s), float32_two, s); | |
4373f3ce PB |
9460 | } |
9461 | ||
8f8e3aa4 PB |
9462 | /* NEON helpers. */ |
9463 | ||
56bf4fe2 CL |
9464 | /* Constants 256 and 512 are used in some helpers; we avoid relying on |
9465 | * int->float conversions at run-time. */ | |
9466 | #define float64_256 make_float64(0x4070000000000000LL) | |
9467 | #define float64_512 make_float64(0x4080000000000000LL) | |
b6d4443a AB |
9468 | #define float32_maxnorm make_float32(0x7f7fffff) |
9469 | #define float64_maxnorm make_float64(0x7fefffffffffffffLL) | |
56bf4fe2 | 9470 | |
b6d4443a AB |
9471 | /* Reciprocal functions |
9472 | * | |
9473 | * The algorithm that must be used to calculate the estimate | |
9474 | * is specified by the ARM ARM, see FPRecipEstimate() | |
fe0e4872 | 9475 | */ |
b6d4443a AB |
9476 | |
9477 | static float64 recip_estimate(float64 a, float_status *real_fp_status) | |
fe0e4872 | 9478 | { |
1146a817 PM |
9479 | /* These calculations mustn't set any fp exception flags, |
9480 | * so we use a local copy of the fp_status. | |
9481 | */ | |
b6d4443a | 9482 | float_status dummy_status = *real_fp_status; |
1146a817 | 9483 | float_status *s = &dummy_status; |
fe0e4872 CL |
9484 | /* q = (int)(a * 512.0) */ |
9485 | float64 q = float64_mul(float64_512, a, s); | |
9486 | int64_t q_int = float64_to_int64_round_to_zero(q, s); | |
9487 | ||
9488 | /* r = 1.0 / (((double)q + 0.5) / 512.0) */ | |
9489 | q = int64_to_float64(q_int, s); | |
9490 | q = float64_add(q, float64_half, s); | |
9491 | q = float64_div(q, float64_512, s); | |
9492 | q = float64_div(float64_one, q, s); | |
9493 | ||
9494 | /* s = (int)(256.0 * r + 0.5) */ | |
9495 | q = float64_mul(q, float64_256, s); | |
9496 | q = float64_add(q, float64_half, s); | |
9497 | q_int = float64_to_int64_round_to_zero(q, s); | |
9498 | ||
9499 | /* return (double)s / 256.0 */ | |
9500 | return float64_div(int64_to_float64(q_int, s), float64_256, s); | |
9501 | } | |
9502 | ||
b6d4443a AB |
9503 | /* Common wrapper to call recip_estimate */ |
9504 | static float64 call_recip_estimate(float64 num, int off, float_status *fpst) | |
4373f3ce | 9505 | { |
b6d4443a AB |
9506 | uint64_t val64 = float64_val(num); |
9507 | uint64_t frac = extract64(val64, 0, 52); | |
9508 | int64_t exp = extract64(val64, 52, 11); | |
9509 | uint64_t sbit; | |
9510 | float64 scaled, estimate; | |
fe0e4872 | 9511 | |
b6d4443a AB |
9512 | /* Generate the scaled number for the estimate function */ |
9513 | if (exp == 0) { | |
9514 | if (extract64(frac, 51, 1) == 0) { | |
9515 | exp = -1; | |
9516 | frac = extract64(frac, 0, 50) << 2; | |
9517 | } else { | |
9518 | frac = extract64(frac, 0, 51) << 1; | |
9519 | } | |
9520 | } | |
fe0e4872 | 9521 | |
b6d4443a AB |
9522 | /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */ |
9523 | scaled = make_float64((0x3feULL << 52) | |
9524 | | extract64(frac, 44, 8) << 44); | |
9525 | ||
9526 | estimate = recip_estimate(scaled, fpst); | |
9527 | ||
9528 | /* Build new result */ | |
9529 | val64 = float64_val(estimate); | |
9530 | sbit = 0x8000000000000000ULL & val64; | |
9531 | exp = off - exp; | |
9532 | frac = extract64(val64, 0, 52); | |
9533 | ||
9534 | if (exp == 0) { | |
9535 | frac = 1ULL << 51 | extract64(frac, 1, 51); | |
9536 | } else if (exp == -1) { | |
9537 | frac = 1ULL << 50 | extract64(frac, 2, 50); | |
9538 | exp = 0; | |
9539 | } | |
9540 | ||
9541 | return make_float64(sbit | (exp << 52) | frac); | |
9542 | } | |
9543 | ||
9544 | static bool round_to_inf(float_status *fpst, bool sign_bit) | |
9545 | { | |
9546 | switch (fpst->float_rounding_mode) { | |
9547 | case float_round_nearest_even: /* Round to Nearest */ | |
9548 | return true; | |
9549 | case float_round_up: /* Round to +Inf */ | |
9550 | return !sign_bit; | |
9551 | case float_round_down: /* Round to -Inf */ | |
9552 | return sign_bit; | |
9553 | case float_round_to_zero: /* Round to Zero */ | |
9554 | return false; | |
9555 | } | |
9556 | ||
9557 | g_assert_not_reached(); | |
9558 | } | |
9559 | ||
9560 | float32 HELPER(recpe_f32)(float32 input, void *fpstp) | |
9561 | { | |
9562 | float_status *fpst = fpstp; | |
9563 | float32 f32 = float32_squash_input_denormal(input, fpst); | |
9564 | uint32_t f32_val = float32_val(f32); | |
9565 | uint32_t f32_sbit = 0x80000000ULL & f32_val; | |
9566 | int32_t f32_exp = extract32(f32_val, 23, 8); | |
9567 | uint32_t f32_frac = extract32(f32_val, 0, 23); | |
9568 | float64 f64, r64; | |
9569 | uint64_t r64_val; | |
9570 | int64_t r64_exp; | |
9571 | uint64_t r64_frac; | |
9572 | ||
9573 | if (float32_is_any_nan(f32)) { | |
9574 | float32 nan = f32; | |
af39bc8c | 9575 | if (float32_is_signaling_nan(f32, fpst)) { |
b6d4443a | 9576 | float_raise(float_flag_invalid, fpst); |
af39bc8c | 9577 | nan = float32_maybe_silence_nan(f32, fpst); |
fe0e4872 | 9578 | } |
b6d4443a | 9579 | if (fpst->default_nan_mode) { |
af39bc8c | 9580 | nan = float32_default_nan(fpst); |
43fe9bdb | 9581 | } |
b6d4443a AB |
9582 | return nan; |
9583 | } else if (float32_is_infinity(f32)) { | |
9584 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
9585 | } else if (float32_is_zero(f32)) { | |
9586 | float_raise(float_flag_divbyzero, fpst); | |
9587 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
9588 | } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) { | |
9589 | /* Abs(value) < 2.0^-128 */ | |
9590 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
9591 | if (round_to_inf(fpst, f32_sbit)) { | |
9592 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
9593 | } else { | |
9594 | return float32_set_sign(float32_maxnorm, float32_is_neg(f32)); | |
9595 | } | |
9596 | } else if (f32_exp >= 253 && fpst->flush_to_zero) { | |
9597 | float_raise(float_flag_underflow, fpst); | |
9598 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
fe0e4872 CL |
9599 | } |
9600 | ||
fe0e4872 | 9601 | |
b6d4443a AB |
9602 | f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29); |
9603 | r64 = call_recip_estimate(f64, 253, fpst); | |
9604 | r64_val = float64_val(r64); | |
9605 | r64_exp = extract64(r64_val, 52, 11); | |
9606 | r64_frac = extract64(r64_val, 0, 52); | |
9607 | ||
9608 | /* result = sign : result_exp<7:0> : fraction<51:29>; */ | |
9609 | return make_float32(f32_sbit | | |
9610 | (r64_exp & 0xff) << 23 | | |
9611 | extract64(r64_frac, 29, 24)); | |
9612 | } | |
9613 | ||
9614 | float64 HELPER(recpe_f64)(float64 input, void *fpstp) | |
9615 | { | |
9616 | float_status *fpst = fpstp; | |
9617 | float64 f64 = float64_squash_input_denormal(input, fpst); | |
9618 | uint64_t f64_val = float64_val(f64); | |
9619 | uint64_t f64_sbit = 0x8000000000000000ULL & f64_val; | |
9620 | int64_t f64_exp = extract64(f64_val, 52, 11); | |
9621 | float64 r64; | |
9622 | uint64_t r64_val; | |
9623 | int64_t r64_exp; | |
9624 | uint64_t r64_frac; | |
9625 | ||
9626 | /* Deal with any special cases */ | |
9627 | if (float64_is_any_nan(f64)) { | |
9628 | float64 nan = f64; | |
af39bc8c | 9629 | if (float64_is_signaling_nan(f64, fpst)) { |
b6d4443a | 9630 | float_raise(float_flag_invalid, fpst); |
af39bc8c | 9631 | nan = float64_maybe_silence_nan(f64, fpst); |
b6d4443a AB |
9632 | } |
9633 | if (fpst->default_nan_mode) { | |
af39bc8c | 9634 | nan = float64_default_nan(fpst); |
b6d4443a AB |
9635 | } |
9636 | return nan; | |
9637 | } else if (float64_is_infinity(f64)) { | |
9638 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
9639 | } else if (float64_is_zero(f64)) { | |
9640 | float_raise(float_flag_divbyzero, fpst); | |
9641 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
9642 | } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { | |
9643 | /* Abs(value) < 2.0^-1024 */ | |
9644 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
9645 | if (round_to_inf(fpst, f64_sbit)) { | |
9646 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
9647 | } else { | |
9648 | return float64_set_sign(float64_maxnorm, float64_is_neg(f64)); | |
9649 | } | |
fc1792e9 | 9650 | } else if (f64_exp >= 2045 && fpst->flush_to_zero) { |
b6d4443a AB |
9651 | float_raise(float_flag_underflow, fpst); |
9652 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
9653 | } | |
fe0e4872 | 9654 | |
b6d4443a AB |
9655 | r64 = call_recip_estimate(f64, 2045, fpst); |
9656 | r64_val = float64_val(r64); | |
9657 | r64_exp = extract64(r64_val, 52, 11); | |
9658 | r64_frac = extract64(r64_val, 0, 52); | |
fe0e4872 | 9659 | |
b6d4443a AB |
9660 | /* result = sign : result_exp<10:0> : fraction<51:0> */ |
9661 | return make_float64(f64_sbit | | |
9662 | ((r64_exp & 0x7ff) << 52) | | |
9663 | r64_frac); | |
4373f3ce PB |
9664 | } |
9665 | ||
e07be5d2 CL |
9666 | /* The algorithm that must be used to calculate the estimate |
9667 | * is specified by the ARM ARM. | |
9668 | */ | |
c2fb418e | 9669 | static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status) |
e07be5d2 | 9670 | { |
1146a817 PM |
9671 | /* These calculations mustn't set any fp exception flags, |
9672 | * so we use a local copy of the fp_status. | |
9673 | */ | |
c2fb418e | 9674 | float_status dummy_status = *real_fp_status; |
1146a817 | 9675 | float_status *s = &dummy_status; |
e07be5d2 CL |
9676 | float64 q; |
9677 | int64_t q_int; | |
9678 | ||
9679 | if (float64_lt(a, float64_half, s)) { | |
9680 | /* range 0.25 <= a < 0.5 */ | |
9681 | ||
9682 | /* a in units of 1/512 rounded down */ | |
9683 | /* q0 = (int)(a * 512.0); */ | |
9684 | q = float64_mul(float64_512, a, s); | |
9685 | q_int = float64_to_int64_round_to_zero(q, s); | |
9686 | ||
9687 | /* reciprocal root r */ | |
9688 | /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */ | |
9689 | q = int64_to_float64(q_int, s); | |
9690 | q = float64_add(q, float64_half, s); | |
9691 | q = float64_div(q, float64_512, s); | |
9692 | q = float64_sqrt(q, s); | |
9693 | q = float64_div(float64_one, q, s); | |
9694 | } else { | |
9695 | /* range 0.5 <= a < 1.0 */ | |
9696 | ||
9697 | /* a in units of 1/256 rounded down */ | |
9698 | /* q1 = (int)(a * 256.0); */ | |
9699 | q = float64_mul(float64_256, a, s); | |
9700 | int64_t q_int = float64_to_int64_round_to_zero(q, s); | |
9701 | ||
9702 | /* reciprocal root r */ | |
9703 | /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */ | |
9704 | q = int64_to_float64(q_int, s); | |
9705 | q = float64_add(q, float64_half, s); | |
9706 | q = float64_div(q, float64_256, s); | |
9707 | q = float64_sqrt(q, s); | |
9708 | q = float64_div(float64_one, q, s); | |
9709 | } | |
9710 | /* r in units of 1/256 rounded to nearest */ | |
9711 | /* s = (int)(256.0 * r + 0.5); */ | |
9712 | ||
9713 | q = float64_mul(q, float64_256,s ); | |
9714 | q = float64_add(q, float64_half, s); | |
9715 | q_int = float64_to_int64_round_to_zero(q, s); | |
9716 | ||
9717 | /* return (double)s / 256.0;*/ | |
9718 | return float64_div(int64_to_float64(q_int, s), float64_256, s); | |
9719 | } | |
9720 | ||
c2fb418e | 9721 | float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) |
4373f3ce | 9722 | { |
c2fb418e AB |
9723 | float_status *s = fpstp; |
9724 | float32 f32 = float32_squash_input_denormal(input, s); | |
9725 | uint32_t val = float32_val(f32); | |
9726 | uint32_t f32_sbit = 0x80000000 & val; | |
9727 | int32_t f32_exp = extract32(val, 23, 8); | |
9728 | uint32_t f32_frac = extract32(val, 0, 23); | |
9729 | uint64_t f64_frac; | |
9730 | uint64_t val64; | |
e07be5d2 CL |
9731 | int result_exp; |
9732 | float64 f64; | |
e07be5d2 | 9733 | |
c2fb418e AB |
9734 | if (float32_is_any_nan(f32)) { |
9735 | float32 nan = f32; | |
af39bc8c | 9736 | if (float32_is_signaling_nan(f32, s)) { |
e07be5d2 | 9737 | float_raise(float_flag_invalid, s); |
af39bc8c | 9738 | nan = float32_maybe_silence_nan(f32, s); |
e07be5d2 | 9739 | } |
c2fb418e | 9740 | if (s->default_nan_mode) { |
af39bc8c | 9741 | nan = float32_default_nan(s); |
43fe9bdb | 9742 | } |
c2fb418e AB |
9743 | return nan; |
9744 | } else if (float32_is_zero(f32)) { | |
e07be5d2 | 9745 | float_raise(float_flag_divbyzero, s); |
c2fb418e AB |
9746 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); |
9747 | } else if (float32_is_neg(f32)) { | |
e07be5d2 | 9748 | float_raise(float_flag_invalid, s); |
af39bc8c | 9749 | return float32_default_nan(s); |
c2fb418e | 9750 | } else if (float32_is_infinity(f32)) { |
e07be5d2 CL |
9751 | return float32_zero; |
9752 | } | |
9753 | ||
c2fb418e | 9754 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, |
e07be5d2 | 9755 | * preserving the parity of the exponent. */ |
c2fb418e AB |
9756 | |
9757 | f64_frac = ((uint64_t) f32_frac) << 29; | |
9758 | if (f32_exp == 0) { | |
9759 | while (extract64(f64_frac, 51, 1) == 0) { | |
9760 | f64_frac = f64_frac << 1; | |
9761 | f32_exp = f32_exp-1; | |
9762 | } | |
9763 | f64_frac = extract64(f64_frac, 0, 51) << 1; | |
9764 | } | |
9765 | ||
9766 | if (extract64(f32_exp, 0, 1) == 0) { | |
9767 | f64 = make_float64(((uint64_t) f32_sbit) << 32 | |
e07be5d2 | 9768 | | (0x3feULL << 52) |
c2fb418e | 9769 | | f64_frac); |
e07be5d2 | 9770 | } else { |
c2fb418e | 9771 | f64 = make_float64(((uint64_t) f32_sbit) << 32 |
e07be5d2 | 9772 | | (0x3fdULL << 52) |
c2fb418e | 9773 | | f64_frac); |
e07be5d2 CL |
9774 | } |
9775 | ||
c2fb418e | 9776 | result_exp = (380 - f32_exp) / 2; |
e07be5d2 | 9777 | |
c2fb418e | 9778 | f64 = recip_sqrt_estimate(f64, s); |
e07be5d2 CL |
9779 | |
9780 | val64 = float64_val(f64); | |
9781 | ||
26cc6abf | 9782 | val = ((result_exp & 0xff) << 23) |
e07be5d2 CL |
9783 | | ((val64 >> 29) & 0x7fffff); |
9784 | return make_float32(val); | |
4373f3ce PB |
9785 | } |
9786 | ||
c2fb418e AB |
9787 | float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) |
9788 | { | |
9789 | float_status *s = fpstp; | |
9790 | float64 f64 = float64_squash_input_denormal(input, s); | |
9791 | uint64_t val = float64_val(f64); | |
9792 | uint64_t f64_sbit = 0x8000000000000000ULL & val; | |
9793 | int64_t f64_exp = extract64(val, 52, 11); | |
9794 | uint64_t f64_frac = extract64(val, 0, 52); | |
9795 | int64_t result_exp; | |
9796 | uint64_t result_frac; | |
9797 | ||
9798 | if (float64_is_any_nan(f64)) { | |
9799 | float64 nan = f64; | |
af39bc8c | 9800 | if (float64_is_signaling_nan(f64, s)) { |
c2fb418e | 9801 | float_raise(float_flag_invalid, s); |
af39bc8c | 9802 | nan = float64_maybe_silence_nan(f64, s); |
c2fb418e AB |
9803 | } |
9804 | if (s->default_nan_mode) { | |
af39bc8c | 9805 | nan = float64_default_nan(s); |
c2fb418e AB |
9806 | } |
9807 | return nan; | |
9808 | } else if (float64_is_zero(f64)) { | |
9809 | float_raise(float_flag_divbyzero, s); | |
9810 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
9811 | } else if (float64_is_neg(f64)) { | |
9812 | float_raise(float_flag_invalid, s); | |
af39bc8c | 9813 | return float64_default_nan(s); |
c2fb418e AB |
9814 | } else if (float64_is_infinity(f64)) { |
9815 | return float64_zero; | |
9816 | } | |
9817 | ||
9818 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, | |
9819 | * preserving the parity of the exponent. */ | |
9820 | ||
9821 | if (f64_exp == 0) { | |
9822 | while (extract64(f64_frac, 51, 1) == 0) { | |
9823 | f64_frac = f64_frac << 1; | |
9824 | f64_exp = f64_exp - 1; | |
9825 | } | |
9826 | f64_frac = extract64(f64_frac, 0, 51) << 1; | |
9827 | } | |
9828 | ||
9829 | if (extract64(f64_exp, 0, 1) == 0) { | |
9830 | f64 = make_float64(f64_sbit | |
9831 | | (0x3feULL << 52) | |
9832 | | f64_frac); | |
9833 | } else { | |
9834 | f64 = make_float64(f64_sbit | |
9835 | | (0x3fdULL << 52) | |
9836 | | f64_frac); | |
9837 | } | |
9838 | ||
9839 | result_exp = (3068 - f64_exp) / 2; | |
9840 | ||
9841 | f64 = recip_sqrt_estimate(f64, s); | |
9842 | ||
9843 | result_frac = extract64(float64_val(f64), 0, 52); | |
9844 | ||
9845 | return make_float64(f64_sbit | | |
9846 | ((result_exp & 0x7ff) << 52) | | |
9847 | result_frac); | |
9848 | } | |
9849 | ||
b6d4443a | 9850 | uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) |
4373f3ce | 9851 | { |
b6d4443a | 9852 | float_status *s = fpstp; |
fe0e4872 CL |
9853 | float64 f64; |
9854 | ||
9855 | if ((a & 0x80000000) == 0) { | |
9856 | return 0xffffffff; | |
9857 | } | |
9858 | ||
9859 | f64 = make_float64((0x3feULL << 52) | |
9860 | | ((int64_t)(a & 0x7fffffff) << 21)); | |
9861 | ||
b6d4443a | 9862 | f64 = recip_estimate(f64, s); |
fe0e4872 CL |
9863 | |
9864 | return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); | |
4373f3ce PB |
9865 | } |
9866 | ||
c2fb418e | 9867 | uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) |
4373f3ce | 9868 | { |
c2fb418e | 9869 | float_status *fpst = fpstp; |
e07be5d2 CL |
9870 | float64 f64; |
9871 | ||
9872 | if ((a & 0xc0000000) == 0) { | |
9873 | return 0xffffffff; | |
9874 | } | |
9875 | ||
9876 | if (a & 0x80000000) { | |
9877 | f64 = make_float64((0x3feULL << 52) | |
9878 | | ((uint64_t)(a & 0x7fffffff) << 21)); | |
9879 | } else { /* bits 31-30 == '01' */ | |
9880 | f64 = make_float64((0x3fdULL << 52) | |
9881 | | ((uint64_t)(a & 0x3fffffff) << 22)); | |
9882 | } | |
9883 | ||
c2fb418e | 9884 | f64 = recip_sqrt_estimate(f64, fpst); |
e07be5d2 CL |
9885 | |
9886 | return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); | |
4373f3ce | 9887 | } |
fe1479c3 | 9888 | |
da97f52c PM |
9889 | /* VFPv4 fused multiply-accumulate */ |
9890 | float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) | |
9891 | { | |
9892 | float_status *fpst = fpstp; | |
9893 | return float32_muladd(a, b, c, 0, fpst); | |
9894 | } | |
9895 | ||
9896 | float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) | |
9897 | { | |
9898 | float_status *fpst = fpstp; | |
9899 | return float64_muladd(a, b, c, 0, fpst); | |
9900 | } | |
d9b0848d PM |
9901 | |
9902 | /* ARMv8 round to integral */ | |
9903 | float32 HELPER(rints_exact)(float32 x, void *fp_status) | |
9904 | { | |
9905 | return float32_round_to_int(x, fp_status); | |
9906 | } | |
9907 | ||
9908 | float64 HELPER(rintd_exact)(float64 x, void *fp_status) | |
9909 | { | |
9910 | return float64_round_to_int(x, fp_status); | |
9911 | } | |
9912 | ||
9913 | float32 HELPER(rints)(float32 x, void *fp_status) | |
9914 | { | |
9915 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
9916 | float32 ret; | |
9917 | ||
9918 | ret = float32_round_to_int(x, fp_status); | |
9919 | ||
9920 | /* Suppress any inexact exceptions the conversion produced */ | |
9921 | if (!(old_flags & float_flag_inexact)) { | |
9922 | new_flags = get_float_exception_flags(fp_status); | |
9923 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
9924 | } | |
9925 | ||
9926 | return ret; | |
9927 | } | |
9928 | ||
9929 | float64 HELPER(rintd)(float64 x, void *fp_status) | |
9930 | { | |
9931 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
9932 | float64 ret; | |
9933 | ||
9934 | ret = float64_round_to_int(x, fp_status); | |
9935 | ||
9936 | new_flags = get_float_exception_flags(fp_status); | |
9937 | ||
9938 | /* Suppress any inexact exceptions the conversion produced */ | |
9939 | if (!(old_flags & float_flag_inexact)) { | |
9940 | new_flags = get_float_exception_flags(fp_status); | |
9941 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
9942 | } | |
9943 | ||
9944 | return ret; | |
9945 | } | |
9972da66 WN |
9946 | |
9947 | /* Convert ARM rounding mode to softfloat */ | |
9948 | int arm_rmode_to_sf(int rmode) | |
9949 | { | |
9950 | switch (rmode) { | |
9951 | case FPROUNDING_TIEAWAY: | |
9952 | rmode = float_round_ties_away; | |
9953 | break; | |
9954 | case FPROUNDING_ODD: | |
9955 | /* FIXME: add support for TIEAWAY and ODD */ | |
9956 | qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", | |
9957 | rmode); | |
9958 | case FPROUNDING_TIEEVEN: | |
9959 | default: | |
9960 | rmode = float_round_nearest_even; | |
9961 | break; | |
9962 | case FPROUNDING_POSINF: | |
9963 | rmode = float_round_up; | |
9964 | break; | |
9965 | case FPROUNDING_NEGINF: | |
9966 | rmode = float_round_down; | |
9967 | break; | |
9968 | case FPROUNDING_ZERO: | |
9969 | rmode = float_round_to_zero; | |
9970 | break; | |
9971 | } | |
9972 | return rmode; | |
9973 | } | |
eb0ecd5a | 9974 | |
aa633469 PM |
9975 | /* CRC helpers. |
9976 | * The upper bytes of val (above the number specified by 'bytes') must have | |
9977 | * been zeroed out by the caller. | |
9978 | */ | |
eb0ecd5a WN |
9979 | uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) |
9980 | { | |
9981 | uint8_t buf[4]; | |
9982 | ||
aa633469 | 9983 | stl_le_p(buf, val); |
eb0ecd5a WN |
9984 | |
9985 | /* zlib crc32 converts the accumulator and output to one's complement. */ | |
9986 | return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | |
9987 | } | |
9988 | ||
9989 | uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | |
9990 | { | |
9991 | uint8_t buf[4]; | |
9992 | ||
aa633469 | 9993 | stl_le_p(buf, val); |
eb0ecd5a WN |
9994 | |
9995 | /* Linux crc32c converts the output to one's complement. */ | |
9996 | return crc32c(acc, buf, bytes) ^ 0xffffffff; | |
9997 | } |