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74c21bd0 | 1 | #include "qemu/osdep.h" |
194cbc49 | 2 | #include "trace.h" |
b5ff1b31 | 3 | #include "cpu.h" |
ccd38087 | 4 | #include "internals.h" |
022c62cb | 5 | #include "exec/gdbstub.h" |
2ef6175a | 6 | #include "exec/helper-proto.h" |
1de7afc9 | 7 | #include "qemu/host-utils.h" |
78027bb6 | 8 | #include "sysemu/arch_init.h" |
9c17d615 | 9 | #include "sysemu/sysemu.h" |
1de7afc9 | 10 | #include "qemu/bitops.h" |
eb0ecd5a | 11 | #include "qemu/crc32c.h" |
63c91552 | 12 | #include "exec/exec-all.h" |
f08b6170 | 13 | #include "exec/cpu_ldst.h" |
1d854765 | 14 | #include "arm_ldst.h" |
eb0ecd5a | 15 | #include <zlib.h> /* For crc32 */ |
cfe67cef | 16 | #include "exec/semihost.h" |
f3a9b694 | 17 | #include "sysemu/kvm.h" |
0b03bdfc | 18 | |
352c98e5 LV |
19 | #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ |
20 | ||
4a501606 | 21 | #ifndef CONFIG_USER_ONLY |
5b2d261d AB |
22 | /* Cacheability and shareability attributes for a memory access */ |
23 | typedef struct ARMCacheAttrs { | |
24 | unsigned int attrs:8; /* as in the MAIR register encoding */ | |
25 | unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */ | |
26 | } ARMCacheAttrs; | |
27 | ||
af51f566 | 28 | static bool get_phys_addr(CPUARMState *env, target_ulong address, |
03ae85f8 | 29 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
af51f566 | 30 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, |
bc52bfeb | 31 | target_ulong *page_size, |
5b2d261d | 32 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); |
7c2cb42b | 33 | |
37785977 | 34 | static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
03ae85f8 | 35 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
37785977 | 36 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, |
da909b2c | 37 | target_ulong *page_size_ptr, |
5b2d261d | 38 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); |
37785977 | 39 | |
35337cc3 PM |
40 | /* Security attributes for an address, as returned by v8m_security_lookup. */ |
41 | typedef struct V8M_SAttributes { | |
42 | bool ns; | |
43 | bool nsc; | |
44 | uint8_t sregion; | |
45 | bool srvalid; | |
46 | uint8_t iregion; | |
47 | bool irvalid; | |
48 | } V8M_SAttributes; | |
49 | ||
333e10c5 PM |
50 | static void v8m_security_lookup(CPUARMState *env, uint32_t address, |
51 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
52 | V8M_SAttributes *sattrs); | |
53 | ||
7c2cb42b AF |
54 | /* Definitions for the PMCCNTR and PMCR registers */ |
55 | #define PMCRD 0x8 | |
56 | #define PMCRC 0x4 | |
57 | #define PMCRE 0x1 | |
4a501606 PM |
58 | #endif |
59 | ||
0ecb72a5 | 60 | static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
61 | { |
62 | int nregs; | |
63 | ||
64 | /* VFP data registers are always little-endian. */ | |
65 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
66 | if (reg < nregs) { | |
67 | stfq_le_p(buf, env->vfp.regs[reg]); | |
68 | return 8; | |
69 | } | |
70 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
71 | /* Aliases for Q regs. */ | |
72 | nregs += 16; | |
73 | if (reg < nregs) { | |
74 | stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); | |
75 | stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); | |
76 | return 16; | |
77 | } | |
78 | } | |
79 | switch (reg - nregs) { | |
80 | case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; | |
81 | case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; | |
82 | case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; | |
83 | } | |
84 | return 0; | |
85 | } | |
86 | ||
0ecb72a5 | 87 | static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
88 | { |
89 | int nregs; | |
90 | ||
91 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
92 | if (reg < nregs) { | |
93 | env->vfp.regs[reg] = ldfq_le_p(buf); | |
94 | return 8; | |
95 | } | |
96 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
97 | nregs += 16; | |
98 | if (reg < nregs) { | |
99 | env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); | |
100 | env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); | |
101 | return 16; | |
102 | } | |
103 | } | |
104 | switch (reg - nregs) { | |
105 | case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; | |
106 | case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; | |
71b3c3de | 107 | case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
56aebc89 PB |
108 | } |
109 | return 0; | |
110 | } | |
111 | ||
6a669427 PM |
112 | static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
113 | { | |
114 | switch (reg) { | |
115 | case 0 ... 31: | |
116 | /* 128 bit FP register */ | |
117 | stfq_le_p(buf, env->vfp.regs[reg * 2]); | |
118 | stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); | |
119 | return 16; | |
120 | case 32: | |
121 | /* FPSR */ | |
122 | stl_p(buf, vfp_get_fpsr(env)); | |
123 | return 4; | |
124 | case 33: | |
125 | /* FPCR */ | |
126 | stl_p(buf, vfp_get_fpcr(env)); | |
127 | return 4; | |
128 | default: | |
129 | return 0; | |
130 | } | |
131 | } | |
132 | ||
133 | static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) | |
134 | { | |
135 | switch (reg) { | |
136 | case 0 ... 31: | |
137 | /* 128 bit FP register */ | |
138 | env->vfp.regs[reg * 2] = ldfq_le_p(buf); | |
139 | env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8); | |
140 | return 16; | |
141 | case 32: | |
142 | /* FPSR */ | |
143 | vfp_set_fpsr(env, ldl_p(buf)); | |
144 | return 4; | |
145 | case 33: | |
146 | /* FPCR */ | |
147 | vfp_set_fpcr(env, ldl_p(buf)); | |
148 | return 4; | |
149 | default: | |
150 | return 0; | |
151 | } | |
152 | } | |
153 | ||
c4241c7d | 154 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) |
d4e6df63 | 155 | { |
375421cc | 156 | assert(ri->fieldoffset); |
67ed771d | 157 | if (cpreg_field_is_64bit(ri)) { |
c4241c7d | 158 | return CPREG_FIELD64(env, ri); |
22d9e1a9 | 159 | } else { |
c4241c7d | 160 | return CPREG_FIELD32(env, ri); |
22d9e1a9 | 161 | } |
d4e6df63 PM |
162 | } |
163 | ||
c4241c7d PM |
164 | static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
165 | uint64_t value) | |
d4e6df63 | 166 | { |
375421cc | 167 | assert(ri->fieldoffset); |
67ed771d | 168 | if (cpreg_field_is_64bit(ri)) { |
22d9e1a9 PM |
169 | CPREG_FIELD64(env, ri) = value; |
170 | } else { | |
171 | CPREG_FIELD32(env, ri) = value; | |
172 | } | |
d4e6df63 PM |
173 | } |
174 | ||
11f136ee FA |
175 | static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) |
176 | { | |
177 | return (char *)env + ri->fieldoffset; | |
178 | } | |
179 | ||
49a66191 | 180 | uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) |
721fae12 | 181 | { |
59a1c327 | 182 | /* Raw read of a coprocessor register (as needed for migration, etc). */ |
721fae12 | 183 | if (ri->type & ARM_CP_CONST) { |
59a1c327 | 184 | return ri->resetvalue; |
721fae12 | 185 | } else if (ri->raw_readfn) { |
59a1c327 | 186 | return ri->raw_readfn(env, ri); |
721fae12 | 187 | } else if (ri->readfn) { |
59a1c327 | 188 | return ri->readfn(env, ri); |
721fae12 | 189 | } else { |
59a1c327 | 190 | return raw_read(env, ri); |
721fae12 | 191 | } |
721fae12 PM |
192 | } |
193 | ||
59a1c327 | 194 | static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, |
7900e9f1 | 195 | uint64_t v) |
721fae12 PM |
196 | { |
197 | /* Raw write of a coprocessor register (as needed for migration, etc). | |
721fae12 PM |
198 | * Note that constant registers are treated as write-ignored; the |
199 | * caller should check for success by whether a readback gives the | |
200 | * value written. | |
201 | */ | |
202 | if (ri->type & ARM_CP_CONST) { | |
59a1c327 | 203 | return; |
721fae12 | 204 | } else if (ri->raw_writefn) { |
c4241c7d | 205 | ri->raw_writefn(env, ri, v); |
721fae12 | 206 | } else if (ri->writefn) { |
c4241c7d | 207 | ri->writefn(env, ri, v); |
721fae12 | 208 | } else { |
afb2530f | 209 | raw_write(env, ri, v); |
721fae12 | 210 | } |
721fae12 PM |
211 | } |
212 | ||
375421cc PM |
213 | static bool raw_accessors_invalid(const ARMCPRegInfo *ri) |
214 | { | |
215 | /* Return true if the regdef would cause an assertion if you called | |
216 | * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a | |
217 | * program bug for it not to have the NO_RAW flag). | |
218 | * NB that returning false here doesn't necessarily mean that calling | |
219 | * read/write_raw_cp_reg() is safe, because we can't distinguish "has | |
220 | * read/write access functions which are safe for raw use" from "has | |
221 | * read/write access functions which have side effects but has forgotten | |
222 | * to provide raw access functions". | |
223 | * The tests here line up with the conditions in read/write_raw_cp_reg() | |
224 | * and assertions in raw_read()/raw_write(). | |
225 | */ | |
226 | if ((ri->type & ARM_CP_CONST) || | |
227 | ri->fieldoffset || | |
228 | ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { | |
229 | return false; | |
230 | } | |
231 | return true; | |
232 | } | |
233 | ||
721fae12 PM |
234 | bool write_cpustate_to_list(ARMCPU *cpu) |
235 | { | |
236 | /* Write the coprocessor state from cpu->env to the (index,value) list. */ | |
237 | int i; | |
238 | bool ok = true; | |
239 | ||
240 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
241 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
242 | const ARMCPRegInfo *ri; | |
59a1c327 | 243 | |
60322b39 | 244 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
245 | if (!ri) { |
246 | ok = false; | |
247 | continue; | |
248 | } | |
7a0e58fa | 249 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
250 | continue; |
251 | } | |
59a1c327 | 252 | cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri); |
721fae12 PM |
253 | } |
254 | return ok; | |
255 | } | |
256 | ||
257 | bool write_list_to_cpustate(ARMCPU *cpu) | |
258 | { | |
259 | int i; | |
260 | bool ok = true; | |
261 | ||
262 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
263 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
264 | uint64_t v = cpu->cpreg_values[i]; | |
721fae12 PM |
265 | const ARMCPRegInfo *ri; |
266 | ||
60322b39 | 267 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
268 | if (!ri) { |
269 | ok = false; | |
270 | continue; | |
271 | } | |
7a0e58fa | 272 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
273 | continue; |
274 | } | |
275 | /* Write value and confirm it reads back as written | |
276 | * (to catch read-only registers and partially read-only | |
277 | * registers where the incoming migration value doesn't match) | |
278 | */ | |
59a1c327 PM |
279 | write_raw_cp_reg(&cpu->env, ri, v); |
280 | if (read_raw_cp_reg(&cpu->env, ri) != v) { | |
721fae12 PM |
281 | ok = false; |
282 | } | |
283 | } | |
284 | return ok; | |
285 | } | |
286 | ||
287 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | |
288 | { | |
289 | ARMCPU *cpu = opaque; | |
290 | uint64_t regidx; | |
291 | const ARMCPRegInfo *ri; | |
292 | ||
293 | regidx = *(uint32_t *)key; | |
60322b39 | 294 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 | 295 | |
7a0e58fa | 296 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
297 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); |
298 | /* The value array need not be initialized at this point */ | |
299 | cpu->cpreg_array_len++; | |
300 | } | |
301 | } | |
302 | ||
303 | static void count_cpreg(gpointer key, gpointer opaque) | |
304 | { | |
305 | ARMCPU *cpu = opaque; | |
306 | uint64_t regidx; | |
307 | const ARMCPRegInfo *ri; | |
308 | ||
309 | regidx = *(uint32_t *)key; | |
60322b39 | 310 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 | 311 | |
7a0e58fa | 312 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
313 | cpu->cpreg_array_len++; |
314 | } | |
315 | } | |
316 | ||
317 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | |
318 | { | |
cbf239b7 AR |
319 | uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); |
320 | uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); | |
721fae12 | 321 | |
cbf239b7 AR |
322 | if (aidx > bidx) { |
323 | return 1; | |
324 | } | |
325 | if (aidx < bidx) { | |
326 | return -1; | |
327 | } | |
328 | return 0; | |
721fae12 PM |
329 | } |
330 | ||
331 | void init_cpreg_list(ARMCPU *cpu) | |
332 | { | |
333 | /* Initialise the cpreg_tuples[] array based on the cp_regs hash. | |
334 | * Note that we require cpreg_tuples[] to be sorted by key ID. | |
335 | */ | |
57b6d95e | 336 | GList *keys; |
721fae12 PM |
337 | int arraylen; |
338 | ||
57b6d95e | 339 | keys = g_hash_table_get_keys(cpu->cp_regs); |
721fae12 PM |
340 | keys = g_list_sort(keys, cpreg_key_compare); |
341 | ||
342 | cpu->cpreg_array_len = 0; | |
343 | ||
344 | g_list_foreach(keys, count_cpreg, cpu); | |
345 | ||
346 | arraylen = cpu->cpreg_array_len; | |
347 | cpu->cpreg_indexes = g_new(uint64_t, arraylen); | |
348 | cpu->cpreg_values = g_new(uint64_t, arraylen); | |
349 | cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); | |
350 | cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); | |
351 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; | |
352 | cpu->cpreg_array_len = 0; | |
353 | ||
354 | g_list_foreach(keys, add_cpreg_to_list, cpu); | |
355 | ||
356 | assert(cpu->cpreg_array_len == arraylen); | |
357 | ||
358 | g_list_free(keys); | |
359 | } | |
360 | ||
68e9c2fe EI |
361 | /* |
362 | * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but | |
363 | * they are accessible when EL3 is using AArch64 regardless of EL3.NS. | |
364 | * | |
365 | * access_el3_aa32ns: Used to check AArch32 register views. | |
366 | * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views. | |
367 | */ | |
368 | static CPAccessResult access_el3_aa32ns(CPUARMState *env, | |
3f208fd7 PM |
369 | const ARMCPRegInfo *ri, |
370 | bool isread) | |
68e9c2fe EI |
371 | { |
372 | bool secure = arm_is_secure_below_el3(env); | |
373 | ||
374 | assert(!arm_el_is_aa64(env, 3)); | |
375 | if (secure) { | |
376 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
377 | } | |
378 | return CP_ACCESS_OK; | |
379 | } | |
380 | ||
381 | static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env, | |
3f208fd7 PM |
382 | const ARMCPRegInfo *ri, |
383 | bool isread) | |
68e9c2fe EI |
384 | { |
385 | if (!arm_el_is_aa64(env, 3)) { | |
3f208fd7 | 386 | return access_el3_aa32ns(env, ri, isread); |
68e9c2fe EI |
387 | } |
388 | return CP_ACCESS_OK; | |
389 | } | |
390 | ||
5513c3ab PM |
391 | /* Some secure-only AArch32 registers trap to EL3 if used from |
392 | * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). | |
393 | * Note that an access from Secure EL1 can only happen if EL3 is AArch64. | |
394 | * We assume that the .access field is set to PL1_RW. | |
395 | */ | |
396 | static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, | |
3f208fd7 PM |
397 | const ARMCPRegInfo *ri, |
398 | bool isread) | |
5513c3ab PM |
399 | { |
400 | if (arm_current_el(env) == 3) { | |
401 | return CP_ACCESS_OK; | |
402 | } | |
403 | if (arm_is_secure_below_el3(env)) { | |
404 | return CP_ACCESS_TRAP_EL3; | |
405 | } | |
406 | /* This will be EL1 NS and EL2 NS, which just UNDEF */ | |
407 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
408 | } | |
409 | ||
187f678d PM |
410 | /* Check for traps to "powerdown debug" registers, which are controlled |
411 | * by MDCR.TDOSA | |
412 | */ | |
413 | static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, | |
414 | bool isread) | |
415 | { | |
416 | int el = arm_current_el(env); | |
417 | ||
418 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA) | |
419 | && !arm_is_secure_below_el3(env)) { | |
420 | return CP_ACCESS_TRAP_EL2; | |
421 | } | |
422 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { | |
423 | return CP_ACCESS_TRAP_EL3; | |
424 | } | |
425 | return CP_ACCESS_OK; | |
426 | } | |
427 | ||
91b0a238 PM |
428 | /* Check for traps to "debug ROM" registers, which are controlled |
429 | * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. | |
430 | */ | |
431 | static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, | |
432 | bool isread) | |
433 | { | |
434 | int el = arm_current_el(env); | |
435 | ||
436 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA) | |
437 | && !arm_is_secure_below_el3(env)) { | |
438 | return CP_ACCESS_TRAP_EL2; | |
439 | } | |
440 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
441 | return CP_ACCESS_TRAP_EL3; | |
442 | } | |
443 | return CP_ACCESS_OK; | |
444 | } | |
445 | ||
d6c8cf81 PM |
446 | /* Check for traps to general debug registers, which are controlled |
447 | * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. | |
448 | */ | |
449 | static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, | |
450 | bool isread) | |
451 | { | |
452 | int el = arm_current_el(env); | |
453 | ||
454 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA) | |
455 | && !arm_is_secure_below_el3(env)) { | |
456 | return CP_ACCESS_TRAP_EL2; | |
457 | } | |
458 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
459 | return CP_ACCESS_TRAP_EL3; | |
460 | } | |
461 | return CP_ACCESS_OK; | |
462 | } | |
463 | ||
1fce1ba9 PM |
464 | /* Check for traps to performance monitor registers, which are controlled |
465 | * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. | |
466 | */ | |
467 | static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, | |
468 | bool isread) | |
469 | { | |
470 | int el = arm_current_el(env); | |
471 | ||
472 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) | |
473 | && !arm_is_secure_below_el3(env)) { | |
474 | return CP_ACCESS_TRAP_EL2; | |
475 | } | |
476 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
477 | return CP_ACCESS_TRAP_EL3; | |
478 | } | |
479 | return CP_ACCESS_OK; | |
480 | } | |
481 | ||
c4241c7d | 482 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
c983fe6c | 483 | { |
00c8cb0a AF |
484 | ARMCPU *cpu = arm_env_get_cpu(env); |
485 | ||
8d5c773e | 486 | raw_write(env, ri, value); |
d10eb08f | 487 | tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ |
c983fe6c PM |
488 | } |
489 | ||
c4241c7d | 490 | static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
08de207b | 491 | { |
00c8cb0a AF |
492 | ARMCPU *cpu = arm_env_get_cpu(env); |
493 | ||
8d5c773e | 494 | if (raw_read(env, ri) != value) { |
08de207b PM |
495 | /* Unlike real hardware the qemu TLB uses virtual addresses, |
496 | * not modified virtual addresses, so this causes a TLB flush. | |
497 | */ | |
d10eb08f | 498 | tlb_flush(CPU(cpu)); |
8d5c773e | 499 | raw_write(env, ri, value); |
08de207b | 500 | } |
08de207b | 501 | } |
c4241c7d PM |
502 | |
503 | static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
504 | uint64_t value) | |
08de207b | 505 | { |
00c8cb0a AF |
506 | ARMCPU *cpu = arm_env_get_cpu(env); |
507 | ||
452a0955 | 508 | if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) |
014406b5 | 509 | && !extended_addresses_enabled(env)) { |
08de207b PM |
510 | /* For VMSA (when not using the LPAE long descriptor page table |
511 | * format) this register includes the ASID, so do a TLB flush. | |
512 | * For PMSA it is purely a process ID and no action is needed. | |
513 | */ | |
d10eb08f | 514 | tlb_flush(CPU(cpu)); |
08de207b | 515 | } |
8d5c773e | 516 | raw_write(env, ri, value); |
08de207b PM |
517 | } |
518 | ||
c4241c7d PM |
519 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
520 | uint64_t value) | |
d929823f PM |
521 | { |
522 | /* Invalidate all (TLBIALL) */ | |
00c8cb0a AF |
523 | ARMCPU *cpu = arm_env_get_cpu(env); |
524 | ||
d10eb08f | 525 | tlb_flush(CPU(cpu)); |
d929823f PM |
526 | } |
527 | ||
c4241c7d PM |
528 | static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
529 | uint64_t value) | |
d929823f PM |
530 | { |
531 | /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ | |
31b030d4 AF |
532 | ARMCPU *cpu = arm_env_get_cpu(env); |
533 | ||
534 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); | |
d929823f PM |
535 | } |
536 | ||
c4241c7d PM |
537 | static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
538 | uint64_t value) | |
d929823f PM |
539 | { |
540 | /* Invalidate by ASID (TLBIASID) */ | |
00c8cb0a AF |
541 | ARMCPU *cpu = arm_env_get_cpu(env); |
542 | ||
d10eb08f | 543 | tlb_flush(CPU(cpu)); |
d929823f PM |
544 | } |
545 | ||
c4241c7d PM |
546 | static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
547 | uint64_t value) | |
d929823f PM |
548 | { |
549 | /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ | |
31b030d4 AF |
550 | ARMCPU *cpu = arm_env_get_cpu(env); |
551 | ||
552 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); | |
d929823f PM |
553 | } |
554 | ||
fa439fc5 PM |
555 | /* IS variants of TLB operations must affect all cores */ |
556 | static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
557 | uint64_t value) | |
558 | { | |
a67cf277 | 559 | CPUState *cs = ENV_GET_CPU(env); |
fa439fc5 | 560 | |
a67cf277 | 561 | tlb_flush_all_cpus_synced(cs); |
fa439fc5 PM |
562 | } |
563 | ||
564 | static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
565 | uint64_t value) | |
566 | { | |
a67cf277 | 567 | CPUState *cs = ENV_GET_CPU(env); |
fa439fc5 | 568 | |
a67cf277 | 569 | tlb_flush_all_cpus_synced(cs); |
fa439fc5 PM |
570 | } |
571 | ||
572 | static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
573 | uint64_t value) | |
574 | { | |
a67cf277 | 575 | CPUState *cs = ENV_GET_CPU(env); |
fa439fc5 | 576 | |
a67cf277 | 577 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); |
fa439fc5 PM |
578 | } |
579 | ||
580 | static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
581 | uint64_t value) | |
582 | { | |
a67cf277 | 583 | CPUState *cs = ENV_GET_CPU(env); |
fa439fc5 | 584 | |
a67cf277 | 585 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); |
fa439fc5 PM |
586 | } |
587 | ||
541ef8c2 SS |
588 | static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, |
589 | uint64_t value) | |
590 | { | |
591 | CPUState *cs = ENV_GET_CPU(env); | |
592 | ||
0336cbf8 | 593 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
594 | ARMMMUIdxBit_S12NSE1 | |
595 | ARMMMUIdxBit_S12NSE0 | | |
596 | ARMMMUIdxBit_S2NS); | |
541ef8c2 SS |
597 | } |
598 | ||
599 | static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
600 | uint64_t value) | |
601 | { | |
a67cf277 | 602 | CPUState *cs = ENV_GET_CPU(env); |
541ef8c2 | 603 | |
a67cf277 | 604 | tlb_flush_by_mmuidx_all_cpus_synced(cs, |
8bd5c820 PM |
605 | ARMMMUIdxBit_S12NSE1 | |
606 | ARMMMUIdxBit_S12NSE0 | | |
607 | ARMMMUIdxBit_S2NS); | |
541ef8c2 SS |
608 | } |
609 | ||
610 | static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
611 | uint64_t value) | |
612 | { | |
613 | /* Invalidate by IPA. This has to invalidate any structures that | |
614 | * contain only stage 2 translation information, but does not need | |
615 | * to apply to structures that contain combined stage 1 and stage 2 | |
616 | * translation information. | |
617 | * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. | |
618 | */ | |
619 | CPUState *cs = ENV_GET_CPU(env); | |
620 | uint64_t pageaddr; | |
621 | ||
622 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
623 | return; | |
624 | } | |
625 | ||
626 | pageaddr = sextract64(value << 12, 0, 40); | |
627 | ||
8bd5c820 | 628 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); |
541ef8c2 SS |
629 | } |
630 | ||
631 | static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
632 | uint64_t value) | |
633 | { | |
a67cf277 | 634 | CPUState *cs = ENV_GET_CPU(env); |
541ef8c2 SS |
635 | uint64_t pageaddr; |
636 | ||
637 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
638 | return; | |
639 | } | |
640 | ||
641 | pageaddr = sextract64(value << 12, 0, 40); | |
642 | ||
a67cf277 | 643 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 644 | ARMMMUIdxBit_S2NS); |
541ef8c2 SS |
645 | } |
646 | ||
647 | static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
648 | uint64_t value) | |
649 | { | |
650 | CPUState *cs = ENV_GET_CPU(env); | |
651 | ||
8bd5c820 | 652 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
653 | } |
654 | ||
655 | static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
656 | uint64_t value) | |
657 | { | |
a67cf277 | 658 | CPUState *cs = ENV_GET_CPU(env); |
541ef8c2 | 659 | |
8bd5c820 | 660 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
661 | } |
662 | ||
663 | static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
664 | uint64_t value) | |
665 | { | |
666 | CPUState *cs = ENV_GET_CPU(env); | |
667 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); | |
668 | ||
8bd5c820 | 669 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
670 | } |
671 | ||
672 | static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
673 | uint64_t value) | |
674 | { | |
a67cf277 | 675 | CPUState *cs = ENV_GET_CPU(env); |
541ef8c2 SS |
676 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
677 | ||
a67cf277 | 678 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 679 | ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
680 | } |
681 | ||
e9aa6c21 | 682 | static const ARMCPRegInfo cp_reginfo[] = { |
54bf36ed FA |
683 | /* Define the secure and non-secure FCSE identifier CP registers |
684 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
685 | * the secure register to be properly reset and migrated. There is also no | |
686 | * v8 EL1 version of the register so the non-secure instance stands alone. | |
687 | */ | |
688 | { .name = "FCSEIDR(NS)", | |
689 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, | |
690 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, | |
691 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), | |
692 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, | |
693 | { .name = "FCSEIDR(S)", | |
694 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, | |
695 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
696 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), | |
d4e6df63 | 697 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, |
54bf36ed FA |
698 | /* Define the secure and non-secure context identifier CP registers |
699 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
700 | * the secure register to be properly reset and migrated. In the | |
701 | * non-secure case, the 32-bit register will have reset and migration | |
702 | * disabled during registration as it is handled by the 64-bit instance. | |
703 | */ | |
704 | { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
014406b5 | 705 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
54bf36ed FA |
706 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, |
707 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), | |
708 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, | |
709 | { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32, | |
710 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, | |
711 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
712 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), | |
d4e6df63 | 713 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, |
9449fdf6 PM |
714 | REGINFO_SENTINEL |
715 | }; | |
716 | ||
717 | static const ARMCPRegInfo not_v8_cp_reginfo[] = { | |
718 | /* NB: Some of these registers exist in v8 but with more precise | |
719 | * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). | |
720 | */ | |
721 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
722 | { .name = "DACR", |
723 | .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, | |
724 | .access = PL1_RW, .resetvalue = 0, | |
725 | .writefn = dacr_write, .raw_writefn = raw_write, | |
726 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
727 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a903c449 EI |
728 | /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. |
729 | * For v6 and v5, these mappings are overly broad. | |
4fdd17dd | 730 | */ |
a903c449 EI |
731 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0, |
732 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
733 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1, | |
734 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
735 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4, | |
736 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
737 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8, | |
4fdd17dd | 738 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, |
c4804214 PM |
739 | /* Cache maintenance ops; some of this space may be overridden later. */ |
740 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | |
741 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | |
742 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | |
e9aa6c21 PM |
743 | REGINFO_SENTINEL |
744 | }; | |
745 | ||
7d57f408 PM |
746 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
747 | /* Not all pre-v6 cores implemented this WFI, so this is slightly | |
748 | * over-broad. | |
749 | */ | |
750 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | |
751 | .access = PL1_W, .type = ARM_CP_WFI }, | |
752 | REGINFO_SENTINEL | |
753 | }; | |
754 | ||
755 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | |
756 | /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which | |
757 | * is UNPREDICTABLE; we choose to NOP as most implementations do). | |
758 | */ | |
759 | { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
760 | .access = PL1_W, .type = ARM_CP_WFI }, | |
34f90529 PM |
761 | /* L1 cache lockdown. Not architectural in v6 and earlier but in practice |
762 | * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and | |
763 | * OMAPCP will override this space. | |
764 | */ | |
765 | { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, | |
766 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), | |
767 | .resetvalue = 0 }, | |
768 | { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, | |
769 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), | |
770 | .resetvalue = 0 }, | |
776d4e5c PM |
771 | /* v6 doesn't have the cache ID registers but Linux reads them anyway */ |
772 | { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, | |
7a0e58fa | 773 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 774 | .resetvalue = 0 }, |
50300698 PM |
775 | /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; |
776 | * implementing it as RAZ means the "debug architecture version" bits | |
777 | * will read as a reserved value, which should cause Linux to not try | |
778 | * to use the debug hardware. | |
779 | */ | |
780 | { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
781 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
995939a6 PM |
782 | /* MMU TLB control. Note that the wildcarding means we cover not just |
783 | * the unified TLB ops but also the dside/iside/inner-shareable variants. | |
784 | */ | |
785 | { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, | |
786 | .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, | |
7a0e58fa | 787 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
788 | { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, |
789 | .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, | |
7a0e58fa | 790 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
791 | { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, |
792 | .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, | |
7a0e58fa | 793 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
794 | { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, |
795 | .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, | |
7a0e58fa | 796 | .type = ARM_CP_NO_RAW }, |
a903c449 EI |
797 | { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2, |
798 | .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, | |
799 | { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, | |
800 | .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, | |
7d57f408 PM |
801 | REGINFO_SENTINEL |
802 | }; | |
803 | ||
c4241c7d PM |
804 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
805 | uint64_t value) | |
2771db27 | 806 | { |
f0aff255 FA |
807 | uint32_t mask = 0; |
808 | ||
809 | /* In ARMv8 most bits of CPACR_EL1 are RES0. */ | |
810 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
811 | /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. | |
812 | * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. | |
813 | * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. | |
814 | */ | |
815 | if (arm_feature(env, ARM_FEATURE_VFP)) { | |
816 | /* VFP coprocessor: cp10 & cp11 [23:20] */ | |
817 | mask |= (1 << 31) | (1 << 30) | (0xf << 20); | |
818 | ||
819 | if (!arm_feature(env, ARM_FEATURE_NEON)) { | |
820 | /* ASEDIS [31] bit is RAO/WI */ | |
821 | value |= (1 << 31); | |
822 | } | |
823 | ||
824 | /* VFPv3 and upwards with NEON implement 32 double precision | |
825 | * registers (D0-D31). | |
826 | */ | |
827 | if (!arm_feature(env, ARM_FEATURE_NEON) || | |
828 | !arm_feature(env, ARM_FEATURE_VFP3)) { | |
829 | /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ | |
830 | value |= (1 << 30); | |
831 | } | |
832 | } | |
833 | value &= mask; | |
2771db27 | 834 | } |
7ebd5f2e | 835 | env->cp15.cpacr_el1 = value; |
2771db27 PM |
836 | } |
837 | ||
3f208fd7 PM |
838 | static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
839 | bool isread) | |
c6f19164 GB |
840 | { |
841 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
842 | /* Check if CPACR accesses are to be trapped to EL2 */ | |
843 | if (arm_current_el(env) == 1 && | |
844 | (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) { | |
845 | return CP_ACCESS_TRAP_EL2; | |
846 | /* Check if CPACR accesses are to be trapped to EL3 */ | |
847 | } else if (arm_current_el(env) < 3 && | |
848 | (env->cp15.cptr_el[3] & CPTR_TCPAC)) { | |
849 | return CP_ACCESS_TRAP_EL3; | |
850 | } | |
851 | } | |
852 | ||
853 | return CP_ACCESS_OK; | |
854 | } | |
855 | ||
3f208fd7 PM |
856 | static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
857 | bool isread) | |
c6f19164 GB |
858 | { |
859 | /* Check if CPTR accesses are set to trap to EL3 */ | |
860 | if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) { | |
861 | return CP_ACCESS_TRAP_EL3; | |
862 | } | |
863 | ||
864 | return CP_ACCESS_OK; | |
865 | } | |
866 | ||
7d57f408 PM |
867 | static const ARMCPRegInfo v6_cp_reginfo[] = { |
868 | /* prefetch by MVA in v6, NOP in v7 */ | |
869 | { .name = "MVA_prefetch", | |
870 | .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, | |
871 | .access = PL1_W, .type = ARM_CP_NOP }, | |
6df99dec SS |
872 | /* We need to break the TB after ISB to execute self-modifying code |
873 | * correctly and also to take any pending interrupts immediately. | |
874 | * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. | |
875 | */ | |
7d57f408 | 876 | { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, |
6df99dec | 877 | .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, |
091fd17c | 878 | { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
7d57f408 | 879 | .access = PL0_W, .type = ARM_CP_NOP }, |
091fd17c | 880 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
7d57f408 | 881 | .access = PL0_W, .type = ARM_CP_NOP }, |
06d76f31 | 882 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
6cd8a264 | 883 | .access = PL1_RW, |
b848ce2b FA |
884 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), |
885 | offsetof(CPUARMState, cp15.ifar_ns) }, | |
06d76f31 PM |
886 | .resetvalue = 0, }, |
887 | /* Watchpoint Fault Address Register : should actually only be present | |
888 | * for 1136, 1176, 11MPCore. | |
889 | */ | |
890 | { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
891 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, | |
34222fb8 | 892 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, |
c6f19164 | 893 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, |
7ebd5f2e | 894 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), |
2771db27 | 895 | .resetvalue = 0, .writefn = cpacr_write }, |
7d57f408 PM |
896 | REGINFO_SENTINEL |
897 | }; | |
898 | ||
3f208fd7 PM |
899 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, |
900 | bool isread) | |
200ac0ef | 901 | { |
3b163b01 | 902 | /* Performance monitor registers user accessibility is controlled |
1fce1ba9 PM |
903 | * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable |
904 | * trapping to EL2 or EL3 for other accesses. | |
200ac0ef | 905 | */ |
1fce1ba9 PM |
906 | int el = arm_current_el(env); |
907 | ||
6ecd0b6b | 908 | if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { |
fcd25206 | 909 | return CP_ACCESS_TRAP; |
200ac0ef | 910 | } |
1fce1ba9 PM |
911 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) |
912 | && !arm_is_secure_below_el3(env)) { | |
913 | return CP_ACCESS_TRAP_EL2; | |
914 | } | |
915 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
916 | return CP_ACCESS_TRAP_EL3; | |
917 | } | |
918 | ||
fcd25206 | 919 | return CP_ACCESS_OK; |
200ac0ef PM |
920 | } |
921 | ||
6ecd0b6b AB |
922 | static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, |
923 | const ARMCPRegInfo *ri, | |
924 | bool isread) | |
925 | { | |
926 | /* ER: event counter read trap control */ | |
927 | if (arm_feature(env, ARM_FEATURE_V8) | |
928 | && arm_current_el(env) == 0 | |
929 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 | |
930 | && isread) { | |
931 | return CP_ACCESS_OK; | |
932 | } | |
933 | ||
934 | return pmreg_access(env, ri, isread); | |
935 | } | |
936 | ||
937 | static CPAccessResult pmreg_access_swinc(CPUARMState *env, | |
938 | const ARMCPRegInfo *ri, | |
939 | bool isread) | |
940 | { | |
941 | /* SW: software increment write trap control */ | |
942 | if (arm_feature(env, ARM_FEATURE_V8) | |
943 | && arm_current_el(env) == 0 | |
944 | && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 | |
945 | && !isread) { | |
946 | return CP_ACCESS_OK; | |
947 | } | |
948 | ||
949 | return pmreg_access(env, ri, isread); | |
950 | } | |
951 | ||
7c2cb42b | 952 | #ifndef CONFIG_USER_ONLY |
87124fde | 953 | |
6ecd0b6b AB |
954 | static CPAccessResult pmreg_access_selr(CPUARMState *env, |
955 | const ARMCPRegInfo *ri, | |
956 | bool isread) | |
957 | { | |
958 | /* ER: event counter read trap control */ | |
959 | if (arm_feature(env, ARM_FEATURE_V8) | |
960 | && arm_current_el(env) == 0 | |
961 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { | |
962 | return CP_ACCESS_OK; | |
963 | } | |
964 | ||
965 | return pmreg_access(env, ri, isread); | |
966 | } | |
967 | ||
968 | static CPAccessResult pmreg_access_ccntr(CPUARMState *env, | |
969 | const ARMCPRegInfo *ri, | |
970 | bool isread) | |
971 | { | |
972 | /* CR: cycle counter read trap control */ | |
973 | if (arm_feature(env, ARM_FEATURE_V8) | |
974 | && arm_current_el(env) == 0 | |
975 | && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 | |
976 | && isread) { | |
977 | return CP_ACCESS_OK; | |
978 | } | |
979 | ||
980 | return pmreg_access(env, ri, isread); | |
981 | } | |
982 | ||
87124fde AF |
983 | static inline bool arm_ccnt_enabled(CPUARMState *env) |
984 | { | |
985 | /* This does not support checking PMCCFILTR_EL0 register */ | |
986 | ||
987 | if (!(env->cp15.c9_pmcr & PMCRE)) { | |
988 | return false; | |
989 | } | |
990 | ||
991 | return true; | |
992 | } | |
993 | ||
ec7b4ce4 AF |
994 | void pmccntr_sync(CPUARMState *env) |
995 | { | |
996 | uint64_t temp_ticks; | |
997 | ||
352c98e5 LV |
998 | temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
999 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); | |
ec7b4ce4 AF |
1000 | |
1001 | if (env->cp15.c9_pmcr & PMCRD) { | |
1002 | /* Increment once every 64 processor clock cycles */ | |
1003 | temp_ticks /= 64; | |
1004 | } | |
1005 | ||
1006 | if (arm_ccnt_enabled(env)) { | |
1007 | env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt; | |
1008 | } | |
1009 | } | |
1010 | ||
c4241c7d PM |
1011 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1012 | uint64_t value) | |
200ac0ef | 1013 | { |
942a155b | 1014 | pmccntr_sync(env); |
7c2cb42b AF |
1015 | |
1016 | if (value & PMCRC) { | |
1017 | /* The counter has been reset */ | |
1018 | env->cp15.c15_ccnt = 0; | |
1019 | } | |
1020 | ||
200ac0ef PM |
1021 | /* only the DP, X, D and E bits are writable */ |
1022 | env->cp15.c9_pmcr &= ~0x39; | |
1023 | env->cp15.c9_pmcr |= (value & 0x39); | |
7c2cb42b | 1024 | |
942a155b | 1025 | pmccntr_sync(env); |
7c2cb42b AF |
1026 | } |
1027 | ||
1028 | static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1029 | { | |
c92c0687 | 1030 | uint64_t total_ticks; |
7c2cb42b | 1031 | |
942a155b | 1032 | if (!arm_ccnt_enabled(env)) { |
7c2cb42b AF |
1033 | /* Counter is disabled, do not change value */ |
1034 | return env->cp15.c15_ccnt; | |
1035 | } | |
1036 | ||
352c98e5 LV |
1037 | total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
1038 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); | |
7c2cb42b AF |
1039 | |
1040 | if (env->cp15.c9_pmcr & PMCRD) { | |
1041 | /* Increment once every 64 processor clock cycles */ | |
1042 | total_ticks /= 64; | |
1043 | } | |
1044 | return total_ticks - env->cp15.c15_ccnt; | |
1045 | } | |
1046 | ||
6b040780 WH |
1047 | static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1048 | uint64_t value) | |
1049 | { | |
1050 | /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and | |
1051 | * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the | |
1052 | * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are | |
1053 | * accessed. | |
1054 | */ | |
1055 | env->cp15.c9_pmselr = value & 0x1f; | |
1056 | } | |
1057 | ||
7c2cb42b AF |
1058 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1059 | uint64_t value) | |
1060 | { | |
c92c0687 | 1061 | uint64_t total_ticks; |
7c2cb42b | 1062 | |
942a155b | 1063 | if (!arm_ccnt_enabled(env)) { |
7c2cb42b AF |
1064 | /* Counter is disabled, set the absolute value */ |
1065 | env->cp15.c15_ccnt = value; | |
1066 | return; | |
1067 | } | |
1068 | ||
352c98e5 LV |
1069 | total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), |
1070 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); | |
7c2cb42b AF |
1071 | |
1072 | if (env->cp15.c9_pmcr & PMCRD) { | |
1073 | /* Increment once every 64 processor clock cycles */ | |
1074 | total_ticks /= 64; | |
1075 | } | |
1076 | env->cp15.c15_ccnt = total_ticks - value; | |
200ac0ef | 1077 | } |
421c7ebd PC |
1078 | |
1079 | static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1080 | uint64_t value) | |
1081 | { | |
1082 | uint64_t cur_val = pmccntr_read(env, NULL); | |
1083 | ||
1084 | pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); | |
1085 | } | |
1086 | ||
ec7b4ce4 AF |
1087 | #else /* CONFIG_USER_ONLY */ |
1088 | ||
1089 | void pmccntr_sync(CPUARMState *env) | |
1090 | { | |
1091 | } | |
1092 | ||
7c2cb42b | 1093 | #endif |
200ac0ef | 1094 | |
0614601c AF |
1095 | static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1096 | uint64_t value) | |
1097 | { | |
1098 | pmccntr_sync(env); | |
1099 | env->cp15.pmccfiltr_el0 = value & 0x7E000000; | |
1100 | pmccntr_sync(env); | |
1101 | } | |
1102 | ||
c4241c7d | 1103 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1104 | uint64_t value) |
1105 | { | |
200ac0ef PM |
1106 | value &= (1 << 31); |
1107 | env->cp15.c9_pmcnten |= value; | |
200ac0ef PM |
1108 | } |
1109 | ||
c4241c7d PM |
1110 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1111 | uint64_t value) | |
200ac0ef | 1112 | { |
200ac0ef PM |
1113 | value &= (1 << 31); |
1114 | env->cp15.c9_pmcnten &= ~value; | |
200ac0ef PM |
1115 | } |
1116 | ||
c4241c7d PM |
1117 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1118 | uint64_t value) | |
200ac0ef | 1119 | { |
200ac0ef | 1120 | env->cp15.c9_pmovsr &= ~value; |
200ac0ef PM |
1121 | } |
1122 | ||
c4241c7d PM |
1123 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1124 | uint64_t value) | |
200ac0ef | 1125 | { |
fdb86656 WH |
1126 | /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when |
1127 | * PMSELR value is equal to or greater than the number of implemented | |
1128 | * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. | |
1129 | */ | |
1130 | if (env->cp15.c9_pmselr == 0x1f) { | |
1131 | pmccfiltr_write(env, ri, value); | |
1132 | } | |
1133 | } | |
1134 | ||
1135 | static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1136 | { | |
1137 | /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER | |
1138 | * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write(). | |
1139 | */ | |
1140 | if (env->cp15.c9_pmselr == 0x1f) { | |
1141 | return env->cp15.pmccfiltr_el0; | |
1142 | } else { | |
1143 | return 0; | |
1144 | } | |
200ac0ef PM |
1145 | } |
1146 | ||
c4241c7d | 1147 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1148 | uint64_t value) |
1149 | { | |
6ecd0b6b AB |
1150 | if (arm_feature(env, ARM_FEATURE_V8)) { |
1151 | env->cp15.c9_pmuserenr = value & 0xf; | |
1152 | } else { | |
1153 | env->cp15.c9_pmuserenr = value & 1; | |
1154 | } | |
200ac0ef PM |
1155 | } |
1156 | ||
c4241c7d PM |
1157 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1158 | uint64_t value) | |
200ac0ef PM |
1159 | { |
1160 | /* We have no event counters so only the C bit can be changed */ | |
1161 | value &= (1 << 31); | |
1162 | env->cp15.c9_pminten |= value; | |
200ac0ef PM |
1163 | } |
1164 | ||
c4241c7d PM |
1165 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1166 | uint64_t value) | |
200ac0ef PM |
1167 | { |
1168 | value &= (1 << 31); | |
1169 | env->cp15.c9_pminten &= ~value; | |
200ac0ef PM |
1170 | } |
1171 | ||
c4241c7d PM |
1172 | static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1173 | uint64_t value) | |
8641136c | 1174 | { |
a505d7fe PM |
1175 | /* Note that even though the AArch64 view of this register has bits |
1176 | * [10:0] all RES0 we can only mask the bottom 5, to comply with the | |
1177 | * architectural requirements for bits which are RES0 only in some | |
1178 | * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 | |
1179 | * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) | |
1180 | */ | |
855ea66d | 1181 | raw_write(env, ri, value & ~0x1FULL); |
8641136c NR |
1182 | } |
1183 | ||
64e0e2de EI |
1184 | static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
1185 | { | |
1186 | /* We only mask off bits that are RES0 both for AArch64 and AArch32. | |
1187 | * For bits that vary between AArch32/64, code needs to check the | |
1188 | * current execution mode before directly using the feature bit. | |
1189 | */ | |
1190 | uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK; | |
1191 | ||
1192 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | |
1193 | valid_mask &= ~SCR_HCE; | |
1194 | ||
1195 | /* On ARMv7, SMD (or SCD as it is called in v7) is only | |
1196 | * supported if EL2 exists. The bit is UNK/SBZP when | |
1197 | * EL2 is unavailable. In QEMU ARMv7, we force it to always zero | |
1198 | * when EL2 is unavailable. | |
4eb27640 | 1199 | * On ARMv8, this bit is always available. |
64e0e2de | 1200 | */ |
4eb27640 GB |
1201 | if (arm_feature(env, ARM_FEATURE_V7) && |
1202 | !arm_feature(env, ARM_FEATURE_V8)) { | |
64e0e2de EI |
1203 | valid_mask &= ~SCR_SMD; |
1204 | } | |
1205 | } | |
1206 | ||
1207 | /* Clear all-context RES0 bits. */ | |
1208 | value &= valid_mask; | |
1209 | raw_write(env, ri, value); | |
1210 | } | |
1211 | ||
c4241c7d | 1212 | static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
776d4e5c PM |
1213 | { |
1214 | ARMCPU *cpu = arm_env_get_cpu(env); | |
b85a1fd6 FA |
1215 | |
1216 | /* Acquire the CSSELR index from the bank corresponding to the CCSIDR | |
1217 | * bank | |
1218 | */ | |
1219 | uint32_t index = A32_BANKED_REG_GET(env, csselr, | |
1220 | ri->secure & ARM_CP_SECSTATE_S); | |
1221 | ||
1222 | return cpu->ccsidr[index]; | |
776d4e5c PM |
1223 | } |
1224 | ||
c4241c7d PM |
1225 | static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1226 | uint64_t value) | |
776d4e5c | 1227 | { |
8d5c773e | 1228 | raw_write(env, ri, value & 0xf); |
776d4e5c PM |
1229 | } |
1230 | ||
1090b9c6 PM |
1231 | static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1232 | { | |
1233 | CPUState *cs = ENV_GET_CPU(env); | |
1234 | uint64_t ret = 0; | |
1235 | ||
1236 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { | |
1237 | ret |= CPSR_I; | |
1238 | } | |
1239 | if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { | |
1240 | ret |= CPSR_F; | |
1241 | } | |
1242 | /* External aborts are not possible in QEMU so A bit is always clear */ | |
1243 | return ret; | |
1244 | } | |
1245 | ||
e9aa6c21 | 1246 | static const ARMCPRegInfo v7_cp_reginfo[] = { |
7d57f408 PM |
1247 | /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ |
1248 | { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
1249 | .access = PL1_W, .type = ARM_CP_NOP }, | |
200ac0ef PM |
1250 | /* Performance monitors are implementation defined in v7, |
1251 | * but with an ARM recommended set of registers, which we | |
1252 | * follow (although we don't actually implement any counters) | |
1253 | * | |
1254 | * Performance registers fall into three categories: | |
1255 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) | |
1256 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) | |
1257 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) | |
1258 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW | |
1259 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. | |
1260 | */ | |
1261 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 1262 | .access = PL0_RW, .type = ARM_CP_ALIAS, |
8521466b | 1263 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), |
fcd25206 PM |
1264 | .writefn = pmcntenset_write, |
1265 | .accessfn = pmreg_access, | |
1266 | .raw_writefn = raw_write }, | |
8521466b AF |
1267 | { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, |
1268 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, | |
1269 | .access = PL0_RW, .accessfn = pmreg_access, | |
1270 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, | |
1271 | .writefn = pmcntenset_write, .raw_writefn = raw_write }, | |
200ac0ef | 1272 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
8521466b AF |
1273 | .access = PL0_RW, |
1274 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
1275 | .accessfn = pmreg_access, |
1276 | .writefn = pmcntenclr_write, | |
7a0e58fa | 1277 | .type = ARM_CP_ALIAS }, |
8521466b AF |
1278 | { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, |
1279 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, | |
1280 | .access = PL0_RW, .accessfn = pmreg_access, | |
7a0e58fa | 1281 | .type = ARM_CP_ALIAS, |
8521466b AF |
1282 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), |
1283 | .writefn = pmcntenclr_write }, | |
200ac0ef PM |
1284 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
1285 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), | |
fcd25206 PM |
1286 | .accessfn = pmreg_access, |
1287 | .writefn = pmovsr_write, | |
1288 | .raw_writefn = raw_write }, | |
978364f1 AF |
1289 | { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, |
1290 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, | |
1291 | .access = PL0_RW, .accessfn = pmreg_access, | |
1292 | .type = ARM_CP_ALIAS, | |
1293 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), | |
1294 | .writefn = pmovsr_write, | |
1295 | .raw_writefn = raw_write }, | |
fcd25206 | 1296 | /* Unimplemented so WI. */ |
200ac0ef | 1297 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
6ecd0b6b | 1298 | .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP }, |
7c2cb42b | 1299 | #ifndef CONFIG_USER_ONLY |
6b040780 WH |
1300 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, |
1301 | .access = PL0_RW, .type = ARM_CP_ALIAS, | |
1302 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), | |
6ecd0b6b | 1303 | .accessfn = pmreg_access_selr, .writefn = pmselr_write, |
6b040780 WH |
1304 | .raw_writefn = raw_write}, |
1305 | { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, | |
1306 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, | |
6ecd0b6b | 1307 | .access = PL0_RW, .accessfn = pmreg_access_selr, |
6b040780 WH |
1308 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), |
1309 | .writefn = pmselr_write, .raw_writefn = raw_write, }, | |
200ac0ef | 1310 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
7c2cb42b | 1311 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, |
421c7ebd | 1312 | .readfn = pmccntr_read, .writefn = pmccntr_write32, |
6ecd0b6b | 1313 | .accessfn = pmreg_access_ccntr }, |
8521466b AF |
1314 | { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, |
1315 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, | |
6ecd0b6b | 1316 | .access = PL0_RW, .accessfn = pmreg_access_ccntr, |
8521466b AF |
1317 | .type = ARM_CP_IO, |
1318 | .readfn = pmccntr_read, .writefn = pmccntr_write, }, | |
7c2cb42b | 1319 | #endif |
8521466b AF |
1320 | { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, |
1321 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, | |
0614601c | 1322 | .writefn = pmccfiltr_write, |
8521466b AF |
1323 | .access = PL0_RW, .accessfn = pmreg_access, |
1324 | .type = ARM_CP_IO, | |
1325 | .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), | |
1326 | .resetvalue = 0, }, | |
200ac0ef | 1327 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
fdb86656 WH |
1328 | .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access, |
1329 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, | |
1330 | { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, | |
1331 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, | |
1332 | .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access, | |
1333 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, | |
fcd25206 | 1334 | /* Unimplemented, RAZ/WI. */ |
200ac0ef | 1335 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
fcd25206 | 1336 | .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
6ecd0b6b | 1337 | .accessfn = pmreg_access_xevcntr }, |
200ac0ef | 1338 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
1fce1ba9 | 1339 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, |
200ac0ef PM |
1340 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), |
1341 | .resetvalue = 0, | |
d4e6df63 | 1342 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
8a83ffc2 AF |
1343 | { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, |
1344 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, | |
1fce1ba9 | 1345 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, |
8a83ffc2 AF |
1346 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), |
1347 | .resetvalue = 0, | |
1348 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, | |
200ac0ef | 1349 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
1fce1ba9 | 1350 | .access = PL1_RW, .accessfn = access_tpm, |
e6ec5457 WH |
1351 | .type = ARM_CP_ALIAS, |
1352 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), | |
200ac0ef | 1353 | .resetvalue = 0, |
d4e6df63 | 1354 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
e6ec5457 WH |
1355 | { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, |
1356 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, | |
1357 | .access = PL1_RW, .accessfn = access_tpm, | |
1358 | .type = ARM_CP_IO, | |
1359 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
1360 | .writefn = pmintenset_write, .raw_writefn = raw_write, | |
1361 | .resetvalue = 0x0 }, | |
200ac0ef | 1362 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
1fce1ba9 | 1363 | .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, |
200ac0ef | 1364 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
b061a82b | 1365 | .writefn = pmintenclr_write, }, |
978364f1 AF |
1366 | { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, |
1367 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, | |
1fce1ba9 | 1368 | .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, |
978364f1 AF |
1369 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
1370 | .writefn = pmintenclr_write }, | |
7da845b0 PM |
1371 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, |
1372 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | |
7a0e58fa | 1373 | .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, |
7da845b0 PM |
1374 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, |
1375 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | |
b85a1fd6 FA |
1376 | .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, |
1377 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), | |
1378 | offsetof(CPUARMState, cp15.csselr_ns) } }, | |
776d4e5c PM |
1379 | /* Auxiliary ID register: this actually has an IMPDEF value but for now |
1380 | * just RAZ for all cores: | |
1381 | */ | |
0ff644a7 PM |
1382 | { .name = "AIDR", .state = ARM_CP_STATE_BOTH, |
1383 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, | |
776d4e5c | 1384 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f32cdad5 PM |
1385 | /* Auxiliary fault status registers: these also are IMPDEF, and we |
1386 | * choose to RAZ/WI for all cores. | |
1387 | */ | |
1388 | { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, | |
1389 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, | |
1390 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1391 | { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, | |
1392 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, | |
1393 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b0fe2427 PM |
1394 | /* MAIR can just read-as-written because we don't implement caches |
1395 | * and so don't need to care about memory attributes. | |
1396 | */ | |
1397 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | |
1398 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | |
be693c87 | 1399 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), |
b0fe2427 | 1400 | .resetvalue = 0 }, |
4cfb8ad8 PM |
1401 | { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, |
1402 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, | |
1403 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), | |
1404 | .resetvalue = 0 }, | |
b0fe2427 PM |
1405 | /* For non-long-descriptor page tables these are PRRR and NMRR; |
1406 | * regardless they still act as reads-as-written for QEMU. | |
b0fe2427 | 1407 | */ |
1281f8e3 | 1408 | /* MAIR0/1 are defined separately from their 64-bit counterpart which |
be693c87 GB |
1409 | * allows them to assign the correct fieldoffset based on the endianness |
1410 | * handled in the field definitions. | |
1411 | */ | |
a903c449 | 1412 | { .name = "MAIR0", .state = ARM_CP_STATE_AA32, |
b0fe2427 | 1413 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, |
be693c87 GB |
1414 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), |
1415 | offsetof(CPUARMState, cp15.mair0_ns) }, | |
b0fe2427 | 1416 | .resetfn = arm_cp_reset_ignore }, |
a903c449 | 1417 | { .name = "MAIR1", .state = ARM_CP_STATE_AA32, |
b0fe2427 | 1418 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, |
be693c87 GB |
1419 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), |
1420 | offsetof(CPUARMState, cp15.mair1_ns) }, | |
b0fe2427 | 1421 | .resetfn = arm_cp_reset_ignore }, |
1090b9c6 PM |
1422 | { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, |
1423 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, | |
7a0e58fa | 1424 | .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, |
995939a6 PM |
1425 | /* 32 bit ITLB invalidates */ |
1426 | { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, | |
7a0e58fa | 1427 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 1428 | { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, |
7a0e58fa | 1429 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 1430 | { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, |
7a0e58fa | 1431 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 PM |
1432 | /* 32 bit DTLB invalidates */ |
1433 | { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, | |
7a0e58fa | 1434 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 1435 | { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, |
7a0e58fa | 1436 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 1437 | { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, |
7a0e58fa | 1438 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 PM |
1439 | /* 32 bit TLB invalidates */ |
1440 | { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | |
7a0e58fa | 1441 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 1442 | { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
7a0e58fa | 1443 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 1444 | { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
7a0e58fa | 1445 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 | 1446 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
7a0e58fa | 1447 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, |
995939a6 PM |
1448 | REGINFO_SENTINEL |
1449 | }; | |
1450 | ||
1451 | static const ARMCPRegInfo v7mp_cp_reginfo[] = { | |
1452 | /* 32 bit TLB invalidates, Inner Shareable */ | |
1453 | { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | |
7a0e58fa | 1454 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write }, |
995939a6 | 1455 | { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
7a0e58fa | 1456 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, |
995939a6 | 1457 | { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
7a0e58fa | 1458 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 1459 | .writefn = tlbiasid_is_write }, |
995939a6 | 1460 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
7a0e58fa | 1461 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 1462 | .writefn = tlbimvaa_is_write }, |
e9aa6c21 PM |
1463 | REGINFO_SENTINEL |
1464 | }; | |
1465 | ||
c4241c7d PM |
1466 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1467 | uint64_t value) | |
c326b979 PM |
1468 | { |
1469 | value &= 1; | |
1470 | env->teecr = value; | |
c326b979 PM |
1471 | } |
1472 | ||
3f208fd7 PM |
1473 | static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1474 | bool isread) | |
c326b979 | 1475 | { |
dcbff19b | 1476 | if (arm_current_el(env) == 0 && (env->teecr & 1)) { |
92611c00 | 1477 | return CP_ACCESS_TRAP; |
c326b979 | 1478 | } |
92611c00 | 1479 | return CP_ACCESS_OK; |
c326b979 PM |
1480 | } |
1481 | ||
1482 | static const ARMCPRegInfo t2ee_cp_reginfo[] = { | |
1483 | { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, | |
1484 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), | |
1485 | .resetvalue = 0, | |
1486 | .writefn = teecr_write }, | |
1487 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, | |
1488 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | |
92611c00 | 1489 | .accessfn = teehbr_access, .resetvalue = 0 }, |
c326b979 PM |
1490 | REGINFO_SENTINEL |
1491 | }; | |
1492 | ||
4d31c596 | 1493 | static const ARMCPRegInfo v6k_cp_reginfo[] = { |
e4fe830b PM |
1494 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, |
1495 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | |
1496 | .access = PL0_RW, | |
54bf36ed | 1497 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, |
4d31c596 PM |
1498 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
1499 | .access = PL0_RW, | |
54bf36ed FA |
1500 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), |
1501 | offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, | |
e4fe830b PM |
1502 | .resetfn = arm_cp_reset_ignore }, |
1503 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | |
1504 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | |
1505 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
1506 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), |
1507 | .resetvalue = 0}, | |
4d31c596 PM |
1508 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
1509 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
1510 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), |
1511 | offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, | |
e4fe830b | 1512 | .resetfn = arm_cp_reset_ignore }, |
54bf36ed | 1513 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, |
e4fe830b | 1514 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, |
4d31c596 | 1515 | .access = PL1_RW, |
54bf36ed FA |
1516 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, |
1517 | { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, | |
1518 | .access = PL1_RW, | |
1519 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), | |
1520 | offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, | |
1521 | .resetvalue = 0 }, | |
4d31c596 PM |
1522 | REGINFO_SENTINEL |
1523 | }; | |
1524 | ||
55d284af PM |
1525 | #ifndef CONFIG_USER_ONLY |
1526 | ||
3f208fd7 PM |
1527 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1528 | bool isread) | |
00108f2d | 1529 | { |
75502672 PM |
1530 | /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. |
1531 | * Writable only at the highest implemented exception level. | |
1532 | */ | |
1533 | int el = arm_current_el(env); | |
1534 | ||
1535 | switch (el) { | |
1536 | case 0: | |
1537 | if (!extract32(env->cp15.c14_cntkctl, 0, 2)) { | |
1538 | return CP_ACCESS_TRAP; | |
1539 | } | |
1540 | break; | |
1541 | case 1: | |
1542 | if (!isread && ri->state == ARM_CP_STATE_AA32 && | |
1543 | arm_is_secure_below_el3(env)) { | |
1544 | /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ | |
1545 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
1546 | } | |
1547 | break; | |
1548 | case 2: | |
1549 | case 3: | |
1550 | break; | |
00108f2d | 1551 | } |
75502672 PM |
1552 | |
1553 | if (!isread && el < arm_highest_el(env)) { | |
1554 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
1555 | } | |
1556 | ||
00108f2d PM |
1557 | return CP_ACCESS_OK; |
1558 | } | |
1559 | ||
3f208fd7 PM |
1560 | static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, |
1561 | bool isread) | |
00108f2d | 1562 | { |
0b6440af EI |
1563 | unsigned int cur_el = arm_current_el(env); |
1564 | bool secure = arm_is_secure(env); | |
1565 | ||
00108f2d | 1566 | /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ |
0b6440af | 1567 | if (cur_el == 0 && |
00108f2d PM |
1568 | !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { |
1569 | return CP_ACCESS_TRAP; | |
1570 | } | |
0b6440af EI |
1571 | |
1572 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
1573 | timeridx == GTIMER_PHYS && !secure && cur_el < 2 && | |
1574 | !extract32(env->cp15.cnthctl_el2, 0, 1)) { | |
1575 | return CP_ACCESS_TRAP_EL2; | |
1576 | } | |
00108f2d PM |
1577 | return CP_ACCESS_OK; |
1578 | } | |
1579 | ||
3f208fd7 PM |
1580 | static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, |
1581 | bool isread) | |
00108f2d | 1582 | { |
0b6440af EI |
1583 | unsigned int cur_el = arm_current_el(env); |
1584 | bool secure = arm_is_secure(env); | |
1585 | ||
00108f2d PM |
1586 | /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if |
1587 | * EL0[PV]TEN is zero. | |
1588 | */ | |
0b6440af | 1589 | if (cur_el == 0 && |
00108f2d PM |
1590 | !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { |
1591 | return CP_ACCESS_TRAP; | |
1592 | } | |
0b6440af EI |
1593 | |
1594 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
1595 | timeridx == GTIMER_PHYS && !secure && cur_el < 2 && | |
1596 | !extract32(env->cp15.cnthctl_el2, 1, 1)) { | |
1597 | return CP_ACCESS_TRAP_EL2; | |
1598 | } | |
00108f2d PM |
1599 | return CP_ACCESS_OK; |
1600 | } | |
1601 | ||
1602 | static CPAccessResult gt_pct_access(CPUARMState *env, | |
3f208fd7 PM |
1603 | const ARMCPRegInfo *ri, |
1604 | bool isread) | |
00108f2d | 1605 | { |
3f208fd7 | 1606 | return gt_counter_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
1607 | } |
1608 | ||
1609 | static CPAccessResult gt_vct_access(CPUARMState *env, | |
3f208fd7 PM |
1610 | const ARMCPRegInfo *ri, |
1611 | bool isread) | |
00108f2d | 1612 | { |
3f208fd7 | 1613 | return gt_counter_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
1614 | } |
1615 | ||
3f208fd7 PM |
1616 | static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1617 | bool isread) | |
00108f2d | 1618 | { |
3f208fd7 | 1619 | return gt_timer_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
1620 | } |
1621 | ||
3f208fd7 PM |
1622 | static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1623 | bool isread) | |
00108f2d | 1624 | { |
3f208fd7 | 1625 | return gt_timer_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
1626 | } |
1627 | ||
b4d3978c | 1628 | static CPAccessResult gt_stimer_access(CPUARMState *env, |
3f208fd7 PM |
1629 | const ARMCPRegInfo *ri, |
1630 | bool isread) | |
b4d3978c PM |
1631 | { |
1632 | /* The AArch64 register view of the secure physical timer is | |
1633 | * always accessible from EL3, and configurably accessible from | |
1634 | * Secure EL1. | |
1635 | */ | |
1636 | switch (arm_current_el(env)) { | |
1637 | case 1: | |
1638 | if (!arm_is_secure(env)) { | |
1639 | return CP_ACCESS_TRAP; | |
1640 | } | |
1641 | if (!(env->cp15.scr_el3 & SCR_ST)) { | |
1642 | return CP_ACCESS_TRAP_EL3; | |
1643 | } | |
1644 | return CP_ACCESS_OK; | |
1645 | case 0: | |
1646 | case 2: | |
1647 | return CP_ACCESS_TRAP; | |
1648 | case 3: | |
1649 | return CP_ACCESS_OK; | |
1650 | default: | |
1651 | g_assert_not_reached(); | |
1652 | } | |
1653 | } | |
1654 | ||
55d284af PM |
1655 | static uint64_t gt_get_countervalue(CPUARMState *env) |
1656 | { | |
bc72ad67 | 1657 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; |
55d284af PM |
1658 | } |
1659 | ||
1660 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) | |
1661 | { | |
1662 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; | |
1663 | ||
1664 | if (gt->ctl & 1) { | |
1665 | /* Timer enabled: calculate and set current ISTATUS, irq, and | |
1666 | * reset timer to when ISTATUS next has to change | |
1667 | */ | |
edac4d8a EI |
1668 | uint64_t offset = timeridx == GTIMER_VIRT ? |
1669 | cpu->env.cp15.cntvoff_el2 : 0; | |
55d284af PM |
1670 | uint64_t count = gt_get_countervalue(&cpu->env); |
1671 | /* Note that this must be unsigned 64 bit arithmetic: */ | |
edac4d8a | 1672 | int istatus = count - offset >= gt->cval; |
55d284af | 1673 | uint64_t nexttick; |
194cbc49 | 1674 | int irqstate; |
55d284af PM |
1675 | |
1676 | gt->ctl = deposit32(gt->ctl, 2, 1, istatus); | |
194cbc49 PM |
1677 | |
1678 | irqstate = (istatus && !(gt->ctl & 2)); | |
1679 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
1680 | ||
55d284af PM |
1681 | if (istatus) { |
1682 | /* Next transition is when count rolls back over to zero */ | |
1683 | nexttick = UINT64_MAX; | |
1684 | } else { | |
1685 | /* Next transition is when we hit cval */ | |
edac4d8a | 1686 | nexttick = gt->cval + offset; |
55d284af PM |
1687 | } |
1688 | /* Note that the desired next expiry time might be beyond the | |
1689 | * signed-64-bit range of a QEMUTimer -- in this case we just | |
1690 | * set the timer for as far in the future as possible. When the | |
1691 | * timer expires we will reset the timer for any remaining period. | |
1692 | */ | |
1693 | if (nexttick > INT64_MAX / GTIMER_SCALE) { | |
1694 | nexttick = INT64_MAX / GTIMER_SCALE; | |
1695 | } | |
bc72ad67 | 1696 | timer_mod(cpu->gt_timer[timeridx], nexttick); |
194cbc49 | 1697 | trace_arm_gt_recalc(timeridx, irqstate, nexttick); |
55d284af PM |
1698 | } else { |
1699 | /* Timer disabled: ISTATUS and timer output always clear */ | |
1700 | gt->ctl &= ~4; | |
1701 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); | |
bc72ad67 | 1702 | timer_del(cpu->gt_timer[timeridx]); |
194cbc49 | 1703 | trace_arm_gt_recalc_disabled(timeridx); |
55d284af PM |
1704 | } |
1705 | } | |
1706 | ||
0e3eca4c EI |
1707 | static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, |
1708 | int timeridx) | |
55d284af PM |
1709 | { |
1710 | ARMCPU *cpu = arm_env_get_cpu(env); | |
55d284af | 1711 | |
bc72ad67 | 1712 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
1713 | } |
1714 | ||
c4241c7d | 1715 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
55d284af | 1716 | { |
c4241c7d | 1717 | return gt_get_countervalue(env); |
55d284af PM |
1718 | } |
1719 | ||
edac4d8a EI |
1720 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1721 | { | |
1722 | return gt_get_countervalue(env) - env->cp15.cntvoff_el2; | |
1723 | } | |
1724 | ||
c4241c7d | 1725 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 1726 | int timeridx, |
c4241c7d | 1727 | uint64_t value) |
55d284af | 1728 | { |
194cbc49 | 1729 | trace_arm_gt_cval_write(timeridx, value); |
55d284af PM |
1730 | env->cp15.c14_timer[timeridx].cval = value; |
1731 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); | |
55d284af | 1732 | } |
c4241c7d | 1733 | |
0e3eca4c EI |
1734 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, |
1735 | int timeridx) | |
55d284af | 1736 | { |
edac4d8a | 1737 | uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; |
55d284af | 1738 | |
c4241c7d | 1739 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - |
edac4d8a | 1740 | (gt_get_countervalue(env) - offset)); |
55d284af PM |
1741 | } |
1742 | ||
c4241c7d | 1743 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 1744 | int timeridx, |
c4241c7d | 1745 | uint64_t value) |
55d284af | 1746 | { |
edac4d8a | 1747 | uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; |
55d284af | 1748 | |
194cbc49 | 1749 | trace_arm_gt_tval_write(timeridx, value); |
edac4d8a | 1750 | env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + |
18084b2f | 1751 | sextract64(value, 0, 32); |
55d284af | 1752 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); |
55d284af PM |
1753 | } |
1754 | ||
c4241c7d | 1755 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 1756 | int timeridx, |
c4241c7d | 1757 | uint64_t value) |
55d284af PM |
1758 | { |
1759 | ARMCPU *cpu = arm_env_get_cpu(env); | |
55d284af PM |
1760 | uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; |
1761 | ||
194cbc49 | 1762 | trace_arm_gt_ctl_write(timeridx, value); |
d3afacc7 | 1763 | env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); |
55d284af PM |
1764 | if ((oldval ^ value) & 1) { |
1765 | /* Enable toggled */ | |
1766 | gt_recalc_timer(cpu, timeridx); | |
d3afacc7 | 1767 | } else if ((oldval ^ value) & 2) { |
55d284af PM |
1768 | /* IMASK toggled: don't need to recalculate, |
1769 | * just set the interrupt line based on ISTATUS | |
1770 | */ | |
194cbc49 PM |
1771 | int irqstate = (oldval & 4) && !(value & 2); |
1772 | ||
1773 | trace_arm_gt_imask_toggle(timeridx, irqstate); | |
1774 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
55d284af | 1775 | } |
55d284af PM |
1776 | } |
1777 | ||
0e3eca4c EI |
1778 | static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1779 | { | |
1780 | gt_timer_reset(env, ri, GTIMER_PHYS); | |
1781 | } | |
1782 | ||
1783 | static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1784 | uint64_t value) | |
1785 | { | |
1786 | gt_cval_write(env, ri, GTIMER_PHYS, value); | |
1787 | } | |
1788 | ||
1789 | static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1790 | { | |
1791 | return gt_tval_read(env, ri, GTIMER_PHYS); | |
1792 | } | |
1793 | ||
1794 | static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1795 | uint64_t value) | |
1796 | { | |
1797 | gt_tval_write(env, ri, GTIMER_PHYS, value); | |
1798 | } | |
1799 | ||
1800 | static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1801 | uint64_t value) | |
1802 | { | |
1803 | gt_ctl_write(env, ri, GTIMER_PHYS, value); | |
1804 | } | |
1805 | ||
1806 | static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) | |
1807 | { | |
1808 | gt_timer_reset(env, ri, GTIMER_VIRT); | |
1809 | } | |
1810 | ||
1811 | static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1812 | uint64_t value) | |
1813 | { | |
1814 | gt_cval_write(env, ri, GTIMER_VIRT, value); | |
1815 | } | |
1816 | ||
1817 | static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1818 | { | |
1819 | return gt_tval_read(env, ri, GTIMER_VIRT); | |
1820 | } | |
1821 | ||
1822 | static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1823 | uint64_t value) | |
1824 | { | |
1825 | gt_tval_write(env, ri, GTIMER_VIRT, value); | |
1826 | } | |
1827 | ||
1828 | static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1829 | uint64_t value) | |
1830 | { | |
1831 | gt_ctl_write(env, ri, GTIMER_VIRT, value); | |
1832 | } | |
1833 | ||
edac4d8a EI |
1834 | static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1835 | uint64_t value) | |
1836 | { | |
1837 | ARMCPU *cpu = arm_env_get_cpu(env); | |
1838 | ||
194cbc49 | 1839 | trace_arm_gt_cntvoff_write(value); |
edac4d8a EI |
1840 | raw_write(env, ri, value); |
1841 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
1842 | } | |
1843 | ||
b0e66d95 EI |
1844 | static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1845 | { | |
1846 | gt_timer_reset(env, ri, GTIMER_HYP); | |
1847 | } | |
1848 | ||
1849 | static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1850 | uint64_t value) | |
1851 | { | |
1852 | gt_cval_write(env, ri, GTIMER_HYP, value); | |
1853 | } | |
1854 | ||
1855 | static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1856 | { | |
1857 | return gt_tval_read(env, ri, GTIMER_HYP); | |
1858 | } | |
1859 | ||
1860 | static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1861 | uint64_t value) | |
1862 | { | |
1863 | gt_tval_write(env, ri, GTIMER_HYP, value); | |
1864 | } | |
1865 | ||
1866 | static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1867 | uint64_t value) | |
1868 | { | |
1869 | gt_ctl_write(env, ri, GTIMER_HYP, value); | |
1870 | } | |
1871 | ||
b4d3978c PM |
1872 | static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1873 | { | |
1874 | gt_timer_reset(env, ri, GTIMER_SEC); | |
1875 | } | |
1876 | ||
1877 | static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1878 | uint64_t value) | |
1879 | { | |
1880 | gt_cval_write(env, ri, GTIMER_SEC, value); | |
1881 | } | |
1882 | ||
1883 | static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1884 | { | |
1885 | return gt_tval_read(env, ri, GTIMER_SEC); | |
1886 | } | |
1887 | ||
1888 | static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1889 | uint64_t value) | |
1890 | { | |
1891 | gt_tval_write(env, ri, GTIMER_SEC, value); | |
1892 | } | |
1893 | ||
1894 | static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1895 | uint64_t value) | |
1896 | { | |
1897 | gt_ctl_write(env, ri, GTIMER_SEC, value); | |
1898 | } | |
1899 | ||
55d284af PM |
1900 | void arm_gt_ptimer_cb(void *opaque) |
1901 | { | |
1902 | ARMCPU *cpu = opaque; | |
1903 | ||
1904 | gt_recalc_timer(cpu, GTIMER_PHYS); | |
1905 | } | |
1906 | ||
1907 | void arm_gt_vtimer_cb(void *opaque) | |
1908 | { | |
1909 | ARMCPU *cpu = opaque; | |
1910 | ||
1911 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
1912 | } | |
1913 | ||
b0e66d95 EI |
1914 | void arm_gt_htimer_cb(void *opaque) |
1915 | { | |
1916 | ARMCPU *cpu = opaque; | |
1917 | ||
1918 | gt_recalc_timer(cpu, GTIMER_HYP); | |
1919 | } | |
1920 | ||
b4d3978c PM |
1921 | void arm_gt_stimer_cb(void *opaque) |
1922 | { | |
1923 | ARMCPU *cpu = opaque; | |
1924 | ||
1925 | gt_recalc_timer(cpu, GTIMER_SEC); | |
1926 | } | |
1927 | ||
55d284af PM |
1928 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
1929 | /* Note that CNTFRQ is purely reads-as-written for the benefit | |
1930 | * of software; writing it doesn't actually change the timer frequency. | |
1931 | * Our reset value matches the fixed frequency we implement the timer at. | |
1932 | */ | |
1933 | { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 1934 | .type = ARM_CP_ALIAS, |
a7adc4b7 PM |
1935 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, |
1936 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), | |
a7adc4b7 PM |
1937 | }, |
1938 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, | |
1939 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
1940 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
55d284af PM |
1941 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), |
1942 | .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE, | |
55d284af PM |
1943 | }, |
1944 | /* overall control: mostly access permissions */ | |
a7adc4b7 PM |
1945 | { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, |
1946 | .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, | |
55d284af PM |
1947 | .access = PL1_RW, |
1948 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), | |
1949 | .resetvalue = 0, | |
1950 | }, | |
1951 | /* per-timer control */ | |
1952 | { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
9ff9dd3c | 1953 | .secure = ARM_CP_SECSTATE_NS, |
7a0e58fa | 1954 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, |
a7adc4b7 PM |
1955 | .accessfn = gt_ptimer_access, |
1956 | .fieldoffset = offsetoflow32(CPUARMState, | |
1957 | cp15.c14_timer[GTIMER_PHYS].ctl), | |
0e3eca4c | 1958 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, |
a7adc4b7 | 1959 | }, |
9ff9dd3c PM |
1960 | { .name = "CNTP_CTL(S)", |
1961 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
1962 | .secure = ARM_CP_SECSTATE_S, | |
1963 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, | |
1964 | .accessfn = gt_ptimer_access, | |
1965 | .fieldoffset = offsetoflow32(CPUARMState, | |
1966 | cp15.c14_timer[GTIMER_SEC].ctl), | |
1967 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
1968 | }, | |
a7adc4b7 PM |
1969 | { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, |
1970 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, | |
55d284af | 1971 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, |
a7adc4b7 | 1972 | .accessfn = gt_ptimer_access, |
55d284af PM |
1973 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), |
1974 | .resetvalue = 0, | |
0e3eca4c | 1975 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
1976 | }, |
1977 | { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 1978 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, |
a7adc4b7 PM |
1979 | .accessfn = gt_vtimer_access, |
1980 | .fieldoffset = offsetoflow32(CPUARMState, | |
1981 | cp15.c14_timer[GTIMER_VIRT].ctl), | |
0e3eca4c | 1982 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, |
a7adc4b7 PM |
1983 | }, |
1984 | { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
1985 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, | |
55d284af | 1986 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, |
a7adc4b7 | 1987 | .accessfn = gt_vtimer_access, |
55d284af PM |
1988 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), |
1989 | .resetvalue = 0, | |
0e3eca4c | 1990 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
1991 | }, |
1992 | /* TimerValue views: a 32 bit downcounting view of the underlying state */ | |
1993 | { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
9ff9dd3c | 1994 | .secure = ARM_CP_SECSTATE_NS, |
7a0e58fa | 1995 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, |
00108f2d | 1996 | .accessfn = gt_ptimer_access, |
0e3eca4c | 1997 | .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, |
55d284af | 1998 | }, |
9ff9dd3c PM |
1999 | { .name = "CNTP_TVAL(S)", |
2000 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
2001 | .secure = ARM_CP_SECSTATE_S, | |
2002 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
2003 | .accessfn = gt_ptimer_access, | |
2004 | .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, | |
2005 | }, | |
a7adc4b7 PM |
2006 | { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
2007 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, | |
7a0e58fa | 2008 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, |
0e3eca4c EI |
2009 | .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, |
2010 | .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, | |
a7adc4b7 | 2011 | }, |
55d284af | 2012 | { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, |
7a0e58fa | 2013 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, |
00108f2d | 2014 | .accessfn = gt_vtimer_access, |
0e3eca4c | 2015 | .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, |
55d284af | 2016 | }, |
a7adc4b7 PM |
2017 | { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
2018 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, | |
7a0e58fa | 2019 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, |
0e3eca4c EI |
2020 | .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, |
2021 | .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, | |
a7adc4b7 | 2022 | }, |
55d284af PM |
2023 | /* The counter itself */ |
2024 | { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, | |
7a0e58fa | 2025 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 2026 | .accessfn = gt_pct_access, |
a7adc4b7 PM |
2027 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
2028 | }, | |
2029 | { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, | |
2030 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, | |
7a0e58fa | 2031 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 2032 | .accessfn = gt_pct_access, .readfn = gt_cnt_read, |
55d284af PM |
2033 | }, |
2034 | { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, | |
7a0e58fa | 2035 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 2036 | .accessfn = gt_vct_access, |
edac4d8a | 2037 | .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, |
a7adc4b7 PM |
2038 | }, |
2039 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
2040 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
7a0e58fa | 2041 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 2042 | .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, |
55d284af PM |
2043 | }, |
2044 | /* Comparison value, indicating when the timer goes off */ | |
2045 | { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, | |
9ff9dd3c | 2046 | .secure = ARM_CP_SECSTATE_NS, |
55d284af | 2047 | .access = PL1_RW | PL0_R, |
7a0e58fa | 2048 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 2049 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), |
b061a82b | 2050 | .accessfn = gt_ptimer_access, |
0e3eca4c | 2051 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write, |
a7adc4b7 | 2052 | }, |
9ff9dd3c PM |
2053 | { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2, |
2054 | .secure = ARM_CP_SECSTATE_S, | |
2055 | .access = PL1_RW | PL0_R, | |
2056 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, | |
2057 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
2058 | .accessfn = gt_ptimer_access, | |
2059 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
2060 | }, | |
a7adc4b7 PM |
2061 | { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, |
2062 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, | |
2063 | .access = PL1_RW | PL0_R, | |
2064 | .type = ARM_CP_IO, | |
2065 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
12cde08a | 2066 | .resetvalue = 0, .accessfn = gt_ptimer_access, |
0e3eca4c | 2067 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write, |
55d284af PM |
2068 | }, |
2069 | { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, | |
2070 | .access = PL1_RW | PL0_R, | |
7a0e58fa | 2071 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 2072 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), |
b061a82b | 2073 | .accessfn = gt_vtimer_access, |
0e3eca4c | 2074 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write, |
a7adc4b7 PM |
2075 | }, |
2076 | { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
2077 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, | |
2078 | .access = PL1_RW | PL0_R, | |
2079 | .type = ARM_CP_IO, | |
2080 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
2081 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
0e3eca4c | 2082 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write, |
55d284af | 2083 | }, |
b4d3978c PM |
2084 | /* Secure timer -- this is actually restricted to only EL3 |
2085 | * and configurably Secure-EL1 via the accessfn. | |
2086 | */ | |
2087 | { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, | |
2088 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, | |
2089 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, | |
2090 | .accessfn = gt_stimer_access, | |
2091 | .readfn = gt_sec_tval_read, | |
2092 | .writefn = gt_sec_tval_write, | |
2093 | .resetfn = gt_sec_timer_reset, | |
2094 | }, | |
2095 | { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64, | |
2096 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1, | |
2097 | .type = ARM_CP_IO, .access = PL1_RW, | |
2098 | .accessfn = gt_stimer_access, | |
2099 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), | |
2100 | .resetvalue = 0, | |
2101 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
2102 | }, | |
2103 | { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, | |
2104 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, | |
2105 | .type = ARM_CP_IO, .access = PL1_RW, | |
2106 | .accessfn = gt_stimer_access, | |
2107 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
2108 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
2109 | }, | |
55d284af PM |
2110 | REGINFO_SENTINEL |
2111 | }; | |
2112 | ||
2113 | #else | |
2114 | /* In user-mode none of the generic timer registers are accessible, | |
bc72ad67 | 2115 | * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs, |
55d284af PM |
2116 | * so instead just don't register any of them. |
2117 | */ | |
6cc7a3ae | 2118 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
6cc7a3ae PM |
2119 | REGINFO_SENTINEL |
2120 | }; | |
2121 | ||
55d284af PM |
2122 | #endif |
2123 | ||
c4241c7d | 2124 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 2125 | { |
891a2fe7 | 2126 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8d5c773e | 2127 | raw_write(env, ri, value); |
891a2fe7 | 2128 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8d5c773e | 2129 | raw_write(env, ri, value & 0xfffff6ff); |
4a501606 | 2130 | } else { |
8d5c773e | 2131 | raw_write(env, ri, value & 0xfffff1ff); |
4a501606 | 2132 | } |
4a501606 PM |
2133 | } |
2134 | ||
2135 | #ifndef CONFIG_USER_ONLY | |
2136 | /* get_phys_addr() isn't present for user-mode-only targets */ | |
702a9357 | 2137 | |
3f208fd7 PM |
2138 | static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2139 | bool isread) | |
92611c00 PM |
2140 | { |
2141 | if (ri->opc2 & 4) { | |
87562e4f PM |
2142 | /* The ATS12NSO* operations must trap to EL3 if executed in |
2143 | * Secure EL1 (which can only happen if EL3 is AArch64). | |
2144 | * They are simply UNDEF if executed from NS EL1. | |
2145 | * They function normally from EL2 or EL3. | |
92611c00 | 2146 | */ |
87562e4f PM |
2147 | if (arm_current_el(env) == 1) { |
2148 | if (arm_is_secure_below_el3(env)) { | |
2149 | return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; | |
2150 | } | |
2151 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2152 | } | |
92611c00 PM |
2153 | } |
2154 | return CP_ACCESS_OK; | |
2155 | } | |
2156 | ||
060e8a48 | 2157 | static uint64_t do_ats_write(CPUARMState *env, uint64_t value, |
03ae85f8 | 2158 | MMUAccessType access_type, ARMMMUIdx mmu_idx) |
4a501606 | 2159 | { |
a8170e5e | 2160 | hwaddr phys_addr; |
4a501606 PM |
2161 | target_ulong page_size; |
2162 | int prot; | |
b7cc4e82 | 2163 | bool ret; |
01c097f7 | 2164 | uint64_t par64; |
1313e2d7 | 2165 | bool format64 = false; |
8bf5b6a9 | 2166 | MemTxAttrs attrs = {}; |
e14b5a23 | 2167 | ARMMMUFaultInfo fi = {}; |
5b2d261d | 2168 | ARMCacheAttrs cacheattrs = {}; |
4a501606 | 2169 | |
5b2d261d | 2170 | ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, |
bc52bfeb | 2171 | &prot, &page_size, &fi, &cacheattrs); |
1313e2d7 EI |
2172 | |
2173 | if (is_a64(env)) { | |
2174 | format64 = true; | |
2175 | } else if (arm_feature(env, ARM_FEATURE_LPAE)) { | |
2176 | /* | |
2177 | * ATS1Cxx: | |
2178 | * * TTBCR.EAE determines whether the result is returned using the | |
2179 | * 32-bit or the 64-bit PAR format | |
2180 | * * Instructions executed in Hyp mode always use the 64bit format | |
2181 | * | |
2182 | * ATS1S2NSOxx uses the 64bit format if any of the following is true: | |
2183 | * * The Non-secure TTBCR.EAE bit is set to 1 | |
2184 | * * The implementation includes EL2, and the value of HCR.VM is 1 | |
2185 | * | |
2186 | * ATS1Hx always uses the 64bit format (not supported yet). | |
2187 | */ | |
2188 | format64 = arm_s1_regime_using_lpae_format(env, mmu_idx); | |
2189 | ||
2190 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
2191 | if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { | |
2192 | format64 |= env->cp15.hcr_el2 & HCR_VM; | |
2193 | } else { | |
2194 | format64 |= arm_current_el(env) == 2; | |
2195 | } | |
2196 | } | |
2197 | } | |
2198 | ||
2199 | if (format64) { | |
5efe9ed4 | 2200 | /* Create a 64-bit PAR */ |
01c097f7 | 2201 | par64 = (1 << 11); /* LPAE bit always set */ |
b7cc4e82 | 2202 | if (!ret) { |
702a9357 | 2203 | par64 |= phys_addr & ~0xfffULL; |
8bf5b6a9 PM |
2204 | if (!attrs.secure) { |
2205 | par64 |= (1 << 9); /* NS */ | |
2206 | } | |
5b2d261d AB |
2207 | par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */ |
2208 | par64 |= cacheattrs.shareability << 7; /* SH */ | |
4a501606 | 2209 | } else { |
5efe9ed4 PM |
2210 | uint32_t fsr = arm_fi_to_lfsc(&fi); |
2211 | ||
702a9357 | 2212 | par64 |= 1; /* F */ |
b7cc4e82 | 2213 | par64 |= (fsr & 0x3f) << 1; /* FS */ |
702a9357 PM |
2214 | /* Note that S2WLK and FSTAGE are always zero, because we don't |
2215 | * implement virtualization and therefore there can't be a stage 2 | |
2216 | * fault. | |
2217 | */ | |
4a501606 PM |
2218 | } |
2219 | } else { | |
b7cc4e82 | 2220 | /* fsr is a DFSR/IFSR value for the short descriptor |
702a9357 PM |
2221 | * translation table format (with WnR always clear). |
2222 | * Convert it to a 32-bit PAR. | |
2223 | */ | |
b7cc4e82 | 2224 | if (!ret) { |
702a9357 PM |
2225 | /* We do not set any attribute bits in the PAR */ |
2226 | if (page_size == (1 << 24) | |
2227 | && arm_feature(env, ARM_FEATURE_V7)) { | |
01c097f7 | 2228 | par64 = (phys_addr & 0xff000000) | (1 << 1); |
702a9357 | 2229 | } else { |
01c097f7 | 2230 | par64 = phys_addr & 0xfffff000; |
702a9357 | 2231 | } |
8bf5b6a9 PM |
2232 | if (!attrs.secure) { |
2233 | par64 |= (1 << 9); /* NS */ | |
2234 | } | |
702a9357 | 2235 | } else { |
5efe9ed4 PM |
2236 | uint32_t fsr = arm_fi_to_sfsc(&fi); |
2237 | ||
b7cc4e82 PC |
2238 | par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | |
2239 | ((fsr & 0xf) << 1) | 1; | |
702a9357 | 2240 | } |
4a501606 | 2241 | } |
060e8a48 PM |
2242 | return par64; |
2243 | } | |
2244 | ||
2245 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | |
2246 | { | |
03ae85f8 | 2247 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
060e8a48 | 2248 | uint64_t par64; |
d3649702 PM |
2249 | ARMMMUIdx mmu_idx; |
2250 | int el = arm_current_el(env); | |
2251 | bool secure = arm_is_secure_below_el3(env); | |
060e8a48 | 2252 | |
d3649702 PM |
2253 | switch (ri->opc2 & 6) { |
2254 | case 0: | |
2255 | /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ | |
2256 | switch (el) { | |
2257 | case 3: | |
2258 | mmu_idx = ARMMMUIdx_S1E3; | |
2259 | break; | |
2260 | case 2: | |
2261 | mmu_idx = ARMMMUIdx_S1NSE1; | |
2262 | break; | |
2263 | case 1: | |
2264 | mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; | |
2265 | break; | |
2266 | default: | |
2267 | g_assert_not_reached(); | |
2268 | } | |
2269 | break; | |
2270 | case 2: | |
2271 | /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ | |
2272 | switch (el) { | |
2273 | case 3: | |
2274 | mmu_idx = ARMMMUIdx_S1SE0; | |
2275 | break; | |
2276 | case 2: | |
2277 | mmu_idx = ARMMMUIdx_S1NSE0; | |
2278 | break; | |
2279 | case 1: | |
2280 | mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; | |
2281 | break; | |
2282 | default: | |
2283 | g_assert_not_reached(); | |
2284 | } | |
2285 | break; | |
2286 | case 4: | |
2287 | /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ | |
2288 | mmu_idx = ARMMMUIdx_S12NSE1; | |
2289 | break; | |
2290 | case 6: | |
2291 | /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ | |
2292 | mmu_idx = ARMMMUIdx_S12NSE0; | |
2293 | break; | |
2294 | default: | |
2295 | g_assert_not_reached(); | |
2296 | } | |
2297 | ||
2298 | par64 = do_ats_write(env, value, access_type, mmu_idx); | |
01c097f7 FA |
2299 | |
2300 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
4a501606 | 2301 | } |
060e8a48 | 2302 | |
14db7fe0 PM |
2303 | static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2304 | uint64_t value) | |
2305 | { | |
03ae85f8 | 2306 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
14db7fe0 PM |
2307 | uint64_t par64; |
2308 | ||
2309 | par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS); | |
2310 | ||
2311 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
2312 | } | |
2313 | ||
3f208fd7 PM |
2314 | static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2315 | bool isread) | |
2a47df95 PM |
2316 | { |
2317 | if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) { | |
2318 | return CP_ACCESS_TRAP; | |
2319 | } | |
2320 | return CP_ACCESS_OK; | |
2321 | } | |
2322 | ||
060e8a48 PM |
2323 | static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, |
2324 | uint64_t value) | |
2325 | { | |
03ae85f8 | 2326 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
d3649702 PM |
2327 | ARMMMUIdx mmu_idx; |
2328 | int secure = arm_is_secure_below_el3(env); | |
2329 | ||
2330 | switch (ri->opc2 & 6) { | |
2331 | case 0: | |
2332 | switch (ri->opc1) { | |
2333 | case 0: /* AT S1E1R, AT S1E1W */ | |
2334 | mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; | |
2335 | break; | |
2336 | case 4: /* AT S1E2R, AT S1E2W */ | |
2337 | mmu_idx = ARMMMUIdx_S1E2; | |
2338 | break; | |
2339 | case 6: /* AT S1E3R, AT S1E3W */ | |
2340 | mmu_idx = ARMMMUIdx_S1E3; | |
2341 | break; | |
2342 | default: | |
2343 | g_assert_not_reached(); | |
2344 | } | |
2345 | break; | |
2346 | case 2: /* AT S1E0R, AT S1E0W */ | |
2347 | mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; | |
2348 | break; | |
2349 | case 4: /* AT S12E1R, AT S12E1W */ | |
2a47df95 | 2350 | mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1; |
d3649702 PM |
2351 | break; |
2352 | case 6: /* AT S12E0R, AT S12E0W */ | |
2a47df95 | 2353 | mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0; |
d3649702 PM |
2354 | break; |
2355 | default: | |
2356 | g_assert_not_reached(); | |
2357 | } | |
060e8a48 | 2358 | |
d3649702 | 2359 | env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); |
060e8a48 | 2360 | } |
4a501606 PM |
2361 | #endif |
2362 | ||
2363 | static const ARMCPRegInfo vapa_cp_reginfo[] = { | |
2364 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, | |
2365 | .access = PL1_RW, .resetvalue = 0, | |
01c097f7 FA |
2366 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), |
2367 | offsetoflow32(CPUARMState, cp15.par_ns) }, | |
4a501606 PM |
2368 | .writefn = par_write }, |
2369 | #ifndef CONFIG_USER_ONLY | |
87562e4f | 2370 | /* This underdecoding is safe because the reginfo is NO_RAW. */ |
4a501606 | 2371 | { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, |
92611c00 | 2372 | .access = PL1_W, .accessfn = ats_access, |
7a0e58fa | 2373 | .writefn = ats_write, .type = ARM_CP_NO_RAW }, |
4a501606 PM |
2374 | #endif |
2375 | REGINFO_SENTINEL | |
2376 | }; | |
2377 | ||
18032bec PM |
2378 | /* Return basic MPU access permission bits. */ |
2379 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
2380 | { | |
2381 | uint32_t ret; | |
2382 | uint32_t mask; | |
2383 | int i; | |
2384 | ret = 0; | |
2385 | mask = 3; | |
2386 | for (i = 0; i < 16; i += 2) { | |
2387 | ret |= (val >> i) & mask; | |
2388 | mask <<= 2; | |
2389 | } | |
2390 | return ret; | |
2391 | } | |
2392 | ||
2393 | /* Pad basic MPU access permission bits to extended format. */ | |
2394 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
2395 | { | |
2396 | uint32_t ret; | |
2397 | uint32_t mask; | |
2398 | int i; | |
2399 | ret = 0; | |
2400 | mask = 3; | |
2401 | for (i = 0; i < 16; i += 2) { | |
2402 | ret |= (val & mask) << i; | |
2403 | mask <<= 2; | |
2404 | } | |
2405 | return ret; | |
2406 | } | |
2407 | ||
c4241c7d PM |
2408 | static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2409 | uint64_t value) | |
18032bec | 2410 | { |
7e09797c | 2411 | env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); |
18032bec PM |
2412 | } |
2413 | ||
c4241c7d | 2414 | static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 2415 | { |
7e09797c | 2416 | return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); |
18032bec PM |
2417 | } |
2418 | ||
c4241c7d PM |
2419 | static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2420 | uint64_t value) | |
18032bec | 2421 | { |
7e09797c | 2422 | env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); |
18032bec PM |
2423 | } |
2424 | ||
c4241c7d | 2425 | static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 2426 | { |
7e09797c | 2427 | return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); |
18032bec PM |
2428 | } |
2429 | ||
6cb0b013 PC |
2430 | static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2431 | { | |
2432 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); | |
2433 | ||
2434 | if (!u32p) { | |
2435 | return 0; | |
2436 | } | |
2437 | ||
1bc04a88 | 2438 | u32p += env->pmsav7.rnr[M_REG_NS]; |
6cb0b013 PC |
2439 | return *u32p; |
2440 | } | |
2441 | ||
2442 | static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2443 | uint64_t value) | |
2444 | { | |
2445 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2446 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); | |
2447 | ||
2448 | if (!u32p) { | |
2449 | return; | |
2450 | } | |
2451 | ||
1bc04a88 | 2452 | u32p += env->pmsav7.rnr[M_REG_NS]; |
d10eb08f | 2453 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ |
6cb0b013 PC |
2454 | *u32p = value; |
2455 | } | |
2456 | ||
6cb0b013 PC |
2457 | static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2458 | uint64_t value) | |
2459 | { | |
2460 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2461 | uint32_t nrgs = cpu->pmsav7_dregion; | |
2462 | ||
2463 | if (value >= nrgs) { | |
2464 | qemu_log_mask(LOG_GUEST_ERROR, | |
2465 | "PMSAv7 RGNR write >= # supported regions, %" PRIu32 | |
2466 | " > %" PRIu32 "\n", (uint32_t)value, nrgs); | |
2467 | return; | |
2468 | } | |
2469 | ||
2470 | raw_write(env, ri, value); | |
2471 | } | |
2472 | ||
2473 | static const ARMCPRegInfo pmsav7_cp_reginfo[] = { | |
69ceea64 PM |
2474 | /* Reset for all these registers is handled in arm_cpu_reset(), |
2475 | * because the PMSAv7 is also used by M-profile CPUs, which do | |
2476 | * not register cpregs but still need the state to be reset. | |
2477 | */ | |
6cb0b013 PC |
2478 | { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, |
2479 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
2480 | .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), | |
69ceea64 PM |
2481 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
2482 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
2483 | { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, |
2484 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
2485 | .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), | |
69ceea64 PM |
2486 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
2487 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
2488 | { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, |
2489 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
2490 | .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), | |
69ceea64 PM |
2491 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
2492 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
2493 | { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, |
2494 | .access = PL1_RW, | |
1bc04a88 | 2495 | .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), |
69ceea64 PM |
2496 | .writefn = pmsav7_rgnr_write, |
2497 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
2498 | REGINFO_SENTINEL |
2499 | }; | |
2500 | ||
18032bec PM |
2501 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { |
2502 | { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 2503 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 2504 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
18032bec PM |
2505 | .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, |
2506 | { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 2507 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 2508 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
18032bec PM |
2509 | .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, |
2510 | { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, | |
2511 | .access = PL1_RW, | |
7e09797c PM |
2512 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
2513 | .resetvalue = 0, }, | |
18032bec PM |
2514 | { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, |
2515 | .access = PL1_RW, | |
7e09797c PM |
2516 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
2517 | .resetvalue = 0, }, | |
ecce5c3c PM |
2518 | { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
2519 | .access = PL1_RW, | |
2520 | .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, | |
2521 | { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
2522 | .access = PL1_RW, | |
2523 | .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, | |
06d76f31 | 2524 | /* Protection region base and size registers */ |
e508a92b PM |
2525 | { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, |
2526 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2527 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, | |
2528 | { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, | |
2529 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2530 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, | |
2531 | { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, | |
2532 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2533 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, | |
2534 | { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, | |
2535 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2536 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, | |
2537 | { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, | |
2538 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2539 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, | |
2540 | { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, | |
2541 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2542 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, | |
2543 | { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, | |
2544 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2545 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, | |
2546 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | |
2547 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
2548 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | |
18032bec PM |
2549 | REGINFO_SENTINEL |
2550 | }; | |
2551 | ||
c4241c7d PM |
2552 | static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2553 | uint64_t value) | |
ecce5c3c | 2554 | { |
11f136ee | 2555 | TCR *tcr = raw_ptr(env, ri); |
2ebcebe2 PM |
2556 | int maskshift = extract32(value, 0, 3); |
2557 | ||
e389be16 FA |
2558 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
2559 | if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { | |
2560 | /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when | |
2561 | * using Long-desciptor translation table format */ | |
2562 | value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); | |
2563 | } else if (arm_feature(env, ARM_FEATURE_EL3)) { | |
2564 | /* In an implementation that includes the Security Extensions | |
2565 | * TTBCR has additional fields PD0 [4] and PD1 [5] for | |
2566 | * Short-descriptor translation table format. | |
2567 | */ | |
2568 | value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; | |
2569 | } else { | |
2570 | value &= TTBCR_N; | |
2571 | } | |
e42c4db3 | 2572 | } |
e389be16 | 2573 | |
b6af0975 | 2574 | /* Update the masks corresponding to the TCR bank being written |
11f136ee | 2575 | * Note that we always calculate mask and base_mask, but |
e42c4db3 | 2576 | * they are only used for short-descriptor tables (ie if EAE is 0); |
11f136ee FA |
2577 | * for long-descriptor tables the TCR fields are used differently |
2578 | * and the mask and base_mask values are meaningless. | |
e42c4db3 | 2579 | */ |
11f136ee FA |
2580 | tcr->raw_tcr = value; |
2581 | tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift); | |
2582 | tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift); | |
ecce5c3c PM |
2583 | } |
2584 | ||
c4241c7d PM |
2585 | static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2586 | uint64_t value) | |
d4e6df63 | 2587 | { |
00c8cb0a AF |
2588 | ARMCPU *cpu = arm_env_get_cpu(env); |
2589 | ||
d4e6df63 PM |
2590 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
2591 | /* With LPAE the TTBCR could result in a change of ASID | |
2592 | * via the TTBCR.A1 bit, so do a TLB flush. | |
2593 | */ | |
d10eb08f | 2594 | tlb_flush(CPU(cpu)); |
d4e6df63 | 2595 | } |
c4241c7d | 2596 | vmsa_ttbcr_raw_write(env, ri, value); |
d4e6df63 PM |
2597 | } |
2598 | ||
ecce5c3c PM |
2599 | static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2600 | { | |
11f136ee FA |
2601 | TCR *tcr = raw_ptr(env, ri); |
2602 | ||
2603 | /* Reset both the TCR as well as the masks corresponding to the bank of | |
2604 | * the TCR being reset. | |
2605 | */ | |
2606 | tcr->raw_tcr = 0; | |
2607 | tcr->mask = 0; | |
2608 | tcr->base_mask = 0xffffc000u; | |
ecce5c3c PM |
2609 | } |
2610 | ||
cb2e37df PM |
2611 | static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2612 | uint64_t value) | |
2613 | { | |
00c8cb0a | 2614 | ARMCPU *cpu = arm_env_get_cpu(env); |
11f136ee | 2615 | TCR *tcr = raw_ptr(env, ri); |
00c8cb0a | 2616 | |
cb2e37df | 2617 | /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ |
d10eb08f | 2618 | tlb_flush(CPU(cpu)); |
11f136ee | 2619 | tcr->raw_tcr = value; |
cb2e37df PM |
2620 | } |
2621 | ||
327ed10f PM |
2622 | static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2623 | uint64_t value) | |
2624 | { | |
2625 | /* 64 bit accesses to the TTBRs can change the ASID and so we | |
2626 | * must flush the TLB. | |
2627 | */ | |
2628 | if (cpreg_field_is_64bit(ri)) { | |
00c8cb0a AF |
2629 | ARMCPU *cpu = arm_env_get_cpu(env); |
2630 | ||
d10eb08f | 2631 | tlb_flush(CPU(cpu)); |
327ed10f PM |
2632 | } |
2633 | raw_write(env, ri, value); | |
2634 | } | |
2635 | ||
b698e9cf EI |
2636 | static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2637 | uint64_t value) | |
2638 | { | |
2639 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2640 | CPUState *cs = CPU(cpu); | |
2641 | ||
2642 | /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ | |
2643 | if (raw_read(env, ri) != value) { | |
0336cbf8 | 2644 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
2645 | ARMMMUIdxBit_S12NSE1 | |
2646 | ARMMMUIdxBit_S12NSE0 | | |
2647 | ARMMMUIdxBit_S2NS); | |
b698e9cf EI |
2648 | raw_write(env, ri, value); |
2649 | } | |
2650 | } | |
2651 | ||
8e5d75c9 | 2652 | static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { |
18032bec | 2653 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, |
7a0e58fa | 2654 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
4a7e2d73 | 2655 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), |
b061a82b | 2656 | offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, |
18032bec | 2657 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, |
88ca1c2d FA |
2658 | .access = PL1_RW, .resetvalue = 0, |
2659 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), | |
2660 | offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, | |
8e5d75c9 PC |
2661 | { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, |
2662 | .access = PL1_RW, .resetvalue = 0, | |
2663 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), | |
2664 | offsetof(CPUARMState, cp15.dfar_ns) } }, | |
2665 | { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, | |
2666 | .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, | |
2667 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), | |
2668 | .resetvalue = 0, }, | |
2669 | REGINFO_SENTINEL | |
2670 | }; | |
2671 | ||
2672 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { | |
6cd8a264 RH |
2673 | { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, |
2674 | .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, | |
2675 | .access = PL1_RW, | |
d81c519c | 2676 | .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, |
327ed10f | 2677 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af FA |
2678 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, |
2679 | .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
2680 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), | |
2681 | offsetof(CPUARMState, cp15.ttbr0_ns) } }, | |
327ed10f | 2682 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af FA |
2683 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, |
2684 | .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
2685 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), | |
2686 | offsetof(CPUARMState, cp15.ttbr1_ns) } }, | |
cb2e37df PM |
2687 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, |
2688 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | |
2689 | .access = PL1_RW, .writefn = vmsa_tcr_el1_write, | |
2690 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, | |
11f136ee | 2691 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, |
cb2e37df | 2692 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
7a0e58fa | 2693 | .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, |
b061a82b | 2694 | .raw_writefn = vmsa_ttbcr_raw_write, |
11f136ee FA |
2695 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), |
2696 | offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, | |
18032bec PM |
2697 | REGINFO_SENTINEL |
2698 | }; | |
2699 | ||
c4241c7d PM |
2700 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2701 | uint64_t value) | |
1047b9d7 PM |
2702 | { |
2703 | env->cp15.c15_ticonfig = value & 0xe7; | |
2704 | /* The OS_TYPE bit in this register changes the reported CPUID! */ | |
2705 | env->cp15.c0_cpuid = (value & (1 << 5)) ? | |
2706 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1047b9d7 PM |
2707 | } |
2708 | ||
c4241c7d PM |
2709 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2710 | uint64_t value) | |
1047b9d7 PM |
2711 | { |
2712 | env->cp15.c15_threadid = value & 0xffff; | |
1047b9d7 PM |
2713 | } |
2714 | ||
c4241c7d PM |
2715 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2716 | uint64_t value) | |
1047b9d7 PM |
2717 | { |
2718 | /* Wait-for-interrupt (deprecated) */ | |
c3affe56 | 2719 | cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); |
1047b9d7 PM |
2720 | } |
2721 | ||
c4241c7d PM |
2722 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2723 | uint64_t value) | |
c4804214 PM |
2724 | { |
2725 | /* On OMAP there are registers indicating the max/min index of dcache lines | |
2726 | * containing a dirty line; cache flush operations have to reset these. | |
2727 | */ | |
2728 | env->cp15.c15_i_max = 0x000; | |
2729 | env->cp15.c15_i_min = 0xff0; | |
c4804214 PM |
2730 | } |
2731 | ||
18032bec PM |
2732 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
2733 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, | |
2734 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, | |
d81c519c | 2735 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 2736 | .resetvalue = 0, }, |
1047b9d7 PM |
2737 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
2738 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
2739 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
2740 | .access = PL1_RW, | |
2741 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, | |
2742 | .writefn = omap_ticonfig_write }, | |
2743 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, | |
2744 | .access = PL1_RW, | |
2745 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, | |
2746 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, | |
2747 | .access = PL1_RW, .resetvalue = 0xff0, | |
2748 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, | |
2749 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, | |
2750 | .access = PL1_RW, | |
2751 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, | |
2752 | .writefn = omap_threadid_write }, | |
2753 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, | |
2754 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
7a0e58fa | 2755 | .type = ARM_CP_NO_RAW, |
1047b9d7 PM |
2756 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
2757 | /* TODO: Peripheral port remap register: | |
2758 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller | |
2759 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), | |
2760 | * when MMU is off. | |
2761 | */ | |
c4804214 | 2762 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
d4e6df63 | 2763 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
7a0e58fa | 2764 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, |
c4804214 | 2765 | .writefn = omap_cachemaint_write }, |
34f90529 PM |
2766 | { .name = "C9", .cp = 15, .crn = 9, |
2767 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | |
2768 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | |
1047b9d7 PM |
2769 | REGINFO_SENTINEL |
2770 | }; | |
2771 | ||
c4241c7d PM |
2772 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2773 | uint64_t value) | |
1047b9d7 | 2774 | { |
c0f4af17 | 2775 | env->cp15.c15_cpar = value & 0x3fff; |
1047b9d7 PM |
2776 | } |
2777 | ||
2778 | static const ARMCPRegInfo xscale_cp_reginfo[] = { | |
2779 | { .name = "XSCALE_CPAR", | |
2780 | .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
2781 | .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, | |
2782 | .writefn = xscale_cpar_write, }, | |
2771db27 PM |
2783 | { .name = "XSCALE_AUXCR", |
2784 | .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, | |
2785 | .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), | |
2786 | .resetvalue = 0, }, | |
3b771579 PM |
2787 | /* XScale specific cache-lockdown: since we have no cache we NOP these |
2788 | * and hope the guest does not really rely on cache behaviour. | |
2789 | */ | |
2790 | { .name = "XSCALE_LOCK_ICACHE_LINE", | |
2791 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
2792 | .access = PL1_W, .type = ARM_CP_NOP }, | |
2793 | { .name = "XSCALE_UNLOCK_ICACHE", | |
2794 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
2795 | .access = PL1_W, .type = ARM_CP_NOP }, | |
2796 | { .name = "XSCALE_DCACHE_LOCK", | |
2797 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, | |
2798 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
2799 | { .name = "XSCALE_UNLOCK_DCACHE", | |
2800 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, | |
2801 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1047b9d7 PM |
2802 | REGINFO_SENTINEL |
2803 | }; | |
2804 | ||
2805 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | |
2806 | /* RAZ/WI the whole crn=15 space, when we don't have a more specific | |
2807 | * implementation of this implementation-defined space. | |
2808 | * Ideally this should eventually disappear in favour of actually | |
2809 | * implementing the correct behaviour for all cores. | |
2810 | */ | |
2811 | { .name = "C15_IMPDEF", .cp = 15, .crn = 15, | |
2812 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
3671cd87 | 2813 | .access = PL1_RW, |
7a0e58fa | 2814 | .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, |
d4e6df63 | 2815 | .resetvalue = 0 }, |
18032bec PM |
2816 | REGINFO_SENTINEL |
2817 | }; | |
2818 | ||
c4804214 PM |
2819 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
2820 | /* Cache status: RAZ because we have no cache so it's always clean */ | |
2821 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | |
7a0e58fa | 2822 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 2823 | .resetvalue = 0 }, |
c4804214 PM |
2824 | REGINFO_SENTINEL |
2825 | }; | |
2826 | ||
2827 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | |
2828 | /* We never have a a block transfer operation in progress */ | |
2829 | { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, | |
7a0e58fa | 2830 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 2831 | .resetvalue = 0 }, |
30b05bba PM |
2832 | /* The cache ops themselves: these all NOP for QEMU */ |
2833 | { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, | |
2834 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
2835 | { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, | |
2836 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
2837 | { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, | |
2838 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
2839 | { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, | |
2840 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
2841 | { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, | |
2842 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
2843 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, | |
2844 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
c4804214 PM |
2845 | REGINFO_SENTINEL |
2846 | }; | |
2847 | ||
2848 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | |
2849 | /* The cache test-and-clean instructions always return (1 << 30) | |
2850 | * to indicate that there are no dirty cache lines. | |
2851 | */ | |
2852 | { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, | |
7a0e58fa | 2853 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 2854 | .resetvalue = (1 << 30) }, |
c4804214 | 2855 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
7a0e58fa | 2856 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 2857 | .resetvalue = (1 << 30) }, |
c4804214 PM |
2858 | REGINFO_SENTINEL |
2859 | }; | |
2860 | ||
34f90529 PM |
2861 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
2862 | /* Ignore ReadBuffer accesses */ | |
2863 | { .name = "C9_READBUFFER", .cp = 15, .crn = 9, | |
2864 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
d4e6df63 | 2865 | .access = PL1_RW, .resetvalue = 0, |
7a0e58fa | 2866 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, |
34f90529 PM |
2867 | REGINFO_SENTINEL |
2868 | }; | |
2869 | ||
731de9e6 EI |
2870 | static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2871 | { | |
2872 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2873 | unsigned int cur_el = arm_current_el(env); | |
2874 | bool secure = arm_is_secure(env); | |
2875 | ||
2876 | if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { | |
2877 | return env->cp15.vpidr_el2; | |
2878 | } | |
2879 | return raw_read(env, ri); | |
2880 | } | |
2881 | ||
06a7e647 | 2882 | static uint64_t mpidr_read_val(CPUARMState *env) |
81bdde9d | 2883 | { |
eb5e1d3c PF |
2884 | ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env)); |
2885 | uint64_t mpidr = cpu->mp_affinity; | |
2886 | ||
81bdde9d | 2887 | if (arm_feature(env, ARM_FEATURE_V7MP)) { |
78dbbbe4 | 2888 | mpidr |= (1U << 31); |
81bdde9d PM |
2889 | /* Cores which are uniprocessor (non-coherent) |
2890 | * but still implement the MP extensions set | |
a8e81b31 | 2891 | * bit 30. (For instance, Cortex-R5). |
81bdde9d | 2892 | */ |
a8e81b31 PC |
2893 | if (cpu->mp_is_up) { |
2894 | mpidr |= (1u << 30); | |
2895 | } | |
81bdde9d | 2896 | } |
c4241c7d | 2897 | return mpidr; |
81bdde9d PM |
2898 | } |
2899 | ||
06a7e647 EI |
2900 | static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2901 | { | |
f0d574d6 EI |
2902 | unsigned int cur_el = arm_current_el(env); |
2903 | bool secure = arm_is_secure(env); | |
2904 | ||
2905 | if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { | |
2906 | return env->cp15.vmpidr_el2; | |
2907 | } | |
06a7e647 EI |
2908 | return mpidr_read_val(env); |
2909 | } | |
2910 | ||
81bdde9d | 2911 | static const ARMCPRegInfo mpidr_cp_reginfo[] = { |
4b7fff2f PM |
2912 | { .name = "MPIDR", .state = ARM_CP_STATE_BOTH, |
2913 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | |
7a0e58fa | 2914 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, |
81bdde9d PM |
2915 | REGINFO_SENTINEL |
2916 | }; | |
2917 | ||
7ac681cf | 2918 | static const ARMCPRegInfo lpae_cp_reginfo[] = { |
a903c449 | 2919 | /* NOP AMAIR0/1 */ |
b0fe2427 PM |
2920 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, |
2921 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | |
a903c449 | 2922 | .access = PL1_RW, .type = ARM_CP_CONST, |
7ac681cf | 2923 | .resetvalue = 0 }, |
b0fe2427 | 2924 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ |
7ac681cf | 2925 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
a903c449 | 2926 | .access = PL1_RW, .type = ARM_CP_CONST, |
7ac681cf | 2927 | .resetvalue = 0 }, |
891a2fe7 | 2928 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
01c097f7 FA |
2929 | .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, |
2930 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), | |
2931 | offsetof(CPUARMState, cp15.par_ns)} }, | |
891a2fe7 | 2932 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, |
7a0e58fa | 2933 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, |
7dd8c9af FA |
2934 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
2935 | offsetof(CPUARMState, cp15.ttbr0_ns) }, | |
b061a82b | 2936 | .writefn = vmsa_ttbr_write, }, |
891a2fe7 | 2937 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
7a0e58fa | 2938 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, |
7dd8c9af FA |
2939 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
2940 | offsetof(CPUARMState, cp15.ttbr1_ns) }, | |
b061a82b | 2941 | .writefn = vmsa_ttbr_write, }, |
7ac681cf PM |
2942 | REGINFO_SENTINEL |
2943 | }; | |
2944 | ||
c4241c7d | 2945 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 2946 | { |
c4241c7d | 2947 | return vfp_get_fpcr(env); |
b0d2b7d0 PM |
2948 | } |
2949 | ||
c4241c7d PM |
2950 | static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2951 | uint64_t value) | |
b0d2b7d0 PM |
2952 | { |
2953 | vfp_set_fpcr(env, value); | |
b0d2b7d0 PM |
2954 | } |
2955 | ||
c4241c7d | 2956 | static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 2957 | { |
c4241c7d | 2958 | return vfp_get_fpsr(env); |
b0d2b7d0 PM |
2959 | } |
2960 | ||
c4241c7d PM |
2961 | static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2962 | uint64_t value) | |
b0d2b7d0 PM |
2963 | { |
2964 | vfp_set_fpsr(env, value); | |
b0d2b7d0 PM |
2965 | } |
2966 | ||
3f208fd7 PM |
2967 | static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2968 | bool isread) | |
c2b820fe | 2969 | { |
137feaa9 | 2970 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { |
c2b820fe PM |
2971 | return CP_ACCESS_TRAP; |
2972 | } | |
2973 | return CP_ACCESS_OK; | |
2974 | } | |
2975 | ||
2976 | static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2977 | uint64_t value) | |
2978 | { | |
2979 | env->daif = value & PSTATE_DAIF; | |
2980 | } | |
2981 | ||
8af35c37 | 2982 | static CPAccessResult aa64_cacheop_access(CPUARMState *env, |
3f208fd7 PM |
2983 | const ARMCPRegInfo *ri, |
2984 | bool isread) | |
8af35c37 PM |
2985 | { |
2986 | /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless | |
2987 | * SCTLR_EL1.UCI is set. | |
2988 | */ | |
137feaa9 | 2989 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) { |
8af35c37 PM |
2990 | return CP_ACCESS_TRAP; |
2991 | } | |
2992 | return CP_ACCESS_OK; | |
2993 | } | |
2994 | ||
dbb1fb27 AB |
2995 | /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions |
2996 | * Page D4-1736 (DDI0487A.b) | |
2997 | */ | |
2998 | ||
fd3ed969 PM |
2999 | static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3000 | uint64_t value) | |
168aa23b | 3001 | { |
a67cf277 | 3002 | CPUState *cs = ENV_GET_CPU(env); |
dbb1fb27 | 3003 | |
fd3ed969 | 3004 | if (arm_is_secure_below_el3(env)) { |
0336cbf8 | 3005 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
3006 | ARMMMUIdxBit_S1SE1 | |
3007 | ARMMMUIdxBit_S1SE0); | |
fd3ed969 | 3008 | } else { |
0336cbf8 | 3009 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
3010 | ARMMMUIdxBit_S12NSE1 | |
3011 | ARMMMUIdxBit_S12NSE0); | |
fd3ed969 | 3012 | } |
168aa23b PM |
3013 | } |
3014 | ||
fd3ed969 PM |
3015 | static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3016 | uint64_t value) | |
168aa23b | 3017 | { |
a67cf277 | 3018 | CPUState *cs = ENV_GET_CPU(env); |
fd3ed969 | 3019 | bool sec = arm_is_secure_below_el3(env); |
dbb1fb27 | 3020 | |
a67cf277 AB |
3021 | if (sec) { |
3022 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3023 | ARMMMUIdxBit_S1SE1 | |
3024 | ARMMMUIdxBit_S1SE0); | |
a67cf277 AB |
3025 | } else { |
3026 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3027 | ARMMMUIdxBit_S12NSE1 | |
3028 | ARMMMUIdxBit_S12NSE0); | |
fd3ed969 | 3029 | } |
168aa23b PM |
3030 | } |
3031 | ||
fd3ed969 PM |
3032 | static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3033 | uint64_t value) | |
168aa23b | 3034 | { |
fd3ed969 PM |
3035 | /* Note that the 'ALL' scope must invalidate both stage 1 and |
3036 | * stage 2 translations, whereas most other scopes only invalidate | |
3037 | * stage 1 translations. | |
3038 | */ | |
00c8cb0a | 3039 | ARMCPU *cpu = arm_env_get_cpu(env); |
fd3ed969 PM |
3040 | CPUState *cs = CPU(cpu); |
3041 | ||
3042 | if (arm_is_secure_below_el3(env)) { | |
0336cbf8 | 3043 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
3044 | ARMMMUIdxBit_S1SE1 | |
3045 | ARMMMUIdxBit_S1SE0); | |
fd3ed969 PM |
3046 | } else { |
3047 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
0336cbf8 | 3048 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
3049 | ARMMMUIdxBit_S12NSE1 | |
3050 | ARMMMUIdxBit_S12NSE0 | | |
3051 | ARMMMUIdxBit_S2NS); | |
fd3ed969 | 3052 | } else { |
0336cbf8 | 3053 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
3054 | ARMMMUIdxBit_S12NSE1 | |
3055 | ARMMMUIdxBit_S12NSE0); | |
fd3ed969 PM |
3056 | } |
3057 | } | |
168aa23b PM |
3058 | } |
3059 | ||
fd3ed969 | 3060 | static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
fa439fc5 PM |
3061 | uint64_t value) |
3062 | { | |
fd3ed969 PM |
3063 | ARMCPU *cpu = arm_env_get_cpu(env); |
3064 | CPUState *cs = CPU(cpu); | |
3065 | ||
8bd5c820 | 3066 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); |
fd3ed969 PM |
3067 | } |
3068 | ||
43efaa33 PM |
3069 | static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3070 | uint64_t value) | |
3071 | { | |
3072 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3073 | CPUState *cs = CPU(cpu); | |
3074 | ||
8bd5c820 | 3075 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3); |
43efaa33 PM |
3076 | } |
3077 | ||
fd3ed969 PM |
3078 | static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3079 | uint64_t value) | |
3080 | { | |
3081 | /* Note that the 'ALL' scope must invalidate both stage 1 and | |
3082 | * stage 2 translations, whereas most other scopes only invalidate | |
3083 | * stage 1 translations. | |
3084 | */ | |
a67cf277 | 3085 | CPUState *cs = ENV_GET_CPU(env); |
fd3ed969 PM |
3086 | bool sec = arm_is_secure_below_el3(env); |
3087 | bool has_el2 = arm_feature(env, ARM_FEATURE_EL2); | |
a67cf277 AB |
3088 | |
3089 | if (sec) { | |
3090 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3091 | ARMMMUIdxBit_S1SE1 | |
3092 | ARMMMUIdxBit_S1SE0); | |
a67cf277 AB |
3093 | } else if (has_el2) { |
3094 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3095 | ARMMMUIdxBit_S12NSE1 | |
3096 | ARMMMUIdxBit_S12NSE0 | | |
3097 | ARMMMUIdxBit_S2NS); | |
a67cf277 AB |
3098 | } else { |
3099 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3100 | ARMMMUIdxBit_S12NSE1 | |
3101 | ARMMMUIdxBit_S12NSE0); | |
fa439fc5 PM |
3102 | } |
3103 | } | |
3104 | ||
2bfb9d75 PM |
3105 | static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3106 | uint64_t value) | |
3107 | { | |
a67cf277 | 3108 | CPUState *cs = ENV_GET_CPU(env); |
2bfb9d75 | 3109 | |
8bd5c820 | 3110 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); |
2bfb9d75 PM |
3111 | } |
3112 | ||
43efaa33 PM |
3113 | static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3114 | uint64_t value) | |
3115 | { | |
a67cf277 | 3116 | CPUState *cs = ENV_GET_CPU(env); |
43efaa33 | 3117 | |
8bd5c820 | 3118 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3); |
43efaa33 PM |
3119 | } |
3120 | ||
fd3ed969 PM |
3121 | static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3122 | uint64_t value) | |
3123 | { | |
3124 | /* Invalidate by VA, EL1&0 (AArch64 version). | |
3125 | * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, | |
3126 | * since we don't support flush-for-specific-ASID-only or | |
3127 | * flush-last-level-only. | |
3128 | */ | |
3129 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3130 | CPUState *cs = CPU(cpu); | |
3131 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
3132 | ||
3133 | if (arm_is_secure_below_el3(env)) { | |
0336cbf8 | 3134 | tlb_flush_page_by_mmuidx(cs, pageaddr, |
8bd5c820 PM |
3135 | ARMMMUIdxBit_S1SE1 | |
3136 | ARMMMUIdxBit_S1SE0); | |
fd3ed969 | 3137 | } else { |
0336cbf8 | 3138 | tlb_flush_page_by_mmuidx(cs, pageaddr, |
8bd5c820 PM |
3139 | ARMMMUIdxBit_S12NSE1 | |
3140 | ARMMMUIdxBit_S12NSE0); | |
fd3ed969 PM |
3141 | } |
3142 | } | |
3143 | ||
3144 | static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3145 | uint64_t value) | |
fa439fc5 | 3146 | { |
fd3ed969 PM |
3147 | /* Invalidate by VA, EL2 |
3148 | * Currently handles both VAE2 and VALE2, since we don't support | |
3149 | * flush-last-level-only. | |
3150 | */ | |
3151 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3152 | CPUState *cs = CPU(cpu); | |
3153 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
3154 | ||
8bd5c820 | 3155 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); |
fd3ed969 PM |
3156 | } |
3157 | ||
43efaa33 PM |
3158 | static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3159 | uint64_t value) | |
3160 | { | |
3161 | /* Invalidate by VA, EL3 | |
3162 | * Currently handles both VAE3 and VALE3, since we don't support | |
3163 | * flush-last-level-only. | |
3164 | */ | |
3165 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3166 | CPUState *cs = CPU(cpu); | |
3167 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
3168 | ||
8bd5c820 | 3169 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3); |
43efaa33 PM |
3170 | } |
3171 | ||
fd3ed969 PM |
3172 | static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3173 | uint64_t value) | |
3174 | { | |
a67cf277 AB |
3175 | ARMCPU *cpu = arm_env_get_cpu(env); |
3176 | CPUState *cs = CPU(cpu); | |
fd3ed969 | 3177 | bool sec = arm_is_secure_below_el3(env); |
fa439fc5 PM |
3178 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
3179 | ||
a67cf277 AB |
3180 | if (sec) { |
3181 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, | |
8bd5c820 PM |
3182 | ARMMMUIdxBit_S1SE1 | |
3183 | ARMMMUIdxBit_S1SE0); | |
a67cf277 AB |
3184 | } else { |
3185 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, | |
8bd5c820 PM |
3186 | ARMMMUIdxBit_S12NSE1 | |
3187 | ARMMMUIdxBit_S12NSE0); | |
fa439fc5 PM |
3188 | } |
3189 | } | |
3190 | ||
fd3ed969 PM |
3191 | static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3192 | uint64_t value) | |
fa439fc5 | 3193 | { |
a67cf277 | 3194 | CPUState *cs = ENV_GET_CPU(env); |
fd3ed969 | 3195 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
fa439fc5 | 3196 | |
a67cf277 | 3197 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 3198 | ARMMMUIdxBit_S1E2); |
fa439fc5 PM |
3199 | } |
3200 | ||
43efaa33 PM |
3201 | static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3202 | uint64_t value) | |
3203 | { | |
a67cf277 | 3204 | CPUState *cs = ENV_GET_CPU(env); |
43efaa33 PM |
3205 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
3206 | ||
a67cf277 | 3207 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 3208 | ARMMMUIdxBit_S1E3); |
43efaa33 PM |
3209 | } |
3210 | ||
cea66e91 PM |
3211 | static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3212 | uint64_t value) | |
3213 | { | |
3214 | /* Invalidate by IPA. This has to invalidate any structures that | |
3215 | * contain only stage 2 translation information, but does not need | |
3216 | * to apply to structures that contain combined stage 1 and stage 2 | |
3217 | * translation information. | |
3218 | * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. | |
3219 | */ | |
3220 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3221 | CPUState *cs = CPU(cpu); | |
3222 | uint64_t pageaddr; | |
3223 | ||
3224 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
3225 | return; | |
3226 | } | |
3227 | ||
3228 | pageaddr = sextract64(value << 12, 0, 48); | |
3229 | ||
8bd5c820 | 3230 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); |
cea66e91 PM |
3231 | } |
3232 | ||
3233 | static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3234 | uint64_t value) | |
3235 | { | |
a67cf277 | 3236 | CPUState *cs = ENV_GET_CPU(env); |
cea66e91 PM |
3237 | uint64_t pageaddr; |
3238 | ||
3239 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
3240 | return; | |
3241 | } | |
3242 | ||
3243 | pageaddr = sextract64(value << 12, 0, 48); | |
3244 | ||
a67cf277 | 3245 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 3246 | ARMMMUIdxBit_S2NS); |
cea66e91 PM |
3247 | } |
3248 | ||
3f208fd7 PM |
3249 | static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3250 | bool isread) | |
aca3f40b PM |
3251 | { |
3252 | /* We don't implement EL2, so the only control on DC ZVA is the | |
3253 | * bit in the SCTLR which can prohibit access for EL0. | |
3254 | */ | |
137feaa9 | 3255 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) { |
aca3f40b PM |
3256 | return CP_ACCESS_TRAP; |
3257 | } | |
3258 | return CP_ACCESS_OK; | |
3259 | } | |
3260 | ||
3261 | static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3262 | { | |
3263 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3264 | int dzp_bit = 1 << 4; | |
3265 | ||
3266 | /* DZP indicates whether DC ZVA access is allowed */ | |
3f208fd7 | 3267 | if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) { |
aca3f40b PM |
3268 | dzp_bit = 0; |
3269 | } | |
3270 | return cpu->dcz_blocksize | dzp_bit; | |
3271 | } | |
3272 | ||
3f208fd7 PM |
3273 | static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3274 | bool isread) | |
f502cfc2 | 3275 | { |
cdcf1405 | 3276 | if (!(env->pstate & PSTATE_SP)) { |
f502cfc2 PM |
3277 | /* Access to SP_EL0 is undefined if it's being used as |
3278 | * the stack pointer. | |
3279 | */ | |
3280 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
3281 | } | |
3282 | return CP_ACCESS_OK; | |
3283 | } | |
3284 | ||
3285 | static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3286 | { | |
3287 | return env->pstate & PSTATE_SP; | |
3288 | } | |
3289 | ||
3290 | static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
3291 | { | |
3292 | update_spsel(env, val); | |
3293 | } | |
3294 | ||
137feaa9 FA |
3295 | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3296 | uint64_t value) | |
3297 | { | |
3298 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3299 | ||
3300 | if (raw_read(env, ri) == value) { | |
3301 | /* Skip the TLB flush if nothing actually changed; Linux likes | |
3302 | * to do a lot of pointless SCTLR writes. | |
3303 | */ | |
3304 | return; | |
3305 | } | |
3306 | ||
06312feb PM |
3307 | if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { |
3308 | /* M bit is RAZ/WI for PMSA with no MPU implemented */ | |
3309 | value &= ~SCTLR_M; | |
3310 | } | |
3311 | ||
137feaa9 FA |
3312 | raw_write(env, ri, value); |
3313 | /* ??? Lots of these bits are not implemented. */ | |
3314 | /* This may enable/disable the MMU, so do a TLB flush. */ | |
d10eb08f | 3315 | tlb_flush(CPU(cpu)); |
137feaa9 FA |
3316 | } |
3317 | ||
3f208fd7 PM |
3318 | static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3319 | bool isread) | |
03fbf20f PM |
3320 | { |
3321 | if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { | |
f2cae609 | 3322 | return CP_ACCESS_TRAP_FP_EL2; |
03fbf20f PM |
3323 | } |
3324 | if (env->cp15.cptr_el[3] & CPTR_TFP) { | |
f2cae609 | 3325 | return CP_ACCESS_TRAP_FP_EL3; |
03fbf20f PM |
3326 | } |
3327 | return CP_ACCESS_OK; | |
3328 | } | |
3329 | ||
a8d64e73 PM |
3330 | static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3331 | uint64_t value) | |
3332 | { | |
3333 | env->cp15.mdcr_el3 = value & SDCR_VALID_MASK; | |
3334 | } | |
3335 | ||
b0d2b7d0 PM |
3336 | static const ARMCPRegInfo v8_cp_reginfo[] = { |
3337 | /* Minimal set of EL0-visible registers. This will need to be expanded | |
3338 | * significantly for system emulation of AArch64 CPUs. | |
3339 | */ | |
3340 | { .name = "NZCV", .state = ARM_CP_STATE_AA64, | |
3341 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, | |
3342 | .access = PL0_RW, .type = ARM_CP_NZCV }, | |
c2b820fe PM |
3343 | { .name = "DAIF", .state = ARM_CP_STATE_AA64, |
3344 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, | |
7a0e58fa | 3345 | .type = ARM_CP_NO_RAW, |
c2b820fe PM |
3346 | .access = PL0_RW, .accessfn = aa64_daif_access, |
3347 | .fieldoffset = offsetof(CPUARMState, daif), | |
3348 | .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, | |
b0d2b7d0 PM |
3349 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, |
3350 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | |
3351 | .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, | |
3352 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, | |
3353 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | |
3354 | .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, | |
b0d2b7d0 PM |
3355 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, |
3356 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | |
7a0e58fa | 3357 | .access = PL0_R, .type = ARM_CP_NO_RAW, |
aca3f40b PM |
3358 | .readfn = aa64_dczid_read }, |
3359 | { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, | |
3360 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, | |
3361 | .access = PL0_W, .type = ARM_CP_DC_ZVA, | |
3362 | #ifndef CONFIG_USER_ONLY | |
3363 | /* Avoid overhead of an access check that always passes in user-mode */ | |
3364 | .accessfn = aa64_zva_access, | |
3365 | #endif | |
3366 | }, | |
0eef9d98 PM |
3367 | { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, |
3368 | .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, | |
3369 | .access = PL1_R, .type = ARM_CP_CURRENTEL }, | |
8af35c37 PM |
3370 | /* Cache ops: all NOPs since we don't emulate caches */ |
3371 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, | |
3372 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
3373 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3374 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, | |
3375 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
3376 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3377 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, | |
3378 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | |
3379 | .access = PL0_W, .type = ARM_CP_NOP, | |
3380 | .accessfn = aa64_cacheop_access }, | |
3381 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, | |
3382 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
3383 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3384 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, | |
3385 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
3386 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3387 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, | |
3388 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | |
3389 | .access = PL0_W, .type = ARM_CP_NOP, | |
3390 | .accessfn = aa64_cacheop_access }, | |
3391 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, | |
3392 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
3393 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3394 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, | |
3395 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | |
3396 | .access = PL0_W, .type = ARM_CP_NOP, | |
3397 | .accessfn = aa64_cacheop_access }, | |
3398 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, | |
3399 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | |
3400 | .access = PL0_W, .type = ARM_CP_NOP, | |
3401 | .accessfn = aa64_cacheop_access }, | |
3402 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, | |
3403 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
3404 | .access = PL1_W, .type = ARM_CP_NOP }, | |
168aa23b PM |
3405 | /* TLBI operations */ |
3406 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 3407 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, |
7a0e58fa | 3408 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3409 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 3410 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3411 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
7a0e58fa | 3412 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3413 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 3414 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3415 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
7a0e58fa | 3416 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3417 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 3418 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3419 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
7a0e58fa | 3420 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3421 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 3422 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3423 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
7a0e58fa | 3424 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3425 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 3426 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3427 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
7a0e58fa | 3428 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3429 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 3430 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3431 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, |
7a0e58fa | 3432 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3433 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 3434 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3435 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
7a0e58fa | 3436 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3437 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 3438 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3439 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
7a0e58fa | 3440 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3441 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 3442 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3443 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
7a0e58fa | 3444 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3445 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 3446 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3447 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
7a0e58fa | 3448 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3449 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 3450 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 3451 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
7a0e58fa | 3452 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 3453 | .writefn = tlbi_aa64_vae1_write }, |
cea66e91 PM |
3454 | { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, |
3455 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
3456 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3457 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
3458 | { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, | |
3459 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
3460 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3461 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
83ddf975 PM |
3462 | { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, |
3463 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
3464 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 3465 | .writefn = tlbi_aa64_alle1is_write }, |
43efaa33 PM |
3466 | { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, |
3467 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, | |
3468 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3469 | .writefn = tlbi_aa64_alle1is_write }, | |
cea66e91 PM |
3470 | { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, |
3471 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
3472 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3473 | .writefn = tlbi_aa64_ipas2e1_write }, | |
3474 | { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, | |
3475 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
3476 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3477 | .writefn = tlbi_aa64_ipas2e1_write }, | |
83ddf975 PM |
3478 | { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, |
3479 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
3480 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 3481 | .writefn = tlbi_aa64_alle1_write }, |
43efaa33 PM |
3482 | { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, |
3483 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, | |
3484 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3485 | .writefn = tlbi_aa64_alle1is_write }, | |
19525524 PM |
3486 | #ifndef CONFIG_USER_ONLY |
3487 | /* 64 bit address translation operations */ | |
3488 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
3489 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, | |
060e8a48 | 3490 | .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
19525524 PM |
3491 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, |
3492 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, | |
060e8a48 | 3493 | .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
19525524 PM |
3494 | { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, |
3495 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, | |
060e8a48 | 3496 | .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
19525524 PM |
3497 | { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, |
3498 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, | |
060e8a48 | 3499 | .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
2a47df95 | 3500 | { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 3501 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, |
2a47df95 PM |
3502 | .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
3503 | { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, | |
7a379c7e | 3504 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, |
2a47df95 PM |
3505 | .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
3506 | { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, | |
7a379c7e | 3507 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, |
2a47df95 PM |
3508 | .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
3509 | { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, | |
7a379c7e | 3510 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, |
2a47df95 PM |
3511 | .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
3512 | /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ | |
3513 | { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, | |
3514 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, | |
3515 | .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, | |
3516 | { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, | |
3517 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, | |
3518 | .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, | |
c96fc9b5 EI |
3519 | { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, |
3520 | .type = ARM_CP_ALIAS, | |
3521 | .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, | |
3522 | .access = PL1_RW, .resetvalue = 0, | |
3523 | .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), | |
3524 | .writefn = par_write }, | |
19525524 | 3525 | #endif |
995939a6 | 3526 | /* TLB invalidate last level of translation table walk */ |
9449fdf6 | 3527 | { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
7a0e58fa | 3528 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, |
9449fdf6 | 3529 | { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
7a0e58fa | 3530 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 3531 | .writefn = tlbimvaa_is_write }, |
9449fdf6 | 3532 | { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
7a0e58fa | 3533 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
9449fdf6 | 3534 | { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
7a0e58fa | 3535 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, |
541ef8c2 SS |
3536 | { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, |
3537 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3538 | .writefn = tlbimva_hyp_write }, | |
3539 | { .name = "TLBIMVALHIS", | |
3540 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
3541 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3542 | .writefn = tlbimva_hyp_is_write }, | |
3543 | { .name = "TLBIIPAS2", | |
3544 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
3545 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3546 | .writefn = tlbiipas2_write }, | |
3547 | { .name = "TLBIIPAS2IS", | |
3548 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
3549 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3550 | .writefn = tlbiipas2_is_write }, | |
3551 | { .name = "TLBIIPAS2L", | |
3552 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
3553 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3554 | .writefn = tlbiipas2_write }, | |
3555 | { .name = "TLBIIPAS2LIS", | |
3556 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
3557 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3558 | .writefn = tlbiipas2_is_write }, | |
9449fdf6 PM |
3559 | /* 32 bit cache operations */ |
3560 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
3561 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3562 | { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, | |
3563 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3564 | { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
3565 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3566 | { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, | |
3567 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3568 | { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, | |
3569 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3570 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | |
3571 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3572 | { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
3573 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3574 | { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
3575 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3576 | { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, | |
3577 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3578 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
3579 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3580 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, | |
3581 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3582 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, | |
3583 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3584 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
3585 | .type = ARM_CP_NOP, .access = PL1_W }, | |
3586 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
3587 | { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, |
3588 | .access = PL1_RW, .resetvalue = 0, | |
3589 | .writefn = dacr_write, .raw_writefn = raw_write, | |
3590 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
3591 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a0618a19 | 3592 | { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 3593 | .type = ARM_CP_ALIAS, |
a0618a19 | 3594 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, |
6947f059 EI |
3595 | .access = PL1_RW, |
3596 | .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, | |
a65f1de9 | 3597 | { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 3598 | .type = ARM_CP_ALIAS, |
a65f1de9 | 3599 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
3600 | .access = PL1_RW, |
3601 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, | |
f502cfc2 PM |
3602 | /* We rely on the access checks not allowing the guest to write to the |
3603 | * state field when SPSel indicates that it's being used as the stack | |
3604 | * pointer. | |
3605 | */ | |
3606 | { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, | |
3607 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, | |
3608 | .access = PL1_RW, .accessfn = sp_el0_access, | |
7a0e58fa | 3609 | .type = ARM_CP_ALIAS, |
f502cfc2 | 3610 | .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, |
884b4dee GB |
3611 | { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, |
3612 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 3613 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
884b4dee | 3614 | .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, |
f502cfc2 PM |
3615 | { .name = "SPSel", .state = ARM_CP_STATE_AA64, |
3616 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, | |
7a0e58fa | 3617 | .type = ARM_CP_NO_RAW, |
f502cfc2 | 3618 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, |
03fbf20f PM |
3619 | { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, |
3620 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, | |
3621 | .type = ARM_CP_ALIAS, | |
3622 | .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), | |
3623 | .access = PL2_RW, .accessfn = fpexc32_access }, | |
6a43e0b6 PM |
3624 | { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, |
3625 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, | |
3626 | .access = PL2_RW, .resetvalue = 0, | |
3627 | .writefn = dacr_write, .raw_writefn = raw_write, | |
3628 | .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, | |
3629 | { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, | |
3630 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, | |
3631 | .access = PL2_RW, .resetvalue = 0, | |
3632 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, | |
3633 | { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, | |
3634 | .type = ARM_CP_ALIAS, | |
3635 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, | |
3636 | .access = PL2_RW, | |
3637 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, | |
3638 | { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, | |
3639 | .type = ARM_CP_ALIAS, | |
3640 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, | |
3641 | .access = PL2_RW, | |
3642 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, | |
3643 | { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, | |
3644 | .type = ARM_CP_ALIAS, | |
3645 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, | |
3646 | .access = PL2_RW, | |
3647 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, | |
3648 | { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, | |
3649 | .type = ARM_CP_ALIAS, | |
3650 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, | |
3651 | .access = PL2_RW, | |
3652 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, | |
a8d64e73 PM |
3653 | { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, |
3654 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, | |
3655 | .resetvalue = 0, | |
3656 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) }, | |
3657 | { .name = "SDCR", .type = ARM_CP_ALIAS, | |
3658 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1, | |
3659 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, | |
3660 | .writefn = sdcr_write, | |
3661 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, | |
b0d2b7d0 PM |
3662 | REGINFO_SENTINEL |
3663 | }; | |
3664 | ||
d42e3c26 | 3665 | /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ |
4771cd01 | 3666 | static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { |
d42e3c26 EI |
3667 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, |
3668 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | |
3669 | .access = PL2_RW, | |
3670 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | |
f149e3e8 | 3671 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 3672 | .type = ARM_CP_NO_RAW, |
f149e3e8 EI |
3673 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
3674 | .access = PL2_RW, | |
3675 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | |
c6f19164 GB |
3676 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
3677 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
3678 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
95f949ac EI |
3679 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
3680 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
3681 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3682 | .resetvalue = 0 }, | |
3683 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
3684 | .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, | |
3685 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2179ef95 PM |
3686 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
3687 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
3688 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3689 | .resetvalue = 0 }, | |
3690 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
3691 | .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, | |
3692 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3693 | .resetvalue = 0 }, | |
37cd6c24 PM |
3694 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
3695 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
3696 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3697 | .resetvalue = 0 }, | |
3698 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
3699 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
3700 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3701 | .resetvalue = 0 }, | |
06ec4c8c EI |
3702 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
3703 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
3704 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
68e9c2fe EI |
3705 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH, |
3706 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
3707 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
3708 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b698e9cf EI |
3709 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
3710 | .cp = 15, .opc1 = 6, .crm = 2, | |
3711 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
3712 | .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | |
3713 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
3714 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
3715 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b9cb5323 EI |
3716 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
3717 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
3718 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
ff05f37b EI |
3719 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
3720 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
3721 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
a57633c0 EI |
3722 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
3723 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
3724 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3725 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
3726 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
3727 | .resetvalue = 0 }, | |
0b6440af EI |
3728 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
3729 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
3730 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
edac4d8a EI |
3731 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
3732 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
3733 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3734 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
3735 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
3736 | .resetvalue = 0 }, | |
b0e66d95 EI |
3737 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
3738 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
3739 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3740 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
3741 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
3742 | .resetvalue = 0 }, | |
3743 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
3744 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
3745 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3746 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
3747 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
3748 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
14cc7b54 SF |
3749 | { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, |
3750 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | |
d6c8cf81 PM |
3751 | .access = PL2_RW, .accessfn = access_tda, |
3752 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
59e05530 EI |
3753 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, |
3754 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
3755 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
3756 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2a5a9abd AF |
3757 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
3758 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
3759 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
d42e3c26 EI |
3760 | REGINFO_SENTINEL |
3761 | }; | |
3762 | ||
f149e3e8 EI |
3763 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
3764 | { | |
3765 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3766 | uint64_t valid_mask = HCR_MASK; | |
3767 | ||
3768 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
3769 | valid_mask &= ~HCR_HCD; | |
77077a83 JK |
3770 | } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { |
3771 | /* Architecturally HCR.TSC is RES0 if EL3 is not implemented. | |
3772 | * However, if we're using the SMC PSCI conduit then QEMU is | |
3773 | * effectively acting like EL3 firmware and so the guest at | |
3774 | * EL2 should retain the ability to prevent EL1 from being | |
3775 | * able to make SMC calls into the ersatz firmware, so in | |
3776 | * that case HCR.TSC should be read/write. | |
3777 | */ | |
f149e3e8 EI |
3778 | valid_mask &= ~HCR_TSC; |
3779 | } | |
3780 | ||
3781 | /* Clear RES0 bits. */ | |
3782 | value &= valid_mask; | |
3783 | ||
3784 | /* These bits change the MMU setup: | |
3785 | * HCR_VM enables stage 2 translation | |
3786 | * HCR_PTW forbids certain page-table setups | |
3787 | * HCR_DC Disables stage1 and enables stage2 translation | |
3788 | */ | |
3789 | if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { | |
d10eb08f | 3790 | tlb_flush(CPU(cpu)); |
f149e3e8 EI |
3791 | } |
3792 | raw_write(env, ri, value); | |
3793 | } | |
3794 | ||
4771cd01 | 3795 | static const ARMCPRegInfo el2_cp_reginfo[] = { |
f149e3e8 EI |
3796 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
3797 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, | |
3798 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
3799 | .writefn = hcr_write }, | |
3b685ba7 | 3800 | { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 3801 | .type = ARM_CP_ALIAS, |
3b685ba7 EI |
3802 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, |
3803 | .access = PL2_RW, | |
3804 | .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, | |
f2c30f42 | 3805 | { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, |
f2c30f42 EI |
3806 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, |
3807 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, | |
63b60551 EI |
3808 | { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, |
3809 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, | |
3810 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, | |
3b685ba7 | 3811 | { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 3812 | .type = ARM_CP_ALIAS, |
3b685ba7 | 3813 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
3814 | .access = PL2_RW, |
3815 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, | |
d42e3c26 EI |
3816 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, |
3817 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | |
3818 | .access = PL2_RW, .writefn = vbar_write, | |
3819 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), | |
3820 | .resetvalue = 0 }, | |
884b4dee GB |
3821 | { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, |
3822 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 3823 | .access = PL3_RW, .type = ARM_CP_ALIAS, |
884b4dee | 3824 | .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, |
c6f19164 GB |
3825 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
3826 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
3827 | .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, | |
3828 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) }, | |
95f949ac EI |
3829 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
3830 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
3831 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), | |
3832 | .resetvalue = 0 }, | |
3833 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
3834 | .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, | |
3835 | .access = PL2_RW, .type = ARM_CP_ALIAS, | |
3836 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, | |
2179ef95 PM |
3837 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
3838 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
3839 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3840 | .resetvalue = 0 }, | |
3841 | /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ | |
3842 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
3843 | .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, | |
3844 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3845 | .resetvalue = 0 }, | |
37cd6c24 PM |
3846 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
3847 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
3848 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3849 | .resetvalue = 0 }, | |
3850 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
3851 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
3852 | .access = PL2_RW, .type = ARM_CP_CONST, | |
3853 | .resetvalue = 0 }, | |
06ec4c8c EI |
3854 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
3855 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
6459b94c PM |
3856 | .access = PL2_RW, |
3857 | /* no .writefn needed as this can't cause an ASID change; | |
3858 | * no .raw_writefn or .resetfn needed as we never use mask/base_mask | |
3859 | */ | |
06ec4c8c | 3860 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, |
68e9c2fe EI |
3861 | { .name = "VTCR", .state = ARM_CP_STATE_AA32, |
3862 | .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 | 3863 | .type = ARM_CP_ALIAS, |
68e9c2fe EI |
3864 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
3865 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, | |
3866 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, | |
3867 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 PM |
3868 | .access = PL2_RW, |
3869 | /* no .writefn needed as this can't cause an ASID change; | |
3870 | * no .raw_writefn or .resetfn needed as we never use mask/base_mask | |
3871 | */ | |
68e9c2fe | 3872 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, |
b698e9cf EI |
3873 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
3874 | .cp = 15, .opc1 = 6, .crm = 2, | |
3875 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
3876 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
3877 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), | |
3878 | .writefn = vttbr_write }, | |
3879 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
3880 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
3881 | .access = PL2_RW, .writefn = vttbr_write, | |
3882 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, | |
b9cb5323 EI |
3883 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
3884 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
3885 | .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, | |
3886 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, | |
ff05f37b EI |
3887 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
3888 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
3889 | .access = PL2_RW, .resetvalue = 0, | |
3890 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, | |
a57633c0 EI |
3891 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
3892 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
3893 | .access = PL2_RW, .resetvalue = 0, | |
3894 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, | |
3895 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
3896 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
a57633c0 | 3897 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
541ef8c2 SS |
3898 | { .name = "TLBIALLNSNH", |
3899 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
3900 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3901 | .writefn = tlbiall_nsnh_write }, | |
3902 | { .name = "TLBIALLNSNHIS", | |
3903 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
3904 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3905 | .writefn = tlbiall_nsnh_is_write }, | |
3906 | { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
3907 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3908 | .writefn = tlbiall_hyp_write }, | |
3909 | { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
3910 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3911 | .writefn = tlbiall_hyp_is_write }, | |
3912 | { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
3913 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3914 | .writefn = tlbimva_hyp_write }, | |
3915 | { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
3916 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
3917 | .writefn = tlbimva_hyp_is_write }, | |
51da9014 EI |
3918 | { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, |
3919 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
3920 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 3921 | .writefn = tlbi_aa64_alle2_write }, |
8742d49d EI |
3922 | { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, |
3923 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
3924 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 3925 | .writefn = tlbi_aa64_vae2_write }, |
2bfb9d75 PM |
3926 | { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, |
3927 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, | |
3928 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3929 | .writefn = tlbi_aa64_vae2_write }, | |
3930 | { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, | |
3931 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
3932 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3933 | .writefn = tlbi_aa64_alle2is_write }, | |
8742d49d EI |
3934 | { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, |
3935 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
3936 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 3937 | .writefn = tlbi_aa64_vae2is_write }, |
2bfb9d75 PM |
3938 | { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, |
3939 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
3940 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
3941 | .writefn = tlbi_aa64_vae2is_write }, | |
edac4d8a | 3942 | #ifndef CONFIG_USER_ONLY |
2a47df95 PM |
3943 | /* Unlike the other EL2-related AT operations, these must |
3944 | * UNDEF from EL3 if EL2 is not implemented, which is why we | |
3945 | * define them here rather than with the rest of the AT ops. | |
3946 | */ | |
3947 | { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, | |
3948 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
3949 | .access = PL2_W, .accessfn = at_s1e2_access, | |
3950 | .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, | |
3951 | { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, | |
3952 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | |
3953 | .access = PL2_W, .accessfn = at_s1e2_access, | |
3954 | .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, | |
14db7fe0 PM |
3955 | /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE |
3956 | * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 | |
3957 | * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose | |
3958 | * to behave as if SCR.NS was 1. | |
3959 | */ | |
3960 | { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
3961 | .access = PL2_W, | |
3962 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, | |
3963 | { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | |
3964 | .access = PL2_W, | |
3965 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, | |
0b6440af EI |
3966 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
3967 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
3968 | /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the | |
3969 | * reset values as IMPDEF. We choose to reset to 3 to comply with | |
3970 | * both ARMv7 and ARMv8. | |
3971 | */ | |
3972 | .access = PL2_RW, .resetvalue = 3, | |
3973 | .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, | |
edac4d8a EI |
3974 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
3975 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
3976 | .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, | |
3977 | .writefn = gt_cntvoff_write, | |
3978 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
3979 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
3980 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, | |
3981 | .writefn = gt_cntvoff_write, | |
3982 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
b0e66d95 EI |
3983 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
3984 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
3985 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
3986 | .type = ARM_CP_IO, .access = PL2_RW, | |
3987 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
3988 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
3989 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
3990 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO, | |
3991 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
3992 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
3993 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
d44ec156 | 3994 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, |
b0e66d95 EI |
3995 | .resetfn = gt_hyp_timer_reset, |
3996 | .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, | |
3997 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
3998 | .type = ARM_CP_IO, | |
3999 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
4000 | .access = PL2_RW, | |
4001 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), | |
4002 | .resetvalue = 0, | |
4003 | .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, | |
edac4d8a | 4004 | #endif |
14cc7b54 SF |
4005 | /* The only field of MDCR_EL2 that has a defined architectural reset value |
4006 | * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we | |
4007 | * don't impelment any PMU event counters, so using zero as a reset | |
4008 | * value for MDCR_EL2 is okay | |
4009 | */ | |
4010 | { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, | |
4011 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | |
4012 | .access = PL2_RW, .resetvalue = 0, | |
4013 | .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), }, | |
59e05530 EI |
4014 | { .name = "HPFAR", .state = ARM_CP_STATE_AA32, |
4015 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
4016 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
4017 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
4018 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, | |
4019 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
4020 | .access = PL2_RW, | |
4021 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
2a5a9abd AF |
4022 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
4023 | .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
4024 | .access = PL2_RW, | |
4025 | .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, | |
3b685ba7 EI |
4026 | REGINFO_SENTINEL |
4027 | }; | |
4028 | ||
2f027fc5 PM |
4029 | static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4030 | bool isread) | |
4031 | { | |
4032 | /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. | |
4033 | * At Secure EL1 it traps to EL3. | |
4034 | */ | |
4035 | if (arm_current_el(env) == 3) { | |
4036 | return CP_ACCESS_OK; | |
4037 | } | |
4038 | if (arm_is_secure_below_el3(env)) { | |
4039 | return CP_ACCESS_TRAP_EL3; | |
4040 | } | |
4041 | /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ | |
4042 | if (isread) { | |
4043 | return CP_ACCESS_OK; | |
4044 | } | |
4045 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
4046 | } | |
4047 | ||
60fb1a87 GB |
4048 | static const ARMCPRegInfo el3_cp_reginfo[] = { |
4049 | { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, | |
4050 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, | |
4051 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), | |
4052 | .resetvalue = 0, .writefn = scr_write }, | |
7a0e58fa | 4053 | { .name = "SCR", .type = ARM_CP_ALIAS, |
60fb1a87 | 4054 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, |
efe4a274 PM |
4055 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
4056 | .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), | |
b061a82b | 4057 | .writefn = scr_write }, |
60fb1a87 GB |
4058 | { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, |
4059 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, | |
4060 | .access = PL3_RW, .resetvalue = 0, | |
4061 | .fieldoffset = offsetof(CPUARMState, cp15.sder) }, | |
4062 | { .name = "SDER", | |
4063 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, | |
4064 | .access = PL3_RW, .resetvalue = 0, | |
4065 | .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, | |
60fb1a87 | 4066 | { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, |
efe4a274 PM |
4067 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
4068 | .writefn = vbar_write, .resetvalue = 0, | |
60fb1a87 | 4069 | .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, |
7dd8c9af FA |
4070 | { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, |
4071 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, | |
4072 | .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
4073 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, | |
11f136ee FA |
4074 | { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, |
4075 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, | |
6459b94c PM |
4076 | .access = PL3_RW, |
4077 | /* no .writefn needed as this can't cause an ASID change; | |
811595a2 PM |
4078 | * we must provide a .raw_writefn and .resetfn because we handle |
4079 | * reset and migration for the AArch32 TTBCR(S), which might be | |
4080 | * using mask and base_mask. | |
6459b94c | 4081 | */ |
811595a2 | 4082 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, |
11f136ee | 4083 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, |
81547d66 | 4084 | { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4085 | .type = ARM_CP_ALIAS, |
81547d66 EI |
4086 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, |
4087 | .access = PL3_RW, | |
4088 | .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, | |
f2c30f42 | 4089 | { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, |
f2c30f42 EI |
4090 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, |
4091 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, | |
63b60551 EI |
4092 | { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, |
4093 | .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, | |
4094 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, | |
81547d66 | 4095 | { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4096 | .type = ARM_CP_ALIAS, |
81547d66 | 4097 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
4098 | .access = PL3_RW, |
4099 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) }, | |
a1ba125c EI |
4100 | { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, |
4101 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, | |
4102 | .access = PL3_RW, .writefn = vbar_write, | |
4103 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), | |
4104 | .resetvalue = 0 }, | |
c6f19164 GB |
4105 | { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, |
4106 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, | |
4107 | .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, | |
4108 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, | |
4cfb8ad8 PM |
4109 | { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, |
4110 | .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, | |
4111 | .access = PL3_RW, .resetvalue = 0, | |
4112 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, | |
2179ef95 PM |
4113 | { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64, |
4114 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, | |
4115 | .access = PL3_RW, .type = ARM_CP_CONST, | |
4116 | .resetvalue = 0 }, | |
37cd6c24 PM |
4117 | { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, |
4118 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, | |
4119 | .access = PL3_RW, .type = ARM_CP_CONST, | |
4120 | .resetvalue = 0 }, | |
4121 | { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, | |
4122 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, | |
4123 | .access = PL3_RW, .type = ARM_CP_CONST, | |
4124 | .resetvalue = 0 }, | |
43efaa33 PM |
4125 | { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, |
4126 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, | |
4127 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
4128 | .writefn = tlbi_aa64_alle3is_write }, | |
4129 | { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, | |
4130 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, | |
4131 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
4132 | .writefn = tlbi_aa64_vae3is_write }, | |
4133 | { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, | |
4134 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, | |
4135 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
4136 | .writefn = tlbi_aa64_vae3is_write }, | |
4137 | { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, | |
4138 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, | |
4139 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
4140 | .writefn = tlbi_aa64_alle3_write }, | |
4141 | { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, | |
4142 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, | |
4143 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
4144 | .writefn = tlbi_aa64_vae3_write }, | |
4145 | { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, | |
4146 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, | |
4147 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
4148 | .writefn = tlbi_aa64_vae3_write }, | |
0f1a3b24 FA |
4149 | REGINFO_SENTINEL |
4150 | }; | |
4151 | ||
3f208fd7 PM |
4152 | static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4153 | bool isread) | |
7da845b0 PM |
4154 | { |
4155 | /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, | |
4156 | * but the AArch32 CTR has its own reginfo struct) | |
4157 | */ | |
137feaa9 | 4158 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) { |
7da845b0 PM |
4159 | return CP_ACCESS_TRAP; |
4160 | } | |
4161 | return CP_ACCESS_OK; | |
4162 | } | |
4163 | ||
1424ca8d DM |
4164 | static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4165 | uint64_t value) | |
4166 | { | |
4167 | /* Writes to OSLAR_EL1 may update the OS lock status, which can be | |
4168 | * read via a bit in OSLSR_EL1. | |
4169 | */ | |
4170 | int oslock; | |
4171 | ||
4172 | if (ri->state == ARM_CP_STATE_AA32) { | |
4173 | oslock = (value == 0xC5ACCE55); | |
4174 | } else { | |
4175 | oslock = value & 1; | |
4176 | } | |
4177 | ||
4178 | env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); | |
4179 | } | |
4180 | ||
50300698 | 4181 | static const ARMCPRegInfo debug_cp_reginfo[] = { |
50300698 | 4182 | /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped |
10aae104 PM |
4183 | * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; |
4184 | * unlike DBGDRAR it is never accessible from EL0. | |
4185 | * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 | |
4186 | * accessor. | |
50300698 PM |
4187 | */ |
4188 | { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
91b0a238 PM |
4189 | .access = PL0_R, .accessfn = access_tdra, |
4190 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
10aae104 PM |
4191 | { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, |
4192 | .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, | |
91b0a238 PM |
4193 | .access = PL1_R, .accessfn = access_tdra, |
4194 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
50300698 | 4195 | { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
91b0a238 PM |
4196 | .access = PL0_R, .accessfn = access_tdra, |
4197 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
17a9eb53 | 4198 | /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ |
10aae104 PM |
4199 | { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, |
4200 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
d6c8cf81 | 4201 | .access = PL1_RW, .accessfn = access_tda, |
0e5e8935 PM |
4202 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), |
4203 | .resetvalue = 0 }, | |
5e8b12ff PM |
4204 | /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. |
4205 | * We don't implement the configurable EL0 access. | |
4206 | */ | |
4207 | { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH, | |
4208 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
7a0e58fa | 4209 | .type = ARM_CP_ALIAS, |
d6c8cf81 | 4210 | .access = PL1_R, .accessfn = access_tda, |
b061a82b | 4211 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, |
10aae104 PM |
4212 | { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, |
4213 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, | |
1424ca8d | 4214 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
187f678d | 4215 | .accessfn = access_tdosa, |
1424ca8d DM |
4216 | .writefn = oslar_write }, |
4217 | { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, | |
4218 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, | |
4219 | .access = PL1_R, .resetvalue = 10, | |
187f678d | 4220 | .accessfn = access_tdosa, |
1424ca8d | 4221 | .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, |
5e8b12ff PM |
4222 | /* Dummy OSDLR_EL1: 32-bit Linux will read this */ |
4223 | { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, | |
4224 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, | |
187f678d PM |
4225 | .access = PL1_RW, .accessfn = access_tdosa, |
4226 | .type = ARM_CP_NOP }, | |
5e8b12ff PM |
4227 | /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't |
4228 | * implement vector catch debug events yet. | |
4229 | */ | |
4230 | { .name = "DBGVCR", | |
4231 | .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
d6c8cf81 PM |
4232 | .access = PL1_RW, .accessfn = access_tda, |
4233 | .type = ARM_CP_NOP }, | |
4d2ec4da PM |
4234 | /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor |
4235 | * to save and restore a 32-bit guest's DBGVCR) | |
4236 | */ | |
4237 | { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, | |
4238 | .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, | |
4239 | .access = PL2_RW, .accessfn = access_tda, | |
4240 | .type = ARM_CP_NOP }, | |
5dbdc434 PM |
4241 | /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications |
4242 | * Channel but Linux may try to access this register. The 32-bit | |
4243 | * alias is DBGDCCINT. | |
4244 | */ | |
4245 | { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, | |
4246 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
4247 | .access = PL1_RW, .accessfn = access_tda, | |
4248 | .type = ARM_CP_NOP }, | |
50300698 PM |
4249 | REGINFO_SENTINEL |
4250 | }; | |
4251 | ||
4252 | static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | |
4253 | /* 64 bit access versions of the (dummy) debug registers */ | |
4254 | { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, | |
4255 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
4256 | { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | |
4257 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
4258 | REGINFO_SENTINEL | |
4259 | }; | |
4260 | ||
9ee98ce8 PM |
4261 | void hw_watchpoint_update(ARMCPU *cpu, int n) |
4262 | { | |
4263 | CPUARMState *env = &cpu->env; | |
4264 | vaddr len = 0; | |
4265 | vaddr wvr = env->cp15.dbgwvr[n]; | |
4266 | uint64_t wcr = env->cp15.dbgwcr[n]; | |
4267 | int mask; | |
4268 | int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; | |
4269 | ||
4270 | if (env->cpu_watchpoint[n]) { | |
4271 | cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); | |
4272 | env->cpu_watchpoint[n] = NULL; | |
4273 | } | |
4274 | ||
4275 | if (!extract64(wcr, 0, 1)) { | |
4276 | /* E bit clear : watchpoint disabled */ | |
4277 | return; | |
4278 | } | |
4279 | ||
4280 | switch (extract64(wcr, 3, 2)) { | |
4281 | case 0: | |
4282 | /* LSC 00 is reserved and must behave as if the wp is disabled */ | |
4283 | return; | |
4284 | case 1: | |
4285 | flags |= BP_MEM_READ; | |
4286 | break; | |
4287 | case 2: | |
4288 | flags |= BP_MEM_WRITE; | |
4289 | break; | |
4290 | case 3: | |
4291 | flags |= BP_MEM_ACCESS; | |
4292 | break; | |
4293 | } | |
4294 | ||
4295 | /* Attempts to use both MASK and BAS fields simultaneously are | |
4296 | * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, | |
4297 | * thus generating a watchpoint for every byte in the masked region. | |
4298 | */ | |
4299 | mask = extract64(wcr, 24, 4); | |
4300 | if (mask == 1 || mask == 2) { | |
4301 | /* Reserved values of MASK; we must act as if the mask value was | |
4302 | * some non-reserved value, or as if the watchpoint were disabled. | |
4303 | * We choose the latter. | |
4304 | */ | |
4305 | return; | |
4306 | } else if (mask) { | |
4307 | /* Watchpoint covers an aligned area up to 2GB in size */ | |
4308 | len = 1ULL << mask; | |
4309 | /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE | |
4310 | * whether the watchpoint fires when the unmasked bits match; we opt | |
4311 | * to generate the exceptions. | |
4312 | */ | |
4313 | wvr &= ~(len - 1); | |
4314 | } else { | |
4315 | /* Watchpoint covers bytes defined by the byte address select bits */ | |
4316 | int bas = extract64(wcr, 5, 8); | |
4317 | int basstart; | |
4318 | ||
4319 | if (bas == 0) { | |
4320 | /* This must act as if the watchpoint is disabled */ | |
4321 | return; | |
4322 | } | |
4323 | ||
4324 | if (extract64(wvr, 2, 1)) { | |
4325 | /* Deprecated case of an only 4-aligned address. BAS[7:4] are | |
4326 | * ignored, and BAS[3:0] define which bytes to watch. | |
4327 | */ | |
4328 | bas &= 0xf; | |
4329 | } | |
4330 | /* The BAS bits are supposed to be programmed to indicate a contiguous | |
4331 | * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether | |
4332 | * we fire for each byte in the word/doubleword addressed by the WVR. | |
4333 | * We choose to ignore any non-zero bits after the first range of 1s. | |
4334 | */ | |
4335 | basstart = ctz32(bas); | |
4336 | len = cto32(bas >> basstart); | |
4337 | wvr += basstart; | |
4338 | } | |
4339 | ||
4340 | cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, | |
4341 | &env->cpu_watchpoint[n]); | |
4342 | } | |
4343 | ||
4344 | void hw_watchpoint_update_all(ARMCPU *cpu) | |
4345 | { | |
4346 | int i; | |
4347 | CPUARMState *env = &cpu->env; | |
4348 | ||
4349 | /* Completely clear out existing QEMU watchpoints and our array, to | |
4350 | * avoid possible stale entries following migration load. | |
4351 | */ | |
4352 | cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); | |
4353 | memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); | |
4354 | ||
4355 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { | |
4356 | hw_watchpoint_update(cpu, i); | |
4357 | } | |
4358 | } | |
4359 | ||
4360 | static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4361 | uint64_t value) | |
4362 | { | |
4363 | ARMCPU *cpu = arm_env_get_cpu(env); | |
4364 | int i = ri->crm; | |
4365 | ||
4366 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, the | |
4367 | * register reads and behaves as if values written are sign extended. | |
4368 | * Bits [1:0] are RES0. | |
4369 | */ | |
4370 | value = sextract64(value, 0, 49) & ~3ULL; | |
4371 | ||
4372 | raw_write(env, ri, value); | |
4373 | hw_watchpoint_update(cpu, i); | |
4374 | } | |
4375 | ||
4376 | static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4377 | uint64_t value) | |
4378 | { | |
4379 | ARMCPU *cpu = arm_env_get_cpu(env); | |
4380 | int i = ri->crm; | |
4381 | ||
4382 | raw_write(env, ri, value); | |
4383 | hw_watchpoint_update(cpu, i); | |
4384 | } | |
4385 | ||
46747d15 PM |
4386 | void hw_breakpoint_update(ARMCPU *cpu, int n) |
4387 | { | |
4388 | CPUARMState *env = &cpu->env; | |
4389 | uint64_t bvr = env->cp15.dbgbvr[n]; | |
4390 | uint64_t bcr = env->cp15.dbgbcr[n]; | |
4391 | vaddr addr; | |
4392 | int bt; | |
4393 | int flags = BP_CPU; | |
4394 | ||
4395 | if (env->cpu_breakpoint[n]) { | |
4396 | cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); | |
4397 | env->cpu_breakpoint[n] = NULL; | |
4398 | } | |
4399 | ||
4400 | if (!extract64(bcr, 0, 1)) { | |
4401 | /* E bit clear : watchpoint disabled */ | |
4402 | return; | |
4403 | } | |
4404 | ||
4405 | bt = extract64(bcr, 20, 4); | |
4406 | ||
4407 | switch (bt) { | |
4408 | case 4: /* unlinked address mismatch (reserved if AArch64) */ | |
4409 | case 5: /* linked address mismatch (reserved if AArch64) */ | |
4410 | qemu_log_mask(LOG_UNIMP, | |
4411 | "arm: address mismatch breakpoint types not implemented"); | |
4412 | return; | |
4413 | case 0: /* unlinked address match */ | |
4414 | case 1: /* linked address match */ | |
4415 | { | |
4416 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, | |
4417 | * we behave as if the register was sign extended. Bits [1:0] are | |
4418 | * RES0. The BAS field is used to allow setting breakpoints on 16 | |
4419 | * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether | |
4420 | * a bp will fire if the addresses covered by the bp and the addresses | |
4421 | * covered by the insn overlap but the insn doesn't start at the | |
4422 | * start of the bp address range. We choose to require the insn and | |
4423 | * the bp to have the same address. The constraints on writing to | |
4424 | * BAS enforced in dbgbcr_write mean we have only four cases: | |
4425 | * 0b0000 => no breakpoint | |
4426 | * 0b0011 => breakpoint on addr | |
4427 | * 0b1100 => breakpoint on addr + 2 | |
4428 | * 0b1111 => breakpoint on addr | |
4429 | * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). | |
4430 | */ | |
4431 | int bas = extract64(bcr, 5, 4); | |
4432 | addr = sextract64(bvr, 0, 49) & ~3ULL; | |
4433 | if (bas == 0) { | |
4434 | return; | |
4435 | } | |
4436 | if (bas == 0xc) { | |
4437 | addr += 2; | |
4438 | } | |
4439 | break; | |
4440 | } | |
4441 | case 2: /* unlinked context ID match */ | |
4442 | case 8: /* unlinked VMID match (reserved if no EL2) */ | |
4443 | case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ | |
4444 | qemu_log_mask(LOG_UNIMP, | |
4445 | "arm: unlinked context breakpoint types not implemented"); | |
4446 | return; | |
4447 | case 9: /* linked VMID match (reserved if no EL2) */ | |
4448 | case 11: /* linked context ID and VMID match (reserved if no EL2) */ | |
4449 | case 3: /* linked context ID match */ | |
4450 | default: | |
4451 | /* We must generate no events for Linked context matches (unless | |
4452 | * they are linked to by some other bp/wp, which is handled in | |
4453 | * updates for the linking bp/wp). We choose to also generate no events | |
4454 | * for reserved values. | |
4455 | */ | |
4456 | return; | |
4457 | } | |
4458 | ||
4459 | cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); | |
4460 | } | |
4461 | ||
4462 | void hw_breakpoint_update_all(ARMCPU *cpu) | |
4463 | { | |
4464 | int i; | |
4465 | CPUARMState *env = &cpu->env; | |
4466 | ||
4467 | /* Completely clear out existing QEMU breakpoints and our array, to | |
4468 | * avoid possible stale entries following migration load. | |
4469 | */ | |
4470 | cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); | |
4471 | memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); | |
4472 | ||
4473 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { | |
4474 | hw_breakpoint_update(cpu, i); | |
4475 | } | |
4476 | } | |
4477 | ||
4478 | static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4479 | uint64_t value) | |
4480 | { | |
4481 | ARMCPU *cpu = arm_env_get_cpu(env); | |
4482 | int i = ri->crm; | |
4483 | ||
4484 | raw_write(env, ri, value); | |
4485 | hw_breakpoint_update(cpu, i); | |
4486 | } | |
4487 | ||
4488 | static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4489 | uint64_t value) | |
4490 | { | |
4491 | ARMCPU *cpu = arm_env_get_cpu(env); | |
4492 | int i = ri->crm; | |
4493 | ||
4494 | /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only | |
4495 | * copy of BAS[0]. | |
4496 | */ | |
4497 | value = deposit64(value, 6, 1, extract64(value, 5, 1)); | |
4498 | value = deposit64(value, 8, 1, extract64(value, 7, 1)); | |
4499 | ||
4500 | raw_write(env, ri, value); | |
4501 | hw_breakpoint_update(cpu, i); | |
4502 | } | |
4503 | ||
50300698 | 4504 | static void define_debug_regs(ARMCPU *cpu) |
0b45451e | 4505 | { |
50300698 PM |
4506 | /* Define v7 and v8 architectural debug registers. |
4507 | * These are just dummy implementations for now. | |
0b45451e PM |
4508 | */ |
4509 | int i; | |
3ff6fc91 | 4510 | int wrps, brps, ctx_cmps; |
48eb3ae6 PM |
4511 | ARMCPRegInfo dbgdidr = { |
4512 | .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
d6c8cf81 PM |
4513 | .access = PL0_R, .accessfn = access_tda, |
4514 | .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr, | |
48eb3ae6 PM |
4515 | }; |
4516 | ||
3ff6fc91 | 4517 | /* Note that all these register fields hold "number of Xs minus 1". */ |
48eb3ae6 PM |
4518 | brps = extract32(cpu->dbgdidr, 24, 4); |
4519 | wrps = extract32(cpu->dbgdidr, 28, 4); | |
3ff6fc91 PM |
4520 | ctx_cmps = extract32(cpu->dbgdidr, 20, 4); |
4521 | ||
4522 | assert(ctx_cmps <= brps); | |
48eb3ae6 PM |
4523 | |
4524 | /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties | |
4525 | * of the debug registers such as number of breakpoints; | |
4526 | * check that if they both exist then they agree. | |
4527 | */ | |
4528 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
4529 | assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps); | |
4530 | assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps); | |
3ff6fc91 | 4531 | assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps); |
48eb3ae6 | 4532 | } |
0b45451e | 4533 | |
48eb3ae6 | 4534 | define_one_arm_cp_reg(cpu, &dbgdidr); |
50300698 PM |
4535 | define_arm_cp_regs(cpu, debug_cp_reginfo); |
4536 | ||
4537 | if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { | |
4538 | define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); | |
4539 | } | |
4540 | ||
48eb3ae6 | 4541 | for (i = 0; i < brps + 1; i++) { |
0b45451e | 4542 | ARMCPRegInfo dbgregs[] = { |
10aae104 PM |
4543 | { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH, |
4544 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, | |
d6c8cf81 | 4545 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
4546 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), |
4547 | .writefn = dbgbvr_write, .raw_writefn = raw_write | |
4548 | }, | |
10aae104 PM |
4549 | { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH, |
4550 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, | |
d6c8cf81 | 4551 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
4552 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), |
4553 | .writefn = dbgbcr_write, .raw_writefn = raw_write | |
4554 | }, | |
48eb3ae6 PM |
4555 | REGINFO_SENTINEL |
4556 | }; | |
4557 | define_arm_cp_regs(cpu, dbgregs); | |
4558 | } | |
4559 | ||
4560 | for (i = 0; i < wrps + 1; i++) { | |
4561 | ARMCPRegInfo dbgregs[] = { | |
10aae104 PM |
4562 | { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH, |
4563 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, | |
d6c8cf81 | 4564 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
4565 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), |
4566 | .writefn = dbgwvr_write, .raw_writefn = raw_write | |
4567 | }, | |
10aae104 PM |
4568 | { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH, |
4569 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, | |
d6c8cf81 | 4570 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
4571 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), |
4572 | .writefn = dbgwcr_write, .raw_writefn = raw_write | |
4573 | }, | |
4574 | REGINFO_SENTINEL | |
0b45451e PM |
4575 | }; |
4576 | define_arm_cp_regs(cpu, dbgregs); | |
4577 | } | |
4578 | } | |
4579 | ||
96a8b92e PM |
4580 | /* We don't know until after realize whether there's a GICv3 |
4581 | * attached, and that is what registers the gicv3 sysregs. | |
4582 | * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1 | |
4583 | * at runtime. | |
4584 | */ | |
4585 | static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
4586 | { | |
4587 | ARMCPU *cpu = arm_env_get_cpu(env); | |
4588 | uint64_t pfr1 = cpu->id_pfr1; | |
4589 | ||
4590 | if (env->gicv3state) { | |
4591 | pfr1 |= 1 << 28; | |
4592 | } | |
4593 | return pfr1; | |
4594 | } | |
4595 | ||
4596 | static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
4597 | { | |
4598 | ARMCPU *cpu = arm_env_get_cpu(env); | |
4599 | uint64_t pfr0 = cpu->id_aa64pfr0; | |
4600 | ||
4601 | if (env->gicv3state) { | |
4602 | pfr0 |= 1 << 24; | |
4603 | } | |
4604 | return pfr0; | |
4605 | } | |
4606 | ||
2ceb98c0 PM |
4607 | void register_cp_regs_for_features(ARMCPU *cpu) |
4608 | { | |
4609 | /* Register all the coprocessor registers based on feature bits */ | |
4610 | CPUARMState *env = &cpu->env; | |
4611 | if (arm_feature(env, ARM_FEATURE_M)) { | |
4612 | /* M profile has no coprocessor registers */ | |
4613 | return; | |
4614 | } | |
4615 | ||
e9aa6c21 | 4616 | define_arm_cp_regs(cpu, cp_reginfo); |
9449fdf6 PM |
4617 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
4618 | /* Must go early as it is full of wildcards that may be | |
4619 | * overridden by later definitions. | |
4620 | */ | |
4621 | define_arm_cp_regs(cpu, not_v8_cp_reginfo); | |
4622 | } | |
4623 | ||
7d57f408 | 4624 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8515a092 PM |
4625 | /* The ID registers all have impdef reset values */ |
4626 | ARMCPRegInfo v6_idregs[] = { | |
0ff644a7 PM |
4627 | { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, |
4628 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
4629 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4630 | .resetvalue = cpu->id_pfr0 }, |
96a8b92e PM |
4631 | /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know |
4632 | * the value of the GIC field until after we define these regs. | |
4633 | */ | |
0ff644a7 PM |
4634 | { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, |
4635 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | |
96a8b92e PM |
4636 | .access = PL1_R, .type = ARM_CP_NO_RAW, |
4637 | .readfn = id_pfr1_read, | |
4638 | .writefn = arm_cp_write_ignore }, | |
0ff644a7 PM |
4639 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, |
4640 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | |
4641 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4642 | .resetvalue = cpu->id_dfr0 }, |
0ff644a7 PM |
4643 | { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, |
4644 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, | |
4645 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4646 | .resetvalue = cpu->id_afr0 }, |
0ff644a7 PM |
4647 | { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, |
4648 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, | |
4649 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4650 | .resetvalue = cpu->id_mmfr0 }, |
0ff644a7 PM |
4651 | { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, |
4652 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, | |
4653 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4654 | .resetvalue = cpu->id_mmfr1 }, |
0ff644a7 PM |
4655 | { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, |
4656 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, | |
4657 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4658 | .resetvalue = cpu->id_mmfr2 }, |
0ff644a7 PM |
4659 | { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, |
4660 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, | |
4661 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4662 | .resetvalue = cpu->id_mmfr3 }, |
0ff644a7 PM |
4663 | { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, |
4664 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
4665 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4666 | .resetvalue = cpu->id_isar0 }, |
0ff644a7 PM |
4667 | { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, |
4668 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, | |
4669 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4670 | .resetvalue = cpu->id_isar1 }, |
0ff644a7 PM |
4671 | { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, |
4672 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
4673 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4674 | .resetvalue = cpu->id_isar2 }, |
0ff644a7 PM |
4675 | { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, |
4676 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, | |
4677 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4678 | .resetvalue = cpu->id_isar3 }, |
0ff644a7 PM |
4679 | { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, |
4680 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, | |
4681 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4682 | .resetvalue = cpu->id_isar4 }, |
0ff644a7 PM |
4683 | { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, |
4684 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, | |
4685 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 4686 | .resetvalue = cpu->id_isar5 }, |
e20d84c1 PM |
4687 | { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, |
4688 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, | |
4689 | .access = PL1_R, .type = ARM_CP_CONST, | |
4690 | .resetvalue = cpu->id_mmfr4 }, | |
4691 | /* 7 is as yet unallocated and must RAZ */ | |
4692 | { .name = "ID_ISAR7_RESERVED", .state = ARM_CP_STATE_BOTH, | |
4693 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, | |
4694 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 PM |
4695 | .resetvalue = 0 }, |
4696 | REGINFO_SENTINEL | |
4697 | }; | |
4698 | define_arm_cp_regs(cpu, v6_idregs); | |
7d57f408 PM |
4699 | define_arm_cp_regs(cpu, v6_cp_reginfo); |
4700 | } else { | |
4701 | define_arm_cp_regs(cpu, not_v6_cp_reginfo); | |
4702 | } | |
4d31c596 PM |
4703 | if (arm_feature(env, ARM_FEATURE_V6K)) { |
4704 | define_arm_cp_regs(cpu, v6k_cp_reginfo); | |
4705 | } | |
5e5cf9e3 | 4706 | if (arm_feature(env, ARM_FEATURE_V7MP) && |
452a0955 | 4707 | !arm_feature(env, ARM_FEATURE_PMSA)) { |
995939a6 PM |
4708 | define_arm_cp_regs(cpu, v7mp_cp_reginfo); |
4709 | } | |
e9aa6c21 | 4710 | if (arm_feature(env, ARM_FEATURE_V7)) { |
200ac0ef | 4711 | /* v7 performance monitor control register: same implementor |
7c2cb42b AF |
4712 | * field as main ID register, and we implement only the cycle |
4713 | * count register. | |
200ac0ef | 4714 | */ |
7c2cb42b | 4715 | #ifndef CONFIG_USER_ONLY |
200ac0ef PM |
4716 | ARMCPRegInfo pmcr = { |
4717 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | |
8521466b | 4718 | .access = PL0_RW, |
7a0e58fa | 4719 | .type = ARM_CP_IO | ARM_CP_ALIAS, |
8521466b | 4720 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), |
fcd25206 PM |
4721 | .accessfn = pmreg_access, .writefn = pmcr_write, |
4722 | .raw_writefn = raw_write, | |
200ac0ef | 4723 | }; |
8521466b AF |
4724 | ARMCPRegInfo pmcr64 = { |
4725 | .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, | |
4726 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, | |
4727 | .access = PL0_RW, .accessfn = pmreg_access, | |
4728 | .type = ARM_CP_IO, | |
4729 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), | |
4730 | .resetvalue = cpu->midr & 0xff000000, | |
4731 | .writefn = pmcr_write, .raw_writefn = raw_write, | |
4732 | }; | |
7c2cb42b | 4733 | define_one_arm_cp_reg(cpu, &pmcr); |
8521466b | 4734 | define_one_arm_cp_reg(cpu, &pmcr64); |
7c2cb42b | 4735 | #endif |
776d4e5c | 4736 | ARMCPRegInfo clidr = { |
7da845b0 PM |
4737 | .name = "CLIDR", .state = ARM_CP_STATE_BOTH, |
4738 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | |
776d4e5c PM |
4739 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr |
4740 | }; | |
776d4e5c | 4741 | define_one_arm_cp_reg(cpu, &clidr); |
e9aa6c21 | 4742 | define_arm_cp_regs(cpu, v7_cp_reginfo); |
50300698 | 4743 | define_debug_regs(cpu); |
7d57f408 PM |
4744 | } else { |
4745 | define_arm_cp_regs(cpu, not_v7_cp_reginfo); | |
e9aa6c21 | 4746 | } |
b0d2b7d0 | 4747 | if (arm_feature(env, ARM_FEATURE_V8)) { |
e20d84c1 PM |
4748 | /* AArch64 ID registers, which all have impdef reset values. |
4749 | * Note that within the ID register ranges the unused slots | |
4750 | * must all RAZ, not UNDEF; future architecture versions may | |
4751 | * define new registers here. | |
4752 | */ | |
e60cef86 | 4753 | ARMCPRegInfo v8_idregs[] = { |
96a8b92e PM |
4754 | /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't |
4755 | * know the right value for the GIC field until after we | |
4756 | * define these regs. | |
4757 | */ | |
e60cef86 PM |
4758 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, |
4759 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | |
96a8b92e PM |
4760 | .access = PL1_R, .type = ARM_CP_NO_RAW, |
4761 | .readfn = id_aa64pfr0_read, | |
4762 | .writefn = arm_cp_write_ignore }, | |
e60cef86 PM |
4763 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, |
4764 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | |
4765 | .access = PL1_R, .type = ARM_CP_CONST, | |
4766 | .resetvalue = cpu->id_aa64pfr1}, | |
e20d84c1 PM |
4767 | { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
4768 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, | |
4769 | .access = PL1_R, .type = ARM_CP_CONST, | |
4770 | .resetvalue = 0 }, | |
4771 | { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4772 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, | |
4773 | .access = PL1_R, .type = ARM_CP_CONST, | |
4774 | .resetvalue = 0 }, | |
4775 | { .name = "ID_AA64PFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4776 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, | |
4777 | .access = PL1_R, .type = ARM_CP_CONST, | |
4778 | .resetvalue = 0 }, | |
4779 | { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4780 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, | |
4781 | .access = PL1_R, .type = ARM_CP_CONST, | |
4782 | .resetvalue = 0 }, | |
4783 | { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4784 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, | |
4785 | .access = PL1_R, .type = ARM_CP_CONST, | |
4786 | .resetvalue = 0 }, | |
4787 | { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4788 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, | |
4789 | .access = PL1_R, .type = ARM_CP_CONST, | |
4790 | .resetvalue = 0 }, | |
e60cef86 PM |
4791 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, |
4792 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | |
4793 | .access = PL1_R, .type = ARM_CP_CONST, | |
d6f02ce3 | 4794 | .resetvalue = cpu->id_aa64dfr0 }, |
e60cef86 PM |
4795 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, |
4796 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | |
4797 | .access = PL1_R, .type = ARM_CP_CONST, | |
4798 | .resetvalue = cpu->id_aa64dfr1 }, | |
e20d84c1 PM |
4799 | { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
4800 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, | |
4801 | .access = PL1_R, .type = ARM_CP_CONST, | |
4802 | .resetvalue = 0 }, | |
4803 | { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4804 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, | |
4805 | .access = PL1_R, .type = ARM_CP_CONST, | |
4806 | .resetvalue = 0 }, | |
e60cef86 PM |
4807 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, |
4808 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | |
4809 | .access = PL1_R, .type = ARM_CP_CONST, | |
4810 | .resetvalue = cpu->id_aa64afr0 }, | |
4811 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | |
4812 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | |
4813 | .access = PL1_R, .type = ARM_CP_CONST, | |
4814 | .resetvalue = cpu->id_aa64afr1 }, | |
e20d84c1 PM |
4815 | { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
4816 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, | |
4817 | .access = PL1_R, .type = ARM_CP_CONST, | |
4818 | .resetvalue = 0 }, | |
4819 | { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4820 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, | |
4821 | .access = PL1_R, .type = ARM_CP_CONST, | |
4822 | .resetvalue = 0 }, | |
e60cef86 PM |
4823 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, |
4824 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | |
4825 | .access = PL1_R, .type = ARM_CP_CONST, | |
4826 | .resetvalue = cpu->id_aa64isar0 }, | |
4827 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, | |
4828 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | |
4829 | .access = PL1_R, .type = ARM_CP_CONST, | |
4830 | .resetvalue = cpu->id_aa64isar1 }, | |
e20d84c1 PM |
4831 | { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
4832 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, | |
4833 | .access = PL1_R, .type = ARM_CP_CONST, | |
4834 | .resetvalue = 0 }, | |
4835 | { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4836 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, | |
4837 | .access = PL1_R, .type = ARM_CP_CONST, | |
4838 | .resetvalue = 0 }, | |
4839 | { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4840 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, | |
4841 | .access = PL1_R, .type = ARM_CP_CONST, | |
4842 | .resetvalue = 0 }, | |
4843 | { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4844 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, | |
4845 | .access = PL1_R, .type = ARM_CP_CONST, | |
4846 | .resetvalue = 0 }, | |
4847 | { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4848 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, | |
4849 | .access = PL1_R, .type = ARM_CP_CONST, | |
4850 | .resetvalue = 0 }, | |
4851 | { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4852 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, | |
4853 | .access = PL1_R, .type = ARM_CP_CONST, | |
4854 | .resetvalue = 0 }, | |
e60cef86 PM |
4855 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, |
4856 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
4857 | .access = PL1_R, .type = ARM_CP_CONST, | |
4858 | .resetvalue = cpu->id_aa64mmfr0 }, | |
4859 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, | |
4860 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | |
4861 | .access = PL1_R, .type = ARM_CP_CONST, | |
4862 | .resetvalue = cpu->id_aa64mmfr1 }, | |
e20d84c1 PM |
4863 | { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
4864 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, | |
4865 | .access = PL1_R, .type = ARM_CP_CONST, | |
4866 | .resetvalue = 0 }, | |
4867 | { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4868 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, | |
4869 | .access = PL1_R, .type = ARM_CP_CONST, | |
4870 | .resetvalue = 0 }, | |
4871 | { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4872 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, | |
4873 | .access = PL1_R, .type = ARM_CP_CONST, | |
4874 | .resetvalue = 0 }, | |
4875 | { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4876 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, | |
4877 | .access = PL1_R, .type = ARM_CP_CONST, | |
4878 | .resetvalue = 0 }, | |
4879 | { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4880 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, | |
4881 | .access = PL1_R, .type = ARM_CP_CONST, | |
4882 | .resetvalue = 0 }, | |
4883 | { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4884 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, | |
4885 | .access = PL1_R, .type = ARM_CP_CONST, | |
4886 | .resetvalue = 0 }, | |
a50c0f51 PM |
4887 | { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, |
4888 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
4889 | .access = PL1_R, .type = ARM_CP_CONST, | |
4890 | .resetvalue = cpu->mvfr0 }, | |
4891 | { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, | |
4892 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
4893 | .access = PL1_R, .type = ARM_CP_CONST, | |
4894 | .resetvalue = cpu->mvfr1 }, | |
4895 | { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, | |
4896 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
4897 | .access = PL1_R, .type = ARM_CP_CONST, | |
4898 | .resetvalue = cpu->mvfr2 }, | |
e20d84c1 PM |
4899 | { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
4900 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, | |
4901 | .access = PL1_R, .type = ARM_CP_CONST, | |
4902 | .resetvalue = 0 }, | |
4903 | { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4904 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, | |
4905 | .access = PL1_R, .type = ARM_CP_CONST, | |
4906 | .resetvalue = 0 }, | |
4907 | { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4908 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, | |
4909 | .access = PL1_R, .type = ARM_CP_CONST, | |
4910 | .resetvalue = 0 }, | |
4911 | { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4912 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, | |
4913 | .access = PL1_R, .type = ARM_CP_CONST, | |
4914 | .resetvalue = 0 }, | |
4915 | { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
4916 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, | |
4917 | .access = PL1_R, .type = ARM_CP_CONST, | |
4918 | .resetvalue = 0 }, | |
4054bfa9 AF |
4919 | { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, |
4920 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, | |
4921 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
4922 | .resetvalue = cpu->pmceid0 }, | |
4923 | { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, | |
4924 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, | |
4925 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
4926 | .resetvalue = cpu->pmceid0 }, | |
4927 | { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, | |
4928 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, | |
4929 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
4930 | .resetvalue = cpu->pmceid1 }, | |
4931 | { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, | |
4932 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, | |
4933 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
4934 | .resetvalue = cpu->pmceid1 }, | |
e60cef86 PM |
4935 | REGINFO_SENTINEL |
4936 | }; | |
be8e8128 GB |
4937 | /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ |
4938 | if (!arm_feature(env, ARM_FEATURE_EL3) && | |
4939 | !arm_feature(env, ARM_FEATURE_EL2)) { | |
4940 | ARMCPRegInfo rvbar = { | |
4941 | .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, | |
4942 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, | |
4943 | .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar | |
4944 | }; | |
4945 | define_one_arm_cp_reg(cpu, &rvbar); | |
4946 | } | |
e60cef86 | 4947 | define_arm_cp_regs(cpu, v8_idregs); |
b0d2b7d0 PM |
4948 | define_arm_cp_regs(cpu, v8_cp_reginfo); |
4949 | } | |
3b685ba7 | 4950 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
f0d574d6 | 4951 | uint64_t vmpidr_def = mpidr_read_val(env); |
731de9e6 EI |
4952 | ARMCPRegInfo vpidr_regs[] = { |
4953 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | |
4954 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
4955 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
4956 | .resetvalue = cpu->midr, | |
4957 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
4958 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, | |
4959 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
4960 | .access = PL2_RW, .resetvalue = cpu->midr, | |
4961 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
f0d574d6 EI |
4962 | { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, |
4963 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
4964 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
4965 | .resetvalue = vmpidr_def, | |
4966 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | |
4967 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, | |
4968 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
4969 | .access = PL2_RW, | |
4970 | .resetvalue = vmpidr_def, | |
4971 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | |
731de9e6 EI |
4972 | REGINFO_SENTINEL |
4973 | }; | |
4974 | define_arm_cp_regs(cpu, vpidr_regs); | |
4771cd01 | 4975 | define_arm_cp_regs(cpu, el2_cp_reginfo); |
be8e8128 GB |
4976 | /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ |
4977 | if (!arm_feature(env, ARM_FEATURE_EL3)) { | |
4978 | ARMCPRegInfo rvbar = { | |
4979 | .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, | |
4980 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, | |
4981 | .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar | |
4982 | }; | |
4983 | define_one_arm_cp_reg(cpu, &rvbar); | |
4984 | } | |
d42e3c26 EI |
4985 | } else { |
4986 | /* If EL2 is missing but higher ELs are enabled, we need to | |
4987 | * register the no_el2 reginfos. | |
4988 | */ | |
4989 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
f0d574d6 EI |
4990 | /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value |
4991 | * of MIDR_EL1 and MPIDR_EL1. | |
731de9e6 EI |
4992 | */ |
4993 | ARMCPRegInfo vpidr_regs[] = { | |
4994 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH, | |
4995 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
4996 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
4997 | .type = ARM_CP_CONST, .resetvalue = cpu->midr, | |
4998 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
f0d574d6 EI |
4999 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
5000 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
5001 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
5002 | .type = ARM_CP_NO_RAW, | |
5003 | .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, | |
731de9e6 EI |
5004 | REGINFO_SENTINEL |
5005 | }; | |
5006 | define_arm_cp_regs(cpu, vpidr_regs); | |
4771cd01 | 5007 | define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); |
d42e3c26 | 5008 | } |
3b685ba7 | 5009 | } |
81547d66 | 5010 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0f1a3b24 | 5011 | define_arm_cp_regs(cpu, el3_cp_reginfo); |
e24fdd23 PM |
5012 | ARMCPRegInfo el3_regs[] = { |
5013 | { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, | |
5014 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, | |
5015 | .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, | |
5016 | { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, | |
5017 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, | |
5018 | .access = PL3_RW, | |
5019 | .raw_writefn = raw_write, .writefn = sctlr_write, | |
5020 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), | |
5021 | .resetvalue = cpu->reset_sctlr }, | |
5022 | REGINFO_SENTINEL | |
be8e8128 | 5023 | }; |
e24fdd23 PM |
5024 | |
5025 | define_arm_cp_regs(cpu, el3_regs); | |
81547d66 | 5026 | } |
2f027fc5 PM |
5027 | /* The behaviour of NSACR is sufficiently various that we don't |
5028 | * try to describe it in a single reginfo: | |
5029 | * if EL3 is 64 bit, then trap to EL3 from S EL1, | |
5030 | * reads as constant 0xc00 from NS EL1 and NS EL2 | |
5031 | * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 | |
5032 | * if v7 without EL3, register doesn't exist | |
5033 | * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 | |
5034 | */ | |
5035 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
5036 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
5037 | ARMCPRegInfo nsacr = { | |
5038 | .name = "NSACR", .type = ARM_CP_CONST, | |
5039 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
5040 | .access = PL1_RW, .accessfn = nsacr_access, | |
5041 | .resetvalue = 0xc00 | |
5042 | }; | |
5043 | define_one_arm_cp_reg(cpu, &nsacr); | |
5044 | } else { | |
5045 | ARMCPRegInfo nsacr = { | |
5046 | .name = "NSACR", | |
5047 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
5048 | .access = PL3_RW | PL1_R, | |
5049 | .resetvalue = 0, | |
5050 | .fieldoffset = offsetof(CPUARMState, cp15.nsacr) | |
5051 | }; | |
5052 | define_one_arm_cp_reg(cpu, &nsacr); | |
5053 | } | |
5054 | } else { | |
5055 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
5056 | ARMCPRegInfo nsacr = { | |
5057 | .name = "NSACR", .type = ARM_CP_CONST, | |
5058 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
5059 | .access = PL1_R, | |
5060 | .resetvalue = 0xc00 | |
5061 | }; | |
5062 | define_one_arm_cp_reg(cpu, &nsacr); | |
5063 | } | |
5064 | } | |
5065 | ||
452a0955 | 5066 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
6cb0b013 PC |
5067 | if (arm_feature(env, ARM_FEATURE_V6)) { |
5068 | /* PMSAv6 not implemented */ | |
5069 | assert(arm_feature(env, ARM_FEATURE_V7)); | |
5070 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); | |
5071 | define_arm_cp_regs(cpu, pmsav7_cp_reginfo); | |
5072 | } else { | |
5073 | define_arm_cp_regs(cpu, pmsav5_cp_reginfo); | |
5074 | } | |
18032bec | 5075 | } else { |
8e5d75c9 | 5076 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); |
18032bec PM |
5077 | define_arm_cp_regs(cpu, vmsa_cp_reginfo); |
5078 | } | |
c326b979 PM |
5079 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
5080 | define_arm_cp_regs(cpu, t2ee_cp_reginfo); | |
5081 | } | |
6cc7a3ae PM |
5082 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
5083 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); | |
5084 | } | |
4a501606 PM |
5085 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
5086 | define_arm_cp_regs(cpu, vapa_cp_reginfo); | |
5087 | } | |
c4804214 PM |
5088 | if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { |
5089 | define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); | |
5090 | } | |
5091 | if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { | |
5092 | define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); | |
5093 | } | |
5094 | if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { | |
5095 | define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); | |
5096 | } | |
18032bec PM |
5097 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
5098 | define_arm_cp_regs(cpu, omap_cp_reginfo); | |
5099 | } | |
34f90529 PM |
5100 | if (arm_feature(env, ARM_FEATURE_STRONGARM)) { |
5101 | define_arm_cp_regs(cpu, strongarm_cp_reginfo); | |
5102 | } | |
1047b9d7 PM |
5103 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
5104 | define_arm_cp_regs(cpu, xscale_cp_reginfo); | |
5105 | } | |
5106 | if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { | |
5107 | define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); | |
5108 | } | |
7ac681cf PM |
5109 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
5110 | define_arm_cp_regs(cpu, lpae_cp_reginfo); | |
5111 | } | |
7884849c PM |
5112 | /* Slightly awkwardly, the OMAP and StrongARM cores need all of |
5113 | * cp15 crn=0 to be writes-ignored, whereas for other cores they should | |
5114 | * be read-only (ie write causes UNDEF exception). | |
5115 | */ | |
5116 | { | |
00a29f3d PM |
5117 | ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { |
5118 | /* Pre-v8 MIDR space. | |
5119 | * Note that the MIDR isn't a simple constant register because | |
7884849c PM |
5120 | * of the TI925 behaviour where writes to another register can |
5121 | * cause the MIDR value to change. | |
97ce8d61 PC |
5122 | * |
5123 | * Unimplemented registers in the c15 0 0 0 space default to | |
5124 | * MIDR. Define MIDR first as this entire space, then CTR, TCMTR | |
5125 | * and friends override accordingly. | |
7884849c PM |
5126 | */ |
5127 | { .name = "MIDR", | |
97ce8d61 | 5128 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, |
7884849c | 5129 | .access = PL1_R, .resetvalue = cpu->midr, |
d4e6df63 | 5130 | .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, |
731de9e6 | 5131 | .readfn = midr_read, |
97ce8d61 PC |
5132 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
5133 | .type = ARM_CP_OVERRIDE }, | |
7884849c PM |
5134 | /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ |
5135 | { .name = "DUMMY", | |
5136 | .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, | |
5137 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5138 | { .name = "DUMMY", | |
5139 | .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, | |
5140 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5141 | { .name = "DUMMY", | |
5142 | .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, | |
5143 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5144 | { .name = "DUMMY", | |
5145 | .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, | |
5146 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5147 | { .name = "DUMMY", | |
5148 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | |
5149 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
5150 | REGINFO_SENTINEL | |
5151 | }; | |
00a29f3d | 5152 | ARMCPRegInfo id_v8_midr_cp_reginfo[] = { |
00a29f3d PM |
5153 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, |
5154 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, | |
731de9e6 EI |
5155 | .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, |
5156 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), | |
5157 | .readfn = midr_read }, | |
ac00c79f SF |
5158 | /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ |
5159 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
5160 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
5161 | .access = PL1_R, .resetvalue = cpu->midr }, | |
5162 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
5163 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, | |
5164 | .access = PL1_R, .resetvalue = cpu->midr }, | |
00a29f3d PM |
5165 | { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, |
5166 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, | |
13b72b2b | 5167 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, |
00a29f3d PM |
5168 | REGINFO_SENTINEL |
5169 | }; | |
5170 | ARMCPRegInfo id_cp_reginfo[] = { | |
5171 | /* These are common to v8 and pre-v8 */ | |
5172 | { .name = "CTR", | |
5173 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, | |
5174 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
5175 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, | |
5176 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, | |
5177 | .access = PL0_R, .accessfn = ctr_el0_access, | |
5178 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
5179 | /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ | |
5180 | { .name = "TCMTR", | |
5181 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, | |
5182 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
00a29f3d PM |
5183 | REGINFO_SENTINEL |
5184 | }; | |
8085ce63 PC |
5185 | /* TLBTR is specific to VMSA */ |
5186 | ARMCPRegInfo id_tlbtr_reginfo = { | |
5187 | .name = "TLBTR", | |
5188 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, | |
5189 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0, | |
5190 | }; | |
3281af81 PC |
5191 | /* MPUIR is specific to PMSA V6+ */ |
5192 | ARMCPRegInfo id_mpuir_reginfo = { | |
5193 | .name = "MPUIR", | |
5194 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
5195 | .access = PL1_R, .type = ARM_CP_CONST, | |
5196 | .resetvalue = cpu->pmsav7_dregion << 8 | |
5197 | }; | |
7884849c PM |
5198 | ARMCPRegInfo crn0_wi_reginfo = { |
5199 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, | |
5200 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | |
5201 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | |
5202 | }; | |
5203 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || | |
5204 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | |
5205 | ARMCPRegInfo *r; | |
5206 | /* Register the blanket "writes ignored" value first to cover the | |
a703eda1 PC |
5207 | * whole space. Then update the specific ID registers to allow write |
5208 | * access, so that they ignore writes rather than causing them to | |
5209 | * UNDEF. | |
7884849c PM |
5210 | */ |
5211 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | |
00a29f3d PM |
5212 | for (r = id_pre_v8_midr_cp_reginfo; |
5213 | r->type != ARM_CP_SENTINEL; r++) { | |
5214 | r->access = PL1_RW; | |
5215 | } | |
7884849c PM |
5216 | for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { |
5217 | r->access = PL1_RW; | |
7884849c | 5218 | } |
8085ce63 | 5219 | id_tlbtr_reginfo.access = PL1_RW; |
3281af81 | 5220 | id_tlbtr_reginfo.access = PL1_RW; |
7884849c | 5221 | } |
00a29f3d PM |
5222 | if (arm_feature(env, ARM_FEATURE_V8)) { |
5223 | define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); | |
5224 | } else { | |
5225 | define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); | |
5226 | } | |
a703eda1 | 5227 | define_arm_cp_regs(cpu, id_cp_reginfo); |
452a0955 | 5228 | if (!arm_feature(env, ARM_FEATURE_PMSA)) { |
8085ce63 | 5229 | define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); |
3281af81 PC |
5230 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
5231 | define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); | |
8085ce63 | 5232 | } |
7884849c PM |
5233 | } |
5234 | ||
97ce8d61 PC |
5235 | if (arm_feature(env, ARM_FEATURE_MPIDR)) { |
5236 | define_arm_cp_regs(cpu, mpidr_cp_reginfo); | |
5237 | } | |
5238 | ||
2771db27 | 5239 | if (arm_feature(env, ARM_FEATURE_AUXCR)) { |
834a6c69 PM |
5240 | ARMCPRegInfo auxcr_reginfo[] = { |
5241 | { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, | |
5242 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, | |
5243 | .access = PL1_RW, .type = ARM_CP_CONST, | |
5244 | .resetvalue = cpu->reset_auxcr }, | |
5245 | { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, | |
5246 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, | |
5247 | .access = PL2_RW, .type = ARM_CP_CONST, | |
5248 | .resetvalue = 0 }, | |
5249 | { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, | |
5250 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, | |
5251 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5252 | .resetvalue = 0 }, | |
5253 | REGINFO_SENTINEL | |
2771db27 | 5254 | }; |
834a6c69 | 5255 | define_arm_cp_regs(cpu, auxcr_reginfo); |
2771db27 PM |
5256 | } |
5257 | ||
d8ba780b | 5258 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
f318cec6 PM |
5259 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
5260 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | |
5261 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | |
5262 | | extract64(cpu->reset_cbar, 32, 12); | |
5263 | ARMCPRegInfo cbar_reginfo[] = { | |
5264 | { .name = "CBAR", | |
5265 | .type = ARM_CP_CONST, | |
5266 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
5267 | .access = PL1_R, .resetvalue = cpu->reset_cbar }, | |
5268 | { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, | |
5269 | .type = ARM_CP_CONST, | |
5270 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | |
5271 | .access = PL1_R, .resetvalue = cbar32 }, | |
5272 | REGINFO_SENTINEL | |
5273 | }; | |
5274 | /* We don't implement a r/w 64 bit CBAR currently */ | |
5275 | assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); | |
5276 | define_arm_cp_regs(cpu, cbar_reginfo); | |
5277 | } else { | |
5278 | ARMCPRegInfo cbar = { | |
5279 | .name = "CBAR", | |
5280 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
5281 | .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, | |
5282 | .fieldoffset = offsetof(CPUARMState, | |
5283 | cp15.c15_config_base_address) | |
5284 | }; | |
5285 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | |
5286 | cbar.access = PL1_R; | |
5287 | cbar.fieldoffset = 0; | |
5288 | cbar.type = ARM_CP_CONST; | |
5289 | } | |
5290 | define_one_arm_cp_reg(cpu, &cbar); | |
5291 | } | |
d8ba780b PC |
5292 | } |
5293 | ||
91db4642 CLG |
5294 | if (arm_feature(env, ARM_FEATURE_VBAR)) { |
5295 | ARMCPRegInfo vbar_cp_reginfo[] = { | |
5296 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, | |
5297 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | |
5298 | .access = PL1_RW, .writefn = vbar_write, | |
5299 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), | |
5300 | offsetof(CPUARMState, cp15.vbar_ns) }, | |
5301 | .resetvalue = 0 }, | |
5302 | REGINFO_SENTINEL | |
5303 | }; | |
5304 | define_arm_cp_regs(cpu, vbar_cp_reginfo); | |
5305 | } | |
5306 | ||
2771db27 PM |
5307 | /* Generic registers whose values depend on the implementation */ |
5308 | { | |
5309 | ARMCPRegInfo sctlr = { | |
5ebafdf3 | 5310 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, |
137feaa9 FA |
5311 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, |
5312 | .access = PL1_RW, | |
5313 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), | |
5314 | offsetof(CPUARMState, cp15.sctlr_ns) }, | |
d4e6df63 PM |
5315 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, |
5316 | .raw_writefn = raw_write, | |
2771db27 PM |
5317 | }; |
5318 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
5319 | /* Normally we would always end the TB on an SCTLR write, but Linux | |
5320 | * arch/arm/mach-pxa/sleep.S expects two instructions following | |
5321 | * an MMU enable to execute from cache. Imitate this behaviour. | |
5322 | */ | |
5323 | sctlr.type |= ARM_CP_SUPPRESS_TB_END; | |
5324 | } | |
5325 | define_one_arm_cp_reg(cpu, &sctlr); | |
5326 | } | |
2ceb98c0 PM |
5327 | } |
5328 | ||
14969266 AF |
5329 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) |
5330 | { | |
22169d41 | 5331 | CPUState *cs = CPU(cpu); |
14969266 AF |
5332 | CPUARMState *env = &cpu->env; |
5333 | ||
6a669427 PM |
5334 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
5335 | gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, | |
5336 | aarch64_fpu_gdb_set_reg, | |
5337 | 34, "aarch64-fpu.xml", 0); | |
5338 | } else if (arm_feature(env, ARM_FEATURE_NEON)) { | |
22169d41 | 5339 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
5340 | 51, "arm-neon.xml", 0); |
5341 | } else if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
22169d41 | 5342 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
5343 | 35, "arm-vfp3.xml", 0); |
5344 | } else if (arm_feature(env, ARM_FEATURE_VFP)) { | |
22169d41 | 5345 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
5346 | 19, "arm-vfp.xml", 0); |
5347 | } | |
40f137e1 PB |
5348 | } |
5349 | ||
777dc784 PM |
5350 | /* Sort alphabetically by type name, except for "any". */ |
5351 | static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) | |
5adb4839 | 5352 | { |
777dc784 PM |
5353 | ObjectClass *class_a = (ObjectClass *)a; |
5354 | ObjectClass *class_b = (ObjectClass *)b; | |
5355 | const char *name_a, *name_b; | |
5adb4839 | 5356 | |
777dc784 PM |
5357 | name_a = object_class_get_name(class_a); |
5358 | name_b = object_class_get_name(class_b); | |
51492fd1 | 5359 | if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 | 5360 | return 1; |
51492fd1 | 5361 | } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 PM |
5362 | return -1; |
5363 | } else { | |
5364 | return strcmp(name_a, name_b); | |
5adb4839 PB |
5365 | } |
5366 | } | |
5367 | ||
777dc784 | 5368 | static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
40f137e1 | 5369 | { |
777dc784 | 5370 | ObjectClass *oc = data; |
92a31361 | 5371 | CPUListState *s = user_data; |
51492fd1 AF |
5372 | const char *typename; |
5373 | char *name; | |
3371d272 | 5374 | |
51492fd1 AF |
5375 | typename = object_class_get_name(oc); |
5376 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
777dc784 | 5377 | (*s->cpu_fprintf)(s->file, " %s\n", |
51492fd1 AF |
5378 | name); |
5379 | g_free(name); | |
777dc784 PM |
5380 | } |
5381 | ||
5382 | void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
5383 | { | |
92a31361 | 5384 | CPUListState s = { |
777dc784 PM |
5385 | .file = f, |
5386 | .cpu_fprintf = cpu_fprintf, | |
5387 | }; | |
5388 | GSList *list; | |
5389 | ||
5390 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
5391 | list = g_slist_sort(list, arm_cpu_list_compare); | |
5392 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
5393 | g_slist_foreach(list, arm_cpu_list_entry, &s); | |
5394 | g_slist_free(list); | |
a96c0514 PM |
5395 | #ifdef CONFIG_KVM |
5396 | /* The 'host' CPU type is dynamically registered only if KVM is | |
5397 | * enabled, so we have to special-case it here: | |
5398 | */ | |
5399 | (*cpu_fprintf)(f, " host (only available in KVM mode)\n"); | |
5400 | #endif | |
40f137e1 PB |
5401 | } |
5402 | ||
78027bb6 CR |
5403 | static void arm_cpu_add_definition(gpointer data, gpointer user_data) |
5404 | { | |
5405 | ObjectClass *oc = data; | |
5406 | CpuDefinitionInfoList **cpu_list = user_data; | |
5407 | CpuDefinitionInfoList *entry; | |
5408 | CpuDefinitionInfo *info; | |
5409 | const char *typename; | |
5410 | ||
5411 | typename = object_class_get_name(oc); | |
5412 | info = g_malloc0(sizeof(*info)); | |
5413 | info->name = g_strndup(typename, | |
5414 | strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
8ed877b7 | 5415 | info->q_typename = g_strdup(typename); |
78027bb6 CR |
5416 | |
5417 | entry = g_malloc0(sizeof(*entry)); | |
5418 | entry->value = info; | |
5419 | entry->next = *cpu_list; | |
5420 | *cpu_list = entry; | |
5421 | } | |
5422 | ||
5423 | CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) | |
5424 | { | |
5425 | CpuDefinitionInfoList *cpu_list = NULL; | |
5426 | GSList *list; | |
5427 | ||
5428 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
5429 | g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); | |
5430 | g_slist_free(list); | |
5431 | ||
5432 | return cpu_list; | |
5433 | } | |
5434 | ||
6e6efd61 | 5435 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
51a79b03 | 5436 | void *opaque, int state, int secstate, |
f5a0a5a5 | 5437 | int crm, int opc1, int opc2) |
6e6efd61 PM |
5438 | { |
5439 | /* Private utility function for define_one_arm_cp_reg_with_opaque(): | |
5440 | * add a single reginfo struct to the hash table. | |
5441 | */ | |
5442 | uint32_t *key = g_new(uint32_t, 1); | |
5443 | ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); | |
5444 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | |
3f3c82a5 FA |
5445 | int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; |
5446 | ||
5447 | /* Reset the secure state to the specific incoming state. This is | |
5448 | * necessary as the register may have been defined with both states. | |
5449 | */ | |
5450 | r2->secure = secstate; | |
5451 | ||
5452 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
5453 | /* Register is banked (using both entries in array). | |
5454 | * Overwriting fieldoffset as the array is only used to define | |
5455 | * banked registers but later only fieldoffset is used. | |
f5a0a5a5 | 5456 | */ |
3f3c82a5 FA |
5457 | r2->fieldoffset = r->bank_fieldoffsets[ns]; |
5458 | } | |
5459 | ||
5460 | if (state == ARM_CP_STATE_AA32) { | |
5461 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
5462 | /* If the register is banked then we don't need to migrate or | |
5463 | * reset the 32-bit instance in certain cases: | |
5464 | * | |
5465 | * 1) If the register has both 32-bit and 64-bit instances then we | |
5466 | * can count on the 64-bit instance taking care of the | |
5467 | * non-secure bank. | |
5468 | * 2) If ARMv8 is enabled then we can count on a 64-bit version | |
5469 | * taking care of the secure bank. This requires that separate | |
5470 | * 32 and 64-bit definitions are provided. | |
5471 | */ | |
5472 | if ((r->state == ARM_CP_STATE_BOTH && ns) || | |
5473 | (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { | |
7a0e58fa | 5474 | r2->type |= ARM_CP_ALIAS; |
3f3c82a5 FA |
5475 | } |
5476 | } else if ((secstate != r->secure) && !ns) { | |
5477 | /* The register is not banked so we only want to allow migration of | |
5478 | * the non-secure instance. | |
5479 | */ | |
7a0e58fa | 5480 | r2->type |= ARM_CP_ALIAS; |
58a1d8ce | 5481 | } |
3f3c82a5 FA |
5482 | |
5483 | if (r->state == ARM_CP_STATE_BOTH) { | |
5484 | /* We assume it is a cp15 register if the .cp field is left unset. | |
5485 | */ | |
5486 | if (r2->cp == 0) { | |
5487 | r2->cp = 15; | |
5488 | } | |
5489 | ||
f5a0a5a5 | 5490 | #ifdef HOST_WORDS_BIGENDIAN |
3f3c82a5 FA |
5491 | if (r2->fieldoffset) { |
5492 | r2->fieldoffset += sizeof(uint32_t); | |
5493 | } | |
f5a0a5a5 | 5494 | #endif |
3f3c82a5 | 5495 | } |
f5a0a5a5 PM |
5496 | } |
5497 | if (state == ARM_CP_STATE_AA64) { | |
5498 | /* To allow abbreviation of ARMCPRegInfo | |
5499 | * definitions, we treat cp == 0 as equivalent to | |
5500 | * the value for "standard guest-visible sysreg". | |
58a1d8ce PM |
5501 | * STATE_BOTH definitions are also always "standard |
5502 | * sysreg" in their AArch64 view (the .cp value may | |
5503 | * be non-zero for the benefit of the AArch32 view). | |
f5a0a5a5 | 5504 | */ |
58a1d8ce | 5505 | if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { |
f5a0a5a5 PM |
5506 | r2->cp = CP_REG_ARM64_SYSREG_CP; |
5507 | } | |
5508 | *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | |
5509 | r2->opc0, opc1, opc2); | |
5510 | } else { | |
51a79b03 | 5511 | *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); |
f5a0a5a5 | 5512 | } |
6e6efd61 PM |
5513 | if (opaque) { |
5514 | r2->opaque = opaque; | |
5515 | } | |
67ed771d PM |
5516 | /* reginfo passed to helpers is correct for the actual access, |
5517 | * and is never ARM_CP_STATE_BOTH: | |
5518 | */ | |
5519 | r2->state = state; | |
6e6efd61 PM |
5520 | /* Make sure reginfo passed to helpers for wildcarded regs |
5521 | * has the correct crm/opc1/opc2 for this reg, not CP_ANY: | |
5522 | */ | |
5523 | r2->crm = crm; | |
5524 | r2->opc1 = opc1; | |
5525 | r2->opc2 = opc2; | |
5526 | /* By convention, for wildcarded registers only the first | |
5527 | * entry is used for migration; the others are marked as | |
7a0e58fa | 5528 | * ALIAS so we don't try to transfer the register |
6e6efd61 | 5529 | * multiple times. Special registers (ie NOP/WFI) are |
7a0e58fa | 5530 | * never migratable and not even raw-accessible. |
6e6efd61 | 5531 | */ |
7a0e58fa PM |
5532 | if ((r->type & ARM_CP_SPECIAL)) { |
5533 | r2->type |= ARM_CP_NO_RAW; | |
5534 | } | |
5535 | if (((r->crm == CP_ANY) && crm != 0) || | |
6e6efd61 PM |
5536 | ((r->opc1 == CP_ANY) && opc1 != 0) || |
5537 | ((r->opc2 == CP_ANY) && opc2 != 0)) { | |
7a0e58fa | 5538 | r2->type |= ARM_CP_ALIAS; |
6e6efd61 PM |
5539 | } |
5540 | ||
375421cc PM |
5541 | /* Check that raw accesses are either forbidden or handled. Note that |
5542 | * we can't assert this earlier because the setup of fieldoffset for | |
5543 | * banked registers has to be done first. | |
5544 | */ | |
5545 | if (!(r2->type & ARM_CP_NO_RAW)) { | |
5546 | assert(!raw_accessors_invalid(r2)); | |
5547 | } | |
5548 | ||
6e6efd61 PM |
5549 | /* Overriding of an existing definition must be explicitly |
5550 | * requested. | |
5551 | */ | |
5552 | if (!(r->type & ARM_CP_OVERRIDE)) { | |
5553 | ARMCPRegInfo *oldreg; | |
5554 | oldreg = g_hash_table_lookup(cpu->cp_regs, key); | |
5555 | if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { | |
5556 | fprintf(stderr, "Register redefined: cp=%d %d bit " | |
5557 | "crn=%d crm=%d opc1=%d opc2=%d, " | |
5558 | "was %s, now %s\n", r2->cp, 32 + 32 * is64, | |
5559 | r2->crn, r2->crm, r2->opc1, r2->opc2, | |
5560 | oldreg->name, r2->name); | |
5561 | g_assert_not_reached(); | |
5562 | } | |
5563 | } | |
5564 | g_hash_table_insert(cpu->cp_regs, key, r2); | |
5565 | } | |
5566 | ||
5567 | ||
4b6a83fb PM |
5568 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
5569 | const ARMCPRegInfo *r, void *opaque) | |
5570 | { | |
5571 | /* Define implementations of coprocessor registers. | |
5572 | * We store these in a hashtable because typically | |
5573 | * there are less than 150 registers in a space which | |
5574 | * is 16*16*16*8*8 = 262144 in size. | |
5575 | * Wildcarding is supported for the crm, opc1 and opc2 fields. | |
5576 | * If a register is defined twice then the second definition is | |
5577 | * used, so this can be used to define some generic registers and | |
5578 | * then override them with implementation specific variations. | |
5579 | * At least one of the original and the second definition should | |
5580 | * include ARM_CP_OVERRIDE in its type bits -- this is just a guard | |
5581 | * against accidental use. | |
f5a0a5a5 PM |
5582 | * |
5583 | * The state field defines whether the register is to be | |
5584 | * visible in the AArch32 or AArch64 execution state. If the | |
5585 | * state is set to ARM_CP_STATE_BOTH then we synthesise a | |
5586 | * reginfo structure for the AArch32 view, which sees the lower | |
5587 | * 32 bits of the 64 bit register. | |
5588 | * | |
5589 | * Only registers visible in AArch64 may set r->opc0; opc0 cannot | |
5590 | * be wildcarded. AArch64 registers are always considered to be 64 | |
5591 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | |
5592 | * the register, if any. | |
4b6a83fb | 5593 | */ |
f5a0a5a5 | 5594 | int crm, opc1, opc2, state; |
4b6a83fb PM |
5595 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
5596 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | |
5597 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | |
5598 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | |
5599 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | |
5600 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | |
5601 | /* 64 bit registers have only CRm and Opc1 fields */ | |
5602 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | |
f5a0a5a5 PM |
5603 | /* op0 only exists in the AArch64 encodings */ |
5604 | assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); | |
5605 | /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ | |
5606 | assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); | |
5607 | /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 | |
5608 | * encodes a minimum access level for the register. We roll this | |
5609 | * runtime check into our general permission check code, so check | |
5610 | * here that the reginfo's specified permissions are strict enough | |
5611 | * to encompass the generic architectural permission check. | |
5612 | */ | |
5613 | if (r->state != ARM_CP_STATE_AA32) { | |
5614 | int mask = 0; | |
5615 | switch (r->opc1) { | |
5616 | case 0: case 1: case 2: | |
5617 | /* min_EL EL1 */ | |
5618 | mask = PL1_RW; | |
5619 | break; | |
5620 | case 3: | |
5621 | /* min_EL EL0 */ | |
5622 | mask = PL0_RW; | |
5623 | break; | |
5624 | case 4: | |
5625 | /* min_EL EL2 */ | |
5626 | mask = PL2_RW; | |
5627 | break; | |
5628 | case 5: | |
5629 | /* unallocated encoding, so not possible */ | |
5630 | assert(false); | |
5631 | break; | |
5632 | case 6: | |
5633 | /* min_EL EL3 */ | |
5634 | mask = PL3_RW; | |
5635 | break; | |
5636 | case 7: | |
5637 | /* min_EL EL1, secure mode only (we don't check the latter) */ | |
5638 | mask = PL1_RW; | |
5639 | break; | |
5640 | default: | |
5641 | /* broken reginfo with out-of-range opc1 */ | |
5642 | assert(false); | |
5643 | break; | |
5644 | } | |
5645 | /* assert our permissions are not too lax (stricter is fine) */ | |
5646 | assert((r->access & ~mask) == 0); | |
5647 | } | |
5648 | ||
4b6a83fb PM |
5649 | /* Check that the register definition has enough info to handle |
5650 | * reads and writes if they are permitted. | |
5651 | */ | |
5652 | if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { | |
5653 | if (r->access & PL3_R) { | |
3f3c82a5 FA |
5654 | assert((r->fieldoffset || |
5655 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
5656 | r->readfn); | |
4b6a83fb PM |
5657 | } |
5658 | if (r->access & PL3_W) { | |
3f3c82a5 FA |
5659 | assert((r->fieldoffset || |
5660 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
5661 | r->writefn); | |
4b6a83fb PM |
5662 | } |
5663 | } | |
5664 | /* Bad type field probably means missing sentinel at end of reg list */ | |
5665 | assert(cptype_valid(r->type)); | |
5666 | for (crm = crmmin; crm <= crmmax; crm++) { | |
5667 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | |
5668 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | |
f5a0a5a5 PM |
5669 | for (state = ARM_CP_STATE_AA32; |
5670 | state <= ARM_CP_STATE_AA64; state++) { | |
5671 | if (r->state != state && r->state != ARM_CP_STATE_BOTH) { | |
5672 | continue; | |
5673 | } | |
3f3c82a5 FA |
5674 | if (state == ARM_CP_STATE_AA32) { |
5675 | /* Under AArch32 CP registers can be common | |
5676 | * (same for secure and non-secure world) or banked. | |
5677 | */ | |
5678 | switch (r->secure) { | |
5679 | case ARM_CP_SECSTATE_S: | |
5680 | case ARM_CP_SECSTATE_NS: | |
5681 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
5682 | r->secure, crm, opc1, opc2); | |
5683 | break; | |
5684 | default: | |
5685 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
5686 | ARM_CP_SECSTATE_S, | |
5687 | crm, opc1, opc2); | |
5688 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
5689 | ARM_CP_SECSTATE_NS, | |
5690 | crm, opc1, opc2); | |
5691 | break; | |
5692 | } | |
5693 | } else { | |
5694 | /* AArch64 registers get mapped to non-secure instance | |
5695 | * of AArch32 */ | |
5696 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
5697 | ARM_CP_SECSTATE_NS, | |
5698 | crm, opc1, opc2); | |
5699 | } | |
f5a0a5a5 | 5700 | } |
4b6a83fb PM |
5701 | } |
5702 | } | |
5703 | } | |
5704 | } | |
5705 | ||
5706 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
5707 | const ARMCPRegInfo *regs, void *opaque) | |
5708 | { | |
5709 | /* Define a whole list of registers */ | |
5710 | const ARMCPRegInfo *r; | |
5711 | for (r = regs; r->type != ARM_CP_SENTINEL; r++) { | |
5712 | define_one_arm_cp_reg_with_opaque(cpu, r, opaque); | |
5713 | } | |
5714 | } | |
5715 | ||
60322b39 | 5716 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) |
4b6a83fb | 5717 | { |
60322b39 | 5718 | return g_hash_table_lookup(cpregs, &encoded_cp); |
4b6a83fb PM |
5719 | } |
5720 | ||
c4241c7d PM |
5721 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
5722 | uint64_t value) | |
4b6a83fb PM |
5723 | { |
5724 | /* Helper coprocessor write function for write-ignore registers */ | |
4b6a83fb PM |
5725 | } |
5726 | ||
c4241c7d | 5727 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) |
4b6a83fb PM |
5728 | { |
5729 | /* Helper coprocessor write function for read-as-zero registers */ | |
4b6a83fb PM |
5730 | return 0; |
5731 | } | |
5732 | ||
f5a0a5a5 PM |
5733 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) |
5734 | { | |
5735 | /* Helper coprocessor reset function for do-nothing-on-reset registers */ | |
5736 | } | |
5737 | ||
af393ffc | 5738 | static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) |
37064a8b PM |
5739 | { |
5740 | /* Return true if it is not valid for us to switch to | |
5741 | * this CPU mode (ie all the UNPREDICTABLE cases in | |
5742 | * the ARM ARM CPSRWriteByInstr pseudocode). | |
5743 | */ | |
af393ffc PM |
5744 | |
5745 | /* Changes to or from Hyp via MSR and CPS are illegal. */ | |
5746 | if (write_type == CPSRWriteByInstr && | |
5747 | ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || | |
5748 | mode == ARM_CPU_MODE_HYP)) { | |
5749 | return 1; | |
5750 | } | |
5751 | ||
37064a8b PM |
5752 | switch (mode) { |
5753 | case ARM_CPU_MODE_USR: | |
10eacda7 | 5754 | return 0; |
37064a8b PM |
5755 | case ARM_CPU_MODE_SYS: |
5756 | case ARM_CPU_MODE_SVC: | |
5757 | case ARM_CPU_MODE_ABT: | |
5758 | case ARM_CPU_MODE_UND: | |
5759 | case ARM_CPU_MODE_IRQ: | |
5760 | case ARM_CPU_MODE_FIQ: | |
52ff951b PM |
5761 | /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 |
5762 | * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) | |
5763 | */ | |
10eacda7 PM |
5764 | /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR |
5765 | * and CPS are treated as illegal mode changes. | |
5766 | */ | |
5767 | if (write_type == CPSRWriteByInstr && | |
5768 | (env->cp15.hcr_el2 & HCR_TGE) && | |
5769 | (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && | |
5770 | !arm_is_secure_below_el3(env)) { | |
5771 | return 1; | |
5772 | } | |
37064a8b | 5773 | return 0; |
e6c8fc07 PM |
5774 | case ARM_CPU_MODE_HYP: |
5775 | return !arm_feature(env, ARM_FEATURE_EL2) | |
5776 | || arm_current_el(env) < 2 || arm_is_secure(env); | |
027fc527 | 5777 | case ARM_CPU_MODE_MON: |
58ae2d1f | 5778 | return arm_current_el(env) < 3; |
37064a8b PM |
5779 | default: |
5780 | return 1; | |
5781 | } | |
5782 | } | |
5783 | ||
2f4a40e5 AZ |
5784 | uint32_t cpsr_read(CPUARMState *env) |
5785 | { | |
5786 | int ZF; | |
6fbe23d5 PB |
5787 | ZF = (env->ZF == 0); |
5788 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
5789 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
5790 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
5791 | | ((env->condexec_bits & 0xfc) << 8) | |
af519934 | 5792 | | (env->GE << 16) | (env->daif & CPSR_AIF); |
2f4a40e5 AZ |
5793 | } |
5794 | ||
50866ba5 PM |
5795 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, |
5796 | CPSRWriteType write_type) | |
2f4a40e5 | 5797 | { |
6e8801f9 FA |
5798 | uint32_t changed_daif; |
5799 | ||
2f4a40e5 | 5800 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
5801 | env->ZF = (~val) & CPSR_Z; |
5802 | env->NF = val; | |
2f4a40e5 AZ |
5803 | env->CF = (val >> 29) & 1; |
5804 | env->VF = (val << 3) & 0x80000000; | |
5805 | } | |
5806 | if (mask & CPSR_Q) | |
5807 | env->QF = ((val & CPSR_Q) != 0); | |
5808 | if (mask & CPSR_T) | |
5809 | env->thumb = ((val & CPSR_T) != 0); | |
5810 | if (mask & CPSR_IT_0_1) { | |
5811 | env->condexec_bits &= ~3; | |
5812 | env->condexec_bits |= (val >> 25) & 3; | |
5813 | } | |
5814 | if (mask & CPSR_IT_2_7) { | |
5815 | env->condexec_bits &= 3; | |
5816 | env->condexec_bits |= (val >> 8) & 0xfc; | |
5817 | } | |
5818 | if (mask & CPSR_GE) { | |
5819 | env->GE = (val >> 16) & 0xf; | |
5820 | } | |
5821 | ||
6e8801f9 FA |
5822 | /* In a V7 implementation that includes the security extensions but does |
5823 | * not include Virtualization Extensions the SCR.FW and SCR.AW bits control | |
5824 | * whether non-secure software is allowed to change the CPSR_F and CPSR_A | |
5825 | * bits respectively. | |
5826 | * | |
5827 | * In a V8 implementation, it is permitted for privileged software to | |
5828 | * change the CPSR A/F bits regardless of the SCR.AW/FW bits. | |
5829 | */ | |
f8c88bbc | 5830 | if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && |
6e8801f9 FA |
5831 | arm_feature(env, ARM_FEATURE_EL3) && |
5832 | !arm_feature(env, ARM_FEATURE_EL2) && | |
5833 | !arm_is_secure(env)) { | |
5834 | ||
5835 | changed_daif = (env->daif ^ val) & mask; | |
5836 | ||
5837 | if (changed_daif & CPSR_A) { | |
5838 | /* Check to see if we are allowed to change the masking of async | |
5839 | * abort exceptions from a non-secure state. | |
5840 | */ | |
5841 | if (!(env->cp15.scr_el3 & SCR_AW)) { | |
5842 | qemu_log_mask(LOG_GUEST_ERROR, | |
5843 | "Ignoring attempt to switch CPSR_A flag from " | |
5844 | "non-secure world with SCR.AW bit clear\n"); | |
5845 | mask &= ~CPSR_A; | |
5846 | } | |
5847 | } | |
5848 | ||
5849 | if (changed_daif & CPSR_F) { | |
5850 | /* Check to see if we are allowed to change the masking of FIQ | |
5851 | * exceptions from a non-secure state. | |
5852 | */ | |
5853 | if (!(env->cp15.scr_el3 & SCR_FW)) { | |
5854 | qemu_log_mask(LOG_GUEST_ERROR, | |
5855 | "Ignoring attempt to switch CPSR_F flag from " | |
5856 | "non-secure world with SCR.FW bit clear\n"); | |
5857 | mask &= ~CPSR_F; | |
5858 | } | |
5859 | ||
5860 | /* Check whether non-maskable FIQ (NMFI) support is enabled. | |
5861 | * If this bit is set software is not allowed to mask | |
5862 | * FIQs, but is allowed to set CPSR_F to 0. | |
5863 | */ | |
5864 | if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && | |
5865 | (val & CPSR_F)) { | |
5866 | qemu_log_mask(LOG_GUEST_ERROR, | |
5867 | "Ignoring attempt to enable CPSR_F flag " | |
5868 | "(non-maskable FIQ [NMFI] support enabled)\n"); | |
5869 | mask &= ~CPSR_F; | |
5870 | } | |
5871 | } | |
5872 | } | |
5873 | ||
4cc35614 PM |
5874 | env->daif &= ~(CPSR_AIF & mask); |
5875 | env->daif |= val & CPSR_AIF & mask; | |
5876 | ||
f8c88bbc PM |
5877 | if (write_type != CPSRWriteRaw && |
5878 | ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { | |
8c4f0eb9 PM |
5879 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { |
5880 | /* Note that we can only get here in USR mode if this is a | |
5881 | * gdb stub write; for this case we follow the architectural | |
5882 | * behaviour for guest writes in USR mode of ignoring an attempt | |
5883 | * to switch mode. (Those are caught by translate.c for writes | |
5884 | * triggered by guest instructions.) | |
5885 | */ | |
5886 | mask &= ~CPSR_M; | |
5887 | } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { | |
81907a58 PM |
5888 | /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in |
5889 | * v7, and has defined behaviour in v8: | |
5890 | * + leave CPSR.M untouched | |
5891 | * + allow changes to the other CPSR fields | |
5892 | * + set PSTATE.IL | |
5893 | * For user changes via the GDB stub, we don't set PSTATE.IL, | |
5894 | * as this would be unnecessarily harsh for a user error. | |
37064a8b PM |
5895 | */ |
5896 | mask &= ~CPSR_M; | |
81907a58 PM |
5897 | if (write_type != CPSRWriteByGDBStub && |
5898 | arm_feature(env, ARM_FEATURE_V8)) { | |
5899 | mask |= CPSR_IL; | |
5900 | val |= CPSR_IL; | |
5901 | } | |
37064a8b PM |
5902 | } else { |
5903 | switch_mode(env, val & CPSR_M); | |
5904 | } | |
2f4a40e5 AZ |
5905 | } |
5906 | mask &= ~CACHED_CPSR_BITS; | |
5907 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
5908 | } | |
5909 | ||
b26eefb6 PB |
5910 | /* Sign/zero extend */ |
5911 | uint32_t HELPER(sxtb16)(uint32_t x) | |
5912 | { | |
5913 | uint32_t res; | |
5914 | res = (uint16_t)(int8_t)x; | |
5915 | res |= (uint32_t)(int8_t)(x >> 16) << 16; | |
5916 | return res; | |
5917 | } | |
5918 | ||
5919 | uint32_t HELPER(uxtb16)(uint32_t x) | |
5920 | { | |
5921 | uint32_t res; | |
5922 | res = (uint16_t)(uint8_t)x; | |
5923 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; | |
5924 | return res; | |
5925 | } | |
5926 | ||
3670669c PB |
5927 | int32_t HELPER(sdiv)(int32_t num, int32_t den) |
5928 | { | |
5929 | if (den == 0) | |
5930 | return 0; | |
686eeb93 AJ |
5931 | if (num == INT_MIN && den == -1) |
5932 | return INT_MIN; | |
3670669c PB |
5933 | return num / den; |
5934 | } | |
5935 | ||
5936 | uint32_t HELPER(udiv)(uint32_t num, uint32_t den) | |
5937 | { | |
5938 | if (den == 0) | |
5939 | return 0; | |
5940 | return num / den; | |
5941 | } | |
5942 | ||
5943 | uint32_t HELPER(rbit)(uint32_t x) | |
5944 | { | |
42fedbca | 5945 | return revbit32(x); |
3670669c PB |
5946 | } |
5947 | ||
5fafdf24 | 5948 | #if defined(CONFIG_USER_ONLY) |
b5ff1b31 | 5949 | |
9ee6e8bb | 5950 | /* These should probably raise undefined insn exceptions. */ |
0ecb72a5 | 5951 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) |
9ee6e8bb | 5952 | { |
a47dddd7 AF |
5953 | ARMCPU *cpu = arm_env_get_cpu(env); |
5954 | ||
5955 | cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); | |
9ee6e8bb PB |
5956 | } |
5957 | ||
0ecb72a5 | 5958 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb | 5959 | { |
a47dddd7 AF |
5960 | ARMCPU *cpu = arm_env_get_cpu(env); |
5961 | ||
5962 | cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); | |
9ee6e8bb PB |
5963 | return 0; |
5964 | } | |
5965 | ||
fb602cb7 PM |
5966 | void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) |
5967 | { | |
5968 | /* translate.c should never generate calls here in user-only mode */ | |
5969 | g_assert_not_reached(); | |
5970 | } | |
5971 | ||
3e3fa230 PM |
5972 | void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) |
5973 | { | |
5974 | /* translate.c should never generate calls here in user-only mode */ | |
5975 | g_assert_not_reached(); | |
5976 | } | |
5977 | ||
5158de24 PM |
5978 | uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) |
5979 | { | |
5980 | /* The TT instructions can be used by unprivileged code, but in | |
5981 | * user-only emulation we don't have the MPU. | |
5982 | * Luckily since we know we are NonSecure unprivileged (and that in | |
5983 | * turn means that the A flag wasn't specified), all the bits in the | |
5984 | * register must be zero: | |
5985 | * IREGION: 0 because IRVALID is 0 | |
5986 | * IRVALID: 0 because NS | |
5987 | * S: 0 because NS | |
5988 | * NSRW: 0 because NS | |
5989 | * NSR: 0 because NS | |
5990 | * RW: 0 because unpriv and A flag not set | |
5991 | * R: 0 because unpriv and A flag not set | |
5992 | * SRVALID: 0 because NS | |
5993 | * MRVALID: 0 because unpriv and A flag not set | |
5994 | * SREGION: 0 becaus SRVALID is 0 | |
5995 | * MREGION: 0 because MRVALID is 0 | |
5996 | */ | |
5997 | return 0; | |
5998 | } | |
5999 | ||
0ecb72a5 | 6000 | void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 | 6001 | { |
a47dddd7 AF |
6002 | ARMCPU *cpu = arm_env_get_cpu(env); |
6003 | ||
6004 | if (mode != ARM_CPU_MODE_USR) { | |
6005 | cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); | |
6006 | } | |
b5ff1b31 FB |
6007 | } |
6008 | ||
012a906b GB |
6009 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
6010 | uint32_t cur_el, bool secure) | |
9e729b57 EI |
6011 | { |
6012 | return 1; | |
6013 | } | |
6014 | ||
ce02049d GB |
6015 | void aarch64_sync_64_to_32(CPUARMState *env) |
6016 | { | |
6017 | g_assert_not_reached(); | |
6018 | } | |
6019 | ||
b5ff1b31 FB |
6020 | #else |
6021 | ||
0ecb72a5 | 6022 | void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
6023 | { |
6024 | int old_mode; | |
6025 | int i; | |
6026 | ||
6027 | old_mode = env->uncached_cpsr & CPSR_M; | |
6028 | if (mode == old_mode) | |
6029 | return; | |
6030 | ||
6031 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
6032 | memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 6033 | memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
6034 | } else if (mode == ARM_CPU_MODE_FIQ) { |
6035 | memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 6036 | memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
6037 | } |
6038 | ||
f5206413 | 6039 | i = bank_number(old_mode); |
b5ff1b31 FB |
6040 | env->banked_r13[i] = env->regs[13]; |
6041 | env->banked_r14[i] = env->regs[14]; | |
6042 | env->banked_spsr[i] = env->spsr; | |
6043 | ||
f5206413 | 6044 | i = bank_number(mode); |
b5ff1b31 FB |
6045 | env->regs[13] = env->banked_r13[i]; |
6046 | env->regs[14] = env->banked_r14[i]; | |
6047 | env->spsr = env->banked_spsr[i]; | |
6048 | } | |
6049 | ||
0eeb17d6 GB |
6050 | /* Physical Interrupt Target EL Lookup Table |
6051 | * | |
6052 | * [ From ARM ARM section G1.13.4 (Table G1-15) ] | |
6053 | * | |
6054 | * The below multi-dimensional table is used for looking up the target | |
6055 | * exception level given numerous condition criteria. Specifically, the | |
6056 | * target EL is based on SCR and HCR routing controls as well as the | |
6057 | * currently executing EL and secure state. | |
6058 | * | |
6059 | * Dimensions: | |
6060 | * target_el_table[2][2][2][2][2][4] | |
6061 | * | | | | | +--- Current EL | |
6062 | * | | | | +------ Non-secure(0)/Secure(1) | |
6063 | * | | | +--------- HCR mask override | |
6064 | * | | +------------ SCR exec state control | |
6065 | * | +--------------- SCR mask override | |
6066 | * +------------------ 32-bit(0)/64-bit(1) EL3 | |
6067 | * | |
6068 | * The table values are as such: | |
6069 | * 0-3 = EL0-EL3 | |
6070 | * -1 = Cannot occur | |
6071 | * | |
6072 | * The ARM ARM target EL table includes entries indicating that an "exception | |
6073 | * is not taken". The two cases where this is applicable are: | |
6074 | * 1) An exception is taken from EL3 but the SCR does not have the exception | |
6075 | * routed to EL3. | |
6076 | * 2) An exception is taken from EL2 but the HCR does not have the exception | |
6077 | * routed to EL2. | |
6078 | * In these two cases, the below table contain a target of EL1. This value is | |
6079 | * returned as it is expected that the consumer of the table data will check | |
6080 | * for "target EL >= current EL" to ensure the exception is not taken. | |
6081 | * | |
6082 | * SCR HCR | |
6083 | * 64 EA AMO From | |
6084 | * BIT IRQ IMO Non-secure Secure | |
6085 | * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 | |
6086 | */ | |
82c39f6a | 6087 | static const int8_t target_el_table[2][2][2][2][2][4] = { |
0eeb17d6 GB |
6088 | {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, |
6089 | {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, | |
6090 | {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, | |
6091 | {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, | |
6092 | {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
6093 | {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, | |
6094 | {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
6095 | {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, | |
6096 | {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, | |
6097 | {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},}, | |
6098 | {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },}, | |
6099 | {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},}, | |
6100 | {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, | |
6101 | {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, | |
6102 | {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, | |
6103 | {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},}, | |
6104 | }; | |
6105 | ||
6106 | /* | |
6107 | * Determine the target EL for physical exceptions | |
6108 | */ | |
012a906b GB |
6109 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
6110 | uint32_t cur_el, bool secure) | |
0eeb17d6 GB |
6111 | { |
6112 | CPUARMState *env = cs->env_ptr; | |
2cde031f | 6113 | int rw; |
0eeb17d6 GB |
6114 | int scr; |
6115 | int hcr; | |
6116 | int target_el; | |
2cde031f SS |
6117 | /* Is the highest EL AArch64? */ |
6118 | int is64 = arm_feature(env, ARM_FEATURE_AARCH64); | |
6119 | ||
6120 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
6121 | rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); | |
6122 | } else { | |
6123 | /* Either EL2 is the highest EL (and so the EL2 register width | |
6124 | * is given by is64); or there is no EL2 or EL3, in which case | |
6125 | * the value of 'rw' does not affect the table lookup anyway. | |
6126 | */ | |
6127 | rw = is64; | |
6128 | } | |
0eeb17d6 GB |
6129 | |
6130 | switch (excp_idx) { | |
6131 | case EXCP_IRQ: | |
6132 | scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); | |
6133 | hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO); | |
6134 | break; | |
6135 | case EXCP_FIQ: | |
6136 | scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); | |
6137 | hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO); | |
6138 | break; | |
6139 | default: | |
6140 | scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); | |
6141 | hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO); | |
6142 | break; | |
6143 | }; | |
6144 | ||
6145 | /* If HCR.TGE is set then HCR is treated as being 1 */ | |
6146 | hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE); | |
6147 | ||
6148 | /* Perform a table-lookup for the target EL given the current state */ | |
6149 | target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; | |
6150 | ||
6151 | assert(target_el > 0); | |
6152 | ||
6153 | return target_el; | |
6154 | } | |
6155 | ||
9ee6e8bb PB |
6156 | static void v7m_push(CPUARMState *env, uint32_t val) |
6157 | { | |
70d74660 AF |
6158 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
6159 | ||
9ee6e8bb | 6160 | env->regs[13] -= 4; |
ab1da857 | 6161 | stl_phys(cs->as, env->regs[13], val); |
9ee6e8bb PB |
6162 | } |
6163 | ||
fb602cb7 PM |
6164 | /* Return true if we're using the process stack pointer (not the MSP) */ |
6165 | static bool v7m_using_psp(CPUARMState *env) | |
6166 | { | |
6167 | /* Handler mode always uses the main stack; for thread mode | |
6168 | * the CONTROL.SPSEL bit determines the answer. | |
6169 | * Note that in v7M it is not possible to be in Handler mode with | |
6170 | * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both. | |
6171 | */ | |
6172 | return !arm_v7m_is_handler_mode(env) && | |
6173 | env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; | |
6174 | } | |
6175 | ||
3f0cddee PM |
6176 | /* Write to v7M CONTROL.SPSEL bit for the specified security bank. |
6177 | * This may change the current stack pointer between Main and Process | |
6178 | * stack pointers if it is done for the CONTROL register for the current | |
6179 | * security state. | |
de2db7ec | 6180 | */ |
3f0cddee PM |
6181 | static void write_v7m_control_spsel_for_secstate(CPUARMState *env, |
6182 | bool new_spsel, | |
6183 | bool secstate) | |
9ee6e8bb | 6184 | { |
3f0cddee | 6185 | bool old_is_psp = v7m_using_psp(env); |
de2db7ec | 6186 | |
3f0cddee PM |
6187 | env->v7m.control[secstate] = |
6188 | deposit32(env->v7m.control[secstate], | |
de2db7ec PM |
6189 | R_V7M_CONTROL_SPSEL_SHIFT, |
6190 | R_V7M_CONTROL_SPSEL_LENGTH, new_spsel); | |
6191 | ||
3f0cddee PM |
6192 | if (secstate == env->v7m.secure) { |
6193 | bool new_is_psp = v7m_using_psp(env); | |
6194 | uint32_t tmp; | |
abc24d86 | 6195 | |
3f0cddee PM |
6196 | if (old_is_psp != new_is_psp) { |
6197 | tmp = env->v7m.other_sp; | |
6198 | env->v7m.other_sp = env->regs[13]; | |
6199 | env->regs[13] = tmp; | |
6200 | } | |
de2db7ec PM |
6201 | } |
6202 | } | |
6203 | ||
3f0cddee PM |
6204 | /* Write to v7M CONTROL.SPSEL bit. This may change the current |
6205 | * stack pointer between Main and Process stack pointers. | |
6206 | */ | |
6207 | static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel) | |
6208 | { | |
6209 | write_v7m_control_spsel_for_secstate(env, new_spsel, env->v7m.secure); | |
6210 | } | |
6211 | ||
de2db7ec PM |
6212 | void write_v7m_exception(CPUARMState *env, uint32_t new_exc) |
6213 | { | |
6214 | /* Write a new value to v7m.exception, thus transitioning into or out | |
6215 | * of Handler mode; this may result in a change of active stack pointer. | |
6216 | */ | |
6217 | bool new_is_psp, old_is_psp = v7m_using_psp(env); | |
6218 | uint32_t tmp; | |
abc24d86 | 6219 | |
de2db7ec PM |
6220 | env->v7m.exception = new_exc; |
6221 | ||
6222 | new_is_psp = v7m_using_psp(env); | |
6223 | ||
6224 | if (old_is_psp != new_is_psp) { | |
6225 | tmp = env->v7m.other_sp; | |
6226 | env->v7m.other_sp = env->regs[13]; | |
6227 | env->regs[13] = tmp; | |
9ee6e8bb PB |
6228 | } |
6229 | } | |
6230 | ||
fb602cb7 PM |
6231 | /* Switch M profile security state between NS and S */ |
6232 | static void switch_v7m_security_state(CPUARMState *env, bool new_secstate) | |
6233 | { | |
6234 | uint32_t new_ss_msp, new_ss_psp; | |
6235 | ||
6236 | if (env->v7m.secure == new_secstate) { | |
6237 | return; | |
6238 | } | |
6239 | ||
6240 | /* All the banked state is accessed by looking at env->v7m.secure | |
6241 | * except for the stack pointer; rearrange the SP appropriately. | |
6242 | */ | |
6243 | new_ss_msp = env->v7m.other_ss_msp; | |
6244 | new_ss_psp = env->v7m.other_ss_psp; | |
6245 | ||
6246 | if (v7m_using_psp(env)) { | |
6247 | env->v7m.other_ss_psp = env->regs[13]; | |
6248 | env->v7m.other_ss_msp = env->v7m.other_sp; | |
6249 | } else { | |
6250 | env->v7m.other_ss_msp = env->regs[13]; | |
6251 | env->v7m.other_ss_psp = env->v7m.other_sp; | |
6252 | } | |
6253 | ||
6254 | env->v7m.secure = new_secstate; | |
6255 | ||
6256 | if (v7m_using_psp(env)) { | |
6257 | env->regs[13] = new_ss_psp; | |
6258 | env->v7m.other_sp = new_ss_msp; | |
6259 | } else { | |
6260 | env->regs[13] = new_ss_msp; | |
6261 | env->v7m.other_sp = new_ss_psp; | |
6262 | } | |
6263 | } | |
6264 | ||
6265 | void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) | |
6266 | { | |
6267 | /* Handle v7M BXNS: | |
6268 | * - if the return value is a magic value, do exception return (like BX) | |
6269 | * - otherwise bit 0 of the return value is the target security state | |
6270 | */ | |
d02a8698 PM |
6271 | uint32_t min_magic; |
6272 | ||
6273 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
6274 | /* Covers FNC_RETURN and EXC_RETURN magic */ | |
6275 | min_magic = FNC_RETURN_MIN_MAGIC; | |
6276 | } else { | |
6277 | /* EXC_RETURN magic only */ | |
6278 | min_magic = EXC_RETURN_MIN_MAGIC; | |
6279 | } | |
6280 | ||
6281 | if (dest >= min_magic) { | |
fb602cb7 PM |
6282 | /* This is an exception return magic value; put it where |
6283 | * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT. | |
6284 | * Note that if we ever add gen_ss_advance() singlestep support to | |
6285 | * M profile this should count as an "instruction execution complete" | |
6286 | * event (compare gen_bx_excret_final_code()). | |
6287 | */ | |
6288 | env->regs[15] = dest & ~1; | |
6289 | env->thumb = dest & 1; | |
6290 | HELPER(exception_internal)(env, EXCP_EXCEPTION_EXIT); | |
6291 | /* notreached */ | |
6292 | } | |
6293 | ||
6294 | /* translate.c should have made BXNS UNDEF unless we're secure */ | |
6295 | assert(env->v7m.secure); | |
6296 | ||
6297 | switch_v7m_security_state(env, dest & 1); | |
6298 | env->thumb = 1; | |
6299 | env->regs[15] = dest & ~1; | |
6300 | } | |
6301 | ||
3e3fa230 PM |
6302 | void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) |
6303 | { | |
6304 | /* Handle v7M BLXNS: | |
6305 | * - bit 0 of the destination address is the target security state | |
6306 | */ | |
6307 | ||
6308 | /* At this point regs[15] is the address just after the BLXNS */ | |
6309 | uint32_t nextinst = env->regs[15] | 1; | |
6310 | uint32_t sp = env->regs[13] - 8; | |
6311 | uint32_t saved_psr; | |
6312 | ||
6313 | /* translate.c will have made BLXNS UNDEF unless we're secure */ | |
6314 | assert(env->v7m.secure); | |
6315 | ||
6316 | if (dest & 1) { | |
6317 | /* target is Secure, so this is just a normal BLX, | |
6318 | * except that the low bit doesn't indicate Thumb/not. | |
6319 | */ | |
6320 | env->regs[14] = nextinst; | |
6321 | env->thumb = 1; | |
6322 | env->regs[15] = dest & ~1; | |
6323 | return; | |
6324 | } | |
6325 | ||
6326 | /* Target is non-secure: first push a stack frame */ | |
6327 | if (!QEMU_IS_ALIGNED(sp, 8)) { | |
6328 | qemu_log_mask(LOG_GUEST_ERROR, | |
6329 | "BLXNS with misaligned SP is UNPREDICTABLE\n"); | |
6330 | } | |
6331 | ||
6332 | saved_psr = env->v7m.exception; | |
6333 | if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK) { | |
6334 | saved_psr |= XPSR_SFPA; | |
6335 | } | |
6336 | ||
6337 | /* Note that these stores can throw exceptions on MPU faults */ | |
6338 | cpu_stl_data(env, sp, nextinst); | |
6339 | cpu_stl_data(env, sp + 4, saved_psr); | |
6340 | ||
6341 | env->regs[13] = sp; | |
6342 | env->regs[14] = 0xfeffffff; | |
6343 | if (arm_v7m_is_handler_mode(env)) { | |
6344 | /* Write a dummy value to IPSR, to avoid leaking the current secure | |
6345 | * exception number to non-secure code. This is guaranteed not | |
6346 | * to cause write_v7m_exception() to actually change stacks. | |
6347 | */ | |
6348 | write_v7m_exception(env, 1); | |
6349 | } | |
6350 | switch_v7m_security_state(env, 0); | |
6351 | env->thumb = 1; | |
6352 | env->regs[15] = dest; | |
6353 | } | |
6354 | ||
5b522399 PM |
6355 | static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode, |
6356 | bool spsel) | |
6357 | { | |
6358 | /* Return a pointer to the location where we currently store the | |
6359 | * stack pointer for the requested security state and thread mode. | |
6360 | * This pointer will become invalid if the CPU state is updated | |
6361 | * such that the stack pointers are switched around (eg changing | |
6362 | * the SPSEL control bit). | |
6363 | * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode(). | |
6364 | * Unlike that pseudocode, we require the caller to pass us in the | |
6365 | * SPSEL control bit value; this is because we also use this | |
6366 | * function in handling of pushing of the callee-saves registers | |
6367 | * part of the v8M stack frame (pseudocode PushCalleeStack()), | |
6368 | * and in the tailchain codepath the SPSEL bit comes from the exception | |
6369 | * return magic LR value from the previous exception. The pseudocode | |
6370 | * opencodes the stack-selection in PushCalleeStack(), but we prefer | |
6371 | * to make this utility function generic enough to do the job. | |
6372 | */ | |
6373 | bool want_psp = threadmode && spsel; | |
6374 | ||
6375 | if (secure == env->v7m.secure) { | |
de2db7ec PM |
6376 | if (want_psp == v7m_using_psp(env)) { |
6377 | return &env->regs[13]; | |
6378 | } else { | |
6379 | return &env->v7m.other_sp; | |
6380 | } | |
5b522399 PM |
6381 | } else { |
6382 | if (want_psp) { | |
6383 | return &env->v7m.other_ss_psp; | |
6384 | } else { | |
6385 | return &env->v7m.other_ss_msp; | |
6386 | } | |
6387 | } | |
6388 | } | |
6389 | ||
d3392718 | 6390 | static uint32_t arm_v7m_load_vector(ARMCPU *cpu, bool targets_secure) |
39ae2474 PM |
6391 | { |
6392 | CPUState *cs = CPU(cpu); | |
6393 | CPUARMState *env = &cpu->env; | |
6394 | MemTxResult result; | |
d3392718 | 6395 | hwaddr vec = env->v7m.vecbase[targets_secure] + env->v7m.exception * 4; |
39ae2474 PM |
6396 | uint32_t addr; |
6397 | ||
6398 | addr = address_space_ldl(cs->as, vec, | |
6399 | MEMTXATTRS_UNSPECIFIED, &result); | |
6400 | if (result != MEMTX_OK) { | |
6401 | /* Architecturally this should cause a HardFault setting HSFR.VECTTBL, | |
6402 | * which would then be immediately followed by our failing to load | |
6403 | * the entry vector for that HardFault, which is a Lockup case. | |
6404 | * Since we don't model Lockup, we just report this guest error | |
6405 | * via cpu_abort(). | |
6406 | */ | |
d3392718 PM |
6407 | cpu_abort(cs, "Failed to read from %s exception vector table " |
6408 | "entry %08x\n", targets_secure ? "secure" : "nonsecure", | |
6409 | (unsigned)vec); | |
39ae2474 PM |
6410 | } |
6411 | return addr; | |
6412 | } | |
6413 | ||
d3392718 PM |
6414 | static void v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain) |
6415 | { | |
6416 | /* For v8M, push the callee-saves register part of the stack frame. | |
6417 | * Compare the v8M pseudocode PushCalleeStack(). | |
6418 | * In the tailchaining case this may not be the current stack. | |
6419 | */ | |
6420 | CPUARMState *env = &cpu->env; | |
6421 | CPUState *cs = CPU(cpu); | |
6422 | uint32_t *frame_sp_p; | |
6423 | uint32_t frameptr; | |
6424 | ||
6425 | if (dotailchain) { | |
6426 | frame_sp_p = get_v7m_sp_ptr(env, true, | |
6427 | lr & R_V7M_EXCRET_MODE_MASK, | |
6428 | lr & R_V7M_EXCRET_SPSEL_MASK); | |
6429 | } else { | |
6430 | frame_sp_p = &env->regs[13]; | |
6431 | } | |
6432 | ||
6433 | frameptr = *frame_sp_p - 0x28; | |
6434 | ||
6435 | stl_phys(cs->as, frameptr, 0xfefa125b); | |
6436 | stl_phys(cs->as, frameptr + 0x8, env->regs[4]); | |
6437 | stl_phys(cs->as, frameptr + 0xc, env->regs[5]); | |
6438 | stl_phys(cs->as, frameptr + 0x10, env->regs[6]); | |
6439 | stl_phys(cs->as, frameptr + 0x14, env->regs[7]); | |
6440 | stl_phys(cs->as, frameptr + 0x18, env->regs[8]); | |
6441 | stl_phys(cs->as, frameptr + 0x1c, env->regs[9]); | |
6442 | stl_phys(cs->as, frameptr + 0x20, env->regs[10]); | |
6443 | stl_phys(cs->as, frameptr + 0x24, env->regs[11]); | |
6444 | ||
6445 | *frame_sp_p = frameptr; | |
6446 | } | |
6447 | ||
6448 | static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain) | |
39ae2474 PM |
6449 | { |
6450 | /* Do the "take the exception" parts of exception entry, | |
6451 | * but not the pushing of state to the stack. This is | |
6452 | * similar to the pseudocode ExceptionTaken() function. | |
6453 | */ | |
6454 | CPUARMState *env = &cpu->env; | |
6455 | uint32_t addr; | |
d3392718 PM |
6456 | bool targets_secure; |
6457 | ||
6458 | targets_secure = armv7m_nvic_acknowledge_irq(env->nvic); | |
6459 | ||
6460 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
6461 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && | |
6462 | (lr & R_V7M_EXCRET_S_MASK)) { | |
6463 | /* The background code (the owner of the registers in the | |
6464 | * exception frame) is Secure. This means it may either already | |
6465 | * have or now needs to push callee-saves registers. | |
6466 | */ | |
6467 | if (targets_secure) { | |
6468 | if (dotailchain && !(lr & R_V7M_EXCRET_ES_MASK)) { | |
6469 | /* We took an exception from Secure to NonSecure | |
6470 | * (which means the callee-saved registers got stacked) | |
6471 | * and are now tailchaining to a Secure exception. | |
6472 | * Clear DCRS so eventual return from this Secure | |
6473 | * exception unstacks the callee-saved registers. | |
6474 | */ | |
6475 | lr &= ~R_V7M_EXCRET_DCRS_MASK; | |
6476 | } | |
6477 | } else { | |
6478 | /* We're going to a non-secure exception; push the | |
6479 | * callee-saves registers to the stack now, if they're | |
6480 | * not already saved. | |
6481 | */ | |
6482 | if (lr & R_V7M_EXCRET_DCRS_MASK && | |
6483 | !(dotailchain && (lr & R_V7M_EXCRET_ES_MASK))) { | |
6484 | v7m_push_callee_stack(cpu, lr, dotailchain); | |
6485 | } | |
6486 | lr |= R_V7M_EXCRET_DCRS_MASK; | |
6487 | } | |
6488 | } | |
6489 | ||
6490 | lr &= ~R_V7M_EXCRET_ES_MASK; | |
6491 | if (targets_secure || !arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
6492 | lr |= R_V7M_EXCRET_ES_MASK; | |
6493 | } | |
6494 | lr &= ~R_V7M_EXCRET_SPSEL_MASK; | |
6495 | if (env->v7m.control[targets_secure] & R_V7M_CONTROL_SPSEL_MASK) { | |
6496 | lr |= R_V7M_EXCRET_SPSEL_MASK; | |
6497 | } | |
6498 | ||
6499 | /* Clear registers if necessary to prevent non-secure exception | |
6500 | * code being able to see register values from secure code. | |
6501 | * Where register values become architecturally UNKNOWN we leave | |
6502 | * them with their previous values. | |
6503 | */ | |
6504 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
6505 | if (!targets_secure) { | |
6506 | /* Always clear the caller-saved registers (they have been | |
6507 | * pushed to the stack earlier in v7m_push_stack()). | |
6508 | * Clear callee-saved registers if the background code is | |
6509 | * Secure (in which case these regs were saved in | |
6510 | * v7m_push_callee_stack()). | |
6511 | */ | |
6512 | int i; | |
6513 | ||
6514 | for (i = 0; i < 13; i++) { | |
6515 | /* r4..r11 are callee-saves, zero only if EXCRET.S == 1 */ | |
6516 | if (i < 4 || i > 11 || (lr & R_V7M_EXCRET_S_MASK)) { | |
6517 | env->regs[i] = 0; | |
6518 | } | |
6519 | } | |
6520 | /* Clear EAPSR */ | |
6521 | xpsr_write(env, 0, XPSR_NZCV | XPSR_Q | XPSR_GE | XPSR_IT); | |
6522 | } | |
6523 | } | |
6524 | } | |
39ae2474 | 6525 | |
d3392718 PM |
6526 | /* Switch to target security state -- must do this before writing SPSEL */ |
6527 | switch_v7m_security_state(env, targets_secure); | |
de2db7ec | 6528 | write_v7m_control_spsel(env, 0); |
dc3c4c14 | 6529 | arm_clear_exclusive(env); |
39ae2474 PM |
6530 | /* Clear IT bits */ |
6531 | env->condexec_bits = 0; | |
6532 | env->regs[14] = lr; | |
d3392718 | 6533 | addr = arm_v7m_load_vector(cpu, targets_secure); |
39ae2474 PM |
6534 | env->regs[15] = addr & 0xfffffffe; |
6535 | env->thumb = addr & 1; | |
6536 | } | |
6537 | ||
6538 | static void v7m_push_stack(ARMCPU *cpu) | |
6539 | { | |
6540 | /* Do the "set up stack frame" part of exception entry, | |
6541 | * similar to pseudocode PushStack(). | |
6542 | */ | |
6543 | CPUARMState *env = &cpu->env; | |
6544 | uint32_t xpsr = xpsr_read(env); | |
6545 | ||
6546 | /* Align stack pointer if the guest wants that */ | |
9d40cd8a PM |
6547 | if ((env->regs[13] & 4) && |
6548 | (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKALIGN_MASK)) { | |
39ae2474 | 6549 | env->regs[13] -= 4; |
987ab45e | 6550 | xpsr |= XPSR_SPREALIGN; |
39ae2474 PM |
6551 | } |
6552 | /* Switch to the handler mode. */ | |
6553 | v7m_push(env, xpsr); | |
6554 | v7m_push(env, env->regs[15]); | |
6555 | v7m_push(env, env->regs[14]); | |
6556 | v7m_push(env, env->regs[12]); | |
6557 | v7m_push(env, env->regs[3]); | |
6558 | v7m_push(env, env->regs[2]); | |
6559 | v7m_push(env, env->regs[1]); | |
6560 | v7m_push(env, env->regs[0]); | |
6561 | } | |
6562 | ||
aa488fe3 | 6563 | static void do_v7m_exception_exit(ARMCPU *cpu) |
9ee6e8bb | 6564 | { |
aa488fe3 | 6565 | CPUARMState *env = &cpu->env; |
5b522399 | 6566 | CPUState *cs = CPU(cpu); |
351e527a | 6567 | uint32_t excret; |
9ee6e8bb | 6568 | uint32_t xpsr; |
aa488fe3 | 6569 | bool ufault = false; |
bfb2eb52 PM |
6570 | bool sfault = false; |
6571 | bool return_to_sp_process; | |
6572 | bool return_to_handler; | |
aa488fe3 | 6573 | bool rettobase = false; |
5cb18069 | 6574 | bool exc_secure = false; |
5b522399 | 6575 | bool return_to_secure; |
aa488fe3 | 6576 | |
d02a8698 PM |
6577 | /* If we're not in Handler mode then jumps to magic exception-exit |
6578 | * addresses don't have magic behaviour. However for the v8M | |
6579 | * security extensions the magic secure-function-return has to | |
6580 | * work in thread mode too, so to avoid doing an extra check in | |
6581 | * the generated code we allow exception-exit magic to also cause the | |
6582 | * internal exception and bring us here in thread mode. Correct code | |
6583 | * will never try to do this (the following insn fetch will always | |
6584 | * fault) so we the overhead of having taken an unnecessary exception | |
6585 | * doesn't matter. | |
aa488fe3 | 6586 | */ |
d02a8698 PM |
6587 | if (!arm_v7m_is_handler_mode(env)) { |
6588 | return; | |
6589 | } | |
aa488fe3 PM |
6590 | |
6591 | /* In the spec pseudocode ExceptionReturn() is called directly | |
6592 | * from BXWritePC() and gets the full target PC value including | |
6593 | * bit zero. In QEMU's implementation we treat it as a normal | |
6594 | * jump-to-register (which is then caught later on), and so split | |
6595 | * the target value up between env->regs[15] and env->thumb in | |
6596 | * gen_bx(). Reconstitute it. | |
6597 | */ | |
351e527a | 6598 | excret = env->regs[15]; |
aa488fe3 | 6599 | if (env->thumb) { |
351e527a | 6600 | excret |= 1; |
aa488fe3 PM |
6601 | } |
6602 | ||
6603 | qemu_log_mask(CPU_LOG_INT, "Exception return: magic PC %" PRIx32 | |
6604 | " previous exception %d\n", | |
351e527a | 6605 | excret, env->v7m.exception); |
aa488fe3 | 6606 | |
351e527a | 6607 | if ((excret & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) { |
aa488fe3 | 6608 | qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception " |
351e527a PM |
6609 | "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", |
6610 | excret); | |
aa488fe3 PM |
6611 | } |
6612 | ||
bfb2eb52 PM |
6613 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
6614 | /* EXC_RETURN.ES validation check (R_SMFL). We must do this before | |
6615 | * we pick which FAULTMASK to clear. | |
6616 | */ | |
6617 | if (!env->v7m.secure && | |
6618 | ((excret & R_V7M_EXCRET_ES_MASK) || | |
6619 | !(excret & R_V7M_EXCRET_DCRS_MASK))) { | |
6620 | sfault = 1; | |
6621 | /* For all other purposes, treat ES as 0 (R_HXSR) */ | |
6622 | excret &= ~R_V7M_EXCRET_ES_MASK; | |
6623 | } | |
6624 | } | |
6625 | ||
a20ee600 | 6626 | if (env->v7m.exception != ARMV7M_EXCP_NMI) { |
42a6686b PM |
6627 | /* Auto-clear FAULTMASK on return from other than NMI. |
6628 | * If the security extension is implemented then this only | |
6629 | * happens if the raw execution priority is >= 0; the | |
6630 | * value of the ES bit in the exception return value indicates | |
6631 | * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) | |
6632 | */ | |
6633 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
5cb18069 | 6634 | exc_secure = excret & R_V7M_EXCRET_ES_MASK; |
42a6686b | 6635 | if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) { |
5cb18069 | 6636 | env->v7m.faultmask[exc_secure] = 0; |
42a6686b PM |
6637 | } |
6638 | } else { | |
6639 | env->v7m.faultmask[M_REG_NS] = 0; | |
6640 | } | |
a20ee600 | 6641 | } |
aa488fe3 | 6642 | |
5cb18069 PM |
6643 | switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception, |
6644 | exc_secure)) { | |
aa488fe3 PM |
6645 | case -1: |
6646 | /* attempt to exit an exception that isn't active */ | |
6647 | ufault = true; | |
6648 | break; | |
6649 | case 0: | |
6650 | /* still an irq active now */ | |
6651 | break; | |
6652 | case 1: | |
6653 | /* we returned to base exception level, no nesting. | |
6654 | * (In the pseudocode this is written using "NestedActivation != 1" | |
6655 | * where we have 'rettobase == false'.) | |
6656 | */ | |
6657 | rettobase = true; | |
6658 | break; | |
6659 | default: | |
6660 | g_assert_not_reached(); | |
6661 | } | |
6662 | ||
bfb2eb52 PM |
6663 | return_to_handler = !(excret & R_V7M_EXCRET_MODE_MASK); |
6664 | return_to_sp_process = excret & R_V7M_EXCRET_SPSEL_MASK; | |
5b522399 PM |
6665 | return_to_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) && |
6666 | (excret & R_V7M_EXCRET_S_MASK); | |
6667 | ||
bfb2eb52 PM |
6668 | if (arm_feature(env, ARM_FEATURE_V8)) { |
6669 | if (!arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
6670 | /* UNPREDICTABLE if S == 1 or DCRS == 0 or ES == 1 (R_XLCP); | |
6671 | * we choose to take the UsageFault. | |
6672 | */ | |
6673 | if ((excret & R_V7M_EXCRET_S_MASK) || | |
6674 | (excret & R_V7M_EXCRET_ES_MASK) || | |
6675 | !(excret & R_V7M_EXCRET_DCRS_MASK)) { | |
6676 | ufault = true; | |
6677 | } | |
6678 | } | |
6679 | if (excret & R_V7M_EXCRET_RES0_MASK) { | |
aa488fe3 PM |
6680 | ufault = true; |
6681 | } | |
bfb2eb52 PM |
6682 | } else { |
6683 | /* For v7M we only recognize certain combinations of the low bits */ | |
6684 | switch (excret & 0xf) { | |
6685 | case 1: /* Return to Handler */ | |
6686 | break; | |
6687 | case 13: /* Return to Thread using Process stack */ | |
6688 | case 9: /* Return to Thread using Main stack */ | |
6689 | /* We only need to check NONBASETHRDENA for v7M, because in | |
6690 | * v8M this bit does not exist (it is RES1). | |
6691 | */ | |
6692 | if (!rettobase && | |
6693 | !(env->v7m.ccr[env->v7m.secure] & | |
6694 | R_V7M_CCR_NONBASETHRDENA_MASK)) { | |
6695 | ufault = true; | |
6696 | } | |
6697 | break; | |
6698 | default: | |
6699 | ufault = true; | |
6700 | } | |
6701 | } | |
6702 | ||
6703 | if (sfault) { | |
6704 | env->v7m.sfsr |= R_V7M_SFSR_INVER_MASK; | |
6705 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | |
d3392718 | 6706 | v7m_exception_taken(cpu, excret, true); |
bfb2eb52 PM |
6707 | qemu_log_mask(CPU_LOG_INT, "...taking SecureFault on existing " |
6708 | "stackframe: failed EXC_RETURN.ES validity check\n"); | |
6709 | return; | |
aa488fe3 PM |
6710 | } |
6711 | ||
6712 | if (ufault) { | |
6713 | /* Bad exception return: instead of popping the exception | |
6714 | * stack, directly take a usage fault on the current stack. | |
6715 | */ | |
334e8dad | 6716 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; |
2fb50a33 | 6717 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); |
d3392718 | 6718 | v7m_exception_taken(cpu, excret, true); |
aa488fe3 PM |
6719 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " |
6720 | "stackframe: failed exception return integrity check\n"); | |
6721 | return; | |
a20ee600 | 6722 | } |
9ee6e8bb | 6723 | |
de2db7ec PM |
6724 | /* Set CONTROL.SPSEL from excret.SPSEL. Since we're still in |
6725 | * Handler mode (and will be until we write the new XPSR.Interrupt | |
6726 | * field) this does not switch around the current stack pointer. | |
5b522399 | 6727 | */ |
3f0cddee | 6728 | write_v7m_control_spsel_for_secstate(env, return_to_sp_process, exc_secure); |
5b522399 | 6729 | |
3919e60b PM |
6730 | switch_v7m_security_state(env, return_to_secure); |
6731 | ||
5b522399 PM |
6732 | { |
6733 | /* The stack pointer we should be reading the exception frame from | |
6734 | * depends on bits in the magic exception return type value (and | |
6735 | * for v8M isn't necessarily the stack pointer we will eventually | |
6736 | * end up resuming execution with). Get a pointer to the location | |
6737 | * in the CPU state struct where the SP we need is currently being | |
6738 | * stored; we will use and modify it in place. | |
6739 | * We use this limited C variable scope so we don't accidentally | |
6740 | * use 'frame_sp_p' after we do something that makes it invalid. | |
fcf83ab1 | 6741 | */ |
5b522399 PM |
6742 | uint32_t *frame_sp_p = get_v7m_sp_ptr(env, |
6743 | return_to_secure, | |
6744 | !return_to_handler, | |
6745 | return_to_sp_process); | |
6746 | uint32_t frameptr = *frame_sp_p; | |
6747 | ||
cb484f9a PM |
6748 | if (!QEMU_IS_ALIGNED(frameptr, 8) && |
6749 | arm_feature(env, ARM_FEATURE_V8)) { | |
6750 | qemu_log_mask(LOG_GUEST_ERROR, | |
6751 | "M profile exception return with non-8-aligned SP " | |
6752 | "for destination state is UNPREDICTABLE\n"); | |
6753 | } | |
6754 | ||
907bedb3 PM |
6755 | /* Do we need to pop callee-saved registers? */ |
6756 | if (return_to_secure && | |
6757 | ((excret & R_V7M_EXCRET_ES_MASK) == 0 || | |
6758 | (excret & R_V7M_EXCRET_DCRS_MASK) == 0)) { | |
6759 | uint32_t expected_sig = 0xfefa125b; | |
6760 | uint32_t actual_sig = ldl_phys(cs->as, frameptr); | |
6761 | ||
6762 | if (expected_sig != actual_sig) { | |
6763 | /* Take a SecureFault on the current stack */ | |
6764 | env->v7m.sfsr |= R_V7M_SFSR_INVIS_MASK; | |
6765 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | |
d3392718 | 6766 | v7m_exception_taken(cpu, excret, true); |
907bedb3 PM |
6767 | qemu_log_mask(CPU_LOG_INT, "...taking SecureFault on existing " |
6768 | "stackframe: failed exception return integrity " | |
6769 | "signature check\n"); | |
6770 | return; | |
6771 | } | |
6772 | ||
6773 | env->regs[4] = ldl_phys(cs->as, frameptr + 0x8); | |
6774 | env->regs[5] = ldl_phys(cs->as, frameptr + 0xc); | |
6775 | env->regs[6] = ldl_phys(cs->as, frameptr + 0x10); | |
6776 | env->regs[7] = ldl_phys(cs->as, frameptr + 0x14); | |
6777 | env->regs[8] = ldl_phys(cs->as, frameptr + 0x18); | |
6778 | env->regs[9] = ldl_phys(cs->as, frameptr + 0x1c); | |
6779 | env->regs[10] = ldl_phys(cs->as, frameptr + 0x20); | |
6780 | env->regs[11] = ldl_phys(cs->as, frameptr + 0x24); | |
6781 | ||
6782 | frameptr += 0x28; | |
6783 | } | |
6784 | ||
5b522399 PM |
6785 | /* Pop registers. TODO: make these accesses use the correct |
6786 | * attributes and address space (S/NS, priv/unpriv) and handle | |
6787 | * memory transaction failures. | |
6788 | */ | |
6789 | env->regs[0] = ldl_phys(cs->as, frameptr); | |
6790 | env->regs[1] = ldl_phys(cs->as, frameptr + 0x4); | |
6791 | env->regs[2] = ldl_phys(cs->as, frameptr + 0x8); | |
6792 | env->regs[3] = ldl_phys(cs->as, frameptr + 0xc); | |
6793 | env->regs[12] = ldl_phys(cs->as, frameptr + 0x10); | |
6794 | env->regs[14] = ldl_phys(cs->as, frameptr + 0x14); | |
6795 | env->regs[15] = ldl_phys(cs->as, frameptr + 0x18); | |
4e4259d3 PM |
6796 | |
6797 | /* Returning from an exception with a PC with bit 0 set is defined | |
6798 | * behaviour on v8M (bit 0 is ignored), but for v7M it was specified | |
6799 | * to be UNPREDICTABLE. In practice actual v7M hardware seems to ignore | |
6800 | * the lsbit, and there are several RTOSes out there which incorrectly | |
6801 | * assume the r15 in the stack frame should be a Thumb-style "lsbit | |
6802 | * indicates ARM/Thumb" value, so ignore the bit on v7M as well, but | |
6803 | * complain about the badly behaved guest. | |
6804 | */ | |
5b522399 | 6805 | if (env->regs[15] & 1) { |
5b522399 | 6806 | env->regs[15] &= ~1U; |
4e4259d3 PM |
6807 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
6808 | qemu_log_mask(LOG_GUEST_ERROR, | |
6809 | "M profile return from interrupt with misaligned " | |
6810 | "PC is UNPREDICTABLE on v7M\n"); | |
6811 | } | |
5b522399 | 6812 | } |
4e4259d3 | 6813 | |
5b522399 PM |
6814 | xpsr = ldl_phys(cs->as, frameptr + 0x1c); |
6815 | ||
224e0c30 PM |
6816 | if (arm_feature(env, ARM_FEATURE_V8)) { |
6817 | /* For v8M we have to check whether the xPSR exception field | |
6818 | * matches the EXCRET value for return to handler/thread | |
6819 | * before we commit to changing the SP and xPSR. | |
6820 | */ | |
6821 | bool will_be_handler = (xpsr & XPSR_EXCP) != 0; | |
6822 | if (return_to_handler != will_be_handler) { | |
6823 | /* Take an INVPC UsageFault on the current stack. | |
6824 | * By this point we will have switched to the security state | |
6825 | * for the background state, so this UsageFault will target | |
6826 | * that state. | |
6827 | */ | |
6828 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, | |
6829 | env->v7m.secure); | |
6830 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; | |
d3392718 | 6831 | v7m_exception_taken(cpu, excret, true); |
224e0c30 PM |
6832 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " |
6833 | "stackframe: failed exception return integrity " | |
6834 | "check\n"); | |
6835 | return; | |
6836 | } | |
6837 | } | |
6838 | ||
5b522399 PM |
6839 | /* Commit to consuming the stack frame */ |
6840 | frameptr += 0x20; | |
6841 | /* Undo stack alignment (the SPREALIGN bit indicates that the original | |
6842 | * pre-exception SP was not 8-aligned and we added a padding word to | |
6843 | * align it, so we undo this by ORing in the bit that increases it | |
6844 | * from the current 8-aligned value to the 8-unaligned value. (Adding 4 | |
6845 | * would work too but a logical OR is how the pseudocode specifies it.) | |
6846 | */ | |
6847 | if (xpsr & XPSR_SPREALIGN) { | |
6848 | frameptr |= 4; | |
6849 | } | |
6850 | *frame_sp_p = frameptr; | |
fcf83ab1 | 6851 | } |
5b522399 | 6852 | /* This xpsr_write() will invalidate frame_sp_p as it may switch stack */ |
987ab45e | 6853 | xpsr_write(env, xpsr, ~XPSR_SPREALIGN); |
aa488fe3 PM |
6854 | |
6855 | /* The restored xPSR exception field will be zero if we're | |
6856 | * resuming in Thread mode. If that doesn't match what the | |
351e527a | 6857 | * exception return excret specified then this is a UsageFault. |
224e0c30 | 6858 | * v7M requires we make this check here; v8M did it earlier. |
aa488fe3 | 6859 | */ |
15b3f556 | 6860 | if (return_to_handler != arm_v7m_is_handler_mode(env)) { |
224e0c30 PM |
6861 | /* Take an INVPC UsageFault by pushing the stack again; |
6862 | * we know we're v7M so this is never a Secure UsageFault. | |
2fb50a33 | 6863 | */ |
224e0c30 | 6864 | assert(!arm_feature(env, ARM_FEATURE_V8)); |
2fb50a33 | 6865 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, false); |
334e8dad | 6866 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; |
aa488fe3 | 6867 | v7m_push_stack(cpu); |
d3392718 | 6868 | v7m_exception_taken(cpu, excret, false); |
aa488fe3 PM |
6869 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: " |
6870 | "failed exception return integrity check\n"); | |
6871 | return; | |
6872 | } | |
6873 | ||
6874 | /* Otherwise, we have a successful exception exit. */ | |
dc3c4c14 | 6875 | arm_clear_exclusive(env); |
aa488fe3 | 6876 | qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); |
9ee6e8bb PB |
6877 | } |
6878 | ||
d02a8698 PM |
6879 | static bool do_v7m_function_return(ARMCPU *cpu) |
6880 | { | |
6881 | /* v8M security extensions magic function return. | |
6882 | * We may either: | |
6883 | * (1) throw an exception (longjump) | |
6884 | * (2) return true if we successfully handled the function return | |
6885 | * (3) return false if we failed a consistency check and have | |
6886 | * pended a UsageFault that needs to be taken now | |
6887 | * | |
6888 | * At this point the magic return value is split between env->regs[15] | |
6889 | * and env->thumb. We don't bother to reconstitute it because we don't | |
6890 | * need it (all values are handled the same way). | |
6891 | */ | |
6892 | CPUARMState *env = &cpu->env; | |
6893 | uint32_t newpc, newpsr, newpsr_exc; | |
6894 | ||
6895 | qemu_log_mask(CPU_LOG_INT, "...really v7M secure function return\n"); | |
6896 | ||
6897 | { | |
6898 | bool threadmode, spsel; | |
6899 | TCGMemOpIdx oi; | |
6900 | ARMMMUIdx mmu_idx; | |
6901 | uint32_t *frame_sp_p; | |
6902 | uint32_t frameptr; | |
6903 | ||
6904 | /* Pull the return address and IPSR from the Secure stack */ | |
6905 | threadmode = !arm_v7m_is_handler_mode(env); | |
6906 | spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK; | |
6907 | ||
6908 | frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel); | |
6909 | frameptr = *frame_sp_p; | |
6910 | ||
6911 | /* These loads may throw an exception (for MPU faults). We want to | |
6912 | * do them as secure, so work out what MMU index that is. | |
6913 | */ | |
6914 | mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true); | |
6915 | oi = make_memop_idx(MO_LE, arm_to_core_mmu_idx(mmu_idx)); | |
6916 | newpc = helper_le_ldul_mmu(env, frameptr, oi, 0); | |
6917 | newpsr = helper_le_ldul_mmu(env, frameptr + 4, oi, 0); | |
6918 | ||
6919 | /* Consistency checks on new IPSR */ | |
6920 | newpsr_exc = newpsr & XPSR_EXCP; | |
6921 | if (!((env->v7m.exception == 0 && newpsr_exc == 0) || | |
6922 | (env->v7m.exception == 1 && newpsr_exc != 0))) { | |
6923 | /* Pend the fault and tell our caller to take it */ | |
6924 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; | |
6925 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, | |
6926 | env->v7m.secure); | |
6927 | qemu_log_mask(CPU_LOG_INT, | |
6928 | "...taking INVPC UsageFault: " | |
6929 | "IPSR consistency check failed\n"); | |
6930 | return false; | |
6931 | } | |
6932 | ||
6933 | *frame_sp_p = frameptr + 8; | |
6934 | } | |
6935 | ||
6936 | /* This invalidates frame_sp_p */ | |
6937 | switch_v7m_security_state(env, true); | |
6938 | env->v7m.exception = newpsr_exc; | |
6939 | env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; | |
6940 | if (newpsr & XPSR_SFPA) { | |
6941 | env->v7m.control[M_REG_S] |= R_V7M_CONTROL_SFPA_MASK; | |
6942 | } | |
6943 | xpsr_write(env, 0, XPSR_IT); | |
6944 | env->thumb = newpc & 1; | |
6945 | env->regs[15] = newpc & ~1; | |
6946 | ||
6947 | qemu_log_mask(CPU_LOG_INT, "...function return successful\n"); | |
6948 | return true; | |
6949 | } | |
6950 | ||
27a7ea8a PB |
6951 | static void arm_log_exception(int idx) |
6952 | { | |
6953 | if (qemu_loglevel_mask(CPU_LOG_INT)) { | |
6954 | const char *exc = NULL; | |
2c4a7cc5 PM |
6955 | static const char * const excnames[] = { |
6956 | [EXCP_UDEF] = "Undefined Instruction", | |
6957 | [EXCP_SWI] = "SVC", | |
6958 | [EXCP_PREFETCH_ABORT] = "Prefetch Abort", | |
6959 | [EXCP_DATA_ABORT] = "Data Abort", | |
6960 | [EXCP_IRQ] = "IRQ", | |
6961 | [EXCP_FIQ] = "FIQ", | |
6962 | [EXCP_BKPT] = "Breakpoint", | |
6963 | [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", | |
6964 | [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", | |
6965 | [EXCP_HVC] = "Hypervisor Call", | |
6966 | [EXCP_HYP_TRAP] = "Hypervisor Trap", | |
6967 | [EXCP_SMC] = "Secure Monitor Call", | |
6968 | [EXCP_VIRQ] = "Virtual IRQ", | |
6969 | [EXCP_VFIQ] = "Virtual FIQ", | |
6970 | [EXCP_SEMIHOST] = "Semihosting call", | |
6971 | [EXCP_NOCP] = "v7M NOCP UsageFault", | |
6972 | [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", | |
6973 | }; | |
27a7ea8a PB |
6974 | |
6975 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | |
6976 | exc = excnames[idx]; | |
6977 | } | |
6978 | if (!exc) { | |
6979 | exc = "unknown"; | |
6980 | } | |
6981 | qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); | |
6982 | } | |
6983 | } | |
6984 | ||
333e10c5 PM |
6985 | static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, |
6986 | uint32_t addr, uint16_t *insn) | |
6987 | { | |
6988 | /* Load a 16-bit portion of a v7M instruction, returning true on success, | |
6989 | * or false on failure (in which case we will have pended the appropriate | |
6990 | * exception). | |
6991 | * We need to do the instruction fetch's MPU and SAU checks | |
6992 | * like this because there is no MMU index that would allow | |
6993 | * doing the load with a single function call. Instead we must | |
6994 | * first check that the security attributes permit the load | |
6995 | * and that they don't mismatch on the two halves of the instruction, | |
6996 | * and then we do the load as a secure load (ie using the security | |
6997 | * attributes of the address, not the CPU, as architecturally required). | |
6998 | */ | |
6999 | CPUState *cs = CPU(cpu); | |
7000 | CPUARMState *env = &cpu->env; | |
7001 | V8M_SAttributes sattrs = {}; | |
7002 | MemTxAttrs attrs = {}; | |
7003 | ARMMMUFaultInfo fi = {}; | |
7004 | MemTxResult txres; | |
7005 | target_ulong page_size; | |
7006 | hwaddr physaddr; | |
7007 | int prot; | |
333e10c5 PM |
7008 | |
7009 | v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs); | |
7010 | if (!sattrs.nsc || sattrs.ns) { | |
7011 | /* This must be the second half of the insn, and it straddles a | |
7012 | * region boundary with the second half not being S&NSC. | |
7013 | */ | |
7014 | env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK; | |
7015 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | |
7016 | qemu_log_mask(CPU_LOG_INT, | |
7017 | "...really SecureFault with SFSR.INVEP\n"); | |
7018 | return false; | |
7019 | } | |
7020 | if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, | |
bc52bfeb | 7021 | &physaddr, &attrs, &prot, &page_size, &fi, NULL)) { |
333e10c5 PM |
7022 | /* the MPU lookup failed */ |
7023 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; | |
7024 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure); | |
7025 | qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL\n"); | |
7026 | return false; | |
7027 | } | |
7028 | *insn = address_space_lduw_le(arm_addressspace(cs, attrs), physaddr, | |
7029 | attrs, &txres); | |
7030 | if (txres != MEMTX_OK) { | |
7031 | env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK; | |
7032 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); | |
7033 | qemu_log_mask(CPU_LOG_INT, "...really BusFault with CFSR.IBUSERR\n"); | |
7034 | return false; | |
7035 | } | |
7036 | return true; | |
7037 | } | |
7038 | ||
7039 | static bool v7m_handle_execute_nsc(ARMCPU *cpu) | |
7040 | { | |
7041 | /* Check whether this attempt to execute code in a Secure & NS-Callable | |
7042 | * memory region is for an SG instruction; if so, then emulate the | |
7043 | * effect of the SG instruction and return true. Otherwise pend | |
7044 | * the correct kind of exception and return false. | |
7045 | */ | |
7046 | CPUARMState *env = &cpu->env; | |
7047 | ARMMMUIdx mmu_idx; | |
7048 | uint16_t insn; | |
7049 | ||
7050 | /* We should never get here unless get_phys_addr_pmsav8() caused | |
7051 | * an exception for NS executing in S&NSC memory. | |
7052 | */ | |
7053 | assert(!env->v7m.secure); | |
7054 | assert(arm_feature(env, ARM_FEATURE_M_SECURITY)); | |
7055 | ||
7056 | /* We want to do the MPU lookup as secure; work out what mmu_idx that is */ | |
7057 | mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true); | |
7058 | ||
7059 | if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) { | |
7060 | return false; | |
7061 | } | |
7062 | ||
7063 | if (!env->thumb) { | |
7064 | goto gen_invep; | |
7065 | } | |
7066 | ||
7067 | if (insn != 0xe97f) { | |
7068 | /* Not an SG instruction first half (we choose the IMPDEF | |
7069 | * early-SG-check option). | |
7070 | */ | |
7071 | goto gen_invep; | |
7072 | } | |
7073 | ||
7074 | if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) { | |
7075 | return false; | |
7076 | } | |
7077 | ||
7078 | if (insn != 0xe97f) { | |
7079 | /* Not an SG instruction second half (yes, both halves of the SG | |
7080 | * insn have the same hex value) | |
7081 | */ | |
7082 | goto gen_invep; | |
7083 | } | |
7084 | ||
7085 | /* OK, we have confirmed that we really have an SG instruction. | |
7086 | * We know we're NS in S memory so don't need to repeat those checks. | |
7087 | */ | |
7088 | qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32 | |
7089 | ", executing it\n", env->regs[15]); | |
7090 | env->regs[14] &= ~1; | |
7091 | switch_v7m_security_state(env, true); | |
7092 | xpsr_write(env, 0, XPSR_IT); | |
7093 | env->regs[15] += 4; | |
7094 | return true; | |
7095 | ||
7096 | gen_invep: | |
7097 | env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK; | |
7098 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | |
7099 | qemu_log_mask(CPU_LOG_INT, | |
7100 | "...really SecureFault with SFSR.INVEP\n"); | |
7101 | return false; | |
7102 | } | |
7103 | ||
e6f010cc | 7104 | void arm_v7m_cpu_do_interrupt(CPUState *cs) |
9ee6e8bb | 7105 | { |
e6f010cc AF |
7106 | ARMCPU *cpu = ARM_CPU(cs); |
7107 | CPUARMState *env = &cpu->env; | |
9ee6e8bb | 7108 | uint32_t lr; |
9ee6e8bb | 7109 | |
27103424 | 7110 | arm_log_exception(cs->exception_index); |
3f1beaca | 7111 | |
9ee6e8bb PB |
7112 | /* For exceptions we just mark as pending on the NVIC, and let that |
7113 | handle it. */ | |
27103424 | 7114 | switch (cs->exception_index) { |
9ee6e8bb | 7115 | case EXCP_UDEF: |
2fb50a33 | 7116 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); |
334e8dad | 7117 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK; |
a25dc805 | 7118 | break; |
7517748e | 7119 | case EXCP_NOCP: |
2fb50a33 | 7120 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); |
334e8dad | 7121 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK; |
a25dc805 | 7122 | break; |
e13886e3 | 7123 | case EXCP_INVSTATE: |
2fb50a33 | 7124 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); |
334e8dad | 7125 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK; |
e13886e3 | 7126 | break; |
9ee6e8bb | 7127 | case EXCP_SWI: |
314e2296 | 7128 | /* The PC already points to the next instruction. */ |
2fb50a33 | 7129 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure); |
a25dc805 | 7130 | break; |
9ee6e8bb PB |
7131 | case EXCP_PREFETCH_ABORT: |
7132 | case EXCP_DATA_ABORT: | |
5dd0641d MD |
7133 | /* Note that for M profile we don't have a guest facing FSR, but |
7134 | * the env->exception.fsr will be populated by the code that | |
7135 | * raises the fault, in the A profile short-descriptor format. | |
abf1172f | 7136 | */ |
5dd0641d | 7137 | switch (env->exception.fsr & 0xf) { |
35337cc3 PM |
7138 | case M_FAKE_FSR_NSC_EXEC: |
7139 | /* Exception generated when we try to execute code at an address | |
7140 | * which is marked as Secure & Non-Secure Callable and the CPU | |
7141 | * is in the Non-Secure state. The only instruction which can | |
7142 | * be executed like this is SG (and that only if both halves of | |
7143 | * the SG instruction have the same security attributes.) | |
7144 | * Everything else must generate an INVEP SecureFault, so we | |
7145 | * emulate the SG instruction here. | |
35337cc3 | 7146 | */ |
333e10c5 PM |
7147 | if (v7m_handle_execute_nsc(cpu)) { |
7148 | return; | |
7149 | } | |
35337cc3 PM |
7150 | break; |
7151 | case M_FAKE_FSR_SFAULT: | |
7152 | /* Various flavours of SecureFault for attempts to execute or | |
7153 | * access data in the wrong security state. | |
7154 | */ | |
7155 | switch (cs->exception_index) { | |
7156 | case EXCP_PREFETCH_ABORT: | |
7157 | if (env->v7m.secure) { | |
7158 | env->v7m.sfsr |= R_V7M_SFSR_INVTRAN_MASK; | |
7159 | qemu_log_mask(CPU_LOG_INT, | |
7160 | "...really SecureFault with SFSR.INVTRAN\n"); | |
7161 | } else { | |
7162 | env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK; | |
7163 | qemu_log_mask(CPU_LOG_INT, | |
7164 | "...really SecureFault with SFSR.INVEP\n"); | |
7165 | } | |
7166 | break; | |
7167 | case EXCP_DATA_ABORT: | |
7168 | /* This must be an NS access to S memory */ | |
7169 | env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK; | |
7170 | qemu_log_mask(CPU_LOG_INT, | |
7171 | "...really SecureFault with SFSR.AUVIOL\n"); | |
7172 | break; | |
7173 | } | |
7174 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | |
7175 | break; | |
5dd0641d MD |
7176 | case 0x8: /* External Abort */ |
7177 | switch (cs->exception_index) { | |
7178 | case EXCP_PREFETCH_ABORT: | |
c6158878 PM |
7179 | env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK; |
7180 | qemu_log_mask(CPU_LOG_INT, "...with CFSR.IBUSERR\n"); | |
5dd0641d MD |
7181 | break; |
7182 | case EXCP_DATA_ABORT: | |
334e8dad | 7183 | env->v7m.cfsr[M_REG_NS] |= |
c6158878 | 7184 | (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK); |
5dd0641d MD |
7185 | env->v7m.bfar = env->exception.vaddress; |
7186 | qemu_log_mask(CPU_LOG_INT, | |
c6158878 | 7187 | "...with CFSR.PRECISERR and BFAR 0x%x\n", |
5dd0641d MD |
7188 | env->v7m.bfar); |
7189 | break; | |
7190 | } | |
2fb50a33 | 7191 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); |
5dd0641d MD |
7192 | break; |
7193 | default: | |
7194 | /* All other FSR values are either MPU faults or "can't happen | |
7195 | * for M profile" cases. | |
7196 | */ | |
7197 | switch (cs->exception_index) { | |
7198 | case EXCP_PREFETCH_ABORT: | |
334e8dad | 7199 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; |
5dd0641d MD |
7200 | qemu_log_mask(CPU_LOG_INT, "...with CFSR.IACCVIOL\n"); |
7201 | break; | |
7202 | case EXCP_DATA_ABORT: | |
334e8dad | 7203 | env->v7m.cfsr[env->v7m.secure] |= |
5dd0641d | 7204 | (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK); |
c51a5cfc | 7205 | env->v7m.mmfar[env->v7m.secure] = env->exception.vaddress; |
5dd0641d MD |
7206 | qemu_log_mask(CPU_LOG_INT, |
7207 | "...with CFSR.DACCVIOL and MMFAR 0x%x\n", | |
c51a5cfc | 7208 | env->v7m.mmfar[env->v7m.secure]); |
5dd0641d MD |
7209 | break; |
7210 | } | |
2fb50a33 PM |
7211 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, |
7212 | env->v7m.secure); | |
5dd0641d MD |
7213 | break; |
7214 | } | |
a25dc805 | 7215 | break; |
9ee6e8bb | 7216 | case EXCP_BKPT: |
cfe67cef | 7217 | if (semihosting_enabled()) { |
2ad207d4 | 7218 | int nr; |
f9fd40eb | 7219 | nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff; |
2ad207d4 PB |
7220 | if (nr == 0xab) { |
7221 | env->regs[15] += 2; | |
205ace55 CC |
7222 | qemu_log_mask(CPU_LOG_INT, |
7223 | "...handling as semihosting call 0x%x\n", | |
7224 | env->regs[0]); | |
2ad207d4 PB |
7225 | env->regs[0] = do_arm_semihosting(env); |
7226 | return; | |
7227 | } | |
7228 | } | |
2fb50a33 | 7229 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false); |
a25dc805 | 7230 | break; |
9ee6e8bb | 7231 | case EXCP_IRQ: |
9ee6e8bb PB |
7232 | break; |
7233 | case EXCP_EXCEPTION_EXIT: | |
d02a8698 PM |
7234 | if (env->regs[15] < EXC_RETURN_MIN_MAGIC) { |
7235 | /* Must be v8M security extension function return */ | |
7236 | assert(env->regs[15] >= FNC_RETURN_MIN_MAGIC); | |
7237 | assert(arm_feature(env, ARM_FEATURE_M_SECURITY)); | |
7238 | if (do_v7m_function_return(cpu)) { | |
7239 | return; | |
7240 | } | |
7241 | } else { | |
7242 | do_v7m_exception_exit(cpu); | |
7243 | return; | |
7244 | } | |
7245 | break; | |
9ee6e8bb | 7246 | default: |
a47dddd7 | 7247 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
9ee6e8bb PB |
7248 | return; /* Never happens. Keep compiler happy. */ |
7249 | } | |
7250 | ||
d3392718 PM |
7251 | if (arm_feature(env, ARM_FEATURE_V8)) { |
7252 | lr = R_V7M_EXCRET_RES1_MASK | | |
7253 | R_V7M_EXCRET_DCRS_MASK | | |
7254 | R_V7M_EXCRET_FTYPE_MASK; | |
7255 | /* The S bit indicates whether we should return to Secure | |
7256 | * or NonSecure (ie our current state). | |
7257 | * The ES bit indicates whether we're taking this exception | |
7258 | * to Secure or NonSecure (ie our target state). We set it | |
7259 | * later, in v7m_exception_taken(). | |
7260 | * The SPSEL bit is also set in v7m_exception_taken() for v8M. | |
7261 | * This corresponds to the ARM ARM pseudocode for v8M setting | |
7262 | * some LR bits in PushStack() and some in ExceptionTaken(); | |
7263 | * the distinction matters for the tailchain cases where we | |
7264 | * can take an exception without pushing the stack. | |
7265 | */ | |
7266 | if (env->v7m.secure) { | |
7267 | lr |= R_V7M_EXCRET_S_MASK; | |
7268 | } | |
7269 | } else { | |
7270 | lr = R_V7M_EXCRET_RES1_MASK | | |
7271 | R_V7M_EXCRET_S_MASK | | |
7272 | R_V7M_EXCRET_DCRS_MASK | | |
7273 | R_V7M_EXCRET_FTYPE_MASK | | |
7274 | R_V7M_EXCRET_ES_MASK; | |
7275 | if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) { | |
7276 | lr |= R_V7M_EXCRET_SPSEL_MASK; | |
7277 | } | |
bd70b29b | 7278 | } |
15b3f556 | 7279 | if (!arm_v7m_is_handler_mode(env)) { |
4d1e7a47 | 7280 | lr |= R_V7M_EXCRET_MODE_MASK; |
bd70b29b PM |
7281 | } |
7282 | ||
39ae2474 | 7283 | v7m_push_stack(cpu); |
d3392718 | 7284 | v7m_exception_taken(cpu, lr, false); |
a25dc805 | 7285 | qemu_log_mask(CPU_LOG_INT, "... as %d\n", env->v7m.exception); |
9ee6e8bb PB |
7286 | } |
7287 | ||
ce02049d GB |
7288 | /* Function used to synchronize QEMU's AArch64 register set with AArch32 |
7289 | * register set. This is necessary when switching between AArch32 and AArch64 | |
7290 | * execution state. | |
7291 | */ | |
7292 | void aarch64_sync_32_to_64(CPUARMState *env) | |
7293 | { | |
7294 | int i; | |
7295 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
7296 | ||
7297 | /* We can blanket copy R[0:7] to X[0:7] */ | |
7298 | for (i = 0; i < 8; i++) { | |
7299 | env->xregs[i] = env->regs[i]; | |
7300 | } | |
7301 | ||
7302 | /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. | |
7303 | * Otherwise, they come from the banked user regs. | |
7304 | */ | |
7305 | if (mode == ARM_CPU_MODE_FIQ) { | |
7306 | for (i = 8; i < 13; i++) { | |
7307 | env->xregs[i] = env->usr_regs[i - 8]; | |
7308 | } | |
7309 | } else { | |
7310 | for (i = 8; i < 13; i++) { | |
7311 | env->xregs[i] = env->regs[i]; | |
7312 | } | |
7313 | } | |
7314 | ||
7315 | /* Registers x13-x23 are the various mode SP and FP registers. Registers | |
7316 | * r13 and r14 are only copied if we are in that mode, otherwise we copy | |
7317 | * from the mode banked register. | |
7318 | */ | |
7319 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { | |
7320 | env->xregs[13] = env->regs[13]; | |
7321 | env->xregs[14] = env->regs[14]; | |
7322 | } else { | |
7323 | env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; | |
7324 | /* HYP is an exception in that it is copied from r14 */ | |
7325 | if (mode == ARM_CPU_MODE_HYP) { | |
7326 | env->xregs[14] = env->regs[14]; | |
7327 | } else { | |
7328 | env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)]; | |
7329 | } | |
7330 | } | |
7331 | ||
7332 | if (mode == ARM_CPU_MODE_HYP) { | |
7333 | env->xregs[15] = env->regs[13]; | |
7334 | } else { | |
7335 | env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; | |
7336 | } | |
7337 | ||
7338 | if (mode == ARM_CPU_MODE_IRQ) { | |
3a9148d0 SS |
7339 | env->xregs[16] = env->regs[14]; |
7340 | env->xregs[17] = env->regs[13]; | |
ce02049d | 7341 | } else { |
3a9148d0 SS |
7342 | env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)]; |
7343 | env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; | |
ce02049d GB |
7344 | } |
7345 | ||
7346 | if (mode == ARM_CPU_MODE_SVC) { | |
3a9148d0 SS |
7347 | env->xregs[18] = env->regs[14]; |
7348 | env->xregs[19] = env->regs[13]; | |
ce02049d | 7349 | } else { |
3a9148d0 SS |
7350 | env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)]; |
7351 | env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; | |
ce02049d GB |
7352 | } |
7353 | ||
7354 | if (mode == ARM_CPU_MODE_ABT) { | |
3a9148d0 SS |
7355 | env->xregs[20] = env->regs[14]; |
7356 | env->xregs[21] = env->regs[13]; | |
ce02049d | 7357 | } else { |
3a9148d0 SS |
7358 | env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)]; |
7359 | env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; | |
ce02049d GB |
7360 | } |
7361 | ||
7362 | if (mode == ARM_CPU_MODE_UND) { | |
3a9148d0 SS |
7363 | env->xregs[22] = env->regs[14]; |
7364 | env->xregs[23] = env->regs[13]; | |
ce02049d | 7365 | } else { |
3a9148d0 SS |
7366 | env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)]; |
7367 | env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; | |
ce02049d GB |
7368 | } |
7369 | ||
7370 | /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ | |
7371 | * mode, then we can copy from r8-r14. Otherwise, we copy from the | |
7372 | * FIQ bank for r8-r14. | |
7373 | */ | |
7374 | if (mode == ARM_CPU_MODE_FIQ) { | |
7375 | for (i = 24; i < 31; i++) { | |
7376 | env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ | |
7377 | } | |
7378 | } else { | |
7379 | for (i = 24; i < 29; i++) { | |
7380 | env->xregs[i] = env->fiq_regs[i - 24]; | |
7381 | } | |
7382 | env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; | |
7383 | env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)]; | |
7384 | } | |
7385 | ||
7386 | env->pc = env->regs[15]; | |
7387 | } | |
7388 | ||
7389 | /* Function used to synchronize QEMU's AArch32 register set with AArch64 | |
7390 | * register set. This is necessary when switching between AArch32 and AArch64 | |
7391 | * execution state. | |
7392 | */ | |
7393 | void aarch64_sync_64_to_32(CPUARMState *env) | |
7394 | { | |
7395 | int i; | |
7396 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
7397 | ||
7398 | /* We can blanket copy X[0:7] to R[0:7] */ | |
7399 | for (i = 0; i < 8; i++) { | |
7400 | env->regs[i] = env->xregs[i]; | |
7401 | } | |
7402 | ||
7403 | /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. | |
7404 | * Otherwise, we copy x8-x12 into the banked user regs. | |
7405 | */ | |
7406 | if (mode == ARM_CPU_MODE_FIQ) { | |
7407 | for (i = 8; i < 13; i++) { | |
7408 | env->usr_regs[i - 8] = env->xregs[i]; | |
7409 | } | |
7410 | } else { | |
7411 | for (i = 8; i < 13; i++) { | |
7412 | env->regs[i] = env->xregs[i]; | |
7413 | } | |
7414 | } | |
7415 | ||
7416 | /* Registers r13 & r14 depend on the current mode. | |
7417 | * If we are in a given mode, we copy the corresponding x registers to r13 | |
7418 | * and r14. Otherwise, we copy the x register to the banked r13 and r14 | |
7419 | * for the mode. | |
7420 | */ | |
7421 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { | |
7422 | env->regs[13] = env->xregs[13]; | |
7423 | env->regs[14] = env->xregs[14]; | |
7424 | } else { | |
7425 | env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; | |
7426 | ||
7427 | /* HYP is an exception in that it does not have its own banked r14 but | |
7428 | * shares the USR r14 | |
7429 | */ | |
7430 | if (mode == ARM_CPU_MODE_HYP) { | |
7431 | env->regs[14] = env->xregs[14]; | |
7432 | } else { | |
7433 | env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; | |
7434 | } | |
7435 | } | |
7436 | ||
7437 | if (mode == ARM_CPU_MODE_HYP) { | |
7438 | env->regs[13] = env->xregs[15]; | |
7439 | } else { | |
7440 | env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; | |
7441 | } | |
7442 | ||
7443 | if (mode == ARM_CPU_MODE_IRQ) { | |
3a9148d0 SS |
7444 | env->regs[14] = env->xregs[16]; |
7445 | env->regs[13] = env->xregs[17]; | |
ce02049d | 7446 | } else { |
3a9148d0 SS |
7447 | env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; |
7448 | env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; | |
ce02049d GB |
7449 | } |
7450 | ||
7451 | if (mode == ARM_CPU_MODE_SVC) { | |
3a9148d0 SS |
7452 | env->regs[14] = env->xregs[18]; |
7453 | env->regs[13] = env->xregs[19]; | |
ce02049d | 7454 | } else { |
3a9148d0 SS |
7455 | env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; |
7456 | env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; | |
ce02049d GB |
7457 | } |
7458 | ||
7459 | if (mode == ARM_CPU_MODE_ABT) { | |
3a9148d0 SS |
7460 | env->regs[14] = env->xregs[20]; |
7461 | env->regs[13] = env->xregs[21]; | |
ce02049d | 7462 | } else { |
3a9148d0 SS |
7463 | env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; |
7464 | env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; | |
ce02049d GB |
7465 | } |
7466 | ||
7467 | if (mode == ARM_CPU_MODE_UND) { | |
3a9148d0 SS |
7468 | env->regs[14] = env->xregs[22]; |
7469 | env->regs[13] = env->xregs[23]; | |
ce02049d | 7470 | } else { |
3a9148d0 SS |
7471 | env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; |
7472 | env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; | |
ce02049d GB |
7473 | } |
7474 | ||
7475 | /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ | |
7476 | * mode, then we can copy to r8-r14. Otherwise, we copy to the | |
7477 | * FIQ bank for r8-r14. | |
7478 | */ | |
7479 | if (mode == ARM_CPU_MODE_FIQ) { | |
7480 | for (i = 24; i < 31; i++) { | |
7481 | env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ | |
7482 | } | |
7483 | } else { | |
7484 | for (i = 24; i < 29; i++) { | |
7485 | env->fiq_regs[i - 24] = env->xregs[i]; | |
7486 | } | |
7487 | env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; | |
7488 | env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; | |
7489 | } | |
7490 | ||
7491 | env->regs[15] = env->pc; | |
7492 | } | |
7493 | ||
966f758c | 7494 | static void arm_cpu_do_interrupt_aarch32(CPUState *cs) |
b5ff1b31 | 7495 | { |
97a8ea5a AF |
7496 | ARMCPU *cpu = ARM_CPU(cs); |
7497 | CPUARMState *env = &cpu->env; | |
b5ff1b31 FB |
7498 | uint32_t addr; |
7499 | uint32_t mask; | |
7500 | int new_mode; | |
7501 | uint32_t offset; | |
16a906fd | 7502 | uint32_t moe; |
b5ff1b31 | 7503 | |
16a906fd PM |
7504 | /* If this is a debug exception we must update the DBGDSCR.MOE bits */ |
7505 | switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) { | |
7506 | case EC_BREAKPOINT: | |
7507 | case EC_BREAKPOINT_SAME_EL: | |
7508 | moe = 1; | |
7509 | break; | |
7510 | case EC_WATCHPOINT: | |
7511 | case EC_WATCHPOINT_SAME_EL: | |
7512 | moe = 10; | |
7513 | break; | |
7514 | case EC_AA32_BKPT: | |
7515 | moe = 3; | |
7516 | break; | |
7517 | case EC_VECTORCATCH: | |
7518 | moe = 5; | |
7519 | break; | |
7520 | default: | |
7521 | moe = 0; | |
7522 | break; | |
7523 | } | |
7524 | ||
7525 | if (moe) { | |
7526 | env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); | |
7527 | } | |
7528 | ||
b5ff1b31 | 7529 | /* TODO: Vectored interrupt controller. */ |
27103424 | 7530 | switch (cs->exception_index) { |
b5ff1b31 FB |
7531 | case EXCP_UDEF: |
7532 | new_mode = ARM_CPU_MODE_UND; | |
7533 | addr = 0x04; | |
7534 | mask = CPSR_I; | |
7535 | if (env->thumb) | |
7536 | offset = 2; | |
7537 | else | |
7538 | offset = 4; | |
7539 | break; | |
7540 | case EXCP_SWI: | |
7541 | new_mode = ARM_CPU_MODE_SVC; | |
7542 | addr = 0x08; | |
7543 | mask = CPSR_I; | |
601d70b9 | 7544 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
7545 | offset = 0; |
7546 | break; | |
06c949e6 | 7547 | case EXCP_BKPT: |
abf1172f | 7548 | env->exception.fsr = 2; |
9ee6e8bb PB |
7549 | /* Fall through to prefetch abort. */ |
7550 | case EXCP_PREFETCH_ABORT: | |
88ca1c2d | 7551 | A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); |
b848ce2b | 7552 | A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); |
3f1beaca | 7553 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", |
88ca1c2d | 7554 | env->exception.fsr, (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
7555 | new_mode = ARM_CPU_MODE_ABT; |
7556 | addr = 0x0c; | |
7557 | mask = CPSR_A | CPSR_I; | |
7558 | offset = 4; | |
7559 | break; | |
7560 | case EXCP_DATA_ABORT: | |
4a7e2d73 | 7561 | A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); |
b848ce2b | 7562 | A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); |
3f1beaca | 7563 | qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", |
4a7e2d73 | 7564 | env->exception.fsr, |
6cd8a264 | 7565 | (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
7566 | new_mode = ARM_CPU_MODE_ABT; |
7567 | addr = 0x10; | |
7568 | mask = CPSR_A | CPSR_I; | |
7569 | offset = 8; | |
7570 | break; | |
7571 | case EXCP_IRQ: | |
7572 | new_mode = ARM_CPU_MODE_IRQ; | |
7573 | addr = 0x18; | |
7574 | /* Disable IRQ and imprecise data aborts. */ | |
7575 | mask = CPSR_A | CPSR_I; | |
7576 | offset = 4; | |
de38d23b FA |
7577 | if (env->cp15.scr_el3 & SCR_IRQ) { |
7578 | /* IRQ routed to monitor mode */ | |
7579 | new_mode = ARM_CPU_MODE_MON; | |
7580 | mask |= CPSR_F; | |
7581 | } | |
b5ff1b31 FB |
7582 | break; |
7583 | case EXCP_FIQ: | |
7584 | new_mode = ARM_CPU_MODE_FIQ; | |
7585 | addr = 0x1c; | |
7586 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
7587 | mask = CPSR_A | CPSR_I | CPSR_F; | |
de38d23b FA |
7588 | if (env->cp15.scr_el3 & SCR_FIQ) { |
7589 | /* FIQ routed to monitor mode */ | |
7590 | new_mode = ARM_CPU_MODE_MON; | |
7591 | } | |
b5ff1b31 FB |
7592 | offset = 4; |
7593 | break; | |
87a4b270 PM |
7594 | case EXCP_VIRQ: |
7595 | new_mode = ARM_CPU_MODE_IRQ; | |
7596 | addr = 0x18; | |
7597 | /* Disable IRQ and imprecise data aborts. */ | |
7598 | mask = CPSR_A | CPSR_I; | |
7599 | offset = 4; | |
7600 | break; | |
7601 | case EXCP_VFIQ: | |
7602 | new_mode = ARM_CPU_MODE_FIQ; | |
7603 | addr = 0x1c; | |
7604 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
7605 | mask = CPSR_A | CPSR_I | CPSR_F; | |
7606 | offset = 4; | |
7607 | break; | |
dbe9d163 FA |
7608 | case EXCP_SMC: |
7609 | new_mode = ARM_CPU_MODE_MON; | |
7610 | addr = 0x08; | |
7611 | mask = CPSR_A | CPSR_I | CPSR_F; | |
7612 | offset = 0; | |
7613 | break; | |
b5ff1b31 | 7614 | default: |
a47dddd7 | 7615 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
b5ff1b31 FB |
7616 | return; /* Never happens. Keep compiler happy. */ |
7617 | } | |
e89e51a1 FA |
7618 | |
7619 | if (new_mode == ARM_CPU_MODE_MON) { | |
7620 | addr += env->cp15.mvbar; | |
137feaa9 | 7621 | } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { |
e89e51a1 | 7622 | /* High vectors. When enabled, base address cannot be remapped. */ |
b5ff1b31 | 7623 | addr += 0xffff0000; |
8641136c NR |
7624 | } else { |
7625 | /* ARM v7 architectures provide a vector base address register to remap | |
7626 | * the interrupt vector table. | |
e89e51a1 | 7627 | * This register is only followed in non-monitor mode, and is banked. |
8641136c NR |
7628 | * Note: only bits 31:5 are valid. |
7629 | */ | |
fb6c91ba | 7630 | addr += A32_BANKED_CURRENT_REG_GET(env, vbar); |
b5ff1b31 | 7631 | } |
dbe9d163 FA |
7632 | |
7633 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
7634 | env->cp15.scr_el3 &= ~SCR_NS; | |
7635 | } | |
7636 | ||
b5ff1b31 | 7637 | switch_mode (env, new_mode); |
662cefb7 PM |
7638 | /* For exceptions taken to AArch32 we must clear the SS bit in both |
7639 | * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. | |
7640 | */ | |
7641 | env->uncached_cpsr &= ~PSTATE_SS; | |
b5ff1b31 | 7642 | env->spsr = cpsr_read(env); |
9ee6e8bb PB |
7643 | /* Clear IT bits. */ |
7644 | env->condexec_bits = 0; | |
30a8cac1 | 7645 | /* Switch to the new mode, and to the correct instruction set. */ |
6d7e6326 | 7646 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; |
73462ddd PC |
7647 | /* Set new mode endianness */ |
7648 | env->uncached_cpsr &= ~CPSR_E; | |
7649 | if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { | |
3823b9db | 7650 | env->uncached_cpsr |= CPSR_E; |
73462ddd | 7651 | } |
4cc35614 | 7652 | env->daif |= mask; |
be5e7a76 DES |
7653 | /* this is a lie, as the was no c1_sys on V4T/V5, but who cares |
7654 | * and we should just guard the thumb mode on V4 */ | |
7655 | if (arm_feature(env, ARM_FEATURE_V4T)) { | |
137feaa9 | 7656 | env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; |
be5e7a76 | 7657 | } |
b5ff1b31 FB |
7658 | env->regs[14] = env->regs[15] + offset; |
7659 | env->regs[15] = addr; | |
b5ff1b31 FB |
7660 | } |
7661 | ||
966f758c PM |
7662 | /* Handle exception entry to a target EL which is using AArch64 */ |
7663 | static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | |
f3a9b694 PM |
7664 | { |
7665 | ARMCPU *cpu = ARM_CPU(cs); | |
7666 | CPUARMState *env = &cpu->env; | |
7667 | unsigned int new_el = env->exception.target_el; | |
7668 | target_ulong addr = env->cp15.vbar_el[new_el]; | |
7669 | unsigned int new_mode = aarch64_pstate_mode(new_el, true); | |
7670 | ||
7671 | if (arm_current_el(env) < new_el) { | |
3d6f7617 PM |
7672 | /* Entry vector offset depends on whether the implemented EL |
7673 | * immediately lower than the target level is using AArch32 or AArch64 | |
7674 | */ | |
7675 | bool is_aa64; | |
7676 | ||
7677 | switch (new_el) { | |
7678 | case 3: | |
7679 | is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; | |
7680 | break; | |
7681 | case 2: | |
7682 | is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0; | |
7683 | break; | |
7684 | case 1: | |
7685 | is_aa64 = is_a64(env); | |
7686 | break; | |
7687 | default: | |
7688 | g_assert_not_reached(); | |
7689 | } | |
7690 | ||
7691 | if (is_aa64) { | |
f3a9b694 PM |
7692 | addr += 0x400; |
7693 | } else { | |
7694 | addr += 0x600; | |
7695 | } | |
7696 | } else if (pstate_read(env) & PSTATE_SP) { | |
7697 | addr += 0x200; | |
7698 | } | |
7699 | ||
f3a9b694 PM |
7700 | switch (cs->exception_index) { |
7701 | case EXCP_PREFETCH_ABORT: | |
7702 | case EXCP_DATA_ABORT: | |
7703 | env->cp15.far_el[new_el] = env->exception.vaddress; | |
7704 | qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", | |
7705 | env->cp15.far_el[new_el]); | |
7706 | /* fall through */ | |
7707 | case EXCP_BKPT: | |
7708 | case EXCP_UDEF: | |
7709 | case EXCP_SWI: | |
7710 | case EXCP_HVC: | |
7711 | case EXCP_HYP_TRAP: | |
7712 | case EXCP_SMC: | |
7713 | env->cp15.esr_el[new_el] = env->exception.syndrome; | |
7714 | break; | |
7715 | case EXCP_IRQ: | |
7716 | case EXCP_VIRQ: | |
7717 | addr += 0x80; | |
7718 | break; | |
7719 | case EXCP_FIQ: | |
7720 | case EXCP_VFIQ: | |
7721 | addr += 0x100; | |
7722 | break; | |
7723 | case EXCP_SEMIHOST: | |
7724 | qemu_log_mask(CPU_LOG_INT, | |
7725 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
7726 | env->xregs[0]); | |
7727 | env->xregs[0] = do_arm_semihosting(env); | |
7728 | return; | |
7729 | default: | |
7730 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
7731 | } | |
7732 | ||
7733 | if (is_a64(env)) { | |
7734 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env); | |
7735 | aarch64_save_sp(env, arm_current_el(env)); | |
7736 | env->elr_el[new_el] = env->pc; | |
7737 | } else { | |
7738 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env); | |
f3a9b694 PM |
7739 | env->elr_el[new_el] = env->regs[15]; |
7740 | ||
7741 | aarch64_sync_32_to_64(env); | |
7742 | ||
7743 | env->condexec_bits = 0; | |
7744 | } | |
7745 | qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", | |
7746 | env->elr_el[new_el]); | |
7747 | ||
7748 | pstate_write(env, PSTATE_DAIF | new_mode); | |
7749 | env->aarch64 = 1; | |
7750 | aarch64_restore_sp(env, new_el); | |
7751 | ||
7752 | env->pc = addr; | |
7753 | ||
7754 | qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", | |
7755 | new_el, env->pc, pstate_read(env)); | |
966f758c PM |
7756 | } |
7757 | ||
904c04de PM |
7758 | static inline bool check_for_semihosting(CPUState *cs) |
7759 | { | |
7760 | /* Check whether this exception is a semihosting call; if so | |
7761 | * then handle it and return true; otherwise return false. | |
7762 | */ | |
7763 | ARMCPU *cpu = ARM_CPU(cs); | |
7764 | CPUARMState *env = &cpu->env; | |
7765 | ||
7766 | if (is_a64(env)) { | |
7767 | if (cs->exception_index == EXCP_SEMIHOST) { | |
7768 | /* This is always the 64-bit semihosting exception. | |
7769 | * The "is this usermode" and "is semihosting enabled" | |
7770 | * checks have been done at translate time. | |
7771 | */ | |
7772 | qemu_log_mask(CPU_LOG_INT, | |
7773 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
7774 | env->xregs[0]); | |
7775 | env->xregs[0] = do_arm_semihosting(env); | |
7776 | return true; | |
7777 | } | |
7778 | return false; | |
7779 | } else { | |
7780 | uint32_t imm; | |
7781 | ||
7782 | /* Only intercept calls from privileged modes, to provide some | |
7783 | * semblance of security. | |
7784 | */ | |
19a6e31c PM |
7785 | if (cs->exception_index != EXCP_SEMIHOST && |
7786 | (!semihosting_enabled() || | |
7787 | ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) { | |
904c04de PM |
7788 | return false; |
7789 | } | |
7790 | ||
7791 | switch (cs->exception_index) { | |
19a6e31c PM |
7792 | case EXCP_SEMIHOST: |
7793 | /* This is always a semihosting call; the "is this usermode" | |
7794 | * and "is semihosting enabled" checks have been done at | |
7795 | * translate time. | |
7796 | */ | |
7797 | break; | |
904c04de PM |
7798 | case EXCP_SWI: |
7799 | /* Check for semihosting interrupt. */ | |
7800 | if (env->thumb) { | |
f9fd40eb | 7801 | imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env)) |
904c04de PM |
7802 | & 0xff; |
7803 | if (imm == 0xab) { | |
7804 | break; | |
7805 | } | |
7806 | } else { | |
f9fd40eb | 7807 | imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env)) |
904c04de PM |
7808 | & 0xffffff; |
7809 | if (imm == 0x123456) { | |
7810 | break; | |
7811 | } | |
7812 | } | |
7813 | return false; | |
7814 | case EXCP_BKPT: | |
7815 | /* See if this is a semihosting syscall. */ | |
7816 | if (env->thumb) { | |
f9fd40eb | 7817 | imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) |
904c04de PM |
7818 | & 0xff; |
7819 | if (imm == 0xab) { | |
7820 | env->regs[15] += 2; | |
7821 | break; | |
7822 | } | |
7823 | } | |
7824 | return false; | |
7825 | default: | |
7826 | return false; | |
7827 | } | |
7828 | ||
7829 | qemu_log_mask(CPU_LOG_INT, | |
7830 | "...handling as semihosting call 0x%x\n", | |
7831 | env->regs[0]); | |
7832 | env->regs[0] = do_arm_semihosting(env); | |
7833 | return true; | |
7834 | } | |
7835 | } | |
7836 | ||
966f758c PM |
7837 | /* Handle a CPU exception for A and R profile CPUs. |
7838 | * Do any appropriate logging, handle PSCI calls, and then hand off | |
7839 | * to the AArch64-entry or AArch32-entry function depending on the | |
7840 | * target exception level's register width. | |
7841 | */ | |
7842 | void arm_cpu_do_interrupt(CPUState *cs) | |
7843 | { | |
7844 | ARMCPU *cpu = ARM_CPU(cs); | |
7845 | CPUARMState *env = &cpu->env; | |
7846 | unsigned int new_el = env->exception.target_el; | |
7847 | ||
531c60a9 | 7848 | assert(!arm_feature(env, ARM_FEATURE_M)); |
966f758c PM |
7849 | |
7850 | arm_log_exception(cs->exception_index); | |
7851 | qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), | |
7852 | new_el); | |
7853 | if (qemu_loglevel_mask(CPU_LOG_INT) | |
7854 | && !excp_is_internal(cs->exception_index)) { | |
6568da45 | 7855 | qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", |
966f758c PM |
7856 | env->exception.syndrome >> ARM_EL_EC_SHIFT, |
7857 | env->exception.syndrome); | |
7858 | } | |
7859 | ||
7860 | if (arm_is_psci_call(cpu, cs->exception_index)) { | |
7861 | arm_handle_psci_call(cpu); | |
7862 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | |
7863 | return; | |
7864 | } | |
7865 | ||
904c04de PM |
7866 | /* Semihosting semantics depend on the register width of the |
7867 | * code that caused the exception, not the target exception level, | |
7868 | * so must be handled here. | |
966f758c | 7869 | */ |
904c04de PM |
7870 | if (check_for_semihosting(cs)) { |
7871 | return; | |
7872 | } | |
7873 | ||
7874 | assert(!excp_is_internal(cs->exception_index)); | |
7875 | if (arm_el_is_aa64(env, new_el)) { | |
966f758c PM |
7876 | arm_cpu_do_interrupt_aarch64(cs); |
7877 | } else { | |
7878 | arm_cpu_do_interrupt_aarch32(cs); | |
7879 | } | |
f3a9b694 | 7880 | |
8d04fb55 JK |
7881 | /* Hooks may change global state so BQL should be held, also the |
7882 | * BQL needs to be held for any modification of | |
7883 | * cs->interrupt_request. | |
7884 | */ | |
7885 | g_assert(qemu_mutex_iothread_locked()); | |
7886 | ||
bd7d00fc PM |
7887 | arm_call_el_change_hook(cpu); |
7888 | ||
f3a9b694 PM |
7889 | if (!kvm_enabled()) { |
7890 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
7891 | } | |
7892 | } | |
0480f69a PM |
7893 | |
7894 | /* Return the exception level which controls this address translation regime */ | |
7895 | static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) | |
7896 | { | |
7897 | switch (mmu_idx) { | |
7898 | case ARMMMUIdx_S2NS: | |
7899 | case ARMMMUIdx_S1E2: | |
7900 | return 2; | |
7901 | case ARMMMUIdx_S1E3: | |
7902 | return 3; | |
7903 | case ARMMMUIdx_S1SE0: | |
7904 | return arm_el_is_aa64(env, 3) ? 1 : 3; | |
7905 | case ARMMMUIdx_S1SE1: | |
7906 | case ARMMMUIdx_S1NSE0: | |
7907 | case ARMMMUIdx_S1NSE1: | |
62593718 PM |
7908 | case ARMMMUIdx_MPrivNegPri: |
7909 | case ARMMMUIdx_MUserNegPri: | |
e7b921c2 PM |
7910 | case ARMMMUIdx_MPriv: |
7911 | case ARMMMUIdx_MUser: | |
62593718 PM |
7912 | case ARMMMUIdx_MSPrivNegPri: |
7913 | case ARMMMUIdx_MSUserNegPri: | |
66787c78 | 7914 | case ARMMMUIdx_MSPriv: |
66787c78 | 7915 | case ARMMMUIdx_MSUser: |
0480f69a PM |
7916 | return 1; |
7917 | default: | |
7918 | g_assert_not_reached(); | |
7919 | } | |
7920 | } | |
7921 | ||
7922 | /* Return the SCTLR value which controls this address translation regime */ | |
7923 | static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) | |
7924 | { | |
7925 | return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; | |
7926 | } | |
7927 | ||
7928 | /* Return true if the specified stage of address translation is disabled */ | |
7929 | static inline bool regime_translation_disabled(CPUARMState *env, | |
7930 | ARMMMUIdx mmu_idx) | |
7931 | { | |
29c483a5 | 7932 | if (arm_feature(env, ARM_FEATURE_M)) { |
ecf5e8ea | 7933 | switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & |
3bef7012 PM |
7934 | (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { |
7935 | case R_V7M_MPU_CTRL_ENABLE_MASK: | |
7936 | /* Enabled, but not for HardFault and NMI */ | |
62593718 | 7937 | return mmu_idx & ARM_MMU_IDX_M_NEGPRI; |
3bef7012 PM |
7938 | case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: |
7939 | /* Enabled for all cases */ | |
7940 | return false; | |
7941 | case 0: | |
7942 | default: | |
7943 | /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but | |
7944 | * we warned about that in armv7m_nvic.c when the guest set it. | |
7945 | */ | |
7946 | return true; | |
7947 | } | |
29c483a5 MD |
7948 | } |
7949 | ||
0480f69a PM |
7950 | if (mmu_idx == ARMMMUIdx_S2NS) { |
7951 | return (env->cp15.hcr_el2 & HCR_VM) == 0; | |
7952 | } | |
7953 | return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; | |
7954 | } | |
7955 | ||
73462ddd PC |
7956 | static inline bool regime_translation_big_endian(CPUARMState *env, |
7957 | ARMMMUIdx mmu_idx) | |
7958 | { | |
7959 | return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; | |
7960 | } | |
7961 | ||
0480f69a PM |
7962 | /* Return the TCR controlling this translation regime */ |
7963 | static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) | |
7964 | { | |
7965 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
68e9c2fe | 7966 | return &env->cp15.vtcr_el2; |
0480f69a PM |
7967 | } |
7968 | return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; | |
7969 | } | |
7970 | ||
8bd5c820 PM |
7971 | /* Convert a possible stage1+2 MMU index into the appropriate |
7972 | * stage 1 MMU index | |
7973 | */ | |
7974 | static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) | |
7975 | { | |
7976 | if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { | |
7977 | mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0); | |
7978 | } | |
7979 | return mmu_idx; | |
7980 | } | |
7981 | ||
86fb3fa4 TH |
7982 | /* Returns TBI0 value for current regime el */ |
7983 | uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx) | |
7984 | { | |
7985 | TCR *tcr; | |
7986 | uint32_t el; | |
7987 | ||
7988 | /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert | |
8bd5c820 PM |
7989 | * a stage 1+2 mmu index into the appropriate stage 1 mmu index. |
7990 | */ | |
7991 | mmu_idx = stage_1_mmu_idx(mmu_idx); | |
86fb3fa4 TH |
7992 | |
7993 | tcr = regime_tcr(env, mmu_idx); | |
7994 | el = regime_el(env, mmu_idx); | |
7995 | ||
7996 | if (el > 1) { | |
7997 | return extract64(tcr->raw_tcr, 20, 1); | |
7998 | } else { | |
7999 | return extract64(tcr->raw_tcr, 37, 1); | |
8000 | } | |
8001 | } | |
8002 | ||
8003 | /* Returns TBI1 value for current regime el */ | |
8004 | uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) | |
8005 | { | |
8006 | TCR *tcr; | |
8007 | uint32_t el; | |
8008 | ||
8009 | /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert | |
8bd5c820 PM |
8010 | * a stage 1+2 mmu index into the appropriate stage 1 mmu index. |
8011 | */ | |
8012 | mmu_idx = stage_1_mmu_idx(mmu_idx); | |
86fb3fa4 TH |
8013 | |
8014 | tcr = regime_tcr(env, mmu_idx); | |
8015 | el = regime_el(env, mmu_idx); | |
8016 | ||
8017 | if (el > 1) { | |
8018 | return 0; | |
8019 | } else { | |
8020 | return extract64(tcr->raw_tcr, 38, 1); | |
8021 | } | |
8022 | } | |
8023 | ||
aef878be GB |
8024 | /* Return the TTBR associated with this translation regime */ |
8025 | static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, | |
8026 | int ttbrn) | |
8027 | { | |
8028 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
b698e9cf | 8029 | return env->cp15.vttbr_el2; |
aef878be GB |
8030 | } |
8031 | if (ttbrn == 0) { | |
8032 | return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; | |
8033 | } else { | |
8034 | return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; | |
8035 | } | |
8036 | } | |
8037 | ||
0480f69a PM |
8038 | /* Return true if the translation regime is using LPAE format page tables */ |
8039 | static inline bool regime_using_lpae_format(CPUARMState *env, | |
8040 | ARMMMUIdx mmu_idx) | |
8041 | { | |
8042 | int el = regime_el(env, mmu_idx); | |
8043 | if (el == 2 || arm_el_is_aa64(env, el)) { | |
8044 | return true; | |
8045 | } | |
8046 | if (arm_feature(env, ARM_FEATURE_LPAE) | |
8047 | && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { | |
8048 | return true; | |
8049 | } | |
8050 | return false; | |
8051 | } | |
8052 | ||
deb2db99 AR |
8053 | /* Returns true if the stage 1 translation regime is using LPAE format page |
8054 | * tables. Used when raising alignment exceptions, whose FSR changes depending | |
8055 | * on whether the long or short descriptor format is in use. */ | |
8056 | bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) | |
30901475 | 8057 | { |
8bd5c820 | 8058 | mmu_idx = stage_1_mmu_idx(mmu_idx); |
deb2db99 | 8059 | |
30901475 AB |
8060 | return regime_using_lpae_format(env, mmu_idx); |
8061 | } | |
8062 | ||
0480f69a PM |
8063 | static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) |
8064 | { | |
8065 | switch (mmu_idx) { | |
8066 | case ARMMMUIdx_S1SE0: | |
8067 | case ARMMMUIdx_S1NSE0: | |
e7b921c2 | 8068 | case ARMMMUIdx_MUser: |
871bec7c | 8069 | case ARMMMUIdx_MSUser: |
62593718 PM |
8070 | case ARMMMUIdx_MUserNegPri: |
8071 | case ARMMMUIdx_MSUserNegPri: | |
0480f69a PM |
8072 | return true; |
8073 | default: | |
8074 | return false; | |
8075 | case ARMMMUIdx_S12NSE0: | |
8076 | case ARMMMUIdx_S12NSE1: | |
8077 | g_assert_not_reached(); | |
8078 | } | |
8079 | } | |
8080 | ||
0fbf5238 AJ |
8081 | /* Translate section/page access permissions to page |
8082 | * R/W protection flags | |
d76951b6 AJ |
8083 | * |
8084 | * @env: CPUARMState | |
8085 | * @mmu_idx: MMU index indicating required translation regime | |
8086 | * @ap: The 3-bit access permissions (AP[2:0]) | |
8087 | * @domain_prot: The 2-bit domain access permissions | |
0fbf5238 AJ |
8088 | */ |
8089 | static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, | |
8090 | int ap, int domain_prot) | |
8091 | { | |
554b0b09 PM |
8092 | bool is_user = regime_is_user(env, mmu_idx); |
8093 | ||
8094 | if (domain_prot == 3) { | |
8095 | return PAGE_READ | PAGE_WRITE; | |
8096 | } | |
8097 | ||
554b0b09 PM |
8098 | switch (ap) { |
8099 | case 0: | |
8100 | if (arm_feature(env, ARM_FEATURE_V7)) { | |
8101 | return 0; | |
8102 | } | |
554b0b09 PM |
8103 | switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) { |
8104 | case SCTLR_S: | |
8105 | return is_user ? 0 : PAGE_READ; | |
8106 | case SCTLR_R: | |
8107 | return PAGE_READ; | |
8108 | default: | |
8109 | return 0; | |
8110 | } | |
8111 | case 1: | |
8112 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
8113 | case 2: | |
87c3d486 | 8114 | if (is_user) { |
0fbf5238 | 8115 | return PAGE_READ; |
87c3d486 | 8116 | } else { |
554b0b09 | 8117 | return PAGE_READ | PAGE_WRITE; |
87c3d486 | 8118 | } |
554b0b09 PM |
8119 | case 3: |
8120 | return PAGE_READ | PAGE_WRITE; | |
8121 | case 4: /* Reserved. */ | |
8122 | return 0; | |
8123 | case 5: | |
0fbf5238 | 8124 | return is_user ? 0 : PAGE_READ; |
554b0b09 | 8125 | case 6: |
0fbf5238 | 8126 | return PAGE_READ; |
554b0b09 | 8127 | case 7: |
87c3d486 | 8128 | if (!arm_feature(env, ARM_FEATURE_V6K)) { |
554b0b09 | 8129 | return 0; |
87c3d486 | 8130 | } |
0fbf5238 | 8131 | return PAGE_READ; |
554b0b09 | 8132 | default: |
0fbf5238 | 8133 | g_assert_not_reached(); |
554b0b09 | 8134 | } |
b5ff1b31 FB |
8135 | } |
8136 | ||
d76951b6 AJ |
8137 | /* Translate section/page access permissions to page |
8138 | * R/W protection flags. | |
8139 | * | |
d76951b6 | 8140 | * @ap: The 2-bit simple AP (AP[2:1]) |
d8e052b3 | 8141 | * @is_user: TRUE if accessing from PL0 |
d76951b6 | 8142 | */ |
d8e052b3 | 8143 | static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user) |
d76951b6 | 8144 | { |
d76951b6 AJ |
8145 | switch (ap) { |
8146 | case 0: | |
8147 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
8148 | case 1: | |
8149 | return PAGE_READ | PAGE_WRITE; | |
8150 | case 2: | |
8151 | return is_user ? 0 : PAGE_READ; | |
8152 | case 3: | |
8153 | return PAGE_READ; | |
8154 | default: | |
8155 | g_assert_not_reached(); | |
8156 | } | |
8157 | } | |
8158 | ||
d8e052b3 AJ |
8159 | static inline int |
8160 | simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) | |
8161 | { | |
8162 | return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); | |
8163 | } | |
8164 | ||
6ab1a5ee EI |
8165 | /* Translate S2 section/page access permissions to protection flags |
8166 | * | |
8167 | * @env: CPUARMState | |
8168 | * @s2ap: The 2-bit stage2 access permissions (S2AP) | |
8169 | * @xn: XN (execute-never) bit | |
8170 | */ | |
8171 | static int get_S2prot(CPUARMState *env, int s2ap, int xn) | |
8172 | { | |
8173 | int prot = 0; | |
8174 | ||
8175 | if (s2ap & 1) { | |
8176 | prot |= PAGE_READ; | |
8177 | } | |
8178 | if (s2ap & 2) { | |
8179 | prot |= PAGE_WRITE; | |
8180 | } | |
8181 | if (!xn) { | |
dfda6837 SS |
8182 | if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { |
8183 | prot |= PAGE_EXEC; | |
8184 | } | |
6ab1a5ee EI |
8185 | } |
8186 | return prot; | |
8187 | } | |
8188 | ||
d8e052b3 AJ |
8189 | /* Translate section/page access permissions to protection flags |
8190 | * | |
8191 | * @env: CPUARMState | |
8192 | * @mmu_idx: MMU index indicating required translation regime | |
8193 | * @is_aa64: TRUE if AArch64 | |
8194 | * @ap: The 2-bit simple AP (AP[2:1]) | |
8195 | * @ns: NS (non-secure) bit | |
8196 | * @xn: XN (execute-never) bit | |
8197 | * @pxn: PXN (privileged execute-never) bit | |
8198 | */ | |
8199 | static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, | |
8200 | int ap, int ns, int xn, int pxn) | |
8201 | { | |
8202 | bool is_user = regime_is_user(env, mmu_idx); | |
8203 | int prot_rw, user_rw; | |
8204 | bool have_wxn; | |
8205 | int wxn = 0; | |
8206 | ||
8207 | assert(mmu_idx != ARMMMUIdx_S2NS); | |
8208 | ||
8209 | user_rw = simple_ap_to_rw_prot_is_user(ap, true); | |
8210 | if (is_user) { | |
8211 | prot_rw = user_rw; | |
8212 | } else { | |
8213 | prot_rw = simple_ap_to_rw_prot_is_user(ap, false); | |
8214 | } | |
8215 | ||
8216 | if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { | |
8217 | return prot_rw; | |
8218 | } | |
8219 | ||
8220 | /* TODO have_wxn should be replaced with | |
8221 | * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) | |
8222 | * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE | |
8223 | * compatible processors have EL2, which is required for [U]WXN. | |
8224 | */ | |
8225 | have_wxn = arm_feature(env, ARM_FEATURE_LPAE); | |
8226 | ||
8227 | if (have_wxn) { | |
8228 | wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN; | |
8229 | } | |
8230 | ||
8231 | if (is_aa64) { | |
8232 | switch (regime_el(env, mmu_idx)) { | |
8233 | case 1: | |
8234 | if (!is_user) { | |
8235 | xn = pxn || (user_rw & PAGE_WRITE); | |
8236 | } | |
8237 | break; | |
8238 | case 2: | |
8239 | case 3: | |
8240 | break; | |
8241 | } | |
8242 | } else if (arm_feature(env, ARM_FEATURE_V7)) { | |
8243 | switch (regime_el(env, mmu_idx)) { | |
8244 | case 1: | |
8245 | case 3: | |
8246 | if (is_user) { | |
8247 | xn = xn || !(user_rw & PAGE_READ); | |
8248 | } else { | |
8249 | int uwxn = 0; | |
8250 | if (have_wxn) { | |
8251 | uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN; | |
8252 | } | |
8253 | xn = xn || !(prot_rw & PAGE_READ) || pxn || | |
8254 | (uwxn && (user_rw & PAGE_WRITE)); | |
8255 | } | |
8256 | break; | |
8257 | case 2: | |
8258 | break; | |
8259 | } | |
8260 | } else { | |
8261 | xn = wxn = 0; | |
8262 | } | |
8263 | ||
8264 | if (xn || (wxn && (prot_rw & PAGE_WRITE))) { | |
8265 | return prot_rw; | |
8266 | } | |
8267 | return prot_rw | PAGE_EXEC; | |
8268 | } | |
8269 | ||
0480f69a PM |
8270 | static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, |
8271 | uint32_t *table, uint32_t address) | |
b2fa1797 | 8272 | { |
0480f69a | 8273 | /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ |
0480f69a | 8274 | TCR *tcr = regime_tcr(env, mmu_idx); |
11f136ee | 8275 | |
11f136ee FA |
8276 | if (address & tcr->mask) { |
8277 | if (tcr->raw_tcr & TTBCR_PD1) { | |
e389be16 FA |
8278 | /* Translation table walk disabled for TTBR1 */ |
8279 | return false; | |
8280 | } | |
aef878be | 8281 | *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; |
e389be16 | 8282 | } else { |
11f136ee | 8283 | if (tcr->raw_tcr & TTBCR_PD0) { |
e389be16 FA |
8284 | /* Translation table walk disabled for TTBR0 */ |
8285 | return false; | |
8286 | } | |
aef878be | 8287 | *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; |
e389be16 FA |
8288 | } |
8289 | *table |= (address >> 18) & 0x3ffc; | |
8290 | return true; | |
b2fa1797 PB |
8291 | } |
8292 | ||
37785977 EI |
8293 | /* Translate a S1 pagetable walk through S2 if needed. */ |
8294 | static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, | |
8295 | hwaddr addr, MemTxAttrs txattrs, | |
37785977 EI |
8296 | ARMMMUFaultInfo *fi) |
8297 | { | |
8298 | if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) && | |
8299 | !regime_translation_disabled(env, ARMMMUIdx_S2NS)) { | |
8300 | target_ulong s2size; | |
8301 | hwaddr s2pa; | |
8302 | int s2prot; | |
8303 | int ret; | |
8304 | ||
8305 | ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, | |
da909b2c | 8306 | &txattrs, &s2prot, &s2size, fi, NULL); |
37785977 EI |
8307 | if (ret) { |
8308 | fi->s2addr = addr; | |
8309 | fi->stage2 = true; | |
8310 | fi->s1ptw = true; | |
8311 | return ~0; | |
8312 | } | |
8313 | addr = s2pa; | |
8314 | } | |
8315 | return addr; | |
8316 | } | |
8317 | ||
ebca90e4 PM |
8318 | /* All loads done in the course of a page table walk go through here. |
8319 | * TODO: rather than ignoring errors from physical memory reads (which | |
8320 | * are external aborts in ARM terminology) we should propagate this | |
8321 | * error out so that we can turn it into a Data Abort if this walk | |
8322 | * was being done for a CPU load/store or an address translation instruction | |
8323 | * (but not if it was for a debug access). | |
8324 | */ | |
a614e698 | 8325 | static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, |
3795a6de | 8326 | ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) |
ebca90e4 | 8327 | { |
a614e698 EI |
8328 | ARMCPU *cpu = ARM_CPU(cs); |
8329 | CPUARMState *env = &cpu->env; | |
ebca90e4 | 8330 | MemTxAttrs attrs = {}; |
5ce4ff65 | 8331 | AddressSpace *as; |
ebca90e4 PM |
8332 | |
8333 | attrs.secure = is_secure; | |
5ce4ff65 | 8334 | as = arm_addressspace(cs, attrs); |
3795a6de | 8335 | addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi); |
a614e698 EI |
8336 | if (fi->s1ptw) { |
8337 | return 0; | |
8338 | } | |
73462ddd PC |
8339 | if (regime_translation_big_endian(env, mmu_idx)) { |
8340 | return address_space_ldl_be(as, addr, attrs, NULL); | |
8341 | } else { | |
8342 | return address_space_ldl_le(as, addr, attrs, NULL); | |
8343 | } | |
ebca90e4 PM |
8344 | } |
8345 | ||
37785977 | 8346 | static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, |
3795a6de | 8347 | ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) |
ebca90e4 | 8348 | { |
37785977 EI |
8349 | ARMCPU *cpu = ARM_CPU(cs); |
8350 | CPUARMState *env = &cpu->env; | |
ebca90e4 | 8351 | MemTxAttrs attrs = {}; |
5ce4ff65 | 8352 | AddressSpace *as; |
ebca90e4 PM |
8353 | |
8354 | attrs.secure = is_secure; | |
5ce4ff65 | 8355 | as = arm_addressspace(cs, attrs); |
3795a6de | 8356 | addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi); |
37785977 EI |
8357 | if (fi->s1ptw) { |
8358 | return 0; | |
8359 | } | |
73462ddd PC |
8360 | if (regime_translation_big_endian(env, mmu_idx)) { |
8361 | return address_space_ldq_be(as, addr, attrs, NULL); | |
8362 | } else { | |
8363 | return address_space_ldq_le(as, addr, attrs, NULL); | |
8364 | } | |
ebca90e4 PM |
8365 | } |
8366 | ||
b7cc4e82 | 8367 | static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, |
03ae85f8 | 8368 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
b7cc4e82 | 8369 | hwaddr *phys_ptr, int *prot, |
f989983e | 8370 | target_ulong *page_size, |
e14b5a23 | 8371 | ARMMMUFaultInfo *fi) |
b5ff1b31 | 8372 | { |
70d74660 | 8373 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
f989983e | 8374 | int level = 1; |
b5ff1b31 FB |
8375 | uint32_t table; |
8376 | uint32_t desc; | |
8377 | int type; | |
8378 | int ap; | |
e389be16 | 8379 | int domain = 0; |
dd4ebc2e | 8380 | int domain_prot; |
a8170e5e | 8381 | hwaddr phys_addr; |
0480f69a | 8382 | uint32_t dacr; |
b5ff1b31 | 8383 | |
9ee6e8bb PB |
8384 | /* Pagetable walk. */ |
8385 | /* Lookup l1 descriptor. */ | |
0480f69a | 8386 | if (!get_level1_table_address(env, mmu_idx, &table, address)) { |
e389be16 | 8387 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ |
f989983e | 8388 | fi->type = ARMFault_Translation; |
e389be16 FA |
8389 | goto do_fault; |
8390 | } | |
a614e698 | 8391 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 8392 | mmu_idx, fi); |
9ee6e8bb | 8393 | type = (desc & 3); |
dd4ebc2e | 8394 | domain = (desc >> 5) & 0x0f; |
0480f69a PM |
8395 | if (regime_el(env, mmu_idx) == 1) { |
8396 | dacr = env->cp15.dacr_ns; | |
8397 | } else { | |
8398 | dacr = env->cp15.dacr_s; | |
8399 | } | |
8400 | domain_prot = (dacr >> (domain * 2)) & 3; | |
9ee6e8bb | 8401 | if (type == 0) { |
601d70b9 | 8402 | /* Section translation fault. */ |
f989983e | 8403 | fi->type = ARMFault_Translation; |
9ee6e8bb PB |
8404 | goto do_fault; |
8405 | } | |
f989983e PM |
8406 | if (type != 2) { |
8407 | level = 2; | |
8408 | } | |
dd4ebc2e | 8409 | if (domain_prot == 0 || domain_prot == 2) { |
f989983e | 8410 | fi->type = ARMFault_Domain; |
9ee6e8bb PB |
8411 | goto do_fault; |
8412 | } | |
8413 | if (type == 2) { | |
8414 | /* 1Mb section. */ | |
8415 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
8416 | ap = (desc >> 10) & 3; | |
d4c430a8 | 8417 | *page_size = 1024 * 1024; |
9ee6e8bb PB |
8418 | } else { |
8419 | /* Lookup l2 entry. */ | |
554b0b09 PM |
8420 | if (type == 1) { |
8421 | /* Coarse pagetable. */ | |
8422 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
8423 | } else { | |
8424 | /* Fine pagetable. */ | |
8425 | table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); | |
8426 | } | |
a614e698 | 8427 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 8428 | mmu_idx, fi); |
9ee6e8bb PB |
8429 | switch (desc & 3) { |
8430 | case 0: /* Page translation fault. */ | |
f989983e | 8431 | fi->type = ARMFault_Translation; |
9ee6e8bb PB |
8432 | goto do_fault; |
8433 | case 1: /* 64k page. */ | |
8434 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
8435 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
d4c430a8 | 8436 | *page_size = 0x10000; |
ce819861 | 8437 | break; |
9ee6e8bb PB |
8438 | case 2: /* 4k page. */ |
8439 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
c10f7fc3 | 8440 | ap = (desc >> (4 + ((address >> 9) & 6))) & 3; |
d4c430a8 | 8441 | *page_size = 0x1000; |
ce819861 | 8442 | break; |
fc1891c7 | 8443 | case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ |
554b0b09 | 8444 | if (type == 1) { |
fc1891c7 PM |
8445 | /* ARMv6/XScale extended small page format */ |
8446 | if (arm_feature(env, ARM_FEATURE_XSCALE) | |
8447 | || arm_feature(env, ARM_FEATURE_V6)) { | |
554b0b09 | 8448 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
fc1891c7 | 8449 | *page_size = 0x1000; |
554b0b09 | 8450 | } else { |
fc1891c7 PM |
8451 | /* UNPREDICTABLE in ARMv5; we choose to take a |
8452 | * page translation fault. | |
8453 | */ | |
f989983e | 8454 | fi->type = ARMFault_Translation; |
554b0b09 PM |
8455 | goto do_fault; |
8456 | } | |
8457 | } else { | |
8458 | phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); | |
fc1891c7 | 8459 | *page_size = 0x400; |
554b0b09 | 8460 | } |
9ee6e8bb | 8461 | ap = (desc >> 4) & 3; |
ce819861 PB |
8462 | break; |
8463 | default: | |
9ee6e8bb PB |
8464 | /* Never happens, but compiler isn't smart enough to tell. */ |
8465 | abort(); | |
ce819861 | 8466 | } |
9ee6e8bb | 8467 | } |
0fbf5238 AJ |
8468 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); |
8469 | *prot |= *prot ? PAGE_EXEC : 0; | |
8470 | if (!(*prot & (1 << access_type))) { | |
9ee6e8bb | 8471 | /* Access permission fault. */ |
f989983e | 8472 | fi->type = ARMFault_Permission; |
9ee6e8bb PB |
8473 | goto do_fault; |
8474 | } | |
8475 | *phys_ptr = phys_addr; | |
b7cc4e82 | 8476 | return false; |
9ee6e8bb | 8477 | do_fault: |
f989983e PM |
8478 | fi->domain = domain; |
8479 | fi->level = level; | |
b7cc4e82 | 8480 | return true; |
9ee6e8bb PB |
8481 | } |
8482 | ||
b7cc4e82 | 8483 | static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, |
03ae85f8 | 8484 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
b7cc4e82 | 8485 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, |
f06cf243 | 8486 | target_ulong *page_size, ARMMMUFaultInfo *fi) |
9ee6e8bb | 8487 | { |
70d74660 | 8488 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
f06cf243 | 8489 | int level = 1; |
9ee6e8bb PB |
8490 | uint32_t table; |
8491 | uint32_t desc; | |
8492 | uint32_t xn; | |
de9b05b8 | 8493 | uint32_t pxn = 0; |
9ee6e8bb PB |
8494 | int type; |
8495 | int ap; | |
de9b05b8 | 8496 | int domain = 0; |
dd4ebc2e | 8497 | int domain_prot; |
a8170e5e | 8498 | hwaddr phys_addr; |
0480f69a | 8499 | uint32_t dacr; |
8bf5b6a9 | 8500 | bool ns; |
9ee6e8bb PB |
8501 | |
8502 | /* Pagetable walk. */ | |
8503 | /* Lookup l1 descriptor. */ | |
0480f69a | 8504 | if (!get_level1_table_address(env, mmu_idx, &table, address)) { |
e389be16 | 8505 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ |
f06cf243 | 8506 | fi->type = ARMFault_Translation; |
e389be16 FA |
8507 | goto do_fault; |
8508 | } | |
a614e698 | 8509 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 8510 | mmu_idx, fi); |
9ee6e8bb | 8511 | type = (desc & 3); |
de9b05b8 PM |
8512 | if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { |
8513 | /* Section translation fault, or attempt to use the encoding | |
8514 | * which is Reserved on implementations without PXN. | |
8515 | */ | |
f06cf243 | 8516 | fi->type = ARMFault_Translation; |
9ee6e8bb | 8517 | goto do_fault; |
de9b05b8 PM |
8518 | } |
8519 | if ((type == 1) || !(desc & (1 << 18))) { | |
8520 | /* Page or Section. */ | |
dd4ebc2e | 8521 | domain = (desc >> 5) & 0x0f; |
9ee6e8bb | 8522 | } |
0480f69a PM |
8523 | if (regime_el(env, mmu_idx) == 1) { |
8524 | dacr = env->cp15.dacr_ns; | |
8525 | } else { | |
8526 | dacr = env->cp15.dacr_s; | |
8527 | } | |
f06cf243 PM |
8528 | if (type == 1) { |
8529 | level = 2; | |
8530 | } | |
0480f69a | 8531 | domain_prot = (dacr >> (domain * 2)) & 3; |
dd4ebc2e | 8532 | if (domain_prot == 0 || domain_prot == 2) { |
f06cf243 PM |
8533 | /* Section or Page domain fault */ |
8534 | fi->type = ARMFault_Domain; | |
9ee6e8bb PB |
8535 | goto do_fault; |
8536 | } | |
de9b05b8 | 8537 | if (type != 1) { |
9ee6e8bb PB |
8538 | if (desc & (1 << 18)) { |
8539 | /* Supersection. */ | |
8540 | phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); | |
4e42a6ca SF |
8541 | phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32; |
8542 | phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36; | |
d4c430a8 | 8543 | *page_size = 0x1000000; |
b5ff1b31 | 8544 | } else { |
9ee6e8bb PB |
8545 | /* Section. */ |
8546 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
d4c430a8 | 8547 | *page_size = 0x100000; |
b5ff1b31 | 8548 | } |
9ee6e8bb PB |
8549 | ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
8550 | xn = desc & (1 << 4); | |
de9b05b8 | 8551 | pxn = desc & 1; |
8bf5b6a9 | 8552 | ns = extract32(desc, 19, 1); |
9ee6e8bb | 8553 | } else { |
de9b05b8 PM |
8554 | if (arm_feature(env, ARM_FEATURE_PXN)) { |
8555 | pxn = (desc >> 2) & 1; | |
8556 | } | |
8bf5b6a9 | 8557 | ns = extract32(desc, 3, 1); |
9ee6e8bb PB |
8558 | /* Lookup l2 entry. */ |
8559 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
a614e698 | 8560 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 8561 | mmu_idx, fi); |
9ee6e8bb PB |
8562 | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
8563 | switch (desc & 3) { | |
8564 | case 0: /* Page translation fault. */ | |
f06cf243 | 8565 | fi->type = ARMFault_Translation; |
b5ff1b31 | 8566 | goto do_fault; |
9ee6e8bb PB |
8567 | case 1: /* 64k page. */ |
8568 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
8569 | xn = desc & (1 << 15); | |
d4c430a8 | 8570 | *page_size = 0x10000; |
9ee6e8bb PB |
8571 | break; |
8572 | case 2: case 3: /* 4k page. */ | |
8573 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
8574 | xn = desc & 1; | |
d4c430a8 | 8575 | *page_size = 0x1000; |
9ee6e8bb PB |
8576 | break; |
8577 | default: | |
8578 | /* Never happens, but compiler isn't smart enough to tell. */ | |
8579 | abort(); | |
b5ff1b31 | 8580 | } |
9ee6e8bb | 8581 | } |
dd4ebc2e | 8582 | if (domain_prot == 3) { |
c0034328 JR |
8583 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
8584 | } else { | |
0480f69a | 8585 | if (pxn && !regime_is_user(env, mmu_idx)) { |
de9b05b8 PM |
8586 | xn = 1; |
8587 | } | |
f06cf243 PM |
8588 | if (xn && access_type == MMU_INST_FETCH) { |
8589 | fi->type = ARMFault_Permission; | |
c0034328 | 8590 | goto do_fault; |
f06cf243 | 8591 | } |
9ee6e8bb | 8592 | |
d76951b6 AJ |
8593 | if (arm_feature(env, ARM_FEATURE_V6K) && |
8594 | (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { | |
8595 | /* The simplified model uses AP[0] as an access control bit. */ | |
8596 | if ((ap & 1) == 0) { | |
8597 | /* Access flag fault. */ | |
f06cf243 | 8598 | fi->type = ARMFault_AccessFlag; |
d76951b6 AJ |
8599 | goto do_fault; |
8600 | } | |
8601 | *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); | |
8602 | } else { | |
8603 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); | |
c0034328 | 8604 | } |
0fbf5238 AJ |
8605 | if (*prot && !xn) { |
8606 | *prot |= PAGE_EXEC; | |
8607 | } | |
8608 | if (!(*prot & (1 << access_type))) { | |
c0034328 | 8609 | /* Access permission fault. */ |
f06cf243 | 8610 | fi->type = ARMFault_Permission; |
c0034328 JR |
8611 | goto do_fault; |
8612 | } | |
3ad493fc | 8613 | } |
8bf5b6a9 PM |
8614 | if (ns) { |
8615 | /* The NS bit will (as required by the architecture) have no effect if | |
8616 | * the CPU doesn't support TZ or this is a non-secure translation | |
8617 | * regime, because the attribute will already be non-secure. | |
8618 | */ | |
8619 | attrs->secure = false; | |
8620 | } | |
9ee6e8bb | 8621 | *phys_ptr = phys_addr; |
b7cc4e82 | 8622 | return false; |
b5ff1b31 | 8623 | do_fault: |
f06cf243 PM |
8624 | fi->domain = domain; |
8625 | fi->level = level; | |
b7cc4e82 | 8626 | return true; |
b5ff1b31 FB |
8627 | } |
8628 | ||
1853d5a9 | 8629 | /* |
a0e966c9 | 8630 | * check_s2_mmu_setup |
1853d5a9 EI |
8631 | * @cpu: ARMCPU |
8632 | * @is_aa64: True if the translation regime is in AArch64 state | |
8633 | * @startlevel: Suggested starting level | |
8634 | * @inputsize: Bitsize of IPAs | |
8635 | * @stride: Page-table stride (See the ARM ARM) | |
8636 | * | |
a0e966c9 EI |
8637 | * Returns true if the suggested S2 translation parameters are OK and |
8638 | * false otherwise. | |
1853d5a9 | 8639 | */ |
a0e966c9 EI |
8640 | static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, |
8641 | int inputsize, int stride) | |
1853d5a9 | 8642 | { |
98d68ec2 EI |
8643 | const int grainsize = stride + 3; |
8644 | int startsizecheck; | |
8645 | ||
1853d5a9 EI |
8646 | /* Negative levels are never allowed. */ |
8647 | if (level < 0) { | |
8648 | return false; | |
8649 | } | |
8650 | ||
98d68ec2 EI |
8651 | startsizecheck = inputsize - ((3 - level) * stride + grainsize); |
8652 | if (startsizecheck < 1 || startsizecheck > stride + 4) { | |
8653 | return false; | |
8654 | } | |
8655 | ||
1853d5a9 | 8656 | if (is_aa64) { |
3526423e | 8657 | CPUARMState *env = &cpu->env; |
1853d5a9 EI |
8658 | unsigned int pamax = arm_pamax(cpu); |
8659 | ||
8660 | switch (stride) { | |
8661 | case 13: /* 64KB Pages. */ | |
8662 | if (level == 0 || (level == 1 && pamax <= 42)) { | |
8663 | return false; | |
8664 | } | |
8665 | break; | |
8666 | case 11: /* 16KB Pages. */ | |
8667 | if (level == 0 || (level == 1 && pamax <= 40)) { | |
8668 | return false; | |
8669 | } | |
8670 | break; | |
8671 | case 9: /* 4KB Pages. */ | |
8672 | if (level == 0 && pamax <= 42) { | |
8673 | return false; | |
8674 | } | |
8675 | break; | |
8676 | default: | |
8677 | g_assert_not_reached(); | |
8678 | } | |
3526423e EI |
8679 | |
8680 | /* Inputsize checks. */ | |
8681 | if (inputsize > pamax && | |
8682 | (arm_el_is_aa64(env, 1) || inputsize > 40)) { | |
8683 | /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ | |
8684 | return false; | |
8685 | } | |
1853d5a9 | 8686 | } else { |
1853d5a9 EI |
8687 | /* AArch32 only supports 4KB pages. Assert on that. */ |
8688 | assert(stride == 9); | |
8689 | ||
8690 | if (level == 0) { | |
8691 | return false; | |
8692 | } | |
1853d5a9 EI |
8693 | } |
8694 | return true; | |
8695 | } | |
8696 | ||
5b2d261d AB |
8697 | /* Translate from the 4-bit stage 2 representation of |
8698 | * memory attributes (without cache-allocation hints) to | |
8699 | * the 8-bit representation of the stage 1 MAIR registers | |
8700 | * (which includes allocation hints). | |
8701 | * | |
8702 | * ref: shared/translation/attrs/S2AttrDecode() | |
8703 | * .../S2ConvertAttrsHints() | |
8704 | */ | |
8705 | static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) | |
8706 | { | |
8707 | uint8_t hiattr = extract32(s2attrs, 2, 2); | |
8708 | uint8_t loattr = extract32(s2attrs, 0, 2); | |
8709 | uint8_t hihint = 0, lohint = 0; | |
8710 | ||
8711 | if (hiattr != 0) { /* normal memory */ | |
8712 | if ((env->cp15.hcr_el2 & HCR_CD) != 0) { /* cache disabled */ | |
8713 | hiattr = loattr = 1; /* non-cacheable */ | |
8714 | } else { | |
8715 | if (hiattr != 1) { /* Write-through or write-back */ | |
8716 | hihint = 3; /* RW allocate */ | |
8717 | } | |
8718 | if (loattr != 1) { /* Write-through or write-back */ | |
8719 | lohint = 3; /* RW allocate */ | |
8720 | } | |
8721 | } | |
8722 | } | |
8723 | ||
8724 | return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; | |
8725 | } | |
8726 | ||
b7cc4e82 | 8727 | static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
03ae85f8 | 8728 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
b7cc4e82 | 8729 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, |
da909b2c | 8730 | target_ulong *page_size_ptr, |
5b2d261d | 8731 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) |
3dde962f | 8732 | { |
1853d5a9 EI |
8733 | ARMCPU *cpu = arm_env_get_cpu(env); |
8734 | CPUState *cs = CPU(cpu); | |
3dde962f | 8735 | /* Read an LPAE long-descriptor translation table. */ |
da909b2c | 8736 | ARMFaultType fault_type = ARMFault_Translation; |
1b4093ea | 8737 | uint32_t level; |
0c5fbf3b | 8738 | uint32_t epd = 0; |
1f4c8c18 | 8739 | int32_t t0sz, t1sz; |
2c8dd318 | 8740 | uint32_t tg; |
3dde962f PM |
8741 | uint64_t ttbr; |
8742 | int ttbr_select; | |
dddb5223 | 8743 | hwaddr descaddr, indexmask, indexmask_grainsize; |
3dde962f PM |
8744 | uint32_t tableattrs; |
8745 | target_ulong page_size; | |
8746 | uint32_t attrs; | |
973a5434 | 8747 | int32_t stride = 9; |
6e99f762 | 8748 | int32_t addrsize; |
4ca6a051 | 8749 | int inputsize; |
2c8dd318 | 8750 | int32_t tbi = 0; |
0480f69a | 8751 | TCR *tcr = regime_tcr(env, mmu_idx); |
d8e052b3 | 8752 | int ap, ns, xn, pxn; |
88e8add8 GB |
8753 | uint32_t el = regime_el(env, mmu_idx); |
8754 | bool ttbr1_valid = true; | |
6109769a | 8755 | uint64_t descaddrmask; |
6e99f762 | 8756 | bool aarch64 = arm_el_is_aa64(env, el); |
0480f69a PM |
8757 | |
8758 | /* TODO: | |
88e8add8 GB |
8759 | * This code does not handle the different format TCR for VTCR_EL2. |
8760 | * This code also does not support shareability levels. | |
8761 | * Attribute and permission bit handling should also be checked when adding | |
8762 | * support for those page table walks. | |
0480f69a | 8763 | */ |
6e99f762 | 8764 | if (aarch64) { |
1b4093ea | 8765 | level = 0; |
6e99f762 | 8766 | addrsize = 64; |
88e8add8 | 8767 | if (el > 1) { |
1edee470 EI |
8768 | if (mmu_idx != ARMMMUIdx_S2NS) { |
8769 | tbi = extract64(tcr->raw_tcr, 20, 1); | |
8770 | } | |
88e8add8 GB |
8771 | } else { |
8772 | if (extract64(address, 55, 1)) { | |
8773 | tbi = extract64(tcr->raw_tcr, 38, 1); | |
8774 | } else { | |
8775 | tbi = extract64(tcr->raw_tcr, 37, 1); | |
8776 | } | |
8777 | } | |
2c8dd318 | 8778 | tbi *= 8; |
88e8add8 GB |
8779 | |
8780 | /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it | |
8781 | * invalid. | |
8782 | */ | |
8783 | if (el > 1) { | |
8784 | ttbr1_valid = false; | |
8785 | } | |
d0a2cbce | 8786 | } else { |
1b4093ea | 8787 | level = 1; |
6e99f762 | 8788 | addrsize = 32; |
d0a2cbce PM |
8789 | /* There is no TTBR1 for EL2 */ |
8790 | if (el == 2) { | |
8791 | ttbr1_valid = false; | |
8792 | } | |
2c8dd318 | 8793 | } |
3dde962f PM |
8794 | |
8795 | /* Determine whether this address is in the region controlled by | |
8796 | * TTBR0 or TTBR1 (or if it is in neither region and should fault). | |
8797 | * This is a Non-secure PL0/1 stage 1 translation, so controlled by | |
8798 | * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: | |
8799 | */ | |
6e99f762 | 8800 | if (aarch64) { |
4ee38098 EI |
8801 | /* AArch64 translation. */ |
8802 | t0sz = extract32(tcr->raw_tcr, 0, 6); | |
2c8dd318 RH |
8803 | t0sz = MIN(t0sz, 39); |
8804 | t0sz = MAX(t0sz, 16); | |
4ee38098 EI |
8805 | } else if (mmu_idx != ARMMMUIdx_S2NS) { |
8806 | /* AArch32 stage 1 translation. */ | |
8807 | t0sz = extract32(tcr->raw_tcr, 0, 3); | |
8808 | } else { | |
8809 | /* AArch32 stage 2 translation. */ | |
8810 | bool sext = extract32(tcr->raw_tcr, 4, 1); | |
8811 | bool sign = extract32(tcr->raw_tcr, 3, 1); | |
6e99f762 SS |
8812 | /* Address size is 40-bit for a stage 2 translation, |
8813 | * and t0sz can be negative (from -8 to 7), | |
8814 | * so we need to adjust it to use the TTBR selecting logic below. | |
8815 | */ | |
8816 | addrsize = 40; | |
8817 | t0sz = sextract32(tcr->raw_tcr, 0, 4) + 8; | |
4ee38098 EI |
8818 | |
8819 | /* If the sign-extend bit is not the same as t0sz[3], the result | |
8820 | * is unpredictable. Flag this as a guest error. */ | |
8821 | if (sign != sext) { | |
8822 | qemu_log_mask(LOG_GUEST_ERROR, | |
39cba610 | 8823 | "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); |
4ee38098 | 8824 | } |
2c8dd318 | 8825 | } |
1f4c8c18 | 8826 | t1sz = extract32(tcr->raw_tcr, 16, 6); |
6e99f762 | 8827 | if (aarch64) { |
2c8dd318 RH |
8828 | t1sz = MIN(t1sz, 39); |
8829 | t1sz = MAX(t1sz, 16); | |
8830 | } | |
6e99f762 | 8831 | if (t0sz && !extract64(address, addrsize - t0sz, t0sz - tbi)) { |
3dde962f PM |
8832 | /* there is a ttbr0 region and we are in it (high bits all zero) */ |
8833 | ttbr_select = 0; | |
88e8add8 | 8834 | } else if (ttbr1_valid && t1sz && |
6e99f762 | 8835 | !extract64(~address, addrsize - t1sz, t1sz - tbi)) { |
3dde962f PM |
8836 | /* there is a ttbr1 region and we are in it (high bits all one) */ |
8837 | ttbr_select = 1; | |
8838 | } else if (!t0sz) { | |
8839 | /* ttbr0 region is "everything not in the ttbr1 region" */ | |
8840 | ttbr_select = 0; | |
88e8add8 | 8841 | } else if (!t1sz && ttbr1_valid) { |
3dde962f PM |
8842 | /* ttbr1 region is "everything not in the ttbr0 region" */ |
8843 | ttbr_select = 1; | |
8844 | } else { | |
8845 | /* in the gap between the two regions, this is a Translation fault */ | |
da909b2c | 8846 | fault_type = ARMFault_Translation; |
3dde962f PM |
8847 | goto do_fault; |
8848 | } | |
8849 | ||
8850 | /* Note that QEMU ignores shareability and cacheability attributes, | |
8851 | * so we don't need to do anything with the SH, ORGN, IRGN fields | |
8852 | * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the | |
8853 | * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently | |
8854 | * implement any ASID-like capability so we can ignore it (instead | |
8855 | * we will always flush the TLB any time the ASID is changed). | |
8856 | */ | |
8857 | if (ttbr_select == 0) { | |
aef878be | 8858 | ttbr = regime_ttbr(env, mmu_idx, 0); |
0c5fbf3b EI |
8859 | if (el < 2) { |
8860 | epd = extract32(tcr->raw_tcr, 7, 1); | |
8861 | } | |
6e99f762 | 8862 | inputsize = addrsize - t0sz; |
2c8dd318 | 8863 | |
11f136ee | 8864 | tg = extract32(tcr->raw_tcr, 14, 2); |
2c8dd318 | 8865 | if (tg == 1) { /* 64KB pages */ |
973a5434 | 8866 | stride = 13; |
2c8dd318 RH |
8867 | } |
8868 | if (tg == 2) { /* 16KB pages */ | |
973a5434 | 8869 | stride = 11; |
2c8dd318 | 8870 | } |
3dde962f | 8871 | } else { |
88e8add8 GB |
8872 | /* We should only be here if TTBR1 is valid */ |
8873 | assert(ttbr1_valid); | |
8874 | ||
aef878be | 8875 | ttbr = regime_ttbr(env, mmu_idx, 1); |
11f136ee | 8876 | epd = extract32(tcr->raw_tcr, 23, 1); |
6e99f762 | 8877 | inputsize = addrsize - t1sz; |
2c8dd318 | 8878 | |
11f136ee | 8879 | tg = extract32(tcr->raw_tcr, 30, 2); |
2c8dd318 | 8880 | if (tg == 3) { /* 64KB pages */ |
973a5434 | 8881 | stride = 13; |
2c8dd318 RH |
8882 | } |
8883 | if (tg == 1) { /* 16KB pages */ | |
973a5434 | 8884 | stride = 11; |
2c8dd318 | 8885 | } |
3dde962f PM |
8886 | } |
8887 | ||
0480f69a | 8888 | /* Here we should have set up all the parameters for the translation: |
6e99f762 | 8889 | * inputsize, ttbr, epd, stride, tbi |
0480f69a PM |
8890 | */ |
8891 | ||
3dde962f | 8892 | if (epd) { |
88e8add8 GB |
8893 | /* Translation table walk disabled => Translation fault on TLB miss |
8894 | * Note: This is always 0 on 64-bit EL2 and EL3. | |
8895 | */ | |
3dde962f PM |
8896 | goto do_fault; |
8897 | } | |
8898 | ||
1853d5a9 EI |
8899 | if (mmu_idx != ARMMMUIdx_S2NS) { |
8900 | /* The starting level depends on the virtual address size (which can | |
8901 | * be up to 48 bits) and the translation granule size. It indicates | |
8902 | * the number of strides (stride bits at a time) needed to | |
8903 | * consume the bits of the input address. In the pseudocode this is: | |
8904 | * level = 4 - RoundUp((inputsize - grainsize) / stride) | |
8905 | * where their 'inputsize' is our 'inputsize', 'grainsize' is | |
8906 | * our 'stride + 3' and 'stride' is our 'stride'. | |
8907 | * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: | |
8908 | * = 4 - (inputsize - stride - 3 + stride - 1) / stride | |
8909 | * = 4 - (inputsize - 4) / stride; | |
8910 | */ | |
8911 | level = 4 - (inputsize - 4) / stride; | |
8912 | } else { | |
8913 | /* For stage 2 translations the starting level is specified by the | |
8914 | * VTCR_EL2.SL0 field (whose interpretation depends on the page size) | |
8915 | */ | |
1b4093ea SS |
8916 | uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); |
8917 | uint32_t startlevel; | |
1853d5a9 EI |
8918 | bool ok; |
8919 | ||
6e99f762 | 8920 | if (!aarch64 || stride == 9) { |
1853d5a9 | 8921 | /* AArch32 or 4KB pages */ |
1b4093ea | 8922 | startlevel = 2 - sl0; |
1853d5a9 EI |
8923 | } else { |
8924 | /* 16KB or 64KB pages */ | |
1b4093ea | 8925 | startlevel = 3 - sl0; |
1853d5a9 EI |
8926 | } |
8927 | ||
8928 | /* Check that the starting level is valid. */ | |
6e99f762 | 8929 | ok = check_s2_mmu_setup(cpu, aarch64, startlevel, |
1b4093ea | 8930 | inputsize, stride); |
1853d5a9 | 8931 | if (!ok) { |
da909b2c | 8932 | fault_type = ARMFault_Translation; |
1853d5a9 EI |
8933 | goto do_fault; |
8934 | } | |
1b4093ea | 8935 | level = startlevel; |
1853d5a9 | 8936 | } |
3dde962f | 8937 | |
dddb5223 SS |
8938 | indexmask_grainsize = (1ULL << (stride + 3)) - 1; |
8939 | indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; | |
3dde962f PM |
8940 | |
8941 | /* Now we can extract the actual base address from the TTBR */ | |
2c8dd318 | 8942 | descaddr = extract64(ttbr, 0, 48); |
dddb5223 | 8943 | descaddr &= ~indexmask; |
3dde962f | 8944 | |
6109769a | 8945 | /* The address field in the descriptor goes up to bit 39 for ARMv7 |
dddb5223 SS |
8946 | * but up to bit 47 for ARMv8, but we use the descaddrmask |
8947 | * up to bit 39 for AArch32, because we don't need other bits in that case | |
8948 | * to construct next descriptor address (anyway they should be all zeroes). | |
6109769a | 8949 | */ |
6e99f762 | 8950 | descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) & |
dddb5223 | 8951 | ~indexmask_grainsize; |
6109769a | 8952 | |
ebca90e4 PM |
8953 | /* Secure accesses start with the page table in secure memory and |
8954 | * can be downgraded to non-secure at any step. Non-secure accesses | |
8955 | * remain non-secure. We implement this by just ORing in the NSTable/NS | |
8956 | * bits at each step. | |
8957 | */ | |
8958 | tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); | |
3dde962f PM |
8959 | for (;;) { |
8960 | uint64_t descriptor; | |
ebca90e4 | 8961 | bool nstable; |
3dde962f | 8962 | |
dddb5223 | 8963 | descaddr |= (address >> (stride * (4 - level))) & indexmask; |
2c8dd318 | 8964 | descaddr &= ~7ULL; |
ebca90e4 | 8965 | nstable = extract32(tableattrs, 4, 1); |
3795a6de | 8966 | descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi); |
37785977 EI |
8967 | if (fi->s1ptw) { |
8968 | goto do_fault; | |
8969 | } | |
8970 | ||
3dde962f PM |
8971 | if (!(descriptor & 1) || |
8972 | (!(descriptor & 2) && (level == 3))) { | |
8973 | /* Invalid, or the Reserved level 3 encoding */ | |
8974 | goto do_fault; | |
8975 | } | |
6109769a | 8976 | descaddr = descriptor & descaddrmask; |
3dde962f PM |
8977 | |
8978 | if ((descriptor & 2) && (level < 3)) { | |
8979 | /* Table entry. The top five bits are attributes which may | |
8980 | * propagate down through lower levels of the table (and | |
8981 | * which are all arranged so that 0 means "no effect", so | |
8982 | * we can gather them up by ORing in the bits at each level). | |
8983 | */ | |
8984 | tableattrs |= extract64(descriptor, 59, 5); | |
8985 | level++; | |
dddb5223 | 8986 | indexmask = indexmask_grainsize; |
3dde962f PM |
8987 | continue; |
8988 | } | |
8989 | /* Block entry at level 1 or 2, or page entry at level 3. | |
8990 | * These are basically the same thing, although the number | |
8991 | * of bits we pull in from the vaddr varies. | |
8992 | */ | |
973a5434 | 8993 | page_size = (1ULL << ((stride * (4 - level)) + 3)); |
3dde962f | 8994 | descaddr |= (address & (page_size - 1)); |
6ab1a5ee | 8995 | /* Extract attributes from the descriptor */ |
d615efac IC |
8996 | attrs = extract64(descriptor, 2, 10) |
8997 | | (extract64(descriptor, 52, 12) << 10); | |
6ab1a5ee EI |
8998 | |
8999 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
9000 | /* Stage 2 table descriptors do not include any attribute fields */ | |
9001 | break; | |
9002 | } | |
9003 | /* Merge in attributes from table descriptors */ | |
3dde962f PM |
9004 | attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ |
9005 | attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ | |
9006 | /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 | |
9007 | * means "force PL1 access only", which means forcing AP[1] to 0. | |
9008 | */ | |
9009 | if (extract32(tableattrs, 2, 1)) { | |
9010 | attrs &= ~(1 << 4); | |
9011 | } | |
ebca90e4 | 9012 | attrs |= nstable << 3; /* NS */ |
3dde962f PM |
9013 | break; |
9014 | } | |
9015 | /* Here descaddr is the final physical address, and attributes | |
9016 | * are all in attrs. | |
9017 | */ | |
da909b2c | 9018 | fault_type = ARMFault_AccessFlag; |
3dde962f PM |
9019 | if ((attrs & (1 << 8)) == 0) { |
9020 | /* Access flag */ | |
9021 | goto do_fault; | |
9022 | } | |
d8e052b3 AJ |
9023 | |
9024 | ap = extract32(attrs, 4, 2); | |
d8e052b3 | 9025 | xn = extract32(attrs, 12, 1); |
d8e052b3 | 9026 | |
6ab1a5ee EI |
9027 | if (mmu_idx == ARMMMUIdx_S2NS) { |
9028 | ns = true; | |
9029 | *prot = get_S2prot(env, ap, xn); | |
9030 | } else { | |
9031 | ns = extract32(attrs, 3, 1); | |
9032 | pxn = extract32(attrs, 11, 1); | |
6e99f762 | 9033 | *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); |
6ab1a5ee | 9034 | } |
d8e052b3 | 9035 | |
da909b2c | 9036 | fault_type = ARMFault_Permission; |
d8e052b3 | 9037 | if (!(*prot & (1 << access_type))) { |
3dde962f PM |
9038 | goto do_fault; |
9039 | } | |
3dde962f | 9040 | |
8bf5b6a9 PM |
9041 | if (ns) { |
9042 | /* The NS bit will (as required by the architecture) have no effect if | |
9043 | * the CPU doesn't support TZ or this is a non-secure translation | |
9044 | * regime, because the attribute will already be non-secure. | |
9045 | */ | |
9046 | txattrs->secure = false; | |
9047 | } | |
5b2d261d AB |
9048 | |
9049 | if (cacheattrs != NULL) { | |
9050 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
9051 | cacheattrs->attrs = convert_stage2_attrs(env, | |
9052 | extract32(attrs, 0, 4)); | |
9053 | } else { | |
9054 | /* Index into MAIR registers for cache attributes */ | |
9055 | uint8_t attrindx = extract32(attrs, 0, 3); | |
9056 | uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; | |
9057 | assert(attrindx <= 7); | |
9058 | cacheattrs->attrs = extract64(mair, attrindx * 8, 8); | |
9059 | } | |
9060 | cacheattrs->shareability = extract32(attrs, 6, 2); | |
9061 | } | |
9062 | ||
3dde962f PM |
9063 | *phys_ptr = descaddr; |
9064 | *page_size_ptr = page_size; | |
b7cc4e82 | 9065 | return false; |
3dde962f PM |
9066 | |
9067 | do_fault: | |
da909b2c PM |
9068 | fi->type = fault_type; |
9069 | fi->level = level; | |
37785977 EI |
9070 | /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ |
9071 | fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS); | |
b7cc4e82 | 9072 | return true; |
3dde962f PM |
9073 | } |
9074 | ||
f6bda88f PC |
9075 | static inline void get_phys_addr_pmsav7_default(CPUARMState *env, |
9076 | ARMMMUIdx mmu_idx, | |
9077 | int32_t address, int *prot) | |
9078 | { | |
3a00d560 MD |
9079 | if (!arm_feature(env, ARM_FEATURE_M)) { |
9080 | *prot = PAGE_READ | PAGE_WRITE; | |
9081 | switch (address) { | |
9082 | case 0xF0000000 ... 0xFFFFFFFF: | |
9083 | if (regime_sctlr(env, mmu_idx) & SCTLR_V) { | |
9084 | /* hivecs execing is ok */ | |
9085 | *prot |= PAGE_EXEC; | |
9086 | } | |
9087 | break; | |
9088 | case 0x00000000 ... 0x7FFFFFFF: | |
f6bda88f | 9089 | *prot |= PAGE_EXEC; |
3a00d560 MD |
9090 | break; |
9091 | } | |
9092 | } else { | |
9093 | /* Default system address map for M profile cores. | |
9094 | * The architecture specifies which regions are execute-never; | |
9095 | * at the MPU level no other checks are defined. | |
9096 | */ | |
9097 | switch (address) { | |
9098 | case 0x00000000 ... 0x1fffffff: /* ROM */ | |
9099 | case 0x20000000 ... 0x3fffffff: /* SRAM */ | |
9100 | case 0x60000000 ... 0x7fffffff: /* RAM */ | |
9101 | case 0x80000000 ... 0x9fffffff: /* RAM */ | |
9102 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
9103 | break; | |
9104 | case 0x40000000 ... 0x5fffffff: /* Peripheral */ | |
9105 | case 0xa0000000 ... 0xbfffffff: /* Device */ | |
9106 | case 0xc0000000 ... 0xdfffffff: /* Device */ | |
9107 | case 0xe0000000 ... 0xffffffff: /* System */ | |
9108 | *prot = PAGE_READ | PAGE_WRITE; | |
9109 | break; | |
9110 | default: | |
9111 | g_assert_not_reached(); | |
f6bda88f | 9112 | } |
f6bda88f | 9113 | } |
f6bda88f PC |
9114 | } |
9115 | ||
29c483a5 MD |
9116 | static bool pmsav7_use_background_region(ARMCPU *cpu, |
9117 | ARMMMUIdx mmu_idx, bool is_user) | |
9118 | { | |
9119 | /* Return true if we should use the default memory map as a | |
9120 | * "background" region if there are no hits against any MPU regions. | |
9121 | */ | |
9122 | CPUARMState *env = &cpu->env; | |
9123 | ||
9124 | if (is_user) { | |
9125 | return false; | |
9126 | } | |
9127 | ||
9128 | if (arm_feature(env, ARM_FEATURE_M)) { | |
ecf5e8ea PM |
9129 | return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] |
9130 | & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; | |
29c483a5 MD |
9131 | } else { |
9132 | return regime_sctlr(env, mmu_idx) & SCTLR_BR; | |
9133 | } | |
9134 | } | |
9135 | ||
38aaa60c PM |
9136 | static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address) |
9137 | { | |
9138 | /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */ | |
9139 | return arm_feature(env, ARM_FEATURE_M) && | |
9140 | extract32(address, 20, 12) == 0xe00; | |
9141 | } | |
9142 | ||
bf446a11 PM |
9143 | static inline bool m_is_system_region(CPUARMState *env, uint32_t address) |
9144 | { | |
9145 | /* True if address is in the M profile system region | |
9146 | * 0xe0000000 - 0xffffffff | |
9147 | */ | |
9148 | return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7; | |
9149 | } | |
9150 | ||
f6bda88f | 9151 | static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, |
03ae85f8 | 9152 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
9375ad15 PM |
9153 | hwaddr *phys_ptr, int *prot, |
9154 | ARMMMUFaultInfo *fi) | |
f6bda88f PC |
9155 | { |
9156 | ARMCPU *cpu = arm_env_get_cpu(env); | |
9157 | int n; | |
9158 | bool is_user = regime_is_user(env, mmu_idx); | |
9159 | ||
9160 | *phys_ptr = address; | |
9161 | *prot = 0; | |
9162 | ||
38aaa60c PM |
9163 | if (regime_translation_disabled(env, mmu_idx) || |
9164 | m_is_ppb_region(env, address)) { | |
9165 | /* MPU disabled or M profile PPB access: use default memory map. | |
9166 | * The other case which uses the default memory map in the | |
9167 | * v7M ARM ARM pseudocode is exception vector reads from the vector | |
9168 | * table. In QEMU those accesses are done in arm_v7m_load_vector(), | |
9169 | * which always does a direct read using address_space_ldl(), rather | |
9170 | * than going via this function, so we don't need to check that here. | |
9171 | */ | |
f6bda88f PC |
9172 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); |
9173 | } else { /* MPU enabled */ | |
9174 | for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { | |
9175 | /* region search */ | |
9176 | uint32_t base = env->pmsav7.drbar[n]; | |
9177 | uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5); | |
9178 | uint32_t rmask; | |
9179 | bool srdis = false; | |
9180 | ||
9181 | if (!(env->pmsav7.drsr[n] & 0x1)) { | |
9182 | continue; | |
9183 | } | |
9184 | ||
9185 | if (!rsize) { | |
c9f9f124 MD |
9186 | qemu_log_mask(LOG_GUEST_ERROR, |
9187 | "DRSR[%d]: Rsize field cannot be 0\n", n); | |
f6bda88f PC |
9188 | continue; |
9189 | } | |
9190 | rsize++; | |
9191 | rmask = (1ull << rsize) - 1; | |
9192 | ||
9193 | if (base & rmask) { | |
c9f9f124 MD |
9194 | qemu_log_mask(LOG_GUEST_ERROR, |
9195 | "DRBAR[%d]: 0x%" PRIx32 " misaligned " | |
9196 | "to DRSR region size, mask = 0x%" PRIx32 "\n", | |
9197 | n, base, rmask); | |
f6bda88f PC |
9198 | continue; |
9199 | } | |
9200 | ||
9201 | if (address < base || address > base + rmask) { | |
9202 | continue; | |
9203 | } | |
9204 | ||
9205 | /* Region matched */ | |
9206 | ||
9207 | if (rsize >= 8) { /* no subregions for regions < 256 bytes */ | |
9208 | int i, snd; | |
9209 | uint32_t srdis_mask; | |
9210 | ||
9211 | rsize -= 3; /* sub region size (power of 2) */ | |
9212 | snd = ((address - base) >> rsize) & 0x7; | |
9213 | srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1); | |
9214 | ||
9215 | srdis_mask = srdis ? 0x3 : 0x0; | |
9216 | for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) { | |
9217 | /* This will check in groups of 2, 4 and then 8, whether | |
9218 | * the subregion bits are consistent. rsize is incremented | |
9219 | * back up to give the region size, considering consistent | |
9220 | * adjacent subregions as one region. Stop testing if rsize | |
9221 | * is already big enough for an entire QEMU page. | |
9222 | */ | |
9223 | int snd_rounded = snd & ~(i - 1); | |
9224 | uint32_t srdis_multi = extract32(env->pmsav7.drsr[n], | |
9225 | snd_rounded + 8, i); | |
9226 | if (srdis_mask ^ srdis_multi) { | |
9227 | break; | |
9228 | } | |
9229 | srdis_mask = (srdis_mask << i) | srdis_mask; | |
9230 | rsize++; | |
9231 | } | |
9232 | } | |
9233 | if (rsize < TARGET_PAGE_BITS) { | |
c9f9f124 MD |
9234 | qemu_log_mask(LOG_UNIMP, |
9235 | "DRSR[%d]: No support for MPU (sub)region " | |
f6bda88f | 9236 | "alignment of %" PRIu32 " bits. Minimum is %d\n", |
c9f9f124 | 9237 | n, rsize, TARGET_PAGE_BITS); |
f6bda88f PC |
9238 | continue; |
9239 | } | |
9240 | if (srdis) { | |
9241 | continue; | |
9242 | } | |
9243 | break; | |
9244 | } | |
9245 | ||
9246 | if (n == -1) { /* no hits */ | |
29c483a5 | 9247 | if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { |
f6bda88f | 9248 | /* background fault */ |
9375ad15 | 9249 | fi->type = ARMFault_Background; |
f6bda88f PC |
9250 | return true; |
9251 | } | |
9252 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | |
9253 | } else { /* a MPU hit! */ | |
9254 | uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); | |
bf446a11 PM |
9255 | uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1); |
9256 | ||
9257 | if (m_is_system_region(env, address)) { | |
9258 | /* System space is always execute never */ | |
9259 | xn = 1; | |
9260 | } | |
f6bda88f PC |
9261 | |
9262 | if (is_user) { /* User mode AP bit decoding */ | |
9263 | switch (ap) { | |
9264 | case 0: | |
9265 | case 1: | |
9266 | case 5: | |
9267 | break; /* no access */ | |
9268 | case 3: | |
9269 | *prot |= PAGE_WRITE; | |
9270 | /* fall through */ | |
9271 | case 2: | |
9272 | case 6: | |
9273 | *prot |= PAGE_READ | PAGE_EXEC; | |
9274 | break; | |
8638f1ad PM |
9275 | case 7: |
9276 | /* for v7M, same as 6; for R profile a reserved value */ | |
9277 | if (arm_feature(env, ARM_FEATURE_M)) { | |
9278 | *prot |= PAGE_READ | PAGE_EXEC; | |
9279 | break; | |
9280 | } | |
9281 | /* fall through */ | |
f6bda88f PC |
9282 | default: |
9283 | qemu_log_mask(LOG_GUEST_ERROR, | |
c9f9f124 MD |
9284 | "DRACR[%d]: Bad value for AP bits: 0x%" |
9285 | PRIx32 "\n", n, ap); | |
f6bda88f PC |
9286 | } |
9287 | } else { /* Priv. mode AP bits decoding */ | |
9288 | switch (ap) { | |
9289 | case 0: | |
9290 | break; /* no access */ | |
9291 | case 1: | |
9292 | case 2: | |
9293 | case 3: | |
9294 | *prot |= PAGE_WRITE; | |
9295 | /* fall through */ | |
9296 | case 5: | |
9297 | case 6: | |
9298 | *prot |= PAGE_READ | PAGE_EXEC; | |
9299 | break; | |
8638f1ad PM |
9300 | case 7: |
9301 | /* for v7M, same as 6; for R profile a reserved value */ | |
9302 | if (arm_feature(env, ARM_FEATURE_M)) { | |
9303 | *prot |= PAGE_READ | PAGE_EXEC; | |
9304 | break; | |
9305 | } | |
9306 | /* fall through */ | |
f6bda88f PC |
9307 | default: |
9308 | qemu_log_mask(LOG_GUEST_ERROR, | |
c9f9f124 MD |
9309 | "DRACR[%d]: Bad value for AP bits: 0x%" |
9310 | PRIx32 "\n", n, ap); | |
f6bda88f PC |
9311 | } |
9312 | } | |
9313 | ||
9314 | /* execute never */ | |
bf446a11 | 9315 | if (xn) { |
f6bda88f PC |
9316 | *prot &= ~PAGE_EXEC; |
9317 | } | |
9318 | } | |
9319 | } | |
9320 | ||
9375ad15 PM |
9321 | fi->type = ARMFault_Permission; |
9322 | fi->level = 1; | |
f6bda88f PC |
9323 | return !(*prot & (1 << access_type)); |
9324 | } | |
9325 | ||
35337cc3 PM |
9326 | static bool v8m_is_sau_exempt(CPUARMState *env, |
9327 | uint32_t address, MMUAccessType access_type) | |
9328 | { | |
9329 | /* The architecture specifies that certain address ranges are | |
9330 | * exempt from v8M SAU/IDAU checks. | |
9331 | */ | |
9332 | return | |
9333 | (access_type == MMU_INST_FETCH && m_is_system_region(env, address)) || | |
9334 | (address >= 0xe0000000 && address <= 0xe0002fff) || | |
9335 | (address >= 0xe000e000 && address <= 0xe000efff) || | |
9336 | (address >= 0xe002e000 && address <= 0xe002efff) || | |
9337 | (address >= 0xe0040000 && address <= 0xe0041fff) || | |
9338 | (address >= 0xe00ff000 && address <= 0xe00fffff); | |
9339 | } | |
9340 | ||
9341 | static void v8m_security_lookup(CPUARMState *env, uint32_t address, | |
9342 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
9343 | V8M_SAttributes *sattrs) | |
9344 | { | |
9345 | /* Look up the security attributes for this address. Compare the | |
9346 | * pseudocode SecurityCheck() function. | |
9347 | * We assume the caller has zero-initialized *sattrs. | |
9348 | */ | |
9349 | ARMCPU *cpu = arm_env_get_cpu(env); | |
9350 | int r; | |
9351 | ||
9352 | /* TODO: implement IDAU */ | |
9353 | ||
9354 | if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) { | |
9355 | /* 0xf0000000..0xffffffff is always S for insn fetches */ | |
9356 | return; | |
9357 | } | |
9358 | ||
9359 | if (v8m_is_sau_exempt(env, address, access_type)) { | |
9360 | sattrs->ns = !regime_is_secure(env, mmu_idx); | |
9361 | return; | |
9362 | } | |
9363 | ||
9364 | switch (env->sau.ctrl & 3) { | |
9365 | case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */ | |
9366 | break; | |
9367 | case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */ | |
9368 | sattrs->ns = true; | |
9369 | break; | |
9370 | default: /* SAU.ENABLE == 1 */ | |
9371 | for (r = 0; r < cpu->sau_sregion; r++) { | |
9372 | if (env->sau.rlar[r] & 1) { | |
9373 | uint32_t base = env->sau.rbar[r] & ~0x1f; | |
9374 | uint32_t limit = env->sau.rlar[r] | 0x1f; | |
9375 | ||
9376 | if (base <= address && limit >= address) { | |
9377 | if (sattrs->srvalid) { | |
9378 | /* If we hit in more than one region then we must report | |
9379 | * as Secure, not NS-Callable, with no valid region | |
9380 | * number info. | |
9381 | */ | |
9382 | sattrs->ns = false; | |
9383 | sattrs->nsc = false; | |
9384 | sattrs->sregion = 0; | |
9385 | sattrs->srvalid = false; | |
9386 | break; | |
9387 | } else { | |
9388 | if (env->sau.rlar[r] & 2) { | |
9389 | sattrs->nsc = true; | |
9390 | } else { | |
9391 | sattrs->ns = true; | |
9392 | } | |
9393 | sattrs->srvalid = true; | |
9394 | sattrs->sregion = r; | |
9395 | } | |
9396 | } | |
9397 | } | |
9398 | } | |
9399 | ||
9400 | /* TODO when we support the IDAU then it may override the result here */ | |
9401 | break; | |
9402 | } | |
9403 | } | |
9404 | ||
54317c0f PM |
9405 | static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, |
9406 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
9407 | hwaddr *phys_ptr, MemTxAttrs *txattrs, | |
3f551b5b | 9408 | int *prot, ARMMMUFaultInfo *fi, uint32_t *mregion) |
54317c0f PM |
9409 | { |
9410 | /* Perform a PMSAv8 MPU lookup (without also doing the SAU check | |
9411 | * that a full phys-to-virt translation does). | |
9412 | * mregion is (if not NULL) set to the region number which matched, | |
9413 | * or -1 if no region number is returned (MPU off, address did not | |
9414 | * hit a region, address hit in multiple regions). | |
9415 | */ | |
504e3cc3 PM |
9416 | ARMCPU *cpu = arm_env_get_cpu(env); |
9417 | bool is_user = regime_is_user(env, mmu_idx); | |
62c58ee0 | 9418 | uint32_t secure = regime_is_secure(env, mmu_idx); |
504e3cc3 PM |
9419 | int n; |
9420 | int matchregion = -1; | |
9421 | bool hit = false; | |
9422 | ||
9423 | *phys_ptr = address; | |
9424 | *prot = 0; | |
54317c0f PM |
9425 | if (mregion) { |
9426 | *mregion = -1; | |
35337cc3 PM |
9427 | } |
9428 | ||
504e3cc3 PM |
9429 | /* Unlike the ARM ARM pseudocode, we don't need to check whether this |
9430 | * was an exception vector read from the vector table (which is always | |
9431 | * done using the default system address map), because those accesses | |
9432 | * are done in arm_v7m_load_vector(), which always does a direct | |
9433 | * read using address_space_ldl(), rather than going via this function. | |
9434 | */ | |
9435 | if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ | |
9436 | hit = true; | |
9437 | } else if (m_is_ppb_region(env, address)) { | |
9438 | hit = true; | |
9439 | } else if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) { | |
9440 | hit = true; | |
9441 | } else { | |
9442 | for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { | |
9443 | /* region search */ | |
9444 | /* Note that the base address is bits [31:5] from the register | |
9445 | * with bits [4:0] all zeroes, but the limit address is bits | |
9446 | * [31:5] from the register with bits [4:0] all ones. | |
9447 | */ | |
62c58ee0 PM |
9448 | uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f; |
9449 | uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f; | |
504e3cc3 | 9450 | |
62c58ee0 | 9451 | if (!(env->pmsav8.rlar[secure][n] & 0x1)) { |
504e3cc3 PM |
9452 | /* Region disabled */ |
9453 | continue; | |
9454 | } | |
9455 | ||
9456 | if (address < base || address > limit) { | |
9457 | continue; | |
9458 | } | |
9459 | ||
9460 | if (hit) { | |
9461 | /* Multiple regions match -- always a failure (unlike | |
9462 | * PMSAv7 where highest-numbered-region wins) | |
9463 | */ | |
3f551b5b PM |
9464 | fi->type = ARMFault_Permission; |
9465 | fi->level = 1; | |
504e3cc3 PM |
9466 | return true; |
9467 | } | |
9468 | ||
9469 | matchregion = n; | |
9470 | hit = true; | |
9471 | ||
9472 | if (base & ~TARGET_PAGE_MASK) { | |
9473 | qemu_log_mask(LOG_UNIMP, | |
9474 | "MPU_RBAR[%d]: No support for MPU region base" | |
9475 | "address of 0x%" PRIx32 ". Minimum alignment is " | |
9476 | "%d\n", | |
9477 | n, base, TARGET_PAGE_BITS); | |
9478 | continue; | |
9479 | } | |
9480 | if ((limit + 1) & ~TARGET_PAGE_MASK) { | |
9481 | qemu_log_mask(LOG_UNIMP, | |
9482 | "MPU_RBAR[%d]: No support for MPU region limit" | |
9483 | "address of 0x%" PRIx32 ". Minimum alignment is " | |
9484 | "%d\n", | |
9485 | n, limit, TARGET_PAGE_BITS); | |
9486 | continue; | |
9487 | } | |
9488 | } | |
9489 | } | |
9490 | ||
9491 | if (!hit) { | |
9492 | /* background fault */ | |
3f551b5b | 9493 | fi->type = ARMFault_Background; |
504e3cc3 PM |
9494 | return true; |
9495 | } | |
9496 | ||
9497 | if (matchregion == -1) { | |
9498 | /* hit using the background region */ | |
9499 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | |
9500 | } else { | |
62c58ee0 PM |
9501 | uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2); |
9502 | uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1); | |
504e3cc3 PM |
9503 | |
9504 | if (m_is_system_region(env, address)) { | |
9505 | /* System space is always execute never */ | |
9506 | xn = 1; | |
9507 | } | |
9508 | ||
9509 | *prot = simple_ap_to_rw_prot(env, mmu_idx, ap); | |
9510 | if (*prot && !xn) { | |
9511 | *prot |= PAGE_EXEC; | |
9512 | } | |
9513 | /* We don't need to look the attribute up in the MAIR0/MAIR1 | |
9514 | * registers because that only tells us about cacheability. | |
9515 | */ | |
54317c0f PM |
9516 | if (mregion) { |
9517 | *mregion = matchregion; | |
9518 | } | |
504e3cc3 PM |
9519 | } |
9520 | ||
3f551b5b PM |
9521 | fi->type = ARMFault_Permission; |
9522 | fi->level = 1; | |
504e3cc3 PM |
9523 | return !(*prot & (1 << access_type)); |
9524 | } | |
9525 | ||
54317c0f PM |
9526 | |
9527 | static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, | |
9528 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
9529 | hwaddr *phys_ptr, MemTxAttrs *txattrs, | |
3f551b5b | 9530 | int *prot, ARMMMUFaultInfo *fi) |
54317c0f PM |
9531 | { |
9532 | uint32_t secure = regime_is_secure(env, mmu_idx); | |
9533 | V8M_SAttributes sattrs = {}; | |
9534 | ||
9535 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
9536 | v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs); | |
9537 | if (access_type == MMU_INST_FETCH) { | |
9538 | /* Instruction fetches always use the MMU bank and the | |
9539 | * transaction attribute determined by the fetch address, | |
9540 | * regardless of CPU state. This is painful for QEMU | |
9541 | * to handle, because it would mean we need to encode | |
9542 | * into the mmu_idx not just the (user, negpri) information | |
9543 | * for the current security state but also that for the | |
9544 | * other security state, which would balloon the number | |
9545 | * of mmu_idx values needed alarmingly. | |
9546 | * Fortunately we can avoid this because it's not actually | |
9547 | * possible to arbitrarily execute code from memory with | |
9548 | * the wrong security attribute: it will always generate | |
9549 | * an exception of some kind or another, apart from the | |
9550 | * special case of an NS CPU executing an SG instruction | |
9551 | * in S&NSC memory. So we always just fail the translation | |
9552 | * here and sort things out in the exception handler | |
9553 | * (including possibly emulating an SG instruction). | |
9554 | */ | |
9555 | if (sattrs.ns != !secure) { | |
3f551b5b PM |
9556 | if (sattrs.nsc) { |
9557 | fi->type = ARMFault_QEMU_NSCExec; | |
9558 | } else { | |
9559 | fi->type = ARMFault_QEMU_SFault; | |
9560 | } | |
54317c0f PM |
9561 | *phys_ptr = address; |
9562 | *prot = 0; | |
9563 | return true; | |
9564 | } | |
9565 | } else { | |
9566 | /* For data accesses we always use the MMU bank indicated | |
9567 | * by the current CPU state, but the security attributes | |
9568 | * might downgrade a secure access to nonsecure. | |
9569 | */ | |
9570 | if (sattrs.ns) { | |
9571 | txattrs->secure = false; | |
9572 | } else if (!secure) { | |
9573 | /* NS access to S memory must fault. | |
9574 | * Architecturally we should first check whether the | |
9575 | * MPU information for this address indicates that we | |
9576 | * are doing an unaligned access to Device memory, which | |
9577 | * should generate a UsageFault instead. QEMU does not | |
9578 | * currently check for that kind of unaligned access though. | |
9579 | * If we added it we would need to do so as a special case | |
9580 | * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). | |
9581 | */ | |
3f551b5b | 9582 | fi->type = ARMFault_QEMU_SFault; |
54317c0f PM |
9583 | *phys_ptr = address; |
9584 | *prot = 0; | |
9585 | return true; | |
9586 | } | |
9587 | } | |
9588 | } | |
9589 | ||
9590 | return pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, | |
3f551b5b | 9591 | txattrs, prot, fi, NULL); |
54317c0f PM |
9592 | } |
9593 | ||
13689d43 | 9594 | static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, |
03ae85f8 | 9595 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
53a4e5c5 PM |
9596 | hwaddr *phys_ptr, int *prot, |
9597 | ARMMMUFaultInfo *fi) | |
9ee6e8bb PB |
9598 | { |
9599 | int n; | |
9600 | uint32_t mask; | |
9601 | uint32_t base; | |
0480f69a | 9602 | bool is_user = regime_is_user(env, mmu_idx); |
9ee6e8bb | 9603 | |
3279adb9 PM |
9604 | if (regime_translation_disabled(env, mmu_idx)) { |
9605 | /* MPU disabled. */ | |
9606 | *phys_ptr = address; | |
9607 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
9608 | return false; | |
9609 | } | |
9610 | ||
9ee6e8bb PB |
9611 | *phys_ptr = address; |
9612 | for (n = 7; n >= 0; n--) { | |
554b0b09 | 9613 | base = env->cp15.c6_region[n]; |
87c3d486 | 9614 | if ((base & 1) == 0) { |
554b0b09 | 9615 | continue; |
87c3d486 | 9616 | } |
554b0b09 PM |
9617 | mask = 1 << ((base >> 1) & 0x1f); |
9618 | /* Keep this shift separate from the above to avoid an | |
9619 | (undefined) << 32. */ | |
9620 | mask = (mask << 1) - 1; | |
87c3d486 | 9621 | if (((base ^ address) & ~mask) == 0) { |
554b0b09 | 9622 | break; |
87c3d486 | 9623 | } |
9ee6e8bb | 9624 | } |
87c3d486 | 9625 | if (n < 0) { |
53a4e5c5 | 9626 | fi->type = ARMFault_Background; |
b7cc4e82 | 9627 | return true; |
87c3d486 | 9628 | } |
9ee6e8bb | 9629 | |
03ae85f8 | 9630 | if (access_type == MMU_INST_FETCH) { |
7e09797c | 9631 | mask = env->cp15.pmsav5_insn_ap; |
9ee6e8bb | 9632 | } else { |
7e09797c | 9633 | mask = env->cp15.pmsav5_data_ap; |
9ee6e8bb PB |
9634 | } |
9635 | mask = (mask >> (n * 4)) & 0xf; | |
9636 | switch (mask) { | |
9637 | case 0: | |
53a4e5c5 PM |
9638 | fi->type = ARMFault_Permission; |
9639 | fi->level = 1; | |
b7cc4e82 | 9640 | return true; |
9ee6e8bb | 9641 | case 1: |
87c3d486 | 9642 | if (is_user) { |
53a4e5c5 PM |
9643 | fi->type = ARMFault_Permission; |
9644 | fi->level = 1; | |
b7cc4e82 | 9645 | return true; |
87c3d486 | 9646 | } |
554b0b09 PM |
9647 | *prot = PAGE_READ | PAGE_WRITE; |
9648 | break; | |
9ee6e8bb | 9649 | case 2: |
554b0b09 | 9650 | *prot = PAGE_READ; |
87c3d486 | 9651 | if (!is_user) { |
554b0b09 | 9652 | *prot |= PAGE_WRITE; |
87c3d486 | 9653 | } |
554b0b09 | 9654 | break; |
9ee6e8bb | 9655 | case 3: |
554b0b09 PM |
9656 | *prot = PAGE_READ | PAGE_WRITE; |
9657 | break; | |
9ee6e8bb | 9658 | case 5: |
87c3d486 | 9659 | if (is_user) { |
53a4e5c5 PM |
9660 | fi->type = ARMFault_Permission; |
9661 | fi->level = 1; | |
b7cc4e82 | 9662 | return true; |
87c3d486 | 9663 | } |
554b0b09 PM |
9664 | *prot = PAGE_READ; |
9665 | break; | |
9ee6e8bb | 9666 | case 6: |
554b0b09 PM |
9667 | *prot = PAGE_READ; |
9668 | break; | |
9ee6e8bb | 9669 | default: |
554b0b09 | 9670 | /* Bad permission. */ |
53a4e5c5 PM |
9671 | fi->type = ARMFault_Permission; |
9672 | fi->level = 1; | |
b7cc4e82 | 9673 | return true; |
9ee6e8bb | 9674 | } |
3ad493fc | 9675 | *prot |= PAGE_EXEC; |
b7cc4e82 | 9676 | return false; |
9ee6e8bb PB |
9677 | } |
9678 | ||
5b2d261d AB |
9679 | /* Combine either inner or outer cacheability attributes for normal |
9680 | * memory, according to table D4-42 and pseudocode procedure | |
9681 | * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). | |
9682 | * | |
9683 | * NB: only stage 1 includes allocation hints (RW bits), leading to | |
9684 | * some asymmetry. | |
9685 | */ | |
9686 | static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2) | |
9687 | { | |
9688 | if (s1 == 4 || s2 == 4) { | |
9689 | /* non-cacheable has precedence */ | |
9690 | return 4; | |
9691 | } else if (extract32(s1, 2, 2) == 0 || extract32(s1, 2, 2) == 2) { | |
9692 | /* stage 1 write-through takes precedence */ | |
9693 | return s1; | |
9694 | } else if (extract32(s2, 2, 2) == 2) { | |
9695 | /* stage 2 write-through takes precedence, but the allocation hint | |
9696 | * is still taken from stage 1 | |
9697 | */ | |
9698 | return (2 << 2) | extract32(s1, 0, 2); | |
9699 | } else { /* write-back */ | |
9700 | return s1; | |
9701 | } | |
9702 | } | |
9703 | ||
9704 | /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 | |
9705 | * and CombineS1S2Desc() | |
9706 | * | |
9707 | * @s1: Attributes from stage 1 walk | |
9708 | * @s2: Attributes from stage 2 walk | |
9709 | */ | |
9710 | static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) | |
9711 | { | |
9712 | uint8_t s1lo = extract32(s1.attrs, 0, 4), s2lo = extract32(s2.attrs, 0, 4); | |
9713 | uint8_t s1hi = extract32(s1.attrs, 4, 4), s2hi = extract32(s2.attrs, 4, 4); | |
9714 | ARMCacheAttrs ret; | |
9715 | ||
9716 | /* Combine shareability attributes (table D4-43) */ | |
9717 | if (s1.shareability == 2 || s2.shareability == 2) { | |
9718 | /* if either are outer-shareable, the result is outer-shareable */ | |
9719 | ret.shareability = 2; | |
9720 | } else if (s1.shareability == 3 || s2.shareability == 3) { | |
9721 | /* if either are inner-shareable, the result is inner-shareable */ | |
9722 | ret.shareability = 3; | |
9723 | } else { | |
9724 | /* both non-shareable */ | |
9725 | ret.shareability = 0; | |
9726 | } | |
9727 | ||
9728 | /* Combine memory type and cacheability attributes */ | |
9729 | if (s1hi == 0 || s2hi == 0) { | |
9730 | /* Device has precedence over normal */ | |
9731 | if (s1lo == 0 || s2lo == 0) { | |
9732 | /* nGnRnE has precedence over anything */ | |
9733 | ret.attrs = 0; | |
9734 | } else if (s1lo == 4 || s2lo == 4) { | |
9735 | /* non-Reordering has precedence over Reordering */ | |
9736 | ret.attrs = 4; /* nGnRE */ | |
9737 | } else if (s1lo == 8 || s2lo == 8) { | |
9738 | /* non-Gathering has precedence over Gathering */ | |
9739 | ret.attrs = 8; /* nGRE */ | |
9740 | } else { | |
9741 | ret.attrs = 0xc; /* GRE */ | |
9742 | } | |
9743 | ||
9744 | /* Any location for which the resultant memory type is any | |
9745 | * type of Device memory is always treated as Outer Shareable. | |
9746 | */ | |
9747 | ret.shareability = 2; | |
9748 | } else { /* Normal memory */ | |
9749 | /* Outer/inner cacheability combine independently */ | |
9750 | ret.attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4 | |
9751 | | combine_cacheattr_nibble(s1lo, s2lo); | |
9752 | ||
9753 | if (ret.attrs == 0x44) { | |
9754 | /* Any location for which the resultant memory type is Normal | |
9755 | * Inner Non-cacheable, Outer Non-cacheable is always treated | |
9756 | * as Outer Shareable. | |
9757 | */ | |
9758 | ret.shareability = 2; | |
9759 | } | |
9760 | } | |
9761 | ||
9762 | return ret; | |
9763 | } | |
9764 | ||
9765 | ||
702a9357 PM |
9766 | /* get_phys_addr - get the physical address for this virtual address |
9767 | * | |
9768 | * Find the physical address corresponding to the given virtual address, | |
9769 | * by doing a translation table walk on MMU based systems or using the | |
9770 | * MPU state on MPU based systems. | |
9771 | * | |
b7cc4e82 PC |
9772 | * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, |
9773 | * prot and page_size may not be filled in, and the populated fsr value provides | |
702a9357 PM |
9774 | * information on why the translation aborted, in the format of a |
9775 | * DFSR/IFSR fault register, with the following caveats: | |
9776 | * * we honour the short vs long DFSR format differences. | |
9777 | * * the WnR bit is never set (the caller must do this). | |
f6bda88f | 9778 | * * for PSMAv5 based systems we don't bother to return a full FSR format |
702a9357 PM |
9779 | * value. |
9780 | * | |
9781 | * @env: CPUARMState | |
9782 | * @address: virtual address to get physical address for | |
9783 | * @access_type: 0 for read, 1 for write, 2 for execute | |
d3649702 | 9784 | * @mmu_idx: MMU index indicating required translation regime |
702a9357 | 9785 | * @phys_ptr: set to the physical address corresponding to the virtual address |
8bf5b6a9 | 9786 | * @attrs: set to the memory transaction attributes to use |
702a9357 PM |
9787 | * @prot: set to the permissions for the page containing phys_ptr |
9788 | * @page_size: set to the size of the page containing phys_ptr | |
5b2d261d AB |
9789 | * @fi: set to fault info if the translation fails |
9790 | * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes | |
702a9357 | 9791 | */ |
af51f566 | 9792 | static bool get_phys_addr(CPUARMState *env, target_ulong address, |
03ae85f8 | 9793 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
af51f566 | 9794 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, |
bc52bfeb | 9795 | target_ulong *page_size, |
5b2d261d | 9796 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) |
9ee6e8bb | 9797 | { |
0480f69a | 9798 | if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { |
9b539263 EI |
9799 | /* Call ourselves recursively to do the stage 1 and then stage 2 |
9800 | * translations. | |
0480f69a | 9801 | */ |
9b539263 EI |
9802 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
9803 | hwaddr ipa; | |
9804 | int s2_prot; | |
9805 | int ret; | |
5b2d261d | 9806 | ARMCacheAttrs cacheattrs2 = {}; |
9b539263 EI |
9807 | |
9808 | ret = get_phys_addr(env, address, access_type, | |
8bd5c820 | 9809 | stage_1_mmu_idx(mmu_idx), &ipa, attrs, |
bc52bfeb | 9810 | prot, page_size, fi, cacheattrs); |
9b539263 EI |
9811 | |
9812 | /* If S1 fails or S2 is disabled, return early. */ | |
9813 | if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { | |
9814 | *phys_ptr = ipa; | |
9815 | return ret; | |
9816 | } | |
9817 | ||
9818 | /* S1 is done. Now do S2 translation. */ | |
9819 | ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS, | |
9820 | phys_ptr, attrs, &s2_prot, | |
da909b2c | 9821 | page_size, fi, |
5b2d261d | 9822 | cacheattrs != NULL ? &cacheattrs2 : NULL); |
9b539263 EI |
9823 | fi->s2addr = ipa; |
9824 | /* Combine the S1 and S2 perms. */ | |
9825 | *prot &= s2_prot; | |
5b2d261d AB |
9826 | |
9827 | /* Combine the S1 and S2 cache attributes, if needed */ | |
9828 | if (!ret && cacheattrs != NULL) { | |
9829 | *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2); | |
9830 | } | |
9831 | ||
9b539263 EI |
9832 | return ret; |
9833 | } else { | |
9834 | /* | |
9835 | * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. | |
9836 | */ | |
8bd5c820 | 9837 | mmu_idx = stage_1_mmu_idx(mmu_idx); |
9b539263 | 9838 | } |
0480f69a | 9839 | } |
d3649702 | 9840 | |
8bf5b6a9 PM |
9841 | /* The page table entries may downgrade secure to non-secure, but |
9842 | * cannot upgrade an non-secure translation regime's attributes | |
9843 | * to secure. | |
9844 | */ | |
9845 | attrs->secure = regime_is_secure(env, mmu_idx); | |
0995bf8c | 9846 | attrs->user = regime_is_user(env, mmu_idx); |
8bf5b6a9 | 9847 | |
0480f69a PM |
9848 | /* Fast Context Switch Extension. This doesn't exist at all in v8. |
9849 | * In v7 and earlier it affects all stage 1 translations. | |
9850 | */ | |
9851 | if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS | |
9852 | && !arm_feature(env, ARM_FEATURE_V8)) { | |
9853 | if (regime_el(env, mmu_idx) == 3) { | |
9854 | address += env->cp15.fcseidr_s; | |
9855 | } else { | |
9856 | address += env->cp15.fcseidr_ns; | |
9857 | } | |
54bf36ed | 9858 | } |
9ee6e8bb | 9859 | |
3279adb9 | 9860 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
c9f9f124 | 9861 | bool ret; |
f6bda88f | 9862 | *page_size = TARGET_PAGE_SIZE; |
3279adb9 | 9863 | |
504e3cc3 PM |
9864 | if (arm_feature(env, ARM_FEATURE_V8)) { |
9865 | /* PMSAv8 */ | |
9866 | ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, | |
3f551b5b | 9867 | phys_ptr, attrs, prot, fi); |
504e3cc3 | 9868 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
3279adb9 PM |
9869 | /* PMSAv7 */ |
9870 | ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, | |
9375ad15 | 9871 | phys_ptr, prot, fi); |
3279adb9 PM |
9872 | } else { |
9873 | /* Pre-v7 MPU */ | |
9874 | ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, | |
53a4e5c5 | 9875 | phys_ptr, prot, fi); |
3279adb9 PM |
9876 | } |
9877 | qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 | |
c9f9f124 | 9878 | " mmu_idx %u -> %s (prot %c%c%c)\n", |
709e4407 PM |
9879 | access_type == MMU_DATA_LOAD ? "reading" : |
9880 | (access_type == MMU_DATA_STORE ? "writing" : "execute"), | |
c9f9f124 MD |
9881 | (uint32_t)address, mmu_idx, |
9882 | ret ? "Miss" : "Hit", | |
9883 | *prot & PAGE_READ ? 'r' : '-', | |
9884 | *prot & PAGE_WRITE ? 'w' : '-', | |
9885 | *prot & PAGE_EXEC ? 'x' : '-'); | |
9886 | ||
9887 | return ret; | |
f6bda88f PC |
9888 | } |
9889 | ||
3279adb9 PM |
9890 | /* Definitely a real MMU, not an MPU */ |
9891 | ||
0480f69a | 9892 | if (regime_translation_disabled(env, mmu_idx)) { |
3279adb9 | 9893 | /* MMU disabled. */ |
9ee6e8bb | 9894 | *phys_ptr = address; |
3ad493fc | 9895 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
d4c430a8 | 9896 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb | 9897 | return 0; |
0480f69a PM |
9898 | } |
9899 | ||
0480f69a | 9900 | if (regime_using_lpae_format(env, mmu_idx)) { |
bc52bfeb PM |
9901 | return get_phys_addr_lpae(env, address, access_type, mmu_idx, |
9902 | phys_ptr, attrs, prot, page_size, | |
9903 | fi, cacheattrs); | |
0480f69a | 9904 | } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { |
bc52bfeb PM |
9905 | return get_phys_addr_v6(env, address, access_type, mmu_idx, |
9906 | phys_ptr, attrs, prot, page_size, fi); | |
9ee6e8bb | 9907 | } else { |
bc52bfeb | 9908 | return get_phys_addr_v5(env, address, access_type, mmu_idx, |
f989983e | 9909 | phys_ptr, prot, page_size, fi); |
9ee6e8bb PB |
9910 | } |
9911 | } | |
9912 | ||
8c6084bf | 9913 | /* Walk the page table and (if the mapping exists) add the page |
b7cc4e82 PC |
9914 | * to the TLB. Return false on success, or true on failure. Populate |
9915 | * fsr with ARM DFSR/IFSR fault register format value on failure. | |
8c6084bf | 9916 | */ |
b7cc4e82 | 9917 | bool arm_tlb_fill(CPUState *cs, vaddr address, |
bc52bfeb | 9918 | MMUAccessType access_type, int mmu_idx, |
e14b5a23 | 9919 | ARMMMUFaultInfo *fi) |
b5ff1b31 | 9920 | { |
7510454e AF |
9921 | ARMCPU *cpu = ARM_CPU(cs); |
9922 | CPUARMState *env = &cpu->env; | |
a8170e5e | 9923 | hwaddr phys_addr; |
d4c430a8 | 9924 | target_ulong page_size; |
b5ff1b31 | 9925 | int prot; |
d3649702 | 9926 | int ret; |
8bf5b6a9 | 9927 | MemTxAttrs attrs = {}; |
b5ff1b31 | 9928 | |
8bd5c820 PM |
9929 | ret = get_phys_addr(env, address, access_type, |
9930 | core_to_arm_mmu_idx(env, mmu_idx), &phys_addr, | |
bc52bfeb | 9931 | &attrs, &prot, &page_size, fi, NULL); |
b7cc4e82 | 9932 | if (!ret) { |
b5ff1b31 | 9933 | /* Map a single [sub]page. */ |
dcd82c11 AB |
9934 | phys_addr &= TARGET_PAGE_MASK; |
9935 | address &= TARGET_PAGE_MASK; | |
8bf5b6a9 PM |
9936 | tlb_set_page_with_attrs(cs, address, phys_addr, attrs, |
9937 | prot, mmu_idx, page_size); | |
d4c430a8 | 9938 | return 0; |
b5ff1b31 FB |
9939 | } |
9940 | ||
8c6084bf | 9941 | return ret; |
b5ff1b31 FB |
9942 | } |
9943 | ||
0faea0c7 PM |
9944 | hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, |
9945 | MemTxAttrs *attrs) | |
b5ff1b31 | 9946 | { |
00b941e5 | 9947 | ARMCPU *cpu = ARM_CPU(cs); |
d3649702 | 9948 | CPUARMState *env = &cpu->env; |
a8170e5e | 9949 | hwaddr phys_addr; |
d4c430a8 | 9950 | target_ulong page_size; |
b5ff1b31 | 9951 | int prot; |
b7cc4e82 | 9952 | bool ret; |
e14b5a23 | 9953 | ARMMMUFaultInfo fi = {}; |
8bd5c820 | 9954 | ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); |
b5ff1b31 | 9955 | |
0faea0c7 PM |
9956 | *attrs = (MemTxAttrs) {}; |
9957 | ||
8bd5c820 | 9958 | ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr, |
bc52bfeb | 9959 | attrs, &prot, &page_size, &fi, NULL); |
b5ff1b31 | 9960 | |
b7cc4e82 | 9961 | if (ret) { |
b5ff1b31 | 9962 | return -1; |
00b941e5 | 9963 | } |
b5ff1b31 FB |
9964 | return phys_addr; |
9965 | } | |
9966 | ||
0ecb72a5 | 9967 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb | 9968 | { |
58117c9b MD |
9969 | uint32_t mask; |
9970 | unsigned el = arm_current_el(env); | |
9971 | ||
9972 | /* First handle registers which unprivileged can read */ | |
9973 | ||
9974 | switch (reg) { | |
9975 | case 0 ... 7: /* xPSR sub-fields */ | |
9976 | mask = 0; | |
9977 | if ((reg & 1) && el) { | |
987ab45e | 9978 | mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */ |
58117c9b MD |
9979 | } |
9980 | if (!(reg & 4)) { | |
987ab45e | 9981 | mask |= XPSR_NZCV | XPSR_Q; /* APSR */ |
58117c9b MD |
9982 | } |
9983 | /* EPSR reads as zero */ | |
9984 | return xpsr_read(env) & mask; | |
9985 | break; | |
9986 | case 20: /* CONTROL */ | |
8bfc26ea | 9987 | return env->v7m.control[env->v7m.secure]; |
50f11062 PM |
9988 | case 0x94: /* CONTROL_NS */ |
9989 | /* We have to handle this here because unprivileged Secure code | |
9990 | * can read the NS CONTROL register. | |
9991 | */ | |
9992 | if (!env->v7m.secure) { | |
9993 | return 0; | |
9994 | } | |
9995 | return env->v7m.control[M_REG_NS]; | |
58117c9b MD |
9996 | } |
9997 | ||
9998 | if (el == 0) { | |
9999 | return 0; /* unprivileged reads others as zero */ | |
10000 | } | |
a47dddd7 | 10001 | |
50f11062 PM |
10002 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
10003 | switch (reg) { | |
10004 | case 0x88: /* MSP_NS */ | |
10005 | if (!env->v7m.secure) { | |
10006 | return 0; | |
10007 | } | |
10008 | return env->v7m.other_ss_msp; | |
10009 | case 0x89: /* PSP_NS */ | |
10010 | if (!env->v7m.secure) { | |
10011 | return 0; | |
10012 | } | |
10013 | return env->v7m.other_ss_psp; | |
10014 | case 0x90: /* PRIMASK_NS */ | |
10015 | if (!env->v7m.secure) { | |
10016 | return 0; | |
10017 | } | |
10018 | return env->v7m.primask[M_REG_NS]; | |
10019 | case 0x91: /* BASEPRI_NS */ | |
10020 | if (!env->v7m.secure) { | |
10021 | return 0; | |
10022 | } | |
10023 | return env->v7m.basepri[M_REG_NS]; | |
10024 | case 0x93: /* FAULTMASK_NS */ | |
10025 | if (!env->v7m.secure) { | |
10026 | return 0; | |
10027 | } | |
10028 | return env->v7m.faultmask[M_REG_NS]; | |
10029 | case 0x98: /* SP_NS */ | |
10030 | { | |
10031 | /* This gives the non-secure SP selected based on whether we're | |
10032 | * currently in handler mode or not, using the NS CONTROL.SPSEL. | |
10033 | */ | |
10034 | bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK; | |
10035 | ||
10036 | if (!env->v7m.secure) { | |
10037 | return 0; | |
10038 | } | |
10039 | if (!arm_v7m_is_handler_mode(env) && spsel) { | |
10040 | return env->v7m.other_ss_psp; | |
10041 | } else { | |
10042 | return env->v7m.other_ss_msp; | |
10043 | } | |
10044 | } | |
10045 | default: | |
10046 | break; | |
10047 | } | |
10048 | } | |
10049 | ||
9ee6e8bb | 10050 | switch (reg) { |
9ee6e8bb | 10051 | case 8: /* MSP */ |
1169d3aa | 10052 | return v7m_using_psp(env) ? env->v7m.other_sp : env->regs[13]; |
9ee6e8bb | 10053 | case 9: /* PSP */ |
1169d3aa | 10054 | return v7m_using_psp(env) ? env->regs[13] : env->v7m.other_sp; |
9ee6e8bb | 10055 | case 16: /* PRIMASK */ |
6d804834 | 10056 | return env->v7m.primask[env->v7m.secure]; |
82845826 SH |
10057 | case 17: /* BASEPRI */ |
10058 | case 18: /* BASEPRI_MAX */ | |
acf94941 | 10059 | return env->v7m.basepri[env->v7m.secure]; |
82845826 | 10060 | case 19: /* FAULTMASK */ |
42a6686b | 10061 | return env->v7m.faultmask[env->v7m.secure]; |
9ee6e8bb | 10062 | default: |
58117c9b MD |
10063 | qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special" |
10064 | " register %d\n", reg); | |
9ee6e8bb PB |
10065 | return 0; |
10066 | } | |
10067 | } | |
10068 | ||
b28b3377 PM |
10069 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) |
10070 | { | |
10071 | /* We're passed bits [11..0] of the instruction; extract | |
10072 | * SYSm and the mask bits. | |
10073 | * Invalid combinations of SYSm and mask are UNPREDICTABLE; | |
10074 | * we choose to treat them as if the mask bits were valid. | |
10075 | * NB that the pseudocode 'mask' variable is bits [11..10], | |
10076 | * whereas ours is [11..8]. | |
10077 | */ | |
10078 | uint32_t mask = extract32(maskreg, 8, 4); | |
10079 | uint32_t reg = extract32(maskreg, 0, 8); | |
10080 | ||
58117c9b MD |
10081 | if (arm_current_el(env) == 0 && reg > 7) { |
10082 | /* only xPSR sub-fields may be written by unprivileged */ | |
10083 | return; | |
10084 | } | |
a47dddd7 | 10085 | |
50f11062 PM |
10086 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
10087 | switch (reg) { | |
10088 | case 0x88: /* MSP_NS */ | |
10089 | if (!env->v7m.secure) { | |
10090 | return; | |
10091 | } | |
10092 | env->v7m.other_ss_msp = val; | |
10093 | return; | |
10094 | case 0x89: /* PSP_NS */ | |
10095 | if (!env->v7m.secure) { | |
10096 | return; | |
10097 | } | |
10098 | env->v7m.other_ss_psp = val; | |
10099 | return; | |
10100 | case 0x90: /* PRIMASK_NS */ | |
10101 | if (!env->v7m.secure) { | |
10102 | return; | |
10103 | } | |
10104 | env->v7m.primask[M_REG_NS] = val & 1; | |
10105 | return; | |
10106 | case 0x91: /* BASEPRI_NS */ | |
10107 | if (!env->v7m.secure) { | |
10108 | return; | |
10109 | } | |
10110 | env->v7m.basepri[M_REG_NS] = val & 0xff; | |
10111 | return; | |
10112 | case 0x93: /* FAULTMASK_NS */ | |
10113 | if (!env->v7m.secure) { | |
10114 | return; | |
10115 | } | |
10116 | env->v7m.faultmask[M_REG_NS] = val & 1; | |
10117 | return; | |
10118 | case 0x98: /* SP_NS */ | |
10119 | { | |
10120 | /* This gives the non-secure SP selected based on whether we're | |
10121 | * currently in handler mode or not, using the NS CONTROL.SPSEL. | |
10122 | */ | |
10123 | bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK; | |
10124 | ||
10125 | if (!env->v7m.secure) { | |
10126 | return; | |
10127 | } | |
10128 | if (!arm_v7m_is_handler_mode(env) && spsel) { | |
10129 | env->v7m.other_ss_psp = val; | |
10130 | } else { | |
10131 | env->v7m.other_ss_msp = val; | |
10132 | } | |
10133 | return; | |
10134 | } | |
10135 | default: | |
10136 | break; | |
10137 | } | |
10138 | } | |
10139 | ||
9ee6e8bb | 10140 | switch (reg) { |
58117c9b MD |
10141 | case 0 ... 7: /* xPSR sub-fields */ |
10142 | /* only APSR is actually writable */ | |
b28b3377 PM |
10143 | if (!(reg & 4)) { |
10144 | uint32_t apsrmask = 0; | |
10145 | ||
10146 | if (mask & 8) { | |
987ab45e | 10147 | apsrmask |= XPSR_NZCV | XPSR_Q; |
b28b3377 PM |
10148 | } |
10149 | if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { | |
987ab45e | 10150 | apsrmask |= XPSR_GE; |
b28b3377 PM |
10151 | } |
10152 | xpsr_write(env, val, apsrmask); | |
58117c9b | 10153 | } |
9ee6e8bb PB |
10154 | break; |
10155 | case 8: /* MSP */ | |
1169d3aa | 10156 | if (v7m_using_psp(env)) { |
9ee6e8bb | 10157 | env->v7m.other_sp = val; |
abc24d86 | 10158 | } else { |
9ee6e8bb | 10159 | env->regs[13] = val; |
abc24d86 | 10160 | } |
9ee6e8bb PB |
10161 | break; |
10162 | case 9: /* PSP */ | |
1169d3aa | 10163 | if (v7m_using_psp(env)) { |
9ee6e8bb | 10164 | env->regs[13] = val; |
abc24d86 | 10165 | } else { |
9ee6e8bb | 10166 | env->v7m.other_sp = val; |
abc24d86 | 10167 | } |
9ee6e8bb PB |
10168 | break; |
10169 | case 16: /* PRIMASK */ | |
6d804834 | 10170 | env->v7m.primask[env->v7m.secure] = val & 1; |
9ee6e8bb | 10171 | break; |
82845826 | 10172 | case 17: /* BASEPRI */ |
acf94941 | 10173 | env->v7m.basepri[env->v7m.secure] = val & 0xff; |
9ee6e8bb | 10174 | break; |
82845826 | 10175 | case 18: /* BASEPRI_MAX */ |
9ee6e8bb | 10176 | val &= 0xff; |
acf94941 PM |
10177 | if (val != 0 && (val < env->v7m.basepri[env->v7m.secure] |
10178 | || env->v7m.basepri[env->v7m.secure] == 0)) { | |
10179 | env->v7m.basepri[env->v7m.secure] = val; | |
10180 | } | |
9ee6e8bb | 10181 | break; |
82845826 | 10182 | case 19: /* FAULTMASK */ |
42a6686b | 10183 | env->v7m.faultmask[env->v7m.secure] = val & 1; |
82845826 | 10184 | break; |
9ee6e8bb | 10185 | case 20: /* CONTROL */ |
792dac30 PM |
10186 | /* Writing to the SPSEL bit only has an effect if we are in |
10187 | * thread mode; other bits can be updated by any privileged code. | |
de2db7ec | 10188 | * write_v7m_control_spsel() deals with updating the SPSEL bit in |
792dac30 | 10189 | * env->v7m.control, so we only need update the others. |
83d7f86d PM |
10190 | * For v7M, we must just ignore explicit writes to SPSEL in handler |
10191 | * mode; for v8M the write is permitted but will have no effect. | |
792dac30 | 10192 | */ |
83d7f86d PM |
10193 | if (arm_feature(env, ARM_FEATURE_V8) || |
10194 | !arm_v7m_is_handler_mode(env)) { | |
de2db7ec | 10195 | write_v7m_control_spsel(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0); |
792dac30 | 10196 | } |
8bfc26ea PM |
10197 | env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK; |
10198 | env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK; | |
9ee6e8bb PB |
10199 | break; |
10200 | default: | |
58117c9b MD |
10201 | qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special" |
10202 | " register %d\n", reg); | |
9ee6e8bb PB |
10203 | return; |
10204 | } | |
10205 | } | |
10206 | ||
5158de24 PM |
10207 | uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) |
10208 | { | |
10209 | /* Implement the TT instruction. op is bits [7:6] of the insn. */ | |
10210 | bool forceunpriv = op & 1; | |
10211 | bool alt = op & 2; | |
10212 | V8M_SAttributes sattrs = {}; | |
10213 | uint32_t tt_resp; | |
10214 | bool r, rw, nsr, nsrw, mrvalid; | |
10215 | int prot; | |
3f551b5b | 10216 | ARMMMUFaultInfo fi = {}; |
5158de24 PM |
10217 | MemTxAttrs attrs = {}; |
10218 | hwaddr phys_addr; | |
5158de24 PM |
10219 | ARMMMUIdx mmu_idx; |
10220 | uint32_t mregion; | |
10221 | bool targetpriv; | |
10222 | bool targetsec = env->v7m.secure; | |
10223 | ||
10224 | /* Work out what the security state and privilege level we're | |
10225 | * interested in is... | |
10226 | */ | |
10227 | if (alt) { | |
10228 | targetsec = !targetsec; | |
10229 | } | |
10230 | ||
10231 | if (forceunpriv) { | |
10232 | targetpriv = false; | |
10233 | } else { | |
10234 | targetpriv = arm_v7m_is_handler_mode(env) || | |
10235 | !(env->v7m.control[targetsec] & R_V7M_CONTROL_NPRIV_MASK); | |
10236 | } | |
10237 | ||
10238 | /* ...and then figure out which MMU index this is */ | |
10239 | mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, targetsec, targetpriv); | |
10240 | ||
10241 | /* We know that the MPU and SAU don't care about the access type | |
10242 | * for our purposes beyond that we don't want to claim to be | |
10243 | * an insn fetch, so we arbitrarily call this a read. | |
10244 | */ | |
10245 | ||
10246 | /* MPU region info only available for privileged or if | |
10247 | * inspecting the other MPU state. | |
10248 | */ | |
10249 | if (arm_current_el(env) != 0 || alt) { | |
10250 | /* We can ignore the return value as prot is always set */ | |
10251 | pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, | |
3f551b5b | 10252 | &phys_addr, &attrs, &prot, &fi, &mregion); |
5158de24 PM |
10253 | if (mregion == -1) { |
10254 | mrvalid = false; | |
10255 | mregion = 0; | |
10256 | } else { | |
10257 | mrvalid = true; | |
10258 | } | |
10259 | r = prot & PAGE_READ; | |
10260 | rw = prot & PAGE_WRITE; | |
10261 | } else { | |
10262 | r = false; | |
10263 | rw = false; | |
10264 | mrvalid = false; | |
10265 | mregion = 0; | |
10266 | } | |
10267 | ||
10268 | if (env->v7m.secure) { | |
10269 | v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs); | |
10270 | nsr = sattrs.ns && r; | |
10271 | nsrw = sattrs.ns && rw; | |
10272 | } else { | |
10273 | sattrs.ns = true; | |
10274 | nsr = false; | |
10275 | nsrw = false; | |
10276 | } | |
10277 | ||
10278 | tt_resp = (sattrs.iregion << 24) | | |
10279 | (sattrs.irvalid << 23) | | |
10280 | ((!sattrs.ns) << 22) | | |
10281 | (nsrw << 21) | | |
10282 | (nsr << 20) | | |
10283 | (rw << 19) | | |
10284 | (r << 18) | | |
10285 | (sattrs.srvalid << 17) | | |
10286 | (mrvalid << 16) | | |
10287 | (sattrs.sregion << 8) | | |
10288 | mregion; | |
10289 | ||
10290 | return tt_resp; | |
10291 | } | |
10292 | ||
b5ff1b31 | 10293 | #endif |
6ddbc6e4 | 10294 | |
aca3f40b PM |
10295 | void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) |
10296 | { | |
10297 | /* Implement DC ZVA, which zeroes a fixed-length block of memory. | |
10298 | * Note that we do not implement the (architecturally mandated) | |
10299 | * alignment fault for attempts to use this on Device memory | |
10300 | * (which matches the usual QEMU behaviour of not implementing either | |
10301 | * alignment faults or any memory attribute handling). | |
10302 | */ | |
10303 | ||
10304 | ARMCPU *cpu = arm_env_get_cpu(env); | |
10305 | uint64_t blocklen = 4 << cpu->dcz_blocksize; | |
10306 | uint64_t vaddr = vaddr_in & ~(blocklen - 1); | |
10307 | ||
10308 | #ifndef CONFIG_USER_ONLY | |
10309 | { | |
10310 | /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than | |
10311 | * the block size so we might have to do more than one TLB lookup. | |
10312 | * We know that in fact for any v8 CPU the page size is at least 4K | |
10313 | * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only | |
10314 | * 1K as an artefact of legacy v5 subpage support being present in the | |
10315 | * same QEMU executable. | |
10316 | */ | |
10317 | int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); | |
10318 | void *hostaddr[maxidx]; | |
10319 | int try, i; | |
97ed5ccd | 10320 | unsigned mmu_idx = cpu_mmu_index(env, false); |
3972ef6f | 10321 | TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); |
aca3f40b PM |
10322 | |
10323 | for (try = 0; try < 2; try++) { | |
10324 | ||
10325 | for (i = 0; i < maxidx; i++) { | |
10326 | hostaddr[i] = tlb_vaddr_to_host(env, | |
10327 | vaddr + TARGET_PAGE_SIZE * i, | |
3972ef6f | 10328 | 1, mmu_idx); |
aca3f40b PM |
10329 | if (!hostaddr[i]) { |
10330 | break; | |
10331 | } | |
10332 | } | |
10333 | if (i == maxidx) { | |
10334 | /* If it's all in the TLB it's fair game for just writing to; | |
10335 | * we know we don't need to update dirty status, etc. | |
10336 | */ | |
10337 | for (i = 0; i < maxidx - 1; i++) { | |
10338 | memset(hostaddr[i], 0, TARGET_PAGE_SIZE); | |
10339 | } | |
10340 | memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); | |
10341 | return; | |
10342 | } | |
10343 | /* OK, try a store and see if we can populate the tlb. This | |
10344 | * might cause an exception if the memory isn't writable, | |
10345 | * in which case we will longjmp out of here. We must for | |
10346 | * this purpose use the actual register value passed to us | |
10347 | * so that we get the fault address right. | |
10348 | */ | |
01ecaf43 | 10349 | helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC()); |
aca3f40b PM |
10350 | /* Now we can populate the other TLB entries, if any */ |
10351 | for (i = 0; i < maxidx; i++) { | |
10352 | uint64_t va = vaddr + TARGET_PAGE_SIZE * i; | |
10353 | if (va != (vaddr_in & TARGET_PAGE_MASK)) { | |
01ecaf43 | 10354 | helper_ret_stb_mmu(env, va, 0, oi, GETPC()); |
aca3f40b PM |
10355 | } |
10356 | } | |
10357 | } | |
10358 | ||
10359 | /* Slow path (probably attempt to do this to an I/O device or | |
10360 | * similar, or clearing of a block of code we have translations | |
10361 | * cached for). Just do a series of byte writes as the architecture | |
10362 | * demands. It's not worth trying to use a cpu_physical_memory_map(), | |
10363 | * memset(), unmap() sequence here because: | |
10364 | * + we'd need to account for the blocksize being larger than a page | |
10365 | * + the direct-RAM access case is almost always going to be dealt | |
10366 | * with in the fastpath code above, so there's no speed benefit | |
10367 | * + we would have to deal with the map returning NULL because the | |
10368 | * bounce buffer was in use | |
10369 | */ | |
10370 | for (i = 0; i < blocklen; i++) { | |
01ecaf43 | 10371 | helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC()); |
aca3f40b PM |
10372 | } |
10373 | } | |
10374 | #else | |
10375 | memset(g2h(vaddr), 0, blocklen); | |
10376 | #endif | |
10377 | } | |
10378 | ||
6ddbc6e4 PB |
10379 | /* Note that signed overflow is undefined in C. The following routines are |
10380 | careful to use unsigned types where modulo arithmetic is required. | |
10381 | Failure to do so _will_ break on newer gcc. */ | |
10382 | ||
10383 | /* Signed saturating arithmetic. */ | |
10384 | ||
1654b2d6 | 10385 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
10386 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
10387 | { | |
10388 | uint16_t res; | |
10389 | ||
10390 | res = a + b; | |
10391 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
10392 | if (a & 0x8000) | |
10393 | res = 0x8000; | |
10394 | else | |
10395 | res = 0x7fff; | |
10396 | } | |
10397 | return res; | |
10398 | } | |
10399 | ||
1654b2d6 | 10400 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
10401 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
10402 | { | |
10403 | uint8_t res; | |
10404 | ||
10405 | res = a + b; | |
10406 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
10407 | if (a & 0x80) | |
10408 | res = 0x80; | |
10409 | else | |
10410 | res = 0x7f; | |
10411 | } | |
10412 | return res; | |
10413 | } | |
10414 | ||
1654b2d6 | 10415 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
10416 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
10417 | { | |
10418 | uint16_t res; | |
10419 | ||
10420 | res = a - b; | |
10421 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
10422 | if (a & 0x8000) | |
10423 | res = 0x8000; | |
10424 | else | |
10425 | res = 0x7fff; | |
10426 | } | |
10427 | return res; | |
10428 | } | |
10429 | ||
1654b2d6 | 10430 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
10431 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
10432 | { | |
10433 | uint8_t res; | |
10434 | ||
10435 | res = a - b; | |
10436 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
10437 | if (a & 0x80) | |
10438 | res = 0x80; | |
10439 | else | |
10440 | res = 0x7f; | |
10441 | } | |
10442 | return res; | |
10443 | } | |
10444 | ||
10445 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
10446 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
10447 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
10448 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
10449 | #define PFX q | |
10450 | ||
10451 | #include "op_addsub.h" | |
10452 | ||
10453 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 10454 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
10455 | { |
10456 | uint16_t res; | |
10457 | res = a + b; | |
10458 | if (res < a) | |
10459 | res = 0xffff; | |
10460 | return res; | |
10461 | } | |
10462 | ||
460a09c1 | 10463 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 | 10464 | { |
4c4fd3f8 | 10465 | if (a > b) |
6ddbc6e4 PB |
10466 | return a - b; |
10467 | else | |
10468 | return 0; | |
10469 | } | |
10470 | ||
10471 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
10472 | { | |
10473 | uint8_t res; | |
10474 | res = a + b; | |
10475 | if (res < a) | |
10476 | res = 0xff; | |
10477 | return res; | |
10478 | } | |
10479 | ||
10480 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
10481 | { | |
4c4fd3f8 | 10482 | if (a > b) |
6ddbc6e4 PB |
10483 | return a - b; |
10484 | else | |
10485 | return 0; | |
10486 | } | |
10487 | ||
10488 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
10489 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
10490 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
10491 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
10492 | #define PFX uq | |
10493 | ||
10494 | #include "op_addsub.h" | |
10495 | ||
10496 | /* Signed modulo arithmetic. */ | |
10497 | #define SARITH16(a, b, n, op) do { \ | |
10498 | int32_t sum; \ | |
db6e2e65 | 10499 | sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
6ddbc6e4 PB |
10500 | RESULT(sum, n, 16); \ |
10501 | if (sum >= 0) \ | |
10502 | ge |= 3 << (n * 2); \ | |
10503 | } while(0) | |
10504 | ||
10505 | #define SARITH8(a, b, n, op) do { \ | |
10506 | int32_t sum; \ | |
db6e2e65 | 10507 | sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
6ddbc6e4 PB |
10508 | RESULT(sum, n, 8); \ |
10509 | if (sum >= 0) \ | |
10510 | ge |= 1 << n; \ | |
10511 | } while(0) | |
10512 | ||
10513 | ||
10514 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
10515 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
10516 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
10517 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
10518 | #define PFX s | |
10519 | #define ARITH_GE | |
10520 | ||
10521 | #include "op_addsub.h" | |
10522 | ||
10523 | /* Unsigned modulo arithmetic. */ | |
10524 | #define ADD16(a, b, n) do { \ | |
10525 | uint32_t sum; \ | |
10526 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
10527 | RESULT(sum, n, 16); \ | |
a87aa10b | 10528 | if ((sum >> 16) == 1) \ |
6ddbc6e4 PB |
10529 | ge |= 3 << (n * 2); \ |
10530 | } while(0) | |
10531 | ||
10532 | #define ADD8(a, b, n) do { \ | |
10533 | uint32_t sum; \ | |
10534 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
10535 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
10536 | if ((sum >> 8) == 1) \ |
10537 | ge |= 1 << n; \ | |
6ddbc6e4 PB |
10538 | } while(0) |
10539 | ||
10540 | #define SUB16(a, b, n) do { \ | |
10541 | uint32_t sum; \ | |
10542 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
10543 | RESULT(sum, n, 16); \ | |
10544 | if ((sum >> 16) == 0) \ | |
10545 | ge |= 3 << (n * 2); \ | |
10546 | } while(0) | |
10547 | ||
10548 | #define SUB8(a, b, n) do { \ | |
10549 | uint32_t sum; \ | |
10550 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
10551 | RESULT(sum, n, 8); \ | |
10552 | if ((sum >> 8) == 0) \ | |
a87aa10b | 10553 | ge |= 1 << n; \ |
6ddbc6e4 PB |
10554 | } while(0) |
10555 | ||
10556 | #define PFX u | |
10557 | #define ARITH_GE | |
10558 | ||
10559 | #include "op_addsub.h" | |
10560 | ||
10561 | /* Halved signed arithmetic. */ | |
10562 | #define ADD16(a, b, n) \ | |
10563 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
10564 | #define SUB16(a, b, n) \ | |
10565 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
10566 | #define ADD8(a, b, n) \ | |
10567 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
10568 | #define SUB8(a, b, n) \ | |
10569 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
10570 | #define PFX sh | |
10571 | ||
10572 | #include "op_addsub.h" | |
10573 | ||
10574 | /* Halved unsigned arithmetic. */ | |
10575 | #define ADD16(a, b, n) \ | |
10576 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
10577 | #define SUB16(a, b, n) \ | |
10578 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
10579 | #define ADD8(a, b, n) \ | |
10580 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
10581 | #define SUB8(a, b, n) \ | |
10582 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
10583 | #define PFX uh | |
10584 | ||
10585 | #include "op_addsub.h" | |
10586 | ||
10587 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
10588 | { | |
10589 | if (a > b) | |
10590 | return a - b; | |
10591 | else | |
10592 | return b - a; | |
10593 | } | |
10594 | ||
10595 | /* Unsigned sum of absolute byte differences. */ | |
10596 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
10597 | { | |
10598 | uint32_t sum; | |
10599 | sum = do_usad(a, b); | |
10600 | sum += do_usad(a >> 8, b >> 8); | |
10601 | sum += do_usad(a >> 16, b >>16); | |
10602 | sum += do_usad(a >> 24, b >> 24); | |
10603 | return sum; | |
10604 | } | |
10605 | ||
10606 | /* For ARMv6 SEL instruction. */ | |
10607 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
10608 | { | |
10609 | uint32_t mask; | |
10610 | ||
10611 | mask = 0; | |
10612 | if (flags & 1) | |
10613 | mask |= 0xff; | |
10614 | if (flags & 2) | |
10615 | mask |= 0xff00; | |
10616 | if (flags & 4) | |
10617 | mask |= 0xff0000; | |
10618 | if (flags & 8) | |
10619 | mask |= 0xff000000; | |
10620 | return (a & mask) | (b & ~mask); | |
10621 | } | |
10622 | ||
b90372ad PM |
10623 | /* VFP support. We follow the convention used for VFP instructions: |
10624 | Single precision routines have a "s" suffix, double precision a | |
4373f3ce PB |
10625 | "d" suffix. */ |
10626 | ||
10627 | /* Convert host exception flags to vfp form. */ | |
10628 | static inline int vfp_exceptbits_from_host(int host_bits) | |
10629 | { | |
10630 | int target_bits = 0; | |
10631 | ||
10632 | if (host_bits & float_flag_invalid) | |
10633 | target_bits |= 1; | |
10634 | if (host_bits & float_flag_divbyzero) | |
10635 | target_bits |= 2; | |
10636 | if (host_bits & float_flag_overflow) | |
10637 | target_bits |= 4; | |
36802b6b | 10638 | if (host_bits & (float_flag_underflow | float_flag_output_denormal)) |
4373f3ce PB |
10639 | target_bits |= 8; |
10640 | if (host_bits & float_flag_inexact) | |
10641 | target_bits |= 0x10; | |
cecd8504 PM |
10642 | if (host_bits & float_flag_input_denormal) |
10643 | target_bits |= 0x80; | |
4373f3ce PB |
10644 | return target_bits; |
10645 | } | |
10646 | ||
0ecb72a5 | 10647 | uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) |
4373f3ce PB |
10648 | { |
10649 | int i; | |
10650 | uint32_t fpscr; | |
10651 | ||
10652 | fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) | |
10653 | | (env->vfp.vec_len << 16) | |
10654 | | (env->vfp.vec_stride << 20); | |
10655 | i = get_float_exception_flags(&env->vfp.fp_status); | |
3a492f3a | 10656 | i |= get_float_exception_flags(&env->vfp.standard_fp_status); |
4373f3ce PB |
10657 | fpscr |= vfp_exceptbits_from_host(i); |
10658 | return fpscr; | |
10659 | } | |
10660 | ||
0ecb72a5 | 10661 | uint32_t vfp_get_fpscr(CPUARMState *env) |
01653295 PM |
10662 | { |
10663 | return HELPER(vfp_get_fpscr)(env); | |
10664 | } | |
10665 | ||
4373f3ce PB |
10666 | /* Convert vfp exception flags to target form. */ |
10667 | static inline int vfp_exceptbits_to_host(int target_bits) | |
10668 | { | |
10669 | int host_bits = 0; | |
10670 | ||
10671 | if (target_bits & 1) | |
10672 | host_bits |= float_flag_invalid; | |
10673 | if (target_bits & 2) | |
10674 | host_bits |= float_flag_divbyzero; | |
10675 | if (target_bits & 4) | |
10676 | host_bits |= float_flag_overflow; | |
10677 | if (target_bits & 8) | |
10678 | host_bits |= float_flag_underflow; | |
10679 | if (target_bits & 0x10) | |
10680 | host_bits |= float_flag_inexact; | |
cecd8504 PM |
10681 | if (target_bits & 0x80) |
10682 | host_bits |= float_flag_input_denormal; | |
4373f3ce PB |
10683 | return host_bits; |
10684 | } | |
10685 | ||
0ecb72a5 | 10686 | void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) |
4373f3ce PB |
10687 | { |
10688 | int i; | |
10689 | uint32_t changed; | |
10690 | ||
10691 | changed = env->vfp.xregs[ARM_VFP_FPSCR]; | |
10692 | env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); | |
10693 | env->vfp.vec_len = (val >> 16) & 7; | |
10694 | env->vfp.vec_stride = (val >> 20) & 3; | |
10695 | ||
10696 | changed ^= val; | |
10697 | if (changed & (3 << 22)) { | |
10698 | i = (val >> 22) & 3; | |
10699 | switch (i) { | |
4d3da0f3 | 10700 | case FPROUNDING_TIEEVEN: |
4373f3ce PB |
10701 | i = float_round_nearest_even; |
10702 | break; | |
4d3da0f3 | 10703 | case FPROUNDING_POSINF: |
4373f3ce PB |
10704 | i = float_round_up; |
10705 | break; | |
4d3da0f3 | 10706 | case FPROUNDING_NEGINF: |
4373f3ce PB |
10707 | i = float_round_down; |
10708 | break; | |
4d3da0f3 | 10709 | case FPROUNDING_ZERO: |
4373f3ce PB |
10710 | i = float_round_to_zero; |
10711 | break; | |
10712 | } | |
10713 | set_float_rounding_mode(i, &env->vfp.fp_status); | |
10714 | } | |
cecd8504 | 10715 | if (changed & (1 << 24)) { |
fe76d976 | 10716 | set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
cecd8504 PM |
10717 | set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); |
10718 | } | |
5c7908ed PB |
10719 | if (changed & (1 << 25)) |
10720 | set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); | |
4373f3ce | 10721 | |
b12c390b | 10722 | i = vfp_exceptbits_to_host(val); |
4373f3ce | 10723 | set_float_exception_flags(i, &env->vfp.fp_status); |
3a492f3a | 10724 | set_float_exception_flags(0, &env->vfp.standard_fp_status); |
4373f3ce PB |
10725 | } |
10726 | ||
0ecb72a5 | 10727 | void vfp_set_fpscr(CPUARMState *env, uint32_t val) |
01653295 PM |
10728 | { |
10729 | HELPER(vfp_set_fpscr)(env, val); | |
10730 | } | |
10731 | ||
4373f3ce PB |
10732 | #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) |
10733 | ||
10734 | #define VFP_BINOP(name) \ | |
ae1857ec | 10735 | float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ |
4373f3ce | 10736 | { \ |
ae1857ec PM |
10737 | float_status *fpst = fpstp; \ |
10738 | return float32_ ## name(a, b, fpst); \ | |
4373f3ce | 10739 | } \ |
ae1857ec | 10740 | float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ |
4373f3ce | 10741 | { \ |
ae1857ec PM |
10742 | float_status *fpst = fpstp; \ |
10743 | return float64_ ## name(a, b, fpst); \ | |
4373f3ce PB |
10744 | } |
10745 | VFP_BINOP(add) | |
10746 | VFP_BINOP(sub) | |
10747 | VFP_BINOP(mul) | |
10748 | VFP_BINOP(div) | |
f71a2ae5 PM |
10749 | VFP_BINOP(min) |
10750 | VFP_BINOP(max) | |
10751 | VFP_BINOP(minnum) | |
10752 | VFP_BINOP(maxnum) | |
4373f3ce PB |
10753 | #undef VFP_BINOP |
10754 | ||
10755 | float32 VFP_HELPER(neg, s)(float32 a) | |
10756 | { | |
10757 | return float32_chs(a); | |
10758 | } | |
10759 | ||
10760 | float64 VFP_HELPER(neg, d)(float64 a) | |
10761 | { | |
66230e0d | 10762 | return float64_chs(a); |
4373f3ce PB |
10763 | } |
10764 | ||
10765 | float32 VFP_HELPER(abs, s)(float32 a) | |
10766 | { | |
10767 | return float32_abs(a); | |
10768 | } | |
10769 | ||
10770 | float64 VFP_HELPER(abs, d)(float64 a) | |
10771 | { | |
66230e0d | 10772 | return float64_abs(a); |
4373f3ce PB |
10773 | } |
10774 | ||
0ecb72a5 | 10775 | float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) |
4373f3ce PB |
10776 | { |
10777 | return float32_sqrt(a, &env->vfp.fp_status); | |
10778 | } | |
10779 | ||
0ecb72a5 | 10780 | float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) |
4373f3ce PB |
10781 | { |
10782 | return float64_sqrt(a, &env->vfp.fp_status); | |
10783 | } | |
10784 | ||
10785 | /* XXX: check quiet/signaling case */ | |
10786 | #define DO_VFP_cmp(p, type) \ | |
0ecb72a5 | 10787 | void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
10788 | { \ |
10789 | uint32_t flags; \ | |
10790 | switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ | |
10791 | case 0: flags = 0x6; break; \ | |
10792 | case -1: flags = 0x8; break; \ | |
10793 | case 1: flags = 0x2; break; \ | |
10794 | default: case 2: flags = 0x3; break; \ | |
10795 | } \ | |
10796 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
10797 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
10798 | } \ | |
0ecb72a5 | 10799 | void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
10800 | { \ |
10801 | uint32_t flags; \ | |
10802 | switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ | |
10803 | case 0: flags = 0x6; break; \ | |
10804 | case -1: flags = 0x8; break; \ | |
10805 | case 1: flags = 0x2; break; \ | |
10806 | default: case 2: flags = 0x3; break; \ | |
10807 | } \ | |
10808 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
10809 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
10810 | } | |
10811 | DO_VFP_cmp(s, float32) | |
10812 | DO_VFP_cmp(d, float64) | |
10813 | #undef DO_VFP_cmp | |
10814 | ||
5500b06c | 10815 | /* Integer to float and float to integer conversions */ |
4373f3ce | 10816 | |
5500b06c PM |
10817 | #define CONV_ITOF(name, fsz, sign) \ |
10818 | float##fsz HELPER(name)(uint32_t x, void *fpstp) \ | |
10819 | { \ | |
10820 | float_status *fpst = fpstp; \ | |
85836979 | 10821 | return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ |
4373f3ce PB |
10822 | } |
10823 | ||
5500b06c PM |
10824 | #define CONV_FTOI(name, fsz, sign, round) \ |
10825 | uint32_t HELPER(name)(float##fsz x, void *fpstp) \ | |
10826 | { \ | |
10827 | float_status *fpst = fpstp; \ | |
10828 | if (float##fsz##_is_any_nan(x)) { \ | |
10829 | float_raise(float_flag_invalid, fpst); \ | |
10830 | return 0; \ | |
10831 | } \ | |
10832 | return float##fsz##_to_##sign##int32##round(x, fpst); \ | |
4373f3ce PB |
10833 | } |
10834 | ||
5500b06c PM |
10835 | #define FLOAT_CONVS(name, p, fsz, sign) \ |
10836 | CONV_ITOF(vfp_##name##to##p, fsz, sign) \ | |
10837 | CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ | |
10838 | CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) | |
4373f3ce | 10839 | |
5500b06c PM |
10840 | FLOAT_CONVS(si, s, 32, ) |
10841 | FLOAT_CONVS(si, d, 64, ) | |
10842 | FLOAT_CONVS(ui, s, 32, u) | |
10843 | FLOAT_CONVS(ui, d, 64, u) | |
4373f3ce | 10844 | |
5500b06c PM |
10845 | #undef CONV_ITOF |
10846 | #undef CONV_FTOI | |
10847 | #undef FLOAT_CONVS | |
4373f3ce PB |
10848 | |
10849 | /* floating point conversion */ | |
0ecb72a5 | 10850 | float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) |
4373f3ce | 10851 | { |
2d627737 PM |
10852 | float64 r = float32_to_float64(x, &env->vfp.fp_status); |
10853 | /* ARM requires that S<->D conversion of any kind of NaN generates | |
10854 | * a quiet NaN by forcing the most significant frac bit to 1. | |
10855 | */ | |
af39bc8c | 10856 | return float64_maybe_silence_nan(r, &env->vfp.fp_status); |
4373f3ce PB |
10857 | } |
10858 | ||
0ecb72a5 | 10859 | float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) |
4373f3ce | 10860 | { |
2d627737 PM |
10861 | float32 r = float64_to_float32(x, &env->vfp.fp_status); |
10862 | /* ARM requires that S<->D conversion of any kind of NaN generates | |
10863 | * a quiet NaN by forcing the most significant frac bit to 1. | |
10864 | */ | |
af39bc8c | 10865 | return float32_maybe_silence_nan(r, &env->vfp.fp_status); |
4373f3ce PB |
10866 | } |
10867 | ||
10868 | /* VFP3 fixed point conversion. */ | |
16d5b3ca | 10869 | #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ |
8ed697e8 WN |
10870 | float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ |
10871 | void *fpstp) \ | |
4373f3ce | 10872 | { \ |
5500b06c | 10873 | float_status *fpst = fpstp; \ |
622465e1 | 10874 | float##fsz tmp; \ |
8ed697e8 | 10875 | tmp = itype##_to_##float##fsz(x, fpst); \ |
5500b06c | 10876 | return float##fsz##_scalbn(tmp, -(int)shift, fpst); \ |
16d5b3ca WN |
10877 | } |
10878 | ||
abe66f70 PM |
10879 | /* Notice that we want only input-denormal exception flags from the |
10880 | * scalbn operation: the other possible flags (overflow+inexact if | |
10881 | * we overflow to infinity, output-denormal) aren't correct for the | |
10882 | * complete scale-and-convert operation. | |
10883 | */ | |
16d5b3ca WN |
10884 | #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \ |
10885 | uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \ | |
10886 | uint32_t shift, \ | |
10887 | void *fpstp) \ | |
4373f3ce | 10888 | { \ |
5500b06c | 10889 | float_status *fpst = fpstp; \ |
abe66f70 | 10890 | int old_exc_flags = get_float_exception_flags(fpst); \ |
622465e1 PM |
10891 | float##fsz tmp; \ |
10892 | if (float##fsz##_is_any_nan(x)) { \ | |
5500b06c | 10893 | float_raise(float_flag_invalid, fpst); \ |
622465e1 | 10894 | return 0; \ |
09d9487f | 10895 | } \ |
5500b06c | 10896 | tmp = float##fsz##_scalbn(x, shift, fpst); \ |
abe66f70 PM |
10897 | old_exc_flags |= get_float_exception_flags(fpst) \ |
10898 | & float_flag_input_denormal; \ | |
10899 | set_float_exception_flags(old_exc_flags, fpst); \ | |
16d5b3ca | 10900 | return float##fsz##_to_##itype##round(tmp, fpst); \ |
622465e1 PM |
10901 | } |
10902 | ||
16d5b3ca WN |
10903 | #define VFP_CONV_FIX(name, p, fsz, isz, itype) \ |
10904 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
3c6a074a WN |
10905 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \ |
10906 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) | |
10907 | ||
10908 | #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \ | |
10909 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
10910 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ) | |
16d5b3ca | 10911 | |
8ed697e8 WN |
10912 | VFP_CONV_FIX(sh, d, 64, 64, int16) |
10913 | VFP_CONV_FIX(sl, d, 64, 64, int32) | |
3c6a074a | 10914 | VFP_CONV_FIX_A64(sq, d, 64, 64, int64) |
8ed697e8 WN |
10915 | VFP_CONV_FIX(uh, d, 64, 64, uint16) |
10916 | VFP_CONV_FIX(ul, d, 64, 64, uint32) | |
3c6a074a | 10917 | VFP_CONV_FIX_A64(uq, d, 64, 64, uint64) |
8ed697e8 WN |
10918 | VFP_CONV_FIX(sh, s, 32, 32, int16) |
10919 | VFP_CONV_FIX(sl, s, 32, 32, int32) | |
3c6a074a | 10920 | VFP_CONV_FIX_A64(sq, s, 32, 64, int64) |
8ed697e8 WN |
10921 | VFP_CONV_FIX(uh, s, 32, 32, uint16) |
10922 | VFP_CONV_FIX(ul, s, 32, 32, uint32) | |
3c6a074a | 10923 | VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) |
4373f3ce | 10924 | #undef VFP_CONV_FIX |
16d5b3ca WN |
10925 | #undef VFP_CONV_FIX_FLOAT |
10926 | #undef VFP_CONV_FLOAT_FIX_ROUND | |
4373f3ce | 10927 | |
52a1f6a3 AG |
10928 | /* Set the current fp rounding mode and return the old one. |
10929 | * The argument is a softfloat float_round_ value. | |
10930 | */ | |
10931 | uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env) | |
10932 | { | |
10933 | float_status *fp_status = &env->vfp.fp_status; | |
10934 | ||
10935 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
10936 | set_float_rounding_mode(rmode, fp_status); | |
10937 | ||
10938 | return prev_rmode; | |
10939 | } | |
10940 | ||
43630e58 WN |
10941 | /* Set the current fp rounding mode in the standard fp status and return |
10942 | * the old one. This is for NEON instructions that need to change the | |
10943 | * rounding mode but wish to use the standard FPSCR values for everything | |
10944 | * else. Always set the rounding mode back to the correct value after | |
10945 | * modifying it. | |
10946 | * The argument is a softfloat float_round_ value. | |
10947 | */ | |
10948 | uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) | |
10949 | { | |
10950 | float_status *fp_status = &env->vfp.standard_fp_status; | |
10951 | ||
10952 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
10953 | set_float_rounding_mode(rmode, fp_status); | |
10954 | ||
10955 | return prev_rmode; | |
10956 | } | |
10957 | ||
60011498 | 10958 | /* Half precision conversions. */ |
0ecb72a5 | 10959 | static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s) |
60011498 | 10960 | { |
60011498 | 10961 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
fb91678d PM |
10962 | float32 r = float16_to_float32(make_float16(a), ieee, s); |
10963 | if (ieee) { | |
af39bc8c | 10964 | return float32_maybe_silence_nan(r, s); |
fb91678d PM |
10965 | } |
10966 | return r; | |
60011498 PB |
10967 | } |
10968 | ||
0ecb72a5 | 10969 | static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s) |
60011498 | 10970 | { |
60011498 | 10971 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; |
fb91678d PM |
10972 | float16 r = float32_to_float16(a, ieee, s); |
10973 | if (ieee) { | |
af39bc8c | 10974 | r = float16_maybe_silence_nan(r, s); |
fb91678d PM |
10975 | } |
10976 | return float16_val(r); | |
60011498 PB |
10977 | } |
10978 | ||
0ecb72a5 | 10979 | float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
2d981da7 PM |
10980 | { |
10981 | return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status); | |
10982 | } | |
10983 | ||
0ecb72a5 | 10984 | uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
2d981da7 PM |
10985 | { |
10986 | return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status); | |
10987 | } | |
10988 | ||
0ecb72a5 | 10989 | float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env) |
2d981da7 PM |
10990 | { |
10991 | return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status); | |
10992 | } | |
10993 | ||
0ecb72a5 | 10994 | uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env) |
2d981da7 PM |
10995 | { |
10996 | return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status); | |
10997 | } | |
10998 | ||
8900aad2 PM |
10999 | float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env) |
11000 | { | |
11001 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
11002 | float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status); | |
11003 | if (ieee) { | |
af39bc8c | 11004 | return float64_maybe_silence_nan(r, &env->vfp.fp_status); |
8900aad2 PM |
11005 | } |
11006 | return r; | |
11007 | } | |
11008 | ||
11009 | uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env) | |
11010 | { | |
11011 | int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0; | |
11012 | float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status); | |
11013 | if (ieee) { | |
af39bc8c | 11014 | r = float16_maybe_silence_nan(r, &env->vfp.fp_status); |
8900aad2 PM |
11015 | } |
11016 | return float16_val(r); | |
11017 | } | |
11018 | ||
dda3ec49 | 11019 | #define float32_two make_float32(0x40000000) |
6aae3df1 PM |
11020 | #define float32_three make_float32(0x40400000) |
11021 | #define float32_one_point_five make_float32(0x3fc00000) | |
dda3ec49 | 11022 | |
0ecb72a5 | 11023 | float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 11024 | { |
dda3ec49 PM |
11025 | float_status *s = &env->vfp.standard_fp_status; |
11026 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
11027 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
11028 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
11029 | float_raise(float_flag_input_denormal, s); | |
11030 | } | |
dda3ec49 PM |
11031 | return float32_two; |
11032 | } | |
11033 | return float32_sub(float32_two, float32_mul(a, b, s), s); | |
4373f3ce PB |
11034 | } |
11035 | ||
0ecb72a5 | 11036 | float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 11037 | { |
71826966 | 11038 | float_status *s = &env->vfp.standard_fp_status; |
9ea62f57 PM |
11039 | float32 product; |
11040 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
11041 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
11042 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
11043 | float_raise(float_flag_input_denormal, s); | |
11044 | } | |
6aae3df1 | 11045 | return float32_one_point_five; |
9ea62f57 | 11046 | } |
6aae3df1 PM |
11047 | product = float32_mul(a, b, s); |
11048 | return float32_div(float32_sub(float32_three, product, s), float32_two, s); | |
4373f3ce PB |
11049 | } |
11050 | ||
8f8e3aa4 PB |
11051 | /* NEON helpers. */ |
11052 | ||
56bf4fe2 CL |
11053 | /* Constants 256 and 512 are used in some helpers; we avoid relying on |
11054 | * int->float conversions at run-time. */ | |
11055 | #define float64_256 make_float64(0x4070000000000000LL) | |
11056 | #define float64_512 make_float64(0x4080000000000000LL) | |
b6d4443a AB |
11057 | #define float32_maxnorm make_float32(0x7f7fffff) |
11058 | #define float64_maxnorm make_float64(0x7fefffffffffffffLL) | |
56bf4fe2 | 11059 | |
b6d4443a AB |
11060 | /* Reciprocal functions |
11061 | * | |
11062 | * The algorithm that must be used to calculate the estimate | |
11063 | * is specified by the ARM ARM, see FPRecipEstimate() | |
fe0e4872 | 11064 | */ |
b6d4443a AB |
11065 | |
11066 | static float64 recip_estimate(float64 a, float_status *real_fp_status) | |
fe0e4872 | 11067 | { |
1146a817 PM |
11068 | /* These calculations mustn't set any fp exception flags, |
11069 | * so we use a local copy of the fp_status. | |
11070 | */ | |
b6d4443a | 11071 | float_status dummy_status = *real_fp_status; |
1146a817 | 11072 | float_status *s = &dummy_status; |
fe0e4872 CL |
11073 | /* q = (int)(a * 512.0) */ |
11074 | float64 q = float64_mul(float64_512, a, s); | |
11075 | int64_t q_int = float64_to_int64_round_to_zero(q, s); | |
11076 | ||
11077 | /* r = 1.0 / (((double)q + 0.5) / 512.0) */ | |
11078 | q = int64_to_float64(q_int, s); | |
11079 | q = float64_add(q, float64_half, s); | |
11080 | q = float64_div(q, float64_512, s); | |
11081 | q = float64_div(float64_one, q, s); | |
11082 | ||
11083 | /* s = (int)(256.0 * r + 0.5) */ | |
11084 | q = float64_mul(q, float64_256, s); | |
11085 | q = float64_add(q, float64_half, s); | |
11086 | q_int = float64_to_int64_round_to_zero(q, s); | |
11087 | ||
11088 | /* return (double)s / 256.0 */ | |
11089 | return float64_div(int64_to_float64(q_int, s), float64_256, s); | |
11090 | } | |
11091 | ||
b6d4443a AB |
11092 | /* Common wrapper to call recip_estimate */ |
11093 | static float64 call_recip_estimate(float64 num, int off, float_status *fpst) | |
4373f3ce | 11094 | { |
b6d4443a AB |
11095 | uint64_t val64 = float64_val(num); |
11096 | uint64_t frac = extract64(val64, 0, 52); | |
11097 | int64_t exp = extract64(val64, 52, 11); | |
11098 | uint64_t sbit; | |
11099 | float64 scaled, estimate; | |
fe0e4872 | 11100 | |
b6d4443a AB |
11101 | /* Generate the scaled number for the estimate function */ |
11102 | if (exp == 0) { | |
11103 | if (extract64(frac, 51, 1) == 0) { | |
11104 | exp = -1; | |
11105 | frac = extract64(frac, 0, 50) << 2; | |
11106 | } else { | |
11107 | frac = extract64(frac, 0, 51) << 1; | |
11108 | } | |
11109 | } | |
fe0e4872 | 11110 | |
b6d4443a AB |
11111 | /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */ |
11112 | scaled = make_float64((0x3feULL << 52) | |
11113 | | extract64(frac, 44, 8) << 44); | |
11114 | ||
11115 | estimate = recip_estimate(scaled, fpst); | |
11116 | ||
11117 | /* Build new result */ | |
11118 | val64 = float64_val(estimate); | |
11119 | sbit = 0x8000000000000000ULL & val64; | |
11120 | exp = off - exp; | |
11121 | frac = extract64(val64, 0, 52); | |
11122 | ||
11123 | if (exp == 0) { | |
11124 | frac = 1ULL << 51 | extract64(frac, 1, 51); | |
11125 | } else if (exp == -1) { | |
11126 | frac = 1ULL << 50 | extract64(frac, 2, 50); | |
11127 | exp = 0; | |
11128 | } | |
11129 | ||
11130 | return make_float64(sbit | (exp << 52) | frac); | |
11131 | } | |
11132 | ||
11133 | static bool round_to_inf(float_status *fpst, bool sign_bit) | |
11134 | { | |
11135 | switch (fpst->float_rounding_mode) { | |
11136 | case float_round_nearest_even: /* Round to Nearest */ | |
11137 | return true; | |
11138 | case float_round_up: /* Round to +Inf */ | |
11139 | return !sign_bit; | |
11140 | case float_round_down: /* Round to -Inf */ | |
11141 | return sign_bit; | |
11142 | case float_round_to_zero: /* Round to Zero */ | |
11143 | return false; | |
11144 | } | |
11145 | ||
11146 | g_assert_not_reached(); | |
11147 | } | |
11148 | ||
11149 | float32 HELPER(recpe_f32)(float32 input, void *fpstp) | |
11150 | { | |
11151 | float_status *fpst = fpstp; | |
11152 | float32 f32 = float32_squash_input_denormal(input, fpst); | |
11153 | uint32_t f32_val = float32_val(f32); | |
11154 | uint32_t f32_sbit = 0x80000000ULL & f32_val; | |
11155 | int32_t f32_exp = extract32(f32_val, 23, 8); | |
11156 | uint32_t f32_frac = extract32(f32_val, 0, 23); | |
11157 | float64 f64, r64; | |
11158 | uint64_t r64_val; | |
11159 | int64_t r64_exp; | |
11160 | uint64_t r64_frac; | |
11161 | ||
11162 | if (float32_is_any_nan(f32)) { | |
11163 | float32 nan = f32; | |
af39bc8c | 11164 | if (float32_is_signaling_nan(f32, fpst)) { |
b6d4443a | 11165 | float_raise(float_flag_invalid, fpst); |
af39bc8c | 11166 | nan = float32_maybe_silence_nan(f32, fpst); |
fe0e4872 | 11167 | } |
b6d4443a | 11168 | if (fpst->default_nan_mode) { |
af39bc8c | 11169 | nan = float32_default_nan(fpst); |
43fe9bdb | 11170 | } |
b6d4443a AB |
11171 | return nan; |
11172 | } else if (float32_is_infinity(f32)) { | |
11173 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
11174 | } else if (float32_is_zero(f32)) { | |
11175 | float_raise(float_flag_divbyzero, fpst); | |
11176 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
11177 | } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) { | |
11178 | /* Abs(value) < 2.0^-128 */ | |
11179 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
11180 | if (round_to_inf(fpst, f32_sbit)) { | |
11181 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
11182 | } else { | |
11183 | return float32_set_sign(float32_maxnorm, float32_is_neg(f32)); | |
11184 | } | |
11185 | } else if (f32_exp >= 253 && fpst->flush_to_zero) { | |
11186 | float_raise(float_flag_underflow, fpst); | |
11187 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
fe0e4872 CL |
11188 | } |
11189 | ||
fe0e4872 | 11190 | |
b6d4443a AB |
11191 | f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29); |
11192 | r64 = call_recip_estimate(f64, 253, fpst); | |
11193 | r64_val = float64_val(r64); | |
11194 | r64_exp = extract64(r64_val, 52, 11); | |
11195 | r64_frac = extract64(r64_val, 0, 52); | |
11196 | ||
11197 | /* result = sign : result_exp<7:0> : fraction<51:29>; */ | |
11198 | return make_float32(f32_sbit | | |
11199 | (r64_exp & 0xff) << 23 | | |
11200 | extract64(r64_frac, 29, 24)); | |
11201 | } | |
11202 | ||
11203 | float64 HELPER(recpe_f64)(float64 input, void *fpstp) | |
11204 | { | |
11205 | float_status *fpst = fpstp; | |
11206 | float64 f64 = float64_squash_input_denormal(input, fpst); | |
11207 | uint64_t f64_val = float64_val(f64); | |
11208 | uint64_t f64_sbit = 0x8000000000000000ULL & f64_val; | |
11209 | int64_t f64_exp = extract64(f64_val, 52, 11); | |
11210 | float64 r64; | |
11211 | uint64_t r64_val; | |
11212 | int64_t r64_exp; | |
11213 | uint64_t r64_frac; | |
11214 | ||
11215 | /* Deal with any special cases */ | |
11216 | if (float64_is_any_nan(f64)) { | |
11217 | float64 nan = f64; | |
af39bc8c | 11218 | if (float64_is_signaling_nan(f64, fpst)) { |
b6d4443a | 11219 | float_raise(float_flag_invalid, fpst); |
af39bc8c | 11220 | nan = float64_maybe_silence_nan(f64, fpst); |
b6d4443a AB |
11221 | } |
11222 | if (fpst->default_nan_mode) { | |
af39bc8c | 11223 | nan = float64_default_nan(fpst); |
b6d4443a AB |
11224 | } |
11225 | return nan; | |
11226 | } else if (float64_is_infinity(f64)) { | |
11227 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
11228 | } else if (float64_is_zero(f64)) { | |
11229 | float_raise(float_flag_divbyzero, fpst); | |
11230 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
11231 | } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { | |
11232 | /* Abs(value) < 2.0^-1024 */ | |
11233 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
11234 | if (round_to_inf(fpst, f64_sbit)) { | |
11235 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
11236 | } else { | |
11237 | return float64_set_sign(float64_maxnorm, float64_is_neg(f64)); | |
11238 | } | |
fc1792e9 | 11239 | } else if (f64_exp >= 2045 && fpst->flush_to_zero) { |
b6d4443a AB |
11240 | float_raise(float_flag_underflow, fpst); |
11241 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
11242 | } | |
fe0e4872 | 11243 | |
b6d4443a AB |
11244 | r64 = call_recip_estimate(f64, 2045, fpst); |
11245 | r64_val = float64_val(r64); | |
11246 | r64_exp = extract64(r64_val, 52, 11); | |
11247 | r64_frac = extract64(r64_val, 0, 52); | |
fe0e4872 | 11248 | |
b6d4443a AB |
11249 | /* result = sign : result_exp<10:0> : fraction<51:0> */ |
11250 | return make_float64(f64_sbit | | |
11251 | ((r64_exp & 0x7ff) << 52) | | |
11252 | r64_frac); | |
4373f3ce PB |
11253 | } |
11254 | ||
e07be5d2 CL |
11255 | /* The algorithm that must be used to calculate the estimate |
11256 | * is specified by the ARM ARM. | |
11257 | */ | |
c2fb418e | 11258 | static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status) |
e07be5d2 | 11259 | { |
1146a817 PM |
11260 | /* These calculations mustn't set any fp exception flags, |
11261 | * so we use a local copy of the fp_status. | |
11262 | */ | |
c2fb418e | 11263 | float_status dummy_status = *real_fp_status; |
1146a817 | 11264 | float_status *s = &dummy_status; |
e07be5d2 CL |
11265 | float64 q; |
11266 | int64_t q_int; | |
11267 | ||
11268 | if (float64_lt(a, float64_half, s)) { | |
11269 | /* range 0.25 <= a < 0.5 */ | |
11270 | ||
11271 | /* a in units of 1/512 rounded down */ | |
11272 | /* q0 = (int)(a * 512.0); */ | |
11273 | q = float64_mul(float64_512, a, s); | |
11274 | q_int = float64_to_int64_round_to_zero(q, s); | |
11275 | ||
11276 | /* reciprocal root r */ | |
11277 | /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */ | |
11278 | q = int64_to_float64(q_int, s); | |
11279 | q = float64_add(q, float64_half, s); | |
11280 | q = float64_div(q, float64_512, s); | |
11281 | q = float64_sqrt(q, s); | |
11282 | q = float64_div(float64_one, q, s); | |
11283 | } else { | |
11284 | /* range 0.5 <= a < 1.0 */ | |
11285 | ||
11286 | /* a in units of 1/256 rounded down */ | |
11287 | /* q1 = (int)(a * 256.0); */ | |
11288 | q = float64_mul(float64_256, a, s); | |
11289 | int64_t q_int = float64_to_int64_round_to_zero(q, s); | |
11290 | ||
11291 | /* reciprocal root r */ | |
11292 | /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */ | |
11293 | q = int64_to_float64(q_int, s); | |
11294 | q = float64_add(q, float64_half, s); | |
11295 | q = float64_div(q, float64_256, s); | |
11296 | q = float64_sqrt(q, s); | |
11297 | q = float64_div(float64_one, q, s); | |
11298 | } | |
11299 | /* r in units of 1/256 rounded to nearest */ | |
11300 | /* s = (int)(256.0 * r + 0.5); */ | |
11301 | ||
11302 | q = float64_mul(q, float64_256,s ); | |
11303 | q = float64_add(q, float64_half, s); | |
11304 | q_int = float64_to_int64_round_to_zero(q, s); | |
11305 | ||
11306 | /* return (double)s / 256.0;*/ | |
11307 | return float64_div(int64_to_float64(q_int, s), float64_256, s); | |
11308 | } | |
11309 | ||
c2fb418e | 11310 | float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) |
4373f3ce | 11311 | { |
c2fb418e AB |
11312 | float_status *s = fpstp; |
11313 | float32 f32 = float32_squash_input_denormal(input, s); | |
11314 | uint32_t val = float32_val(f32); | |
11315 | uint32_t f32_sbit = 0x80000000 & val; | |
11316 | int32_t f32_exp = extract32(val, 23, 8); | |
11317 | uint32_t f32_frac = extract32(val, 0, 23); | |
11318 | uint64_t f64_frac; | |
11319 | uint64_t val64; | |
e07be5d2 CL |
11320 | int result_exp; |
11321 | float64 f64; | |
e07be5d2 | 11322 | |
c2fb418e AB |
11323 | if (float32_is_any_nan(f32)) { |
11324 | float32 nan = f32; | |
af39bc8c | 11325 | if (float32_is_signaling_nan(f32, s)) { |
e07be5d2 | 11326 | float_raise(float_flag_invalid, s); |
af39bc8c | 11327 | nan = float32_maybe_silence_nan(f32, s); |
e07be5d2 | 11328 | } |
c2fb418e | 11329 | if (s->default_nan_mode) { |
af39bc8c | 11330 | nan = float32_default_nan(s); |
43fe9bdb | 11331 | } |
c2fb418e AB |
11332 | return nan; |
11333 | } else if (float32_is_zero(f32)) { | |
e07be5d2 | 11334 | float_raise(float_flag_divbyzero, s); |
c2fb418e AB |
11335 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); |
11336 | } else if (float32_is_neg(f32)) { | |
e07be5d2 | 11337 | float_raise(float_flag_invalid, s); |
af39bc8c | 11338 | return float32_default_nan(s); |
c2fb418e | 11339 | } else if (float32_is_infinity(f32)) { |
e07be5d2 CL |
11340 | return float32_zero; |
11341 | } | |
11342 | ||
c2fb418e | 11343 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, |
e07be5d2 | 11344 | * preserving the parity of the exponent. */ |
c2fb418e AB |
11345 | |
11346 | f64_frac = ((uint64_t) f32_frac) << 29; | |
11347 | if (f32_exp == 0) { | |
11348 | while (extract64(f64_frac, 51, 1) == 0) { | |
11349 | f64_frac = f64_frac << 1; | |
11350 | f32_exp = f32_exp-1; | |
11351 | } | |
11352 | f64_frac = extract64(f64_frac, 0, 51) << 1; | |
11353 | } | |
11354 | ||
11355 | if (extract64(f32_exp, 0, 1) == 0) { | |
11356 | f64 = make_float64(((uint64_t) f32_sbit) << 32 | |
e07be5d2 | 11357 | | (0x3feULL << 52) |
c2fb418e | 11358 | | f64_frac); |
e07be5d2 | 11359 | } else { |
c2fb418e | 11360 | f64 = make_float64(((uint64_t) f32_sbit) << 32 |
e07be5d2 | 11361 | | (0x3fdULL << 52) |
c2fb418e | 11362 | | f64_frac); |
e07be5d2 CL |
11363 | } |
11364 | ||
c2fb418e | 11365 | result_exp = (380 - f32_exp) / 2; |
e07be5d2 | 11366 | |
c2fb418e | 11367 | f64 = recip_sqrt_estimate(f64, s); |
e07be5d2 CL |
11368 | |
11369 | val64 = float64_val(f64); | |
11370 | ||
26cc6abf | 11371 | val = ((result_exp & 0xff) << 23) |
e07be5d2 CL |
11372 | | ((val64 >> 29) & 0x7fffff); |
11373 | return make_float32(val); | |
4373f3ce PB |
11374 | } |
11375 | ||
c2fb418e AB |
11376 | float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) |
11377 | { | |
11378 | float_status *s = fpstp; | |
11379 | float64 f64 = float64_squash_input_denormal(input, s); | |
11380 | uint64_t val = float64_val(f64); | |
11381 | uint64_t f64_sbit = 0x8000000000000000ULL & val; | |
11382 | int64_t f64_exp = extract64(val, 52, 11); | |
11383 | uint64_t f64_frac = extract64(val, 0, 52); | |
11384 | int64_t result_exp; | |
11385 | uint64_t result_frac; | |
11386 | ||
11387 | if (float64_is_any_nan(f64)) { | |
11388 | float64 nan = f64; | |
af39bc8c | 11389 | if (float64_is_signaling_nan(f64, s)) { |
c2fb418e | 11390 | float_raise(float_flag_invalid, s); |
af39bc8c | 11391 | nan = float64_maybe_silence_nan(f64, s); |
c2fb418e AB |
11392 | } |
11393 | if (s->default_nan_mode) { | |
af39bc8c | 11394 | nan = float64_default_nan(s); |
c2fb418e AB |
11395 | } |
11396 | return nan; | |
11397 | } else if (float64_is_zero(f64)) { | |
11398 | float_raise(float_flag_divbyzero, s); | |
11399 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
11400 | } else if (float64_is_neg(f64)) { | |
11401 | float_raise(float_flag_invalid, s); | |
af39bc8c | 11402 | return float64_default_nan(s); |
c2fb418e AB |
11403 | } else if (float64_is_infinity(f64)) { |
11404 | return float64_zero; | |
11405 | } | |
11406 | ||
11407 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, | |
11408 | * preserving the parity of the exponent. */ | |
11409 | ||
11410 | if (f64_exp == 0) { | |
11411 | while (extract64(f64_frac, 51, 1) == 0) { | |
11412 | f64_frac = f64_frac << 1; | |
11413 | f64_exp = f64_exp - 1; | |
11414 | } | |
11415 | f64_frac = extract64(f64_frac, 0, 51) << 1; | |
11416 | } | |
11417 | ||
11418 | if (extract64(f64_exp, 0, 1) == 0) { | |
11419 | f64 = make_float64(f64_sbit | |
11420 | | (0x3feULL << 52) | |
11421 | | f64_frac); | |
11422 | } else { | |
11423 | f64 = make_float64(f64_sbit | |
11424 | | (0x3fdULL << 52) | |
11425 | | f64_frac); | |
11426 | } | |
11427 | ||
11428 | result_exp = (3068 - f64_exp) / 2; | |
11429 | ||
11430 | f64 = recip_sqrt_estimate(f64, s); | |
11431 | ||
11432 | result_frac = extract64(float64_val(f64), 0, 52); | |
11433 | ||
11434 | return make_float64(f64_sbit | | |
11435 | ((result_exp & 0x7ff) << 52) | | |
11436 | result_frac); | |
11437 | } | |
11438 | ||
b6d4443a | 11439 | uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) |
4373f3ce | 11440 | { |
b6d4443a | 11441 | float_status *s = fpstp; |
fe0e4872 CL |
11442 | float64 f64; |
11443 | ||
11444 | if ((a & 0x80000000) == 0) { | |
11445 | return 0xffffffff; | |
11446 | } | |
11447 | ||
11448 | f64 = make_float64((0x3feULL << 52) | |
11449 | | ((int64_t)(a & 0x7fffffff) << 21)); | |
11450 | ||
b6d4443a | 11451 | f64 = recip_estimate(f64, s); |
fe0e4872 CL |
11452 | |
11453 | return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); | |
4373f3ce PB |
11454 | } |
11455 | ||
c2fb418e | 11456 | uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) |
4373f3ce | 11457 | { |
c2fb418e | 11458 | float_status *fpst = fpstp; |
e07be5d2 CL |
11459 | float64 f64; |
11460 | ||
11461 | if ((a & 0xc0000000) == 0) { | |
11462 | return 0xffffffff; | |
11463 | } | |
11464 | ||
11465 | if (a & 0x80000000) { | |
11466 | f64 = make_float64((0x3feULL << 52) | |
11467 | | ((uint64_t)(a & 0x7fffffff) << 21)); | |
11468 | } else { /* bits 31-30 == '01' */ | |
11469 | f64 = make_float64((0x3fdULL << 52) | |
11470 | | ((uint64_t)(a & 0x3fffffff) << 22)); | |
11471 | } | |
11472 | ||
c2fb418e | 11473 | f64 = recip_sqrt_estimate(f64, fpst); |
e07be5d2 CL |
11474 | |
11475 | return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); | |
4373f3ce | 11476 | } |
fe1479c3 | 11477 | |
da97f52c PM |
11478 | /* VFPv4 fused multiply-accumulate */ |
11479 | float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) | |
11480 | { | |
11481 | float_status *fpst = fpstp; | |
11482 | return float32_muladd(a, b, c, 0, fpst); | |
11483 | } | |
11484 | ||
11485 | float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) | |
11486 | { | |
11487 | float_status *fpst = fpstp; | |
11488 | return float64_muladd(a, b, c, 0, fpst); | |
11489 | } | |
d9b0848d PM |
11490 | |
11491 | /* ARMv8 round to integral */ | |
11492 | float32 HELPER(rints_exact)(float32 x, void *fp_status) | |
11493 | { | |
11494 | return float32_round_to_int(x, fp_status); | |
11495 | } | |
11496 | ||
11497 | float64 HELPER(rintd_exact)(float64 x, void *fp_status) | |
11498 | { | |
11499 | return float64_round_to_int(x, fp_status); | |
11500 | } | |
11501 | ||
11502 | float32 HELPER(rints)(float32 x, void *fp_status) | |
11503 | { | |
11504 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
11505 | float32 ret; | |
11506 | ||
11507 | ret = float32_round_to_int(x, fp_status); | |
11508 | ||
11509 | /* Suppress any inexact exceptions the conversion produced */ | |
11510 | if (!(old_flags & float_flag_inexact)) { | |
11511 | new_flags = get_float_exception_flags(fp_status); | |
11512 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
11513 | } | |
11514 | ||
11515 | return ret; | |
11516 | } | |
11517 | ||
11518 | float64 HELPER(rintd)(float64 x, void *fp_status) | |
11519 | { | |
11520 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
11521 | float64 ret; | |
11522 | ||
11523 | ret = float64_round_to_int(x, fp_status); | |
11524 | ||
11525 | new_flags = get_float_exception_flags(fp_status); | |
11526 | ||
11527 | /* Suppress any inexact exceptions the conversion produced */ | |
11528 | if (!(old_flags & float_flag_inexact)) { | |
11529 | new_flags = get_float_exception_flags(fp_status); | |
11530 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
11531 | } | |
11532 | ||
11533 | return ret; | |
11534 | } | |
9972da66 WN |
11535 | |
11536 | /* Convert ARM rounding mode to softfloat */ | |
11537 | int arm_rmode_to_sf(int rmode) | |
11538 | { | |
11539 | switch (rmode) { | |
11540 | case FPROUNDING_TIEAWAY: | |
11541 | rmode = float_round_ties_away; | |
11542 | break; | |
11543 | case FPROUNDING_ODD: | |
11544 | /* FIXME: add support for TIEAWAY and ODD */ | |
11545 | qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", | |
11546 | rmode); | |
11547 | case FPROUNDING_TIEEVEN: | |
11548 | default: | |
11549 | rmode = float_round_nearest_even; | |
11550 | break; | |
11551 | case FPROUNDING_POSINF: | |
11552 | rmode = float_round_up; | |
11553 | break; | |
11554 | case FPROUNDING_NEGINF: | |
11555 | rmode = float_round_down; | |
11556 | break; | |
11557 | case FPROUNDING_ZERO: | |
11558 | rmode = float_round_to_zero; | |
11559 | break; | |
11560 | } | |
11561 | return rmode; | |
11562 | } | |
eb0ecd5a | 11563 | |
aa633469 PM |
11564 | /* CRC helpers. |
11565 | * The upper bytes of val (above the number specified by 'bytes') must have | |
11566 | * been zeroed out by the caller. | |
11567 | */ | |
eb0ecd5a WN |
11568 | uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) |
11569 | { | |
11570 | uint8_t buf[4]; | |
11571 | ||
aa633469 | 11572 | stl_le_p(buf, val); |
eb0ecd5a WN |
11573 | |
11574 | /* zlib crc32 converts the accumulator and output to one's complement. */ | |
11575 | return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | |
11576 | } | |
11577 | ||
11578 | uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | |
11579 | { | |
11580 | uint8_t buf[4]; | |
11581 | ||
aa633469 | 11582 | stl_le_p(buf, val); |
eb0ecd5a WN |
11583 | |
11584 | /* Linux crc32c converts the output to one's complement. */ | |
11585 | return crc32c(acc, buf, bytes) ^ 0xffffffff; | |
11586 | } |