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74c21bd0 | 1 | #include "qemu/osdep.h" |
181962fd | 2 | #include "target/arm/idau.h" |
194cbc49 | 3 | #include "trace.h" |
b5ff1b31 | 4 | #include "cpu.h" |
ccd38087 | 5 | #include "internals.h" |
022c62cb | 6 | #include "exec/gdbstub.h" |
2ef6175a | 7 | #include "exec/helper-proto.h" |
1de7afc9 | 8 | #include "qemu/host-utils.h" |
78027bb6 | 9 | #include "sysemu/arch_init.h" |
9c17d615 | 10 | #include "sysemu/sysemu.h" |
1de7afc9 | 11 | #include "qemu/bitops.h" |
eb0ecd5a | 12 | #include "qemu/crc32c.h" |
63c91552 | 13 | #include "exec/exec-all.h" |
f08b6170 | 14 | #include "exec/cpu_ldst.h" |
1d854765 | 15 | #include "arm_ldst.h" |
eb0ecd5a | 16 | #include <zlib.h> /* For crc32 */ |
cfe67cef | 17 | #include "exec/semihost.h" |
b2e23725 | 18 | #include "sysemu/cpus.h" |
f3a9b694 | 19 | #include "sysemu/kvm.h" |
24f91e81 | 20 | #include "fpu/softfloat.h" |
9d2b5a58 | 21 | #include "qemu/range.h" |
0b03bdfc | 22 | |
352c98e5 LV |
23 | #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ |
24 | ||
4a501606 | 25 | #ifndef CONFIG_USER_ONLY |
5b2d261d AB |
26 | /* Cacheability and shareability attributes for a memory access */ |
27 | typedef struct ARMCacheAttrs { | |
28 | unsigned int attrs:8; /* as in the MAIR register encoding */ | |
29 | unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */ | |
30 | } ARMCacheAttrs; | |
31 | ||
af51f566 | 32 | static bool get_phys_addr(CPUARMState *env, target_ulong address, |
03ae85f8 | 33 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
af51f566 | 34 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, |
bc52bfeb | 35 | target_ulong *page_size, |
5b2d261d | 36 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); |
7c2cb42b | 37 | |
37785977 | 38 | static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
03ae85f8 | 39 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
37785977 | 40 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, |
da909b2c | 41 | target_ulong *page_size_ptr, |
5b2d261d | 42 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); |
37785977 | 43 | |
35337cc3 PM |
44 | /* Security attributes for an address, as returned by v8m_security_lookup. */ |
45 | typedef struct V8M_SAttributes { | |
72042435 | 46 | bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */ |
35337cc3 PM |
47 | bool ns; |
48 | bool nsc; | |
49 | uint8_t sregion; | |
50 | bool srvalid; | |
51 | uint8_t iregion; | |
52 | bool irvalid; | |
53 | } V8M_SAttributes; | |
54 | ||
333e10c5 PM |
55 | static void v8m_security_lookup(CPUARMState *env, uint32_t address, |
56 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
57 | V8M_SAttributes *sattrs); | |
4a501606 PM |
58 | #endif |
59 | ||
affdb64d PM |
60 | static void switch_mode(CPUARMState *env, int mode); |
61 | ||
0ecb72a5 | 62 | static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
63 | { |
64 | int nregs; | |
65 | ||
66 | /* VFP data registers are always little-endian. */ | |
67 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
68 | if (reg < nregs) { | |
9a2b5256 | 69 | stq_le_p(buf, *aa32_vfp_dreg(env, reg)); |
56aebc89 PB |
70 | return 8; |
71 | } | |
72 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
73 | /* Aliases for Q regs. */ | |
74 | nregs += 16; | |
75 | if (reg < nregs) { | |
9a2b5256 RH |
76 | uint64_t *q = aa32_vfp_qreg(env, reg - 32); |
77 | stq_le_p(buf, q[0]); | |
78 | stq_le_p(buf + 8, q[1]); | |
56aebc89 PB |
79 | return 16; |
80 | } | |
81 | } | |
82 | switch (reg - nregs) { | |
83 | case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; | |
84 | case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; | |
85 | case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; | |
86 | } | |
87 | return 0; | |
88 | } | |
89 | ||
0ecb72a5 | 90 | static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
91 | { |
92 | int nregs; | |
93 | ||
94 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
95 | if (reg < nregs) { | |
9a2b5256 | 96 | *aa32_vfp_dreg(env, reg) = ldq_le_p(buf); |
56aebc89 PB |
97 | return 8; |
98 | } | |
99 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
100 | nregs += 16; | |
101 | if (reg < nregs) { | |
9a2b5256 RH |
102 | uint64_t *q = aa32_vfp_qreg(env, reg - 32); |
103 | q[0] = ldq_le_p(buf); | |
104 | q[1] = ldq_le_p(buf + 8); | |
56aebc89 PB |
105 | return 16; |
106 | } | |
107 | } | |
108 | switch (reg - nregs) { | |
109 | case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; | |
110 | case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; | |
71b3c3de | 111 | case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
56aebc89 PB |
112 | } |
113 | return 0; | |
114 | } | |
115 | ||
6a669427 PM |
116 | static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
117 | { | |
118 | switch (reg) { | |
119 | case 0 ... 31: | |
120 | /* 128 bit FP register */ | |
9a2b5256 RH |
121 | { |
122 | uint64_t *q = aa64_vfp_qreg(env, reg); | |
123 | stq_le_p(buf, q[0]); | |
124 | stq_le_p(buf + 8, q[1]); | |
125 | return 16; | |
126 | } | |
6a669427 PM |
127 | case 32: |
128 | /* FPSR */ | |
129 | stl_p(buf, vfp_get_fpsr(env)); | |
130 | return 4; | |
131 | case 33: | |
132 | /* FPCR */ | |
133 | stl_p(buf, vfp_get_fpcr(env)); | |
134 | return 4; | |
135 | default: | |
136 | return 0; | |
137 | } | |
138 | } | |
139 | ||
140 | static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) | |
141 | { | |
142 | switch (reg) { | |
143 | case 0 ... 31: | |
144 | /* 128 bit FP register */ | |
9a2b5256 RH |
145 | { |
146 | uint64_t *q = aa64_vfp_qreg(env, reg); | |
147 | q[0] = ldq_le_p(buf); | |
148 | q[1] = ldq_le_p(buf + 8); | |
149 | return 16; | |
150 | } | |
6a669427 PM |
151 | case 32: |
152 | /* FPSR */ | |
153 | vfp_set_fpsr(env, ldl_p(buf)); | |
154 | return 4; | |
155 | case 33: | |
156 | /* FPCR */ | |
157 | vfp_set_fpcr(env, ldl_p(buf)); | |
158 | return 4; | |
159 | default: | |
160 | return 0; | |
161 | } | |
162 | } | |
163 | ||
c4241c7d | 164 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) |
d4e6df63 | 165 | { |
375421cc | 166 | assert(ri->fieldoffset); |
67ed771d | 167 | if (cpreg_field_is_64bit(ri)) { |
c4241c7d | 168 | return CPREG_FIELD64(env, ri); |
22d9e1a9 | 169 | } else { |
c4241c7d | 170 | return CPREG_FIELD32(env, ri); |
22d9e1a9 | 171 | } |
d4e6df63 PM |
172 | } |
173 | ||
c4241c7d PM |
174 | static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
175 | uint64_t value) | |
d4e6df63 | 176 | { |
375421cc | 177 | assert(ri->fieldoffset); |
67ed771d | 178 | if (cpreg_field_is_64bit(ri)) { |
22d9e1a9 PM |
179 | CPREG_FIELD64(env, ri) = value; |
180 | } else { | |
181 | CPREG_FIELD32(env, ri) = value; | |
182 | } | |
d4e6df63 PM |
183 | } |
184 | ||
11f136ee FA |
185 | static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) |
186 | { | |
187 | return (char *)env + ri->fieldoffset; | |
188 | } | |
189 | ||
49a66191 | 190 | uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) |
721fae12 | 191 | { |
59a1c327 | 192 | /* Raw read of a coprocessor register (as needed for migration, etc). */ |
721fae12 | 193 | if (ri->type & ARM_CP_CONST) { |
59a1c327 | 194 | return ri->resetvalue; |
721fae12 | 195 | } else if (ri->raw_readfn) { |
59a1c327 | 196 | return ri->raw_readfn(env, ri); |
721fae12 | 197 | } else if (ri->readfn) { |
59a1c327 | 198 | return ri->readfn(env, ri); |
721fae12 | 199 | } else { |
59a1c327 | 200 | return raw_read(env, ri); |
721fae12 | 201 | } |
721fae12 PM |
202 | } |
203 | ||
59a1c327 | 204 | static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, |
7900e9f1 | 205 | uint64_t v) |
721fae12 PM |
206 | { |
207 | /* Raw write of a coprocessor register (as needed for migration, etc). | |
721fae12 PM |
208 | * Note that constant registers are treated as write-ignored; the |
209 | * caller should check for success by whether a readback gives the | |
210 | * value written. | |
211 | */ | |
212 | if (ri->type & ARM_CP_CONST) { | |
59a1c327 | 213 | return; |
721fae12 | 214 | } else if (ri->raw_writefn) { |
c4241c7d | 215 | ri->raw_writefn(env, ri, v); |
721fae12 | 216 | } else if (ri->writefn) { |
c4241c7d | 217 | ri->writefn(env, ri, v); |
721fae12 | 218 | } else { |
afb2530f | 219 | raw_write(env, ri, v); |
721fae12 | 220 | } |
721fae12 PM |
221 | } |
222 | ||
200bf5b7 AB |
223 | static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg) |
224 | { | |
225 | ARMCPU *cpu = arm_env_get_cpu(env); | |
226 | const ARMCPRegInfo *ri; | |
227 | uint32_t key; | |
228 | ||
229 | key = cpu->dyn_xml.cpregs_keys[reg]; | |
230 | ri = get_arm_cp_reginfo(cpu->cp_regs, key); | |
231 | if (ri) { | |
232 | if (cpreg_field_is_64bit(ri)) { | |
233 | return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); | |
234 | } else { | |
235 | return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); | |
236 | } | |
237 | } | |
238 | return 0; | |
239 | } | |
240 | ||
241 | static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) | |
242 | { | |
243 | return 0; | |
244 | } | |
245 | ||
375421cc PM |
246 | static bool raw_accessors_invalid(const ARMCPRegInfo *ri) |
247 | { | |
248 | /* Return true if the regdef would cause an assertion if you called | |
249 | * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a | |
250 | * program bug for it not to have the NO_RAW flag). | |
251 | * NB that returning false here doesn't necessarily mean that calling | |
252 | * read/write_raw_cp_reg() is safe, because we can't distinguish "has | |
253 | * read/write access functions which are safe for raw use" from "has | |
254 | * read/write access functions which have side effects but has forgotten | |
255 | * to provide raw access functions". | |
256 | * The tests here line up with the conditions in read/write_raw_cp_reg() | |
257 | * and assertions in raw_read()/raw_write(). | |
258 | */ | |
259 | if ((ri->type & ARM_CP_CONST) || | |
260 | ri->fieldoffset || | |
261 | ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { | |
262 | return false; | |
263 | } | |
264 | return true; | |
265 | } | |
266 | ||
721fae12 PM |
267 | bool write_cpustate_to_list(ARMCPU *cpu) |
268 | { | |
269 | /* Write the coprocessor state from cpu->env to the (index,value) list. */ | |
270 | int i; | |
271 | bool ok = true; | |
272 | ||
273 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
274 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
275 | const ARMCPRegInfo *ri; | |
59a1c327 | 276 | |
60322b39 | 277 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
278 | if (!ri) { |
279 | ok = false; | |
280 | continue; | |
281 | } | |
7a0e58fa | 282 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
283 | continue; |
284 | } | |
59a1c327 | 285 | cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri); |
721fae12 PM |
286 | } |
287 | return ok; | |
288 | } | |
289 | ||
290 | bool write_list_to_cpustate(ARMCPU *cpu) | |
291 | { | |
292 | int i; | |
293 | bool ok = true; | |
294 | ||
295 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
296 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
297 | uint64_t v = cpu->cpreg_values[i]; | |
721fae12 PM |
298 | const ARMCPRegInfo *ri; |
299 | ||
60322b39 | 300 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
301 | if (!ri) { |
302 | ok = false; | |
303 | continue; | |
304 | } | |
7a0e58fa | 305 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
306 | continue; |
307 | } | |
308 | /* Write value and confirm it reads back as written | |
309 | * (to catch read-only registers and partially read-only | |
310 | * registers where the incoming migration value doesn't match) | |
311 | */ | |
59a1c327 PM |
312 | write_raw_cp_reg(&cpu->env, ri, v); |
313 | if (read_raw_cp_reg(&cpu->env, ri) != v) { | |
721fae12 PM |
314 | ok = false; |
315 | } | |
316 | } | |
317 | return ok; | |
318 | } | |
319 | ||
320 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | |
321 | { | |
322 | ARMCPU *cpu = opaque; | |
323 | uint64_t regidx; | |
324 | const ARMCPRegInfo *ri; | |
325 | ||
326 | regidx = *(uint32_t *)key; | |
60322b39 | 327 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 | 328 | |
7a0e58fa | 329 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
330 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); |
331 | /* The value array need not be initialized at this point */ | |
332 | cpu->cpreg_array_len++; | |
333 | } | |
334 | } | |
335 | ||
336 | static void count_cpreg(gpointer key, gpointer opaque) | |
337 | { | |
338 | ARMCPU *cpu = opaque; | |
339 | uint64_t regidx; | |
340 | const ARMCPRegInfo *ri; | |
341 | ||
342 | regidx = *(uint32_t *)key; | |
60322b39 | 343 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 | 344 | |
7a0e58fa | 345 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
346 | cpu->cpreg_array_len++; |
347 | } | |
348 | } | |
349 | ||
350 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | |
351 | { | |
cbf239b7 AR |
352 | uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); |
353 | uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); | |
721fae12 | 354 | |
cbf239b7 AR |
355 | if (aidx > bidx) { |
356 | return 1; | |
357 | } | |
358 | if (aidx < bidx) { | |
359 | return -1; | |
360 | } | |
361 | return 0; | |
721fae12 PM |
362 | } |
363 | ||
364 | void init_cpreg_list(ARMCPU *cpu) | |
365 | { | |
366 | /* Initialise the cpreg_tuples[] array based on the cp_regs hash. | |
367 | * Note that we require cpreg_tuples[] to be sorted by key ID. | |
368 | */ | |
57b6d95e | 369 | GList *keys; |
721fae12 PM |
370 | int arraylen; |
371 | ||
57b6d95e | 372 | keys = g_hash_table_get_keys(cpu->cp_regs); |
721fae12 PM |
373 | keys = g_list_sort(keys, cpreg_key_compare); |
374 | ||
375 | cpu->cpreg_array_len = 0; | |
376 | ||
377 | g_list_foreach(keys, count_cpreg, cpu); | |
378 | ||
379 | arraylen = cpu->cpreg_array_len; | |
380 | cpu->cpreg_indexes = g_new(uint64_t, arraylen); | |
381 | cpu->cpreg_values = g_new(uint64_t, arraylen); | |
382 | cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); | |
383 | cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); | |
384 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; | |
385 | cpu->cpreg_array_len = 0; | |
386 | ||
387 | g_list_foreach(keys, add_cpreg_to_list, cpu); | |
388 | ||
389 | assert(cpu->cpreg_array_len == arraylen); | |
390 | ||
391 | g_list_free(keys); | |
392 | } | |
393 | ||
68e9c2fe EI |
394 | /* |
395 | * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but | |
396 | * they are accessible when EL3 is using AArch64 regardless of EL3.NS. | |
397 | * | |
398 | * access_el3_aa32ns: Used to check AArch32 register views. | |
399 | * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views. | |
400 | */ | |
401 | static CPAccessResult access_el3_aa32ns(CPUARMState *env, | |
3f208fd7 PM |
402 | const ARMCPRegInfo *ri, |
403 | bool isread) | |
68e9c2fe EI |
404 | { |
405 | bool secure = arm_is_secure_below_el3(env); | |
406 | ||
407 | assert(!arm_el_is_aa64(env, 3)); | |
408 | if (secure) { | |
409 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
410 | } | |
411 | return CP_ACCESS_OK; | |
412 | } | |
413 | ||
414 | static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env, | |
3f208fd7 PM |
415 | const ARMCPRegInfo *ri, |
416 | bool isread) | |
68e9c2fe EI |
417 | { |
418 | if (!arm_el_is_aa64(env, 3)) { | |
3f208fd7 | 419 | return access_el3_aa32ns(env, ri, isread); |
68e9c2fe EI |
420 | } |
421 | return CP_ACCESS_OK; | |
422 | } | |
423 | ||
5513c3ab PM |
424 | /* Some secure-only AArch32 registers trap to EL3 if used from |
425 | * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). | |
426 | * Note that an access from Secure EL1 can only happen if EL3 is AArch64. | |
427 | * We assume that the .access field is set to PL1_RW. | |
428 | */ | |
429 | static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, | |
3f208fd7 PM |
430 | const ARMCPRegInfo *ri, |
431 | bool isread) | |
5513c3ab PM |
432 | { |
433 | if (arm_current_el(env) == 3) { | |
434 | return CP_ACCESS_OK; | |
435 | } | |
436 | if (arm_is_secure_below_el3(env)) { | |
437 | return CP_ACCESS_TRAP_EL3; | |
438 | } | |
439 | /* This will be EL1 NS and EL2 NS, which just UNDEF */ | |
440 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
441 | } | |
442 | ||
187f678d PM |
443 | /* Check for traps to "powerdown debug" registers, which are controlled |
444 | * by MDCR.TDOSA | |
445 | */ | |
446 | static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, | |
447 | bool isread) | |
448 | { | |
449 | int el = arm_current_el(env); | |
30ac6339 PM |
450 | bool mdcr_el2_tdosa = (env->cp15.mdcr_el2 & MDCR_TDOSA) || |
451 | (env->cp15.mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 452 | (arm_hcr_el2_eff(env) & HCR_TGE); |
187f678d | 453 | |
30ac6339 | 454 | if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) { |
187f678d PM |
455 | return CP_ACCESS_TRAP_EL2; |
456 | } | |
457 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { | |
458 | return CP_ACCESS_TRAP_EL3; | |
459 | } | |
460 | return CP_ACCESS_OK; | |
461 | } | |
462 | ||
91b0a238 PM |
463 | /* Check for traps to "debug ROM" registers, which are controlled |
464 | * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. | |
465 | */ | |
466 | static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, | |
467 | bool isread) | |
468 | { | |
469 | int el = arm_current_el(env); | |
30ac6339 PM |
470 | bool mdcr_el2_tdra = (env->cp15.mdcr_el2 & MDCR_TDRA) || |
471 | (env->cp15.mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 472 | (arm_hcr_el2_eff(env) & HCR_TGE); |
91b0a238 | 473 | |
30ac6339 | 474 | if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) { |
91b0a238 PM |
475 | return CP_ACCESS_TRAP_EL2; |
476 | } | |
477 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
478 | return CP_ACCESS_TRAP_EL3; | |
479 | } | |
480 | return CP_ACCESS_OK; | |
481 | } | |
482 | ||
d6c8cf81 PM |
483 | /* Check for traps to general debug registers, which are controlled |
484 | * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. | |
485 | */ | |
486 | static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, | |
487 | bool isread) | |
488 | { | |
489 | int el = arm_current_el(env); | |
30ac6339 PM |
490 | bool mdcr_el2_tda = (env->cp15.mdcr_el2 & MDCR_TDA) || |
491 | (env->cp15.mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 492 | (arm_hcr_el2_eff(env) & HCR_TGE); |
d6c8cf81 | 493 | |
30ac6339 | 494 | if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) { |
d6c8cf81 PM |
495 | return CP_ACCESS_TRAP_EL2; |
496 | } | |
497 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
498 | return CP_ACCESS_TRAP_EL3; | |
499 | } | |
500 | return CP_ACCESS_OK; | |
501 | } | |
502 | ||
1fce1ba9 PM |
503 | /* Check for traps to performance monitor registers, which are controlled |
504 | * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. | |
505 | */ | |
506 | static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, | |
507 | bool isread) | |
508 | { | |
509 | int el = arm_current_el(env); | |
510 | ||
511 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) | |
512 | && !arm_is_secure_below_el3(env)) { | |
513 | return CP_ACCESS_TRAP_EL2; | |
514 | } | |
515 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
516 | return CP_ACCESS_TRAP_EL3; | |
517 | } | |
518 | return CP_ACCESS_OK; | |
519 | } | |
520 | ||
c4241c7d | 521 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
c983fe6c | 522 | { |
00c8cb0a AF |
523 | ARMCPU *cpu = arm_env_get_cpu(env); |
524 | ||
8d5c773e | 525 | raw_write(env, ri, value); |
d10eb08f | 526 | tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ |
c983fe6c PM |
527 | } |
528 | ||
c4241c7d | 529 | static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
08de207b | 530 | { |
00c8cb0a AF |
531 | ARMCPU *cpu = arm_env_get_cpu(env); |
532 | ||
8d5c773e | 533 | if (raw_read(env, ri) != value) { |
08de207b PM |
534 | /* Unlike real hardware the qemu TLB uses virtual addresses, |
535 | * not modified virtual addresses, so this causes a TLB flush. | |
536 | */ | |
d10eb08f | 537 | tlb_flush(CPU(cpu)); |
8d5c773e | 538 | raw_write(env, ri, value); |
08de207b | 539 | } |
08de207b | 540 | } |
c4241c7d PM |
541 | |
542 | static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
543 | uint64_t value) | |
08de207b | 544 | { |
00c8cb0a AF |
545 | ARMCPU *cpu = arm_env_get_cpu(env); |
546 | ||
452a0955 | 547 | if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) |
014406b5 | 548 | && !extended_addresses_enabled(env)) { |
08de207b PM |
549 | /* For VMSA (when not using the LPAE long descriptor page table |
550 | * format) this register includes the ASID, so do a TLB flush. | |
551 | * For PMSA it is purely a process ID and no action is needed. | |
552 | */ | |
d10eb08f | 553 | tlb_flush(CPU(cpu)); |
08de207b | 554 | } |
8d5c773e | 555 | raw_write(env, ri, value); |
08de207b PM |
556 | } |
557 | ||
b4ab8ce9 PM |
558 | /* IS variants of TLB operations must affect all cores */ |
559 | static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
560 | uint64_t value) | |
561 | { | |
562 | CPUState *cs = ENV_GET_CPU(env); | |
563 | ||
564 | tlb_flush_all_cpus_synced(cs); | |
565 | } | |
566 | ||
567 | static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
568 | uint64_t value) | |
569 | { | |
570 | CPUState *cs = ENV_GET_CPU(env); | |
571 | ||
572 | tlb_flush_all_cpus_synced(cs); | |
573 | } | |
574 | ||
575 | static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
576 | uint64_t value) | |
577 | { | |
578 | CPUState *cs = ENV_GET_CPU(env); | |
579 | ||
580 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
581 | } | |
582 | ||
583 | static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
584 | uint64_t value) | |
585 | { | |
586 | CPUState *cs = ENV_GET_CPU(env); | |
587 | ||
588 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
589 | } | |
590 | ||
591 | /* | |
592 | * Non-IS variants of TLB operations are upgraded to | |
593 | * IS versions if we are at NS EL1 and HCR_EL2.FB is set to | |
594 | * force broadcast of these operations. | |
595 | */ | |
596 | static bool tlb_force_broadcast(CPUARMState *env) | |
597 | { | |
598 | return (env->cp15.hcr_el2 & HCR_FB) && | |
599 | arm_current_el(env) == 1 && arm_is_secure_below_el3(env); | |
600 | } | |
601 | ||
c4241c7d PM |
602 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
603 | uint64_t value) | |
d929823f PM |
604 | { |
605 | /* Invalidate all (TLBIALL) */ | |
00c8cb0a AF |
606 | ARMCPU *cpu = arm_env_get_cpu(env); |
607 | ||
b4ab8ce9 PM |
608 | if (tlb_force_broadcast(env)) { |
609 | tlbiall_is_write(env, NULL, value); | |
610 | return; | |
611 | } | |
612 | ||
d10eb08f | 613 | tlb_flush(CPU(cpu)); |
d929823f PM |
614 | } |
615 | ||
c4241c7d PM |
616 | static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
617 | uint64_t value) | |
d929823f PM |
618 | { |
619 | /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ | |
31b030d4 AF |
620 | ARMCPU *cpu = arm_env_get_cpu(env); |
621 | ||
b4ab8ce9 PM |
622 | if (tlb_force_broadcast(env)) { |
623 | tlbimva_is_write(env, NULL, value); | |
624 | return; | |
625 | } | |
626 | ||
31b030d4 | 627 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); |
d929823f PM |
628 | } |
629 | ||
c4241c7d PM |
630 | static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
631 | uint64_t value) | |
d929823f PM |
632 | { |
633 | /* Invalidate by ASID (TLBIASID) */ | |
00c8cb0a AF |
634 | ARMCPU *cpu = arm_env_get_cpu(env); |
635 | ||
b4ab8ce9 PM |
636 | if (tlb_force_broadcast(env)) { |
637 | tlbiasid_is_write(env, NULL, value); | |
638 | return; | |
639 | } | |
640 | ||
d10eb08f | 641 | tlb_flush(CPU(cpu)); |
d929823f PM |
642 | } |
643 | ||
c4241c7d PM |
644 | static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
645 | uint64_t value) | |
d929823f PM |
646 | { |
647 | /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ | |
31b030d4 AF |
648 | ARMCPU *cpu = arm_env_get_cpu(env); |
649 | ||
b4ab8ce9 PM |
650 | if (tlb_force_broadcast(env)) { |
651 | tlbimvaa_is_write(env, NULL, value); | |
652 | return; | |
653 | } | |
fa439fc5 | 654 | |
b4ab8ce9 | 655 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); |
fa439fc5 PM |
656 | } |
657 | ||
541ef8c2 SS |
658 | static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, |
659 | uint64_t value) | |
660 | { | |
661 | CPUState *cs = ENV_GET_CPU(env); | |
662 | ||
0336cbf8 | 663 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
664 | ARMMMUIdxBit_S12NSE1 | |
665 | ARMMMUIdxBit_S12NSE0 | | |
666 | ARMMMUIdxBit_S2NS); | |
541ef8c2 SS |
667 | } |
668 | ||
669 | static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
670 | uint64_t value) | |
671 | { | |
a67cf277 | 672 | CPUState *cs = ENV_GET_CPU(env); |
541ef8c2 | 673 | |
a67cf277 | 674 | tlb_flush_by_mmuidx_all_cpus_synced(cs, |
8bd5c820 PM |
675 | ARMMMUIdxBit_S12NSE1 | |
676 | ARMMMUIdxBit_S12NSE0 | | |
677 | ARMMMUIdxBit_S2NS); | |
541ef8c2 SS |
678 | } |
679 | ||
680 | static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
681 | uint64_t value) | |
682 | { | |
683 | /* Invalidate by IPA. This has to invalidate any structures that | |
684 | * contain only stage 2 translation information, but does not need | |
685 | * to apply to structures that contain combined stage 1 and stage 2 | |
686 | * translation information. | |
687 | * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. | |
688 | */ | |
689 | CPUState *cs = ENV_GET_CPU(env); | |
690 | uint64_t pageaddr; | |
691 | ||
692 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
693 | return; | |
694 | } | |
695 | ||
696 | pageaddr = sextract64(value << 12, 0, 40); | |
697 | ||
8bd5c820 | 698 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); |
541ef8c2 SS |
699 | } |
700 | ||
701 | static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
702 | uint64_t value) | |
703 | { | |
a67cf277 | 704 | CPUState *cs = ENV_GET_CPU(env); |
541ef8c2 SS |
705 | uint64_t pageaddr; |
706 | ||
707 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
708 | return; | |
709 | } | |
710 | ||
711 | pageaddr = sextract64(value << 12, 0, 40); | |
712 | ||
a67cf277 | 713 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 714 | ARMMMUIdxBit_S2NS); |
541ef8c2 SS |
715 | } |
716 | ||
717 | static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
718 | uint64_t value) | |
719 | { | |
720 | CPUState *cs = ENV_GET_CPU(env); | |
721 | ||
8bd5c820 | 722 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
723 | } |
724 | ||
725 | static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
726 | uint64_t value) | |
727 | { | |
a67cf277 | 728 | CPUState *cs = ENV_GET_CPU(env); |
541ef8c2 | 729 | |
8bd5c820 | 730 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
731 | } |
732 | ||
733 | static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
734 | uint64_t value) | |
735 | { | |
736 | CPUState *cs = ENV_GET_CPU(env); | |
737 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); | |
738 | ||
8bd5c820 | 739 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
740 | } |
741 | ||
742 | static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
743 | uint64_t value) | |
744 | { | |
a67cf277 | 745 | CPUState *cs = ENV_GET_CPU(env); |
541ef8c2 SS |
746 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
747 | ||
a67cf277 | 748 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 749 | ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
750 | } |
751 | ||
e9aa6c21 | 752 | static const ARMCPRegInfo cp_reginfo[] = { |
54bf36ed FA |
753 | /* Define the secure and non-secure FCSE identifier CP registers |
754 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
755 | * the secure register to be properly reset and migrated. There is also no | |
756 | * v8 EL1 version of the register so the non-secure instance stands alone. | |
757 | */ | |
9c513e78 | 758 | { .name = "FCSEIDR", |
54bf36ed FA |
759 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
760 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, | |
761 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), | |
762 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, | |
9c513e78 | 763 | { .name = "FCSEIDR_S", |
54bf36ed FA |
764 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
765 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
766 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), | |
d4e6df63 | 767 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, |
54bf36ed FA |
768 | /* Define the secure and non-secure context identifier CP registers |
769 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
770 | * the secure register to be properly reset and migrated. In the | |
771 | * non-secure case, the 32-bit register will have reset and migration | |
772 | * disabled during registration as it is handled by the 64-bit instance. | |
773 | */ | |
774 | { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
014406b5 | 775 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
54bf36ed FA |
776 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, |
777 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), | |
778 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, | |
9c513e78 | 779 | { .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32, |
54bf36ed FA |
780 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
781 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
782 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), | |
d4e6df63 | 783 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, |
9449fdf6 PM |
784 | REGINFO_SENTINEL |
785 | }; | |
786 | ||
787 | static const ARMCPRegInfo not_v8_cp_reginfo[] = { | |
788 | /* NB: Some of these registers exist in v8 but with more precise | |
789 | * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). | |
790 | */ | |
791 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
792 | { .name = "DACR", |
793 | .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, | |
794 | .access = PL1_RW, .resetvalue = 0, | |
795 | .writefn = dacr_write, .raw_writefn = raw_write, | |
796 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
797 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a903c449 EI |
798 | /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. |
799 | * For v6 and v5, these mappings are overly broad. | |
4fdd17dd | 800 | */ |
a903c449 EI |
801 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0, |
802 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
803 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1, | |
804 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
805 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4, | |
806 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
807 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8, | |
4fdd17dd | 808 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, |
c4804214 PM |
809 | /* Cache maintenance ops; some of this space may be overridden later. */ |
810 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | |
811 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | |
812 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | |
e9aa6c21 PM |
813 | REGINFO_SENTINEL |
814 | }; | |
815 | ||
7d57f408 PM |
816 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
817 | /* Not all pre-v6 cores implemented this WFI, so this is slightly | |
818 | * over-broad. | |
819 | */ | |
820 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | |
821 | .access = PL1_W, .type = ARM_CP_WFI }, | |
822 | REGINFO_SENTINEL | |
823 | }; | |
824 | ||
825 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | |
826 | /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which | |
827 | * is UNPREDICTABLE; we choose to NOP as most implementations do). | |
828 | */ | |
829 | { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
830 | .access = PL1_W, .type = ARM_CP_WFI }, | |
34f90529 PM |
831 | /* L1 cache lockdown. Not architectural in v6 and earlier but in practice |
832 | * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and | |
833 | * OMAPCP will override this space. | |
834 | */ | |
835 | { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, | |
836 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), | |
837 | .resetvalue = 0 }, | |
838 | { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, | |
839 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), | |
840 | .resetvalue = 0 }, | |
776d4e5c PM |
841 | /* v6 doesn't have the cache ID registers but Linux reads them anyway */ |
842 | { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, | |
7a0e58fa | 843 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 844 | .resetvalue = 0 }, |
50300698 PM |
845 | /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; |
846 | * implementing it as RAZ means the "debug architecture version" bits | |
847 | * will read as a reserved value, which should cause Linux to not try | |
848 | * to use the debug hardware. | |
849 | */ | |
850 | { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
851 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
995939a6 PM |
852 | /* MMU TLB control. Note that the wildcarding means we cover not just |
853 | * the unified TLB ops but also the dside/iside/inner-shareable variants. | |
854 | */ | |
855 | { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, | |
856 | .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, | |
7a0e58fa | 857 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
858 | { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, |
859 | .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, | |
7a0e58fa | 860 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
861 | { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, |
862 | .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, | |
7a0e58fa | 863 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
864 | { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, |
865 | .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, | |
7a0e58fa | 866 | .type = ARM_CP_NO_RAW }, |
a903c449 EI |
867 | { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2, |
868 | .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, | |
869 | { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, | |
870 | .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, | |
7d57f408 PM |
871 | REGINFO_SENTINEL |
872 | }; | |
873 | ||
c4241c7d PM |
874 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
875 | uint64_t value) | |
2771db27 | 876 | { |
f0aff255 FA |
877 | uint32_t mask = 0; |
878 | ||
879 | /* In ARMv8 most bits of CPACR_EL1 are RES0. */ | |
880 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
881 | /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. | |
882 | * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. | |
883 | * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. | |
884 | */ | |
885 | if (arm_feature(env, ARM_FEATURE_VFP)) { | |
886 | /* VFP coprocessor: cp10 & cp11 [23:20] */ | |
887 | mask |= (1 << 31) | (1 << 30) | (0xf << 20); | |
888 | ||
889 | if (!arm_feature(env, ARM_FEATURE_NEON)) { | |
890 | /* ASEDIS [31] bit is RAO/WI */ | |
891 | value |= (1 << 31); | |
892 | } | |
893 | ||
894 | /* VFPv3 and upwards with NEON implement 32 double precision | |
895 | * registers (D0-D31). | |
896 | */ | |
897 | if (!arm_feature(env, ARM_FEATURE_NEON) || | |
898 | !arm_feature(env, ARM_FEATURE_VFP3)) { | |
899 | /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ | |
900 | value |= (1 << 30); | |
901 | } | |
902 | } | |
903 | value &= mask; | |
2771db27 | 904 | } |
7ebd5f2e | 905 | env->cp15.cpacr_el1 = value; |
2771db27 PM |
906 | } |
907 | ||
5deac39c PM |
908 | static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
909 | { | |
910 | /* Call cpacr_write() so that we reset with the correct RAO bits set | |
911 | * for our CPU features. | |
912 | */ | |
913 | cpacr_write(env, ri, 0); | |
914 | } | |
915 | ||
3f208fd7 PM |
916 | static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
917 | bool isread) | |
c6f19164 GB |
918 | { |
919 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
920 | /* Check if CPACR accesses are to be trapped to EL2 */ | |
921 | if (arm_current_el(env) == 1 && | |
922 | (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) { | |
923 | return CP_ACCESS_TRAP_EL2; | |
924 | /* Check if CPACR accesses are to be trapped to EL3 */ | |
925 | } else if (arm_current_el(env) < 3 && | |
926 | (env->cp15.cptr_el[3] & CPTR_TCPAC)) { | |
927 | return CP_ACCESS_TRAP_EL3; | |
928 | } | |
929 | } | |
930 | ||
931 | return CP_ACCESS_OK; | |
932 | } | |
933 | ||
3f208fd7 PM |
934 | static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
935 | bool isread) | |
c6f19164 GB |
936 | { |
937 | /* Check if CPTR accesses are set to trap to EL3 */ | |
938 | if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) { | |
939 | return CP_ACCESS_TRAP_EL3; | |
940 | } | |
941 | ||
942 | return CP_ACCESS_OK; | |
943 | } | |
944 | ||
7d57f408 PM |
945 | static const ARMCPRegInfo v6_cp_reginfo[] = { |
946 | /* prefetch by MVA in v6, NOP in v7 */ | |
947 | { .name = "MVA_prefetch", | |
948 | .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, | |
949 | .access = PL1_W, .type = ARM_CP_NOP }, | |
6df99dec SS |
950 | /* We need to break the TB after ISB to execute self-modifying code |
951 | * correctly and also to take any pending interrupts immediately. | |
952 | * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. | |
953 | */ | |
7d57f408 | 954 | { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, |
6df99dec | 955 | .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, |
091fd17c | 956 | { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
7d57f408 | 957 | .access = PL0_W, .type = ARM_CP_NOP }, |
091fd17c | 958 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
7d57f408 | 959 | .access = PL0_W, .type = ARM_CP_NOP }, |
06d76f31 | 960 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
6cd8a264 | 961 | .access = PL1_RW, |
b848ce2b FA |
962 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), |
963 | offsetof(CPUARMState, cp15.ifar_ns) }, | |
06d76f31 PM |
964 | .resetvalue = 0, }, |
965 | /* Watchpoint Fault Address Register : should actually only be present | |
966 | * for 1136, 1176, 11MPCore. | |
967 | */ | |
968 | { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
969 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, | |
34222fb8 | 970 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, |
c6f19164 | 971 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, |
7ebd5f2e | 972 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), |
5deac39c | 973 | .resetfn = cpacr_reset, .writefn = cpacr_write }, |
7d57f408 PM |
974 | REGINFO_SENTINEL |
975 | }; | |
976 | ||
7ece99b1 AL |
977 | /* Definitions for the PMU registers */ |
978 | #define PMCRN_MASK 0xf800 | |
979 | #define PMCRN_SHIFT 11 | |
033614c4 | 980 | #define PMCRDP 0x10 |
7ece99b1 AL |
981 | #define PMCRD 0x8 |
982 | #define PMCRC 0x4 | |
5ecdd3e4 | 983 | #define PMCRP 0x2 |
7ece99b1 AL |
984 | #define PMCRE 0x1 |
985 | ||
033614c4 AL |
986 | #define PMXEVTYPER_P 0x80000000 |
987 | #define PMXEVTYPER_U 0x40000000 | |
988 | #define PMXEVTYPER_NSK 0x20000000 | |
989 | #define PMXEVTYPER_NSU 0x10000000 | |
990 | #define PMXEVTYPER_NSH 0x08000000 | |
991 | #define PMXEVTYPER_M 0x04000000 | |
992 | #define PMXEVTYPER_MT 0x02000000 | |
993 | #define PMXEVTYPER_EVTCOUNT 0x0000ffff | |
994 | #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \ | |
995 | PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ | |
996 | PMXEVTYPER_M | PMXEVTYPER_MT | \ | |
997 | PMXEVTYPER_EVTCOUNT) | |
998 | ||
4b8afa1f AL |
999 | #define PMCCFILTR 0xf8000000 |
1000 | #define PMCCFILTR_M PMXEVTYPER_M | |
1001 | #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) | |
1002 | ||
7ece99b1 AL |
1003 | static inline uint32_t pmu_num_counters(CPUARMState *env) |
1004 | { | |
1005 | return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; | |
1006 | } | |
1007 | ||
1008 | /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ | |
1009 | static inline uint64_t pmu_counter_mask(CPUARMState *env) | |
1010 | { | |
1011 | return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); | |
1012 | } | |
1013 | ||
57a4a11b AL |
1014 | typedef struct pm_event { |
1015 | uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ | |
1016 | /* If the event is supported on this CPU (used to generate PMCEID[01]) */ | |
1017 | bool (*supported)(CPUARMState *); | |
1018 | /* | |
1019 | * Retrieve the current count of the underlying event. The programmed | |
1020 | * counters hold a difference from the return value from this function | |
1021 | */ | |
1022 | uint64_t (*get_count)(CPUARMState *); | |
1023 | } pm_event; | |
1024 | ||
b2e23725 AL |
1025 | static bool event_always_supported(CPUARMState *env) |
1026 | { | |
1027 | return true; | |
1028 | } | |
1029 | ||
0d4bfd7d AL |
1030 | static uint64_t swinc_get_count(CPUARMState *env) |
1031 | { | |
1032 | /* | |
1033 | * SW_INCR events are written directly to the pmevcntr's by writes to | |
1034 | * PMSWINC, so there is no underlying count maintained by the PMU itself | |
1035 | */ | |
1036 | return 0; | |
1037 | } | |
1038 | ||
b2e23725 AL |
1039 | /* |
1040 | * Return the underlying cycle count for the PMU cycle counters. If we're in | |
1041 | * usermode, simply return 0. | |
1042 | */ | |
1043 | static uint64_t cycles_get_count(CPUARMState *env) | |
1044 | { | |
1045 | #ifndef CONFIG_USER_ONLY | |
1046 | return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
1047 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); | |
1048 | #else | |
1049 | return cpu_get_host_ticks(); | |
1050 | #endif | |
1051 | } | |
1052 | ||
1053 | #ifndef CONFIG_USER_ONLY | |
1054 | static bool instructions_supported(CPUARMState *env) | |
1055 | { | |
1056 | return use_icount == 1 /* Precise instruction counting */; | |
1057 | } | |
1058 | ||
1059 | static uint64_t instructions_get_count(CPUARMState *env) | |
1060 | { | |
1061 | return (uint64_t)cpu_get_icount_raw(); | |
1062 | } | |
1063 | #endif | |
1064 | ||
57a4a11b | 1065 | static const pm_event pm_events[] = { |
0d4bfd7d AL |
1066 | { .number = 0x000, /* SW_INCR */ |
1067 | .supported = event_always_supported, | |
1068 | .get_count = swinc_get_count, | |
1069 | }, | |
b2e23725 AL |
1070 | #ifndef CONFIG_USER_ONLY |
1071 | { .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */ | |
1072 | .supported = instructions_supported, | |
1073 | .get_count = instructions_get_count, | |
1074 | }, | |
1075 | { .number = 0x011, /* CPU_CYCLES, Cycle */ | |
1076 | .supported = event_always_supported, | |
1077 | .get_count = cycles_get_count, | |
1078 | } | |
1079 | #endif | |
57a4a11b AL |
1080 | }; |
1081 | ||
1082 | /* | |
1083 | * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of | |
1084 | * events (i.e. the statistical profiling extension), this implementation | |
1085 | * should first be updated to something sparse instead of the current | |
1086 | * supported_event_map[] array. | |
1087 | */ | |
b2e23725 | 1088 | #define MAX_EVENT_ID 0x11 |
57a4a11b AL |
1089 | #define UNSUPPORTED_EVENT UINT16_MAX |
1090 | static uint16_t supported_event_map[MAX_EVENT_ID + 1]; | |
1091 | ||
1092 | /* | |
1093 | * Called upon initialization to build PMCEID0_EL0 or PMCEID1_EL0 (indicated by | |
1094 | * 'which'). We also use it to build a map of ARM event numbers to indices in | |
1095 | * our pm_events array. | |
1096 | * | |
1097 | * Note: Events in the 0x40XX range are not currently supported. | |
1098 | */ | |
1099 | uint64_t get_pmceid(CPUARMState *env, unsigned which) | |
1100 | { | |
1101 | uint64_t pmceid = 0; | |
1102 | unsigned int i; | |
1103 | ||
1104 | assert(which <= 1); | |
1105 | ||
1106 | for (i = 0; i < ARRAY_SIZE(supported_event_map); i++) { | |
1107 | supported_event_map[i] = UNSUPPORTED_EVENT; | |
1108 | } | |
1109 | ||
1110 | for (i = 0; i < ARRAY_SIZE(pm_events); i++) { | |
1111 | const pm_event *cnt = &pm_events[i]; | |
1112 | assert(cnt->number <= MAX_EVENT_ID); | |
1113 | /* We do not currently support events in the 0x40xx range */ | |
1114 | assert(cnt->number <= 0x3f); | |
1115 | ||
1116 | if ((cnt->number & 0x20) == (which << 6) && | |
1117 | cnt->supported(env)) { | |
1118 | pmceid |= (1 << (cnt->number & 0x1f)); | |
1119 | supported_event_map[cnt->number] = i; | |
1120 | } | |
1121 | } | |
1122 | return pmceid; | |
1123 | } | |
1124 | ||
5ecdd3e4 AL |
1125 | /* |
1126 | * Check at runtime whether a PMU event is supported for the current machine | |
1127 | */ | |
1128 | static bool event_supported(uint16_t number) | |
1129 | { | |
1130 | if (number > MAX_EVENT_ID) { | |
1131 | return false; | |
1132 | } | |
1133 | return supported_event_map[number] != UNSUPPORTED_EVENT; | |
1134 | } | |
1135 | ||
3f208fd7 PM |
1136 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1137 | bool isread) | |
200ac0ef | 1138 | { |
3b163b01 | 1139 | /* Performance monitor registers user accessibility is controlled |
1fce1ba9 PM |
1140 | * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable |
1141 | * trapping to EL2 or EL3 for other accesses. | |
200ac0ef | 1142 | */ |
1fce1ba9 PM |
1143 | int el = arm_current_el(env); |
1144 | ||
6ecd0b6b | 1145 | if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { |
fcd25206 | 1146 | return CP_ACCESS_TRAP; |
200ac0ef | 1147 | } |
1fce1ba9 PM |
1148 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) |
1149 | && !arm_is_secure_below_el3(env)) { | |
1150 | return CP_ACCESS_TRAP_EL2; | |
1151 | } | |
1152 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
1153 | return CP_ACCESS_TRAP_EL3; | |
1154 | } | |
1155 | ||
fcd25206 | 1156 | return CP_ACCESS_OK; |
200ac0ef PM |
1157 | } |
1158 | ||
6ecd0b6b AB |
1159 | static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, |
1160 | const ARMCPRegInfo *ri, | |
1161 | bool isread) | |
1162 | { | |
1163 | /* ER: event counter read trap control */ | |
1164 | if (arm_feature(env, ARM_FEATURE_V8) | |
1165 | && arm_current_el(env) == 0 | |
1166 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 | |
1167 | && isread) { | |
1168 | return CP_ACCESS_OK; | |
1169 | } | |
1170 | ||
1171 | return pmreg_access(env, ri, isread); | |
1172 | } | |
1173 | ||
1174 | static CPAccessResult pmreg_access_swinc(CPUARMState *env, | |
1175 | const ARMCPRegInfo *ri, | |
1176 | bool isread) | |
1177 | { | |
1178 | /* SW: software increment write trap control */ | |
1179 | if (arm_feature(env, ARM_FEATURE_V8) | |
1180 | && arm_current_el(env) == 0 | |
1181 | && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 | |
1182 | && !isread) { | |
1183 | return CP_ACCESS_OK; | |
1184 | } | |
1185 | ||
1186 | return pmreg_access(env, ri, isread); | |
1187 | } | |
1188 | ||
6ecd0b6b AB |
1189 | static CPAccessResult pmreg_access_selr(CPUARMState *env, |
1190 | const ARMCPRegInfo *ri, | |
1191 | bool isread) | |
1192 | { | |
1193 | /* ER: event counter read trap control */ | |
1194 | if (arm_feature(env, ARM_FEATURE_V8) | |
1195 | && arm_current_el(env) == 0 | |
1196 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { | |
1197 | return CP_ACCESS_OK; | |
1198 | } | |
1199 | ||
1200 | return pmreg_access(env, ri, isread); | |
1201 | } | |
1202 | ||
1203 | static CPAccessResult pmreg_access_ccntr(CPUARMState *env, | |
1204 | const ARMCPRegInfo *ri, | |
1205 | bool isread) | |
1206 | { | |
1207 | /* CR: cycle counter read trap control */ | |
1208 | if (arm_feature(env, ARM_FEATURE_V8) | |
1209 | && arm_current_el(env) == 0 | |
1210 | && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 | |
1211 | && isread) { | |
1212 | return CP_ACCESS_OK; | |
1213 | } | |
1214 | ||
1215 | return pmreg_access(env, ri, isread); | |
1216 | } | |
1217 | ||
033614c4 AL |
1218 | /* Returns true if the counter (pass 31 for PMCCNTR) should count events using |
1219 | * the current EL, security state, and register configuration. | |
1220 | */ | |
1221 | static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) | |
87124fde | 1222 | { |
033614c4 AL |
1223 | uint64_t filter; |
1224 | bool e, p, u, nsk, nsu, nsh, m; | |
1225 | bool enabled, prohibited, filtered; | |
1226 | bool secure = arm_is_secure(env); | |
1227 | int el = arm_current_el(env); | |
1228 | uint8_t hpmn = env->cp15.mdcr_el2 & MDCR_HPMN; | |
87124fde | 1229 | |
033614c4 AL |
1230 | if (!arm_feature(env, ARM_FEATURE_EL2) || |
1231 | (counter < hpmn || counter == 31)) { | |
1232 | e = env->cp15.c9_pmcr & PMCRE; | |
1233 | } else { | |
1234 | e = env->cp15.mdcr_el2 & MDCR_HPME; | |
87124fde | 1235 | } |
033614c4 | 1236 | enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); |
87124fde | 1237 | |
033614c4 AL |
1238 | if (!secure) { |
1239 | if (el == 2 && (counter < hpmn || counter == 31)) { | |
1240 | prohibited = env->cp15.mdcr_el2 & MDCR_HPMD; | |
1241 | } else { | |
1242 | prohibited = false; | |
1243 | } | |
1244 | } else { | |
1245 | prohibited = arm_feature(env, ARM_FEATURE_EL3) && | |
1246 | (env->cp15.mdcr_el3 & MDCR_SPME); | |
1247 | } | |
1248 | ||
1249 | if (prohibited && counter == 31) { | |
1250 | prohibited = env->cp15.c9_pmcr & PMCRDP; | |
1251 | } | |
1252 | ||
5ecdd3e4 AL |
1253 | if (counter == 31) { |
1254 | filter = env->cp15.pmccfiltr_el0; | |
1255 | } else { | |
1256 | filter = env->cp15.c14_pmevtyper[counter]; | |
1257 | } | |
033614c4 AL |
1258 | |
1259 | p = filter & PMXEVTYPER_P; | |
1260 | u = filter & PMXEVTYPER_U; | |
1261 | nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); | |
1262 | nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); | |
1263 | nsh = arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); | |
1264 | m = arm_el_is_aa64(env, 1) && | |
1265 | arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); | |
1266 | ||
1267 | if (el == 0) { | |
1268 | filtered = secure ? u : u != nsu; | |
1269 | } else if (el == 1) { | |
1270 | filtered = secure ? p : p != nsk; | |
1271 | } else if (el == 2) { | |
1272 | filtered = !nsh; | |
1273 | } else { /* EL3 */ | |
1274 | filtered = m != p; | |
1275 | } | |
1276 | ||
5ecdd3e4 AL |
1277 | if (counter != 31) { |
1278 | /* | |
1279 | * If not checking PMCCNTR, ensure the counter is setup to an event we | |
1280 | * support | |
1281 | */ | |
1282 | uint16_t event = filter & PMXEVTYPER_EVTCOUNT; | |
1283 | if (!event_supported(event)) { | |
1284 | return false; | |
1285 | } | |
1286 | } | |
1287 | ||
033614c4 | 1288 | return enabled && !prohibited && !filtered; |
87124fde | 1289 | } |
033614c4 | 1290 | |
5d05b9d4 AL |
1291 | /* |
1292 | * Ensure c15_ccnt is the guest-visible count so that operations such as | |
1293 | * enabling/disabling the counter or filtering, modifying the count itself, | |
1294 | * etc. can be done logically. This is essentially a no-op if the counter is | |
1295 | * not enabled at the time of the call. | |
1296 | */ | |
1297 | void pmccntr_op_start(CPUARMState *env) | |
ec7b4ce4 | 1298 | { |
b2e23725 | 1299 | uint64_t cycles = cycles_get_count(env); |
ec7b4ce4 | 1300 | |
033614c4 | 1301 | if (pmu_counter_enabled(env, 31)) { |
5d05b9d4 AL |
1302 | uint64_t eff_cycles = cycles; |
1303 | if (env->cp15.c9_pmcr & PMCRD) { | |
1304 | /* Increment once every 64 processor clock cycles */ | |
1305 | eff_cycles /= 64; | |
1306 | } | |
1307 | ||
1308 | env->cp15.c15_ccnt = eff_cycles - env->cp15.c15_ccnt_delta; | |
ec7b4ce4 | 1309 | } |
5d05b9d4 AL |
1310 | env->cp15.c15_ccnt_delta = cycles; |
1311 | } | |
ec7b4ce4 | 1312 | |
5d05b9d4 AL |
1313 | /* |
1314 | * If PMCCNTR is enabled, recalculate the delta between the clock and the | |
1315 | * guest-visible count. A call to pmccntr_op_finish should follow every call to | |
1316 | * pmccntr_op_start. | |
1317 | */ | |
1318 | void pmccntr_op_finish(CPUARMState *env) | |
1319 | { | |
033614c4 | 1320 | if (pmu_counter_enabled(env, 31)) { |
5d05b9d4 AL |
1321 | uint64_t prev_cycles = env->cp15.c15_ccnt_delta; |
1322 | ||
1323 | if (env->cp15.c9_pmcr & PMCRD) { | |
1324 | /* Increment once every 64 processor clock cycles */ | |
1325 | prev_cycles /= 64; | |
1326 | } | |
1327 | ||
1328 | env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt; | |
ec7b4ce4 AF |
1329 | } |
1330 | } | |
1331 | ||
5ecdd3e4 AL |
1332 | static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) |
1333 | { | |
1334 | ||
1335 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; | |
1336 | uint64_t count = 0; | |
1337 | if (event_supported(event)) { | |
1338 | uint16_t event_idx = supported_event_map[event]; | |
1339 | count = pm_events[event_idx].get_count(env); | |
1340 | } | |
1341 | ||
1342 | if (pmu_counter_enabled(env, counter)) { | |
1343 | env->cp15.c14_pmevcntr[counter] = | |
1344 | count - env->cp15.c14_pmevcntr_delta[counter]; | |
1345 | } | |
1346 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1347 | } | |
1348 | ||
1349 | static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) | |
1350 | { | |
1351 | if (pmu_counter_enabled(env, counter)) { | |
1352 | env->cp15.c14_pmevcntr_delta[counter] -= | |
1353 | env->cp15.c14_pmevcntr[counter]; | |
1354 | } | |
1355 | } | |
1356 | ||
5d05b9d4 AL |
1357 | void pmu_op_start(CPUARMState *env) |
1358 | { | |
5ecdd3e4 | 1359 | unsigned int i; |
5d05b9d4 | 1360 | pmccntr_op_start(env); |
5ecdd3e4 AL |
1361 | for (i = 0; i < pmu_num_counters(env); i++) { |
1362 | pmevcntr_op_start(env, i); | |
1363 | } | |
5d05b9d4 AL |
1364 | } |
1365 | ||
1366 | void pmu_op_finish(CPUARMState *env) | |
1367 | { | |
5ecdd3e4 | 1368 | unsigned int i; |
5d05b9d4 | 1369 | pmccntr_op_finish(env); |
5ecdd3e4 AL |
1370 | for (i = 0; i < pmu_num_counters(env); i++) { |
1371 | pmevcntr_op_finish(env, i); | |
1372 | } | |
5d05b9d4 AL |
1373 | } |
1374 | ||
033614c4 AL |
1375 | void pmu_pre_el_change(ARMCPU *cpu, void *ignored) |
1376 | { | |
1377 | pmu_op_start(&cpu->env); | |
1378 | } | |
1379 | ||
1380 | void pmu_post_el_change(ARMCPU *cpu, void *ignored) | |
1381 | { | |
1382 | pmu_op_finish(&cpu->env); | |
1383 | } | |
1384 | ||
c4241c7d PM |
1385 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1386 | uint64_t value) | |
200ac0ef | 1387 | { |
5d05b9d4 | 1388 | pmu_op_start(env); |
7c2cb42b AF |
1389 | |
1390 | if (value & PMCRC) { | |
1391 | /* The counter has been reset */ | |
1392 | env->cp15.c15_ccnt = 0; | |
1393 | } | |
1394 | ||
5ecdd3e4 AL |
1395 | if (value & PMCRP) { |
1396 | unsigned int i; | |
1397 | for (i = 0; i < pmu_num_counters(env); i++) { | |
1398 | env->cp15.c14_pmevcntr[i] = 0; | |
1399 | } | |
1400 | } | |
1401 | ||
200ac0ef PM |
1402 | /* only the DP, X, D and E bits are writable */ |
1403 | env->cp15.c9_pmcr &= ~0x39; | |
1404 | env->cp15.c9_pmcr |= (value & 0x39); | |
7c2cb42b | 1405 | |
5d05b9d4 | 1406 | pmu_op_finish(env); |
7c2cb42b AF |
1407 | } |
1408 | ||
0d4bfd7d AL |
1409 | static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1410 | uint64_t value) | |
1411 | { | |
1412 | unsigned int i; | |
1413 | for (i = 0; i < pmu_num_counters(env); i++) { | |
1414 | /* Increment a counter's count iff: */ | |
1415 | if ((value & (1 << i)) && /* counter's bit is set */ | |
1416 | /* counter is enabled and not filtered */ | |
1417 | pmu_counter_enabled(env, i) && | |
1418 | /* counter is SW_INCR */ | |
1419 | (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { | |
1420 | pmevcntr_op_start(env, i); | |
1421 | env->cp15.c14_pmevcntr[i]++; | |
1422 | pmevcntr_op_finish(env, i); | |
1423 | } | |
1424 | } | |
1425 | } | |
1426 | ||
7c2cb42b AF |
1427 | static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1428 | { | |
5d05b9d4 AL |
1429 | uint64_t ret; |
1430 | pmccntr_op_start(env); | |
1431 | ret = env->cp15.c15_ccnt; | |
1432 | pmccntr_op_finish(env); | |
1433 | return ret; | |
7c2cb42b AF |
1434 | } |
1435 | ||
6b040780 WH |
1436 | static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1437 | uint64_t value) | |
1438 | { | |
1439 | /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and | |
1440 | * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the | |
1441 | * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are | |
1442 | * accessed. | |
1443 | */ | |
1444 | env->cp15.c9_pmselr = value & 0x1f; | |
1445 | } | |
1446 | ||
7c2cb42b AF |
1447 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1448 | uint64_t value) | |
1449 | { | |
5d05b9d4 AL |
1450 | pmccntr_op_start(env); |
1451 | env->cp15.c15_ccnt = value; | |
1452 | pmccntr_op_finish(env); | |
200ac0ef | 1453 | } |
421c7ebd PC |
1454 | |
1455 | static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1456 | uint64_t value) | |
1457 | { | |
1458 | uint64_t cur_val = pmccntr_read(env, NULL); | |
1459 | ||
1460 | pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); | |
1461 | } | |
1462 | ||
0614601c AF |
1463 | static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1464 | uint64_t value) | |
1465 | { | |
5d05b9d4 | 1466 | pmccntr_op_start(env); |
4b8afa1f AL |
1467 | env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0; |
1468 | pmccntr_op_finish(env); | |
1469 | } | |
1470 | ||
1471 | static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1472 | uint64_t value) | |
1473 | { | |
1474 | pmccntr_op_start(env); | |
1475 | /* M is not accessible from AArch32 */ | |
1476 | env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | | |
1477 | (value & PMCCFILTR); | |
5d05b9d4 | 1478 | pmccntr_op_finish(env); |
0614601c AF |
1479 | } |
1480 | ||
4b8afa1f AL |
1481 | static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri) |
1482 | { | |
1483 | /* M is not visible in AArch32 */ | |
1484 | return env->cp15.pmccfiltr_el0 & PMCCFILTR; | |
1485 | } | |
1486 | ||
c4241c7d | 1487 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1488 | uint64_t value) |
1489 | { | |
7ece99b1 | 1490 | value &= pmu_counter_mask(env); |
200ac0ef | 1491 | env->cp15.c9_pmcnten |= value; |
200ac0ef PM |
1492 | } |
1493 | ||
c4241c7d PM |
1494 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1495 | uint64_t value) | |
200ac0ef | 1496 | { |
7ece99b1 | 1497 | value &= pmu_counter_mask(env); |
200ac0ef | 1498 | env->cp15.c9_pmcnten &= ~value; |
200ac0ef PM |
1499 | } |
1500 | ||
c4241c7d PM |
1501 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1502 | uint64_t value) | |
200ac0ef | 1503 | { |
599b71e2 | 1504 | value &= pmu_counter_mask(env); |
200ac0ef | 1505 | env->cp15.c9_pmovsr &= ~value; |
200ac0ef PM |
1506 | } |
1507 | ||
327dd510 AL |
1508 | static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1509 | uint64_t value) | |
1510 | { | |
1511 | value &= pmu_counter_mask(env); | |
1512 | env->cp15.c9_pmovsr |= value; | |
1513 | } | |
1514 | ||
5ecdd3e4 AL |
1515 | static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1516 | uint64_t value, const uint8_t counter) | |
200ac0ef | 1517 | { |
5ecdd3e4 AL |
1518 | if (counter == 31) { |
1519 | pmccfiltr_write(env, ri, value); | |
1520 | } else if (counter < pmu_num_counters(env)) { | |
1521 | pmevcntr_op_start(env, counter); | |
1522 | ||
1523 | /* | |
1524 | * If this counter's event type is changing, store the current | |
1525 | * underlying count for the new type in c14_pmevcntr_delta[counter] so | |
1526 | * pmevcntr_op_finish has the correct baseline when it converts back to | |
1527 | * a delta. | |
1528 | */ | |
1529 | uint16_t old_event = env->cp15.c14_pmevtyper[counter] & | |
1530 | PMXEVTYPER_EVTCOUNT; | |
1531 | uint16_t new_event = value & PMXEVTYPER_EVTCOUNT; | |
1532 | if (old_event != new_event) { | |
1533 | uint64_t count = 0; | |
1534 | if (event_supported(new_event)) { | |
1535 | uint16_t event_idx = supported_event_map[new_event]; | |
1536 | count = pm_events[event_idx].get_count(env); | |
1537 | } | |
1538 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1539 | } | |
1540 | ||
1541 | env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK; | |
1542 | pmevcntr_op_finish(env, counter); | |
1543 | } | |
fdb86656 WH |
1544 | /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when |
1545 | * PMSELR value is equal to or greater than the number of implemented | |
1546 | * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. | |
1547 | */ | |
5ecdd3e4 AL |
1548 | } |
1549 | ||
1550 | static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1551 | const uint8_t counter) | |
1552 | { | |
1553 | if (counter == 31) { | |
1554 | return env->cp15.pmccfiltr_el0; | |
1555 | } else if (counter < pmu_num_counters(env)) { | |
1556 | return env->cp15.c14_pmevtyper[counter]; | |
1557 | } else { | |
1558 | /* | |
1559 | * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER | |
1560 | * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). | |
1561 | */ | |
1562 | return 0; | |
1563 | } | |
1564 | } | |
1565 | ||
1566 | static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, | |
1567 | uint64_t value) | |
1568 | { | |
1569 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1570 | pmevtyper_write(env, ri, value, counter); | |
1571 | } | |
1572 | ||
1573 | static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1574 | uint64_t value) | |
1575 | { | |
1576 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1577 | env->cp15.c14_pmevtyper[counter] = value; | |
1578 | ||
1579 | /* | |
1580 | * pmevtyper_rawwrite is called between a pair of pmu_op_start and | |
1581 | * pmu_op_finish calls when loading saved state for a migration. Because | |
1582 | * we're potentially updating the type of event here, the value written to | |
1583 | * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a | |
1584 | * different counter type. Therefore, we need to set this value to the | |
1585 | * current count for the counter type we're writing so that pmu_op_finish | |
1586 | * has the correct count for its calculation. | |
1587 | */ | |
1588 | uint16_t event = value & PMXEVTYPER_EVTCOUNT; | |
1589 | if (event_supported(event)) { | |
1590 | uint16_t event_idx = supported_event_map[event]; | |
1591 | env->cp15.c14_pmevcntr_delta[counter] = | |
1592 | pm_events[event_idx].get_count(env); | |
fdb86656 WH |
1593 | } |
1594 | } | |
1595 | ||
5ecdd3e4 AL |
1596 | static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) |
1597 | { | |
1598 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1599 | return pmevtyper_read(env, ri, counter); | |
1600 | } | |
1601 | ||
1602 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1603 | uint64_t value) | |
1604 | { | |
1605 | pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1606 | } | |
1607 | ||
fdb86656 WH |
1608 | static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1609 | { | |
5ecdd3e4 AL |
1610 | return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); |
1611 | } | |
1612 | ||
1613 | static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1614 | uint64_t value, uint8_t counter) | |
1615 | { | |
1616 | if (counter < pmu_num_counters(env)) { | |
1617 | pmevcntr_op_start(env, counter); | |
1618 | env->cp15.c14_pmevcntr[counter] = value; | |
1619 | pmevcntr_op_finish(env, counter); | |
1620 | } | |
1621 | /* | |
1622 | * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR | |
1623 | * are CONSTRAINED UNPREDICTABLE. | |
fdb86656 | 1624 | */ |
5ecdd3e4 AL |
1625 | } |
1626 | ||
1627 | static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1628 | uint8_t counter) | |
1629 | { | |
1630 | if (counter < pmu_num_counters(env)) { | |
1631 | uint64_t ret; | |
1632 | pmevcntr_op_start(env, counter); | |
1633 | ret = env->cp15.c14_pmevcntr[counter]; | |
1634 | pmevcntr_op_finish(env, counter); | |
1635 | return ret; | |
fdb86656 | 1636 | } else { |
5ecdd3e4 AL |
1637 | /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR |
1638 | * are CONSTRAINED UNPREDICTABLE. */ | |
fdb86656 WH |
1639 | return 0; |
1640 | } | |
200ac0ef PM |
1641 | } |
1642 | ||
5ecdd3e4 AL |
1643 | static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, |
1644 | uint64_t value) | |
1645 | { | |
1646 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1647 | pmevcntr_write(env, ri, value, counter); | |
1648 | } | |
1649 | ||
1650 | static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) | |
1651 | { | |
1652 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1653 | return pmevcntr_read(env, ri, counter); | |
1654 | } | |
1655 | ||
1656 | static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1657 | uint64_t value) | |
1658 | { | |
1659 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1660 | assert(counter < pmu_num_counters(env)); | |
1661 | env->cp15.c14_pmevcntr[counter] = value; | |
1662 | pmevcntr_write(env, ri, value, counter); | |
1663 | } | |
1664 | ||
1665 | static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri) | |
1666 | { | |
1667 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1668 | assert(counter < pmu_num_counters(env)); | |
1669 | return env->cp15.c14_pmevcntr[counter]; | |
1670 | } | |
1671 | ||
1672 | static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1673 | uint64_t value) | |
1674 | { | |
1675 | pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1676 | } | |
1677 | ||
1678 | static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1679 | { | |
1680 | return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); | |
1681 | } | |
1682 | ||
c4241c7d | 1683 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1684 | uint64_t value) |
1685 | { | |
6ecd0b6b AB |
1686 | if (arm_feature(env, ARM_FEATURE_V8)) { |
1687 | env->cp15.c9_pmuserenr = value & 0xf; | |
1688 | } else { | |
1689 | env->cp15.c9_pmuserenr = value & 1; | |
1690 | } | |
200ac0ef PM |
1691 | } |
1692 | ||
c4241c7d PM |
1693 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1694 | uint64_t value) | |
200ac0ef PM |
1695 | { |
1696 | /* We have no event counters so only the C bit can be changed */ | |
7ece99b1 | 1697 | value &= pmu_counter_mask(env); |
200ac0ef | 1698 | env->cp15.c9_pminten |= value; |
200ac0ef PM |
1699 | } |
1700 | ||
c4241c7d PM |
1701 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1702 | uint64_t value) | |
200ac0ef | 1703 | { |
7ece99b1 | 1704 | value &= pmu_counter_mask(env); |
200ac0ef | 1705 | env->cp15.c9_pminten &= ~value; |
200ac0ef PM |
1706 | } |
1707 | ||
c4241c7d PM |
1708 | static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1709 | uint64_t value) | |
8641136c | 1710 | { |
a505d7fe PM |
1711 | /* Note that even though the AArch64 view of this register has bits |
1712 | * [10:0] all RES0 we can only mask the bottom 5, to comply with the | |
1713 | * architectural requirements for bits which are RES0 only in some | |
1714 | * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 | |
1715 | * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) | |
1716 | */ | |
855ea66d | 1717 | raw_write(env, ri, value & ~0x1FULL); |
8641136c NR |
1718 | } |
1719 | ||
64e0e2de EI |
1720 | static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
1721 | { | |
ea22747c RH |
1722 | /* Begin with base v8.0 state. */ |
1723 | uint32_t valid_mask = 0x3fff; | |
2d7137c1 | 1724 | ARMCPU *cpu = arm_env_get_cpu(env); |
ea22747c RH |
1725 | |
1726 | if (arm_el_is_aa64(env, 3)) { | |
1727 | value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ | |
1728 | valid_mask &= ~SCR_NET; | |
1729 | } else { | |
1730 | valid_mask &= ~(SCR_RW | SCR_ST); | |
1731 | } | |
64e0e2de EI |
1732 | |
1733 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | |
1734 | valid_mask &= ~SCR_HCE; | |
1735 | ||
1736 | /* On ARMv7, SMD (or SCD as it is called in v7) is only | |
1737 | * supported if EL2 exists. The bit is UNK/SBZP when | |
1738 | * EL2 is unavailable. In QEMU ARMv7, we force it to always zero | |
1739 | * when EL2 is unavailable. | |
4eb27640 | 1740 | * On ARMv8, this bit is always available. |
64e0e2de | 1741 | */ |
4eb27640 GB |
1742 | if (arm_feature(env, ARM_FEATURE_V7) && |
1743 | !arm_feature(env, ARM_FEATURE_V8)) { | |
64e0e2de EI |
1744 | valid_mask &= ~SCR_SMD; |
1745 | } | |
1746 | } | |
2d7137c1 RH |
1747 | if (cpu_isar_feature(aa64_lor, cpu)) { |
1748 | valid_mask |= SCR_TLOR; | |
1749 | } | |
64e0e2de EI |
1750 | |
1751 | /* Clear all-context RES0 bits. */ | |
1752 | value &= valid_mask; | |
1753 | raw_write(env, ri, value); | |
1754 | } | |
1755 | ||
c4241c7d | 1756 | static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
776d4e5c PM |
1757 | { |
1758 | ARMCPU *cpu = arm_env_get_cpu(env); | |
b85a1fd6 FA |
1759 | |
1760 | /* Acquire the CSSELR index from the bank corresponding to the CCSIDR | |
1761 | * bank | |
1762 | */ | |
1763 | uint32_t index = A32_BANKED_REG_GET(env, csselr, | |
1764 | ri->secure & ARM_CP_SECSTATE_S); | |
1765 | ||
1766 | return cpu->ccsidr[index]; | |
776d4e5c PM |
1767 | } |
1768 | ||
c4241c7d PM |
1769 | static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1770 | uint64_t value) | |
776d4e5c | 1771 | { |
8d5c773e | 1772 | raw_write(env, ri, value & 0xf); |
776d4e5c PM |
1773 | } |
1774 | ||
1090b9c6 PM |
1775 | static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1776 | { | |
1777 | CPUState *cs = ENV_GET_CPU(env); | |
f7778444 | 1778 | uint64_t hcr_el2 = arm_hcr_el2_eff(env); |
1090b9c6 PM |
1779 | uint64_t ret = 0; |
1780 | ||
f7778444 | 1781 | if (hcr_el2 & HCR_IMO) { |
636540e9 PM |
1782 | if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { |
1783 | ret |= CPSR_I; | |
1784 | } | |
1785 | } else { | |
1786 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { | |
1787 | ret |= CPSR_I; | |
1788 | } | |
1090b9c6 | 1789 | } |
636540e9 | 1790 | |
f7778444 | 1791 | if (hcr_el2 & HCR_FMO) { |
636540e9 PM |
1792 | if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { |
1793 | ret |= CPSR_F; | |
1794 | } | |
1795 | } else { | |
1796 | if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { | |
1797 | ret |= CPSR_F; | |
1798 | } | |
1090b9c6 | 1799 | } |
636540e9 | 1800 | |
1090b9c6 PM |
1801 | /* External aborts are not possible in QEMU so A bit is always clear */ |
1802 | return ret; | |
1803 | } | |
1804 | ||
e9aa6c21 | 1805 | static const ARMCPRegInfo v7_cp_reginfo[] = { |
7d57f408 PM |
1806 | /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ |
1807 | { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
1808 | .access = PL1_W, .type = ARM_CP_NOP }, | |
200ac0ef PM |
1809 | /* Performance monitors are implementation defined in v7, |
1810 | * but with an ARM recommended set of registers, which we | |
ac689a2e | 1811 | * follow. |
200ac0ef PM |
1812 | * |
1813 | * Performance registers fall into three categories: | |
1814 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) | |
1815 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) | |
1816 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) | |
1817 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW | |
1818 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. | |
1819 | */ | |
1820 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 1821 | .access = PL0_RW, .type = ARM_CP_ALIAS, |
8521466b | 1822 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), |
fcd25206 PM |
1823 | .writefn = pmcntenset_write, |
1824 | .accessfn = pmreg_access, | |
1825 | .raw_writefn = raw_write }, | |
8521466b AF |
1826 | { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, |
1827 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, | |
1828 | .access = PL0_RW, .accessfn = pmreg_access, | |
1829 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, | |
1830 | .writefn = pmcntenset_write, .raw_writefn = raw_write }, | |
200ac0ef | 1831 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
8521466b AF |
1832 | .access = PL0_RW, |
1833 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
1834 | .accessfn = pmreg_access, |
1835 | .writefn = pmcntenclr_write, | |
7a0e58fa | 1836 | .type = ARM_CP_ALIAS }, |
8521466b AF |
1837 | { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, |
1838 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, | |
1839 | .access = PL0_RW, .accessfn = pmreg_access, | |
7a0e58fa | 1840 | .type = ARM_CP_ALIAS, |
8521466b AF |
1841 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), |
1842 | .writefn = pmcntenclr_write }, | |
200ac0ef | 1843 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
e4e91a21 AL |
1844 | .access = PL0_RW, |
1845 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), | |
fcd25206 PM |
1846 | .accessfn = pmreg_access, |
1847 | .writefn = pmovsr_write, | |
1848 | .raw_writefn = raw_write }, | |
978364f1 AF |
1849 | { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, |
1850 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, | |
1851 | .access = PL0_RW, .accessfn = pmreg_access, | |
1852 | .type = ARM_CP_ALIAS, | |
1853 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), | |
1854 | .writefn = pmovsr_write, | |
1855 | .raw_writefn = raw_write }, | |
200ac0ef | 1856 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
0d4bfd7d AL |
1857 | .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NO_RAW, |
1858 | .writefn = pmswinc_write }, | |
1859 | { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64, | |
1860 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4, | |
1861 | .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NO_RAW, | |
1862 | .writefn = pmswinc_write }, | |
6b040780 WH |
1863 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, |
1864 | .access = PL0_RW, .type = ARM_CP_ALIAS, | |
1865 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), | |
6ecd0b6b | 1866 | .accessfn = pmreg_access_selr, .writefn = pmselr_write, |
6b040780 WH |
1867 | .raw_writefn = raw_write}, |
1868 | { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, | |
1869 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, | |
6ecd0b6b | 1870 | .access = PL0_RW, .accessfn = pmreg_access_selr, |
6b040780 WH |
1871 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), |
1872 | .writefn = pmselr_write, .raw_writefn = raw_write, }, | |
200ac0ef | 1873 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
169c8938 | 1874 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO, |
421c7ebd | 1875 | .readfn = pmccntr_read, .writefn = pmccntr_write32, |
6ecd0b6b | 1876 | .accessfn = pmreg_access_ccntr }, |
8521466b AF |
1877 | { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, |
1878 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, | |
6ecd0b6b | 1879 | .access = PL0_RW, .accessfn = pmreg_access_ccntr, |
8521466b | 1880 | .type = ARM_CP_IO, |
980ebe87 AL |
1881 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt), |
1882 | .readfn = pmccntr_read, .writefn = pmccntr_write, | |
1883 | .raw_readfn = raw_read, .raw_writefn = raw_write, }, | |
4b8afa1f AL |
1884 | { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7, |
1885 | .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32, | |
1886 | .access = PL0_RW, .accessfn = pmreg_access, | |
1887 | .type = ARM_CP_ALIAS | ARM_CP_IO, | |
1888 | .resetvalue = 0, }, | |
8521466b AF |
1889 | { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, |
1890 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, | |
980ebe87 | 1891 | .writefn = pmccfiltr_write, .raw_writefn = raw_write, |
8521466b AF |
1892 | .access = PL0_RW, .accessfn = pmreg_access, |
1893 | .type = ARM_CP_IO, | |
1894 | .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), | |
1895 | .resetvalue = 0, }, | |
200ac0ef | 1896 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
5ecdd3e4 AL |
1897 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
1898 | .accessfn = pmreg_access, | |
fdb86656 WH |
1899 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
1900 | { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, | |
1901 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, | |
5ecdd3e4 AL |
1902 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
1903 | .accessfn = pmreg_access, | |
fdb86656 | 1904 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
200ac0ef | 1905 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
5ecdd3e4 AL |
1906 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
1907 | .accessfn = pmreg_access_xevcntr, | |
1908 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, | |
1909 | { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64, | |
1910 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2, | |
1911 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
1912 | .accessfn = pmreg_access_xevcntr, | |
1913 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, | |
200ac0ef | 1914 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
1fce1ba9 | 1915 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, |
e4e91a21 | 1916 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr), |
200ac0ef | 1917 | .resetvalue = 0, |
d4e6df63 | 1918 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
8a83ffc2 AF |
1919 | { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, |
1920 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, | |
1fce1ba9 | 1921 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, |
8a83ffc2 AF |
1922 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), |
1923 | .resetvalue = 0, | |
1924 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, | |
200ac0ef | 1925 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
1fce1ba9 | 1926 | .access = PL1_RW, .accessfn = access_tpm, |
b7d793ad | 1927 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
e6ec5457 | 1928 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), |
200ac0ef | 1929 | .resetvalue = 0, |
d4e6df63 | 1930 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
e6ec5457 WH |
1931 | { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, |
1932 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, | |
1933 | .access = PL1_RW, .accessfn = access_tpm, | |
1934 | .type = ARM_CP_IO, | |
1935 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
1936 | .writefn = pmintenset_write, .raw_writefn = raw_write, | |
1937 | .resetvalue = 0x0 }, | |
200ac0ef | 1938 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
fc5f6856 AL |
1939 | .access = PL1_RW, .accessfn = access_tpm, |
1940 | .type = ARM_CP_ALIAS | ARM_CP_IO, | |
200ac0ef | 1941 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
b061a82b | 1942 | .writefn = pmintenclr_write, }, |
978364f1 AF |
1943 | { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, |
1944 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, | |
fc5f6856 AL |
1945 | .access = PL1_RW, .accessfn = access_tpm, |
1946 | .type = ARM_CP_ALIAS | ARM_CP_IO, | |
978364f1 AF |
1947 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
1948 | .writefn = pmintenclr_write }, | |
7da845b0 PM |
1949 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, |
1950 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | |
7a0e58fa | 1951 | .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, |
7da845b0 PM |
1952 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, |
1953 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | |
b85a1fd6 FA |
1954 | .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, |
1955 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), | |
1956 | offsetof(CPUARMState, cp15.csselr_ns) } }, | |
776d4e5c PM |
1957 | /* Auxiliary ID register: this actually has an IMPDEF value but for now |
1958 | * just RAZ for all cores: | |
1959 | */ | |
0ff644a7 PM |
1960 | { .name = "AIDR", .state = ARM_CP_STATE_BOTH, |
1961 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, | |
776d4e5c | 1962 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f32cdad5 PM |
1963 | /* Auxiliary fault status registers: these also are IMPDEF, and we |
1964 | * choose to RAZ/WI for all cores. | |
1965 | */ | |
1966 | { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, | |
1967 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, | |
1968 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
1969 | { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, | |
1970 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, | |
1971 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b0fe2427 PM |
1972 | /* MAIR can just read-as-written because we don't implement caches |
1973 | * and so don't need to care about memory attributes. | |
1974 | */ | |
1975 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | |
1976 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | |
be693c87 | 1977 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), |
b0fe2427 | 1978 | .resetvalue = 0 }, |
4cfb8ad8 PM |
1979 | { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, |
1980 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, | |
1981 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), | |
1982 | .resetvalue = 0 }, | |
b0fe2427 PM |
1983 | /* For non-long-descriptor page tables these are PRRR and NMRR; |
1984 | * regardless they still act as reads-as-written for QEMU. | |
b0fe2427 | 1985 | */ |
1281f8e3 | 1986 | /* MAIR0/1 are defined separately from their 64-bit counterpart which |
be693c87 GB |
1987 | * allows them to assign the correct fieldoffset based on the endianness |
1988 | * handled in the field definitions. | |
1989 | */ | |
a903c449 | 1990 | { .name = "MAIR0", .state = ARM_CP_STATE_AA32, |
b0fe2427 | 1991 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, |
be693c87 GB |
1992 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), |
1993 | offsetof(CPUARMState, cp15.mair0_ns) }, | |
b0fe2427 | 1994 | .resetfn = arm_cp_reset_ignore }, |
a903c449 | 1995 | { .name = "MAIR1", .state = ARM_CP_STATE_AA32, |
b0fe2427 | 1996 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, |
be693c87 GB |
1997 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), |
1998 | offsetof(CPUARMState, cp15.mair1_ns) }, | |
b0fe2427 | 1999 | .resetfn = arm_cp_reset_ignore }, |
1090b9c6 PM |
2000 | { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, |
2001 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, | |
7a0e58fa | 2002 | .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, |
995939a6 PM |
2003 | /* 32 bit ITLB invalidates */ |
2004 | { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, | |
7a0e58fa | 2005 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 2006 | { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, |
7a0e58fa | 2007 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 2008 | { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, |
7a0e58fa | 2009 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 PM |
2010 | /* 32 bit DTLB invalidates */ |
2011 | { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, | |
7a0e58fa | 2012 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 2013 | { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, |
7a0e58fa | 2014 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 2015 | { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, |
7a0e58fa | 2016 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 PM |
2017 | /* 32 bit TLB invalidates */ |
2018 | { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | |
7a0e58fa | 2019 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 2020 | { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
7a0e58fa | 2021 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 2022 | { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
7a0e58fa | 2023 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 | 2024 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
7a0e58fa | 2025 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, |
995939a6 PM |
2026 | REGINFO_SENTINEL |
2027 | }; | |
2028 | ||
2029 | static const ARMCPRegInfo v7mp_cp_reginfo[] = { | |
2030 | /* 32 bit TLB invalidates, Inner Shareable */ | |
2031 | { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | |
7a0e58fa | 2032 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write }, |
995939a6 | 2033 | { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
7a0e58fa | 2034 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, |
995939a6 | 2035 | { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
7a0e58fa | 2036 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 2037 | .writefn = tlbiasid_is_write }, |
995939a6 | 2038 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
7a0e58fa | 2039 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 2040 | .writefn = tlbimvaa_is_write }, |
e9aa6c21 PM |
2041 | REGINFO_SENTINEL |
2042 | }; | |
2043 | ||
327dd510 AL |
2044 | static const ARMCPRegInfo pmovsset_cp_reginfo[] = { |
2045 | /* PMOVSSET is not implemented in v7 before v7ve */ | |
2046 | { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3, | |
2047 | .access = PL0_RW, .accessfn = pmreg_access, | |
2048 | .type = ARM_CP_ALIAS, | |
2049 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), | |
2050 | .writefn = pmovsset_write, | |
2051 | .raw_writefn = raw_write }, | |
2052 | { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64, | |
2053 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3, | |
2054 | .access = PL0_RW, .accessfn = pmreg_access, | |
2055 | .type = ARM_CP_ALIAS, | |
2056 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), | |
2057 | .writefn = pmovsset_write, | |
2058 | .raw_writefn = raw_write }, | |
2059 | REGINFO_SENTINEL | |
2060 | }; | |
2061 | ||
c4241c7d PM |
2062 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2063 | uint64_t value) | |
c326b979 PM |
2064 | { |
2065 | value &= 1; | |
2066 | env->teecr = value; | |
c326b979 PM |
2067 | } |
2068 | ||
3f208fd7 PM |
2069 | static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2070 | bool isread) | |
c326b979 | 2071 | { |
dcbff19b | 2072 | if (arm_current_el(env) == 0 && (env->teecr & 1)) { |
92611c00 | 2073 | return CP_ACCESS_TRAP; |
c326b979 | 2074 | } |
92611c00 | 2075 | return CP_ACCESS_OK; |
c326b979 PM |
2076 | } |
2077 | ||
2078 | static const ARMCPRegInfo t2ee_cp_reginfo[] = { | |
2079 | { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, | |
2080 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), | |
2081 | .resetvalue = 0, | |
2082 | .writefn = teecr_write }, | |
2083 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, | |
2084 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | |
92611c00 | 2085 | .accessfn = teehbr_access, .resetvalue = 0 }, |
c326b979 PM |
2086 | REGINFO_SENTINEL |
2087 | }; | |
2088 | ||
4d31c596 | 2089 | static const ARMCPRegInfo v6k_cp_reginfo[] = { |
e4fe830b PM |
2090 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, |
2091 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | |
2092 | .access = PL0_RW, | |
54bf36ed | 2093 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, |
4d31c596 PM |
2094 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
2095 | .access = PL0_RW, | |
54bf36ed FA |
2096 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), |
2097 | offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, | |
e4fe830b PM |
2098 | .resetfn = arm_cp_reset_ignore }, |
2099 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | |
2100 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | |
2101 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
2102 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), |
2103 | .resetvalue = 0}, | |
4d31c596 PM |
2104 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
2105 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
2106 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), |
2107 | offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, | |
e4fe830b | 2108 | .resetfn = arm_cp_reset_ignore }, |
54bf36ed | 2109 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, |
e4fe830b | 2110 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, |
4d31c596 | 2111 | .access = PL1_RW, |
54bf36ed FA |
2112 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, |
2113 | { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, | |
2114 | .access = PL1_RW, | |
2115 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), | |
2116 | offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, | |
2117 | .resetvalue = 0 }, | |
4d31c596 PM |
2118 | REGINFO_SENTINEL |
2119 | }; | |
2120 | ||
55d284af PM |
2121 | #ifndef CONFIG_USER_ONLY |
2122 | ||
3f208fd7 PM |
2123 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2124 | bool isread) | |
00108f2d | 2125 | { |
75502672 PM |
2126 | /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. |
2127 | * Writable only at the highest implemented exception level. | |
2128 | */ | |
2129 | int el = arm_current_el(env); | |
2130 | ||
2131 | switch (el) { | |
2132 | case 0: | |
2133 | if (!extract32(env->cp15.c14_cntkctl, 0, 2)) { | |
2134 | return CP_ACCESS_TRAP; | |
2135 | } | |
2136 | break; | |
2137 | case 1: | |
2138 | if (!isread && ri->state == ARM_CP_STATE_AA32 && | |
2139 | arm_is_secure_below_el3(env)) { | |
2140 | /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ | |
2141 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2142 | } | |
2143 | break; | |
2144 | case 2: | |
2145 | case 3: | |
2146 | break; | |
00108f2d | 2147 | } |
75502672 PM |
2148 | |
2149 | if (!isread && el < arm_highest_el(env)) { | |
2150 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2151 | } | |
2152 | ||
00108f2d PM |
2153 | return CP_ACCESS_OK; |
2154 | } | |
2155 | ||
3f208fd7 PM |
2156 | static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, |
2157 | bool isread) | |
00108f2d | 2158 | { |
0b6440af EI |
2159 | unsigned int cur_el = arm_current_el(env); |
2160 | bool secure = arm_is_secure(env); | |
2161 | ||
00108f2d | 2162 | /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ |
0b6440af | 2163 | if (cur_el == 0 && |
00108f2d PM |
2164 | !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { |
2165 | return CP_ACCESS_TRAP; | |
2166 | } | |
0b6440af EI |
2167 | |
2168 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
2169 | timeridx == GTIMER_PHYS && !secure && cur_el < 2 && | |
2170 | !extract32(env->cp15.cnthctl_el2, 0, 1)) { | |
2171 | return CP_ACCESS_TRAP_EL2; | |
2172 | } | |
00108f2d PM |
2173 | return CP_ACCESS_OK; |
2174 | } | |
2175 | ||
3f208fd7 PM |
2176 | static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, |
2177 | bool isread) | |
00108f2d | 2178 | { |
0b6440af EI |
2179 | unsigned int cur_el = arm_current_el(env); |
2180 | bool secure = arm_is_secure(env); | |
2181 | ||
00108f2d PM |
2182 | /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if |
2183 | * EL0[PV]TEN is zero. | |
2184 | */ | |
0b6440af | 2185 | if (cur_el == 0 && |
00108f2d PM |
2186 | !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { |
2187 | return CP_ACCESS_TRAP; | |
2188 | } | |
0b6440af EI |
2189 | |
2190 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
2191 | timeridx == GTIMER_PHYS && !secure && cur_el < 2 && | |
2192 | !extract32(env->cp15.cnthctl_el2, 1, 1)) { | |
2193 | return CP_ACCESS_TRAP_EL2; | |
2194 | } | |
00108f2d PM |
2195 | return CP_ACCESS_OK; |
2196 | } | |
2197 | ||
2198 | static CPAccessResult gt_pct_access(CPUARMState *env, | |
3f208fd7 PM |
2199 | const ARMCPRegInfo *ri, |
2200 | bool isread) | |
00108f2d | 2201 | { |
3f208fd7 | 2202 | return gt_counter_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2203 | } |
2204 | ||
2205 | static CPAccessResult gt_vct_access(CPUARMState *env, | |
3f208fd7 PM |
2206 | const ARMCPRegInfo *ri, |
2207 | bool isread) | |
00108f2d | 2208 | { |
3f208fd7 | 2209 | return gt_counter_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2210 | } |
2211 | ||
3f208fd7 PM |
2212 | static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2213 | bool isread) | |
00108f2d | 2214 | { |
3f208fd7 | 2215 | return gt_timer_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2216 | } |
2217 | ||
3f208fd7 PM |
2218 | static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2219 | bool isread) | |
00108f2d | 2220 | { |
3f208fd7 | 2221 | return gt_timer_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2222 | } |
2223 | ||
b4d3978c | 2224 | static CPAccessResult gt_stimer_access(CPUARMState *env, |
3f208fd7 PM |
2225 | const ARMCPRegInfo *ri, |
2226 | bool isread) | |
b4d3978c PM |
2227 | { |
2228 | /* The AArch64 register view of the secure physical timer is | |
2229 | * always accessible from EL3, and configurably accessible from | |
2230 | * Secure EL1. | |
2231 | */ | |
2232 | switch (arm_current_el(env)) { | |
2233 | case 1: | |
2234 | if (!arm_is_secure(env)) { | |
2235 | return CP_ACCESS_TRAP; | |
2236 | } | |
2237 | if (!(env->cp15.scr_el3 & SCR_ST)) { | |
2238 | return CP_ACCESS_TRAP_EL3; | |
2239 | } | |
2240 | return CP_ACCESS_OK; | |
2241 | case 0: | |
2242 | case 2: | |
2243 | return CP_ACCESS_TRAP; | |
2244 | case 3: | |
2245 | return CP_ACCESS_OK; | |
2246 | default: | |
2247 | g_assert_not_reached(); | |
2248 | } | |
2249 | } | |
2250 | ||
55d284af PM |
2251 | static uint64_t gt_get_countervalue(CPUARMState *env) |
2252 | { | |
bc72ad67 | 2253 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; |
55d284af PM |
2254 | } |
2255 | ||
2256 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) | |
2257 | { | |
2258 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; | |
2259 | ||
2260 | if (gt->ctl & 1) { | |
2261 | /* Timer enabled: calculate and set current ISTATUS, irq, and | |
2262 | * reset timer to when ISTATUS next has to change | |
2263 | */ | |
edac4d8a EI |
2264 | uint64_t offset = timeridx == GTIMER_VIRT ? |
2265 | cpu->env.cp15.cntvoff_el2 : 0; | |
55d284af PM |
2266 | uint64_t count = gt_get_countervalue(&cpu->env); |
2267 | /* Note that this must be unsigned 64 bit arithmetic: */ | |
edac4d8a | 2268 | int istatus = count - offset >= gt->cval; |
55d284af | 2269 | uint64_t nexttick; |
194cbc49 | 2270 | int irqstate; |
55d284af PM |
2271 | |
2272 | gt->ctl = deposit32(gt->ctl, 2, 1, istatus); | |
194cbc49 PM |
2273 | |
2274 | irqstate = (istatus && !(gt->ctl & 2)); | |
2275 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
2276 | ||
55d284af PM |
2277 | if (istatus) { |
2278 | /* Next transition is when count rolls back over to zero */ | |
2279 | nexttick = UINT64_MAX; | |
2280 | } else { | |
2281 | /* Next transition is when we hit cval */ | |
edac4d8a | 2282 | nexttick = gt->cval + offset; |
55d284af PM |
2283 | } |
2284 | /* Note that the desired next expiry time might be beyond the | |
2285 | * signed-64-bit range of a QEMUTimer -- in this case we just | |
2286 | * set the timer for as far in the future as possible. When the | |
2287 | * timer expires we will reset the timer for any remaining period. | |
2288 | */ | |
2289 | if (nexttick > INT64_MAX / GTIMER_SCALE) { | |
2290 | nexttick = INT64_MAX / GTIMER_SCALE; | |
2291 | } | |
bc72ad67 | 2292 | timer_mod(cpu->gt_timer[timeridx], nexttick); |
194cbc49 | 2293 | trace_arm_gt_recalc(timeridx, irqstate, nexttick); |
55d284af PM |
2294 | } else { |
2295 | /* Timer disabled: ISTATUS and timer output always clear */ | |
2296 | gt->ctl &= ~4; | |
2297 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); | |
bc72ad67 | 2298 | timer_del(cpu->gt_timer[timeridx]); |
194cbc49 | 2299 | trace_arm_gt_recalc_disabled(timeridx); |
55d284af PM |
2300 | } |
2301 | } | |
2302 | ||
0e3eca4c EI |
2303 | static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, |
2304 | int timeridx) | |
55d284af PM |
2305 | { |
2306 | ARMCPU *cpu = arm_env_get_cpu(env); | |
55d284af | 2307 | |
bc72ad67 | 2308 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
2309 | } |
2310 | ||
c4241c7d | 2311 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
55d284af | 2312 | { |
c4241c7d | 2313 | return gt_get_countervalue(env); |
55d284af PM |
2314 | } |
2315 | ||
edac4d8a EI |
2316 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2317 | { | |
2318 | return gt_get_countervalue(env) - env->cp15.cntvoff_el2; | |
2319 | } | |
2320 | ||
c4241c7d | 2321 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2322 | int timeridx, |
c4241c7d | 2323 | uint64_t value) |
55d284af | 2324 | { |
194cbc49 | 2325 | trace_arm_gt_cval_write(timeridx, value); |
55d284af PM |
2326 | env->cp15.c14_timer[timeridx].cval = value; |
2327 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); | |
55d284af | 2328 | } |
c4241c7d | 2329 | |
0e3eca4c EI |
2330 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, |
2331 | int timeridx) | |
55d284af | 2332 | { |
edac4d8a | 2333 | uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; |
55d284af | 2334 | |
c4241c7d | 2335 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - |
edac4d8a | 2336 | (gt_get_countervalue(env) - offset)); |
55d284af PM |
2337 | } |
2338 | ||
c4241c7d | 2339 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2340 | int timeridx, |
c4241c7d | 2341 | uint64_t value) |
55d284af | 2342 | { |
edac4d8a | 2343 | uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; |
55d284af | 2344 | |
194cbc49 | 2345 | trace_arm_gt_tval_write(timeridx, value); |
edac4d8a | 2346 | env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + |
18084b2f | 2347 | sextract64(value, 0, 32); |
55d284af | 2348 | gt_recalc_timer(arm_env_get_cpu(env), timeridx); |
55d284af PM |
2349 | } |
2350 | ||
c4241c7d | 2351 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2352 | int timeridx, |
c4241c7d | 2353 | uint64_t value) |
55d284af PM |
2354 | { |
2355 | ARMCPU *cpu = arm_env_get_cpu(env); | |
55d284af PM |
2356 | uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; |
2357 | ||
194cbc49 | 2358 | trace_arm_gt_ctl_write(timeridx, value); |
d3afacc7 | 2359 | env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); |
55d284af PM |
2360 | if ((oldval ^ value) & 1) { |
2361 | /* Enable toggled */ | |
2362 | gt_recalc_timer(cpu, timeridx); | |
d3afacc7 | 2363 | } else if ((oldval ^ value) & 2) { |
55d284af PM |
2364 | /* IMASK toggled: don't need to recalculate, |
2365 | * just set the interrupt line based on ISTATUS | |
2366 | */ | |
194cbc49 PM |
2367 | int irqstate = (oldval & 4) && !(value & 2); |
2368 | ||
2369 | trace_arm_gt_imask_toggle(timeridx, irqstate); | |
2370 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
55d284af | 2371 | } |
55d284af PM |
2372 | } |
2373 | ||
0e3eca4c EI |
2374 | static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2375 | { | |
2376 | gt_timer_reset(env, ri, GTIMER_PHYS); | |
2377 | } | |
2378 | ||
2379 | static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2380 | uint64_t value) | |
2381 | { | |
2382 | gt_cval_write(env, ri, GTIMER_PHYS, value); | |
2383 | } | |
2384 | ||
2385 | static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2386 | { | |
2387 | return gt_tval_read(env, ri, GTIMER_PHYS); | |
2388 | } | |
2389 | ||
2390 | static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2391 | uint64_t value) | |
2392 | { | |
2393 | gt_tval_write(env, ri, GTIMER_PHYS, value); | |
2394 | } | |
2395 | ||
2396 | static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2397 | uint64_t value) | |
2398 | { | |
2399 | gt_ctl_write(env, ri, GTIMER_PHYS, value); | |
2400 | } | |
2401 | ||
2402 | static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) | |
2403 | { | |
2404 | gt_timer_reset(env, ri, GTIMER_VIRT); | |
2405 | } | |
2406 | ||
2407 | static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2408 | uint64_t value) | |
2409 | { | |
2410 | gt_cval_write(env, ri, GTIMER_VIRT, value); | |
2411 | } | |
2412 | ||
2413 | static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2414 | { | |
2415 | return gt_tval_read(env, ri, GTIMER_VIRT); | |
2416 | } | |
2417 | ||
2418 | static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2419 | uint64_t value) | |
2420 | { | |
2421 | gt_tval_write(env, ri, GTIMER_VIRT, value); | |
2422 | } | |
2423 | ||
2424 | static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2425 | uint64_t value) | |
2426 | { | |
2427 | gt_ctl_write(env, ri, GTIMER_VIRT, value); | |
2428 | } | |
2429 | ||
edac4d8a EI |
2430 | static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2431 | uint64_t value) | |
2432 | { | |
2433 | ARMCPU *cpu = arm_env_get_cpu(env); | |
2434 | ||
194cbc49 | 2435 | trace_arm_gt_cntvoff_write(value); |
edac4d8a EI |
2436 | raw_write(env, ri, value); |
2437 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
2438 | } | |
2439 | ||
b0e66d95 EI |
2440 | static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2441 | { | |
2442 | gt_timer_reset(env, ri, GTIMER_HYP); | |
2443 | } | |
2444 | ||
2445 | static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2446 | uint64_t value) | |
2447 | { | |
2448 | gt_cval_write(env, ri, GTIMER_HYP, value); | |
2449 | } | |
2450 | ||
2451 | static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2452 | { | |
2453 | return gt_tval_read(env, ri, GTIMER_HYP); | |
2454 | } | |
2455 | ||
2456 | static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2457 | uint64_t value) | |
2458 | { | |
2459 | gt_tval_write(env, ri, GTIMER_HYP, value); | |
2460 | } | |
2461 | ||
2462 | static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2463 | uint64_t value) | |
2464 | { | |
2465 | gt_ctl_write(env, ri, GTIMER_HYP, value); | |
2466 | } | |
2467 | ||
b4d3978c PM |
2468 | static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2469 | { | |
2470 | gt_timer_reset(env, ri, GTIMER_SEC); | |
2471 | } | |
2472 | ||
2473 | static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2474 | uint64_t value) | |
2475 | { | |
2476 | gt_cval_write(env, ri, GTIMER_SEC, value); | |
2477 | } | |
2478 | ||
2479 | static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2480 | { | |
2481 | return gt_tval_read(env, ri, GTIMER_SEC); | |
2482 | } | |
2483 | ||
2484 | static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2485 | uint64_t value) | |
2486 | { | |
2487 | gt_tval_write(env, ri, GTIMER_SEC, value); | |
2488 | } | |
2489 | ||
2490 | static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2491 | uint64_t value) | |
2492 | { | |
2493 | gt_ctl_write(env, ri, GTIMER_SEC, value); | |
2494 | } | |
2495 | ||
55d284af PM |
2496 | void arm_gt_ptimer_cb(void *opaque) |
2497 | { | |
2498 | ARMCPU *cpu = opaque; | |
2499 | ||
2500 | gt_recalc_timer(cpu, GTIMER_PHYS); | |
2501 | } | |
2502 | ||
2503 | void arm_gt_vtimer_cb(void *opaque) | |
2504 | { | |
2505 | ARMCPU *cpu = opaque; | |
2506 | ||
2507 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
2508 | } | |
2509 | ||
b0e66d95 EI |
2510 | void arm_gt_htimer_cb(void *opaque) |
2511 | { | |
2512 | ARMCPU *cpu = opaque; | |
2513 | ||
2514 | gt_recalc_timer(cpu, GTIMER_HYP); | |
2515 | } | |
2516 | ||
b4d3978c PM |
2517 | void arm_gt_stimer_cb(void *opaque) |
2518 | { | |
2519 | ARMCPU *cpu = opaque; | |
2520 | ||
2521 | gt_recalc_timer(cpu, GTIMER_SEC); | |
2522 | } | |
2523 | ||
55d284af PM |
2524 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
2525 | /* Note that CNTFRQ is purely reads-as-written for the benefit | |
2526 | * of software; writing it doesn't actually change the timer frequency. | |
2527 | * Our reset value matches the fixed frequency we implement the timer at. | |
2528 | */ | |
2529 | { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 2530 | .type = ARM_CP_ALIAS, |
a7adc4b7 PM |
2531 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, |
2532 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), | |
a7adc4b7 PM |
2533 | }, |
2534 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, | |
2535 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
2536 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
55d284af PM |
2537 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), |
2538 | .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE, | |
55d284af PM |
2539 | }, |
2540 | /* overall control: mostly access permissions */ | |
a7adc4b7 PM |
2541 | { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, |
2542 | .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, | |
55d284af PM |
2543 | .access = PL1_RW, |
2544 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), | |
2545 | .resetvalue = 0, | |
2546 | }, | |
2547 | /* per-timer control */ | |
2548 | { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
9ff9dd3c | 2549 | .secure = ARM_CP_SECSTATE_NS, |
7a0e58fa | 2550 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, |
a7adc4b7 PM |
2551 | .accessfn = gt_ptimer_access, |
2552 | .fieldoffset = offsetoflow32(CPUARMState, | |
2553 | cp15.c14_timer[GTIMER_PHYS].ctl), | |
0e3eca4c | 2554 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, |
a7adc4b7 | 2555 | }, |
9c513e78 | 2556 | { .name = "CNTP_CTL_S", |
9ff9dd3c PM |
2557 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, |
2558 | .secure = ARM_CP_SECSTATE_S, | |
2559 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, | |
2560 | .accessfn = gt_ptimer_access, | |
2561 | .fieldoffset = offsetoflow32(CPUARMState, | |
2562 | cp15.c14_timer[GTIMER_SEC].ctl), | |
2563 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
2564 | }, | |
a7adc4b7 PM |
2565 | { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, |
2566 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, | |
55d284af | 2567 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, |
a7adc4b7 | 2568 | .accessfn = gt_ptimer_access, |
55d284af PM |
2569 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), |
2570 | .resetvalue = 0, | |
0e3eca4c | 2571 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
2572 | }, |
2573 | { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 2574 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R, |
a7adc4b7 PM |
2575 | .accessfn = gt_vtimer_access, |
2576 | .fieldoffset = offsetoflow32(CPUARMState, | |
2577 | cp15.c14_timer[GTIMER_VIRT].ctl), | |
0e3eca4c | 2578 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, |
a7adc4b7 PM |
2579 | }, |
2580 | { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
2581 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, | |
55d284af | 2582 | .type = ARM_CP_IO, .access = PL1_RW | PL0_R, |
a7adc4b7 | 2583 | .accessfn = gt_vtimer_access, |
55d284af PM |
2584 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), |
2585 | .resetvalue = 0, | |
0e3eca4c | 2586 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
2587 | }, |
2588 | /* TimerValue views: a 32 bit downcounting view of the underlying state */ | |
2589 | { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
9ff9dd3c | 2590 | .secure = ARM_CP_SECSTATE_NS, |
7a0e58fa | 2591 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, |
00108f2d | 2592 | .accessfn = gt_ptimer_access, |
0e3eca4c | 2593 | .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, |
55d284af | 2594 | }, |
9c513e78 | 2595 | { .name = "CNTP_TVAL_S", |
9ff9dd3c PM |
2596 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, |
2597 | .secure = ARM_CP_SECSTATE_S, | |
2598 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, | |
2599 | .accessfn = gt_ptimer_access, | |
2600 | .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, | |
2601 | }, | |
a7adc4b7 PM |
2602 | { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
2603 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, | |
7a0e58fa | 2604 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, |
0e3eca4c EI |
2605 | .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, |
2606 | .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, | |
a7adc4b7 | 2607 | }, |
55d284af | 2608 | { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, |
7a0e58fa | 2609 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, |
00108f2d | 2610 | .accessfn = gt_vtimer_access, |
0e3eca4c | 2611 | .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, |
55d284af | 2612 | }, |
a7adc4b7 PM |
2613 | { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
2614 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, | |
7a0e58fa | 2615 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R, |
0e3eca4c EI |
2616 | .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, |
2617 | .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, | |
a7adc4b7 | 2618 | }, |
55d284af PM |
2619 | /* The counter itself */ |
2620 | { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, | |
7a0e58fa | 2621 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 2622 | .accessfn = gt_pct_access, |
a7adc4b7 PM |
2623 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
2624 | }, | |
2625 | { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, | |
2626 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, | |
7a0e58fa | 2627 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 2628 | .accessfn = gt_pct_access, .readfn = gt_cnt_read, |
55d284af PM |
2629 | }, |
2630 | { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, | |
7a0e58fa | 2631 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 2632 | .accessfn = gt_vct_access, |
edac4d8a | 2633 | .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, |
a7adc4b7 PM |
2634 | }, |
2635 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
2636 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
7a0e58fa | 2637 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 2638 | .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, |
55d284af PM |
2639 | }, |
2640 | /* Comparison value, indicating when the timer goes off */ | |
2641 | { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, | |
9ff9dd3c | 2642 | .secure = ARM_CP_SECSTATE_NS, |
55d284af | 2643 | .access = PL1_RW | PL0_R, |
7a0e58fa | 2644 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 2645 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), |
b061a82b | 2646 | .accessfn = gt_ptimer_access, |
0e3eca4c | 2647 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write, |
a7adc4b7 | 2648 | }, |
9c513e78 | 2649 | { .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2, |
9ff9dd3c PM |
2650 | .secure = ARM_CP_SECSTATE_S, |
2651 | .access = PL1_RW | PL0_R, | |
2652 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, | |
2653 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
2654 | .accessfn = gt_ptimer_access, | |
2655 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
2656 | }, | |
a7adc4b7 PM |
2657 | { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, |
2658 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, | |
2659 | .access = PL1_RW | PL0_R, | |
2660 | .type = ARM_CP_IO, | |
2661 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
12cde08a | 2662 | .resetvalue = 0, .accessfn = gt_ptimer_access, |
0e3eca4c | 2663 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write, |
55d284af PM |
2664 | }, |
2665 | { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, | |
2666 | .access = PL1_RW | PL0_R, | |
7a0e58fa | 2667 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 2668 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), |
b061a82b | 2669 | .accessfn = gt_vtimer_access, |
0e3eca4c | 2670 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write, |
a7adc4b7 PM |
2671 | }, |
2672 | { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
2673 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, | |
2674 | .access = PL1_RW | PL0_R, | |
2675 | .type = ARM_CP_IO, | |
2676 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
2677 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
0e3eca4c | 2678 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write, |
55d284af | 2679 | }, |
b4d3978c PM |
2680 | /* Secure timer -- this is actually restricted to only EL3 |
2681 | * and configurably Secure-EL1 via the accessfn. | |
2682 | */ | |
2683 | { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, | |
2684 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, | |
2685 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, | |
2686 | .accessfn = gt_stimer_access, | |
2687 | .readfn = gt_sec_tval_read, | |
2688 | .writefn = gt_sec_tval_write, | |
2689 | .resetfn = gt_sec_timer_reset, | |
2690 | }, | |
2691 | { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64, | |
2692 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1, | |
2693 | .type = ARM_CP_IO, .access = PL1_RW, | |
2694 | .accessfn = gt_stimer_access, | |
2695 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), | |
2696 | .resetvalue = 0, | |
2697 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
2698 | }, | |
2699 | { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, | |
2700 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, | |
2701 | .type = ARM_CP_IO, .access = PL1_RW, | |
2702 | .accessfn = gt_stimer_access, | |
2703 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
2704 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
2705 | }, | |
55d284af PM |
2706 | REGINFO_SENTINEL |
2707 | }; | |
2708 | ||
2709 | #else | |
26c4a83b AB |
2710 | |
2711 | /* In user-mode most of the generic timer registers are inaccessible | |
2712 | * however modern kernels (4.12+) allow access to cntvct_el0 | |
55d284af | 2713 | */ |
26c4a83b AB |
2714 | |
2715 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2716 | { | |
2717 | /* Currently we have no support for QEMUTimer in linux-user so we | |
2718 | * can't call gt_get_countervalue(env), instead we directly | |
2719 | * call the lower level functions. | |
2720 | */ | |
2721 | return cpu_get_clock() / GTIMER_SCALE; | |
2722 | } | |
2723 | ||
6cc7a3ae | 2724 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
26c4a83b AB |
2725 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, |
2726 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
2727 | .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */, | |
2728 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), | |
2729 | .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE, | |
2730 | }, | |
2731 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
2732 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
2733 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
2734 | .readfn = gt_virt_cnt_read, | |
2735 | }, | |
6cc7a3ae PM |
2736 | REGINFO_SENTINEL |
2737 | }; | |
2738 | ||
55d284af PM |
2739 | #endif |
2740 | ||
c4241c7d | 2741 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 2742 | { |
891a2fe7 | 2743 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8d5c773e | 2744 | raw_write(env, ri, value); |
891a2fe7 | 2745 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8d5c773e | 2746 | raw_write(env, ri, value & 0xfffff6ff); |
4a501606 | 2747 | } else { |
8d5c773e | 2748 | raw_write(env, ri, value & 0xfffff1ff); |
4a501606 | 2749 | } |
4a501606 PM |
2750 | } |
2751 | ||
2752 | #ifndef CONFIG_USER_ONLY | |
2753 | /* get_phys_addr() isn't present for user-mode-only targets */ | |
702a9357 | 2754 | |
3f208fd7 PM |
2755 | static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2756 | bool isread) | |
92611c00 PM |
2757 | { |
2758 | if (ri->opc2 & 4) { | |
87562e4f PM |
2759 | /* The ATS12NSO* operations must trap to EL3 if executed in |
2760 | * Secure EL1 (which can only happen if EL3 is AArch64). | |
2761 | * They are simply UNDEF if executed from NS EL1. | |
2762 | * They function normally from EL2 or EL3. | |
92611c00 | 2763 | */ |
87562e4f PM |
2764 | if (arm_current_el(env) == 1) { |
2765 | if (arm_is_secure_below_el3(env)) { | |
2766 | return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; | |
2767 | } | |
2768 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2769 | } | |
92611c00 PM |
2770 | } |
2771 | return CP_ACCESS_OK; | |
2772 | } | |
2773 | ||
060e8a48 | 2774 | static uint64_t do_ats_write(CPUARMState *env, uint64_t value, |
03ae85f8 | 2775 | MMUAccessType access_type, ARMMMUIdx mmu_idx) |
4a501606 | 2776 | { |
a8170e5e | 2777 | hwaddr phys_addr; |
4a501606 PM |
2778 | target_ulong page_size; |
2779 | int prot; | |
b7cc4e82 | 2780 | bool ret; |
01c097f7 | 2781 | uint64_t par64; |
1313e2d7 | 2782 | bool format64 = false; |
8bf5b6a9 | 2783 | MemTxAttrs attrs = {}; |
e14b5a23 | 2784 | ARMMMUFaultInfo fi = {}; |
5b2d261d | 2785 | ARMCacheAttrs cacheattrs = {}; |
4a501606 | 2786 | |
5b2d261d | 2787 | ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, |
bc52bfeb | 2788 | &prot, &page_size, &fi, &cacheattrs); |
1313e2d7 EI |
2789 | |
2790 | if (is_a64(env)) { | |
2791 | format64 = true; | |
2792 | } else if (arm_feature(env, ARM_FEATURE_LPAE)) { | |
2793 | /* | |
2794 | * ATS1Cxx: | |
2795 | * * TTBCR.EAE determines whether the result is returned using the | |
2796 | * 32-bit or the 64-bit PAR format | |
2797 | * * Instructions executed in Hyp mode always use the 64bit format | |
2798 | * | |
2799 | * ATS1S2NSOxx uses the 64bit format if any of the following is true: | |
2800 | * * The Non-secure TTBCR.EAE bit is set to 1 | |
2801 | * * The implementation includes EL2, and the value of HCR.VM is 1 | |
2802 | * | |
9d1bab33 PM |
2803 | * (Note that HCR.DC makes HCR.VM behave as if it is 1.) |
2804 | * | |
23463e0e | 2805 | * ATS1Hx always uses the 64bit format. |
1313e2d7 EI |
2806 | */ |
2807 | format64 = arm_s1_regime_using_lpae_format(env, mmu_idx); | |
2808 | ||
2809 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
2810 | if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { | |
9d1bab33 | 2811 | format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC); |
1313e2d7 EI |
2812 | } else { |
2813 | format64 |= arm_current_el(env) == 2; | |
2814 | } | |
2815 | } | |
2816 | } | |
2817 | ||
2818 | if (format64) { | |
5efe9ed4 | 2819 | /* Create a 64-bit PAR */ |
01c097f7 | 2820 | par64 = (1 << 11); /* LPAE bit always set */ |
b7cc4e82 | 2821 | if (!ret) { |
702a9357 | 2822 | par64 |= phys_addr & ~0xfffULL; |
8bf5b6a9 PM |
2823 | if (!attrs.secure) { |
2824 | par64 |= (1 << 9); /* NS */ | |
2825 | } | |
5b2d261d AB |
2826 | par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */ |
2827 | par64 |= cacheattrs.shareability << 7; /* SH */ | |
4a501606 | 2828 | } else { |
5efe9ed4 PM |
2829 | uint32_t fsr = arm_fi_to_lfsc(&fi); |
2830 | ||
702a9357 | 2831 | par64 |= 1; /* F */ |
b7cc4e82 | 2832 | par64 |= (fsr & 0x3f) << 1; /* FS */ |
0f7b791b PM |
2833 | if (fi.stage2) { |
2834 | par64 |= (1 << 9); /* S */ | |
2835 | } | |
2836 | if (fi.s1ptw) { | |
2837 | par64 |= (1 << 8); /* PTW */ | |
2838 | } | |
4a501606 PM |
2839 | } |
2840 | } else { | |
b7cc4e82 | 2841 | /* fsr is a DFSR/IFSR value for the short descriptor |
702a9357 PM |
2842 | * translation table format (with WnR always clear). |
2843 | * Convert it to a 32-bit PAR. | |
2844 | */ | |
b7cc4e82 | 2845 | if (!ret) { |
702a9357 PM |
2846 | /* We do not set any attribute bits in the PAR */ |
2847 | if (page_size == (1 << 24) | |
2848 | && arm_feature(env, ARM_FEATURE_V7)) { | |
01c097f7 | 2849 | par64 = (phys_addr & 0xff000000) | (1 << 1); |
702a9357 | 2850 | } else { |
01c097f7 | 2851 | par64 = phys_addr & 0xfffff000; |
702a9357 | 2852 | } |
8bf5b6a9 PM |
2853 | if (!attrs.secure) { |
2854 | par64 |= (1 << 9); /* NS */ | |
2855 | } | |
702a9357 | 2856 | } else { |
5efe9ed4 PM |
2857 | uint32_t fsr = arm_fi_to_sfsc(&fi); |
2858 | ||
b7cc4e82 PC |
2859 | par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | |
2860 | ((fsr & 0xf) << 1) | 1; | |
702a9357 | 2861 | } |
4a501606 | 2862 | } |
060e8a48 PM |
2863 | return par64; |
2864 | } | |
2865 | ||
2866 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | |
2867 | { | |
03ae85f8 | 2868 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
060e8a48 | 2869 | uint64_t par64; |
d3649702 PM |
2870 | ARMMMUIdx mmu_idx; |
2871 | int el = arm_current_el(env); | |
2872 | bool secure = arm_is_secure_below_el3(env); | |
060e8a48 | 2873 | |
d3649702 PM |
2874 | switch (ri->opc2 & 6) { |
2875 | case 0: | |
2876 | /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ | |
2877 | switch (el) { | |
2878 | case 3: | |
2879 | mmu_idx = ARMMMUIdx_S1E3; | |
2880 | break; | |
2881 | case 2: | |
2882 | mmu_idx = ARMMMUIdx_S1NSE1; | |
2883 | break; | |
2884 | case 1: | |
2885 | mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; | |
2886 | break; | |
2887 | default: | |
2888 | g_assert_not_reached(); | |
2889 | } | |
2890 | break; | |
2891 | case 2: | |
2892 | /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ | |
2893 | switch (el) { | |
2894 | case 3: | |
2895 | mmu_idx = ARMMMUIdx_S1SE0; | |
2896 | break; | |
2897 | case 2: | |
2898 | mmu_idx = ARMMMUIdx_S1NSE0; | |
2899 | break; | |
2900 | case 1: | |
2901 | mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; | |
2902 | break; | |
2903 | default: | |
2904 | g_assert_not_reached(); | |
2905 | } | |
2906 | break; | |
2907 | case 4: | |
2908 | /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ | |
2909 | mmu_idx = ARMMMUIdx_S12NSE1; | |
2910 | break; | |
2911 | case 6: | |
2912 | /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ | |
2913 | mmu_idx = ARMMMUIdx_S12NSE0; | |
2914 | break; | |
2915 | default: | |
2916 | g_assert_not_reached(); | |
2917 | } | |
2918 | ||
2919 | par64 = do_ats_write(env, value, access_type, mmu_idx); | |
01c097f7 FA |
2920 | |
2921 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
4a501606 | 2922 | } |
060e8a48 | 2923 | |
14db7fe0 PM |
2924 | static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2925 | uint64_t value) | |
2926 | { | |
03ae85f8 | 2927 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
14db7fe0 PM |
2928 | uint64_t par64; |
2929 | ||
23463e0e | 2930 | par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S1E2); |
14db7fe0 PM |
2931 | |
2932 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
2933 | } | |
2934 | ||
3f208fd7 PM |
2935 | static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2936 | bool isread) | |
2a47df95 PM |
2937 | { |
2938 | if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) { | |
2939 | return CP_ACCESS_TRAP; | |
2940 | } | |
2941 | return CP_ACCESS_OK; | |
2942 | } | |
2943 | ||
060e8a48 PM |
2944 | static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, |
2945 | uint64_t value) | |
2946 | { | |
03ae85f8 | 2947 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
d3649702 PM |
2948 | ARMMMUIdx mmu_idx; |
2949 | int secure = arm_is_secure_below_el3(env); | |
2950 | ||
2951 | switch (ri->opc2 & 6) { | |
2952 | case 0: | |
2953 | switch (ri->opc1) { | |
2954 | case 0: /* AT S1E1R, AT S1E1W */ | |
2955 | mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; | |
2956 | break; | |
2957 | case 4: /* AT S1E2R, AT S1E2W */ | |
2958 | mmu_idx = ARMMMUIdx_S1E2; | |
2959 | break; | |
2960 | case 6: /* AT S1E3R, AT S1E3W */ | |
2961 | mmu_idx = ARMMMUIdx_S1E3; | |
2962 | break; | |
2963 | default: | |
2964 | g_assert_not_reached(); | |
2965 | } | |
2966 | break; | |
2967 | case 2: /* AT S1E0R, AT S1E0W */ | |
2968 | mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; | |
2969 | break; | |
2970 | case 4: /* AT S12E1R, AT S12E1W */ | |
2a47df95 | 2971 | mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1; |
d3649702 PM |
2972 | break; |
2973 | case 6: /* AT S12E0R, AT S12E0W */ | |
2a47df95 | 2974 | mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0; |
d3649702 PM |
2975 | break; |
2976 | default: | |
2977 | g_assert_not_reached(); | |
2978 | } | |
060e8a48 | 2979 | |
d3649702 | 2980 | env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); |
060e8a48 | 2981 | } |
4a501606 PM |
2982 | #endif |
2983 | ||
2984 | static const ARMCPRegInfo vapa_cp_reginfo[] = { | |
2985 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, | |
2986 | .access = PL1_RW, .resetvalue = 0, | |
01c097f7 FA |
2987 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), |
2988 | offsetoflow32(CPUARMState, cp15.par_ns) }, | |
4a501606 PM |
2989 | .writefn = par_write }, |
2990 | #ifndef CONFIG_USER_ONLY | |
87562e4f | 2991 | /* This underdecoding is safe because the reginfo is NO_RAW. */ |
4a501606 | 2992 | { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, |
92611c00 | 2993 | .access = PL1_W, .accessfn = ats_access, |
7a0e58fa | 2994 | .writefn = ats_write, .type = ARM_CP_NO_RAW }, |
4a501606 PM |
2995 | #endif |
2996 | REGINFO_SENTINEL | |
2997 | }; | |
2998 | ||
18032bec PM |
2999 | /* Return basic MPU access permission bits. */ |
3000 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
3001 | { | |
3002 | uint32_t ret; | |
3003 | uint32_t mask; | |
3004 | int i; | |
3005 | ret = 0; | |
3006 | mask = 3; | |
3007 | for (i = 0; i < 16; i += 2) { | |
3008 | ret |= (val >> i) & mask; | |
3009 | mask <<= 2; | |
3010 | } | |
3011 | return ret; | |
3012 | } | |
3013 | ||
3014 | /* Pad basic MPU access permission bits to extended format. */ | |
3015 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
3016 | { | |
3017 | uint32_t ret; | |
3018 | uint32_t mask; | |
3019 | int i; | |
3020 | ret = 0; | |
3021 | mask = 3; | |
3022 | for (i = 0; i < 16; i += 2) { | |
3023 | ret |= (val & mask) << i; | |
3024 | mask <<= 2; | |
3025 | } | |
3026 | return ret; | |
3027 | } | |
3028 | ||
c4241c7d PM |
3029 | static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3030 | uint64_t value) | |
18032bec | 3031 | { |
7e09797c | 3032 | env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3033 | } |
3034 | ||
c4241c7d | 3035 | static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3036 | { |
7e09797c | 3037 | return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); |
18032bec PM |
3038 | } |
3039 | ||
c4241c7d PM |
3040 | static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3041 | uint64_t value) | |
18032bec | 3042 | { |
7e09797c | 3043 | env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3044 | } |
3045 | ||
c4241c7d | 3046 | static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3047 | { |
7e09797c | 3048 | return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); |
18032bec PM |
3049 | } |
3050 | ||
6cb0b013 PC |
3051 | static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) |
3052 | { | |
3053 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); | |
3054 | ||
3055 | if (!u32p) { | |
3056 | return 0; | |
3057 | } | |
3058 | ||
1bc04a88 | 3059 | u32p += env->pmsav7.rnr[M_REG_NS]; |
6cb0b013 PC |
3060 | return *u32p; |
3061 | } | |
3062 | ||
3063 | static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3064 | uint64_t value) | |
3065 | { | |
3066 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3067 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); | |
3068 | ||
3069 | if (!u32p) { | |
3070 | return; | |
3071 | } | |
3072 | ||
1bc04a88 | 3073 | u32p += env->pmsav7.rnr[M_REG_NS]; |
d10eb08f | 3074 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ |
6cb0b013 PC |
3075 | *u32p = value; |
3076 | } | |
3077 | ||
6cb0b013 PC |
3078 | static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3079 | uint64_t value) | |
3080 | { | |
3081 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3082 | uint32_t nrgs = cpu->pmsav7_dregion; | |
3083 | ||
3084 | if (value >= nrgs) { | |
3085 | qemu_log_mask(LOG_GUEST_ERROR, | |
3086 | "PMSAv7 RGNR write >= # supported regions, %" PRIu32 | |
3087 | " > %" PRIu32 "\n", (uint32_t)value, nrgs); | |
3088 | return; | |
3089 | } | |
3090 | ||
3091 | raw_write(env, ri, value); | |
3092 | } | |
3093 | ||
3094 | static const ARMCPRegInfo pmsav7_cp_reginfo[] = { | |
69ceea64 PM |
3095 | /* Reset for all these registers is handled in arm_cpu_reset(), |
3096 | * because the PMSAv7 is also used by M-profile CPUs, which do | |
3097 | * not register cpregs but still need the state to be reset. | |
3098 | */ | |
6cb0b013 PC |
3099 | { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, |
3100 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3101 | .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), | |
69ceea64 PM |
3102 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3103 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3104 | { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, |
3105 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3106 | .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), | |
69ceea64 PM |
3107 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3108 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3109 | { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, |
3110 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3111 | .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), | |
69ceea64 PM |
3112 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3113 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3114 | { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, |
3115 | .access = PL1_RW, | |
1bc04a88 | 3116 | .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), |
69ceea64 PM |
3117 | .writefn = pmsav7_rgnr_write, |
3118 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3119 | REGINFO_SENTINEL |
3120 | }; | |
3121 | ||
18032bec PM |
3122 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { |
3123 | { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 3124 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 3125 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
18032bec PM |
3126 | .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, |
3127 | { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 3128 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 3129 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
18032bec PM |
3130 | .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, |
3131 | { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, | |
3132 | .access = PL1_RW, | |
7e09797c PM |
3133 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
3134 | .resetvalue = 0, }, | |
18032bec PM |
3135 | { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, |
3136 | .access = PL1_RW, | |
7e09797c PM |
3137 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
3138 | .resetvalue = 0, }, | |
ecce5c3c PM |
3139 | { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
3140 | .access = PL1_RW, | |
3141 | .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, | |
3142 | { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
3143 | .access = PL1_RW, | |
3144 | .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, | |
06d76f31 | 3145 | /* Protection region base and size registers */ |
e508a92b PM |
3146 | { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, |
3147 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3148 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, | |
3149 | { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, | |
3150 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3151 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, | |
3152 | { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, | |
3153 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3154 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, | |
3155 | { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, | |
3156 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3157 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, | |
3158 | { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, | |
3159 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3160 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, | |
3161 | { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, | |
3162 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3163 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, | |
3164 | { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, | |
3165 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3166 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, | |
3167 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | |
3168 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3169 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | |
18032bec PM |
3170 | REGINFO_SENTINEL |
3171 | }; | |
3172 | ||
c4241c7d PM |
3173 | static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3174 | uint64_t value) | |
ecce5c3c | 3175 | { |
11f136ee | 3176 | TCR *tcr = raw_ptr(env, ri); |
2ebcebe2 PM |
3177 | int maskshift = extract32(value, 0, 3); |
3178 | ||
e389be16 FA |
3179 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
3180 | if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { | |
3181 | /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when | |
3182 | * using Long-desciptor translation table format */ | |
3183 | value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); | |
3184 | } else if (arm_feature(env, ARM_FEATURE_EL3)) { | |
3185 | /* In an implementation that includes the Security Extensions | |
3186 | * TTBCR has additional fields PD0 [4] and PD1 [5] for | |
3187 | * Short-descriptor translation table format. | |
3188 | */ | |
3189 | value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; | |
3190 | } else { | |
3191 | value &= TTBCR_N; | |
3192 | } | |
e42c4db3 | 3193 | } |
e389be16 | 3194 | |
b6af0975 | 3195 | /* Update the masks corresponding to the TCR bank being written |
11f136ee | 3196 | * Note that we always calculate mask and base_mask, but |
e42c4db3 | 3197 | * they are only used for short-descriptor tables (ie if EAE is 0); |
11f136ee FA |
3198 | * for long-descriptor tables the TCR fields are used differently |
3199 | * and the mask and base_mask values are meaningless. | |
e42c4db3 | 3200 | */ |
11f136ee FA |
3201 | tcr->raw_tcr = value; |
3202 | tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift); | |
3203 | tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift); | |
ecce5c3c PM |
3204 | } |
3205 | ||
c4241c7d PM |
3206 | static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3207 | uint64_t value) | |
d4e6df63 | 3208 | { |
00c8cb0a | 3209 | ARMCPU *cpu = arm_env_get_cpu(env); |
ab638a32 | 3210 | TCR *tcr = raw_ptr(env, ri); |
00c8cb0a | 3211 | |
d4e6df63 PM |
3212 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
3213 | /* With LPAE the TTBCR could result in a change of ASID | |
3214 | * via the TTBCR.A1 bit, so do a TLB flush. | |
3215 | */ | |
d10eb08f | 3216 | tlb_flush(CPU(cpu)); |
d4e6df63 | 3217 | } |
ab638a32 RH |
3218 | /* Preserve the high half of TCR_EL1, set via TTBCR2. */ |
3219 | value = deposit64(tcr->raw_tcr, 0, 32, value); | |
c4241c7d | 3220 | vmsa_ttbcr_raw_write(env, ri, value); |
d4e6df63 PM |
3221 | } |
3222 | ||
ecce5c3c PM |
3223 | static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
3224 | { | |
11f136ee FA |
3225 | TCR *tcr = raw_ptr(env, ri); |
3226 | ||
3227 | /* Reset both the TCR as well as the masks corresponding to the bank of | |
3228 | * the TCR being reset. | |
3229 | */ | |
3230 | tcr->raw_tcr = 0; | |
3231 | tcr->mask = 0; | |
3232 | tcr->base_mask = 0xffffc000u; | |
ecce5c3c PM |
3233 | } |
3234 | ||
cb2e37df PM |
3235 | static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3236 | uint64_t value) | |
3237 | { | |
00c8cb0a | 3238 | ARMCPU *cpu = arm_env_get_cpu(env); |
11f136ee | 3239 | TCR *tcr = raw_ptr(env, ri); |
00c8cb0a | 3240 | |
cb2e37df | 3241 | /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ |
d10eb08f | 3242 | tlb_flush(CPU(cpu)); |
11f136ee | 3243 | tcr->raw_tcr = value; |
cb2e37df PM |
3244 | } |
3245 | ||
327ed10f PM |
3246 | static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3247 | uint64_t value) | |
3248 | { | |
93f379b0 RH |
3249 | /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ |
3250 | if (cpreg_field_is_64bit(ri) && | |
3251 | extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { | |
00c8cb0a | 3252 | ARMCPU *cpu = arm_env_get_cpu(env); |
d10eb08f | 3253 | tlb_flush(CPU(cpu)); |
327ed10f PM |
3254 | } |
3255 | raw_write(env, ri, value); | |
3256 | } | |
3257 | ||
b698e9cf EI |
3258 | static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3259 | uint64_t value) | |
3260 | { | |
3261 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3262 | CPUState *cs = CPU(cpu); | |
3263 | ||
3264 | /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ | |
3265 | if (raw_read(env, ri) != value) { | |
0336cbf8 | 3266 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
3267 | ARMMMUIdxBit_S12NSE1 | |
3268 | ARMMMUIdxBit_S12NSE0 | | |
3269 | ARMMMUIdxBit_S2NS); | |
b698e9cf EI |
3270 | raw_write(env, ri, value); |
3271 | } | |
3272 | } | |
3273 | ||
8e5d75c9 | 3274 | static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { |
18032bec | 3275 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, |
7a0e58fa | 3276 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
4a7e2d73 | 3277 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), |
b061a82b | 3278 | offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, |
18032bec | 3279 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, |
88ca1c2d FA |
3280 | .access = PL1_RW, .resetvalue = 0, |
3281 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), | |
3282 | offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, | |
8e5d75c9 PC |
3283 | { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, |
3284 | .access = PL1_RW, .resetvalue = 0, | |
3285 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), | |
3286 | offsetof(CPUARMState, cp15.dfar_ns) } }, | |
3287 | { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, | |
3288 | .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, | |
3289 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), | |
3290 | .resetvalue = 0, }, | |
3291 | REGINFO_SENTINEL | |
3292 | }; | |
3293 | ||
3294 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { | |
6cd8a264 RH |
3295 | { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, |
3296 | .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, | |
3297 | .access = PL1_RW, | |
d81c519c | 3298 | .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, |
327ed10f | 3299 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af FA |
3300 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, |
3301 | .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
3302 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), | |
3303 | offsetof(CPUARMState, cp15.ttbr0_ns) } }, | |
327ed10f | 3304 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af FA |
3305 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, |
3306 | .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
3307 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), | |
3308 | offsetof(CPUARMState, cp15.ttbr1_ns) } }, | |
cb2e37df PM |
3309 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, |
3310 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | |
3311 | .access = PL1_RW, .writefn = vmsa_tcr_el1_write, | |
3312 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, | |
11f136ee | 3313 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, |
cb2e37df | 3314 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
7a0e58fa | 3315 | .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, |
b061a82b | 3316 | .raw_writefn = vmsa_ttbcr_raw_write, |
11f136ee FA |
3317 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), |
3318 | offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, | |
18032bec PM |
3319 | REGINFO_SENTINEL |
3320 | }; | |
3321 | ||
ab638a32 RH |
3322 | /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing |
3323 | * qemu tlbs nor adjusting cached masks. | |
3324 | */ | |
3325 | static const ARMCPRegInfo ttbcr2_reginfo = { | |
3326 | .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3, | |
3327 | .access = PL1_RW, .type = ARM_CP_ALIAS, | |
3328 | .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), | |
3329 | offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, | |
3330 | }; | |
3331 | ||
c4241c7d PM |
3332 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3333 | uint64_t value) | |
1047b9d7 PM |
3334 | { |
3335 | env->cp15.c15_ticonfig = value & 0xe7; | |
3336 | /* The OS_TYPE bit in this register changes the reported CPUID! */ | |
3337 | env->cp15.c0_cpuid = (value & (1 << 5)) ? | |
3338 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1047b9d7 PM |
3339 | } |
3340 | ||
c4241c7d PM |
3341 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3342 | uint64_t value) | |
1047b9d7 PM |
3343 | { |
3344 | env->cp15.c15_threadid = value & 0xffff; | |
1047b9d7 PM |
3345 | } |
3346 | ||
c4241c7d PM |
3347 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3348 | uint64_t value) | |
1047b9d7 PM |
3349 | { |
3350 | /* Wait-for-interrupt (deprecated) */ | |
c3affe56 | 3351 | cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); |
1047b9d7 PM |
3352 | } |
3353 | ||
c4241c7d PM |
3354 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3355 | uint64_t value) | |
c4804214 PM |
3356 | { |
3357 | /* On OMAP there are registers indicating the max/min index of dcache lines | |
3358 | * containing a dirty line; cache flush operations have to reset these. | |
3359 | */ | |
3360 | env->cp15.c15_i_max = 0x000; | |
3361 | env->cp15.c15_i_min = 0xff0; | |
c4804214 PM |
3362 | } |
3363 | ||
18032bec PM |
3364 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
3365 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, | |
3366 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, | |
d81c519c | 3367 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 3368 | .resetvalue = 0, }, |
1047b9d7 PM |
3369 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
3370 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
3371 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
3372 | .access = PL1_RW, | |
3373 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, | |
3374 | .writefn = omap_ticonfig_write }, | |
3375 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, | |
3376 | .access = PL1_RW, | |
3377 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, | |
3378 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, | |
3379 | .access = PL1_RW, .resetvalue = 0xff0, | |
3380 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, | |
3381 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, | |
3382 | .access = PL1_RW, | |
3383 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, | |
3384 | .writefn = omap_threadid_write }, | |
3385 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, | |
3386 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
7a0e58fa | 3387 | .type = ARM_CP_NO_RAW, |
1047b9d7 PM |
3388 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
3389 | /* TODO: Peripheral port remap register: | |
3390 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller | |
3391 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), | |
3392 | * when MMU is off. | |
3393 | */ | |
c4804214 | 3394 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
d4e6df63 | 3395 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
7a0e58fa | 3396 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, |
c4804214 | 3397 | .writefn = omap_cachemaint_write }, |
34f90529 PM |
3398 | { .name = "C9", .cp = 15, .crn = 9, |
3399 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | |
3400 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | |
1047b9d7 PM |
3401 | REGINFO_SENTINEL |
3402 | }; | |
3403 | ||
c4241c7d PM |
3404 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3405 | uint64_t value) | |
1047b9d7 | 3406 | { |
c0f4af17 | 3407 | env->cp15.c15_cpar = value & 0x3fff; |
1047b9d7 PM |
3408 | } |
3409 | ||
3410 | static const ARMCPRegInfo xscale_cp_reginfo[] = { | |
3411 | { .name = "XSCALE_CPAR", | |
3412 | .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
3413 | .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, | |
3414 | .writefn = xscale_cpar_write, }, | |
2771db27 PM |
3415 | { .name = "XSCALE_AUXCR", |
3416 | .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, | |
3417 | .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), | |
3418 | .resetvalue = 0, }, | |
3b771579 PM |
3419 | /* XScale specific cache-lockdown: since we have no cache we NOP these |
3420 | * and hope the guest does not really rely on cache behaviour. | |
3421 | */ | |
3422 | { .name = "XSCALE_LOCK_ICACHE_LINE", | |
3423 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
3424 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3425 | { .name = "XSCALE_UNLOCK_ICACHE", | |
3426 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
3427 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3428 | { .name = "XSCALE_DCACHE_LOCK", | |
3429 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, | |
3430 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
3431 | { .name = "XSCALE_UNLOCK_DCACHE", | |
3432 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, | |
3433 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1047b9d7 PM |
3434 | REGINFO_SENTINEL |
3435 | }; | |
3436 | ||
3437 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | |
3438 | /* RAZ/WI the whole crn=15 space, when we don't have a more specific | |
3439 | * implementation of this implementation-defined space. | |
3440 | * Ideally this should eventually disappear in favour of actually | |
3441 | * implementing the correct behaviour for all cores. | |
3442 | */ | |
3443 | { .name = "C15_IMPDEF", .cp = 15, .crn = 15, | |
3444 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
3671cd87 | 3445 | .access = PL1_RW, |
7a0e58fa | 3446 | .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, |
d4e6df63 | 3447 | .resetvalue = 0 }, |
18032bec PM |
3448 | REGINFO_SENTINEL |
3449 | }; | |
3450 | ||
c4804214 PM |
3451 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
3452 | /* Cache status: RAZ because we have no cache so it's always clean */ | |
3453 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | |
7a0e58fa | 3454 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 3455 | .resetvalue = 0 }, |
c4804214 PM |
3456 | REGINFO_SENTINEL |
3457 | }; | |
3458 | ||
3459 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | |
3460 | /* We never have a a block transfer operation in progress */ | |
3461 | { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, | |
7a0e58fa | 3462 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 3463 | .resetvalue = 0 }, |
30b05bba PM |
3464 | /* The cache ops themselves: these all NOP for QEMU */ |
3465 | { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, | |
3466 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3467 | { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, | |
3468 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3469 | { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, | |
3470 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3471 | { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, | |
3472 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3473 | { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, | |
3474 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3475 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, | |
3476 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
c4804214 PM |
3477 | REGINFO_SENTINEL |
3478 | }; | |
3479 | ||
3480 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | |
3481 | /* The cache test-and-clean instructions always return (1 << 30) | |
3482 | * to indicate that there are no dirty cache lines. | |
3483 | */ | |
3484 | { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, | |
7a0e58fa | 3485 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 3486 | .resetvalue = (1 << 30) }, |
c4804214 | 3487 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
7a0e58fa | 3488 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 3489 | .resetvalue = (1 << 30) }, |
c4804214 PM |
3490 | REGINFO_SENTINEL |
3491 | }; | |
3492 | ||
34f90529 PM |
3493 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
3494 | /* Ignore ReadBuffer accesses */ | |
3495 | { .name = "C9_READBUFFER", .cp = 15, .crn = 9, | |
3496 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
d4e6df63 | 3497 | .access = PL1_RW, .resetvalue = 0, |
7a0e58fa | 3498 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, |
34f90529 PM |
3499 | REGINFO_SENTINEL |
3500 | }; | |
3501 | ||
731de9e6 EI |
3502 | static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
3503 | { | |
3504 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3505 | unsigned int cur_el = arm_current_el(env); | |
3506 | bool secure = arm_is_secure(env); | |
3507 | ||
3508 | if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { | |
3509 | return env->cp15.vpidr_el2; | |
3510 | } | |
3511 | return raw_read(env, ri); | |
3512 | } | |
3513 | ||
06a7e647 | 3514 | static uint64_t mpidr_read_val(CPUARMState *env) |
81bdde9d | 3515 | { |
eb5e1d3c PF |
3516 | ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env)); |
3517 | uint64_t mpidr = cpu->mp_affinity; | |
3518 | ||
81bdde9d | 3519 | if (arm_feature(env, ARM_FEATURE_V7MP)) { |
78dbbbe4 | 3520 | mpidr |= (1U << 31); |
81bdde9d PM |
3521 | /* Cores which are uniprocessor (non-coherent) |
3522 | * but still implement the MP extensions set | |
a8e81b31 | 3523 | * bit 30. (For instance, Cortex-R5). |
81bdde9d | 3524 | */ |
a8e81b31 PC |
3525 | if (cpu->mp_is_up) { |
3526 | mpidr |= (1u << 30); | |
3527 | } | |
81bdde9d | 3528 | } |
c4241c7d | 3529 | return mpidr; |
81bdde9d PM |
3530 | } |
3531 | ||
06a7e647 EI |
3532 | static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
3533 | { | |
f0d574d6 EI |
3534 | unsigned int cur_el = arm_current_el(env); |
3535 | bool secure = arm_is_secure(env); | |
3536 | ||
3537 | if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { | |
3538 | return env->cp15.vmpidr_el2; | |
3539 | } | |
06a7e647 EI |
3540 | return mpidr_read_val(env); |
3541 | } | |
3542 | ||
81bdde9d | 3543 | static const ARMCPRegInfo mpidr_cp_reginfo[] = { |
4b7fff2f PM |
3544 | { .name = "MPIDR", .state = ARM_CP_STATE_BOTH, |
3545 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | |
7a0e58fa | 3546 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, |
81bdde9d PM |
3547 | REGINFO_SENTINEL |
3548 | }; | |
3549 | ||
7ac681cf | 3550 | static const ARMCPRegInfo lpae_cp_reginfo[] = { |
a903c449 | 3551 | /* NOP AMAIR0/1 */ |
b0fe2427 PM |
3552 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, |
3553 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | |
a903c449 | 3554 | .access = PL1_RW, .type = ARM_CP_CONST, |
7ac681cf | 3555 | .resetvalue = 0 }, |
b0fe2427 | 3556 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ |
7ac681cf | 3557 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
a903c449 | 3558 | .access = PL1_RW, .type = ARM_CP_CONST, |
7ac681cf | 3559 | .resetvalue = 0 }, |
891a2fe7 | 3560 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
01c097f7 FA |
3561 | .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, |
3562 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), | |
3563 | offsetof(CPUARMState, cp15.par_ns)} }, | |
891a2fe7 | 3564 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, |
7a0e58fa | 3565 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, |
7dd8c9af FA |
3566 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
3567 | offsetof(CPUARMState, cp15.ttbr0_ns) }, | |
b061a82b | 3568 | .writefn = vmsa_ttbr_write, }, |
891a2fe7 | 3569 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
7a0e58fa | 3570 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, |
7dd8c9af FA |
3571 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
3572 | offsetof(CPUARMState, cp15.ttbr1_ns) }, | |
b061a82b | 3573 | .writefn = vmsa_ttbr_write, }, |
7ac681cf PM |
3574 | REGINFO_SENTINEL |
3575 | }; | |
3576 | ||
c4241c7d | 3577 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 3578 | { |
c4241c7d | 3579 | return vfp_get_fpcr(env); |
b0d2b7d0 PM |
3580 | } |
3581 | ||
c4241c7d PM |
3582 | static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3583 | uint64_t value) | |
b0d2b7d0 PM |
3584 | { |
3585 | vfp_set_fpcr(env, value); | |
b0d2b7d0 PM |
3586 | } |
3587 | ||
c4241c7d | 3588 | static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 3589 | { |
c4241c7d | 3590 | return vfp_get_fpsr(env); |
b0d2b7d0 PM |
3591 | } |
3592 | ||
c4241c7d PM |
3593 | static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3594 | uint64_t value) | |
b0d2b7d0 PM |
3595 | { |
3596 | vfp_set_fpsr(env, value); | |
b0d2b7d0 PM |
3597 | } |
3598 | ||
3f208fd7 PM |
3599 | static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3600 | bool isread) | |
c2b820fe | 3601 | { |
137feaa9 | 3602 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { |
c2b820fe PM |
3603 | return CP_ACCESS_TRAP; |
3604 | } | |
3605 | return CP_ACCESS_OK; | |
3606 | } | |
3607 | ||
3608 | static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3609 | uint64_t value) | |
3610 | { | |
3611 | env->daif = value & PSTATE_DAIF; | |
3612 | } | |
3613 | ||
8af35c37 | 3614 | static CPAccessResult aa64_cacheop_access(CPUARMState *env, |
3f208fd7 PM |
3615 | const ARMCPRegInfo *ri, |
3616 | bool isread) | |
8af35c37 PM |
3617 | { |
3618 | /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless | |
3619 | * SCTLR_EL1.UCI is set. | |
3620 | */ | |
137feaa9 | 3621 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) { |
8af35c37 PM |
3622 | return CP_ACCESS_TRAP; |
3623 | } | |
3624 | return CP_ACCESS_OK; | |
3625 | } | |
3626 | ||
dbb1fb27 AB |
3627 | /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions |
3628 | * Page D4-1736 (DDI0487A.b) | |
3629 | */ | |
3630 | ||
fd3ed969 PM |
3631 | static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3632 | uint64_t value) | |
168aa23b | 3633 | { |
a67cf277 | 3634 | CPUState *cs = ENV_GET_CPU(env); |
fd3ed969 | 3635 | bool sec = arm_is_secure_below_el3(env); |
dbb1fb27 | 3636 | |
a67cf277 AB |
3637 | if (sec) { |
3638 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3639 | ARMMMUIdxBit_S1SE1 | |
3640 | ARMMMUIdxBit_S1SE0); | |
a67cf277 AB |
3641 | } else { |
3642 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3643 | ARMMMUIdxBit_S12NSE1 | |
3644 | ARMMMUIdxBit_S12NSE0); | |
fd3ed969 | 3645 | } |
168aa23b PM |
3646 | } |
3647 | ||
b4ab8ce9 PM |
3648 | static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3649 | uint64_t value) | |
3650 | { | |
3651 | CPUState *cs = ENV_GET_CPU(env); | |
3652 | ||
3653 | if (tlb_force_broadcast(env)) { | |
09a86dfa | 3654 | tlbi_aa64_vmalle1is_write(env, NULL, value); |
b4ab8ce9 PM |
3655 | return; |
3656 | } | |
3657 | ||
3658 | if (arm_is_secure_below_el3(env)) { | |
3659 | tlb_flush_by_mmuidx(cs, | |
3660 | ARMMMUIdxBit_S1SE1 | | |
3661 | ARMMMUIdxBit_S1SE0); | |
3662 | } else { | |
3663 | tlb_flush_by_mmuidx(cs, | |
3664 | ARMMMUIdxBit_S12NSE1 | | |
3665 | ARMMMUIdxBit_S12NSE0); | |
3666 | } | |
3667 | } | |
3668 | ||
fd3ed969 PM |
3669 | static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3670 | uint64_t value) | |
168aa23b | 3671 | { |
fd3ed969 PM |
3672 | /* Note that the 'ALL' scope must invalidate both stage 1 and |
3673 | * stage 2 translations, whereas most other scopes only invalidate | |
3674 | * stage 1 translations. | |
3675 | */ | |
00c8cb0a | 3676 | ARMCPU *cpu = arm_env_get_cpu(env); |
fd3ed969 PM |
3677 | CPUState *cs = CPU(cpu); |
3678 | ||
3679 | if (arm_is_secure_below_el3(env)) { | |
0336cbf8 | 3680 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
3681 | ARMMMUIdxBit_S1SE1 | |
3682 | ARMMMUIdxBit_S1SE0); | |
fd3ed969 PM |
3683 | } else { |
3684 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
0336cbf8 | 3685 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
3686 | ARMMMUIdxBit_S12NSE1 | |
3687 | ARMMMUIdxBit_S12NSE0 | | |
3688 | ARMMMUIdxBit_S2NS); | |
fd3ed969 | 3689 | } else { |
0336cbf8 | 3690 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
3691 | ARMMMUIdxBit_S12NSE1 | |
3692 | ARMMMUIdxBit_S12NSE0); | |
fd3ed969 PM |
3693 | } |
3694 | } | |
168aa23b PM |
3695 | } |
3696 | ||
fd3ed969 | 3697 | static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
fa439fc5 PM |
3698 | uint64_t value) |
3699 | { | |
fd3ed969 PM |
3700 | ARMCPU *cpu = arm_env_get_cpu(env); |
3701 | CPUState *cs = CPU(cpu); | |
3702 | ||
8bd5c820 | 3703 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); |
fd3ed969 PM |
3704 | } |
3705 | ||
43efaa33 PM |
3706 | static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3707 | uint64_t value) | |
3708 | { | |
3709 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3710 | CPUState *cs = CPU(cpu); | |
3711 | ||
8bd5c820 | 3712 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3); |
43efaa33 PM |
3713 | } |
3714 | ||
fd3ed969 PM |
3715 | static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3716 | uint64_t value) | |
3717 | { | |
3718 | /* Note that the 'ALL' scope must invalidate both stage 1 and | |
3719 | * stage 2 translations, whereas most other scopes only invalidate | |
3720 | * stage 1 translations. | |
3721 | */ | |
a67cf277 | 3722 | CPUState *cs = ENV_GET_CPU(env); |
fd3ed969 PM |
3723 | bool sec = arm_is_secure_below_el3(env); |
3724 | bool has_el2 = arm_feature(env, ARM_FEATURE_EL2); | |
a67cf277 AB |
3725 | |
3726 | if (sec) { | |
3727 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3728 | ARMMMUIdxBit_S1SE1 | |
3729 | ARMMMUIdxBit_S1SE0); | |
a67cf277 AB |
3730 | } else if (has_el2) { |
3731 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3732 | ARMMMUIdxBit_S12NSE1 | |
3733 | ARMMMUIdxBit_S12NSE0 | | |
3734 | ARMMMUIdxBit_S2NS); | |
a67cf277 AB |
3735 | } else { |
3736 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3737 | ARMMMUIdxBit_S12NSE1 | |
3738 | ARMMMUIdxBit_S12NSE0); | |
fa439fc5 PM |
3739 | } |
3740 | } | |
3741 | ||
2bfb9d75 PM |
3742 | static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3743 | uint64_t value) | |
3744 | { | |
a67cf277 | 3745 | CPUState *cs = ENV_GET_CPU(env); |
2bfb9d75 | 3746 | |
8bd5c820 | 3747 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); |
2bfb9d75 PM |
3748 | } |
3749 | ||
43efaa33 PM |
3750 | static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3751 | uint64_t value) | |
3752 | { | |
a67cf277 | 3753 | CPUState *cs = ENV_GET_CPU(env); |
43efaa33 | 3754 | |
8bd5c820 | 3755 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3); |
43efaa33 PM |
3756 | } |
3757 | ||
fd3ed969 PM |
3758 | static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3759 | uint64_t value) | |
fa439fc5 | 3760 | { |
fd3ed969 PM |
3761 | /* Invalidate by VA, EL2 |
3762 | * Currently handles both VAE2 and VALE2, since we don't support | |
3763 | * flush-last-level-only. | |
3764 | */ | |
3765 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3766 | CPUState *cs = CPU(cpu); | |
3767 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
3768 | ||
8bd5c820 | 3769 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); |
fd3ed969 PM |
3770 | } |
3771 | ||
43efaa33 PM |
3772 | static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3773 | uint64_t value) | |
3774 | { | |
3775 | /* Invalidate by VA, EL3 | |
3776 | * Currently handles both VAE3 and VALE3, since we don't support | |
3777 | * flush-last-level-only. | |
3778 | */ | |
3779 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3780 | CPUState *cs = CPU(cpu); | |
3781 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
3782 | ||
8bd5c820 | 3783 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3); |
43efaa33 PM |
3784 | } |
3785 | ||
fd3ed969 PM |
3786 | static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3787 | uint64_t value) | |
3788 | { | |
a67cf277 AB |
3789 | ARMCPU *cpu = arm_env_get_cpu(env); |
3790 | CPUState *cs = CPU(cpu); | |
fd3ed969 | 3791 | bool sec = arm_is_secure_below_el3(env); |
fa439fc5 PM |
3792 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
3793 | ||
a67cf277 AB |
3794 | if (sec) { |
3795 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, | |
8bd5c820 PM |
3796 | ARMMMUIdxBit_S1SE1 | |
3797 | ARMMMUIdxBit_S1SE0); | |
a67cf277 AB |
3798 | } else { |
3799 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, | |
8bd5c820 PM |
3800 | ARMMMUIdxBit_S12NSE1 | |
3801 | ARMMMUIdxBit_S12NSE0); | |
fa439fc5 PM |
3802 | } |
3803 | } | |
3804 | ||
b4ab8ce9 PM |
3805 | static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3806 | uint64_t value) | |
3807 | { | |
3808 | /* Invalidate by VA, EL1&0 (AArch64 version). | |
3809 | * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, | |
3810 | * since we don't support flush-for-specific-ASID-only or | |
3811 | * flush-last-level-only. | |
3812 | */ | |
3813 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3814 | CPUState *cs = CPU(cpu); | |
3815 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
3816 | ||
3817 | if (tlb_force_broadcast(env)) { | |
3818 | tlbi_aa64_vae1is_write(env, NULL, value); | |
3819 | return; | |
3820 | } | |
3821 | ||
3822 | if (arm_is_secure_below_el3(env)) { | |
3823 | tlb_flush_page_by_mmuidx(cs, pageaddr, | |
3824 | ARMMMUIdxBit_S1SE1 | | |
3825 | ARMMMUIdxBit_S1SE0); | |
3826 | } else { | |
3827 | tlb_flush_page_by_mmuidx(cs, pageaddr, | |
3828 | ARMMMUIdxBit_S12NSE1 | | |
3829 | ARMMMUIdxBit_S12NSE0); | |
3830 | } | |
3831 | } | |
3832 | ||
fd3ed969 PM |
3833 | static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3834 | uint64_t value) | |
fa439fc5 | 3835 | { |
a67cf277 | 3836 | CPUState *cs = ENV_GET_CPU(env); |
fd3ed969 | 3837 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
fa439fc5 | 3838 | |
a67cf277 | 3839 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 3840 | ARMMMUIdxBit_S1E2); |
fa439fc5 PM |
3841 | } |
3842 | ||
43efaa33 PM |
3843 | static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3844 | uint64_t value) | |
3845 | { | |
a67cf277 | 3846 | CPUState *cs = ENV_GET_CPU(env); |
43efaa33 PM |
3847 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
3848 | ||
a67cf277 | 3849 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 3850 | ARMMMUIdxBit_S1E3); |
43efaa33 PM |
3851 | } |
3852 | ||
cea66e91 PM |
3853 | static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3854 | uint64_t value) | |
3855 | { | |
3856 | /* Invalidate by IPA. This has to invalidate any structures that | |
3857 | * contain only stage 2 translation information, but does not need | |
3858 | * to apply to structures that contain combined stage 1 and stage 2 | |
3859 | * translation information. | |
3860 | * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. | |
3861 | */ | |
3862 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3863 | CPUState *cs = CPU(cpu); | |
3864 | uint64_t pageaddr; | |
3865 | ||
3866 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
3867 | return; | |
3868 | } | |
3869 | ||
3870 | pageaddr = sextract64(value << 12, 0, 48); | |
3871 | ||
8bd5c820 | 3872 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); |
cea66e91 PM |
3873 | } |
3874 | ||
3875 | static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3876 | uint64_t value) | |
3877 | { | |
a67cf277 | 3878 | CPUState *cs = ENV_GET_CPU(env); |
cea66e91 PM |
3879 | uint64_t pageaddr; |
3880 | ||
3881 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
3882 | return; | |
3883 | } | |
3884 | ||
3885 | pageaddr = sextract64(value << 12, 0, 48); | |
3886 | ||
a67cf277 | 3887 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 3888 | ARMMMUIdxBit_S2NS); |
cea66e91 PM |
3889 | } |
3890 | ||
3f208fd7 PM |
3891 | static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3892 | bool isread) | |
aca3f40b PM |
3893 | { |
3894 | /* We don't implement EL2, so the only control on DC ZVA is the | |
3895 | * bit in the SCTLR which can prohibit access for EL0. | |
3896 | */ | |
137feaa9 | 3897 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) { |
aca3f40b PM |
3898 | return CP_ACCESS_TRAP; |
3899 | } | |
3900 | return CP_ACCESS_OK; | |
3901 | } | |
3902 | ||
3903 | static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3904 | { | |
3905 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3906 | int dzp_bit = 1 << 4; | |
3907 | ||
3908 | /* DZP indicates whether DC ZVA access is allowed */ | |
3f208fd7 | 3909 | if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) { |
aca3f40b PM |
3910 | dzp_bit = 0; |
3911 | } | |
3912 | return cpu->dcz_blocksize | dzp_bit; | |
3913 | } | |
3914 | ||
3f208fd7 PM |
3915 | static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3916 | bool isread) | |
f502cfc2 | 3917 | { |
cdcf1405 | 3918 | if (!(env->pstate & PSTATE_SP)) { |
f502cfc2 PM |
3919 | /* Access to SP_EL0 is undefined if it's being used as |
3920 | * the stack pointer. | |
3921 | */ | |
3922 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
3923 | } | |
3924 | return CP_ACCESS_OK; | |
3925 | } | |
3926 | ||
3927 | static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3928 | { | |
3929 | return env->pstate & PSTATE_SP; | |
3930 | } | |
3931 | ||
3932 | static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
3933 | { | |
3934 | update_spsel(env, val); | |
3935 | } | |
3936 | ||
137feaa9 FA |
3937 | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3938 | uint64_t value) | |
3939 | { | |
3940 | ARMCPU *cpu = arm_env_get_cpu(env); | |
3941 | ||
3942 | if (raw_read(env, ri) == value) { | |
3943 | /* Skip the TLB flush if nothing actually changed; Linux likes | |
3944 | * to do a lot of pointless SCTLR writes. | |
3945 | */ | |
3946 | return; | |
3947 | } | |
3948 | ||
06312feb PM |
3949 | if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { |
3950 | /* M bit is RAZ/WI for PMSA with no MPU implemented */ | |
3951 | value &= ~SCTLR_M; | |
3952 | } | |
3953 | ||
137feaa9 FA |
3954 | raw_write(env, ri, value); |
3955 | /* ??? Lots of these bits are not implemented. */ | |
3956 | /* This may enable/disable the MMU, so do a TLB flush. */ | |
d10eb08f | 3957 | tlb_flush(CPU(cpu)); |
137feaa9 FA |
3958 | } |
3959 | ||
3f208fd7 PM |
3960 | static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3961 | bool isread) | |
03fbf20f PM |
3962 | { |
3963 | if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { | |
f2cae609 | 3964 | return CP_ACCESS_TRAP_FP_EL2; |
03fbf20f PM |
3965 | } |
3966 | if (env->cp15.cptr_el[3] & CPTR_TFP) { | |
f2cae609 | 3967 | return CP_ACCESS_TRAP_FP_EL3; |
03fbf20f PM |
3968 | } |
3969 | return CP_ACCESS_OK; | |
3970 | } | |
3971 | ||
a8d64e73 PM |
3972 | static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3973 | uint64_t value) | |
3974 | { | |
3975 | env->cp15.mdcr_el3 = value & SDCR_VALID_MASK; | |
3976 | } | |
3977 | ||
b0d2b7d0 PM |
3978 | static const ARMCPRegInfo v8_cp_reginfo[] = { |
3979 | /* Minimal set of EL0-visible registers. This will need to be expanded | |
3980 | * significantly for system emulation of AArch64 CPUs. | |
3981 | */ | |
3982 | { .name = "NZCV", .state = ARM_CP_STATE_AA64, | |
3983 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, | |
3984 | .access = PL0_RW, .type = ARM_CP_NZCV }, | |
c2b820fe PM |
3985 | { .name = "DAIF", .state = ARM_CP_STATE_AA64, |
3986 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, | |
7a0e58fa | 3987 | .type = ARM_CP_NO_RAW, |
c2b820fe PM |
3988 | .access = PL0_RW, .accessfn = aa64_daif_access, |
3989 | .fieldoffset = offsetof(CPUARMState, daif), | |
3990 | .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, | |
b0d2b7d0 PM |
3991 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, |
3992 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | |
b916c9c3 | 3993 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 3994 | .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, |
b0d2b7d0 PM |
3995 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, |
3996 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | |
b916c9c3 | 3997 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 3998 | .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, |
b0d2b7d0 PM |
3999 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, |
4000 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | |
7a0e58fa | 4001 | .access = PL0_R, .type = ARM_CP_NO_RAW, |
aca3f40b PM |
4002 | .readfn = aa64_dczid_read }, |
4003 | { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, | |
4004 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, | |
4005 | .access = PL0_W, .type = ARM_CP_DC_ZVA, | |
4006 | #ifndef CONFIG_USER_ONLY | |
4007 | /* Avoid overhead of an access check that always passes in user-mode */ | |
4008 | .accessfn = aa64_zva_access, | |
4009 | #endif | |
4010 | }, | |
0eef9d98 PM |
4011 | { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, |
4012 | .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, | |
4013 | .access = PL1_R, .type = ARM_CP_CURRENTEL }, | |
8af35c37 PM |
4014 | /* Cache ops: all NOPs since we don't emulate caches */ |
4015 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, | |
4016 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
4017 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4018 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, | |
4019 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
4020 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4021 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, | |
4022 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | |
4023 | .access = PL0_W, .type = ARM_CP_NOP, | |
4024 | .accessfn = aa64_cacheop_access }, | |
4025 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, | |
4026 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
4027 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4028 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, | |
4029 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
4030 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4031 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, | |
4032 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | |
4033 | .access = PL0_W, .type = ARM_CP_NOP, | |
4034 | .accessfn = aa64_cacheop_access }, | |
4035 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, | |
4036 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
4037 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4038 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, | |
4039 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | |
4040 | .access = PL0_W, .type = ARM_CP_NOP, | |
4041 | .accessfn = aa64_cacheop_access }, | |
4042 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, | |
4043 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | |
4044 | .access = PL0_W, .type = ARM_CP_NOP, | |
4045 | .accessfn = aa64_cacheop_access }, | |
4046 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, | |
4047 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
4048 | .access = PL1_W, .type = ARM_CP_NOP }, | |
168aa23b PM |
4049 | /* TLBI operations */ |
4050 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 4051 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, |
7a0e58fa | 4052 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4053 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 4054 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4055 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
7a0e58fa | 4056 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4057 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4058 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4059 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
7a0e58fa | 4060 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4061 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 4062 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4063 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
7a0e58fa | 4064 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4065 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4066 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4067 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
7a0e58fa | 4068 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4069 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4070 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4071 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
7a0e58fa | 4072 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4073 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4074 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4075 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, |
7a0e58fa | 4076 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4077 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 4078 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4079 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
7a0e58fa | 4080 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4081 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4082 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4083 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
7a0e58fa | 4084 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4085 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 4086 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4087 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
7a0e58fa | 4088 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4089 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4090 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4091 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
7a0e58fa | 4092 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4093 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4094 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4095 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
7a0e58fa | 4096 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4097 | .writefn = tlbi_aa64_vae1_write }, |
cea66e91 PM |
4098 | { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, |
4099 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
4100 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4101 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
4102 | { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, | |
4103 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
4104 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4105 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
83ddf975 PM |
4106 | { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, |
4107 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
4108 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 4109 | .writefn = tlbi_aa64_alle1is_write }, |
43efaa33 PM |
4110 | { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, |
4111 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, | |
4112 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4113 | .writefn = tlbi_aa64_alle1is_write }, | |
cea66e91 PM |
4114 | { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, |
4115 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
4116 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4117 | .writefn = tlbi_aa64_ipas2e1_write }, | |
4118 | { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, | |
4119 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
4120 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4121 | .writefn = tlbi_aa64_ipas2e1_write }, | |
83ddf975 PM |
4122 | { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, |
4123 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
4124 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 4125 | .writefn = tlbi_aa64_alle1_write }, |
43efaa33 PM |
4126 | { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, |
4127 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, | |
4128 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4129 | .writefn = tlbi_aa64_alle1is_write }, | |
19525524 PM |
4130 | #ifndef CONFIG_USER_ONLY |
4131 | /* 64 bit address translation operations */ | |
4132 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
4133 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, | |
060e8a48 | 4134 | .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
19525524 PM |
4135 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, |
4136 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, | |
060e8a48 | 4137 | .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
19525524 PM |
4138 | { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, |
4139 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, | |
060e8a48 | 4140 | .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
19525524 PM |
4141 | { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, |
4142 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, | |
060e8a48 | 4143 | .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
2a47df95 | 4144 | { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4145 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, |
2a47df95 PM |
4146 | .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
4147 | { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, | |
7a379c7e | 4148 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, |
2a47df95 PM |
4149 | .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
4150 | { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, | |
7a379c7e | 4151 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, |
2a47df95 PM |
4152 | .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
4153 | { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, | |
7a379c7e | 4154 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, |
2a47df95 PM |
4155 | .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, |
4156 | /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ | |
4157 | { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, | |
4158 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, | |
4159 | .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, | |
4160 | { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, | |
4161 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, | |
4162 | .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, | |
c96fc9b5 EI |
4163 | { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, |
4164 | .type = ARM_CP_ALIAS, | |
4165 | .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, | |
4166 | .access = PL1_RW, .resetvalue = 0, | |
4167 | .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), | |
4168 | .writefn = par_write }, | |
19525524 | 4169 | #endif |
995939a6 | 4170 | /* TLB invalidate last level of translation table walk */ |
9449fdf6 | 4171 | { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
7a0e58fa | 4172 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, |
9449fdf6 | 4173 | { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
7a0e58fa | 4174 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 4175 | .writefn = tlbimvaa_is_write }, |
9449fdf6 | 4176 | { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
7a0e58fa | 4177 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
9449fdf6 | 4178 | { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
7a0e58fa | 4179 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, |
541ef8c2 SS |
4180 | { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, |
4181 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4182 | .writefn = tlbimva_hyp_write }, | |
4183 | { .name = "TLBIMVALHIS", | |
4184 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
4185 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4186 | .writefn = tlbimva_hyp_is_write }, | |
4187 | { .name = "TLBIIPAS2", | |
4188 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
4189 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4190 | .writefn = tlbiipas2_write }, | |
4191 | { .name = "TLBIIPAS2IS", | |
4192 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
4193 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4194 | .writefn = tlbiipas2_is_write }, | |
4195 | { .name = "TLBIIPAS2L", | |
4196 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
4197 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4198 | .writefn = tlbiipas2_write }, | |
4199 | { .name = "TLBIIPAS2LIS", | |
4200 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
4201 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4202 | .writefn = tlbiipas2_is_write }, | |
9449fdf6 PM |
4203 | /* 32 bit cache operations */ |
4204 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
4205 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4206 | { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, | |
4207 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4208 | { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
4209 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4210 | { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, | |
4211 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4212 | { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, | |
4213 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4214 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | |
4215 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4216 | { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
4217 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4218 | { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
4219 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4220 | { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, | |
4221 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4222 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
4223 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4224 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, | |
4225 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4226 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, | |
4227 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4228 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
4229 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4230 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
4231 | { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, |
4232 | .access = PL1_RW, .resetvalue = 0, | |
4233 | .writefn = dacr_write, .raw_writefn = raw_write, | |
4234 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
4235 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a0618a19 | 4236 | { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4237 | .type = ARM_CP_ALIAS, |
a0618a19 | 4238 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, |
6947f059 EI |
4239 | .access = PL1_RW, |
4240 | .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, | |
a65f1de9 | 4241 | { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4242 | .type = ARM_CP_ALIAS, |
a65f1de9 | 4243 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
4244 | .access = PL1_RW, |
4245 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, | |
f502cfc2 PM |
4246 | /* We rely on the access checks not allowing the guest to write to the |
4247 | * state field when SPSel indicates that it's being used as the stack | |
4248 | * pointer. | |
4249 | */ | |
4250 | { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, | |
4251 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, | |
4252 | .access = PL1_RW, .accessfn = sp_el0_access, | |
7a0e58fa | 4253 | .type = ARM_CP_ALIAS, |
f502cfc2 | 4254 | .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, |
884b4dee GB |
4255 | { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, |
4256 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 4257 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
884b4dee | 4258 | .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, |
f502cfc2 PM |
4259 | { .name = "SPSel", .state = ARM_CP_STATE_AA64, |
4260 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, | |
7a0e58fa | 4261 | .type = ARM_CP_NO_RAW, |
f502cfc2 | 4262 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, |
03fbf20f PM |
4263 | { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, |
4264 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, | |
4265 | .type = ARM_CP_ALIAS, | |
4266 | .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), | |
4267 | .access = PL2_RW, .accessfn = fpexc32_access }, | |
6a43e0b6 PM |
4268 | { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, |
4269 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, | |
4270 | .access = PL2_RW, .resetvalue = 0, | |
4271 | .writefn = dacr_write, .raw_writefn = raw_write, | |
4272 | .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, | |
4273 | { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, | |
4274 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, | |
4275 | .access = PL2_RW, .resetvalue = 0, | |
4276 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, | |
4277 | { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, | |
4278 | .type = ARM_CP_ALIAS, | |
4279 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, | |
4280 | .access = PL2_RW, | |
4281 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, | |
4282 | { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, | |
4283 | .type = ARM_CP_ALIAS, | |
4284 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, | |
4285 | .access = PL2_RW, | |
4286 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, | |
4287 | { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, | |
4288 | .type = ARM_CP_ALIAS, | |
4289 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, | |
4290 | .access = PL2_RW, | |
4291 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, | |
4292 | { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, | |
4293 | .type = ARM_CP_ALIAS, | |
4294 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, | |
4295 | .access = PL2_RW, | |
4296 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, | |
a8d64e73 PM |
4297 | { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, |
4298 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, | |
4299 | .resetvalue = 0, | |
4300 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) }, | |
4301 | { .name = "SDCR", .type = ARM_CP_ALIAS, | |
4302 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1, | |
4303 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, | |
4304 | .writefn = sdcr_write, | |
4305 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, | |
b0d2b7d0 PM |
4306 | REGINFO_SENTINEL |
4307 | }; | |
4308 | ||
d42e3c26 | 4309 | /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ |
4771cd01 | 4310 | static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { |
d79e0c06 | 4311 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, |
d42e3c26 EI |
4312 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, |
4313 | .access = PL2_RW, | |
4314 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | |
ce4afed8 | 4315 | { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH, |
7a0e58fa | 4316 | .type = ARM_CP_NO_RAW, |
f149e3e8 EI |
4317 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
4318 | .access = PL2_RW, | |
ce4afed8 | 4319 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
68e78e33 PM |
4320 | { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, |
4321 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, | |
4322 | .access = PL2_RW, | |
4323 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
c6f19164 GB |
4324 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
4325 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
4326 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
95f949ac EI |
4327 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
4328 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
4329 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4330 | .resetvalue = 0 }, | |
4331 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
b5ede85b | 4332 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, |
95f949ac | 4333 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
2179ef95 PM |
4334 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
4335 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
4336 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4337 | .resetvalue = 0 }, | |
55b53c71 | 4338 | { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, |
b5ede85b | 4339 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, |
2179ef95 PM |
4340 | .access = PL2_RW, .type = ARM_CP_CONST, |
4341 | .resetvalue = 0 }, | |
37cd6c24 PM |
4342 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
4343 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
4344 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4345 | .resetvalue = 0 }, | |
4346 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
4347 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
4348 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4349 | .resetvalue = 0 }, | |
06ec4c8c EI |
4350 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
4351 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
4352 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
68e9c2fe EI |
4353 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH, |
4354 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
4355 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
4356 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b698e9cf EI |
4357 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
4358 | .cp = 15, .opc1 = 6, .crm = 2, | |
4359 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
4360 | .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | |
4361 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
4362 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
4363 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b9cb5323 EI |
4364 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
4365 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
4366 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
ff05f37b EI |
4367 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
4368 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
4369 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
a57633c0 EI |
4370 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
4371 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
4372 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4373 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
4374 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
4375 | .resetvalue = 0 }, | |
0b6440af EI |
4376 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
4377 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
4378 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
edac4d8a EI |
4379 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
4380 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
4381 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4382 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
4383 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
4384 | .resetvalue = 0 }, | |
b0e66d95 EI |
4385 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
4386 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
4387 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4388 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
4389 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
4390 | .resetvalue = 0 }, | |
4391 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
4392 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
4393 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4394 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
4395 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
4396 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
14cc7b54 SF |
4397 | { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, |
4398 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | |
d6c8cf81 PM |
4399 | .access = PL2_RW, .accessfn = access_tda, |
4400 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
59e05530 EI |
4401 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, |
4402 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
4403 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
4404 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2a5a9abd AF |
4405 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
4406 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
4407 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
cba517c3 PM |
4408 | { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, |
4409 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, | |
4410 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4411 | { .name = "HIFAR", .state = ARM_CP_STATE_AA32, | |
4412 | .type = ARM_CP_CONST, | |
4413 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | |
4414 | .access = PL2_RW, .resetvalue = 0 }, | |
d42e3c26 EI |
4415 | REGINFO_SENTINEL |
4416 | }; | |
4417 | ||
ce4afed8 PM |
4418 | /* Ditto, but for registers which exist in ARMv8 but not v7 */ |
4419 | static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { | |
4420 | { .name = "HCR2", .state = ARM_CP_STATE_AA32, | |
4421 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, | |
4422 | .access = PL2_RW, | |
4423 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4424 | REGINFO_SENTINEL | |
4425 | }; | |
4426 | ||
f149e3e8 EI |
4427 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4428 | { | |
4429 | ARMCPU *cpu = arm_env_get_cpu(env); | |
4430 | uint64_t valid_mask = HCR_MASK; | |
4431 | ||
4432 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
4433 | valid_mask &= ~HCR_HCD; | |
77077a83 JK |
4434 | } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { |
4435 | /* Architecturally HCR.TSC is RES0 if EL3 is not implemented. | |
4436 | * However, if we're using the SMC PSCI conduit then QEMU is | |
4437 | * effectively acting like EL3 firmware and so the guest at | |
4438 | * EL2 should retain the ability to prevent EL1 from being | |
4439 | * able to make SMC calls into the ersatz firmware, so in | |
4440 | * that case HCR.TSC should be read/write. | |
4441 | */ | |
f149e3e8 EI |
4442 | valid_mask &= ~HCR_TSC; |
4443 | } | |
2d7137c1 RH |
4444 | if (cpu_isar_feature(aa64_lor, cpu)) { |
4445 | valid_mask |= HCR_TLOR; | |
4446 | } | |
f149e3e8 EI |
4447 | |
4448 | /* Clear RES0 bits. */ | |
4449 | value &= valid_mask; | |
4450 | ||
4451 | /* These bits change the MMU setup: | |
4452 | * HCR_VM enables stage 2 translation | |
4453 | * HCR_PTW forbids certain page-table setups | |
4454 | * HCR_DC Disables stage1 and enables stage2 translation | |
4455 | */ | |
ce4afed8 | 4456 | if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { |
d10eb08f | 4457 | tlb_flush(CPU(cpu)); |
f149e3e8 | 4458 | } |
ce4afed8 | 4459 | env->cp15.hcr_el2 = value; |
89430fc6 PM |
4460 | |
4461 | /* | |
4462 | * Updates to VI and VF require us to update the status of | |
4463 | * virtual interrupts, which are the logical OR of these bits | |
4464 | * and the state of the input lines from the GIC. (This requires | |
4465 | * that we have the iothread lock, which is done by marking the | |
4466 | * reginfo structs as ARM_CP_IO.) | |
4467 | * Note that if a write to HCR pends a VIRQ or VFIQ it is never | |
4468 | * possible for it to be taken immediately, because VIRQ and | |
4469 | * VFIQ are masked unless running at EL0 or EL1, and HCR | |
4470 | * can only be written at EL2. | |
4471 | */ | |
4472 | g_assert(qemu_mutex_iothread_locked()); | |
4473 | arm_cpu_update_virq(cpu); | |
4474 | arm_cpu_update_vfiq(cpu); | |
ce4afed8 PM |
4475 | } |
4476 | ||
4477 | static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, | |
4478 | uint64_t value) | |
4479 | { | |
4480 | /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */ | |
4481 | value = deposit64(env->cp15.hcr_el2, 32, 32, value); | |
4482 | hcr_write(env, NULL, value); | |
4483 | } | |
4484 | ||
4485 | static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, | |
4486 | uint64_t value) | |
4487 | { | |
4488 | /* Handle HCR write, i.e. write to low half of HCR_EL2 */ | |
4489 | value = deposit64(env->cp15.hcr_el2, 0, 32, value); | |
4490 | hcr_write(env, NULL, value); | |
f149e3e8 EI |
4491 | } |
4492 | ||
f7778444 RH |
4493 | /* |
4494 | * Return the effective value of HCR_EL2. | |
4495 | * Bits that are not included here: | |
4496 | * RW (read from SCR_EL3.RW as needed) | |
4497 | */ | |
4498 | uint64_t arm_hcr_el2_eff(CPUARMState *env) | |
4499 | { | |
4500 | uint64_t ret = env->cp15.hcr_el2; | |
4501 | ||
4502 | if (arm_is_secure_below_el3(env)) { | |
4503 | /* | |
4504 | * "This register has no effect if EL2 is not enabled in the | |
4505 | * current Security state". This is ARMv8.4-SecEL2 speak for | |
4506 | * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1). | |
4507 | * | |
4508 | * Prior to that, the language was "In an implementation that | |
4509 | * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves | |
4510 | * as if this field is 0 for all purposes other than a direct | |
4511 | * read or write access of HCR_EL2". With lots of enumeration | |
4512 | * on a per-field basis. In current QEMU, this is condition | |
4513 | * is arm_is_secure_below_el3. | |
4514 | * | |
4515 | * Since the v8.4 language applies to the entire register, and | |
4516 | * appears to be backward compatible, use that. | |
4517 | */ | |
4518 | ret = 0; | |
4519 | } else if (ret & HCR_TGE) { | |
4520 | /* These bits are up-to-date as of ARMv8.4. */ | |
4521 | if (ret & HCR_E2H) { | |
4522 | ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | | |
4523 | HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | | |
4524 | HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | | |
4525 | HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE); | |
4526 | } else { | |
4527 | ret |= HCR_FMO | HCR_IMO | HCR_AMO; | |
4528 | } | |
4529 | ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | | |
4530 | HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | | |
4531 | HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | | |
4532 | HCR_TLOR); | |
4533 | } | |
4534 | ||
4535 | return ret; | |
4536 | } | |
4537 | ||
4771cd01 | 4538 | static const ARMCPRegInfo el2_cp_reginfo[] = { |
f149e3e8 | 4539 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
89430fc6 | 4540 | .type = ARM_CP_IO, |
f149e3e8 EI |
4541 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
4542 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
c624ea0f | 4543 | .writefn = hcr_write }, |
ce4afed8 | 4544 | { .name = "HCR", .state = ARM_CP_STATE_AA32, |
89430fc6 | 4545 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
4546 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
4547 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
c624ea0f | 4548 | .writefn = hcr_writelow }, |
3b685ba7 | 4549 | { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4550 | .type = ARM_CP_ALIAS, |
3b685ba7 EI |
4551 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, |
4552 | .access = PL2_RW, | |
4553 | .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, | |
68e78e33 | 4554 | { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, |
f2c30f42 EI |
4555 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, |
4556 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, | |
cba517c3 | 4557 | { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, |
63b60551 EI |
4558 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, |
4559 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, | |
cba517c3 PM |
4560 | { .name = "HIFAR", .state = ARM_CP_STATE_AA32, |
4561 | .type = ARM_CP_ALIAS, | |
4562 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | |
4563 | .access = PL2_RW, | |
4564 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) }, | |
3b685ba7 | 4565 | { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4566 | .type = ARM_CP_ALIAS, |
3b685ba7 | 4567 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
4568 | .access = PL2_RW, |
4569 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, | |
d79e0c06 | 4570 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, |
d42e3c26 EI |
4571 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, |
4572 | .access = PL2_RW, .writefn = vbar_write, | |
4573 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), | |
4574 | .resetvalue = 0 }, | |
884b4dee GB |
4575 | { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, |
4576 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 4577 | .access = PL3_RW, .type = ARM_CP_ALIAS, |
884b4dee | 4578 | .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, |
c6f19164 GB |
4579 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
4580 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
4581 | .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, | |
4582 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) }, | |
95f949ac EI |
4583 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
4584 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
4585 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), | |
4586 | .resetvalue = 0 }, | |
4587 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
b5ede85b | 4588 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, |
95f949ac EI |
4589 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
4590 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, | |
2179ef95 PM |
4591 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
4592 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
4593 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4594 | .resetvalue = 0 }, | |
4595 | /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ | |
55b53c71 | 4596 | { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, |
b5ede85b | 4597 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, |
2179ef95 PM |
4598 | .access = PL2_RW, .type = ARM_CP_CONST, |
4599 | .resetvalue = 0 }, | |
37cd6c24 PM |
4600 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
4601 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
4602 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4603 | .resetvalue = 0 }, | |
4604 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
4605 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
4606 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4607 | .resetvalue = 0 }, | |
06ec4c8c EI |
4608 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
4609 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
6459b94c PM |
4610 | .access = PL2_RW, |
4611 | /* no .writefn needed as this can't cause an ASID change; | |
4612 | * no .raw_writefn or .resetfn needed as we never use mask/base_mask | |
4613 | */ | |
06ec4c8c | 4614 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, |
68e9c2fe EI |
4615 | { .name = "VTCR", .state = ARM_CP_STATE_AA32, |
4616 | .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 | 4617 | .type = ARM_CP_ALIAS, |
68e9c2fe EI |
4618 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
4619 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, | |
4620 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, | |
4621 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 PM |
4622 | .access = PL2_RW, |
4623 | /* no .writefn needed as this can't cause an ASID change; | |
4624 | * no .raw_writefn or .resetfn needed as we never use mask/base_mask | |
4625 | */ | |
68e9c2fe | 4626 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, |
b698e9cf EI |
4627 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
4628 | .cp = 15, .opc1 = 6, .crm = 2, | |
4629 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
4630 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
4631 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), | |
4632 | .writefn = vttbr_write }, | |
4633 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
4634 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
4635 | .access = PL2_RW, .writefn = vttbr_write, | |
4636 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, | |
b9cb5323 EI |
4637 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
4638 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
4639 | .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, | |
4640 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, | |
ff05f37b EI |
4641 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
4642 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
4643 | .access = PL2_RW, .resetvalue = 0, | |
4644 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, | |
a57633c0 EI |
4645 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
4646 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
4647 | .access = PL2_RW, .resetvalue = 0, | |
4648 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, | |
4649 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
4650 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
a57633c0 | 4651 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
541ef8c2 SS |
4652 | { .name = "TLBIALLNSNH", |
4653 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
4654 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4655 | .writefn = tlbiall_nsnh_write }, | |
4656 | { .name = "TLBIALLNSNHIS", | |
4657 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
4658 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4659 | .writefn = tlbiall_nsnh_is_write }, | |
4660 | { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
4661 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4662 | .writefn = tlbiall_hyp_write }, | |
4663 | { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
4664 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4665 | .writefn = tlbiall_hyp_is_write }, | |
4666 | { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
4667 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4668 | .writefn = tlbimva_hyp_write }, | |
4669 | { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
4670 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4671 | .writefn = tlbimva_hyp_is_write }, | |
51da9014 EI |
4672 | { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, |
4673 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
4674 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 4675 | .writefn = tlbi_aa64_alle2_write }, |
8742d49d EI |
4676 | { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, |
4677 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
4678 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 4679 | .writefn = tlbi_aa64_vae2_write }, |
2bfb9d75 PM |
4680 | { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, |
4681 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, | |
4682 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4683 | .writefn = tlbi_aa64_vae2_write }, | |
4684 | { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, | |
4685 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
4686 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4687 | .writefn = tlbi_aa64_alle2is_write }, | |
8742d49d EI |
4688 | { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, |
4689 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
4690 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 4691 | .writefn = tlbi_aa64_vae2is_write }, |
2bfb9d75 PM |
4692 | { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, |
4693 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
4694 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4695 | .writefn = tlbi_aa64_vae2is_write }, | |
edac4d8a | 4696 | #ifndef CONFIG_USER_ONLY |
2a47df95 PM |
4697 | /* Unlike the other EL2-related AT operations, these must |
4698 | * UNDEF from EL3 if EL2 is not implemented, which is why we | |
4699 | * define them here rather than with the rest of the AT ops. | |
4700 | */ | |
4701 | { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, | |
4702 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
4703 | .access = PL2_W, .accessfn = at_s1e2_access, | |
4704 | .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, | |
4705 | { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, | |
4706 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | |
4707 | .access = PL2_W, .accessfn = at_s1e2_access, | |
4708 | .type = ARM_CP_NO_RAW, .writefn = ats_write64 }, | |
14db7fe0 PM |
4709 | /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE |
4710 | * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 | |
4711 | * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose | |
4712 | * to behave as if SCR.NS was 1. | |
4713 | */ | |
4714 | { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
4715 | .access = PL2_W, | |
4716 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, | |
4717 | { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | |
4718 | .access = PL2_W, | |
4719 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW }, | |
0b6440af EI |
4720 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
4721 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
4722 | /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the | |
4723 | * reset values as IMPDEF. We choose to reset to 3 to comply with | |
4724 | * both ARMv7 and ARMv8. | |
4725 | */ | |
4726 | .access = PL2_RW, .resetvalue = 3, | |
4727 | .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, | |
edac4d8a EI |
4728 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
4729 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
4730 | .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, | |
4731 | .writefn = gt_cntvoff_write, | |
4732 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
4733 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
4734 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, | |
4735 | .writefn = gt_cntvoff_write, | |
4736 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
b0e66d95 EI |
4737 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
4738 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
4739 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
4740 | .type = ARM_CP_IO, .access = PL2_RW, | |
4741 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
4742 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
4743 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
4744 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO, | |
4745 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
4746 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
4747 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
d44ec156 | 4748 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, |
b0e66d95 EI |
4749 | .resetfn = gt_hyp_timer_reset, |
4750 | .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, | |
4751 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
4752 | .type = ARM_CP_IO, | |
4753 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
4754 | .access = PL2_RW, | |
4755 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), | |
4756 | .resetvalue = 0, | |
4757 | .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, | |
edac4d8a | 4758 | #endif |
14cc7b54 SF |
4759 | /* The only field of MDCR_EL2 that has a defined architectural reset value |
4760 | * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we | |
5ecdd3e4 | 4761 | * don't implement any PMU event counters, so using zero as a reset |
14cc7b54 SF |
4762 | * value for MDCR_EL2 is okay |
4763 | */ | |
4764 | { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, | |
4765 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | |
4766 | .access = PL2_RW, .resetvalue = 0, | |
4767 | .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), }, | |
59e05530 EI |
4768 | { .name = "HPFAR", .state = ARM_CP_STATE_AA32, |
4769 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
4770 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
4771 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
4772 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, | |
4773 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
4774 | .access = PL2_RW, | |
4775 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
2a5a9abd AF |
4776 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
4777 | .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
4778 | .access = PL2_RW, | |
4779 | .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, | |
3b685ba7 EI |
4780 | REGINFO_SENTINEL |
4781 | }; | |
4782 | ||
ce4afed8 PM |
4783 | static const ARMCPRegInfo el2_v8_cp_reginfo[] = { |
4784 | { .name = "HCR2", .state = ARM_CP_STATE_AA32, | |
89430fc6 | 4785 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
4786 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, |
4787 | .access = PL2_RW, | |
4788 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2), | |
4789 | .writefn = hcr_writehigh }, | |
4790 | REGINFO_SENTINEL | |
4791 | }; | |
4792 | ||
2f027fc5 PM |
4793 | static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4794 | bool isread) | |
4795 | { | |
4796 | /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. | |
4797 | * At Secure EL1 it traps to EL3. | |
4798 | */ | |
4799 | if (arm_current_el(env) == 3) { | |
4800 | return CP_ACCESS_OK; | |
4801 | } | |
4802 | if (arm_is_secure_below_el3(env)) { | |
4803 | return CP_ACCESS_TRAP_EL3; | |
4804 | } | |
4805 | /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ | |
4806 | if (isread) { | |
4807 | return CP_ACCESS_OK; | |
4808 | } | |
4809 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
4810 | } | |
4811 | ||
60fb1a87 GB |
4812 | static const ARMCPRegInfo el3_cp_reginfo[] = { |
4813 | { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, | |
4814 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, | |
4815 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), | |
4816 | .resetvalue = 0, .writefn = scr_write }, | |
7a0e58fa | 4817 | { .name = "SCR", .type = ARM_CP_ALIAS, |
60fb1a87 | 4818 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, |
efe4a274 PM |
4819 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
4820 | .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), | |
b061a82b | 4821 | .writefn = scr_write }, |
60fb1a87 GB |
4822 | { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, |
4823 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, | |
4824 | .access = PL3_RW, .resetvalue = 0, | |
4825 | .fieldoffset = offsetof(CPUARMState, cp15.sder) }, | |
4826 | { .name = "SDER", | |
4827 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, | |
4828 | .access = PL3_RW, .resetvalue = 0, | |
4829 | .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, | |
60fb1a87 | 4830 | { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, |
efe4a274 PM |
4831 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
4832 | .writefn = vbar_write, .resetvalue = 0, | |
60fb1a87 | 4833 | .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, |
7dd8c9af FA |
4834 | { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, |
4835 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, | |
f478847f | 4836 | .access = PL3_RW, .resetvalue = 0, |
7dd8c9af | 4837 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, |
11f136ee FA |
4838 | { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, |
4839 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, | |
6459b94c PM |
4840 | .access = PL3_RW, |
4841 | /* no .writefn needed as this can't cause an ASID change; | |
811595a2 PM |
4842 | * we must provide a .raw_writefn and .resetfn because we handle |
4843 | * reset and migration for the AArch32 TTBCR(S), which might be | |
4844 | * using mask and base_mask. | |
6459b94c | 4845 | */ |
811595a2 | 4846 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, |
11f136ee | 4847 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, |
81547d66 | 4848 | { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4849 | .type = ARM_CP_ALIAS, |
81547d66 EI |
4850 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, |
4851 | .access = PL3_RW, | |
4852 | .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, | |
f2c30f42 | 4853 | { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, |
f2c30f42 EI |
4854 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, |
4855 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, | |
63b60551 EI |
4856 | { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, |
4857 | .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, | |
4858 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, | |
81547d66 | 4859 | { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4860 | .type = ARM_CP_ALIAS, |
81547d66 | 4861 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
4862 | .access = PL3_RW, |
4863 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) }, | |
a1ba125c EI |
4864 | { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, |
4865 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, | |
4866 | .access = PL3_RW, .writefn = vbar_write, | |
4867 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), | |
4868 | .resetvalue = 0 }, | |
c6f19164 GB |
4869 | { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, |
4870 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, | |
4871 | .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, | |
4872 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, | |
4cfb8ad8 PM |
4873 | { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, |
4874 | .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, | |
4875 | .access = PL3_RW, .resetvalue = 0, | |
4876 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, | |
2179ef95 PM |
4877 | { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64, |
4878 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, | |
4879 | .access = PL3_RW, .type = ARM_CP_CONST, | |
4880 | .resetvalue = 0 }, | |
37cd6c24 PM |
4881 | { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, |
4882 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, | |
4883 | .access = PL3_RW, .type = ARM_CP_CONST, | |
4884 | .resetvalue = 0 }, | |
4885 | { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, | |
4886 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, | |
4887 | .access = PL3_RW, .type = ARM_CP_CONST, | |
4888 | .resetvalue = 0 }, | |
43efaa33 PM |
4889 | { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, |
4890 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, | |
4891 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
4892 | .writefn = tlbi_aa64_alle3is_write }, | |
4893 | { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, | |
4894 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, | |
4895 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
4896 | .writefn = tlbi_aa64_vae3is_write }, | |
4897 | { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, | |
4898 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, | |
4899 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
4900 | .writefn = tlbi_aa64_vae3is_write }, | |
4901 | { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, | |
4902 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, | |
4903 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
4904 | .writefn = tlbi_aa64_alle3_write }, | |
4905 | { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, | |
4906 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, | |
4907 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
4908 | .writefn = tlbi_aa64_vae3_write }, | |
4909 | { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, | |
4910 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, | |
4911 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
4912 | .writefn = tlbi_aa64_vae3_write }, | |
0f1a3b24 FA |
4913 | REGINFO_SENTINEL |
4914 | }; | |
4915 | ||
3f208fd7 PM |
4916 | static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4917 | bool isread) | |
7da845b0 PM |
4918 | { |
4919 | /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, | |
4920 | * but the AArch32 CTR has its own reginfo struct) | |
4921 | */ | |
137feaa9 | 4922 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) { |
7da845b0 PM |
4923 | return CP_ACCESS_TRAP; |
4924 | } | |
4925 | return CP_ACCESS_OK; | |
4926 | } | |
4927 | ||
1424ca8d DM |
4928 | static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4929 | uint64_t value) | |
4930 | { | |
4931 | /* Writes to OSLAR_EL1 may update the OS lock status, which can be | |
4932 | * read via a bit in OSLSR_EL1. | |
4933 | */ | |
4934 | int oslock; | |
4935 | ||
4936 | if (ri->state == ARM_CP_STATE_AA32) { | |
4937 | oslock = (value == 0xC5ACCE55); | |
4938 | } else { | |
4939 | oslock = value & 1; | |
4940 | } | |
4941 | ||
4942 | env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); | |
4943 | } | |
4944 | ||
50300698 | 4945 | static const ARMCPRegInfo debug_cp_reginfo[] = { |
50300698 | 4946 | /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped |
10aae104 PM |
4947 | * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; |
4948 | * unlike DBGDRAR it is never accessible from EL0. | |
4949 | * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 | |
4950 | * accessor. | |
50300698 PM |
4951 | */ |
4952 | { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
91b0a238 PM |
4953 | .access = PL0_R, .accessfn = access_tdra, |
4954 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
10aae104 PM |
4955 | { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, |
4956 | .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, | |
91b0a238 PM |
4957 | .access = PL1_R, .accessfn = access_tdra, |
4958 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
50300698 | 4959 | { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
91b0a238 PM |
4960 | .access = PL0_R, .accessfn = access_tdra, |
4961 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
17a9eb53 | 4962 | /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ |
10aae104 PM |
4963 | { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, |
4964 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
d6c8cf81 | 4965 | .access = PL1_RW, .accessfn = access_tda, |
0e5e8935 PM |
4966 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), |
4967 | .resetvalue = 0 }, | |
5e8b12ff PM |
4968 | /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. |
4969 | * We don't implement the configurable EL0 access. | |
4970 | */ | |
4971 | { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH, | |
4972 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
7a0e58fa | 4973 | .type = ARM_CP_ALIAS, |
d6c8cf81 | 4974 | .access = PL1_R, .accessfn = access_tda, |
b061a82b | 4975 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, |
10aae104 PM |
4976 | { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, |
4977 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, | |
1424ca8d | 4978 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
187f678d | 4979 | .accessfn = access_tdosa, |
1424ca8d DM |
4980 | .writefn = oslar_write }, |
4981 | { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, | |
4982 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, | |
4983 | .access = PL1_R, .resetvalue = 10, | |
187f678d | 4984 | .accessfn = access_tdosa, |
1424ca8d | 4985 | .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, |
5e8b12ff PM |
4986 | /* Dummy OSDLR_EL1: 32-bit Linux will read this */ |
4987 | { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, | |
4988 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, | |
187f678d PM |
4989 | .access = PL1_RW, .accessfn = access_tdosa, |
4990 | .type = ARM_CP_NOP }, | |
5e8b12ff PM |
4991 | /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't |
4992 | * implement vector catch debug events yet. | |
4993 | */ | |
4994 | { .name = "DBGVCR", | |
4995 | .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
d6c8cf81 PM |
4996 | .access = PL1_RW, .accessfn = access_tda, |
4997 | .type = ARM_CP_NOP }, | |
4d2ec4da PM |
4998 | /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor |
4999 | * to save and restore a 32-bit guest's DBGVCR) | |
5000 | */ | |
5001 | { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, | |
5002 | .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, | |
5003 | .access = PL2_RW, .accessfn = access_tda, | |
5004 | .type = ARM_CP_NOP }, | |
5dbdc434 PM |
5005 | /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications |
5006 | * Channel but Linux may try to access this register. The 32-bit | |
5007 | * alias is DBGDCCINT. | |
5008 | */ | |
5009 | { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, | |
5010 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
5011 | .access = PL1_RW, .accessfn = access_tda, | |
5012 | .type = ARM_CP_NOP }, | |
50300698 PM |
5013 | REGINFO_SENTINEL |
5014 | }; | |
5015 | ||
5016 | static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | |
5017 | /* 64 bit access versions of the (dummy) debug registers */ | |
5018 | { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, | |
5019 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
5020 | { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | |
5021 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
5022 | REGINFO_SENTINEL | |
5023 | }; | |
5024 | ||
60eed086 RH |
5025 | /* Return the exception level to which exceptions should be taken |
5026 | * via SVEAccessTrap. If an exception should be routed through | |
5027 | * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should | |
5028 | * take care of raising that exception. | |
5029 | * C.f. the ARM pseudocode function CheckSVEEnabled. | |
5be5e8ed | 5030 | */ |
ced31551 | 5031 | int sve_exception_el(CPUARMState *env, int el) |
5be5e8ed RH |
5032 | { |
5033 | #ifndef CONFIG_USER_ONLY | |
2de7ace2 | 5034 | if (el <= 1) { |
60eed086 RH |
5035 | bool disabled = false; |
5036 | ||
5037 | /* The CPACR.ZEN controls traps to EL1: | |
5038 | * 0, 2 : trap EL0 and EL1 accesses | |
5039 | * 1 : trap only EL0 accesses | |
5040 | * 3 : trap no accesses | |
5041 | */ | |
5042 | if (!extract32(env->cp15.cpacr_el1, 16, 1)) { | |
5043 | disabled = true; | |
5044 | } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) { | |
2de7ace2 | 5045 | disabled = el == 0; |
5be5e8ed | 5046 | } |
60eed086 RH |
5047 | if (disabled) { |
5048 | /* route_to_el2 */ | |
5049 | return (arm_feature(env, ARM_FEATURE_EL2) | |
7c208e0f | 5050 | && (arm_hcr_el2_eff(env) & HCR_TGE) ? 2 : 1); |
5be5e8ed | 5051 | } |
5be5e8ed | 5052 | |
60eed086 RH |
5053 | /* Check CPACR.FPEN. */ |
5054 | if (!extract32(env->cp15.cpacr_el1, 20, 1)) { | |
5055 | disabled = true; | |
5056 | } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) { | |
2de7ace2 | 5057 | disabled = el == 0; |
5be5e8ed | 5058 | } |
60eed086 RH |
5059 | if (disabled) { |
5060 | return 0; | |
5be5e8ed | 5061 | } |
5be5e8ed RH |
5062 | } |
5063 | ||
60eed086 RH |
5064 | /* CPTR_EL2. Since TZ and TFP are positive, |
5065 | * they will be zero when EL2 is not present. | |
5066 | */ | |
2de7ace2 | 5067 | if (el <= 2 && !arm_is_secure_below_el3(env)) { |
60eed086 RH |
5068 | if (env->cp15.cptr_el[2] & CPTR_TZ) { |
5069 | return 2; | |
5070 | } | |
5071 | if (env->cp15.cptr_el[2] & CPTR_TFP) { | |
5072 | return 0; | |
5073 | } | |
5be5e8ed RH |
5074 | } |
5075 | ||
60eed086 RH |
5076 | /* CPTR_EL3. Since EZ is negative we must check for EL3. */ |
5077 | if (arm_feature(env, ARM_FEATURE_EL3) | |
5078 | && !(env->cp15.cptr_el[3] & CPTR_EZ)) { | |
5be5e8ed RH |
5079 | return 3; |
5080 | } | |
5081 | #endif | |
5082 | return 0; | |
5083 | } | |
5084 | ||
0ab5953b RH |
5085 | /* |
5086 | * Given that SVE is enabled, return the vector length for EL. | |
5087 | */ | |
ced31551 | 5088 | uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) |
0ab5953b RH |
5089 | { |
5090 | ARMCPU *cpu = arm_env_get_cpu(env); | |
5091 | uint32_t zcr_len = cpu->sve_max_vq - 1; | |
5092 | ||
5093 | if (el <= 1) { | |
5094 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); | |
5095 | } | |
5096 | if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { | |
5097 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); | |
5098 | } | |
5099 | if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) { | |
5100 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); | |
5101 | } | |
5102 | return zcr_len; | |
5103 | } | |
5104 | ||
5be5e8ed RH |
5105 | static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5106 | uint64_t value) | |
5107 | { | |
0ab5953b RH |
5108 | int cur_el = arm_current_el(env); |
5109 | int old_len = sve_zcr_len_for_el(env, cur_el); | |
5110 | int new_len; | |
5111 | ||
5be5e8ed RH |
5112 | /* Bits other than [3:0] are RAZ/WI. */ |
5113 | raw_write(env, ri, value & 0xf); | |
0ab5953b RH |
5114 | |
5115 | /* | |
5116 | * Because we arrived here, we know both FP and SVE are enabled; | |
5117 | * otherwise we would have trapped access to the ZCR_ELn register. | |
5118 | */ | |
5119 | new_len = sve_zcr_len_for_el(env, cur_el); | |
5120 | if (new_len < old_len) { | |
5121 | aarch64_sve_narrow_vq(env, new_len + 1); | |
5122 | } | |
5be5e8ed RH |
5123 | } |
5124 | ||
5125 | static const ARMCPRegInfo zcr_el1_reginfo = { | |
5126 | .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | |
5127 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 5128 | .access = PL1_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
5129 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), |
5130 | .writefn = zcr_write, .raw_writefn = raw_write | |
5131 | }; | |
5132 | ||
5133 | static const ARMCPRegInfo zcr_el2_reginfo = { | |
5134 | .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | |
5135 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 5136 | .access = PL2_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
5137 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), |
5138 | .writefn = zcr_write, .raw_writefn = raw_write | |
5139 | }; | |
5140 | ||
5141 | static const ARMCPRegInfo zcr_no_el2_reginfo = { | |
5142 | .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | |
5143 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 5144 | .access = PL2_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
5145 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore |
5146 | }; | |
5147 | ||
5148 | static const ARMCPRegInfo zcr_el3_reginfo = { | |
5149 | .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | |
5150 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 5151 | .access = PL3_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
5152 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), |
5153 | .writefn = zcr_write, .raw_writefn = raw_write | |
5154 | }; | |
5155 | ||
9ee98ce8 PM |
5156 | void hw_watchpoint_update(ARMCPU *cpu, int n) |
5157 | { | |
5158 | CPUARMState *env = &cpu->env; | |
5159 | vaddr len = 0; | |
5160 | vaddr wvr = env->cp15.dbgwvr[n]; | |
5161 | uint64_t wcr = env->cp15.dbgwcr[n]; | |
5162 | int mask; | |
5163 | int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; | |
5164 | ||
5165 | if (env->cpu_watchpoint[n]) { | |
5166 | cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); | |
5167 | env->cpu_watchpoint[n] = NULL; | |
5168 | } | |
5169 | ||
5170 | if (!extract64(wcr, 0, 1)) { | |
5171 | /* E bit clear : watchpoint disabled */ | |
5172 | return; | |
5173 | } | |
5174 | ||
5175 | switch (extract64(wcr, 3, 2)) { | |
5176 | case 0: | |
5177 | /* LSC 00 is reserved and must behave as if the wp is disabled */ | |
5178 | return; | |
5179 | case 1: | |
5180 | flags |= BP_MEM_READ; | |
5181 | break; | |
5182 | case 2: | |
5183 | flags |= BP_MEM_WRITE; | |
5184 | break; | |
5185 | case 3: | |
5186 | flags |= BP_MEM_ACCESS; | |
5187 | break; | |
5188 | } | |
5189 | ||
5190 | /* Attempts to use both MASK and BAS fields simultaneously are | |
5191 | * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, | |
5192 | * thus generating a watchpoint for every byte in the masked region. | |
5193 | */ | |
5194 | mask = extract64(wcr, 24, 4); | |
5195 | if (mask == 1 || mask == 2) { | |
5196 | /* Reserved values of MASK; we must act as if the mask value was | |
5197 | * some non-reserved value, or as if the watchpoint were disabled. | |
5198 | * We choose the latter. | |
5199 | */ | |
5200 | return; | |
5201 | } else if (mask) { | |
5202 | /* Watchpoint covers an aligned area up to 2GB in size */ | |
5203 | len = 1ULL << mask; | |
5204 | /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE | |
5205 | * whether the watchpoint fires when the unmasked bits match; we opt | |
5206 | * to generate the exceptions. | |
5207 | */ | |
5208 | wvr &= ~(len - 1); | |
5209 | } else { | |
5210 | /* Watchpoint covers bytes defined by the byte address select bits */ | |
5211 | int bas = extract64(wcr, 5, 8); | |
5212 | int basstart; | |
5213 | ||
5214 | if (bas == 0) { | |
5215 | /* This must act as if the watchpoint is disabled */ | |
5216 | return; | |
5217 | } | |
5218 | ||
5219 | if (extract64(wvr, 2, 1)) { | |
5220 | /* Deprecated case of an only 4-aligned address. BAS[7:4] are | |
5221 | * ignored, and BAS[3:0] define which bytes to watch. | |
5222 | */ | |
5223 | bas &= 0xf; | |
5224 | } | |
5225 | /* The BAS bits are supposed to be programmed to indicate a contiguous | |
5226 | * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether | |
5227 | * we fire for each byte in the word/doubleword addressed by the WVR. | |
5228 | * We choose to ignore any non-zero bits after the first range of 1s. | |
5229 | */ | |
5230 | basstart = ctz32(bas); | |
5231 | len = cto32(bas >> basstart); | |
5232 | wvr += basstart; | |
5233 | } | |
5234 | ||
5235 | cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, | |
5236 | &env->cpu_watchpoint[n]); | |
5237 | } | |
5238 | ||
5239 | void hw_watchpoint_update_all(ARMCPU *cpu) | |
5240 | { | |
5241 | int i; | |
5242 | CPUARMState *env = &cpu->env; | |
5243 | ||
5244 | /* Completely clear out existing QEMU watchpoints and our array, to | |
5245 | * avoid possible stale entries following migration load. | |
5246 | */ | |
5247 | cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); | |
5248 | memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); | |
5249 | ||
5250 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { | |
5251 | hw_watchpoint_update(cpu, i); | |
5252 | } | |
5253 | } | |
5254 | ||
5255 | static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5256 | uint64_t value) | |
5257 | { | |
5258 | ARMCPU *cpu = arm_env_get_cpu(env); | |
5259 | int i = ri->crm; | |
5260 | ||
5261 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, the | |
5262 | * register reads and behaves as if values written are sign extended. | |
5263 | * Bits [1:0] are RES0. | |
5264 | */ | |
5265 | value = sextract64(value, 0, 49) & ~3ULL; | |
5266 | ||
5267 | raw_write(env, ri, value); | |
5268 | hw_watchpoint_update(cpu, i); | |
5269 | } | |
5270 | ||
5271 | static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5272 | uint64_t value) | |
5273 | { | |
5274 | ARMCPU *cpu = arm_env_get_cpu(env); | |
5275 | int i = ri->crm; | |
5276 | ||
5277 | raw_write(env, ri, value); | |
5278 | hw_watchpoint_update(cpu, i); | |
5279 | } | |
5280 | ||
46747d15 PM |
5281 | void hw_breakpoint_update(ARMCPU *cpu, int n) |
5282 | { | |
5283 | CPUARMState *env = &cpu->env; | |
5284 | uint64_t bvr = env->cp15.dbgbvr[n]; | |
5285 | uint64_t bcr = env->cp15.dbgbcr[n]; | |
5286 | vaddr addr; | |
5287 | int bt; | |
5288 | int flags = BP_CPU; | |
5289 | ||
5290 | if (env->cpu_breakpoint[n]) { | |
5291 | cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); | |
5292 | env->cpu_breakpoint[n] = NULL; | |
5293 | } | |
5294 | ||
5295 | if (!extract64(bcr, 0, 1)) { | |
5296 | /* E bit clear : watchpoint disabled */ | |
5297 | return; | |
5298 | } | |
5299 | ||
5300 | bt = extract64(bcr, 20, 4); | |
5301 | ||
5302 | switch (bt) { | |
5303 | case 4: /* unlinked address mismatch (reserved if AArch64) */ | |
5304 | case 5: /* linked address mismatch (reserved if AArch64) */ | |
5305 | qemu_log_mask(LOG_UNIMP, | |
0221c8fd | 5306 | "arm: address mismatch breakpoint types not implemented\n"); |
46747d15 PM |
5307 | return; |
5308 | case 0: /* unlinked address match */ | |
5309 | case 1: /* linked address match */ | |
5310 | { | |
5311 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, | |
5312 | * we behave as if the register was sign extended. Bits [1:0] are | |
5313 | * RES0. The BAS field is used to allow setting breakpoints on 16 | |
5314 | * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether | |
5315 | * a bp will fire if the addresses covered by the bp and the addresses | |
5316 | * covered by the insn overlap but the insn doesn't start at the | |
5317 | * start of the bp address range. We choose to require the insn and | |
5318 | * the bp to have the same address. The constraints on writing to | |
5319 | * BAS enforced in dbgbcr_write mean we have only four cases: | |
5320 | * 0b0000 => no breakpoint | |
5321 | * 0b0011 => breakpoint on addr | |
5322 | * 0b1100 => breakpoint on addr + 2 | |
5323 | * 0b1111 => breakpoint on addr | |
5324 | * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). | |
5325 | */ | |
5326 | int bas = extract64(bcr, 5, 4); | |
5327 | addr = sextract64(bvr, 0, 49) & ~3ULL; | |
5328 | if (bas == 0) { | |
5329 | return; | |
5330 | } | |
5331 | if (bas == 0xc) { | |
5332 | addr += 2; | |
5333 | } | |
5334 | break; | |
5335 | } | |
5336 | case 2: /* unlinked context ID match */ | |
5337 | case 8: /* unlinked VMID match (reserved if no EL2) */ | |
5338 | case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ | |
5339 | qemu_log_mask(LOG_UNIMP, | |
0221c8fd | 5340 | "arm: unlinked context breakpoint types not implemented\n"); |
46747d15 PM |
5341 | return; |
5342 | case 9: /* linked VMID match (reserved if no EL2) */ | |
5343 | case 11: /* linked context ID and VMID match (reserved if no EL2) */ | |
5344 | case 3: /* linked context ID match */ | |
5345 | default: | |
5346 | /* We must generate no events for Linked context matches (unless | |
5347 | * they are linked to by some other bp/wp, which is handled in | |
5348 | * updates for the linking bp/wp). We choose to also generate no events | |
5349 | * for reserved values. | |
5350 | */ | |
5351 | return; | |
5352 | } | |
5353 | ||
5354 | cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); | |
5355 | } | |
5356 | ||
5357 | void hw_breakpoint_update_all(ARMCPU *cpu) | |
5358 | { | |
5359 | int i; | |
5360 | CPUARMState *env = &cpu->env; | |
5361 | ||
5362 | /* Completely clear out existing QEMU breakpoints and our array, to | |
5363 | * avoid possible stale entries following migration load. | |
5364 | */ | |
5365 | cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); | |
5366 | memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); | |
5367 | ||
5368 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { | |
5369 | hw_breakpoint_update(cpu, i); | |
5370 | } | |
5371 | } | |
5372 | ||
5373 | static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5374 | uint64_t value) | |
5375 | { | |
5376 | ARMCPU *cpu = arm_env_get_cpu(env); | |
5377 | int i = ri->crm; | |
5378 | ||
5379 | raw_write(env, ri, value); | |
5380 | hw_breakpoint_update(cpu, i); | |
5381 | } | |
5382 | ||
5383 | static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5384 | uint64_t value) | |
5385 | { | |
5386 | ARMCPU *cpu = arm_env_get_cpu(env); | |
5387 | int i = ri->crm; | |
5388 | ||
5389 | /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only | |
5390 | * copy of BAS[0]. | |
5391 | */ | |
5392 | value = deposit64(value, 6, 1, extract64(value, 5, 1)); | |
5393 | value = deposit64(value, 8, 1, extract64(value, 7, 1)); | |
5394 | ||
5395 | raw_write(env, ri, value); | |
5396 | hw_breakpoint_update(cpu, i); | |
5397 | } | |
5398 | ||
50300698 | 5399 | static void define_debug_regs(ARMCPU *cpu) |
0b45451e | 5400 | { |
50300698 PM |
5401 | /* Define v7 and v8 architectural debug registers. |
5402 | * These are just dummy implementations for now. | |
0b45451e PM |
5403 | */ |
5404 | int i; | |
3ff6fc91 | 5405 | int wrps, brps, ctx_cmps; |
48eb3ae6 PM |
5406 | ARMCPRegInfo dbgdidr = { |
5407 | .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
d6c8cf81 PM |
5408 | .access = PL0_R, .accessfn = access_tda, |
5409 | .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr, | |
48eb3ae6 PM |
5410 | }; |
5411 | ||
3ff6fc91 | 5412 | /* Note that all these register fields hold "number of Xs minus 1". */ |
48eb3ae6 PM |
5413 | brps = extract32(cpu->dbgdidr, 24, 4); |
5414 | wrps = extract32(cpu->dbgdidr, 28, 4); | |
3ff6fc91 PM |
5415 | ctx_cmps = extract32(cpu->dbgdidr, 20, 4); |
5416 | ||
5417 | assert(ctx_cmps <= brps); | |
48eb3ae6 PM |
5418 | |
5419 | /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties | |
5420 | * of the debug registers such as number of breakpoints; | |
5421 | * check that if they both exist then they agree. | |
5422 | */ | |
5423 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
5424 | assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps); | |
5425 | assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps); | |
3ff6fc91 | 5426 | assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps); |
48eb3ae6 | 5427 | } |
0b45451e | 5428 | |
48eb3ae6 | 5429 | define_one_arm_cp_reg(cpu, &dbgdidr); |
50300698 PM |
5430 | define_arm_cp_regs(cpu, debug_cp_reginfo); |
5431 | ||
5432 | if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { | |
5433 | define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); | |
5434 | } | |
5435 | ||
48eb3ae6 | 5436 | for (i = 0; i < brps + 1; i++) { |
0b45451e | 5437 | ARMCPRegInfo dbgregs[] = { |
10aae104 PM |
5438 | { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH, |
5439 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, | |
d6c8cf81 | 5440 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
5441 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), |
5442 | .writefn = dbgbvr_write, .raw_writefn = raw_write | |
5443 | }, | |
10aae104 PM |
5444 | { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH, |
5445 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, | |
d6c8cf81 | 5446 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
5447 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), |
5448 | .writefn = dbgbcr_write, .raw_writefn = raw_write | |
5449 | }, | |
48eb3ae6 PM |
5450 | REGINFO_SENTINEL |
5451 | }; | |
5452 | define_arm_cp_regs(cpu, dbgregs); | |
5453 | } | |
5454 | ||
5455 | for (i = 0; i < wrps + 1; i++) { | |
5456 | ARMCPRegInfo dbgregs[] = { | |
10aae104 PM |
5457 | { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH, |
5458 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, | |
d6c8cf81 | 5459 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
5460 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), |
5461 | .writefn = dbgwvr_write, .raw_writefn = raw_write | |
5462 | }, | |
10aae104 PM |
5463 | { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH, |
5464 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, | |
d6c8cf81 | 5465 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
5466 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), |
5467 | .writefn = dbgwcr_write, .raw_writefn = raw_write | |
5468 | }, | |
5469 | REGINFO_SENTINEL | |
0b45451e PM |
5470 | }; |
5471 | define_arm_cp_regs(cpu, dbgregs); | |
5472 | } | |
5473 | } | |
5474 | ||
96a8b92e PM |
5475 | /* We don't know until after realize whether there's a GICv3 |
5476 | * attached, and that is what registers the gicv3 sysregs. | |
5477 | * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1 | |
5478 | * at runtime. | |
5479 | */ | |
5480 | static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5481 | { | |
5482 | ARMCPU *cpu = arm_env_get_cpu(env); | |
5483 | uint64_t pfr1 = cpu->id_pfr1; | |
5484 | ||
5485 | if (env->gicv3state) { | |
5486 | pfr1 |= 1 << 28; | |
5487 | } | |
5488 | return pfr1; | |
5489 | } | |
5490 | ||
5491 | static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5492 | { | |
5493 | ARMCPU *cpu = arm_env_get_cpu(env); | |
47576b94 | 5494 | uint64_t pfr0 = cpu->isar.id_aa64pfr0; |
96a8b92e PM |
5495 | |
5496 | if (env->gicv3state) { | |
5497 | pfr0 |= 1 << 24; | |
5498 | } | |
5499 | return pfr0; | |
5500 | } | |
5501 | ||
2d7137c1 RH |
5502 | /* Shared logic between LORID and the rest of the LOR* registers. |
5503 | * Secure state has already been delt with. | |
5504 | */ | |
5505 | static CPAccessResult access_lor_ns(CPUARMState *env) | |
5506 | { | |
5507 | int el = arm_current_el(env); | |
5508 | ||
5509 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) { | |
5510 | return CP_ACCESS_TRAP_EL2; | |
5511 | } | |
5512 | if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { | |
5513 | return CP_ACCESS_TRAP_EL3; | |
5514 | } | |
5515 | return CP_ACCESS_OK; | |
5516 | } | |
5517 | ||
5518 | static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri, | |
5519 | bool isread) | |
5520 | { | |
5521 | if (arm_is_secure_below_el3(env)) { | |
5522 | /* Access ok in secure mode. */ | |
5523 | return CP_ACCESS_OK; | |
5524 | } | |
5525 | return access_lor_ns(env); | |
5526 | } | |
5527 | ||
5528 | static CPAccessResult access_lor_other(CPUARMState *env, | |
5529 | const ARMCPRegInfo *ri, bool isread) | |
5530 | { | |
5531 | if (arm_is_secure_below_el3(env)) { | |
5532 | /* Access denied in secure mode. */ | |
5533 | return CP_ACCESS_TRAP; | |
5534 | } | |
5535 | return access_lor_ns(env); | |
5536 | } | |
5537 | ||
967aa94f RH |
5538 | #ifdef TARGET_AARCH64 |
5539 | static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, | |
5540 | bool isread) | |
5541 | { | |
5542 | int el = arm_current_el(env); | |
5543 | ||
5544 | if (el < 2 && | |
5545 | arm_feature(env, ARM_FEATURE_EL2) && | |
5546 | !(arm_hcr_el2_eff(env) & HCR_APK)) { | |
5547 | return CP_ACCESS_TRAP_EL2; | |
5548 | } | |
5549 | if (el < 3 && | |
5550 | arm_feature(env, ARM_FEATURE_EL3) && | |
5551 | !(env->cp15.scr_el3 & SCR_APK)) { | |
5552 | return CP_ACCESS_TRAP_EL3; | |
5553 | } | |
5554 | return CP_ACCESS_OK; | |
5555 | } | |
5556 | ||
5557 | static const ARMCPRegInfo pauth_reginfo[] = { | |
5558 | { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64, | |
5559 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0, | |
5560 | .access = PL1_RW, .accessfn = access_pauth, | |
5561 | .fieldoffset = offsetof(CPUARMState, apda_key.lo) }, | |
5562 | { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64, | |
5563 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1, | |
5564 | .access = PL1_RW, .accessfn = access_pauth, | |
5565 | .fieldoffset = offsetof(CPUARMState, apda_key.hi) }, | |
5566 | { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64, | |
5567 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2, | |
5568 | .access = PL1_RW, .accessfn = access_pauth, | |
5569 | .fieldoffset = offsetof(CPUARMState, apdb_key.lo) }, | |
5570 | { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64, | |
5571 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3, | |
5572 | .access = PL1_RW, .accessfn = access_pauth, | |
5573 | .fieldoffset = offsetof(CPUARMState, apdb_key.hi) }, | |
5574 | { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64, | |
5575 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0, | |
5576 | .access = PL1_RW, .accessfn = access_pauth, | |
5577 | .fieldoffset = offsetof(CPUARMState, apga_key.lo) }, | |
5578 | { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64, | |
5579 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1, | |
5580 | .access = PL1_RW, .accessfn = access_pauth, | |
5581 | .fieldoffset = offsetof(CPUARMState, apga_key.hi) }, | |
5582 | { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64, | |
5583 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0, | |
5584 | .access = PL1_RW, .accessfn = access_pauth, | |
5585 | .fieldoffset = offsetof(CPUARMState, apia_key.lo) }, | |
5586 | { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64, | |
5587 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1, | |
5588 | .access = PL1_RW, .accessfn = access_pauth, | |
5589 | .fieldoffset = offsetof(CPUARMState, apia_key.hi) }, | |
5590 | { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64, | |
5591 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2, | |
5592 | .access = PL1_RW, .accessfn = access_pauth, | |
5593 | .fieldoffset = offsetof(CPUARMState, apib_key.lo) }, | |
5594 | { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64, | |
5595 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3, | |
5596 | .access = PL1_RW, .accessfn = access_pauth, | |
5597 | .fieldoffset = offsetof(CPUARMState, apib_key.hi) }, | |
5598 | REGINFO_SENTINEL | |
5599 | }; | |
5600 | #endif | |
5601 | ||
2ceb98c0 PM |
5602 | void register_cp_regs_for_features(ARMCPU *cpu) |
5603 | { | |
5604 | /* Register all the coprocessor registers based on feature bits */ | |
5605 | CPUARMState *env = &cpu->env; | |
5606 | if (arm_feature(env, ARM_FEATURE_M)) { | |
5607 | /* M profile has no coprocessor registers */ | |
5608 | return; | |
5609 | } | |
5610 | ||
e9aa6c21 | 5611 | define_arm_cp_regs(cpu, cp_reginfo); |
9449fdf6 PM |
5612 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
5613 | /* Must go early as it is full of wildcards that may be | |
5614 | * overridden by later definitions. | |
5615 | */ | |
5616 | define_arm_cp_regs(cpu, not_v8_cp_reginfo); | |
5617 | } | |
5618 | ||
7d57f408 | 5619 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8515a092 PM |
5620 | /* The ID registers all have impdef reset values */ |
5621 | ARMCPRegInfo v6_idregs[] = { | |
0ff644a7 PM |
5622 | { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, |
5623 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
5624 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 5625 | .resetvalue = cpu->id_pfr0 }, |
96a8b92e PM |
5626 | /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know |
5627 | * the value of the GIC field until after we define these regs. | |
5628 | */ | |
0ff644a7 PM |
5629 | { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, |
5630 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | |
96a8b92e PM |
5631 | .access = PL1_R, .type = ARM_CP_NO_RAW, |
5632 | .readfn = id_pfr1_read, | |
5633 | .writefn = arm_cp_write_ignore }, | |
0ff644a7 PM |
5634 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, |
5635 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | |
5636 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 5637 | .resetvalue = cpu->id_dfr0 }, |
0ff644a7 PM |
5638 | { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, |
5639 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, | |
5640 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 5641 | .resetvalue = cpu->id_afr0 }, |
0ff644a7 PM |
5642 | { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, |
5643 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, | |
5644 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 5645 | .resetvalue = cpu->id_mmfr0 }, |
0ff644a7 PM |
5646 | { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, |
5647 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, | |
5648 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 5649 | .resetvalue = cpu->id_mmfr1 }, |
0ff644a7 PM |
5650 | { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, |
5651 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, | |
5652 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 5653 | .resetvalue = cpu->id_mmfr2 }, |
0ff644a7 PM |
5654 | { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, |
5655 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, | |
5656 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 5657 | .resetvalue = cpu->id_mmfr3 }, |
0ff644a7 PM |
5658 | { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, |
5659 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
5660 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 5661 | .resetvalue = cpu->isar.id_isar0 }, |
0ff644a7 PM |
5662 | { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, |
5663 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, | |
5664 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 5665 | .resetvalue = cpu->isar.id_isar1 }, |
0ff644a7 PM |
5666 | { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, |
5667 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
5668 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 5669 | .resetvalue = cpu->isar.id_isar2 }, |
0ff644a7 PM |
5670 | { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, |
5671 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, | |
5672 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 5673 | .resetvalue = cpu->isar.id_isar3 }, |
0ff644a7 PM |
5674 | { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, |
5675 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, | |
5676 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 5677 | .resetvalue = cpu->isar.id_isar4 }, |
0ff644a7 PM |
5678 | { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, |
5679 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, | |
5680 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 5681 | .resetvalue = cpu->isar.id_isar5 }, |
e20d84c1 PM |
5682 | { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, |
5683 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, | |
5684 | .access = PL1_R, .type = ARM_CP_CONST, | |
5685 | .resetvalue = cpu->id_mmfr4 }, | |
802abf40 | 5686 | { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
5687 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, |
5688 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 5689 | .resetvalue = cpu->isar.id_isar6 }, |
8515a092 PM |
5690 | REGINFO_SENTINEL |
5691 | }; | |
5692 | define_arm_cp_regs(cpu, v6_idregs); | |
7d57f408 PM |
5693 | define_arm_cp_regs(cpu, v6_cp_reginfo); |
5694 | } else { | |
5695 | define_arm_cp_regs(cpu, not_v6_cp_reginfo); | |
5696 | } | |
4d31c596 PM |
5697 | if (arm_feature(env, ARM_FEATURE_V6K)) { |
5698 | define_arm_cp_regs(cpu, v6k_cp_reginfo); | |
5699 | } | |
5e5cf9e3 | 5700 | if (arm_feature(env, ARM_FEATURE_V7MP) && |
452a0955 | 5701 | !arm_feature(env, ARM_FEATURE_PMSA)) { |
995939a6 PM |
5702 | define_arm_cp_regs(cpu, v7mp_cp_reginfo); |
5703 | } | |
327dd510 AL |
5704 | if (arm_feature(env, ARM_FEATURE_V7VE)) { |
5705 | define_arm_cp_regs(cpu, pmovsset_cp_reginfo); | |
5706 | } | |
e9aa6c21 | 5707 | if (arm_feature(env, ARM_FEATURE_V7)) { |
200ac0ef | 5708 | /* v7 performance monitor control register: same implementor |
ac689a2e AL |
5709 | * field as main ID register, and we implement four counters in |
5710 | * addition to the cycle count register. | |
200ac0ef | 5711 | */ |
ac689a2e | 5712 | unsigned int i, pmcrn = 4; |
200ac0ef PM |
5713 | ARMCPRegInfo pmcr = { |
5714 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | |
8521466b | 5715 | .access = PL0_RW, |
7a0e58fa | 5716 | .type = ARM_CP_IO | ARM_CP_ALIAS, |
8521466b | 5717 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), |
fcd25206 PM |
5718 | .accessfn = pmreg_access, .writefn = pmcr_write, |
5719 | .raw_writefn = raw_write, | |
200ac0ef | 5720 | }; |
8521466b AF |
5721 | ARMCPRegInfo pmcr64 = { |
5722 | .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, | |
5723 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, | |
5724 | .access = PL0_RW, .accessfn = pmreg_access, | |
5725 | .type = ARM_CP_IO, | |
5726 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), | |
ac689a2e | 5727 | .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT), |
8521466b AF |
5728 | .writefn = pmcr_write, .raw_writefn = raw_write, |
5729 | }; | |
7c2cb42b | 5730 | define_one_arm_cp_reg(cpu, &pmcr); |
8521466b | 5731 | define_one_arm_cp_reg(cpu, &pmcr64); |
5ecdd3e4 AL |
5732 | for (i = 0; i < pmcrn; i++) { |
5733 | char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i); | |
5734 | char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i); | |
5735 | char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i); | |
5736 | char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i); | |
5737 | ARMCPRegInfo pmev_regs[] = { | |
5738 | { .name = pmevcntr_name, .cp = 15, .crn = 15, | |
5739 | .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, | |
5740 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
5741 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, | |
5742 | .accessfn = pmreg_access }, | |
5743 | { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64, | |
5744 | .opc0 = 3, .opc1 = 3, .crn = 15, .crm = 8 | (3 & (i >> 3)), | |
5745 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, | |
5746 | .type = ARM_CP_IO, | |
5747 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, | |
5748 | .raw_readfn = pmevcntr_rawread, | |
5749 | .raw_writefn = pmevcntr_rawwrite }, | |
5750 | { .name = pmevtyper_name, .cp = 15, .crn = 15, | |
5751 | .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, | |
5752 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
5753 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | |
5754 | .accessfn = pmreg_access }, | |
5755 | { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64, | |
5756 | .opc0 = 3, .opc1 = 3, .crn = 15, .crm = 12 | (3 & (i >> 3)), | |
5757 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, | |
5758 | .type = ARM_CP_IO, | |
5759 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | |
5760 | .raw_writefn = pmevtyper_rawwrite }, | |
5761 | REGINFO_SENTINEL | |
5762 | }; | |
5763 | define_arm_cp_regs(cpu, pmev_regs); | |
5764 | g_free(pmevcntr_name); | |
5765 | g_free(pmevcntr_el0_name); | |
5766 | g_free(pmevtyper_name); | |
5767 | g_free(pmevtyper_el0_name); | |
5768 | } | |
776d4e5c | 5769 | ARMCPRegInfo clidr = { |
7da845b0 PM |
5770 | .name = "CLIDR", .state = ARM_CP_STATE_BOTH, |
5771 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | |
776d4e5c PM |
5772 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr |
5773 | }; | |
776d4e5c | 5774 | define_one_arm_cp_reg(cpu, &clidr); |
e9aa6c21 | 5775 | define_arm_cp_regs(cpu, v7_cp_reginfo); |
50300698 | 5776 | define_debug_regs(cpu); |
7d57f408 PM |
5777 | } else { |
5778 | define_arm_cp_regs(cpu, not_v7_cp_reginfo); | |
e9aa6c21 | 5779 | } |
cad86737 AL |
5780 | if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 && |
5781 | FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) { | |
5782 | ARMCPRegInfo v81_pmu_regs[] = { | |
5783 | { .name = "PMCEID2", .state = ARM_CP_STATE_AA32, | |
5784 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4, | |
5785 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
5786 | .resetvalue = extract64(cpu->pmceid0, 32, 32) }, | |
5787 | { .name = "PMCEID3", .state = ARM_CP_STATE_AA32, | |
5788 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5, | |
5789 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
5790 | .resetvalue = extract64(cpu->pmceid1, 32, 32) }, | |
5791 | REGINFO_SENTINEL | |
5792 | }; | |
5793 | define_arm_cp_regs(cpu, v81_pmu_regs); | |
5794 | } | |
b0d2b7d0 | 5795 | if (arm_feature(env, ARM_FEATURE_V8)) { |
e20d84c1 PM |
5796 | /* AArch64 ID registers, which all have impdef reset values. |
5797 | * Note that within the ID register ranges the unused slots | |
5798 | * must all RAZ, not UNDEF; future architecture versions may | |
5799 | * define new registers here. | |
5800 | */ | |
e60cef86 | 5801 | ARMCPRegInfo v8_idregs[] = { |
96a8b92e PM |
5802 | /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't |
5803 | * know the right value for the GIC field until after we | |
5804 | * define these regs. | |
5805 | */ | |
e60cef86 PM |
5806 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, |
5807 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | |
96a8b92e PM |
5808 | .access = PL1_R, .type = ARM_CP_NO_RAW, |
5809 | .readfn = id_aa64pfr0_read, | |
5810 | .writefn = arm_cp_write_ignore }, | |
e60cef86 PM |
5811 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, |
5812 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | |
5813 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 5814 | .resetvalue = cpu->isar.id_aa64pfr1}, |
e20d84c1 PM |
5815 | { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
5816 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, | |
5817 | .access = PL1_R, .type = ARM_CP_CONST, | |
5818 | .resetvalue = 0 }, | |
5819 | { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5820 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, | |
5821 | .access = PL1_R, .type = ARM_CP_CONST, | |
5822 | .resetvalue = 0 }, | |
9516d772 | 5823 | { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
5824 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, |
5825 | .access = PL1_R, .type = ARM_CP_CONST, | |
9516d772 | 5826 | /* At present, only SVEver == 0 is defined anyway. */ |
e20d84c1 PM |
5827 | .resetvalue = 0 }, |
5828 | { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5829 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, | |
5830 | .access = PL1_R, .type = ARM_CP_CONST, | |
5831 | .resetvalue = 0 }, | |
5832 | { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5833 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, | |
5834 | .access = PL1_R, .type = ARM_CP_CONST, | |
5835 | .resetvalue = 0 }, | |
5836 | { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5837 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, | |
5838 | .access = PL1_R, .type = ARM_CP_CONST, | |
5839 | .resetvalue = 0 }, | |
e60cef86 PM |
5840 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, |
5841 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | |
5842 | .access = PL1_R, .type = ARM_CP_CONST, | |
d6f02ce3 | 5843 | .resetvalue = cpu->id_aa64dfr0 }, |
e60cef86 PM |
5844 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, |
5845 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | |
5846 | .access = PL1_R, .type = ARM_CP_CONST, | |
5847 | .resetvalue = cpu->id_aa64dfr1 }, | |
e20d84c1 PM |
5848 | { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
5849 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, | |
5850 | .access = PL1_R, .type = ARM_CP_CONST, | |
5851 | .resetvalue = 0 }, | |
5852 | { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5853 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, | |
5854 | .access = PL1_R, .type = ARM_CP_CONST, | |
5855 | .resetvalue = 0 }, | |
e60cef86 PM |
5856 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, |
5857 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | |
5858 | .access = PL1_R, .type = ARM_CP_CONST, | |
5859 | .resetvalue = cpu->id_aa64afr0 }, | |
5860 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | |
5861 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | |
5862 | .access = PL1_R, .type = ARM_CP_CONST, | |
5863 | .resetvalue = cpu->id_aa64afr1 }, | |
e20d84c1 PM |
5864 | { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
5865 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, | |
5866 | .access = PL1_R, .type = ARM_CP_CONST, | |
5867 | .resetvalue = 0 }, | |
5868 | { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5869 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, | |
5870 | .access = PL1_R, .type = ARM_CP_CONST, | |
5871 | .resetvalue = 0 }, | |
e60cef86 PM |
5872 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, |
5873 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | |
5874 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 5875 | .resetvalue = cpu->isar.id_aa64isar0 }, |
e60cef86 PM |
5876 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, |
5877 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | |
5878 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 5879 | .resetvalue = cpu->isar.id_aa64isar1 }, |
e20d84c1 PM |
5880 | { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
5881 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, | |
5882 | .access = PL1_R, .type = ARM_CP_CONST, | |
5883 | .resetvalue = 0 }, | |
5884 | { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5885 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, | |
5886 | .access = PL1_R, .type = ARM_CP_CONST, | |
5887 | .resetvalue = 0 }, | |
5888 | { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5889 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, | |
5890 | .access = PL1_R, .type = ARM_CP_CONST, | |
5891 | .resetvalue = 0 }, | |
5892 | { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5893 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, | |
5894 | .access = PL1_R, .type = ARM_CP_CONST, | |
5895 | .resetvalue = 0 }, | |
5896 | { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5897 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, | |
5898 | .access = PL1_R, .type = ARM_CP_CONST, | |
5899 | .resetvalue = 0 }, | |
5900 | { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5901 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, | |
5902 | .access = PL1_R, .type = ARM_CP_CONST, | |
5903 | .resetvalue = 0 }, | |
e60cef86 PM |
5904 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, |
5905 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
5906 | .access = PL1_R, .type = ARM_CP_CONST, | |
3dc91ddb | 5907 | .resetvalue = cpu->isar.id_aa64mmfr0 }, |
e60cef86 PM |
5908 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, |
5909 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | |
5910 | .access = PL1_R, .type = ARM_CP_CONST, | |
3dc91ddb | 5911 | .resetvalue = cpu->isar.id_aa64mmfr1 }, |
e20d84c1 PM |
5912 | { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
5913 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, | |
5914 | .access = PL1_R, .type = ARM_CP_CONST, | |
5915 | .resetvalue = 0 }, | |
5916 | { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5917 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, | |
5918 | .access = PL1_R, .type = ARM_CP_CONST, | |
5919 | .resetvalue = 0 }, | |
5920 | { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5921 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, | |
5922 | .access = PL1_R, .type = ARM_CP_CONST, | |
5923 | .resetvalue = 0 }, | |
5924 | { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5925 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, | |
5926 | .access = PL1_R, .type = ARM_CP_CONST, | |
5927 | .resetvalue = 0 }, | |
5928 | { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5929 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, | |
5930 | .access = PL1_R, .type = ARM_CP_CONST, | |
5931 | .resetvalue = 0 }, | |
5932 | { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5933 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, | |
5934 | .access = PL1_R, .type = ARM_CP_CONST, | |
5935 | .resetvalue = 0 }, | |
a50c0f51 PM |
5936 | { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, |
5937 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
5938 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 5939 | .resetvalue = cpu->isar.mvfr0 }, |
a50c0f51 PM |
5940 | { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, |
5941 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
5942 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 5943 | .resetvalue = cpu->isar.mvfr1 }, |
a50c0f51 PM |
5944 | { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, |
5945 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
5946 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 5947 | .resetvalue = cpu->isar.mvfr2 }, |
e20d84c1 PM |
5948 | { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
5949 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, | |
5950 | .access = PL1_R, .type = ARM_CP_CONST, | |
5951 | .resetvalue = 0 }, | |
5952 | { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5953 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, | |
5954 | .access = PL1_R, .type = ARM_CP_CONST, | |
5955 | .resetvalue = 0 }, | |
5956 | { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5957 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, | |
5958 | .access = PL1_R, .type = ARM_CP_CONST, | |
5959 | .resetvalue = 0 }, | |
5960 | { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5961 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, | |
5962 | .access = PL1_R, .type = ARM_CP_CONST, | |
5963 | .resetvalue = 0 }, | |
5964 | { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
5965 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, | |
5966 | .access = PL1_R, .type = ARM_CP_CONST, | |
5967 | .resetvalue = 0 }, | |
4054bfa9 AF |
5968 | { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, |
5969 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, | |
5970 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
cad86737 | 5971 | .resetvalue = extract64(cpu->pmceid0, 0, 32) }, |
4054bfa9 AF |
5972 | { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, |
5973 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, | |
5974 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
5975 | .resetvalue = cpu->pmceid0 }, | |
5976 | { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, | |
5977 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, | |
5978 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
cad86737 | 5979 | .resetvalue = extract64(cpu->pmceid1, 0, 32) }, |
4054bfa9 AF |
5980 | { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, |
5981 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, | |
5982 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
5983 | .resetvalue = cpu->pmceid1 }, | |
e60cef86 PM |
5984 | REGINFO_SENTINEL |
5985 | }; | |
be8e8128 GB |
5986 | /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ |
5987 | if (!arm_feature(env, ARM_FEATURE_EL3) && | |
5988 | !arm_feature(env, ARM_FEATURE_EL2)) { | |
5989 | ARMCPRegInfo rvbar = { | |
5990 | .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, | |
5991 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, | |
5992 | .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar | |
5993 | }; | |
5994 | define_one_arm_cp_reg(cpu, &rvbar); | |
5995 | } | |
e60cef86 | 5996 | define_arm_cp_regs(cpu, v8_idregs); |
b0d2b7d0 PM |
5997 | define_arm_cp_regs(cpu, v8_cp_reginfo); |
5998 | } | |
3b685ba7 | 5999 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
f0d574d6 | 6000 | uint64_t vmpidr_def = mpidr_read_val(env); |
731de9e6 EI |
6001 | ARMCPRegInfo vpidr_regs[] = { |
6002 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | |
6003 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
6004 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
36476562 PM |
6005 | .resetvalue = cpu->midr, .type = ARM_CP_ALIAS, |
6006 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) }, | |
731de9e6 EI |
6007 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, |
6008 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
6009 | .access = PL2_RW, .resetvalue = cpu->midr, | |
6010 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
f0d574d6 EI |
6011 | { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, |
6012 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
6013 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
36476562 PM |
6014 | .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS, |
6015 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) }, | |
f0d574d6 EI |
6016 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, |
6017 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
6018 | .access = PL2_RW, | |
6019 | .resetvalue = vmpidr_def, | |
6020 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | |
731de9e6 EI |
6021 | REGINFO_SENTINEL |
6022 | }; | |
6023 | define_arm_cp_regs(cpu, vpidr_regs); | |
4771cd01 | 6024 | define_arm_cp_regs(cpu, el2_cp_reginfo); |
ce4afed8 PM |
6025 | if (arm_feature(env, ARM_FEATURE_V8)) { |
6026 | define_arm_cp_regs(cpu, el2_v8_cp_reginfo); | |
6027 | } | |
be8e8128 GB |
6028 | /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ |
6029 | if (!arm_feature(env, ARM_FEATURE_EL3)) { | |
6030 | ARMCPRegInfo rvbar = { | |
6031 | .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, | |
6032 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, | |
6033 | .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar | |
6034 | }; | |
6035 | define_one_arm_cp_reg(cpu, &rvbar); | |
6036 | } | |
d42e3c26 EI |
6037 | } else { |
6038 | /* If EL2 is missing but higher ELs are enabled, we need to | |
6039 | * register the no_el2 reginfos. | |
6040 | */ | |
6041 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
f0d574d6 EI |
6042 | /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value |
6043 | * of MIDR_EL1 and MPIDR_EL1. | |
731de9e6 EI |
6044 | */ |
6045 | ARMCPRegInfo vpidr_regs[] = { | |
6046 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH, | |
6047 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
6048 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
6049 | .type = ARM_CP_CONST, .resetvalue = cpu->midr, | |
6050 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
f0d574d6 EI |
6051 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
6052 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
6053 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
6054 | .type = ARM_CP_NO_RAW, | |
6055 | .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, | |
731de9e6 EI |
6056 | REGINFO_SENTINEL |
6057 | }; | |
6058 | define_arm_cp_regs(cpu, vpidr_regs); | |
4771cd01 | 6059 | define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); |
ce4afed8 PM |
6060 | if (arm_feature(env, ARM_FEATURE_V8)) { |
6061 | define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo); | |
6062 | } | |
d42e3c26 | 6063 | } |
3b685ba7 | 6064 | } |
81547d66 | 6065 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0f1a3b24 | 6066 | define_arm_cp_regs(cpu, el3_cp_reginfo); |
e24fdd23 PM |
6067 | ARMCPRegInfo el3_regs[] = { |
6068 | { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, | |
6069 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, | |
6070 | .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, | |
6071 | { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, | |
6072 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, | |
6073 | .access = PL3_RW, | |
6074 | .raw_writefn = raw_write, .writefn = sctlr_write, | |
6075 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), | |
6076 | .resetvalue = cpu->reset_sctlr }, | |
6077 | REGINFO_SENTINEL | |
be8e8128 | 6078 | }; |
e24fdd23 PM |
6079 | |
6080 | define_arm_cp_regs(cpu, el3_regs); | |
81547d66 | 6081 | } |
2f027fc5 PM |
6082 | /* The behaviour of NSACR is sufficiently various that we don't |
6083 | * try to describe it in a single reginfo: | |
6084 | * if EL3 is 64 bit, then trap to EL3 from S EL1, | |
6085 | * reads as constant 0xc00 from NS EL1 and NS EL2 | |
6086 | * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 | |
6087 | * if v7 without EL3, register doesn't exist | |
6088 | * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 | |
6089 | */ | |
6090 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
6091 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
6092 | ARMCPRegInfo nsacr = { | |
6093 | .name = "NSACR", .type = ARM_CP_CONST, | |
6094 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
6095 | .access = PL1_RW, .accessfn = nsacr_access, | |
6096 | .resetvalue = 0xc00 | |
6097 | }; | |
6098 | define_one_arm_cp_reg(cpu, &nsacr); | |
6099 | } else { | |
6100 | ARMCPRegInfo nsacr = { | |
6101 | .name = "NSACR", | |
6102 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
6103 | .access = PL3_RW | PL1_R, | |
6104 | .resetvalue = 0, | |
6105 | .fieldoffset = offsetof(CPUARMState, cp15.nsacr) | |
6106 | }; | |
6107 | define_one_arm_cp_reg(cpu, &nsacr); | |
6108 | } | |
6109 | } else { | |
6110 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
6111 | ARMCPRegInfo nsacr = { | |
6112 | .name = "NSACR", .type = ARM_CP_CONST, | |
6113 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
6114 | .access = PL1_R, | |
6115 | .resetvalue = 0xc00 | |
6116 | }; | |
6117 | define_one_arm_cp_reg(cpu, &nsacr); | |
6118 | } | |
6119 | } | |
6120 | ||
452a0955 | 6121 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
6cb0b013 PC |
6122 | if (arm_feature(env, ARM_FEATURE_V6)) { |
6123 | /* PMSAv6 not implemented */ | |
6124 | assert(arm_feature(env, ARM_FEATURE_V7)); | |
6125 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); | |
6126 | define_arm_cp_regs(cpu, pmsav7_cp_reginfo); | |
6127 | } else { | |
6128 | define_arm_cp_regs(cpu, pmsav5_cp_reginfo); | |
6129 | } | |
18032bec | 6130 | } else { |
8e5d75c9 | 6131 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); |
18032bec | 6132 | define_arm_cp_regs(cpu, vmsa_cp_reginfo); |
ab638a32 RH |
6133 | /* TTCBR2 is introduced with ARMv8.2-A32HPD. */ |
6134 | if (FIELD_EX32(cpu->id_mmfr4, ID_MMFR4, HPDS) != 0) { | |
6135 | define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); | |
6136 | } | |
18032bec | 6137 | } |
c326b979 PM |
6138 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
6139 | define_arm_cp_regs(cpu, t2ee_cp_reginfo); | |
6140 | } | |
6cc7a3ae PM |
6141 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
6142 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); | |
6143 | } | |
4a501606 PM |
6144 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
6145 | define_arm_cp_regs(cpu, vapa_cp_reginfo); | |
6146 | } | |
c4804214 PM |
6147 | if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { |
6148 | define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); | |
6149 | } | |
6150 | if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { | |
6151 | define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); | |
6152 | } | |
6153 | if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { | |
6154 | define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); | |
6155 | } | |
18032bec PM |
6156 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
6157 | define_arm_cp_regs(cpu, omap_cp_reginfo); | |
6158 | } | |
34f90529 PM |
6159 | if (arm_feature(env, ARM_FEATURE_STRONGARM)) { |
6160 | define_arm_cp_regs(cpu, strongarm_cp_reginfo); | |
6161 | } | |
1047b9d7 PM |
6162 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
6163 | define_arm_cp_regs(cpu, xscale_cp_reginfo); | |
6164 | } | |
6165 | if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { | |
6166 | define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); | |
6167 | } | |
7ac681cf PM |
6168 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
6169 | define_arm_cp_regs(cpu, lpae_cp_reginfo); | |
6170 | } | |
7884849c PM |
6171 | /* Slightly awkwardly, the OMAP and StrongARM cores need all of |
6172 | * cp15 crn=0 to be writes-ignored, whereas for other cores they should | |
6173 | * be read-only (ie write causes UNDEF exception). | |
6174 | */ | |
6175 | { | |
00a29f3d PM |
6176 | ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { |
6177 | /* Pre-v8 MIDR space. | |
6178 | * Note that the MIDR isn't a simple constant register because | |
7884849c PM |
6179 | * of the TI925 behaviour where writes to another register can |
6180 | * cause the MIDR value to change. | |
97ce8d61 PC |
6181 | * |
6182 | * Unimplemented registers in the c15 0 0 0 space default to | |
6183 | * MIDR. Define MIDR first as this entire space, then CTR, TCMTR | |
6184 | * and friends override accordingly. | |
7884849c PM |
6185 | */ |
6186 | { .name = "MIDR", | |
97ce8d61 | 6187 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, |
7884849c | 6188 | .access = PL1_R, .resetvalue = cpu->midr, |
d4e6df63 | 6189 | .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, |
731de9e6 | 6190 | .readfn = midr_read, |
97ce8d61 PC |
6191 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
6192 | .type = ARM_CP_OVERRIDE }, | |
7884849c PM |
6193 | /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ |
6194 | { .name = "DUMMY", | |
6195 | .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, | |
6196 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6197 | { .name = "DUMMY", | |
6198 | .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, | |
6199 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6200 | { .name = "DUMMY", | |
6201 | .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, | |
6202 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6203 | { .name = "DUMMY", | |
6204 | .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, | |
6205 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6206 | { .name = "DUMMY", | |
6207 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | |
6208 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6209 | REGINFO_SENTINEL | |
6210 | }; | |
00a29f3d | 6211 | ARMCPRegInfo id_v8_midr_cp_reginfo[] = { |
00a29f3d PM |
6212 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, |
6213 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, | |
731de9e6 EI |
6214 | .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, |
6215 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), | |
6216 | .readfn = midr_read }, | |
ac00c79f SF |
6217 | /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ |
6218 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
6219 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
6220 | .access = PL1_R, .resetvalue = cpu->midr }, | |
6221 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
6222 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, | |
6223 | .access = PL1_R, .resetvalue = cpu->midr }, | |
00a29f3d PM |
6224 | { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, |
6225 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, | |
13b72b2b | 6226 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, |
00a29f3d PM |
6227 | REGINFO_SENTINEL |
6228 | }; | |
6229 | ARMCPRegInfo id_cp_reginfo[] = { | |
6230 | /* These are common to v8 and pre-v8 */ | |
6231 | { .name = "CTR", | |
6232 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, | |
6233 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
6234 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, | |
6235 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, | |
6236 | .access = PL0_R, .accessfn = ctr_el0_access, | |
6237 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
6238 | /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ | |
6239 | { .name = "TCMTR", | |
6240 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, | |
6241 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
00a29f3d PM |
6242 | REGINFO_SENTINEL |
6243 | }; | |
8085ce63 PC |
6244 | /* TLBTR is specific to VMSA */ |
6245 | ARMCPRegInfo id_tlbtr_reginfo = { | |
6246 | .name = "TLBTR", | |
6247 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, | |
6248 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0, | |
6249 | }; | |
3281af81 PC |
6250 | /* MPUIR is specific to PMSA V6+ */ |
6251 | ARMCPRegInfo id_mpuir_reginfo = { | |
6252 | .name = "MPUIR", | |
6253 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
6254 | .access = PL1_R, .type = ARM_CP_CONST, | |
6255 | .resetvalue = cpu->pmsav7_dregion << 8 | |
6256 | }; | |
7884849c PM |
6257 | ARMCPRegInfo crn0_wi_reginfo = { |
6258 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, | |
6259 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | |
6260 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | |
6261 | }; | |
6262 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || | |
6263 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | |
6264 | ARMCPRegInfo *r; | |
6265 | /* Register the blanket "writes ignored" value first to cover the | |
a703eda1 PC |
6266 | * whole space. Then update the specific ID registers to allow write |
6267 | * access, so that they ignore writes rather than causing them to | |
6268 | * UNDEF. | |
7884849c PM |
6269 | */ |
6270 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | |
00a29f3d PM |
6271 | for (r = id_pre_v8_midr_cp_reginfo; |
6272 | r->type != ARM_CP_SENTINEL; r++) { | |
6273 | r->access = PL1_RW; | |
6274 | } | |
7884849c PM |
6275 | for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { |
6276 | r->access = PL1_RW; | |
7884849c | 6277 | } |
10006112 | 6278 | id_mpuir_reginfo.access = PL1_RW; |
3281af81 | 6279 | id_tlbtr_reginfo.access = PL1_RW; |
7884849c | 6280 | } |
00a29f3d PM |
6281 | if (arm_feature(env, ARM_FEATURE_V8)) { |
6282 | define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); | |
6283 | } else { | |
6284 | define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); | |
6285 | } | |
a703eda1 | 6286 | define_arm_cp_regs(cpu, id_cp_reginfo); |
452a0955 | 6287 | if (!arm_feature(env, ARM_FEATURE_PMSA)) { |
8085ce63 | 6288 | define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); |
3281af81 PC |
6289 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
6290 | define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); | |
8085ce63 | 6291 | } |
7884849c PM |
6292 | } |
6293 | ||
97ce8d61 PC |
6294 | if (arm_feature(env, ARM_FEATURE_MPIDR)) { |
6295 | define_arm_cp_regs(cpu, mpidr_cp_reginfo); | |
6296 | } | |
6297 | ||
2771db27 | 6298 | if (arm_feature(env, ARM_FEATURE_AUXCR)) { |
834a6c69 PM |
6299 | ARMCPRegInfo auxcr_reginfo[] = { |
6300 | { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, | |
6301 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, | |
6302 | .access = PL1_RW, .type = ARM_CP_CONST, | |
6303 | .resetvalue = cpu->reset_auxcr }, | |
6304 | { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, | |
6305 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, | |
6306 | .access = PL2_RW, .type = ARM_CP_CONST, | |
6307 | .resetvalue = 0 }, | |
6308 | { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, | |
6309 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, | |
6310 | .access = PL3_RW, .type = ARM_CP_CONST, | |
6311 | .resetvalue = 0 }, | |
6312 | REGINFO_SENTINEL | |
2771db27 | 6313 | }; |
834a6c69 | 6314 | define_arm_cp_regs(cpu, auxcr_reginfo); |
0e0456ab PM |
6315 | if (arm_feature(env, ARM_FEATURE_V8)) { |
6316 | /* HACTLR2 maps to ACTLR_EL2[63:32] and is not in ARMv7 */ | |
6317 | ARMCPRegInfo hactlr2_reginfo = { | |
6318 | .name = "HACTLR2", .state = ARM_CP_STATE_AA32, | |
6319 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3, | |
6320 | .access = PL2_RW, .type = ARM_CP_CONST, | |
6321 | .resetvalue = 0 | |
6322 | }; | |
6323 | define_one_arm_cp_reg(cpu, &hactlr2_reginfo); | |
6324 | } | |
2771db27 PM |
6325 | } |
6326 | ||
d8ba780b | 6327 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
f318cec6 PM |
6328 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
6329 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | |
6330 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | |
6331 | | extract64(cpu->reset_cbar, 32, 12); | |
6332 | ARMCPRegInfo cbar_reginfo[] = { | |
6333 | { .name = "CBAR", | |
6334 | .type = ARM_CP_CONST, | |
6335 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
6336 | .access = PL1_R, .resetvalue = cpu->reset_cbar }, | |
6337 | { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, | |
6338 | .type = ARM_CP_CONST, | |
6339 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | |
6340 | .access = PL1_R, .resetvalue = cbar32 }, | |
6341 | REGINFO_SENTINEL | |
6342 | }; | |
6343 | /* We don't implement a r/w 64 bit CBAR currently */ | |
6344 | assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); | |
6345 | define_arm_cp_regs(cpu, cbar_reginfo); | |
6346 | } else { | |
6347 | ARMCPRegInfo cbar = { | |
6348 | .name = "CBAR", | |
6349 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
6350 | .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, | |
6351 | .fieldoffset = offsetof(CPUARMState, | |
6352 | cp15.c15_config_base_address) | |
6353 | }; | |
6354 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | |
6355 | cbar.access = PL1_R; | |
6356 | cbar.fieldoffset = 0; | |
6357 | cbar.type = ARM_CP_CONST; | |
6358 | } | |
6359 | define_one_arm_cp_reg(cpu, &cbar); | |
6360 | } | |
d8ba780b PC |
6361 | } |
6362 | ||
91db4642 CLG |
6363 | if (arm_feature(env, ARM_FEATURE_VBAR)) { |
6364 | ARMCPRegInfo vbar_cp_reginfo[] = { | |
6365 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, | |
6366 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | |
6367 | .access = PL1_RW, .writefn = vbar_write, | |
6368 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), | |
6369 | offsetof(CPUARMState, cp15.vbar_ns) }, | |
6370 | .resetvalue = 0 }, | |
6371 | REGINFO_SENTINEL | |
6372 | }; | |
6373 | define_arm_cp_regs(cpu, vbar_cp_reginfo); | |
6374 | } | |
6375 | ||
2771db27 PM |
6376 | /* Generic registers whose values depend on the implementation */ |
6377 | { | |
6378 | ARMCPRegInfo sctlr = { | |
5ebafdf3 | 6379 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, |
137feaa9 FA |
6380 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, |
6381 | .access = PL1_RW, | |
6382 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), | |
6383 | offsetof(CPUARMState, cp15.sctlr_ns) }, | |
d4e6df63 PM |
6384 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, |
6385 | .raw_writefn = raw_write, | |
2771db27 PM |
6386 | }; |
6387 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
6388 | /* Normally we would always end the TB on an SCTLR write, but Linux | |
6389 | * arch/arm/mach-pxa/sleep.S expects two instructions following | |
6390 | * an MMU enable to execute from cache. Imitate this behaviour. | |
6391 | */ | |
6392 | sctlr.type |= ARM_CP_SUPPRESS_TB_END; | |
6393 | } | |
6394 | define_one_arm_cp_reg(cpu, &sctlr); | |
6395 | } | |
5be5e8ed | 6396 | |
2d7137c1 RH |
6397 | if (cpu_isar_feature(aa64_lor, cpu)) { |
6398 | /* | |
6399 | * A trivial implementation of ARMv8.1-LOR leaves all of these | |
6400 | * registers fixed at 0, which indicates that there are zero | |
6401 | * supported Limited Ordering regions. | |
6402 | */ | |
6403 | static const ARMCPRegInfo lor_reginfo[] = { | |
6404 | { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, | |
6405 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, | |
6406 | .access = PL1_RW, .accessfn = access_lor_other, | |
6407 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6408 | { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, | |
6409 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, | |
6410 | .access = PL1_RW, .accessfn = access_lor_other, | |
6411 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6412 | { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, | |
6413 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, | |
6414 | .access = PL1_RW, .accessfn = access_lor_other, | |
6415 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6416 | { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, | |
6417 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, | |
6418 | .access = PL1_RW, .accessfn = access_lor_other, | |
6419 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6420 | { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, | |
6421 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, | |
6422 | .access = PL1_R, .accessfn = access_lorid, | |
6423 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6424 | REGINFO_SENTINEL | |
6425 | }; | |
6426 | define_arm_cp_regs(cpu, lor_reginfo); | |
6427 | } | |
6428 | ||
cd208a1c | 6429 | if (cpu_isar_feature(aa64_sve, cpu)) { |
5be5e8ed RH |
6430 | define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); |
6431 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
6432 | define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); | |
6433 | } else { | |
6434 | define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo); | |
6435 | } | |
6436 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
6437 | define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); | |
6438 | } | |
6439 | } | |
967aa94f RH |
6440 | |
6441 | #ifdef TARGET_AARCH64 | |
6442 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
6443 | define_arm_cp_regs(cpu, pauth_reginfo); | |
6444 | } | |
6445 | #endif | |
2ceb98c0 PM |
6446 | } |
6447 | ||
14969266 AF |
6448 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) |
6449 | { | |
22169d41 | 6450 | CPUState *cs = CPU(cpu); |
14969266 AF |
6451 | CPUARMState *env = &cpu->env; |
6452 | ||
6a669427 PM |
6453 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
6454 | gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, | |
6455 | aarch64_fpu_gdb_set_reg, | |
6456 | 34, "aarch64-fpu.xml", 0); | |
6457 | } else if (arm_feature(env, ARM_FEATURE_NEON)) { | |
22169d41 | 6458 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
6459 | 51, "arm-neon.xml", 0); |
6460 | } else if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
22169d41 | 6461 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
6462 | 35, "arm-vfp3.xml", 0); |
6463 | } else if (arm_feature(env, ARM_FEATURE_VFP)) { | |
22169d41 | 6464 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
6465 | 19, "arm-vfp.xml", 0); |
6466 | } | |
200bf5b7 AB |
6467 | gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, |
6468 | arm_gen_dynamic_xml(cs), | |
6469 | "system-registers.xml", 0); | |
40f137e1 PB |
6470 | } |
6471 | ||
777dc784 PM |
6472 | /* Sort alphabetically by type name, except for "any". */ |
6473 | static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) | |
5adb4839 | 6474 | { |
777dc784 PM |
6475 | ObjectClass *class_a = (ObjectClass *)a; |
6476 | ObjectClass *class_b = (ObjectClass *)b; | |
6477 | const char *name_a, *name_b; | |
5adb4839 | 6478 | |
777dc784 PM |
6479 | name_a = object_class_get_name(class_a); |
6480 | name_b = object_class_get_name(class_b); | |
51492fd1 | 6481 | if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 | 6482 | return 1; |
51492fd1 | 6483 | } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 PM |
6484 | return -1; |
6485 | } else { | |
6486 | return strcmp(name_a, name_b); | |
5adb4839 PB |
6487 | } |
6488 | } | |
6489 | ||
777dc784 | 6490 | static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
40f137e1 | 6491 | { |
777dc784 | 6492 | ObjectClass *oc = data; |
92a31361 | 6493 | CPUListState *s = user_data; |
51492fd1 AF |
6494 | const char *typename; |
6495 | char *name; | |
3371d272 | 6496 | |
51492fd1 AF |
6497 | typename = object_class_get_name(oc); |
6498 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
777dc784 | 6499 | (*s->cpu_fprintf)(s->file, " %s\n", |
51492fd1 AF |
6500 | name); |
6501 | g_free(name); | |
777dc784 PM |
6502 | } |
6503 | ||
6504 | void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
6505 | { | |
92a31361 | 6506 | CPUListState s = { |
777dc784 PM |
6507 | .file = f, |
6508 | .cpu_fprintf = cpu_fprintf, | |
6509 | }; | |
6510 | GSList *list; | |
6511 | ||
6512 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
6513 | list = g_slist_sort(list, arm_cpu_list_compare); | |
6514 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
6515 | g_slist_foreach(list, arm_cpu_list_entry, &s); | |
6516 | g_slist_free(list); | |
40f137e1 PB |
6517 | } |
6518 | ||
78027bb6 CR |
6519 | static void arm_cpu_add_definition(gpointer data, gpointer user_data) |
6520 | { | |
6521 | ObjectClass *oc = data; | |
6522 | CpuDefinitionInfoList **cpu_list = user_data; | |
6523 | CpuDefinitionInfoList *entry; | |
6524 | CpuDefinitionInfo *info; | |
6525 | const char *typename; | |
6526 | ||
6527 | typename = object_class_get_name(oc); | |
6528 | info = g_malloc0(sizeof(*info)); | |
6529 | info->name = g_strndup(typename, | |
6530 | strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
8ed877b7 | 6531 | info->q_typename = g_strdup(typename); |
78027bb6 CR |
6532 | |
6533 | entry = g_malloc0(sizeof(*entry)); | |
6534 | entry->value = info; | |
6535 | entry->next = *cpu_list; | |
6536 | *cpu_list = entry; | |
6537 | } | |
6538 | ||
6539 | CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) | |
6540 | { | |
6541 | CpuDefinitionInfoList *cpu_list = NULL; | |
6542 | GSList *list; | |
6543 | ||
6544 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
6545 | g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); | |
6546 | g_slist_free(list); | |
6547 | ||
6548 | return cpu_list; | |
6549 | } | |
6550 | ||
6e6efd61 | 6551 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
51a79b03 | 6552 | void *opaque, int state, int secstate, |
9c513e78 AB |
6553 | int crm, int opc1, int opc2, |
6554 | const char *name) | |
6e6efd61 PM |
6555 | { |
6556 | /* Private utility function for define_one_arm_cp_reg_with_opaque(): | |
6557 | * add a single reginfo struct to the hash table. | |
6558 | */ | |
6559 | uint32_t *key = g_new(uint32_t, 1); | |
6560 | ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); | |
6561 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | |
3f3c82a5 FA |
6562 | int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; |
6563 | ||
9c513e78 | 6564 | r2->name = g_strdup(name); |
3f3c82a5 FA |
6565 | /* Reset the secure state to the specific incoming state. This is |
6566 | * necessary as the register may have been defined with both states. | |
6567 | */ | |
6568 | r2->secure = secstate; | |
6569 | ||
6570 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
6571 | /* Register is banked (using both entries in array). | |
6572 | * Overwriting fieldoffset as the array is only used to define | |
6573 | * banked registers but later only fieldoffset is used. | |
f5a0a5a5 | 6574 | */ |
3f3c82a5 FA |
6575 | r2->fieldoffset = r->bank_fieldoffsets[ns]; |
6576 | } | |
6577 | ||
6578 | if (state == ARM_CP_STATE_AA32) { | |
6579 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
6580 | /* If the register is banked then we don't need to migrate or | |
6581 | * reset the 32-bit instance in certain cases: | |
6582 | * | |
6583 | * 1) If the register has both 32-bit and 64-bit instances then we | |
6584 | * can count on the 64-bit instance taking care of the | |
6585 | * non-secure bank. | |
6586 | * 2) If ARMv8 is enabled then we can count on a 64-bit version | |
6587 | * taking care of the secure bank. This requires that separate | |
6588 | * 32 and 64-bit definitions are provided. | |
6589 | */ | |
6590 | if ((r->state == ARM_CP_STATE_BOTH && ns) || | |
6591 | (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { | |
7a0e58fa | 6592 | r2->type |= ARM_CP_ALIAS; |
3f3c82a5 FA |
6593 | } |
6594 | } else if ((secstate != r->secure) && !ns) { | |
6595 | /* The register is not banked so we only want to allow migration of | |
6596 | * the non-secure instance. | |
6597 | */ | |
7a0e58fa | 6598 | r2->type |= ARM_CP_ALIAS; |
58a1d8ce | 6599 | } |
3f3c82a5 FA |
6600 | |
6601 | if (r->state == ARM_CP_STATE_BOTH) { | |
6602 | /* We assume it is a cp15 register if the .cp field is left unset. | |
6603 | */ | |
6604 | if (r2->cp == 0) { | |
6605 | r2->cp = 15; | |
6606 | } | |
6607 | ||
f5a0a5a5 | 6608 | #ifdef HOST_WORDS_BIGENDIAN |
3f3c82a5 FA |
6609 | if (r2->fieldoffset) { |
6610 | r2->fieldoffset += sizeof(uint32_t); | |
6611 | } | |
f5a0a5a5 | 6612 | #endif |
3f3c82a5 | 6613 | } |
f5a0a5a5 PM |
6614 | } |
6615 | if (state == ARM_CP_STATE_AA64) { | |
6616 | /* To allow abbreviation of ARMCPRegInfo | |
6617 | * definitions, we treat cp == 0 as equivalent to | |
6618 | * the value for "standard guest-visible sysreg". | |
58a1d8ce PM |
6619 | * STATE_BOTH definitions are also always "standard |
6620 | * sysreg" in their AArch64 view (the .cp value may | |
6621 | * be non-zero for the benefit of the AArch32 view). | |
f5a0a5a5 | 6622 | */ |
58a1d8ce | 6623 | if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { |
f5a0a5a5 PM |
6624 | r2->cp = CP_REG_ARM64_SYSREG_CP; |
6625 | } | |
6626 | *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | |
6627 | r2->opc0, opc1, opc2); | |
6628 | } else { | |
51a79b03 | 6629 | *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); |
f5a0a5a5 | 6630 | } |
6e6efd61 PM |
6631 | if (opaque) { |
6632 | r2->opaque = opaque; | |
6633 | } | |
67ed771d PM |
6634 | /* reginfo passed to helpers is correct for the actual access, |
6635 | * and is never ARM_CP_STATE_BOTH: | |
6636 | */ | |
6637 | r2->state = state; | |
6e6efd61 PM |
6638 | /* Make sure reginfo passed to helpers for wildcarded regs |
6639 | * has the correct crm/opc1/opc2 for this reg, not CP_ANY: | |
6640 | */ | |
6641 | r2->crm = crm; | |
6642 | r2->opc1 = opc1; | |
6643 | r2->opc2 = opc2; | |
6644 | /* By convention, for wildcarded registers only the first | |
6645 | * entry is used for migration; the others are marked as | |
7a0e58fa | 6646 | * ALIAS so we don't try to transfer the register |
6e6efd61 | 6647 | * multiple times. Special registers (ie NOP/WFI) are |
7a0e58fa | 6648 | * never migratable and not even raw-accessible. |
6e6efd61 | 6649 | */ |
7a0e58fa PM |
6650 | if ((r->type & ARM_CP_SPECIAL)) { |
6651 | r2->type |= ARM_CP_NO_RAW; | |
6652 | } | |
6653 | if (((r->crm == CP_ANY) && crm != 0) || | |
6e6efd61 PM |
6654 | ((r->opc1 == CP_ANY) && opc1 != 0) || |
6655 | ((r->opc2 == CP_ANY) && opc2 != 0)) { | |
1f163787 | 6656 | r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB; |
6e6efd61 PM |
6657 | } |
6658 | ||
375421cc PM |
6659 | /* Check that raw accesses are either forbidden or handled. Note that |
6660 | * we can't assert this earlier because the setup of fieldoffset for | |
6661 | * banked registers has to be done first. | |
6662 | */ | |
6663 | if (!(r2->type & ARM_CP_NO_RAW)) { | |
6664 | assert(!raw_accessors_invalid(r2)); | |
6665 | } | |
6666 | ||
6e6efd61 PM |
6667 | /* Overriding of an existing definition must be explicitly |
6668 | * requested. | |
6669 | */ | |
6670 | if (!(r->type & ARM_CP_OVERRIDE)) { | |
6671 | ARMCPRegInfo *oldreg; | |
6672 | oldreg = g_hash_table_lookup(cpu->cp_regs, key); | |
6673 | if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { | |
6674 | fprintf(stderr, "Register redefined: cp=%d %d bit " | |
6675 | "crn=%d crm=%d opc1=%d opc2=%d, " | |
6676 | "was %s, now %s\n", r2->cp, 32 + 32 * is64, | |
6677 | r2->crn, r2->crm, r2->opc1, r2->opc2, | |
6678 | oldreg->name, r2->name); | |
6679 | g_assert_not_reached(); | |
6680 | } | |
6681 | } | |
6682 | g_hash_table_insert(cpu->cp_regs, key, r2); | |
6683 | } | |
6684 | ||
6685 | ||
4b6a83fb PM |
6686 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
6687 | const ARMCPRegInfo *r, void *opaque) | |
6688 | { | |
6689 | /* Define implementations of coprocessor registers. | |
6690 | * We store these in a hashtable because typically | |
6691 | * there are less than 150 registers in a space which | |
6692 | * is 16*16*16*8*8 = 262144 in size. | |
6693 | * Wildcarding is supported for the crm, opc1 and opc2 fields. | |
6694 | * If a register is defined twice then the second definition is | |
6695 | * used, so this can be used to define some generic registers and | |
6696 | * then override them with implementation specific variations. | |
6697 | * At least one of the original and the second definition should | |
6698 | * include ARM_CP_OVERRIDE in its type bits -- this is just a guard | |
6699 | * against accidental use. | |
f5a0a5a5 PM |
6700 | * |
6701 | * The state field defines whether the register is to be | |
6702 | * visible in the AArch32 or AArch64 execution state. If the | |
6703 | * state is set to ARM_CP_STATE_BOTH then we synthesise a | |
6704 | * reginfo structure for the AArch32 view, which sees the lower | |
6705 | * 32 bits of the 64 bit register. | |
6706 | * | |
6707 | * Only registers visible in AArch64 may set r->opc0; opc0 cannot | |
6708 | * be wildcarded. AArch64 registers are always considered to be 64 | |
6709 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | |
6710 | * the register, if any. | |
4b6a83fb | 6711 | */ |
f5a0a5a5 | 6712 | int crm, opc1, opc2, state; |
4b6a83fb PM |
6713 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
6714 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | |
6715 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | |
6716 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | |
6717 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | |
6718 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | |
6719 | /* 64 bit registers have only CRm and Opc1 fields */ | |
6720 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | |
f5a0a5a5 PM |
6721 | /* op0 only exists in the AArch64 encodings */ |
6722 | assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); | |
6723 | /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ | |
6724 | assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); | |
6725 | /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 | |
6726 | * encodes a minimum access level for the register. We roll this | |
6727 | * runtime check into our general permission check code, so check | |
6728 | * here that the reginfo's specified permissions are strict enough | |
6729 | * to encompass the generic architectural permission check. | |
6730 | */ | |
6731 | if (r->state != ARM_CP_STATE_AA32) { | |
6732 | int mask = 0; | |
6733 | switch (r->opc1) { | |
6734 | case 0: case 1: case 2: | |
6735 | /* min_EL EL1 */ | |
6736 | mask = PL1_RW; | |
6737 | break; | |
6738 | case 3: | |
6739 | /* min_EL EL0 */ | |
6740 | mask = PL0_RW; | |
6741 | break; | |
6742 | case 4: | |
6743 | /* min_EL EL2 */ | |
6744 | mask = PL2_RW; | |
6745 | break; | |
6746 | case 5: | |
6747 | /* unallocated encoding, so not possible */ | |
6748 | assert(false); | |
6749 | break; | |
6750 | case 6: | |
6751 | /* min_EL EL3 */ | |
6752 | mask = PL3_RW; | |
6753 | break; | |
6754 | case 7: | |
6755 | /* min_EL EL1, secure mode only (we don't check the latter) */ | |
6756 | mask = PL1_RW; | |
6757 | break; | |
6758 | default: | |
6759 | /* broken reginfo with out-of-range opc1 */ | |
6760 | assert(false); | |
6761 | break; | |
6762 | } | |
6763 | /* assert our permissions are not too lax (stricter is fine) */ | |
6764 | assert((r->access & ~mask) == 0); | |
6765 | } | |
6766 | ||
4b6a83fb PM |
6767 | /* Check that the register definition has enough info to handle |
6768 | * reads and writes if they are permitted. | |
6769 | */ | |
6770 | if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { | |
6771 | if (r->access & PL3_R) { | |
3f3c82a5 FA |
6772 | assert((r->fieldoffset || |
6773 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
6774 | r->readfn); | |
4b6a83fb PM |
6775 | } |
6776 | if (r->access & PL3_W) { | |
3f3c82a5 FA |
6777 | assert((r->fieldoffset || |
6778 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
6779 | r->writefn); | |
4b6a83fb PM |
6780 | } |
6781 | } | |
6782 | /* Bad type field probably means missing sentinel at end of reg list */ | |
6783 | assert(cptype_valid(r->type)); | |
6784 | for (crm = crmmin; crm <= crmmax; crm++) { | |
6785 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | |
6786 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | |
f5a0a5a5 PM |
6787 | for (state = ARM_CP_STATE_AA32; |
6788 | state <= ARM_CP_STATE_AA64; state++) { | |
6789 | if (r->state != state && r->state != ARM_CP_STATE_BOTH) { | |
6790 | continue; | |
6791 | } | |
3f3c82a5 FA |
6792 | if (state == ARM_CP_STATE_AA32) { |
6793 | /* Under AArch32 CP registers can be common | |
6794 | * (same for secure and non-secure world) or banked. | |
6795 | */ | |
9c513e78 AB |
6796 | char *name; |
6797 | ||
3f3c82a5 FA |
6798 | switch (r->secure) { |
6799 | case ARM_CP_SECSTATE_S: | |
6800 | case ARM_CP_SECSTATE_NS: | |
6801 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
9c513e78 AB |
6802 | r->secure, crm, opc1, opc2, |
6803 | r->name); | |
3f3c82a5 FA |
6804 | break; |
6805 | default: | |
9c513e78 | 6806 | name = g_strdup_printf("%s_S", r->name); |
3f3c82a5 FA |
6807 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
6808 | ARM_CP_SECSTATE_S, | |
9c513e78 AB |
6809 | crm, opc1, opc2, name); |
6810 | g_free(name); | |
3f3c82a5 FA |
6811 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
6812 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 6813 | crm, opc1, opc2, r->name); |
3f3c82a5 FA |
6814 | break; |
6815 | } | |
6816 | } else { | |
6817 | /* AArch64 registers get mapped to non-secure instance | |
6818 | * of AArch32 */ | |
6819 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
6820 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 6821 | crm, opc1, opc2, r->name); |
3f3c82a5 | 6822 | } |
f5a0a5a5 | 6823 | } |
4b6a83fb PM |
6824 | } |
6825 | } | |
6826 | } | |
6827 | } | |
6828 | ||
6829 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
6830 | const ARMCPRegInfo *regs, void *opaque) | |
6831 | { | |
6832 | /* Define a whole list of registers */ | |
6833 | const ARMCPRegInfo *r; | |
6834 | for (r = regs; r->type != ARM_CP_SENTINEL; r++) { | |
6835 | define_one_arm_cp_reg_with_opaque(cpu, r, opaque); | |
6836 | } | |
6837 | } | |
6838 | ||
60322b39 | 6839 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) |
4b6a83fb | 6840 | { |
60322b39 | 6841 | return g_hash_table_lookup(cpregs, &encoded_cp); |
4b6a83fb PM |
6842 | } |
6843 | ||
c4241c7d PM |
6844 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
6845 | uint64_t value) | |
4b6a83fb PM |
6846 | { |
6847 | /* Helper coprocessor write function for write-ignore registers */ | |
4b6a83fb PM |
6848 | } |
6849 | ||
c4241c7d | 6850 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) |
4b6a83fb PM |
6851 | { |
6852 | /* Helper coprocessor write function for read-as-zero registers */ | |
4b6a83fb PM |
6853 | return 0; |
6854 | } | |
6855 | ||
f5a0a5a5 PM |
6856 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) |
6857 | { | |
6858 | /* Helper coprocessor reset function for do-nothing-on-reset registers */ | |
6859 | } | |
6860 | ||
af393ffc | 6861 | static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) |
37064a8b PM |
6862 | { |
6863 | /* Return true if it is not valid for us to switch to | |
6864 | * this CPU mode (ie all the UNPREDICTABLE cases in | |
6865 | * the ARM ARM CPSRWriteByInstr pseudocode). | |
6866 | */ | |
af393ffc PM |
6867 | |
6868 | /* Changes to or from Hyp via MSR and CPS are illegal. */ | |
6869 | if (write_type == CPSRWriteByInstr && | |
6870 | ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || | |
6871 | mode == ARM_CPU_MODE_HYP)) { | |
6872 | return 1; | |
6873 | } | |
6874 | ||
37064a8b PM |
6875 | switch (mode) { |
6876 | case ARM_CPU_MODE_USR: | |
10eacda7 | 6877 | return 0; |
37064a8b PM |
6878 | case ARM_CPU_MODE_SYS: |
6879 | case ARM_CPU_MODE_SVC: | |
6880 | case ARM_CPU_MODE_ABT: | |
6881 | case ARM_CPU_MODE_UND: | |
6882 | case ARM_CPU_MODE_IRQ: | |
6883 | case ARM_CPU_MODE_FIQ: | |
52ff951b PM |
6884 | /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 |
6885 | * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) | |
6886 | */ | |
10eacda7 PM |
6887 | /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR |
6888 | * and CPS are treated as illegal mode changes. | |
6889 | */ | |
6890 | if (write_type == CPSRWriteByInstr && | |
10eacda7 | 6891 | (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && |
7c208e0f | 6892 | (arm_hcr_el2_eff(env) & HCR_TGE)) { |
10eacda7 PM |
6893 | return 1; |
6894 | } | |
37064a8b | 6895 | return 0; |
e6c8fc07 PM |
6896 | case ARM_CPU_MODE_HYP: |
6897 | return !arm_feature(env, ARM_FEATURE_EL2) | |
2d2a4549 | 6898 | || arm_current_el(env) < 2 || arm_is_secure_below_el3(env); |
027fc527 | 6899 | case ARM_CPU_MODE_MON: |
58ae2d1f | 6900 | return arm_current_el(env) < 3; |
37064a8b PM |
6901 | default: |
6902 | return 1; | |
6903 | } | |
6904 | } | |
6905 | ||
2f4a40e5 AZ |
6906 | uint32_t cpsr_read(CPUARMState *env) |
6907 | { | |
6908 | int ZF; | |
6fbe23d5 PB |
6909 | ZF = (env->ZF == 0); |
6910 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
6911 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
6912 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
6913 | | ((env->condexec_bits & 0xfc) << 8) | |
af519934 | 6914 | | (env->GE << 16) | (env->daif & CPSR_AIF); |
2f4a40e5 AZ |
6915 | } |
6916 | ||
50866ba5 PM |
6917 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, |
6918 | CPSRWriteType write_type) | |
2f4a40e5 | 6919 | { |
6e8801f9 FA |
6920 | uint32_t changed_daif; |
6921 | ||
2f4a40e5 | 6922 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
6923 | env->ZF = (~val) & CPSR_Z; |
6924 | env->NF = val; | |
2f4a40e5 AZ |
6925 | env->CF = (val >> 29) & 1; |
6926 | env->VF = (val << 3) & 0x80000000; | |
6927 | } | |
6928 | if (mask & CPSR_Q) | |
6929 | env->QF = ((val & CPSR_Q) != 0); | |
6930 | if (mask & CPSR_T) | |
6931 | env->thumb = ((val & CPSR_T) != 0); | |
6932 | if (mask & CPSR_IT_0_1) { | |
6933 | env->condexec_bits &= ~3; | |
6934 | env->condexec_bits |= (val >> 25) & 3; | |
6935 | } | |
6936 | if (mask & CPSR_IT_2_7) { | |
6937 | env->condexec_bits &= 3; | |
6938 | env->condexec_bits |= (val >> 8) & 0xfc; | |
6939 | } | |
6940 | if (mask & CPSR_GE) { | |
6941 | env->GE = (val >> 16) & 0xf; | |
6942 | } | |
6943 | ||
6e8801f9 FA |
6944 | /* In a V7 implementation that includes the security extensions but does |
6945 | * not include Virtualization Extensions the SCR.FW and SCR.AW bits control | |
6946 | * whether non-secure software is allowed to change the CPSR_F and CPSR_A | |
6947 | * bits respectively. | |
6948 | * | |
6949 | * In a V8 implementation, it is permitted for privileged software to | |
6950 | * change the CPSR A/F bits regardless of the SCR.AW/FW bits. | |
6951 | */ | |
f8c88bbc | 6952 | if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && |
6e8801f9 FA |
6953 | arm_feature(env, ARM_FEATURE_EL3) && |
6954 | !arm_feature(env, ARM_FEATURE_EL2) && | |
6955 | !arm_is_secure(env)) { | |
6956 | ||
6957 | changed_daif = (env->daif ^ val) & mask; | |
6958 | ||
6959 | if (changed_daif & CPSR_A) { | |
6960 | /* Check to see if we are allowed to change the masking of async | |
6961 | * abort exceptions from a non-secure state. | |
6962 | */ | |
6963 | if (!(env->cp15.scr_el3 & SCR_AW)) { | |
6964 | qemu_log_mask(LOG_GUEST_ERROR, | |
6965 | "Ignoring attempt to switch CPSR_A flag from " | |
6966 | "non-secure world with SCR.AW bit clear\n"); | |
6967 | mask &= ~CPSR_A; | |
6968 | } | |
6969 | } | |
6970 | ||
6971 | if (changed_daif & CPSR_F) { | |
6972 | /* Check to see if we are allowed to change the masking of FIQ | |
6973 | * exceptions from a non-secure state. | |
6974 | */ | |
6975 | if (!(env->cp15.scr_el3 & SCR_FW)) { | |
6976 | qemu_log_mask(LOG_GUEST_ERROR, | |
6977 | "Ignoring attempt to switch CPSR_F flag from " | |
6978 | "non-secure world with SCR.FW bit clear\n"); | |
6979 | mask &= ~CPSR_F; | |
6980 | } | |
6981 | ||
6982 | /* Check whether non-maskable FIQ (NMFI) support is enabled. | |
6983 | * If this bit is set software is not allowed to mask | |
6984 | * FIQs, but is allowed to set CPSR_F to 0. | |
6985 | */ | |
6986 | if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && | |
6987 | (val & CPSR_F)) { | |
6988 | qemu_log_mask(LOG_GUEST_ERROR, | |
6989 | "Ignoring attempt to enable CPSR_F flag " | |
6990 | "(non-maskable FIQ [NMFI] support enabled)\n"); | |
6991 | mask &= ~CPSR_F; | |
6992 | } | |
6993 | } | |
6994 | } | |
6995 | ||
4cc35614 PM |
6996 | env->daif &= ~(CPSR_AIF & mask); |
6997 | env->daif |= val & CPSR_AIF & mask; | |
6998 | ||
f8c88bbc PM |
6999 | if (write_type != CPSRWriteRaw && |
7000 | ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { | |
8c4f0eb9 PM |
7001 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { |
7002 | /* Note that we can only get here in USR mode if this is a | |
7003 | * gdb stub write; for this case we follow the architectural | |
7004 | * behaviour for guest writes in USR mode of ignoring an attempt | |
7005 | * to switch mode. (Those are caught by translate.c for writes | |
7006 | * triggered by guest instructions.) | |
7007 | */ | |
7008 | mask &= ~CPSR_M; | |
7009 | } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { | |
81907a58 PM |
7010 | /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in |
7011 | * v7, and has defined behaviour in v8: | |
7012 | * + leave CPSR.M untouched | |
7013 | * + allow changes to the other CPSR fields | |
7014 | * + set PSTATE.IL | |
7015 | * For user changes via the GDB stub, we don't set PSTATE.IL, | |
7016 | * as this would be unnecessarily harsh for a user error. | |
37064a8b PM |
7017 | */ |
7018 | mask &= ~CPSR_M; | |
81907a58 PM |
7019 | if (write_type != CPSRWriteByGDBStub && |
7020 | arm_feature(env, ARM_FEATURE_V8)) { | |
7021 | mask |= CPSR_IL; | |
7022 | val |= CPSR_IL; | |
7023 | } | |
81e37284 PM |
7024 | qemu_log_mask(LOG_GUEST_ERROR, |
7025 | "Illegal AArch32 mode switch attempt from %s to %s\n", | |
7026 | aarch32_mode_name(env->uncached_cpsr), | |
7027 | aarch32_mode_name(val)); | |
37064a8b | 7028 | } else { |
81e37284 PM |
7029 | qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n", |
7030 | write_type == CPSRWriteExceptionReturn ? | |
7031 | "Exception return from AArch32" : | |
7032 | "AArch32 mode switch from", | |
7033 | aarch32_mode_name(env->uncached_cpsr), | |
7034 | aarch32_mode_name(val), env->regs[15]); | |
37064a8b PM |
7035 | switch_mode(env, val & CPSR_M); |
7036 | } | |
2f4a40e5 AZ |
7037 | } |
7038 | mask &= ~CACHED_CPSR_BITS; | |
7039 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
7040 | } | |
7041 | ||
b26eefb6 PB |
7042 | /* Sign/zero extend */ |
7043 | uint32_t HELPER(sxtb16)(uint32_t x) | |
7044 | { | |
7045 | uint32_t res; | |
7046 | res = (uint16_t)(int8_t)x; | |
7047 | res |= (uint32_t)(int8_t)(x >> 16) << 16; | |
7048 | return res; | |
7049 | } | |
7050 | ||
7051 | uint32_t HELPER(uxtb16)(uint32_t x) | |
7052 | { | |
7053 | uint32_t res; | |
7054 | res = (uint16_t)(uint8_t)x; | |
7055 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; | |
7056 | return res; | |
7057 | } | |
7058 | ||
3670669c PB |
7059 | int32_t HELPER(sdiv)(int32_t num, int32_t den) |
7060 | { | |
7061 | if (den == 0) | |
7062 | return 0; | |
686eeb93 AJ |
7063 | if (num == INT_MIN && den == -1) |
7064 | return INT_MIN; | |
3670669c PB |
7065 | return num / den; |
7066 | } | |
7067 | ||
7068 | uint32_t HELPER(udiv)(uint32_t num, uint32_t den) | |
7069 | { | |
7070 | if (den == 0) | |
7071 | return 0; | |
7072 | return num / den; | |
7073 | } | |
7074 | ||
7075 | uint32_t HELPER(rbit)(uint32_t x) | |
7076 | { | |
42fedbca | 7077 | return revbit32(x); |
3670669c PB |
7078 | } |
7079 | ||
5fafdf24 | 7080 | #if defined(CONFIG_USER_ONLY) |
b5ff1b31 | 7081 | |
9ee6e8bb | 7082 | /* These should probably raise undefined insn exceptions. */ |
0ecb72a5 | 7083 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) |
9ee6e8bb | 7084 | { |
a47dddd7 AF |
7085 | ARMCPU *cpu = arm_env_get_cpu(env); |
7086 | ||
7087 | cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); | |
9ee6e8bb PB |
7088 | } |
7089 | ||
0ecb72a5 | 7090 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb | 7091 | { |
a47dddd7 AF |
7092 | ARMCPU *cpu = arm_env_get_cpu(env); |
7093 | ||
7094 | cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); | |
9ee6e8bb PB |
7095 | return 0; |
7096 | } | |
7097 | ||
fb602cb7 PM |
7098 | void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) |
7099 | { | |
7100 | /* translate.c should never generate calls here in user-only mode */ | |
7101 | g_assert_not_reached(); | |
7102 | } | |
7103 | ||
3e3fa230 PM |
7104 | void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) |
7105 | { | |
7106 | /* translate.c should never generate calls here in user-only mode */ | |
7107 | g_assert_not_reached(); | |
7108 | } | |
7109 | ||
5158de24 PM |
7110 | uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) |
7111 | { | |
7112 | /* The TT instructions can be used by unprivileged code, but in | |
7113 | * user-only emulation we don't have the MPU. | |
7114 | * Luckily since we know we are NonSecure unprivileged (and that in | |
7115 | * turn means that the A flag wasn't specified), all the bits in the | |
7116 | * register must be zero: | |
7117 | * IREGION: 0 because IRVALID is 0 | |
7118 | * IRVALID: 0 because NS | |
7119 | * S: 0 because NS | |
7120 | * NSRW: 0 because NS | |
7121 | * NSR: 0 because NS | |
7122 | * RW: 0 because unpriv and A flag not set | |
7123 | * R: 0 because unpriv and A flag not set | |
7124 | * SRVALID: 0 because NS | |
7125 | * MRVALID: 0 because unpriv and A flag not set | |
7126 | * SREGION: 0 becaus SRVALID is 0 | |
7127 | * MREGION: 0 because MRVALID is 0 | |
7128 | */ | |
7129 | return 0; | |
7130 | } | |
7131 | ||
affdb64d | 7132 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 | 7133 | { |
a47dddd7 AF |
7134 | ARMCPU *cpu = arm_env_get_cpu(env); |
7135 | ||
7136 | if (mode != ARM_CPU_MODE_USR) { | |
7137 | cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); | |
7138 | } | |
b5ff1b31 FB |
7139 | } |
7140 | ||
012a906b GB |
7141 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
7142 | uint32_t cur_el, bool secure) | |
9e729b57 EI |
7143 | { |
7144 | return 1; | |
7145 | } | |
7146 | ||
ce02049d GB |
7147 | void aarch64_sync_64_to_32(CPUARMState *env) |
7148 | { | |
7149 | g_assert_not_reached(); | |
7150 | } | |
7151 | ||
b5ff1b31 FB |
7152 | #else |
7153 | ||
affdb64d | 7154 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
7155 | { |
7156 | int old_mode; | |
7157 | int i; | |
7158 | ||
7159 | old_mode = env->uncached_cpsr & CPSR_M; | |
7160 | if (mode == old_mode) | |
7161 | return; | |
7162 | ||
7163 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
7164 | memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 7165 | memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
7166 | } else if (mode == ARM_CPU_MODE_FIQ) { |
7167 | memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 7168 | memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
7169 | } |
7170 | ||
f5206413 | 7171 | i = bank_number(old_mode); |
b5ff1b31 | 7172 | env->banked_r13[i] = env->regs[13]; |
b5ff1b31 FB |
7173 | env->banked_spsr[i] = env->spsr; |
7174 | ||
f5206413 | 7175 | i = bank_number(mode); |
b5ff1b31 | 7176 | env->regs[13] = env->banked_r13[i]; |
b5ff1b31 | 7177 | env->spsr = env->banked_spsr[i]; |
593cfa2b PM |
7178 | |
7179 | env->banked_r14[r14_bank_number(old_mode)] = env->regs[14]; | |
7180 | env->regs[14] = env->banked_r14[r14_bank_number(mode)]; | |
b5ff1b31 FB |
7181 | } |
7182 | ||
0eeb17d6 GB |
7183 | /* Physical Interrupt Target EL Lookup Table |
7184 | * | |
7185 | * [ From ARM ARM section G1.13.4 (Table G1-15) ] | |
7186 | * | |
7187 | * The below multi-dimensional table is used for looking up the target | |
7188 | * exception level given numerous condition criteria. Specifically, the | |
7189 | * target EL is based on SCR and HCR routing controls as well as the | |
7190 | * currently executing EL and secure state. | |
7191 | * | |
7192 | * Dimensions: | |
7193 | * target_el_table[2][2][2][2][2][4] | |
7194 | * | | | | | +--- Current EL | |
7195 | * | | | | +------ Non-secure(0)/Secure(1) | |
7196 | * | | | +--------- HCR mask override | |
7197 | * | | +------------ SCR exec state control | |
7198 | * | +--------------- SCR mask override | |
7199 | * +------------------ 32-bit(0)/64-bit(1) EL3 | |
7200 | * | |
7201 | * The table values are as such: | |
7202 | * 0-3 = EL0-EL3 | |
7203 | * -1 = Cannot occur | |
7204 | * | |
7205 | * The ARM ARM target EL table includes entries indicating that an "exception | |
7206 | * is not taken". The two cases where this is applicable are: | |
7207 | * 1) An exception is taken from EL3 but the SCR does not have the exception | |
7208 | * routed to EL3. | |
7209 | * 2) An exception is taken from EL2 but the HCR does not have the exception | |
7210 | * routed to EL2. | |
7211 | * In these two cases, the below table contain a target of EL1. This value is | |
7212 | * returned as it is expected that the consumer of the table data will check | |
7213 | * for "target EL >= current EL" to ensure the exception is not taken. | |
7214 | * | |
7215 | * SCR HCR | |
7216 | * 64 EA AMO From | |
7217 | * BIT IRQ IMO Non-secure Secure | |
7218 | * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 | |
7219 | */ | |
82c39f6a | 7220 | static const int8_t target_el_table[2][2][2][2][2][4] = { |
0eeb17d6 GB |
7221 | {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, |
7222 | {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, | |
7223 | {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, | |
7224 | {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, | |
7225 | {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
7226 | {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, | |
7227 | {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
7228 | {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, | |
7229 | {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, | |
7230 | {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},}, | |
7231 | {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },}, | |
7232 | {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},}, | |
7233 | {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, | |
7234 | {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, | |
7235 | {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, | |
7236 | {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},}, | |
7237 | }; | |
7238 | ||
7239 | /* | |
7240 | * Determine the target EL for physical exceptions | |
7241 | */ | |
012a906b GB |
7242 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
7243 | uint32_t cur_el, bool secure) | |
0eeb17d6 GB |
7244 | { |
7245 | CPUARMState *env = cs->env_ptr; | |
f7778444 RH |
7246 | bool rw; |
7247 | bool scr; | |
7248 | bool hcr; | |
0eeb17d6 | 7249 | int target_el; |
2cde031f | 7250 | /* Is the highest EL AArch64? */ |
f7778444 RH |
7251 | bool is64 = arm_feature(env, ARM_FEATURE_AARCH64); |
7252 | uint64_t hcr_el2; | |
2cde031f SS |
7253 | |
7254 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
7255 | rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); | |
7256 | } else { | |
7257 | /* Either EL2 is the highest EL (and so the EL2 register width | |
7258 | * is given by is64); or there is no EL2 or EL3, in which case | |
7259 | * the value of 'rw' does not affect the table lookup anyway. | |
7260 | */ | |
7261 | rw = is64; | |
7262 | } | |
0eeb17d6 | 7263 | |
f7778444 | 7264 | hcr_el2 = arm_hcr_el2_eff(env); |
0eeb17d6 GB |
7265 | switch (excp_idx) { |
7266 | case EXCP_IRQ: | |
7267 | scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); | |
f7778444 | 7268 | hcr = hcr_el2 & HCR_IMO; |
0eeb17d6 GB |
7269 | break; |
7270 | case EXCP_FIQ: | |
7271 | scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); | |
f7778444 | 7272 | hcr = hcr_el2 & HCR_FMO; |
0eeb17d6 GB |
7273 | break; |
7274 | default: | |
7275 | scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); | |
f7778444 | 7276 | hcr = hcr_el2 & HCR_AMO; |
0eeb17d6 GB |
7277 | break; |
7278 | }; | |
7279 | ||
0eeb17d6 GB |
7280 | /* Perform a table-lookup for the target EL given the current state */ |
7281 | target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; | |
7282 | ||
7283 | assert(target_el > 0); | |
7284 | ||
7285 | return target_el; | |
7286 | } | |
7287 | ||
fd592d89 PM |
7288 | static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, |
7289 | ARMMMUIdx mmu_idx, bool ignfault) | |
9ee6e8bb | 7290 | { |
fd592d89 PM |
7291 | CPUState *cs = CPU(cpu); |
7292 | CPUARMState *env = &cpu->env; | |
7293 | MemTxAttrs attrs = {}; | |
7294 | MemTxResult txres; | |
7295 | target_ulong page_size; | |
7296 | hwaddr physaddr; | |
7297 | int prot; | |
ab44c7b7 | 7298 | ARMMMUFaultInfo fi = {}; |
fd592d89 PM |
7299 | bool secure = mmu_idx & ARM_MMU_IDX_M_S; |
7300 | int exc; | |
7301 | bool exc_secure; | |
7302 | ||
7303 | if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &physaddr, | |
7304 | &attrs, &prot, &page_size, &fi, NULL)) { | |
7305 | /* MPU/SAU lookup failed */ | |
7306 | if (fi.type == ARMFault_QEMU_SFault) { | |
7307 | qemu_log_mask(CPU_LOG_INT, | |
7308 | "...SecureFault with SFSR.AUVIOL during stacking\n"); | |
7309 | env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVALID_MASK; | |
7310 | env->v7m.sfar = addr; | |
7311 | exc = ARMV7M_EXCP_SECURE; | |
7312 | exc_secure = false; | |
7313 | } else { | |
7314 | qemu_log_mask(CPU_LOG_INT, "...MemManageFault with CFSR.MSTKERR\n"); | |
7315 | env->v7m.cfsr[secure] |= R_V7M_CFSR_MSTKERR_MASK; | |
7316 | exc = ARMV7M_EXCP_MEM; | |
7317 | exc_secure = secure; | |
7318 | } | |
7319 | goto pend_fault; | |
7320 | } | |
7321 | address_space_stl_le(arm_addressspace(cs, attrs), physaddr, value, | |
7322 | attrs, &txres); | |
7323 | if (txres != MEMTX_OK) { | |
7324 | /* BusFault trying to write the data */ | |
7325 | qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.STKERR\n"); | |
7326 | env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_STKERR_MASK; | |
7327 | exc = ARMV7M_EXCP_BUS; | |
7328 | exc_secure = false; | |
7329 | goto pend_fault; | |
7330 | } | |
7331 | return true; | |
70d74660 | 7332 | |
fd592d89 PM |
7333 | pend_fault: |
7334 | /* By pending the exception at this point we are making | |
7335 | * the IMPDEF choice "overridden exceptions pended" (see the | |
7336 | * MergeExcInfo() pseudocode). The other choice would be to not | |
7337 | * pend them now and then make a choice about which to throw away | |
7338 | * later if we have two derived exceptions. | |
7339 | * The only case when we must not pend the exception but instead | |
7340 | * throw it away is if we are doing the push of the callee registers | |
7341 | * and we've already generated a derived exception. Even in this | |
7342 | * case we will still update the fault status registers. | |
7343 | */ | |
7344 | if (!ignfault) { | |
7345 | armv7m_nvic_set_pending_derived(env->nvic, exc, exc_secure); | |
7346 | } | |
7347 | return false; | |
9ee6e8bb PB |
7348 | } |
7349 | ||
95695eff PM |
7350 | static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr, |
7351 | ARMMMUIdx mmu_idx) | |
7352 | { | |
7353 | CPUState *cs = CPU(cpu); | |
7354 | CPUARMState *env = &cpu->env; | |
7355 | MemTxAttrs attrs = {}; | |
7356 | MemTxResult txres; | |
7357 | target_ulong page_size; | |
7358 | hwaddr physaddr; | |
7359 | int prot; | |
ab44c7b7 | 7360 | ARMMMUFaultInfo fi = {}; |
95695eff PM |
7361 | bool secure = mmu_idx & ARM_MMU_IDX_M_S; |
7362 | int exc; | |
7363 | bool exc_secure; | |
7364 | uint32_t value; | |
7365 | ||
7366 | if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr, | |
7367 | &attrs, &prot, &page_size, &fi, NULL)) { | |
7368 | /* MPU/SAU lookup failed */ | |
7369 | if (fi.type == ARMFault_QEMU_SFault) { | |
7370 | qemu_log_mask(CPU_LOG_INT, | |
7371 | "...SecureFault with SFSR.AUVIOL during unstack\n"); | |
7372 | env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVALID_MASK; | |
7373 | env->v7m.sfar = addr; | |
7374 | exc = ARMV7M_EXCP_SECURE; | |
7375 | exc_secure = false; | |
7376 | } else { | |
7377 | qemu_log_mask(CPU_LOG_INT, | |
7378 | "...MemManageFault with CFSR.MUNSTKERR\n"); | |
7379 | env->v7m.cfsr[secure] |= R_V7M_CFSR_MUNSTKERR_MASK; | |
7380 | exc = ARMV7M_EXCP_MEM; | |
7381 | exc_secure = secure; | |
7382 | } | |
7383 | goto pend_fault; | |
7384 | } | |
7385 | ||
7386 | value = address_space_ldl(arm_addressspace(cs, attrs), physaddr, | |
7387 | attrs, &txres); | |
7388 | if (txres != MEMTX_OK) { | |
7389 | /* BusFault trying to read the data */ | |
7390 | qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n"); | |
7391 | env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_UNSTKERR_MASK; | |
7392 | exc = ARMV7M_EXCP_BUS; | |
7393 | exc_secure = false; | |
7394 | goto pend_fault; | |
7395 | } | |
7396 | ||
7397 | *dest = value; | |
7398 | return true; | |
7399 | ||
7400 | pend_fault: | |
7401 | /* By pending the exception at this point we are making | |
7402 | * the IMPDEF choice "overridden exceptions pended" (see the | |
7403 | * MergeExcInfo() pseudocode). The other choice would be to not | |
7404 | * pend them now and then make a choice about which to throw away | |
7405 | * later if we have two derived exceptions. | |
7406 | */ | |
7407 | armv7m_nvic_set_pending(env->nvic, exc, exc_secure); | |
7408 | return false; | |
7409 | } | |
7410 | ||
3f0cddee PM |
7411 | /* Write to v7M CONTROL.SPSEL bit for the specified security bank. |
7412 | * This may change the current stack pointer between Main and Process | |
7413 | * stack pointers if it is done for the CONTROL register for the current | |
7414 | * security state. | |
de2db7ec | 7415 | */ |
3f0cddee PM |
7416 | static void write_v7m_control_spsel_for_secstate(CPUARMState *env, |
7417 | bool new_spsel, | |
7418 | bool secstate) | |
9ee6e8bb | 7419 | { |
3f0cddee | 7420 | bool old_is_psp = v7m_using_psp(env); |
de2db7ec | 7421 | |
3f0cddee PM |
7422 | env->v7m.control[secstate] = |
7423 | deposit32(env->v7m.control[secstate], | |
de2db7ec PM |
7424 | R_V7M_CONTROL_SPSEL_SHIFT, |
7425 | R_V7M_CONTROL_SPSEL_LENGTH, new_spsel); | |
7426 | ||
3f0cddee PM |
7427 | if (secstate == env->v7m.secure) { |
7428 | bool new_is_psp = v7m_using_psp(env); | |
7429 | uint32_t tmp; | |
abc24d86 | 7430 | |
3f0cddee PM |
7431 | if (old_is_psp != new_is_psp) { |
7432 | tmp = env->v7m.other_sp; | |
7433 | env->v7m.other_sp = env->regs[13]; | |
7434 | env->regs[13] = tmp; | |
7435 | } | |
de2db7ec PM |
7436 | } |
7437 | } | |
7438 | ||
3f0cddee PM |
7439 | /* Write to v7M CONTROL.SPSEL bit. This may change the current |
7440 | * stack pointer between Main and Process stack pointers. | |
7441 | */ | |
7442 | static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel) | |
7443 | { | |
7444 | write_v7m_control_spsel_for_secstate(env, new_spsel, env->v7m.secure); | |
7445 | } | |
7446 | ||
de2db7ec PM |
7447 | void write_v7m_exception(CPUARMState *env, uint32_t new_exc) |
7448 | { | |
7449 | /* Write a new value to v7m.exception, thus transitioning into or out | |
7450 | * of Handler mode; this may result in a change of active stack pointer. | |
7451 | */ | |
7452 | bool new_is_psp, old_is_psp = v7m_using_psp(env); | |
7453 | uint32_t tmp; | |
abc24d86 | 7454 | |
de2db7ec PM |
7455 | env->v7m.exception = new_exc; |
7456 | ||
7457 | new_is_psp = v7m_using_psp(env); | |
7458 | ||
7459 | if (old_is_psp != new_is_psp) { | |
7460 | tmp = env->v7m.other_sp; | |
7461 | env->v7m.other_sp = env->regs[13]; | |
7462 | env->regs[13] = tmp; | |
9ee6e8bb PB |
7463 | } |
7464 | } | |
7465 | ||
fb602cb7 PM |
7466 | /* Switch M profile security state between NS and S */ |
7467 | static void switch_v7m_security_state(CPUARMState *env, bool new_secstate) | |
7468 | { | |
7469 | uint32_t new_ss_msp, new_ss_psp; | |
7470 | ||
7471 | if (env->v7m.secure == new_secstate) { | |
7472 | return; | |
7473 | } | |
7474 | ||
7475 | /* All the banked state is accessed by looking at env->v7m.secure | |
7476 | * except for the stack pointer; rearrange the SP appropriately. | |
7477 | */ | |
7478 | new_ss_msp = env->v7m.other_ss_msp; | |
7479 | new_ss_psp = env->v7m.other_ss_psp; | |
7480 | ||
7481 | if (v7m_using_psp(env)) { | |
7482 | env->v7m.other_ss_psp = env->regs[13]; | |
7483 | env->v7m.other_ss_msp = env->v7m.other_sp; | |
7484 | } else { | |
7485 | env->v7m.other_ss_msp = env->regs[13]; | |
7486 | env->v7m.other_ss_psp = env->v7m.other_sp; | |
7487 | } | |
7488 | ||
7489 | env->v7m.secure = new_secstate; | |
7490 | ||
7491 | if (v7m_using_psp(env)) { | |
7492 | env->regs[13] = new_ss_psp; | |
7493 | env->v7m.other_sp = new_ss_msp; | |
7494 | } else { | |
7495 | env->regs[13] = new_ss_msp; | |
7496 | env->v7m.other_sp = new_ss_psp; | |
7497 | } | |
7498 | } | |
7499 | ||
7500 | void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) | |
7501 | { | |
7502 | /* Handle v7M BXNS: | |
7503 | * - if the return value is a magic value, do exception return (like BX) | |
7504 | * - otherwise bit 0 of the return value is the target security state | |
7505 | */ | |
d02a8698 PM |
7506 | uint32_t min_magic; |
7507 | ||
7508 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
7509 | /* Covers FNC_RETURN and EXC_RETURN magic */ | |
7510 | min_magic = FNC_RETURN_MIN_MAGIC; | |
7511 | } else { | |
7512 | /* EXC_RETURN magic only */ | |
7513 | min_magic = EXC_RETURN_MIN_MAGIC; | |
7514 | } | |
7515 | ||
7516 | if (dest >= min_magic) { | |
fb602cb7 PM |
7517 | /* This is an exception return magic value; put it where |
7518 | * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT. | |
7519 | * Note that if we ever add gen_ss_advance() singlestep support to | |
7520 | * M profile this should count as an "instruction execution complete" | |
7521 | * event (compare gen_bx_excret_final_code()). | |
7522 | */ | |
7523 | env->regs[15] = dest & ~1; | |
7524 | env->thumb = dest & 1; | |
7525 | HELPER(exception_internal)(env, EXCP_EXCEPTION_EXIT); | |
7526 | /* notreached */ | |
7527 | } | |
7528 | ||
7529 | /* translate.c should have made BXNS UNDEF unless we're secure */ | |
7530 | assert(env->v7m.secure); | |
7531 | ||
7532 | switch_v7m_security_state(env, dest & 1); | |
7533 | env->thumb = 1; | |
7534 | env->regs[15] = dest & ~1; | |
7535 | } | |
7536 | ||
3e3fa230 PM |
7537 | void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) |
7538 | { | |
7539 | /* Handle v7M BLXNS: | |
7540 | * - bit 0 of the destination address is the target security state | |
7541 | */ | |
7542 | ||
7543 | /* At this point regs[15] is the address just after the BLXNS */ | |
7544 | uint32_t nextinst = env->regs[15] | 1; | |
7545 | uint32_t sp = env->regs[13] - 8; | |
7546 | uint32_t saved_psr; | |
7547 | ||
7548 | /* translate.c will have made BLXNS UNDEF unless we're secure */ | |
7549 | assert(env->v7m.secure); | |
7550 | ||
7551 | if (dest & 1) { | |
7552 | /* target is Secure, so this is just a normal BLX, | |
7553 | * except that the low bit doesn't indicate Thumb/not. | |
7554 | */ | |
7555 | env->regs[14] = nextinst; | |
7556 | env->thumb = 1; | |
7557 | env->regs[15] = dest & ~1; | |
7558 | return; | |
7559 | } | |
7560 | ||
7561 | /* Target is non-secure: first push a stack frame */ | |
7562 | if (!QEMU_IS_ALIGNED(sp, 8)) { | |
7563 | qemu_log_mask(LOG_GUEST_ERROR, | |
7564 | "BLXNS with misaligned SP is UNPREDICTABLE\n"); | |
7565 | } | |
7566 | ||
597610eb PM |
7567 | if (sp < v7m_sp_limit(env)) { |
7568 | raise_exception(env, EXCP_STKOF, 0, 1); | |
7569 | } | |
7570 | ||
3e3fa230 PM |
7571 | saved_psr = env->v7m.exception; |
7572 | if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK) { | |
7573 | saved_psr |= XPSR_SFPA; | |
7574 | } | |
7575 | ||
7576 | /* Note that these stores can throw exceptions on MPU faults */ | |
7577 | cpu_stl_data(env, sp, nextinst); | |
7578 | cpu_stl_data(env, sp + 4, saved_psr); | |
7579 | ||
7580 | env->regs[13] = sp; | |
7581 | env->regs[14] = 0xfeffffff; | |
7582 | if (arm_v7m_is_handler_mode(env)) { | |
7583 | /* Write a dummy value to IPSR, to avoid leaking the current secure | |
7584 | * exception number to non-secure code. This is guaranteed not | |
7585 | * to cause write_v7m_exception() to actually change stacks. | |
7586 | */ | |
7587 | write_v7m_exception(env, 1); | |
7588 | } | |
7589 | switch_v7m_security_state(env, 0); | |
7590 | env->thumb = 1; | |
7591 | env->regs[15] = dest; | |
7592 | } | |
7593 | ||
5b522399 PM |
7594 | static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode, |
7595 | bool spsel) | |
7596 | { | |
7597 | /* Return a pointer to the location where we currently store the | |
7598 | * stack pointer for the requested security state and thread mode. | |
7599 | * This pointer will become invalid if the CPU state is updated | |
7600 | * such that the stack pointers are switched around (eg changing | |
7601 | * the SPSEL control bit). | |
7602 | * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode(). | |
7603 | * Unlike that pseudocode, we require the caller to pass us in the | |
7604 | * SPSEL control bit value; this is because we also use this | |
7605 | * function in handling of pushing of the callee-saves registers | |
7606 | * part of the v8M stack frame (pseudocode PushCalleeStack()), | |
7607 | * and in the tailchain codepath the SPSEL bit comes from the exception | |
7608 | * return magic LR value from the previous exception. The pseudocode | |
7609 | * opencodes the stack-selection in PushCalleeStack(), but we prefer | |
7610 | * to make this utility function generic enough to do the job. | |
7611 | */ | |
7612 | bool want_psp = threadmode && spsel; | |
7613 | ||
7614 | if (secure == env->v7m.secure) { | |
de2db7ec PM |
7615 | if (want_psp == v7m_using_psp(env)) { |
7616 | return &env->regs[13]; | |
7617 | } else { | |
7618 | return &env->v7m.other_sp; | |
7619 | } | |
5b522399 PM |
7620 | } else { |
7621 | if (want_psp) { | |
7622 | return &env->v7m.other_ss_psp; | |
7623 | } else { | |
7624 | return &env->v7m.other_ss_msp; | |
7625 | } | |
7626 | } | |
7627 | } | |
7628 | ||
600c33f2 PM |
7629 | static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure, |
7630 | uint32_t *pvec) | |
39ae2474 PM |
7631 | { |
7632 | CPUState *cs = CPU(cpu); | |
7633 | CPUARMState *env = &cpu->env; | |
7634 | MemTxResult result; | |
600c33f2 PM |
7635 | uint32_t addr = env->v7m.vecbase[targets_secure] + exc * 4; |
7636 | uint32_t vector_entry; | |
7637 | MemTxAttrs attrs = {}; | |
7638 | ARMMMUIdx mmu_idx; | |
7639 | bool exc_secure; | |
7640 | ||
7641 | mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, targets_secure, true); | |
39ae2474 | 7642 | |
600c33f2 PM |
7643 | /* We don't do a get_phys_addr() here because the rules for vector |
7644 | * loads are special: they always use the default memory map, and | |
7645 | * the default memory map permits reads from all addresses. | |
7646 | * Since there's no easy way to pass through to pmsav8_mpu_lookup() | |
7647 | * that we want this special case which would always say "yes", | |
7648 | * we just do the SAU lookup here followed by a direct physical load. | |
7649 | */ | |
7650 | attrs.secure = targets_secure; | |
7651 | attrs.user = false; | |
7652 | ||
7653 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
7654 | V8M_SAttributes sattrs = {}; | |
7655 | ||
7656 | v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs); | |
7657 | if (sattrs.ns) { | |
7658 | attrs.secure = false; | |
7659 | } else if (!targets_secure) { | |
7660 | /* NS access to S memory */ | |
7661 | goto load_fail; | |
7662 | } | |
7663 | } | |
7664 | ||
7665 | vector_entry = address_space_ldl(arm_addressspace(cs, attrs), addr, | |
7666 | attrs, &result); | |
39ae2474 | 7667 | if (result != MEMTX_OK) { |
600c33f2 | 7668 | goto load_fail; |
39ae2474 | 7669 | } |
600c33f2 PM |
7670 | *pvec = vector_entry; |
7671 | return true; | |
7672 | ||
7673 | load_fail: | |
7674 | /* All vector table fetch fails are reported as HardFault, with | |
7675 | * HFSR.VECTTBL and .FORCED set. (FORCED is set because | |
7676 | * technically the underlying exception is a MemManage or BusFault | |
7677 | * that is escalated to HardFault.) This is a terminal exception, | |
7678 | * so we will either take the HardFault immediately or else enter | |
7679 | * lockup (the latter case is handled in armv7m_nvic_set_pending_derived()). | |
7680 | */ | |
7681 | exc_secure = targets_secure || | |
7682 | !(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK); | |
7683 | env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK | R_V7M_HFSR_FORCED_MASK; | |
7684 | armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secure); | |
7685 | return false; | |
39ae2474 PM |
7686 | } |
7687 | ||
65b4234f | 7688 | static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, |
0094ca70 | 7689 | bool ignore_faults) |
d3392718 PM |
7690 | { |
7691 | /* For v8M, push the callee-saves register part of the stack frame. | |
7692 | * Compare the v8M pseudocode PushCalleeStack(). | |
7693 | * In the tailchaining case this may not be the current stack. | |
7694 | */ | |
7695 | CPUARMState *env = &cpu->env; | |
d3392718 PM |
7696 | uint32_t *frame_sp_p; |
7697 | uint32_t frameptr; | |
65b4234f PM |
7698 | ARMMMUIdx mmu_idx; |
7699 | bool stacked_ok; | |
c32da7aa PM |
7700 | uint32_t limit; |
7701 | bool want_psp; | |
d3392718 PM |
7702 | |
7703 | if (dotailchain) { | |
65b4234f PM |
7704 | bool mode = lr & R_V7M_EXCRET_MODE_MASK; |
7705 | bool priv = !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_NPRIV_MASK) || | |
7706 | !mode; | |
7707 | ||
7708 | mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, priv); | |
7709 | frame_sp_p = get_v7m_sp_ptr(env, M_REG_S, mode, | |
d3392718 | 7710 | lr & R_V7M_EXCRET_SPSEL_MASK); |
c32da7aa PM |
7711 | want_psp = mode && (lr & R_V7M_EXCRET_SPSEL_MASK); |
7712 | if (want_psp) { | |
7713 | limit = env->v7m.psplim[M_REG_S]; | |
7714 | } else { | |
7715 | limit = env->v7m.msplim[M_REG_S]; | |
7716 | } | |
d3392718 | 7717 | } else { |
50494a27 | 7718 | mmu_idx = arm_mmu_idx(env); |
d3392718 | 7719 | frame_sp_p = &env->regs[13]; |
c32da7aa | 7720 | limit = v7m_sp_limit(env); |
d3392718 PM |
7721 | } |
7722 | ||
7723 | frameptr = *frame_sp_p - 0x28; | |
c32da7aa PM |
7724 | if (frameptr < limit) { |
7725 | /* | |
7726 | * Stack limit failure: set SP to the limit value, and generate | |
7727 | * STKOF UsageFault. Stack pushes below the limit must not be | |
7728 | * performed. It is IMPDEF whether pushes above the limit are | |
7729 | * performed; we choose not to. | |
7730 | */ | |
7731 | qemu_log_mask(CPU_LOG_INT, | |
7732 | "...STKOF during callee-saves register stacking\n"); | |
7733 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_STKOF_MASK; | |
7734 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, | |
7735 | env->v7m.secure); | |
7736 | *frame_sp_p = limit; | |
7737 | return true; | |
7738 | } | |
d3392718 | 7739 | |
65b4234f PM |
7740 | /* Write as much of the stack frame as we can. A write failure may |
7741 | * cause us to pend a derived exception. | |
7742 | */ | |
7743 | stacked_ok = | |
7744 | v7m_stack_write(cpu, frameptr, 0xfefa125b, mmu_idx, ignore_faults) && | |
7745 | v7m_stack_write(cpu, frameptr + 0x8, env->regs[4], mmu_idx, | |
7746 | ignore_faults) && | |
7747 | v7m_stack_write(cpu, frameptr + 0xc, env->regs[5], mmu_idx, | |
7748 | ignore_faults) && | |
7749 | v7m_stack_write(cpu, frameptr + 0x10, env->regs[6], mmu_idx, | |
7750 | ignore_faults) && | |
7751 | v7m_stack_write(cpu, frameptr + 0x14, env->regs[7], mmu_idx, | |
7752 | ignore_faults) && | |
7753 | v7m_stack_write(cpu, frameptr + 0x18, env->regs[8], mmu_idx, | |
7754 | ignore_faults) && | |
7755 | v7m_stack_write(cpu, frameptr + 0x1c, env->regs[9], mmu_idx, | |
7756 | ignore_faults) && | |
7757 | v7m_stack_write(cpu, frameptr + 0x20, env->regs[10], mmu_idx, | |
7758 | ignore_faults) && | |
7759 | v7m_stack_write(cpu, frameptr + 0x24, env->regs[11], mmu_idx, | |
7760 | ignore_faults); | |
7761 | ||
c32da7aa | 7762 | /* Update SP regardless of whether any of the stack accesses failed. */ |
d3392718 | 7763 | *frame_sp_p = frameptr; |
65b4234f PM |
7764 | |
7765 | return !stacked_ok; | |
d3392718 PM |
7766 | } |
7767 | ||
0094ca70 PM |
7768 | static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain, |
7769 | bool ignore_stackfaults) | |
39ae2474 PM |
7770 | { |
7771 | /* Do the "take the exception" parts of exception entry, | |
7772 | * but not the pushing of state to the stack. This is | |
7773 | * similar to the pseudocode ExceptionTaken() function. | |
7774 | */ | |
7775 | CPUARMState *env = &cpu->env; | |
7776 | uint32_t addr; | |
d3392718 | 7777 | bool targets_secure; |
6c948518 | 7778 | int exc; |
65b4234f | 7779 | bool push_failed = false; |
d3392718 | 7780 | |
6c948518 | 7781 | armv7m_nvic_get_pending_irq_info(env->nvic, &exc, &targets_secure); |
a9074977 PM |
7782 | qemu_log_mask(CPU_LOG_INT, "...taking pending %s exception %d\n", |
7783 | targets_secure ? "secure" : "nonsecure", exc); | |
d3392718 PM |
7784 | |
7785 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
7786 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && | |
7787 | (lr & R_V7M_EXCRET_S_MASK)) { | |
7788 | /* The background code (the owner of the registers in the | |
7789 | * exception frame) is Secure. This means it may either already | |
7790 | * have or now needs to push callee-saves registers. | |
7791 | */ | |
7792 | if (targets_secure) { | |
7793 | if (dotailchain && !(lr & R_V7M_EXCRET_ES_MASK)) { | |
7794 | /* We took an exception from Secure to NonSecure | |
7795 | * (which means the callee-saved registers got stacked) | |
7796 | * and are now tailchaining to a Secure exception. | |
7797 | * Clear DCRS so eventual return from this Secure | |
7798 | * exception unstacks the callee-saved registers. | |
7799 | */ | |
7800 | lr &= ~R_V7M_EXCRET_DCRS_MASK; | |
7801 | } | |
7802 | } else { | |
7803 | /* We're going to a non-secure exception; push the | |
7804 | * callee-saves registers to the stack now, if they're | |
7805 | * not already saved. | |
7806 | */ | |
7807 | if (lr & R_V7M_EXCRET_DCRS_MASK && | |
7b73a1ca | 7808 | !(dotailchain && !(lr & R_V7M_EXCRET_ES_MASK))) { |
65b4234f PM |
7809 | push_failed = v7m_push_callee_stack(cpu, lr, dotailchain, |
7810 | ignore_stackfaults); | |
d3392718 PM |
7811 | } |
7812 | lr |= R_V7M_EXCRET_DCRS_MASK; | |
7813 | } | |
7814 | } | |
7815 | ||
7816 | lr &= ~R_V7M_EXCRET_ES_MASK; | |
7817 | if (targets_secure || !arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
7818 | lr |= R_V7M_EXCRET_ES_MASK; | |
7819 | } | |
7820 | lr &= ~R_V7M_EXCRET_SPSEL_MASK; | |
7821 | if (env->v7m.control[targets_secure] & R_V7M_CONTROL_SPSEL_MASK) { | |
7822 | lr |= R_V7M_EXCRET_SPSEL_MASK; | |
7823 | } | |
7824 | ||
7825 | /* Clear registers if necessary to prevent non-secure exception | |
7826 | * code being able to see register values from secure code. | |
7827 | * Where register values become architecturally UNKNOWN we leave | |
7828 | * them with their previous values. | |
7829 | */ | |
7830 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
7831 | if (!targets_secure) { | |
7832 | /* Always clear the caller-saved registers (they have been | |
7833 | * pushed to the stack earlier in v7m_push_stack()). | |
7834 | * Clear callee-saved registers if the background code is | |
7835 | * Secure (in which case these regs were saved in | |
7836 | * v7m_push_callee_stack()). | |
7837 | */ | |
7838 | int i; | |
7839 | ||
7840 | for (i = 0; i < 13; i++) { | |
7841 | /* r4..r11 are callee-saves, zero only if EXCRET.S == 1 */ | |
7842 | if (i < 4 || i > 11 || (lr & R_V7M_EXCRET_S_MASK)) { | |
7843 | env->regs[i] = 0; | |
7844 | } | |
7845 | } | |
7846 | /* Clear EAPSR */ | |
7847 | xpsr_write(env, 0, XPSR_NZCV | XPSR_Q | XPSR_GE | XPSR_IT); | |
7848 | } | |
7849 | } | |
7850 | } | |
39ae2474 | 7851 | |
65b4234f PM |
7852 | if (push_failed && !ignore_stackfaults) { |
7853 | /* Derived exception on callee-saves register stacking: | |
7854 | * we might now want to take a different exception which | |
7855 | * targets a different security state, so try again from the top. | |
7856 | */ | |
a9074977 PM |
7857 | qemu_log_mask(CPU_LOG_INT, |
7858 | "...derived exception on callee-saves register stacking"); | |
65b4234f PM |
7859 | v7m_exception_taken(cpu, lr, true, true); |
7860 | return; | |
7861 | } | |
7862 | ||
600c33f2 PM |
7863 | if (!arm_v7m_load_vector(cpu, exc, targets_secure, &addr)) { |
7864 | /* Vector load failed: derived exception */ | |
a9074977 | 7865 | qemu_log_mask(CPU_LOG_INT, "...derived exception on vector table load"); |
600c33f2 PM |
7866 | v7m_exception_taken(cpu, lr, true, true); |
7867 | return; | |
7868 | } | |
6c948518 PM |
7869 | |
7870 | /* Now we've done everything that might cause a derived exception | |
7871 | * we can go ahead and activate whichever exception we're going to | |
7872 | * take (which might now be the derived exception). | |
7873 | */ | |
7874 | armv7m_nvic_acknowledge_irq(env->nvic); | |
7875 | ||
d3392718 PM |
7876 | /* Switch to target security state -- must do this before writing SPSEL */ |
7877 | switch_v7m_security_state(env, targets_secure); | |
de2db7ec | 7878 | write_v7m_control_spsel(env, 0); |
dc3c4c14 | 7879 | arm_clear_exclusive(env); |
39ae2474 PM |
7880 | /* Clear IT bits */ |
7881 | env->condexec_bits = 0; | |
7882 | env->regs[14] = lr; | |
39ae2474 PM |
7883 | env->regs[15] = addr & 0xfffffffe; |
7884 | env->thumb = addr & 1; | |
7885 | } | |
7886 | ||
0094ca70 | 7887 | static bool v7m_push_stack(ARMCPU *cpu) |
39ae2474 PM |
7888 | { |
7889 | /* Do the "set up stack frame" part of exception entry, | |
7890 | * similar to pseudocode PushStack(). | |
0094ca70 PM |
7891 | * Return true if we generate a derived exception (and so |
7892 | * should ignore further stack faults trying to process | |
7893 | * that derived exception.) | |
39ae2474 | 7894 | */ |
fd592d89 | 7895 | bool stacked_ok; |
39ae2474 PM |
7896 | CPUARMState *env = &cpu->env; |
7897 | uint32_t xpsr = xpsr_read(env); | |
fd592d89 | 7898 | uint32_t frameptr = env->regs[13]; |
50494a27 | 7899 | ARMMMUIdx mmu_idx = arm_mmu_idx(env); |
39ae2474 PM |
7900 | |
7901 | /* Align stack pointer if the guest wants that */ | |
fd592d89 | 7902 | if ((frameptr & 4) && |
9d40cd8a | 7903 | (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKALIGN_MASK)) { |
fd592d89 | 7904 | frameptr -= 4; |
987ab45e | 7905 | xpsr |= XPSR_SPREALIGN; |
39ae2474 | 7906 | } |
0094ca70 | 7907 | |
fd592d89 PM |
7908 | frameptr -= 0x20; |
7909 | ||
c32da7aa PM |
7910 | if (arm_feature(env, ARM_FEATURE_V8)) { |
7911 | uint32_t limit = v7m_sp_limit(env); | |
7912 | ||
7913 | if (frameptr < limit) { | |
7914 | /* | |
7915 | * Stack limit failure: set SP to the limit value, and generate | |
7916 | * STKOF UsageFault. Stack pushes below the limit must not be | |
7917 | * performed. It is IMPDEF whether pushes above the limit are | |
7918 | * performed; we choose not to. | |
7919 | */ | |
7920 | qemu_log_mask(CPU_LOG_INT, | |
7921 | "...STKOF during stacking\n"); | |
7922 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_STKOF_MASK; | |
7923 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, | |
7924 | env->v7m.secure); | |
7925 | env->regs[13] = limit; | |
7926 | return true; | |
7927 | } | |
7928 | } | |
7929 | ||
fd592d89 PM |
7930 | /* Write as much of the stack frame as we can. If we fail a stack |
7931 | * write this will result in a derived exception being pended | |
7932 | * (which may be taken in preference to the one we started with | |
7933 | * if it has higher priority). | |
7934 | */ | |
7935 | stacked_ok = | |
7936 | v7m_stack_write(cpu, frameptr, env->regs[0], mmu_idx, false) && | |
7937 | v7m_stack_write(cpu, frameptr + 4, env->regs[1], mmu_idx, false) && | |
7938 | v7m_stack_write(cpu, frameptr + 8, env->regs[2], mmu_idx, false) && | |
7939 | v7m_stack_write(cpu, frameptr + 12, env->regs[3], mmu_idx, false) && | |
7940 | v7m_stack_write(cpu, frameptr + 16, env->regs[12], mmu_idx, false) && | |
7941 | v7m_stack_write(cpu, frameptr + 20, env->regs[14], mmu_idx, false) && | |
7942 | v7m_stack_write(cpu, frameptr + 24, env->regs[15], mmu_idx, false) && | |
7943 | v7m_stack_write(cpu, frameptr + 28, xpsr, mmu_idx, false); | |
7944 | ||
c32da7aa | 7945 | /* Update SP regardless of whether any of the stack accesses failed. */ |
fd592d89 PM |
7946 | env->regs[13] = frameptr; |
7947 | ||
7948 | return !stacked_ok; | |
39ae2474 PM |
7949 | } |
7950 | ||
aa488fe3 | 7951 | static void do_v7m_exception_exit(ARMCPU *cpu) |
9ee6e8bb | 7952 | { |
aa488fe3 | 7953 | CPUARMState *env = &cpu->env; |
351e527a | 7954 | uint32_t excret; |
9ee6e8bb | 7955 | uint32_t xpsr; |
aa488fe3 | 7956 | bool ufault = false; |
bfb2eb52 PM |
7957 | bool sfault = false; |
7958 | bool return_to_sp_process; | |
7959 | bool return_to_handler; | |
aa488fe3 | 7960 | bool rettobase = false; |
5cb18069 | 7961 | bool exc_secure = false; |
5b522399 | 7962 | bool return_to_secure; |
aa488fe3 | 7963 | |
d02a8698 PM |
7964 | /* If we're not in Handler mode then jumps to magic exception-exit |
7965 | * addresses don't have magic behaviour. However for the v8M | |
7966 | * security extensions the magic secure-function-return has to | |
7967 | * work in thread mode too, so to avoid doing an extra check in | |
7968 | * the generated code we allow exception-exit magic to also cause the | |
7969 | * internal exception and bring us here in thread mode. Correct code | |
7970 | * will never try to do this (the following insn fetch will always | |
7971 | * fault) so we the overhead of having taken an unnecessary exception | |
7972 | * doesn't matter. | |
aa488fe3 | 7973 | */ |
d02a8698 PM |
7974 | if (!arm_v7m_is_handler_mode(env)) { |
7975 | return; | |
7976 | } | |
aa488fe3 PM |
7977 | |
7978 | /* In the spec pseudocode ExceptionReturn() is called directly | |
7979 | * from BXWritePC() and gets the full target PC value including | |
7980 | * bit zero. In QEMU's implementation we treat it as a normal | |
7981 | * jump-to-register (which is then caught later on), and so split | |
7982 | * the target value up between env->regs[15] and env->thumb in | |
7983 | * gen_bx(). Reconstitute it. | |
7984 | */ | |
351e527a | 7985 | excret = env->regs[15]; |
aa488fe3 | 7986 | if (env->thumb) { |
351e527a | 7987 | excret |= 1; |
aa488fe3 PM |
7988 | } |
7989 | ||
7990 | qemu_log_mask(CPU_LOG_INT, "Exception return: magic PC %" PRIx32 | |
7991 | " previous exception %d\n", | |
351e527a | 7992 | excret, env->v7m.exception); |
aa488fe3 | 7993 | |
351e527a | 7994 | if ((excret & R_V7M_EXCRET_RES1_MASK) != R_V7M_EXCRET_RES1_MASK) { |
aa488fe3 | 7995 | qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in exception " |
351e527a PM |
7996 | "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", |
7997 | excret); | |
aa488fe3 PM |
7998 | } |
7999 | ||
bfb2eb52 PM |
8000 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
8001 | /* EXC_RETURN.ES validation check (R_SMFL). We must do this before | |
8002 | * we pick which FAULTMASK to clear. | |
8003 | */ | |
8004 | if (!env->v7m.secure && | |
8005 | ((excret & R_V7M_EXCRET_ES_MASK) || | |
8006 | !(excret & R_V7M_EXCRET_DCRS_MASK))) { | |
8007 | sfault = 1; | |
8008 | /* For all other purposes, treat ES as 0 (R_HXSR) */ | |
8009 | excret &= ~R_V7M_EXCRET_ES_MASK; | |
8010 | } | |
b8109608 | 8011 | exc_secure = excret & R_V7M_EXCRET_ES_MASK; |
bfb2eb52 PM |
8012 | } |
8013 | ||
a20ee600 | 8014 | if (env->v7m.exception != ARMV7M_EXCP_NMI) { |
42a6686b PM |
8015 | /* Auto-clear FAULTMASK on return from other than NMI. |
8016 | * If the security extension is implemented then this only | |
8017 | * happens if the raw execution priority is >= 0; the | |
8018 | * value of the ES bit in the exception return value indicates | |
8019 | * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) | |
8020 | */ | |
8021 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
42a6686b | 8022 | if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) { |
5cb18069 | 8023 | env->v7m.faultmask[exc_secure] = 0; |
42a6686b PM |
8024 | } |
8025 | } else { | |
8026 | env->v7m.faultmask[M_REG_NS] = 0; | |
8027 | } | |
a20ee600 | 8028 | } |
aa488fe3 | 8029 | |
5cb18069 PM |
8030 | switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception, |
8031 | exc_secure)) { | |
aa488fe3 PM |
8032 | case -1: |
8033 | /* attempt to exit an exception that isn't active */ | |
8034 | ufault = true; | |
8035 | break; | |
8036 | case 0: | |
8037 | /* still an irq active now */ | |
8038 | break; | |
8039 | case 1: | |
8040 | /* we returned to base exception level, no nesting. | |
8041 | * (In the pseudocode this is written using "NestedActivation != 1" | |
8042 | * where we have 'rettobase == false'.) | |
8043 | */ | |
8044 | rettobase = true; | |
8045 | break; | |
8046 | default: | |
8047 | g_assert_not_reached(); | |
8048 | } | |
8049 | ||
bfb2eb52 PM |
8050 | return_to_handler = !(excret & R_V7M_EXCRET_MODE_MASK); |
8051 | return_to_sp_process = excret & R_V7M_EXCRET_SPSEL_MASK; | |
5b522399 PM |
8052 | return_to_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) && |
8053 | (excret & R_V7M_EXCRET_S_MASK); | |
8054 | ||
bfb2eb52 PM |
8055 | if (arm_feature(env, ARM_FEATURE_V8)) { |
8056 | if (!arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
8057 | /* UNPREDICTABLE if S == 1 or DCRS == 0 or ES == 1 (R_XLCP); | |
8058 | * we choose to take the UsageFault. | |
8059 | */ | |
8060 | if ((excret & R_V7M_EXCRET_S_MASK) || | |
8061 | (excret & R_V7M_EXCRET_ES_MASK) || | |
8062 | !(excret & R_V7M_EXCRET_DCRS_MASK)) { | |
8063 | ufault = true; | |
8064 | } | |
8065 | } | |
8066 | if (excret & R_V7M_EXCRET_RES0_MASK) { | |
aa488fe3 PM |
8067 | ufault = true; |
8068 | } | |
bfb2eb52 PM |
8069 | } else { |
8070 | /* For v7M we only recognize certain combinations of the low bits */ | |
8071 | switch (excret & 0xf) { | |
8072 | case 1: /* Return to Handler */ | |
8073 | break; | |
8074 | case 13: /* Return to Thread using Process stack */ | |
8075 | case 9: /* Return to Thread using Main stack */ | |
8076 | /* We only need to check NONBASETHRDENA for v7M, because in | |
8077 | * v8M this bit does not exist (it is RES1). | |
8078 | */ | |
8079 | if (!rettobase && | |
8080 | !(env->v7m.ccr[env->v7m.secure] & | |
8081 | R_V7M_CCR_NONBASETHRDENA_MASK)) { | |
8082 | ufault = true; | |
8083 | } | |
8084 | break; | |
8085 | default: | |
8086 | ufault = true; | |
8087 | } | |
8088 | } | |
8089 | ||
89b1fec1 PM |
8090 | /* |
8091 | * Set CONTROL.SPSEL from excret.SPSEL. Since we're still in | |
8092 | * Handler mode (and will be until we write the new XPSR.Interrupt | |
8093 | * field) this does not switch around the current stack pointer. | |
8094 | * We must do this before we do any kind of tailchaining, including | |
8095 | * for the derived exceptions on integrity check failures, or we will | |
8096 | * give the guest an incorrect EXCRET.SPSEL value on exception entry. | |
8097 | */ | |
8098 | write_v7m_control_spsel_for_secstate(env, return_to_sp_process, exc_secure); | |
8099 | ||
bfb2eb52 PM |
8100 | if (sfault) { |
8101 | env->v7m.sfsr |= R_V7M_SFSR_INVER_MASK; | |
8102 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | |
bfb2eb52 PM |
8103 | qemu_log_mask(CPU_LOG_INT, "...taking SecureFault on existing " |
8104 | "stackframe: failed EXC_RETURN.ES validity check\n"); | |
a9074977 | 8105 | v7m_exception_taken(cpu, excret, true, false); |
bfb2eb52 | 8106 | return; |
aa488fe3 PM |
8107 | } |
8108 | ||
8109 | if (ufault) { | |
8110 | /* Bad exception return: instead of popping the exception | |
8111 | * stack, directly take a usage fault on the current stack. | |
8112 | */ | |
334e8dad | 8113 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; |
2fb50a33 | 8114 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); |
aa488fe3 PM |
8115 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " |
8116 | "stackframe: failed exception return integrity check\n"); | |
a9074977 | 8117 | v7m_exception_taken(cpu, excret, true, false); |
aa488fe3 | 8118 | return; |
a20ee600 | 8119 | } |
9ee6e8bb | 8120 | |
5f62d3b9 PM |
8121 | /* |
8122 | * Tailchaining: if there is currently a pending exception that | |
8123 | * is high enough priority to preempt execution at the level we're | |
8124 | * about to return to, then just directly take that exception now, | |
8125 | * avoiding an unstack-and-then-stack. Note that now we have | |
8126 | * deactivated the previous exception by calling armv7m_nvic_complete_irq() | |
8127 | * our current execution priority is already the execution priority we are | |
8128 | * returning to -- none of the state we would unstack or set based on | |
8129 | * the EXCRET value affects it. | |
8130 | */ | |
8131 | if (armv7m_nvic_can_take_pending_exception(env->nvic)) { | |
8132 | qemu_log_mask(CPU_LOG_INT, "...tailchaining to pending exception\n"); | |
8133 | v7m_exception_taken(cpu, excret, true, false); | |
8134 | return; | |
8135 | } | |
8136 | ||
3919e60b PM |
8137 | switch_v7m_security_state(env, return_to_secure); |
8138 | ||
5b522399 PM |
8139 | { |
8140 | /* The stack pointer we should be reading the exception frame from | |
8141 | * depends on bits in the magic exception return type value (and | |
8142 | * for v8M isn't necessarily the stack pointer we will eventually | |
8143 | * end up resuming execution with). Get a pointer to the location | |
8144 | * in the CPU state struct where the SP we need is currently being | |
8145 | * stored; we will use and modify it in place. | |
8146 | * We use this limited C variable scope so we don't accidentally | |
8147 | * use 'frame_sp_p' after we do something that makes it invalid. | |
fcf83ab1 | 8148 | */ |
5b522399 PM |
8149 | uint32_t *frame_sp_p = get_v7m_sp_ptr(env, |
8150 | return_to_secure, | |
8151 | !return_to_handler, | |
8152 | return_to_sp_process); | |
8153 | uint32_t frameptr = *frame_sp_p; | |
95695eff PM |
8154 | bool pop_ok = true; |
8155 | ARMMMUIdx mmu_idx; | |
2b83714d PM |
8156 | bool return_to_priv = return_to_handler || |
8157 | !(env->v7m.control[return_to_secure] & R_V7M_CONTROL_NPRIV_MASK); | |
95695eff PM |
8158 | |
8159 | mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, return_to_secure, | |
2b83714d | 8160 | return_to_priv); |
5b522399 | 8161 | |
cb484f9a PM |
8162 | if (!QEMU_IS_ALIGNED(frameptr, 8) && |
8163 | arm_feature(env, ARM_FEATURE_V8)) { | |
8164 | qemu_log_mask(LOG_GUEST_ERROR, | |
8165 | "M profile exception return with non-8-aligned SP " | |
8166 | "for destination state is UNPREDICTABLE\n"); | |
8167 | } | |
8168 | ||
907bedb3 PM |
8169 | /* Do we need to pop callee-saved registers? */ |
8170 | if (return_to_secure && | |
8171 | ((excret & R_V7M_EXCRET_ES_MASK) == 0 || | |
8172 | (excret & R_V7M_EXCRET_DCRS_MASK) == 0)) { | |
8173 | uint32_t expected_sig = 0xfefa125b; | |
4818bad9 PM |
8174 | uint32_t actual_sig; |
8175 | ||
8176 | pop_ok = v7m_stack_read(cpu, &actual_sig, frameptr, mmu_idx); | |
907bedb3 | 8177 | |
4818bad9 | 8178 | if (pop_ok && expected_sig != actual_sig) { |
907bedb3 PM |
8179 | /* Take a SecureFault on the current stack */ |
8180 | env->v7m.sfsr |= R_V7M_SFSR_INVIS_MASK; | |
8181 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | |
907bedb3 PM |
8182 | qemu_log_mask(CPU_LOG_INT, "...taking SecureFault on existing " |
8183 | "stackframe: failed exception return integrity " | |
8184 | "signature check\n"); | |
a9074977 | 8185 | v7m_exception_taken(cpu, excret, true, false); |
907bedb3 PM |
8186 | return; |
8187 | } | |
8188 | ||
4818bad9 | 8189 | pop_ok = pop_ok && |
95695eff PM |
8190 | v7m_stack_read(cpu, &env->regs[4], frameptr + 0x8, mmu_idx) && |
8191 | v7m_stack_read(cpu, &env->regs[5], frameptr + 0xc, mmu_idx) && | |
8192 | v7m_stack_read(cpu, &env->regs[6], frameptr + 0x10, mmu_idx) && | |
8193 | v7m_stack_read(cpu, &env->regs[7], frameptr + 0x14, mmu_idx) && | |
8194 | v7m_stack_read(cpu, &env->regs[8], frameptr + 0x18, mmu_idx) && | |
8195 | v7m_stack_read(cpu, &env->regs[9], frameptr + 0x1c, mmu_idx) && | |
8196 | v7m_stack_read(cpu, &env->regs[10], frameptr + 0x20, mmu_idx) && | |
8197 | v7m_stack_read(cpu, &env->regs[11], frameptr + 0x24, mmu_idx); | |
907bedb3 PM |
8198 | |
8199 | frameptr += 0x28; | |
8200 | } | |
8201 | ||
95695eff PM |
8202 | /* Pop registers */ |
8203 | pop_ok = pop_ok && | |
8204 | v7m_stack_read(cpu, &env->regs[0], frameptr, mmu_idx) && | |
8205 | v7m_stack_read(cpu, &env->regs[1], frameptr + 0x4, mmu_idx) && | |
8206 | v7m_stack_read(cpu, &env->regs[2], frameptr + 0x8, mmu_idx) && | |
8207 | v7m_stack_read(cpu, &env->regs[3], frameptr + 0xc, mmu_idx) && | |
8208 | v7m_stack_read(cpu, &env->regs[12], frameptr + 0x10, mmu_idx) && | |
8209 | v7m_stack_read(cpu, &env->regs[14], frameptr + 0x14, mmu_idx) && | |
8210 | v7m_stack_read(cpu, &env->regs[15], frameptr + 0x18, mmu_idx) && | |
8211 | v7m_stack_read(cpu, &xpsr, frameptr + 0x1c, mmu_idx); | |
8212 | ||
8213 | if (!pop_ok) { | |
8214 | /* v7m_stack_read() pended a fault, so take it (as a tail | |
8215 | * chained exception on the same stack frame) | |
8216 | */ | |
a9074977 | 8217 | qemu_log_mask(CPU_LOG_INT, "...derived exception on unstacking\n"); |
95695eff PM |
8218 | v7m_exception_taken(cpu, excret, true, false); |
8219 | return; | |
8220 | } | |
4e4259d3 PM |
8221 | |
8222 | /* Returning from an exception with a PC with bit 0 set is defined | |
8223 | * behaviour on v8M (bit 0 is ignored), but for v7M it was specified | |
8224 | * to be UNPREDICTABLE. In practice actual v7M hardware seems to ignore | |
8225 | * the lsbit, and there are several RTOSes out there which incorrectly | |
8226 | * assume the r15 in the stack frame should be a Thumb-style "lsbit | |
8227 | * indicates ARM/Thumb" value, so ignore the bit on v7M as well, but | |
8228 | * complain about the badly behaved guest. | |
8229 | */ | |
5b522399 | 8230 | if (env->regs[15] & 1) { |
5b522399 | 8231 | env->regs[15] &= ~1U; |
4e4259d3 PM |
8232 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
8233 | qemu_log_mask(LOG_GUEST_ERROR, | |
8234 | "M profile return from interrupt with misaligned " | |
8235 | "PC is UNPREDICTABLE on v7M\n"); | |
8236 | } | |
5b522399 | 8237 | } |
4e4259d3 | 8238 | |
224e0c30 PM |
8239 | if (arm_feature(env, ARM_FEATURE_V8)) { |
8240 | /* For v8M we have to check whether the xPSR exception field | |
8241 | * matches the EXCRET value for return to handler/thread | |
8242 | * before we commit to changing the SP and xPSR. | |
8243 | */ | |
8244 | bool will_be_handler = (xpsr & XPSR_EXCP) != 0; | |
8245 | if (return_to_handler != will_be_handler) { | |
8246 | /* Take an INVPC UsageFault on the current stack. | |
8247 | * By this point we will have switched to the security state | |
8248 | * for the background state, so this UsageFault will target | |
8249 | * that state. | |
8250 | */ | |
8251 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, | |
8252 | env->v7m.secure); | |
8253 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; | |
224e0c30 PM |
8254 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " |
8255 | "stackframe: failed exception return integrity " | |
8256 | "check\n"); | |
a9074977 | 8257 | v7m_exception_taken(cpu, excret, true, false); |
224e0c30 PM |
8258 | return; |
8259 | } | |
8260 | } | |
8261 | ||
5b522399 PM |
8262 | /* Commit to consuming the stack frame */ |
8263 | frameptr += 0x20; | |
8264 | /* Undo stack alignment (the SPREALIGN bit indicates that the original | |
8265 | * pre-exception SP was not 8-aligned and we added a padding word to | |
8266 | * align it, so we undo this by ORing in the bit that increases it | |
8267 | * from the current 8-aligned value to the 8-unaligned value. (Adding 4 | |
8268 | * would work too but a logical OR is how the pseudocode specifies it.) | |
8269 | */ | |
8270 | if (xpsr & XPSR_SPREALIGN) { | |
8271 | frameptr |= 4; | |
8272 | } | |
8273 | *frame_sp_p = frameptr; | |
fcf83ab1 | 8274 | } |
5b522399 | 8275 | /* This xpsr_write() will invalidate frame_sp_p as it may switch stack */ |
987ab45e | 8276 | xpsr_write(env, xpsr, ~XPSR_SPREALIGN); |
aa488fe3 PM |
8277 | |
8278 | /* The restored xPSR exception field will be zero if we're | |
8279 | * resuming in Thread mode. If that doesn't match what the | |
351e527a | 8280 | * exception return excret specified then this is a UsageFault. |
224e0c30 | 8281 | * v7M requires we make this check here; v8M did it earlier. |
aa488fe3 | 8282 | */ |
15b3f556 | 8283 | if (return_to_handler != arm_v7m_is_handler_mode(env)) { |
224e0c30 PM |
8284 | /* Take an INVPC UsageFault by pushing the stack again; |
8285 | * we know we're v7M so this is never a Secure UsageFault. | |
2fb50a33 | 8286 | */ |
0094ca70 PM |
8287 | bool ignore_stackfaults; |
8288 | ||
224e0c30 | 8289 | assert(!arm_feature(env, ARM_FEATURE_V8)); |
2fb50a33 | 8290 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, false); |
334e8dad | 8291 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; |
0094ca70 | 8292 | ignore_stackfaults = v7m_push_stack(cpu); |
aa488fe3 PM |
8293 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe: " |
8294 | "failed exception return integrity check\n"); | |
a9074977 | 8295 | v7m_exception_taken(cpu, excret, false, ignore_stackfaults); |
aa488fe3 PM |
8296 | return; |
8297 | } | |
8298 | ||
8299 | /* Otherwise, we have a successful exception exit. */ | |
dc3c4c14 | 8300 | arm_clear_exclusive(env); |
aa488fe3 | 8301 | qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); |
9ee6e8bb PB |
8302 | } |
8303 | ||
d02a8698 PM |
8304 | static bool do_v7m_function_return(ARMCPU *cpu) |
8305 | { | |
8306 | /* v8M security extensions magic function return. | |
8307 | * We may either: | |
8308 | * (1) throw an exception (longjump) | |
8309 | * (2) return true if we successfully handled the function return | |
8310 | * (3) return false if we failed a consistency check and have | |
8311 | * pended a UsageFault that needs to be taken now | |
8312 | * | |
8313 | * At this point the magic return value is split between env->regs[15] | |
8314 | * and env->thumb. We don't bother to reconstitute it because we don't | |
8315 | * need it (all values are handled the same way). | |
8316 | */ | |
8317 | CPUARMState *env = &cpu->env; | |
8318 | uint32_t newpc, newpsr, newpsr_exc; | |
8319 | ||
8320 | qemu_log_mask(CPU_LOG_INT, "...really v7M secure function return\n"); | |
8321 | ||
8322 | { | |
8323 | bool threadmode, spsel; | |
8324 | TCGMemOpIdx oi; | |
8325 | ARMMMUIdx mmu_idx; | |
8326 | uint32_t *frame_sp_p; | |
8327 | uint32_t frameptr; | |
8328 | ||
8329 | /* Pull the return address and IPSR from the Secure stack */ | |
8330 | threadmode = !arm_v7m_is_handler_mode(env); | |
8331 | spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK; | |
8332 | ||
8333 | frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel); | |
8334 | frameptr = *frame_sp_p; | |
8335 | ||
8336 | /* These loads may throw an exception (for MPU faults). We want to | |
8337 | * do them as secure, so work out what MMU index that is. | |
8338 | */ | |
8339 | mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true); | |
8340 | oi = make_memop_idx(MO_LE, arm_to_core_mmu_idx(mmu_idx)); | |
8341 | newpc = helper_le_ldul_mmu(env, frameptr, oi, 0); | |
8342 | newpsr = helper_le_ldul_mmu(env, frameptr + 4, oi, 0); | |
8343 | ||
8344 | /* Consistency checks on new IPSR */ | |
8345 | newpsr_exc = newpsr & XPSR_EXCP; | |
8346 | if (!((env->v7m.exception == 0 && newpsr_exc == 0) || | |
8347 | (env->v7m.exception == 1 && newpsr_exc != 0))) { | |
8348 | /* Pend the fault and tell our caller to take it */ | |
8349 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK; | |
8350 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, | |
8351 | env->v7m.secure); | |
8352 | qemu_log_mask(CPU_LOG_INT, | |
8353 | "...taking INVPC UsageFault: " | |
8354 | "IPSR consistency check failed\n"); | |
8355 | return false; | |
8356 | } | |
8357 | ||
8358 | *frame_sp_p = frameptr + 8; | |
8359 | } | |
8360 | ||
8361 | /* This invalidates frame_sp_p */ | |
8362 | switch_v7m_security_state(env, true); | |
8363 | env->v7m.exception = newpsr_exc; | |
8364 | env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; | |
8365 | if (newpsr & XPSR_SFPA) { | |
8366 | env->v7m.control[M_REG_S] |= R_V7M_CONTROL_SFPA_MASK; | |
8367 | } | |
8368 | xpsr_write(env, 0, XPSR_IT); | |
8369 | env->thumb = newpc & 1; | |
8370 | env->regs[15] = newpc & ~1; | |
8371 | ||
8372 | qemu_log_mask(CPU_LOG_INT, "...function return successful\n"); | |
8373 | return true; | |
8374 | } | |
8375 | ||
27a7ea8a PB |
8376 | static void arm_log_exception(int idx) |
8377 | { | |
8378 | if (qemu_loglevel_mask(CPU_LOG_INT)) { | |
8379 | const char *exc = NULL; | |
2c4a7cc5 PM |
8380 | static const char * const excnames[] = { |
8381 | [EXCP_UDEF] = "Undefined Instruction", | |
8382 | [EXCP_SWI] = "SVC", | |
8383 | [EXCP_PREFETCH_ABORT] = "Prefetch Abort", | |
8384 | [EXCP_DATA_ABORT] = "Data Abort", | |
8385 | [EXCP_IRQ] = "IRQ", | |
8386 | [EXCP_FIQ] = "FIQ", | |
8387 | [EXCP_BKPT] = "Breakpoint", | |
8388 | [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", | |
8389 | [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", | |
8390 | [EXCP_HVC] = "Hypervisor Call", | |
8391 | [EXCP_HYP_TRAP] = "Hypervisor Trap", | |
8392 | [EXCP_SMC] = "Secure Monitor Call", | |
8393 | [EXCP_VIRQ] = "Virtual IRQ", | |
8394 | [EXCP_VFIQ] = "Virtual FIQ", | |
8395 | [EXCP_SEMIHOST] = "Semihosting call", | |
8396 | [EXCP_NOCP] = "v7M NOCP UsageFault", | |
8397 | [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", | |
86f026de | 8398 | [EXCP_STKOF] = "v8M STKOF UsageFault", |
2c4a7cc5 | 8399 | }; |
27a7ea8a PB |
8400 | |
8401 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | |
8402 | exc = excnames[idx]; | |
8403 | } | |
8404 | if (!exc) { | |
8405 | exc = "unknown"; | |
8406 | } | |
8407 | qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); | |
8408 | } | |
8409 | } | |
8410 | ||
333e10c5 PM |
8411 | static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, |
8412 | uint32_t addr, uint16_t *insn) | |
8413 | { | |
8414 | /* Load a 16-bit portion of a v7M instruction, returning true on success, | |
8415 | * or false on failure (in which case we will have pended the appropriate | |
8416 | * exception). | |
8417 | * We need to do the instruction fetch's MPU and SAU checks | |
8418 | * like this because there is no MMU index that would allow | |
8419 | * doing the load with a single function call. Instead we must | |
8420 | * first check that the security attributes permit the load | |
8421 | * and that they don't mismatch on the two halves of the instruction, | |
8422 | * and then we do the load as a secure load (ie using the security | |
8423 | * attributes of the address, not the CPU, as architecturally required). | |
8424 | */ | |
8425 | CPUState *cs = CPU(cpu); | |
8426 | CPUARMState *env = &cpu->env; | |
8427 | V8M_SAttributes sattrs = {}; | |
8428 | MemTxAttrs attrs = {}; | |
8429 | ARMMMUFaultInfo fi = {}; | |
8430 | MemTxResult txres; | |
8431 | target_ulong page_size; | |
8432 | hwaddr physaddr; | |
8433 | int prot; | |
333e10c5 PM |
8434 | |
8435 | v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs); | |
8436 | if (!sattrs.nsc || sattrs.ns) { | |
8437 | /* This must be the second half of the insn, and it straddles a | |
8438 | * region boundary with the second half not being S&NSC. | |
8439 | */ | |
8440 | env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK; | |
8441 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | |
8442 | qemu_log_mask(CPU_LOG_INT, | |
8443 | "...really SecureFault with SFSR.INVEP\n"); | |
8444 | return false; | |
8445 | } | |
8446 | if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, | |
bc52bfeb | 8447 | &physaddr, &attrs, &prot, &page_size, &fi, NULL)) { |
333e10c5 PM |
8448 | /* the MPU lookup failed */ |
8449 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; | |
8450 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure); | |
8451 | qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL\n"); | |
8452 | return false; | |
8453 | } | |
8454 | *insn = address_space_lduw_le(arm_addressspace(cs, attrs), physaddr, | |
8455 | attrs, &txres); | |
8456 | if (txres != MEMTX_OK) { | |
8457 | env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK; | |
8458 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); | |
8459 | qemu_log_mask(CPU_LOG_INT, "...really BusFault with CFSR.IBUSERR\n"); | |
8460 | return false; | |
8461 | } | |
8462 | return true; | |
8463 | } | |
8464 | ||
8465 | static bool v7m_handle_execute_nsc(ARMCPU *cpu) | |
8466 | { | |
8467 | /* Check whether this attempt to execute code in a Secure & NS-Callable | |
8468 | * memory region is for an SG instruction; if so, then emulate the | |
8469 | * effect of the SG instruction and return true. Otherwise pend | |
8470 | * the correct kind of exception and return false. | |
8471 | */ | |
8472 | CPUARMState *env = &cpu->env; | |
8473 | ARMMMUIdx mmu_idx; | |
8474 | uint16_t insn; | |
8475 | ||
8476 | /* We should never get here unless get_phys_addr_pmsav8() caused | |
8477 | * an exception for NS executing in S&NSC memory. | |
8478 | */ | |
8479 | assert(!env->v7m.secure); | |
8480 | assert(arm_feature(env, ARM_FEATURE_M_SECURITY)); | |
8481 | ||
8482 | /* We want to do the MPU lookup as secure; work out what mmu_idx that is */ | |
8483 | mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true); | |
8484 | ||
8485 | if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) { | |
8486 | return false; | |
8487 | } | |
8488 | ||
8489 | if (!env->thumb) { | |
8490 | goto gen_invep; | |
8491 | } | |
8492 | ||
8493 | if (insn != 0xe97f) { | |
8494 | /* Not an SG instruction first half (we choose the IMPDEF | |
8495 | * early-SG-check option). | |
8496 | */ | |
8497 | goto gen_invep; | |
8498 | } | |
8499 | ||
8500 | if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) { | |
8501 | return false; | |
8502 | } | |
8503 | ||
8504 | if (insn != 0xe97f) { | |
8505 | /* Not an SG instruction second half (yes, both halves of the SG | |
8506 | * insn have the same hex value) | |
8507 | */ | |
8508 | goto gen_invep; | |
8509 | } | |
8510 | ||
8511 | /* OK, we have confirmed that we really have an SG instruction. | |
8512 | * We know we're NS in S memory so don't need to repeat those checks. | |
8513 | */ | |
8514 | qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32 | |
8515 | ", executing it\n", env->regs[15]); | |
8516 | env->regs[14] &= ~1; | |
8517 | switch_v7m_security_state(env, true); | |
8518 | xpsr_write(env, 0, XPSR_IT); | |
8519 | env->regs[15] += 4; | |
8520 | return true; | |
8521 | ||
8522 | gen_invep: | |
8523 | env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK; | |
8524 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | |
8525 | qemu_log_mask(CPU_LOG_INT, | |
8526 | "...really SecureFault with SFSR.INVEP\n"); | |
8527 | return false; | |
8528 | } | |
8529 | ||
e6f010cc | 8530 | void arm_v7m_cpu_do_interrupt(CPUState *cs) |
9ee6e8bb | 8531 | { |
e6f010cc AF |
8532 | ARMCPU *cpu = ARM_CPU(cs); |
8533 | CPUARMState *env = &cpu->env; | |
9ee6e8bb | 8534 | uint32_t lr; |
0094ca70 | 8535 | bool ignore_stackfaults; |
9ee6e8bb | 8536 | |
27103424 | 8537 | arm_log_exception(cs->exception_index); |
3f1beaca | 8538 | |
9ee6e8bb PB |
8539 | /* For exceptions we just mark as pending on the NVIC, and let that |
8540 | handle it. */ | |
27103424 | 8541 | switch (cs->exception_index) { |
9ee6e8bb | 8542 | case EXCP_UDEF: |
2fb50a33 | 8543 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); |
334e8dad | 8544 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK; |
a25dc805 | 8545 | break; |
7517748e | 8546 | case EXCP_NOCP: |
2fb50a33 | 8547 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); |
334e8dad | 8548 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK; |
a25dc805 | 8549 | break; |
e13886e3 | 8550 | case EXCP_INVSTATE: |
2fb50a33 | 8551 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); |
334e8dad | 8552 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK; |
e13886e3 | 8553 | break; |
86f026de PM |
8554 | case EXCP_STKOF: |
8555 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); | |
8556 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_STKOF_MASK; | |
8557 | break; | |
9ee6e8bb | 8558 | case EXCP_SWI: |
314e2296 | 8559 | /* The PC already points to the next instruction. */ |
2fb50a33 | 8560 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure); |
a25dc805 | 8561 | break; |
9ee6e8bb PB |
8562 | case EXCP_PREFETCH_ABORT: |
8563 | case EXCP_DATA_ABORT: | |
5dd0641d MD |
8564 | /* Note that for M profile we don't have a guest facing FSR, but |
8565 | * the env->exception.fsr will be populated by the code that | |
8566 | * raises the fault, in the A profile short-descriptor format. | |
abf1172f | 8567 | */ |
5dd0641d | 8568 | switch (env->exception.fsr & 0xf) { |
35337cc3 PM |
8569 | case M_FAKE_FSR_NSC_EXEC: |
8570 | /* Exception generated when we try to execute code at an address | |
8571 | * which is marked as Secure & Non-Secure Callable and the CPU | |
8572 | * is in the Non-Secure state. The only instruction which can | |
8573 | * be executed like this is SG (and that only if both halves of | |
8574 | * the SG instruction have the same security attributes.) | |
8575 | * Everything else must generate an INVEP SecureFault, so we | |
8576 | * emulate the SG instruction here. | |
35337cc3 | 8577 | */ |
333e10c5 PM |
8578 | if (v7m_handle_execute_nsc(cpu)) { |
8579 | return; | |
8580 | } | |
35337cc3 PM |
8581 | break; |
8582 | case M_FAKE_FSR_SFAULT: | |
8583 | /* Various flavours of SecureFault for attempts to execute or | |
8584 | * access data in the wrong security state. | |
8585 | */ | |
8586 | switch (cs->exception_index) { | |
8587 | case EXCP_PREFETCH_ABORT: | |
8588 | if (env->v7m.secure) { | |
8589 | env->v7m.sfsr |= R_V7M_SFSR_INVTRAN_MASK; | |
8590 | qemu_log_mask(CPU_LOG_INT, | |
8591 | "...really SecureFault with SFSR.INVTRAN\n"); | |
8592 | } else { | |
8593 | env->v7m.sfsr |= R_V7M_SFSR_INVEP_MASK; | |
8594 | qemu_log_mask(CPU_LOG_INT, | |
8595 | "...really SecureFault with SFSR.INVEP\n"); | |
8596 | } | |
8597 | break; | |
8598 | case EXCP_DATA_ABORT: | |
8599 | /* This must be an NS access to S memory */ | |
8600 | env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK; | |
8601 | qemu_log_mask(CPU_LOG_INT, | |
8602 | "...really SecureFault with SFSR.AUVIOL\n"); | |
8603 | break; | |
8604 | } | |
8605 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | |
8606 | break; | |
5dd0641d MD |
8607 | case 0x8: /* External Abort */ |
8608 | switch (cs->exception_index) { | |
8609 | case EXCP_PREFETCH_ABORT: | |
c6158878 PM |
8610 | env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK; |
8611 | qemu_log_mask(CPU_LOG_INT, "...with CFSR.IBUSERR\n"); | |
5dd0641d MD |
8612 | break; |
8613 | case EXCP_DATA_ABORT: | |
334e8dad | 8614 | env->v7m.cfsr[M_REG_NS] |= |
c6158878 | 8615 | (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK); |
5dd0641d MD |
8616 | env->v7m.bfar = env->exception.vaddress; |
8617 | qemu_log_mask(CPU_LOG_INT, | |
c6158878 | 8618 | "...with CFSR.PRECISERR and BFAR 0x%x\n", |
5dd0641d MD |
8619 | env->v7m.bfar); |
8620 | break; | |
8621 | } | |
2fb50a33 | 8622 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); |
5dd0641d MD |
8623 | break; |
8624 | default: | |
8625 | /* All other FSR values are either MPU faults or "can't happen | |
8626 | * for M profile" cases. | |
8627 | */ | |
8628 | switch (cs->exception_index) { | |
8629 | case EXCP_PREFETCH_ABORT: | |
334e8dad | 8630 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; |
5dd0641d MD |
8631 | qemu_log_mask(CPU_LOG_INT, "...with CFSR.IACCVIOL\n"); |
8632 | break; | |
8633 | case EXCP_DATA_ABORT: | |
334e8dad | 8634 | env->v7m.cfsr[env->v7m.secure] |= |
5dd0641d | 8635 | (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK); |
c51a5cfc | 8636 | env->v7m.mmfar[env->v7m.secure] = env->exception.vaddress; |
5dd0641d MD |
8637 | qemu_log_mask(CPU_LOG_INT, |
8638 | "...with CFSR.DACCVIOL and MMFAR 0x%x\n", | |
c51a5cfc | 8639 | env->v7m.mmfar[env->v7m.secure]); |
5dd0641d MD |
8640 | break; |
8641 | } | |
2fb50a33 PM |
8642 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, |
8643 | env->v7m.secure); | |
5dd0641d MD |
8644 | break; |
8645 | } | |
a25dc805 | 8646 | break; |
9ee6e8bb | 8647 | case EXCP_BKPT: |
cfe67cef | 8648 | if (semihosting_enabled()) { |
2ad207d4 | 8649 | int nr; |
f9fd40eb | 8650 | nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff; |
2ad207d4 PB |
8651 | if (nr == 0xab) { |
8652 | env->regs[15] += 2; | |
205ace55 CC |
8653 | qemu_log_mask(CPU_LOG_INT, |
8654 | "...handling as semihosting call 0x%x\n", | |
8655 | env->regs[0]); | |
2ad207d4 PB |
8656 | env->regs[0] = do_arm_semihosting(env); |
8657 | return; | |
8658 | } | |
8659 | } | |
2fb50a33 | 8660 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false); |
a25dc805 | 8661 | break; |
9ee6e8bb | 8662 | case EXCP_IRQ: |
9ee6e8bb PB |
8663 | break; |
8664 | case EXCP_EXCEPTION_EXIT: | |
d02a8698 PM |
8665 | if (env->regs[15] < EXC_RETURN_MIN_MAGIC) { |
8666 | /* Must be v8M security extension function return */ | |
8667 | assert(env->regs[15] >= FNC_RETURN_MIN_MAGIC); | |
8668 | assert(arm_feature(env, ARM_FEATURE_M_SECURITY)); | |
8669 | if (do_v7m_function_return(cpu)) { | |
8670 | return; | |
8671 | } | |
8672 | } else { | |
8673 | do_v7m_exception_exit(cpu); | |
8674 | return; | |
8675 | } | |
8676 | break; | |
9ee6e8bb | 8677 | default: |
a47dddd7 | 8678 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
9ee6e8bb PB |
8679 | return; /* Never happens. Keep compiler happy. */ |
8680 | } | |
8681 | ||
d3392718 PM |
8682 | if (arm_feature(env, ARM_FEATURE_V8)) { |
8683 | lr = R_V7M_EXCRET_RES1_MASK | | |
8684 | R_V7M_EXCRET_DCRS_MASK | | |
8685 | R_V7M_EXCRET_FTYPE_MASK; | |
8686 | /* The S bit indicates whether we should return to Secure | |
8687 | * or NonSecure (ie our current state). | |
8688 | * The ES bit indicates whether we're taking this exception | |
8689 | * to Secure or NonSecure (ie our target state). We set it | |
8690 | * later, in v7m_exception_taken(). | |
8691 | * The SPSEL bit is also set in v7m_exception_taken() for v8M. | |
8692 | * This corresponds to the ARM ARM pseudocode for v8M setting | |
8693 | * some LR bits in PushStack() and some in ExceptionTaken(); | |
8694 | * the distinction matters for the tailchain cases where we | |
8695 | * can take an exception without pushing the stack. | |
8696 | */ | |
8697 | if (env->v7m.secure) { | |
8698 | lr |= R_V7M_EXCRET_S_MASK; | |
8699 | } | |
8700 | } else { | |
8701 | lr = R_V7M_EXCRET_RES1_MASK | | |
8702 | R_V7M_EXCRET_S_MASK | | |
8703 | R_V7M_EXCRET_DCRS_MASK | | |
8704 | R_V7M_EXCRET_FTYPE_MASK | | |
8705 | R_V7M_EXCRET_ES_MASK; | |
8706 | if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) { | |
8707 | lr |= R_V7M_EXCRET_SPSEL_MASK; | |
8708 | } | |
bd70b29b | 8709 | } |
15b3f556 | 8710 | if (!arm_v7m_is_handler_mode(env)) { |
4d1e7a47 | 8711 | lr |= R_V7M_EXCRET_MODE_MASK; |
bd70b29b PM |
8712 | } |
8713 | ||
0094ca70 PM |
8714 | ignore_stackfaults = v7m_push_stack(cpu); |
8715 | v7m_exception_taken(cpu, lr, false, ignore_stackfaults); | |
9ee6e8bb PB |
8716 | } |
8717 | ||
ce02049d GB |
8718 | /* Function used to synchronize QEMU's AArch64 register set with AArch32 |
8719 | * register set. This is necessary when switching between AArch32 and AArch64 | |
8720 | * execution state. | |
8721 | */ | |
8722 | void aarch64_sync_32_to_64(CPUARMState *env) | |
8723 | { | |
8724 | int i; | |
8725 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
8726 | ||
8727 | /* We can blanket copy R[0:7] to X[0:7] */ | |
8728 | for (i = 0; i < 8; i++) { | |
8729 | env->xregs[i] = env->regs[i]; | |
8730 | } | |
8731 | ||
8732 | /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. | |
8733 | * Otherwise, they come from the banked user regs. | |
8734 | */ | |
8735 | if (mode == ARM_CPU_MODE_FIQ) { | |
8736 | for (i = 8; i < 13; i++) { | |
8737 | env->xregs[i] = env->usr_regs[i - 8]; | |
8738 | } | |
8739 | } else { | |
8740 | for (i = 8; i < 13; i++) { | |
8741 | env->xregs[i] = env->regs[i]; | |
8742 | } | |
8743 | } | |
8744 | ||
8745 | /* Registers x13-x23 are the various mode SP and FP registers. Registers | |
8746 | * r13 and r14 are only copied if we are in that mode, otherwise we copy | |
8747 | * from the mode banked register. | |
8748 | */ | |
8749 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { | |
8750 | env->xregs[13] = env->regs[13]; | |
8751 | env->xregs[14] = env->regs[14]; | |
8752 | } else { | |
8753 | env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; | |
8754 | /* HYP is an exception in that it is copied from r14 */ | |
8755 | if (mode == ARM_CPU_MODE_HYP) { | |
8756 | env->xregs[14] = env->regs[14]; | |
8757 | } else { | |
593cfa2b | 8758 | env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)]; |
ce02049d GB |
8759 | } |
8760 | } | |
8761 | ||
8762 | if (mode == ARM_CPU_MODE_HYP) { | |
8763 | env->xregs[15] = env->regs[13]; | |
8764 | } else { | |
8765 | env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; | |
8766 | } | |
8767 | ||
8768 | if (mode == ARM_CPU_MODE_IRQ) { | |
3a9148d0 SS |
8769 | env->xregs[16] = env->regs[14]; |
8770 | env->xregs[17] = env->regs[13]; | |
ce02049d | 8771 | } else { |
593cfa2b | 8772 | env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)]; |
3a9148d0 | 8773 | env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; |
ce02049d GB |
8774 | } |
8775 | ||
8776 | if (mode == ARM_CPU_MODE_SVC) { | |
3a9148d0 SS |
8777 | env->xregs[18] = env->regs[14]; |
8778 | env->xregs[19] = env->regs[13]; | |
ce02049d | 8779 | } else { |
593cfa2b | 8780 | env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)]; |
3a9148d0 | 8781 | env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; |
ce02049d GB |
8782 | } |
8783 | ||
8784 | if (mode == ARM_CPU_MODE_ABT) { | |
3a9148d0 SS |
8785 | env->xregs[20] = env->regs[14]; |
8786 | env->xregs[21] = env->regs[13]; | |
ce02049d | 8787 | } else { |
593cfa2b | 8788 | env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)]; |
3a9148d0 | 8789 | env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; |
ce02049d GB |
8790 | } |
8791 | ||
8792 | if (mode == ARM_CPU_MODE_UND) { | |
3a9148d0 SS |
8793 | env->xregs[22] = env->regs[14]; |
8794 | env->xregs[23] = env->regs[13]; | |
ce02049d | 8795 | } else { |
593cfa2b | 8796 | env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)]; |
3a9148d0 | 8797 | env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; |
ce02049d GB |
8798 | } |
8799 | ||
8800 | /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ | |
8801 | * mode, then we can copy from r8-r14. Otherwise, we copy from the | |
8802 | * FIQ bank for r8-r14. | |
8803 | */ | |
8804 | if (mode == ARM_CPU_MODE_FIQ) { | |
8805 | for (i = 24; i < 31; i++) { | |
8806 | env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ | |
8807 | } | |
8808 | } else { | |
8809 | for (i = 24; i < 29; i++) { | |
8810 | env->xregs[i] = env->fiq_regs[i - 24]; | |
8811 | } | |
8812 | env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; | |
593cfa2b | 8813 | env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)]; |
ce02049d GB |
8814 | } |
8815 | ||
8816 | env->pc = env->regs[15]; | |
8817 | } | |
8818 | ||
8819 | /* Function used to synchronize QEMU's AArch32 register set with AArch64 | |
8820 | * register set. This is necessary when switching between AArch32 and AArch64 | |
8821 | * execution state. | |
8822 | */ | |
8823 | void aarch64_sync_64_to_32(CPUARMState *env) | |
8824 | { | |
8825 | int i; | |
8826 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
8827 | ||
8828 | /* We can blanket copy X[0:7] to R[0:7] */ | |
8829 | for (i = 0; i < 8; i++) { | |
8830 | env->regs[i] = env->xregs[i]; | |
8831 | } | |
8832 | ||
8833 | /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. | |
8834 | * Otherwise, we copy x8-x12 into the banked user regs. | |
8835 | */ | |
8836 | if (mode == ARM_CPU_MODE_FIQ) { | |
8837 | for (i = 8; i < 13; i++) { | |
8838 | env->usr_regs[i - 8] = env->xregs[i]; | |
8839 | } | |
8840 | } else { | |
8841 | for (i = 8; i < 13; i++) { | |
8842 | env->regs[i] = env->xregs[i]; | |
8843 | } | |
8844 | } | |
8845 | ||
8846 | /* Registers r13 & r14 depend on the current mode. | |
8847 | * If we are in a given mode, we copy the corresponding x registers to r13 | |
8848 | * and r14. Otherwise, we copy the x register to the banked r13 and r14 | |
8849 | * for the mode. | |
8850 | */ | |
8851 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { | |
8852 | env->regs[13] = env->xregs[13]; | |
8853 | env->regs[14] = env->xregs[14]; | |
8854 | } else { | |
8855 | env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; | |
8856 | ||
8857 | /* HYP is an exception in that it does not have its own banked r14 but | |
8858 | * shares the USR r14 | |
8859 | */ | |
8860 | if (mode == ARM_CPU_MODE_HYP) { | |
8861 | env->regs[14] = env->xregs[14]; | |
8862 | } else { | |
593cfa2b | 8863 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; |
ce02049d GB |
8864 | } |
8865 | } | |
8866 | ||
8867 | if (mode == ARM_CPU_MODE_HYP) { | |
8868 | env->regs[13] = env->xregs[15]; | |
8869 | } else { | |
8870 | env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; | |
8871 | } | |
8872 | ||
8873 | if (mode == ARM_CPU_MODE_IRQ) { | |
3a9148d0 SS |
8874 | env->regs[14] = env->xregs[16]; |
8875 | env->regs[13] = env->xregs[17]; | |
ce02049d | 8876 | } else { |
593cfa2b | 8877 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; |
3a9148d0 | 8878 | env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; |
ce02049d GB |
8879 | } |
8880 | ||
8881 | if (mode == ARM_CPU_MODE_SVC) { | |
3a9148d0 SS |
8882 | env->regs[14] = env->xregs[18]; |
8883 | env->regs[13] = env->xregs[19]; | |
ce02049d | 8884 | } else { |
593cfa2b | 8885 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; |
3a9148d0 | 8886 | env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; |
ce02049d GB |
8887 | } |
8888 | ||
8889 | if (mode == ARM_CPU_MODE_ABT) { | |
3a9148d0 SS |
8890 | env->regs[14] = env->xregs[20]; |
8891 | env->regs[13] = env->xregs[21]; | |
ce02049d | 8892 | } else { |
593cfa2b | 8893 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; |
3a9148d0 | 8894 | env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; |
ce02049d GB |
8895 | } |
8896 | ||
8897 | if (mode == ARM_CPU_MODE_UND) { | |
3a9148d0 SS |
8898 | env->regs[14] = env->xregs[22]; |
8899 | env->regs[13] = env->xregs[23]; | |
ce02049d | 8900 | } else { |
593cfa2b | 8901 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; |
3a9148d0 | 8902 | env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; |
ce02049d GB |
8903 | } |
8904 | ||
8905 | /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ | |
8906 | * mode, then we can copy to r8-r14. Otherwise, we copy to the | |
8907 | * FIQ bank for r8-r14. | |
8908 | */ | |
8909 | if (mode == ARM_CPU_MODE_FIQ) { | |
8910 | for (i = 24; i < 31; i++) { | |
8911 | env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ | |
8912 | } | |
8913 | } else { | |
8914 | for (i = 24; i < 29; i++) { | |
8915 | env->fiq_regs[i - 24] = env->xregs[i]; | |
8916 | } | |
8917 | env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; | |
593cfa2b | 8918 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; |
ce02049d GB |
8919 | } |
8920 | ||
8921 | env->regs[15] = env->pc; | |
8922 | } | |
8923 | ||
dea8378b PM |
8924 | static void take_aarch32_exception(CPUARMState *env, int new_mode, |
8925 | uint32_t mask, uint32_t offset, | |
8926 | uint32_t newpc) | |
8927 | { | |
8928 | /* Change the CPU state so as to actually take the exception. */ | |
8929 | switch_mode(env, new_mode); | |
8930 | /* | |
8931 | * For exceptions taken to AArch32 we must clear the SS bit in both | |
8932 | * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. | |
8933 | */ | |
8934 | env->uncached_cpsr &= ~PSTATE_SS; | |
8935 | env->spsr = cpsr_read(env); | |
8936 | /* Clear IT bits. */ | |
8937 | env->condexec_bits = 0; | |
8938 | /* Switch to the new mode, and to the correct instruction set. */ | |
8939 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; | |
8940 | /* Set new mode endianness */ | |
8941 | env->uncached_cpsr &= ~CPSR_E; | |
8942 | if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { | |
8943 | env->uncached_cpsr |= CPSR_E; | |
8944 | } | |
829f9fd3 PM |
8945 | /* J and IL must always be cleared for exception entry */ |
8946 | env->uncached_cpsr &= ~(CPSR_IL | CPSR_J); | |
dea8378b PM |
8947 | env->daif |= mask; |
8948 | ||
8949 | if (new_mode == ARM_CPU_MODE_HYP) { | |
8950 | env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0; | |
8951 | env->elr_el[2] = env->regs[15]; | |
8952 | } else { | |
8953 | /* | |
8954 | * this is a lie, as there was no c1_sys on V4T/V5, but who cares | |
8955 | * and we should just guard the thumb mode on V4 | |
8956 | */ | |
8957 | if (arm_feature(env, ARM_FEATURE_V4T)) { | |
8958 | env->thumb = | |
8959 | (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; | |
8960 | } | |
8961 | env->regs[14] = env->regs[15] + offset; | |
8962 | } | |
8963 | env->regs[15] = newpc; | |
8964 | } | |
8965 | ||
b9bc21ff PM |
8966 | static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) |
8967 | { | |
8968 | /* | |
8969 | * Handle exception entry to Hyp mode; this is sufficiently | |
8970 | * different to entry to other AArch32 modes that we handle it | |
8971 | * separately here. | |
8972 | * | |
8973 | * The vector table entry used is always the 0x14 Hyp mode entry point, | |
8974 | * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp. | |
8975 | * The offset applied to the preferred return address is always zero | |
8976 | * (see DDI0487C.a section G1.12.3). | |
8977 | * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. | |
8978 | */ | |
8979 | uint32_t addr, mask; | |
8980 | ARMCPU *cpu = ARM_CPU(cs); | |
8981 | CPUARMState *env = &cpu->env; | |
8982 | ||
8983 | switch (cs->exception_index) { | |
8984 | case EXCP_UDEF: | |
8985 | addr = 0x04; | |
8986 | break; | |
8987 | case EXCP_SWI: | |
8988 | addr = 0x14; | |
8989 | break; | |
8990 | case EXCP_BKPT: | |
8991 | /* Fall through to prefetch abort. */ | |
8992 | case EXCP_PREFETCH_ABORT: | |
8993 | env->cp15.ifar_s = env->exception.vaddress; | |
8994 | qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n", | |
8995 | (uint32_t)env->exception.vaddress); | |
8996 | addr = 0x0c; | |
8997 | break; | |
8998 | case EXCP_DATA_ABORT: | |
8999 | env->cp15.dfar_s = env->exception.vaddress; | |
9000 | qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n", | |
9001 | (uint32_t)env->exception.vaddress); | |
9002 | addr = 0x10; | |
9003 | break; | |
9004 | case EXCP_IRQ: | |
9005 | addr = 0x18; | |
9006 | break; | |
9007 | case EXCP_FIQ: | |
9008 | addr = 0x1c; | |
9009 | break; | |
9010 | case EXCP_HVC: | |
9011 | addr = 0x08; | |
9012 | break; | |
9013 | case EXCP_HYP_TRAP: | |
9014 | addr = 0x14; | |
9015 | default: | |
9016 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
9017 | } | |
9018 | ||
9019 | if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) { | |
2ed08180 PM |
9020 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
9021 | /* | |
9022 | * QEMU syndrome values are v8-style. v7 has the IL bit | |
9023 | * UNK/SBZP for "field not valid" cases, where v8 uses RES1. | |
9024 | * If this is a v7 CPU, squash the IL bit in those cases. | |
9025 | */ | |
9026 | if (cs->exception_index == EXCP_PREFETCH_ABORT || | |
9027 | (cs->exception_index == EXCP_DATA_ABORT && | |
9028 | !(env->exception.syndrome & ARM_EL_ISV)) || | |
9029 | syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) { | |
9030 | env->exception.syndrome &= ~ARM_EL_IL; | |
9031 | } | |
9032 | } | |
b9bc21ff PM |
9033 | env->cp15.esr_el[2] = env->exception.syndrome; |
9034 | } | |
9035 | ||
9036 | if (arm_current_el(env) != 2 && addr < 0x14) { | |
9037 | addr = 0x14; | |
9038 | } | |
9039 | ||
9040 | mask = 0; | |
9041 | if (!(env->cp15.scr_el3 & SCR_EA)) { | |
9042 | mask |= CPSR_A; | |
9043 | } | |
9044 | if (!(env->cp15.scr_el3 & SCR_IRQ)) { | |
9045 | mask |= CPSR_I; | |
9046 | } | |
9047 | if (!(env->cp15.scr_el3 & SCR_FIQ)) { | |
9048 | mask |= CPSR_F; | |
9049 | } | |
9050 | ||
9051 | addr += env->cp15.hvbar; | |
9052 | ||
9053 | take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr); | |
9054 | } | |
9055 | ||
966f758c | 9056 | static void arm_cpu_do_interrupt_aarch32(CPUState *cs) |
b5ff1b31 | 9057 | { |
97a8ea5a AF |
9058 | ARMCPU *cpu = ARM_CPU(cs); |
9059 | CPUARMState *env = &cpu->env; | |
b5ff1b31 FB |
9060 | uint32_t addr; |
9061 | uint32_t mask; | |
9062 | int new_mode; | |
9063 | uint32_t offset; | |
16a906fd | 9064 | uint32_t moe; |
b5ff1b31 | 9065 | |
16a906fd | 9066 | /* If this is a debug exception we must update the DBGDSCR.MOE bits */ |
64b91e3f | 9067 | switch (syn_get_ec(env->exception.syndrome)) { |
16a906fd PM |
9068 | case EC_BREAKPOINT: |
9069 | case EC_BREAKPOINT_SAME_EL: | |
9070 | moe = 1; | |
9071 | break; | |
9072 | case EC_WATCHPOINT: | |
9073 | case EC_WATCHPOINT_SAME_EL: | |
9074 | moe = 10; | |
9075 | break; | |
9076 | case EC_AA32_BKPT: | |
9077 | moe = 3; | |
9078 | break; | |
9079 | case EC_VECTORCATCH: | |
9080 | moe = 5; | |
9081 | break; | |
9082 | default: | |
9083 | moe = 0; | |
9084 | break; | |
9085 | } | |
9086 | ||
9087 | if (moe) { | |
9088 | env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); | |
9089 | } | |
9090 | ||
b9bc21ff PM |
9091 | if (env->exception.target_el == 2) { |
9092 | arm_cpu_do_interrupt_aarch32_hyp(cs); | |
9093 | return; | |
9094 | } | |
9095 | ||
27103424 | 9096 | switch (cs->exception_index) { |
b5ff1b31 FB |
9097 | case EXCP_UDEF: |
9098 | new_mode = ARM_CPU_MODE_UND; | |
9099 | addr = 0x04; | |
9100 | mask = CPSR_I; | |
9101 | if (env->thumb) | |
9102 | offset = 2; | |
9103 | else | |
9104 | offset = 4; | |
9105 | break; | |
9106 | case EXCP_SWI: | |
9107 | new_mode = ARM_CPU_MODE_SVC; | |
9108 | addr = 0x08; | |
9109 | mask = CPSR_I; | |
601d70b9 | 9110 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
9111 | offset = 0; |
9112 | break; | |
06c949e6 | 9113 | case EXCP_BKPT: |
9ee6e8bb PB |
9114 | /* Fall through to prefetch abort. */ |
9115 | case EXCP_PREFETCH_ABORT: | |
88ca1c2d | 9116 | A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); |
b848ce2b | 9117 | A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); |
3f1beaca | 9118 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", |
88ca1c2d | 9119 | env->exception.fsr, (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
9120 | new_mode = ARM_CPU_MODE_ABT; |
9121 | addr = 0x0c; | |
9122 | mask = CPSR_A | CPSR_I; | |
9123 | offset = 4; | |
9124 | break; | |
9125 | case EXCP_DATA_ABORT: | |
4a7e2d73 | 9126 | A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); |
b848ce2b | 9127 | A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); |
3f1beaca | 9128 | qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", |
4a7e2d73 | 9129 | env->exception.fsr, |
6cd8a264 | 9130 | (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
9131 | new_mode = ARM_CPU_MODE_ABT; |
9132 | addr = 0x10; | |
9133 | mask = CPSR_A | CPSR_I; | |
9134 | offset = 8; | |
9135 | break; | |
9136 | case EXCP_IRQ: | |
9137 | new_mode = ARM_CPU_MODE_IRQ; | |
9138 | addr = 0x18; | |
9139 | /* Disable IRQ and imprecise data aborts. */ | |
9140 | mask = CPSR_A | CPSR_I; | |
9141 | offset = 4; | |
de38d23b FA |
9142 | if (env->cp15.scr_el3 & SCR_IRQ) { |
9143 | /* IRQ routed to monitor mode */ | |
9144 | new_mode = ARM_CPU_MODE_MON; | |
9145 | mask |= CPSR_F; | |
9146 | } | |
b5ff1b31 FB |
9147 | break; |
9148 | case EXCP_FIQ: | |
9149 | new_mode = ARM_CPU_MODE_FIQ; | |
9150 | addr = 0x1c; | |
9151 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
9152 | mask = CPSR_A | CPSR_I | CPSR_F; | |
de38d23b FA |
9153 | if (env->cp15.scr_el3 & SCR_FIQ) { |
9154 | /* FIQ routed to monitor mode */ | |
9155 | new_mode = ARM_CPU_MODE_MON; | |
9156 | } | |
b5ff1b31 FB |
9157 | offset = 4; |
9158 | break; | |
87a4b270 PM |
9159 | case EXCP_VIRQ: |
9160 | new_mode = ARM_CPU_MODE_IRQ; | |
9161 | addr = 0x18; | |
9162 | /* Disable IRQ and imprecise data aborts. */ | |
9163 | mask = CPSR_A | CPSR_I; | |
9164 | offset = 4; | |
9165 | break; | |
9166 | case EXCP_VFIQ: | |
9167 | new_mode = ARM_CPU_MODE_FIQ; | |
9168 | addr = 0x1c; | |
9169 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
9170 | mask = CPSR_A | CPSR_I | CPSR_F; | |
9171 | offset = 4; | |
9172 | break; | |
dbe9d163 FA |
9173 | case EXCP_SMC: |
9174 | new_mode = ARM_CPU_MODE_MON; | |
9175 | addr = 0x08; | |
9176 | mask = CPSR_A | CPSR_I | CPSR_F; | |
9177 | offset = 0; | |
9178 | break; | |
b5ff1b31 | 9179 | default: |
a47dddd7 | 9180 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
b5ff1b31 FB |
9181 | return; /* Never happens. Keep compiler happy. */ |
9182 | } | |
e89e51a1 FA |
9183 | |
9184 | if (new_mode == ARM_CPU_MODE_MON) { | |
9185 | addr += env->cp15.mvbar; | |
137feaa9 | 9186 | } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { |
e89e51a1 | 9187 | /* High vectors. When enabled, base address cannot be remapped. */ |
b5ff1b31 | 9188 | addr += 0xffff0000; |
8641136c NR |
9189 | } else { |
9190 | /* ARM v7 architectures provide a vector base address register to remap | |
9191 | * the interrupt vector table. | |
e89e51a1 | 9192 | * This register is only followed in non-monitor mode, and is banked. |
8641136c NR |
9193 | * Note: only bits 31:5 are valid. |
9194 | */ | |
fb6c91ba | 9195 | addr += A32_BANKED_CURRENT_REG_GET(env, vbar); |
b5ff1b31 | 9196 | } |
dbe9d163 FA |
9197 | |
9198 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
9199 | env->cp15.scr_el3 &= ~SCR_NS; | |
9200 | } | |
9201 | ||
dea8378b | 9202 | take_aarch32_exception(env, new_mode, mask, offset, addr); |
b5ff1b31 FB |
9203 | } |
9204 | ||
966f758c PM |
9205 | /* Handle exception entry to a target EL which is using AArch64 */ |
9206 | static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | |
f3a9b694 PM |
9207 | { |
9208 | ARMCPU *cpu = ARM_CPU(cs); | |
9209 | CPUARMState *env = &cpu->env; | |
9210 | unsigned int new_el = env->exception.target_el; | |
9211 | target_ulong addr = env->cp15.vbar_el[new_el]; | |
9212 | unsigned int new_mode = aarch64_pstate_mode(new_el, true); | |
0ab5953b RH |
9213 | unsigned int cur_el = arm_current_el(env); |
9214 | ||
9a05f7b6 RH |
9215 | /* |
9216 | * Note that new_el can never be 0. If cur_el is 0, then | |
9217 | * el0_a64 is is_a64(), else el0_a64 is ignored. | |
9218 | */ | |
9219 | aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); | |
f3a9b694 | 9220 | |
0ab5953b | 9221 | if (cur_el < new_el) { |
3d6f7617 PM |
9222 | /* Entry vector offset depends on whether the implemented EL |
9223 | * immediately lower than the target level is using AArch32 or AArch64 | |
9224 | */ | |
9225 | bool is_aa64; | |
9226 | ||
9227 | switch (new_el) { | |
9228 | case 3: | |
9229 | is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; | |
9230 | break; | |
9231 | case 2: | |
9232 | is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0; | |
9233 | break; | |
9234 | case 1: | |
9235 | is_aa64 = is_a64(env); | |
9236 | break; | |
9237 | default: | |
9238 | g_assert_not_reached(); | |
9239 | } | |
9240 | ||
9241 | if (is_aa64) { | |
f3a9b694 PM |
9242 | addr += 0x400; |
9243 | } else { | |
9244 | addr += 0x600; | |
9245 | } | |
9246 | } else if (pstate_read(env) & PSTATE_SP) { | |
9247 | addr += 0x200; | |
9248 | } | |
9249 | ||
f3a9b694 PM |
9250 | switch (cs->exception_index) { |
9251 | case EXCP_PREFETCH_ABORT: | |
9252 | case EXCP_DATA_ABORT: | |
9253 | env->cp15.far_el[new_el] = env->exception.vaddress; | |
9254 | qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", | |
9255 | env->cp15.far_el[new_el]); | |
9256 | /* fall through */ | |
9257 | case EXCP_BKPT: | |
9258 | case EXCP_UDEF: | |
9259 | case EXCP_SWI: | |
9260 | case EXCP_HVC: | |
9261 | case EXCP_HYP_TRAP: | |
9262 | case EXCP_SMC: | |
4be42f40 PM |
9263 | if (syn_get_ec(env->exception.syndrome) == EC_ADVSIMDFPACCESSTRAP) { |
9264 | /* | |
9265 | * QEMU internal FP/SIMD syndromes from AArch32 include the | |
9266 | * TA and coproc fields which are only exposed if the exception | |
9267 | * is taken to AArch32 Hyp mode. Mask them out to get a valid | |
9268 | * AArch64 format syndrome. | |
9269 | */ | |
9270 | env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20); | |
9271 | } | |
f3a9b694 PM |
9272 | env->cp15.esr_el[new_el] = env->exception.syndrome; |
9273 | break; | |
9274 | case EXCP_IRQ: | |
9275 | case EXCP_VIRQ: | |
9276 | addr += 0x80; | |
9277 | break; | |
9278 | case EXCP_FIQ: | |
9279 | case EXCP_VFIQ: | |
9280 | addr += 0x100; | |
9281 | break; | |
9282 | case EXCP_SEMIHOST: | |
9283 | qemu_log_mask(CPU_LOG_INT, | |
9284 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
9285 | env->xregs[0]); | |
9286 | env->xregs[0] = do_arm_semihosting(env); | |
9287 | return; | |
9288 | default: | |
9289 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
9290 | } | |
9291 | ||
9292 | if (is_a64(env)) { | |
9293 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env); | |
9294 | aarch64_save_sp(env, arm_current_el(env)); | |
9295 | env->elr_el[new_el] = env->pc; | |
9296 | } else { | |
9297 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env); | |
f3a9b694 PM |
9298 | env->elr_el[new_el] = env->regs[15]; |
9299 | ||
9300 | aarch64_sync_32_to_64(env); | |
9301 | ||
9302 | env->condexec_bits = 0; | |
9303 | } | |
9304 | qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", | |
9305 | env->elr_el[new_el]); | |
9306 | ||
9307 | pstate_write(env, PSTATE_DAIF | new_mode); | |
9308 | env->aarch64 = 1; | |
9309 | aarch64_restore_sp(env, new_el); | |
9310 | ||
9311 | env->pc = addr; | |
9312 | ||
9313 | qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", | |
9314 | new_el, env->pc, pstate_read(env)); | |
966f758c PM |
9315 | } |
9316 | ||
904c04de PM |
9317 | static inline bool check_for_semihosting(CPUState *cs) |
9318 | { | |
9319 | /* Check whether this exception is a semihosting call; if so | |
9320 | * then handle it and return true; otherwise return false. | |
9321 | */ | |
9322 | ARMCPU *cpu = ARM_CPU(cs); | |
9323 | CPUARMState *env = &cpu->env; | |
9324 | ||
9325 | if (is_a64(env)) { | |
9326 | if (cs->exception_index == EXCP_SEMIHOST) { | |
9327 | /* This is always the 64-bit semihosting exception. | |
9328 | * The "is this usermode" and "is semihosting enabled" | |
9329 | * checks have been done at translate time. | |
9330 | */ | |
9331 | qemu_log_mask(CPU_LOG_INT, | |
9332 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
9333 | env->xregs[0]); | |
9334 | env->xregs[0] = do_arm_semihosting(env); | |
9335 | return true; | |
9336 | } | |
9337 | return false; | |
9338 | } else { | |
9339 | uint32_t imm; | |
9340 | ||
9341 | /* Only intercept calls from privileged modes, to provide some | |
9342 | * semblance of security. | |
9343 | */ | |
19a6e31c PM |
9344 | if (cs->exception_index != EXCP_SEMIHOST && |
9345 | (!semihosting_enabled() || | |
9346 | ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) { | |
904c04de PM |
9347 | return false; |
9348 | } | |
9349 | ||
9350 | switch (cs->exception_index) { | |
19a6e31c PM |
9351 | case EXCP_SEMIHOST: |
9352 | /* This is always a semihosting call; the "is this usermode" | |
9353 | * and "is semihosting enabled" checks have been done at | |
9354 | * translate time. | |
9355 | */ | |
9356 | break; | |
904c04de PM |
9357 | case EXCP_SWI: |
9358 | /* Check for semihosting interrupt. */ | |
9359 | if (env->thumb) { | |
f9fd40eb | 9360 | imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env)) |
904c04de PM |
9361 | & 0xff; |
9362 | if (imm == 0xab) { | |
9363 | break; | |
9364 | } | |
9365 | } else { | |
f9fd40eb | 9366 | imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env)) |
904c04de PM |
9367 | & 0xffffff; |
9368 | if (imm == 0x123456) { | |
9369 | break; | |
9370 | } | |
9371 | } | |
9372 | return false; | |
9373 | case EXCP_BKPT: | |
9374 | /* See if this is a semihosting syscall. */ | |
9375 | if (env->thumb) { | |
f9fd40eb | 9376 | imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) |
904c04de PM |
9377 | & 0xff; |
9378 | if (imm == 0xab) { | |
9379 | env->regs[15] += 2; | |
9380 | break; | |
9381 | } | |
9382 | } | |
9383 | return false; | |
9384 | default: | |
9385 | return false; | |
9386 | } | |
9387 | ||
9388 | qemu_log_mask(CPU_LOG_INT, | |
9389 | "...handling as semihosting call 0x%x\n", | |
9390 | env->regs[0]); | |
9391 | env->regs[0] = do_arm_semihosting(env); | |
9392 | return true; | |
9393 | } | |
9394 | } | |
9395 | ||
966f758c PM |
9396 | /* Handle a CPU exception for A and R profile CPUs. |
9397 | * Do any appropriate logging, handle PSCI calls, and then hand off | |
9398 | * to the AArch64-entry or AArch32-entry function depending on the | |
9399 | * target exception level's register width. | |
9400 | */ | |
9401 | void arm_cpu_do_interrupt(CPUState *cs) | |
9402 | { | |
9403 | ARMCPU *cpu = ARM_CPU(cs); | |
9404 | CPUARMState *env = &cpu->env; | |
9405 | unsigned int new_el = env->exception.target_el; | |
9406 | ||
531c60a9 | 9407 | assert(!arm_feature(env, ARM_FEATURE_M)); |
966f758c PM |
9408 | |
9409 | arm_log_exception(cs->exception_index); | |
9410 | qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), | |
9411 | new_el); | |
9412 | if (qemu_loglevel_mask(CPU_LOG_INT) | |
9413 | && !excp_is_internal(cs->exception_index)) { | |
6568da45 | 9414 | qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", |
64b91e3f | 9415 | syn_get_ec(env->exception.syndrome), |
966f758c PM |
9416 | env->exception.syndrome); |
9417 | } | |
9418 | ||
9419 | if (arm_is_psci_call(cpu, cs->exception_index)) { | |
9420 | arm_handle_psci_call(cpu); | |
9421 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | |
9422 | return; | |
9423 | } | |
9424 | ||
904c04de PM |
9425 | /* Semihosting semantics depend on the register width of the |
9426 | * code that caused the exception, not the target exception level, | |
9427 | * so must be handled here. | |
966f758c | 9428 | */ |
904c04de PM |
9429 | if (check_for_semihosting(cs)) { |
9430 | return; | |
9431 | } | |
9432 | ||
b5c53d1b AL |
9433 | /* Hooks may change global state so BQL should be held, also the |
9434 | * BQL needs to be held for any modification of | |
9435 | * cs->interrupt_request. | |
9436 | */ | |
9437 | g_assert(qemu_mutex_iothread_locked()); | |
9438 | ||
9439 | arm_call_pre_el_change_hook(cpu); | |
9440 | ||
904c04de PM |
9441 | assert(!excp_is_internal(cs->exception_index)); |
9442 | if (arm_el_is_aa64(env, new_el)) { | |
966f758c PM |
9443 | arm_cpu_do_interrupt_aarch64(cs); |
9444 | } else { | |
9445 | arm_cpu_do_interrupt_aarch32(cs); | |
9446 | } | |
f3a9b694 | 9447 | |
bd7d00fc PM |
9448 | arm_call_el_change_hook(cpu); |
9449 | ||
f3a9b694 PM |
9450 | if (!kvm_enabled()) { |
9451 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
9452 | } | |
9453 | } | |
0480f69a PM |
9454 | |
9455 | /* Return the exception level which controls this address translation regime */ | |
9456 | static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) | |
9457 | { | |
9458 | switch (mmu_idx) { | |
9459 | case ARMMMUIdx_S2NS: | |
9460 | case ARMMMUIdx_S1E2: | |
9461 | return 2; | |
9462 | case ARMMMUIdx_S1E3: | |
9463 | return 3; | |
9464 | case ARMMMUIdx_S1SE0: | |
9465 | return arm_el_is_aa64(env, 3) ? 1 : 3; | |
9466 | case ARMMMUIdx_S1SE1: | |
9467 | case ARMMMUIdx_S1NSE0: | |
9468 | case ARMMMUIdx_S1NSE1: | |
62593718 PM |
9469 | case ARMMMUIdx_MPrivNegPri: |
9470 | case ARMMMUIdx_MUserNegPri: | |
e7b921c2 PM |
9471 | case ARMMMUIdx_MPriv: |
9472 | case ARMMMUIdx_MUser: | |
62593718 PM |
9473 | case ARMMMUIdx_MSPrivNegPri: |
9474 | case ARMMMUIdx_MSUserNegPri: | |
66787c78 | 9475 | case ARMMMUIdx_MSPriv: |
66787c78 | 9476 | case ARMMMUIdx_MSUser: |
0480f69a PM |
9477 | return 1; |
9478 | default: | |
9479 | g_assert_not_reached(); | |
9480 | } | |
9481 | } | |
9482 | ||
9483 | /* Return the SCTLR value which controls this address translation regime */ | |
9484 | static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) | |
9485 | { | |
9486 | return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; | |
9487 | } | |
9488 | ||
9489 | /* Return true if the specified stage of address translation is disabled */ | |
9490 | static inline bool regime_translation_disabled(CPUARMState *env, | |
9491 | ARMMMUIdx mmu_idx) | |
9492 | { | |
29c483a5 | 9493 | if (arm_feature(env, ARM_FEATURE_M)) { |
ecf5e8ea | 9494 | switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & |
3bef7012 PM |
9495 | (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { |
9496 | case R_V7M_MPU_CTRL_ENABLE_MASK: | |
9497 | /* Enabled, but not for HardFault and NMI */ | |
62593718 | 9498 | return mmu_idx & ARM_MMU_IDX_M_NEGPRI; |
3bef7012 PM |
9499 | case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: |
9500 | /* Enabled for all cases */ | |
9501 | return false; | |
9502 | case 0: | |
9503 | default: | |
9504 | /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but | |
9505 | * we warned about that in armv7m_nvic.c when the guest set it. | |
9506 | */ | |
9507 | return true; | |
9508 | } | |
29c483a5 MD |
9509 | } |
9510 | ||
0480f69a | 9511 | if (mmu_idx == ARMMMUIdx_S2NS) { |
9d1bab33 PM |
9512 | /* HCR.DC means HCR.VM behaves as 1 */ |
9513 | return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) == 0; | |
0480f69a | 9514 | } |
3d0e3080 PM |
9515 | |
9516 | if (env->cp15.hcr_el2 & HCR_TGE) { | |
9517 | /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ | |
9518 | if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) { | |
9519 | return true; | |
9520 | } | |
9521 | } | |
9522 | ||
9d1bab33 PM |
9523 | if ((env->cp15.hcr_el2 & HCR_DC) && |
9524 | (mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1)) { | |
9525 | /* HCR.DC means SCTLR_EL1.M behaves as 0 */ | |
9526 | return true; | |
9527 | } | |
9528 | ||
0480f69a PM |
9529 | return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; |
9530 | } | |
9531 | ||
73462ddd PC |
9532 | static inline bool regime_translation_big_endian(CPUARMState *env, |
9533 | ARMMMUIdx mmu_idx) | |
9534 | { | |
9535 | return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; | |
9536 | } | |
9537 | ||
0480f69a PM |
9538 | /* Return the TCR controlling this translation regime */ |
9539 | static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) | |
9540 | { | |
9541 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
68e9c2fe | 9542 | return &env->cp15.vtcr_el2; |
0480f69a PM |
9543 | } |
9544 | return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; | |
9545 | } | |
9546 | ||
8bd5c820 PM |
9547 | /* Convert a possible stage1+2 MMU index into the appropriate |
9548 | * stage 1 MMU index | |
9549 | */ | |
9550 | static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) | |
9551 | { | |
9552 | if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { | |
9553 | mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0); | |
9554 | } | |
9555 | return mmu_idx; | |
9556 | } | |
9557 | ||
aef878be GB |
9558 | /* Return the TTBR associated with this translation regime */ |
9559 | static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, | |
9560 | int ttbrn) | |
9561 | { | |
9562 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
b698e9cf | 9563 | return env->cp15.vttbr_el2; |
aef878be GB |
9564 | } |
9565 | if (ttbrn == 0) { | |
9566 | return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; | |
9567 | } else { | |
9568 | return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; | |
9569 | } | |
9570 | } | |
9571 | ||
0480f69a PM |
9572 | /* Return true if the translation regime is using LPAE format page tables */ |
9573 | static inline bool regime_using_lpae_format(CPUARMState *env, | |
9574 | ARMMMUIdx mmu_idx) | |
9575 | { | |
9576 | int el = regime_el(env, mmu_idx); | |
9577 | if (el == 2 || arm_el_is_aa64(env, el)) { | |
9578 | return true; | |
9579 | } | |
9580 | if (arm_feature(env, ARM_FEATURE_LPAE) | |
9581 | && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { | |
9582 | return true; | |
9583 | } | |
9584 | return false; | |
9585 | } | |
9586 | ||
deb2db99 AR |
9587 | /* Returns true if the stage 1 translation regime is using LPAE format page |
9588 | * tables. Used when raising alignment exceptions, whose FSR changes depending | |
9589 | * on whether the long or short descriptor format is in use. */ | |
9590 | bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) | |
30901475 | 9591 | { |
8bd5c820 | 9592 | mmu_idx = stage_1_mmu_idx(mmu_idx); |
deb2db99 | 9593 | |
30901475 AB |
9594 | return regime_using_lpae_format(env, mmu_idx); |
9595 | } | |
9596 | ||
0480f69a PM |
9597 | static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) |
9598 | { | |
9599 | switch (mmu_idx) { | |
9600 | case ARMMMUIdx_S1SE0: | |
9601 | case ARMMMUIdx_S1NSE0: | |
e7b921c2 | 9602 | case ARMMMUIdx_MUser: |
871bec7c | 9603 | case ARMMMUIdx_MSUser: |
62593718 PM |
9604 | case ARMMMUIdx_MUserNegPri: |
9605 | case ARMMMUIdx_MSUserNegPri: | |
0480f69a PM |
9606 | return true; |
9607 | default: | |
9608 | return false; | |
9609 | case ARMMMUIdx_S12NSE0: | |
9610 | case ARMMMUIdx_S12NSE1: | |
9611 | g_assert_not_reached(); | |
9612 | } | |
9613 | } | |
9614 | ||
0fbf5238 AJ |
9615 | /* Translate section/page access permissions to page |
9616 | * R/W protection flags | |
d76951b6 AJ |
9617 | * |
9618 | * @env: CPUARMState | |
9619 | * @mmu_idx: MMU index indicating required translation regime | |
9620 | * @ap: The 3-bit access permissions (AP[2:0]) | |
9621 | * @domain_prot: The 2-bit domain access permissions | |
0fbf5238 AJ |
9622 | */ |
9623 | static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, | |
9624 | int ap, int domain_prot) | |
9625 | { | |
554b0b09 PM |
9626 | bool is_user = regime_is_user(env, mmu_idx); |
9627 | ||
9628 | if (domain_prot == 3) { | |
9629 | return PAGE_READ | PAGE_WRITE; | |
9630 | } | |
9631 | ||
554b0b09 PM |
9632 | switch (ap) { |
9633 | case 0: | |
9634 | if (arm_feature(env, ARM_FEATURE_V7)) { | |
9635 | return 0; | |
9636 | } | |
554b0b09 PM |
9637 | switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) { |
9638 | case SCTLR_S: | |
9639 | return is_user ? 0 : PAGE_READ; | |
9640 | case SCTLR_R: | |
9641 | return PAGE_READ; | |
9642 | default: | |
9643 | return 0; | |
9644 | } | |
9645 | case 1: | |
9646 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
9647 | case 2: | |
87c3d486 | 9648 | if (is_user) { |
0fbf5238 | 9649 | return PAGE_READ; |
87c3d486 | 9650 | } else { |
554b0b09 | 9651 | return PAGE_READ | PAGE_WRITE; |
87c3d486 | 9652 | } |
554b0b09 PM |
9653 | case 3: |
9654 | return PAGE_READ | PAGE_WRITE; | |
9655 | case 4: /* Reserved. */ | |
9656 | return 0; | |
9657 | case 5: | |
0fbf5238 | 9658 | return is_user ? 0 : PAGE_READ; |
554b0b09 | 9659 | case 6: |
0fbf5238 | 9660 | return PAGE_READ; |
554b0b09 | 9661 | case 7: |
87c3d486 | 9662 | if (!arm_feature(env, ARM_FEATURE_V6K)) { |
554b0b09 | 9663 | return 0; |
87c3d486 | 9664 | } |
0fbf5238 | 9665 | return PAGE_READ; |
554b0b09 | 9666 | default: |
0fbf5238 | 9667 | g_assert_not_reached(); |
554b0b09 | 9668 | } |
b5ff1b31 FB |
9669 | } |
9670 | ||
d76951b6 AJ |
9671 | /* Translate section/page access permissions to page |
9672 | * R/W protection flags. | |
9673 | * | |
d76951b6 | 9674 | * @ap: The 2-bit simple AP (AP[2:1]) |
d8e052b3 | 9675 | * @is_user: TRUE if accessing from PL0 |
d76951b6 | 9676 | */ |
d8e052b3 | 9677 | static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user) |
d76951b6 | 9678 | { |
d76951b6 AJ |
9679 | switch (ap) { |
9680 | case 0: | |
9681 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
9682 | case 1: | |
9683 | return PAGE_READ | PAGE_WRITE; | |
9684 | case 2: | |
9685 | return is_user ? 0 : PAGE_READ; | |
9686 | case 3: | |
9687 | return PAGE_READ; | |
9688 | default: | |
9689 | g_assert_not_reached(); | |
9690 | } | |
9691 | } | |
9692 | ||
d8e052b3 AJ |
9693 | static inline int |
9694 | simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) | |
9695 | { | |
9696 | return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); | |
9697 | } | |
9698 | ||
6ab1a5ee EI |
9699 | /* Translate S2 section/page access permissions to protection flags |
9700 | * | |
9701 | * @env: CPUARMState | |
9702 | * @s2ap: The 2-bit stage2 access permissions (S2AP) | |
9703 | * @xn: XN (execute-never) bit | |
9704 | */ | |
9705 | static int get_S2prot(CPUARMState *env, int s2ap, int xn) | |
9706 | { | |
9707 | int prot = 0; | |
9708 | ||
9709 | if (s2ap & 1) { | |
9710 | prot |= PAGE_READ; | |
9711 | } | |
9712 | if (s2ap & 2) { | |
9713 | prot |= PAGE_WRITE; | |
9714 | } | |
9715 | if (!xn) { | |
dfda6837 SS |
9716 | if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { |
9717 | prot |= PAGE_EXEC; | |
9718 | } | |
6ab1a5ee EI |
9719 | } |
9720 | return prot; | |
9721 | } | |
9722 | ||
d8e052b3 AJ |
9723 | /* Translate section/page access permissions to protection flags |
9724 | * | |
9725 | * @env: CPUARMState | |
9726 | * @mmu_idx: MMU index indicating required translation regime | |
9727 | * @is_aa64: TRUE if AArch64 | |
9728 | * @ap: The 2-bit simple AP (AP[2:1]) | |
9729 | * @ns: NS (non-secure) bit | |
9730 | * @xn: XN (execute-never) bit | |
9731 | * @pxn: PXN (privileged execute-never) bit | |
9732 | */ | |
9733 | static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, | |
9734 | int ap, int ns, int xn, int pxn) | |
9735 | { | |
9736 | bool is_user = regime_is_user(env, mmu_idx); | |
9737 | int prot_rw, user_rw; | |
9738 | bool have_wxn; | |
9739 | int wxn = 0; | |
9740 | ||
9741 | assert(mmu_idx != ARMMMUIdx_S2NS); | |
9742 | ||
9743 | user_rw = simple_ap_to_rw_prot_is_user(ap, true); | |
9744 | if (is_user) { | |
9745 | prot_rw = user_rw; | |
9746 | } else { | |
9747 | prot_rw = simple_ap_to_rw_prot_is_user(ap, false); | |
9748 | } | |
9749 | ||
9750 | if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { | |
9751 | return prot_rw; | |
9752 | } | |
9753 | ||
9754 | /* TODO have_wxn should be replaced with | |
9755 | * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) | |
9756 | * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE | |
9757 | * compatible processors have EL2, which is required for [U]WXN. | |
9758 | */ | |
9759 | have_wxn = arm_feature(env, ARM_FEATURE_LPAE); | |
9760 | ||
9761 | if (have_wxn) { | |
9762 | wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN; | |
9763 | } | |
9764 | ||
9765 | if (is_aa64) { | |
9766 | switch (regime_el(env, mmu_idx)) { | |
9767 | case 1: | |
9768 | if (!is_user) { | |
9769 | xn = pxn || (user_rw & PAGE_WRITE); | |
9770 | } | |
9771 | break; | |
9772 | case 2: | |
9773 | case 3: | |
9774 | break; | |
9775 | } | |
9776 | } else if (arm_feature(env, ARM_FEATURE_V7)) { | |
9777 | switch (regime_el(env, mmu_idx)) { | |
9778 | case 1: | |
9779 | case 3: | |
9780 | if (is_user) { | |
9781 | xn = xn || !(user_rw & PAGE_READ); | |
9782 | } else { | |
9783 | int uwxn = 0; | |
9784 | if (have_wxn) { | |
9785 | uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN; | |
9786 | } | |
9787 | xn = xn || !(prot_rw & PAGE_READ) || pxn || | |
9788 | (uwxn && (user_rw & PAGE_WRITE)); | |
9789 | } | |
9790 | break; | |
9791 | case 2: | |
9792 | break; | |
9793 | } | |
9794 | } else { | |
9795 | xn = wxn = 0; | |
9796 | } | |
9797 | ||
9798 | if (xn || (wxn && (prot_rw & PAGE_WRITE))) { | |
9799 | return prot_rw; | |
9800 | } | |
9801 | return prot_rw | PAGE_EXEC; | |
9802 | } | |
9803 | ||
0480f69a PM |
9804 | static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, |
9805 | uint32_t *table, uint32_t address) | |
b2fa1797 | 9806 | { |
0480f69a | 9807 | /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ |
0480f69a | 9808 | TCR *tcr = regime_tcr(env, mmu_idx); |
11f136ee | 9809 | |
11f136ee FA |
9810 | if (address & tcr->mask) { |
9811 | if (tcr->raw_tcr & TTBCR_PD1) { | |
e389be16 FA |
9812 | /* Translation table walk disabled for TTBR1 */ |
9813 | return false; | |
9814 | } | |
aef878be | 9815 | *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; |
e389be16 | 9816 | } else { |
11f136ee | 9817 | if (tcr->raw_tcr & TTBCR_PD0) { |
e389be16 FA |
9818 | /* Translation table walk disabled for TTBR0 */ |
9819 | return false; | |
9820 | } | |
aef878be | 9821 | *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; |
e389be16 FA |
9822 | } |
9823 | *table |= (address >> 18) & 0x3ffc; | |
9824 | return true; | |
b2fa1797 PB |
9825 | } |
9826 | ||
37785977 EI |
9827 | /* Translate a S1 pagetable walk through S2 if needed. */ |
9828 | static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, | |
9829 | hwaddr addr, MemTxAttrs txattrs, | |
37785977 EI |
9830 | ARMMMUFaultInfo *fi) |
9831 | { | |
9832 | if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) && | |
9833 | !regime_translation_disabled(env, ARMMMUIdx_S2NS)) { | |
9834 | target_ulong s2size; | |
9835 | hwaddr s2pa; | |
9836 | int s2prot; | |
9837 | int ret; | |
eadb2feb PM |
9838 | ARMCacheAttrs cacheattrs = {}; |
9839 | ARMCacheAttrs *pcacheattrs = NULL; | |
9840 | ||
9841 | if (env->cp15.hcr_el2 & HCR_PTW) { | |
9842 | /* | |
9843 | * PTW means we must fault if this S1 walk touches S2 Device | |
9844 | * memory; otherwise we don't care about the attributes and can | |
9845 | * save the S2 translation the effort of computing them. | |
9846 | */ | |
9847 | pcacheattrs = &cacheattrs; | |
9848 | } | |
37785977 EI |
9849 | |
9850 | ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, | |
eadb2feb | 9851 | &txattrs, &s2prot, &s2size, fi, pcacheattrs); |
37785977 | 9852 | if (ret) { |
3b39d734 | 9853 | assert(fi->type != ARMFault_None); |
37785977 EI |
9854 | fi->s2addr = addr; |
9855 | fi->stage2 = true; | |
9856 | fi->s1ptw = true; | |
9857 | return ~0; | |
9858 | } | |
eadb2feb PM |
9859 | if (pcacheattrs && (pcacheattrs->attrs & 0xf0) == 0) { |
9860 | /* Access was to Device memory: generate Permission fault */ | |
9861 | fi->type = ARMFault_Permission; | |
9862 | fi->s2addr = addr; | |
9863 | fi->stage2 = true; | |
9864 | fi->s1ptw = true; | |
9865 | return ~0; | |
9866 | } | |
37785977 EI |
9867 | addr = s2pa; |
9868 | } | |
9869 | return addr; | |
9870 | } | |
9871 | ||
14577270 | 9872 | /* All loads done in the course of a page table walk go through here. */ |
a614e698 | 9873 | static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, |
3795a6de | 9874 | ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) |
ebca90e4 | 9875 | { |
a614e698 EI |
9876 | ARMCPU *cpu = ARM_CPU(cs); |
9877 | CPUARMState *env = &cpu->env; | |
ebca90e4 | 9878 | MemTxAttrs attrs = {}; |
3b39d734 | 9879 | MemTxResult result = MEMTX_OK; |
5ce4ff65 | 9880 | AddressSpace *as; |
3b39d734 | 9881 | uint32_t data; |
ebca90e4 PM |
9882 | |
9883 | attrs.secure = is_secure; | |
5ce4ff65 | 9884 | as = arm_addressspace(cs, attrs); |
3795a6de | 9885 | addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi); |
a614e698 EI |
9886 | if (fi->s1ptw) { |
9887 | return 0; | |
9888 | } | |
73462ddd | 9889 | if (regime_translation_big_endian(env, mmu_idx)) { |
3b39d734 | 9890 | data = address_space_ldl_be(as, addr, attrs, &result); |
73462ddd | 9891 | } else { |
3b39d734 | 9892 | data = address_space_ldl_le(as, addr, attrs, &result); |
73462ddd | 9893 | } |
3b39d734 PM |
9894 | if (result == MEMTX_OK) { |
9895 | return data; | |
9896 | } | |
9897 | fi->type = ARMFault_SyncExternalOnWalk; | |
9898 | fi->ea = arm_extabort_type(result); | |
9899 | return 0; | |
ebca90e4 PM |
9900 | } |
9901 | ||
37785977 | 9902 | static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, |
3795a6de | 9903 | ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) |
ebca90e4 | 9904 | { |
37785977 EI |
9905 | ARMCPU *cpu = ARM_CPU(cs); |
9906 | CPUARMState *env = &cpu->env; | |
ebca90e4 | 9907 | MemTxAttrs attrs = {}; |
3b39d734 | 9908 | MemTxResult result = MEMTX_OK; |
5ce4ff65 | 9909 | AddressSpace *as; |
9aea1ea3 | 9910 | uint64_t data; |
ebca90e4 PM |
9911 | |
9912 | attrs.secure = is_secure; | |
5ce4ff65 | 9913 | as = arm_addressspace(cs, attrs); |
3795a6de | 9914 | addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi); |
37785977 EI |
9915 | if (fi->s1ptw) { |
9916 | return 0; | |
9917 | } | |
73462ddd | 9918 | if (regime_translation_big_endian(env, mmu_idx)) { |
3b39d734 | 9919 | data = address_space_ldq_be(as, addr, attrs, &result); |
73462ddd | 9920 | } else { |
3b39d734 PM |
9921 | data = address_space_ldq_le(as, addr, attrs, &result); |
9922 | } | |
9923 | if (result == MEMTX_OK) { | |
9924 | return data; | |
73462ddd | 9925 | } |
3b39d734 PM |
9926 | fi->type = ARMFault_SyncExternalOnWalk; |
9927 | fi->ea = arm_extabort_type(result); | |
9928 | return 0; | |
ebca90e4 PM |
9929 | } |
9930 | ||
b7cc4e82 | 9931 | static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, |
03ae85f8 | 9932 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
b7cc4e82 | 9933 | hwaddr *phys_ptr, int *prot, |
f989983e | 9934 | target_ulong *page_size, |
e14b5a23 | 9935 | ARMMMUFaultInfo *fi) |
b5ff1b31 | 9936 | { |
70d74660 | 9937 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
f989983e | 9938 | int level = 1; |
b5ff1b31 FB |
9939 | uint32_t table; |
9940 | uint32_t desc; | |
9941 | int type; | |
9942 | int ap; | |
e389be16 | 9943 | int domain = 0; |
dd4ebc2e | 9944 | int domain_prot; |
a8170e5e | 9945 | hwaddr phys_addr; |
0480f69a | 9946 | uint32_t dacr; |
b5ff1b31 | 9947 | |
9ee6e8bb PB |
9948 | /* Pagetable walk. */ |
9949 | /* Lookup l1 descriptor. */ | |
0480f69a | 9950 | if (!get_level1_table_address(env, mmu_idx, &table, address)) { |
e389be16 | 9951 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ |
f989983e | 9952 | fi->type = ARMFault_Translation; |
e389be16 FA |
9953 | goto do_fault; |
9954 | } | |
a614e698 | 9955 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 9956 | mmu_idx, fi); |
3b39d734 PM |
9957 | if (fi->type != ARMFault_None) { |
9958 | goto do_fault; | |
9959 | } | |
9ee6e8bb | 9960 | type = (desc & 3); |
dd4ebc2e | 9961 | domain = (desc >> 5) & 0x0f; |
0480f69a PM |
9962 | if (regime_el(env, mmu_idx) == 1) { |
9963 | dacr = env->cp15.dacr_ns; | |
9964 | } else { | |
9965 | dacr = env->cp15.dacr_s; | |
9966 | } | |
9967 | domain_prot = (dacr >> (domain * 2)) & 3; | |
9ee6e8bb | 9968 | if (type == 0) { |
601d70b9 | 9969 | /* Section translation fault. */ |
f989983e | 9970 | fi->type = ARMFault_Translation; |
9ee6e8bb PB |
9971 | goto do_fault; |
9972 | } | |
f989983e PM |
9973 | if (type != 2) { |
9974 | level = 2; | |
9975 | } | |
dd4ebc2e | 9976 | if (domain_prot == 0 || domain_prot == 2) { |
f989983e | 9977 | fi->type = ARMFault_Domain; |
9ee6e8bb PB |
9978 | goto do_fault; |
9979 | } | |
9980 | if (type == 2) { | |
9981 | /* 1Mb section. */ | |
9982 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
9983 | ap = (desc >> 10) & 3; | |
d4c430a8 | 9984 | *page_size = 1024 * 1024; |
9ee6e8bb PB |
9985 | } else { |
9986 | /* Lookup l2 entry. */ | |
554b0b09 PM |
9987 | if (type == 1) { |
9988 | /* Coarse pagetable. */ | |
9989 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
9990 | } else { | |
9991 | /* Fine pagetable. */ | |
9992 | table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); | |
9993 | } | |
a614e698 | 9994 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 9995 | mmu_idx, fi); |
3b39d734 PM |
9996 | if (fi->type != ARMFault_None) { |
9997 | goto do_fault; | |
9998 | } | |
9ee6e8bb PB |
9999 | switch (desc & 3) { |
10000 | case 0: /* Page translation fault. */ | |
f989983e | 10001 | fi->type = ARMFault_Translation; |
9ee6e8bb PB |
10002 | goto do_fault; |
10003 | case 1: /* 64k page. */ | |
10004 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
10005 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
d4c430a8 | 10006 | *page_size = 0x10000; |
ce819861 | 10007 | break; |
9ee6e8bb PB |
10008 | case 2: /* 4k page. */ |
10009 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
c10f7fc3 | 10010 | ap = (desc >> (4 + ((address >> 9) & 6))) & 3; |
d4c430a8 | 10011 | *page_size = 0x1000; |
ce819861 | 10012 | break; |
fc1891c7 | 10013 | case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ |
554b0b09 | 10014 | if (type == 1) { |
fc1891c7 PM |
10015 | /* ARMv6/XScale extended small page format */ |
10016 | if (arm_feature(env, ARM_FEATURE_XSCALE) | |
10017 | || arm_feature(env, ARM_FEATURE_V6)) { | |
554b0b09 | 10018 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
fc1891c7 | 10019 | *page_size = 0x1000; |
554b0b09 | 10020 | } else { |
fc1891c7 PM |
10021 | /* UNPREDICTABLE in ARMv5; we choose to take a |
10022 | * page translation fault. | |
10023 | */ | |
f989983e | 10024 | fi->type = ARMFault_Translation; |
554b0b09 PM |
10025 | goto do_fault; |
10026 | } | |
10027 | } else { | |
10028 | phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); | |
fc1891c7 | 10029 | *page_size = 0x400; |
554b0b09 | 10030 | } |
9ee6e8bb | 10031 | ap = (desc >> 4) & 3; |
ce819861 PB |
10032 | break; |
10033 | default: | |
9ee6e8bb PB |
10034 | /* Never happens, but compiler isn't smart enough to tell. */ |
10035 | abort(); | |
ce819861 | 10036 | } |
9ee6e8bb | 10037 | } |
0fbf5238 AJ |
10038 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); |
10039 | *prot |= *prot ? PAGE_EXEC : 0; | |
10040 | if (!(*prot & (1 << access_type))) { | |
9ee6e8bb | 10041 | /* Access permission fault. */ |
f989983e | 10042 | fi->type = ARMFault_Permission; |
9ee6e8bb PB |
10043 | goto do_fault; |
10044 | } | |
10045 | *phys_ptr = phys_addr; | |
b7cc4e82 | 10046 | return false; |
9ee6e8bb | 10047 | do_fault: |
f989983e PM |
10048 | fi->domain = domain; |
10049 | fi->level = level; | |
b7cc4e82 | 10050 | return true; |
9ee6e8bb PB |
10051 | } |
10052 | ||
b7cc4e82 | 10053 | static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, |
03ae85f8 | 10054 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
b7cc4e82 | 10055 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, |
f06cf243 | 10056 | target_ulong *page_size, ARMMMUFaultInfo *fi) |
9ee6e8bb | 10057 | { |
70d74660 | 10058 | CPUState *cs = CPU(arm_env_get_cpu(env)); |
f06cf243 | 10059 | int level = 1; |
9ee6e8bb PB |
10060 | uint32_t table; |
10061 | uint32_t desc; | |
10062 | uint32_t xn; | |
de9b05b8 | 10063 | uint32_t pxn = 0; |
9ee6e8bb PB |
10064 | int type; |
10065 | int ap; | |
de9b05b8 | 10066 | int domain = 0; |
dd4ebc2e | 10067 | int domain_prot; |
a8170e5e | 10068 | hwaddr phys_addr; |
0480f69a | 10069 | uint32_t dacr; |
8bf5b6a9 | 10070 | bool ns; |
9ee6e8bb PB |
10071 | |
10072 | /* Pagetable walk. */ | |
10073 | /* Lookup l1 descriptor. */ | |
0480f69a | 10074 | if (!get_level1_table_address(env, mmu_idx, &table, address)) { |
e389be16 | 10075 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ |
f06cf243 | 10076 | fi->type = ARMFault_Translation; |
e389be16 FA |
10077 | goto do_fault; |
10078 | } | |
a614e698 | 10079 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 10080 | mmu_idx, fi); |
3b39d734 PM |
10081 | if (fi->type != ARMFault_None) { |
10082 | goto do_fault; | |
10083 | } | |
9ee6e8bb | 10084 | type = (desc & 3); |
de9b05b8 PM |
10085 | if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { |
10086 | /* Section translation fault, or attempt to use the encoding | |
10087 | * which is Reserved on implementations without PXN. | |
10088 | */ | |
f06cf243 | 10089 | fi->type = ARMFault_Translation; |
9ee6e8bb | 10090 | goto do_fault; |
de9b05b8 PM |
10091 | } |
10092 | if ((type == 1) || !(desc & (1 << 18))) { | |
10093 | /* Page or Section. */ | |
dd4ebc2e | 10094 | domain = (desc >> 5) & 0x0f; |
9ee6e8bb | 10095 | } |
0480f69a PM |
10096 | if (regime_el(env, mmu_idx) == 1) { |
10097 | dacr = env->cp15.dacr_ns; | |
10098 | } else { | |
10099 | dacr = env->cp15.dacr_s; | |
10100 | } | |
f06cf243 PM |
10101 | if (type == 1) { |
10102 | level = 2; | |
10103 | } | |
0480f69a | 10104 | domain_prot = (dacr >> (domain * 2)) & 3; |
dd4ebc2e | 10105 | if (domain_prot == 0 || domain_prot == 2) { |
f06cf243 PM |
10106 | /* Section or Page domain fault */ |
10107 | fi->type = ARMFault_Domain; | |
9ee6e8bb PB |
10108 | goto do_fault; |
10109 | } | |
de9b05b8 | 10110 | if (type != 1) { |
9ee6e8bb PB |
10111 | if (desc & (1 << 18)) { |
10112 | /* Supersection. */ | |
10113 | phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); | |
4e42a6ca SF |
10114 | phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32; |
10115 | phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36; | |
d4c430a8 | 10116 | *page_size = 0x1000000; |
b5ff1b31 | 10117 | } else { |
9ee6e8bb PB |
10118 | /* Section. */ |
10119 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
d4c430a8 | 10120 | *page_size = 0x100000; |
b5ff1b31 | 10121 | } |
9ee6e8bb PB |
10122 | ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
10123 | xn = desc & (1 << 4); | |
de9b05b8 | 10124 | pxn = desc & 1; |
8bf5b6a9 | 10125 | ns = extract32(desc, 19, 1); |
9ee6e8bb | 10126 | } else { |
de9b05b8 PM |
10127 | if (arm_feature(env, ARM_FEATURE_PXN)) { |
10128 | pxn = (desc >> 2) & 1; | |
10129 | } | |
8bf5b6a9 | 10130 | ns = extract32(desc, 3, 1); |
9ee6e8bb PB |
10131 | /* Lookup l2 entry. */ |
10132 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
a614e698 | 10133 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 10134 | mmu_idx, fi); |
3b39d734 PM |
10135 | if (fi->type != ARMFault_None) { |
10136 | goto do_fault; | |
10137 | } | |
9ee6e8bb PB |
10138 | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
10139 | switch (desc & 3) { | |
10140 | case 0: /* Page translation fault. */ | |
f06cf243 | 10141 | fi->type = ARMFault_Translation; |
b5ff1b31 | 10142 | goto do_fault; |
9ee6e8bb PB |
10143 | case 1: /* 64k page. */ |
10144 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
10145 | xn = desc & (1 << 15); | |
d4c430a8 | 10146 | *page_size = 0x10000; |
9ee6e8bb PB |
10147 | break; |
10148 | case 2: case 3: /* 4k page. */ | |
10149 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
10150 | xn = desc & 1; | |
d4c430a8 | 10151 | *page_size = 0x1000; |
9ee6e8bb PB |
10152 | break; |
10153 | default: | |
10154 | /* Never happens, but compiler isn't smart enough to tell. */ | |
10155 | abort(); | |
b5ff1b31 | 10156 | } |
9ee6e8bb | 10157 | } |
dd4ebc2e | 10158 | if (domain_prot == 3) { |
c0034328 JR |
10159 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
10160 | } else { | |
0480f69a | 10161 | if (pxn && !regime_is_user(env, mmu_idx)) { |
de9b05b8 PM |
10162 | xn = 1; |
10163 | } | |
f06cf243 PM |
10164 | if (xn && access_type == MMU_INST_FETCH) { |
10165 | fi->type = ARMFault_Permission; | |
c0034328 | 10166 | goto do_fault; |
f06cf243 | 10167 | } |
9ee6e8bb | 10168 | |
d76951b6 AJ |
10169 | if (arm_feature(env, ARM_FEATURE_V6K) && |
10170 | (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { | |
10171 | /* The simplified model uses AP[0] as an access control bit. */ | |
10172 | if ((ap & 1) == 0) { | |
10173 | /* Access flag fault. */ | |
f06cf243 | 10174 | fi->type = ARMFault_AccessFlag; |
d76951b6 AJ |
10175 | goto do_fault; |
10176 | } | |
10177 | *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); | |
10178 | } else { | |
10179 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); | |
c0034328 | 10180 | } |
0fbf5238 AJ |
10181 | if (*prot && !xn) { |
10182 | *prot |= PAGE_EXEC; | |
10183 | } | |
10184 | if (!(*prot & (1 << access_type))) { | |
c0034328 | 10185 | /* Access permission fault. */ |
f06cf243 | 10186 | fi->type = ARMFault_Permission; |
c0034328 JR |
10187 | goto do_fault; |
10188 | } | |
3ad493fc | 10189 | } |
8bf5b6a9 PM |
10190 | if (ns) { |
10191 | /* The NS bit will (as required by the architecture) have no effect if | |
10192 | * the CPU doesn't support TZ or this is a non-secure translation | |
10193 | * regime, because the attribute will already be non-secure. | |
10194 | */ | |
10195 | attrs->secure = false; | |
10196 | } | |
9ee6e8bb | 10197 | *phys_ptr = phys_addr; |
b7cc4e82 | 10198 | return false; |
b5ff1b31 | 10199 | do_fault: |
f06cf243 PM |
10200 | fi->domain = domain; |
10201 | fi->level = level; | |
b7cc4e82 | 10202 | return true; |
b5ff1b31 FB |
10203 | } |
10204 | ||
1853d5a9 | 10205 | /* |
a0e966c9 | 10206 | * check_s2_mmu_setup |
1853d5a9 EI |
10207 | * @cpu: ARMCPU |
10208 | * @is_aa64: True if the translation regime is in AArch64 state | |
10209 | * @startlevel: Suggested starting level | |
10210 | * @inputsize: Bitsize of IPAs | |
10211 | * @stride: Page-table stride (See the ARM ARM) | |
10212 | * | |
a0e966c9 EI |
10213 | * Returns true if the suggested S2 translation parameters are OK and |
10214 | * false otherwise. | |
1853d5a9 | 10215 | */ |
a0e966c9 EI |
10216 | static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, |
10217 | int inputsize, int stride) | |
1853d5a9 | 10218 | { |
98d68ec2 EI |
10219 | const int grainsize = stride + 3; |
10220 | int startsizecheck; | |
10221 | ||
1853d5a9 EI |
10222 | /* Negative levels are never allowed. */ |
10223 | if (level < 0) { | |
10224 | return false; | |
10225 | } | |
10226 | ||
98d68ec2 EI |
10227 | startsizecheck = inputsize - ((3 - level) * stride + grainsize); |
10228 | if (startsizecheck < 1 || startsizecheck > stride + 4) { | |
10229 | return false; | |
10230 | } | |
10231 | ||
1853d5a9 | 10232 | if (is_aa64) { |
3526423e | 10233 | CPUARMState *env = &cpu->env; |
1853d5a9 EI |
10234 | unsigned int pamax = arm_pamax(cpu); |
10235 | ||
10236 | switch (stride) { | |
10237 | case 13: /* 64KB Pages. */ | |
10238 | if (level == 0 || (level == 1 && pamax <= 42)) { | |
10239 | return false; | |
10240 | } | |
10241 | break; | |
10242 | case 11: /* 16KB Pages. */ | |
10243 | if (level == 0 || (level == 1 && pamax <= 40)) { | |
10244 | return false; | |
10245 | } | |
10246 | break; | |
10247 | case 9: /* 4KB Pages. */ | |
10248 | if (level == 0 && pamax <= 42) { | |
10249 | return false; | |
10250 | } | |
10251 | break; | |
10252 | default: | |
10253 | g_assert_not_reached(); | |
10254 | } | |
3526423e EI |
10255 | |
10256 | /* Inputsize checks. */ | |
10257 | if (inputsize > pamax && | |
10258 | (arm_el_is_aa64(env, 1) || inputsize > 40)) { | |
10259 | /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ | |
10260 | return false; | |
10261 | } | |
1853d5a9 | 10262 | } else { |
1853d5a9 EI |
10263 | /* AArch32 only supports 4KB pages. Assert on that. */ |
10264 | assert(stride == 9); | |
10265 | ||
10266 | if (level == 0) { | |
10267 | return false; | |
10268 | } | |
1853d5a9 EI |
10269 | } |
10270 | return true; | |
10271 | } | |
10272 | ||
5b2d261d AB |
10273 | /* Translate from the 4-bit stage 2 representation of |
10274 | * memory attributes (without cache-allocation hints) to | |
10275 | * the 8-bit representation of the stage 1 MAIR registers | |
10276 | * (which includes allocation hints). | |
10277 | * | |
10278 | * ref: shared/translation/attrs/S2AttrDecode() | |
10279 | * .../S2ConvertAttrsHints() | |
10280 | */ | |
10281 | static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) | |
10282 | { | |
10283 | uint8_t hiattr = extract32(s2attrs, 2, 2); | |
10284 | uint8_t loattr = extract32(s2attrs, 0, 2); | |
10285 | uint8_t hihint = 0, lohint = 0; | |
10286 | ||
10287 | if (hiattr != 0) { /* normal memory */ | |
10288 | if ((env->cp15.hcr_el2 & HCR_CD) != 0) { /* cache disabled */ | |
10289 | hiattr = loattr = 1; /* non-cacheable */ | |
10290 | } else { | |
10291 | if (hiattr != 1) { /* Write-through or write-back */ | |
10292 | hihint = 3; /* RW allocate */ | |
10293 | } | |
10294 | if (loattr != 1) { /* Write-through or write-back */ | |
10295 | lohint = 3; /* RW allocate */ | |
10296 | } | |
10297 | } | |
10298 | } | |
10299 | ||
10300 | return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; | |
10301 | } | |
10302 | ||
e737ed2a RH |
10303 | ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, |
10304 | ARMMMUIdx mmu_idx) | |
ba97be9f RH |
10305 | { |
10306 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | |
10307 | uint32_t el = regime_el(env, mmu_idx); | |
8220af7e | 10308 | bool tbi, tbid, epd, hpd, using16k, using64k; |
ba97be9f RH |
10309 | int select, tsz; |
10310 | ||
10311 | /* | |
10312 | * Bit 55 is always between the two regions, and is canonical for | |
10313 | * determining if address tagging is enabled. | |
10314 | */ | |
10315 | select = extract64(va, 55, 1); | |
10316 | ||
10317 | if (el > 1) { | |
10318 | tsz = extract32(tcr, 0, 6); | |
10319 | using64k = extract32(tcr, 14, 1); | |
10320 | using16k = extract32(tcr, 15, 1); | |
10321 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
10322 | /* VTCR_EL2 */ | |
8220af7e | 10323 | tbi = tbid = hpd = false; |
ba97be9f RH |
10324 | } else { |
10325 | tbi = extract32(tcr, 20, 1); | |
10326 | hpd = extract32(tcr, 24, 1); | |
8220af7e | 10327 | tbid = extract32(tcr, 29, 1); |
ba97be9f RH |
10328 | } |
10329 | epd = false; | |
10330 | } else if (!select) { | |
10331 | tsz = extract32(tcr, 0, 6); | |
10332 | epd = extract32(tcr, 7, 1); | |
10333 | using64k = extract32(tcr, 14, 1); | |
10334 | using16k = extract32(tcr, 15, 1); | |
10335 | tbi = extract64(tcr, 37, 1); | |
10336 | hpd = extract64(tcr, 41, 1); | |
8220af7e | 10337 | tbid = extract64(tcr, 51, 1); |
ba97be9f RH |
10338 | } else { |
10339 | int tg = extract32(tcr, 30, 2); | |
10340 | using16k = tg == 1; | |
10341 | using64k = tg == 3; | |
10342 | tsz = extract32(tcr, 16, 6); | |
10343 | epd = extract32(tcr, 23, 1); | |
10344 | tbi = extract64(tcr, 38, 1); | |
10345 | hpd = extract64(tcr, 42, 1); | |
8220af7e | 10346 | tbid = extract64(tcr, 52, 1); |
ba97be9f RH |
10347 | } |
10348 | tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ | |
10349 | tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ | |
10350 | ||
10351 | return (ARMVAParameters) { | |
10352 | .tsz = tsz, | |
10353 | .select = select, | |
10354 | .tbi = tbi, | |
8220af7e | 10355 | .tbid = tbid, |
ba97be9f RH |
10356 | .epd = epd, |
10357 | .hpd = hpd, | |
10358 | .using16k = using16k, | |
10359 | .using64k = using64k, | |
10360 | }; | |
10361 | } | |
10362 | ||
e737ed2a RH |
10363 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, |
10364 | ARMMMUIdx mmu_idx, bool data) | |
10365 | { | |
8220af7e RH |
10366 | ARMVAParameters ret = aa64_va_parameters_both(env, va, mmu_idx); |
10367 | ||
10368 | /* Present TBI as a composite with TBID. */ | |
10369 | ret.tbi &= (data || !ret.tbid); | |
10370 | return ret; | |
e737ed2a RH |
10371 | } |
10372 | ||
ba97be9f RH |
10373 | static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, |
10374 | ARMMMUIdx mmu_idx) | |
10375 | { | |
10376 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | |
10377 | uint32_t el = regime_el(env, mmu_idx); | |
10378 | int select, tsz; | |
10379 | bool epd, hpd; | |
10380 | ||
10381 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
10382 | /* VTCR */ | |
10383 | bool sext = extract32(tcr, 4, 1); | |
10384 | bool sign = extract32(tcr, 3, 1); | |
10385 | ||
10386 | /* | |
10387 | * If the sign-extend bit is not the same as t0sz[3], the result | |
10388 | * is unpredictable. Flag this as a guest error. | |
10389 | */ | |
10390 | if (sign != sext) { | |
10391 | qemu_log_mask(LOG_GUEST_ERROR, | |
10392 | "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); | |
10393 | } | |
10394 | tsz = sextract32(tcr, 0, 4) + 8; | |
10395 | select = 0; | |
10396 | hpd = false; | |
10397 | epd = false; | |
10398 | } else if (el == 2) { | |
10399 | /* HTCR */ | |
10400 | tsz = extract32(tcr, 0, 3); | |
10401 | select = 0; | |
10402 | hpd = extract64(tcr, 24, 1); | |
10403 | epd = false; | |
10404 | } else { | |
10405 | int t0sz = extract32(tcr, 0, 3); | |
10406 | int t1sz = extract32(tcr, 16, 3); | |
10407 | ||
10408 | if (t1sz == 0) { | |
10409 | select = va > (0xffffffffu >> t0sz); | |
10410 | } else { | |
10411 | /* Note that we will detect errors later. */ | |
10412 | select = va >= ~(0xffffffffu >> t1sz); | |
10413 | } | |
10414 | if (!select) { | |
10415 | tsz = t0sz; | |
10416 | epd = extract32(tcr, 7, 1); | |
10417 | hpd = extract64(tcr, 41, 1); | |
10418 | } else { | |
10419 | tsz = t1sz; | |
10420 | epd = extract32(tcr, 23, 1); | |
10421 | hpd = extract64(tcr, 42, 1); | |
10422 | } | |
10423 | /* For aarch32, hpd0 is not enabled without t2e as well. */ | |
10424 | hpd &= extract32(tcr, 6, 1); | |
10425 | } | |
10426 | ||
10427 | return (ARMVAParameters) { | |
10428 | .tsz = tsz, | |
10429 | .select = select, | |
10430 | .epd = epd, | |
10431 | .hpd = hpd, | |
10432 | }; | |
10433 | } | |
10434 | ||
b7cc4e82 | 10435 | static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
03ae85f8 | 10436 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
b7cc4e82 | 10437 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, |
da909b2c | 10438 | target_ulong *page_size_ptr, |
5b2d261d | 10439 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) |
3dde962f | 10440 | { |
1853d5a9 EI |
10441 | ARMCPU *cpu = arm_env_get_cpu(env); |
10442 | CPUState *cs = CPU(cpu); | |
3dde962f | 10443 | /* Read an LPAE long-descriptor translation table. */ |
da909b2c | 10444 | ARMFaultType fault_type = ARMFault_Translation; |
1b4093ea | 10445 | uint32_t level; |
ba97be9f | 10446 | ARMVAParameters param; |
3dde962f | 10447 | uint64_t ttbr; |
dddb5223 | 10448 | hwaddr descaddr, indexmask, indexmask_grainsize; |
3dde962f | 10449 | uint32_t tableattrs; |
36d820af | 10450 | target_ulong page_size; |
3dde962f | 10451 | uint32_t attrs; |
ba97be9f RH |
10452 | int32_t stride; |
10453 | int addrsize, inputsize; | |
0480f69a | 10454 | TCR *tcr = regime_tcr(env, mmu_idx); |
d8e052b3 | 10455 | int ap, ns, xn, pxn; |
88e8add8 | 10456 | uint32_t el = regime_el(env, mmu_idx); |
ba97be9f | 10457 | bool ttbr1_valid; |
6109769a | 10458 | uint64_t descaddrmask; |
6e99f762 | 10459 | bool aarch64 = arm_el_is_aa64(env, el); |
0480f69a PM |
10460 | |
10461 | /* TODO: | |
88e8add8 GB |
10462 | * This code does not handle the different format TCR for VTCR_EL2. |
10463 | * This code also does not support shareability levels. | |
10464 | * Attribute and permission bit handling should also be checked when adding | |
10465 | * support for those page table walks. | |
0480f69a | 10466 | */ |
6e99f762 | 10467 | if (aarch64) { |
ba97be9f RH |
10468 | param = aa64_va_parameters(env, address, mmu_idx, |
10469 | access_type != MMU_INST_FETCH); | |
1b4093ea | 10470 | level = 0; |
88e8add8 GB |
10471 | /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it |
10472 | * invalid. | |
10473 | */ | |
ba97be9f RH |
10474 | ttbr1_valid = (el < 2); |
10475 | addrsize = 64 - 8 * param.tbi; | |
10476 | inputsize = 64 - param.tsz; | |
d0a2cbce | 10477 | } else { |
ba97be9f | 10478 | param = aa32_va_parameters(env, address, mmu_idx); |
1b4093ea | 10479 | level = 1; |
d0a2cbce | 10480 | /* There is no TTBR1 for EL2 */ |
ba97be9f RH |
10481 | ttbr1_valid = (el != 2); |
10482 | addrsize = (mmu_idx == ARMMMUIdx_S2NS ? 40 : 32); | |
10483 | inputsize = addrsize - param.tsz; | |
2c8dd318 | 10484 | } |
3dde962f | 10485 | |
ba97be9f RH |
10486 | /* |
10487 | * We determined the region when collecting the parameters, but we | |
10488 | * have not yet validated that the address is valid for the region. | |
10489 | * Extract the top bits and verify that they all match select. | |
36d820af RH |
10490 | * |
10491 | * For aa32, if inputsize == addrsize, then we have selected the | |
10492 | * region by exclusion in aa32_va_parameters and there is no more | |
10493 | * validation to do here. | |
10494 | */ | |
10495 | if (inputsize < addrsize) { | |
10496 | target_ulong top_bits = sextract64(address, inputsize, | |
10497 | addrsize - inputsize); | |
10498 | if (-top_bits != param.select || (param.select && !ttbr1_valid)) { | |
10499 | /* The gap between the two regions is a Translation fault */ | |
10500 | fault_type = ARMFault_Translation; | |
10501 | goto do_fault; | |
10502 | } | |
3dde962f PM |
10503 | } |
10504 | ||
ba97be9f RH |
10505 | if (param.using64k) { |
10506 | stride = 13; | |
10507 | } else if (param.using16k) { | |
10508 | stride = 11; | |
10509 | } else { | |
10510 | stride = 9; | |
10511 | } | |
10512 | ||
3dde962f PM |
10513 | /* Note that QEMU ignores shareability and cacheability attributes, |
10514 | * so we don't need to do anything with the SH, ORGN, IRGN fields | |
10515 | * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the | |
10516 | * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently | |
10517 | * implement any ASID-like capability so we can ignore it (instead | |
10518 | * we will always flush the TLB any time the ASID is changed). | |
10519 | */ | |
ba97be9f | 10520 | ttbr = regime_ttbr(env, mmu_idx, param.select); |
3dde962f | 10521 | |
0480f69a | 10522 | /* Here we should have set up all the parameters for the translation: |
6e99f762 | 10523 | * inputsize, ttbr, epd, stride, tbi |
0480f69a PM |
10524 | */ |
10525 | ||
ba97be9f | 10526 | if (param.epd) { |
88e8add8 GB |
10527 | /* Translation table walk disabled => Translation fault on TLB miss |
10528 | * Note: This is always 0 on 64-bit EL2 and EL3. | |
10529 | */ | |
3dde962f PM |
10530 | goto do_fault; |
10531 | } | |
10532 | ||
1853d5a9 EI |
10533 | if (mmu_idx != ARMMMUIdx_S2NS) { |
10534 | /* The starting level depends on the virtual address size (which can | |
10535 | * be up to 48 bits) and the translation granule size. It indicates | |
10536 | * the number of strides (stride bits at a time) needed to | |
10537 | * consume the bits of the input address. In the pseudocode this is: | |
10538 | * level = 4 - RoundUp((inputsize - grainsize) / stride) | |
10539 | * where their 'inputsize' is our 'inputsize', 'grainsize' is | |
10540 | * our 'stride + 3' and 'stride' is our 'stride'. | |
10541 | * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: | |
10542 | * = 4 - (inputsize - stride - 3 + stride - 1) / stride | |
10543 | * = 4 - (inputsize - 4) / stride; | |
10544 | */ | |
10545 | level = 4 - (inputsize - 4) / stride; | |
10546 | } else { | |
10547 | /* For stage 2 translations the starting level is specified by the | |
10548 | * VTCR_EL2.SL0 field (whose interpretation depends on the page size) | |
10549 | */ | |
1b4093ea SS |
10550 | uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); |
10551 | uint32_t startlevel; | |
1853d5a9 EI |
10552 | bool ok; |
10553 | ||
6e99f762 | 10554 | if (!aarch64 || stride == 9) { |
1853d5a9 | 10555 | /* AArch32 or 4KB pages */ |
1b4093ea | 10556 | startlevel = 2 - sl0; |
1853d5a9 EI |
10557 | } else { |
10558 | /* 16KB or 64KB pages */ | |
1b4093ea | 10559 | startlevel = 3 - sl0; |
1853d5a9 EI |
10560 | } |
10561 | ||
10562 | /* Check that the starting level is valid. */ | |
6e99f762 | 10563 | ok = check_s2_mmu_setup(cpu, aarch64, startlevel, |
1b4093ea | 10564 | inputsize, stride); |
1853d5a9 | 10565 | if (!ok) { |
da909b2c | 10566 | fault_type = ARMFault_Translation; |
1853d5a9 EI |
10567 | goto do_fault; |
10568 | } | |
1b4093ea | 10569 | level = startlevel; |
1853d5a9 | 10570 | } |
3dde962f | 10571 | |
dddb5223 SS |
10572 | indexmask_grainsize = (1ULL << (stride + 3)) - 1; |
10573 | indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; | |
3dde962f PM |
10574 | |
10575 | /* Now we can extract the actual base address from the TTBR */ | |
2c8dd318 | 10576 | descaddr = extract64(ttbr, 0, 48); |
dddb5223 | 10577 | descaddr &= ~indexmask; |
3dde962f | 10578 | |
6109769a | 10579 | /* The address field in the descriptor goes up to bit 39 for ARMv7 |
dddb5223 SS |
10580 | * but up to bit 47 for ARMv8, but we use the descaddrmask |
10581 | * up to bit 39 for AArch32, because we don't need other bits in that case | |
10582 | * to construct next descriptor address (anyway they should be all zeroes). | |
6109769a | 10583 | */ |
6e99f762 | 10584 | descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) & |
dddb5223 | 10585 | ~indexmask_grainsize; |
6109769a | 10586 | |
ebca90e4 PM |
10587 | /* Secure accesses start with the page table in secure memory and |
10588 | * can be downgraded to non-secure at any step. Non-secure accesses | |
10589 | * remain non-secure. We implement this by just ORing in the NSTable/NS | |
10590 | * bits at each step. | |
10591 | */ | |
10592 | tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); | |
3dde962f PM |
10593 | for (;;) { |
10594 | uint64_t descriptor; | |
ebca90e4 | 10595 | bool nstable; |
3dde962f | 10596 | |
dddb5223 | 10597 | descaddr |= (address >> (stride * (4 - level))) & indexmask; |
2c8dd318 | 10598 | descaddr &= ~7ULL; |
ebca90e4 | 10599 | nstable = extract32(tableattrs, 4, 1); |
3795a6de | 10600 | descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi); |
3b39d734 | 10601 | if (fi->type != ARMFault_None) { |
37785977 EI |
10602 | goto do_fault; |
10603 | } | |
10604 | ||
3dde962f PM |
10605 | if (!(descriptor & 1) || |
10606 | (!(descriptor & 2) && (level == 3))) { | |
10607 | /* Invalid, or the Reserved level 3 encoding */ | |
10608 | goto do_fault; | |
10609 | } | |
6109769a | 10610 | descaddr = descriptor & descaddrmask; |
3dde962f PM |
10611 | |
10612 | if ((descriptor & 2) && (level < 3)) { | |
037c13c5 | 10613 | /* Table entry. The top five bits are attributes which may |
3dde962f PM |
10614 | * propagate down through lower levels of the table (and |
10615 | * which are all arranged so that 0 means "no effect", so | |
10616 | * we can gather them up by ORing in the bits at each level). | |
10617 | */ | |
10618 | tableattrs |= extract64(descriptor, 59, 5); | |
10619 | level++; | |
dddb5223 | 10620 | indexmask = indexmask_grainsize; |
3dde962f PM |
10621 | continue; |
10622 | } | |
10623 | /* Block entry at level 1 or 2, or page entry at level 3. | |
10624 | * These are basically the same thing, although the number | |
10625 | * of bits we pull in from the vaddr varies. | |
10626 | */ | |
973a5434 | 10627 | page_size = (1ULL << ((stride * (4 - level)) + 3)); |
3dde962f | 10628 | descaddr |= (address & (page_size - 1)); |
6ab1a5ee | 10629 | /* Extract attributes from the descriptor */ |
d615efac IC |
10630 | attrs = extract64(descriptor, 2, 10) |
10631 | | (extract64(descriptor, 52, 12) << 10); | |
6ab1a5ee EI |
10632 | |
10633 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
10634 | /* Stage 2 table descriptors do not include any attribute fields */ | |
10635 | break; | |
10636 | } | |
10637 | /* Merge in attributes from table descriptors */ | |
037c13c5 | 10638 | attrs |= nstable << 3; /* NS */ |
ba97be9f | 10639 | if (param.hpd) { |
037c13c5 RH |
10640 | /* HPD disables all the table attributes except NSTable. */ |
10641 | break; | |
10642 | } | |
10643 | attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ | |
3dde962f PM |
10644 | /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 |
10645 | * means "force PL1 access only", which means forcing AP[1] to 0. | |
10646 | */ | |
037c13c5 RH |
10647 | attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */ |
10648 | attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */ | |
3dde962f PM |
10649 | break; |
10650 | } | |
10651 | /* Here descaddr is the final physical address, and attributes | |
10652 | * are all in attrs. | |
10653 | */ | |
da909b2c | 10654 | fault_type = ARMFault_AccessFlag; |
3dde962f PM |
10655 | if ((attrs & (1 << 8)) == 0) { |
10656 | /* Access flag */ | |
10657 | goto do_fault; | |
10658 | } | |
d8e052b3 AJ |
10659 | |
10660 | ap = extract32(attrs, 4, 2); | |
d8e052b3 | 10661 | xn = extract32(attrs, 12, 1); |
d8e052b3 | 10662 | |
6ab1a5ee EI |
10663 | if (mmu_idx == ARMMMUIdx_S2NS) { |
10664 | ns = true; | |
10665 | *prot = get_S2prot(env, ap, xn); | |
10666 | } else { | |
10667 | ns = extract32(attrs, 3, 1); | |
10668 | pxn = extract32(attrs, 11, 1); | |
6e99f762 | 10669 | *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); |
6ab1a5ee | 10670 | } |
d8e052b3 | 10671 | |
da909b2c | 10672 | fault_type = ARMFault_Permission; |
d8e052b3 | 10673 | if (!(*prot & (1 << access_type))) { |
3dde962f PM |
10674 | goto do_fault; |
10675 | } | |
3dde962f | 10676 | |
8bf5b6a9 PM |
10677 | if (ns) { |
10678 | /* The NS bit will (as required by the architecture) have no effect if | |
10679 | * the CPU doesn't support TZ or this is a non-secure translation | |
10680 | * regime, because the attribute will already be non-secure. | |
10681 | */ | |
10682 | txattrs->secure = false; | |
10683 | } | |
5b2d261d AB |
10684 | |
10685 | if (cacheattrs != NULL) { | |
10686 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
10687 | cacheattrs->attrs = convert_stage2_attrs(env, | |
10688 | extract32(attrs, 0, 4)); | |
10689 | } else { | |
10690 | /* Index into MAIR registers for cache attributes */ | |
10691 | uint8_t attrindx = extract32(attrs, 0, 3); | |
10692 | uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; | |
10693 | assert(attrindx <= 7); | |
10694 | cacheattrs->attrs = extract64(mair, attrindx * 8, 8); | |
10695 | } | |
10696 | cacheattrs->shareability = extract32(attrs, 6, 2); | |
10697 | } | |
10698 | ||
3dde962f PM |
10699 | *phys_ptr = descaddr; |
10700 | *page_size_ptr = page_size; | |
b7cc4e82 | 10701 | return false; |
3dde962f PM |
10702 | |
10703 | do_fault: | |
da909b2c PM |
10704 | fi->type = fault_type; |
10705 | fi->level = level; | |
37785977 EI |
10706 | /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ |
10707 | fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS); | |
b7cc4e82 | 10708 | return true; |
3dde962f PM |
10709 | } |
10710 | ||
f6bda88f PC |
10711 | static inline void get_phys_addr_pmsav7_default(CPUARMState *env, |
10712 | ARMMMUIdx mmu_idx, | |
10713 | int32_t address, int *prot) | |
10714 | { | |
3a00d560 MD |
10715 | if (!arm_feature(env, ARM_FEATURE_M)) { |
10716 | *prot = PAGE_READ | PAGE_WRITE; | |
10717 | switch (address) { | |
10718 | case 0xF0000000 ... 0xFFFFFFFF: | |
10719 | if (regime_sctlr(env, mmu_idx) & SCTLR_V) { | |
10720 | /* hivecs execing is ok */ | |
10721 | *prot |= PAGE_EXEC; | |
10722 | } | |
10723 | break; | |
10724 | case 0x00000000 ... 0x7FFFFFFF: | |
f6bda88f | 10725 | *prot |= PAGE_EXEC; |
3a00d560 MD |
10726 | break; |
10727 | } | |
10728 | } else { | |
10729 | /* Default system address map for M profile cores. | |
10730 | * The architecture specifies which regions are execute-never; | |
10731 | * at the MPU level no other checks are defined. | |
10732 | */ | |
10733 | switch (address) { | |
10734 | case 0x00000000 ... 0x1fffffff: /* ROM */ | |
10735 | case 0x20000000 ... 0x3fffffff: /* SRAM */ | |
10736 | case 0x60000000 ... 0x7fffffff: /* RAM */ | |
10737 | case 0x80000000 ... 0x9fffffff: /* RAM */ | |
10738 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
10739 | break; | |
10740 | case 0x40000000 ... 0x5fffffff: /* Peripheral */ | |
10741 | case 0xa0000000 ... 0xbfffffff: /* Device */ | |
10742 | case 0xc0000000 ... 0xdfffffff: /* Device */ | |
10743 | case 0xe0000000 ... 0xffffffff: /* System */ | |
10744 | *prot = PAGE_READ | PAGE_WRITE; | |
10745 | break; | |
10746 | default: | |
10747 | g_assert_not_reached(); | |
f6bda88f | 10748 | } |
f6bda88f | 10749 | } |
f6bda88f PC |
10750 | } |
10751 | ||
29c483a5 MD |
10752 | static bool pmsav7_use_background_region(ARMCPU *cpu, |
10753 | ARMMMUIdx mmu_idx, bool is_user) | |
10754 | { | |
10755 | /* Return true if we should use the default memory map as a | |
10756 | * "background" region if there are no hits against any MPU regions. | |
10757 | */ | |
10758 | CPUARMState *env = &cpu->env; | |
10759 | ||
10760 | if (is_user) { | |
10761 | return false; | |
10762 | } | |
10763 | ||
10764 | if (arm_feature(env, ARM_FEATURE_M)) { | |
ecf5e8ea PM |
10765 | return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] |
10766 | & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; | |
29c483a5 MD |
10767 | } else { |
10768 | return regime_sctlr(env, mmu_idx) & SCTLR_BR; | |
10769 | } | |
10770 | } | |
10771 | ||
38aaa60c PM |
10772 | static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address) |
10773 | { | |
10774 | /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */ | |
10775 | return arm_feature(env, ARM_FEATURE_M) && | |
10776 | extract32(address, 20, 12) == 0xe00; | |
10777 | } | |
10778 | ||
bf446a11 PM |
10779 | static inline bool m_is_system_region(CPUARMState *env, uint32_t address) |
10780 | { | |
10781 | /* True if address is in the M profile system region | |
10782 | * 0xe0000000 - 0xffffffff | |
10783 | */ | |
10784 | return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7; | |
10785 | } | |
10786 | ||
f6bda88f | 10787 | static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, |
03ae85f8 | 10788 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
9375ad15 | 10789 | hwaddr *phys_ptr, int *prot, |
e5e40999 | 10790 | target_ulong *page_size, |
9375ad15 | 10791 | ARMMMUFaultInfo *fi) |
f6bda88f PC |
10792 | { |
10793 | ARMCPU *cpu = arm_env_get_cpu(env); | |
10794 | int n; | |
10795 | bool is_user = regime_is_user(env, mmu_idx); | |
10796 | ||
10797 | *phys_ptr = address; | |
e5e40999 | 10798 | *page_size = TARGET_PAGE_SIZE; |
f6bda88f PC |
10799 | *prot = 0; |
10800 | ||
38aaa60c PM |
10801 | if (regime_translation_disabled(env, mmu_idx) || |
10802 | m_is_ppb_region(env, address)) { | |
10803 | /* MPU disabled or M profile PPB access: use default memory map. | |
10804 | * The other case which uses the default memory map in the | |
10805 | * v7M ARM ARM pseudocode is exception vector reads from the vector | |
10806 | * table. In QEMU those accesses are done in arm_v7m_load_vector(), | |
10807 | * which always does a direct read using address_space_ldl(), rather | |
10808 | * than going via this function, so we don't need to check that here. | |
10809 | */ | |
f6bda88f PC |
10810 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); |
10811 | } else { /* MPU enabled */ | |
10812 | for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { | |
10813 | /* region search */ | |
10814 | uint32_t base = env->pmsav7.drbar[n]; | |
10815 | uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5); | |
10816 | uint32_t rmask; | |
10817 | bool srdis = false; | |
10818 | ||
10819 | if (!(env->pmsav7.drsr[n] & 0x1)) { | |
10820 | continue; | |
10821 | } | |
10822 | ||
10823 | if (!rsize) { | |
c9f9f124 MD |
10824 | qemu_log_mask(LOG_GUEST_ERROR, |
10825 | "DRSR[%d]: Rsize field cannot be 0\n", n); | |
f6bda88f PC |
10826 | continue; |
10827 | } | |
10828 | rsize++; | |
10829 | rmask = (1ull << rsize) - 1; | |
10830 | ||
10831 | if (base & rmask) { | |
c9f9f124 MD |
10832 | qemu_log_mask(LOG_GUEST_ERROR, |
10833 | "DRBAR[%d]: 0x%" PRIx32 " misaligned " | |
10834 | "to DRSR region size, mask = 0x%" PRIx32 "\n", | |
10835 | n, base, rmask); | |
f6bda88f PC |
10836 | continue; |
10837 | } | |
10838 | ||
10839 | if (address < base || address > base + rmask) { | |
9d2b5a58 PM |
10840 | /* |
10841 | * Address not in this region. We must check whether the | |
10842 | * region covers addresses in the same page as our address. | |
10843 | * In that case we must not report a size that covers the | |
10844 | * whole page for a subsequent hit against a different MPU | |
10845 | * region or the background region, because it would result in | |
10846 | * incorrect TLB hits for subsequent accesses to addresses that | |
10847 | * are in this MPU region. | |
10848 | */ | |
10849 | if (ranges_overlap(base, rmask, | |
10850 | address & TARGET_PAGE_MASK, | |
10851 | TARGET_PAGE_SIZE)) { | |
10852 | *page_size = 1; | |
10853 | } | |
f6bda88f PC |
10854 | continue; |
10855 | } | |
10856 | ||
10857 | /* Region matched */ | |
10858 | ||
10859 | if (rsize >= 8) { /* no subregions for regions < 256 bytes */ | |
10860 | int i, snd; | |
10861 | uint32_t srdis_mask; | |
10862 | ||
10863 | rsize -= 3; /* sub region size (power of 2) */ | |
10864 | snd = ((address - base) >> rsize) & 0x7; | |
10865 | srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1); | |
10866 | ||
10867 | srdis_mask = srdis ? 0x3 : 0x0; | |
10868 | for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) { | |
10869 | /* This will check in groups of 2, 4 and then 8, whether | |
10870 | * the subregion bits are consistent. rsize is incremented | |
10871 | * back up to give the region size, considering consistent | |
10872 | * adjacent subregions as one region. Stop testing if rsize | |
10873 | * is already big enough for an entire QEMU page. | |
10874 | */ | |
10875 | int snd_rounded = snd & ~(i - 1); | |
10876 | uint32_t srdis_multi = extract32(env->pmsav7.drsr[n], | |
10877 | snd_rounded + 8, i); | |
10878 | if (srdis_mask ^ srdis_multi) { | |
10879 | break; | |
10880 | } | |
10881 | srdis_mask = (srdis_mask << i) | srdis_mask; | |
10882 | rsize++; | |
10883 | } | |
10884 | } | |
f6bda88f PC |
10885 | if (srdis) { |
10886 | continue; | |
10887 | } | |
e5e40999 PM |
10888 | if (rsize < TARGET_PAGE_BITS) { |
10889 | *page_size = 1 << rsize; | |
10890 | } | |
f6bda88f PC |
10891 | break; |
10892 | } | |
10893 | ||
10894 | if (n == -1) { /* no hits */ | |
29c483a5 | 10895 | if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { |
f6bda88f | 10896 | /* background fault */ |
9375ad15 | 10897 | fi->type = ARMFault_Background; |
f6bda88f PC |
10898 | return true; |
10899 | } | |
10900 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | |
10901 | } else { /* a MPU hit! */ | |
10902 | uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); | |
bf446a11 PM |
10903 | uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1); |
10904 | ||
10905 | if (m_is_system_region(env, address)) { | |
10906 | /* System space is always execute never */ | |
10907 | xn = 1; | |
10908 | } | |
f6bda88f PC |
10909 | |
10910 | if (is_user) { /* User mode AP bit decoding */ | |
10911 | switch (ap) { | |
10912 | case 0: | |
10913 | case 1: | |
10914 | case 5: | |
10915 | break; /* no access */ | |
10916 | case 3: | |
10917 | *prot |= PAGE_WRITE; | |
10918 | /* fall through */ | |
10919 | case 2: | |
10920 | case 6: | |
10921 | *prot |= PAGE_READ | PAGE_EXEC; | |
10922 | break; | |
8638f1ad PM |
10923 | case 7: |
10924 | /* for v7M, same as 6; for R profile a reserved value */ | |
10925 | if (arm_feature(env, ARM_FEATURE_M)) { | |
10926 | *prot |= PAGE_READ | PAGE_EXEC; | |
10927 | break; | |
10928 | } | |
10929 | /* fall through */ | |
f6bda88f PC |
10930 | default: |
10931 | qemu_log_mask(LOG_GUEST_ERROR, | |
c9f9f124 MD |
10932 | "DRACR[%d]: Bad value for AP bits: 0x%" |
10933 | PRIx32 "\n", n, ap); | |
f6bda88f PC |
10934 | } |
10935 | } else { /* Priv. mode AP bits decoding */ | |
10936 | switch (ap) { | |
10937 | case 0: | |
10938 | break; /* no access */ | |
10939 | case 1: | |
10940 | case 2: | |
10941 | case 3: | |
10942 | *prot |= PAGE_WRITE; | |
10943 | /* fall through */ | |
10944 | case 5: | |
10945 | case 6: | |
10946 | *prot |= PAGE_READ | PAGE_EXEC; | |
10947 | break; | |
8638f1ad PM |
10948 | case 7: |
10949 | /* for v7M, same as 6; for R profile a reserved value */ | |
10950 | if (arm_feature(env, ARM_FEATURE_M)) { | |
10951 | *prot |= PAGE_READ | PAGE_EXEC; | |
10952 | break; | |
10953 | } | |
10954 | /* fall through */ | |
f6bda88f PC |
10955 | default: |
10956 | qemu_log_mask(LOG_GUEST_ERROR, | |
c9f9f124 MD |
10957 | "DRACR[%d]: Bad value for AP bits: 0x%" |
10958 | PRIx32 "\n", n, ap); | |
f6bda88f PC |
10959 | } |
10960 | } | |
10961 | ||
10962 | /* execute never */ | |
bf446a11 | 10963 | if (xn) { |
f6bda88f PC |
10964 | *prot &= ~PAGE_EXEC; |
10965 | } | |
10966 | } | |
10967 | } | |
10968 | ||
9375ad15 PM |
10969 | fi->type = ARMFault_Permission; |
10970 | fi->level = 1; | |
f6bda88f PC |
10971 | return !(*prot & (1 << access_type)); |
10972 | } | |
10973 | ||
35337cc3 PM |
10974 | static bool v8m_is_sau_exempt(CPUARMState *env, |
10975 | uint32_t address, MMUAccessType access_type) | |
10976 | { | |
10977 | /* The architecture specifies that certain address ranges are | |
10978 | * exempt from v8M SAU/IDAU checks. | |
10979 | */ | |
10980 | return | |
10981 | (access_type == MMU_INST_FETCH && m_is_system_region(env, address)) || | |
10982 | (address >= 0xe0000000 && address <= 0xe0002fff) || | |
10983 | (address >= 0xe000e000 && address <= 0xe000efff) || | |
10984 | (address >= 0xe002e000 && address <= 0xe002efff) || | |
10985 | (address >= 0xe0040000 && address <= 0xe0041fff) || | |
10986 | (address >= 0xe00ff000 && address <= 0xe00fffff); | |
10987 | } | |
10988 | ||
10989 | static void v8m_security_lookup(CPUARMState *env, uint32_t address, | |
10990 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
10991 | V8M_SAttributes *sattrs) | |
10992 | { | |
10993 | /* Look up the security attributes for this address. Compare the | |
10994 | * pseudocode SecurityCheck() function. | |
10995 | * We assume the caller has zero-initialized *sattrs. | |
10996 | */ | |
10997 | ARMCPU *cpu = arm_env_get_cpu(env); | |
10998 | int r; | |
181962fd PM |
10999 | bool idau_exempt = false, idau_ns = true, idau_nsc = true; |
11000 | int idau_region = IREGION_NOTVALID; | |
72042435 PM |
11001 | uint32_t addr_page_base = address & TARGET_PAGE_MASK; |
11002 | uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); | |
35337cc3 | 11003 | |
181962fd PM |
11004 | if (cpu->idau) { |
11005 | IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau); | |
11006 | IDAUInterface *ii = IDAU_INTERFACE(cpu->idau); | |
11007 | ||
11008 | iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns, | |
11009 | &idau_nsc); | |
11010 | } | |
35337cc3 PM |
11011 | |
11012 | if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) { | |
11013 | /* 0xf0000000..0xffffffff is always S for insn fetches */ | |
11014 | return; | |
11015 | } | |
11016 | ||
181962fd | 11017 | if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) { |
35337cc3 PM |
11018 | sattrs->ns = !regime_is_secure(env, mmu_idx); |
11019 | return; | |
11020 | } | |
11021 | ||
181962fd PM |
11022 | if (idau_region != IREGION_NOTVALID) { |
11023 | sattrs->irvalid = true; | |
11024 | sattrs->iregion = idau_region; | |
11025 | } | |
11026 | ||
35337cc3 PM |
11027 | switch (env->sau.ctrl & 3) { |
11028 | case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */ | |
11029 | break; | |
11030 | case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */ | |
11031 | sattrs->ns = true; | |
11032 | break; | |
11033 | default: /* SAU.ENABLE == 1 */ | |
11034 | for (r = 0; r < cpu->sau_sregion; r++) { | |
11035 | if (env->sau.rlar[r] & 1) { | |
11036 | uint32_t base = env->sau.rbar[r] & ~0x1f; | |
11037 | uint32_t limit = env->sau.rlar[r] | 0x1f; | |
11038 | ||
11039 | if (base <= address && limit >= address) { | |
72042435 PM |
11040 | if (base > addr_page_base || limit < addr_page_limit) { |
11041 | sattrs->subpage = true; | |
11042 | } | |
35337cc3 PM |
11043 | if (sattrs->srvalid) { |
11044 | /* If we hit in more than one region then we must report | |
11045 | * as Secure, not NS-Callable, with no valid region | |
11046 | * number info. | |
11047 | */ | |
11048 | sattrs->ns = false; | |
11049 | sattrs->nsc = false; | |
11050 | sattrs->sregion = 0; | |
11051 | sattrs->srvalid = false; | |
11052 | break; | |
11053 | } else { | |
11054 | if (env->sau.rlar[r] & 2) { | |
11055 | sattrs->nsc = true; | |
11056 | } else { | |
11057 | sattrs->ns = true; | |
11058 | } | |
11059 | sattrs->srvalid = true; | |
11060 | sattrs->sregion = r; | |
11061 | } | |
9d2b5a58 PM |
11062 | } else { |
11063 | /* | |
11064 | * Address not in this region. We must check whether the | |
11065 | * region covers addresses in the same page as our address. | |
11066 | * In that case we must not report a size that covers the | |
11067 | * whole page for a subsequent hit against a different MPU | |
11068 | * region or the background region, because it would result | |
11069 | * in incorrect TLB hits for subsequent accesses to | |
11070 | * addresses that are in this MPU region. | |
11071 | */ | |
11072 | if (limit >= base && | |
11073 | ranges_overlap(base, limit - base + 1, | |
11074 | addr_page_base, | |
11075 | TARGET_PAGE_SIZE)) { | |
11076 | sattrs->subpage = true; | |
11077 | } | |
35337cc3 PM |
11078 | } |
11079 | } | |
11080 | } | |
7e3f1223 TR |
11081 | break; |
11082 | } | |
35337cc3 | 11083 | |
7e3f1223 TR |
11084 | /* |
11085 | * The IDAU will override the SAU lookup results if it specifies | |
11086 | * higher security than the SAU does. | |
11087 | */ | |
11088 | if (!idau_ns) { | |
11089 | if (sattrs->ns || (!idau_nsc && sattrs->nsc)) { | |
11090 | sattrs->ns = false; | |
11091 | sattrs->nsc = idau_nsc; | |
181962fd | 11092 | } |
35337cc3 PM |
11093 | } |
11094 | } | |
11095 | ||
54317c0f PM |
11096 | static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, |
11097 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
11098 | hwaddr *phys_ptr, MemTxAttrs *txattrs, | |
72042435 PM |
11099 | int *prot, bool *is_subpage, |
11100 | ARMMMUFaultInfo *fi, uint32_t *mregion) | |
54317c0f PM |
11101 | { |
11102 | /* Perform a PMSAv8 MPU lookup (without also doing the SAU check | |
11103 | * that a full phys-to-virt translation does). | |
11104 | * mregion is (if not NULL) set to the region number which matched, | |
11105 | * or -1 if no region number is returned (MPU off, address did not | |
11106 | * hit a region, address hit in multiple regions). | |
72042435 PM |
11107 | * We set is_subpage to true if the region hit doesn't cover the |
11108 | * entire TARGET_PAGE the address is within. | |
54317c0f | 11109 | */ |
504e3cc3 PM |
11110 | ARMCPU *cpu = arm_env_get_cpu(env); |
11111 | bool is_user = regime_is_user(env, mmu_idx); | |
62c58ee0 | 11112 | uint32_t secure = regime_is_secure(env, mmu_idx); |
504e3cc3 PM |
11113 | int n; |
11114 | int matchregion = -1; | |
11115 | bool hit = false; | |
72042435 PM |
11116 | uint32_t addr_page_base = address & TARGET_PAGE_MASK; |
11117 | uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); | |
504e3cc3 | 11118 | |
72042435 | 11119 | *is_subpage = false; |
504e3cc3 PM |
11120 | *phys_ptr = address; |
11121 | *prot = 0; | |
54317c0f PM |
11122 | if (mregion) { |
11123 | *mregion = -1; | |
35337cc3 PM |
11124 | } |
11125 | ||
504e3cc3 PM |
11126 | /* Unlike the ARM ARM pseudocode, we don't need to check whether this |
11127 | * was an exception vector read from the vector table (which is always | |
11128 | * done using the default system address map), because those accesses | |
11129 | * are done in arm_v7m_load_vector(), which always does a direct | |
11130 | * read using address_space_ldl(), rather than going via this function. | |
11131 | */ | |
11132 | if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ | |
11133 | hit = true; | |
11134 | } else if (m_is_ppb_region(env, address)) { | |
11135 | hit = true; | |
11136 | } else if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) { | |
11137 | hit = true; | |
11138 | } else { | |
11139 | for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { | |
11140 | /* region search */ | |
11141 | /* Note that the base address is bits [31:5] from the register | |
11142 | * with bits [4:0] all zeroes, but the limit address is bits | |
11143 | * [31:5] from the register with bits [4:0] all ones. | |
11144 | */ | |
62c58ee0 PM |
11145 | uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f; |
11146 | uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f; | |
504e3cc3 | 11147 | |
62c58ee0 | 11148 | if (!(env->pmsav8.rlar[secure][n] & 0x1)) { |
504e3cc3 PM |
11149 | /* Region disabled */ |
11150 | continue; | |
11151 | } | |
11152 | ||
11153 | if (address < base || address > limit) { | |
9d2b5a58 PM |
11154 | /* |
11155 | * Address not in this region. We must check whether the | |
11156 | * region covers addresses in the same page as our address. | |
11157 | * In that case we must not report a size that covers the | |
11158 | * whole page for a subsequent hit against a different MPU | |
11159 | * region or the background region, because it would result in | |
11160 | * incorrect TLB hits for subsequent accesses to addresses that | |
11161 | * are in this MPU region. | |
11162 | */ | |
11163 | if (limit >= base && | |
11164 | ranges_overlap(base, limit - base + 1, | |
11165 | addr_page_base, | |
11166 | TARGET_PAGE_SIZE)) { | |
11167 | *is_subpage = true; | |
11168 | } | |
504e3cc3 PM |
11169 | continue; |
11170 | } | |
11171 | ||
72042435 PM |
11172 | if (base > addr_page_base || limit < addr_page_limit) { |
11173 | *is_subpage = true; | |
11174 | } | |
11175 | ||
504e3cc3 PM |
11176 | if (hit) { |
11177 | /* Multiple regions match -- always a failure (unlike | |
11178 | * PMSAv7 where highest-numbered-region wins) | |
11179 | */ | |
3f551b5b PM |
11180 | fi->type = ARMFault_Permission; |
11181 | fi->level = 1; | |
504e3cc3 PM |
11182 | return true; |
11183 | } | |
11184 | ||
11185 | matchregion = n; | |
11186 | hit = true; | |
504e3cc3 PM |
11187 | } |
11188 | } | |
11189 | ||
11190 | if (!hit) { | |
11191 | /* background fault */ | |
3f551b5b | 11192 | fi->type = ARMFault_Background; |
504e3cc3 PM |
11193 | return true; |
11194 | } | |
11195 | ||
11196 | if (matchregion == -1) { | |
11197 | /* hit using the background region */ | |
11198 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | |
11199 | } else { | |
62c58ee0 PM |
11200 | uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2); |
11201 | uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1); | |
504e3cc3 PM |
11202 | |
11203 | if (m_is_system_region(env, address)) { | |
11204 | /* System space is always execute never */ | |
11205 | xn = 1; | |
11206 | } | |
11207 | ||
11208 | *prot = simple_ap_to_rw_prot(env, mmu_idx, ap); | |
11209 | if (*prot && !xn) { | |
11210 | *prot |= PAGE_EXEC; | |
11211 | } | |
11212 | /* We don't need to look the attribute up in the MAIR0/MAIR1 | |
11213 | * registers because that only tells us about cacheability. | |
11214 | */ | |
54317c0f PM |
11215 | if (mregion) { |
11216 | *mregion = matchregion; | |
11217 | } | |
504e3cc3 PM |
11218 | } |
11219 | ||
3f551b5b PM |
11220 | fi->type = ARMFault_Permission; |
11221 | fi->level = 1; | |
504e3cc3 PM |
11222 | return !(*prot & (1 << access_type)); |
11223 | } | |
11224 | ||
54317c0f PM |
11225 | |
11226 | static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, | |
11227 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
11228 | hwaddr *phys_ptr, MemTxAttrs *txattrs, | |
72042435 PM |
11229 | int *prot, target_ulong *page_size, |
11230 | ARMMMUFaultInfo *fi) | |
54317c0f PM |
11231 | { |
11232 | uint32_t secure = regime_is_secure(env, mmu_idx); | |
11233 | V8M_SAttributes sattrs = {}; | |
72042435 PM |
11234 | bool ret; |
11235 | bool mpu_is_subpage; | |
54317c0f PM |
11236 | |
11237 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
11238 | v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs); | |
11239 | if (access_type == MMU_INST_FETCH) { | |
11240 | /* Instruction fetches always use the MMU bank and the | |
11241 | * transaction attribute determined by the fetch address, | |
11242 | * regardless of CPU state. This is painful for QEMU | |
11243 | * to handle, because it would mean we need to encode | |
11244 | * into the mmu_idx not just the (user, negpri) information | |
11245 | * for the current security state but also that for the | |
11246 | * other security state, which would balloon the number | |
11247 | * of mmu_idx values needed alarmingly. | |
11248 | * Fortunately we can avoid this because it's not actually | |
11249 | * possible to arbitrarily execute code from memory with | |
11250 | * the wrong security attribute: it will always generate | |
11251 | * an exception of some kind or another, apart from the | |
11252 | * special case of an NS CPU executing an SG instruction | |
11253 | * in S&NSC memory. So we always just fail the translation | |
11254 | * here and sort things out in the exception handler | |
11255 | * (including possibly emulating an SG instruction). | |
11256 | */ | |
11257 | if (sattrs.ns != !secure) { | |
3f551b5b PM |
11258 | if (sattrs.nsc) { |
11259 | fi->type = ARMFault_QEMU_NSCExec; | |
11260 | } else { | |
11261 | fi->type = ARMFault_QEMU_SFault; | |
11262 | } | |
72042435 | 11263 | *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; |
54317c0f PM |
11264 | *phys_ptr = address; |
11265 | *prot = 0; | |
11266 | return true; | |
11267 | } | |
11268 | } else { | |
11269 | /* For data accesses we always use the MMU bank indicated | |
11270 | * by the current CPU state, but the security attributes | |
11271 | * might downgrade a secure access to nonsecure. | |
11272 | */ | |
11273 | if (sattrs.ns) { | |
11274 | txattrs->secure = false; | |
11275 | } else if (!secure) { | |
11276 | /* NS access to S memory must fault. | |
11277 | * Architecturally we should first check whether the | |
11278 | * MPU information for this address indicates that we | |
11279 | * are doing an unaligned access to Device memory, which | |
11280 | * should generate a UsageFault instead. QEMU does not | |
11281 | * currently check for that kind of unaligned access though. | |
11282 | * If we added it we would need to do so as a special case | |
11283 | * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). | |
11284 | */ | |
3f551b5b | 11285 | fi->type = ARMFault_QEMU_SFault; |
72042435 | 11286 | *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; |
54317c0f PM |
11287 | *phys_ptr = address; |
11288 | *prot = 0; | |
11289 | return true; | |
11290 | } | |
11291 | } | |
11292 | } | |
11293 | ||
72042435 PM |
11294 | ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, |
11295 | txattrs, prot, &mpu_is_subpage, fi, NULL); | |
72042435 PM |
11296 | *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; |
11297 | return ret; | |
54317c0f PM |
11298 | } |
11299 | ||
13689d43 | 11300 | static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, |
03ae85f8 | 11301 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
53a4e5c5 PM |
11302 | hwaddr *phys_ptr, int *prot, |
11303 | ARMMMUFaultInfo *fi) | |
9ee6e8bb PB |
11304 | { |
11305 | int n; | |
11306 | uint32_t mask; | |
11307 | uint32_t base; | |
0480f69a | 11308 | bool is_user = regime_is_user(env, mmu_idx); |
9ee6e8bb | 11309 | |
3279adb9 PM |
11310 | if (regime_translation_disabled(env, mmu_idx)) { |
11311 | /* MPU disabled. */ | |
11312 | *phys_ptr = address; | |
11313 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
11314 | return false; | |
11315 | } | |
11316 | ||
9ee6e8bb PB |
11317 | *phys_ptr = address; |
11318 | for (n = 7; n >= 0; n--) { | |
554b0b09 | 11319 | base = env->cp15.c6_region[n]; |
87c3d486 | 11320 | if ((base & 1) == 0) { |
554b0b09 | 11321 | continue; |
87c3d486 | 11322 | } |
554b0b09 PM |
11323 | mask = 1 << ((base >> 1) & 0x1f); |
11324 | /* Keep this shift separate from the above to avoid an | |
11325 | (undefined) << 32. */ | |
11326 | mask = (mask << 1) - 1; | |
87c3d486 | 11327 | if (((base ^ address) & ~mask) == 0) { |
554b0b09 | 11328 | break; |
87c3d486 | 11329 | } |
9ee6e8bb | 11330 | } |
87c3d486 | 11331 | if (n < 0) { |
53a4e5c5 | 11332 | fi->type = ARMFault_Background; |
b7cc4e82 | 11333 | return true; |
87c3d486 | 11334 | } |
9ee6e8bb | 11335 | |
03ae85f8 | 11336 | if (access_type == MMU_INST_FETCH) { |
7e09797c | 11337 | mask = env->cp15.pmsav5_insn_ap; |
9ee6e8bb | 11338 | } else { |
7e09797c | 11339 | mask = env->cp15.pmsav5_data_ap; |
9ee6e8bb PB |
11340 | } |
11341 | mask = (mask >> (n * 4)) & 0xf; | |
11342 | switch (mask) { | |
11343 | case 0: | |
53a4e5c5 PM |
11344 | fi->type = ARMFault_Permission; |
11345 | fi->level = 1; | |
b7cc4e82 | 11346 | return true; |
9ee6e8bb | 11347 | case 1: |
87c3d486 | 11348 | if (is_user) { |
53a4e5c5 PM |
11349 | fi->type = ARMFault_Permission; |
11350 | fi->level = 1; | |
b7cc4e82 | 11351 | return true; |
87c3d486 | 11352 | } |
554b0b09 PM |
11353 | *prot = PAGE_READ | PAGE_WRITE; |
11354 | break; | |
9ee6e8bb | 11355 | case 2: |
554b0b09 | 11356 | *prot = PAGE_READ; |
87c3d486 | 11357 | if (!is_user) { |
554b0b09 | 11358 | *prot |= PAGE_WRITE; |
87c3d486 | 11359 | } |
554b0b09 | 11360 | break; |
9ee6e8bb | 11361 | case 3: |
554b0b09 PM |
11362 | *prot = PAGE_READ | PAGE_WRITE; |
11363 | break; | |
9ee6e8bb | 11364 | case 5: |
87c3d486 | 11365 | if (is_user) { |
53a4e5c5 PM |
11366 | fi->type = ARMFault_Permission; |
11367 | fi->level = 1; | |
b7cc4e82 | 11368 | return true; |
87c3d486 | 11369 | } |
554b0b09 PM |
11370 | *prot = PAGE_READ; |
11371 | break; | |
9ee6e8bb | 11372 | case 6: |
554b0b09 PM |
11373 | *prot = PAGE_READ; |
11374 | break; | |
9ee6e8bb | 11375 | default: |
554b0b09 | 11376 | /* Bad permission. */ |
53a4e5c5 PM |
11377 | fi->type = ARMFault_Permission; |
11378 | fi->level = 1; | |
b7cc4e82 | 11379 | return true; |
9ee6e8bb | 11380 | } |
3ad493fc | 11381 | *prot |= PAGE_EXEC; |
b7cc4e82 | 11382 | return false; |
9ee6e8bb PB |
11383 | } |
11384 | ||
5b2d261d AB |
11385 | /* Combine either inner or outer cacheability attributes for normal |
11386 | * memory, according to table D4-42 and pseudocode procedure | |
11387 | * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). | |
11388 | * | |
11389 | * NB: only stage 1 includes allocation hints (RW bits), leading to | |
11390 | * some asymmetry. | |
11391 | */ | |
11392 | static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2) | |
11393 | { | |
11394 | if (s1 == 4 || s2 == 4) { | |
11395 | /* non-cacheable has precedence */ | |
11396 | return 4; | |
11397 | } else if (extract32(s1, 2, 2) == 0 || extract32(s1, 2, 2) == 2) { | |
11398 | /* stage 1 write-through takes precedence */ | |
11399 | return s1; | |
11400 | } else if (extract32(s2, 2, 2) == 2) { | |
11401 | /* stage 2 write-through takes precedence, but the allocation hint | |
11402 | * is still taken from stage 1 | |
11403 | */ | |
11404 | return (2 << 2) | extract32(s1, 0, 2); | |
11405 | } else { /* write-back */ | |
11406 | return s1; | |
11407 | } | |
11408 | } | |
11409 | ||
11410 | /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 | |
11411 | * and CombineS1S2Desc() | |
11412 | * | |
11413 | * @s1: Attributes from stage 1 walk | |
11414 | * @s2: Attributes from stage 2 walk | |
11415 | */ | |
11416 | static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) | |
11417 | { | |
11418 | uint8_t s1lo = extract32(s1.attrs, 0, 4), s2lo = extract32(s2.attrs, 0, 4); | |
11419 | uint8_t s1hi = extract32(s1.attrs, 4, 4), s2hi = extract32(s2.attrs, 4, 4); | |
11420 | ARMCacheAttrs ret; | |
11421 | ||
11422 | /* Combine shareability attributes (table D4-43) */ | |
11423 | if (s1.shareability == 2 || s2.shareability == 2) { | |
11424 | /* if either are outer-shareable, the result is outer-shareable */ | |
11425 | ret.shareability = 2; | |
11426 | } else if (s1.shareability == 3 || s2.shareability == 3) { | |
11427 | /* if either are inner-shareable, the result is inner-shareable */ | |
11428 | ret.shareability = 3; | |
11429 | } else { | |
11430 | /* both non-shareable */ | |
11431 | ret.shareability = 0; | |
11432 | } | |
11433 | ||
11434 | /* Combine memory type and cacheability attributes */ | |
11435 | if (s1hi == 0 || s2hi == 0) { | |
11436 | /* Device has precedence over normal */ | |
11437 | if (s1lo == 0 || s2lo == 0) { | |
11438 | /* nGnRnE has precedence over anything */ | |
11439 | ret.attrs = 0; | |
11440 | } else if (s1lo == 4 || s2lo == 4) { | |
11441 | /* non-Reordering has precedence over Reordering */ | |
11442 | ret.attrs = 4; /* nGnRE */ | |
11443 | } else if (s1lo == 8 || s2lo == 8) { | |
11444 | /* non-Gathering has precedence over Gathering */ | |
11445 | ret.attrs = 8; /* nGRE */ | |
11446 | } else { | |
11447 | ret.attrs = 0xc; /* GRE */ | |
11448 | } | |
11449 | ||
11450 | /* Any location for which the resultant memory type is any | |
11451 | * type of Device memory is always treated as Outer Shareable. | |
11452 | */ | |
11453 | ret.shareability = 2; | |
11454 | } else { /* Normal memory */ | |
11455 | /* Outer/inner cacheability combine independently */ | |
11456 | ret.attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4 | |
11457 | | combine_cacheattr_nibble(s1lo, s2lo); | |
11458 | ||
11459 | if (ret.attrs == 0x44) { | |
11460 | /* Any location for which the resultant memory type is Normal | |
11461 | * Inner Non-cacheable, Outer Non-cacheable is always treated | |
11462 | * as Outer Shareable. | |
11463 | */ | |
11464 | ret.shareability = 2; | |
11465 | } | |
11466 | } | |
11467 | ||
11468 | return ret; | |
11469 | } | |
11470 | ||
11471 | ||
702a9357 PM |
11472 | /* get_phys_addr - get the physical address for this virtual address |
11473 | * | |
11474 | * Find the physical address corresponding to the given virtual address, | |
11475 | * by doing a translation table walk on MMU based systems or using the | |
11476 | * MPU state on MPU based systems. | |
11477 | * | |
b7cc4e82 PC |
11478 | * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, |
11479 | * prot and page_size may not be filled in, and the populated fsr value provides | |
702a9357 PM |
11480 | * information on why the translation aborted, in the format of a |
11481 | * DFSR/IFSR fault register, with the following caveats: | |
11482 | * * we honour the short vs long DFSR format differences. | |
11483 | * * the WnR bit is never set (the caller must do this). | |
f6bda88f | 11484 | * * for PSMAv5 based systems we don't bother to return a full FSR format |
702a9357 PM |
11485 | * value. |
11486 | * | |
11487 | * @env: CPUARMState | |
11488 | * @address: virtual address to get physical address for | |
11489 | * @access_type: 0 for read, 1 for write, 2 for execute | |
d3649702 | 11490 | * @mmu_idx: MMU index indicating required translation regime |
702a9357 | 11491 | * @phys_ptr: set to the physical address corresponding to the virtual address |
8bf5b6a9 | 11492 | * @attrs: set to the memory transaction attributes to use |
702a9357 PM |
11493 | * @prot: set to the permissions for the page containing phys_ptr |
11494 | * @page_size: set to the size of the page containing phys_ptr | |
5b2d261d AB |
11495 | * @fi: set to fault info if the translation fails |
11496 | * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes | |
702a9357 | 11497 | */ |
af51f566 | 11498 | static bool get_phys_addr(CPUARMState *env, target_ulong address, |
03ae85f8 | 11499 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
af51f566 | 11500 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, |
bc52bfeb | 11501 | target_ulong *page_size, |
5b2d261d | 11502 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) |
9ee6e8bb | 11503 | { |
0480f69a | 11504 | if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { |
9b539263 EI |
11505 | /* Call ourselves recursively to do the stage 1 and then stage 2 |
11506 | * translations. | |
0480f69a | 11507 | */ |
9b539263 EI |
11508 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
11509 | hwaddr ipa; | |
11510 | int s2_prot; | |
11511 | int ret; | |
5b2d261d | 11512 | ARMCacheAttrs cacheattrs2 = {}; |
9b539263 EI |
11513 | |
11514 | ret = get_phys_addr(env, address, access_type, | |
8bd5c820 | 11515 | stage_1_mmu_idx(mmu_idx), &ipa, attrs, |
bc52bfeb | 11516 | prot, page_size, fi, cacheattrs); |
9b539263 EI |
11517 | |
11518 | /* If S1 fails or S2 is disabled, return early. */ | |
11519 | if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { | |
11520 | *phys_ptr = ipa; | |
11521 | return ret; | |
11522 | } | |
11523 | ||
11524 | /* S1 is done. Now do S2 translation. */ | |
11525 | ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS, | |
11526 | phys_ptr, attrs, &s2_prot, | |
da909b2c | 11527 | page_size, fi, |
5b2d261d | 11528 | cacheattrs != NULL ? &cacheattrs2 : NULL); |
9b539263 EI |
11529 | fi->s2addr = ipa; |
11530 | /* Combine the S1 and S2 perms. */ | |
11531 | *prot &= s2_prot; | |
5b2d261d AB |
11532 | |
11533 | /* Combine the S1 and S2 cache attributes, if needed */ | |
11534 | if (!ret && cacheattrs != NULL) { | |
9d1bab33 PM |
11535 | if (env->cp15.hcr_el2 & HCR_DC) { |
11536 | /* | |
11537 | * HCR.DC forces the first stage attributes to | |
11538 | * Normal Non-Shareable, | |
11539 | * Inner Write-Back Read-Allocate Write-Allocate, | |
11540 | * Outer Write-Back Read-Allocate Write-Allocate. | |
11541 | */ | |
11542 | cacheattrs->attrs = 0xff; | |
11543 | cacheattrs->shareability = 0; | |
11544 | } | |
5b2d261d AB |
11545 | *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2); |
11546 | } | |
11547 | ||
9b539263 EI |
11548 | return ret; |
11549 | } else { | |
11550 | /* | |
11551 | * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. | |
11552 | */ | |
8bd5c820 | 11553 | mmu_idx = stage_1_mmu_idx(mmu_idx); |
9b539263 | 11554 | } |
0480f69a | 11555 | } |
d3649702 | 11556 | |
8bf5b6a9 PM |
11557 | /* The page table entries may downgrade secure to non-secure, but |
11558 | * cannot upgrade an non-secure translation regime's attributes | |
11559 | * to secure. | |
11560 | */ | |
11561 | attrs->secure = regime_is_secure(env, mmu_idx); | |
0995bf8c | 11562 | attrs->user = regime_is_user(env, mmu_idx); |
8bf5b6a9 | 11563 | |
0480f69a PM |
11564 | /* Fast Context Switch Extension. This doesn't exist at all in v8. |
11565 | * In v7 and earlier it affects all stage 1 translations. | |
11566 | */ | |
11567 | if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS | |
11568 | && !arm_feature(env, ARM_FEATURE_V8)) { | |
11569 | if (regime_el(env, mmu_idx) == 3) { | |
11570 | address += env->cp15.fcseidr_s; | |
11571 | } else { | |
11572 | address += env->cp15.fcseidr_ns; | |
11573 | } | |
54bf36ed | 11574 | } |
9ee6e8bb | 11575 | |
3279adb9 | 11576 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
c9f9f124 | 11577 | bool ret; |
f6bda88f | 11578 | *page_size = TARGET_PAGE_SIZE; |
3279adb9 | 11579 | |
504e3cc3 PM |
11580 | if (arm_feature(env, ARM_FEATURE_V8)) { |
11581 | /* PMSAv8 */ | |
11582 | ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, | |
72042435 | 11583 | phys_ptr, attrs, prot, page_size, fi); |
504e3cc3 | 11584 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
3279adb9 PM |
11585 | /* PMSAv7 */ |
11586 | ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, | |
e5e40999 | 11587 | phys_ptr, prot, page_size, fi); |
3279adb9 PM |
11588 | } else { |
11589 | /* Pre-v7 MPU */ | |
11590 | ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, | |
53a4e5c5 | 11591 | phys_ptr, prot, fi); |
3279adb9 PM |
11592 | } |
11593 | qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 | |
c9f9f124 | 11594 | " mmu_idx %u -> %s (prot %c%c%c)\n", |
709e4407 PM |
11595 | access_type == MMU_DATA_LOAD ? "reading" : |
11596 | (access_type == MMU_DATA_STORE ? "writing" : "execute"), | |
c9f9f124 MD |
11597 | (uint32_t)address, mmu_idx, |
11598 | ret ? "Miss" : "Hit", | |
11599 | *prot & PAGE_READ ? 'r' : '-', | |
11600 | *prot & PAGE_WRITE ? 'w' : '-', | |
11601 | *prot & PAGE_EXEC ? 'x' : '-'); | |
11602 | ||
11603 | return ret; | |
f6bda88f PC |
11604 | } |
11605 | ||
3279adb9 PM |
11606 | /* Definitely a real MMU, not an MPU */ |
11607 | ||
0480f69a | 11608 | if (regime_translation_disabled(env, mmu_idx)) { |
3279adb9 | 11609 | /* MMU disabled. */ |
9ee6e8bb | 11610 | *phys_ptr = address; |
3ad493fc | 11611 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
d4c430a8 | 11612 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb | 11613 | return 0; |
0480f69a PM |
11614 | } |
11615 | ||
0480f69a | 11616 | if (regime_using_lpae_format(env, mmu_idx)) { |
bc52bfeb PM |
11617 | return get_phys_addr_lpae(env, address, access_type, mmu_idx, |
11618 | phys_ptr, attrs, prot, page_size, | |
11619 | fi, cacheattrs); | |
0480f69a | 11620 | } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { |
bc52bfeb PM |
11621 | return get_phys_addr_v6(env, address, access_type, mmu_idx, |
11622 | phys_ptr, attrs, prot, page_size, fi); | |
9ee6e8bb | 11623 | } else { |
bc52bfeb | 11624 | return get_phys_addr_v5(env, address, access_type, mmu_idx, |
f989983e | 11625 | phys_ptr, prot, page_size, fi); |
9ee6e8bb PB |
11626 | } |
11627 | } | |
11628 | ||
8c6084bf | 11629 | /* Walk the page table and (if the mapping exists) add the page |
b7cc4e82 PC |
11630 | * to the TLB. Return false on success, or true on failure. Populate |
11631 | * fsr with ARM DFSR/IFSR fault register format value on failure. | |
8c6084bf | 11632 | */ |
b7cc4e82 | 11633 | bool arm_tlb_fill(CPUState *cs, vaddr address, |
bc52bfeb | 11634 | MMUAccessType access_type, int mmu_idx, |
e14b5a23 | 11635 | ARMMMUFaultInfo *fi) |
b5ff1b31 | 11636 | { |
7510454e AF |
11637 | ARMCPU *cpu = ARM_CPU(cs); |
11638 | CPUARMState *env = &cpu->env; | |
a8170e5e | 11639 | hwaddr phys_addr; |
d4c430a8 | 11640 | target_ulong page_size; |
b5ff1b31 | 11641 | int prot; |
d3649702 | 11642 | int ret; |
8bf5b6a9 | 11643 | MemTxAttrs attrs = {}; |
b5ff1b31 | 11644 | |
8bd5c820 PM |
11645 | ret = get_phys_addr(env, address, access_type, |
11646 | core_to_arm_mmu_idx(env, mmu_idx), &phys_addr, | |
bc52bfeb | 11647 | &attrs, &prot, &page_size, fi, NULL); |
b7cc4e82 | 11648 | if (!ret) { |
e5e40999 PM |
11649 | /* |
11650 | * Map a single [sub]page. Regions smaller than our declared | |
11651 | * target page size are handled specially, so for those we | |
11652 | * pass in the exact addresses. | |
11653 | */ | |
11654 | if (page_size >= TARGET_PAGE_SIZE) { | |
11655 | phys_addr &= TARGET_PAGE_MASK; | |
11656 | address &= TARGET_PAGE_MASK; | |
11657 | } | |
8bf5b6a9 PM |
11658 | tlb_set_page_with_attrs(cs, address, phys_addr, attrs, |
11659 | prot, mmu_idx, page_size); | |
d4c430a8 | 11660 | return 0; |
b5ff1b31 FB |
11661 | } |
11662 | ||
8c6084bf | 11663 | return ret; |
b5ff1b31 FB |
11664 | } |
11665 | ||
0faea0c7 PM |
11666 | hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, |
11667 | MemTxAttrs *attrs) | |
b5ff1b31 | 11668 | { |
00b941e5 | 11669 | ARMCPU *cpu = ARM_CPU(cs); |
d3649702 | 11670 | CPUARMState *env = &cpu->env; |
a8170e5e | 11671 | hwaddr phys_addr; |
d4c430a8 | 11672 | target_ulong page_size; |
b5ff1b31 | 11673 | int prot; |
b7cc4e82 | 11674 | bool ret; |
e14b5a23 | 11675 | ARMMMUFaultInfo fi = {}; |
50494a27 | 11676 | ARMMMUIdx mmu_idx = arm_mmu_idx(env); |
b5ff1b31 | 11677 | |
0faea0c7 PM |
11678 | *attrs = (MemTxAttrs) {}; |
11679 | ||
8bd5c820 | 11680 | ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr, |
bc52bfeb | 11681 | attrs, &prot, &page_size, &fi, NULL); |
b5ff1b31 | 11682 | |
b7cc4e82 | 11683 | if (ret) { |
b5ff1b31 | 11684 | return -1; |
00b941e5 | 11685 | } |
b5ff1b31 FB |
11686 | return phys_addr; |
11687 | } | |
11688 | ||
0ecb72a5 | 11689 | uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) |
9ee6e8bb | 11690 | { |
58117c9b MD |
11691 | uint32_t mask; |
11692 | unsigned el = arm_current_el(env); | |
11693 | ||
11694 | /* First handle registers which unprivileged can read */ | |
11695 | ||
11696 | switch (reg) { | |
11697 | case 0 ... 7: /* xPSR sub-fields */ | |
11698 | mask = 0; | |
11699 | if ((reg & 1) && el) { | |
987ab45e | 11700 | mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */ |
58117c9b MD |
11701 | } |
11702 | if (!(reg & 4)) { | |
987ab45e | 11703 | mask |= XPSR_NZCV | XPSR_Q; /* APSR */ |
58117c9b MD |
11704 | } |
11705 | /* EPSR reads as zero */ | |
11706 | return xpsr_read(env) & mask; | |
11707 | break; | |
11708 | case 20: /* CONTROL */ | |
8bfc26ea | 11709 | return env->v7m.control[env->v7m.secure]; |
50f11062 PM |
11710 | case 0x94: /* CONTROL_NS */ |
11711 | /* We have to handle this here because unprivileged Secure code | |
11712 | * can read the NS CONTROL register. | |
11713 | */ | |
11714 | if (!env->v7m.secure) { | |
11715 | return 0; | |
11716 | } | |
11717 | return env->v7m.control[M_REG_NS]; | |
58117c9b MD |
11718 | } |
11719 | ||
11720 | if (el == 0) { | |
11721 | return 0; /* unprivileged reads others as zero */ | |
11722 | } | |
a47dddd7 | 11723 | |
50f11062 PM |
11724 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
11725 | switch (reg) { | |
11726 | case 0x88: /* MSP_NS */ | |
11727 | if (!env->v7m.secure) { | |
11728 | return 0; | |
11729 | } | |
11730 | return env->v7m.other_ss_msp; | |
11731 | case 0x89: /* PSP_NS */ | |
11732 | if (!env->v7m.secure) { | |
11733 | return 0; | |
11734 | } | |
11735 | return env->v7m.other_ss_psp; | |
57bb3156 PM |
11736 | case 0x8a: /* MSPLIM_NS */ |
11737 | if (!env->v7m.secure) { | |
11738 | return 0; | |
11739 | } | |
11740 | return env->v7m.msplim[M_REG_NS]; | |
11741 | case 0x8b: /* PSPLIM_NS */ | |
11742 | if (!env->v7m.secure) { | |
11743 | return 0; | |
11744 | } | |
11745 | return env->v7m.psplim[M_REG_NS]; | |
50f11062 PM |
11746 | case 0x90: /* PRIMASK_NS */ |
11747 | if (!env->v7m.secure) { | |
11748 | return 0; | |
11749 | } | |
11750 | return env->v7m.primask[M_REG_NS]; | |
11751 | case 0x91: /* BASEPRI_NS */ | |
11752 | if (!env->v7m.secure) { | |
11753 | return 0; | |
11754 | } | |
11755 | return env->v7m.basepri[M_REG_NS]; | |
11756 | case 0x93: /* FAULTMASK_NS */ | |
11757 | if (!env->v7m.secure) { | |
11758 | return 0; | |
11759 | } | |
11760 | return env->v7m.faultmask[M_REG_NS]; | |
11761 | case 0x98: /* SP_NS */ | |
11762 | { | |
11763 | /* This gives the non-secure SP selected based on whether we're | |
11764 | * currently in handler mode or not, using the NS CONTROL.SPSEL. | |
11765 | */ | |
11766 | bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK; | |
11767 | ||
11768 | if (!env->v7m.secure) { | |
11769 | return 0; | |
11770 | } | |
11771 | if (!arm_v7m_is_handler_mode(env) && spsel) { | |
11772 | return env->v7m.other_ss_psp; | |
11773 | } else { | |
11774 | return env->v7m.other_ss_msp; | |
11775 | } | |
11776 | } | |
11777 | default: | |
11778 | break; | |
11779 | } | |
11780 | } | |
11781 | ||
9ee6e8bb | 11782 | switch (reg) { |
9ee6e8bb | 11783 | case 8: /* MSP */ |
1169d3aa | 11784 | return v7m_using_psp(env) ? env->v7m.other_sp : env->regs[13]; |
9ee6e8bb | 11785 | case 9: /* PSP */ |
1169d3aa | 11786 | return v7m_using_psp(env) ? env->regs[13] : env->v7m.other_sp; |
57bb3156 PM |
11787 | case 10: /* MSPLIM */ |
11788 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
11789 | goto bad_reg; | |
11790 | } | |
11791 | return env->v7m.msplim[env->v7m.secure]; | |
11792 | case 11: /* PSPLIM */ | |
11793 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
11794 | goto bad_reg; | |
11795 | } | |
11796 | return env->v7m.psplim[env->v7m.secure]; | |
9ee6e8bb | 11797 | case 16: /* PRIMASK */ |
6d804834 | 11798 | return env->v7m.primask[env->v7m.secure]; |
82845826 SH |
11799 | case 17: /* BASEPRI */ |
11800 | case 18: /* BASEPRI_MAX */ | |
acf94941 | 11801 | return env->v7m.basepri[env->v7m.secure]; |
82845826 | 11802 | case 19: /* FAULTMASK */ |
42a6686b | 11803 | return env->v7m.faultmask[env->v7m.secure]; |
9ee6e8bb | 11804 | default: |
57bb3156 | 11805 | bad_reg: |
58117c9b MD |
11806 | qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special" |
11807 | " register %d\n", reg); | |
9ee6e8bb PB |
11808 | return 0; |
11809 | } | |
11810 | } | |
11811 | ||
b28b3377 PM |
11812 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) |
11813 | { | |
11814 | /* We're passed bits [11..0] of the instruction; extract | |
11815 | * SYSm and the mask bits. | |
11816 | * Invalid combinations of SYSm and mask are UNPREDICTABLE; | |
11817 | * we choose to treat them as if the mask bits were valid. | |
11818 | * NB that the pseudocode 'mask' variable is bits [11..10], | |
11819 | * whereas ours is [11..8]. | |
11820 | */ | |
11821 | uint32_t mask = extract32(maskreg, 8, 4); | |
11822 | uint32_t reg = extract32(maskreg, 0, 8); | |
11823 | ||
58117c9b MD |
11824 | if (arm_current_el(env) == 0 && reg > 7) { |
11825 | /* only xPSR sub-fields may be written by unprivileged */ | |
11826 | return; | |
11827 | } | |
a47dddd7 | 11828 | |
50f11062 PM |
11829 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { |
11830 | switch (reg) { | |
11831 | case 0x88: /* MSP_NS */ | |
11832 | if (!env->v7m.secure) { | |
11833 | return; | |
11834 | } | |
11835 | env->v7m.other_ss_msp = val; | |
11836 | return; | |
11837 | case 0x89: /* PSP_NS */ | |
11838 | if (!env->v7m.secure) { | |
11839 | return; | |
11840 | } | |
11841 | env->v7m.other_ss_psp = val; | |
11842 | return; | |
57bb3156 PM |
11843 | case 0x8a: /* MSPLIM_NS */ |
11844 | if (!env->v7m.secure) { | |
11845 | return; | |
11846 | } | |
11847 | env->v7m.msplim[M_REG_NS] = val & ~7; | |
11848 | return; | |
11849 | case 0x8b: /* PSPLIM_NS */ | |
11850 | if (!env->v7m.secure) { | |
11851 | return; | |
11852 | } | |
11853 | env->v7m.psplim[M_REG_NS] = val & ~7; | |
11854 | return; | |
50f11062 PM |
11855 | case 0x90: /* PRIMASK_NS */ |
11856 | if (!env->v7m.secure) { | |
11857 | return; | |
11858 | } | |
11859 | env->v7m.primask[M_REG_NS] = val & 1; | |
11860 | return; | |
11861 | case 0x91: /* BASEPRI_NS */ | |
22ab3460 | 11862 | if (!env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_MAIN)) { |
50f11062 PM |
11863 | return; |
11864 | } | |
11865 | env->v7m.basepri[M_REG_NS] = val & 0xff; | |
11866 | return; | |
11867 | case 0x93: /* FAULTMASK_NS */ | |
22ab3460 | 11868 | if (!env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_MAIN)) { |
50f11062 PM |
11869 | return; |
11870 | } | |
11871 | env->v7m.faultmask[M_REG_NS] = val & 1; | |
11872 | return; | |
6eb3a64e PM |
11873 | case 0x94: /* CONTROL_NS */ |
11874 | if (!env->v7m.secure) { | |
11875 | return; | |
11876 | } | |
11877 | write_v7m_control_spsel_for_secstate(env, | |
11878 | val & R_V7M_CONTROL_SPSEL_MASK, | |
11879 | M_REG_NS); | |
def18344 JS |
11880 | if (arm_feature(env, ARM_FEATURE_M_MAIN)) { |
11881 | env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK; | |
11882 | env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK; | |
11883 | } | |
6eb3a64e | 11884 | return; |
50f11062 PM |
11885 | case 0x98: /* SP_NS */ |
11886 | { | |
11887 | /* This gives the non-secure SP selected based on whether we're | |
11888 | * currently in handler mode or not, using the NS CONTROL.SPSEL. | |
11889 | */ | |
11890 | bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK; | |
167765f0 PM |
11891 | bool is_psp = !arm_v7m_is_handler_mode(env) && spsel; |
11892 | uint32_t limit; | |
50f11062 PM |
11893 | |
11894 | if (!env->v7m.secure) { | |
11895 | return; | |
11896 | } | |
167765f0 PM |
11897 | |
11898 | limit = is_psp ? env->v7m.psplim[false] : env->v7m.msplim[false]; | |
11899 | ||
11900 | if (val < limit) { | |
11901 | CPUState *cs = CPU(arm_env_get_cpu(env)); | |
11902 | ||
11903 | cpu_restore_state(cs, GETPC(), true); | |
11904 | raise_exception(env, EXCP_STKOF, 0, 1); | |
11905 | } | |
11906 | ||
11907 | if (is_psp) { | |
50f11062 PM |
11908 | env->v7m.other_ss_psp = val; |
11909 | } else { | |
11910 | env->v7m.other_ss_msp = val; | |
11911 | } | |
11912 | return; | |
11913 | } | |
11914 | default: | |
11915 | break; | |
11916 | } | |
11917 | } | |
11918 | ||
9ee6e8bb | 11919 | switch (reg) { |
58117c9b MD |
11920 | case 0 ... 7: /* xPSR sub-fields */ |
11921 | /* only APSR is actually writable */ | |
b28b3377 PM |
11922 | if (!(reg & 4)) { |
11923 | uint32_t apsrmask = 0; | |
11924 | ||
11925 | if (mask & 8) { | |
987ab45e | 11926 | apsrmask |= XPSR_NZCV | XPSR_Q; |
b28b3377 PM |
11927 | } |
11928 | if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { | |
987ab45e | 11929 | apsrmask |= XPSR_GE; |
b28b3377 PM |
11930 | } |
11931 | xpsr_write(env, val, apsrmask); | |
58117c9b | 11932 | } |
9ee6e8bb PB |
11933 | break; |
11934 | case 8: /* MSP */ | |
1169d3aa | 11935 | if (v7m_using_psp(env)) { |
9ee6e8bb | 11936 | env->v7m.other_sp = val; |
abc24d86 | 11937 | } else { |
9ee6e8bb | 11938 | env->regs[13] = val; |
abc24d86 | 11939 | } |
9ee6e8bb PB |
11940 | break; |
11941 | case 9: /* PSP */ | |
1169d3aa | 11942 | if (v7m_using_psp(env)) { |
9ee6e8bb | 11943 | env->regs[13] = val; |
abc24d86 | 11944 | } else { |
9ee6e8bb | 11945 | env->v7m.other_sp = val; |
abc24d86 | 11946 | } |
9ee6e8bb | 11947 | break; |
57bb3156 PM |
11948 | case 10: /* MSPLIM */ |
11949 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
11950 | goto bad_reg; | |
11951 | } | |
11952 | env->v7m.msplim[env->v7m.secure] = val & ~7; | |
11953 | break; | |
11954 | case 11: /* PSPLIM */ | |
11955 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
11956 | goto bad_reg; | |
11957 | } | |
11958 | env->v7m.psplim[env->v7m.secure] = val & ~7; | |
11959 | break; | |
9ee6e8bb | 11960 | case 16: /* PRIMASK */ |
6d804834 | 11961 | env->v7m.primask[env->v7m.secure] = val & 1; |
9ee6e8bb | 11962 | break; |
82845826 | 11963 | case 17: /* BASEPRI */ |
22ab3460 JS |
11964 | if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { |
11965 | goto bad_reg; | |
11966 | } | |
acf94941 | 11967 | env->v7m.basepri[env->v7m.secure] = val & 0xff; |
9ee6e8bb | 11968 | break; |
82845826 | 11969 | case 18: /* BASEPRI_MAX */ |
22ab3460 JS |
11970 | if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { |
11971 | goto bad_reg; | |
11972 | } | |
9ee6e8bb | 11973 | val &= 0xff; |
acf94941 PM |
11974 | if (val != 0 && (val < env->v7m.basepri[env->v7m.secure] |
11975 | || env->v7m.basepri[env->v7m.secure] == 0)) { | |
11976 | env->v7m.basepri[env->v7m.secure] = val; | |
11977 | } | |
9ee6e8bb | 11978 | break; |
82845826 | 11979 | case 19: /* FAULTMASK */ |
22ab3460 JS |
11980 | if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { |
11981 | goto bad_reg; | |
11982 | } | |
42a6686b | 11983 | env->v7m.faultmask[env->v7m.secure] = val & 1; |
82845826 | 11984 | break; |
9ee6e8bb | 11985 | case 20: /* CONTROL */ |
792dac30 PM |
11986 | /* Writing to the SPSEL bit only has an effect if we are in |
11987 | * thread mode; other bits can be updated by any privileged code. | |
de2db7ec | 11988 | * write_v7m_control_spsel() deals with updating the SPSEL bit in |
792dac30 | 11989 | * env->v7m.control, so we only need update the others. |
83d7f86d PM |
11990 | * For v7M, we must just ignore explicit writes to SPSEL in handler |
11991 | * mode; for v8M the write is permitted but will have no effect. | |
792dac30 | 11992 | */ |
83d7f86d PM |
11993 | if (arm_feature(env, ARM_FEATURE_V8) || |
11994 | !arm_v7m_is_handler_mode(env)) { | |
de2db7ec | 11995 | write_v7m_control_spsel(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0); |
792dac30 | 11996 | } |
def18344 JS |
11997 | if (arm_feature(env, ARM_FEATURE_M_MAIN)) { |
11998 | env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK; | |
11999 | env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK; | |
12000 | } | |
9ee6e8bb PB |
12001 | break; |
12002 | default: | |
57bb3156 | 12003 | bad_reg: |
58117c9b MD |
12004 | qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special" |
12005 | " register %d\n", reg); | |
9ee6e8bb PB |
12006 | return; |
12007 | } | |
12008 | } | |
12009 | ||
5158de24 PM |
12010 | uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) |
12011 | { | |
12012 | /* Implement the TT instruction. op is bits [7:6] of the insn. */ | |
12013 | bool forceunpriv = op & 1; | |
12014 | bool alt = op & 2; | |
12015 | V8M_SAttributes sattrs = {}; | |
12016 | uint32_t tt_resp; | |
12017 | bool r, rw, nsr, nsrw, mrvalid; | |
12018 | int prot; | |
3f551b5b | 12019 | ARMMMUFaultInfo fi = {}; |
5158de24 PM |
12020 | MemTxAttrs attrs = {}; |
12021 | hwaddr phys_addr; | |
5158de24 PM |
12022 | ARMMMUIdx mmu_idx; |
12023 | uint32_t mregion; | |
12024 | bool targetpriv; | |
12025 | bool targetsec = env->v7m.secure; | |
72042435 | 12026 | bool is_subpage; |
5158de24 PM |
12027 | |
12028 | /* Work out what the security state and privilege level we're | |
12029 | * interested in is... | |
12030 | */ | |
12031 | if (alt) { | |
12032 | targetsec = !targetsec; | |
12033 | } | |
12034 | ||
12035 | if (forceunpriv) { | |
12036 | targetpriv = false; | |
12037 | } else { | |
12038 | targetpriv = arm_v7m_is_handler_mode(env) || | |
12039 | !(env->v7m.control[targetsec] & R_V7M_CONTROL_NPRIV_MASK); | |
12040 | } | |
12041 | ||
12042 | /* ...and then figure out which MMU index this is */ | |
12043 | mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, targetsec, targetpriv); | |
12044 | ||
12045 | /* We know that the MPU and SAU don't care about the access type | |
12046 | * for our purposes beyond that we don't want to claim to be | |
12047 | * an insn fetch, so we arbitrarily call this a read. | |
12048 | */ | |
12049 | ||
12050 | /* MPU region info only available for privileged or if | |
12051 | * inspecting the other MPU state. | |
12052 | */ | |
12053 | if (arm_current_el(env) != 0 || alt) { | |
12054 | /* We can ignore the return value as prot is always set */ | |
12055 | pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, | |
72042435 PM |
12056 | &phys_addr, &attrs, &prot, &is_subpage, |
12057 | &fi, &mregion); | |
5158de24 PM |
12058 | if (mregion == -1) { |
12059 | mrvalid = false; | |
12060 | mregion = 0; | |
12061 | } else { | |
12062 | mrvalid = true; | |
12063 | } | |
12064 | r = prot & PAGE_READ; | |
12065 | rw = prot & PAGE_WRITE; | |
12066 | } else { | |
12067 | r = false; | |
12068 | rw = false; | |
12069 | mrvalid = false; | |
12070 | mregion = 0; | |
12071 | } | |
12072 | ||
12073 | if (env->v7m.secure) { | |
12074 | v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs); | |
12075 | nsr = sattrs.ns && r; | |
12076 | nsrw = sattrs.ns && rw; | |
12077 | } else { | |
12078 | sattrs.ns = true; | |
12079 | nsr = false; | |
12080 | nsrw = false; | |
12081 | } | |
12082 | ||
12083 | tt_resp = (sattrs.iregion << 24) | | |
12084 | (sattrs.irvalid << 23) | | |
12085 | ((!sattrs.ns) << 22) | | |
12086 | (nsrw << 21) | | |
12087 | (nsr << 20) | | |
12088 | (rw << 19) | | |
12089 | (r << 18) | | |
12090 | (sattrs.srvalid << 17) | | |
12091 | (mrvalid << 16) | | |
12092 | (sattrs.sregion << 8) | | |
12093 | mregion; | |
12094 | ||
12095 | return tt_resp; | |
12096 | } | |
12097 | ||
b5ff1b31 | 12098 | #endif |
6ddbc6e4 | 12099 | |
aca3f40b PM |
12100 | void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) |
12101 | { | |
12102 | /* Implement DC ZVA, which zeroes a fixed-length block of memory. | |
12103 | * Note that we do not implement the (architecturally mandated) | |
12104 | * alignment fault for attempts to use this on Device memory | |
12105 | * (which matches the usual QEMU behaviour of not implementing either | |
12106 | * alignment faults or any memory attribute handling). | |
12107 | */ | |
12108 | ||
12109 | ARMCPU *cpu = arm_env_get_cpu(env); | |
12110 | uint64_t blocklen = 4 << cpu->dcz_blocksize; | |
12111 | uint64_t vaddr = vaddr_in & ~(blocklen - 1); | |
12112 | ||
12113 | #ifndef CONFIG_USER_ONLY | |
12114 | { | |
12115 | /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than | |
12116 | * the block size so we might have to do more than one TLB lookup. | |
12117 | * We know that in fact for any v8 CPU the page size is at least 4K | |
12118 | * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only | |
12119 | * 1K as an artefact of legacy v5 subpage support being present in the | |
12120 | * same QEMU executable. | |
12121 | */ | |
12122 | int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE); | |
12123 | void *hostaddr[maxidx]; | |
12124 | int try, i; | |
97ed5ccd | 12125 | unsigned mmu_idx = cpu_mmu_index(env, false); |
3972ef6f | 12126 | TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); |
aca3f40b PM |
12127 | |
12128 | for (try = 0; try < 2; try++) { | |
12129 | ||
12130 | for (i = 0; i < maxidx; i++) { | |
12131 | hostaddr[i] = tlb_vaddr_to_host(env, | |
12132 | vaddr + TARGET_PAGE_SIZE * i, | |
3972ef6f | 12133 | 1, mmu_idx); |
aca3f40b PM |
12134 | if (!hostaddr[i]) { |
12135 | break; | |
12136 | } | |
12137 | } | |
12138 | if (i == maxidx) { | |
12139 | /* If it's all in the TLB it's fair game for just writing to; | |
12140 | * we know we don't need to update dirty status, etc. | |
12141 | */ | |
12142 | for (i = 0; i < maxidx - 1; i++) { | |
12143 | memset(hostaddr[i], 0, TARGET_PAGE_SIZE); | |
12144 | } | |
12145 | memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE)); | |
12146 | return; | |
12147 | } | |
12148 | /* OK, try a store and see if we can populate the tlb. This | |
12149 | * might cause an exception if the memory isn't writable, | |
12150 | * in which case we will longjmp out of here. We must for | |
12151 | * this purpose use the actual register value passed to us | |
12152 | * so that we get the fault address right. | |
12153 | */ | |
01ecaf43 | 12154 | helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETPC()); |
aca3f40b PM |
12155 | /* Now we can populate the other TLB entries, if any */ |
12156 | for (i = 0; i < maxidx; i++) { | |
12157 | uint64_t va = vaddr + TARGET_PAGE_SIZE * i; | |
12158 | if (va != (vaddr_in & TARGET_PAGE_MASK)) { | |
01ecaf43 | 12159 | helper_ret_stb_mmu(env, va, 0, oi, GETPC()); |
aca3f40b PM |
12160 | } |
12161 | } | |
12162 | } | |
12163 | ||
12164 | /* Slow path (probably attempt to do this to an I/O device or | |
12165 | * similar, or clearing of a block of code we have translations | |
12166 | * cached for). Just do a series of byte writes as the architecture | |
12167 | * demands. It's not worth trying to use a cpu_physical_memory_map(), | |
12168 | * memset(), unmap() sequence here because: | |
12169 | * + we'd need to account for the blocksize being larger than a page | |
12170 | * + the direct-RAM access case is almost always going to be dealt | |
12171 | * with in the fastpath code above, so there's no speed benefit | |
12172 | * + we would have to deal with the map returning NULL because the | |
12173 | * bounce buffer was in use | |
12174 | */ | |
12175 | for (i = 0; i < blocklen; i++) { | |
01ecaf43 | 12176 | helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETPC()); |
aca3f40b PM |
12177 | } |
12178 | } | |
12179 | #else | |
12180 | memset(g2h(vaddr), 0, blocklen); | |
12181 | #endif | |
12182 | } | |
12183 | ||
6ddbc6e4 PB |
12184 | /* Note that signed overflow is undefined in C. The following routines are |
12185 | careful to use unsigned types where modulo arithmetic is required. | |
12186 | Failure to do so _will_ break on newer gcc. */ | |
12187 | ||
12188 | /* Signed saturating arithmetic. */ | |
12189 | ||
1654b2d6 | 12190 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
12191 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
12192 | { | |
12193 | uint16_t res; | |
12194 | ||
12195 | res = a + b; | |
12196 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
12197 | if (a & 0x8000) | |
12198 | res = 0x8000; | |
12199 | else | |
12200 | res = 0x7fff; | |
12201 | } | |
12202 | return res; | |
12203 | } | |
12204 | ||
1654b2d6 | 12205 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
12206 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
12207 | { | |
12208 | uint8_t res; | |
12209 | ||
12210 | res = a + b; | |
12211 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
12212 | if (a & 0x80) | |
12213 | res = 0x80; | |
12214 | else | |
12215 | res = 0x7f; | |
12216 | } | |
12217 | return res; | |
12218 | } | |
12219 | ||
1654b2d6 | 12220 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
12221 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
12222 | { | |
12223 | uint16_t res; | |
12224 | ||
12225 | res = a - b; | |
12226 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
12227 | if (a & 0x8000) | |
12228 | res = 0x8000; | |
12229 | else | |
12230 | res = 0x7fff; | |
12231 | } | |
12232 | return res; | |
12233 | } | |
12234 | ||
1654b2d6 | 12235 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
12236 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
12237 | { | |
12238 | uint8_t res; | |
12239 | ||
12240 | res = a - b; | |
12241 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
12242 | if (a & 0x80) | |
12243 | res = 0x80; | |
12244 | else | |
12245 | res = 0x7f; | |
12246 | } | |
12247 | return res; | |
12248 | } | |
12249 | ||
12250 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
12251 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
12252 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
12253 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
12254 | #define PFX q | |
12255 | ||
12256 | #include "op_addsub.h" | |
12257 | ||
12258 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 12259 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
12260 | { |
12261 | uint16_t res; | |
12262 | res = a + b; | |
12263 | if (res < a) | |
12264 | res = 0xffff; | |
12265 | return res; | |
12266 | } | |
12267 | ||
460a09c1 | 12268 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 | 12269 | { |
4c4fd3f8 | 12270 | if (a > b) |
6ddbc6e4 PB |
12271 | return a - b; |
12272 | else | |
12273 | return 0; | |
12274 | } | |
12275 | ||
12276 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
12277 | { | |
12278 | uint8_t res; | |
12279 | res = a + b; | |
12280 | if (res < a) | |
12281 | res = 0xff; | |
12282 | return res; | |
12283 | } | |
12284 | ||
12285 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
12286 | { | |
4c4fd3f8 | 12287 | if (a > b) |
6ddbc6e4 PB |
12288 | return a - b; |
12289 | else | |
12290 | return 0; | |
12291 | } | |
12292 | ||
12293 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
12294 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
12295 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
12296 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
12297 | #define PFX uq | |
12298 | ||
12299 | #include "op_addsub.h" | |
12300 | ||
12301 | /* Signed modulo arithmetic. */ | |
12302 | #define SARITH16(a, b, n, op) do { \ | |
12303 | int32_t sum; \ | |
db6e2e65 | 12304 | sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
6ddbc6e4 PB |
12305 | RESULT(sum, n, 16); \ |
12306 | if (sum >= 0) \ | |
12307 | ge |= 3 << (n * 2); \ | |
12308 | } while(0) | |
12309 | ||
12310 | #define SARITH8(a, b, n, op) do { \ | |
12311 | int32_t sum; \ | |
db6e2e65 | 12312 | sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
6ddbc6e4 PB |
12313 | RESULT(sum, n, 8); \ |
12314 | if (sum >= 0) \ | |
12315 | ge |= 1 << n; \ | |
12316 | } while(0) | |
12317 | ||
12318 | ||
12319 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
12320 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
12321 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
12322 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
12323 | #define PFX s | |
12324 | #define ARITH_GE | |
12325 | ||
12326 | #include "op_addsub.h" | |
12327 | ||
12328 | /* Unsigned modulo arithmetic. */ | |
12329 | #define ADD16(a, b, n) do { \ | |
12330 | uint32_t sum; \ | |
12331 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
12332 | RESULT(sum, n, 16); \ | |
a87aa10b | 12333 | if ((sum >> 16) == 1) \ |
6ddbc6e4 PB |
12334 | ge |= 3 << (n * 2); \ |
12335 | } while(0) | |
12336 | ||
12337 | #define ADD8(a, b, n) do { \ | |
12338 | uint32_t sum; \ | |
12339 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
12340 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
12341 | if ((sum >> 8) == 1) \ |
12342 | ge |= 1 << n; \ | |
6ddbc6e4 PB |
12343 | } while(0) |
12344 | ||
12345 | #define SUB16(a, b, n) do { \ | |
12346 | uint32_t sum; \ | |
12347 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
12348 | RESULT(sum, n, 16); \ | |
12349 | if ((sum >> 16) == 0) \ | |
12350 | ge |= 3 << (n * 2); \ | |
12351 | } while(0) | |
12352 | ||
12353 | #define SUB8(a, b, n) do { \ | |
12354 | uint32_t sum; \ | |
12355 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
12356 | RESULT(sum, n, 8); \ | |
12357 | if ((sum >> 8) == 0) \ | |
a87aa10b | 12358 | ge |= 1 << n; \ |
6ddbc6e4 PB |
12359 | } while(0) |
12360 | ||
12361 | #define PFX u | |
12362 | #define ARITH_GE | |
12363 | ||
12364 | #include "op_addsub.h" | |
12365 | ||
12366 | /* Halved signed arithmetic. */ | |
12367 | #define ADD16(a, b, n) \ | |
12368 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
12369 | #define SUB16(a, b, n) \ | |
12370 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
12371 | #define ADD8(a, b, n) \ | |
12372 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
12373 | #define SUB8(a, b, n) \ | |
12374 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
12375 | #define PFX sh | |
12376 | ||
12377 | #include "op_addsub.h" | |
12378 | ||
12379 | /* Halved unsigned arithmetic. */ | |
12380 | #define ADD16(a, b, n) \ | |
12381 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
12382 | #define SUB16(a, b, n) \ | |
12383 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
12384 | #define ADD8(a, b, n) \ | |
12385 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
12386 | #define SUB8(a, b, n) \ | |
12387 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
12388 | #define PFX uh | |
12389 | ||
12390 | #include "op_addsub.h" | |
12391 | ||
12392 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
12393 | { | |
12394 | if (a > b) | |
12395 | return a - b; | |
12396 | else | |
12397 | return b - a; | |
12398 | } | |
12399 | ||
12400 | /* Unsigned sum of absolute byte differences. */ | |
12401 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
12402 | { | |
12403 | uint32_t sum; | |
12404 | sum = do_usad(a, b); | |
12405 | sum += do_usad(a >> 8, b >> 8); | |
12406 | sum += do_usad(a >> 16, b >>16); | |
12407 | sum += do_usad(a >> 24, b >> 24); | |
12408 | return sum; | |
12409 | } | |
12410 | ||
12411 | /* For ARMv6 SEL instruction. */ | |
12412 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
12413 | { | |
12414 | uint32_t mask; | |
12415 | ||
12416 | mask = 0; | |
12417 | if (flags & 1) | |
12418 | mask |= 0xff; | |
12419 | if (flags & 2) | |
12420 | mask |= 0xff00; | |
12421 | if (flags & 4) | |
12422 | mask |= 0xff0000; | |
12423 | if (flags & 8) | |
12424 | mask |= 0xff000000; | |
12425 | return (a & mask) | (b & ~mask); | |
12426 | } | |
12427 | ||
b90372ad PM |
12428 | /* VFP support. We follow the convention used for VFP instructions: |
12429 | Single precision routines have a "s" suffix, double precision a | |
4373f3ce PB |
12430 | "d" suffix. */ |
12431 | ||
12432 | /* Convert host exception flags to vfp form. */ | |
12433 | static inline int vfp_exceptbits_from_host(int host_bits) | |
12434 | { | |
12435 | int target_bits = 0; | |
12436 | ||
12437 | if (host_bits & float_flag_invalid) | |
12438 | target_bits |= 1; | |
12439 | if (host_bits & float_flag_divbyzero) | |
12440 | target_bits |= 2; | |
12441 | if (host_bits & float_flag_overflow) | |
12442 | target_bits |= 4; | |
36802b6b | 12443 | if (host_bits & (float_flag_underflow | float_flag_output_denormal)) |
4373f3ce PB |
12444 | target_bits |= 8; |
12445 | if (host_bits & float_flag_inexact) | |
12446 | target_bits |= 0x10; | |
cecd8504 PM |
12447 | if (host_bits & float_flag_input_denormal) |
12448 | target_bits |= 0x80; | |
4373f3ce PB |
12449 | return target_bits; |
12450 | } | |
12451 | ||
0ecb72a5 | 12452 | uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) |
4373f3ce PB |
12453 | { |
12454 | int i; | |
12455 | uint32_t fpscr; | |
12456 | ||
12457 | fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) | |
12458 | | (env->vfp.vec_len << 16) | |
12459 | | (env->vfp.vec_stride << 20); | |
19062c16 | 12460 | |
4373f3ce | 12461 | i = get_float_exception_flags(&env->vfp.fp_status); |
3a492f3a | 12462 | i |= get_float_exception_flags(&env->vfp.standard_fp_status); |
19062c16 RH |
12463 | /* FZ16 does not generate an input denormal exception. */ |
12464 | i |= (get_float_exception_flags(&env->vfp.fp_status_f16) | |
12465 | & ~float_flag_input_denormal); | |
12466 | ||
4373f3ce PB |
12467 | fpscr |= vfp_exceptbits_from_host(i); |
12468 | return fpscr; | |
12469 | } | |
12470 | ||
0ecb72a5 | 12471 | uint32_t vfp_get_fpscr(CPUARMState *env) |
01653295 PM |
12472 | { |
12473 | return HELPER(vfp_get_fpscr)(env); | |
12474 | } | |
12475 | ||
4373f3ce PB |
12476 | /* Convert vfp exception flags to target form. */ |
12477 | static inline int vfp_exceptbits_to_host(int target_bits) | |
12478 | { | |
12479 | int host_bits = 0; | |
12480 | ||
12481 | if (target_bits & 1) | |
12482 | host_bits |= float_flag_invalid; | |
12483 | if (target_bits & 2) | |
12484 | host_bits |= float_flag_divbyzero; | |
12485 | if (target_bits & 4) | |
12486 | host_bits |= float_flag_overflow; | |
12487 | if (target_bits & 8) | |
12488 | host_bits |= float_flag_underflow; | |
12489 | if (target_bits & 0x10) | |
12490 | host_bits |= float_flag_inexact; | |
cecd8504 PM |
12491 | if (target_bits & 0x80) |
12492 | host_bits |= float_flag_input_denormal; | |
4373f3ce PB |
12493 | return host_bits; |
12494 | } | |
12495 | ||
0ecb72a5 | 12496 | void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) |
4373f3ce PB |
12497 | { |
12498 | int i; | |
12499 | uint32_t changed; | |
12500 | ||
0b62159b | 12501 | /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ |
5763190f | 12502 | if (!cpu_isar_feature(aa64_fp16, arm_env_get_cpu(env))) { |
0b62159b RH |
12503 | val &= ~FPCR_FZ16; |
12504 | } | |
12505 | ||
4373f3ce PB |
12506 | changed = env->vfp.xregs[ARM_VFP_FPSCR]; |
12507 | env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); | |
12508 | env->vfp.vec_len = (val >> 16) & 7; | |
12509 | env->vfp.vec_stride = (val >> 20) & 3; | |
12510 | ||
12511 | changed ^= val; | |
12512 | if (changed & (3 << 22)) { | |
12513 | i = (val >> 22) & 3; | |
12514 | switch (i) { | |
4d3da0f3 | 12515 | case FPROUNDING_TIEEVEN: |
4373f3ce PB |
12516 | i = float_round_nearest_even; |
12517 | break; | |
4d3da0f3 | 12518 | case FPROUNDING_POSINF: |
4373f3ce PB |
12519 | i = float_round_up; |
12520 | break; | |
4d3da0f3 | 12521 | case FPROUNDING_NEGINF: |
4373f3ce PB |
12522 | i = float_round_down; |
12523 | break; | |
4d3da0f3 | 12524 | case FPROUNDING_ZERO: |
4373f3ce PB |
12525 | i = float_round_to_zero; |
12526 | break; | |
12527 | } | |
12528 | set_float_rounding_mode(i, &env->vfp.fp_status); | |
d81ce0ef | 12529 | set_float_rounding_mode(i, &env->vfp.fp_status_f16); |
4373f3ce | 12530 | } |
d81ce0ef AB |
12531 | if (changed & FPCR_FZ16) { |
12532 | bool ftz_enabled = val & FPCR_FZ16; | |
12533 | set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16); | |
12534 | set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16); | |
12535 | } | |
12536 | if (changed & FPCR_FZ) { | |
12537 | bool ftz_enabled = val & FPCR_FZ; | |
12538 | set_flush_to_zero(ftz_enabled, &env->vfp.fp_status); | |
12539 | set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status); | |
12540 | } | |
12541 | if (changed & FPCR_DN) { | |
12542 | bool dnan_enabled = val & FPCR_DN; | |
12543 | set_default_nan_mode(dnan_enabled, &env->vfp.fp_status); | |
12544 | set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16); | |
cecd8504 | 12545 | } |
4373f3ce | 12546 | |
d81ce0ef AB |
12547 | /* The exception flags are ORed together when we read fpscr so we |
12548 | * only need to preserve the current state in one of our | |
12549 | * float_status values. | |
12550 | */ | |
b12c390b | 12551 | i = vfp_exceptbits_to_host(val); |
4373f3ce | 12552 | set_float_exception_flags(i, &env->vfp.fp_status); |
d81ce0ef | 12553 | set_float_exception_flags(0, &env->vfp.fp_status_f16); |
3a492f3a | 12554 | set_float_exception_flags(0, &env->vfp.standard_fp_status); |
4373f3ce PB |
12555 | } |
12556 | ||
0ecb72a5 | 12557 | void vfp_set_fpscr(CPUARMState *env, uint32_t val) |
01653295 PM |
12558 | { |
12559 | HELPER(vfp_set_fpscr)(env, val); | |
12560 | } | |
12561 | ||
4373f3ce PB |
12562 | #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) |
12563 | ||
12564 | #define VFP_BINOP(name) \ | |
ae1857ec | 12565 | float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \ |
4373f3ce | 12566 | { \ |
ae1857ec PM |
12567 | float_status *fpst = fpstp; \ |
12568 | return float32_ ## name(a, b, fpst); \ | |
4373f3ce | 12569 | } \ |
ae1857ec | 12570 | float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \ |
4373f3ce | 12571 | { \ |
ae1857ec PM |
12572 | float_status *fpst = fpstp; \ |
12573 | return float64_ ## name(a, b, fpst); \ | |
4373f3ce PB |
12574 | } |
12575 | VFP_BINOP(add) | |
12576 | VFP_BINOP(sub) | |
12577 | VFP_BINOP(mul) | |
12578 | VFP_BINOP(div) | |
f71a2ae5 PM |
12579 | VFP_BINOP(min) |
12580 | VFP_BINOP(max) | |
12581 | VFP_BINOP(minnum) | |
12582 | VFP_BINOP(maxnum) | |
4373f3ce PB |
12583 | #undef VFP_BINOP |
12584 | ||
12585 | float32 VFP_HELPER(neg, s)(float32 a) | |
12586 | { | |
12587 | return float32_chs(a); | |
12588 | } | |
12589 | ||
12590 | float64 VFP_HELPER(neg, d)(float64 a) | |
12591 | { | |
66230e0d | 12592 | return float64_chs(a); |
4373f3ce PB |
12593 | } |
12594 | ||
12595 | float32 VFP_HELPER(abs, s)(float32 a) | |
12596 | { | |
12597 | return float32_abs(a); | |
12598 | } | |
12599 | ||
12600 | float64 VFP_HELPER(abs, d)(float64 a) | |
12601 | { | |
66230e0d | 12602 | return float64_abs(a); |
4373f3ce PB |
12603 | } |
12604 | ||
0ecb72a5 | 12605 | float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env) |
4373f3ce PB |
12606 | { |
12607 | return float32_sqrt(a, &env->vfp.fp_status); | |
12608 | } | |
12609 | ||
0ecb72a5 | 12610 | float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) |
4373f3ce PB |
12611 | { |
12612 | return float64_sqrt(a, &env->vfp.fp_status); | |
12613 | } | |
12614 | ||
12615 | /* XXX: check quiet/signaling case */ | |
12616 | #define DO_VFP_cmp(p, type) \ | |
0ecb72a5 | 12617 | void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
12618 | { \ |
12619 | uint32_t flags; \ | |
12620 | switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ | |
12621 | case 0: flags = 0x6; break; \ | |
12622 | case -1: flags = 0x8; break; \ | |
12623 | case 1: flags = 0x2; break; \ | |
12624 | default: case 2: flags = 0x3; break; \ | |
12625 | } \ | |
12626 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
12627 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
12628 | } \ | |
0ecb72a5 | 12629 | void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \ |
4373f3ce PB |
12630 | { \ |
12631 | uint32_t flags; \ | |
12632 | switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ | |
12633 | case 0: flags = 0x6; break; \ | |
12634 | case -1: flags = 0x8; break; \ | |
12635 | case 1: flags = 0x2; break; \ | |
12636 | default: case 2: flags = 0x3; break; \ | |
12637 | } \ | |
12638 | env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ | |
12639 | | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ | |
12640 | } | |
12641 | DO_VFP_cmp(s, float32) | |
12642 | DO_VFP_cmp(d, float64) | |
12643 | #undef DO_VFP_cmp | |
12644 | ||
5500b06c | 12645 | /* Integer to float and float to integer conversions */ |
4373f3ce | 12646 | |
6c2be133 RH |
12647 | #define CONV_ITOF(name, ftype, fsz, sign) \ |
12648 | ftype HELPER(name)(uint32_t x, void *fpstp) \ | |
12649 | { \ | |
12650 | float_status *fpst = fpstp; \ | |
12651 | return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ | |
12652 | } | |
12653 | ||
12654 | #define CONV_FTOI(name, ftype, fsz, sign, round) \ | |
df4de1af | 12655 | sign##int32_t HELPER(name)(ftype x, void *fpstp) \ |
6c2be133 RH |
12656 | { \ |
12657 | float_status *fpst = fpstp; \ | |
12658 | if (float##fsz##_is_any_nan(x)) { \ | |
12659 | float_raise(float_flag_invalid, fpst); \ | |
12660 | return 0; \ | |
12661 | } \ | |
12662 | return float##fsz##_to_##sign##int32##round(x, fpst); \ | |
12663 | } | |
12664 | ||
12665 | #define FLOAT_CONVS(name, p, ftype, fsz, sign) \ | |
12666 | CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \ | |
12667 | CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \ | |
12668 | CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero) | |
12669 | ||
12670 | FLOAT_CONVS(si, h, uint32_t, 16, ) | |
12671 | FLOAT_CONVS(si, s, float32, 32, ) | |
12672 | FLOAT_CONVS(si, d, float64, 64, ) | |
12673 | FLOAT_CONVS(ui, h, uint32_t, 16, u) | |
12674 | FLOAT_CONVS(ui, s, float32, 32, u) | |
12675 | FLOAT_CONVS(ui, d, float64, 64, u) | |
4373f3ce | 12676 | |
5500b06c PM |
12677 | #undef CONV_ITOF |
12678 | #undef CONV_FTOI | |
12679 | #undef FLOAT_CONVS | |
4373f3ce PB |
12680 | |
12681 | /* floating point conversion */ | |
0ecb72a5 | 12682 | float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) |
4373f3ce | 12683 | { |
a9d173dc | 12684 | return float32_to_float64(x, &env->vfp.fp_status); |
4373f3ce PB |
12685 | } |
12686 | ||
0ecb72a5 | 12687 | float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) |
4373f3ce | 12688 | { |
a9d173dc | 12689 | return float64_to_float32(x, &env->vfp.fp_status); |
4373f3ce PB |
12690 | } |
12691 | ||
12692 | /* VFP3 fixed point conversion. */ | |
16d5b3ca | 12693 | #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ |
8ed697e8 WN |
12694 | float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ |
12695 | void *fpstp) \ | |
b9b903cf | 12696 | { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); } |
16d5b3ca | 12697 | |
323cd490 RH |
12698 | #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ROUND, suff) \ |
12699 | uint##isz##_t HELPER(vfp_to##name##p##suff)(float##fsz x, uint32_t shift, \ | |
12700 | void *fpst) \ | |
12701 | { \ | |
12702 | if (unlikely(float##fsz##_is_any_nan(x))) { \ | |
12703 | float_raise(float_flag_invalid, fpst); \ | |
12704 | return 0; \ | |
12705 | } \ | |
12706 | return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \ | |
622465e1 PM |
12707 | } |
12708 | ||
16d5b3ca WN |
12709 | #define VFP_CONV_FIX(name, p, fsz, isz, itype) \ |
12710 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
323cd490 RH |
12711 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \ |
12712 | float_round_to_zero, _round_to_zero) \ | |
12713 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \ | |
12714 | get_float_rounding_mode(fpst), ) | |
3c6a074a WN |
12715 | |
12716 | #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \ | |
12717 | VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \ | |
323cd490 RH |
12718 | VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \ |
12719 | get_float_rounding_mode(fpst), ) | |
16d5b3ca | 12720 | |
8ed697e8 WN |
12721 | VFP_CONV_FIX(sh, d, 64, 64, int16) |
12722 | VFP_CONV_FIX(sl, d, 64, 64, int32) | |
3c6a074a | 12723 | VFP_CONV_FIX_A64(sq, d, 64, 64, int64) |
8ed697e8 WN |
12724 | VFP_CONV_FIX(uh, d, 64, 64, uint16) |
12725 | VFP_CONV_FIX(ul, d, 64, 64, uint32) | |
3c6a074a | 12726 | VFP_CONV_FIX_A64(uq, d, 64, 64, uint64) |
8ed697e8 WN |
12727 | VFP_CONV_FIX(sh, s, 32, 32, int16) |
12728 | VFP_CONV_FIX(sl, s, 32, 32, int32) | |
3c6a074a | 12729 | VFP_CONV_FIX_A64(sq, s, 32, 64, int64) |
8ed697e8 WN |
12730 | VFP_CONV_FIX(uh, s, 32, 32, uint16) |
12731 | VFP_CONV_FIX(ul, s, 32, 32, uint32) | |
3c6a074a | 12732 | VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) |
88808a02 | 12733 | |
4373f3ce | 12734 | #undef VFP_CONV_FIX |
16d5b3ca WN |
12735 | #undef VFP_CONV_FIX_FLOAT |
12736 | #undef VFP_CONV_FLOAT_FIX_ROUND | |
88808a02 RH |
12737 | #undef VFP_CONV_FIX_A64 |
12738 | ||
6c2be133 | 12739 | uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst) |
88808a02 | 12740 | { |
b9b903cf | 12741 | return int32_to_float16_scalbn(x, -shift, fpst); |
88808a02 RH |
12742 | } |
12743 | ||
6c2be133 | 12744 | uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst) |
88808a02 | 12745 | { |
b9b903cf | 12746 | return uint32_to_float16_scalbn(x, -shift, fpst); |
88808a02 RH |
12747 | } |
12748 | ||
6c2be133 | 12749 | uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst) |
564a0632 | 12750 | { |
b9b903cf | 12751 | return int64_to_float16_scalbn(x, -shift, fpst); |
564a0632 RH |
12752 | } |
12753 | ||
6c2be133 | 12754 | uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst) |
564a0632 | 12755 | { |
b9b903cf | 12756 | return uint64_to_float16_scalbn(x, -shift, fpst); |
564a0632 RH |
12757 | } |
12758 | ||
323cd490 | 12759 | uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst) |
88808a02 | 12760 | { |
323cd490 | 12761 | if (unlikely(float16_is_any_nan(x))) { |
88808a02 RH |
12762 | float_raise(float_flag_invalid, fpst); |
12763 | return 0; | |
88808a02 | 12764 | } |
323cd490 RH |
12765 | return float16_to_int16_scalbn(x, get_float_rounding_mode(fpst), |
12766 | shift, fpst); | |
88808a02 RH |
12767 | } |
12768 | ||
6c2be133 | 12769 | uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst) |
88808a02 | 12770 | { |
323cd490 RH |
12771 | if (unlikely(float16_is_any_nan(x))) { |
12772 | float_raise(float_flag_invalid, fpst); | |
12773 | return 0; | |
12774 | } | |
12775 | return float16_to_uint16_scalbn(x, get_float_rounding_mode(fpst), | |
12776 | shift, fpst); | |
88808a02 | 12777 | } |
4373f3ce | 12778 | |
6c2be133 | 12779 | uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst) |
564a0632 | 12780 | { |
323cd490 RH |
12781 | if (unlikely(float16_is_any_nan(x))) { |
12782 | float_raise(float_flag_invalid, fpst); | |
12783 | return 0; | |
12784 | } | |
12785 | return float16_to_int32_scalbn(x, get_float_rounding_mode(fpst), | |
12786 | shift, fpst); | |
564a0632 RH |
12787 | } |
12788 | ||
6c2be133 | 12789 | uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst) |
564a0632 | 12790 | { |
323cd490 RH |
12791 | if (unlikely(float16_is_any_nan(x))) { |
12792 | float_raise(float_flag_invalid, fpst); | |
12793 | return 0; | |
12794 | } | |
12795 | return float16_to_uint32_scalbn(x, get_float_rounding_mode(fpst), | |
12796 | shift, fpst); | |
564a0632 RH |
12797 | } |
12798 | ||
6c2be133 | 12799 | uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst) |
564a0632 | 12800 | { |
323cd490 RH |
12801 | if (unlikely(float16_is_any_nan(x))) { |
12802 | float_raise(float_flag_invalid, fpst); | |
12803 | return 0; | |
12804 | } | |
12805 | return float16_to_int64_scalbn(x, get_float_rounding_mode(fpst), | |
12806 | shift, fpst); | |
564a0632 RH |
12807 | } |
12808 | ||
6c2be133 | 12809 | uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst) |
564a0632 | 12810 | { |
323cd490 RH |
12811 | if (unlikely(float16_is_any_nan(x))) { |
12812 | float_raise(float_flag_invalid, fpst); | |
12813 | return 0; | |
12814 | } | |
12815 | return float16_to_uint64_scalbn(x, get_float_rounding_mode(fpst), | |
12816 | shift, fpst); | |
564a0632 RH |
12817 | } |
12818 | ||
52a1f6a3 AG |
12819 | /* Set the current fp rounding mode and return the old one. |
12820 | * The argument is a softfloat float_round_ value. | |
12821 | */ | |
9b049916 | 12822 | uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp) |
52a1f6a3 | 12823 | { |
9b049916 | 12824 | float_status *fp_status = fpstp; |
52a1f6a3 AG |
12825 | |
12826 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
12827 | set_float_rounding_mode(rmode, fp_status); | |
12828 | ||
12829 | return prev_rmode; | |
12830 | } | |
12831 | ||
43630e58 WN |
12832 | /* Set the current fp rounding mode in the standard fp status and return |
12833 | * the old one. This is for NEON instructions that need to change the | |
12834 | * rounding mode but wish to use the standard FPSCR values for everything | |
12835 | * else. Always set the rounding mode back to the correct value after | |
12836 | * modifying it. | |
12837 | * The argument is a softfloat float_round_ value. | |
12838 | */ | |
12839 | uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) | |
12840 | { | |
12841 | float_status *fp_status = &env->vfp.standard_fp_status; | |
12842 | ||
12843 | uint32_t prev_rmode = get_float_rounding_mode(fp_status); | |
12844 | set_float_rounding_mode(rmode, fp_status); | |
12845 | ||
12846 | return prev_rmode; | |
12847 | } | |
12848 | ||
60011498 | 12849 | /* Half precision conversions. */ |
6c2be133 | 12850 | float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode) |
60011498 | 12851 | { |
0acb9e7c AB |
12852 | /* Squash FZ16 to 0 for the duration of conversion. In this case, |
12853 | * it would affect flushing input denormals. | |
12854 | */ | |
12855 | float_status *fpst = fpstp; | |
12856 | flag save = get_flush_inputs_to_zero(fpst); | |
12857 | set_flush_inputs_to_zero(false, fpst); | |
12858 | float32 r = float16_to_float32(a, !ahp_mode, fpst); | |
12859 | set_flush_inputs_to_zero(save, fpst); | |
12860 | return r; | |
2d981da7 PM |
12861 | } |
12862 | ||
6c2be133 | 12863 | uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode) |
2d981da7 | 12864 | { |
0acb9e7c AB |
12865 | /* Squash FZ16 to 0 for the duration of conversion. In this case, |
12866 | * it would affect flushing output denormals. | |
12867 | */ | |
12868 | float_status *fpst = fpstp; | |
12869 | flag save = get_flush_to_zero(fpst); | |
12870 | set_flush_to_zero(false, fpst); | |
12871 | float16 r = float32_to_float16(a, !ahp_mode, fpst); | |
12872 | set_flush_to_zero(save, fpst); | |
12873 | return r; | |
2d981da7 PM |
12874 | } |
12875 | ||
6c2be133 | 12876 | float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode) |
2d981da7 | 12877 | { |
0acb9e7c AB |
12878 | /* Squash FZ16 to 0 for the duration of conversion. In this case, |
12879 | * it would affect flushing input denormals. | |
12880 | */ | |
12881 | float_status *fpst = fpstp; | |
12882 | flag save = get_flush_inputs_to_zero(fpst); | |
12883 | set_flush_inputs_to_zero(false, fpst); | |
12884 | float64 r = float16_to_float64(a, !ahp_mode, fpst); | |
12885 | set_flush_inputs_to_zero(save, fpst); | |
12886 | return r; | |
2d981da7 PM |
12887 | } |
12888 | ||
6c2be133 | 12889 | uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode) |
2d981da7 | 12890 | { |
0acb9e7c AB |
12891 | /* Squash FZ16 to 0 for the duration of conversion. In this case, |
12892 | * it would affect flushing output denormals. | |
12893 | */ | |
12894 | float_status *fpst = fpstp; | |
12895 | flag save = get_flush_to_zero(fpst); | |
12896 | set_flush_to_zero(false, fpst); | |
12897 | float16 r = float64_to_float16(a, !ahp_mode, fpst); | |
12898 | set_flush_to_zero(save, fpst); | |
12899 | return r; | |
8900aad2 PM |
12900 | } |
12901 | ||
dda3ec49 | 12902 | #define float32_two make_float32(0x40000000) |
6aae3df1 PM |
12903 | #define float32_three make_float32(0x40400000) |
12904 | #define float32_one_point_five make_float32(0x3fc00000) | |
dda3ec49 | 12905 | |
0ecb72a5 | 12906 | float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 12907 | { |
dda3ec49 PM |
12908 | float_status *s = &env->vfp.standard_fp_status; |
12909 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
12910 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
12911 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
12912 | float_raise(float_flag_input_denormal, s); | |
12913 | } | |
dda3ec49 PM |
12914 | return float32_two; |
12915 | } | |
12916 | return float32_sub(float32_two, float32_mul(a, b, s), s); | |
4373f3ce PB |
12917 | } |
12918 | ||
0ecb72a5 | 12919 | float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) |
4373f3ce | 12920 | { |
71826966 | 12921 | float_status *s = &env->vfp.standard_fp_status; |
9ea62f57 PM |
12922 | float32 product; |
12923 | if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) || | |
12924 | (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) { | |
43fe9bdb PM |
12925 | if (!(float32_is_zero(a) || float32_is_zero(b))) { |
12926 | float_raise(float_flag_input_denormal, s); | |
12927 | } | |
6aae3df1 | 12928 | return float32_one_point_five; |
9ea62f57 | 12929 | } |
6aae3df1 PM |
12930 | product = float32_mul(a, b, s); |
12931 | return float32_div(float32_sub(float32_three, product, s), float32_two, s); | |
4373f3ce PB |
12932 | } |
12933 | ||
8f8e3aa4 PB |
12934 | /* NEON helpers. */ |
12935 | ||
56bf4fe2 CL |
12936 | /* Constants 256 and 512 are used in some helpers; we avoid relying on |
12937 | * int->float conversions at run-time. */ | |
12938 | #define float64_256 make_float64(0x4070000000000000LL) | |
12939 | #define float64_512 make_float64(0x4080000000000000LL) | |
5eb70735 | 12940 | #define float16_maxnorm make_float16(0x7bff) |
b6d4443a AB |
12941 | #define float32_maxnorm make_float32(0x7f7fffff) |
12942 | #define float64_maxnorm make_float64(0x7fefffffffffffffLL) | |
56bf4fe2 | 12943 | |
b6d4443a AB |
12944 | /* Reciprocal functions |
12945 | * | |
12946 | * The algorithm that must be used to calculate the estimate | |
5eb70735 | 12947 | * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate |
fe0e4872 | 12948 | */ |
b6d4443a | 12949 | |
5eb70735 AB |
12950 | /* See RecipEstimate() |
12951 | * | |
12952 | * input is a 9 bit fixed point number | |
12953 | * input range 256 .. 511 for a number from 0.5 <= x < 1.0. | |
12954 | * result range 256 .. 511 for a number from 1.0 to 511/256. | |
12955 | */ | |
fe0e4872 | 12956 | |
5eb70735 AB |
12957 | static int recip_estimate(int input) |
12958 | { | |
12959 | int a, b, r; | |
12960 | assert(256 <= input && input < 512); | |
12961 | a = (input * 2) + 1; | |
12962 | b = (1 << 19) / a; | |
12963 | r = (b + 1) >> 1; | |
12964 | assert(256 <= r && r < 512); | |
12965 | return r; | |
fe0e4872 CL |
12966 | } |
12967 | ||
5eb70735 AB |
12968 | /* |
12969 | * Common wrapper to call recip_estimate | |
12970 | * | |
12971 | * The parameters are exponent and 64 bit fraction (without implicit | |
12972 | * bit) where the binary point is nominally at bit 52. Returns a | |
12973 | * float64 which can then be rounded to the appropriate size by the | |
12974 | * callee. | |
12975 | */ | |
12976 | ||
12977 | static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac) | |
4373f3ce | 12978 | { |
5eb70735 AB |
12979 | uint32_t scaled, estimate; |
12980 | uint64_t result_frac; | |
12981 | int result_exp; | |
fe0e4872 | 12982 | |
5eb70735 AB |
12983 | /* Handle sub-normals */ |
12984 | if (*exp == 0) { | |
b6d4443a | 12985 | if (extract64(frac, 51, 1) == 0) { |
5eb70735 AB |
12986 | *exp = -1; |
12987 | frac <<= 2; | |
b6d4443a | 12988 | } else { |
5eb70735 | 12989 | frac <<= 1; |
b6d4443a AB |
12990 | } |
12991 | } | |
fe0e4872 | 12992 | |
5eb70735 AB |
12993 | /* scaled = UInt('1':fraction<51:44>) */ |
12994 | scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); | |
12995 | estimate = recip_estimate(scaled); | |
b6d4443a | 12996 | |
5eb70735 AB |
12997 | result_exp = exp_off - *exp; |
12998 | result_frac = deposit64(0, 44, 8, estimate); | |
12999 | if (result_exp == 0) { | |
13000 | result_frac = deposit64(result_frac >> 1, 51, 1, 1); | |
13001 | } else if (result_exp == -1) { | |
13002 | result_frac = deposit64(result_frac >> 2, 50, 2, 1); | |
13003 | result_exp = 0; | |
b6d4443a AB |
13004 | } |
13005 | ||
5eb70735 AB |
13006 | *exp = result_exp; |
13007 | ||
13008 | return result_frac; | |
b6d4443a AB |
13009 | } |
13010 | ||
13011 | static bool round_to_inf(float_status *fpst, bool sign_bit) | |
13012 | { | |
13013 | switch (fpst->float_rounding_mode) { | |
13014 | case float_round_nearest_even: /* Round to Nearest */ | |
13015 | return true; | |
13016 | case float_round_up: /* Round to +Inf */ | |
13017 | return !sign_bit; | |
13018 | case float_round_down: /* Round to -Inf */ | |
13019 | return sign_bit; | |
13020 | case float_round_to_zero: /* Round to Zero */ | |
13021 | return false; | |
13022 | } | |
13023 | ||
13024 | g_assert_not_reached(); | |
13025 | } | |
13026 | ||
6c2be133 | 13027 | uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp) |
5eb70735 AB |
13028 | { |
13029 | float_status *fpst = fpstp; | |
13030 | float16 f16 = float16_squash_input_denormal(input, fpst); | |
13031 | uint32_t f16_val = float16_val(f16); | |
13032 | uint32_t f16_sign = float16_is_neg(f16); | |
13033 | int f16_exp = extract32(f16_val, 10, 5); | |
13034 | uint32_t f16_frac = extract32(f16_val, 0, 10); | |
13035 | uint64_t f64_frac; | |
13036 | ||
13037 | if (float16_is_any_nan(f16)) { | |
13038 | float16 nan = f16; | |
13039 | if (float16_is_signaling_nan(f16, fpst)) { | |
13040 | float_raise(float_flag_invalid, fpst); | |
d7ecc062 | 13041 | nan = float16_silence_nan(f16, fpst); |
5eb70735 AB |
13042 | } |
13043 | if (fpst->default_nan_mode) { | |
13044 | nan = float16_default_nan(fpst); | |
13045 | } | |
13046 | return nan; | |
13047 | } else if (float16_is_infinity(f16)) { | |
13048 | return float16_set_sign(float16_zero, float16_is_neg(f16)); | |
13049 | } else if (float16_is_zero(f16)) { | |
13050 | float_raise(float_flag_divbyzero, fpst); | |
13051 | return float16_set_sign(float16_infinity, float16_is_neg(f16)); | |
13052 | } else if (float16_abs(f16) < (1 << 8)) { | |
13053 | /* Abs(value) < 2.0^-16 */ | |
13054 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
13055 | if (round_to_inf(fpst, f16_sign)) { | |
13056 | return float16_set_sign(float16_infinity, f16_sign); | |
13057 | } else { | |
13058 | return float16_set_sign(float16_maxnorm, f16_sign); | |
13059 | } | |
13060 | } else if (f16_exp >= 29 && fpst->flush_to_zero) { | |
13061 | float_raise(float_flag_underflow, fpst); | |
13062 | return float16_set_sign(float16_zero, float16_is_neg(f16)); | |
13063 | } | |
13064 | ||
13065 | f64_frac = call_recip_estimate(&f16_exp, 29, | |
13066 | ((uint64_t) f16_frac) << (52 - 10)); | |
13067 | ||
13068 | /* result = sign : result_exp<4:0> : fraction<51:42> */ | |
13069 | f16_val = deposit32(0, 15, 1, f16_sign); | |
13070 | f16_val = deposit32(f16_val, 10, 5, f16_exp); | |
13071 | f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10)); | |
13072 | return make_float16(f16_val); | |
13073 | } | |
13074 | ||
b6d4443a AB |
13075 | float32 HELPER(recpe_f32)(float32 input, void *fpstp) |
13076 | { | |
13077 | float_status *fpst = fpstp; | |
13078 | float32 f32 = float32_squash_input_denormal(input, fpst); | |
13079 | uint32_t f32_val = float32_val(f32); | |
5eb70735 AB |
13080 | bool f32_sign = float32_is_neg(f32); |
13081 | int f32_exp = extract32(f32_val, 23, 8); | |
b6d4443a | 13082 | uint32_t f32_frac = extract32(f32_val, 0, 23); |
5eb70735 | 13083 | uint64_t f64_frac; |
b6d4443a AB |
13084 | |
13085 | if (float32_is_any_nan(f32)) { | |
13086 | float32 nan = f32; | |
af39bc8c | 13087 | if (float32_is_signaling_nan(f32, fpst)) { |
b6d4443a | 13088 | float_raise(float_flag_invalid, fpst); |
d7ecc062 | 13089 | nan = float32_silence_nan(f32, fpst); |
fe0e4872 | 13090 | } |
b6d4443a | 13091 | if (fpst->default_nan_mode) { |
af39bc8c | 13092 | nan = float32_default_nan(fpst); |
43fe9bdb | 13093 | } |
b6d4443a AB |
13094 | return nan; |
13095 | } else if (float32_is_infinity(f32)) { | |
13096 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
13097 | } else if (float32_is_zero(f32)) { | |
13098 | float_raise(float_flag_divbyzero, fpst); | |
13099 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); | |
5eb70735 | 13100 | } else if (float32_abs(f32) < (1ULL << 21)) { |
b6d4443a AB |
13101 | /* Abs(value) < 2.0^-128 */ |
13102 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
5eb70735 AB |
13103 | if (round_to_inf(fpst, f32_sign)) { |
13104 | return float32_set_sign(float32_infinity, f32_sign); | |
b6d4443a | 13105 | } else { |
5eb70735 | 13106 | return float32_set_sign(float32_maxnorm, f32_sign); |
b6d4443a AB |
13107 | } |
13108 | } else if (f32_exp >= 253 && fpst->flush_to_zero) { | |
13109 | float_raise(float_flag_underflow, fpst); | |
13110 | return float32_set_sign(float32_zero, float32_is_neg(f32)); | |
fe0e4872 CL |
13111 | } |
13112 | ||
5eb70735 AB |
13113 | f64_frac = call_recip_estimate(&f32_exp, 253, |
13114 | ((uint64_t) f32_frac) << (52 - 23)); | |
fe0e4872 | 13115 | |
5eb70735 AB |
13116 | /* result = sign : result_exp<7:0> : fraction<51:29> */ |
13117 | f32_val = deposit32(0, 31, 1, f32_sign); | |
13118 | f32_val = deposit32(f32_val, 23, 8, f32_exp); | |
13119 | f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23)); | |
13120 | return make_float32(f32_val); | |
b6d4443a AB |
13121 | } |
13122 | ||
13123 | float64 HELPER(recpe_f64)(float64 input, void *fpstp) | |
13124 | { | |
13125 | float_status *fpst = fpstp; | |
13126 | float64 f64 = float64_squash_input_denormal(input, fpst); | |
13127 | uint64_t f64_val = float64_val(f64); | |
5eb70735 AB |
13128 | bool f64_sign = float64_is_neg(f64); |
13129 | int f64_exp = extract64(f64_val, 52, 11); | |
13130 | uint64_t f64_frac = extract64(f64_val, 0, 52); | |
b6d4443a AB |
13131 | |
13132 | /* Deal with any special cases */ | |
13133 | if (float64_is_any_nan(f64)) { | |
13134 | float64 nan = f64; | |
af39bc8c | 13135 | if (float64_is_signaling_nan(f64, fpst)) { |
b6d4443a | 13136 | float_raise(float_flag_invalid, fpst); |
d7ecc062 | 13137 | nan = float64_silence_nan(f64, fpst); |
b6d4443a AB |
13138 | } |
13139 | if (fpst->default_nan_mode) { | |
af39bc8c | 13140 | nan = float64_default_nan(fpst); |
b6d4443a AB |
13141 | } |
13142 | return nan; | |
13143 | } else if (float64_is_infinity(f64)) { | |
13144 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
13145 | } else if (float64_is_zero(f64)) { | |
13146 | float_raise(float_flag_divbyzero, fpst); | |
13147 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
13148 | } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { | |
13149 | /* Abs(value) < 2.0^-1024 */ | |
13150 | float_raise(float_flag_overflow | float_flag_inexact, fpst); | |
5eb70735 AB |
13151 | if (round_to_inf(fpst, f64_sign)) { |
13152 | return float64_set_sign(float64_infinity, f64_sign); | |
b6d4443a | 13153 | } else { |
5eb70735 | 13154 | return float64_set_sign(float64_maxnorm, f64_sign); |
b6d4443a | 13155 | } |
fc1792e9 | 13156 | } else if (f64_exp >= 2045 && fpst->flush_to_zero) { |
b6d4443a AB |
13157 | float_raise(float_flag_underflow, fpst); |
13158 | return float64_set_sign(float64_zero, float64_is_neg(f64)); | |
13159 | } | |
fe0e4872 | 13160 | |
5eb70735 | 13161 | f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac); |
fe0e4872 | 13162 | |
5eb70735 AB |
13163 | /* result = sign : result_exp<10:0> : fraction<51:0>; */ |
13164 | f64_val = deposit64(0, 63, 1, f64_sign); | |
13165 | f64_val = deposit64(f64_val, 52, 11, f64_exp); | |
13166 | f64_val = deposit64(f64_val, 0, 52, f64_frac); | |
13167 | return make_float64(f64_val); | |
4373f3ce PB |
13168 | } |
13169 | ||
e07be5d2 CL |
13170 | /* The algorithm that must be used to calculate the estimate |
13171 | * is specified by the ARM ARM. | |
13172 | */ | |
d719cbc7 AB |
13173 | |
13174 | static int do_recip_sqrt_estimate(int a) | |
13175 | { | |
13176 | int b, estimate; | |
13177 | ||
13178 | assert(128 <= a && a < 512); | |
13179 | if (a < 256) { | |
13180 | a = a * 2 + 1; | |
e07be5d2 | 13181 | } else { |
d719cbc7 AB |
13182 | a = (a >> 1) << 1; |
13183 | a = (a + 1) * 2; | |
13184 | } | |
13185 | b = 512; | |
13186 | while (a * (b + 1) * (b + 1) < (1 << 28)) { | |
13187 | b += 1; | |
13188 | } | |
13189 | estimate = (b + 1) / 2; | |
13190 | assert(256 <= estimate && estimate < 512); | |
13191 | ||
13192 | return estimate; | |
13193 | } | |
13194 | ||
e07be5d2 | 13195 | |
d719cbc7 AB |
13196 | static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac) |
13197 | { | |
13198 | int estimate; | |
13199 | uint32_t scaled; | |
e07be5d2 | 13200 | |
d719cbc7 AB |
13201 | if (*exp == 0) { |
13202 | while (extract64(frac, 51, 1) == 0) { | |
13203 | frac = frac << 1; | |
13204 | *exp -= 1; | |
13205 | } | |
13206 | frac = extract64(frac, 0, 51) << 1; | |
e07be5d2 | 13207 | } |
e07be5d2 | 13208 | |
d719cbc7 AB |
13209 | if (*exp & 1) { |
13210 | /* scaled = UInt('01':fraction<51:45>) */ | |
13211 | scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7)); | |
13212 | } else { | |
13213 | /* scaled = UInt('1':fraction<51:44>) */ | |
13214 | scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); | |
13215 | } | |
13216 | estimate = do_recip_sqrt_estimate(scaled); | |
e07be5d2 | 13217 | |
d719cbc7 AB |
13218 | *exp = (exp_off - *exp) / 2; |
13219 | return extract64(estimate, 0, 8) << 44; | |
13220 | } | |
13221 | ||
6c2be133 | 13222 | uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp) |
d719cbc7 AB |
13223 | { |
13224 | float_status *s = fpstp; | |
13225 | float16 f16 = float16_squash_input_denormal(input, s); | |
13226 | uint16_t val = float16_val(f16); | |
13227 | bool f16_sign = float16_is_neg(f16); | |
13228 | int f16_exp = extract32(val, 10, 5); | |
13229 | uint16_t f16_frac = extract32(val, 0, 10); | |
13230 | uint64_t f64_frac; | |
13231 | ||
13232 | if (float16_is_any_nan(f16)) { | |
13233 | float16 nan = f16; | |
13234 | if (float16_is_signaling_nan(f16, s)) { | |
13235 | float_raise(float_flag_invalid, s); | |
d7ecc062 | 13236 | nan = float16_silence_nan(f16, s); |
d719cbc7 AB |
13237 | } |
13238 | if (s->default_nan_mode) { | |
13239 | nan = float16_default_nan(s); | |
13240 | } | |
13241 | return nan; | |
13242 | } else if (float16_is_zero(f16)) { | |
13243 | float_raise(float_flag_divbyzero, s); | |
13244 | return float16_set_sign(float16_infinity, f16_sign); | |
13245 | } else if (f16_sign) { | |
13246 | float_raise(float_flag_invalid, s); | |
13247 | return float16_default_nan(s); | |
13248 | } else if (float16_is_infinity(f16)) { | |
13249 | return float16_zero; | |
13250 | } | |
13251 | ||
13252 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, | |
13253 | * preserving the parity of the exponent. */ | |
13254 | ||
13255 | f64_frac = ((uint64_t) f16_frac) << (52 - 10); | |
13256 | ||
13257 | f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac); | |
13258 | ||
13259 | /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */ | |
13260 | val = deposit32(0, 15, 1, f16_sign); | |
13261 | val = deposit32(val, 10, 5, f16_exp); | |
13262 | val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8)); | |
13263 | return make_float16(val); | |
e07be5d2 CL |
13264 | } |
13265 | ||
c2fb418e | 13266 | float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) |
4373f3ce | 13267 | { |
c2fb418e AB |
13268 | float_status *s = fpstp; |
13269 | float32 f32 = float32_squash_input_denormal(input, s); | |
13270 | uint32_t val = float32_val(f32); | |
d719cbc7 AB |
13271 | uint32_t f32_sign = float32_is_neg(f32); |
13272 | int f32_exp = extract32(val, 23, 8); | |
c2fb418e AB |
13273 | uint32_t f32_frac = extract32(val, 0, 23); |
13274 | uint64_t f64_frac; | |
e07be5d2 | 13275 | |
c2fb418e AB |
13276 | if (float32_is_any_nan(f32)) { |
13277 | float32 nan = f32; | |
af39bc8c | 13278 | if (float32_is_signaling_nan(f32, s)) { |
e07be5d2 | 13279 | float_raise(float_flag_invalid, s); |
d7ecc062 | 13280 | nan = float32_silence_nan(f32, s); |
e07be5d2 | 13281 | } |
c2fb418e | 13282 | if (s->default_nan_mode) { |
af39bc8c | 13283 | nan = float32_default_nan(s); |
43fe9bdb | 13284 | } |
c2fb418e AB |
13285 | return nan; |
13286 | } else if (float32_is_zero(f32)) { | |
e07be5d2 | 13287 | float_raise(float_flag_divbyzero, s); |
c2fb418e AB |
13288 | return float32_set_sign(float32_infinity, float32_is_neg(f32)); |
13289 | } else if (float32_is_neg(f32)) { | |
e07be5d2 | 13290 | float_raise(float_flag_invalid, s); |
af39bc8c | 13291 | return float32_default_nan(s); |
c2fb418e | 13292 | } else if (float32_is_infinity(f32)) { |
e07be5d2 CL |
13293 | return float32_zero; |
13294 | } | |
13295 | ||
c2fb418e | 13296 | /* Scale and normalize to a double-precision value between 0.25 and 1.0, |
e07be5d2 | 13297 | * preserving the parity of the exponent. */ |
c2fb418e AB |
13298 | |
13299 | f64_frac = ((uint64_t) f32_frac) << 29; | |
e07be5d2 | 13300 | |
d719cbc7 | 13301 | f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac); |
e07be5d2 | 13302 | |
d719cbc7 AB |
13303 | /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */ |
13304 | val = deposit32(0, 31, 1, f32_sign); | |
13305 | val = deposit32(val, 23, 8, f32_exp); | |
13306 | val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8)); | |
e07be5d2 | 13307 | return make_float32(val); |
4373f3ce PB |
13308 | } |
13309 | ||
c2fb418e AB |
13310 | float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) |
13311 | { | |
13312 | float_status *s = fpstp; | |
13313 | float64 f64 = float64_squash_input_denormal(input, s); | |
13314 | uint64_t val = float64_val(f64); | |
d719cbc7 AB |
13315 | bool f64_sign = float64_is_neg(f64); |
13316 | int f64_exp = extract64(val, 52, 11); | |
c2fb418e | 13317 | uint64_t f64_frac = extract64(val, 0, 52); |
c2fb418e AB |
13318 | |
13319 | if (float64_is_any_nan(f64)) { | |
13320 | float64 nan = f64; | |
af39bc8c | 13321 | if (float64_is_signaling_nan(f64, s)) { |
c2fb418e | 13322 | float_raise(float_flag_invalid, s); |
d7ecc062 | 13323 | nan = float64_silence_nan(f64, s); |
c2fb418e AB |
13324 | } |
13325 | if (s->default_nan_mode) { | |
af39bc8c | 13326 | nan = float64_default_nan(s); |
c2fb418e AB |
13327 | } |
13328 | return nan; | |
13329 | } else if (float64_is_zero(f64)) { | |
13330 | float_raise(float_flag_divbyzero, s); | |
13331 | return float64_set_sign(float64_infinity, float64_is_neg(f64)); | |
13332 | } else if (float64_is_neg(f64)) { | |
13333 | float_raise(float_flag_invalid, s); | |
af39bc8c | 13334 | return float64_default_nan(s); |
c2fb418e AB |
13335 | } else if (float64_is_infinity(f64)) { |
13336 | return float64_zero; | |
13337 | } | |
13338 | ||
d719cbc7 | 13339 | f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac); |
c2fb418e | 13340 | |
d719cbc7 AB |
13341 | /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */ |
13342 | val = deposit64(0, 61, 1, f64_sign); | |
13343 | val = deposit64(val, 52, 11, f64_exp); | |
13344 | val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8)); | |
13345 | return make_float64(val); | |
c2fb418e AB |
13346 | } |
13347 | ||
b6d4443a | 13348 | uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) |
4373f3ce | 13349 | { |
5eb70735 AB |
13350 | /* float_status *s = fpstp; */ |
13351 | int input, estimate; | |
fe0e4872 CL |
13352 | |
13353 | if ((a & 0x80000000) == 0) { | |
13354 | return 0xffffffff; | |
13355 | } | |
13356 | ||
5eb70735 AB |
13357 | input = extract32(a, 23, 9); |
13358 | estimate = recip_estimate(input); | |
fe0e4872 | 13359 | |
5eb70735 | 13360 | return deposit32(0, (32 - 9), 9, estimate); |
4373f3ce PB |
13361 | } |
13362 | ||
c2fb418e | 13363 | uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) |
4373f3ce | 13364 | { |
d719cbc7 | 13365 | int estimate; |
e07be5d2 CL |
13366 | |
13367 | if ((a & 0xc0000000) == 0) { | |
13368 | return 0xffffffff; | |
13369 | } | |
13370 | ||
d719cbc7 | 13371 | estimate = do_recip_sqrt_estimate(extract32(a, 23, 9)); |
e07be5d2 | 13372 | |
d719cbc7 | 13373 | return deposit32(0, 23, 9, estimate); |
4373f3ce | 13374 | } |
fe1479c3 | 13375 | |
da97f52c PM |
13376 | /* VFPv4 fused multiply-accumulate */ |
13377 | float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp) | |
13378 | { | |
13379 | float_status *fpst = fpstp; | |
13380 | return float32_muladd(a, b, c, 0, fpst); | |
13381 | } | |
13382 | ||
13383 | float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) | |
13384 | { | |
13385 | float_status *fpst = fpstp; | |
13386 | return float64_muladd(a, b, c, 0, fpst); | |
13387 | } | |
d9b0848d PM |
13388 | |
13389 | /* ARMv8 round to integral */ | |
13390 | float32 HELPER(rints_exact)(float32 x, void *fp_status) | |
13391 | { | |
13392 | return float32_round_to_int(x, fp_status); | |
13393 | } | |
13394 | ||
13395 | float64 HELPER(rintd_exact)(float64 x, void *fp_status) | |
13396 | { | |
13397 | return float64_round_to_int(x, fp_status); | |
13398 | } | |
13399 | ||
13400 | float32 HELPER(rints)(float32 x, void *fp_status) | |
13401 | { | |
13402 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
13403 | float32 ret; | |
13404 | ||
13405 | ret = float32_round_to_int(x, fp_status); | |
13406 | ||
13407 | /* Suppress any inexact exceptions the conversion produced */ | |
13408 | if (!(old_flags & float_flag_inexact)) { | |
13409 | new_flags = get_float_exception_flags(fp_status); | |
13410 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
13411 | } | |
13412 | ||
13413 | return ret; | |
13414 | } | |
13415 | ||
13416 | float64 HELPER(rintd)(float64 x, void *fp_status) | |
13417 | { | |
13418 | int old_flags = get_float_exception_flags(fp_status), new_flags; | |
13419 | float64 ret; | |
13420 | ||
13421 | ret = float64_round_to_int(x, fp_status); | |
13422 | ||
13423 | new_flags = get_float_exception_flags(fp_status); | |
13424 | ||
13425 | /* Suppress any inexact exceptions the conversion produced */ | |
13426 | if (!(old_flags & float_flag_inexact)) { | |
13427 | new_flags = get_float_exception_flags(fp_status); | |
13428 | set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); | |
13429 | } | |
13430 | ||
13431 | return ret; | |
13432 | } | |
9972da66 WN |
13433 | |
13434 | /* Convert ARM rounding mode to softfloat */ | |
13435 | int arm_rmode_to_sf(int rmode) | |
13436 | { | |
13437 | switch (rmode) { | |
13438 | case FPROUNDING_TIEAWAY: | |
13439 | rmode = float_round_ties_away; | |
13440 | break; | |
13441 | case FPROUNDING_ODD: | |
13442 | /* FIXME: add support for TIEAWAY and ODD */ | |
13443 | qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n", | |
13444 | rmode); | |
edd7541b | 13445 | /* fall through for now */ |
9972da66 WN |
13446 | case FPROUNDING_TIEEVEN: |
13447 | default: | |
13448 | rmode = float_round_nearest_even; | |
13449 | break; | |
13450 | case FPROUNDING_POSINF: | |
13451 | rmode = float_round_up; | |
13452 | break; | |
13453 | case FPROUNDING_NEGINF: | |
13454 | rmode = float_round_down; | |
13455 | break; | |
13456 | case FPROUNDING_ZERO: | |
13457 | rmode = float_round_to_zero; | |
13458 | break; | |
13459 | } | |
13460 | return rmode; | |
13461 | } | |
eb0ecd5a | 13462 | |
aa633469 PM |
13463 | /* CRC helpers. |
13464 | * The upper bytes of val (above the number specified by 'bytes') must have | |
13465 | * been zeroed out by the caller. | |
13466 | */ | |
eb0ecd5a WN |
13467 | uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) |
13468 | { | |
13469 | uint8_t buf[4]; | |
13470 | ||
aa633469 | 13471 | stl_le_p(buf, val); |
eb0ecd5a WN |
13472 | |
13473 | /* zlib crc32 converts the accumulator and output to one's complement. */ | |
13474 | return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | |
13475 | } | |
13476 | ||
13477 | uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | |
13478 | { | |
13479 | uint8_t buf[4]; | |
13480 | ||
aa633469 | 13481 | stl_le_p(buf, val); |
eb0ecd5a WN |
13482 | |
13483 | /* Linux crc32c converts the output to one's complement. */ | |
13484 | return crc32c(acc, buf, bytes) ^ 0xffffffff; | |
13485 | } | |
a9e01311 RH |
13486 | |
13487 | /* Return the exception level to which FP-disabled exceptions should | |
13488 | * be taken, or 0 if FP is enabled. | |
13489 | */ | |
ced31551 | 13490 | int fp_exception_el(CPUARMState *env, int cur_el) |
a9e01311 | 13491 | { |
55faa212 | 13492 | #ifndef CONFIG_USER_ONLY |
a9e01311 | 13493 | int fpen; |
a9e01311 RH |
13494 | |
13495 | /* CPACR and the CPTR registers don't exist before v6, so FP is | |
13496 | * always accessible | |
13497 | */ | |
13498 | if (!arm_feature(env, ARM_FEATURE_V6)) { | |
13499 | return 0; | |
13500 | } | |
13501 | ||
13502 | /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: | |
13503 | * 0, 2 : trap EL0 and EL1/PL1 accesses | |
13504 | * 1 : trap only EL0 accesses | |
13505 | * 3 : trap no accesses | |
13506 | */ | |
13507 | fpen = extract32(env->cp15.cpacr_el1, 20, 2); | |
13508 | switch (fpen) { | |
13509 | case 0: | |
13510 | case 2: | |
13511 | if (cur_el == 0 || cur_el == 1) { | |
13512 | /* Trap to PL1, which might be EL1 or EL3 */ | |
13513 | if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { | |
13514 | return 3; | |
13515 | } | |
13516 | return 1; | |
13517 | } | |
13518 | if (cur_el == 3 && !is_a64(env)) { | |
13519 | /* Secure PL1 running at EL3 */ | |
13520 | return 3; | |
13521 | } | |
13522 | break; | |
13523 | case 1: | |
13524 | if (cur_el == 0) { | |
13525 | return 1; | |
13526 | } | |
13527 | break; | |
13528 | case 3: | |
13529 | break; | |
13530 | } | |
13531 | ||
13532 | /* For the CPTR registers we don't need to guard with an ARM_FEATURE | |
13533 | * check because zero bits in the registers mean "don't trap". | |
13534 | */ | |
13535 | ||
13536 | /* CPTR_EL2 : present in v7VE or v8 */ | |
13537 | if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1) | |
13538 | && !arm_is_secure_below_el3(env)) { | |
13539 | /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ | |
13540 | return 2; | |
13541 | } | |
13542 | ||
13543 | /* CPTR_EL3 : present in v8 */ | |
13544 | if (extract32(env->cp15.cptr_el[3], 10, 1)) { | |
13545 | /* Trap all FP ops to EL3 */ | |
13546 | return 3; | |
13547 | } | |
55faa212 | 13548 | #endif |
a9e01311 RH |
13549 | return 0; |
13550 | } | |
13551 | ||
65e4655c RH |
13552 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, |
13553 | bool secstate, bool priv) | |
13554 | { | |
13555 | ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; | |
13556 | ||
13557 | if (priv) { | |
13558 | mmu_idx |= ARM_MMU_IDX_M_PRIV; | |
13559 | } | |
13560 | ||
13561 | if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { | |
13562 | mmu_idx |= ARM_MMU_IDX_M_NEGPRI; | |
13563 | } | |
13564 | ||
13565 | if (secstate) { | |
13566 | mmu_idx |= ARM_MMU_IDX_M_S; | |
13567 | } | |
13568 | ||
13569 | return mmu_idx; | |
13570 | } | |
13571 | ||
13572 | /* Return the MMU index for a v7M CPU in the specified security state */ | |
13573 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | |
13574 | { | |
13575 | bool priv = arm_current_el(env) != 0; | |
13576 | ||
13577 | return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); | |
13578 | } | |
13579 | ||
50494a27 | 13580 | ARMMMUIdx arm_mmu_idx(CPUARMState *env) |
65e4655c | 13581 | { |
50494a27 | 13582 | int el; |
65e4655c RH |
13583 | |
13584 | if (arm_feature(env, ARM_FEATURE_M)) { | |
50494a27 | 13585 | return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); |
65e4655c RH |
13586 | } |
13587 | ||
50494a27 | 13588 | el = arm_current_el(env); |
65e4655c | 13589 | if (el < 2 && arm_is_secure_below_el3(env)) { |
50494a27 RH |
13590 | return ARMMMUIdx_S1SE0 + el; |
13591 | } else { | |
13592 | return ARMMMUIdx_S12NSE0 + el; | |
65e4655c | 13593 | } |
50494a27 RH |
13594 | } |
13595 | ||
13596 | int cpu_mmu_index(CPUARMState *env, bool ifetch) | |
13597 | { | |
13598 | return arm_to_core_mmu_idx(arm_mmu_idx(env)); | |
65e4655c RH |
13599 | } |
13600 | ||
64be86ab RH |
13601 | #ifndef CONFIG_USER_ONLY |
13602 | ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) | |
13603 | { | |
13604 | return stage_1_mmu_idx(arm_mmu_idx(env)); | |
13605 | } | |
13606 | #endif | |
13607 | ||
a9e01311 | 13608 | void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, |
b9adaa70 | 13609 | target_ulong *cs_base, uint32_t *pflags) |
a9e01311 | 13610 | { |
50494a27 | 13611 | ARMMMUIdx mmu_idx = arm_mmu_idx(env); |
2de7ace2 RH |
13612 | int current_el = arm_current_el(env); |
13613 | int fp_el = fp_exception_el(env, current_el); | |
aad821ac | 13614 | uint32_t flags = 0; |
b9adaa70 | 13615 | |
a9e01311 | 13616 | if (is_a64(env)) { |
cd208a1c RH |
13617 | ARMCPU *cpu = arm_env_get_cpu(env); |
13618 | ||
a9e01311 | 13619 | *pc = env->pc; |
aad821ac | 13620 | flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); |
5d8634f5 RH |
13621 | |
13622 | #ifndef CONFIG_USER_ONLY | |
13623 | /* | |
13624 | * Get control bits for tagged addresses. Note that the | |
13625 | * translator only uses this for instruction addresses. | |
13626 | */ | |
13627 | { | |
13628 | ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); | |
13629 | ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); | |
13630 | int tbii, tbid; | |
13631 | ||
13632 | /* FIXME: ARMv8.1-VHE S2 translation regime. */ | |
13633 | if (regime_el(env, stage1) < 2) { | |
13634 | ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); | |
13635 | tbid = (p1.tbi << 1) | p0.tbi; | |
13636 | tbii = tbid & ~((p1.tbid << 1) | p0.tbid); | |
13637 | } else { | |
13638 | tbid = p0.tbi; | |
13639 | tbii = tbid & !p0.tbid; | |
13640 | } | |
13641 | ||
13642 | flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); | |
13643 | } | |
13644 | #endif | |
1db5e96c | 13645 | |
cd208a1c | 13646 | if (cpu_isar_feature(aa64_sve, cpu)) { |
2de7ace2 | 13647 | int sve_el = sve_exception_el(env, current_el); |
e79b445d | 13648 | uint32_t zcr_len; |
1db5e96c | 13649 | |
e79b445d RH |
13650 | /* If SVE is disabled, but FP is enabled, |
13651 | * then the effective len is 0. | |
13652 | */ | |
13653 | if (sve_el != 0 && fp_el == 0) { | |
13654 | zcr_len = 0; | |
13655 | } else { | |
0ab5953b | 13656 | zcr_len = sve_zcr_len_for_el(env, current_el); |
1db5e96c | 13657 | } |
aad821ac RH |
13658 | flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); |
13659 | flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); | |
1db5e96c | 13660 | } |
0816ef1b RH |
13661 | |
13662 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
13663 | /* | |
13664 | * In order to save space in flags, we record only whether | |
13665 | * pauth is "inactive", meaning all insns are implemented as | |
13666 | * a nop, or "active" when some action must be performed. | |
13667 | * The decision of which action to take is left to a helper. | |
13668 | */ | |
13669 | uint64_t sctlr; | |
13670 | if (current_el == 0) { | |
13671 | /* FIXME: ARMv8.1-VHE S2 translation regime. */ | |
13672 | sctlr = env->cp15.sctlr_el[1]; | |
13673 | } else { | |
13674 | sctlr = env->cp15.sctlr_el[current_el]; | |
13675 | } | |
13676 | if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { | |
13677 | flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); | |
13678 | } | |
13679 | } | |
a9e01311 RH |
13680 | } else { |
13681 | *pc = env->regs[15]; | |
aad821ac RH |
13682 | flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); |
13683 | flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); | |
13684 | flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); | |
13685 | flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); | |
13686 | flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); | |
13687 | flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); | |
a9e01311 RH |
13688 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) |
13689 | || arm_el_is_aa64(env, 1)) { | |
aad821ac | 13690 | flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); |
a9e01311 | 13691 | } |
aad821ac | 13692 | flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); |
a9e01311 RH |
13693 | } |
13694 | ||
aad821ac | 13695 | flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); |
a9e01311 RH |
13696 | |
13697 | /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine | |
13698 | * states defined in the ARM ARM for software singlestep: | |
13699 | * SS_ACTIVE PSTATE.SS State | |
13700 | * 0 x Inactive (the TB flag for SS is always 0) | |
13701 | * 1 0 Active-pending | |
13702 | * 1 1 Active-not-pending | |
13703 | */ | |
13704 | if (arm_singlestep_active(env)) { | |
aad821ac | 13705 | flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); |
a9e01311 RH |
13706 | if (is_a64(env)) { |
13707 | if (env->pstate & PSTATE_SS) { | |
aad821ac | 13708 | flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); |
a9e01311 RH |
13709 | } |
13710 | } else { | |
13711 | if (env->uncached_cpsr & PSTATE_SS) { | |
aad821ac | 13712 | flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); |
a9e01311 RH |
13713 | } |
13714 | } | |
13715 | } | |
13716 | if (arm_cpu_data_is_big_endian(env)) { | |
aad821ac | 13717 | flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); |
a9e01311 | 13718 | } |
aad821ac | 13719 | flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); |
a9e01311 RH |
13720 | |
13721 | if (arm_v7m_is_handler_mode(env)) { | |
aad821ac | 13722 | flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); |
a9e01311 RH |
13723 | } |
13724 | ||
4730fb85 PM |
13725 | /* v8M always applies stack limit checks unless CCR.STKOFHFNMIGN is |
13726 | * suppressing them because the requested execution priority is less than 0. | |
13727 | */ | |
13728 | if (arm_feature(env, ARM_FEATURE_V8) && | |
13729 | arm_feature(env, ARM_FEATURE_M) && | |
13730 | !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && | |
13731 | (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { | |
aad821ac | 13732 | flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); |
4730fb85 PM |
13733 | } |
13734 | ||
b9adaa70 | 13735 | *pflags = flags; |
a9e01311 RH |
13736 | *cs_base = 0; |
13737 | } | |
0ab5953b RH |
13738 | |
13739 | #ifdef TARGET_AARCH64 | |
13740 | /* | |
13741 | * The manual says that when SVE is enabled and VQ is widened the | |
13742 | * implementation is allowed to zero the previously inaccessible | |
13743 | * portion of the registers. The corollary to that is that when | |
13744 | * SVE is enabled and VQ is narrowed we are also allowed to zero | |
13745 | * the now inaccessible portion of the registers. | |
13746 | * | |
13747 | * The intent of this is that no predicate bit beyond VQ is ever set. | |
13748 | * Which means that some operations on predicate registers themselves | |
13749 | * may operate on full uint64_t or even unrolled across the maximum | |
13750 | * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally | |
13751 | * may well be cheaper than conditionals to restrict the operation | |
13752 | * to the relevant portion of a uint16_t[16]. | |
13753 | */ | |
13754 | void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) | |
13755 | { | |
13756 | int i, j; | |
13757 | uint64_t pmask; | |
13758 | ||
13759 | assert(vq >= 1 && vq <= ARM_MAX_VQ); | |
13760 | assert(vq <= arm_env_get_cpu(env)->sve_max_vq); | |
13761 | ||
13762 | /* Zap the high bits of the zregs. */ | |
13763 | for (i = 0; i < 32; i++) { | |
13764 | memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)); | |
13765 | } | |
13766 | ||
13767 | /* Zap the high bits of the pregs and ffr. */ | |
13768 | pmask = 0; | |
13769 | if (vq & 3) { | |
13770 | pmask = ~(-1ULL << (16 * (vq & 3))); | |
13771 | } | |
13772 | for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) { | |
13773 | for (i = 0; i < 17; ++i) { | |
13774 | env->vfp.pregs[i].p[j] &= pmask; | |
13775 | } | |
13776 | pmask = 0; | |
13777 | } | |
13778 | } | |
13779 | ||
13780 | /* | |
13781 | * Notice a change in SVE vector size when changing EL. | |
13782 | */ | |
9a05f7b6 RH |
13783 | void aarch64_sve_change_el(CPUARMState *env, int old_el, |
13784 | int new_el, bool el0_a64) | |
0ab5953b | 13785 | { |
cd208a1c | 13786 | ARMCPU *cpu = arm_env_get_cpu(env); |
0ab5953b | 13787 | int old_len, new_len; |
9a05f7b6 | 13788 | bool old_a64, new_a64; |
0ab5953b RH |
13789 | |
13790 | /* Nothing to do if no SVE. */ | |
cd208a1c | 13791 | if (!cpu_isar_feature(aa64_sve, cpu)) { |
0ab5953b RH |
13792 | return; |
13793 | } | |
13794 | ||
13795 | /* Nothing to do if FP is disabled in either EL. */ | |
13796 | if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) { | |
13797 | return; | |
13798 | } | |
13799 | ||
13800 | /* | |
13801 | * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped | |
13802 | * at ELx, or not available because the EL is in AArch32 state, then | |
13803 | * for all purposes other than a direct read, the ZCR_ELx.LEN field | |
13804 | * has an effective value of 0". | |
13805 | * | |
13806 | * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0). | |
13807 | * If we ignore aa32 state, we would fail to see the vq4->vq0 transition | |
13808 | * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that | |
13809 | * we already have the correct register contents when encountering the | |
13810 | * vq0->vq0 transition between EL0->EL1. | |
13811 | */ | |
9a05f7b6 RH |
13812 | old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; |
13813 | old_len = (old_a64 && !sve_exception_el(env, old_el) | |
0ab5953b | 13814 | ? sve_zcr_len_for_el(env, old_el) : 0); |
9a05f7b6 RH |
13815 | new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; |
13816 | new_len = (new_a64 && !sve_exception_el(env, new_el) | |
0ab5953b RH |
13817 | ? sve_zcr_len_for_el(env, new_el) : 0); |
13818 | ||
13819 | /* When changing vector length, clear inaccessible state. */ | |
13820 | if (new_len < old_len) { | |
13821 | aarch64_sve_narrow_vq(env, new_len + 1); | |
13822 | } | |
13823 | } | |
13824 | #endif |