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Commit | Line | Data |
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ed3baad1 PMD |
1 | /* |
2 | * ARM generic helpers. | |
3 | * | |
4 | * This code is licensed under the GNU GPL v2 or later. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0-or-later | |
7 | */ | |
db725815 | 8 | |
74c21bd0 | 9 | #include "qemu/osdep.h" |
63159601 | 10 | #include "qemu/units.h" |
181962fd | 11 | #include "target/arm/idau.h" |
194cbc49 | 12 | #include "trace.h" |
b5ff1b31 | 13 | #include "cpu.h" |
ccd38087 | 14 | #include "internals.h" |
022c62cb | 15 | #include "exec/gdbstub.h" |
2ef6175a | 16 | #include "exec/helper-proto.h" |
1de7afc9 | 17 | #include "qemu/host-utils.h" |
db725815 | 18 | #include "qemu/main-loop.h" |
1de7afc9 | 19 | #include "qemu/bitops.h" |
eb0ecd5a | 20 | #include "qemu/crc32c.h" |
0442428a | 21 | #include "qemu/qemu-print.h" |
63c91552 | 22 | #include "exec/exec-all.h" |
eb0ecd5a | 23 | #include <zlib.h> /* For crc32 */ |
64552b6b | 24 | #include "hw/irq.h" |
f1672e6f | 25 | #include "hw/semihosting/semihost.h" |
b2e23725 | 26 | #include "sysemu/cpus.h" |
f3a9b694 | 27 | #include "sysemu/kvm.h" |
9d2b5a58 | 28 | #include "qemu/range.h" |
7f7b4e7a | 29 | #include "qapi/qapi-commands-machine-target.h" |
de390645 RH |
30 | #include "qapi/error.h" |
31 | #include "qemu/guest-random.h" | |
91f78c58 PMD |
32 | #ifdef CONFIG_TCG |
33 | #include "arm_ldst.h" | |
7aab5a8c | 34 | #include "exec/cpu_ldst.h" |
91f78c58 | 35 | #endif |
0b03bdfc | 36 | |
352c98e5 LV |
37 | #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ |
38 | ||
4a501606 | 39 | #ifndef CONFIG_USER_ONLY |
7c2cb42b | 40 | |
37785977 | 41 | static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
03ae85f8 | 42 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
37785977 | 43 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, |
da909b2c | 44 | target_ulong *page_size_ptr, |
5b2d261d | 45 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); |
4a501606 PM |
46 | #endif |
47 | ||
affdb64d PM |
48 | static void switch_mode(CPUARMState *env, int mode); |
49 | ||
0ecb72a5 | 50 | static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
51 | { |
52 | int nregs; | |
53 | ||
54 | /* VFP data registers are always little-endian. */ | |
55 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
56 | if (reg < nregs) { | |
9a2b5256 | 57 | stq_le_p(buf, *aa32_vfp_dreg(env, reg)); |
56aebc89 PB |
58 | return 8; |
59 | } | |
60 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
61 | /* Aliases for Q regs. */ | |
62 | nregs += 16; | |
63 | if (reg < nregs) { | |
9a2b5256 RH |
64 | uint64_t *q = aa32_vfp_qreg(env, reg - 32); |
65 | stq_le_p(buf, q[0]); | |
66 | stq_le_p(buf + 8, q[1]); | |
56aebc89 PB |
67 | return 16; |
68 | } | |
69 | } | |
70 | switch (reg - nregs) { | |
71 | case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; | |
b0a909a4 | 72 | case 1: stl_p(buf, vfp_get_fpscr(env)); return 4; |
56aebc89 PB |
73 | case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; |
74 | } | |
75 | return 0; | |
76 | } | |
77 | ||
0ecb72a5 | 78 | static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) |
56aebc89 PB |
79 | { |
80 | int nregs; | |
81 | ||
82 | nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; | |
83 | if (reg < nregs) { | |
9a2b5256 | 84 | *aa32_vfp_dreg(env, reg) = ldq_le_p(buf); |
56aebc89 PB |
85 | return 8; |
86 | } | |
87 | if (arm_feature(env, ARM_FEATURE_NEON)) { | |
88 | nregs += 16; | |
89 | if (reg < nregs) { | |
9a2b5256 RH |
90 | uint64_t *q = aa32_vfp_qreg(env, reg - 32); |
91 | q[0] = ldq_le_p(buf); | |
92 | q[1] = ldq_le_p(buf + 8); | |
56aebc89 PB |
93 | return 16; |
94 | } | |
95 | } | |
96 | switch (reg - nregs) { | |
97 | case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; | |
b0a909a4 | 98 | case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4; |
71b3c3de | 99 | case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
56aebc89 PB |
100 | } |
101 | return 0; | |
102 | } | |
103 | ||
6a669427 PM |
104 | static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) |
105 | { | |
106 | switch (reg) { | |
107 | case 0 ... 31: | |
108 | /* 128 bit FP register */ | |
9a2b5256 RH |
109 | { |
110 | uint64_t *q = aa64_vfp_qreg(env, reg); | |
111 | stq_le_p(buf, q[0]); | |
112 | stq_le_p(buf + 8, q[1]); | |
113 | return 16; | |
114 | } | |
6a669427 PM |
115 | case 32: |
116 | /* FPSR */ | |
117 | stl_p(buf, vfp_get_fpsr(env)); | |
118 | return 4; | |
119 | case 33: | |
120 | /* FPCR */ | |
121 | stl_p(buf, vfp_get_fpcr(env)); | |
122 | return 4; | |
123 | default: | |
124 | return 0; | |
125 | } | |
126 | } | |
127 | ||
128 | static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) | |
129 | { | |
130 | switch (reg) { | |
131 | case 0 ... 31: | |
132 | /* 128 bit FP register */ | |
9a2b5256 RH |
133 | { |
134 | uint64_t *q = aa64_vfp_qreg(env, reg); | |
135 | q[0] = ldq_le_p(buf); | |
136 | q[1] = ldq_le_p(buf + 8); | |
137 | return 16; | |
138 | } | |
6a669427 PM |
139 | case 32: |
140 | /* FPSR */ | |
141 | vfp_set_fpsr(env, ldl_p(buf)); | |
142 | return 4; | |
143 | case 33: | |
144 | /* FPCR */ | |
145 | vfp_set_fpcr(env, ldl_p(buf)); | |
146 | return 4; | |
147 | default: | |
148 | return 0; | |
149 | } | |
150 | } | |
151 | ||
c4241c7d | 152 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) |
d4e6df63 | 153 | { |
375421cc | 154 | assert(ri->fieldoffset); |
67ed771d | 155 | if (cpreg_field_is_64bit(ri)) { |
c4241c7d | 156 | return CPREG_FIELD64(env, ri); |
22d9e1a9 | 157 | } else { |
c4241c7d | 158 | return CPREG_FIELD32(env, ri); |
22d9e1a9 | 159 | } |
d4e6df63 PM |
160 | } |
161 | ||
c4241c7d PM |
162 | static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
163 | uint64_t value) | |
d4e6df63 | 164 | { |
375421cc | 165 | assert(ri->fieldoffset); |
67ed771d | 166 | if (cpreg_field_is_64bit(ri)) { |
22d9e1a9 PM |
167 | CPREG_FIELD64(env, ri) = value; |
168 | } else { | |
169 | CPREG_FIELD32(env, ri) = value; | |
170 | } | |
d4e6df63 PM |
171 | } |
172 | ||
11f136ee FA |
173 | static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) |
174 | { | |
175 | return (char *)env + ri->fieldoffset; | |
176 | } | |
177 | ||
49a66191 | 178 | uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) |
721fae12 | 179 | { |
59a1c327 | 180 | /* Raw read of a coprocessor register (as needed for migration, etc). */ |
721fae12 | 181 | if (ri->type & ARM_CP_CONST) { |
59a1c327 | 182 | return ri->resetvalue; |
721fae12 | 183 | } else if (ri->raw_readfn) { |
59a1c327 | 184 | return ri->raw_readfn(env, ri); |
721fae12 | 185 | } else if (ri->readfn) { |
59a1c327 | 186 | return ri->readfn(env, ri); |
721fae12 | 187 | } else { |
59a1c327 | 188 | return raw_read(env, ri); |
721fae12 | 189 | } |
721fae12 PM |
190 | } |
191 | ||
59a1c327 | 192 | static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, |
7900e9f1 | 193 | uint64_t v) |
721fae12 PM |
194 | { |
195 | /* Raw write of a coprocessor register (as needed for migration, etc). | |
721fae12 PM |
196 | * Note that constant registers are treated as write-ignored; the |
197 | * caller should check for success by whether a readback gives the | |
198 | * value written. | |
199 | */ | |
200 | if (ri->type & ARM_CP_CONST) { | |
59a1c327 | 201 | return; |
721fae12 | 202 | } else if (ri->raw_writefn) { |
c4241c7d | 203 | ri->raw_writefn(env, ri, v); |
721fae12 | 204 | } else if (ri->writefn) { |
c4241c7d | 205 | ri->writefn(env, ri, v); |
721fae12 | 206 | } else { |
afb2530f | 207 | raw_write(env, ri, v); |
721fae12 | 208 | } |
721fae12 PM |
209 | } |
210 | ||
200bf5b7 AB |
211 | static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg) |
212 | { | |
2fc0cc0e | 213 | ARMCPU *cpu = env_archcpu(env); |
200bf5b7 AB |
214 | const ARMCPRegInfo *ri; |
215 | uint32_t key; | |
216 | ||
217 | key = cpu->dyn_xml.cpregs_keys[reg]; | |
218 | ri = get_arm_cp_reginfo(cpu->cp_regs, key); | |
219 | if (ri) { | |
220 | if (cpreg_field_is_64bit(ri)) { | |
221 | return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); | |
222 | } else { | |
223 | return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); | |
224 | } | |
225 | } | |
226 | return 0; | |
227 | } | |
228 | ||
229 | static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) | |
230 | { | |
231 | return 0; | |
232 | } | |
233 | ||
375421cc PM |
234 | static bool raw_accessors_invalid(const ARMCPRegInfo *ri) |
235 | { | |
236 | /* Return true if the regdef would cause an assertion if you called | |
237 | * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a | |
238 | * program bug for it not to have the NO_RAW flag). | |
239 | * NB that returning false here doesn't necessarily mean that calling | |
240 | * read/write_raw_cp_reg() is safe, because we can't distinguish "has | |
241 | * read/write access functions which are safe for raw use" from "has | |
242 | * read/write access functions which have side effects but has forgotten | |
243 | * to provide raw access functions". | |
244 | * The tests here line up with the conditions in read/write_raw_cp_reg() | |
245 | * and assertions in raw_read()/raw_write(). | |
246 | */ | |
247 | if ((ri->type & ARM_CP_CONST) || | |
248 | ri->fieldoffset || | |
249 | ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { | |
250 | return false; | |
251 | } | |
252 | return true; | |
253 | } | |
254 | ||
b698e4ee | 255 | bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync) |
721fae12 PM |
256 | { |
257 | /* Write the coprocessor state from cpu->env to the (index,value) list. */ | |
258 | int i; | |
259 | bool ok = true; | |
260 | ||
261 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
262 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
263 | const ARMCPRegInfo *ri; | |
b698e4ee | 264 | uint64_t newval; |
59a1c327 | 265 | |
60322b39 | 266 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
267 | if (!ri) { |
268 | ok = false; | |
269 | continue; | |
270 | } | |
7a0e58fa | 271 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
272 | continue; |
273 | } | |
b698e4ee PM |
274 | |
275 | newval = read_raw_cp_reg(&cpu->env, ri); | |
276 | if (kvm_sync) { | |
277 | /* | |
278 | * Only sync if the previous list->cpustate sync succeeded. | |
279 | * Rather than tracking the success/failure state for every | |
280 | * item in the list, we just recheck "does the raw write we must | |
281 | * have made in write_list_to_cpustate() read back OK" here. | |
282 | */ | |
283 | uint64_t oldval = cpu->cpreg_values[i]; | |
284 | ||
285 | if (oldval == newval) { | |
286 | continue; | |
287 | } | |
288 | ||
289 | write_raw_cp_reg(&cpu->env, ri, oldval); | |
290 | if (read_raw_cp_reg(&cpu->env, ri) != oldval) { | |
291 | continue; | |
292 | } | |
293 | ||
294 | write_raw_cp_reg(&cpu->env, ri, newval); | |
295 | } | |
296 | cpu->cpreg_values[i] = newval; | |
721fae12 PM |
297 | } |
298 | return ok; | |
299 | } | |
300 | ||
301 | bool write_list_to_cpustate(ARMCPU *cpu) | |
302 | { | |
303 | int i; | |
304 | bool ok = true; | |
305 | ||
306 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
307 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
308 | uint64_t v = cpu->cpreg_values[i]; | |
721fae12 PM |
309 | const ARMCPRegInfo *ri; |
310 | ||
60322b39 | 311 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
312 | if (!ri) { |
313 | ok = false; | |
314 | continue; | |
315 | } | |
7a0e58fa | 316 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
317 | continue; |
318 | } | |
319 | /* Write value and confirm it reads back as written | |
320 | * (to catch read-only registers and partially read-only | |
321 | * registers where the incoming migration value doesn't match) | |
322 | */ | |
59a1c327 PM |
323 | write_raw_cp_reg(&cpu->env, ri, v); |
324 | if (read_raw_cp_reg(&cpu->env, ri) != v) { | |
721fae12 PM |
325 | ok = false; |
326 | } | |
327 | } | |
328 | return ok; | |
329 | } | |
330 | ||
331 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | |
332 | { | |
333 | ARMCPU *cpu = opaque; | |
334 | uint64_t regidx; | |
335 | const ARMCPRegInfo *ri; | |
336 | ||
337 | regidx = *(uint32_t *)key; | |
60322b39 | 338 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 | 339 | |
7a0e58fa | 340 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
341 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); |
342 | /* The value array need not be initialized at this point */ | |
343 | cpu->cpreg_array_len++; | |
344 | } | |
345 | } | |
346 | ||
347 | static void count_cpreg(gpointer key, gpointer opaque) | |
348 | { | |
349 | ARMCPU *cpu = opaque; | |
350 | uint64_t regidx; | |
351 | const ARMCPRegInfo *ri; | |
352 | ||
353 | regidx = *(uint32_t *)key; | |
60322b39 | 354 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 | 355 | |
7a0e58fa | 356 | if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { |
721fae12 PM |
357 | cpu->cpreg_array_len++; |
358 | } | |
359 | } | |
360 | ||
361 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | |
362 | { | |
cbf239b7 AR |
363 | uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a); |
364 | uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b); | |
721fae12 | 365 | |
cbf239b7 AR |
366 | if (aidx > bidx) { |
367 | return 1; | |
368 | } | |
369 | if (aidx < bidx) { | |
370 | return -1; | |
371 | } | |
372 | return 0; | |
721fae12 PM |
373 | } |
374 | ||
375 | void init_cpreg_list(ARMCPU *cpu) | |
376 | { | |
377 | /* Initialise the cpreg_tuples[] array based on the cp_regs hash. | |
378 | * Note that we require cpreg_tuples[] to be sorted by key ID. | |
379 | */ | |
57b6d95e | 380 | GList *keys; |
721fae12 PM |
381 | int arraylen; |
382 | ||
57b6d95e | 383 | keys = g_hash_table_get_keys(cpu->cp_regs); |
721fae12 PM |
384 | keys = g_list_sort(keys, cpreg_key_compare); |
385 | ||
386 | cpu->cpreg_array_len = 0; | |
387 | ||
388 | g_list_foreach(keys, count_cpreg, cpu); | |
389 | ||
390 | arraylen = cpu->cpreg_array_len; | |
391 | cpu->cpreg_indexes = g_new(uint64_t, arraylen); | |
392 | cpu->cpreg_values = g_new(uint64_t, arraylen); | |
393 | cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); | |
394 | cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); | |
395 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; | |
396 | cpu->cpreg_array_len = 0; | |
397 | ||
398 | g_list_foreach(keys, add_cpreg_to_list, cpu); | |
399 | ||
400 | assert(cpu->cpreg_array_len == arraylen); | |
401 | ||
402 | g_list_free(keys); | |
403 | } | |
404 | ||
68e9c2fe EI |
405 | /* |
406 | * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but | |
407 | * they are accessible when EL3 is using AArch64 regardless of EL3.NS. | |
408 | * | |
409 | * access_el3_aa32ns: Used to check AArch32 register views. | |
410 | * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views. | |
411 | */ | |
412 | static CPAccessResult access_el3_aa32ns(CPUARMState *env, | |
3f208fd7 PM |
413 | const ARMCPRegInfo *ri, |
414 | bool isread) | |
68e9c2fe EI |
415 | { |
416 | bool secure = arm_is_secure_below_el3(env); | |
417 | ||
418 | assert(!arm_el_is_aa64(env, 3)); | |
419 | if (secure) { | |
420 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
421 | } | |
422 | return CP_ACCESS_OK; | |
423 | } | |
424 | ||
425 | static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env, | |
3f208fd7 PM |
426 | const ARMCPRegInfo *ri, |
427 | bool isread) | |
68e9c2fe EI |
428 | { |
429 | if (!arm_el_is_aa64(env, 3)) { | |
3f208fd7 | 430 | return access_el3_aa32ns(env, ri, isread); |
68e9c2fe EI |
431 | } |
432 | return CP_ACCESS_OK; | |
433 | } | |
434 | ||
5513c3ab PM |
435 | /* Some secure-only AArch32 registers trap to EL3 if used from |
436 | * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). | |
437 | * Note that an access from Secure EL1 can only happen if EL3 is AArch64. | |
438 | * We assume that the .access field is set to PL1_RW. | |
439 | */ | |
440 | static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, | |
3f208fd7 PM |
441 | const ARMCPRegInfo *ri, |
442 | bool isread) | |
5513c3ab PM |
443 | { |
444 | if (arm_current_el(env) == 3) { | |
445 | return CP_ACCESS_OK; | |
446 | } | |
447 | if (arm_is_secure_below_el3(env)) { | |
448 | return CP_ACCESS_TRAP_EL3; | |
449 | } | |
450 | /* This will be EL1 NS and EL2 NS, which just UNDEF */ | |
451 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
452 | } | |
453 | ||
187f678d PM |
454 | /* Check for traps to "powerdown debug" registers, which are controlled |
455 | * by MDCR.TDOSA | |
456 | */ | |
457 | static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, | |
458 | bool isread) | |
459 | { | |
460 | int el = arm_current_el(env); | |
30ac6339 PM |
461 | bool mdcr_el2_tdosa = (env->cp15.mdcr_el2 & MDCR_TDOSA) || |
462 | (env->cp15.mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 463 | (arm_hcr_el2_eff(env) & HCR_TGE); |
187f678d | 464 | |
30ac6339 | 465 | if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) { |
187f678d PM |
466 | return CP_ACCESS_TRAP_EL2; |
467 | } | |
468 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { | |
469 | return CP_ACCESS_TRAP_EL3; | |
470 | } | |
471 | return CP_ACCESS_OK; | |
472 | } | |
473 | ||
91b0a238 PM |
474 | /* Check for traps to "debug ROM" registers, which are controlled |
475 | * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. | |
476 | */ | |
477 | static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, | |
478 | bool isread) | |
479 | { | |
480 | int el = arm_current_el(env); | |
30ac6339 PM |
481 | bool mdcr_el2_tdra = (env->cp15.mdcr_el2 & MDCR_TDRA) || |
482 | (env->cp15.mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 483 | (arm_hcr_el2_eff(env) & HCR_TGE); |
91b0a238 | 484 | |
30ac6339 | 485 | if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) { |
91b0a238 PM |
486 | return CP_ACCESS_TRAP_EL2; |
487 | } | |
488 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
489 | return CP_ACCESS_TRAP_EL3; | |
490 | } | |
491 | return CP_ACCESS_OK; | |
492 | } | |
493 | ||
d6c8cf81 PM |
494 | /* Check for traps to general debug registers, which are controlled |
495 | * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. | |
496 | */ | |
497 | static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, | |
498 | bool isread) | |
499 | { | |
500 | int el = arm_current_el(env); | |
30ac6339 PM |
501 | bool mdcr_el2_tda = (env->cp15.mdcr_el2 & MDCR_TDA) || |
502 | (env->cp15.mdcr_el2 & MDCR_TDE) || | |
7c208e0f | 503 | (arm_hcr_el2_eff(env) & HCR_TGE); |
d6c8cf81 | 504 | |
30ac6339 | 505 | if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) { |
d6c8cf81 PM |
506 | return CP_ACCESS_TRAP_EL2; |
507 | } | |
508 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | |
509 | return CP_ACCESS_TRAP_EL3; | |
510 | } | |
511 | return CP_ACCESS_OK; | |
512 | } | |
513 | ||
1fce1ba9 PM |
514 | /* Check for traps to performance monitor registers, which are controlled |
515 | * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. | |
516 | */ | |
517 | static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, | |
518 | bool isread) | |
519 | { | |
520 | int el = arm_current_el(env); | |
521 | ||
522 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) | |
523 | && !arm_is_secure_below_el3(env)) { | |
524 | return CP_ACCESS_TRAP_EL2; | |
525 | } | |
526 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
527 | return CP_ACCESS_TRAP_EL3; | |
528 | } | |
529 | return CP_ACCESS_OK; | |
530 | } | |
531 | ||
c4241c7d | 532 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
c983fe6c | 533 | { |
2fc0cc0e | 534 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 535 | |
8d5c773e | 536 | raw_write(env, ri, value); |
d10eb08f | 537 | tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ |
c983fe6c PM |
538 | } |
539 | ||
c4241c7d | 540 | static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
08de207b | 541 | { |
2fc0cc0e | 542 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 543 | |
8d5c773e | 544 | if (raw_read(env, ri) != value) { |
08de207b PM |
545 | /* Unlike real hardware the qemu TLB uses virtual addresses, |
546 | * not modified virtual addresses, so this causes a TLB flush. | |
547 | */ | |
d10eb08f | 548 | tlb_flush(CPU(cpu)); |
8d5c773e | 549 | raw_write(env, ri, value); |
08de207b | 550 | } |
08de207b | 551 | } |
c4241c7d PM |
552 | |
553 | static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
554 | uint64_t value) | |
08de207b | 555 | { |
2fc0cc0e | 556 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 557 | |
452a0955 | 558 | if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) |
014406b5 | 559 | && !extended_addresses_enabled(env)) { |
08de207b PM |
560 | /* For VMSA (when not using the LPAE long descriptor page table |
561 | * format) this register includes the ASID, so do a TLB flush. | |
562 | * For PMSA it is purely a process ID and no action is needed. | |
563 | */ | |
d10eb08f | 564 | tlb_flush(CPU(cpu)); |
08de207b | 565 | } |
8d5c773e | 566 | raw_write(env, ri, value); |
08de207b PM |
567 | } |
568 | ||
b4ab8ce9 PM |
569 | /* IS variants of TLB operations must affect all cores */ |
570 | static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
571 | uint64_t value) | |
572 | { | |
29a0af61 | 573 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
574 | |
575 | tlb_flush_all_cpus_synced(cs); | |
576 | } | |
577 | ||
578 | static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
579 | uint64_t value) | |
580 | { | |
29a0af61 | 581 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
582 | |
583 | tlb_flush_all_cpus_synced(cs); | |
584 | } | |
585 | ||
586 | static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
587 | uint64_t value) | |
588 | { | |
29a0af61 | 589 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
590 | |
591 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
592 | } | |
593 | ||
594 | static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
595 | uint64_t value) | |
596 | { | |
29a0af61 | 597 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
598 | |
599 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
600 | } | |
601 | ||
602 | /* | |
603 | * Non-IS variants of TLB operations are upgraded to | |
604 | * IS versions if we are at NS EL1 and HCR_EL2.FB is set to | |
605 | * force broadcast of these operations. | |
606 | */ | |
607 | static bool tlb_force_broadcast(CPUARMState *env) | |
608 | { | |
609 | return (env->cp15.hcr_el2 & HCR_FB) && | |
610 | arm_current_el(env) == 1 && arm_is_secure_below_el3(env); | |
611 | } | |
612 | ||
c4241c7d PM |
613 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
614 | uint64_t value) | |
d929823f PM |
615 | { |
616 | /* Invalidate all (TLBIALL) */ | |
2fc0cc0e | 617 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 618 | |
b4ab8ce9 PM |
619 | if (tlb_force_broadcast(env)) { |
620 | tlbiall_is_write(env, NULL, value); | |
621 | return; | |
622 | } | |
623 | ||
d10eb08f | 624 | tlb_flush(CPU(cpu)); |
d929823f PM |
625 | } |
626 | ||
c4241c7d PM |
627 | static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
628 | uint64_t value) | |
d929823f PM |
629 | { |
630 | /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ | |
2fc0cc0e | 631 | ARMCPU *cpu = env_archcpu(env); |
31b030d4 | 632 | |
b4ab8ce9 PM |
633 | if (tlb_force_broadcast(env)) { |
634 | tlbimva_is_write(env, NULL, value); | |
635 | return; | |
636 | } | |
637 | ||
31b030d4 | 638 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); |
d929823f PM |
639 | } |
640 | ||
c4241c7d PM |
641 | static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
642 | uint64_t value) | |
d929823f PM |
643 | { |
644 | /* Invalidate by ASID (TLBIASID) */ | |
2fc0cc0e | 645 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 646 | |
b4ab8ce9 PM |
647 | if (tlb_force_broadcast(env)) { |
648 | tlbiasid_is_write(env, NULL, value); | |
649 | return; | |
650 | } | |
651 | ||
d10eb08f | 652 | tlb_flush(CPU(cpu)); |
d929823f PM |
653 | } |
654 | ||
c4241c7d PM |
655 | static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
656 | uint64_t value) | |
d929823f PM |
657 | { |
658 | /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ | |
2fc0cc0e | 659 | ARMCPU *cpu = env_archcpu(env); |
31b030d4 | 660 | |
b4ab8ce9 PM |
661 | if (tlb_force_broadcast(env)) { |
662 | tlbimvaa_is_write(env, NULL, value); | |
663 | return; | |
664 | } | |
fa439fc5 | 665 | |
b4ab8ce9 | 666 | tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK); |
fa439fc5 PM |
667 | } |
668 | ||
541ef8c2 SS |
669 | static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, |
670 | uint64_t value) | |
671 | { | |
29a0af61 | 672 | CPUState *cs = env_cpu(env); |
541ef8c2 | 673 | |
0336cbf8 | 674 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
675 | ARMMMUIdxBit_S12NSE1 | |
676 | ARMMMUIdxBit_S12NSE0 | | |
677 | ARMMMUIdxBit_S2NS); | |
541ef8c2 SS |
678 | } |
679 | ||
680 | static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
681 | uint64_t value) | |
682 | { | |
29a0af61 | 683 | CPUState *cs = env_cpu(env); |
541ef8c2 | 684 | |
a67cf277 | 685 | tlb_flush_by_mmuidx_all_cpus_synced(cs, |
8bd5c820 PM |
686 | ARMMMUIdxBit_S12NSE1 | |
687 | ARMMMUIdxBit_S12NSE0 | | |
688 | ARMMMUIdxBit_S2NS); | |
541ef8c2 SS |
689 | } |
690 | ||
691 | static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
692 | uint64_t value) | |
693 | { | |
694 | /* Invalidate by IPA. This has to invalidate any structures that | |
695 | * contain only stage 2 translation information, but does not need | |
696 | * to apply to structures that contain combined stage 1 and stage 2 | |
697 | * translation information. | |
698 | * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. | |
699 | */ | |
29a0af61 | 700 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
701 | uint64_t pageaddr; |
702 | ||
703 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
704 | return; | |
705 | } | |
706 | ||
707 | pageaddr = sextract64(value << 12, 0, 40); | |
708 | ||
8bd5c820 | 709 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); |
541ef8c2 SS |
710 | } |
711 | ||
712 | static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
713 | uint64_t value) | |
714 | { | |
29a0af61 | 715 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
716 | uint64_t pageaddr; |
717 | ||
718 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
719 | return; | |
720 | } | |
721 | ||
722 | pageaddr = sextract64(value << 12, 0, 40); | |
723 | ||
a67cf277 | 724 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 725 | ARMMMUIdxBit_S2NS); |
541ef8c2 SS |
726 | } |
727 | ||
728 | static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
729 | uint64_t value) | |
730 | { | |
29a0af61 | 731 | CPUState *cs = env_cpu(env); |
541ef8c2 | 732 | |
8bd5c820 | 733 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
734 | } |
735 | ||
736 | static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
737 | uint64_t value) | |
738 | { | |
29a0af61 | 739 | CPUState *cs = env_cpu(env); |
541ef8c2 | 740 | |
8bd5c820 | 741 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
742 | } |
743 | ||
744 | static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
745 | uint64_t value) | |
746 | { | |
29a0af61 | 747 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
748 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
749 | ||
8bd5c820 | 750 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
751 | } |
752 | ||
753 | static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
754 | uint64_t value) | |
755 | { | |
29a0af61 | 756 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
757 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
758 | ||
a67cf277 | 759 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 760 | ARMMMUIdxBit_S1E2); |
541ef8c2 SS |
761 | } |
762 | ||
e9aa6c21 | 763 | static const ARMCPRegInfo cp_reginfo[] = { |
54bf36ed FA |
764 | /* Define the secure and non-secure FCSE identifier CP registers |
765 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
766 | * the secure register to be properly reset and migrated. There is also no | |
767 | * v8 EL1 version of the register so the non-secure instance stands alone. | |
768 | */ | |
9c513e78 | 769 | { .name = "FCSEIDR", |
54bf36ed FA |
770 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
771 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, | |
772 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), | |
773 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, | |
9c513e78 | 774 | { .name = "FCSEIDR_S", |
54bf36ed FA |
775 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
776 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
777 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), | |
d4e6df63 | 778 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, |
54bf36ed FA |
779 | /* Define the secure and non-secure context identifier CP registers |
780 | * separately because there is no secure bank in V8 (no _EL3). This allows | |
781 | * the secure register to be properly reset and migrated. In the | |
782 | * non-secure case, the 32-bit register will have reset and migration | |
783 | * disabled during registration as it is handled by the 64-bit instance. | |
784 | */ | |
785 | { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
014406b5 | 786 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
54bf36ed FA |
787 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, |
788 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), | |
789 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, | |
9c513e78 | 790 | { .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32, |
54bf36ed FA |
791 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
792 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
793 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), | |
d4e6df63 | 794 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, |
9449fdf6 PM |
795 | REGINFO_SENTINEL |
796 | }; | |
797 | ||
798 | static const ARMCPRegInfo not_v8_cp_reginfo[] = { | |
799 | /* NB: Some of these registers exist in v8 but with more precise | |
800 | * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). | |
801 | */ | |
802 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
803 | { .name = "DACR", |
804 | .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, | |
805 | .access = PL1_RW, .resetvalue = 0, | |
806 | .writefn = dacr_write, .raw_writefn = raw_write, | |
807 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
808 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a903c449 EI |
809 | /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. |
810 | * For v6 and v5, these mappings are overly broad. | |
4fdd17dd | 811 | */ |
a903c449 EI |
812 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0, |
813 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
814 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1, | |
815 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
816 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4, | |
817 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
818 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8, | |
4fdd17dd | 819 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, |
c4804214 PM |
820 | /* Cache maintenance ops; some of this space may be overridden later. */ |
821 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | |
822 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | |
823 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | |
e9aa6c21 PM |
824 | REGINFO_SENTINEL |
825 | }; | |
826 | ||
7d57f408 PM |
827 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
828 | /* Not all pre-v6 cores implemented this WFI, so this is slightly | |
829 | * over-broad. | |
830 | */ | |
831 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | |
832 | .access = PL1_W, .type = ARM_CP_WFI }, | |
833 | REGINFO_SENTINEL | |
834 | }; | |
835 | ||
836 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | |
837 | /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which | |
838 | * is UNPREDICTABLE; we choose to NOP as most implementations do). | |
839 | */ | |
840 | { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
841 | .access = PL1_W, .type = ARM_CP_WFI }, | |
34f90529 PM |
842 | /* L1 cache lockdown. Not architectural in v6 and earlier but in practice |
843 | * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and | |
844 | * OMAPCP will override this space. | |
845 | */ | |
846 | { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, | |
847 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), | |
848 | .resetvalue = 0 }, | |
849 | { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, | |
850 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), | |
851 | .resetvalue = 0 }, | |
776d4e5c PM |
852 | /* v6 doesn't have the cache ID registers but Linux reads them anyway */ |
853 | { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, | |
7a0e58fa | 854 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 855 | .resetvalue = 0 }, |
50300698 PM |
856 | /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; |
857 | * implementing it as RAZ means the "debug architecture version" bits | |
858 | * will read as a reserved value, which should cause Linux to not try | |
859 | * to use the debug hardware. | |
860 | */ | |
861 | { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
862 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
995939a6 PM |
863 | /* MMU TLB control. Note that the wildcarding means we cover not just |
864 | * the unified TLB ops but also the dside/iside/inner-shareable variants. | |
865 | */ | |
866 | { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, | |
867 | .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, | |
7a0e58fa | 868 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
869 | { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, |
870 | .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, | |
7a0e58fa | 871 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
872 | { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, |
873 | .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, | |
7a0e58fa | 874 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
875 | { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, |
876 | .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, | |
7a0e58fa | 877 | .type = ARM_CP_NO_RAW }, |
a903c449 EI |
878 | { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2, |
879 | .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, | |
880 | { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, | |
881 | .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, | |
7d57f408 PM |
882 | REGINFO_SENTINEL |
883 | }; | |
884 | ||
c4241c7d PM |
885 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
886 | uint64_t value) | |
2771db27 | 887 | { |
f0aff255 FA |
888 | uint32_t mask = 0; |
889 | ||
890 | /* In ARMv8 most bits of CPACR_EL1 are RES0. */ | |
891 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
892 | /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. | |
893 | * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. | |
894 | * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. | |
895 | */ | |
896 | if (arm_feature(env, ARM_FEATURE_VFP)) { | |
897 | /* VFP coprocessor: cp10 & cp11 [23:20] */ | |
898 | mask |= (1 << 31) | (1 << 30) | (0xf << 20); | |
899 | ||
900 | if (!arm_feature(env, ARM_FEATURE_NEON)) { | |
901 | /* ASEDIS [31] bit is RAO/WI */ | |
902 | value |= (1 << 31); | |
903 | } | |
904 | ||
905 | /* VFPv3 and upwards with NEON implement 32 double precision | |
906 | * registers (D0-D31). | |
907 | */ | |
908 | if (!arm_feature(env, ARM_FEATURE_NEON) || | |
909 | !arm_feature(env, ARM_FEATURE_VFP3)) { | |
910 | /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ | |
911 | value |= (1 << 30); | |
912 | } | |
913 | } | |
914 | value &= mask; | |
2771db27 | 915 | } |
fc1120a7 PM |
916 | |
917 | /* | |
918 | * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 | |
919 | * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. | |
920 | */ | |
921 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
922 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
923 | value &= ~(0xf << 20); | |
924 | value |= env->cp15.cpacr_el1 & (0xf << 20); | |
925 | } | |
926 | ||
7ebd5f2e | 927 | env->cp15.cpacr_el1 = value; |
2771db27 PM |
928 | } |
929 | ||
fc1120a7 PM |
930 | static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
931 | { | |
932 | /* | |
933 | * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 | |
934 | * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. | |
935 | */ | |
936 | uint64_t value = env->cp15.cpacr_el1; | |
937 | ||
938 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
939 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
940 | value &= ~(0xf << 20); | |
941 | } | |
942 | return value; | |
943 | } | |
944 | ||
945 | ||
5deac39c PM |
946 | static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
947 | { | |
948 | /* Call cpacr_write() so that we reset with the correct RAO bits set | |
949 | * for our CPU features. | |
950 | */ | |
951 | cpacr_write(env, ri, 0); | |
952 | } | |
953 | ||
3f208fd7 PM |
954 | static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
955 | bool isread) | |
c6f19164 GB |
956 | { |
957 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
958 | /* Check if CPACR accesses are to be trapped to EL2 */ | |
959 | if (arm_current_el(env) == 1 && | |
960 | (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) { | |
961 | return CP_ACCESS_TRAP_EL2; | |
962 | /* Check if CPACR accesses are to be trapped to EL3 */ | |
963 | } else if (arm_current_el(env) < 3 && | |
964 | (env->cp15.cptr_el[3] & CPTR_TCPAC)) { | |
965 | return CP_ACCESS_TRAP_EL3; | |
966 | } | |
967 | } | |
968 | ||
969 | return CP_ACCESS_OK; | |
970 | } | |
971 | ||
3f208fd7 PM |
972 | static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
973 | bool isread) | |
c6f19164 GB |
974 | { |
975 | /* Check if CPTR accesses are set to trap to EL3 */ | |
976 | if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) { | |
977 | return CP_ACCESS_TRAP_EL3; | |
978 | } | |
979 | ||
980 | return CP_ACCESS_OK; | |
981 | } | |
982 | ||
7d57f408 PM |
983 | static const ARMCPRegInfo v6_cp_reginfo[] = { |
984 | /* prefetch by MVA in v6, NOP in v7 */ | |
985 | { .name = "MVA_prefetch", | |
986 | .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, | |
987 | .access = PL1_W, .type = ARM_CP_NOP }, | |
6df99dec SS |
988 | /* We need to break the TB after ISB to execute self-modifying code |
989 | * correctly and also to take any pending interrupts immediately. | |
990 | * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. | |
991 | */ | |
7d57f408 | 992 | { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, |
6df99dec | 993 | .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, |
091fd17c | 994 | { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
7d57f408 | 995 | .access = PL0_W, .type = ARM_CP_NOP }, |
091fd17c | 996 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
7d57f408 | 997 | .access = PL0_W, .type = ARM_CP_NOP }, |
06d76f31 | 998 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
6cd8a264 | 999 | .access = PL1_RW, |
b848ce2b FA |
1000 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), |
1001 | offsetof(CPUARMState, cp15.ifar_ns) }, | |
06d76f31 PM |
1002 | .resetvalue = 0, }, |
1003 | /* Watchpoint Fault Address Register : should actually only be present | |
1004 | * for 1136, 1176, 11MPCore. | |
1005 | */ | |
1006 | { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
1007 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, | |
34222fb8 | 1008 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, |
c6f19164 | 1009 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, |
7ebd5f2e | 1010 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), |
fc1120a7 | 1011 | .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read }, |
7d57f408 PM |
1012 | REGINFO_SENTINEL |
1013 | }; | |
1014 | ||
7ece99b1 AL |
1015 | /* Definitions for the PMU registers */ |
1016 | #define PMCRN_MASK 0xf800 | |
1017 | #define PMCRN_SHIFT 11 | |
f4efb4b2 | 1018 | #define PMCRLC 0x40 |
033614c4 | 1019 | #define PMCRDP 0x10 |
7ece99b1 AL |
1020 | #define PMCRD 0x8 |
1021 | #define PMCRC 0x4 | |
5ecdd3e4 | 1022 | #define PMCRP 0x2 |
7ece99b1 AL |
1023 | #define PMCRE 0x1 |
1024 | ||
033614c4 AL |
1025 | #define PMXEVTYPER_P 0x80000000 |
1026 | #define PMXEVTYPER_U 0x40000000 | |
1027 | #define PMXEVTYPER_NSK 0x20000000 | |
1028 | #define PMXEVTYPER_NSU 0x10000000 | |
1029 | #define PMXEVTYPER_NSH 0x08000000 | |
1030 | #define PMXEVTYPER_M 0x04000000 | |
1031 | #define PMXEVTYPER_MT 0x02000000 | |
1032 | #define PMXEVTYPER_EVTCOUNT 0x0000ffff | |
1033 | #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \ | |
1034 | PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ | |
1035 | PMXEVTYPER_M | PMXEVTYPER_MT | \ | |
1036 | PMXEVTYPER_EVTCOUNT) | |
1037 | ||
4b8afa1f AL |
1038 | #define PMCCFILTR 0xf8000000 |
1039 | #define PMCCFILTR_M PMXEVTYPER_M | |
1040 | #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) | |
1041 | ||
7ece99b1 AL |
1042 | static inline uint32_t pmu_num_counters(CPUARMState *env) |
1043 | { | |
1044 | return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; | |
1045 | } | |
1046 | ||
1047 | /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ | |
1048 | static inline uint64_t pmu_counter_mask(CPUARMState *env) | |
1049 | { | |
1050 | return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); | |
1051 | } | |
1052 | ||
57a4a11b AL |
1053 | typedef struct pm_event { |
1054 | uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ | |
1055 | /* If the event is supported on this CPU (used to generate PMCEID[01]) */ | |
1056 | bool (*supported)(CPUARMState *); | |
1057 | /* | |
1058 | * Retrieve the current count of the underlying event. The programmed | |
1059 | * counters hold a difference from the return value from this function | |
1060 | */ | |
1061 | uint64_t (*get_count)(CPUARMState *); | |
4e7beb0c AL |
1062 | /* |
1063 | * Return how many nanoseconds it will take (at a minimum) for count events | |
1064 | * to occur. A negative value indicates the counter will never overflow, or | |
1065 | * that the counter has otherwise arranged for the overflow bit to be set | |
1066 | * and the PMU interrupt to be raised on overflow. | |
1067 | */ | |
1068 | int64_t (*ns_per_count)(uint64_t); | |
57a4a11b AL |
1069 | } pm_event; |
1070 | ||
b2e23725 AL |
1071 | static bool event_always_supported(CPUARMState *env) |
1072 | { | |
1073 | return true; | |
1074 | } | |
1075 | ||
0d4bfd7d AL |
1076 | static uint64_t swinc_get_count(CPUARMState *env) |
1077 | { | |
1078 | /* | |
1079 | * SW_INCR events are written directly to the pmevcntr's by writes to | |
1080 | * PMSWINC, so there is no underlying count maintained by the PMU itself | |
1081 | */ | |
1082 | return 0; | |
1083 | } | |
1084 | ||
4e7beb0c AL |
1085 | static int64_t swinc_ns_per(uint64_t ignored) |
1086 | { | |
1087 | return -1; | |
1088 | } | |
1089 | ||
b2e23725 AL |
1090 | /* |
1091 | * Return the underlying cycle count for the PMU cycle counters. If we're in | |
1092 | * usermode, simply return 0. | |
1093 | */ | |
1094 | static uint64_t cycles_get_count(CPUARMState *env) | |
1095 | { | |
1096 | #ifndef CONFIG_USER_ONLY | |
1097 | return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
1098 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); | |
1099 | #else | |
1100 | return cpu_get_host_ticks(); | |
1101 | #endif | |
1102 | } | |
1103 | ||
1104 | #ifndef CONFIG_USER_ONLY | |
4e7beb0c AL |
1105 | static int64_t cycles_ns_per(uint64_t cycles) |
1106 | { | |
1107 | return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles; | |
1108 | } | |
1109 | ||
b2e23725 AL |
1110 | static bool instructions_supported(CPUARMState *env) |
1111 | { | |
1112 | return use_icount == 1 /* Precise instruction counting */; | |
1113 | } | |
1114 | ||
1115 | static uint64_t instructions_get_count(CPUARMState *env) | |
1116 | { | |
1117 | return (uint64_t)cpu_get_icount_raw(); | |
1118 | } | |
4e7beb0c AL |
1119 | |
1120 | static int64_t instructions_ns_per(uint64_t icount) | |
1121 | { | |
1122 | return cpu_icount_to_ns((int64_t)icount); | |
1123 | } | |
b2e23725 AL |
1124 | #endif |
1125 | ||
57a4a11b | 1126 | static const pm_event pm_events[] = { |
0d4bfd7d AL |
1127 | { .number = 0x000, /* SW_INCR */ |
1128 | .supported = event_always_supported, | |
1129 | .get_count = swinc_get_count, | |
4e7beb0c | 1130 | .ns_per_count = swinc_ns_per, |
0d4bfd7d | 1131 | }, |
b2e23725 AL |
1132 | #ifndef CONFIG_USER_ONLY |
1133 | { .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */ | |
1134 | .supported = instructions_supported, | |
1135 | .get_count = instructions_get_count, | |
4e7beb0c | 1136 | .ns_per_count = instructions_ns_per, |
b2e23725 AL |
1137 | }, |
1138 | { .number = 0x011, /* CPU_CYCLES, Cycle */ | |
1139 | .supported = event_always_supported, | |
1140 | .get_count = cycles_get_count, | |
4e7beb0c | 1141 | .ns_per_count = cycles_ns_per, |
b2e23725 AL |
1142 | } |
1143 | #endif | |
57a4a11b AL |
1144 | }; |
1145 | ||
1146 | /* | |
1147 | * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of | |
1148 | * events (i.e. the statistical profiling extension), this implementation | |
1149 | * should first be updated to something sparse instead of the current | |
1150 | * supported_event_map[] array. | |
1151 | */ | |
b2e23725 | 1152 | #define MAX_EVENT_ID 0x11 |
57a4a11b AL |
1153 | #define UNSUPPORTED_EVENT UINT16_MAX |
1154 | static uint16_t supported_event_map[MAX_EVENT_ID + 1]; | |
1155 | ||
1156 | /* | |
bf8d0969 AL |
1157 | * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map |
1158 | * of ARM event numbers to indices in our pm_events array. | |
57a4a11b AL |
1159 | * |
1160 | * Note: Events in the 0x40XX range are not currently supported. | |
1161 | */ | |
bf8d0969 | 1162 | void pmu_init(ARMCPU *cpu) |
57a4a11b | 1163 | { |
57a4a11b AL |
1164 | unsigned int i; |
1165 | ||
bf8d0969 AL |
1166 | /* |
1167 | * Empty supported_event_map and cpu->pmceid[01] before adding supported | |
1168 | * events to them | |
1169 | */ | |
57a4a11b AL |
1170 | for (i = 0; i < ARRAY_SIZE(supported_event_map); i++) { |
1171 | supported_event_map[i] = UNSUPPORTED_EVENT; | |
1172 | } | |
bf8d0969 AL |
1173 | cpu->pmceid0 = 0; |
1174 | cpu->pmceid1 = 0; | |
57a4a11b AL |
1175 | |
1176 | for (i = 0; i < ARRAY_SIZE(pm_events); i++) { | |
1177 | const pm_event *cnt = &pm_events[i]; | |
1178 | assert(cnt->number <= MAX_EVENT_ID); | |
1179 | /* We do not currently support events in the 0x40xx range */ | |
1180 | assert(cnt->number <= 0x3f); | |
1181 | ||
bf8d0969 | 1182 | if (cnt->supported(&cpu->env)) { |
57a4a11b | 1183 | supported_event_map[cnt->number] = i; |
67da43d6 | 1184 | uint64_t event_mask = 1ULL << (cnt->number & 0x1f); |
bf8d0969 AL |
1185 | if (cnt->number & 0x20) { |
1186 | cpu->pmceid1 |= event_mask; | |
1187 | } else { | |
1188 | cpu->pmceid0 |= event_mask; | |
1189 | } | |
57a4a11b AL |
1190 | } |
1191 | } | |
57a4a11b AL |
1192 | } |
1193 | ||
5ecdd3e4 AL |
1194 | /* |
1195 | * Check at runtime whether a PMU event is supported for the current machine | |
1196 | */ | |
1197 | static bool event_supported(uint16_t number) | |
1198 | { | |
1199 | if (number > MAX_EVENT_ID) { | |
1200 | return false; | |
1201 | } | |
1202 | return supported_event_map[number] != UNSUPPORTED_EVENT; | |
1203 | } | |
1204 | ||
3f208fd7 PM |
1205 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1206 | bool isread) | |
200ac0ef | 1207 | { |
3b163b01 | 1208 | /* Performance monitor registers user accessibility is controlled |
1fce1ba9 PM |
1209 | * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable |
1210 | * trapping to EL2 or EL3 for other accesses. | |
200ac0ef | 1211 | */ |
1fce1ba9 PM |
1212 | int el = arm_current_el(env); |
1213 | ||
6ecd0b6b | 1214 | if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { |
fcd25206 | 1215 | return CP_ACCESS_TRAP; |
200ac0ef | 1216 | } |
1fce1ba9 PM |
1217 | if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM) |
1218 | && !arm_is_secure_below_el3(env)) { | |
1219 | return CP_ACCESS_TRAP_EL2; | |
1220 | } | |
1221 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
1222 | return CP_ACCESS_TRAP_EL3; | |
1223 | } | |
1224 | ||
fcd25206 | 1225 | return CP_ACCESS_OK; |
200ac0ef PM |
1226 | } |
1227 | ||
6ecd0b6b AB |
1228 | static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, |
1229 | const ARMCPRegInfo *ri, | |
1230 | bool isread) | |
1231 | { | |
1232 | /* ER: event counter read trap control */ | |
1233 | if (arm_feature(env, ARM_FEATURE_V8) | |
1234 | && arm_current_el(env) == 0 | |
1235 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 | |
1236 | && isread) { | |
1237 | return CP_ACCESS_OK; | |
1238 | } | |
1239 | ||
1240 | return pmreg_access(env, ri, isread); | |
1241 | } | |
1242 | ||
1243 | static CPAccessResult pmreg_access_swinc(CPUARMState *env, | |
1244 | const ARMCPRegInfo *ri, | |
1245 | bool isread) | |
1246 | { | |
1247 | /* SW: software increment write trap control */ | |
1248 | if (arm_feature(env, ARM_FEATURE_V8) | |
1249 | && arm_current_el(env) == 0 | |
1250 | && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 | |
1251 | && !isread) { | |
1252 | return CP_ACCESS_OK; | |
1253 | } | |
1254 | ||
1255 | return pmreg_access(env, ri, isread); | |
1256 | } | |
1257 | ||
6ecd0b6b AB |
1258 | static CPAccessResult pmreg_access_selr(CPUARMState *env, |
1259 | const ARMCPRegInfo *ri, | |
1260 | bool isread) | |
1261 | { | |
1262 | /* ER: event counter read trap control */ | |
1263 | if (arm_feature(env, ARM_FEATURE_V8) | |
1264 | && arm_current_el(env) == 0 | |
1265 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { | |
1266 | return CP_ACCESS_OK; | |
1267 | } | |
1268 | ||
1269 | return pmreg_access(env, ri, isread); | |
1270 | } | |
1271 | ||
1272 | static CPAccessResult pmreg_access_ccntr(CPUARMState *env, | |
1273 | const ARMCPRegInfo *ri, | |
1274 | bool isread) | |
1275 | { | |
1276 | /* CR: cycle counter read trap control */ | |
1277 | if (arm_feature(env, ARM_FEATURE_V8) | |
1278 | && arm_current_el(env) == 0 | |
1279 | && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 | |
1280 | && isread) { | |
1281 | return CP_ACCESS_OK; | |
1282 | } | |
1283 | ||
1284 | return pmreg_access(env, ri, isread); | |
1285 | } | |
1286 | ||
033614c4 AL |
1287 | /* Returns true if the counter (pass 31 for PMCCNTR) should count events using |
1288 | * the current EL, security state, and register configuration. | |
1289 | */ | |
1290 | static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) | |
87124fde | 1291 | { |
033614c4 AL |
1292 | uint64_t filter; |
1293 | bool e, p, u, nsk, nsu, nsh, m; | |
1294 | bool enabled, prohibited, filtered; | |
1295 | bool secure = arm_is_secure(env); | |
1296 | int el = arm_current_el(env); | |
1297 | uint8_t hpmn = env->cp15.mdcr_el2 & MDCR_HPMN; | |
87124fde | 1298 | |
cbbb3041 AJ |
1299 | if (!arm_feature(env, ARM_FEATURE_PMU)) { |
1300 | return false; | |
1301 | } | |
1302 | ||
033614c4 AL |
1303 | if (!arm_feature(env, ARM_FEATURE_EL2) || |
1304 | (counter < hpmn || counter == 31)) { | |
1305 | e = env->cp15.c9_pmcr & PMCRE; | |
1306 | } else { | |
1307 | e = env->cp15.mdcr_el2 & MDCR_HPME; | |
87124fde | 1308 | } |
033614c4 | 1309 | enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); |
87124fde | 1310 | |
033614c4 AL |
1311 | if (!secure) { |
1312 | if (el == 2 && (counter < hpmn || counter == 31)) { | |
1313 | prohibited = env->cp15.mdcr_el2 & MDCR_HPMD; | |
1314 | } else { | |
1315 | prohibited = false; | |
1316 | } | |
1317 | } else { | |
1318 | prohibited = arm_feature(env, ARM_FEATURE_EL3) && | |
1319 | (env->cp15.mdcr_el3 & MDCR_SPME); | |
1320 | } | |
1321 | ||
1322 | if (prohibited && counter == 31) { | |
1323 | prohibited = env->cp15.c9_pmcr & PMCRDP; | |
1324 | } | |
1325 | ||
5ecdd3e4 AL |
1326 | if (counter == 31) { |
1327 | filter = env->cp15.pmccfiltr_el0; | |
1328 | } else { | |
1329 | filter = env->cp15.c14_pmevtyper[counter]; | |
1330 | } | |
033614c4 AL |
1331 | |
1332 | p = filter & PMXEVTYPER_P; | |
1333 | u = filter & PMXEVTYPER_U; | |
1334 | nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); | |
1335 | nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); | |
1336 | nsh = arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); | |
1337 | m = arm_el_is_aa64(env, 1) && | |
1338 | arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); | |
1339 | ||
1340 | if (el == 0) { | |
1341 | filtered = secure ? u : u != nsu; | |
1342 | } else if (el == 1) { | |
1343 | filtered = secure ? p : p != nsk; | |
1344 | } else if (el == 2) { | |
1345 | filtered = !nsh; | |
1346 | } else { /* EL3 */ | |
1347 | filtered = m != p; | |
1348 | } | |
1349 | ||
5ecdd3e4 AL |
1350 | if (counter != 31) { |
1351 | /* | |
1352 | * If not checking PMCCNTR, ensure the counter is setup to an event we | |
1353 | * support | |
1354 | */ | |
1355 | uint16_t event = filter & PMXEVTYPER_EVTCOUNT; | |
1356 | if (!event_supported(event)) { | |
1357 | return false; | |
1358 | } | |
1359 | } | |
1360 | ||
033614c4 | 1361 | return enabled && !prohibited && !filtered; |
87124fde | 1362 | } |
033614c4 | 1363 | |
f4efb4b2 AL |
1364 | static void pmu_update_irq(CPUARMState *env) |
1365 | { | |
2fc0cc0e | 1366 | ARMCPU *cpu = env_archcpu(env); |
f4efb4b2 AL |
1367 | qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && |
1368 | (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); | |
1369 | } | |
1370 | ||
5d05b9d4 AL |
1371 | /* |
1372 | * Ensure c15_ccnt is the guest-visible count so that operations such as | |
1373 | * enabling/disabling the counter or filtering, modifying the count itself, | |
1374 | * etc. can be done logically. This is essentially a no-op if the counter is | |
1375 | * not enabled at the time of the call. | |
1376 | */ | |
f2b2f53f | 1377 | static void pmccntr_op_start(CPUARMState *env) |
ec7b4ce4 | 1378 | { |
b2e23725 | 1379 | uint64_t cycles = cycles_get_count(env); |
ec7b4ce4 | 1380 | |
033614c4 | 1381 | if (pmu_counter_enabled(env, 31)) { |
5d05b9d4 AL |
1382 | uint64_t eff_cycles = cycles; |
1383 | if (env->cp15.c9_pmcr & PMCRD) { | |
1384 | /* Increment once every 64 processor clock cycles */ | |
1385 | eff_cycles /= 64; | |
1386 | } | |
1387 | ||
f4efb4b2 AL |
1388 | uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta; |
1389 | ||
1390 | uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \ | |
1391 | 1ull << 63 : 1ull << 31; | |
1392 | if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { | |
1393 | env->cp15.c9_pmovsr |= (1 << 31); | |
1394 | pmu_update_irq(env); | |
1395 | } | |
1396 | ||
1397 | env->cp15.c15_ccnt = new_pmccntr; | |
ec7b4ce4 | 1398 | } |
5d05b9d4 AL |
1399 | env->cp15.c15_ccnt_delta = cycles; |
1400 | } | |
ec7b4ce4 | 1401 | |
5d05b9d4 AL |
1402 | /* |
1403 | * If PMCCNTR is enabled, recalculate the delta between the clock and the | |
1404 | * guest-visible count. A call to pmccntr_op_finish should follow every call to | |
1405 | * pmccntr_op_start. | |
1406 | */ | |
f2b2f53f | 1407 | static void pmccntr_op_finish(CPUARMState *env) |
5d05b9d4 | 1408 | { |
033614c4 | 1409 | if (pmu_counter_enabled(env, 31)) { |
4e7beb0c AL |
1410 | #ifndef CONFIG_USER_ONLY |
1411 | /* Calculate when the counter will next overflow */ | |
1412 | uint64_t remaining_cycles = -env->cp15.c15_ccnt; | |
1413 | if (!(env->cp15.c9_pmcr & PMCRLC)) { | |
1414 | remaining_cycles = (uint32_t)remaining_cycles; | |
1415 | } | |
1416 | int64_t overflow_in = cycles_ns_per(remaining_cycles); | |
1417 | ||
1418 | if (overflow_in > 0) { | |
1419 | int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
1420 | overflow_in; | |
2fc0cc0e | 1421 | ARMCPU *cpu = env_archcpu(env); |
4e7beb0c AL |
1422 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); |
1423 | } | |
1424 | #endif | |
5d05b9d4 | 1425 | |
4e7beb0c | 1426 | uint64_t prev_cycles = env->cp15.c15_ccnt_delta; |
5d05b9d4 AL |
1427 | if (env->cp15.c9_pmcr & PMCRD) { |
1428 | /* Increment once every 64 processor clock cycles */ | |
1429 | prev_cycles /= 64; | |
1430 | } | |
5d05b9d4 | 1431 | env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt; |
ec7b4ce4 AF |
1432 | } |
1433 | } | |
1434 | ||
5ecdd3e4 AL |
1435 | static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) |
1436 | { | |
1437 | ||
1438 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; | |
1439 | uint64_t count = 0; | |
1440 | if (event_supported(event)) { | |
1441 | uint16_t event_idx = supported_event_map[event]; | |
1442 | count = pm_events[event_idx].get_count(env); | |
1443 | } | |
1444 | ||
1445 | if (pmu_counter_enabled(env, counter)) { | |
f4efb4b2 AL |
1446 | uint32_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter]; |
1447 | ||
1448 | if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & INT32_MIN) { | |
1449 | env->cp15.c9_pmovsr |= (1 << counter); | |
1450 | pmu_update_irq(env); | |
1451 | } | |
1452 | env->cp15.c14_pmevcntr[counter] = new_pmevcntr; | |
5ecdd3e4 AL |
1453 | } |
1454 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1455 | } | |
1456 | ||
1457 | static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) | |
1458 | { | |
1459 | if (pmu_counter_enabled(env, counter)) { | |
4e7beb0c AL |
1460 | #ifndef CONFIG_USER_ONLY |
1461 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; | |
1462 | uint16_t event_idx = supported_event_map[event]; | |
1463 | uint64_t delta = UINT32_MAX - | |
1464 | (uint32_t)env->cp15.c14_pmevcntr[counter] + 1; | |
1465 | int64_t overflow_in = pm_events[event_idx].ns_per_count(delta); | |
1466 | ||
1467 | if (overflow_in > 0) { | |
1468 | int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
1469 | overflow_in; | |
2fc0cc0e | 1470 | ARMCPU *cpu = env_archcpu(env); |
4e7beb0c AL |
1471 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); |
1472 | } | |
1473 | #endif | |
1474 | ||
5ecdd3e4 AL |
1475 | env->cp15.c14_pmevcntr_delta[counter] -= |
1476 | env->cp15.c14_pmevcntr[counter]; | |
1477 | } | |
1478 | } | |
1479 | ||
5d05b9d4 AL |
1480 | void pmu_op_start(CPUARMState *env) |
1481 | { | |
5ecdd3e4 | 1482 | unsigned int i; |
5d05b9d4 | 1483 | pmccntr_op_start(env); |
5ecdd3e4 AL |
1484 | for (i = 0; i < pmu_num_counters(env); i++) { |
1485 | pmevcntr_op_start(env, i); | |
1486 | } | |
5d05b9d4 AL |
1487 | } |
1488 | ||
1489 | void pmu_op_finish(CPUARMState *env) | |
1490 | { | |
5ecdd3e4 | 1491 | unsigned int i; |
5d05b9d4 | 1492 | pmccntr_op_finish(env); |
5ecdd3e4 AL |
1493 | for (i = 0; i < pmu_num_counters(env); i++) { |
1494 | pmevcntr_op_finish(env, i); | |
1495 | } | |
5d05b9d4 AL |
1496 | } |
1497 | ||
033614c4 AL |
1498 | void pmu_pre_el_change(ARMCPU *cpu, void *ignored) |
1499 | { | |
1500 | pmu_op_start(&cpu->env); | |
1501 | } | |
1502 | ||
1503 | void pmu_post_el_change(ARMCPU *cpu, void *ignored) | |
1504 | { | |
1505 | pmu_op_finish(&cpu->env); | |
1506 | } | |
1507 | ||
4e7beb0c AL |
1508 | void arm_pmu_timer_cb(void *opaque) |
1509 | { | |
1510 | ARMCPU *cpu = opaque; | |
1511 | ||
1512 | /* | |
1513 | * Update all the counter values based on the current underlying counts, | |
1514 | * triggering interrupts to be raised, if necessary. pmu_op_finish() also | |
1515 | * has the effect of setting the cpu->pmu_timer to the next earliest time a | |
1516 | * counter may expire. | |
1517 | */ | |
1518 | pmu_op_start(&cpu->env); | |
1519 | pmu_op_finish(&cpu->env); | |
1520 | } | |
1521 | ||
c4241c7d PM |
1522 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1523 | uint64_t value) | |
200ac0ef | 1524 | { |
5d05b9d4 | 1525 | pmu_op_start(env); |
7c2cb42b AF |
1526 | |
1527 | if (value & PMCRC) { | |
1528 | /* The counter has been reset */ | |
1529 | env->cp15.c15_ccnt = 0; | |
1530 | } | |
1531 | ||
5ecdd3e4 AL |
1532 | if (value & PMCRP) { |
1533 | unsigned int i; | |
1534 | for (i = 0; i < pmu_num_counters(env); i++) { | |
1535 | env->cp15.c14_pmevcntr[i] = 0; | |
1536 | } | |
1537 | } | |
1538 | ||
200ac0ef PM |
1539 | /* only the DP, X, D and E bits are writable */ |
1540 | env->cp15.c9_pmcr &= ~0x39; | |
1541 | env->cp15.c9_pmcr |= (value & 0x39); | |
7c2cb42b | 1542 | |
5d05b9d4 | 1543 | pmu_op_finish(env); |
7c2cb42b AF |
1544 | } |
1545 | ||
0d4bfd7d AL |
1546 | static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1547 | uint64_t value) | |
1548 | { | |
1549 | unsigned int i; | |
1550 | for (i = 0; i < pmu_num_counters(env); i++) { | |
1551 | /* Increment a counter's count iff: */ | |
1552 | if ((value & (1 << i)) && /* counter's bit is set */ | |
1553 | /* counter is enabled and not filtered */ | |
1554 | pmu_counter_enabled(env, i) && | |
1555 | /* counter is SW_INCR */ | |
1556 | (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { | |
1557 | pmevcntr_op_start(env, i); | |
f4efb4b2 AL |
1558 | |
1559 | /* | |
1560 | * Detect if this write causes an overflow since we can't predict | |
1561 | * PMSWINC overflows like we can for other events | |
1562 | */ | |
1563 | uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; | |
1564 | ||
1565 | if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { | |
1566 | env->cp15.c9_pmovsr |= (1 << i); | |
1567 | pmu_update_irq(env); | |
1568 | } | |
1569 | ||
1570 | env->cp15.c14_pmevcntr[i] = new_pmswinc; | |
1571 | ||
0d4bfd7d AL |
1572 | pmevcntr_op_finish(env, i); |
1573 | } | |
1574 | } | |
1575 | } | |
1576 | ||
7c2cb42b AF |
1577 | static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1578 | { | |
5d05b9d4 AL |
1579 | uint64_t ret; |
1580 | pmccntr_op_start(env); | |
1581 | ret = env->cp15.c15_ccnt; | |
1582 | pmccntr_op_finish(env); | |
1583 | return ret; | |
7c2cb42b AF |
1584 | } |
1585 | ||
6b040780 WH |
1586 | static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1587 | uint64_t value) | |
1588 | { | |
1589 | /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and | |
1590 | * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the | |
1591 | * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are | |
1592 | * accessed. | |
1593 | */ | |
1594 | env->cp15.c9_pmselr = value & 0x1f; | |
1595 | } | |
1596 | ||
7c2cb42b AF |
1597 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1598 | uint64_t value) | |
1599 | { | |
5d05b9d4 AL |
1600 | pmccntr_op_start(env); |
1601 | env->cp15.c15_ccnt = value; | |
1602 | pmccntr_op_finish(env); | |
200ac0ef | 1603 | } |
421c7ebd PC |
1604 | |
1605 | static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1606 | uint64_t value) | |
1607 | { | |
1608 | uint64_t cur_val = pmccntr_read(env, NULL); | |
1609 | ||
1610 | pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); | |
1611 | } | |
1612 | ||
0614601c AF |
1613 | static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1614 | uint64_t value) | |
1615 | { | |
5d05b9d4 | 1616 | pmccntr_op_start(env); |
4b8afa1f AL |
1617 | env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0; |
1618 | pmccntr_op_finish(env); | |
1619 | } | |
1620 | ||
1621 | static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1622 | uint64_t value) | |
1623 | { | |
1624 | pmccntr_op_start(env); | |
1625 | /* M is not accessible from AArch32 */ | |
1626 | env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | | |
1627 | (value & PMCCFILTR); | |
5d05b9d4 | 1628 | pmccntr_op_finish(env); |
0614601c AF |
1629 | } |
1630 | ||
4b8afa1f AL |
1631 | static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri) |
1632 | { | |
1633 | /* M is not visible in AArch32 */ | |
1634 | return env->cp15.pmccfiltr_el0 & PMCCFILTR; | |
1635 | } | |
1636 | ||
c4241c7d | 1637 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1638 | uint64_t value) |
1639 | { | |
7ece99b1 | 1640 | value &= pmu_counter_mask(env); |
200ac0ef | 1641 | env->cp15.c9_pmcnten |= value; |
200ac0ef PM |
1642 | } |
1643 | ||
c4241c7d PM |
1644 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1645 | uint64_t value) | |
200ac0ef | 1646 | { |
7ece99b1 | 1647 | value &= pmu_counter_mask(env); |
200ac0ef | 1648 | env->cp15.c9_pmcnten &= ~value; |
200ac0ef PM |
1649 | } |
1650 | ||
c4241c7d PM |
1651 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1652 | uint64_t value) | |
200ac0ef | 1653 | { |
599b71e2 | 1654 | value &= pmu_counter_mask(env); |
200ac0ef | 1655 | env->cp15.c9_pmovsr &= ~value; |
f4efb4b2 | 1656 | pmu_update_irq(env); |
200ac0ef PM |
1657 | } |
1658 | ||
327dd510 AL |
1659 | static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1660 | uint64_t value) | |
1661 | { | |
1662 | value &= pmu_counter_mask(env); | |
1663 | env->cp15.c9_pmovsr |= value; | |
f4efb4b2 | 1664 | pmu_update_irq(env); |
327dd510 AL |
1665 | } |
1666 | ||
5ecdd3e4 AL |
1667 | static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1668 | uint64_t value, const uint8_t counter) | |
200ac0ef | 1669 | { |
5ecdd3e4 AL |
1670 | if (counter == 31) { |
1671 | pmccfiltr_write(env, ri, value); | |
1672 | } else if (counter < pmu_num_counters(env)) { | |
1673 | pmevcntr_op_start(env, counter); | |
1674 | ||
1675 | /* | |
1676 | * If this counter's event type is changing, store the current | |
1677 | * underlying count for the new type in c14_pmevcntr_delta[counter] so | |
1678 | * pmevcntr_op_finish has the correct baseline when it converts back to | |
1679 | * a delta. | |
1680 | */ | |
1681 | uint16_t old_event = env->cp15.c14_pmevtyper[counter] & | |
1682 | PMXEVTYPER_EVTCOUNT; | |
1683 | uint16_t new_event = value & PMXEVTYPER_EVTCOUNT; | |
1684 | if (old_event != new_event) { | |
1685 | uint64_t count = 0; | |
1686 | if (event_supported(new_event)) { | |
1687 | uint16_t event_idx = supported_event_map[new_event]; | |
1688 | count = pm_events[event_idx].get_count(env); | |
1689 | } | |
1690 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1691 | } | |
1692 | ||
1693 | env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK; | |
1694 | pmevcntr_op_finish(env, counter); | |
1695 | } | |
fdb86656 WH |
1696 | /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when |
1697 | * PMSELR value is equal to or greater than the number of implemented | |
1698 | * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. | |
1699 | */ | |
5ecdd3e4 AL |
1700 | } |
1701 | ||
1702 | static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1703 | const uint8_t counter) | |
1704 | { | |
1705 | if (counter == 31) { | |
1706 | return env->cp15.pmccfiltr_el0; | |
1707 | } else if (counter < pmu_num_counters(env)) { | |
1708 | return env->cp15.c14_pmevtyper[counter]; | |
1709 | } else { | |
1710 | /* | |
1711 | * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER | |
1712 | * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). | |
1713 | */ | |
1714 | return 0; | |
1715 | } | |
1716 | } | |
1717 | ||
1718 | static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, | |
1719 | uint64_t value) | |
1720 | { | |
1721 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1722 | pmevtyper_write(env, ri, value, counter); | |
1723 | } | |
1724 | ||
1725 | static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1726 | uint64_t value) | |
1727 | { | |
1728 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1729 | env->cp15.c14_pmevtyper[counter] = value; | |
1730 | ||
1731 | /* | |
1732 | * pmevtyper_rawwrite is called between a pair of pmu_op_start and | |
1733 | * pmu_op_finish calls when loading saved state for a migration. Because | |
1734 | * we're potentially updating the type of event here, the value written to | |
1735 | * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a | |
1736 | * different counter type. Therefore, we need to set this value to the | |
1737 | * current count for the counter type we're writing so that pmu_op_finish | |
1738 | * has the correct count for its calculation. | |
1739 | */ | |
1740 | uint16_t event = value & PMXEVTYPER_EVTCOUNT; | |
1741 | if (event_supported(event)) { | |
1742 | uint16_t event_idx = supported_event_map[event]; | |
1743 | env->cp15.c14_pmevcntr_delta[counter] = | |
1744 | pm_events[event_idx].get_count(env); | |
fdb86656 WH |
1745 | } |
1746 | } | |
1747 | ||
5ecdd3e4 AL |
1748 | static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) |
1749 | { | |
1750 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1751 | return pmevtyper_read(env, ri, counter); | |
1752 | } | |
1753 | ||
1754 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1755 | uint64_t value) | |
1756 | { | |
1757 | pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1758 | } | |
1759 | ||
fdb86656 WH |
1760 | static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1761 | { | |
5ecdd3e4 AL |
1762 | return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); |
1763 | } | |
1764 | ||
1765 | static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1766 | uint64_t value, uint8_t counter) | |
1767 | { | |
1768 | if (counter < pmu_num_counters(env)) { | |
1769 | pmevcntr_op_start(env, counter); | |
1770 | env->cp15.c14_pmevcntr[counter] = value; | |
1771 | pmevcntr_op_finish(env, counter); | |
1772 | } | |
1773 | /* | |
1774 | * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR | |
1775 | * are CONSTRAINED UNPREDICTABLE. | |
fdb86656 | 1776 | */ |
5ecdd3e4 AL |
1777 | } |
1778 | ||
1779 | static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1780 | uint8_t counter) | |
1781 | { | |
1782 | if (counter < pmu_num_counters(env)) { | |
1783 | uint64_t ret; | |
1784 | pmevcntr_op_start(env, counter); | |
1785 | ret = env->cp15.c14_pmevcntr[counter]; | |
1786 | pmevcntr_op_finish(env, counter); | |
1787 | return ret; | |
fdb86656 | 1788 | } else { |
5ecdd3e4 AL |
1789 | /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR |
1790 | * are CONSTRAINED UNPREDICTABLE. */ | |
fdb86656 WH |
1791 | return 0; |
1792 | } | |
200ac0ef PM |
1793 | } |
1794 | ||
5ecdd3e4 AL |
1795 | static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, |
1796 | uint64_t value) | |
1797 | { | |
1798 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1799 | pmevcntr_write(env, ri, value, counter); | |
1800 | } | |
1801 | ||
1802 | static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) | |
1803 | { | |
1804 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1805 | return pmevcntr_read(env, ri, counter); | |
1806 | } | |
1807 | ||
1808 | static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1809 | uint64_t value) | |
1810 | { | |
1811 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1812 | assert(counter < pmu_num_counters(env)); | |
1813 | env->cp15.c14_pmevcntr[counter] = value; | |
1814 | pmevcntr_write(env, ri, value, counter); | |
1815 | } | |
1816 | ||
1817 | static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri) | |
1818 | { | |
1819 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1820 | assert(counter < pmu_num_counters(env)); | |
1821 | return env->cp15.c14_pmevcntr[counter]; | |
1822 | } | |
1823 | ||
1824 | static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1825 | uint64_t value) | |
1826 | { | |
1827 | pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1828 | } | |
1829 | ||
1830 | static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1831 | { | |
1832 | return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); | |
1833 | } | |
1834 | ||
c4241c7d | 1835 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1836 | uint64_t value) |
1837 | { | |
6ecd0b6b AB |
1838 | if (arm_feature(env, ARM_FEATURE_V8)) { |
1839 | env->cp15.c9_pmuserenr = value & 0xf; | |
1840 | } else { | |
1841 | env->cp15.c9_pmuserenr = value & 1; | |
1842 | } | |
200ac0ef PM |
1843 | } |
1844 | ||
c4241c7d PM |
1845 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1846 | uint64_t value) | |
200ac0ef PM |
1847 | { |
1848 | /* We have no event counters so only the C bit can be changed */ | |
7ece99b1 | 1849 | value &= pmu_counter_mask(env); |
200ac0ef | 1850 | env->cp15.c9_pminten |= value; |
f4efb4b2 | 1851 | pmu_update_irq(env); |
200ac0ef PM |
1852 | } |
1853 | ||
c4241c7d PM |
1854 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1855 | uint64_t value) | |
200ac0ef | 1856 | { |
7ece99b1 | 1857 | value &= pmu_counter_mask(env); |
200ac0ef | 1858 | env->cp15.c9_pminten &= ~value; |
f4efb4b2 | 1859 | pmu_update_irq(env); |
200ac0ef PM |
1860 | } |
1861 | ||
c4241c7d PM |
1862 | static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1863 | uint64_t value) | |
8641136c | 1864 | { |
a505d7fe PM |
1865 | /* Note that even though the AArch64 view of this register has bits |
1866 | * [10:0] all RES0 we can only mask the bottom 5, to comply with the | |
1867 | * architectural requirements for bits which are RES0 only in some | |
1868 | * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 | |
1869 | * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) | |
1870 | */ | |
855ea66d | 1871 | raw_write(env, ri, value & ~0x1FULL); |
8641136c NR |
1872 | } |
1873 | ||
64e0e2de EI |
1874 | static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
1875 | { | |
ea22747c RH |
1876 | /* Begin with base v8.0 state. */ |
1877 | uint32_t valid_mask = 0x3fff; | |
2fc0cc0e | 1878 | ARMCPU *cpu = env_archcpu(env); |
ea22747c RH |
1879 | |
1880 | if (arm_el_is_aa64(env, 3)) { | |
1881 | value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ | |
1882 | valid_mask &= ~SCR_NET; | |
1883 | } else { | |
1884 | valid_mask &= ~(SCR_RW | SCR_ST); | |
1885 | } | |
64e0e2de EI |
1886 | |
1887 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | |
1888 | valid_mask &= ~SCR_HCE; | |
1889 | ||
1890 | /* On ARMv7, SMD (or SCD as it is called in v7) is only | |
1891 | * supported if EL2 exists. The bit is UNK/SBZP when | |
1892 | * EL2 is unavailable. In QEMU ARMv7, we force it to always zero | |
1893 | * when EL2 is unavailable. | |
4eb27640 | 1894 | * On ARMv8, this bit is always available. |
64e0e2de | 1895 | */ |
4eb27640 GB |
1896 | if (arm_feature(env, ARM_FEATURE_V7) && |
1897 | !arm_feature(env, ARM_FEATURE_V8)) { | |
64e0e2de EI |
1898 | valid_mask &= ~SCR_SMD; |
1899 | } | |
1900 | } | |
2d7137c1 RH |
1901 | if (cpu_isar_feature(aa64_lor, cpu)) { |
1902 | valid_mask |= SCR_TLOR; | |
1903 | } | |
ef682cdb RH |
1904 | if (cpu_isar_feature(aa64_pauth, cpu)) { |
1905 | valid_mask |= SCR_API | SCR_APK; | |
1906 | } | |
64e0e2de EI |
1907 | |
1908 | /* Clear all-context RES0 bits. */ | |
1909 | value &= valid_mask; | |
1910 | raw_write(env, ri, value); | |
1911 | } | |
1912 | ||
c4241c7d | 1913 | static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
776d4e5c | 1914 | { |
2fc0cc0e | 1915 | ARMCPU *cpu = env_archcpu(env); |
b85a1fd6 FA |
1916 | |
1917 | /* Acquire the CSSELR index from the bank corresponding to the CCSIDR | |
1918 | * bank | |
1919 | */ | |
1920 | uint32_t index = A32_BANKED_REG_GET(env, csselr, | |
1921 | ri->secure & ARM_CP_SECSTATE_S); | |
1922 | ||
1923 | return cpu->ccsidr[index]; | |
776d4e5c PM |
1924 | } |
1925 | ||
c4241c7d PM |
1926 | static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1927 | uint64_t value) | |
776d4e5c | 1928 | { |
8d5c773e | 1929 | raw_write(env, ri, value & 0xf); |
776d4e5c PM |
1930 | } |
1931 | ||
1090b9c6 PM |
1932 | static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1933 | { | |
29a0af61 | 1934 | CPUState *cs = env_cpu(env); |
f7778444 | 1935 | uint64_t hcr_el2 = arm_hcr_el2_eff(env); |
1090b9c6 PM |
1936 | uint64_t ret = 0; |
1937 | ||
f7778444 | 1938 | if (hcr_el2 & HCR_IMO) { |
636540e9 PM |
1939 | if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { |
1940 | ret |= CPSR_I; | |
1941 | } | |
1942 | } else { | |
1943 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { | |
1944 | ret |= CPSR_I; | |
1945 | } | |
1090b9c6 | 1946 | } |
636540e9 | 1947 | |
f7778444 | 1948 | if (hcr_el2 & HCR_FMO) { |
636540e9 PM |
1949 | if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { |
1950 | ret |= CPSR_F; | |
1951 | } | |
1952 | } else { | |
1953 | if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { | |
1954 | ret |= CPSR_F; | |
1955 | } | |
1090b9c6 | 1956 | } |
636540e9 | 1957 | |
1090b9c6 PM |
1958 | /* External aborts are not possible in QEMU so A bit is always clear */ |
1959 | return ret; | |
1960 | } | |
1961 | ||
e9aa6c21 | 1962 | static const ARMCPRegInfo v7_cp_reginfo[] = { |
7d57f408 PM |
1963 | /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ |
1964 | { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
1965 | .access = PL1_W, .type = ARM_CP_NOP }, | |
200ac0ef PM |
1966 | /* Performance monitors are implementation defined in v7, |
1967 | * but with an ARM recommended set of registers, which we | |
ac689a2e | 1968 | * follow. |
200ac0ef PM |
1969 | * |
1970 | * Performance registers fall into three categories: | |
1971 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) | |
1972 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) | |
1973 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) | |
1974 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW | |
1975 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. | |
1976 | */ | |
1977 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 1978 | .access = PL0_RW, .type = ARM_CP_ALIAS, |
8521466b | 1979 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), |
fcd25206 PM |
1980 | .writefn = pmcntenset_write, |
1981 | .accessfn = pmreg_access, | |
1982 | .raw_writefn = raw_write }, | |
8521466b AF |
1983 | { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, |
1984 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, | |
1985 | .access = PL0_RW, .accessfn = pmreg_access, | |
1986 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, | |
1987 | .writefn = pmcntenset_write, .raw_writefn = raw_write }, | |
200ac0ef | 1988 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
8521466b AF |
1989 | .access = PL0_RW, |
1990 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 PM |
1991 | .accessfn = pmreg_access, |
1992 | .writefn = pmcntenclr_write, | |
7a0e58fa | 1993 | .type = ARM_CP_ALIAS }, |
8521466b AF |
1994 | { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, |
1995 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, | |
1996 | .access = PL0_RW, .accessfn = pmreg_access, | |
7a0e58fa | 1997 | .type = ARM_CP_ALIAS, |
8521466b AF |
1998 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), |
1999 | .writefn = pmcntenclr_write }, | |
200ac0ef | 2000 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
f4efb4b2 | 2001 | .access = PL0_RW, .type = ARM_CP_IO, |
e4e91a21 | 2002 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
fcd25206 PM |
2003 | .accessfn = pmreg_access, |
2004 | .writefn = pmovsr_write, | |
2005 | .raw_writefn = raw_write }, | |
978364f1 AF |
2006 | { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, |
2007 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, | |
2008 | .access = PL0_RW, .accessfn = pmreg_access, | |
f4efb4b2 | 2009 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
978364f1 AF |
2010 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
2011 | .writefn = pmovsr_write, | |
2012 | .raw_writefn = raw_write }, | |
200ac0ef | 2013 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
f4efb4b2 AL |
2014 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
2015 | .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
0d4bfd7d AL |
2016 | .writefn = pmswinc_write }, |
2017 | { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64, | |
2018 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4, | |
f4efb4b2 AL |
2019 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
2020 | .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
0d4bfd7d | 2021 | .writefn = pmswinc_write }, |
6b040780 WH |
2022 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, |
2023 | .access = PL0_RW, .type = ARM_CP_ALIAS, | |
2024 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), | |
6ecd0b6b | 2025 | .accessfn = pmreg_access_selr, .writefn = pmselr_write, |
6b040780 WH |
2026 | .raw_writefn = raw_write}, |
2027 | { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, | |
2028 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, | |
6ecd0b6b | 2029 | .access = PL0_RW, .accessfn = pmreg_access_selr, |
6b040780 WH |
2030 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), |
2031 | .writefn = pmselr_write, .raw_writefn = raw_write, }, | |
200ac0ef | 2032 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
169c8938 | 2033 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO, |
421c7ebd | 2034 | .readfn = pmccntr_read, .writefn = pmccntr_write32, |
6ecd0b6b | 2035 | .accessfn = pmreg_access_ccntr }, |
8521466b AF |
2036 | { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, |
2037 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, | |
6ecd0b6b | 2038 | .access = PL0_RW, .accessfn = pmreg_access_ccntr, |
8521466b | 2039 | .type = ARM_CP_IO, |
980ebe87 AL |
2040 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt), |
2041 | .readfn = pmccntr_read, .writefn = pmccntr_write, | |
2042 | .raw_readfn = raw_read, .raw_writefn = raw_write, }, | |
4b8afa1f AL |
2043 | { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7, |
2044 | .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32, | |
2045 | .access = PL0_RW, .accessfn = pmreg_access, | |
2046 | .type = ARM_CP_ALIAS | ARM_CP_IO, | |
2047 | .resetvalue = 0, }, | |
8521466b AF |
2048 | { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, |
2049 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, | |
980ebe87 | 2050 | .writefn = pmccfiltr_write, .raw_writefn = raw_write, |
8521466b AF |
2051 | .access = PL0_RW, .accessfn = pmreg_access, |
2052 | .type = ARM_CP_IO, | |
2053 | .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), | |
2054 | .resetvalue = 0, }, | |
200ac0ef | 2055 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
5ecdd3e4 AL |
2056 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
2057 | .accessfn = pmreg_access, | |
fdb86656 WH |
2058 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
2059 | { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, | |
2060 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, | |
5ecdd3e4 AL |
2061 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
2062 | .accessfn = pmreg_access, | |
fdb86656 | 2063 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
200ac0ef | 2064 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
5ecdd3e4 AL |
2065 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
2066 | .accessfn = pmreg_access_xevcntr, | |
2067 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, | |
2068 | { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64, | |
2069 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2, | |
2070 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
2071 | .accessfn = pmreg_access_xevcntr, | |
2072 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, | |
200ac0ef | 2073 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
1fce1ba9 | 2074 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, |
e4e91a21 | 2075 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr), |
200ac0ef | 2076 | .resetvalue = 0, |
d4e6df63 | 2077 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
8a83ffc2 AF |
2078 | { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, |
2079 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, | |
1fce1ba9 | 2080 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, |
8a83ffc2 AF |
2081 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), |
2082 | .resetvalue = 0, | |
2083 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, | |
200ac0ef | 2084 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
1fce1ba9 | 2085 | .access = PL1_RW, .accessfn = access_tpm, |
b7d793ad | 2086 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
e6ec5457 | 2087 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), |
200ac0ef | 2088 | .resetvalue = 0, |
d4e6df63 | 2089 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
e6ec5457 WH |
2090 | { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, |
2091 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, | |
2092 | .access = PL1_RW, .accessfn = access_tpm, | |
2093 | .type = ARM_CP_IO, | |
2094 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
2095 | .writefn = pmintenset_write, .raw_writefn = raw_write, | |
2096 | .resetvalue = 0x0 }, | |
200ac0ef | 2097 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
fc5f6856 AL |
2098 | .access = PL1_RW, .accessfn = access_tpm, |
2099 | .type = ARM_CP_ALIAS | ARM_CP_IO, | |
200ac0ef | 2100 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
b061a82b | 2101 | .writefn = pmintenclr_write, }, |
978364f1 AF |
2102 | { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, |
2103 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, | |
fc5f6856 AL |
2104 | .access = PL1_RW, .accessfn = access_tpm, |
2105 | .type = ARM_CP_ALIAS | ARM_CP_IO, | |
978364f1 AF |
2106 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
2107 | .writefn = pmintenclr_write }, | |
7da845b0 PM |
2108 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, |
2109 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | |
7a0e58fa | 2110 | .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, |
7da845b0 PM |
2111 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, |
2112 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | |
b85a1fd6 FA |
2113 | .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, |
2114 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), | |
2115 | offsetof(CPUARMState, cp15.csselr_ns) } }, | |
776d4e5c PM |
2116 | /* Auxiliary ID register: this actually has an IMPDEF value but for now |
2117 | * just RAZ for all cores: | |
2118 | */ | |
0ff644a7 PM |
2119 | { .name = "AIDR", .state = ARM_CP_STATE_BOTH, |
2120 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, | |
776d4e5c | 2121 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f32cdad5 PM |
2122 | /* Auxiliary fault status registers: these also are IMPDEF, and we |
2123 | * choose to RAZ/WI for all cores. | |
2124 | */ | |
2125 | { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, | |
2126 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, | |
2127 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2128 | { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, | |
2129 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, | |
2130 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b0fe2427 PM |
2131 | /* MAIR can just read-as-written because we don't implement caches |
2132 | * and so don't need to care about memory attributes. | |
2133 | */ | |
2134 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | |
2135 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | |
be693c87 | 2136 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), |
b0fe2427 | 2137 | .resetvalue = 0 }, |
4cfb8ad8 PM |
2138 | { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, |
2139 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, | |
2140 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), | |
2141 | .resetvalue = 0 }, | |
b0fe2427 PM |
2142 | /* For non-long-descriptor page tables these are PRRR and NMRR; |
2143 | * regardless they still act as reads-as-written for QEMU. | |
b0fe2427 | 2144 | */ |
1281f8e3 | 2145 | /* MAIR0/1 are defined separately from their 64-bit counterpart which |
be693c87 GB |
2146 | * allows them to assign the correct fieldoffset based on the endianness |
2147 | * handled in the field definitions. | |
2148 | */ | |
a903c449 | 2149 | { .name = "MAIR0", .state = ARM_CP_STATE_AA32, |
b0fe2427 | 2150 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, |
be693c87 GB |
2151 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), |
2152 | offsetof(CPUARMState, cp15.mair0_ns) }, | |
b0fe2427 | 2153 | .resetfn = arm_cp_reset_ignore }, |
a903c449 | 2154 | { .name = "MAIR1", .state = ARM_CP_STATE_AA32, |
b0fe2427 | 2155 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, |
be693c87 GB |
2156 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), |
2157 | offsetof(CPUARMState, cp15.mair1_ns) }, | |
b0fe2427 | 2158 | .resetfn = arm_cp_reset_ignore }, |
1090b9c6 PM |
2159 | { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, |
2160 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, | |
7a0e58fa | 2161 | .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, |
995939a6 PM |
2162 | /* 32 bit ITLB invalidates */ |
2163 | { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, | |
7a0e58fa | 2164 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 2165 | { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, |
7a0e58fa | 2166 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 2167 | { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, |
7a0e58fa | 2168 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 PM |
2169 | /* 32 bit DTLB invalidates */ |
2170 | { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, | |
7a0e58fa | 2171 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 2172 | { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, |
7a0e58fa | 2173 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 2174 | { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, |
7a0e58fa | 2175 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 PM |
2176 | /* 32 bit TLB invalidates */ |
2177 | { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | |
7a0e58fa | 2178 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write }, |
995939a6 | 2179 | { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
7a0e58fa | 2180 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
995939a6 | 2181 | { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
7a0e58fa | 2182 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write }, |
995939a6 | 2183 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
7a0e58fa | 2184 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, |
995939a6 PM |
2185 | REGINFO_SENTINEL |
2186 | }; | |
2187 | ||
2188 | static const ARMCPRegInfo v7mp_cp_reginfo[] = { | |
2189 | /* 32 bit TLB invalidates, Inner Shareable */ | |
2190 | { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | |
7a0e58fa | 2191 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write }, |
995939a6 | 2192 | { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
7a0e58fa | 2193 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, |
995939a6 | 2194 | { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
7a0e58fa | 2195 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 2196 | .writefn = tlbiasid_is_write }, |
995939a6 | 2197 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
7a0e58fa | 2198 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 2199 | .writefn = tlbimvaa_is_write }, |
e9aa6c21 PM |
2200 | REGINFO_SENTINEL |
2201 | }; | |
2202 | ||
327dd510 AL |
2203 | static const ARMCPRegInfo pmovsset_cp_reginfo[] = { |
2204 | /* PMOVSSET is not implemented in v7 before v7ve */ | |
2205 | { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3, | |
2206 | .access = PL0_RW, .accessfn = pmreg_access, | |
f4efb4b2 | 2207 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
327dd510 AL |
2208 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
2209 | .writefn = pmovsset_write, | |
2210 | .raw_writefn = raw_write }, | |
2211 | { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64, | |
2212 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3, | |
2213 | .access = PL0_RW, .accessfn = pmreg_access, | |
f4efb4b2 | 2214 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
327dd510 AL |
2215 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
2216 | .writefn = pmovsset_write, | |
2217 | .raw_writefn = raw_write }, | |
2218 | REGINFO_SENTINEL | |
2219 | }; | |
2220 | ||
c4241c7d PM |
2221 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2222 | uint64_t value) | |
c326b979 PM |
2223 | { |
2224 | value &= 1; | |
2225 | env->teecr = value; | |
c326b979 PM |
2226 | } |
2227 | ||
3f208fd7 PM |
2228 | static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2229 | bool isread) | |
c326b979 | 2230 | { |
dcbff19b | 2231 | if (arm_current_el(env) == 0 && (env->teecr & 1)) { |
92611c00 | 2232 | return CP_ACCESS_TRAP; |
c326b979 | 2233 | } |
92611c00 | 2234 | return CP_ACCESS_OK; |
c326b979 PM |
2235 | } |
2236 | ||
2237 | static const ARMCPRegInfo t2ee_cp_reginfo[] = { | |
2238 | { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, | |
2239 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), | |
2240 | .resetvalue = 0, | |
2241 | .writefn = teecr_write }, | |
2242 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, | |
2243 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | |
92611c00 | 2244 | .accessfn = teehbr_access, .resetvalue = 0 }, |
c326b979 PM |
2245 | REGINFO_SENTINEL |
2246 | }; | |
2247 | ||
4d31c596 | 2248 | static const ARMCPRegInfo v6k_cp_reginfo[] = { |
e4fe830b PM |
2249 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, |
2250 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | |
2251 | .access = PL0_RW, | |
54bf36ed | 2252 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, |
4d31c596 PM |
2253 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
2254 | .access = PL0_RW, | |
54bf36ed FA |
2255 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), |
2256 | offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, | |
e4fe830b PM |
2257 | .resetfn = arm_cp_reset_ignore }, |
2258 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | |
2259 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | |
2260 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
2261 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), |
2262 | .resetvalue = 0}, | |
4d31c596 PM |
2263 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
2264 | .access = PL0_R|PL1_W, | |
54bf36ed FA |
2265 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), |
2266 | offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, | |
e4fe830b | 2267 | .resetfn = arm_cp_reset_ignore }, |
54bf36ed | 2268 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, |
e4fe830b | 2269 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, |
4d31c596 | 2270 | .access = PL1_RW, |
54bf36ed FA |
2271 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, |
2272 | { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, | |
2273 | .access = PL1_RW, | |
2274 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), | |
2275 | offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, | |
2276 | .resetvalue = 0 }, | |
4d31c596 PM |
2277 | REGINFO_SENTINEL |
2278 | }; | |
2279 | ||
55d284af PM |
2280 | #ifndef CONFIG_USER_ONLY |
2281 | ||
3f208fd7 PM |
2282 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2283 | bool isread) | |
00108f2d | 2284 | { |
75502672 PM |
2285 | /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. |
2286 | * Writable only at the highest implemented exception level. | |
2287 | */ | |
2288 | int el = arm_current_el(env); | |
2289 | ||
2290 | switch (el) { | |
2291 | case 0: | |
2292 | if (!extract32(env->cp15.c14_cntkctl, 0, 2)) { | |
2293 | return CP_ACCESS_TRAP; | |
2294 | } | |
2295 | break; | |
2296 | case 1: | |
2297 | if (!isread && ri->state == ARM_CP_STATE_AA32 && | |
2298 | arm_is_secure_below_el3(env)) { | |
2299 | /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ | |
2300 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2301 | } | |
2302 | break; | |
2303 | case 2: | |
2304 | case 3: | |
2305 | break; | |
00108f2d | 2306 | } |
75502672 PM |
2307 | |
2308 | if (!isread && el < arm_highest_el(env)) { | |
2309 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2310 | } | |
2311 | ||
00108f2d PM |
2312 | return CP_ACCESS_OK; |
2313 | } | |
2314 | ||
3f208fd7 PM |
2315 | static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, |
2316 | bool isread) | |
00108f2d | 2317 | { |
0b6440af EI |
2318 | unsigned int cur_el = arm_current_el(env); |
2319 | bool secure = arm_is_secure(env); | |
2320 | ||
00108f2d | 2321 | /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ |
0b6440af | 2322 | if (cur_el == 0 && |
00108f2d PM |
2323 | !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { |
2324 | return CP_ACCESS_TRAP; | |
2325 | } | |
0b6440af EI |
2326 | |
2327 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
2328 | timeridx == GTIMER_PHYS && !secure && cur_el < 2 && | |
2329 | !extract32(env->cp15.cnthctl_el2, 0, 1)) { | |
2330 | return CP_ACCESS_TRAP_EL2; | |
2331 | } | |
00108f2d PM |
2332 | return CP_ACCESS_OK; |
2333 | } | |
2334 | ||
3f208fd7 PM |
2335 | static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, |
2336 | bool isread) | |
00108f2d | 2337 | { |
0b6440af EI |
2338 | unsigned int cur_el = arm_current_el(env); |
2339 | bool secure = arm_is_secure(env); | |
2340 | ||
00108f2d PM |
2341 | /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if |
2342 | * EL0[PV]TEN is zero. | |
2343 | */ | |
0b6440af | 2344 | if (cur_el == 0 && |
00108f2d PM |
2345 | !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { |
2346 | return CP_ACCESS_TRAP; | |
2347 | } | |
0b6440af EI |
2348 | |
2349 | if (arm_feature(env, ARM_FEATURE_EL2) && | |
2350 | timeridx == GTIMER_PHYS && !secure && cur_el < 2 && | |
2351 | !extract32(env->cp15.cnthctl_el2, 1, 1)) { | |
2352 | return CP_ACCESS_TRAP_EL2; | |
2353 | } | |
00108f2d PM |
2354 | return CP_ACCESS_OK; |
2355 | } | |
2356 | ||
2357 | static CPAccessResult gt_pct_access(CPUARMState *env, | |
3f208fd7 PM |
2358 | const ARMCPRegInfo *ri, |
2359 | bool isread) | |
00108f2d | 2360 | { |
3f208fd7 | 2361 | return gt_counter_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2362 | } |
2363 | ||
2364 | static CPAccessResult gt_vct_access(CPUARMState *env, | |
3f208fd7 PM |
2365 | const ARMCPRegInfo *ri, |
2366 | bool isread) | |
00108f2d | 2367 | { |
3f208fd7 | 2368 | return gt_counter_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2369 | } |
2370 | ||
3f208fd7 PM |
2371 | static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2372 | bool isread) | |
00108f2d | 2373 | { |
3f208fd7 | 2374 | return gt_timer_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2375 | } |
2376 | ||
3f208fd7 PM |
2377 | static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2378 | bool isread) | |
00108f2d | 2379 | { |
3f208fd7 | 2380 | return gt_timer_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2381 | } |
2382 | ||
b4d3978c | 2383 | static CPAccessResult gt_stimer_access(CPUARMState *env, |
3f208fd7 PM |
2384 | const ARMCPRegInfo *ri, |
2385 | bool isread) | |
b4d3978c PM |
2386 | { |
2387 | /* The AArch64 register view of the secure physical timer is | |
2388 | * always accessible from EL3, and configurably accessible from | |
2389 | * Secure EL1. | |
2390 | */ | |
2391 | switch (arm_current_el(env)) { | |
2392 | case 1: | |
2393 | if (!arm_is_secure(env)) { | |
2394 | return CP_ACCESS_TRAP; | |
2395 | } | |
2396 | if (!(env->cp15.scr_el3 & SCR_ST)) { | |
2397 | return CP_ACCESS_TRAP_EL3; | |
2398 | } | |
2399 | return CP_ACCESS_OK; | |
2400 | case 0: | |
2401 | case 2: | |
2402 | return CP_ACCESS_TRAP; | |
2403 | case 3: | |
2404 | return CP_ACCESS_OK; | |
2405 | default: | |
2406 | g_assert_not_reached(); | |
2407 | } | |
2408 | } | |
2409 | ||
55d284af PM |
2410 | static uint64_t gt_get_countervalue(CPUARMState *env) |
2411 | { | |
bc72ad67 | 2412 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE; |
55d284af PM |
2413 | } |
2414 | ||
2415 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) | |
2416 | { | |
2417 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; | |
2418 | ||
2419 | if (gt->ctl & 1) { | |
2420 | /* Timer enabled: calculate and set current ISTATUS, irq, and | |
2421 | * reset timer to when ISTATUS next has to change | |
2422 | */ | |
edac4d8a EI |
2423 | uint64_t offset = timeridx == GTIMER_VIRT ? |
2424 | cpu->env.cp15.cntvoff_el2 : 0; | |
55d284af PM |
2425 | uint64_t count = gt_get_countervalue(&cpu->env); |
2426 | /* Note that this must be unsigned 64 bit arithmetic: */ | |
edac4d8a | 2427 | int istatus = count - offset >= gt->cval; |
55d284af | 2428 | uint64_t nexttick; |
194cbc49 | 2429 | int irqstate; |
55d284af PM |
2430 | |
2431 | gt->ctl = deposit32(gt->ctl, 2, 1, istatus); | |
194cbc49 PM |
2432 | |
2433 | irqstate = (istatus && !(gt->ctl & 2)); | |
2434 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
2435 | ||
55d284af PM |
2436 | if (istatus) { |
2437 | /* Next transition is when count rolls back over to zero */ | |
2438 | nexttick = UINT64_MAX; | |
2439 | } else { | |
2440 | /* Next transition is when we hit cval */ | |
edac4d8a | 2441 | nexttick = gt->cval + offset; |
55d284af PM |
2442 | } |
2443 | /* Note that the desired next expiry time might be beyond the | |
2444 | * signed-64-bit range of a QEMUTimer -- in this case we just | |
2445 | * set the timer for as far in the future as possible. When the | |
2446 | * timer expires we will reset the timer for any remaining period. | |
2447 | */ | |
2448 | if (nexttick > INT64_MAX / GTIMER_SCALE) { | |
2449 | nexttick = INT64_MAX / GTIMER_SCALE; | |
2450 | } | |
bc72ad67 | 2451 | timer_mod(cpu->gt_timer[timeridx], nexttick); |
194cbc49 | 2452 | trace_arm_gt_recalc(timeridx, irqstate, nexttick); |
55d284af PM |
2453 | } else { |
2454 | /* Timer disabled: ISTATUS and timer output always clear */ | |
2455 | gt->ctl &= ~4; | |
2456 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); | |
bc72ad67 | 2457 | timer_del(cpu->gt_timer[timeridx]); |
194cbc49 | 2458 | trace_arm_gt_recalc_disabled(timeridx); |
55d284af PM |
2459 | } |
2460 | } | |
2461 | ||
0e3eca4c EI |
2462 | static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, |
2463 | int timeridx) | |
55d284af | 2464 | { |
2fc0cc0e | 2465 | ARMCPU *cpu = env_archcpu(env); |
55d284af | 2466 | |
bc72ad67 | 2467 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
2468 | } |
2469 | ||
c4241c7d | 2470 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
55d284af | 2471 | { |
c4241c7d | 2472 | return gt_get_countervalue(env); |
55d284af PM |
2473 | } |
2474 | ||
edac4d8a EI |
2475 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2476 | { | |
2477 | return gt_get_countervalue(env) - env->cp15.cntvoff_el2; | |
2478 | } | |
2479 | ||
c4241c7d | 2480 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2481 | int timeridx, |
c4241c7d | 2482 | uint64_t value) |
55d284af | 2483 | { |
194cbc49 | 2484 | trace_arm_gt_cval_write(timeridx, value); |
55d284af | 2485 | env->cp15.c14_timer[timeridx].cval = value; |
2fc0cc0e | 2486 | gt_recalc_timer(env_archcpu(env), timeridx); |
55d284af | 2487 | } |
c4241c7d | 2488 | |
0e3eca4c EI |
2489 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, |
2490 | int timeridx) | |
55d284af | 2491 | { |
edac4d8a | 2492 | uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; |
55d284af | 2493 | |
c4241c7d | 2494 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - |
edac4d8a | 2495 | (gt_get_countervalue(env) - offset)); |
55d284af PM |
2496 | } |
2497 | ||
c4241c7d | 2498 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2499 | int timeridx, |
c4241c7d | 2500 | uint64_t value) |
55d284af | 2501 | { |
edac4d8a | 2502 | uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; |
55d284af | 2503 | |
194cbc49 | 2504 | trace_arm_gt_tval_write(timeridx, value); |
edac4d8a | 2505 | env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + |
18084b2f | 2506 | sextract64(value, 0, 32); |
2fc0cc0e | 2507 | gt_recalc_timer(env_archcpu(env), timeridx); |
55d284af PM |
2508 | } |
2509 | ||
c4241c7d | 2510 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2511 | int timeridx, |
c4241c7d | 2512 | uint64_t value) |
55d284af | 2513 | { |
2fc0cc0e | 2514 | ARMCPU *cpu = env_archcpu(env); |
55d284af PM |
2515 | uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; |
2516 | ||
194cbc49 | 2517 | trace_arm_gt_ctl_write(timeridx, value); |
d3afacc7 | 2518 | env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); |
55d284af PM |
2519 | if ((oldval ^ value) & 1) { |
2520 | /* Enable toggled */ | |
2521 | gt_recalc_timer(cpu, timeridx); | |
d3afacc7 | 2522 | } else if ((oldval ^ value) & 2) { |
55d284af PM |
2523 | /* IMASK toggled: don't need to recalculate, |
2524 | * just set the interrupt line based on ISTATUS | |
2525 | */ | |
194cbc49 PM |
2526 | int irqstate = (oldval & 4) && !(value & 2); |
2527 | ||
2528 | trace_arm_gt_imask_toggle(timeridx, irqstate); | |
2529 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
55d284af | 2530 | } |
55d284af PM |
2531 | } |
2532 | ||
0e3eca4c EI |
2533 | static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2534 | { | |
2535 | gt_timer_reset(env, ri, GTIMER_PHYS); | |
2536 | } | |
2537 | ||
2538 | static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2539 | uint64_t value) | |
2540 | { | |
2541 | gt_cval_write(env, ri, GTIMER_PHYS, value); | |
2542 | } | |
2543 | ||
2544 | static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2545 | { | |
2546 | return gt_tval_read(env, ri, GTIMER_PHYS); | |
2547 | } | |
2548 | ||
2549 | static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2550 | uint64_t value) | |
2551 | { | |
2552 | gt_tval_write(env, ri, GTIMER_PHYS, value); | |
2553 | } | |
2554 | ||
2555 | static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2556 | uint64_t value) | |
2557 | { | |
2558 | gt_ctl_write(env, ri, GTIMER_PHYS, value); | |
2559 | } | |
2560 | ||
2561 | static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) | |
2562 | { | |
2563 | gt_timer_reset(env, ri, GTIMER_VIRT); | |
2564 | } | |
2565 | ||
2566 | static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2567 | uint64_t value) | |
2568 | { | |
2569 | gt_cval_write(env, ri, GTIMER_VIRT, value); | |
2570 | } | |
2571 | ||
2572 | static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2573 | { | |
2574 | return gt_tval_read(env, ri, GTIMER_VIRT); | |
2575 | } | |
2576 | ||
2577 | static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2578 | uint64_t value) | |
2579 | { | |
2580 | gt_tval_write(env, ri, GTIMER_VIRT, value); | |
2581 | } | |
2582 | ||
2583 | static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2584 | uint64_t value) | |
2585 | { | |
2586 | gt_ctl_write(env, ri, GTIMER_VIRT, value); | |
2587 | } | |
2588 | ||
edac4d8a EI |
2589 | static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2590 | uint64_t value) | |
2591 | { | |
2fc0cc0e | 2592 | ARMCPU *cpu = env_archcpu(env); |
edac4d8a | 2593 | |
194cbc49 | 2594 | trace_arm_gt_cntvoff_write(value); |
edac4d8a EI |
2595 | raw_write(env, ri, value); |
2596 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
2597 | } | |
2598 | ||
b0e66d95 EI |
2599 | static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2600 | { | |
2601 | gt_timer_reset(env, ri, GTIMER_HYP); | |
2602 | } | |
2603 | ||
2604 | static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2605 | uint64_t value) | |
2606 | { | |
2607 | gt_cval_write(env, ri, GTIMER_HYP, value); | |
2608 | } | |
2609 | ||
2610 | static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2611 | { | |
2612 | return gt_tval_read(env, ri, GTIMER_HYP); | |
2613 | } | |
2614 | ||
2615 | static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2616 | uint64_t value) | |
2617 | { | |
2618 | gt_tval_write(env, ri, GTIMER_HYP, value); | |
2619 | } | |
2620 | ||
2621 | static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2622 | uint64_t value) | |
2623 | { | |
2624 | gt_ctl_write(env, ri, GTIMER_HYP, value); | |
2625 | } | |
2626 | ||
b4d3978c PM |
2627 | static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2628 | { | |
2629 | gt_timer_reset(env, ri, GTIMER_SEC); | |
2630 | } | |
2631 | ||
2632 | static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2633 | uint64_t value) | |
2634 | { | |
2635 | gt_cval_write(env, ri, GTIMER_SEC, value); | |
2636 | } | |
2637 | ||
2638 | static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2639 | { | |
2640 | return gt_tval_read(env, ri, GTIMER_SEC); | |
2641 | } | |
2642 | ||
2643 | static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2644 | uint64_t value) | |
2645 | { | |
2646 | gt_tval_write(env, ri, GTIMER_SEC, value); | |
2647 | } | |
2648 | ||
2649 | static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2650 | uint64_t value) | |
2651 | { | |
2652 | gt_ctl_write(env, ri, GTIMER_SEC, value); | |
2653 | } | |
2654 | ||
55d284af PM |
2655 | void arm_gt_ptimer_cb(void *opaque) |
2656 | { | |
2657 | ARMCPU *cpu = opaque; | |
2658 | ||
2659 | gt_recalc_timer(cpu, GTIMER_PHYS); | |
2660 | } | |
2661 | ||
2662 | void arm_gt_vtimer_cb(void *opaque) | |
2663 | { | |
2664 | ARMCPU *cpu = opaque; | |
2665 | ||
2666 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
2667 | } | |
2668 | ||
b0e66d95 EI |
2669 | void arm_gt_htimer_cb(void *opaque) |
2670 | { | |
2671 | ARMCPU *cpu = opaque; | |
2672 | ||
2673 | gt_recalc_timer(cpu, GTIMER_HYP); | |
2674 | } | |
2675 | ||
b4d3978c PM |
2676 | void arm_gt_stimer_cb(void *opaque) |
2677 | { | |
2678 | ARMCPU *cpu = opaque; | |
2679 | ||
2680 | gt_recalc_timer(cpu, GTIMER_SEC); | |
2681 | } | |
2682 | ||
55d284af PM |
2683 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
2684 | /* Note that CNTFRQ is purely reads-as-written for the benefit | |
2685 | * of software; writing it doesn't actually change the timer frequency. | |
2686 | * Our reset value matches the fixed frequency we implement the timer at. | |
2687 | */ | |
2688 | { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 2689 | .type = ARM_CP_ALIAS, |
a7adc4b7 PM |
2690 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, |
2691 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), | |
a7adc4b7 PM |
2692 | }, |
2693 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, | |
2694 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
2695 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
55d284af PM |
2696 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), |
2697 | .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE, | |
55d284af PM |
2698 | }, |
2699 | /* overall control: mostly access permissions */ | |
a7adc4b7 PM |
2700 | { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, |
2701 | .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, | |
55d284af PM |
2702 | .access = PL1_RW, |
2703 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), | |
2704 | .resetvalue = 0, | |
2705 | }, | |
2706 | /* per-timer control */ | |
2707 | { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
9ff9dd3c | 2708 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 2709 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
a7adc4b7 PM |
2710 | .accessfn = gt_ptimer_access, |
2711 | .fieldoffset = offsetoflow32(CPUARMState, | |
2712 | cp15.c14_timer[GTIMER_PHYS].ctl), | |
0e3eca4c | 2713 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, |
a7adc4b7 | 2714 | }, |
9c513e78 | 2715 | { .name = "CNTP_CTL_S", |
9ff9dd3c PM |
2716 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, |
2717 | .secure = ARM_CP_SECSTATE_S, | |
daf1dc5f | 2718 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
9ff9dd3c PM |
2719 | .accessfn = gt_ptimer_access, |
2720 | .fieldoffset = offsetoflow32(CPUARMState, | |
2721 | cp15.c14_timer[GTIMER_SEC].ctl), | |
2722 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
2723 | }, | |
a7adc4b7 PM |
2724 | { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, |
2725 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, | |
daf1dc5f | 2726 | .type = ARM_CP_IO, .access = PL0_RW, |
a7adc4b7 | 2727 | .accessfn = gt_ptimer_access, |
55d284af PM |
2728 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), |
2729 | .resetvalue = 0, | |
0e3eca4c | 2730 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
2731 | }, |
2732 | { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, | |
daf1dc5f | 2733 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
a7adc4b7 PM |
2734 | .accessfn = gt_vtimer_access, |
2735 | .fieldoffset = offsetoflow32(CPUARMState, | |
2736 | cp15.c14_timer[GTIMER_VIRT].ctl), | |
0e3eca4c | 2737 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, |
a7adc4b7 PM |
2738 | }, |
2739 | { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
2740 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, | |
daf1dc5f | 2741 | .type = ARM_CP_IO, .access = PL0_RW, |
a7adc4b7 | 2742 | .accessfn = gt_vtimer_access, |
55d284af PM |
2743 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), |
2744 | .resetvalue = 0, | |
0e3eca4c | 2745 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write, |
55d284af PM |
2746 | }, |
2747 | /* TimerValue views: a 32 bit downcounting view of the underlying state */ | |
2748 | { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
9ff9dd3c | 2749 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 2750 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
00108f2d | 2751 | .accessfn = gt_ptimer_access, |
0e3eca4c | 2752 | .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, |
55d284af | 2753 | }, |
9c513e78 | 2754 | { .name = "CNTP_TVAL_S", |
9ff9dd3c PM |
2755 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, |
2756 | .secure = ARM_CP_SECSTATE_S, | |
daf1dc5f | 2757 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
9ff9dd3c PM |
2758 | .accessfn = gt_ptimer_access, |
2759 | .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, | |
2760 | }, | |
a7adc4b7 PM |
2761 | { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
2762 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, | |
daf1dc5f | 2763 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
0e3eca4c EI |
2764 | .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, |
2765 | .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write, | |
a7adc4b7 | 2766 | }, |
55d284af | 2767 | { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, |
daf1dc5f | 2768 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
00108f2d | 2769 | .accessfn = gt_vtimer_access, |
0e3eca4c | 2770 | .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, |
55d284af | 2771 | }, |
a7adc4b7 PM |
2772 | { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
2773 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, | |
daf1dc5f | 2774 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
0e3eca4c EI |
2775 | .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, |
2776 | .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write, | |
a7adc4b7 | 2777 | }, |
55d284af PM |
2778 | /* The counter itself */ |
2779 | { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, | |
7a0e58fa | 2780 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 2781 | .accessfn = gt_pct_access, |
a7adc4b7 PM |
2782 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
2783 | }, | |
2784 | { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, | |
2785 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, | |
7a0e58fa | 2786 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 2787 | .accessfn = gt_pct_access, .readfn = gt_cnt_read, |
55d284af PM |
2788 | }, |
2789 | { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, | |
7a0e58fa | 2790 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 2791 | .accessfn = gt_vct_access, |
edac4d8a | 2792 | .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, |
a7adc4b7 PM |
2793 | }, |
2794 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
2795 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
7a0e58fa | 2796 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 2797 | .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, |
55d284af PM |
2798 | }, |
2799 | /* Comparison value, indicating when the timer goes off */ | |
2800 | { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, | |
9ff9dd3c | 2801 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 2802 | .access = PL0_RW, |
7a0e58fa | 2803 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 2804 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), |
b061a82b | 2805 | .accessfn = gt_ptimer_access, |
0e3eca4c | 2806 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write, |
a7adc4b7 | 2807 | }, |
9c513e78 | 2808 | { .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2, |
9ff9dd3c | 2809 | .secure = ARM_CP_SECSTATE_S, |
daf1dc5f | 2810 | .access = PL0_RW, |
9ff9dd3c PM |
2811 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
2812 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
2813 | .accessfn = gt_ptimer_access, | |
2814 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
2815 | }, | |
a7adc4b7 PM |
2816 | { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, |
2817 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, | |
daf1dc5f | 2818 | .access = PL0_RW, |
a7adc4b7 PM |
2819 | .type = ARM_CP_IO, |
2820 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
12cde08a | 2821 | .resetvalue = 0, .accessfn = gt_ptimer_access, |
0e3eca4c | 2822 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write, |
55d284af PM |
2823 | }, |
2824 | { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, | |
daf1dc5f | 2825 | .access = PL0_RW, |
7a0e58fa | 2826 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 2827 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), |
b061a82b | 2828 | .accessfn = gt_vtimer_access, |
0e3eca4c | 2829 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write, |
a7adc4b7 PM |
2830 | }, |
2831 | { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
2832 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, | |
daf1dc5f | 2833 | .access = PL0_RW, |
a7adc4b7 PM |
2834 | .type = ARM_CP_IO, |
2835 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
2836 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
0e3eca4c | 2837 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write, |
55d284af | 2838 | }, |
b4d3978c PM |
2839 | /* Secure timer -- this is actually restricted to only EL3 |
2840 | * and configurably Secure-EL1 via the accessfn. | |
2841 | */ | |
2842 | { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, | |
2843 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, | |
2844 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, | |
2845 | .accessfn = gt_stimer_access, | |
2846 | .readfn = gt_sec_tval_read, | |
2847 | .writefn = gt_sec_tval_write, | |
2848 | .resetfn = gt_sec_timer_reset, | |
2849 | }, | |
2850 | { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64, | |
2851 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1, | |
2852 | .type = ARM_CP_IO, .access = PL1_RW, | |
2853 | .accessfn = gt_stimer_access, | |
2854 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), | |
2855 | .resetvalue = 0, | |
2856 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
2857 | }, | |
2858 | { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, | |
2859 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, | |
2860 | .type = ARM_CP_IO, .access = PL1_RW, | |
2861 | .accessfn = gt_stimer_access, | |
2862 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
2863 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
2864 | }, | |
55d284af PM |
2865 | REGINFO_SENTINEL |
2866 | }; | |
2867 | ||
2868 | #else | |
26c4a83b AB |
2869 | |
2870 | /* In user-mode most of the generic timer registers are inaccessible | |
2871 | * however modern kernels (4.12+) allow access to cntvct_el0 | |
55d284af | 2872 | */ |
26c4a83b AB |
2873 | |
2874 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2875 | { | |
2876 | /* Currently we have no support for QEMUTimer in linux-user so we | |
2877 | * can't call gt_get_countervalue(env), instead we directly | |
2878 | * call the lower level functions. | |
2879 | */ | |
2880 | return cpu_get_clock() / GTIMER_SCALE; | |
2881 | } | |
2882 | ||
6cc7a3ae | 2883 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
26c4a83b AB |
2884 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, |
2885 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
2886 | .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */, | |
2887 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), | |
2888 | .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE, | |
2889 | }, | |
2890 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
2891 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
2892 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
2893 | .readfn = gt_virt_cnt_read, | |
2894 | }, | |
6cc7a3ae PM |
2895 | REGINFO_SENTINEL |
2896 | }; | |
2897 | ||
55d284af PM |
2898 | #endif |
2899 | ||
c4241c7d | 2900 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 2901 | { |
891a2fe7 | 2902 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8d5c773e | 2903 | raw_write(env, ri, value); |
891a2fe7 | 2904 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8d5c773e | 2905 | raw_write(env, ri, value & 0xfffff6ff); |
4a501606 | 2906 | } else { |
8d5c773e | 2907 | raw_write(env, ri, value & 0xfffff1ff); |
4a501606 | 2908 | } |
4a501606 PM |
2909 | } |
2910 | ||
2911 | #ifndef CONFIG_USER_ONLY | |
2912 | /* get_phys_addr() isn't present for user-mode-only targets */ | |
702a9357 | 2913 | |
3f208fd7 PM |
2914 | static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2915 | bool isread) | |
92611c00 PM |
2916 | { |
2917 | if (ri->opc2 & 4) { | |
87562e4f PM |
2918 | /* The ATS12NSO* operations must trap to EL3 if executed in |
2919 | * Secure EL1 (which can only happen if EL3 is AArch64). | |
2920 | * They are simply UNDEF if executed from NS EL1. | |
2921 | * They function normally from EL2 or EL3. | |
92611c00 | 2922 | */ |
87562e4f PM |
2923 | if (arm_current_el(env) == 1) { |
2924 | if (arm_is_secure_below_el3(env)) { | |
2925 | return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; | |
2926 | } | |
2927 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2928 | } | |
92611c00 PM |
2929 | } |
2930 | return CP_ACCESS_OK; | |
2931 | } | |
2932 | ||
060e8a48 | 2933 | static uint64_t do_ats_write(CPUARMState *env, uint64_t value, |
03ae85f8 | 2934 | MMUAccessType access_type, ARMMMUIdx mmu_idx) |
4a501606 | 2935 | { |
a8170e5e | 2936 | hwaddr phys_addr; |
4a501606 PM |
2937 | target_ulong page_size; |
2938 | int prot; | |
b7cc4e82 | 2939 | bool ret; |
01c097f7 | 2940 | uint64_t par64; |
1313e2d7 | 2941 | bool format64 = false; |
8bf5b6a9 | 2942 | MemTxAttrs attrs = {}; |
e14b5a23 | 2943 | ARMMMUFaultInfo fi = {}; |
5b2d261d | 2944 | ARMCacheAttrs cacheattrs = {}; |
4a501606 | 2945 | |
5b2d261d | 2946 | ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, |
bc52bfeb | 2947 | &prot, &page_size, &fi, &cacheattrs); |
1313e2d7 | 2948 | |
0710b2fa PM |
2949 | if (ret) { |
2950 | /* | |
2951 | * Some kinds of translation fault must cause exceptions rather | |
2952 | * than being reported in the PAR. | |
2953 | */ | |
2954 | int current_el = arm_current_el(env); | |
2955 | int target_el; | |
2956 | uint32_t syn, fsr, fsc; | |
2957 | bool take_exc = false; | |
2958 | ||
2959 | if (fi.s1ptw && current_el == 1 && !arm_is_secure(env) | |
2960 | && (mmu_idx == ARMMMUIdx_S1NSE1 || mmu_idx == ARMMMUIdx_S1NSE0)) { | |
2961 | /* | |
2962 | * Synchronous stage 2 fault on an access made as part of the | |
2963 | * translation table walk for AT S1E0* or AT S1E1* insn | |
2964 | * executed from NS EL1. If this is a synchronous external abort | |
2965 | * and SCR_EL3.EA == 1, then we take a synchronous external abort | |
2966 | * to EL3. Otherwise the fault is taken as an exception to EL2, | |
2967 | * and HPFAR_EL2 holds the faulting IPA. | |
2968 | */ | |
2969 | if (fi.type == ARMFault_SyncExternalOnWalk && | |
2970 | (env->cp15.scr_el3 & SCR_EA)) { | |
2971 | target_el = 3; | |
2972 | } else { | |
2973 | env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; | |
2974 | target_el = 2; | |
2975 | } | |
2976 | take_exc = true; | |
2977 | } else if (fi.type == ARMFault_SyncExternalOnWalk) { | |
2978 | /* | |
2979 | * Synchronous external aborts during a translation table walk | |
2980 | * are taken as Data Abort exceptions. | |
2981 | */ | |
2982 | if (fi.stage2) { | |
2983 | if (current_el == 3) { | |
2984 | target_el = 3; | |
2985 | } else { | |
2986 | target_el = 2; | |
2987 | } | |
2988 | } else { | |
2989 | target_el = exception_target_el(env); | |
2990 | } | |
2991 | take_exc = true; | |
2992 | } | |
2993 | ||
2994 | if (take_exc) { | |
2995 | /* Construct FSR and FSC using same logic as arm_deliver_fault() */ | |
2996 | if (target_el == 2 || arm_el_is_aa64(env, target_el) || | |
2997 | arm_s1_regime_using_lpae_format(env, mmu_idx)) { | |
2998 | fsr = arm_fi_to_lfsc(&fi); | |
2999 | fsc = extract32(fsr, 0, 6); | |
3000 | } else { | |
3001 | fsr = arm_fi_to_sfsc(&fi); | |
3002 | fsc = 0x3f; | |
3003 | } | |
3004 | /* | |
3005 | * Report exception with ESR indicating a fault due to a | |
3006 | * translation table walk for a cache maintenance instruction. | |
3007 | */ | |
3008 | syn = syn_data_abort_no_iss(current_el == target_el, | |
3009 | fi.ea, 1, fi.s1ptw, 1, fsc); | |
3010 | env->exception.vaddress = value; | |
3011 | env->exception.fsr = fsr; | |
3012 | raise_exception(env, EXCP_DATA_ABORT, syn, target_el); | |
3013 | } | |
3014 | } | |
3015 | ||
1313e2d7 EI |
3016 | if (is_a64(env)) { |
3017 | format64 = true; | |
3018 | } else if (arm_feature(env, ARM_FEATURE_LPAE)) { | |
3019 | /* | |
3020 | * ATS1Cxx: | |
3021 | * * TTBCR.EAE determines whether the result is returned using the | |
3022 | * 32-bit or the 64-bit PAR format | |
3023 | * * Instructions executed in Hyp mode always use the 64bit format | |
3024 | * | |
3025 | * ATS1S2NSOxx uses the 64bit format if any of the following is true: | |
3026 | * * The Non-secure TTBCR.EAE bit is set to 1 | |
3027 | * * The implementation includes EL2, and the value of HCR.VM is 1 | |
3028 | * | |
9d1bab33 PM |
3029 | * (Note that HCR.DC makes HCR.VM behave as if it is 1.) |
3030 | * | |
23463e0e | 3031 | * ATS1Hx always uses the 64bit format. |
1313e2d7 EI |
3032 | */ |
3033 | format64 = arm_s1_regime_using_lpae_format(env, mmu_idx); | |
3034 | ||
3035 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
3036 | if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { | |
9d1bab33 | 3037 | format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC); |
1313e2d7 EI |
3038 | } else { |
3039 | format64 |= arm_current_el(env) == 2; | |
3040 | } | |
3041 | } | |
3042 | } | |
3043 | ||
3044 | if (format64) { | |
5efe9ed4 | 3045 | /* Create a 64-bit PAR */ |
01c097f7 | 3046 | par64 = (1 << 11); /* LPAE bit always set */ |
b7cc4e82 | 3047 | if (!ret) { |
702a9357 | 3048 | par64 |= phys_addr & ~0xfffULL; |
8bf5b6a9 PM |
3049 | if (!attrs.secure) { |
3050 | par64 |= (1 << 9); /* NS */ | |
3051 | } | |
5b2d261d AB |
3052 | par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */ |
3053 | par64 |= cacheattrs.shareability << 7; /* SH */ | |
4a501606 | 3054 | } else { |
5efe9ed4 PM |
3055 | uint32_t fsr = arm_fi_to_lfsc(&fi); |
3056 | ||
702a9357 | 3057 | par64 |= 1; /* F */ |
b7cc4e82 | 3058 | par64 |= (fsr & 0x3f) << 1; /* FS */ |
0f7b791b PM |
3059 | if (fi.stage2) { |
3060 | par64 |= (1 << 9); /* S */ | |
3061 | } | |
3062 | if (fi.s1ptw) { | |
3063 | par64 |= (1 << 8); /* PTW */ | |
3064 | } | |
4a501606 PM |
3065 | } |
3066 | } else { | |
b7cc4e82 | 3067 | /* fsr is a DFSR/IFSR value for the short descriptor |
702a9357 PM |
3068 | * translation table format (with WnR always clear). |
3069 | * Convert it to a 32-bit PAR. | |
3070 | */ | |
b7cc4e82 | 3071 | if (!ret) { |
702a9357 PM |
3072 | /* We do not set any attribute bits in the PAR */ |
3073 | if (page_size == (1 << 24) | |
3074 | && arm_feature(env, ARM_FEATURE_V7)) { | |
01c097f7 | 3075 | par64 = (phys_addr & 0xff000000) | (1 << 1); |
702a9357 | 3076 | } else { |
01c097f7 | 3077 | par64 = phys_addr & 0xfffff000; |
702a9357 | 3078 | } |
8bf5b6a9 PM |
3079 | if (!attrs.secure) { |
3080 | par64 |= (1 << 9); /* NS */ | |
3081 | } | |
702a9357 | 3082 | } else { |
5efe9ed4 PM |
3083 | uint32_t fsr = arm_fi_to_sfsc(&fi); |
3084 | ||
b7cc4e82 PC |
3085 | par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | |
3086 | ((fsr & 0xf) << 1) | 1; | |
702a9357 | 3087 | } |
4a501606 | 3088 | } |
060e8a48 PM |
3089 | return par64; |
3090 | } | |
3091 | ||
3092 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | |
3093 | { | |
03ae85f8 | 3094 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
060e8a48 | 3095 | uint64_t par64; |
d3649702 PM |
3096 | ARMMMUIdx mmu_idx; |
3097 | int el = arm_current_el(env); | |
3098 | bool secure = arm_is_secure_below_el3(env); | |
060e8a48 | 3099 | |
d3649702 PM |
3100 | switch (ri->opc2 & 6) { |
3101 | case 0: | |
3102 | /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ | |
3103 | switch (el) { | |
3104 | case 3: | |
3105 | mmu_idx = ARMMMUIdx_S1E3; | |
3106 | break; | |
3107 | case 2: | |
3108 | mmu_idx = ARMMMUIdx_S1NSE1; | |
3109 | break; | |
3110 | case 1: | |
3111 | mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; | |
3112 | break; | |
3113 | default: | |
3114 | g_assert_not_reached(); | |
3115 | } | |
3116 | break; | |
3117 | case 2: | |
3118 | /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ | |
3119 | switch (el) { | |
3120 | case 3: | |
3121 | mmu_idx = ARMMMUIdx_S1SE0; | |
3122 | break; | |
3123 | case 2: | |
3124 | mmu_idx = ARMMMUIdx_S1NSE0; | |
3125 | break; | |
3126 | case 1: | |
3127 | mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; | |
3128 | break; | |
3129 | default: | |
3130 | g_assert_not_reached(); | |
3131 | } | |
3132 | break; | |
3133 | case 4: | |
3134 | /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ | |
3135 | mmu_idx = ARMMMUIdx_S12NSE1; | |
3136 | break; | |
3137 | case 6: | |
3138 | /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ | |
3139 | mmu_idx = ARMMMUIdx_S12NSE0; | |
3140 | break; | |
3141 | default: | |
3142 | g_assert_not_reached(); | |
3143 | } | |
3144 | ||
3145 | par64 = do_ats_write(env, value, access_type, mmu_idx); | |
01c097f7 FA |
3146 | |
3147 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
4a501606 | 3148 | } |
060e8a48 | 3149 | |
14db7fe0 PM |
3150 | static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3151 | uint64_t value) | |
3152 | { | |
03ae85f8 | 3153 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
14db7fe0 PM |
3154 | uint64_t par64; |
3155 | ||
23463e0e | 3156 | par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S1E2); |
14db7fe0 PM |
3157 | |
3158 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
3159 | } | |
3160 | ||
3f208fd7 PM |
3161 | static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3162 | bool isread) | |
2a47df95 PM |
3163 | { |
3164 | if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) { | |
3165 | return CP_ACCESS_TRAP; | |
3166 | } | |
3167 | return CP_ACCESS_OK; | |
3168 | } | |
3169 | ||
060e8a48 PM |
3170 | static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, |
3171 | uint64_t value) | |
3172 | { | |
03ae85f8 | 3173 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
d3649702 PM |
3174 | ARMMMUIdx mmu_idx; |
3175 | int secure = arm_is_secure_below_el3(env); | |
3176 | ||
3177 | switch (ri->opc2 & 6) { | |
3178 | case 0: | |
3179 | switch (ri->opc1) { | |
3180 | case 0: /* AT S1E1R, AT S1E1W */ | |
3181 | mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; | |
3182 | break; | |
3183 | case 4: /* AT S1E2R, AT S1E2W */ | |
3184 | mmu_idx = ARMMMUIdx_S1E2; | |
3185 | break; | |
3186 | case 6: /* AT S1E3R, AT S1E3W */ | |
3187 | mmu_idx = ARMMMUIdx_S1E3; | |
3188 | break; | |
3189 | default: | |
3190 | g_assert_not_reached(); | |
3191 | } | |
3192 | break; | |
3193 | case 2: /* AT S1E0R, AT S1E0W */ | |
3194 | mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; | |
3195 | break; | |
3196 | case 4: /* AT S12E1R, AT S12E1W */ | |
2a47df95 | 3197 | mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1; |
d3649702 PM |
3198 | break; |
3199 | case 6: /* AT S12E0R, AT S12E0W */ | |
2a47df95 | 3200 | mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0; |
d3649702 PM |
3201 | break; |
3202 | default: | |
3203 | g_assert_not_reached(); | |
3204 | } | |
060e8a48 | 3205 | |
d3649702 | 3206 | env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx); |
060e8a48 | 3207 | } |
4a501606 PM |
3208 | #endif |
3209 | ||
3210 | static const ARMCPRegInfo vapa_cp_reginfo[] = { | |
3211 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, | |
3212 | .access = PL1_RW, .resetvalue = 0, | |
01c097f7 FA |
3213 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), |
3214 | offsetoflow32(CPUARMState, cp15.par_ns) }, | |
4a501606 PM |
3215 | .writefn = par_write }, |
3216 | #ifndef CONFIG_USER_ONLY | |
87562e4f | 3217 | /* This underdecoding is safe because the reginfo is NO_RAW. */ |
4a501606 | 3218 | { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, |
92611c00 | 3219 | .access = PL1_W, .accessfn = ats_access, |
0710b2fa | 3220 | .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
4a501606 PM |
3221 | #endif |
3222 | REGINFO_SENTINEL | |
3223 | }; | |
3224 | ||
18032bec PM |
3225 | /* Return basic MPU access permission bits. */ |
3226 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
3227 | { | |
3228 | uint32_t ret; | |
3229 | uint32_t mask; | |
3230 | int i; | |
3231 | ret = 0; | |
3232 | mask = 3; | |
3233 | for (i = 0; i < 16; i += 2) { | |
3234 | ret |= (val >> i) & mask; | |
3235 | mask <<= 2; | |
3236 | } | |
3237 | return ret; | |
3238 | } | |
3239 | ||
3240 | /* Pad basic MPU access permission bits to extended format. */ | |
3241 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
3242 | { | |
3243 | uint32_t ret; | |
3244 | uint32_t mask; | |
3245 | int i; | |
3246 | ret = 0; | |
3247 | mask = 3; | |
3248 | for (i = 0; i < 16; i += 2) { | |
3249 | ret |= (val & mask) << i; | |
3250 | mask <<= 2; | |
3251 | } | |
3252 | return ret; | |
3253 | } | |
3254 | ||
c4241c7d PM |
3255 | static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3256 | uint64_t value) | |
18032bec | 3257 | { |
7e09797c | 3258 | env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3259 | } |
3260 | ||
c4241c7d | 3261 | static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3262 | { |
7e09797c | 3263 | return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); |
18032bec PM |
3264 | } |
3265 | ||
c4241c7d PM |
3266 | static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3267 | uint64_t value) | |
18032bec | 3268 | { |
7e09797c | 3269 | env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3270 | } |
3271 | ||
c4241c7d | 3272 | static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3273 | { |
7e09797c | 3274 | return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); |
18032bec PM |
3275 | } |
3276 | ||
6cb0b013 PC |
3277 | static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) |
3278 | { | |
3279 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); | |
3280 | ||
3281 | if (!u32p) { | |
3282 | return 0; | |
3283 | } | |
3284 | ||
1bc04a88 | 3285 | u32p += env->pmsav7.rnr[M_REG_NS]; |
6cb0b013 PC |
3286 | return *u32p; |
3287 | } | |
3288 | ||
3289 | static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3290 | uint64_t value) | |
3291 | { | |
2fc0cc0e | 3292 | ARMCPU *cpu = env_archcpu(env); |
6cb0b013 PC |
3293 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); |
3294 | ||
3295 | if (!u32p) { | |
3296 | return; | |
3297 | } | |
3298 | ||
1bc04a88 | 3299 | u32p += env->pmsav7.rnr[M_REG_NS]; |
d10eb08f | 3300 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ |
6cb0b013 PC |
3301 | *u32p = value; |
3302 | } | |
3303 | ||
6cb0b013 PC |
3304 | static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3305 | uint64_t value) | |
3306 | { | |
2fc0cc0e | 3307 | ARMCPU *cpu = env_archcpu(env); |
6cb0b013 PC |
3308 | uint32_t nrgs = cpu->pmsav7_dregion; |
3309 | ||
3310 | if (value >= nrgs) { | |
3311 | qemu_log_mask(LOG_GUEST_ERROR, | |
3312 | "PMSAv7 RGNR write >= # supported regions, %" PRIu32 | |
3313 | " > %" PRIu32 "\n", (uint32_t)value, nrgs); | |
3314 | return; | |
3315 | } | |
3316 | ||
3317 | raw_write(env, ri, value); | |
3318 | } | |
3319 | ||
3320 | static const ARMCPRegInfo pmsav7_cp_reginfo[] = { | |
69ceea64 PM |
3321 | /* Reset for all these registers is handled in arm_cpu_reset(), |
3322 | * because the PMSAv7 is also used by M-profile CPUs, which do | |
3323 | * not register cpregs but still need the state to be reset. | |
3324 | */ | |
6cb0b013 PC |
3325 | { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, |
3326 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3327 | .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), | |
69ceea64 PM |
3328 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3329 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3330 | { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, |
3331 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3332 | .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), | |
69ceea64 PM |
3333 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3334 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3335 | { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, |
3336 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
3337 | .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), | |
69ceea64 PM |
3338 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
3339 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3340 | { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, |
3341 | .access = PL1_RW, | |
1bc04a88 | 3342 | .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), |
69ceea64 PM |
3343 | .writefn = pmsav7_rgnr_write, |
3344 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
3345 | REGINFO_SENTINEL |
3346 | }; | |
3347 | ||
18032bec PM |
3348 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { |
3349 | { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 3350 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 3351 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
18032bec PM |
3352 | .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, |
3353 | { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 3354 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 3355 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
18032bec PM |
3356 | .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, |
3357 | { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, | |
3358 | .access = PL1_RW, | |
7e09797c PM |
3359 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
3360 | .resetvalue = 0, }, | |
18032bec PM |
3361 | { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, |
3362 | .access = PL1_RW, | |
7e09797c PM |
3363 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
3364 | .resetvalue = 0, }, | |
ecce5c3c PM |
3365 | { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
3366 | .access = PL1_RW, | |
3367 | .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, | |
3368 | { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
3369 | .access = PL1_RW, | |
3370 | .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, | |
06d76f31 | 3371 | /* Protection region base and size registers */ |
e508a92b PM |
3372 | { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, |
3373 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3374 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, | |
3375 | { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, | |
3376 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3377 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, | |
3378 | { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, | |
3379 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3380 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, | |
3381 | { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, | |
3382 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3383 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, | |
3384 | { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, | |
3385 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3386 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, | |
3387 | { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, | |
3388 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3389 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, | |
3390 | { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, | |
3391 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3392 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, | |
3393 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | |
3394 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
3395 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | |
18032bec PM |
3396 | REGINFO_SENTINEL |
3397 | }; | |
3398 | ||
c4241c7d PM |
3399 | static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3400 | uint64_t value) | |
ecce5c3c | 3401 | { |
11f136ee | 3402 | TCR *tcr = raw_ptr(env, ri); |
2ebcebe2 PM |
3403 | int maskshift = extract32(value, 0, 3); |
3404 | ||
e389be16 FA |
3405 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
3406 | if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { | |
3407 | /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when | |
3408 | * using Long-desciptor translation table format */ | |
3409 | value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); | |
3410 | } else if (arm_feature(env, ARM_FEATURE_EL3)) { | |
3411 | /* In an implementation that includes the Security Extensions | |
3412 | * TTBCR has additional fields PD0 [4] and PD1 [5] for | |
3413 | * Short-descriptor translation table format. | |
3414 | */ | |
3415 | value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; | |
3416 | } else { | |
3417 | value &= TTBCR_N; | |
3418 | } | |
e42c4db3 | 3419 | } |
e389be16 | 3420 | |
b6af0975 | 3421 | /* Update the masks corresponding to the TCR bank being written |
11f136ee | 3422 | * Note that we always calculate mask and base_mask, but |
e42c4db3 | 3423 | * they are only used for short-descriptor tables (ie if EAE is 0); |
11f136ee FA |
3424 | * for long-descriptor tables the TCR fields are used differently |
3425 | * and the mask and base_mask values are meaningless. | |
e42c4db3 | 3426 | */ |
11f136ee FA |
3427 | tcr->raw_tcr = value; |
3428 | tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift); | |
3429 | tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift); | |
ecce5c3c PM |
3430 | } |
3431 | ||
c4241c7d PM |
3432 | static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3433 | uint64_t value) | |
d4e6df63 | 3434 | { |
2fc0cc0e | 3435 | ARMCPU *cpu = env_archcpu(env); |
ab638a32 | 3436 | TCR *tcr = raw_ptr(env, ri); |
00c8cb0a | 3437 | |
d4e6df63 PM |
3438 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
3439 | /* With LPAE the TTBCR could result in a change of ASID | |
3440 | * via the TTBCR.A1 bit, so do a TLB flush. | |
3441 | */ | |
d10eb08f | 3442 | tlb_flush(CPU(cpu)); |
d4e6df63 | 3443 | } |
ab638a32 RH |
3444 | /* Preserve the high half of TCR_EL1, set via TTBCR2. */ |
3445 | value = deposit64(tcr->raw_tcr, 0, 32, value); | |
c4241c7d | 3446 | vmsa_ttbcr_raw_write(env, ri, value); |
d4e6df63 PM |
3447 | } |
3448 | ||
ecce5c3c PM |
3449 | static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
3450 | { | |
11f136ee FA |
3451 | TCR *tcr = raw_ptr(env, ri); |
3452 | ||
3453 | /* Reset both the TCR as well as the masks corresponding to the bank of | |
3454 | * the TCR being reset. | |
3455 | */ | |
3456 | tcr->raw_tcr = 0; | |
3457 | tcr->mask = 0; | |
3458 | tcr->base_mask = 0xffffc000u; | |
ecce5c3c PM |
3459 | } |
3460 | ||
cb2e37df PM |
3461 | static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3462 | uint64_t value) | |
3463 | { | |
2fc0cc0e | 3464 | ARMCPU *cpu = env_archcpu(env); |
11f136ee | 3465 | TCR *tcr = raw_ptr(env, ri); |
00c8cb0a | 3466 | |
cb2e37df | 3467 | /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ |
d10eb08f | 3468 | tlb_flush(CPU(cpu)); |
11f136ee | 3469 | tcr->raw_tcr = value; |
cb2e37df PM |
3470 | } |
3471 | ||
327ed10f PM |
3472 | static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3473 | uint64_t value) | |
3474 | { | |
93f379b0 RH |
3475 | /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ |
3476 | if (cpreg_field_is_64bit(ri) && | |
3477 | extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { | |
2fc0cc0e | 3478 | ARMCPU *cpu = env_archcpu(env); |
d10eb08f | 3479 | tlb_flush(CPU(cpu)); |
327ed10f PM |
3480 | } |
3481 | raw_write(env, ri, value); | |
3482 | } | |
3483 | ||
b698e9cf EI |
3484 | static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3485 | uint64_t value) | |
3486 | { | |
2fc0cc0e | 3487 | ARMCPU *cpu = env_archcpu(env); |
b698e9cf EI |
3488 | CPUState *cs = CPU(cpu); |
3489 | ||
3490 | /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ | |
3491 | if (raw_read(env, ri) != value) { | |
0336cbf8 | 3492 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
3493 | ARMMMUIdxBit_S12NSE1 | |
3494 | ARMMMUIdxBit_S12NSE0 | | |
3495 | ARMMMUIdxBit_S2NS); | |
b698e9cf EI |
3496 | raw_write(env, ri, value); |
3497 | } | |
3498 | } | |
3499 | ||
8e5d75c9 | 3500 | static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { |
18032bec | 3501 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, |
7a0e58fa | 3502 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
4a7e2d73 | 3503 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), |
b061a82b | 3504 | offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, |
18032bec | 3505 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, |
88ca1c2d FA |
3506 | .access = PL1_RW, .resetvalue = 0, |
3507 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), | |
3508 | offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, | |
8e5d75c9 PC |
3509 | { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, |
3510 | .access = PL1_RW, .resetvalue = 0, | |
3511 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), | |
3512 | offsetof(CPUARMState, cp15.dfar_ns) } }, | |
3513 | { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, | |
3514 | .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, | |
3515 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), | |
3516 | .resetvalue = 0, }, | |
3517 | REGINFO_SENTINEL | |
3518 | }; | |
3519 | ||
3520 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { | |
6cd8a264 RH |
3521 | { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, |
3522 | .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, | |
3523 | .access = PL1_RW, | |
d81c519c | 3524 | .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, |
327ed10f | 3525 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af FA |
3526 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, |
3527 | .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
3528 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), | |
3529 | offsetof(CPUARMState, cp15.ttbr0_ns) } }, | |
327ed10f | 3530 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af FA |
3531 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, |
3532 | .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, | |
3533 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), | |
3534 | offsetof(CPUARMState, cp15.ttbr1_ns) } }, | |
cb2e37df PM |
3535 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, |
3536 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | |
3537 | .access = PL1_RW, .writefn = vmsa_tcr_el1_write, | |
3538 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, | |
11f136ee | 3539 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, |
cb2e37df | 3540 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
7a0e58fa | 3541 | .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, |
b061a82b | 3542 | .raw_writefn = vmsa_ttbcr_raw_write, |
11f136ee FA |
3543 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), |
3544 | offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, | |
18032bec PM |
3545 | REGINFO_SENTINEL |
3546 | }; | |
3547 | ||
ab638a32 RH |
3548 | /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing |
3549 | * qemu tlbs nor adjusting cached masks. | |
3550 | */ | |
3551 | static const ARMCPRegInfo ttbcr2_reginfo = { | |
3552 | .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3, | |
3553 | .access = PL1_RW, .type = ARM_CP_ALIAS, | |
3554 | .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), | |
3555 | offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, | |
3556 | }; | |
3557 | ||
c4241c7d PM |
3558 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3559 | uint64_t value) | |
1047b9d7 PM |
3560 | { |
3561 | env->cp15.c15_ticonfig = value & 0xe7; | |
3562 | /* The OS_TYPE bit in this register changes the reported CPUID! */ | |
3563 | env->cp15.c0_cpuid = (value & (1 << 5)) ? | |
3564 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1047b9d7 PM |
3565 | } |
3566 | ||
c4241c7d PM |
3567 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3568 | uint64_t value) | |
1047b9d7 PM |
3569 | { |
3570 | env->cp15.c15_threadid = value & 0xffff; | |
1047b9d7 PM |
3571 | } |
3572 | ||
c4241c7d PM |
3573 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3574 | uint64_t value) | |
1047b9d7 PM |
3575 | { |
3576 | /* Wait-for-interrupt (deprecated) */ | |
2fc0cc0e | 3577 | cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); |
1047b9d7 PM |
3578 | } |
3579 | ||
c4241c7d PM |
3580 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3581 | uint64_t value) | |
c4804214 PM |
3582 | { |
3583 | /* On OMAP there are registers indicating the max/min index of dcache lines | |
3584 | * containing a dirty line; cache flush operations have to reset these. | |
3585 | */ | |
3586 | env->cp15.c15_i_max = 0x000; | |
3587 | env->cp15.c15_i_min = 0xff0; | |
c4804214 PM |
3588 | } |
3589 | ||
18032bec PM |
3590 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
3591 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, | |
3592 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, | |
d81c519c | 3593 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 3594 | .resetvalue = 0, }, |
1047b9d7 PM |
3595 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
3596 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
3597 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
3598 | .access = PL1_RW, | |
3599 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, | |
3600 | .writefn = omap_ticonfig_write }, | |
3601 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, | |
3602 | .access = PL1_RW, | |
3603 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, | |
3604 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, | |
3605 | .access = PL1_RW, .resetvalue = 0xff0, | |
3606 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, | |
3607 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, | |
3608 | .access = PL1_RW, | |
3609 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, | |
3610 | .writefn = omap_threadid_write }, | |
3611 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, | |
3612 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
7a0e58fa | 3613 | .type = ARM_CP_NO_RAW, |
1047b9d7 PM |
3614 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
3615 | /* TODO: Peripheral port remap register: | |
3616 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller | |
3617 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), | |
3618 | * when MMU is off. | |
3619 | */ | |
c4804214 | 3620 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
d4e6df63 | 3621 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
7a0e58fa | 3622 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, |
c4804214 | 3623 | .writefn = omap_cachemaint_write }, |
34f90529 PM |
3624 | { .name = "C9", .cp = 15, .crn = 9, |
3625 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | |
3626 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | |
1047b9d7 PM |
3627 | REGINFO_SENTINEL |
3628 | }; | |
3629 | ||
c4241c7d PM |
3630 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3631 | uint64_t value) | |
1047b9d7 | 3632 | { |
c0f4af17 | 3633 | env->cp15.c15_cpar = value & 0x3fff; |
1047b9d7 PM |
3634 | } |
3635 | ||
3636 | static const ARMCPRegInfo xscale_cp_reginfo[] = { | |
3637 | { .name = "XSCALE_CPAR", | |
3638 | .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
3639 | .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, | |
3640 | .writefn = xscale_cpar_write, }, | |
2771db27 PM |
3641 | { .name = "XSCALE_AUXCR", |
3642 | .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, | |
3643 | .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), | |
3644 | .resetvalue = 0, }, | |
3b771579 PM |
3645 | /* XScale specific cache-lockdown: since we have no cache we NOP these |
3646 | * and hope the guest does not really rely on cache behaviour. | |
3647 | */ | |
3648 | { .name = "XSCALE_LOCK_ICACHE_LINE", | |
3649 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
3650 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3651 | { .name = "XSCALE_UNLOCK_ICACHE", | |
3652 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
3653 | .access = PL1_W, .type = ARM_CP_NOP }, | |
3654 | { .name = "XSCALE_DCACHE_LOCK", | |
3655 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, | |
3656 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
3657 | { .name = "XSCALE_UNLOCK_DCACHE", | |
3658 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, | |
3659 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1047b9d7 PM |
3660 | REGINFO_SENTINEL |
3661 | }; | |
3662 | ||
3663 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | |
3664 | /* RAZ/WI the whole crn=15 space, when we don't have a more specific | |
3665 | * implementation of this implementation-defined space. | |
3666 | * Ideally this should eventually disappear in favour of actually | |
3667 | * implementing the correct behaviour for all cores. | |
3668 | */ | |
3669 | { .name = "C15_IMPDEF", .cp = 15, .crn = 15, | |
3670 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
3671cd87 | 3671 | .access = PL1_RW, |
7a0e58fa | 3672 | .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, |
d4e6df63 | 3673 | .resetvalue = 0 }, |
18032bec PM |
3674 | REGINFO_SENTINEL |
3675 | }; | |
3676 | ||
c4804214 PM |
3677 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
3678 | /* Cache status: RAZ because we have no cache so it's always clean */ | |
3679 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | |
7a0e58fa | 3680 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 3681 | .resetvalue = 0 }, |
c4804214 PM |
3682 | REGINFO_SENTINEL |
3683 | }; | |
3684 | ||
3685 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | |
3686 | /* We never have a a block transfer operation in progress */ | |
3687 | { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, | |
7a0e58fa | 3688 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 3689 | .resetvalue = 0 }, |
30b05bba PM |
3690 | /* The cache ops themselves: these all NOP for QEMU */ |
3691 | { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, | |
3692 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3693 | { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, | |
3694 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3695 | { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, | |
3696 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3697 | { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, | |
3698 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3699 | { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, | |
3700 | .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
3701 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, | |
3702 | .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, | |
c4804214 PM |
3703 | REGINFO_SENTINEL |
3704 | }; | |
3705 | ||
3706 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | |
3707 | /* The cache test-and-clean instructions always return (1 << 30) | |
3708 | * to indicate that there are no dirty cache lines. | |
3709 | */ | |
3710 | { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, | |
7a0e58fa | 3711 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 3712 | .resetvalue = (1 << 30) }, |
c4804214 | 3713 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
7a0e58fa | 3714 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 3715 | .resetvalue = (1 << 30) }, |
c4804214 PM |
3716 | REGINFO_SENTINEL |
3717 | }; | |
3718 | ||
34f90529 PM |
3719 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
3720 | /* Ignore ReadBuffer accesses */ | |
3721 | { .name = "C9_READBUFFER", .cp = 15, .crn = 9, | |
3722 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
d4e6df63 | 3723 | .access = PL1_RW, .resetvalue = 0, |
7a0e58fa | 3724 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, |
34f90529 PM |
3725 | REGINFO_SENTINEL |
3726 | }; | |
3727 | ||
731de9e6 EI |
3728 | static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
3729 | { | |
2fc0cc0e | 3730 | ARMCPU *cpu = env_archcpu(env); |
731de9e6 EI |
3731 | unsigned int cur_el = arm_current_el(env); |
3732 | bool secure = arm_is_secure(env); | |
3733 | ||
3734 | if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { | |
3735 | return env->cp15.vpidr_el2; | |
3736 | } | |
3737 | return raw_read(env, ri); | |
3738 | } | |
3739 | ||
06a7e647 | 3740 | static uint64_t mpidr_read_val(CPUARMState *env) |
81bdde9d | 3741 | { |
2fc0cc0e | 3742 | ARMCPU *cpu = env_archcpu(env); |
eb5e1d3c PF |
3743 | uint64_t mpidr = cpu->mp_affinity; |
3744 | ||
81bdde9d | 3745 | if (arm_feature(env, ARM_FEATURE_V7MP)) { |
78dbbbe4 | 3746 | mpidr |= (1U << 31); |
81bdde9d PM |
3747 | /* Cores which are uniprocessor (non-coherent) |
3748 | * but still implement the MP extensions set | |
a8e81b31 | 3749 | * bit 30. (For instance, Cortex-R5). |
81bdde9d | 3750 | */ |
a8e81b31 PC |
3751 | if (cpu->mp_is_up) { |
3752 | mpidr |= (1u << 30); | |
3753 | } | |
81bdde9d | 3754 | } |
c4241c7d | 3755 | return mpidr; |
81bdde9d PM |
3756 | } |
3757 | ||
06a7e647 EI |
3758 | static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
3759 | { | |
f0d574d6 EI |
3760 | unsigned int cur_el = arm_current_el(env); |
3761 | bool secure = arm_is_secure(env); | |
3762 | ||
3763 | if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) { | |
3764 | return env->cp15.vmpidr_el2; | |
3765 | } | |
06a7e647 EI |
3766 | return mpidr_read_val(env); |
3767 | } | |
3768 | ||
7ac681cf | 3769 | static const ARMCPRegInfo lpae_cp_reginfo[] = { |
a903c449 | 3770 | /* NOP AMAIR0/1 */ |
b0fe2427 PM |
3771 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, |
3772 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | |
a903c449 | 3773 | .access = PL1_RW, .type = ARM_CP_CONST, |
7ac681cf | 3774 | .resetvalue = 0 }, |
b0fe2427 | 3775 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ |
7ac681cf | 3776 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
a903c449 | 3777 | .access = PL1_RW, .type = ARM_CP_CONST, |
7ac681cf | 3778 | .resetvalue = 0 }, |
891a2fe7 | 3779 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
01c097f7 FA |
3780 | .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, |
3781 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), | |
3782 | offsetof(CPUARMState, cp15.par_ns)} }, | |
891a2fe7 | 3783 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, |
7a0e58fa | 3784 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, |
7dd8c9af FA |
3785 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
3786 | offsetof(CPUARMState, cp15.ttbr0_ns) }, | |
b061a82b | 3787 | .writefn = vmsa_ttbr_write, }, |
891a2fe7 | 3788 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
7a0e58fa | 3789 | .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, |
7dd8c9af FA |
3790 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
3791 | offsetof(CPUARMState, cp15.ttbr1_ns) }, | |
b061a82b | 3792 | .writefn = vmsa_ttbr_write, }, |
7ac681cf PM |
3793 | REGINFO_SENTINEL |
3794 | }; | |
3795 | ||
c4241c7d | 3796 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 3797 | { |
c4241c7d | 3798 | return vfp_get_fpcr(env); |
b0d2b7d0 PM |
3799 | } |
3800 | ||
c4241c7d PM |
3801 | static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3802 | uint64_t value) | |
b0d2b7d0 PM |
3803 | { |
3804 | vfp_set_fpcr(env, value); | |
b0d2b7d0 PM |
3805 | } |
3806 | ||
c4241c7d | 3807 | static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 3808 | { |
c4241c7d | 3809 | return vfp_get_fpsr(env); |
b0d2b7d0 PM |
3810 | } |
3811 | ||
c4241c7d PM |
3812 | static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3813 | uint64_t value) | |
b0d2b7d0 PM |
3814 | { |
3815 | vfp_set_fpsr(env, value); | |
b0d2b7d0 PM |
3816 | } |
3817 | ||
3f208fd7 PM |
3818 | static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3819 | bool isread) | |
c2b820fe | 3820 | { |
137feaa9 | 3821 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { |
c2b820fe PM |
3822 | return CP_ACCESS_TRAP; |
3823 | } | |
3824 | return CP_ACCESS_OK; | |
3825 | } | |
3826 | ||
3827 | static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3828 | uint64_t value) | |
3829 | { | |
3830 | env->daif = value & PSTATE_DAIF; | |
3831 | } | |
3832 | ||
8af35c37 | 3833 | static CPAccessResult aa64_cacheop_access(CPUARMState *env, |
3f208fd7 PM |
3834 | const ARMCPRegInfo *ri, |
3835 | bool isread) | |
8af35c37 PM |
3836 | { |
3837 | /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless | |
3838 | * SCTLR_EL1.UCI is set. | |
3839 | */ | |
137feaa9 | 3840 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) { |
8af35c37 PM |
3841 | return CP_ACCESS_TRAP; |
3842 | } | |
3843 | return CP_ACCESS_OK; | |
3844 | } | |
3845 | ||
dbb1fb27 AB |
3846 | /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions |
3847 | * Page D4-1736 (DDI0487A.b) | |
3848 | */ | |
3849 | ||
fd3ed969 PM |
3850 | static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3851 | uint64_t value) | |
168aa23b | 3852 | { |
29a0af61 | 3853 | CPUState *cs = env_cpu(env); |
fd3ed969 | 3854 | bool sec = arm_is_secure_below_el3(env); |
dbb1fb27 | 3855 | |
a67cf277 AB |
3856 | if (sec) { |
3857 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3858 | ARMMMUIdxBit_S1SE1 | |
3859 | ARMMMUIdxBit_S1SE0); | |
a67cf277 AB |
3860 | } else { |
3861 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3862 | ARMMMUIdxBit_S12NSE1 | |
3863 | ARMMMUIdxBit_S12NSE0); | |
fd3ed969 | 3864 | } |
168aa23b PM |
3865 | } |
3866 | ||
b4ab8ce9 PM |
3867 | static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3868 | uint64_t value) | |
3869 | { | |
29a0af61 | 3870 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
3871 | |
3872 | if (tlb_force_broadcast(env)) { | |
09a86dfa | 3873 | tlbi_aa64_vmalle1is_write(env, NULL, value); |
b4ab8ce9 PM |
3874 | return; |
3875 | } | |
3876 | ||
3877 | if (arm_is_secure_below_el3(env)) { | |
3878 | tlb_flush_by_mmuidx(cs, | |
3879 | ARMMMUIdxBit_S1SE1 | | |
3880 | ARMMMUIdxBit_S1SE0); | |
3881 | } else { | |
3882 | tlb_flush_by_mmuidx(cs, | |
3883 | ARMMMUIdxBit_S12NSE1 | | |
3884 | ARMMMUIdxBit_S12NSE0); | |
3885 | } | |
3886 | } | |
3887 | ||
fd3ed969 PM |
3888 | static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3889 | uint64_t value) | |
168aa23b | 3890 | { |
fd3ed969 PM |
3891 | /* Note that the 'ALL' scope must invalidate both stage 1 and |
3892 | * stage 2 translations, whereas most other scopes only invalidate | |
3893 | * stage 1 translations. | |
3894 | */ | |
2fc0cc0e | 3895 | ARMCPU *cpu = env_archcpu(env); |
fd3ed969 PM |
3896 | CPUState *cs = CPU(cpu); |
3897 | ||
3898 | if (arm_is_secure_below_el3(env)) { | |
0336cbf8 | 3899 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
3900 | ARMMMUIdxBit_S1SE1 | |
3901 | ARMMMUIdxBit_S1SE0); | |
fd3ed969 PM |
3902 | } else { |
3903 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
0336cbf8 | 3904 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
3905 | ARMMMUIdxBit_S12NSE1 | |
3906 | ARMMMUIdxBit_S12NSE0 | | |
3907 | ARMMMUIdxBit_S2NS); | |
fd3ed969 | 3908 | } else { |
0336cbf8 | 3909 | tlb_flush_by_mmuidx(cs, |
8bd5c820 PM |
3910 | ARMMMUIdxBit_S12NSE1 | |
3911 | ARMMMUIdxBit_S12NSE0); | |
fd3ed969 PM |
3912 | } |
3913 | } | |
168aa23b PM |
3914 | } |
3915 | ||
fd3ed969 | 3916 | static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
fa439fc5 PM |
3917 | uint64_t value) |
3918 | { | |
2fc0cc0e | 3919 | ARMCPU *cpu = env_archcpu(env); |
fd3ed969 PM |
3920 | CPUState *cs = CPU(cpu); |
3921 | ||
8bd5c820 | 3922 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); |
fd3ed969 PM |
3923 | } |
3924 | ||
43efaa33 PM |
3925 | static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3926 | uint64_t value) | |
3927 | { | |
2fc0cc0e | 3928 | ARMCPU *cpu = env_archcpu(env); |
43efaa33 PM |
3929 | CPUState *cs = CPU(cpu); |
3930 | ||
8bd5c820 | 3931 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3); |
43efaa33 PM |
3932 | } |
3933 | ||
fd3ed969 PM |
3934 | static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3935 | uint64_t value) | |
3936 | { | |
3937 | /* Note that the 'ALL' scope must invalidate both stage 1 and | |
3938 | * stage 2 translations, whereas most other scopes only invalidate | |
3939 | * stage 1 translations. | |
3940 | */ | |
29a0af61 | 3941 | CPUState *cs = env_cpu(env); |
fd3ed969 PM |
3942 | bool sec = arm_is_secure_below_el3(env); |
3943 | bool has_el2 = arm_feature(env, ARM_FEATURE_EL2); | |
a67cf277 AB |
3944 | |
3945 | if (sec) { | |
3946 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3947 | ARMMMUIdxBit_S1SE1 | |
3948 | ARMMMUIdxBit_S1SE0); | |
a67cf277 AB |
3949 | } else if (has_el2) { |
3950 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3951 | ARMMMUIdxBit_S12NSE1 | |
3952 | ARMMMUIdxBit_S12NSE0 | | |
3953 | ARMMMUIdxBit_S2NS); | |
a67cf277 AB |
3954 | } else { |
3955 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | |
8bd5c820 PM |
3956 | ARMMMUIdxBit_S12NSE1 | |
3957 | ARMMMUIdxBit_S12NSE0); | |
fa439fc5 PM |
3958 | } |
3959 | } | |
3960 | ||
2bfb9d75 PM |
3961 | static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3962 | uint64_t value) | |
3963 | { | |
29a0af61 | 3964 | CPUState *cs = env_cpu(env); |
2bfb9d75 | 3965 | |
8bd5c820 | 3966 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2); |
2bfb9d75 PM |
3967 | } |
3968 | ||
43efaa33 PM |
3969 | static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3970 | uint64_t value) | |
3971 | { | |
29a0af61 | 3972 | CPUState *cs = env_cpu(env); |
43efaa33 | 3973 | |
8bd5c820 | 3974 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3); |
43efaa33 PM |
3975 | } |
3976 | ||
fd3ed969 PM |
3977 | static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3978 | uint64_t value) | |
fa439fc5 | 3979 | { |
fd3ed969 PM |
3980 | /* Invalidate by VA, EL2 |
3981 | * Currently handles both VAE2 and VALE2, since we don't support | |
3982 | * flush-last-level-only. | |
3983 | */ | |
2fc0cc0e | 3984 | ARMCPU *cpu = env_archcpu(env); |
fd3ed969 PM |
3985 | CPUState *cs = CPU(cpu); |
3986 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
3987 | ||
8bd5c820 | 3988 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2); |
fd3ed969 PM |
3989 | } |
3990 | ||
43efaa33 PM |
3991 | static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3992 | uint64_t value) | |
3993 | { | |
3994 | /* Invalidate by VA, EL3 | |
3995 | * Currently handles both VAE3 and VALE3, since we don't support | |
3996 | * flush-last-level-only. | |
3997 | */ | |
2fc0cc0e | 3998 | ARMCPU *cpu = env_archcpu(env); |
43efaa33 PM |
3999 | CPUState *cs = CPU(cpu); |
4000 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
4001 | ||
8bd5c820 | 4002 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3); |
43efaa33 PM |
4003 | } |
4004 | ||
fd3ed969 PM |
4005 | static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4006 | uint64_t value) | |
4007 | { | |
2fc0cc0e | 4008 | ARMCPU *cpu = env_archcpu(env); |
a67cf277 | 4009 | CPUState *cs = CPU(cpu); |
fd3ed969 | 4010 | bool sec = arm_is_secure_below_el3(env); |
fa439fc5 PM |
4011 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
4012 | ||
a67cf277 AB |
4013 | if (sec) { |
4014 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, | |
8bd5c820 PM |
4015 | ARMMMUIdxBit_S1SE1 | |
4016 | ARMMMUIdxBit_S1SE0); | |
a67cf277 AB |
4017 | } else { |
4018 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, | |
8bd5c820 PM |
4019 | ARMMMUIdxBit_S12NSE1 | |
4020 | ARMMMUIdxBit_S12NSE0); | |
fa439fc5 PM |
4021 | } |
4022 | } | |
4023 | ||
b4ab8ce9 PM |
4024 | static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4025 | uint64_t value) | |
4026 | { | |
4027 | /* Invalidate by VA, EL1&0 (AArch64 version). | |
4028 | * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, | |
4029 | * since we don't support flush-for-specific-ASID-only or | |
4030 | * flush-last-level-only. | |
4031 | */ | |
2fc0cc0e | 4032 | ARMCPU *cpu = env_archcpu(env); |
b4ab8ce9 PM |
4033 | CPUState *cs = CPU(cpu); |
4034 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
4035 | ||
4036 | if (tlb_force_broadcast(env)) { | |
4037 | tlbi_aa64_vae1is_write(env, NULL, value); | |
4038 | return; | |
4039 | } | |
4040 | ||
4041 | if (arm_is_secure_below_el3(env)) { | |
4042 | tlb_flush_page_by_mmuidx(cs, pageaddr, | |
4043 | ARMMMUIdxBit_S1SE1 | | |
4044 | ARMMMUIdxBit_S1SE0); | |
4045 | } else { | |
4046 | tlb_flush_page_by_mmuidx(cs, pageaddr, | |
4047 | ARMMMUIdxBit_S12NSE1 | | |
4048 | ARMMMUIdxBit_S12NSE0); | |
4049 | } | |
4050 | } | |
4051 | ||
fd3ed969 PM |
4052 | static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4053 | uint64_t value) | |
fa439fc5 | 4054 | { |
29a0af61 | 4055 | CPUState *cs = env_cpu(env); |
fd3ed969 | 4056 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
fa439fc5 | 4057 | |
a67cf277 | 4058 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 4059 | ARMMMUIdxBit_S1E2); |
fa439fc5 PM |
4060 | } |
4061 | ||
43efaa33 PM |
4062 | static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4063 | uint64_t value) | |
4064 | { | |
29a0af61 | 4065 | CPUState *cs = env_cpu(env); |
43efaa33 PM |
4066 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
4067 | ||
a67cf277 | 4068 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 4069 | ARMMMUIdxBit_S1E3); |
43efaa33 PM |
4070 | } |
4071 | ||
cea66e91 PM |
4072 | static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4073 | uint64_t value) | |
4074 | { | |
4075 | /* Invalidate by IPA. This has to invalidate any structures that | |
4076 | * contain only stage 2 translation information, but does not need | |
4077 | * to apply to structures that contain combined stage 1 and stage 2 | |
4078 | * translation information. | |
4079 | * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. | |
4080 | */ | |
2fc0cc0e | 4081 | ARMCPU *cpu = env_archcpu(env); |
cea66e91 PM |
4082 | CPUState *cs = CPU(cpu); |
4083 | uint64_t pageaddr; | |
4084 | ||
4085 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
4086 | return; | |
4087 | } | |
4088 | ||
4089 | pageaddr = sextract64(value << 12, 0, 48); | |
4090 | ||
8bd5c820 | 4091 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S2NS); |
cea66e91 PM |
4092 | } |
4093 | ||
4094 | static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4095 | uint64_t value) | |
4096 | { | |
29a0af61 | 4097 | CPUState *cs = env_cpu(env); |
cea66e91 PM |
4098 | uint64_t pageaddr; |
4099 | ||
4100 | if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | |
4101 | return; | |
4102 | } | |
4103 | ||
4104 | pageaddr = sextract64(value << 12, 0, 48); | |
4105 | ||
a67cf277 | 4106 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
8bd5c820 | 4107 | ARMMMUIdxBit_S2NS); |
cea66e91 PM |
4108 | } |
4109 | ||
3f208fd7 PM |
4110 | static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4111 | bool isread) | |
aca3f40b PM |
4112 | { |
4113 | /* We don't implement EL2, so the only control on DC ZVA is the | |
4114 | * bit in the SCTLR which can prohibit access for EL0. | |
4115 | */ | |
137feaa9 | 4116 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) { |
aca3f40b PM |
4117 | return CP_ACCESS_TRAP; |
4118 | } | |
4119 | return CP_ACCESS_OK; | |
4120 | } | |
4121 | ||
4122 | static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
4123 | { | |
2fc0cc0e | 4124 | ARMCPU *cpu = env_archcpu(env); |
aca3f40b PM |
4125 | int dzp_bit = 1 << 4; |
4126 | ||
4127 | /* DZP indicates whether DC ZVA access is allowed */ | |
3f208fd7 | 4128 | if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) { |
aca3f40b PM |
4129 | dzp_bit = 0; |
4130 | } | |
4131 | return cpu->dcz_blocksize | dzp_bit; | |
4132 | } | |
4133 | ||
3f208fd7 PM |
4134 | static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4135 | bool isread) | |
f502cfc2 | 4136 | { |
cdcf1405 | 4137 | if (!(env->pstate & PSTATE_SP)) { |
f502cfc2 PM |
4138 | /* Access to SP_EL0 is undefined if it's being used as |
4139 | * the stack pointer. | |
4140 | */ | |
4141 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
4142 | } | |
4143 | return CP_ACCESS_OK; | |
4144 | } | |
4145 | ||
4146 | static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
4147 | { | |
4148 | return env->pstate & PSTATE_SP; | |
4149 | } | |
4150 | ||
4151 | static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
4152 | { | |
4153 | update_spsel(env, val); | |
4154 | } | |
4155 | ||
137feaa9 FA |
4156 | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4157 | uint64_t value) | |
4158 | { | |
2fc0cc0e | 4159 | ARMCPU *cpu = env_archcpu(env); |
137feaa9 FA |
4160 | |
4161 | if (raw_read(env, ri) == value) { | |
4162 | /* Skip the TLB flush if nothing actually changed; Linux likes | |
4163 | * to do a lot of pointless SCTLR writes. | |
4164 | */ | |
4165 | return; | |
4166 | } | |
4167 | ||
06312feb PM |
4168 | if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { |
4169 | /* M bit is RAZ/WI for PMSA with no MPU implemented */ | |
4170 | value &= ~SCTLR_M; | |
4171 | } | |
4172 | ||
137feaa9 FA |
4173 | raw_write(env, ri, value); |
4174 | /* ??? Lots of these bits are not implemented. */ | |
4175 | /* This may enable/disable the MMU, so do a TLB flush. */ | |
d10eb08f | 4176 | tlb_flush(CPU(cpu)); |
137feaa9 FA |
4177 | } |
4178 | ||
3f208fd7 PM |
4179 | static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4180 | bool isread) | |
03fbf20f PM |
4181 | { |
4182 | if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { | |
f2cae609 | 4183 | return CP_ACCESS_TRAP_FP_EL2; |
03fbf20f PM |
4184 | } |
4185 | if (env->cp15.cptr_el[3] & CPTR_TFP) { | |
f2cae609 | 4186 | return CP_ACCESS_TRAP_FP_EL3; |
03fbf20f PM |
4187 | } |
4188 | return CP_ACCESS_OK; | |
4189 | } | |
4190 | ||
a8d64e73 PM |
4191 | static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4192 | uint64_t value) | |
4193 | { | |
4194 | env->cp15.mdcr_el3 = value & SDCR_VALID_MASK; | |
4195 | } | |
4196 | ||
b0d2b7d0 PM |
4197 | static const ARMCPRegInfo v8_cp_reginfo[] = { |
4198 | /* Minimal set of EL0-visible registers. This will need to be expanded | |
4199 | * significantly for system emulation of AArch64 CPUs. | |
4200 | */ | |
4201 | { .name = "NZCV", .state = ARM_CP_STATE_AA64, | |
4202 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, | |
4203 | .access = PL0_RW, .type = ARM_CP_NZCV }, | |
c2b820fe PM |
4204 | { .name = "DAIF", .state = ARM_CP_STATE_AA64, |
4205 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, | |
7a0e58fa | 4206 | .type = ARM_CP_NO_RAW, |
c2b820fe PM |
4207 | .access = PL0_RW, .accessfn = aa64_daif_access, |
4208 | .fieldoffset = offsetof(CPUARMState, daif), | |
4209 | .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, | |
b0d2b7d0 PM |
4210 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, |
4211 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | |
b916c9c3 | 4212 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 4213 | .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, |
b0d2b7d0 PM |
4214 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, |
4215 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | |
b916c9c3 | 4216 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 4217 | .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, |
b0d2b7d0 PM |
4218 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, |
4219 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | |
7a0e58fa | 4220 | .access = PL0_R, .type = ARM_CP_NO_RAW, |
aca3f40b PM |
4221 | .readfn = aa64_dczid_read }, |
4222 | { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, | |
4223 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, | |
4224 | .access = PL0_W, .type = ARM_CP_DC_ZVA, | |
4225 | #ifndef CONFIG_USER_ONLY | |
4226 | /* Avoid overhead of an access check that always passes in user-mode */ | |
4227 | .accessfn = aa64_zva_access, | |
4228 | #endif | |
4229 | }, | |
0eef9d98 PM |
4230 | { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, |
4231 | .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, | |
4232 | .access = PL1_R, .type = ARM_CP_CURRENTEL }, | |
8af35c37 PM |
4233 | /* Cache ops: all NOPs since we don't emulate caches */ |
4234 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, | |
4235 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
4236 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4237 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, | |
4238 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
4239 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4240 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, | |
4241 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | |
4242 | .access = PL0_W, .type = ARM_CP_NOP, | |
4243 | .accessfn = aa64_cacheop_access }, | |
4244 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, | |
4245 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
4246 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4247 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, | |
4248 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
4249 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4250 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, | |
4251 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | |
4252 | .access = PL0_W, .type = ARM_CP_NOP, | |
4253 | .accessfn = aa64_cacheop_access }, | |
4254 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, | |
4255 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
4256 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4257 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, | |
4258 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | |
4259 | .access = PL0_W, .type = ARM_CP_NOP, | |
4260 | .accessfn = aa64_cacheop_access }, | |
4261 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, | |
4262 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | |
4263 | .access = PL0_W, .type = ARM_CP_NOP, | |
4264 | .accessfn = aa64_cacheop_access }, | |
4265 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, | |
4266 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
4267 | .access = PL1_W, .type = ARM_CP_NOP }, | |
168aa23b PM |
4268 | /* TLBI operations */ |
4269 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 4270 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, |
7a0e58fa | 4271 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4272 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 4273 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4274 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
7a0e58fa | 4275 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4276 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4277 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4278 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
7a0e58fa | 4279 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4280 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 4281 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4282 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
7a0e58fa | 4283 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4284 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4285 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4286 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
7a0e58fa | 4287 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4288 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4289 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4290 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
7a0e58fa | 4291 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4292 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 4293 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4294 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, |
7a0e58fa | 4295 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4296 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 4297 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4298 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
7a0e58fa | 4299 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4300 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4301 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4302 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
7a0e58fa | 4303 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4304 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 4305 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4306 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
7a0e58fa | 4307 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4308 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4309 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4310 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
7a0e58fa | 4311 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4312 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 4313 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 4314 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
7a0e58fa | 4315 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
fd3ed969 | 4316 | .writefn = tlbi_aa64_vae1_write }, |
cea66e91 PM |
4317 | { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, |
4318 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
4319 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4320 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
4321 | { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, | |
4322 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
4323 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4324 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
83ddf975 PM |
4325 | { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, |
4326 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
4327 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 4328 | .writefn = tlbi_aa64_alle1is_write }, |
43efaa33 PM |
4329 | { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, |
4330 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, | |
4331 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4332 | .writefn = tlbi_aa64_alle1is_write }, | |
cea66e91 PM |
4333 | { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, |
4334 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
4335 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4336 | .writefn = tlbi_aa64_ipas2e1_write }, | |
4337 | { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, | |
4338 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
4339 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4340 | .writefn = tlbi_aa64_ipas2e1_write }, | |
83ddf975 PM |
4341 | { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, |
4342 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
4343 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 4344 | .writefn = tlbi_aa64_alle1_write }, |
43efaa33 PM |
4345 | { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, |
4346 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, | |
4347 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4348 | .writefn = tlbi_aa64_alle1is_write }, | |
19525524 PM |
4349 | #ifndef CONFIG_USER_ONLY |
4350 | /* 64 bit address translation operations */ | |
4351 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
4352 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, | |
0710b2fa PM |
4353 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4354 | .writefn = ats_write64 }, | |
19525524 PM |
4355 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, |
4356 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, | |
0710b2fa PM |
4357 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4358 | .writefn = ats_write64 }, | |
19525524 PM |
4359 | { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, |
4360 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, | |
0710b2fa PM |
4361 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4362 | .writefn = ats_write64 }, | |
19525524 PM |
4363 | { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, |
4364 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, | |
0710b2fa PM |
4365 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4366 | .writefn = ats_write64 }, | |
2a47df95 | 4367 | { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4368 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, |
0710b2fa PM |
4369 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4370 | .writefn = ats_write64 }, | |
2a47df95 | 4371 | { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4372 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, |
0710b2fa PM |
4373 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4374 | .writefn = ats_write64 }, | |
2a47df95 | 4375 | { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4376 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, |
0710b2fa PM |
4377 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4378 | .writefn = ats_write64 }, | |
2a47df95 | 4379 | { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, |
7a379c7e | 4380 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, |
0710b2fa PM |
4381 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4382 | .writefn = ats_write64 }, | |
2a47df95 PM |
4383 | /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ |
4384 | { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, | |
4385 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, | |
0710b2fa PM |
4386 | .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4387 | .writefn = ats_write64 }, | |
2a47df95 PM |
4388 | { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, |
4389 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, | |
0710b2fa PM |
4390 | .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
4391 | .writefn = ats_write64 }, | |
c96fc9b5 EI |
4392 | { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, |
4393 | .type = ARM_CP_ALIAS, | |
4394 | .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, | |
4395 | .access = PL1_RW, .resetvalue = 0, | |
4396 | .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), | |
4397 | .writefn = par_write }, | |
19525524 | 4398 | #endif |
995939a6 | 4399 | /* TLB invalidate last level of translation table walk */ |
9449fdf6 | 4400 | { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
7a0e58fa | 4401 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write }, |
9449fdf6 | 4402 | { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
7a0e58fa | 4403 | .type = ARM_CP_NO_RAW, .access = PL1_W, |
fa439fc5 | 4404 | .writefn = tlbimvaa_is_write }, |
9449fdf6 | 4405 | { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
7a0e58fa | 4406 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write }, |
9449fdf6 | 4407 | { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
7a0e58fa | 4408 | .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write }, |
541ef8c2 SS |
4409 | { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, |
4410 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4411 | .writefn = tlbimva_hyp_write }, | |
4412 | { .name = "TLBIMVALHIS", | |
4413 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
4414 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4415 | .writefn = tlbimva_hyp_is_write }, | |
4416 | { .name = "TLBIIPAS2", | |
4417 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
4418 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4419 | .writefn = tlbiipas2_write }, | |
4420 | { .name = "TLBIIPAS2IS", | |
4421 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
4422 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4423 | .writefn = tlbiipas2_is_write }, | |
4424 | { .name = "TLBIIPAS2L", | |
4425 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
4426 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4427 | .writefn = tlbiipas2_write }, | |
4428 | { .name = "TLBIIPAS2LIS", | |
4429 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
4430 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4431 | .writefn = tlbiipas2_is_write }, | |
9449fdf6 PM |
4432 | /* 32 bit cache operations */ |
4433 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
4434 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4435 | { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, | |
4436 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4437 | { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
4438 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4439 | { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, | |
4440 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4441 | { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, | |
4442 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4443 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | |
4444 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4445 | { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
4446 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4447 | { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
4448 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4449 | { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, | |
4450 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4451 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
4452 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4453 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, | |
4454 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4455 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, | |
4456 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4457 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
4458 | .type = ARM_CP_NOP, .access = PL1_W }, | |
4459 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
4460 | { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, |
4461 | .access = PL1_RW, .resetvalue = 0, | |
4462 | .writefn = dacr_write, .raw_writefn = raw_write, | |
4463 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
4464 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a0618a19 | 4465 | { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4466 | .type = ARM_CP_ALIAS, |
a0618a19 | 4467 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, |
6947f059 EI |
4468 | .access = PL1_RW, |
4469 | .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, | |
a65f1de9 | 4470 | { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4471 | .type = ARM_CP_ALIAS, |
a65f1de9 | 4472 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
4473 | .access = PL1_RW, |
4474 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, | |
f502cfc2 PM |
4475 | /* We rely on the access checks not allowing the guest to write to the |
4476 | * state field when SPSel indicates that it's being used as the stack | |
4477 | * pointer. | |
4478 | */ | |
4479 | { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, | |
4480 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, | |
4481 | .access = PL1_RW, .accessfn = sp_el0_access, | |
7a0e58fa | 4482 | .type = ARM_CP_ALIAS, |
f502cfc2 | 4483 | .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, |
884b4dee GB |
4484 | { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, |
4485 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 4486 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
884b4dee | 4487 | .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, |
f502cfc2 PM |
4488 | { .name = "SPSel", .state = ARM_CP_STATE_AA64, |
4489 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, | |
7a0e58fa | 4490 | .type = ARM_CP_NO_RAW, |
f502cfc2 | 4491 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, |
03fbf20f PM |
4492 | { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, |
4493 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, | |
4494 | .type = ARM_CP_ALIAS, | |
4495 | .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), | |
4496 | .access = PL2_RW, .accessfn = fpexc32_access }, | |
6a43e0b6 PM |
4497 | { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, |
4498 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, | |
4499 | .access = PL2_RW, .resetvalue = 0, | |
4500 | .writefn = dacr_write, .raw_writefn = raw_write, | |
4501 | .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, | |
4502 | { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, | |
4503 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, | |
4504 | .access = PL2_RW, .resetvalue = 0, | |
4505 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, | |
4506 | { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, | |
4507 | .type = ARM_CP_ALIAS, | |
4508 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, | |
4509 | .access = PL2_RW, | |
4510 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, | |
4511 | { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, | |
4512 | .type = ARM_CP_ALIAS, | |
4513 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, | |
4514 | .access = PL2_RW, | |
4515 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, | |
4516 | { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, | |
4517 | .type = ARM_CP_ALIAS, | |
4518 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, | |
4519 | .access = PL2_RW, | |
4520 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, | |
4521 | { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, | |
4522 | .type = ARM_CP_ALIAS, | |
4523 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, | |
4524 | .access = PL2_RW, | |
4525 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, | |
a8d64e73 PM |
4526 | { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, |
4527 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, | |
4528 | .resetvalue = 0, | |
4529 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) }, | |
4530 | { .name = "SDCR", .type = ARM_CP_ALIAS, | |
4531 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1, | |
4532 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, | |
4533 | .writefn = sdcr_write, | |
4534 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, | |
b0d2b7d0 PM |
4535 | REGINFO_SENTINEL |
4536 | }; | |
4537 | ||
d42e3c26 | 4538 | /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ |
4771cd01 | 4539 | static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { |
d79e0c06 | 4540 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, |
d42e3c26 EI |
4541 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, |
4542 | .access = PL2_RW, | |
4543 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | |
ce4afed8 | 4544 | { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH, |
7a0e58fa | 4545 | .type = ARM_CP_NO_RAW, |
f149e3e8 EI |
4546 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
4547 | .access = PL2_RW, | |
ce4afed8 | 4548 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
831a2fca PM |
4549 | { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, |
4550 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, | |
4551 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
68e78e33 PM |
4552 | { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, |
4553 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, | |
4554 | .access = PL2_RW, | |
4555 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
c6f19164 GB |
4556 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
4557 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
4558 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
95f949ac EI |
4559 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
4560 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
4561 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4562 | .resetvalue = 0 }, | |
4563 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
b5ede85b | 4564 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, |
95f949ac | 4565 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
2179ef95 PM |
4566 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
4567 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
4568 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4569 | .resetvalue = 0 }, | |
55b53c71 | 4570 | { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, |
b5ede85b | 4571 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, |
2179ef95 PM |
4572 | .access = PL2_RW, .type = ARM_CP_CONST, |
4573 | .resetvalue = 0 }, | |
37cd6c24 PM |
4574 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
4575 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
4576 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4577 | .resetvalue = 0 }, | |
4578 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
4579 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
4580 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4581 | .resetvalue = 0 }, | |
06ec4c8c EI |
4582 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
4583 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
4584 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
68e9c2fe EI |
4585 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH, |
4586 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
4587 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
4588 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b698e9cf EI |
4589 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
4590 | .cp = 15, .opc1 = 6, .crm = 2, | |
4591 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
4592 | .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | |
4593 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
4594 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
4595 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
b9cb5323 EI |
4596 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
4597 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
4598 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
ff05f37b EI |
4599 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
4600 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
4601 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
a57633c0 EI |
4602 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
4603 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
4604 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4605 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
4606 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
4607 | .resetvalue = 0 }, | |
0b6440af EI |
4608 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
4609 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
4610 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
edac4d8a EI |
4611 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
4612 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
4613 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4614 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
4615 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
4616 | .resetvalue = 0 }, | |
b0e66d95 EI |
4617 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
4618 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
4619 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4620 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
4621 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST, | |
4622 | .resetvalue = 0 }, | |
4623 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
4624 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
4625 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4626 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
4627 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
4628 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
14cc7b54 SF |
4629 | { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, |
4630 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | |
d6c8cf81 PM |
4631 | .access = PL2_RW, .accessfn = access_tda, |
4632 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
59e05530 EI |
4633 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, |
4634 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
4635 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
4636 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
2a5a9abd AF |
4637 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
4638 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
4639 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
cba517c3 PM |
4640 | { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, |
4641 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, | |
4642 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4643 | { .name = "HIFAR", .state = ARM_CP_STATE_AA32, | |
4644 | .type = ARM_CP_CONST, | |
4645 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | |
4646 | .access = PL2_RW, .resetvalue = 0 }, | |
d42e3c26 EI |
4647 | REGINFO_SENTINEL |
4648 | }; | |
4649 | ||
ce4afed8 PM |
4650 | /* Ditto, but for registers which exist in ARMv8 but not v7 */ |
4651 | static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { | |
4652 | { .name = "HCR2", .state = ARM_CP_STATE_AA32, | |
4653 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, | |
4654 | .access = PL2_RW, | |
4655 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
4656 | REGINFO_SENTINEL | |
4657 | }; | |
4658 | ||
f149e3e8 EI |
4659 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4660 | { | |
2fc0cc0e | 4661 | ARMCPU *cpu = env_archcpu(env); |
f149e3e8 EI |
4662 | uint64_t valid_mask = HCR_MASK; |
4663 | ||
4664 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
4665 | valid_mask &= ~HCR_HCD; | |
77077a83 JK |
4666 | } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { |
4667 | /* Architecturally HCR.TSC is RES0 if EL3 is not implemented. | |
4668 | * However, if we're using the SMC PSCI conduit then QEMU is | |
4669 | * effectively acting like EL3 firmware and so the guest at | |
4670 | * EL2 should retain the ability to prevent EL1 from being | |
4671 | * able to make SMC calls into the ersatz firmware, so in | |
4672 | * that case HCR.TSC should be read/write. | |
4673 | */ | |
f149e3e8 EI |
4674 | valid_mask &= ~HCR_TSC; |
4675 | } | |
2d7137c1 RH |
4676 | if (cpu_isar_feature(aa64_lor, cpu)) { |
4677 | valid_mask |= HCR_TLOR; | |
4678 | } | |
ef682cdb RH |
4679 | if (cpu_isar_feature(aa64_pauth, cpu)) { |
4680 | valid_mask |= HCR_API | HCR_APK; | |
4681 | } | |
f149e3e8 EI |
4682 | |
4683 | /* Clear RES0 bits. */ | |
4684 | value &= valid_mask; | |
4685 | ||
4686 | /* These bits change the MMU setup: | |
4687 | * HCR_VM enables stage 2 translation | |
4688 | * HCR_PTW forbids certain page-table setups | |
4689 | * HCR_DC Disables stage1 and enables stage2 translation | |
4690 | */ | |
ce4afed8 | 4691 | if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { |
d10eb08f | 4692 | tlb_flush(CPU(cpu)); |
f149e3e8 | 4693 | } |
ce4afed8 | 4694 | env->cp15.hcr_el2 = value; |
89430fc6 PM |
4695 | |
4696 | /* | |
4697 | * Updates to VI and VF require us to update the status of | |
4698 | * virtual interrupts, which are the logical OR of these bits | |
4699 | * and the state of the input lines from the GIC. (This requires | |
4700 | * that we have the iothread lock, which is done by marking the | |
4701 | * reginfo structs as ARM_CP_IO.) | |
4702 | * Note that if a write to HCR pends a VIRQ or VFIQ it is never | |
4703 | * possible for it to be taken immediately, because VIRQ and | |
4704 | * VFIQ are masked unless running at EL0 or EL1, and HCR | |
4705 | * can only be written at EL2. | |
4706 | */ | |
4707 | g_assert(qemu_mutex_iothread_locked()); | |
4708 | arm_cpu_update_virq(cpu); | |
4709 | arm_cpu_update_vfiq(cpu); | |
ce4afed8 PM |
4710 | } |
4711 | ||
4712 | static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, | |
4713 | uint64_t value) | |
4714 | { | |
4715 | /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */ | |
4716 | value = deposit64(env->cp15.hcr_el2, 32, 32, value); | |
4717 | hcr_write(env, NULL, value); | |
4718 | } | |
4719 | ||
4720 | static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, | |
4721 | uint64_t value) | |
4722 | { | |
4723 | /* Handle HCR write, i.e. write to low half of HCR_EL2 */ | |
4724 | value = deposit64(env->cp15.hcr_el2, 0, 32, value); | |
4725 | hcr_write(env, NULL, value); | |
f149e3e8 EI |
4726 | } |
4727 | ||
f7778444 RH |
4728 | /* |
4729 | * Return the effective value of HCR_EL2. | |
4730 | * Bits that are not included here: | |
4731 | * RW (read from SCR_EL3.RW as needed) | |
4732 | */ | |
4733 | uint64_t arm_hcr_el2_eff(CPUARMState *env) | |
4734 | { | |
4735 | uint64_t ret = env->cp15.hcr_el2; | |
4736 | ||
4737 | if (arm_is_secure_below_el3(env)) { | |
4738 | /* | |
4739 | * "This register has no effect if EL2 is not enabled in the | |
4740 | * current Security state". This is ARMv8.4-SecEL2 speak for | |
4741 | * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1). | |
4742 | * | |
4743 | * Prior to that, the language was "In an implementation that | |
4744 | * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves | |
4745 | * as if this field is 0 for all purposes other than a direct | |
4746 | * read or write access of HCR_EL2". With lots of enumeration | |
4747 | * on a per-field basis. In current QEMU, this is condition | |
4748 | * is arm_is_secure_below_el3. | |
4749 | * | |
4750 | * Since the v8.4 language applies to the entire register, and | |
4751 | * appears to be backward compatible, use that. | |
4752 | */ | |
4753 | ret = 0; | |
4754 | } else if (ret & HCR_TGE) { | |
4755 | /* These bits are up-to-date as of ARMv8.4. */ | |
4756 | if (ret & HCR_E2H) { | |
4757 | ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | | |
4758 | HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | | |
4759 | HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | | |
4760 | HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE); | |
4761 | } else { | |
4762 | ret |= HCR_FMO | HCR_IMO | HCR_AMO; | |
4763 | } | |
4764 | ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | | |
4765 | HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | | |
4766 | HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | | |
4767 | HCR_TLOR); | |
4768 | } | |
4769 | ||
4770 | return ret; | |
4771 | } | |
4772 | ||
fc1120a7 PM |
4773 | static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4774 | uint64_t value) | |
4775 | { | |
4776 | /* | |
4777 | * For A-profile AArch32 EL3, if NSACR.CP10 | |
4778 | * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. | |
4779 | */ | |
4780 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
4781 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
4782 | value &= ~(0x3 << 10); | |
4783 | value |= env->cp15.cptr_el[2] & (0x3 << 10); | |
4784 | } | |
4785 | env->cp15.cptr_el[2] = value; | |
4786 | } | |
4787 | ||
4788 | static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
4789 | { | |
4790 | /* | |
4791 | * For A-profile AArch32 EL3, if NSACR.CP10 | |
4792 | * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. | |
4793 | */ | |
4794 | uint64_t value = env->cp15.cptr_el[2]; | |
4795 | ||
4796 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
4797 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
4798 | value |= 0x3 << 10; | |
4799 | } | |
4800 | return value; | |
4801 | } | |
4802 | ||
4771cd01 | 4803 | static const ARMCPRegInfo el2_cp_reginfo[] = { |
f149e3e8 | 4804 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
89430fc6 | 4805 | .type = ARM_CP_IO, |
f149e3e8 EI |
4806 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
4807 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
c624ea0f | 4808 | .writefn = hcr_write }, |
ce4afed8 | 4809 | { .name = "HCR", .state = ARM_CP_STATE_AA32, |
89430fc6 | 4810 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
4811 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
4812 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
c624ea0f | 4813 | .writefn = hcr_writelow }, |
831a2fca PM |
4814 | { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, |
4815 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, | |
4816 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3b685ba7 | 4817 | { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4818 | .type = ARM_CP_ALIAS, |
3b685ba7 EI |
4819 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, |
4820 | .access = PL2_RW, | |
4821 | .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, | |
68e78e33 | 4822 | { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, |
f2c30f42 EI |
4823 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, |
4824 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, | |
cba517c3 | 4825 | { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, |
63b60551 EI |
4826 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, |
4827 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, | |
cba517c3 PM |
4828 | { .name = "HIFAR", .state = ARM_CP_STATE_AA32, |
4829 | .type = ARM_CP_ALIAS, | |
4830 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | |
4831 | .access = PL2_RW, | |
4832 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) }, | |
3b685ba7 | 4833 | { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 4834 | .type = ARM_CP_ALIAS, |
3b685ba7 | 4835 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
4836 | .access = PL2_RW, |
4837 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, | |
d79e0c06 | 4838 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, |
d42e3c26 EI |
4839 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, |
4840 | .access = PL2_RW, .writefn = vbar_write, | |
4841 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), | |
4842 | .resetvalue = 0 }, | |
884b4dee GB |
4843 | { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, |
4844 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 4845 | .access = PL3_RW, .type = ARM_CP_ALIAS, |
884b4dee | 4846 | .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, |
c6f19164 GB |
4847 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
4848 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
4849 | .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, | |
fc1120a7 PM |
4850 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]), |
4851 | .readfn = cptr_el2_read, .writefn = cptr_el2_write }, | |
95f949ac EI |
4852 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
4853 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
4854 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), | |
4855 | .resetvalue = 0 }, | |
4856 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
b5ede85b | 4857 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, |
95f949ac EI |
4858 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
4859 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, | |
2179ef95 PM |
4860 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
4861 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
4862 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4863 | .resetvalue = 0 }, | |
4864 | /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ | |
55b53c71 | 4865 | { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, |
b5ede85b | 4866 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, |
2179ef95 PM |
4867 | .access = PL2_RW, .type = ARM_CP_CONST, |
4868 | .resetvalue = 0 }, | |
37cd6c24 PM |
4869 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
4870 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
4871 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4872 | .resetvalue = 0 }, | |
4873 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
4874 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
4875 | .access = PL2_RW, .type = ARM_CP_CONST, | |
4876 | .resetvalue = 0 }, | |
06ec4c8c EI |
4877 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
4878 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
6459b94c PM |
4879 | .access = PL2_RW, |
4880 | /* no .writefn needed as this can't cause an ASID change; | |
4881 | * no .raw_writefn or .resetfn needed as we never use mask/base_mask | |
4882 | */ | |
06ec4c8c | 4883 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, |
68e9c2fe EI |
4884 | { .name = "VTCR", .state = ARM_CP_STATE_AA32, |
4885 | .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 | 4886 | .type = ARM_CP_ALIAS, |
68e9c2fe EI |
4887 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
4888 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, | |
4889 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, | |
4890 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 PM |
4891 | .access = PL2_RW, |
4892 | /* no .writefn needed as this can't cause an ASID change; | |
4893 | * no .raw_writefn or .resetfn needed as we never use mask/base_mask | |
4894 | */ | |
68e9c2fe | 4895 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, |
b698e9cf EI |
4896 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
4897 | .cp = 15, .opc1 = 6, .crm = 2, | |
4898 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
4899 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
4900 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), | |
4901 | .writefn = vttbr_write }, | |
4902 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
4903 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
4904 | .access = PL2_RW, .writefn = vttbr_write, | |
4905 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, | |
b9cb5323 EI |
4906 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
4907 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
4908 | .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, | |
4909 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, | |
ff05f37b EI |
4910 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
4911 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
4912 | .access = PL2_RW, .resetvalue = 0, | |
4913 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, | |
a57633c0 EI |
4914 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
4915 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
4916 | .access = PL2_RW, .resetvalue = 0, | |
4917 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, | |
4918 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
4919 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
a57633c0 | 4920 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
541ef8c2 SS |
4921 | { .name = "TLBIALLNSNH", |
4922 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
4923 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4924 | .writefn = tlbiall_nsnh_write }, | |
4925 | { .name = "TLBIALLNSNHIS", | |
4926 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
4927 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4928 | .writefn = tlbiall_nsnh_is_write }, | |
4929 | { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
4930 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4931 | .writefn = tlbiall_hyp_write }, | |
4932 | { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
4933 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4934 | .writefn = tlbiall_hyp_is_write }, | |
4935 | { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
4936 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4937 | .writefn = tlbimva_hyp_write }, | |
4938 | { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
4939 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
4940 | .writefn = tlbimva_hyp_is_write }, | |
51da9014 EI |
4941 | { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, |
4942 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
4943 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 4944 | .writefn = tlbi_aa64_alle2_write }, |
8742d49d EI |
4945 | { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, |
4946 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
4947 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 4948 | .writefn = tlbi_aa64_vae2_write }, |
2bfb9d75 PM |
4949 | { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, |
4950 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, | |
4951 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4952 | .writefn = tlbi_aa64_vae2_write }, | |
4953 | { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, | |
4954 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
4955 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4956 | .writefn = tlbi_aa64_alle2is_write }, | |
8742d49d EI |
4957 | { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, |
4958 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
4959 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
fd3ed969 | 4960 | .writefn = tlbi_aa64_vae2is_write }, |
2bfb9d75 PM |
4961 | { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, |
4962 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
4963 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
4964 | .writefn = tlbi_aa64_vae2is_write }, | |
edac4d8a | 4965 | #ifndef CONFIG_USER_ONLY |
2a47df95 PM |
4966 | /* Unlike the other EL2-related AT operations, these must |
4967 | * UNDEF from EL3 if EL2 is not implemented, which is why we | |
4968 | * define them here rather than with the rest of the AT ops. | |
4969 | */ | |
4970 | { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, | |
4971 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
4972 | .access = PL2_W, .accessfn = at_s1e2_access, | |
0710b2fa | 4973 | .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, |
2a47df95 PM |
4974 | { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, |
4975 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | |
4976 | .access = PL2_W, .accessfn = at_s1e2_access, | |
0710b2fa | 4977 | .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 }, |
14db7fe0 PM |
4978 | /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE |
4979 | * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 | |
4980 | * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose | |
4981 | * to behave as if SCR.NS was 1. | |
4982 | */ | |
4983 | { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
4984 | .access = PL2_W, | |
0710b2fa | 4985 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
14db7fe0 PM |
4986 | { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, |
4987 | .access = PL2_W, | |
0710b2fa | 4988 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
0b6440af EI |
4989 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
4990 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
4991 | /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the | |
4992 | * reset values as IMPDEF. We choose to reset to 3 to comply with | |
4993 | * both ARMv7 and ARMv8. | |
4994 | */ | |
4995 | .access = PL2_RW, .resetvalue = 3, | |
4996 | .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, | |
edac4d8a EI |
4997 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
4998 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
4999 | .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, | |
5000 | .writefn = gt_cntvoff_write, | |
5001 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
5002 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
5003 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, | |
5004 | .writefn = gt_cntvoff_write, | |
5005 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
b0e66d95 EI |
5006 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
5007 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
5008 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
5009 | .type = ARM_CP_IO, .access = PL2_RW, | |
5010 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
5011 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
5012 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
5013 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO, | |
5014 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
5015 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
5016 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
d44ec156 | 5017 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, |
b0e66d95 EI |
5018 | .resetfn = gt_hyp_timer_reset, |
5019 | .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, | |
5020 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
5021 | .type = ARM_CP_IO, | |
5022 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
5023 | .access = PL2_RW, | |
5024 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), | |
5025 | .resetvalue = 0, | |
5026 | .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, | |
edac4d8a | 5027 | #endif |
14cc7b54 SF |
5028 | /* The only field of MDCR_EL2 that has a defined architectural reset value |
5029 | * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we | |
5ecdd3e4 | 5030 | * don't implement any PMU event counters, so using zero as a reset |
14cc7b54 SF |
5031 | * value for MDCR_EL2 is okay |
5032 | */ | |
5033 | { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, | |
5034 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, | |
5035 | .access = PL2_RW, .resetvalue = 0, | |
5036 | .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), }, | |
59e05530 EI |
5037 | { .name = "HPFAR", .state = ARM_CP_STATE_AA32, |
5038 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
5039 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
5040 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
5041 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, | |
5042 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
5043 | .access = PL2_RW, | |
5044 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
2a5a9abd AF |
5045 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
5046 | .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
5047 | .access = PL2_RW, | |
5048 | .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, | |
3b685ba7 EI |
5049 | REGINFO_SENTINEL |
5050 | }; | |
5051 | ||
ce4afed8 PM |
5052 | static const ARMCPRegInfo el2_v8_cp_reginfo[] = { |
5053 | { .name = "HCR2", .state = ARM_CP_STATE_AA32, | |
89430fc6 | 5054 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
5055 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, |
5056 | .access = PL2_RW, | |
5057 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2), | |
5058 | .writefn = hcr_writehigh }, | |
5059 | REGINFO_SENTINEL | |
5060 | }; | |
5061 | ||
2f027fc5 PM |
5062 | static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5063 | bool isread) | |
5064 | { | |
5065 | /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. | |
5066 | * At Secure EL1 it traps to EL3. | |
5067 | */ | |
5068 | if (arm_current_el(env) == 3) { | |
5069 | return CP_ACCESS_OK; | |
5070 | } | |
5071 | if (arm_is_secure_below_el3(env)) { | |
5072 | return CP_ACCESS_TRAP_EL3; | |
5073 | } | |
5074 | /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ | |
5075 | if (isread) { | |
5076 | return CP_ACCESS_OK; | |
5077 | } | |
5078 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
5079 | } | |
5080 | ||
60fb1a87 GB |
5081 | static const ARMCPRegInfo el3_cp_reginfo[] = { |
5082 | { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, | |
5083 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, | |
5084 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), | |
5085 | .resetvalue = 0, .writefn = scr_write }, | |
7a0e58fa | 5086 | { .name = "SCR", .type = ARM_CP_ALIAS, |
60fb1a87 | 5087 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, |
efe4a274 PM |
5088 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
5089 | .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), | |
b061a82b | 5090 | .writefn = scr_write }, |
60fb1a87 GB |
5091 | { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, |
5092 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, | |
5093 | .access = PL3_RW, .resetvalue = 0, | |
5094 | .fieldoffset = offsetof(CPUARMState, cp15.sder) }, | |
5095 | { .name = "SDER", | |
5096 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, | |
5097 | .access = PL3_RW, .resetvalue = 0, | |
5098 | .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, | |
60fb1a87 | 5099 | { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, |
efe4a274 PM |
5100 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
5101 | .writefn = vbar_write, .resetvalue = 0, | |
60fb1a87 | 5102 | .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, |
7dd8c9af FA |
5103 | { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, |
5104 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, | |
f478847f | 5105 | .access = PL3_RW, .resetvalue = 0, |
7dd8c9af | 5106 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, |
11f136ee FA |
5107 | { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, |
5108 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, | |
6459b94c PM |
5109 | .access = PL3_RW, |
5110 | /* no .writefn needed as this can't cause an ASID change; | |
811595a2 PM |
5111 | * we must provide a .raw_writefn and .resetfn because we handle |
5112 | * reset and migration for the AArch32 TTBCR(S), which might be | |
5113 | * using mask and base_mask. | |
6459b94c | 5114 | */ |
811595a2 | 5115 | .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write, |
11f136ee | 5116 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, |
81547d66 | 5117 | { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5118 | .type = ARM_CP_ALIAS, |
81547d66 EI |
5119 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, |
5120 | .access = PL3_RW, | |
5121 | .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, | |
f2c30f42 | 5122 | { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, |
f2c30f42 EI |
5123 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, |
5124 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, | |
63b60551 EI |
5125 | { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, |
5126 | .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, | |
5127 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, | |
81547d66 | 5128 | { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5129 | .type = ARM_CP_ALIAS, |
81547d66 | 5130 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
5131 | .access = PL3_RW, |
5132 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) }, | |
a1ba125c EI |
5133 | { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, |
5134 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, | |
5135 | .access = PL3_RW, .writefn = vbar_write, | |
5136 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), | |
5137 | .resetvalue = 0 }, | |
c6f19164 GB |
5138 | { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, |
5139 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, | |
5140 | .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, | |
5141 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, | |
4cfb8ad8 PM |
5142 | { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, |
5143 | .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, | |
5144 | .access = PL3_RW, .resetvalue = 0, | |
5145 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, | |
2179ef95 PM |
5146 | { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64, |
5147 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, | |
5148 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5149 | .resetvalue = 0 }, | |
37cd6c24 PM |
5150 | { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, |
5151 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, | |
5152 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5153 | .resetvalue = 0 }, | |
5154 | { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, | |
5155 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, | |
5156 | .access = PL3_RW, .type = ARM_CP_CONST, | |
5157 | .resetvalue = 0 }, | |
43efaa33 PM |
5158 | { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, |
5159 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, | |
5160 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5161 | .writefn = tlbi_aa64_alle3is_write }, | |
5162 | { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, | |
5163 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, | |
5164 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5165 | .writefn = tlbi_aa64_vae3is_write }, | |
5166 | { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, | |
5167 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, | |
5168 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5169 | .writefn = tlbi_aa64_vae3is_write }, | |
5170 | { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, | |
5171 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, | |
5172 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5173 | .writefn = tlbi_aa64_alle3_write }, | |
5174 | { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, | |
5175 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, | |
5176 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5177 | .writefn = tlbi_aa64_vae3_write }, | |
5178 | { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, | |
5179 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, | |
5180 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
5181 | .writefn = tlbi_aa64_vae3_write }, | |
0f1a3b24 FA |
5182 | REGINFO_SENTINEL |
5183 | }; | |
5184 | ||
3f208fd7 PM |
5185 | static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5186 | bool isread) | |
7da845b0 PM |
5187 | { |
5188 | /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, | |
5189 | * but the AArch32 CTR has its own reginfo struct) | |
5190 | */ | |
137feaa9 | 5191 | if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) { |
7da845b0 PM |
5192 | return CP_ACCESS_TRAP; |
5193 | } | |
5194 | return CP_ACCESS_OK; | |
5195 | } | |
5196 | ||
1424ca8d DM |
5197 | static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5198 | uint64_t value) | |
5199 | { | |
5200 | /* Writes to OSLAR_EL1 may update the OS lock status, which can be | |
5201 | * read via a bit in OSLSR_EL1. | |
5202 | */ | |
5203 | int oslock; | |
5204 | ||
5205 | if (ri->state == ARM_CP_STATE_AA32) { | |
5206 | oslock = (value == 0xC5ACCE55); | |
5207 | } else { | |
5208 | oslock = value & 1; | |
5209 | } | |
5210 | ||
5211 | env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); | |
5212 | } | |
5213 | ||
50300698 | 5214 | static const ARMCPRegInfo debug_cp_reginfo[] = { |
50300698 | 5215 | /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped |
10aae104 PM |
5216 | * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; |
5217 | * unlike DBGDRAR it is never accessible from EL0. | |
5218 | * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 | |
5219 | * accessor. | |
50300698 PM |
5220 | */ |
5221 | { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | |
91b0a238 PM |
5222 | .access = PL0_R, .accessfn = access_tdra, |
5223 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
10aae104 PM |
5224 | { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, |
5225 | .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, | |
91b0a238 PM |
5226 | .access = PL1_R, .accessfn = access_tdra, |
5227 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
50300698 | 5228 | { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
91b0a238 PM |
5229 | .access = PL0_R, .accessfn = access_tdra, |
5230 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
17a9eb53 | 5231 | /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ |
10aae104 PM |
5232 | { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, |
5233 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
d6c8cf81 | 5234 | .access = PL1_RW, .accessfn = access_tda, |
0e5e8935 PM |
5235 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), |
5236 | .resetvalue = 0 }, | |
5e8b12ff PM |
5237 | /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. |
5238 | * We don't implement the configurable EL0 access. | |
5239 | */ | |
5240 | { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH, | |
5241 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
7a0e58fa | 5242 | .type = ARM_CP_ALIAS, |
d6c8cf81 | 5243 | .access = PL1_R, .accessfn = access_tda, |
b061a82b | 5244 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, |
10aae104 PM |
5245 | { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, |
5246 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, | |
1424ca8d | 5247 | .access = PL1_W, .type = ARM_CP_NO_RAW, |
187f678d | 5248 | .accessfn = access_tdosa, |
1424ca8d DM |
5249 | .writefn = oslar_write }, |
5250 | { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, | |
5251 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, | |
5252 | .access = PL1_R, .resetvalue = 10, | |
187f678d | 5253 | .accessfn = access_tdosa, |
1424ca8d | 5254 | .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, |
5e8b12ff PM |
5255 | /* Dummy OSDLR_EL1: 32-bit Linux will read this */ |
5256 | { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, | |
5257 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, | |
187f678d PM |
5258 | .access = PL1_RW, .accessfn = access_tdosa, |
5259 | .type = ARM_CP_NOP }, | |
5e8b12ff PM |
5260 | /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't |
5261 | * implement vector catch debug events yet. | |
5262 | */ | |
5263 | { .name = "DBGVCR", | |
5264 | .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
d6c8cf81 PM |
5265 | .access = PL1_RW, .accessfn = access_tda, |
5266 | .type = ARM_CP_NOP }, | |
4d2ec4da PM |
5267 | /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor |
5268 | * to save and restore a 32-bit guest's DBGVCR) | |
5269 | */ | |
5270 | { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, | |
5271 | .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, | |
5272 | .access = PL2_RW, .accessfn = access_tda, | |
5273 | .type = ARM_CP_NOP }, | |
5dbdc434 PM |
5274 | /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications |
5275 | * Channel but Linux may try to access this register. The 32-bit | |
5276 | * alias is DBGDCCINT. | |
5277 | */ | |
5278 | { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, | |
5279 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
5280 | .access = PL1_RW, .accessfn = access_tda, | |
5281 | .type = ARM_CP_NOP }, | |
50300698 PM |
5282 | REGINFO_SENTINEL |
5283 | }; | |
5284 | ||
5285 | static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | |
5286 | /* 64 bit access versions of the (dummy) debug registers */ | |
5287 | { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, | |
5288 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
5289 | { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | |
5290 | .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | |
5291 | REGINFO_SENTINEL | |
5292 | }; | |
5293 | ||
60eed086 RH |
5294 | /* Return the exception level to which exceptions should be taken |
5295 | * via SVEAccessTrap. If an exception should be routed through | |
5296 | * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should | |
5297 | * take care of raising that exception. | |
5298 | * C.f. the ARM pseudocode function CheckSVEEnabled. | |
5be5e8ed | 5299 | */ |
ced31551 | 5300 | int sve_exception_el(CPUARMState *env, int el) |
5be5e8ed RH |
5301 | { |
5302 | #ifndef CONFIG_USER_ONLY | |
2de7ace2 | 5303 | if (el <= 1) { |
60eed086 RH |
5304 | bool disabled = false; |
5305 | ||
5306 | /* The CPACR.ZEN controls traps to EL1: | |
5307 | * 0, 2 : trap EL0 and EL1 accesses | |
5308 | * 1 : trap only EL0 accesses | |
5309 | * 3 : trap no accesses | |
5310 | */ | |
5311 | if (!extract32(env->cp15.cpacr_el1, 16, 1)) { | |
5312 | disabled = true; | |
5313 | } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) { | |
2de7ace2 | 5314 | disabled = el == 0; |
5be5e8ed | 5315 | } |
60eed086 RH |
5316 | if (disabled) { |
5317 | /* route_to_el2 */ | |
5318 | return (arm_feature(env, ARM_FEATURE_EL2) | |
7c208e0f | 5319 | && (arm_hcr_el2_eff(env) & HCR_TGE) ? 2 : 1); |
5be5e8ed | 5320 | } |
5be5e8ed | 5321 | |
60eed086 RH |
5322 | /* Check CPACR.FPEN. */ |
5323 | if (!extract32(env->cp15.cpacr_el1, 20, 1)) { | |
5324 | disabled = true; | |
5325 | } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) { | |
2de7ace2 | 5326 | disabled = el == 0; |
5be5e8ed | 5327 | } |
60eed086 RH |
5328 | if (disabled) { |
5329 | return 0; | |
5be5e8ed | 5330 | } |
5be5e8ed RH |
5331 | } |
5332 | ||
60eed086 RH |
5333 | /* CPTR_EL2. Since TZ and TFP are positive, |
5334 | * they will be zero when EL2 is not present. | |
5335 | */ | |
2de7ace2 | 5336 | if (el <= 2 && !arm_is_secure_below_el3(env)) { |
60eed086 RH |
5337 | if (env->cp15.cptr_el[2] & CPTR_TZ) { |
5338 | return 2; | |
5339 | } | |
5340 | if (env->cp15.cptr_el[2] & CPTR_TFP) { | |
5341 | return 0; | |
5342 | } | |
5be5e8ed RH |
5343 | } |
5344 | ||
60eed086 RH |
5345 | /* CPTR_EL3. Since EZ is negative we must check for EL3. */ |
5346 | if (arm_feature(env, ARM_FEATURE_EL3) | |
5347 | && !(env->cp15.cptr_el[3] & CPTR_EZ)) { | |
5be5e8ed RH |
5348 | return 3; |
5349 | } | |
5350 | #endif | |
5351 | return 0; | |
5352 | } | |
5353 | ||
0ab5953b RH |
5354 | /* |
5355 | * Given that SVE is enabled, return the vector length for EL. | |
5356 | */ | |
ced31551 | 5357 | uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) |
0ab5953b | 5358 | { |
2fc0cc0e | 5359 | ARMCPU *cpu = env_archcpu(env); |
0ab5953b RH |
5360 | uint32_t zcr_len = cpu->sve_max_vq - 1; |
5361 | ||
5362 | if (el <= 1) { | |
5363 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); | |
5364 | } | |
6a02a732 | 5365 | if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) { |
0ab5953b RH |
5366 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); |
5367 | } | |
6a02a732 | 5368 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0ab5953b RH |
5369 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); |
5370 | } | |
5371 | return zcr_len; | |
5372 | } | |
5373 | ||
5be5e8ed RH |
5374 | static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5375 | uint64_t value) | |
5376 | { | |
0ab5953b RH |
5377 | int cur_el = arm_current_el(env); |
5378 | int old_len = sve_zcr_len_for_el(env, cur_el); | |
5379 | int new_len; | |
5380 | ||
5be5e8ed | 5381 | /* Bits other than [3:0] are RAZ/WI. */ |
7b351d98 | 5382 | QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16); |
5be5e8ed | 5383 | raw_write(env, ri, value & 0xf); |
0ab5953b RH |
5384 | |
5385 | /* | |
5386 | * Because we arrived here, we know both FP and SVE are enabled; | |
5387 | * otherwise we would have trapped access to the ZCR_ELn register. | |
5388 | */ | |
5389 | new_len = sve_zcr_len_for_el(env, cur_el); | |
5390 | if (new_len < old_len) { | |
5391 | aarch64_sve_narrow_vq(env, new_len + 1); | |
5392 | } | |
5be5e8ed RH |
5393 | } |
5394 | ||
5395 | static const ARMCPRegInfo zcr_el1_reginfo = { | |
5396 | .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | |
5397 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 5398 | .access = PL1_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
5399 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), |
5400 | .writefn = zcr_write, .raw_writefn = raw_write | |
5401 | }; | |
5402 | ||
5403 | static const ARMCPRegInfo zcr_el2_reginfo = { | |
5404 | .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | |
5405 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 5406 | .access = PL2_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
5407 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), |
5408 | .writefn = zcr_write, .raw_writefn = raw_write | |
5409 | }; | |
5410 | ||
5411 | static const ARMCPRegInfo zcr_no_el2_reginfo = { | |
5412 | .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | |
5413 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 5414 | .access = PL2_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
5415 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore |
5416 | }; | |
5417 | ||
5418 | static const ARMCPRegInfo zcr_el3_reginfo = { | |
5419 | .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | |
5420 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | |
11d7870b | 5421 | .access = PL3_RW, .type = ARM_CP_SVE, |
5be5e8ed RH |
5422 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), |
5423 | .writefn = zcr_write, .raw_writefn = raw_write | |
5424 | }; | |
5425 | ||
9ee98ce8 PM |
5426 | void hw_watchpoint_update(ARMCPU *cpu, int n) |
5427 | { | |
5428 | CPUARMState *env = &cpu->env; | |
5429 | vaddr len = 0; | |
5430 | vaddr wvr = env->cp15.dbgwvr[n]; | |
5431 | uint64_t wcr = env->cp15.dbgwcr[n]; | |
5432 | int mask; | |
5433 | int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; | |
5434 | ||
5435 | if (env->cpu_watchpoint[n]) { | |
5436 | cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); | |
5437 | env->cpu_watchpoint[n] = NULL; | |
5438 | } | |
5439 | ||
5440 | if (!extract64(wcr, 0, 1)) { | |
5441 | /* E bit clear : watchpoint disabled */ | |
5442 | return; | |
5443 | } | |
5444 | ||
5445 | switch (extract64(wcr, 3, 2)) { | |
5446 | case 0: | |
5447 | /* LSC 00 is reserved and must behave as if the wp is disabled */ | |
5448 | return; | |
5449 | case 1: | |
5450 | flags |= BP_MEM_READ; | |
5451 | break; | |
5452 | case 2: | |
5453 | flags |= BP_MEM_WRITE; | |
5454 | break; | |
5455 | case 3: | |
5456 | flags |= BP_MEM_ACCESS; | |
5457 | break; | |
5458 | } | |
5459 | ||
5460 | /* Attempts to use both MASK and BAS fields simultaneously are | |
5461 | * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, | |
5462 | * thus generating a watchpoint for every byte in the masked region. | |
5463 | */ | |
5464 | mask = extract64(wcr, 24, 4); | |
5465 | if (mask == 1 || mask == 2) { | |
5466 | /* Reserved values of MASK; we must act as if the mask value was | |
5467 | * some non-reserved value, or as if the watchpoint were disabled. | |
5468 | * We choose the latter. | |
5469 | */ | |
5470 | return; | |
5471 | } else if (mask) { | |
5472 | /* Watchpoint covers an aligned area up to 2GB in size */ | |
5473 | len = 1ULL << mask; | |
5474 | /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE | |
5475 | * whether the watchpoint fires when the unmasked bits match; we opt | |
5476 | * to generate the exceptions. | |
5477 | */ | |
5478 | wvr &= ~(len - 1); | |
5479 | } else { | |
5480 | /* Watchpoint covers bytes defined by the byte address select bits */ | |
5481 | int bas = extract64(wcr, 5, 8); | |
5482 | int basstart; | |
5483 | ||
5484 | if (bas == 0) { | |
5485 | /* This must act as if the watchpoint is disabled */ | |
5486 | return; | |
5487 | } | |
5488 | ||
5489 | if (extract64(wvr, 2, 1)) { | |
5490 | /* Deprecated case of an only 4-aligned address. BAS[7:4] are | |
5491 | * ignored, and BAS[3:0] define which bytes to watch. | |
5492 | */ | |
5493 | bas &= 0xf; | |
5494 | } | |
5495 | /* The BAS bits are supposed to be programmed to indicate a contiguous | |
5496 | * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether | |
5497 | * we fire for each byte in the word/doubleword addressed by the WVR. | |
5498 | * We choose to ignore any non-zero bits after the first range of 1s. | |
5499 | */ | |
5500 | basstart = ctz32(bas); | |
5501 | len = cto32(bas >> basstart); | |
5502 | wvr += basstart; | |
5503 | } | |
5504 | ||
5505 | cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, | |
5506 | &env->cpu_watchpoint[n]); | |
5507 | } | |
5508 | ||
5509 | void hw_watchpoint_update_all(ARMCPU *cpu) | |
5510 | { | |
5511 | int i; | |
5512 | CPUARMState *env = &cpu->env; | |
5513 | ||
5514 | /* Completely clear out existing QEMU watchpoints and our array, to | |
5515 | * avoid possible stale entries following migration load. | |
5516 | */ | |
5517 | cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); | |
5518 | memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); | |
5519 | ||
5520 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { | |
5521 | hw_watchpoint_update(cpu, i); | |
5522 | } | |
5523 | } | |
5524 | ||
5525 | static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5526 | uint64_t value) | |
5527 | { | |
2fc0cc0e | 5528 | ARMCPU *cpu = env_archcpu(env); |
9ee98ce8 PM |
5529 | int i = ri->crm; |
5530 | ||
5531 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, the | |
5532 | * register reads and behaves as if values written are sign extended. | |
5533 | * Bits [1:0] are RES0. | |
5534 | */ | |
5535 | value = sextract64(value, 0, 49) & ~3ULL; | |
5536 | ||
5537 | raw_write(env, ri, value); | |
5538 | hw_watchpoint_update(cpu, i); | |
5539 | } | |
5540 | ||
5541 | static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5542 | uint64_t value) | |
5543 | { | |
2fc0cc0e | 5544 | ARMCPU *cpu = env_archcpu(env); |
9ee98ce8 PM |
5545 | int i = ri->crm; |
5546 | ||
5547 | raw_write(env, ri, value); | |
5548 | hw_watchpoint_update(cpu, i); | |
5549 | } | |
5550 | ||
46747d15 PM |
5551 | void hw_breakpoint_update(ARMCPU *cpu, int n) |
5552 | { | |
5553 | CPUARMState *env = &cpu->env; | |
5554 | uint64_t bvr = env->cp15.dbgbvr[n]; | |
5555 | uint64_t bcr = env->cp15.dbgbcr[n]; | |
5556 | vaddr addr; | |
5557 | int bt; | |
5558 | int flags = BP_CPU; | |
5559 | ||
5560 | if (env->cpu_breakpoint[n]) { | |
5561 | cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); | |
5562 | env->cpu_breakpoint[n] = NULL; | |
5563 | } | |
5564 | ||
5565 | if (!extract64(bcr, 0, 1)) { | |
5566 | /* E bit clear : watchpoint disabled */ | |
5567 | return; | |
5568 | } | |
5569 | ||
5570 | bt = extract64(bcr, 20, 4); | |
5571 | ||
5572 | switch (bt) { | |
5573 | case 4: /* unlinked address mismatch (reserved if AArch64) */ | |
5574 | case 5: /* linked address mismatch (reserved if AArch64) */ | |
5575 | qemu_log_mask(LOG_UNIMP, | |
0221c8fd | 5576 | "arm: address mismatch breakpoint types not implemented\n"); |
46747d15 PM |
5577 | return; |
5578 | case 0: /* unlinked address match */ | |
5579 | case 1: /* linked address match */ | |
5580 | { | |
5581 | /* Bits [63:49] are hardwired to the value of bit [48]; that is, | |
5582 | * we behave as if the register was sign extended. Bits [1:0] are | |
5583 | * RES0. The BAS field is used to allow setting breakpoints on 16 | |
5584 | * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether | |
5585 | * a bp will fire if the addresses covered by the bp and the addresses | |
5586 | * covered by the insn overlap but the insn doesn't start at the | |
5587 | * start of the bp address range. We choose to require the insn and | |
5588 | * the bp to have the same address. The constraints on writing to | |
5589 | * BAS enforced in dbgbcr_write mean we have only four cases: | |
5590 | * 0b0000 => no breakpoint | |
5591 | * 0b0011 => breakpoint on addr | |
5592 | * 0b1100 => breakpoint on addr + 2 | |
5593 | * 0b1111 => breakpoint on addr | |
5594 | * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). | |
5595 | */ | |
5596 | int bas = extract64(bcr, 5, 4); | |
5597 | addr = sextract64(bvr, 0, 49) & ~3ULL; | |
5598 | if (bas == 0) { | |
5599 | return; | |
5600 | } | |
5601 | if (bas == 0xc) { | |
5602 | addr += 2; | |
5603 | } | |
5604 | break; | |
5605 | } | |
5606 | case 2: /* unlinked context ID match */ | |
5607 | case 8: /* unlinked VMID match (reserved if no EL2) */ | |
5608 | case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ | |
5609 | qemu_log_mask(LOG_UNIMP, | |
0221c8fd | 5610 | "arm: unlinked context breakpoint types not implemented\n"); |
46747d15 PM |
5611 | return; |
5612 | case 9: /* linked VMID match (reserved if no EL2) */ | |
5613 | case 11: /* linked context ID and VMID match (reserved if no EL2) */ | |
5614 | case 3: /* linked context ID match */ | |
5615 | default: | |
5616 | /* We must generate no events for Linked context matches (unless | |
5617 | * they are linked to by some other bp/wp, which is handled in | |
5618 | * updates for the linking bp/wp). We choose to also generate no events | |
5619 | * for reserved values. | |
5620 | */ | |
5621 | return; | |
5622 | } | |
5623 | ||
5624 | cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); | |
5625 | } | |
5626 | ||
5627 | void hw_breakpoint_update_all(ARMCPU *cpu) | |
5628 | { | |
5629 | int i; | |
5630 | CPUARMState *env = &cpu->env; | |
5631 | ||
5632 | /* Completely clear out existing QEMU breakpoints and our array, to | |
5633 | * avoid possible stale entries following migration load. | |
5634 | */ | |
5635 | cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); | |
5636 | memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); | |
5637 | ||
5638 | for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { | |
5639 | hw_breakpoint_update(cpu, i); | |
5640 | } | |
5641 | } | |
5642 | ||
5643 | static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5644 | uint64_t value) | |
5645 | { | |
2fc0cc0e | 5646 | ARMCPU *cpu = env_archcpu(env); |
46747d15 PM |
5647 | int i = ri->crm; |
5648 | ||
5649 | raw_write(env, ri, value); | |
5650 | hw_breakpoint_update(cpu, i); | |
5651 | } | |
5652 | ||
5653 | static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5654 | uint64_t value) | |
5655 | { | |
2fc0cc0e | 5656 | ARMCPU *cpu = env_archcpu(env); |
46747d15 PM |
5657 | int i = ri->crm; |
5658 | ||
5659 | /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only | |
5660 | * copy of BAS[0]. | |
5661 | */ | |
5662 | value = deposit64(value, 6, 1, extract64(value, 5, 1)); | |
5663 | value = deposit64(value, 8, 1, extract64(value, 7, 1)); | |
5664 | ||
5665 | raw_write(env, ri, value); | |
5666 | hw_breakpoint_update(cpu, i); | |
5667 | } | |
5668 | ||
50300698 | 5669 | static void define_debug_regs(ARMCPU *cpu) |
0b45451e | 5670 | { |
50300698 PM |
5671 | /* Define v7 and v8 architectural debug registers. |
5672 | * These are just dummy implementations for now. | |
0b45451e PM |
5673 | */ |
5674 | int i; | |
3ff6fc91 | 5675 | int wrps, brps, ctx_cmps; |
48eb3ae6 PM |
5676 | ARMCPRegInfo dbgdidr = { |
5677 | .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
d6c8cf81 PM |
5678 | .access = PL0_R, .accessfn = access_tda, |
5679 | .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr, | |
48eb3ae6 PM |
5680 | }; |
5681 | ||
3ff6fc91 | 5682 | /* Note that all these register fields hold "number of Xs minus 1". */ |
48eb3ae6 PM |
5683 | brps = extract32(cpu->dbgdidr, 24, 4); |
5684 | wrps = extract32(cpu->dbgdidr, 28, 4); | |
3ff6fc91 PM |
5685 | ctx_cmps = extract32(cpu->dbgdidr, 20, 4); |
5686 | ||
5687 | assert(ctx_cmps <= brps); | |
48eb3ae6 PM |
5688 | |
5689 | /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties | |
5690 | * of the debug registers such as number of breakpoints; | |
5691 | * check that if they both exist then they agree. | |
5692 | */ | |
5693 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
5694 | assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps); | |
5695 | assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps); | |
3ff6fc91 | 5696 | assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps); |
48eb3ae6 | 5697 | } |
0b45451e | 5698 | |
48eb3ae6 | 5699 | define_one_arm_cp_reg(cpu, &dbgdidr); |
50300698 PM |
5700 | define_arm_cp_regs(cpu, debug_cp_reginfo); |
5701 | ||
5702 | if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { | |
5703 | define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); | |
5704 | } | |
5705 | ||
48eb3ae6 | 5706 | for (i = 0; i < brps + 1; i++) { |
0b45451e | 5707 | ARMCPRegInfo dbgregs[] = { |
10aae104 PM |
5708 | { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH, |
5709 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, | |
d6c8cf81 | 5710 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
5711 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), |
5712 | .writefn = dbgbvr_write, .raw_writefn = raw_write | |
5713 | }, | |
10aae104 PM |
5714 | { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH, |
5715 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, | |
d6c8cf81 | 5716 | .access = PL1_RW, .accessfn = access_tda, |
46747d15 PM |
5717 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), |
5718 | .writefn = dbgbcr_write, .raw_writefn = raw_write | |
5719 | }, | |
48eb3ae6 PM |
5720 | REGINFO_SENTINEL |
5721 | }; | |
5722 | define_arm_cp_regs(cpu, dbgregs); | |
5723 | } | |
5724 | ||
5725 | for (i = 0; i < wrps + 1; i++) { | |
5726 | ARMCPRegInfo dbgregs[] = { | |
10aae104 PM |
5727 | { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH, |
5728 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, | |
d6c8cf81 | 5729 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
5730 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), |
5731 | .writefn = dbgwvr_write, .raw_writefn = raw_write | |
5732 | }, | |
10aae104 PM |
5733 | { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH, |
5734 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, | |
d6c8cf81 | 5735 | .access = PL1_RW, .accessfn = access_tda, |
9ee98ce8 PM |
5736 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), |
5737 | .writefn = dbgwcr_write, .raw_writefn = raw_write | |
5738 | }, | |
5739 | REGINFO_SENTINEL | |
0b45451e PM |
5740 | }; |
5741 | define_arm_cp_regs(cpu, dbgregs); | |
5742 | } | |
5743 | } | |
5744 | ||
96a8b92e PM |
5745 | /* We don't know until after realize whether there's a GICv3 |
5746 | * attached, and that is what registers the gicv3 sysregs. | |
5747 | * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1 | |
5748 | * at runtime. | |
5749 | */ | |
5750 | static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5751 | { | |
2fc0cc0e | 5752 | ARMCPU *cpu = env_archcpu(env); |
96a8b92e PM |
5753 | uint64_t pfr1 = cpu->id_pfr1; |
5754 | ||
5755 | if (env->gicv3state) { | |
5756 | pfr1 |= 1 << 28; | |
5757 | } | |
5758 | return pfr1; | |
5759 | } | |
5760 | ||
5761 | static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5762 | { | |
2fc0cc0e | 5763 | ARMCPU *cpu = env_archcpu(env); |
47576b94 | 5764 | uint64_t pfr0 = cpu->isar.id_aa64pfr0; |
96a8b92e PM |
5765 | |
5766 | if (env->gicv3state) { | |
5767 | pfr0 |= 1 << 24; | |
5768 | } | |
5769 | return pfr0; | |
5770 | } | |
5771 | ||
2d7137c1 RH |
5772 | /* Shared logic between LORID and the rest of the LOR* registers. |
5773 | * Secure state has already been delt with. | |
5774 | */ | |
5775 | static CPAccessResult access_lor_ns(CPUARMState *env) | |
5776 | { | |
5777 | int el = arm_current_el(env); | |
5778 | ||
5779 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) { | |
5780 | return CP_ACCESS_TRAP_EL2; | |
5781 | } | |
5782 | if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { | |
5783 | return CP_ACCESS_TRAP_EL3; | |
5784 | } | |
5785 | return CP_ACCESS_OK; | |
5786 | } | |
5787 | ||
5788 | static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri, | |
5789 | bool isread) | |
5790 | { | |
5791 | if (arm_is_secure_below_el3(env)) { | |
5792 | /* Access ok in secure mode. */ | |
5793 | return CP_ACCESS_OK; | |
5794 | } | |
5795 | return access_lor_ns(env); | |
5796 | } | |
5797 | ||
5798 | static CPAccessResult access_lor_other(CPUARMState *env, | |
5799 | const ARMCPRegInfo *ri, bool isread) | |
5800 | { | |
5801 | if (arm_is_secure_below_el3(env)) { | |
5802 | /* Access denied in secure mode. */ | |
5803 | return CP_ACCESS_TRAP; | |
5804 | } | |
5805 | return access_lor_ns(env); | |
5806 | } | |
5807 | ||
967aa94f RH |
5808 | #ifdef TARGET_AARCH64 |
5809 | static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, | |
5810 | bool isread) | |
5811 | { | |
5812 | int el = arm_current_el(env); | |
5813 | ||
5814 | if (el < 2 && | |
5815 | arm_feature(env, ARM_FEATURE_EL2) && | |
5816 | !(arm_hcr_el2_eff(env) & HCR_APK)) { | |
5817 | return CP_ACCESS_TRAP_EL2; | |
5818 | } | |
5819 | if (el < 3 && | |
5820 | arm_feature(env, ARM_FEATURE_EL3) && | |
5821 | !(env->cp15.scr_el3 & SCR_APK)) { | |
5822 | return CP_ACCESS_TRAP_EL3; | |
5823 | } | |
5824 | return CP_ACCESS_OK; | |
5825 | } | |
5826 | ||
5827 | static const ARMCPRegInfo pauth_reginfo[] = { | |
5828 | { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64, | |
5829 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0, | |
5830 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5831 | .fieldoffset = offsetof(CPUARMState, keys.apda.lo) }, |
967aa94f RH |
5832 | { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
5833 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1, | |
5834 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5835 | .fieldoffset = offsetof(CPUARMState, keys.apda.hi) }, |
967aa94f RH |
5836 | { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
5837 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2, | |
5838 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5839 | .fieldoffset = offsetof(CPUARMState, keys.apdb.lo) }, |
967aa94f RH |
5840 | { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
5841 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3, | |
5842 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5843 | .fieldoffset = offsetof(CPUARMState, keys.apdb.hi) }, |
967aa94f RH |
5844 | { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
5845 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0, | |
5846 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5847 | .fieldoffset = offsetof(CPUARMState, keys.apga.lo) }, |
967aa94f RH |
5848 | { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
5849 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1, | |
5850 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5851 | .fieldoffset = offsetof(CPUARMState, keys.apga.hi) }, |
967aa94f RH |
5852 | { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
5853 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0, | |
5854 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5855 | .fieldoffset = offsetof(CPUARMState, keys.apia.lo) }, |
967aa94f RH |
5856 | { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
5857 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1, | |
5858 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5859 | .fieldoffset = offsetof(CPUARMState, keys.apia.hi) }, |
967aa94f RH |
5860 | { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
5861 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2, | |
5862 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5863 | .fieldoffset = offsetof(CPUARMState, keys.apib.lo) }, |
967aa94f RH |
5864 | { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
5865 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3, | |
5866 | .access = PL1_RW, .accessfn = access_pauth, | |
108b3ba8 | 5867 | .fieldoffset = offsetof(CPUARMState, keys.apib.hi) }, |
967aa94f RH |
5868 | REGINFO_SENTINEL |
5869 | }; | |
de390645 RH |
5870 | |
5871 | static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) | |
5872 | { | |
5873 | Error *err = NULL; | |
5874 | uint64_t ret; | |
5875 | ||
5876 | /* Success sets NZCV = 0000. */ | |
5877 | env->NF = env->CF = env->VF = 0, env->ZF = 1; | |
5878 | ||
5879 | if (qemu_guest_getrandom(&ret, sizeof(ret), &err) < 0) { | |
5880 | /* | |
5881 | * ??? Failed, for unknown reasons in the crypto subsystem. | |
5882 | * The best we can do is log the reason and return the | |
5883 | * timed-out indication to the guest. There is no reason | |
5884 | * we know to expect this failure to be transitory, so the | |
5885 | * guest may well hang retrying the operation. | |
5886 | */ | |
5887 | qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", | |
5888 | ri->name, error_get_pretty(err)); | |
5889 | error_free(err); | |
5890 | ||
5891 | env->ZF = 0; /* NZCF = 0100 */ | |
5892 | return 0; | |
5893 | } | |
5894 | return ret; | |
5895 | } | |
5896 | ||
5897 | /* We do not support re-seeding, so the two registers operate the same. */ | |
5898 | static const ARMCPRegInfo rndr_reginfo[] = { | |
5899 | { .name = "RNDR", .state = ARM_CP_STATE_AA64, | |
5900 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | |
5901 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 0, | |
5902 | .access = PL0_R, .readfn = rndr_readfn }, | |
5903 | { .name = "RNDRRS", .state = ARM_CP_STATE_AA64, | |
5904 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | |
5905 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1, | |
5906 | .access = PL0_R, .readfn = rndr_readfn }, | |
5907 | REGINFO_SENTINEL | |
5908 | }; | |
967aa94f RH |
5909 | #endif |
5910 | ||
cb570bd3 RH |
5911 | static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, |
5912 | bool isread) | |
5913 | { | |
5914 | int el = arm_current_el(env); | |
5915 | ||
5916 | if (el == 0) { | |
5917 | uint64_t sctlr = arm_sctlr(env, el); | |
5918 | if (!(sctlr & SCTLR_EnRCTX)) { | |
5919 | return CP_ACCESS_TRAP; | |
5920 | } | |
5921 | } else if (el == 1) { | |
5922 | uint64_t hcr = arm_hcr_el2_eff(env); | |
5923 | if (hcr & HCR_NV) { | |
5924 | return CP_ACCESS_TRAP_EL2; | |
5925 | } | |
5926 | } | |
5927 | return CP_ACCESS_OK; | |
5928 | } | |
5929 | ||
5930 | static const ARMCPRegInfo predinv_reginfo[] = { | |
5931 | { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64, | |
5932 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4, | |
5933 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
5934 | { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64, | |
5935 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5, | |
5936 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
5937 | { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64, | |
5938 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7, | |
5939 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
5940 | /* | |
5941 | * Note the AArch32 opcodes have a different OPC1. | |
5942 | */ | |
5943 | { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32, | |
5944 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4, | |
5945 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
5946 | { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32, | |
5947 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5, | |
5948 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
5949 | { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32, | |
5950 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7, | |
5951 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | |
5952 | REGINFO_SENTINEL | |
5953 | }; | |
5954 | ||
2ceb98c0 PM |
5955 | void register_cp_regs_for_features(ARMCPU *cpu) |
5956 | { | |
5957 | /* Register all the coprocessor registers based on feature bits */ | |
5958 | CPUARMState *env = &cpu->env; | |
5959 | if (arm_feature(env, ARM_FEATURE_M)) { | |
5960 | /* M profile has no coprocessor registers */ | |
5961 | return; | |
5962 | } | |
5963 | ||
e9aa6c21 | 5964 | define_arm_cp_regs(cpu, cp_reginfo); |
9449fdf6 PM |
5965 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
5966 | /* Must go early as it is full of wildcards that may be | |
5967 | * overridden by later definitions. | |
5968 | */ | |
5969 | define_arm_cp_regs(cpu, not_v8_cp_reginfo); | |
5970 | } | |
5971 | ||
7d57f408 | 5972 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8515a092 PM |
5973 | /* The ID registers all have impdef reset values */ |
5974 | ARMCPRegInfo v6_idregs[] = { | |
0ff644a7 PM |
5975 | { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, |
5976 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
5977 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 5978 | .resetvalue = cpu->id_pfr0 }, |
96a8b92e PM |
5979 | /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know |
5980 | * the value of the GIC field until after we define these regs. | |
5981 | */ | |
0ff644a7 PM |
5982 | { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, |
5983 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | |
96a8b92e PM |
5984 | .access = PL1_R, .type = ARM_CP_NO_RAW, |
5985 | .readfn = id_pfr1_read, | |
5986 | .writefn = arm_cp_write_ignore }, | |
0ff644a7 PM |
5987 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, |
5988 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | |
5989 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 5990 | .resetvalue = cpu->id_dfr0 }, |
0ff644a7 PM |
5991 | { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, |
5992 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, | |
5993 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 5994 | .resetvalue = cpu->id_afr0 }, |
0ff644a7 PM |
5995 | { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, |
5996 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, | |
5997 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 5998 | .resetvalue = cpu->id_mmfr0 }, |
0ff644a7 PM |
5999 | { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, |
6000 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, | |
6001 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 6002 | .resetvalue = cpu->id_mmfr1 }, |
0ff644a7 PM |
6003 | { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, |
6004 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, | |
6005 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 6006 | .resetvalue = cpu->id_mmfr2 }, |
0ff644a7 PM |
6007 | { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, |
6008 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, | |
6009 | .access = PL1_R, .type = ARM_CP_CONST, | |
8515a092 | 6010 | .resetvalue = cpu->id_mmfr3 }, |
0ff644a7 PM |
6011 | { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, |
6012 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
6013 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 6014 | .resetvalue = cpu->isar.id_isar0 }, |
0ff644a7 PM |
6015 | { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, |
6016 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, | |
6017 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 6018 | .resetvalue = cpu->isar.id_isar1 }, |
0ff644a7 PM |
6019 | { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, |
6020 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
6021 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 6022 | .resetvalue = cpu->isar.id_isar2 }, |
0ff644a7 PM |
6023 | { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, |
6024 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, | |
6025 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 6026 | .resetvalue = cpu->isar.id_isar3 }, |
0ff644a7 PM |
6027 | { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, |
6028 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, | |
6029 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 6030 | .resetvalue = cpu->isar.id_isar4 }, |
0ff644a7 PM |
6031 | { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, |
6032 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, | |
6033 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 6034 | .resetvalue = cpu->isar.id_isar5 }, |
e20d84c1 PM |
6035 | { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, |
6036 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, | |
6037 | .access = PL1_R, .type = ARM_CP_CONST, | |
6038 | .resetvalue = cpu->id_mmfr4 }, | |
802abf40 | 6039 | { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
6040 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, |
6041 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 6042 | .resetvalue = cpu->isar.id_isar6 }, |
8515a092 PM |
6043 | REGINFO_SENTINEL |
6044 | }; | |
6045 | define_arm_cp_regs(cpu, v6_idregs); | |
7d57f408 PM |
6046 | define_arm_cp_regs(cpu, v6_cp_reginfo); |
6047 | } else { | |
6048 | define_arm_cp_regs(cpu, not_v6_cp_reginfo); | |
6049 | } | |
4d31c596 PM |
6050 | if (arm_feature(env, ARM_FEATURE_V6K)) { |
6051 | define_arm_cp_regs(cpu, v6k_cp_reginfo); | |
6052 | } | |
5e5cf9e3 | 6053 | if (arm_feature(env, ARM_FEATURE_V7MP) && |
452a0955 | 6054 | !arm_feature(env, ARM_FEATURE_PMSA)) { |
995939a6 PM |
6055 | define_arm_cp_regs(cpu, v7mp_cp_reginfo); |
6056 | } | |
327dd510 AL |
6057 | if (arm_feature(env, ARM_FEATURE_V7VE)) { |
6058 | define_arm_cp_regs(cpu, pmovsset_cp_reginfo); | |
6059 | } | |
e9aa6c21 | 6060 | if (arm_feature(env, ARM_FEATURE_V7)) { |
200ac0ef | 6061 | /* v7 performance monitor control register: same implementor |
ac689a2e AL |
6062 | * field as main ID register, and we implement four counters in |
6063 | * addition to the cycle count register. | |
200ac0ef | 6064 | */ |
ac689a2e | 6065 | unsigned int i, pmcrn = 4; |
200ac0ef PM |
6066 | ARMCPRegInfo pmcr = { |
6067 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | |
8521466b | 6068 | .access = PL0_RW, |
7a0e58fa | 6069 | .type = ARM_CP_IO | ARM_CP_ALIAS, |
8521466b | 6070 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), |
fcd25206 PM |
6071 | .accessfn = pmreg_access, .writefn = pmcr_write, |
6072 | .raw_writefn = raw_write, | |
200ac0ef | 6073 | }; |
8521466b AF |
6074 | ARMCPRegInfo pmcr64 = { |
6075 | .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, | |
6076 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, | |
6077 | .access = PL0_RW, .accessfn = pmreg_access, | |
6078 | .type = ARM_CP_IO, | |
6079 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), | |
ac689a2e | 6080 | .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT), |
8521466b AF |
6081 | .writefn = pmcr_write, .raw_writefn = raw_write, |
6082 | }; | |
7c2cb42b | 6083 | define_one_arm_cp_reg(cpu, &pmcr); |
8521466b | 6084 | define_one_arm_cp_reg(cpu, &pmcr64); |
5ecdd3e4 AL |
6085 | for (i = 0; i < pmcrn; i++) { |
6086 | char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i); | |
6087 | char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i); | |
6088 | char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i); | |
6089 | char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i); | |
6090 | ARMCPRegInfo pmev_regs[] = { | |
62c7ec34 | 6091 | { .name = pmevcntr_name, .cp = 15, .crn = 14, |
5ecdd3e4 AL |
6092 | .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, |
6093 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6094 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, | |
6095 | .accessfn = pmreg_access }, | |
6096 | { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64, | |
62c7ec34 | 6097 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)), |
5ecdd3e4 AL |
6098 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, |
6099 | .type = ARM_CP_IO, | |
6100 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, | |
6101 | .raw_readfn = pmevcntr_rawread, | |
6102 | .raw_writefn = pmevcntr_rawwrite }, | |
62c7ec34 | 6103 | { .name = pmevtyper_name, .cp = 15, .crn = 14, |
5ecdd3e4 AL |
6104 | .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, |
6105 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
6106 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | |
6107 | .accessfn = pmreg_access }, | |
6108 | { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64, | |
62c7ec34 | 6109 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)), |
5ecdd3e4 AL |
6110 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, |
6111 | .type = ARM_CP_IO, | |
6112 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | |
6113 | .raw_writefn = pmevtyper_rawwrite }, | |
6114 | REGINFO_SENTINEL | |
6115 | }; | |
6116 | define_arm_cp_regs(cpu, pmev_regs); | |
6117 | g_free(pmevcntr_name); | |
6118 | g_free(pmevcntr_el0_name); | |
6119 | g_free(pmevtyper_name); | |
6120 | g_free(pmevtyper_el0_name); | |
6121 | } | |
776d4e5c | 6122 | ARMCPRegInfo clidr = { |
7da845b0 PM |
6123 | .name = "CLIDR", .state = ARM_CP_STATE_BOTH, |
6124 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | |
776d4e5c PM |
6125 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr |
6126 | }; | |
776d4e5c | 6127 | define_one_arm_cp_reg(cpu, &clidr); |
e9aa6c21 | 6128 | define_arm_cp_regs(cpu, v7_cp_reginfo); |
50300698 | 6129 | define_debug_regs(cpu); |
7d57f408 PM |
6130 | } else { |
6131 | define_arm_cp_regs(cpu, not_v7_cp_reginfo); | |
e9aa6c21 | 6132 | } |
cad86737 AL |
6133 | if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 && |
6134 | FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) { | |
6135 | ARMCPRegInfo v81_pmu_regs[] = { | |
6136 | { .name = "PMCEID2", .state = ARM_CP_STATE_AA32, | |
6137 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4, | |
6138 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6139 | .resetvalue = extract64(cpu->pmceid0, 32, 32) }, | |
6140 | { .name = "PMCEID3", .state = ARM_CP_STATE_AA32, | |
6141 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5, | |
6142 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6143 | .resetvalue = extract64(cpu->pmceid1, 32, 32) }, | |
6144 | REGINFO_SENTINEL | |
6145 | }; | |
6146 | define_arm_cp_regs(cpu, v81_pmu_regs); | |
6147 | } | |
b0d2b7d0 | 6148 | if (arm_feature(env, ARM_FEATURE_V8)) { |
e20d84c1 PM |
6149 | /* AArch64 ID registers, which all have impdef reset values. |
6150 | * Note that within the ID register ranges the unused slots | |
6151 | * must all RAZ, not UNDEF; future architecture versions may | |
6152 | * define new registers here. | |
6153 | */ | |
e60cef86 | 6154 | ARMCPRegInfo v8_idregs[] = { |
96a8b92e PM |
6155 | /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't |
6156 | * know the right value for the GIC field until after we | |
6157 | * define these regs. | |
6158 | */ | |
e60cef86 PM |
6159 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, |
6160 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | |
96a8b92e PM |
6161 | .access = PL1_R, .type = ARM_CP_NO_RAW, |
6162 | .readfn = id_aa64pfr0_read, | |
6163 | .writefn = arm_cp_write_ignore }, | |
e60cef86 PM |
6164 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, |
6165 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | |
6166 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 6167 | .resetvalue = cpu->isar.id_aa64pfr1}, |
e20d84c1 PM |
6168 | { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
6169 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, | |
6170 | .access = PL1_R, .type = ARM_CP_CONST, | |
6171 | .resetvalue = 0 }, | |
6172 | { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6173 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, | |
6174 | .access = PL1_R, .type = ARM_CP_CONST, | |
6175 | .resetvalue = 0 }, | |
9516d772 | 6176 | { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
6177 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, |
6178 | .access = PL1_R, .type = ARM_CP_CONST, | |
9516d772 | 6179 | /* At present, only SVEver == 0 is defined anyway. */ |
e20d84c1 PM |
6180 | .resetvalue = 0 }, |
6181 | { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6182 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, | |
6183 | .access = PL1_R, .type = ARM_CP_CONST, | |
6184 | .resetvalue = 0 }, | |
6185 | { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6186 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, | |
6187 | .access = PL1_R, .type = ARM_CP_CONST, | |
6188 | .resetvalue = 0 }, | |
6189 | { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6190 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, | |
6191 | .access = PL1_R, .type = ARM_CP_CONST, | |
6192 | .resetvalue = 0 }, | |
e60cef86 PM |
6193 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, |
6194 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | |
6195 | .access = PL1_R, .type = ARM_CP_CONST, | |
d6f02ce3 | 6196 | .resetvalue = cpu->id_aa64dfr0 }, |
e60cef86 PM |
6197 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, |
6198 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | |
6199 | .access = PL1_R, .type = ARM_CP_CONST, | |
6200 | .resetvalue = cpu->id_aa64dfr1 }, | |
e20d84c1 PM |
6201 | { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
6202 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, | |
6203 | .access = PL1_R, .type = ARM_CP_CONST, | |
6204 | .resetvalue = 0 }, | |
6205 | { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6206 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, | |
6207 | .access = PL1_R, .type = ARM_CP_CONST, | |
6208 | .resetvalue = 0 }, | |
e60cef86 PM |
6209 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, |
6210 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | |
6211 | .access = PL1_R, .type = ARM_CP_CONST, | |
6212 | .resetvalue = cpu->id_aa64afr0 }, | |
6213 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | |
6214 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | |
6215 | .access = PL1_R, .type = ARM_CP_CONST, | |
6216 | .resetvalue = cpu->id_aa64afr1 }, | |
e20d84c1 PM |
6217 | { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
6218 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, | |
6219 | .access = PL1_R, .type = ARM_CP_CONST, | |
6220 | .resetvalue = 0 }, | |
6221 | { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6222 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, | |
6223 | .access = PL1_R, .type = ARM_CP_CONST, | |
6224 | .resetvalue = 0 }, | |
e60cef86 PM |
6225 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, |
6226 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | |
6227 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 6228 | .resetvalue = cpu->isar.id_aa64isar0 }, |
e60cef86 PM |
6229 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, |
6230 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | |
6231 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 6232 | .resetvalue = cpu->isar.id_aa64isar1 }, |
e20d84c1 PM |
6233 | { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
6234 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, | |
6235 | .access = PL1_R, .type = ARM_CP_CONST, | |
6236 | .resetvalue = 0 }, | |
6237 | { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6238 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, | |
6239 | .access = PL1_R, .type = ARM_CP_CONST, | |
6240 | .resetvalue = 0 }, | |
6241 | { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6242 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, | |
6243 | .access = PL1_R, .type = ARM_CP_CONST, | |
6244 | .resetvalue = 0 }, | |
6245 | { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6246 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, | |
6247 | .access = PL1_R, .type = ARM_CP_CONST, | |
6248 | .resetvalue = 0 }, | |
6249 | { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6250 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, | |
6251 | .access = PL1_R, .type = ARM_CP_CONST, | |
6252 | .resetvalue = 0 }, | |
6253 | { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6254 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, | |
6255 | .access = PL1_R, .type = ARM_CP_CONST, | |
6256 | .resetvalue = 0 }, | |
e60cef86 PM |
6257 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, |
6258 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
6259 | .access = PL1_R, .type = ARM_CP_CONST, | |
3dc91ddb | 6260 | .resetvalue = cpu->isar.id_aa64mmfr0 }, |
e60cef86 PM |
6261 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, |
6262 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | |
6263 | .access = PL1_R, .type = ARM_CP_CONST, | |
3dc91ddb | 6264 | .resetvalue = cpu->isar.id_aa64mmfr1 }, |
e20d84c1 PM |
6265 | { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
6266 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, | |
6267 | .access = PL1_R, .type = ARM_CP_CONST, | |
6268 | .resetvalue = 0 }, | |
6269 | { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6270 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, | |
6271 | .access = PL1_R, .type = ARM_CP_CONST, | |
6272 | .resetvalue = 0 }, | |
6273 | { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6274 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, | |
6275 | .access = PL1_R, .type = ARM_CP_CONST, | |
6276 | .resetvalue = 0 }, | |
6277 | { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6278 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, | |
6279 | .access = PL1_R, .type = ARM_CP_CONST, | |
6280 | .resetvalue = 0 }, | |
6281 | { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6282 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, | |
6283 | .access = PL1_R, .type = ARM_CP_CONST, | |
6284 | .resetvalue = 0 }, | |
6285 | { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6286 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, | |
6287 | .access = PL1_R, .type = ARM_CP_CONST, | |
6288 | .resetvalue = 0 }, | |
a50c0f51 PM |
6289 | { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, |
6290 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
6291 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 6292 | .resetvalue = cpu->isar.mvfr0 }, |
a50c0f51 PM |
6293 | { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, |
6294 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
6295 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 6296 | .resetvalue = cpu->isar.mvfr1 }, |
a50c0f51 PM |
6297 | { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, |
6298 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
6299 | .access = PL1_R, .type = ARM_CP_CONST, | |
47576b94 | 6300 | .resetvalue = cpu->isar.mvfr2 }, |
e20d84c1 PM |
6301 | { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
6302 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, | |
6303 | .access = PL1_R, .type = ARM_CP_CONST, | |
6304 | .resetvalue = 0 }, | |
6305 | { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6306 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, | |
6307 | .access = PL1_R, .type = ARM_CP_CONST, | |
6308 | .resetvalue = 0 }, | |
6309 | { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6310 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, | |
6311 | .access = PL1_R, .type = ARM_CP_CONST, | |
6312 | .resetvalue = 0 }, | |
6313 | { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6314 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, | |
6315 | .access = PL1_R, .type = ARM_CP_CONST, | |
6316 | .resetvalue = 0 }, | |
6317 | { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
6318 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, | |
6319 | .access = PL1_R, .type = ARM_CP_CONST, | |
6320 | .resetvalue = 0 }, | |
4054bfa9 AF |
6321 | { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, |
6322 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, | |
6323 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
cad86737 | 6324 | .resetvalue = extract64(cpu->pmceid0, 0, 32) }, |
4054bfa9 AF |
6325 | { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, |
6326 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, | |
6327 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6328 | .resetvalue = cpu->pmceid0 }, | |
6329 | { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, | |
6330 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, | |
6331 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
cad86737 | 6332 | .resetvalue = extract64(cpu->pmceid1, 0, 32) }, |
4054bfa9 AF |
6333 | { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, |
6334 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, | |
6335 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
6336 | .resetvalue = cpu->pmceid1 }, | |
e60cef86 PM |
6337 | REGINFO_SENTINEL |
6338 | }; | |
6c5c0fec AB |
6339 | #ifdef CONFIG_USER_ONLY |
6340 | ARMCPRegUserSpaceInfo v8_user_idregs[] = { | |
6341 | { .name = "ID_AA64PFR0_EL1", | |
6342 | .exported_bits = 0x000f000f00ff0000, | |
6343 | .fixed_bits = 0x0000000000000011 }, | |
6344 | { .name = "ID_AA64PFR1_EL1", | |
6345 | .exported_bits = 0x00000000000000f0 }, | |
d040242e AB |
6346 | { .name = "ID_AA64PFR*_EL1_RESERVED", |
6347 | .is_glob = true }, | |
6c5c0fec AB |
6348 | { .name = "ID_AA64ZFR0_EL1" }, |
6349 | { .name = "ID_AA64MMFR0_EL1", | |
6350 | .fixed_bits = 0x00000000ff000000 }, | |
6351 | { .name = "ID_AA64MMFR1_EL1" }, | |
d040242e AB |
6352 | { .name = "ID_AA64MMFR*_EL1_RESERVED", |
6353 | .is_glob = true }, | |
6c5c0fec AB |
6354 | { .name = "ID_AA64DFR0_EL1", |
6355 | .fixed_bits = 0x0000000000000006 }, | |
6356 | { .name = "ID_AA64DFR1_EL1" }, | |
d040242e AB |
6357 | { .name = "ID_AA64DFR*_EL1_RESERVED", |
6358 | .is_glob = true }, | |
6359 | { .name = "ID_AA64AFR*", | |
6360 | .is_glob = true }, | |
6c5c0fec AB |
6361 | { .name = "ID_AA64ISAR0_EL1", |
6362 | .exported_bits = 0x00fffffff0fffff0 }, | |
6363 | { .name = "ID_AA64ISAR1_EL1", | |
6364 | .exported_bits = 0x000000f0ffffffff }, | |
d040242e AB |
6365 | { .name = "ID_AA64ISAR*_EL1_RESERVED", |
6366 | .is_glob = true }, | |
6c5c0fec AB |
6367 | REGUSERINFO_SENTINEL |
6368 | }; | |
6369 | modify_arm_cp_regs(v8_idregs, v8_user_idregs); | |
6370 | #endif | |
be8e8128 GB |
6371 | /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ |
6372 | if (!arm_feature(env, ARM_FEATURE_EL3) && | |
6373 | !arm_feature(env, ARM_FEATURE_EL2)) { | |
6374 | ARMCPRegInfo rvbar = { | |
6375 | .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, | |
6376 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, | |
6377 | .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar | |
6378 | }; | |
6379 | define_one_arm_cp_reg(cpu, &rvbar); | |
6380 | } | |
e60cef86 | 6381 | define_arm_cp_regs(cpu, v8_idregs); |
b0d2b7d0 PM |
6382 | define_arm_cp_regs(cpu, v8_cp_reginfo); |
6383 | } | |
3b685ba7 | 6384 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
f0d574d6 | 6385 | uint64_t vmpidr_def = mpidr_read_val(env); |
731de9e6 EI |
6386 | ARMCPRegInfo vpidr_regs[] = { |
6387 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | |
6388 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
6389 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
36476562 PM |
6390 | .resetvalue = cpu->midr, .type = ARM_CP_ALIAS, |
6391 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) }, | |
731de9e6 EI |
6392 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, |
6393 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
6394 | .access = PL2_RW, .resetvalue = cpu->midr, | |
6395 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
f0d574d6 EI |
6396 | { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, |
6397 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
6398 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
36476562 PM |
6399 | .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS, |
6400 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) }, | |
f0d574d6 EI |
6401 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, |
6402 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
6403 | .access = PL2_RW, | |
6404 | .resetvalue = vmpidr_def, | |
6405 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, | |
731de9e6 EI |
6406 | REGINFO_SENTINEL |
6407 | }; | |
6408 | define_arm_cp_regs(cpu, vpidr_regs); | |
4771cd01 | 6409 | define_arm_cp_regs(cpu, el2_cp_reginfo); |
ce4afed8 PM |
6410 | if (arm_feature(env, ARM_FEATURE_V8)) { |
6411 | define_arm_cp_regs(cpu, el2_v8_cp_reginfo); | |
6412 | } | |
be8e8128 GB |
6413 | /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ |
6414 | if (!arm_feature(env, ARM_FEATURE_EL3)) { | |
6415 | ARMCPRegInfo rvbar = { | |
6416 | .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, | |
6417 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, | |
6418 | .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar | |
6419 | }; | |
6420 | define_one_arm_cp_reg(cpu, &rvbar); | |
6421 | } | |
d42e3c26 EI |
6422 | } else { |
6423 | /* If EL2 is missing but higher ELs are enabled, we need to | |
6424 | * register the no_el2 reginfos. | |
6425 | */ | |
6426 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
f0d574d6 EI |
6427 | /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value |
6428 | * of MIDR_EL1 and MPIDR_EL1. | |
731de9e6 EI |
6429 | */ |
6430 | ARMCPRegInfo vpidr_regs[] = { | |
6431 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH, | |
6432 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
6433 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
6434 | .type = ARM_CP_CONST, .resetvalue = cpu->midr, | |
6435 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, | |
f0d574d6 EI |
6436 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
6437 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
6438 | .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, | |
6439 | .type = ARM_CP_NO_RAW, | |
6440 | .writefn = arm_cp_write_ignore, .readfn = mpidr_read }, | |
731de9e6 EI |
6441 | REGINFO_SENTINEL |
6442 | }; | |
6443 | define_arm_cp_regs(cpu, vpidr_regs); | |
4771cd01 | 6444 | define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); |
ce4afed8 PM |
6445 | if (arm_feature(env, ARM_FEATURE_V8)) { |
6446 | define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo); | |
6447 | } | |
d42e3c26 | 6448 | } |
3b685ba7 | 6449 | } |
81547d66 | 6450 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0f1a3b24 | 6451 | define_arm_cp_regs(cpu, el3_cp_reginfo); |
e24fdd23 PM |
6452 | ARMCPRegInfo el3_regs[] = { |
6453 | { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, | |
6454 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, | |
6455 | .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar }, | |
6456 | { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, | |
6457 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, | |
6458 | .access = PL3_RW, | |
6459 | .raw_writefn = raw_write, .writefn = sctlr_write, | |
6460 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), | |
6461 | .resetvalue = cpu->reset_sctlr }, | |
6462 | REGINFO_SENTINEL | |
be8e8128 | 6463 | }; |
e24fdd23 PM |
6464 | |
6465 | define_arm_cp_regs(cpu, el3_regs); | |
81547d66 | 6466 | } |
2f027fc5 PM |
6467 | /* The behaviour of NSACR is sufficiently various that we don't |
6468 | * try to describe it in a single reginfo: | |
6469 | * if EL3 is 64 bit, then trap to EL3 from S EL1, | |
6470 | * reads as constant 0xc00 from NS EL1 and NS EL2 | |
6471 | * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 | |
6472 | * if v7 without EL3, register doesn't exist | |
6473 | * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 | |
6474 | */ | |
6475 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
6476 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
6477 | ARMCPRegInfo nsacr = { | |
6478 | .name = "NSACR", .type = ARM_CP_CONST, | |
6479 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
6480 | .access = PL1_RW, .accessfn = nsacr_access, | |
6481 | .resetvalue = 0xc00 | |
6482 | }; | |
6483 | define_one_arm_cp_reg(cpu, &nsacr); | |
6484 | } else { | |
6485 | ARMCPRegInfo nsacr = { | |
6486 | .name = "NSACR", | |
6487 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
6488 | .access = PL3_RW | PL1_R, | |
6489 | .resetvalue = 0, | |
6490 | .fieldoffset = offsetof(CPUARMState, cp15.nsacr) | |
6491 | }; | |
6492 | define_one_arm_cp_reg(cpu, &nsacr); | |
6493 | } | |
6494 | } else { | |
6495 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
6496 | ARMCPRegInfo nsacr = { | |
6497 | .name = "NSACR", .type = ARM_CP_CONST, | |
6498 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
6499 | .access = PL1_R, | |
6500 | .resetvalue = 0xc00 | |
6501 | }; | |
6502 | define_one_arm_cp_reg(cpu, &nsacr); | |
6503 | } | |
6504 | } | |
6505 | ||
452a0955 | 6506 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
6cb0b013 PC |
6507 | if (arm_feature(env, ARM_FEATURE_V6)) { |
6508 | /* PMSAv6 not implemented */ | |
6509 | assert(arm_feature(env, ARM_FEATURE_V7)); | |
6510 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); | |
6511 | define_arm_cp_regs(cpu, pmsav7_cp_reginfo); | |
6512 | } else { | |
6513 | define_arm_cp_regs(cpu, pmsav5_cp_reginfo); | |
6514 | } | |
18032bec | 6515 | } else { |
8e5d75c9 | 6516 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); |
18032bec | 6517 | define_arm_cp_regs(cpu, vmsa_cp_reginfo); |
ab638a32 RH |
6518 | /* TTCBR2 is introduced with ARMv8.2-A32HPD. */ |
6519 | if (FIELD_EX32(cpu->id_mmfr4, ID_MMFR4, HPDS) != 0) { | |
6520 | define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); | |
6521 | } | |
18032bec | 6522 | } |
c326b979 PM |
6523 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
6524 | define_arm_cp_regs(cpu, t2ee_cp_reginfo); | |
6525 | } | |
6cc7a3ae PM |
6526 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
6527 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); | |
6528 | } | |
4a501606 PM |
6529 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
6530 | define_arm_cp_regs(cpu, vapa_cp_reginfo); | |
6531 | } | |
c4804214 PM |
6532 | if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { |
6533 | define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); | |
6534 | } | |
6535 | if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { | |
6536 | define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); | |
6537 | } | |
6538 | if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { | |
6539 | define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); | |
6540 | } | |
18032bec PM |
6541 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
6542 | define_arm_cp_regs(cpu, omap_cp_reginfo); | |
6543 | } | |
34f90529 PM |
6544 | if (arm_feature(env, ARM_FEATURE_STRONGARM)) { |
6545 | define_arm_cp_regs(cpu, strongarm_cp_reginfo); | |
6546 | } | |
1047b9d7 PM |
6547 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
6548 | define_arm_cp_regs(cpu, xscale_cp_reginfo); | |
6549 | } | |
6550 | if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { | |
6551 | define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); | |
6552 | } | |
7ac681cf PM |
6553 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
6554 | define_arm_cp_regs(cpu, lpae_cp_reginfo); | |
6555 | } | |
7884849c PM |
6556 | /* Slightly awkwardly, the OMAP and StrongARM cores need all of |
6557 | * cp15 crn=0 to be writes-ignored, whereas for other cores they should | |
6558 | * be read-only (ie write causes UNDEF exception). | |
6559 | */ | |
6560 | { | |
00a29f3d PM |
6561 | ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { |
6562 | /* Pre-v8 MIDR space. | |
6563 | * Note that the MIDR isn't a simple constant register because | |
7884849c PM |
6564 | * of the TI925 behaviour where writes to another register can |
6565 | * cause the MIDR value to change. | |
97ce8d61 PC |
6566 | * |
6567 | * Unimplemented registers in the c15 0 0 0 space default to | |
6568 | * MIDR. Define MIDR first as this entire space, then CTR, TCMTR | |
6569 | * and friends override accordingly. | |
7884849c PM |
6570 | */ |
6571 | { .name = "MIDR", | |
97ce8d61 | 6572 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, |
7884849c | 6573 | .access = PL1_R, .resetvalue = cpu->midr, |
d4e6df63 | 6574 | .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, |
731de9e6 | 6575 | .readfn = midr_read, |
97ce8d61 PC |
6576 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
6577 | .type = ARM_CP_OVERRIDE }, | |
7884849c PM |
6578 | /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ |
6579 | { .name = "DUMMY", | |
6580 | .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, | |
6581 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6582 | { .name = "DUMMY", | |
6583 | .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, | |
6584 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6585 | { .name = "DUMMY", | |
6586 | .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, | |
6587 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6588 | { .name = "DUMMY", | |
6589 | .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, | |
6590 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6591 | { .name = "DUMMY", | |
6592 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | |
6593 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6594 | REGINFO_SENTINEL | |
6595 | }; | |
00a29f3d | 6596 | ARMCPRegInfo id_v8_midr_cp_reginfo[] = { |
00a29f3d PM |
6597 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, |
6598 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, | |
731de9e6 EI |
6599 | .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, |
6600 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), | |
6601 | .readfn = midr_read }, | |
ac00c79f SF |
6602 | /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ |
6603 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
6604 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
6605 | .access = PL1_R, .resetvalue = cpu->midr }, | |
6606 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, | |
6607 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, | |
6608 | .access = PL1_R, .resetvalue = cpu->midr }, | |
00a29f3d PM |
6609 | { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, |
6610 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, | |
13b72b2b | 6611 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, |
00a29f3d PM |
6612 | REGINFO_SENTINEL |
6613 | }; | |
6614 | ARMCPRegInfo id_cp_reginfo[] = { | |
6615 | /* These are common to v8 and pre-v8 */ | |
6616 | { .name = "CTR", | |
6617 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, | |
6618 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
6619 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, | |
6620 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, | |
6621 | .access = PL0_R, .accessfn = ctr_el0_access, | |
6622 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
6623 | /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ | |
6624 | { .name = "TCMTR", | |
6625 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, | |
6626 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
00a29f3d PM |
6627 | REGINFO_SENTINEL |
6628 | }; | |
8085ce63 PC |
6629 | /* TLBTR is specific to VMSA */ |
6630 | ARMCPRegInfo id_tlbtr_reginfo = { | |
6631 | .name = "TLBTR", | |
6632 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, | |
6633 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0, | |
6634 | }; | |
3281af81 PC |
6635 | /* MPUIR is specific to PMSA V6+ */ |
6636 | ARMCPRegInfo id_mpuir_reginfo = { | |
6637 | .name = "MPUIR", | |
6638 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
6639 | .access = PL1_R, .type = ARM_CP_CONST, | |
6640 | .resetvalue = cpu->pmsav7_dregion << 8 | |
6641 | }; | |
7884849c PM |
6642 | ARMCPRegInfo crn0_wi_reginfo = { |
6643 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, | |
6644 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | |
6645 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | |
6646 | }; | |
6c5c0fec AB |
6647 | #ifdef CONFIG_USER_ONLY |
6648 | ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = { | |
6649 | { .name = "MIDR_EL1", | |
6650 | .exported_bits = 0x00000000ffffffff }, | |
6651 | { .name = "REVIDR_EL1" }, | |
6652 | REGUSERINFO_SENTINEL | |
6653 | }; | |
6654 | modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo); | |
6655 | #endif | |
7884849c PM |
6656 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || |
6657 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | |
6658 | ARMCPRegInfo *r; | |
6659 | /* Register the blanket "writes ignored" value first to cover the | |
a703eda1 PC |
6660 | * whole space. Then update the specific ID registers to allow write |
6661 | * access, so that they ignore writes rather than causing them to | |
6662 | * UNDEF. | |
7884849c PM |
6663 | */ |
6664 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | |
00a29f3d PM |
6665 | for (r = id_pre_v8_midr_cp_reginfo; |
6666 | r->type != ARM_CP_SENTINEL; r++) { | |
6667 | r->access = PL1_RW; | |
6668 | } | |
7884849c PM |
6669 | for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { |
6670 | r->access = PL1_RW; | |
7884849c | 6671 | } |
10006112 | 6672 | id_mpuir_reginfo.access = PL1_RW; |
3281af81 | 6673 | id_tlbtr_reginfo.access = PL1_RW; |
7884849c | 6674 | } |
00a29f3d PM |
6675 | if (arm_feature(env, ARM_FEATURE_V8)) { |
6676 | define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); | |
6677 | } else { | |
6678 | define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); | |
6679 | } | |
a703eda1 | 6680 | define_arm_cp_regs(cpu, id_cp_reginfo); |
452a0955 | 6681 | if (!arm_feature(env, ARM_FEATURE_PMSA)) { |
8085ce63 | 6682 | define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); |
3281af81 PC |
6683 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
6684 | define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); | |
8085ce63 | 6685 | } |
7884849c PM |
6686 | } |
6687 | ||
97ce8d61 | 6688 | if (arm_feature(env, ARM_FEATURE_MPIDR)) { |
52264166 AB |
6689 | ARMCPRegInfo mpidr_cp_reginfo[] = { |
6690 | { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
6691 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | |
6692 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, | |
6693 | REGINFO_SENTINEL | |
6694 | }; | |
6695 | #ifdef CONFIG_USER_ONLY | |
6696 | ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = { | |
6697 | { .name = "MPIDR_EL1", | |
6698 | .fixed_bits = 0x0000000080000000 }, | |
6699 | REGUSERINFO_SENTINEL | |
6700 | }; | |
6701 | modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); | |
6702 | #endif | |
97ce8d61 PC |
6703 | define_arm_cp_regs(cpu, mpidr_cp_reginfo); |
6704 | } | |
6705 | ||
2771db27 | 6706 | if (arm_feature(env, ARM_FEATURE_AUXCR)) { |
834a6c69 PM |
6707 | ARMCPRegInfo auxcr_reginfo[] = { |
6708 | { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, | |
6709 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, | |
6710 | .access = PL1_RW, .type = ARM_CP_CONST, | |
6711 | .resetvalue = cpu->reset_auxcr }, | |
6712 | { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, | |
6713 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, | |
6714 | .access = PL2_RW, .type = ARM_CP_CONST, | |
6715 | .resetvalue = 0 }, | |
6716 | { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, | |
6717 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, | |
6718 | .access = PL3_RW, .type = ARM_CP_CONST, | |
6719 | .resetvalue = 0 }, | |
6720 | REGINFO_SENTINEL | |
2771db27 | 6721 | }; |
834a6c69 | 6722 | define_arm_cp_regs(cpu, auxcr_reginfo); |
0e0456ab PM |
6723 | if (arm_feature(env, ARM_FEATURE_V8)) { |
6724 | /* HACTLR2 maps to ACTLR_EL2[63:32] and is not in ARMv7 */ | |
6725 | ARMCPRegInfo hactlr2_reginfo = { | |
6726 | .name = "HACTLR2", .state = ARM_CP_STATE_AA32, | |
6727 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3, | |
6728 | .access = PL2_RW, .type = ARM_CP_CONST, | |
6729 | .resetvalue = 0 | |
6730 | }; | |
6731 | define_one_arm_cp_reg(cpu, &hactlr2_reginfo); | |
6732 | } | |
2771db27 PM |
6733 | } |
6734 | ||
d8ba780b | 6735 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
d56974af LM |
6736 | /* |
6737 | * CBAR is IMPDEF, but common on Arm Cortex-A implementations. | |
6738 | * There are two flavours: | |
6739 | * (1) older 32-bit only cores have a simple 32-bit CBAR | |
6740 | * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a | |
6741 | * 32-bit register visible to AArch32 at a different encoding | |
6742 | * to the "flavour 1" register and with the bits rearranged to | |
6743 | * be able to squash a 64-bit address into the 32-bit view. | |
6744 | * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but | |
6745 | * in future if we support AArch32-only configs of some of the | |
6746 | * AArch64 cores we might need to add a specific feature flag | |
6747 | * to indicate cores with "flavour 2" CBAR. | |
6748 | */ | |
f318cec6 PM |
6749 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
6750 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | |
6751 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | |
6752 | | extract64(cpu->reset_cbar, 32, 12); | |
6753 | ARMCPRegInfo cbar_reginfo[] = { | |
6754 | { .name = "CBAR", | |
6755 | .type = ARM_CP_CONST, | |
d56974af LM |
6756 | .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0, |
6757 | .access = PL1_R, .resetvalue = cbar32 }, | |
f318cec6 PM |
6758 | { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, |
6759 | .type = ARM_CP_CONST, | |
6760 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | |
d56974af | 6761 | .access = PL1_R, .resetvalue = cpu->reset_cbar }, |
f318cec6 PM |
6762 | REGINFO_SENTINEL |
6763 | }; | |
6764 | /* We don't implement a r/w 64 bit CBAR currently */ | |
6765 | assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); | |
6766 | define_arm_cp_regs(cpu, cbar_reginfo); | |
6767 | } else { | |
6768 | ARMCPRegInfo cbar = { | |
6769 | .name = "CBAR", | |
6770 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
6771 | .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar, | |
6772 | .fieldoffset = offsetof(CPUARMState, | |
6773 | cp15.c15_config_base_address) | |
6774 | }; | |
6775 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | |
6776 | cbar.access = PL1_R; | |
6777 | cbar.fieldoffset = 0; | |
6778 | cbar.type = ARM_CP_CONST; | |
6779 | } | |
6780 | define_one_arm_cp_reg(cpu, &cbar); | |
6781 | } | |
d8ba780b PC |
6782 | } |
6783 | ||
91db4642 CLG |
6784 | if (arm_feature(env, ARM_FEATURE_VBAR)) { |
6785 | ARMCPRegInfo vbar_cp_reginfo[] = { | |
6786 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, | |
6787 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | |
6788 | .access = PL1_RW, .writefn = vbar_write, | |
6789 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), | |
6790 | offsetof(CPUARMState, cp15.vbar_ns) }, | |
6791 | .resetvalue = 0 }, | |
6792 | REGINFO_SENTINEL | |
6793 | }; | |
6794 | define_arm_cp_regs(cpu, vbar_cp_reginfo); | |
6795 | } | |
6796 | ||
2771db27 PM |
6797 | /* Generic registers whose values depend on the implementation */ |
6798 | { | |
6799 | ARMCPRegInfo sctlr = { | |
5ebafdf3 | 6800 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, |
137feaa9 FA |
6801 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, |
6802 | .access = PL1_RW, | |
6803 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), | |
6804 | offsetof(CPUARMState, cp15.sctlr_ns) }, | |
d4e6df63 PM |
6805 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, |
6806 | .raw_writefn = raw_write, | |
2771db27 PM |
6807 | }; |
6808 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
6809 | /* Normally we would always end the TB on an SCTLR write, but Linux | |
6810 | * arch/arm/mach-pxa/sleep.S expects two instructions following | |
6811 | * an MMU enable to execute from cache. Imitate this behaviour. | |
6812 | */ | |
6813 | sctlr.type |= ARM_CP_SUPPRESS_TB_END; | |
6814 | } | |
6815 | define_one_arm_cp_reg(cpu, &sctlr); | |
6816 | } | |
5be5e8ed | 6817 | |
2d7137c1 RH |
6818 | if (cpu_isar_feature(aa64_lor, cpu)) { |
6819 | /* | |
6820 | * A trivial implementation of ARMv8.1-LOR leaves all of these | |
6821 | * registers fixed at 0, which indicates that there are zero | |
6822 | * supported Limited Ordering regions. | |
6823 | */ | |
6824 | static const ARMCPRegInfo lor_reginfo[] = { | |
6825 | { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, | |
6826 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, | |
6827 | .access = PL1_RW, .accessfn = access_lor_other, | |
6828 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6829 | { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, | |
6830 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, | |
6831 | .access = PL1_RW, .accessfn = access_lor_other, | |
6832 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6833 | { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, | |
6834 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, | |
6835 | .access = PL1_RW, .accessfn = access_lor_other, | |
6836 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6837 | { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, | |
6838 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, | |
6839 | .access = PL1_RW, .accessfn = access_lor_other, | |
6840 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6841 | { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, | |
6842 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, | |
6843 | .access = PL1_R, .accessfn = access_lorid, | |
6844 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
6845 | REGINFO_SENTINEL | |
6846 | }; | |
6847 | define_arm_cp_regs(cpu, lor_reginfo); | |
6848 | } | |
6849 | ||
cd208a1c | 6850 | if (cpu_isar_feature(aa64_sve, cpu)) { |
5be5e8ed RH |
6851 | define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); |
6852 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
6853 | define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); | |
6854 | } else { | |
6855 | define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo); | |
6856 | } | |
6857 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
6858 | define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); | |
6859 | } | |
6860 | } | |
967aa94f RH |
6861 | |
6862 | #ifdef TARGET_AARCH64 | |
6863 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
6864 | define_arm_cp_regs(cpu, pauth_reginfo); | |
6865 | } | |
de390645 RH |
6866 | if (cpu_isar_feature(aa64_rndr, cpu)) { |
6867 | define_arm_cp_regs(cpu, rndr_reginfo); | |
6868 | } | |
967aa94f | 6869 | #endif |
cb570bd3 RH |
6870 | |
6871 | /* | |
6872 | * While all v8.0 cpus support aarch64, QEMU does have configurations | |
6873 | * that do not set ID_AA64ISAR1, e.g. user-only qemu-arm -cpu max, | |
6874 | * which will set ID_ISAR6. | |
6875 | */ | |
6876 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) | |
6877 | ? cpu_isar_feature(aa64_predinv, cpu) | |
6878 | : cpu_isar_feature(aa32_predinv, cpu)) { | |
6879 | define_arm_cp_regs(cpu, predinv_reginfo); | |
6880 | } | |
2ceb98c0 PM |
6881 | } |
6882 | ||
14969266 AF |
6883 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) |
6884 | { | |
22169d41 | 6885 | CPUState *cs = CPU(cpu); |
14969266 AF |
6886 | CPUARMState *env = &cpu->env; |
6887 | ||
6a669427 PM |
6888 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
6889 | gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, | |
6890 | aarch64_fpu_gdb_set_reg, | |
6891 | 34, "aarch64-fpu.xml", 0); | |
6892 | } else if (arm_feature(env, ARM_FEATURE_NEON)) { | |
22169d41 | 6893 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
6894 | 51, "arm-neon.xml", 0); |
6895 | } else if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
22169d41 | 6896 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
6897 | 35, "arm-vfp3.xml", 0); |
6898 | } else if (arm_feature(env, ARM_FEATURE_VFP)) { | |
22169d41 | 6899 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
56aebc89 PB |
6900 | 19, "arm-vfp.xml", 0); |
6901 | } | |
200bf5b7 AB |
6902 | gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, |
6903 | arm_gen_dynamic_xml(cs), | |
6904 | "system-registers.xml", 0); | |
40f137e1 PB |
6905 | } |
6906 | ||
777dc784 PM |
6907 | /* Sort alphabetically by type name, except for "any". */ |
6908 | static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) | |
5adb4839 | 6909 | { |
777dc784 PM |
6910 | ObjectClass *class_a = (ObjectClass *)a; |
6911 | ObjectClass *class_b = (ObjectClass *)b; | |
6912 | const char *name_a, *name_b; | |
5adb4839 | 6913 | |
777dc784 PM |
6914 | name_a = object_class_get_name(class_a); |
6915 | name_b = object_class_get_name(class_b); | |
51492fd1 | 6916 | if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 | 6917 | return 1; |
51492fd1 | 6918 | } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) { |
777dc784 PM |
6919 | return -1; |
6920 | } else { | |
6921 | return strcmp(name_a, name_b); | |
5adb4839 PB |
6922 | } |
6923 | } | |
6924 | ||
777dc784 | 6925 | static void arm_cpu_list_entry(gpointer data, gpointer user_data) |
40f137e1 | 6926 | { |
777dc784 | 6927 | ObjectClass *oc = data; |
51492fd1 AF |
6928 | const char *typename; |
6929 | char *name; | |
3371d272 | 6930 | |
51492fd1 AF |
6931 | typename = object_class_get_name(oc); |
6932 | name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
0442428a | 6933 | qemu_printf(" %s\n", name); |
51492fd1 | 6934 | g_free(name); |
777dc784 PM |
6935 | } |
6936 | ||
0442428a | 6937 | void arm_cpu_list(void) |
777dc784 | 6938 | { |
777dc784 PM |
6939 | GSList *list; |
6940 | ||
6941 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
6942 | list = g_slist_sort(list, arm_cpu_list_compare); | |
0442428a MA |
6943 | qemu_printf("Available CPUs:\n"); |
6944 | g_slist_foreach(list, arm_cpu_list_entry, NULL); | |
777dc784 | 6945 | g_slist_free(list); |
40f137e1 PB |
6946 | } |
6947 | ||
78027bb6 CR |
6948 | static void arm_cpu_add_definition(gpointer data, gpointer user_data) |
6949 | { | |
6950 | ObjectClass *oc = data; | |
6951 | CpuDefinitionInfoList **cpu_list = user_data; | |
6952 | CpuDefinitionInfoList *entry; | |
6953 | CpuDefinitionInfo *info; | |
6954 | const char *typename; | |
6955 | ||
6956 | typename = object_class_get_name(oc); | |
6957 | info = g_malloc0(sizeof(*info)); | |
6958 | info->name = g_strndup(typename, | |
6959 | strlen(typename) - strlen("-" TYPE_ARM_CPU)); | |
8ed877b7 | 6960 | info->q_typename = g_strdup(typename); |
78027bb6 CR |
6961 | |
6962 | entry = g_malloc0(sizeof(*entry)); | |
6963 | entry->value = info; | |
6964 | entry->next = *cpu_list; | |
6965 | *cpu_list = entry; | |
6966 | } | |
6967 | ||
25a9d6ca | 6968 | CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) |
78027bb6 CR |
6969 | { |
6970 | CpuDefinitionInfoList *cpu_list = NULL; | |
6971 | GSList *list; | |
6972 | ||
6973 | list = object_class_get_list(TYPE_ARM_CPU, false); | |
6974 | g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); | |
6975 | g_slist_free(list); | |
6976 | ||
6977 | return cpu_list; | |
6978 | } | |
6979 | ||
6e6efd61 | 6980 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
51a79b03 | 6981 | void *opaque, int state, int secstate, |
9c513e78 AB |
6982 | int crm, int opc1, int opc2, |
6983 | const char *name) | |
6e6efd61 PM |
6984 | { |
6985 | /* Private utility function for define_one_arm_cp_reg_with_opaque(): | |
6986 | * add a single reginfo struct to the hash table. | |
6987 | */ | |
6988 | uint32_t *key = g_new(uint32_t, 1); | |
6989 | ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); | |
6990 | int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; | |
3f3c82a5 FA |
6991 | int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; |
6992 | ||
9c513e78 | 6993 | r2->name = g_strdup(name); |
3f3c82a5 FA |
6994 | /* Reset the secure state to the specific incoming state. This is |
6995 | * necessary as the register may have been defined with both states. | |
6996 | */ | |
6997 | r2->secure = secstate; | |
6998 | ||
6999 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
7000 | /* Register is banked (using both entries in array). | |
7001 | * Overwriting fieldoffset as the array is only used to define | |
7002 | * banked registers but later only fieldoffset is used. | |
f5a0a5a5 | 7003 | */ |
3f3c82a5 FA |
7004 | r2->fieldoffset = r->bank_fieldoffsets[ns]; |
7005 | } | |
7006 | ||
7007 | if (state == ARM_CP_STATE_AA32) { | |
7008 | if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { | |
7009 | /* If the register is banked then we don't need to migrate or | |
7010 | * reset the 32-bit instance in certain cases: | |
7011 | * | |
7012 | * 1) If the register has both 32-bit and 64-bit instances then we | |
7013 | * can count on the 64-bit instance taking care of the | |
7014 | * non-secure bank. | |
7015 | * 2) If ARMv8 is enabled then we can count on a 64-bit version | |
7016 | * taking care of the secure bank. This requires that separate | |
7017 | * 32 and 64-bit definitions are provided. | |
7018 | */ | |
7019 | if ((r->state == ARM_CP_STATE_BOTH && ns) || | |
7020 | (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { | |
7a0e58fa | 7021 | r2->type |= ARM_CP_ALIAS; |
3f3c82a5 FA |
7022 | } |
7023 | } else if ((secstate != r->secure) && !ns) { | |
7024 | /* The register is not banked so we only want to allow migration of | |
7025 | * the non-secure instance. | |
7026 | */ | |
7a0e58fa | 7027 | r2->type |= ARM_CP_ALIAS; |
58a1d8ce | 7028 | } |
3f3c82a5 FA |
7029 | |
7030 | if (r->state == ARM_CP_STATE_BOTH) { | |
7031 | /* We assume it is a cp15 register if the .cp field is left unset. | |
7032 | */ | |
7033 | if (r2->cp == 0) { | |
7034 | r2->cp = 15; | |
7035 | } | |
7036 | ||
f5a0a5a5 | 7037 | #ifdef HOST_WORDS_BIGENDIAN |
3f3c82a5 FA |
7038 | if (r2->fieldoffset) { |
7039 | r2->fieldoffset += sizeof(uint32_t); | |
7040 | } | |
f5a0a5a5 | 7041 | #endif |
3f3c82a5 | 7042 | } |
f5a0a5a5 PM |
7043 | } |
7044 | if (state == ARM_CP_STATE_AA64) { | |
7045 | /* To allow abbreviation of ARMCPRegInfo | |
7046 | * definitions, we treat cp == 0 as equivalent to | |
7047 | * the value for "standard guest-visible sysreg". | |
58a1d8ce PM |
7048 | * STATE_BOTH definitions are also always "standard |
7049 | * sysreg" in their AArch64 view (the .cp value may | |
7050 | * be non-zero for the benefit of the AArch32 view). | |
f5a0a5a5 | 7051 | */ |
58a1d8ce | 7052 | if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) { |
f5a0a5a5 PM |
7053 | r2->cp = CP_REG_ARM64_SYSREG_CP; |
7054 | } | |
7055 | *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, | |
7056 | r2->opc0, opc1, opc2); | |
7057 | } else { | |
51a79b03 | 7058 | *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); |
f5a0a5a5 | 7059 | } |
6e6efd61 PM |
7060 | if (opaque) { |
7061 | r2->opaque = opaque; | |
7062 | } | |
67ed771d PM |
7063 | /* reginfo passed to helpers is correct for the actual access, |
7064 | * and is never ARM_CP_STATE_BOTH: | |
7065 | */ | |
7066 | r2->state = state; | |
6e6efd61 PM |
7067 | /* Make sure reginfo passed to helpers for wildcarded regs |
7068 | * has the correct crm/opc1/opc2 for this reg, not CP_ANY: | |
7069 | */ | |
7070 | r2->crm = crm; | |
7071 | r2->opc1 = opc1; | |
7072 | r2->opc2 = opc2; | |
7073 | /* By convention, for wildcarded registers only the first | |
7074 | * entry is used for migration; the others are marked as | |
7a0e58fa | 7075 | * ALIAS so we don't try to transfer the register |
6e6efd61 | 7076 | * multiple times. Special registers (ie NOP/WFI) are |
7a0e58fa | 7077 | * never migratable and not even raw-accessible. |
6e6efd61 | 7078 | */ |
7a0e58fa PM |
7079 | if ((r->type & ARM_CP_SPECIAL)) { |
7080 | r2->type |= ARM_CP_NO_RAW; | |
7081 | } | |
7082 | if (((r->crm == CP_ANY) && crm != 0) || | |
6e6efd61 PM |
7083 | ((r->opc1 == CP_ANY) && opc1 != 0) || |
7084 | ((r->opc2 == CP_ANY) && opc2 != 0)) { | |
1f163787 | 7085 | r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB; |
6e6efd61 PM |
7086 | } |
7087 | ||
375421cc PM |
7088 | /* Check that raw accesses are either forbidden or handled. Note that |
7089 | * we can't assert this earlier because the setup of fieldoffset for | |
7090 | * banked registers has to be done first. | |
7091 | */ | |
7092 | if (!(r2->type & ARM_CP_NO_RAW)) { | |
7093 | assert(!raw_accessors_invalid(r2)); | |
7094 | } | |
7095 | ||
6e6efd61 PM |
7096 | /* Overriding of an existing definition must be explicitly |
7097 | * requested. | |
7098 | */ | |
7099 | if (!(r->type & ARM_CP_OVERRIDE)) { | |
7100 | ARMCPRegInfo *oldreg; | |
7101 | oldreg = g_hash_table_lookup(cpu->cp_regs, key); | |
7102 | if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { | |
7103 | fprintf(stderr, "Register redefined: cp=%d %d bit " | |
7104 | "crn=%d crm=%d opc1=%d opc2=%d, " | |
7105 | "was %s, now %s\n", r2->cp, 32 + 32 * is64, | |
7106 | r2->crn, r2->crm, r2->opc1, r2->opc2, | |
7107 | oldreg->name, r2->name); | |
7108 | g_assert_not_reached(); | |
7109 | } | |
7110 | } | |
7111 | g_hash_table_insert(cpu->cp_regs, key, r2); | |
7112 | } | |
7113 | ||
7114 | ||
4b6a83fb PM |
7115 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
7116 | const ARMCPRegInfo *r, void *opaque) | |
7117 | { | |
7118 | /* Define implementations of coprocessor registers. | |
7119 | * We store these in a hashtable because typically | |
7120 | * there are less than 150 registers in a space which | |
7121 | * is 16*16*16*8*8 = 262144 in size. | |
7122 | * Wildcarding is supported for the crm, opc1 and opc2 fields. | |
7123 | * If a register is defined twice then the second definition is | |
7124 | * used, so this can be used to define some generic registers and | |
7125 | * then override them with implementation specific variations. | |
7126 | * At least one of the original and the second definition should | |
7127 | * include ARM_CP_OVERRIDE in its type bits -- this is just a guard | |
7128 | * against accidental use. | |
f5a0a5a5 PM |
7129 | * |
7130 | * The state field defines whether the register is to be | |
7131 | * visible in the AArch32 or AArch64 execution state. If the | |
7132 | * state is set to ARM_CP_STATE_BOTH then we synthesise a | |
7133 | * reginfo structure for the AArch32 view, which sees the lower | |
7134 | * 32 bits of the 64 bit register. | |
7135 | * | |
7136 | * Only registers visible in AArch64 may set r->opc0; opc0 cannot | |
7137 | * be wildcarded. AArch64 registers are always considered to be 64 | |
7138 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | |
7139 | * the register, if any. | |
4b6a83fb | 7140 | */ |
f5a0a5a5 | 7141 | int crm, opc1, opc2, state; |
4b6a83fb PM |
7142 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
7143 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | |
7144 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | |
7145 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | |
7146 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | |
7147 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | |
7148 | /* 64 bit registers have only CRm and Opc1 fields */ | |
7149 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | |
f5a0a5a5 PM |
7150 | /* op0 only exists in the AArch64 encodings */ |
7151 | assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); | |
7152 | /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ | |
7153 | assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); | |
7154 | /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 | |
7155 | * encodes a minimum access level for the register. We roll this | |
7156 | * runtime check into our general permission check code, so check | |
7157 | * here that the reginfo's specified permissions are strict enough | |
7158 | * to encompass the generic architectural permission check. | |
7159 | */ | |
7160 | if (r->state != ARM_CP_STATE_AA32) { | |
7161 | int mask = 0; | |
7162 | switch (r->opc1) { | |
b5bd7440 AB |
7163 | case 0: |
7164 | /* min_EL EL1, but some accessible to EL0 via kernel ABI */ | |
7165 | mask = PL0U_R | PL1_RW; | |
7166 | break; | |
7167 | case 1: case 2: | |
f5a0a5a5 PM |
7168 | /* min_EL EL1 */ |
7169 | mask = PL1_RW; | |
7170 | break; | |
7171 | case 3: | |
7172 | /* min_EL EL0 */ | |
7173 | mask = PL0_RW; | |
7174 | break; | |
7175 | case 4: | |
7176 | /* min_EL EL2 */ | |
7177 | mask = PL2_RW; | |
7178 | break; | |
7179 | case 5: | |
7180 | /* unallocated encoding, so not possible */ | |
7181 | assert(false); | |
7182 | break; | |
7183 | case 6: | |
7184 | /* min_EL EL3 */ | |
7185 | mask = PL3_RW; | |
7186 | break; | |
7187 | case 7: | |
7188 | /* min_EL EL1, secure mode only (we don't check the latter) */ | |
7189 | mask = PL1_RW; | |
7190 | break; | |
7191 | default: | |
7192 | /* broken reginfo with out-of-range opc1 */ | |
7193 | assert(false); | |
7194 | break; | |
7195 | } | |
7196 | /* assert our permissions are not too lax (stricter is fine) */ | |
7197 | assert((r->access & ~mask) == 0); | |
7198 | } | |
7199 | ||
4b6a83fb PM |
7200 | /* Check that the register definition has enough info to handle |
7201 | * reads and writes if they are permitted. | |
7202 | */ | |
7203 | if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { | |
7204 | if (r->access & PL3_R) { | |
3f3c82a5 FA |
7205 | assert((r->fieldoffset || |
7206 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
7207 | r->readfn); | |
4b6a83fb PM |
7208 | } |
7209 | if (r->access & PL3_W) { | |
3f3c82a5 FA |
7210 | assert((r->fieldoffset || |
7211 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
7212 | r->writefn); | |
4b6a83fb PM |
7213 | } |
7214 | } | |
7215 | /* Bad type field probably means missing sentinel at end of reg list */ | |
7216 | assert(cptype_valid(r->type)); | |
7217 | for (crm = crmmin; crm <= crmmax; crm++) { | |
7218 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | |
7219 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | |
f5a0a5a5 PM |
7220 | for (state = ARM_CP_STATE_AA32; |
7221 | state <= ARM_CP_STATE_AA64; state++) { | |
7222 | if (r->state != state && r->state != ARM_CP_STATE_BOTH) { | |
7223 | continue; | |
7224 | } | |
3f3c82a5 FA |
7225 | if (state == ARM_CP_STATE_AA32) { |
7226 | /* Under AArch32 CP registers can be common | |
7227 | * (same for secure and non-secure world) or banked. | |
7228 | */ | |
9c513e78 AB |
7229 | char *name; |
7230 | ||
3f3c82a5 FA |
7231 | switch (r->secure) { |
7232 | case ARM_CP_SECSTATE_S: | |
7233 | case ARM_CP_SECSTATE_NS: | |
7234 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
9c513e78 AB |
7235 | r->secure, crm, opc1, opc2, |
7236 | r->name); | |
3f3c82a5 FA |
7237 | break; |
7238 | default: | |
9c513e78 | 7239 | name = g_strdup_printf("%s_S", r->name); |
3f3c82a5 FA |
7240 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
7241 | ARM_CP_SECSTATE_S, | |
9c513e78 AB |
7242 | crm, opc1, opc2, name); |
7243 | g_free(name); | |
3f3c82a5 FA |
7244 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
7245 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 7246 | crm, opc1, opc2, r->name); |
3f3c82a5 FA |
7247 | break; |
7248 | } | |
7249 | } else { | |
7250 | /* AArch64 registers get mapped to non-secure instance | |
7251 | * of AArch32 */ | |
7252 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
7253 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 7254 | crm, opc1, opc2, r->name); |
3f3c82a5 | 7255 | } |
f5a0a5a5 | 7256 | } |
4b6a83fb PM |
7257 | } |
7258 | } | |
7259 | } | |
7260 | } | |
7261 | ||
7262 | void define_arm_cp_regs_with_opaque(ARMCPU *cpu, | |
7263 | const ARMCPRegInfo *regs, void *opaque) | |
7264 | { | |
7265 | /* Define a whole list of registers */ | |
7266 | const ARMCPRegInfo *r; | |
7267 | for (r = regs; r->type != ARM_CP_SENTINEL; r++) { | |
7268 | define_one_arm_cp_reg_with_opaque(cpu, r, opaque); | |
7269 | } | |
7270 | } | |
7271 | ||
6c5c0fec AB |
7272 | /* |
7273 | * Modify ARMCPRegInfo for access from userspace. | |
7274 | * | |
7275 | * This is a data driven modification directed by | |
7276 | * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as | |
7277 | * user-space cannot alter any values and dynamic values pertaining to | |
7278 | * execution state are hidden from user space view anyway. | |
7279 | */ | |
7280 | void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods) | |
7281 | { | |
7282 | const ARMCPRegUserSpaceInfo *m; | |
7283 | ARMCPRegInfo *r; | |
7284 | ||
7285 | for (m = mods; m->name; m++) { | |
d040242e AB |
7286 | GPatternSpec *pat = NULL; |
7287 | if (m->is_glob) { | |
7288 | pat = g_pattern_spec_new(m->name); | |
7289 | } | |
6c5c0fec | 7290 | for (r = regs; r->type != ARM_CP_SENTINEL; r++) { |
d040242e AB |
7291 | if (pat && g_pattern_match_string(pat, r->name)) { |
7292 | r->type = ARM_CP_CONST; | |
7293 | r->access = PL0U_R; | |
7294 | r->resetvalue = 0; | |
7295 | /* continue */ | |
7296 | } else if (strcmp(r->name, m->name) == 0) { | |
6c5c0fec AB |
7297 | r->type = ARM_CP_CONST; |
7298 | r->access = PL0U_R; | |
7299 | r->resetvalue &= m->exported_bits; | |
7300 | r->resetvalue |= m->fixed_bits; | |
7301 | break; | |
7302 | } | |
7303 | } | |
d040242e AB |
7304 | if (pat) { |
7305 | g_pattern_spec_free(pat); | |
7306 | } | |
6c5c0fec AB |
7307 | } |
7308 | } | |
7309 | ||
60322b39 | 7310 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) |
4b6a83fb | 7311 | { |
60322b39 | 7312 | return g_hash_table_lookup(cpregs, &encoded_cp); |
4b6a83fb PM |
7313 | } |
7314 | ||
c4241c7d PM |
7315 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
7316 | uint64_t value) | |
4b6a83fb PM |
7317 | { |
7318 | /* Helper coprocessor write function for write-ignore registers */ | |
4b6a83fb PM |
7319 | } |
7320 | ||
c4241c7d | 7321 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) |
4b6a83fb PM |
7322 | { |
7323 | /* Helper coprocessor write function for read-as-zero registers */ | |
4b6a83fb PM |
7324 | return 0; |
7325 | } | |
7326 | ||
f5a0a5a5 PM |
7327 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) |
7328 | { | |
7329 | /* Helper coprocessor reset function for do-nothing-on-reset registers */ | |
7330 | } | |
7331 | ||
af393ffc | 7332 | static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) |
37064a8b PM |
7333 | { |
7334 | /* Return true if it is not valid for us to switch to | |
7335 | * this CPU mode (ie all the UNPREDICTABLE cases in | |
7336 | * the ARM ARM CPSRWriteByInstr pseudocode). | |
7337 | */ | |
af393ffc PM |
7338 | |
7339 | /* Changes to or from Hyp via MSR and CPS are illegal. */ | |
7340 | if (write_type == CPSRWriteByInstr && | |
7341 | ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || | |
7342 | mode == ARM_CPU_MODE_HYP)) { | |
7343 | return 1; | |
7344 | } | |
7345 | ||
37064a8b PM |
7346 | switch (mode) { |
7347 | case ARM_CPU_MODE_USR: | |
10eacda7 | 7348 | return 0; |
37064a8b PM |
7349 | case ARM_CPU_MODE_SYS: |
7350 | case ARM_CPU_MODE_SVC: | |
7351 | case ARM_CPU_MODE_ABT: | |
7352 | case ARM_CPU_MODE_UND: | |
7353 | case ARM_CPU_MODE_IRQ: | |
7354 | case ARM_CPU_MODE_FIQ: | |
52ff951b PM |
7355 | /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 |
7356 | * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) | |
7357 | */ | |
10eacda7 PM |
7358 | /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR |
7359 | * and CPS are treated as illegal mode changes. | |
7360 | */ | |
7361 | if (write_type == CPSRWriteByInstr && | |
10eacda7 | 7362 | (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && |
7c208e0f | 7363 | (arm_hcr_el2_eff(env) & HCR_TGE)) { |
10eacda7 PM |
7364 | return 1; |
7365 | } | |
37064a8b | 7366 | return 0; |
e6c8fc07 PM |
7367 | case ARM_CPU_MODE_HYP: |
7368 | return !arm_feature(env, ARM_FEATURE_EL2) | |
2d2a4549 | 7369 | || arm_current_el(env) < 2 || arm_is_secure_below_el3(env); |
027fc527 | 7370 | case ARM_CPU_MODE_MON: |
58ae2d1f | 7371 | return arm_current_el(env) < 3; |
37064a8b PM |
7372 | default: |
7373 | return 1; | |
7374 | } | |
7375 | } | |
7376 | ||
2f4a40e5 AZ |
7377 | uint32_t cpsr_read(CPUARMState *env) |
7378 | { | |
7379 | int ZF; | |
6fbe23d5 PB |
7380 | ZF = (env->ZF == 0); |
7381 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
7382 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
7383 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
7384 | | ((env->condexec_bits & 0xfc) << 8) | |
af519934 | 7385 | | (env->GE << 16) | (env->daif & CPSR_AIF); |
2f4a40e5 AZ |
7386 | } |
7387 | ||
50866ba5 PM |
7388 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, |
7389 | CPSRWriteType write_type) | |
2f4a40e5 | 7390 | { |
6e8801f9 FA |
7391 | uint32_t changed_daif; |
7392 | ||
2f4a40e5 | 7393 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
7394 | env->ZF = (~val) & CPSR_Z; |
7395 | env->NF = val; | |
2f4a40e5 AZ |
7396 | env->CF = (val >> 29) & 1; |
7397 | env->VF = (val << 3) & 0x80000000; | |
7398 | } | |
7399 | if (mask & CPSR_Q) | |
7400 | env->QF = ((val & CPSR_Q) != 0); | |
7401 | if (mask & CPSR_T) | |
7402 | env->thumb = ((val & CPSR_T) != 0); | |
7403 | if (mask & CPSR_IT_0_1) { | |
7404 | env->condexec_bits &= ~3; | |
7405 | env->condexec_bits |= (val >> 25) & 3; | |
7406 | } | |
7407 | if (mask & CPSR_IT_2_7) { | |
7408 | env->condexec_bits &= 3; | |
7409 | env->condexec_bits |= (val >> 8) & 0xfc; | |
7410 | } | |
7411 | if (mask & CPSR_GE) { | |
7412 | env->GE = (val >> 16) & 0xf; | |
7413 | } | |
7414 | ||
6e8801f9 FA |
7415 | /* In a V7 implementation that includes the security extensions but does |
7416 | * not include Virtualization Extensions the SCR.FW and SCR.AW bits control | |
7417 | * whether non-secure software is allowed to change the CPSR_F and CPSR_A | |
7418 | * bits respectively. | |
7419 | * | |
7420 | * In a V8 implementation, it is permitted for privileged software to | |
7421 | * change the CPSR A/F bits regardless of the SCR.AW/FW bits. | |
7422 | */ | |
f8c88bbc | 7423 | if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && |
6e8801f9 FA |
7424 | arm_feature(env, ARM_FEATURE_EL3) && |
7425 | !arm_feature(env, ARM_FEATURE_EL2) && | |
7426 | !arm_is_secure(env)) { | |
7427 | ||
7428 | changed_daif = (env->daif ^ val) & mask; | |
7429 | ||
7430 | if (changed_daif & CPSR_A) { | |
7431 | /* Check to see if we are allowed to change the masking of async | |
7432 | * abort exceptions from a non-secure state. | |
7433 | */ | |
7434 | if (!(env->cp15.scr_el3 & SCR_AW)) { | |
7435 | qemu_log_mask(LOG_GUEST_ERROR, | |
7436 | "Ignoring attempt to switch CPSR_A flag from " | |
7437 | "non-secure world with SCR.AW bit clear\n"); | |
7438 | mask &= ~CPSR_A; | |
7439 | } | |
7440 | } | |
7441 | ||
7442 | if (changed_daif & CPSR_F) { | |
7443 | /* Check to see if we are allowed to change the masking of FIQ | |
7444 | * exceptions from a non-secure state. | |
7445 | */ | |
7446 | if (!(env->cp15.scr_el3 & SCR_FW)) { | |
7447 | qemu_log_mask(LOG_GUEST_ERROR, | |
7448 | "Ignoring attempt to switch CPSR_F flag from " | |
7449 | "non-secure world with SCR.FW bit clear\n"); | |
7450 | mask &= ~CPSR_F; | |
7451 | } | |
7452 | ||
7453 | /* Check whether non-maskable FIQ (NMFI) support is enabled. | |
7454 | * If this bit is set software is not allowed to mask | |
7455 | * FIQs, but is allowed to set CPSR_F to 0. | |
7456 | */ | |
7457 | if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && | |
7458 | (val & CPSR_F)) { | |
7459 | qemu_log_mask(LOG_GUEST_ERROR, | |
7460 | "Ignoring attempt to enable CPSR_F flag " | |
7461 | "(non-maskable FIQ [NMFI] support enabled)\n"); | |
7462 | mask &= ~CPSR_F; | |
7463 | } | |
7464 | } | |
7465 | } | |
7466 | ||
4cc35614 PM |
7467 | env->daif &= ~(CPSR_AIF & mask); |
7468 | env->daif |= val & CPSR_AIF & mask; | |
7469 | ||
f8c88bbc PM |
7470 | if (write_type != CPSRWriteRaw && |
7471 | ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { | |
8c4f0eb9 PM |
7472 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { |
7473 | /* Note that we can only get here in USR mode if this is a | |
7474 | * gdb stub write; for this case we follow the architectural | |
7475 | * behaviour for guest writes in USR mode of ignoring an attempt | |
7476 | * to switch mode. (Those are caught by translate.c for writes | |
7477 | * triggered by guest instructions.) | |
7478 | */ | |
7479 | mask &= ~CPSR_M; | |
7480 | } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { | |
81907a58 PM |
7481 | /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in |
7482 | * v7, and has defined behaviour in v8: | |
7483 | * + leave CPSR.M untouched | |
7484 | * + allow changes to the other CPSR fields | |
7485 | * + set PSTATE.IL | |
7486 | * For user changes via the GDB stub, we don't set PSTATE.IL, | |
7487 | * as this would be unnecessarily harsh for a user error. | |
37064a8b PM |
7488 | */ |
7489 | mask &= ~CPSR_M; | |
81907a58 PM |
7490 | if (write_type != CPSRWriteByGDBStub && |
7491 | arm_feature(env, ARM_FEATURE_V8)) { | |
7492 | mask |= CPSR_IL; | |
7493 | val |= CPSR_IL; | |
7494 | } | |
81e37284 PM |
7495 | qemu_log_mask(LOG_GUEST_ERROR, |
7496 | "Illegal AArch32 mode switch attempt from %s to %s\n", | |
7497 | aarch32_mode_name(env->uncached_cpsr), | |
7498 | aarch32_mode_name(val)); | |
37064a8b | 7499 | } else { |
81e37284 PM |
7500 | qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n", |
7501 | write_type == CPSRWriteExceptionReturn ? | |
7502 | "Exception return from AArch32" : | |
7503 | "AArch32 mode switch from", | |
7504 | aarch32_mode_name(env->uncached_cpsr), | |
7505 | aarch32_mode_name(val), env->regs[15]); | |
37064a8b PM |
7506 | switch_mode(env, val & CPSR_M); |
7507 | } | |
2f4a40e5 AZ |
7508 | } |
7509 | mask &= ~CACHED_CPSR_BITS; | |
7510 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
7511 | } | |
7512 | ||
b26eefb6 PB |
7513 | /* Sign/zero extend */ |
7514 | uint32_t HELPER(sxtb16)(uint32_t x) | |
7515 | { | |
7516 | uint32_t res; | |
7517 | res = (uint16_t)(int8_t)x; | |
7518 | res |= (uint32_t)(int8_t)(x >> 16) << 16; | |
7519 | return res; | |
7520 | } | |
7521 | ||
7522 | uint32_t HELPER(uxtb16)(uint32_t x) | |
7523 | { | |
7524 | uint32_t res; | |
7525 | res = (uint16_t)(uint8_t)x; | |
7526 | res |= (uint32_t)(uint8_t)(x >> 16) << 16; | |
7527 | return res; | |
7528 | } | |
7529 | ||
3670669c PB |
7530 | int32_t HELPER(sdiv)(int32_t num, int32_t den) |
7531 | { | |
7532 | if (den == 0) | |
7533 | return 0; | |
686eeb93 AJ |
7534 | if (num == INT_MIN && den == -1) |
7535 | return INT_MIN; | |
3670669c PB |
7536 | return num / den; |
7537 | } | |
7538 | ||
7539 | uint32_t HELPER(udiv)(uint32_t num, uint32_t den) | |
7540 | { | |
7541 | if (den == 0) | |
7542 | return 0; | |
7543 | return num / den; | |
7544 | } | |
7545 | ||
7546 | uint32_t HELPER(rbit)(uint32_t x) | |
7547 | { | |
42fedbca | 7548 | return revbit32(x); |
3670669c PB |
7549 | } |
7550 | ||
c47eaf9f | 7551 | #ifdef CONFIG_USER_ONLY |
b5ff1b31 | 7552 | |
affdb64d | 7553 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 | 7554 | { |
2fc0cc0e | 7555 | ARMCPU *cpu = env_archcpu(env); |
a47dddd7 AF |
7556 | |
7557 | if (mode != ARM_CPU_MODE_USR) { | |
7558 | cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); | |
7559 | } | |
b5ff1b31 FB |
7560 | } |
7561 | ||
012a906b GB |
7562 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
7563 | uint32_t cur_el, bool secure) | |
9e729b57 EI |
7564 | { |
7565 | return 1; | |
7566 | } | |
7567 | ||
ce02049d GB |
7568 | void aarch64_sync_64_to_32(CPUARMState *env) |
7569 | { | |
7570 | g_assert_not_reached(); | |
7571 | } | |
7572 | ||
b5ff1b31 FB |
7573 | #else |
7574 | ||
affdb64d | 7575 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
7576 | { |
7577 | int old_mode; | |
7578 | int i; | |
7579 | ||
7580 | old_mode = env->uncached_cpsr & CPSR_M; | |
7581 | if (mode == old_mode) | |
7582 | return; | |
7583 | ||
7584 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
7585 | memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 7586 | memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
7587 | } else if (mode == ARM_CPU_MODE_FIQ) { |
7588 | memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
8637c67f | 7589 | memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); |
b5ff1b31 FB |
7590 | } |
7591 | ||
f5206413 | 7592 | i = bank_number(old_mode); |
b5ff1b31 | 7593 | env->banked_r13[i] = env->regs[13]; |
b5ff1b31 FB |
7594 | env->banked_spsr[i] = env->spsr; |
7595 | ||
f5206413 | 7596 | i = bank_number(mode); |
b5ff1b31 | 7597 | env->regs[13] = env->banked_r13[i]; |
b5ff1b31 | 7598 | env->spsr = env->banked_spsr[i]; |
593cfa2b PM |
7599 | |
7600 | env->banked_r14[r14_bank_number(old_mode)] = env->regs[14]; | |
7601 | env->regs[14] = env->banked_r14[r14_bank_number(mode)]; | |
b5ff1b31 FB |
7602 | } |
7603 | ||
0eeb17d6 GB |
7604 | /* Physical Interrupt Target EL Lookup Table |
7605 | * | |
7606 | * [ From ARM ARM section G1.13.4 (Table G1-15) ] | |
7607 | * | |
7608 | * The below multi-dimensional table is used for looking up the target | |
7609 | * exception level given numerous condition criteria. Specifically, the | |
7610 | * target EL is based on SCR and HCR routing controls as well as the | |
7611 | * currently executing EL and secure state. | |
7612 | * | |
7613 | * Dimensions: | |
7614 | * target_el_table[2][2][2][2][2][4] | |
7615 | * | | | | | +--- Current EL | |
7616 | * | | | | +------ Non-secure(0)/Secure(1) | |
7617 | * | | | +--------- HCR mask override | |
7618 | * | | +------------ SCR exec state control | |
7619 | * | +--------------- SCR mask override | |
7620 | * +------------------ 32-bit(0)/64-bit(1) EL3 | |
7621 | * | |
7622 | * The table values are as such: | |
7623 | * 0-3 = EL0-EL3 | |
7624 | * -1 = Cannot occur | |
7625 | * | |
7626 | * The ARM ARM target EL table includes entries indicating that an "exception | |
7627 | * is not taken". The two cases where this is applicable are: | |
7628 | * 1) An exception is taken from EL3 but the SCR does not have the exception | |
7629 | * routed to EL3. | |
7630 | * 2) An exception is taken from EL2 but the HCR does not have the exception | |
7631 | * routed to EL2. | |
7632 | * In these two cases, the below table contain a target of EL1. This value is | |
7633 | * returned as it is expected that the consumer of the table data will check | |
7634 | * for "target EL >= current EL" to ensure the exception is not taken. | |
7635 | * | |
7636 | * SCR HCR | |
7637 | * 64 EA AMO From | |
7638 | * BIT IRQ IMO Non-secure Secure | |
7639 | * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 | |
7640 | */ | |
82c39f6a | 7641 | static const int8_t target_el_table[2][2][2][2][2][4] = { |
0eeb17d6 GB |
7642 | {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, |
7643 | {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, | |
7644 | {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, | |
7645 | {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, | |
7646 | {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
7647 | {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, | |
7648 | {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
7649 | {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, | |
7650 | {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, | |
7651 | {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},}, | |
7652 | {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },}, | |
7653 | {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},}, | |
7654 | {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, | |
7655 | {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, | |
7656 | {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, | |
7657 | {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},}, | |
7658 | }; | |
7659 | ||
7660 | /* | |
7661 | * Determine the target EL for physical exceptions | |
7662 | */ | |
012a906b GB |
7663 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
7664 | uint32_t cur_el, bool secure) | |
0eeb17d6 GB |
7665 | { |
7666 | CPUARMState *env = cs->env_ptr; | |
f7778444 RH |
7667 | bool rw; |
7668 | bool scr; | |
7669 | bool hcr; | |
0eeb17d6 | 7670 | int target_el; |
2cde031f | 7671 | /* Is the highest EL AArch64? */ |
f7778444 RH |
7672 | bool is64 = arm_feature(env, ARM_FEATURE_AARCH64); |
7673 | uint64_t hcr_el2; | |
2cde031f SS |
7674 | |
7675 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
7676 | rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); | |
7677 | } else { | |
7678 | /* Either EL2 is the highest EL (and so the EL2 register width | |
7679 | * is given by is64); or there is no EL2 or EL3, in which case | |
7680 | * the value of 'rw' does not affect the table lookup anyway. | |
7681 | */ | |
7682 | rw = is64; | |
7683 | } | |
0eeb17d6 | 7684 | |
f7778444 | 7685 | hcr_el2 = arm_hcr_el2_eff(env); |
0eeb17d6 GB |
7686 | switch (excp_idx) { |
7687 | case EXCP_IRQ: | |
7688 | scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); | |
f7778444 | 7689 | hcr = hcr_el2 & HCR_IMO; |
0eeb17d6 GB |
7690 | break; |
7691 | case EXCP_FIQ: | |
7692 | scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); | |
f7778444 | 7693 | hcr = hcr_el2 & HCR_FMO; |
0eeb17d6 GB |
7694 | break; |
7695 | default: | |
7696 | scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); | |
f7778444 | 7697 | hcr = hcr_el2 & HCR_AMO; |
0eeb17d6 GB |
7698 | break; |
7699 | }; | |
7700 | ||
0eeb17d6 GB |
7701 | /* Perform a table-lookup for the target EL given the current state */ |
7702 | target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; | |
7703 | ||
7704 | assert(target_el > 0); | |
7705 | ||
7706 | return target_el; | |
7707 | } | |
7708 | ||
b59f479b PMD |
7709 | void arm_log_exception(int idx) |
7710 | { | |
7711 | if (qemu_loglevel_mask(CPU_LOG_INT)) { | |
7712 | const char *exc = NULL; | |
7713 | static const char * const excnames[] = { | |
7714 | [EXCP_UDEF] = "Undefined Instruction", | |
7715 | [EXCP_SWI] = "SVC", | |
7716 | [EXCP_PREFETCH_ABORT] = "Prefetch Abort", | |
7717 | [EXCP_DATA_ABORT] = "Data Abort", | |
7718 | [EXCP_IRQ] = "IRQ", | |
7719 | [EXCP_FIQ] = "FIQ", | |
7720 | [EXCP_BKPT] = "Breakpoint", | |
7721 | [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", | |
7722 | [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", | |
7723 | [EXCP_HVC] = "Hypervisor Call", | |
7724 | [EXCP_HYP_TRAP] = "Hypervisor Trap", | |
7725 | [EXCP_SMC] = "Secure Monitor Call", | |
7726 | [EXCP_VIRQ] = "Virtual IRQ", | |
7727 | [EXCP_VFIQ] = "Virtual FIQ", | |
7728 | [EXCP_SEMIHOST] = "Semihosting call", | |
7729 | [EXCP_NOCP] = "v7M NOCP UsageFault", | |
7730 | [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", | |
7731 | [EXCP_STKOF] = "v8M STKOF UsageFault", | |
7732 | [EXCP_LAZYFP] = "v7M exception during lazy FP stacking", | |
7733 | [EXCP_LSERR] = "v8M LSERR UsageFault", | |
7734 | [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", | |
7735 | }; | |
7736 | ||
7737 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | |
7738 | exc = excnames[idx]; | |
7739 | } | |
7740 | if (!exc) { | |
7741 | exc = "unknown"; | |
7742 | } | |
7743 | qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); | |
7744 | } | |
7745 | } | |
7746 | ||
a356dacf | 7747 | /* |
7aab5a8c PMD |
7748 | * Function used to synchronize QEMU's AArch64 register set with AArch32 |
7749 | * register set. This is necessary when switching between AArch32 and AArch64 | |
7750 | * execution state. | |
a356dacf | 7751 | */ |
7aab5a8c | 7752 | void aarch64_sync_32_to_64(CPUARMState *env) |
9ee6e8bb | 7753 | { |
7aab5a8c PMD |
7754 | int i; |
7755 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
7756 | ||
7757 | /* We can blanket copy R[0:7] to X[0:7] */ | |
7758 | for (i = 0; i < 8; i++) { | |
7759 | env->xregs[i] = env->regs[i]; | |
fd592d89 | 7760 | } |
70d74660 | 7761 | |
9a223097 | 7762 | /* |
7aab5a8c PMD |
7763 | * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. |
7764 | * Otherwise, they come from the banked user regs. | |
fd592d89 | 7765 | */ |
7aab5a8c PMD |
7766 | if (mode == ARM_CPU_MODE_FIQ) { |
7767 | for (i = 8; i < 13; i++) { | |
7768 | env->xregs[i] = env->usr_regs[i - 8]; | |
7769 | } | |
7770 | } else { | |
7771 | for (i = 8; i < 13; i++) { | |
7772 | env->xregs[i] = env->regs[i]; | |
7773 | } | |
fd592d89 | 7774 | } |
9ee6e8bb | 7775 | |
7aab5a8c PMD |
7776 | /* |
7777 | * Registers x13-x23 are the various mode SP and FP registers. Registers | |
7778 | * r13 and r14 are only copied if we are in that mode, otherwise we copy | |
7779 | * from the mode banked register. | |
7780 | */ | |
7781 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { | |
7782 | env->xregs[13] = env->regs[13]; | |
7783 | env->xregs[14] = env->regs[14]; | |
7784 | } else { | |
7785 | env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; | |
7786 | /* HYP is an exception in that it is copied from r14 */ | |
7787 | if (mode == ARM_CPU_MODE_HYP) { | |
7788 | env->xregs[14] = env->regs[14]; | |
95695eff | 7789 | } else { |
7aab5a8c | 7790 | env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)]; |
95695eff | 7791 | } |
95695eff PM |
7792 | } |
7793 | ||
7aab5a8c PMD |
7794 | if (mode == ARM_CPU_MODE_HYP) { |
7795 | env->xregs[15] = env->regs[13]; | |
7796 | } else { | |
7797 | env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; | |
95695eff PM |
7798 | } |
7799 | ||
7aab5a8c PMD |
7800 | if (mode == ARM_CPU_MODE_IRQ) { |
7801 | env->xregs[16] = env->regs[14]; | |
7802 | env->xregs[17] = env->regs[13]; | |
7803 | } else { | |
7804 | env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)]; | |
7805 | env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; | |
7806 | } | |
95695eff | 7807 | |
7aab5a8c PMD |
7808 | if (mode == ARM_CPU_MODE_SVC) { |
7809 | env->xregs[18] = env->regs[14]; | |
7810 | env->xregs[19] = env->regs[13]; | |
7811 | } else { | |
7812 | env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)]; | |
7813 | env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; | |
7814 | } | |
95695eff | 7815 | |
7aab5a8c PMD |
7816 | if (mode == ARM_CPU_MODE_ABT) { |
7817 | env->xregs[20] = env->regs[14]; | |
7818 | env->xregs[21] = env->regs[13]; | |
7819 | } else { | |
7820 | env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)]; | |
7821 | env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; | |
7822 | } | |
e33cf0f8 | 7823 | |
7aab5a8c PMD |
7824 | if (mode == ARM_CPU_MODE_UND) { |
7825 | env->xregs[22] = env->regs[14]; | |
7826 | env->xregs[23] = env->regs[13]; | |
7827 | } else { | |
7828 | env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)]; | |
7829 | env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; | |
e33cf0f8 PM |
7830 | } |
7831 | ||
7832 | /* | |
7aab5a8c PMD |
7833 | * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ |
7834 | * mode, then we can copy from r8-r14. Otherwise, we copy from the | |
7835 | * FIQ bank for r8-r14. | |
e33cf0f8 | 7836 | */ |
7aab5a8c PMD |
7837 | if (mode == ARM_CPU_MODE_FIQ) { |
7838 | for (i = 24; i < 31; i++) { | |
7839 | env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ | |
7840 | } | |
7841 | } else { | |
7842 | for (i = 24; i < 29; i++) { | |
7843 | env->xregs[i] = env->fiq_regs[i - 24]; | |
e33cf0f8 | 7844 | } |
7aab5a8c PMD |
7845 | env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; |
7846 | env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)]; | |
e33cf0f8 | 7847 | } |
7aab5a8c PMD |
7848 | |
7849 | env->pc = env->regs[15]; | |
e33cf0f8 PM |
7850 | } |
7851 | ||
9a223097 | 7852 | /* |
7aab5a8c PMD |
7853 | * Function used to synchronize QEMU's AArch32 register set with AArch64 |
7854 | * register set. This is necessary when switching between AArch32 and AArch64 | |
7855 | * execution state. | |
de2db7ec | 7856 | */ |
7aab5a8c | 7857 | void aarch64_sync_64_to_32(CPUARMState *env) |
9ee6e8bb | 7858 | { |
7aab5a8c PMD |
7859 | int i; |
7860 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
abc24d86 | 7861 | |
7aab5a8c PMD |
7862 | /* We can blanket copy X[0:7] to R[0:7] */ |
7863 | for (i = 0; i < 8; i++) { | |
7864 | env->regs[i] = env->xregs[i]; | |
de2db7ec | 7865 | } |
3f0cddee | 7866 | |
9a223097 | 7867 | /* |
7aab5a8c PMD |
7868 | * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. |
7869 | * Otherwise, we copy x8-x12 into the banked user regs. | |
de2db7ec | 7870 | */ |
7aab5a8c PMD |
7871 | if (mode == ARM_CPU_MODE_FIQ) { |
7872 | for (i = 8; i < 13; i++) { | |
7873 | env->usr_regs[i - 8] = env->xregs[i]; | |
7874 | } | |
7875 | } else { | |
7876 | for (i = 8; i < 13; i++) { | |
7877 | env->regs[i] = env->xregs[i]; | |
7878 | } | |
fb602cb7 PM |
7879 | } |
7880 | ||
9a223097 | 7881 | /* |
7aab5a8c PMD |
7882 | * Registers r13 & r14 depend on the current mode. |
7883 | * If we are in a given mode, we copy the corresponding x registers to r13 | |
7884 | * and r14. Otherwise, we copy the x register to the banked r13 and r14 | |
7885 | * for the mode. | |
fb602cb7 | 7886 | */ |
7aab5a8c PMD |
7887 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { |
7888 | env->regs[13] = env->xregs[13]; | |
7889 | env->regs[14] = env->xregs[14]; | |
fb602cb7 | 7890 | } else { |
7aab5a8c | 7891 | env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; |
fb602cb7 | 7892 | |
7aab5a8c PMD |
7893 | /* |
7894 | * HYP is an exception in that it does not have its own banked r14 but | |
7895 | * shares the USR r14 | |
7896 | */ | |
7897 | if (mode == ARM_CPU_MODE_HYP) { | |
7898 | env->regs[14] = env->xregs[14]; | |
7899 | } else { | |
7900 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; | |
7901 | } | |
7902 | } | |
fb602cb7 | 7903 | |
7aab5a8c PMD |
7904 | if (mode == ARM_CPU_MODE_HYP) { |
7905 | env->regs[13] = env->xregs[15]; | |
fb602cb7 | 7906 | } else { |
7aab5a8c | 7907 | env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; |
fb602cb7 | 7908 | } |
d02a8698 | 7909 | |
7aab5a8c PMD |
7910 | if (mode == ARM_CPU_MODE_IRQ) { |
7911 | env->regs[14] = env->xregs[16]; | |
7912 | env->regs[13] = env->xregs[17]; | |
d02a8698 | 7913 | } else { |
7aab5a8c PMD |
7914 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; |
7915 | env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; | |
d02a8698 PM |
7916 | } |
7917 | ||
7aab5a8c PMD |
7918 | if (mode == ARM_CPU_MODE_SVC) { |
7919 | env->regs[14] = env->xregs[18]; | |
7920 | env->regs[13] = env->xregs[19]; | |
7921 | } else { | |
7922 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; | |
7923 | env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; | |
fb602cb7 PM |
7924 | } |
7925 | ||
7aab5a8c PMD |
7926 | if (mode == ARM_CPU_MODE_ABT) { |
7927 | env->regs[14] = env->xregs[20]; | |
7928 | env->regs[13] = env->xregs[21]; | |
7929 | } else { | |
7930 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; | |
7931 | env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; | |
ce02049d GB |
7932 | } |
7933 | ||
7934 | if (mode == ARM_CPU_MODE_UND) { | |
3a9148d0 SS |
7935 | env->regs[14] = env->xregs[22]; |
7936 | env->regs[13] = env->xregs[23]; | |
ce02049d | 7937 | } else { |
593cfa2b | 7938 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; |
3a9148d0 | 7939 | env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; |
ce02049d GB |
7940 | } |
7941 | ||
7942 | /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ | |
7943 | * mode, then we can copy to r8-r14. Otherwise, we copy to the | |
7944 | * FIQ bank for r8-r14. | |
7945 | */ | |
7946 | if (mode == ARM_CPU_MODE_FIQ) { | |
7947 | for (i = 24; i < 31; i++) { | |
7948 | env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ | |
7949 | } | |
7950 | } else { | |
7951 | for (i = 24; i < 29; i++) { | |
7952 | env->fiq_regs[i - 24] = env->xregs[i]; | |
7953 | } | |
7954 | env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; | |
593cfa2b | 7955 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; |
ce02049d GB |
7956 | } |
7957 | ||
7958 | env->regs[15] = env->pc; | |
7959 | } | |
7960 | ||
dea8378b PM |
7961 | static void take_aarch32_exception(CPUARMState *env, int new_mode, |
7962 | uint32_t mask, uint32_t offset, | |
7963 | uint32_t newpc) | |
7964 | { | |
7965 | /* Change the CPU state so as to actually take the exception. */ | |
7966 | switch_mode(env, new_mode); | |
7967 | /* | |
7968 | * For exceptions taken to AArch32 we must clear the SS bit in both | |
7969 | * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. | |
7970 | */ | |
7971 | env->uncached_cpsr &= ~PSTATE_SS; | |
7972 | env->spsr = cpsr_read(env); | |
7973 | /* Clear IT bits. */ | |
7974 | env->condexec_bits = 0; | |
7975 | /* Switch to the new mode, and to the correct instruction set. */ | |
7976 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; | |
7977 | /* Set new mode endianness */ | |
7978 | env->uncached_cpsr &= ~CPSR_E; | |
7979 | if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { | |
7980 | env->uncached_cpsr |= CPSR_E; | |
7981 | } | |
829f9fd3 PM |
7982 | /* J and IL must always be cleared for exception entry */ |
7983 | env->uncached_cpsr &= ~(CPSR_IL | CPSR_J); | |
dea8378b PM |
7984 | env->daif |= mask; |
7985 | ||
7986 | if (new_mode == ARM_CPU_MODE_HYP) { | |
7987 | env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0; | |
7988 | env->elr_el[2] = env->regs[15]; | |
7989 | } else { | |
7990 | /* | |
7991 | * this is a lie, as there was no c1_sys on V4T/V5, but who cares | |
7992 | * and we should just guard the thumb mode on V4 | |
7993 | */ | |
7994 | if (arm_feature(env, ARM_FEATURE_V4T)) { | |
7995 | env->thumb = | |
7996 | (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; | |
7997 | } | |
7998 | env->regs[14] = env->regs[15] + offset; | |
7999 | } | |
8000 | env->regs[15] = newpc; | |
8001 | } | |
8002 | ||
b9bc21ff PM |
8003 | static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) |
8004 | { | |
8005 | /* | |
8006 | * Handle exception entry to Hyp mode; this is sufficiently | |
8007 | * different to entry to other AArch32 modes that we handle it | |
8008 | * separately here. | |
8009 | * | |
8010 | * The vector table entry used is always the 0x14 Hyp mode entry point, | |
8011 | * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp. | |
8012 | * The offset applied to the preferred return address is always zero | |
8013 | * (see DDI0487C.a section G1.12.3). | |
8014 | * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. | |
8015 | */ | |
8016 | uint32_t addr, mask; | |
8017 | ARMCPU *cpu = ARM_CPU(cs); | |
8018 | CPUARMState *env = &cpu->env; | |
8019 | ||
8020 | switch (cs->exception_index) { | |
8021 | case EXCP_UDEF: | |
8022 | addr = 0x04; | |
8023 | break; | |
8024 | case EXCP_SWI: | |
8025 | addr = 0x14; | |
8026 | break; | |
8027 | case EXCP_BKPT: | |
8028 | /* Fall through to prefetch abort. */ | |
8029 | case EXCP_PREFETCH_ABORT: | |
8030 | env->cp15.ifar_s = env->exception.vaddress; | |
8031 | qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n", | |
8032 | (uint32_t)env->exception.vaddress); | |
8033 | addr = 0x0c; | |
8034 | break; | |
8035 | case EXCP_DATA_ABORT: | |
8036 | env->cp15.dfar_s = env->exception.vaddress; | |
8037 | qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n", | |
8038 | (uint32_t)env->exception.vaddress); | |
8039 | addr = 0x10; | |
8040 | break; | |
8041 | case EXCP_IRQ: | |
8042 | addr = 0x18; | |
8043 | break; | |
8044 | case EXCP_FIQ: | |
8045 | addr = 0x1c; | |
8046 | break; | |
8047 | case EXCP_HVC: | |
8048 | addr = 0x08; | |
8049 | break; | |
8050 | case EXCP_HYP_TRAP: | |
8051 | addr = 0x14; | |
9bbb4ef9 | 8052 | break; |
b9bc21ff PM |
8053 | default: |
8054 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
8055 | } | |
8056 | ||
8057 | if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) { | |
2ed08180 PM |
8058 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
8059 | /* | |
8060 | * QEMU syndrome values are v8-style. v7 has the IL bit | |
8061 | * UNK/SBZP for "field not valid" cases, where v8 uses RES1. | |
8062 | * If this is a v7 CPU, squash the IL bit in those cases. | |
8063 | */ | |
8064 | if (cs->exception_index == EXCP_PREFETCH_ABORT || | |
8065 | (cs->exception_index == EXCP_DATA_ABORT && | |
8066 | !(env->exception.syndrome & ARM_EL_ISV)) || | |
8067 | syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) { | |
8068 | env->exception.syndrome &= ~ARM_EL_IL; | |
8069 | } | |
8070 | } | |
b9bc21ff PM |
8071 | env->cp15.esr_el[2] = env->exception.syndrome; |
8072 | } | |
8073 | ||
8074 | if (arm_current_el(env) != 2 && addr < 0x14) { | |
8075 | addr = 0x14; | |
8076 | } | |
8077 | ||
8078 | mask = 0; | |
8079 | if (!(env->cp15.scr_el3 & SCR_EA)) { | |
8080 | mask |= CPSR_A; | |
8081 | } | |
8082 | if (!(env->cp15.scr_el3 & SCR_IRQ)) { | |
8083 | mask |= CPSR_I; | |
8084 | } | |
8085 | if (!(env->cp15.scr_el3 & SCR_FIQ)) { | |
8086 | mask |= CPSR_F; | |
8087 | } | |
8088 | ||
8089 | addr += env->cp15.hvbar; | |
8090 | ||
8091 | take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr); | |
8092 | } | |
8093 | ||
966f758c | 8094 | static void arm_cpu_do_interrupt_aarch32(CPUState *cs) |
b5ff1b31 | 8095 | { |
97a8ea5a AF |
8096 | ARMCPU *cpu = ARM_CPU(cs); |
8097 | CPUARMState *env = &cpu->env; | |
b5ff1b31 FB |
8098 | uint32_t addr; |
8099 | uint32_t mask; | |
8100 | int new_mode; | |
8101 | uint32_t offset; | |
16a906fd | 8102 | uint32_t moe; |
b5ff1b31 | 8103 | |
16a906fd | 8104 | /* If this is a debug exception we must update the DBGDSCR.MOE bits */ |
64b91e3f | 8105 | switch (syn_get_ec(env->exception.syndrome)) { |
16a906fd PM |
8106 | case EC_BREAKPOINT: |
8107 | case EC_BREAKPOINT_SAME_EL: | |
8108 | moe = 1; | |
8109 | break; | |
8110 | case EC_WATCHPOINT: | |
8111 | case EC_WATCHPOINT_SAME_EL: | |
8112 | moe = 10; | |
8113 | break; | |
8114 | case EC_AA32_BKPT: | |
8115 | moe = 3; | |
8116 | break; | |
8117 | case EC_VECTORCATCH: | |
8118 | moe = 5; | |
8119 | break; | |
8120 | default: | |
8121 | moe = 0; | |
8122 | break; | |
8123 | } | |
8124 | ||
8125 | if (moe) { | |
8126 | env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); | |
8127 | } | |
8128 | ||
b9bc21ff PM |
8129 | if (env->exception.target_el == 2) { |
8130 | arm_cpu_do_interrupt_aarch32_hyp(cs); | |
8131 | return; | |
8132 | } | |
8133 | ||
27103424 | 8134 | switch (cs->exception_index) { |
b5ff1b31 FB |
8135 | case EXCP_UDEF: |
8136 | new_mode = ARM_CPU_MODE_UND; | |
8137 | addr = 0x04; | |
8138 | mask = CPSR_I; | |
8139 | if (env->thumb) | |
8140 | offset = 2; | |
8141 | else | |
8142 | offset = 4; | |
8143 | break; | |
8144 | case EXCP_SWI: | |
8145 | new_mode = ARM_CPU_MODE_SVC; | |
8146 | addr = 0x08; | |
8147 | mask = CPSR_I; | |
601d70b9 | 8148 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
8149 | offset = 0; |
8150 | break; | |
06c949e6 | 8151 | case EXCP_BKPT: |
9ee6e8bb PB |
8152 | /* Fall through to prefetch abort. */ |
8153 | case EXCP_PREFETCH_ABORT: | |
88ca1c2d | 8154 | A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); |
b848ce2b | 8155 | A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); |
3f1beaca | 8156 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", |
88ca1c2d | 8157 | env->exception.fsr, (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
8158 | new_mode = ARM_CPU_MODE_ABT; |
8159 | addr = 0x0c; | |
8160 | mask = CPSR_A | CPSR_I; | |
8161 | offset = 4; | |
8162 | break; | |
8163 | case EXCP_DATA_ABORT: | |
4a7e2d73 | 8164 | A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); |
b848ce2b | 8165 | A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); |
3f1beaca | 8166 | qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", |
4a7e2d73 | 8167 | env->exception.fsr, |
6cd8a264 | 8168 | (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
8169 | new_mode = ARM_CPU_MODE_ABT; |
8170 | addr = 0x10; | |
8171 | mask = CPSR_A | CPSR_I; | |
8172 | offset = 8; | |
8173 | break; | |
8174 | case EXCP_IRQ: | |
8175 | new_mode = ARM_CPU_MODE_IRQ; | |
8176 | addr = 0x18; | |
8177 | /* Disable IRQ and imprecise data aborts. */ | |
8178 | mask = CPSR_A | CPSR_I; | |
8179 | offset = 4; | |
de38d23b FA |
8180 | if (env->cp15.scr_el3 & SCR_IRQ) { |
8181 | /* IRQ routed to monitor mode */ | |
8182 | new_mode = ARM_CPU_MODE_MON; | |
8183 | mask |= CPSR_F; | |
8184 | } | |
b5ff1b31 FB |
8185 | break; |
8186 | case EXCP_FIQ: | |
8187 | new_mode = ARM_CPU_MODE_FIQ; | |
8188 | addr = 0x1c; | |
8189 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
8190 | mask = CPSR_A | CPSR_I | CPSR_F; | |
de38d23b FA |
8191 | if (env->cp15.scr_el3 & SCR_FIQ) { |
8192 | /* FIQ routed to monitor mode */ | |
8193 | new_mode = ARM_CPU_MODE_MON; | |
8194 | } | |
b5ff1b31 FB |
8195 | offset = 4; |
8196 | break; | |
87a4b270 PM |
8197 | case EXCP_VIRQ: |
8198 | new_mode = ARM_CPU_MODE_IRQ; | |
8199 | addr = 0x18; | |
8200 | /* Disable IRQ and imprecise data aborts. */ | |
8201 | mask = CPSR_A | CPSR_I; | |
8202 | offset = 4; | |
8203 | break; | |
8204 | case EXCP_VFIQ: | |
8205 | new_mode = ARM_CPU_MODE_FIQ; | |
8206 | addr = 0x1c; | |
8207 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
8208 | mask = CPSR_A | CPSR_I | CPSR_F; | |
8209 | offset = 4; | |
8210 | break; | |
dbe9d163 FA |
8211 | case EXCP_SMC: |
8212 | new_mode = ARM_CPU_MODE_MON; | |
8213 | addr = 0x08; | |
8214 | mask = CPSR_A | CPSR_I | CPSR_F; | |
8215 | offset = 0; | |
8216 | break; | |
b5ff1b31 | 8217 | default: |
a47dddd7 | 8218 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
b5ff1b31 FB |
8219 | return; /* Never happens. Keep compiler happy. */ |
8220 | } | |
e89e51a1 FA |
8221 | |
8222 | if (new_mode == ARM_CPU_MODE_MON) { | |
8223 | addr += env->cp15.mvbar; | |
137feaa9 | 8224 | } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { |
e89e51a1 | 8225 | /* High vectors. When enabled, base address cannot be remapped. */ |
b5ff1b31 | 8226 | addr += 0xffff0000; |
8641136c NR |
8227 | } else { |
8228 | /* ARM v7 architectures provide a vector base address register to remap | |
8229 | * the interrupt vector table. | |
e89e51a1 | 8230 | * This register is only followed in non-monitor mode, and is banked. |
8641136c NR |
8231 | * Note: only bits 31:5 are valid. |
8232 | */ | |
fb6c91ba | 8233 | addr += A32_BANKED_CURRENT_REG_GET(env, vbar); |
b5ff1b31 | 8234 | } |
dbe9d163 FA |
8235 | |
8236 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
8237 | env->cp15.scr_el3 &= ~SCR_NS; | |
8238 | } | |
8239 | ||
dea8378b | 8240 | take_aarch32_exception(env, new_mode, mask, offset, addr); |
b5ff1b31 FB |
8241 | } |
8242 | ||
966f758c PM |
8243 | /* Handle exception entry to a target EL which is using AArch64 */ |
8244 | static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | |
f3a9b694 PM |
8245 | { |
8246 | ARMCPU *cpu = ARM_CPU(cs); | |
8247 | CPUARMState *env = &cpu->env; | |
8248 | unsigned int new_el = env->exception.target_el; | |
8249 | target_ulong addr = env->cp15.vbar_el[new_el]; | |
8250 | unsigned int new_mode = aarch64_pstate_mode(new_el, true); | |
0ab5953b RH |
8251 | unsigned int cur_el = arm_current_el(env); |
8252 | ||
9a05f7b6 RH |
8253 | /* |
8254 | * Note that new_el can never be 0. If cur_el is 0, then | |
8255 | * el0_a64 is is_a64(), else el0_a64 is ignored. | |
8256 | */ | |
8257 | aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); | |
f3a9b694 | 8258 | |
0ab5953b | 8259 | if (cur_el < new_el) { |
3d6f7617 PM |
8260 | /* Entry vector offset depends on whether the implemented EL |
8261 | * immediately lower than the target level is using AArch32 or AArch64 | |
8262 | */ | |
8263 | bool is_aa64; | |
8264 | ||
8265 | switch (new_el) { | |
8266 | case 3: | |
8267 | is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; | |
8268 | break; | |
8269 | case 2: | |
8270 | is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0; | |
8271 | break; | |
8272 | case 1: | |
8273 | is_aa64 = is_a64(env); | |
8274 | break; | |
8275 | default: | |
8276 | g_assert_not_reached(); | |
8277 | } | |
8278 | ||
8279 | if (is_aa64) { | |
f3a9b694 PM |
8280 | addr += 0x400; |
8281 | } else { | |
8282 | addr += 0x600; | |
8283 | } | |
8284 | } else if (pstate_read(env) & PSTATE_SP) { | |
8285 | addr += 0x200; | |
8286 | } | |
8287 | ||
f3a9b694 PM |
8288 | switch (cs->exception_index) { |
8289 | case EXCP_PREFETCH_ABORT: | |
8290 | case EXCP_DATA_ABORT: | |
8291 | env->cp15.far_el[new_el] = env->exception.vaddress; | |
8292 | qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", | |
8293 | env->cp15.far_el[new_el]); | |
8294 | /* fall through */ | |
8295 | case EXCP_BKPT: | |
8296 | case EXCP_UDEF: | |
8297 | case EXCP_SWI: | |
8298 | case EXCP_HVC: | |
8299 | case EXCP_HYP_TRAP: | |
8300 | case EXCP_SMC: | |
4be42f40 PM |
8301 | if (syn_get_ec(env->exception.syndrome) == EC_ADVSIMDFPACCESSTRAP) { |
8302 | /* | |
8303 | * QEMU internal FP/SIMD syndromes from AArch32 include the | |
8304 | * TA and coproc fields which are only exposed if the exception | |
8305 | * is taken to AArch32 Hyp mode. Mask them out to get a valid | |
8306 | * AArch64 format syndrome. | |
8307 | */ | |
8308 | env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20); | |
8309 | } | |
f3a9b694 PM |
8310 | env->cp15.esr_el[new_el] = env->exception.syndrome; |
8311 | break; | |
8312 | case EXCP_IRQ: | |
8313 | case EXCP_VIRQ: | |
8314 | addr += 0x80; | |
8315 | break; | |
8316 | case EXCP_FIQ: | |
8317 | case EXCP_VFIQ: | |
8318 | addr += 0x100; | |
8319 | break; | |
8320 | case EXCP_SEMIHOST: | |
8321 | qemu_log_mask(CPU_LOG_INT, | |
8322 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
8323 | env->xregs[0]); | |
8324 | env->xregs[0] = do_arm_semihosting(env); | |
8325 | return; | |
8326 | default: | |
8327 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
8328 | } | |
8329 | ||
8330 | if (is_a64(env)) { | |
8331 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env); | |
8332 | aarch64_save_sp(env, arm_current_el(env)); | |
8333 | env->elr_el[new_el] = env->pc; | |
8334 | } else { | |
8335 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env); | |
f3a9b694 PM |
8336 | env->elr_el[new_el] = env->regs[15]; |
8337 | ||
8338 | aarch64_sync_32_to_64(env); | |
8339 | ||
8340 | env->condexec_bits = 0; | |
8341 | } | |
8342 | qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", | |
8343 | env->elr_el[new_el]); | |
8344 | ||
8345 | pstate_write(env, PSTATE_DAIF | new_mode); | |
8346 | env->aarch64 = 1; | |
8347 | aarch64_restore_sp(env, new_el); | |
8348 | ||
8349 | env->pc = addr; | |
8350 | ||
8351 | qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", | |
8352 | new_el, env->pc, pstate_read(env)); | |
966f758c PM |
8353 | } |
8354 | ||
ed6e6ba9 AB |
8355 | /* |
8356 | * Do semihosting call and set the appropriate return value. All the | |
8357 | * permission and validity checks have been done at translate time. | |
8358 | * | |
8359 | * We only see semihosting exceptions in TCG only as they are not | |
8360 | * trapped to the hypervisor in KVM. | |
8361 | */ | |
91f78c58 | 8362 | #ifdef CONFIG_TCG |
ed6e6ba9 AB |
8363 | static void handle_semihosting(CPUState *cs) |
8364 | { | |
904c04de PM |
8365 | ARMCPU *cpu = ARM_CPU(cs); |
8366 | CPUARMState *env = &cpu->env; | |
8367 | ||
8368 | if (is_a64(env)) { | |
ed6e6ba9 AB |
8369 | qemu_log_mask(CPU_LOG_INT, |
8370 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
8371 | env->xregs[0]); | |
8372 | env->xregs[0] = do_arm_semihosting(env); | |
904c04de | 8373 | } else { |
904c04de PM |
8374 | qemu_log_mask(CPU_LOG_INT, |
8375 | "...handling as semihosting call 0x%x\n", | |
8376 | env->regs[0]); | |
8377 | env->regs[0] = do_arm_semihosting(env); | |
904c04de PM |
8378 | } |
8379 | } | |
ed6e6ba9 | 8380 | #endif |
904c04de | 8381 | |
966f758c PM |
8382 | /* Handle a CPU exception for A and R profile CPUs. |
8383 | * Do any appropriate logging, handle PSCI calls, and then hand off | |
8384 | * to the AArch64-entry or AArch32-entry function depending on the | |
8385 | * target exception level's register width. | |
8386 | */ | |
8387 | void arm_cpu_do_interrupt(CPUState *cs) | |
8388 | { | |
8389 | ARMCPU *cpu = ARM_CPU(cs); | |
8390 | CPUARMState *env = &cpu->env; | |
8391 | unsigned int new_el = env->exception.target_el; | |
8392 | ||
531c60a9 | 8393 | assert(!arm_feature(env, ARM_FEATURE_M)); |
966f758c PM |
8394 | |
8395 | arm_log_exception(cs->exception_index); | |
8396 | qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), | |
8397 | new_el); | |
8398 | if (qemu_loglevel_mask(CPU_LOG_INT) | |
8399 | && !excp_is_internal(cs->exception_index)) { | |
6568da45 | 8400 | qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", |
64b91e3f | 8401 | syn_get_ec(env->exception.syndrome), |
966f758c PM |
8402 | env->exception.syndrome); |
8403 | } | |
8404 | ||
8405 | if (arm_is_psci_call(cpu, cs->exception_index)) { | |
8406 | arm_handle_psci_call(cpu); | |
8407 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | |
8408 | return; | |
8409 | } | |
8410 | ||
ed6e6ba9 AB |
8411 | /* |
8412 | * Semihosting semantics depend on the register width of the code | |
8413 | * that caused the exception, not the target exception level, so | |
8414 | * must be handled here. | |
966f758c | 8415 | */ |
ed6e6ba9 AB |
8416 | #ifdef CONFIG_TCG |
8417 | if (cs->exception_index == EXCP_SEMIHOST) { | |
8418 | handle_semihosting(cs); | |
904c04de PM |
8419 | return; |
8420 | } | |
ed6e6ba9 | 8421 | #endif |
904c04de | 8422 | |
b5c53d1b AL |
8423 | /* Hooks may change global state so BQL should be held, also the |
8424 | * BQL needs to be held for any modification of | |
8425 | * cs->interrupt_request. | |
8426 | */ | |
8427 | g_assert(qemu_mutex_iothread_locked()); | |
8428 | ||
8429 | arm_call_pre_el_change_hook(cpu); | |
8430 | ||
904c04de PM |
8431 | assert(!excp_is_internal(cs->exception_index)); |
8432 | if (arm_el_is_aa64(env, new_el)) { | |
966f758c PM |
8433 | arm_cpu_do_interrupt_aarch64(cs); |
8434 | } else { | |
8435 | arm_cpu_do_interrupt_aarch32(cs); | |
8436 | } | |
f3a9b694 | 8437 | |
bd7d00fc PM |
8438 | arm_call_el_change_hook(cpu); |
8439 | ||
f3a9b694 PM |
8440 | if (!kvm_enabled()) { |
8441 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
8442 | } | |
8443 | } | |
c47eaf9f | 8444 | #endif /* !CONFIG_USER_ONLY */ |
0480f69a PM |
8445 | |
8446 | /* Return the exception level which controls this address translation regime */ | |
8447 | static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) | |
8448 | { | |
8449 | switch (mmu_idx) { | |
8450 | case ARMMMUIdx_S2NS: | |
8451 | case ARMMMUIdx_S1E2: | |
8452 | return 2; | |
8453 | case ARMMMUIdx_S1E3: | |
8454 | return 3; | |
8455 | case ARMMMUIdx_S1SE0: | |
8456 | return arm_el_is_aa64(env, 3) ? 1 : 3; | |
8457 | case ARMMMUIdx_S1SE1: | |
8458 | case ARMMMUIdx_S1NSE0: | |
8459 | case ARMMMUIdx_S1NSE1: | |
62593718 PM |
8460 | case ARMMMUIdx_MPrivNegPri: |
8461 | case ARMMMUIdx_MUserNegPri: | |
e7b921c2 PM |
8462 | case ARMMMUIdx_MPriv: |
8463 | case ARMMMUIdx_MUser: | |
62593718 PM |
8464 | case ARMMMUIdx_MSPrivNegPri: |
8465 | case ARMMMUIdx_MSUserNegPri: | |
66787c78 | 8466 | case ARMMMUIdx_MSPriv: |
66787c78 | 8467 | case ARMMMUIdx_MSUser: |
0480f69a PM |
8468 | return 1; |
8469 | default: | |
8470 | g_assert_not_reached(); | |
8471 | } | |
8472 | } | |
8473 | ||
c47eaf9f PM |
8474 | #ifndef CONFIG_USER_ONLY |
8475 | ||
0480f69a PM |
8476 | /* Return the SCTLR value which controls this address translation regime */ |
8477 | static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) | |
8478 | { | |
8479 | return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; | |
8480 | } | |
8481 | ||
8482 | /* Return true if the specified stage of address translation is disabled */ | |
8483 | static inline bool regime_translation_disabled(CPUARMState *env, | |
8484 | ARMMMUIdx mmu_idx) | |
8485 | { | |
29c483a5 | 8486 | if (arm_feature(env, ARM_FEATURE_M)) { |
ecf5e8ea | 8487 | switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & |
3bef7012 PM |
8488 | (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { |
8489 | case R_V7M_MPU_CTRL_ENABLE_MASK: | |
8490 | /* Enabled, but not for HardFault and NMI */ | |
62593718 | 8491 | return mmu_idx & ARM_MMU_IDX_M_NEGPRI; |
3bef7012 PM |
8492 | case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: |
8493 | /* Enabled for all cases */ | |
8494 | return false; | |
8495 | case 0: | |
8496 | default: | |
8497 | /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but | |
8498 | * we warned about that in armv7m_nvic.c when the guest set it. | |
8499 | */ | |
8500 | return true; | |
8501 | } | |
29c483a5 MD |
8502 | } |
8503 | ||
0480f69a | 8504 | if (mmu_idx == ARMMMUIdx_S2NS) { |
9d1bab33 PM |
8505 | /* HCR.DC means HCR.VM behaves as 1 */ |
8506 | return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) == 0; | |
0480f69a | 8507 | } |
3d0e3080 PM |
8508 | |
8509 | if (env->cp15.hcr_el2 & HCR_TGE) { | |
8510 | /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ | |
8511 | if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) { | |
8512 | return true; | |
8513 | } | |
8514 | } | |
8515 | ||
9d1bab33 PM |
8516 | if ((env->cp15.hcr_el2 & HCR_DC) && |
8517 | (mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1)) { | |
8518 | /* HCR.DC means SCTLR_EL1.M behaves as 0 */ | |
8519 | return true; | |
8520 | } | |
8521 | ||
0480f69a PM |
8522 | return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; |
8523 | } | |
8524 | ||
73462ddd PC |
8525 | static inline bool regime_translation_big_endian(CPUARMState *env, |
8526 | ARMMMUIdx mmu_idx) | |
8527 | { | |
8528 | return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; | |
8529 | } | |
8530 | ||
c47eaf9f PM |
8531 | /* Return the TTBR associated with this translation regime */ |
8532 | static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, | |
8533 | int ttbrn) | |
8534 | { | |
8535 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
8536 | return env->cp15.vttbr_el2; | |
8537 | } | |
8538 | if (ttbrn == 0) { | |
8539 | return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; | |
8540 | } else { | |
8541 | return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; | |
8542 | } | |
8543 | } | |
8544 | ||
8545 | #endif /* !CONFIG_USER_ONLY */ | |
8546 | ||
0480f69a PM |
8547 | /* Return the TCR controlling this translation regime */ |
8548 | static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) | |
8549 | { | |
8550 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
68e9c2fe | 8551 | return &env->cp15.vtcr_el2; |
0480f69a PM |
8552 | } |
8553 | return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; | |
8554 | } | |
8555 | ||
8bd5c820 PM |
8556 | /* Convert a possible stage1+2 MMU index into the appropriate |
8557 | * stage 1 MMU index | |
8558 | */ | |
8559 | static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) | |
8560 | { | |
8561 | if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { | |
8562 | mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_S12NSE0); | |
8563 | } | |
8564 | return mmu_idx; | |
8565 | } | |
8566 | ||
0480f69a PM |
8567 | /* Return true if the translation regime is using LPAE format page tables */ |
8568 | static inline bool regime_using_lpae_format(CPUARMState *env, | |
8569 | ARMMMUIdx mmu_idx) | |
8570 | { | |
8571 | int el = regime_el(env, mmu_idx); | |
8572 | if (el == 2 || arm_el_is_aa64(env, el)) { | |
8573 | return true; | |
8574 | } | |
8575 | if (arm_feature(env, ARM_FEATURE_LPAE) | |
8576 | && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { | |
8577 | return true; | |
8578 | } | |
8579 | return false; | |
8580 | } | |
8581 | ||
deb2db99 AR |
8582 | /* Returns true if the stage 1 translation regime is using LPAE format page |
8583 | * tables. Used when raising alignment exceptions, whose FSR changes depending | |
8584 | * on whether the long or short descriptor format is in use. */ | |
8585 | bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) | |
30901475 | 8586 | { |
8bd5c820 | 8587 | mmu_idx = stage_1_mmu_idx(mmu_idx); |
deb2db99 | 8588 | |
30901475 AB |
8589 | return regime_using_lpae_format(env, mmu_idx); |
8590 | } | |
8591 | ||
c47eaf9f | 8592 | #ifndef CONFIG_USER_ONLY |
0480f69a PM |
8593 | static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) |
8594 | { | |
8595 | switch (mmu_idx) { | |
8596 | case ARMMMUIdx_S1SE0: | |
8597 | case ARMMMUIdx_S1NSE0: | |
e7b921c2 | 8598 | case ARMMMUIdx_MUser: |
871bec7c | 8599 | case ARMMMUIdx_MSUser: |
62593718 PM |
8600 | case ARMMMUIdx_MUserNegPri: |
8601 | case ARMMMUIdx_MSUserNegPri: | |
0480f69a PM |
8602 | return true; |
8603 | default: | |
8604 | return false; | |
8605 | case ARMMMUIdx_S12NSE0: | |
8606 | case ARMMMUIdx_S12NSE1: | |
8607 | g_assert_not_reached(); | |
8608 | } | |
8609 | } | |
8610 | ||
0fbf5238 AJ |
8611 | /* Translate section/page access permissions to page |
8612 | * R/W protection flags | |
d76951b6 AJ |
8613 | * |
8614 | * @env: CPUARMState | |
8615 | * @mmu_idx: MMU index indicating required translation regime | |
8616 | * @ap: The 3-bit access permissions (AP[2:0]) | |
8617 | * @domain_prot: The 2-bit domain access permissions | |
0fbf5238 AJ |
8618 | */ |
8619 | static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, | |
8620 | int ap, int domain_prot) | |
8621 | { | |
554b0b09 PM |
8622 | bool is_user = regime_is_user(env, mmu_idx); |
8623 | ||
8624 | if (domain_prot == 3) { | |
8625 | return PAGE_READ | PAGE_WRITE; | |
8626 | } | |
8627 | ||
554b0b09 PM |
8628 | switch (ap) { |
8629 | case 0: | |
8630 | if (arm_feature(env, ARM_FEATURE_V7)) { | |
8631 | return 0; | |
8632 | } | |
554b0b09 PM |
8633 | switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) { |
8634 | case SCTLR_S: | |
8635 | return is_user ? 0 : PAGE_READ; | |
8636 | case SCTLR_R: | |
8637 | return PAGE_READ; | |
8638 | default: | |
8639 | return 0; | |
8640 | } | |
8641 | case 1: | |
8642 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
8643 | case 2: | |
87c3d486 | 8644 | if (is_user) { |
0fbf5238 | 8645 | return PAGE_READ; |
87c3d486 | 8646 | } else { |
554b0b09 | 8647 | return PAGE_READ | PAGE_WRITE; |
87c3d486 | 8648 | } |
554b0b09 PM |
8649 | case 3: |
8650 | return PAGE_READ | PAGE_WRITE; | |
8651 | case 4: /* Reserved. */ | |
8652 | return 0; | |
8653 | case 5: | |
0fbf5238 | 8654 | return is_user ? 0 : PAGE_READ; |
554b0b09 | 8655 | case 6: |
0fbf5238 | 8656 | return PAGE_READ; |
554b0b09 | 8657 | case 7: |
87c3d486 | 8658 | if (!arm_feature(env, ARM_FEATURE_V6K)) { |
554b0b09 | 8659 | return 0; |
87c3d486 | 8660 | } |
0fbf5238 | 8661 | return PAGE_READ; |
554b0b09 | 8662 | default: |
0fbf5238 | 8663 | g_assert_not_reached(); |
554b0b09 | 8664 | } |
b5ff1b31 FB |
8665 | } |
8666 | ||
d76951b6 AJ |
8667 | /* Translate section/page access permissions to page |
8668 | * R/W protection flags. | |
8669 | * | |
d76951b6 | 8670 | * @ap: The 2-bit simple AP (AP[2:1]) |
d8e052b3 | 8671 | * @is_user: TRUE if accessing from PL0 |
d76951b6 | 8672 | */ |
d8e052b3 | 8673 | static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user) |
d76951b6 | 8674 | { |
d76951b6 AJ |
8675 | switch (ap) { |
8676 | case 0: | |
8677 | return is_user ? 0 : PAGE_READ | PAGE_WRITE; | |
8678 | case 1: | |
8679 | return PAGE_READ | PAGE_WRITE; | |
8680 | case 2: | |
8681 | return is_user ? 0 : PAGE_READ; | |
8682 | case 3: | |
8683 | return PAGE_READ; | |
8684 | default: | |
8685 | g_assert_not_reached(); | |
8686 | } | |
8687 | } | |
8688 | ||
d8e052b3 AJ |
8689 | static inline int |
8690 | simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) | |
8691 | { | |
8692 | return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); | |
8693 | } | |
8694 | ||
6ab1a5ee EI |
8695 | /* Translate S2 section/page access permissions to protection flags |
8696 | * | |
8697 | * @env: CPUARMState | |
8698 | * @s2ap: The 2-bit stage2 access permissions (S2AP) | |
8699 | * @xn: XN (execute-never) bit | |
8700 | */ | |
8701 | static int get_S2prot(CPUARMState *env, int s2ap, int xn) | |
8702 | { | |
8703 | int prot = 0; | |
8704 | ||
8705 | if (s2ap & 1) { | |
8706 | prot |= PAGE_READ; | |
8707 | } | |
8708 | if (s2ap & 2) { | |
8709 | prot |= PAGE_WRITE; | |
8710 | } | |
8711 | if (!xn) { | |
dfda6837 SS |
8712 | if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { |
8713 | prot |= PAGE_EXEC; | |
8714 | } | |
6ab1a5ee EI |
8715 | } |
8716 | return prot; | |
8717 | } | |
8718 | ||
d8e052b3 AJ |
8719 | /* Translate section/page access permissions to protection flags |
8720 | * | |
8721 | * @env: CPUARMState | |
8722 | * @mmu_idx: MMU index indicating required translation regime | |
8723 | * @is_aa64: TRUE if AArch64 | |
8724 | * @ap: The 2-bit simple AP (AP[2:1]) | |
8725 | * @ns: NS (non-secure) bit | |
8726 | * @xn: XN (execute-never) bit | |
8727 | * @pxn: PXN (privileged execute-never) bit | |
8728 | */ | |
8729 | static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, | |
8730 | int ap, int ns, int xn, int pxn) | |
8731 | { | |
8732 | bool is_user = regime_is_user(env, mmu_idx); | |
8733 | int prot_rw, user_rw; | |
8734 | bool have_wxn; | |
8735 | int wxn = 0; | |
8736 | ||
8737 | assert(mmu_idx != ARMMMUIdx_S2NS); | |
8738 | ||
8739 | user_rw = simple_ap_to_rw_prot_is_user(ap, true); | |
8740 | if (is_user) { | |
8741 | prot_rw = user_rw; | |
8742 | } else { | |
8743 | prot_rw = simple_ap_to_rw_prot_is_user(ap, false); | |
8744 | } | |
8745 | ||
8746 | if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { | |
8747 | return prot_rw; | |
8748 | } | |
8749 | ||
8750 | /* TODO have_wxn should be replaced with | |
8751 | * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) | |
8752 | * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE | |
8753 | * compatible processors have EL2, which is required for [U]WXN. | |
8754 | */ | |
8755 | have_wxn = arm_feature(env, ARM_FEATURE_LPAE); | |
8756 | ||
8757 | if (have_wxn) { | |
8758 | wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN; | |
8759 | } | |
8760 | ||
8761 | if (is_aa64) { | |
8762 | switch (regime_el(env, mmu_idx)) { | |
8763 | case 1: | |
8764 | if (!is_user) { | |
8765 | xn = pxn || (user_rw & PAGE_WRITE); | |
8766 | } | |
8767 | break; | |
8768 | case 2: | |
8769 | case 3: | |
8770 | break; | |
8771 | } | |
8772 | } else if (arm_feature(env, ARM_FEATURE_V7)) { | |
8773 | switch (regime_el(env, mmu_idx)) { | |
8774 | case 1: | |
8775 | case 3: | |
8776 | if (is_user) { | |
8777 | xn = xn || !(user_rw & PAGE_READ); | |
8778 | } else { | |
8779 | int uwxn = 0; | |
8780 | if (have_wxn) { | |
8781 | uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN; | |
8782 | } | |
8783 | xn = xn || !(prot_rw & PAGE_READ) || pxn || | |
8784 | (uwxn && (user_rw & PAGE_WRITE)); | |
8785 | } | |
8786 | break; | |
8787 | case 2: | |
8788 | break; | |
8789 | } | |
8790 | } else { | |
8791 | xn = wxn = 0; | |
8792 | } | |
8793 | ||
8794 | if (xn || (wxn && (prot_rw & PAGE_WRITE))) { | |
8795 | return prot_rw; | |
8796 | } | |
8797 | return prot_rw | PAGE_EXEC; | |
8798 | } | |
8799 | ||
0480f69a PM |
8800 | static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, |
8801 | uint32_t *table, uint32_t address) | |
b2fa1797 | 8802 | { |
0480f69a | 8803 | /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ |
0480f69a | 8804 | TCR *tcr = regime_tcr(env, mmu_idx); |
11f136ee | 8805 | |
11f136ee FA |
8806 | if (address & tcr->mask) { |
8807 | if (tcr->raw_tcr & TTBCR_PD1) { | |
e389be16 FA |
8808 | /* Translation table walk disabled for TTBR1 */ |
8809 | return false; | |
8810 | } | |
aef878be | 8811 | *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; |
e389be16 | 8812 | } else { |
11f136ee | 8813 | if (tcr->raw_tcr & TTBCR_PD0) { |
e389be16 FA |
8814 | /* Translation table walk disabled for TTBR0 */ |
8815 | return false; | |
8816 | } | |
aef878be | 8817 | *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; |
e389be16 FA |
8818 | } |
8819 | *table |= (address >> 18) & 0x3ffc; | |
8820 | return true; | |
b2fa1797 PB |
8821 | } |
8822 | ||
37785977 EI |
8823 | /* Translate a S1 pagetable walk through S2 if needed. */ |
8824 | static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, | |
8825 | hwaddr addr, MemTxAttrs txattrs, | |
37785977 EI |
8826 | ARMMMUFaultInfo *fi) |
8827 | { | |
8828 | if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) && | |
8829 | !regime_translation_disabled(env, ARMMMUIdx_S2NS)) { | |
8830 | target_ulong s2size; | |
8831 | hwaddr s2pa; | |
8832 | int s2prot; | |
8833 | int ret; | |
eadb2feb PM |
8834 | ARMCacheAttrs cacheattrs = {}; |
8835 | ARMCacheAttrs *pcacheattrs = NULL; | |
8836 | ||
8837 | if (env->cp15.hcr_el2 & HCR_PTW) { | |
8838 | /* | |
8839 | * PTW means we must fault if this S1 walk touches S2 Device | |
8840 | * memory; otherwise we don't care about the attributes and can | |
8841 | * save the S2 translation the effort of computing them. | |
8842 | */ | |
8843 | pcacheattrs = &cacheattrs; | |
8844 | } | |
37785977 EI |
8845 | |
8846 | ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, | |
eadb2feb | 8847 | &txattrs, &s2prot, &s2size, fi, pcacheattrs); |
37785977 | 8848 | if (ret) { |
3b39d734 | 8849 | assert(fi->type != ARMFault_None); |
37785977 EI |
8850 | fi->s2addr = addr; |
8851 | fi->stage2 = true; | |
8852 | fi->s1ptw = true; | |
8853 | return ~0; | |
8854 | } | |
eadb2feb PM |
8855 | if (pcacheattrs && (pcacheattrs->attrs & 0xf0) == 0) { |
8856 | /* Access was to Device memory: generate Permission fault */ | |
8857 | fi->type = ARMFault_Permission; | |
8858 | fi->s2addr = addr; | |
8859 | fi->stage2 = true; | |
8860 | fi->s1ptw = true; | |
8861 | return ~0; | |
8862 | } | |
37785977 EI |
8863 | addr = s2pa; |
8864 | } | |
8865 | return addr; | |
8866 | } | |
8867 | ||
14577270 | 8868 | /* All loads done in the course of a page table walk go through here. */ |
a614e698 | 8869 | static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, |
3795a6de | 8870 | ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) |
ebca90e4 | 8871 | { |
a614e698 EI |
8872 | ARMCPU *cpu = ARM_CPU(cs); |
8873 | CPUARMState *env = &cpu->env; | |
ebca90e4 | 8874 | MemTxAttrs attrs = {}; |
3b39d734 | 8875 | MemTxResult result = MEMTX_OK; |
5ce4ff65 | 8876 | AddressSpace *as; |
3b39d734 | 8877 | uint32_t data; |
ebca90e4 PM |
8878 | |
8879 | attrs.secure = is_secure; | |
5ce4ff65 | 8880 | as = arm_addressspace(cs, attrs); |
3795a6de | 8881 | addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi); |
a614e698 EI |
8882 | if (fi->s1ptw) { |
8883 | return 0; | |
8884 | } | |
73462ddd | 8885 | if (regime_translation_big_endian(env, mmu_idx)) { |
3b39d734 | 8886 | data = address_space_ldl_be(as, addr, attrs, &result); |
73462ddd | 8887 | } else { |
3b39d734 | 8888 | data = address_space_ldl_le(as, addr, attrs, &result); |
73462ddd | 8889 | } |
3b39d734 PM |
8890 | if (result == MEMTX_OK) { |
8891 | return data; | |
8892 | } | |
8893 | fi->type = ARMFault_SyncExternalOnWalk; | |
8894 | fi->ea = arm_extabort_type(result); | |
8895 | return 0; | |
ebca90e4 PM |
8896 | } |
8897 | ||
37785977 | 8898 | static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, |
3795a6de | 8899 | ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) |
ebca90e4 | 8900 | { |
37785977 EI |
8901 | ARMCPU *cpu = ARM_CPU(cs); |
8902 | CPUARMState *env = &cpu->env; | |
ebca90e4 | 8903 | MemTxAttrs attrs = {}; |
3b39d734 | 8904 | MemTxResult result = MEMTX_OK; |
5ce4ff65 | 8905 | AddressSpace *as; |
9aea1ea3 | 8906 | uint64_t data; |
ebca90e4 PM |
8907 | |
8908 | attrs.secure = is_secure; | |
5ce4ff65 | 8909 | as = arm_addressspace(cs, attrs); |
3795a6de | 8910 | addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi); |
37785977 EI |
8911 | if (fi->s1ptw) { |
8912 | return 0; | |
8913 | } | |
73462ddd | 8914 | if (regime_translation_big_endian(env, mmu_idx)) { |
3b39d734 | 8915 | data = address_space_ldq_be(as, addr, attrs, &result); |
73462ddd | 8916 | } else { |
3b39d734 PM |
8917 | data = address_space_ldq_le(as, addr, attrs, &result); |
8918 | } | |
8919 | if (result == MEMTX_OK) { | |
8920 | return data; | |
73462ddd | 8921 | } |
3b39d734 PM |
8922 | fi->type = ARMFault_SyncExternalOnWalk; |
8923 | fi->ea = arm_extabort_type(result); | |
8924 | return 0; | |
ebca90e4 PM |
8925 | } |
8926 | ||
b7cc4e82 | 8927 | static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, |
03ae85f8 | 8928 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
b7cc4e82 | 8929 | hwaddr *phys_ptr, int *prot, |
f989983e | 8930 | target_ulong *page_size, |
e14b5a23 | 8931 | ARMMMUFaultInfo *fi) |
b5ff1b31 | 8932 | { |
2fc0cc0e | 8933 | CPUState *cs = env_cpu(env); |
f989983e | 8934 | int level = 1; |
b5ff1b31 FB |
8935 | uint32_t table; |
8936 | uint32_t desc; | |
8937 | int type; | |
8938 | int ap; | |
e389be16 | 8939 | int domain = 0; |
dd4ebc2e | 8940 | int domain_prot; |
a8170e5e | 8941 | hwaddr phys_addr; |
0480f69a | 8942 | uint32_t dacr; |
b5ff1b31 | 8943 | |
9ee6e8bb PB |
8944 | /* Pagetable walk. */ |
8945 | /* Lookup l1 descriptor. */ | |
0480f69a | 8946 | if (!get_level1_table_address(env, mmu_idx, &table, address)) { |
e389be16 | 8947 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ |
f989983e | 8948 | fi->type = ARMFault_Translation; |
e389be16 FA |
8949 | goto do_fault; |
8950 | } | |
a614e698 | 8951 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 8952 | mmu_idx, fi); |
3b39d734 PM |
8953 | if (fi->type != ARMFault_None) { |
8954 | goto do_fault; | |
8955 | } | |
9ee6e8bb | 8956 | type = (desc & 3); |
dd4ebc2e | 8957 | domain = (desc >> 5) & 0x0f; |
0480f69a PM |
8958 | if (regime_el(env, mmu_idx) == 1) { |
8959 | dacr = env->cp15.dacr_ns; | |
8960 | } else { | |
8961 | dacr = env->cp15.dacr_s; | |
8962 | } | |
8963 | domain_prot = (dacr >> (domain * 2)) & 3; | |
9ee6e8bb | 8964 | if (type == 0) { |
601d70b9 | 8965 | /* Section translation fault. */ |
f989983e | 8966 | fi->type = ARMFault_Translation; |
9ee6e8bb PB |
8967 | goto do_fault; |
8968 | } | |
f989983e PM |
8969 | if (type != 2) { |
8970 | level = 2; | |
8971 | } | |
dd4ebc2e | 8972 | if (domain_prot == 0 || domain_prot == 2) { |
f989983e | 8973 | fi->type = ARMFault_Domain; |
9ee6e8bb PB |
8974 | goto do_fault; |
8975 | } | |
8976 | if (type == 2) { | |
8977 | /* 1Mb section. */ | |
8978 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
8979 | ap = (desc >> 10) & 3; | |
d4c430a8 | 8980 | *page_size = 1024 * 1024; |
9ee6e8bb PB |
8981 | } else { |
8982 | /* Lookup l2 entry. */ | |
554b0b09 PM |
8983 | if (type == 1) { |
8984 | /* Coarse pagetable. */ | |
8985 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
8986 | } else { | |
8987 | /* Fine pagetable. */ | |
8988 | table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); | |
8989 | } | |
a614e698 | 8990 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 8991 | mmu_idx, fi); |
3b39d734 PM |
8992 | if (fi->type != ARMFault_None) { |
8993 | goto do_fault; | |
8994 | } | |
9ee6e8bb PB |
8995 | switch (desc & 3) { |
8996 | case 0: /* Page translation fault. */ | |
f989983e | 8997 | fi->type = ARMFault_Translation; |
9ee6e8bb PB |
8998 | goto do_fault; |
8999 | case 1: /* 64k page. */ | |
9000 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
9001 | ap = (desc >> (4 + ((address >> 13) & 6))) & 3; | |
d4c430a8 | 9002 | *page_size = 0x10000; |
ce819861 | 9003 | break; |
9ee6e8bb PB |
9004 | case 2: /* 4k page. */ |
9005 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
c10f7fc3 | 9006 | ap = (desc >> (4 + ((address >> 9) & 6))) & 3; |
d4c430a8 | 9007 | *page_size = 0x1000; |
ce819861 | 9008 | break; |
fc1891c7 | 9009 | case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ |
554b0b09 | 9010 | if (type == 1) { |
fc1891c7 PM |
9011 | /* ARMv6/XScale extended small page format */ |
9012 | if (arm_feature(env, ARM_FEATURE_XSCALE) | |
9013 | || arm_feature(env, ARM_FEATURE_V6)) { | |
554b0b09 | 9014 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); |
fc1891c7 | 9015 | *page_size = 0x1000; |
554b0b09 | 9016 | } else { |
fc1891c7 PM |
9017 | /* UNPREDICTABLE in ARMv5; we choose to take a |
9018 | * page translation fault. | |
9019 | */ | |
f989983e | 9020 | fi->type = ARMFault_Translation; |
554b0b09 PM |
9021 | goto do_fault; |
9022 | } | |
9023 | } else { | |
9024 | phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); | |
fc1891c7 | 9025 | *page_size = 0x400; |
554b0b09 | 9026 | } |
9ee6e8bb | 9027 | ap = (desc >> 4) & 3; |
ce819861 PB |
9028 | break; |
9029 | default: | |
9ee6e8bb PB |
9030 | /* Never happens, but compiler isn't smart enough to tell. */ |
9031 | abort(); | |
ce819861 | 9032 | } |
9ee6e8bb | 9033 | } |
0fbf5238 AJ |
9034 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); |
9035 | *prot |= *prot ? PAGE_EXEC : 0; | |
9036 | if (!(*prot & (1 << access_type))) { | |
9ee6e8bb | 9037 | /* Access permission fault. */ |
f989983e | 9038 | fi->type = ARMFault_Permission; |
9ee6e8bb PB |
9039 | goto do_fault; |
9040 | } | |
9041 | *phys_ptr = phys_addr; | |
b7cc4e82 | 9042 | return false; |
9ee6e8bb | 9043 | do_fault: |
f989983e PM |
9044 | fi->domain = domain; |
9045 | fi->level = level; | |
b7cc4e82 | 9046 | return true; |
9ee6e8bb PB |
9047 | } |
9048 | ||
b7cc4e82 | 9049 | static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, |
03ae85f8 | 9050 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
b7cc4e82 | 9051 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, |
f06cf243 | 9052 | target_ulong *page_size, ARMMMUFaultInfo *fi) |
9ee6e8bb | 9053 | { |
2fc0cc0e | 9054 | CPUState *cs = env_cpu(env); |
f06cf243 | 9055 | int level = 1; |
9ee6e8bb PB |
9056 | uint32_t table; |
9057 | uint32_t desc; | |
9058 | uint32_t xn; | |
de9b05b8 | 9059 | uint32_t pxn = 0; |
9ee6e8bb PB |
9060 | int type; |
9061 | int ap; | |
de9b05b8 | 9062 | int domain = 0; |
dd4ebc2e | 9063 | int domain_prot; |
a8170e5e | 9064 | hwaddr phys_addr; |
0480f69a | 9065 | uint32_t dacr; |
8bf5b6a9 | 9066 | bool ns; |
9ee6e8bb PB |
9067 | |
9068 | /* Pagetable walk. */ | |
9069 | /* Lookup l1 descriptor. */ | |
0480f69a | 9070 | if (!get_level1_table_address(env, mmu_idx, &table, address)) { |
e389be16 | 9071 | /* Section translation fault if page walk is disabled by PD0 or PD1 */ |
f06cf243 | 9072 | fi->type = ARMFault_Translation; |
e389be16 FA |
9073 | goto do_fault; |
9074 | } | |
a614e698 | 9075 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 9076 | mmu_idx, fi); |
3b39d734 PM |
9077 | if (fi->type != ARMFault_None) { |
9078 | goto do_fault; | |
9079 | } | |
9ee6e8bb | 9080 | type = (desc & 3); |
de9b05b8 PM |
9081 | if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { |
9082 | /* Section translation fault, or attempt to use the encoding | |
9083 | * which is Reserved on implementations without PXN. | |
9084 | */ | |
f06cf243 | 9085 | fi->type = ARMFault_Translation; |
9ee6e8bb | 9086 | goto do_fault; |
de9b05b8 PM |
9087 | } |
9088 | if ((type == 1) || !(desc & (1 << 18))) { | |
9089 | /* Page or Section. */ | |
dd4ebc2e | 9090 | domain = (desc >> 5) & 0x0f; |
9ee6e8bb | 9091 | } |
0480f69a PM |
9092 | if (regime_el(env, mmu_idx) == 1) { |
9093 | dacr = env->cp15.dacr_ns; | |
9094 | } else { | |
9095 | dacr = env->cp15.dacr_s; | |
9096 | } | |
f06cf243 PM |
9097 | if (type == 1) { |
9098 | level = 2; | |
9099 | } | |
0480f69a | 9100 | domain_prot = (dacr >> (domain * 2)) & 3; |
dd4ebc2e | 9101 | if (domain_prot == 0 || domain_prot == 2) { |
f06cf243 PM |
9102 | /* Section or Page domain fault */ |
9103 | fi->type = ARMFault_Domain; | |
9ee6e8bb PB |
9104 | goto do_fault; |
9105 | } | |
de9b05b8 | 9106 | if (type != 1) { |
9ee6e8bb PB |
9107 | if (desc & (1 << 18)) { |
9108 | /* Supersection. */ | |
9109 | phys_addr = (desc & 0xff000000) | (address & 0x00ffffff); | |
4e42a6ca SF |
9110 | phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32; |
9111 | phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36; | |
d4c430a8 | 9112 | *page_size = 0x1000000; |
b5ff1b31 | 9113 | } else { |
9ee6e8bb PB |
9114 | /* Section. */ |
9115 | phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); | |
d4c430a8 | 9116 | *page_size = 0x100000; |
b5ff1b31 | 9117 | } |
9ee6e8bb PB |
9118 | ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); |
9119 | xn = desc & (1 << 4); | |
de9b05b8 | 9120 | pxn = desc & 1; |
8bf5b6a9 | 9121 | ns = extract32(desc, 19, 1); |
9ee6e8bb | 9122 | } else { |
de9b05b8 PM |
9123 | if (arm_feature(env, ARM_FEATURE_PXN)) { |
9124 | pxn = (desc >> 2) & 1; | |
9125 | } | |
8bf5b6a9 | 9126 | ns = extract32(desc, 3, 1); |
9ee6e8bb PB |
9127 | /* Lookup l2 entry. */ |
9128 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | |
a614e698 | 9129 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), |
3795a6de | 9130 | mmu_idx, fi); |
3b39d734 PM |
9131 | if (fi->type != ARMFault_None) { |
9132 | goto do_fault; | |
9133 | } | |
9ee6e8bb PB |
9134 | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); |
9135 | switch (desc & 3) { | |
9136 | case 0: /* Page translation fault. */ | |
f06cf243 | 9137 | fi->type = ARMFault_Translation; |
b5ff1b31 | 9138 | goto do_fault; |
9ee6e8bb PB |
9139 | case 1: /* 64k page. */ |
9140 | phys_addr = (desc & 0xffff0000) | (address & 0xffff); | |
9141 | xn = desc & (1 << 15); | |
d4c430a8 | 9142 | *page_size = 0x10000; |
9ee6e8bb PB |
9143 | break; |
9144 | case 2: case 3: /* 4k page. */ | |
9145 | phys_addr = (desc & 0xfffff000) | (address & 0xfff); | |
9146 | xn = desc & 1; | |
d4c430a8 | 9147 | *page_size = 0x1000; |
9ee6e8bb PB |
9148 | break; |
9149 | default: | |
9150 | /* Never happens, but compiler isn't smart enough to tell. */ | |
9151 | abort(); | |
b5ff1b31 | 9152 | } |
9ee6e8bb | 9153 | } |
dd4ebc2e | 9154 | if (domain_prot == 3) { |
c0034328 JR |
9155 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
9156 | } else { | |
0480f69a | 9157 | if (pxn && !regime_is_user(env, mmu_idx)) { |
de9b05b8 PM |
9158 | xn = 1; |
9159 | } | |
f06cf243 PM |
9160 | if (xn && access_type == MMU_INST_FETCH) { |
9161 | fi->type = ARMFault_Permission; | |
c0034328 | 9162 | goto do_fault; |
f06cf243 | 9163 | } |
9ee6e8bb | 9164 | |
d76951b6 AJ |
9165 | if (arm_feature(env, ARM_FEATURE_V6K) && |
9166 | (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { | |
9167 | /* The simplified model uses AP[0] as an access control bit. */ | |
9168 | if ((ap & 1) == 0) { | |
9169 | /* Access flag fault. */ | |
f06cf243 | 9170 | fi->type = ARMFault_AccessFlag; |
d76951b6 AJ |
9171 | goto do_fault; |
9172 | } | |
9173 | *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); | |
9174 | } else { | |
9175 | *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); | |
c0034328 | 9176 | } |
0fbf5238 AJ |
9177 | if (*prot && !xn) { |
9178 | *prot |= PAGE_EXEC; | |
9179 | } | |
9180 | if (!(*prot & (1 << access_type))) { | |
c0034328 | 9181 | /* Access permission fault. */ |
f06cf243 | 9182 | fi->type = ARMFault_Permission; |
c0034328 JR |
9183 | goto do_fault; |
9184 | } | |
3ad493fc | 9185 | } |
8bf5b6a9 PM |
9186 | if (ns) { |
9187 | /* The NS bit will (as required by the architecture) have no effect if | |
9188 | * the CPU doesn't support TZ or this is a non-secure translation | |
9189 | * regime, because the attribute will already be non-secure. | |
9190 | */ | |
9191 | attrs->secure = false; | |
9192 | } | |
9ee6e8bb | 9193 | *phys_ptr = phys_addr; |
b7cc4e82 | 9194 | return false; |
b5ff1b31 | 9195 | do_fault: |
f06cf243 PM |
9196 | fi->domain = domain; |
9197 | fi->level = level; | |
b7cc4e82 | 9198 | return true; |
b5ff1b31 FB |
9199 | } |
9200 | ||
1853d5a9 | 9201 | /* |
a0e966c9 | 9202 | * check_s2_mmu_setup |
1853d5a9 EI |
9203 | * @cpu: ARMCPU |
9204 | * @is_aa64: True if the translation regime is in AArch64 state | |
9205 | * @startlevel: Suggested starting level | |
9206 | * @inputsize: Bitsize of IPAs | |
9207 | * @stride: Page-table stride (See the ARM ARM) | |
9208 | * | |
a0e966c9 EI |
9209 | * Returns true if the suggested S2 translation parameters are OK and |
9210 | * false otherwise. | |
1853d5a9 | 9211 | */ |
a0e966c9 EI |
9212 | static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, |
9213 | int inputsize, int stride) | |
1853d5a9 | 9214 | { |
98d68ec2 EI |
9215 | const int grainsize = stride + 3; |
9216 | int startsizecheck; | |
9217 | ||
1853d5a9 EI |
9218 | /* Negative levels are never allowed. */ |
9219 | if (level < 0) { | |
9220 | return false; | |
9221 | } | |
9222 | ||
98d68ec2 EI |
9223 | startsizecheck = inputsize - ((3 - level) * stride + grainsize); |
9224 | if (startsizecheck < 1 || startsizecheck > stride + 4) { | |
9225 | return false; | |
9226 | } | |
9227 | ||
1853d5a9 | 9228 | if (is_aa64) { |
3526423e | 9229 | CPUARMState *env = &cpu->env; |
1853d5a9 EI |
9230 | unsigned int pamax = arm_pamax(cpu); |
9231 | ||
9232 | switch (stride) { | |
9233 | case 13: /* 64KB Pages. */ | |
9234 | if (level == 0 || (level == 1 && pamax <= 42)) { | |
9235 | return false; | |
9236 | } | |
9237 | break; | |
9238 | case 11: /* 16KB Pages. */ | |
9239 | if (level == 0 || (level == 1 && pamax <= 40)) { | |
9240 | return false; | |
9241 | } | |
9242 | break; | |
9243 | case 9: /* 4KB Pages. */ | |
9244 | if (level == 0 && pamax <= 42) { | |
9245 | return false; | |
9246 | } | |
9247 | break; | |
9248 | default: | |
9249 | g_assert_not_reached(); | |
9250 | } | |
3526423e EI |
9251 | |
9252 | /* Inputsize checks. */ | |
9253 | if (inputsize > pamax && | |
9254 | (arm_el_is_aa64(env, 1) || inputsize > 40)) { | |
9255 | /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ | |
9256 | return false; | |
9257 | } | |
1853d5a9 | 9258 | } else { |
1853d5a9 EI |
9259 | /* AArch32 only supports 4KB pages. Assert on that. */ |
9260 | assert(stride == 9); | |
9261 | ||
9262 | if (level == 0) { | |
9263 | return false; | |
9264 | } | |
1853d5a9 EI |
9265 | } |
9266 | return true; | |
9267 | } | |
9268 | ||
5b2d261d AB |
9269 | /* Translate from the 4-bit stage 2 representation of |
9270 | * memory attributes (without cache-allocation hints) to | |
9271 | * the 8-bit representation of the stage 1 MAIR registers | |
9272 | * (which includes allocation hints). | |
9273 | * | |
9274 | * ref: shared/translation/attrs/S2AttrDecode() | |
9275 | * .../S2ConvertAttrsHints() | |
9276 | */ | |
9277 | static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) | |
9278 | { | |
9279 | uint8_t hiattr = extract32(s2attrs, 2, 2); | |
9280 | uint8_t loattr = extract32(s2attrs, 0, 2); | |
9281 | uint8_t hihint = 0, lohint = 0; | |
9282 | ||
9283 | if (hiattr != 0) { /* normal memory */ | |
9284 | if ((env->cp15.hcr_el2 & HCR_CD) != 0) { /* cache disabled */ | |
9285 | hiattr = loattr = 1; /* non-cacheable */ | |
9286 | } else { | |
9287 | if (hiattr != 1) { /* Write-through or write-back */ | |
9288 | hihint = 3; /* RW allocate */ | |
9289 | } | |
9290 | if (loattr != 1) { /* Write-through or write-back */ | |
9291 | lohint = 3; /* RW allocate */ | |
9292 | } | |
9293 | } | |
9294 | } | |
9295 | ||
9296 | return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; | |
9297 | } | |
c47eaf9f | 9298 | #endif /* !CONFIG_USER_ONLY */ |
5b2d261d | 9299 | |
e737ed2a RH |
9300 | ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, |
9301 | ARMMMUIdx mmu_idx) | |
ba97be9f RH |
9302 | { |
9303 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | |
9304 | uint32_t el = regime_el(env, mmu_idx); | |
8220af7e | 9305 | bool tbi, tbid, epd, hpd, using16k, using64k; |
ba97be9f RH |
9306 | int select, tsz; |
9307 | ||
9308 | /* | |
9309 | * Bit 55 is always between the two regions, and is canonical for | |
9310 | * determining if address tagging is enabled. | |
9311 | */ | |
9312 | select = extract64(va, 55, 1); | |
9313 | ||
9314 | if (el > 1) { | |
9315 | tsz = extract32(tcr, 0, 6); | |
9316 | using64k = extract32(tcr, 14, 1); | |
9317 | using16k = extract32(tcr, 15, 1); | |
9318 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
9319 | /* VTCR_EL2 */ | |
8220af7e | 9320 | tbi = tbid = hpd = false; |
ba97be9f RH |
9321 | } else { |
9322 | tbi = extract32(tcr, 20, 1); | |
9323 | hpd = extract32(tcr, 24, 1); | |
8220af7e | 9324 | tbid = extract32(tcr, 29, 1); |
ba97be9f RH |
9325 | } |
9326 | epd = false; | |
9327 | } else if (!select) { | |
9328 | tsz = extract32(tcr, 0, 6); | |
9329 | epd = extract32(tcr, 7, 1); | |
9330 | using64k = extract32(tcr, 14, 1); | |
9331 | using16k = extract32(tcr, 15, 1); | |
9332 | tbi = extract64(tcr, 37, 1); | |
9333 | hpd = extract64(tcr, 41, 1); | |
8220af7e | 9334 | tbid = extract64(tcr, 51, 1); |
ba97be9f RH |
9335 | } else { |
9336 | int tg = extract32(tcr, 30, 2); | |
9337 | using16k = tg == 1; | |
9338 | using64k = tg == 3; | |
9339 | tsz = extract32(tcr, 16, 6); | |
9340 | epd = extract32(tcr, 23, 1); | |
9341 | tbi = extract64(tcr, 38, 1); | |
9342 | hpd = extract64(tcr, 42, 1); | |
8220af7e | 9343 | tbid = extract64(tcr, 52, 1); |
ba97be9f RH |
9344 | } |
9345 | tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ | |
9346 | tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ | |
9347 | ||
9348 | return (ARMVAParameters) { | |
9349 | .tsz = tsz, | |
9350 | .select = select, | |
9351 | .tbi = tbi, | |
8220af7e | 9352 | .tbid = tbid, |
ba97be9f RH |
9353 | .epd = epd, |
9354 | .hpd = hpd, | |
9355 | .using16k = using16k, | |
9356 | .using64k = using64k, | |
9357 | }; | |
9358 | } | |
9359 | ||
e737ed2a RH |
9360 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, |
9361 | ARMMMUIdx mmu_idx, bool data) | |
9362 | { | |
8220af7e RH |
9363 | ARMVAParameters ret = aa64_va_parameters_both(env, va, mmu_idx); |
9364 | ||
9365 | /* Present TBI as a composite with TBID. */ | |
9366 | ret.tbi &= (data || !ret.tbid); | |
9367 | return ret; | |
e737ed2a RH |
9368 | } |
9369 | ||
c47eaf9f | 9370 | #ifndef CONFIG_USER_ONLY |
ba97be9f RH |
9371 | static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, |
9372 | ARMMMUIdx mmu_idx) | |
9373 | { | |
9374 | uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; | |
9375 | uint32_t el = regime_el(env, mmu_idx); | |
9376 | int select, tsz; | |
9377 | bool epd, hpd; | |
9378 | ||
9379 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
9380 | /* VTCR */ | |
9381 | bool sext = extract32(tcr, 4, 1); | |
9382 | bool sign = extract32(tcr, 3, 1); | |
9383 | ||
9384 | /* | |
9385 | * If the sign-extend bit is not the same as t0sz[3], the result | |
9386 | * is unpredictable. Flag this as a guest error. | |
9387 | */ | |
9388 | if (sign != sext) { | |
9389 | qemu_log_mask(LOG_GUEST_ERROR, | |
9390 | "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); | |
9391 | } | |
9392 | tsz = sextract32(tcr, 0, 4) + 8; | |
9393 | select = 0; | |
9394 | hpd = false; | |
9395 | epd = false; | |
9396 | } else if (el == 2) { | |
9397 | /* HTCR */ | |
9398 | tsz = extract32(tcr, 0, 3); | |
9399 | select = 0; | |
9400 | hpd = extract64(tcr, 24, 1); | |
9401 | epd = false; | |
9402 | } else { | |
9403 | int t0sz = extract32(tcr, 0, 3); | |
9404 | int t1sz = extract32(tcr, 16, 3); | |
9405 | ||
9406 | if (t1sz == 0) { | |
9407 | select = va > (0xffffffffu >> t0sz); | |
9408 | } else { | |
9409 | /* Note that we will detect errors later. */ | |
9410 | select = va >= ~(0xffffffffu >> t1sz); | |
9411 | } | |
9412 | if (!select) { | |
9413 | tsz = t0sz; | |
9414 | epd = extract32(tcr, 7, 1); | |
9415 | hpd = extract64(tcr, 41, 1); | |
9416 | } else { | |
9417 | tsz = t1sz; | |
9418 | epd = extract32(tcr, 23, 1); | |
9419 | hpd = extract64(tcr, 42, 1); | |
9420 | } | |
9421 | /* For aarch32, hpd0 is not enabled without t2e as well. */ | |
9422 | hpd &= extract32(tcr, 6, 1); | |
9423 | } | |
9424 | ||
9425 | return (ARMVAParameters) { | |
9426 | .tsz = tsz, | |
9427 | .select = select, | |
9428 | .epd = epd, | |
9429 | .hpd = hpd, | |
9430 | }; | |
9431 | } | |
9432 | ||
b7cc4e82 | 9433 | static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, |
03ae85f8 | 9434 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
b7cc4e82 | 9435 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, |
da909b2c | 9436 | target_ulong *page_size_ptr, |
5b2d261d | 9437 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) |
3dde962f | 9438 | { |
2fc0cc0e | 9439 | ARMCPU *cpu = env_archcpu(env); |
1853d5a9 | 9440 | CPUState *cs = CPU(cpu); |
3dde962f | 9441 | /* Read an LPAE long-descriptor translation table. */ |
da909b2c | 9442 | ARMFaultType fault_type = ARMFault_Translation; |
1b4093ea | 9443 | uint32_t level; |
ba97be9f | 9444 | ARMVAParameters param; |
3dde962f | 9445 | uint64_t ttbr; |
dddb5223 | 9446 | hwaddr descaddr, indexmask, indexmask_grainsize; |
3dde962f | 9447 | uint32_t tableattrs; |
36d820af | 9448 | target_ulong page_size; |
3dde962f | 9449 | uint32_t attrs; |
ba97be9f RH |
9450 | int32_t stride; |
9451 | int addrsize, inputsize; | |
0480f69a | 9452 | TCR *tcr = regime_tcr(env, mmu_idx); |
d8e052b3 | 9453 | int ap, ns, xn, pxn; |
88e8add8 | 9454 | uint32_t el = regime_el(env, mmu_idx); |
ba97be9f | 9455 | bool ttbr1_valid; |
6109769a | 9456 | uint64_t descaddrmask; |
6e99f762 | 9457 | bool aarch64 = arm_el_is_aa64(env, el); |
1bafc2ba | 9458 | bool guarded = false; |
0480f69a PM |
9459 | |
9460 | /* TODO: | |
88e8add8 GB |
9461 | * This code does not handle the different format TCR for VTCR_EL2. |
9462 | * This code also does not support shareability levels. | |
9463 | * Attribute and permission bit handling should also be checked when adding | |
9464 | * support for those page table walks. | |
0480f69a | 9465 | */ |
6e99f762 | 9466 | if (aarch64) { |
ba97be9f RH |
9467 | param = aa64_va_parameters(env, address, mmu_idx, |
9468 | access_type != MMU_INST_FETCH); | |
1b4093ea | 9469 | level = 0; |
88e8add8 GB |
9470 | /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it |
9471 | * invalid. | |
9472 | */ | |
ba97be9f RH |
9473 | ttbr1_valid = (el < 2); |
9474 | addrsize = 64 - 8 * param.tbi; | |
9475 | inputsize = 64 - param.tsz; | |
d0a2cbce | 9476 | } else { |
ba97be9f | 9477 | param = aa32_va_parameters(env, address, mmu_idx); |
1b4093ea | 9478 | level = 1; |
d0a2cbce | 9479 | /* There is no TTBR1 for EL2 */ |
ba97be9f RH |
9480 | ttbr1_valid = (el != 2); |
9481 | addrsize = (mmu_idx == ARMMMUIdx_S2NS ? 40 : 32); | |
9482 | inputsize = addrsize - param.tsz; | |
2c8dd318 | 9483 | } |
3dde962f | 9484 | |
ba97be9f RH |
9485 | /* |
9486 | * We determined the region when collecting the parameters, but we | |
9487 | * have not yet validated that the address is valid for the region. | |
9488 | * Extract the top bits and verify that they all match select. | |
36d820af RH |
9489 | * |
9490 | * For aa32, if inputsize == addrsize, then we have selected the | |
9491 | * region by exclusion in aa32_va_parameters and there is no more | |
9492 | * validation to do here. | |
9493 | */ | |
9494 | if (inputsize < addrsize) { | |
9495 | target_ulong top_bits = sextract64(address, inputsize, | |
9496 | addrsize - inputsize); | |
9497 | if (-top_bits != param.select || (param.select && !ttbr1_valid)) { | |
9498 | /* The gap between the two regions is a Translation fault */ | |
9499 | fault_type = ARMFault_Translation; | |
9500 | goto do_fault; | |
9501 | } | |
3dde962f PM |
9502 | } |
9503 | ||
ba97be9f RH |
9504 | if (param.using64k) { |
9505 | stride = 13; | |
9506 | } else if (param.using16k) { | |
9507 | stride = 11; | |
9508 | } else { | |
9509 | stride = 9; | |
9510 | } | |
9511 | ||
3dde962f PM |
9512 | /* Note that QEMU ignores shareability and cacheability attributes, |
9513 | * so we don't need to do anything with the SH, ORGN, IRGN fields | |
9514 | * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the | |
9515 | * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently | |
9516 | * implement any ASID-like capability so we can ignore it (instead | |
9517 | * we will always flush the TLB any time the ASID is changed). | |
9518 | */ | |
ba97be9f | 9519 | ttbr = regime_ttbr(env, mmu_idx, param.select); |
3dde962f | 9520 | |
0480f69a | 9521 | /* Here we should have set up all the parameters for the translation: |
6e99f762 | 9522 | * inputsize, ttbr, epd, stride, tbi |
0480f69a PM |
9523 | */ |
9524 | ||
ba97be9f | 9525 | if (param.epd) { |
88e8add8 GB |
9526 | /* Translation table walk disabled => Translation fault on TLB miss |
9527 | * Note: This is always 0 on 64-bit EL2 and EL3. | |
9528 | */ | |
3dde962f PM |
9529 | goto do_fault; |
9530 | } | |
9531 | ||
1853d5a9 EI |
9532 | if (mmu_idx != ARMMMUIdx_S2NS) { |
9533 | /* The starting level depends on the virtual address size (which can | |
9534 | * be up to 48 bits) and the translation granule size. It indicates | |
9535 | * the number of strides (stride bits at a time) needed to | |
9536 | * consume the bits of the input address. In the pseudocode this is: | |
9537 | * level = 4 - RoundUp((inputsize - grainsize) / stride) | |
9538 | * where their 'inputsize' is our 'inputsize', 'grainsize' is | |
9539 | * our 'stride + 3' and 'stride' is our 'stride'. | |
9540 | * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: | |
9541 | * = 4 - (inputsize - stride - 3 + stride - 1) / stride | |
9542 | * = 4 - (inputsize - 4) / stride; | |
9543 | */ | |
9544 | level = 4 - (inputsize - 4) / stride; | |
9545 | } else { | |
9546 | /* For stage 2 translations the starting level is specified by the | |
9547 | * VTCR_EL2.SL0 field (whose interpretation depends on the page size) | |
9548 | */ | |
1b4093ea SS |
9549 | uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2); |
9550 | uint32_t startlevel; | |
1853d5a9 EI |
9551 | bool ok; |
9552 | ||
6e99f762 | 9553 | if (!aarch64 || stride == 9) { |
1853d5a9 | 9554 | /* AArch32 or 4KB pages */ |
1b4093ea | 9555 | startlevel = 2 - sl0; |
1853d5a9 EI |
9556 | } else { |
9557 | /* 16KB or 64KB pages */ | |
1b4093ea | 9558 | startlevel = 3 - sl0; |
1853d5a9 EI |
9559 | } |
9560 | ||
9561 | /* Check that the starting level is valid. */ | |
6e99f762 | 9562 | ok = check_s2_mmu_setup(cpu, aarch64, startlevel, |
1b4093ea | 9563 | inputsize, stride); |
1853d5a9 | 9564 | if (!ok) { |
da909b2c | 9565 | fault_type = ARMFault_Translation; |
1853d5a9 EI |
9566 | goto do_fault; |
9567 | } | |
1b4093ea | 9568 | level = startlevel; |
1853d5a9 | 9569 | } |
3dde962f | 9570 | |
dddb5223 SS |
9571 | indexmask_grainsize = (1ULL << (stride + 3)) - 1; |
9572 | indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1; | |
3dde962f PM |
9573 | |
9574 | /* Now we can extract the actual base address from the TTBR */ | |
2c8dd318 | 9575 | descaddr = extract64(ttbr, 0, 48); |
dddb5223 | 9576 | descaddr &= ~indexmask; |
3dde962f | 9577 | |
6109769a | 9578 | /* The address field in the descriptor goes up to bit 39 for ARMv7 |
dddb5223 SS |
9579 | * but up to bit 47 for ARMv8, but we use the descaddrmask |
9580 | * up to bit 39 for AArch32, because we don't need other bits in that case | |
9581 | * to construct next descriptor address (anyway they should be all zeroes). | |
6109769a | 9582 | */ |
6e99f762 | 9583 | descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) & |
dddb5223 | 9584 | ~indexmask_grainsize; |
6109769a | 9585 | |
ebca90e4 PM |
9586 | /* Secure accesses start with the page table in secure memory and |
9587 | * can be downgraded to non-secure at any step. Non-secure accesses | |
9588 | * remain non-secure. We implement this by just ORing in the NSTable/NS | |
9589 | * bits at each step. | |
9590 | */ | |
9591 | tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); | |
3dde962f PM |
9592 | for (;;) { |
9593 | uint64_t descriptor; | |
ebca90e4 | 9594 | bool nstable; |
3dde962f | 9595 | |
dddb5223 | 9596 | descaddr |= (address >> (stride * (4 - level))) & indexmask; |
2c8dd318 | 9597 | descaddr &= ~7ULL; |
ebca90e4 | 9598 | nstable = extract32(tableattrs, 4, 1); |
3795a6de | 9599 | descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi); |
3b39d734 | 9600 | if (fi->type != ARMFault_None) { |
37785977 EI |
9601 | goto do_fault; |
9602 | } | |
9603 | ||
3dde962f PM |
9604 | if (!(descriptor & 1) || |
9605 | (!(descriptor & 2) && (level == 3))) { | |
9606 | /* Invalid, or the Reserved level 3 encoding */ | |
9607 | goto do_fault; | |
9608 | } | |
6109769a | 9609 | descaddr = descriptor & descaddrmask; |
3dde962f PM |
9610 | |
9611 | if ((descriptor & 2) && (level < 3)) { | |
037c13c5 | 9612 | /* Table entry. The top five bits are attributes which may |
3dde962f PM |
9613 | * propagate down through lower levels of the table (and |
9614 | * which are all arranged so that 0 means "no effect", so | |
9615 | * we can gather them up by ORing in the bits at each level). | |
9616 | */ | |
9617 | tableattrs |= extract64(descriptor, 59, 5); | |
9618 | level++; | |
dddb5223 | 9619 | indexmask = indexmask_grainsize; |
3dde962f PM |
9620 | continue; |
9621 | } | |
9622 | /* Block entry at level 1 or 2, or page entry at level 3. | |
9623 | * These are basically the same thing, although the number | |
9624 | * of bits we pull in from the vaddr varies. | |
9625 | */ | |
973a5434 | 9626 | page_size = (1ULL << ((stride * (4 - level)) + 3)); |
3dde962f | 9627 | descaddr |= (address & (page_size - 1)); |
6ab1a5ee | 9628 | /* Extract attributes from the descriptor */ |
d615efac IC |
9629 | attrs = extract64(descriptor, 2, 10) |
9630 | | (extract64(descriptor, 52, 12) << 10); | |
6ab1a5ee EI |
9631 | |
9632 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
9633 | /* Stage 2 table descriptors do not include any attribute fields */ | |
9634 | break; | |
9635 | } | |
9636 | /* Merge in attributes from table descriptors */ | |
037c13c5 | 9637 | attrs |= nstable << 3; /* NS */ |
1bafc2ba | 9638 | guarded = extract64(descriptor, 50, 1); /* GP */ |
ba97be9f | 9639 | if (param.hpd) { |
037c13c5 RH |
9640 | /* HPD disables all the table attributes except NSTable. */ |
9641 | break; | |
9642 | } | |
9643 | attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ | |
3dde962f PM |
9644 | /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 |
9645 | * means "force PL1 access only", which means forcing AP[1] to 0. | |
9646 | */ | |
037c13c5 RH |
9647 | attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */ |
9648 | attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */ | |
3dde962f PM |
9649 | break; |
9650 | } | |
9651 | /* Here descaddr is the final physical address, and attributes | |
9652 | * are all in attrs. | |
9653 | */ | |
da909b2c | 9654 | fault_type = ARMFault_AccessFlag; |
3dde962f PM |
9655 | if ((attrs & (1 << 8)) == 0) { |
9656 | /* Access flag */ | |
9657 | goto do_fault; | |
9658 | } | |
d8e052b3 AJ |
9659 | |
9660 | ap = extract32(attrs, 4, 2); | |
d8e052b3 | 9661 | xn = extract32(attrs, 12, 1); |
d8e052b3 | 9662 | |
6ab1a5ee EI |
9663 | if (mmu_idx == ARMMMUIdx_S2NS) { |
9664 | ns = true; | |
9665 | *prot = get_S2prot(env, ap, xn); | |
9666 | } else { | |
9667 | ns = extract32(attrs, 3, 1); | |
9668 | pxn = extract32(attrs, 11, 1); | |
6e99f762 | 9669 | *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); |
6ab1a5ee | 9670 | } |
d8e052b3 | 9671 | |
da909b2c | 9672 | fault_type = ARMFault_Permission; |
d8e052b3 | 9673 | if (!(*prot & (1 << access_type))) { |
3dde962f PM |
9674 | goto do_fault; |
9675 | } | |
3dde962f | 9676 | |
8bf5b6a9 PM |
9677 | if (ns) { |
9678 | /* The NS bit will (as required by the architecture) have no effect if | |
9679 | * the CPU doesn't support TZ or this is a non-secure translation | |
9680 | * regime, because the attribute will already be non-secure. | |
9681 | */ | |
9682 | txattrs->secure = false; | |
9683 | } | |
1bafc2ba RH |
9684 | /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */ |
9685 | if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { | |
9686 | txattrs->target_tlb_bit0 = true; | |
9687 | } | |
5b2d261d AB |
9688 | |
9689 | if (cacheattrs != NULL) { | |
9690 | if (mmu_idx == ARMMMUIdx_S2NS) { | |
9691 | cacheattrs->attrs = convert_stage2_attrs(env, | |
9692 | extract32(attrs, 0, 4)); | |
9693 | } else { | |
9694 | /* Index into MAIR registers for cache attributes */ | |
9695 | uint8_t attrindx = extract32(attrs, 0, 3); | |
9696 | uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; | |
9697 | assert(attrindx <= 7); | |
9698 | cacheattrs->attrs = extract64(mair, attrindx * 8, 8); | |
9699 | } | |
9700 | cacheattrs->shareability = extract32(attrs, 6, 2); | |
9701 | } | |
9702 | ||
3dde962f PM |
9703 | *phys_ptr = descaddr; |
9704 | *page_size_ptr = page_size; | |
b7cc4e82 | 9705 | return false; |
3dde962f PM |
9706 | |
9707 | do_fault: | |
da909b2c PM |
9708 | fi->type = fault_type; |
9709 | fi->level = level; | |
37785977 EI |
9710 | /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ |
9711 | fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS); | |
b7cc4e82 | 9712 | return true; |
3dde962f PM |
9713 | } |
9714 | ||
f6bda88f PC |
9715 | static inline void get_phys_addr_pmsav7_default(CPUARMState *env, |
9716 | ARMMMUIdx mmu_idx, | |
9717 | int32_t address, int *prot) | |
9718 | { | |
3a00d560 MD |
9719 | if (!arm_feature(env, ARM_FEATURE_M)) { |
9720 | *prot = PAGE_READ | PAGE_WRITE; | |
9721 | switch (address) { | |
9722 | case 0xF0000000 ... 0xFFFFFFFF: | |
9723 | if (regime_sctlr(env, mmu_idx) & SCTLR_V) { | |
9724 | /* hivecs execing is ok */ | |
9725 | *prot |= PAGE_EXEC; | |
9726 | } | |
9727 | break; | |
9728 | case 0x00000000 ... 0x7FFFFFFF: | |
f6bda88f | 9729 | *prot |= PAGE_EXEC; |
3a00d560 MD |
9730 | break; |
9731 | } | |
9732 | } else { | |
9733 | /* Default system address map for M profile cores. | |
9734 | * The architecture specifies which regions are execute-never; | |
9735 | * at the MPU level no other checks are defined. | |
9736 | */ | |
9737 | switch (address) { | |
9738 | case 0x00000000 ... 0x1fffffff: /* ROM */ | |
9739 | case 0x20000000 ... 0x3fffffff: /* SRAM */ | |
9740 | case 0x60000000 ... 0x7fffffff: /* RAM */ | |
9741 | case 0x80000000 ... 0x9fffffff: /* RAM */ | |
9742 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
9743 | break; | |
9744 | case 0x40000000 ... 0x5fffffff: /* Peripheral */ | |
9745 | case 0xa0000000 ... 0xbfffffff: /* Device */ | |
9746 | case 0xc0000000 ... 0xdfffffff: /* Device */ | |
9747 | case 0xe0000000 ... 0xffffffff: /* System */ | |
9748 | *prot = PAGE_READ | PAGE_WRITE; | |
9749 | break; | |
9750 | default: | |
9751 | g_assert_not_reached(); | |
f6bda88f | 9752 | } |
f6bda88f | 9753 | } |
f6bda88f PC |
9754 | } |
9755 | ||
29c483a5 MD |
9756 | static bool pmsav7_use_background_region(ARMCPU *cpu, |
9757 | ARMMMUIdx mmu_idx, bool is_user) | |
9758 | { | |
9759 | /* Return true if we should use the default memory map as a | |
9760 | * "background" region if there are no hits against any MPU regions. | |
9761 | */ | |
9762 | CPUARMState *env = &cpu->env; | |
9763 | ||
9764 | if (is_user) { | |
9765 | return false; | |
9766 | } | |
9767 | ||
9768 | if (arm_feature(env, ARM_FEATURE_M)) { | |
ecf5e8ea PM |
9769 | return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] |
9770 | & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; | |
29c483a5 MD |
9771 | } else { |
9772 | return regime_sctlr(env, mmu_idx) & SCTLR_BR; | |
9773 | } | |
9774 | } | |
9775 | ||
38aaa60c PM |
9776 | static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address) |
9777 | { | |
9778 | /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */ | |
9779 | return arm_feature(env, ARM_FEATURE_M) && | |
9780 | extract32(address, 20, 12) == 0xe00; | |
9781 | } | |
9782 | ||
bf446a11 PM |
9783 | static inline bool m_is_system_region(CPUARMState *env, uint32_t address) |
9784 | { | |
9785 | /* True if address is in the M profile system region | |
9786 | * 0xe0000000 - 0xffffffff | |
9787 | */ | |
9788 | return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7; | |
9789 | } | |
9790 | ||
f6bda88f | 9791 | static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, |
03ae85f8 | 9792 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
9375ad15 | 9793 | hwaddr *phys_ptr, int *prot, |
e5e40999 | 9794 | target_ulong *page_size, |
9375ad15 | 9795 | ARMMMUFaultInfo *fi) |
f6bda88f | 9796 | { |
2fc0cc0e | 9797 | ARMCPU *cpu = env_archcpu(env); |
f6bda88f PC |
9798 | int n; |
9799 | bool is_user = regime_is_user(env, mmu_idx); | |
9800 | ||
9801 | *phys_ptr = address; | |
e5e40999 | 9802 | *page_size = TARGET_PAGE_SIZE; |
f6bda88f PC |
9803 | *prot = 0; |
9804 | ||
38aaa60c PM |
9805 | if (regime_translation_disabled(env, mmu_idx) || |
9806 | m_is_ppb_region(env, address)) { | |
9807 | /* MPU disabled or M profile PPB access: use default memory map. | |
9808 | * The other case which uses the default memory map in the | |
9809 | * v7M ARM ARM pseudocode is exception vector reads from the vector | |
9810 | * table. In QEMU those accesses are done in arm_v7m_load_vector(), | |
9811 | * which always does a direct read using address_space_ldl(), rather | |
9812 | * than going via this function, so we don't need to check that here. | |
9813 | */ | |
f6bda88f PC |
9814 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); |
9815 | } else { /* MPU enabled */ | |
9816 | for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { | |
9817 | /* region search */ | |
9818 | uint32_t base = env->pmsav7.drbar[n]; | |
9819 | uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5); | |
9820 | uint32_t rmask; | |
9821 | bool srdis = false; | |
9822 | ||
9823 | if (!(env->pmsav7.drsr[n] & 0x1)) { | |
9824 | continue; | |
9825 | } | |
9826 | ||
9827 | if (!rsize) { | |
c9f9f124 MD |
9828 | qemu_log_mask(LOG_GUEST_ERROR, |
9829 | "DRSR[%d]: Rsize field cannot be 0\n", n); | |
f6bda88f PC |
9830 | continue; |
9831 | } | |
9832 | rsize++; | |
9833 | rmask = (1ull << rsize) - 1; | |
9834 | ||
9835 | if (base & rmask) { | |
c9f9f124 MD |
9836 | qemu_log_mask(LOG_GUEST_ERROR, |
9837 | "DRBAR[%d]: 0x%" PRIx32 " misaligned " | |
9838 | "to DRSR region size, mask = 0x%" PRIx32 "\n", | |
9839 | n, base, rmask); | |
f6bda88f PC |
9840 | continue; |
9841 | } | |
9842 | ||
9843 | if (address < base || address > base + rmask) { | |
9d2b5a58 PM |
9844 | /* |
9845 | * Address not in this region. We must check whether the | |
9846 | * region covers addresses in the same page as our address. | |
9847 | * In that case we must not report a size that covers the | |
9848 | * whole page for a subsequent hit against a different MPU | |
9849 | * region or the background region, because it would result in | |
9850 | * incorrect TLB hits for subsequent accesses to addresses that | |
9851 | * are in this MPU region. | |
9852 | */ | |
9853 | if (ranges_overlap(base, rmask, | |
9854 | address & TARGET_PAGE_MASK, | |
9855 | TARGET_PAGE_SIZE)) { | |
9856 | *page_size = 1; | |
9857 | } | |
f6bda88f PC |
9858 | continue; |
9859 | } | |
9860 | ||
9861 | /* Region matched */ | |
9862 | ||
9863 | if (rsize >= 8) { /* no subregions for regions < 256 bytes */ | |
9864 | int i, snd; | |
9865 | uint32_t srdis_mask; | |
9866 | ||
9867 | rsize -= 3; /* sub region size (power of 2) */ | |
9868 | snd = ((address - base) >> rsize) & 0x7; | |
9869 | srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1); | |
9870 | ||
9871 | srdis_mask = srdis ? 0x3 : 0x0; | |
9872 | for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) { | |
9873 | /* This will check in groups of 2, 4 and then 8, whether | |
9874 | * the subregion bits are consistent. rsize is incremented | |
9875 | * back up to give the region size, considering consistent | |
9876 | * adjacent subregions as one region. Stop testing if rsize | |
9877 | * is already big enough for an entire QEMU page. | |
9878 | */ | |
9879 | int snd_rounded = snd & ~(i - 1); | |
9880 | uint32_t srdis_multi = extract32(env->pmsav7.drsr[n], | |
9881 | snd_rounded + 8, i); | |
9882 | if (srdis_mask ^ srdis_multi) { | |
9883 | break; | |
9884 | } | |
9885 | srdis_mask = (srdis_mask << i) | srdis_mask; | |
9886 | rsize++; | |
9887 | } | |
9888 | } | |
f6bda88f PC |
9889 | if (srdis) { |
9890 | continue; | |
9891 | } | |
e5e40999 PM |
9892 | if (rsize < TARGET_PAGE_BITS) { |
9893 | *page_size = 1 << rsize; | |
9894 | } | |
f6bda88f PC |
9895 | break; |
9896 | } | |
9897 | ||
9898 | if (n == -1) { /* no hits */ | |
29c483a5 | 9899 | if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { |
f6bda88f | 9900 | /* background fault */ |
9375ad15 | 9901 | fi->type = ARMFault_Background; |
f6bda88f PC |
9902 | return true; |
9903 | } | |
9904 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | |
9905 | } else { /* a MPU hit! */ | |
9906 | uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); | |
bf446a11 PM |
9907 | uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1); |
9908 | ||
9909 | if (m_is_system_region(env, address)) { | |
9910 | /* System space is always execute never */ | |
9911 | xn = 1; | |
9912 | } | |
f6bda88f PC |
9913 | |
9914 | if (is_user) { /* User mode AP bit decoding */ | |
9915 | switch (ap) { | |
9916 | case 0: | |
9917 | case 1: | |
9918 | case 5: | |
9919 | break; /* no access */ | |
9920 | case 3: | |
9921 | *prot |= PAGE_WRITE; | |
9922 | /* fall through */ | |
9923 | case 2: | |
9924 | case 6: | |
9925 | *prot |= PAGE_READ | PAGE_EXEC; | |
9926 | break; | |
8638f1ad PM |
9927 | case 7: |
9928 | /* for v7M, same as 6; for R profile a reserved value */ | |
9929 | if (arm_feature(env, ARM_FEATURE_M)) { | |
9930 | *prot |= PAGE_READ | PAGE_EXEC; | |
9931 | break; | |
9932 | } | |
9933 | /* fall through */ | |
f6bda88f PC |
9934 | default: |
9935 | qemu_log_mask(LOG_GUEST_ERROR, | |
c9f9f124 MD |
9936 | "DRACR[%d]: Bad value for AP bits: 0x%" |
9937 | PRIx32 "\n", n, ap); | |
f6bda88f PC |
9938 | } |
9939 | } else { /* Priv. mode AP bits decoding */ | |
9940 | switch (ap) { | |
9941 | case 0: | |
9942 | break; /* no access */ | |
9943 | case 1: | |
9944 | case 2: | |
9945 | case 3: | |
9946 | *prot |= PAGE_WRITE; | |
9947 | /* fall through */ | |
9948 | case 5: | |
9949 | case 6: | |
9950 | *prot |= PAGE_READ | PAGE_EXEC; | |
9951 | break; | |
8638f1ad PM |
9952 | case 7: |
9953 | /* for v7M, same as 6; for R profile a reserved value */ | |
9954 | if (arm_feature(env, ARM_FEATURE_M)) { | |
9955 | *prot |= PAGE_READ | PAGE_EXEC; | |
9956 | break; | |
9957 | } | |
9958 | /* fall through */ | |
f6bda88f PC |
9959 | default: |
9960 | qemu_log_mask(LOG_GUEST_ERROR, | |
c9f9f124 MD |
9961 | "DRACR[%d]: Bad value for AP bits: 0x%" |
9962 | PRIx32 "\n", n, ap); | |
f6bda88f PC |
9963 | } |
9964 | } | |
9965 | ||
9966 | /* execute never */ | |
bf446a11 | 9967 | if (xn) { |
f6bda88f PC |
9968 | *prot &= ~PAGE_EXEC; |
9969 | } | |
9970 | } | |
9971 | } | |
9972 | ||
9375ad15 PM |
9973 | fi->type = ARMFault_Permission; |
9974 | fi->level = 1; | |
f6bda88f PC |
9975 | return !(*prot & (1 << access_type)); |
9976 | } | |
9977 | ||
35337cc3 PM |
9978 | static bool v8m_is_sau_exempt(CPUARMState *env, |
9979 | uint32_t address, MMUAccessType access_type) | |
9980 | { | |
9981 | /* The architecture specifies that certain address ranges are | |
9982 | * exempt from v8M SAU/IDAU checks. | |
9983 | */ | |
9984 | return | |
9985 | (access_type == MMU_INST_FETCH && m_is_system_region(env, address)) || | |
9986 | (address >= 0xe0000000 && address <= 0xe0002fff) || | |
9987 | (address >= 0xe000e000 && address <= 0xe000efff) || | |
9988 | (address >= 0xe002e000 && address <= 0xe002efff) || | |
9989 | (address >= 0xe0040000 && address <= 0xe0041fff) || | |
9990 | (address >= 0xe00ff000 && address <= 0xe00fffff); | |
9991 | } | |
9992 | ||
787a7e76 | 9993 | void v8m_security_lookup(CPUARMState *env, uint32_t address, |
35337cc3 PM |
9994 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
9995 | V8M_SAttributes *sattrs) | |
9996 | { | |
9997 | /* Look up the security attributes for this address. Compare the | |
9998 | * pseudocode SecurityCheck() function. | |
9999 | * We assume the caller has zero-initialized *sattrs. | |
10000 | */ | |
2fc0cc0e | 10001 | ARMCPU *cpu = env_archcpu(env); |
35337cc3 | 10002 | int r; |
181962fd PM |
10003 | bool idau_exempt = false, idau_ns = true, idau_nsc = true; |
10004 | int idau_region = IREGION_NOTVALID; | |
72042435 PM |
10005 | uint32_t addr_page_base = address & TARGET_PAGE_MASK; |
10006 | uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); | |
35337cc3 | 10007 | |
181962fd PM |
10008 | if (cpu->idau) { |
10009 | IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau); | |
10010 | IDAUInterface *ii = IDAU_INTERFACE(cpu->idau); | |
10011 | ||
10012 | iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns, | |
10013 | &idau_nsc); | |
10014 | } | |
35337cc3 PM |
10015 | |
10016 | if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) { | |
10017 | /* 0xf0000000..0xffffffff is always S for insn fetches */ | |
10018 | return; | |
10019 | } | |
10020 | ||
181962fd | 10021 | if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) { |
35337cc3 PM |
10022 | sattrs->ns = !regime_is_secure(env, mmu_idx); |
10023 | return; | |
10024 | } | |
10025 | ||
181962fd PM |
10026 | if (idau_region != IREGION_NOTVALID) { |
10027 | sattrs->irvalid = true; | |
10028 | sattrs->iregion = idau_region; | |
10029 | } | |
10030 | ||
35337cc3 PM |
10031 | switch (env->sau.ctrl & 3) { |
10032 | case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */ | |
10033 | break; | |
10034 | case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */ | |
10035 | sattrs->ns = true; | |
10036 | break; | |
10037 | default: /* SAU.ENABLE == 1 */ | |
10038 | for (r = 0; r < cpu->sau_sregion; r++) { | |
10039 | if (env->sau.rlar[r] & 1) { | |
10040 | uint32_t base = env->sau.rbar[r] & ~0x1f; | |
10041 | uint32_t limit = env->sau.rlar[r] | 0x1f; | |
10042 | ||
10043 | if (base <= address && limit >= address) { | |
72042435 PM |
10044 | if (base > addr_page_base || limit < addr_page_limit) { |
10045 | sattrs->subpage = true; | |
10046 | } | |
35337cc3 PM |
10047 | if (sattrs->srvalid) { |
10048 | /* If we hit in more than one region then we must report | |
10049 | * as Secure, not NS-Callable, with no valid region | |
10050 | * number info. | |
10051 | */ | |
10052 | sattrs->ns = false; | |
10053 | sattrs->nsc = false; | |
10054 | sattrs->sregion = 0; | |
10055 | sattrs->srvalid = false; | |
10056 | break; | |
10057 | } else { | |
10058 | if (env->sau.rlar[r] & 2) { | |
10059 | sattrs->nsc = true; | |
10060 | } else { | |
10061 | sattrs->ns = true; | |
10062 | } | |
10063 | sattrs->srvalid = true; | |
10064 | sattrs->sregion = r; | |
10065 | } | |
9d2b5a58 PM |
10066 | } else { |
10067 | /* | |
10068 | * Address not in this region. We must check whether the | |
10069 | * region covers addresses in the same page as our address. | |
10070 | * In that case we must not report a size that covers the | |
10071 | * whole page for a subsequent hit against a different MPU | |
10072 | * region or the background region, because it would result | |
10073 | * in incorrect TLB hits for subsequent accesses to | |
10074 | * addresses that are in this MPU region. | |
10075 | */ | |
10076 | if (limit >= base && | |
10077 | ranges_overlap(base, limit - base + 1, | |
10078 | addr_page_base, | |
10079 | TARGET_PAGE_SIZE)) { | |
10080 | sattrs->subpage = true; | |
10081 | } | |
35337cc3 PM |
10082 | } |
10083 | } | |
10084 | } | |
7e3f1223 TR |
10085 | break; |
10086 | } | |
35337cc3 | 10087 | |
7e3f1223 TR |
10088 | /* |
10089 | * The IDAU will override the SAU lookup results if it specifies | |
10090 | * higher security than the SAU does. | |
10091 | */ | |
10092 | if (!idau_ns) { | |
10093 | if (sattrs->ns || (!idau_nsc && sattrs->nsc)) { | |
10094 | sattrs->ns = false; | |
10095 | sattrs->nsc = idau_nsc; | |
181962fd | 10096 | } |
35337cc3 PM |
10097 | } |
10098 | } | |
10099 | ||
787a7e76 | 10100 | bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, |
54317c0f PM |
10101 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
10102 | hwaddr *phys_ptr, MemTxAttrs *txattrs, | |
72042435 PM |
10103 | int *prot, bool *is_subpage, |
10104 | ARMMMUFaultInfo *fi, uint32_t *mregion) | |
54317c0f PM |
10105 | { |
10106 | /* Perform a PMSAv8 MPU lookup (without also doing the SAU check | |
10107 | * that a full phys-to-virt translation does). | |
10108 | * mregion is (if not NULL) set to the region number which matched, | |
10109 | * or -1 if no region number is returned (MPU off, address did not | |
10110 | * hit a region, address hit in multiple regions). | |
72042435 PM |
10111 | * We set is_subpage to true if the region hit doesn't cover the |
10112 | * entire TARGET_PAGE the address is within. | |
54317c0f | 10113 | */ |
2fc0cc0e | 10114 | ARMCPU *cpu = env_archcpu(env); |
504e3cc3 | 10115 | bool is_user = regime_is_user(env, mmu_idx); |
62c58ee0 | 10116 | uint32_t secure = regime_is_secure(env, mmu_idx); |
504e3cc3 PM |
10117 | int n; |
10118 | int matchregion = -1; | |
10119 | bool hit = false; | |
72042435 PM |
10120 | uint32_t addr_page_base = address & TARGET_PAGE_MASK; |
10121 | uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1); | |
504e3cc3 | 10122 | |
72042435 | 10123 | *is_subpage = false; |
504e3cc3 PM |
10124 | *phys_ptr = address; |
10125 | *prot = 0; | |
54317c0f PM |
10126 | if (mregion) { |
10127 | *mregion = -1; | |
35337cc3 PM |
10128 | } |
10129 | ||
504e3cc3 PM |
10130 | /* Unlike the ARM ARM pseudocode, we don't need to check whether this |
10131 | * was an exception vector read from the vector table (which is always | |
10132 | * done using the default system address map), because those accesses | |
10133 | * are done in arm_v7m_load_vector(), which always does a direct | |
10134 | * read using address_space_ldl(), rather than going via this function. | |
10135 | */ | |
10136 | if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ | |
10137 | hit = true; | |
10138 | } else if (m_is_ppb_region(env, address)) { | |
10139 | hit = true; | |
504e3cc3 | 10140 | } else { |
cff21316 PM |
10141 | if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) { |
10142 | hit = true; | |
10143 | } | |
10144 | ||
504e3cc3 PM |
10145 | for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) { |
10146 | /* region search */ | |
10147 | /* Note that the base address is bits [31:5] from the register | |
10148 | * with bits [4:0] all zeroes, but the limit address is bits | |
10149 | * [31:5] from the register with bits [4:0] all ones. | |
10150 | */ | |
62c58ee0 PM |
10151 | uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f; |
10152 | uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f; | |
504e3cc3 | 10153 | |
62c58ee0 | 10154 | if (!(env->pmsav8.rlar[secure][n] & 0x1)) { |
504e3cc3 PM |
10155 | /* Region disabled */ |
10156 | continue; | |
10157 | } | |
10158 | ||
10159 | if (address < base || address > limit) { | |
9d2b5a58 PM |
10160 | /* |
10161 | * Address not in this region. We must check whether the | |
10162 | * region covers addresses in the same page as our address. | |
10163 | * In that case we must not report a size that covers the | |
10164 | * whole page for a subsequent hit against a different MPU | |
10165 | * region or the background region, because it would result in | |
10166 | * incorrect TLB hits for subsequent accesses to addresses that | |
10167 | * are in this MPU region. | |
10168 | */ | |
10169 | if (limit >= base && | |
10170 | ranges_overlap(base, limit - base + 1, | |
10171 | addr_page_base, | |
10172 | TARGET_PAGE_SIZE)) { | |
10173 | *is_subpage = true; | |
10174 | } | |
504e3cc3 PM |
10175 | continue; |
10176 | } | |
10177 | ||
72042435 PM |
10178 | if (base > addr_page_base || limit < addr_page_limit) { |
10179 | *is_subpage = true; | |
10180 | } | |
10181 | ||
cff21316 | 10182 | if (matchregion != -1) { |
504e3cc3 PM |
10183 | /* Multiple regions match -- always a failure (unlike |
10184 | * PMSAv7 where highest-numbered-region wins) | |
10185 | */ | |
3f551b5b PM |
10186 | fi->type = ARMFault_Permission; |
10187 | fi->level = 1; | |
504e3cc3 PM |
10188 | return true; |
10189 | } | |
10190 | ||
10191 | matchregion = n; | |
10192 | hit = true; | |
504e3cc3 PM |
10193 | } |
10194 | } | |
10195 | ||
10196 | if (!hit) { | |
10197 | /* background fault */ | |
3f551b5b | 10198 | fi->type = ARMFault_Background; |
504e3cc3 PM |
10199 | return true; |
10200 | } | |
10201 | ||
10202 | if (matchregion == -1) { | |
10203 | /* hit using the background region */ | |
10204 | get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); | |
10205 | } else { | |
62c58ee0 PM |
10206 | uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2); |
10207 | uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1); | |
504e3cc3 PM |
10208 | |
10209 | if (m_is_system_region(env, address)) { | |
10210 | /* System space is always execute never */ | |
10211 | xn = 1; | |
10212 | } | |
10213 | ||
10214 | *prot = simple_ap_to_rw_prot(env, mmu_idx, ap); | |
10215 | if (*prot && !xn) { | |
10216 | *prot |= PAGE_EXEC; | |
10217 | } | |
10218 | /* We don't need to look the attribute up in the MAIR0/MAIR1 | |
10219 | * registers because that only tells us about cacheability. | |
10220 | */ | |
54317c0f PM |
10221 | if (mregion) { |
10222 | *mregion = matchregion; | |
10223 | } | |
504e3cc3 PM |
10224 | } |
10225 | ||
3f551b5b PM |
10226 | fi->type = ARMFault_Permission; |
10227 | fi->level = 1; | |
504e3cc3 PM |
10228 | return !(*prot & (1 << access_type)); |
10229 | } | |
10230 | ||
54317c0f PM |
10231 | |
10232 | static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, | |
10233 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
10234 | hwaddr *phys_ptr, MemTxAttrs *txattrs, | |
72042435 PM |
10235 | int *prot, target_ulong *page_size, |
10236 | ARMMMUFaultInfo *fi) | |
54317c0f PM |
10237 | { |
10238 | uint32_t secure = regime_is_secure(env, mmu_idx); | |
10239 | V8M_SAttributes sattrs = {}; | |
72042435 PM |
10240 | bool ret; |
10241 | bool mpu_is_subpage; | |
54317c0f PM |
10242 | |
10243 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | |
10244 | v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs); | |
10245 | if (access_type == MMU_INST_FETCH) { | |
10246 | /* Instruction fetches always use the MMU bank and the | |
10247 | * transaction attribute determined by the fetch address, | |
10248 | * regardless of CPU state. This is painful for QEMU | |
10249 | * to handle, because it would mean we need to encode | |
10250 | * into the mmu_idx not just the (user, negpri) information | |
10251 | * for the current security state but also that for the | |
10252 | * other security state, which would balloon the number | |
10253 | * of mmu_idx values needed alarmingly. | |
10254 | * Fortunately we can avoid this because it's not actually | |
10255 | * possible to arbitrarily execute code from memory with | |
10256 | * the wrong security attribute: it will always generate | |
10257 | * an exception of some kind or another, apart from the | |
10258 | * special case of an NS CPU executing an SG instruction | |
10259 | * in S&NSC memory. So we always just fail the translation | |
10260 | * here and sort things out in the exception handler | |
10261 | * (including possibly emulating an SG instruction). | |
10262 | */ | |
10263 | if (sattrs.ns != !secure) { | |
3f551b5b PM |
10264 | if (sattrs.nsc) { |
10265 | fi->type = ARMFault_QEMU_NSCExec; | |
10266 | } else { | |
10267 | fi->type = ARMFault_QEMU_SFault; | |
10268 | } | |
72042435 | 10269 | *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; |
54317c0f PM |
10270 | *phys_ptr = address; |
10271 | *prot = 0; | |
10272 | return true; | |
10273 | } | |
10274 | } else { | |
10275 | /* For data accesses we always use the MMU bank indicated | |
10276 | * by the current CPU state, but the security attributes | |
10277 | * might downgrade a secure access to nonsecure. | |
10278 | */ | |
10279 | if (sattrs.ns) { | |
10280 | txattrs->secure = false; | |
10281 | } else if (!secure) { | |
10282 | /* NS access to S memory must fault. | |
10283 | * Architecturally we should first check whether the | |
10284 | * MPU information for this address indicates that we | |
10285 | * are doing an unaligned access to Device memory, which | |
10286 | * should generate a UsageFault instead. QEMU does not | |
10287 | * currently check for that kind of unaligned access though. | |
10288 | * If we added it we would need to do so as a special case | |
10289 | * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). | |
10290 | */ | |
3f551b5b | 10291 | fi->type = ARMFault_QEMU_SFault; |
72042435 | 10292 | *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE; |
54317c0f PM |
10293 | *phys_ptr = address; |
10294 | *prot = 0; | |
10295 | return true; | |
10296 | } | |
10297 | } | |
10298 | } | |
10299 | ||
72042435 PM |
10300 | ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, |
10301 | txattrs, prot, &mpu_is_subpage, fi, NULL); | |
72042435 PM |
10302 | *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; |
10303 | return ret; | |
54317c0f PM |
10304 | } |
10305 | ||
13689d43 | 10306 | static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, |
03ae85f8 | 10307 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
53a4e5c5 PM |
10308 | hwaddr *phys_ptr, int *prot, |
10309 | ARMMMUFaultInfo *fi) | |
9ee6e8bb PB |
10310 | { |
10311 | int n; | |
10312 | uint32_t mask; | |
10313 | uint32_t base; | |
0480f69a | 10314 | bool is_user = regime_is_user(env, mmu_idx); |
9ee6e8bb | 10315 | |
3279adb9 PM |
10316 | if (regime_translation_disabled(env, mmu_idx)) { |
10317 | /* MPU disabled. */ | |
10318 | *phys_ptr = address; | |
10319 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
10320 | return false; | |
10321 | } | |
10322 | ||
9ee6e8bb PB |
10323 | *phys_ptr = address; |
10324 | for (n = 7; n >= 0; n--) { | |
554b0b09 | 10325 | base = env->cp15.c6_region[n]; |
87c3d486 | 10326 | if ((base & 1) == 0) { |
554b0b09 | 10327 | continue; |
87c3d486 | 10328 | } |
554b0b09 PM |
10329 | mask = 1 << ((base >> 1) & 0x1f); |
10330 | /* Keep this shift separate from the above to avoid an | |
10331 | (undefined) << 32. */ | |
10332 | mask = (mask << 1) - 1; | |
87c3d486 | 10333 | if (((base ^ address) & ~mask) == 0) { |
554b0b09 | 10334 | break; |
87c3d486 | 10335 | } |
9ee6e8bb | 10336 | } |
87c3d486 | 10337 | if (n < 0) { |
53a4e5c5 | 10338 | fi->type = ARMFault_Background; |
b7cc4e82 | 10339 | return true; |
87c3d486 | 10340 | } |
9ee6e8bb | 10341 | |
03ae85f8 | 10342 | if (access_type == MMU_INST_FETCH) { |
7e09797c | 10343 | mask = env->cp15.pmsav5_insn_ap; |
9ee6e8bb | 10344 | } else { |
7e09797c | 10345 | mask = env->cp15.pmsav5_data_ap; |
9ee6e8bb PB |
10346 | } |
10347 | mask = (mask >> (n * 4)) & 0xf; | |
10348 | switch (mask) { | |
10349 | case 0: | |
53a4e5c5 PM |
10350 | fi->type = ARMFault_Permission; |
10351 | fi->level = 1; | |
b7cc4e82 | 10352 | return true; |
9ee6e8bb | 10353 | case 1: |
87c3d486 | 10354 | if (is_user) { |
53a4e5c5 PM |
10355 | fi->type = ARMFault_Permission; |
10356 | fi->level = 1; | |
b7cc4e82 | 10357 | return true; |
87c3d486 | 10358 | } |
554b0b09 PM |
10359 | *prot = PAGE_READ | PAGE_WRITE; |
10360 | break; | |
9ee6e8bb | 10361 | case 2: |
554b0b09 | 10362 | *prot = PAGE_READ; |
87c3d486 | 10363 | if (!is_user) { |
554b0b09 | 10364 | *prot |= PAGE_WRITE; |
87c3d486 | 10365 | } |
554b0b09 | 10366 | break; |
9ee6e8bb | 10367 | case 3: |
554b0b09 PM |
10368 | *prot = PAGE_READ | PAGE_WRITE; |
10369 | break; | |
9ee6e8bb | 10370 | case 5: |
87c3d486 | 10371 | if (is_user) { |
53a4e5c5 PM |
10372 | fi->type = ARMFault_Permission; |
10373 | fi->level = 1; | |
b7cc4e82 | 10374 | return true; |
87c3d486 | 10375 | } |
554b0b09 PM |
10376 | *prot = PAGE_READ; |
10377 | break; | |
9ee6e8bb | 10378 | case 6: |
554b0b09 PM |
10379 | *prot = PAGE_READ; |
10380 | break; | |
9ee6e8bb | 10381 | default: |
554b0b09 | 10382 | /* Bad permission. */ |
53a4e5c5 PM |
10383 | fi->type = ARMFault_Permission; |
10384 | fi->level = 1; | |
b7cc4e82 | 10385 | return true; |
9ee6e8bb | 10386 | } |
3ad493fc | 10387 | *prot |= PAGE_EXEC; |
b7cc4e82 | 10388 | return false; |
9ee6e8bb PB |
10389 | } |
10390 | ||
5b2d261d AB |
10391 | /* Combine either inner or outer cacheability attributes for normal |
10392 | * memory, according to table D4-42 and pseudocode procedure | |
10393 | * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). | |
10394 | * | |
10395 | * NB: only stage 1 includes allocation hints (RW bits), leading to | |
10396 | * some asymmetry. | |
10397 | */ | |
10398 | static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2) | |
10399 | { | |
10400 | if (s1 == 4 || s2 == 4) { | |
10401 | /* non-cacheable has precedence */ | |
10402 | return 4; | |
10403 | } else if (extract32(s1, 2, 2) == 0 || extract32(s1, 2, 2) == 2) { | |
10404 | /* stage 1 write-through takes precedence */ | |
10405 | return s1; | |
10406 | } else if (extract32(s2, 2, 2) == 2) { | |
10407 | /* stage 2 write-through takes precedence, but the allocation hint | |
10408 | * is still taken from stage 1 | |
10409 | */ | |
10410 | return (2 << 2) | extract32(s1, 0, 2); | |
10411 | } else { /* write-back */ | |
10412 | return s1; | |
10413 | } | |
10414 | } | |
10415 | ||
10416 | /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 | |
10417 | * and CombineS1S2Desc() | |
10418 | * | |
10419 | * @s1: Attributes from stage 1 walk | |
10420 | * @s2: Attributes from stage 2 walk | |
10421 | */ | |
10422 | static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) | |
10423 | { | |
10424 | uint8_t s1lo = extract32(s1.attrs, 0, 4), s2lo = extract32(s2.attrs, 0, 4); | |
10425 | uint8_t s1hi = extract32(s1.attrs, 4, 4), s2hi = extract32(s2.attrs, 4, 4); | |
10426 | ARMCacheAttrs ret; | |
10427 | ||
10428 | /* Combine shareability attributes (table D4-43) */ | |
10429 | if (s1.shareability == 2 || s2.shareability == 2) { | |
10430 | /* if either are outer-shareable, the result is outer-shareable */ | |
10431 | ret.shareability = 2; | |
10432 | } else if (s1.shareability == 3 || s2.shareability == 3) { | |
10433 | /* if either are inner-shareable, the result is inner-shareable */ | |
10434 | ret.shareability = 3; | |
10435 | } else { | |
10436 | /* both non-shareable */ | |
10437 | ret.shareability = 0; | |
10438 | } | |
10439 | ||
10440 | /* Combine memory type and cacheability attributes */ | |
10441 | if (s1hi == 0 || s2hi == 0) { | |
10442 | /* Device has precedence over normal */ | |
10443 | if (s1lo == 0 || s2lo == 0) { | |
10444 | /* nGnRnE has precedence over anything */ | |
10445 | ret.attrs = 0; | |
10446 | } else if (s1lo == 4 || s2lo == 4) { | |
10447 | /* non-Reordering has precedence over Reordering */ | |
10448 | ret.attrs = 4; /* nGnRE */ | |
10449 | } else if (s1lo == 8 || s2lo == 8) { | |
10450 | /* non-Gathering has precedence over Gathering */ | |
10451 | ret.attrs = 8; /* nGRE */ | |
10452 | } else { | |
10453 | ret.attrs = 0xc; /* GRE */ | |
10454 | } | |
10455 | ||
10456 | /* Any location for which the resultant memory type is any | |
10457 | * type of Device memory is always treated as Outer Shareable. | |
10458 | */ | |
10459 | ret.shareability = 2; | |
10460 | } else { /* Normal memory */ | |
10461 | /* Outer/inner cacheability combine independently */ | |
10462 | ret.attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4 | |
10463 | | combine_cacheattr_nibble(s1lo, s2lo); | |
10464 | ||
10465 | if (ret.attrs == 0x44) { | |
10466 | /* Any location for which the resultant memory type is Normal | |
10467 | * Inner Non-cacheable, Outer Non-cacheable is always treated | |
10468 | * as Outer Shareable. | |
10469 | */ | |
10470 | ret.shareability = 2; | |
10471 | } | |
10472 | } | |
10473 | ||
10474 | return ret; | |
10475 | } | |
10476 | ||
10477 | ||
702a9357 PM |
10478 | /* get_phys_addr - get the physical address for this virtual address |
10479 | * | |
10480 | * Find the physical address corresponding to the given virtual address, | |
10481 | * by doing a translation table walk on MMU based systems or using the | |
10482 | * MPU state on MPU based systems. | |
10483 | * | |
b7cc4e82 PC |
10484 | * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, |
10485 | * prot and page_size may not be filled in, and the populated fsr value provides | |
702a9357 PM |
10486 | * information on why the translation aborted, in the format of a |
10487 | * DFSR/IFSR fault register, with the following caveats: | |
10488 | * * we honour the short vs long DFSR format differences. | |
10489 | * * the WnR bit is never set (the caller must do this). | |
f6bda88f | 10490 | * * for PSMAv5 based systems we don't bother to return a full FSR format |
702a9357 PM |
10491 | * value. |
10492 | * | |
10493 | * @env: CPUARMState | |
10494 | * @address: virtual address to get physical address for | |
10495 | * @access_type: 0 for read, 1 for write, 2 for execute | |
d3649702 | 10496 | * @mmu_idx: MMU index indicating required translation regime |
702a9357 | 10497 | * @phys_ptr: set to the physical address corresponding to the virtual address |
8bf5b6a9 | 10498 | * @attrs: set to the memory transaction attributes to use |
702a9357 PM |
10499 | * @prot: set to the permissions for the page containing phys_ptr |
10500 | * @page_size: set to the size of the page containing phys_ptr | |
5b2d261d AB |
10501 | * @fi: set to fault info if the translation fails |
10502 | * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes | |
702a9357 | 10503 | */ |
ebae861f PMD |
10504 | bool get_phys_addr(CPUARMState *env, target_ulong address, |
10505 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
10506 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, | |
10507 | target_ulong *page_size, | |
10508 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) | |
9ee6e8bb | 10509 | { |
0480f69a | 10510 | if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { |
9b539263 EI |
10511 | /* Call ourselves recursively to do the stage 1 and then stage 2 |
10512 | * translations. | |
0480f69a | 10513 | */ |
9b539263 EI |
10514 | if (arm_feature(env, ARM_FEATURE_EL2)) { |
10515 | hwaddr ipa; | |
10516 | int s2_prot; | |
10517 | int ret; | |
5b2d261d | 10518 | ARMCacheAttrs cacheattrs2 = {}; |
9b539263 EI |
10519 | |
10520 | ret = get_phys_addr(env, address, access_type, | |
8bd5c820 | 10521 | stage_1_mmu_idx(mmu_idx), &ipa, attrs, |
bc52bfeb | 10522 | prot, page_size, fi, cacheattrs); |
9b539263 EI |
10523 | |
10524 | /* If S1 fails or S2 is disabled, return early. */ | |
10525 | if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { | |
10526 | *phys_ptr = ipa; | |
10527 | return ret; | |
10528 | } | |
10529 | ||
10530 | /* S1 is done. Now do S2 translation. */ | |
10531 | ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS, | |
10532 | phys_ptr, attrs, &s2_prot, | |
da909b2c | 10533 | page_size, fi, |
5b2d261d | 10534 | cacheattrs != NULL ? &cacheattrs2 : NULL); |
9b539263 EI |
10535 | fi->s2addr = ipa; |
10536 | /* Combine the S1 and S2 perms. */ | |
10537 | *prot &= s2_prot; | |
5b2d261d AB |
10538 | |
10539 | /* Combine the S1 and S2 cache attributes, if needed */ | |
10540 | if (!ret && cacheattrs != NULL) { | |
9d1bab33 PM |
10541 | if (env->cp15.hcr_el2 & HCR_DC) { |
10542 | /* | |
10543 | * HCR.DC forces the first stage attributes to | |
10544 | * Normal Non-Shareable, | |
10545 | * Inner Write-Back Read-Allocate Write-Allocate, | |
10546 | * Outer Write-Back Read-Allocate Write-Allocate. | |
10547 | */ | |
10548 | cacheattrs->attrs = 0xff; | |
10549 | cacheattrs->shareability = 0; | |
10550 | } | |
5b2d261d AB |
10551 | *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2); |
10552 | } | |
10553 | ||
9b539263 EI |
10554 | return ret; |
10555 | } else { | |
10556 | /* | |
10557 | * For non-EL2 CPUs a stage1+stage2 translation is just stage 1. | |
10558 | */ | |
8bd5c820 | 10559 | mmu_idx = stage_1_mmu_idx(mmu_idx); |
9b539263 | 10560 | } |
0480f69a | 10561 | } |
d3649702 | 10562 | |
8bf5b6a9 PM |
10563 | /* The page table entries may downgrade secure to non-secure, but |
10564 | * cannot upgrade an non-secure translation regime's attributes | |
10565 | * to secure. | |
10566 | */ | |
10567 | attrs->secure = regime_is_secure(env, mmu_idx); | |
0995bf8c | 10568 | attrs->user = regime_is_user(env, mmu_idx); |
8bf5b6a9 | 10569 | |
0480f69a PM |
10570 | /* Fast Context Switch Extension. This doesn't exist at all in v8. |
10571 | * In v7 and earlier it affects all stage 1 translations. | |
10572 | */ | |
10573 | if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS | |
10574 | && !arm_feature(env, ARM_FEATURE_V8)) { | |
10575 | if (regime_el(env, mmu_idx) == 3) { | |
10576 | address += env->cp15.fcseidr_s; | |
10577 | } else { | |
10578 | address += env->cp15.fcseidr_ns; | |
10579 | } | |
54bf36ed | 10580 | } |
9ee6e8bb | 10581 | |
3279adb9 | 10582 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
c9f9f124 | 10583 | bool ret; |
f6bda88f | 10584 | *page_size = TARGET_PAGE_SIZE; |
3279adb9 | 10585 | |
504e3cc3 PM |
10586 | if (arm_feature(env, ARM_FEATURE_V8)) { |
10587 | /* PMSAv8 */ | |
10588 | ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, | |
72042435 | 10589 | phys_ptr, attrs, prot, page_size, fi); |
504e3cc3 | 10590 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
3279adb9 PM |
10591 | /* PMSAv7 */ |
10592 | ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, | |
e5e40999 | 10593 | phys_ptr, prot, page_size, fi); |
3279adb9 PM |
10594 | } else { |
10595 | /* Pre-v7 MPU */ | |
10596 | ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, | |
53a4e5c5 | 10597 | phys_ptr, prot, fi); |
3279adb9 PM |
10598 | } |
10599 | qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 | |
c9f9f124 | 10600 | " mmu_idx %u -> %s (prot %c%c%c)\n", |
709e4407 PM |
10601 | access_type == MMU_DATA_LOAD ? "reading" : |
10602 | (access_type == MMU_DATA_STORE ? "writing" : "execute"), | |
c9f9f124 MD |
10603 | (uint32_t)address, mmu_idx, |
10604 | ret ? "Miss" : "Hit", | |
10605 | *prot & PAGE_READ ? 'r' : '-', | |
10606 | *prot & PAGE_WRITE ? 'w' : '-', | |
10607 | *prot & PAGE_EXEC ? 'x' : '-'); | |
10608 | ||
10609 | return ret; | |
f6bda88f PC |
10610 | } |
10611 | ||
3279adb9 PM |
10612 | /* Definitely a real MMU, not an MPU */ |
10613 | ||
0480f69a | 10614 | if (regime_translation_disabled(env, mmu_idx)) { |
3279adb9 | 10615 | /* MMU disabled. */ |
9ee6e8bb | 10616 | *phys_ptr = address; |
3ad493fc | 10617 | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
d4c430a8 | 10618 | *page_size = TARGET_PAGE_SIZE; |
9ee6e8bb | 10619 | return 0; |
0480f69a PM |
10620 | } |
10621 | ||
0480f69a | 10622 | if (regime_using_lpae_format(env, mmu_idx)) { |
bc52bfeb PM |
10623 | return get_phys_addr_lpae(env, address, access_type, mmu_idx, |
10624 | phys_ptr, attrs, prot, page_size, | |
10625 | fi, cacheattrs); | |
0480f69a | 10626 | } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { |
bc52bfeb PM |
10627 | return get_phys_addr_v6(env, address, access_type, mmu_idx, |
10628 | phys_ptr, attrs, prot, page_size, fi); | |
9ee6e8bb | 10629 | } else { |
bc52bfeb | 10630 | return get_phys_addr_v5(env, address, access_type, mmu_idx, |
f989983e | 10631 | phys_ptr, prot, page_size, fi); |
9ee6e8bb PB |
10632 | } |
10633 | } | |
10634 | ||
0faea0c7 PM |
10635 | hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, |
10636 | MemTxAttrs *attrs) | |
b5ff1b31 | 10637 | { |
00b941e5 | 10638 | ARMCPU *cpu = ARM_CPU(cs); |
d3649702 | 10639 | CPUARMState *env = &cpu->env; |
a8170e5e | 10640 | hwaddr phys_addr; |
d4c430a8 | 10641 | target_ulong page_size; |
b5ff1b31 | 10642 | int prot; |
b7cc4e82 | 10643 | bool ret; |
e14b5a23 | 10644 | ARMMMUFaultInfo fi = {}; |
50494a27 | 10645 | ARMMMUIdx mmu_idx = arm_mmu_idx(env); |
b5ff1b31 | 10646 | |
0faea0c7 PM |
10647 | *attrs = (MemTxAttrs) {}; |
10648 | ||
8bd5c820 | 10649 | ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr, |
bc52bfeb | 10650 | attrs, &prot, &page_size, &fi, NULL); |
b5ff1b31 | 10651 | |
b7cc4e82 | 10652 | if (ret) { |
b5ff1b31 | 10653 | return -1; |
00b941e5 | 10654 | } |
b5ff1b31 FB |
10655 | return phys_addr; |
10656 | } | |
10657 | ||
b5ff1b31 | 10658 | #endif |
6ddbc6e4 PB |
10659 | |
10660 | /* Note that signed overflow is undefined in C. The following routines are | |
10661 | careful to use unsigned types where modulo arithmetic is required. | |
10662 | Failure to do so _will_ break on newer gcc. */ | |
10663 | ||
10664 | /* Signed saturating arithmetic. */ | |
10665 | ||
1654b2d6 | 10666 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
10667 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
10668 | { | |
10669 | uint16_t res; | |
10670 | ||
10671 | res = a + b; | |
10672 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
10673 | if (a & 0x8000) | |
10674 | res = 0x8000; | |
10675 | else | |
10676 | res = 0x7fff; | |
10677 | } | |
10678 | return res; | |
10679 | } | |
10680 | ||
1654b2d6 | 10681 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
10682 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
10683 | { | |
10684 | uint8_t res; | |
10685 | ||
10686 | res = a + b; | |
10687 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
10688 | if (a & 0x80) | |
10689 | res = 0x80; | |
10690 | else | |
10691 | res = 0x7f; | |
10692 | } | |
10693 | return res; | |
10694 | } | |
10695 | ||
1654b2d6 | 10696 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
10697 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
10698 | { | |
10699 | uint16_t res; | |
10700 | ||
10701 | res = a - b; | |
10702 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
10703 | if (a & 0x8000) | |
10704 | res = 0x8000; | |
10705 | else | |
10706 | res = 0x7fff; | |
10707 | } | |
10708 | return res; | |
10709 | } | |
10710 | ||
1654b2d6 | 10711 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
10712 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
10713 | { | |
10714 | uint8_t res; | |
10715 | ||
10716 | res = a - b; | |
10717 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
10718 | if (a & 0x80) | |
10719 | res = 0x80; | |
10720 | else | |
10721 | res = 0x7f; | |
10722 | } | |
10723 | return res; | |
10724 | } | |
10725 | ||
10726 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
10727 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
10728 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
10729 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
10730 | #define PFX q | |
10731 | ||
10732 | #include "op_addsub.h" | |
10733 | ||
10734 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 10735 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
10736 | { |
10737 | uint16_t res; | |
10738 | res = a + b; | |
10739 | if (res < a) | |
10740 | res = 0xffff; | |
10741 | return res; | |
10742 | } | |
10743 | ||
460a09c1 | 10744 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 | 10745 | { |
4c4fd3f8 | 10746 | if (a > b) |
6ddbc6e4 PB |
10747 | return a - b; |
10748 | else | |
10749 | return 0; | |
10750 | } | |
10751 | ||
10752 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
10753 | { | |
10754 | uint8_t res; | |
10755 | res = a + b; | |
10756 | if (res < a) | |
10757 | res = 0xff; | |
10758 | return res; | |
10759 | } | |
10760 | ||
10761 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
10762 | { | |
4c4fd3f8 | 10763 | if (a > b) |
6ddbc6e4 PB |
10764 | return a - b; |
10765 | else | |
10766 | return 0; | |
10767 | } | |
10768 | ||
10769 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
10770 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
10771 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
10772 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
10773 | #define PFX uq | |
10774 | ||
10775 | #include "op_addsub.h" | |
10776 | ||
10777 | /* Signed modulo arithmetic. */ | |
10778 | #define SARITH16(a, b, n, op) do { \ | |
10779 | int32_t sum; \ | |
db6e2e65 | 10780 | sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
6ddbc6e4 PB |
10781 | RESULT(sum, n, 16); \ |
10782 | if (sum >= 0) \ | |
10783 | ge |= 3 << (n * 2); \ | |
10784 | } while(0) | |
10785 | ||
10786 | #define SARITH8(a, b, n, op) do { \ | |
10787 | int32_t sum; \ | |
db6e2e65 | 10788 | sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
6ddbc6e4 PB |
10789 | RESULT(sum, n, 8); \ |
10790 | if (sum >= 0) \ | |
10791 | ge |= 1 << n; \ | |
10792 | } while(0) | |
10793 | ||
10794 | ||
10795 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
10796 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
10797 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
10798 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
10799 | #define PFX s | |
10800 | #define ARITH_GE | |
10801 | ||
10802 | #include "op_addsub.h" | |
10803 | ||
10804 | /* Unsigned modulo arithmetic. */ | |
10805 | #define ADD16(a, b, n) do { \ | |
10806 | uint32_t sum; \ | |
10807 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
10808 | RESULT(sum, n, 16); \ | |
a87aa10b | 10809 | if ((sum >> 16) == 1) \ |
6ddbc6e4 PB |
10810 | ge |= 3 << (n * 2); \ |
10811 | } while(0) | |
10812 | ||
10813 | #define ADD8(a, b, n) do { \ | |
10814 | uint32_t sum; \ | |
10815 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
10816 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
10817 | if ((sum >> 8) == 1) \ |
10818 | ge |= 1 << n; \ | |
6ddbc6e4 PB |
10819 | } while(0) |
10820 | ||
10821 | #define SUB16(a, b, n) do { \ | |
10822 | uint32_t sum; \ | |
10823 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
10824 | RESULT(sum, n, 16); \ | |
10825 | if ((sum >> 16) == 0) \ | |
10826 | ge |= 3 << (n * 2); \ | |
10827 | } while(0) | |
10828 | ||
10829 | #define SUB8(a, b, n) do { \ | |
10830 | uint32_t sum; \ | |
10831 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
10832 | RESULT(sum, n, 8); \ | |
10833 | if ((sum >> 8) == 0) \ | |
a87aa10b | 10834 | ge |= 1 << n; \ |
6ddbc6e4 PB |
10835 | } while(0) |
10836 | ||
10837 | #define PFX u | |
10838 | #define ARITH_GE | |
10839 | ||
10840 | #include "op_addsub.h" | |
10841 | ||
10842 | /* Halved signed arithmetic. */ | |
10843 | #define ADD16(a, b, n) \ | |
10844 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
10845 | #define SUB16(a, b, n) \ | |
10846 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
10847 | #define ADD8(a, b, n) \ | |
10848 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
10849 | #define SUB8(a, b, n) \ | |
10850 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
10851 | #define PFX sh | |
10852 | ||
10853 | #include "op_addsub.h" | |
10854 | ||
10855 | /* Halved unsigned arithmetic. */ | |
10856 | #define ADD16(a, b, n) \ | |
10857 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
10858 | #define SUB16(a, b, n) \ | |
10859 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
10860 | #define ADD8(a, b, n) \ | |
10861 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
10862 | #define SUB8(a, b, n) \ | |
10863 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
10864 | #define PFX uh | |
10865 | ||
10866 | #include "op_addsub.h" | |
10867 | ||
10868 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
10869 | { | |
10870 | if (a > b) | |
10871 | return a - b; | |
10872 | else | |
10873 | return b - a; | |
10874 | } | |
10875 | ||
10876 | /* Unsigned sum of absolute byte differences. */ | |
10877 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
10878 | { | |
10879 | uint32_t sum; | |
10880 | sum = do_usad(a, b); | |
10881 | sum += do_usad(a >> 8, b >> 8); | |
10882 | sum += do_usad(a >> 16, b >>16); | |
10883 | sum += do_usad(a >> 24, b >> 24); | |
10884 | return sum; | |
10885 | } | |
10886 | ||
10887 | /* For ARMv6 SEL instruction. */ | |
10888 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
10889 | { | |
10890 | uint32_t mask; | |
10891 | ||
10892 | mask = 0; | |
10893 | if (flags & 1) | |
10894 | mask |= 0xff; | |
10895 | if (flags & 2) | |
10896 | mask |= 0xff00; | |
10897 | if (flags & 4) | |
10898 | mask |= 0xff0000; | |
10899 | if (flags & 8) | |
10900 | mask |= 0xff000000; | |
10901 | return (a & mask) | (b & ~mask); | |
10902 | } | |
10903 | ||
aa633469 PM |
10904 | /* CRC helpers. |
10905 | * The upper bytes of val (above the number specified by 'bytes') must have | |
10906 | * been zeroed out by the caller. | |
10907 | */ | |
eb0ecd5a WN |
10908 | uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) |
10909 | { | |
10910 | uint8_t buf[4]; | |
10911 | ||
aa633469 | 10912 | stl_le_p(buf, val); |
eb0ecd5a WN |
10913 | |
10914 | /* zlib crc32 converts the accumulator and output to one's complement. */ | |
10915 | return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | |
10916 | } | |
10917 | ||
10918 | uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | |
10919 | { | |
10920 | uint8_t buf[4]; | |
10921 | ||
aa633469 | 10922 | stl_le_p(buf, val); |
eb0ecd5a WN |
10923 | |
10924 | /* Linux crc32c converts the output to one's complement. */ | |
10925 | return crc32c(acc, buf, bytes) ^ 0xffffffff; | |
10926 | } | |
a9e01311 RH |
10927 | |
10928 | /* Return the exception level to which FP-disabled exceptions should | |
10929 | * be taken, or 0 if FP is enabled. | |
10930 | */ | |
ced31551 | 10931 | int fp_exception_el(CPUARMState *env, int cur_el) |
a9e01311 | 10932 | { |
55faa212 | 10933 | #ifndef CONFIG_USER_ONLY |
a9e01311 | 10934 | int fpen; |
a9e01311 RH |
10935 | |
10936 | /* CPACR and the CPTR registers don't exist before v6, so FP is | |
10937 | * always accessible | |
10938 | */ | |
10939 | if (!arm_feature(env, ARM_FEATURE_V6)) { | |
10940 | return 0; | |
10941 | } | |
10942 | ||
d87513c0 PM |
10943 | if (arm_feature(env, ARM_FEATURE_M)) { |
10944 | /* CPACR can cause a NOCP UsageFault taken to current security state */ | |
10945 | if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) { | |
10946 | return 1; | |
10947 | } | |
10948 | ||
10949 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) { | |
10950 | if (!extract32(env->v7m.nsacr, 10, 1)) { | |
10951 | /* FP insns cause a NOCP UsageFault taken to Secure */ | |
10952 | return 3; | |
10953 | } | |
10954 | } | |
10955 | ||
10956 | return 0; | |
10957 | } | |
10958 | ||
a9e01311 RH |
10959 | /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: |
10960 | * 0, 2 : trap EL0 and EL1/PL1 accesses | |
10961 | * 1 : trap only EL0 accesses | |
10962 | * 3 : trap no accesses | |
10963 | */ | |
10964 | fpen = extract32(env->cp15.cpacr_el1, 20, 2); | |
10965 | switch (fpen) { | |
10966 | case 0: | |
10967 | case 2: | |
10968 | if (cur_el == 0 || cur_el == 1) { | |
10969 | /* Trap to PL1, which might be EL1 or EL3 */ | |
10970 | if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { | |
10971 | return 3; | |
10972 | } | |
10973 | return 1; | |
10974 | } | |
10975 | if (cur_el == 3 && !is_a64(env)) { | |
10976 | /* Secure PL1 running at EL3 */ | |
10977 | return 3; | |
10978 | } | |
10979 | break; | |
10980 | case 1: | |
10981 | if (cur_el == 0) { | |
10982 | return 1; | |
10983 | } | |
10984 | break; | |
10985 | case 3: | |
10986 | break; | |
10987 | } | |
10988 | ||
fc1120a7 PM |
10989 | /* |
10990 | * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode | |
10991 | * to control non-secure access to the FPU. It doesn't have any | |
10992 | * effect if EL3 is AArch64 or if EL3 doesn't exist at all. | |
10993 | */ | |
10994 | if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
10995 | cur_el <= 2 && !arm_is_secure_below_el3(env))) { | |
10996 | if (!extract32(env->cp15.nsacr, 10, 1)) { | |
10997 | /* FP insns act as UNDEF */ | |
10998 | return cur_el == 2 ? 2 : 1; | |
10999 | } | |
11000 | } | |
11001 | ||
a9e01311 RH |
11002 | /* For the CPTR registers we don't need to guard with an ARM_FEATURE |
11003 | * check because zero bits in the registers mean "don't trap". | |
11004 | */ | |
11005 | ||
11006 | /* CPTR_EL2 : present in v7VE or v8 */ | |
11007 | if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1) | |
11008 | && !arm_is_secure_below_el3(env)) { | |
11009 | /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ | |
11010 | return 2; | |
11011 | } | |
11012 | ||
11013 | /* CPTR_EL3 : present in v8 */ | |
11014 | if (extract32(env->cp15.cptr_el[3], 10, 1)) { | |
11015 | /* Trap all FP ops to EL3 */ | |
11016 | return 3; | |
11017 | } | |
55faa212 | 11018 | #endif |
a9e01311 RH |
11019 | return 0; |
11020 | } | |
11021 | ||
7aab5a8c | 11022 | #ifndef CONFIG_TCG |
65e4655c RH |
11023 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
11024 | { | |
7aab5a8c | 11025 | g_assert_not_reached(); |
65e4655c | 11026 | } |
7aab5a8c | 11027 | #endif |
65e4655c | 11028 | |
50494a27 | 11029 | ARMMMUIdx arm_mmu_idx(CPUARMState *env) |
65e4655c | 11030 | { |
50494a27 | 11031 | int el; |
65e4655c RH |
11032 | |
11033 | if (arm_feature(env, ARM_FEATURE_M)) { | |
50494a27 | 11034 | return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); |
65e4655c RH |
11035 | } |
11036 | ||
50494a27 | 11037 | el = arm_current_el(env); |
65e4655c | 11038 | if (el < 2 && arm_is_secure_below_el3(env)) { |
50494a27 RH |
11039 | return ARMMMUIdx_S1SE0 + el; |
11040 | } else { | |
11041 | return ARMMMUIdx_S12NSE0 + el; | |
65e4655c | 11042 | } |
50494a27 RH |
11043 | } |
11044 | ||
11045 | int cpu_mmu_index(CPUARMState *env, bool ifetch) | |
11046 | { | |
11047 | return arm_to_core_mmu_idx(arm_mmu_idx(env)); | |
65e4655c RH |
11048 | } |
11049 | ||
64be86ab RH |
11050 | #ifndef CONFIG_USER_ONLY |
11051 | ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) | |
11052 | { | |
11053 | return stage_1_mmu_idx(arm_mmu_idx(env)); | |
11054 | } | |
11055 | #endif | |
11056 | ||
a9e01311 | 11057 | void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, |
b9adaa70 | 11058 | target_ulong *cs_base, uint32_t *pflags) |
a9e01311 | 11059 | { |
50494a27 | 11060 | ARMMMUIdx mmu_idx = arm_mmu_idx(env); |
2de7ace2 RH |
11061 | int current_el = arm_current_el(env); |
11062 | int fp_el = fp_exception_el(env, current_el); | |
aad821ac | 11063 | uint32_t flags = 0; |
b9adaa70 | 11064 | |
a9e01311 | 11065 | if (is_a64(env)) { |
2fc0cc0e | 11066 | ARMCPU *cpu = env_archcpu(env); |
08f1434a | 11067 | uint64_t sctlr; |
cd208a1c | 11068 | |
a9e01311 | 11069 | *pc = env->pc; |
aad821ac | 11070 | flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); |
5d8634f5 | 11071 | |
c47eaf9f | 11072 | /* Get control bits for tagged addresses. */ |
5d8634f5 RH |
11073 | { |
11074 | ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); | |
11075 | ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); | |
11076 | int tbii, tbid; | |
11077 | ||
11078 | /* FIXME: ARMv8.1-VHE S2 translation regime. */ | |
11079 | if (regime_el(env, stage1) < 2) { | |
11080 | ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); | |
11081 | tbid = (p1.tbi << 1) | p0.tbi; | |
11082 | tbii = tbid & ~((p1.tbid << 1) | p0.tbid); | |
11083 | } else { | |
11084 | tbid = p0.tbi; | |
11085 | tbii = tbid & !p0.tbid; | |
11086 | } | |
11087 | ||
11088 | flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); | |
4a9ee99d | 11089 | flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); |
5d8634f5 | 11090 | } |
1db5e96c | 11091 | |
cd208a1c | 11092 | if (cpu_isar_feature(aa64_sve, cpu)) { |
2de7ace2 | 11093 | int sve_el = sve_exception_el(env, current_el); |
e79b445d | 11094 | uint32_t zcr_len; |
1db5e96c | 11095 | |
e79b445d RH |
11096 | /* If SVE is disabled, but FP is enabled, |
11097 | * then the effective len is 0. | |
11098 | */ | |
11099 | if (sve_el != 0 && fp_el == 0) { | |
11100 | zcr_len = 0; | |
11101 | } else { | |
0ab5953b | 11102 | zcr_len = sve_zcr_len_for_el(env, current_el); |
1db5e96c | 11103 | } |
aad821ac RH |
11104 | flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); |
11105 | flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); | |
1db5e96c | 11106 | } |
0816ef1b | 11107 | |
64e40755 RH |
11108 | sctlr = arm_sctlr(env, current_el); |
11109 | ||
0816ef1b RH |
11110 | if (cpu_isar_feature(aa64_pauth, cpu)) { |
11111 | /* | |
11112 | * In order to save space in flags, we record only whether | |
11113 | * pauth is "inactive", meaning all insns are implemented as | |
11114 | * a nop, or "active" when some action must be performed. | |
11115 | * The decision of which action to take is left to a helper. | |
11116 | */ | |
0816ef1b RH |
11117 | if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { |
11118 | flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); | |
11119 | } | |
11120 | } | |
08f1434a RH |
11121 | |
11122 | if (cpu_isar_feature(aa64_bti, cpu)) { | |
11123 | /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ | |
11124 | if (sctlr & (current_el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { | |
11125 | flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); | |
11126 | } | |
11127 | flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); | |
11128 | } | |
a9e01311 RH |
11129 | } else { |
11130 | *pc = env->regs[15]; | |
aad821ac RH |
11131 | flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); |
11132 | flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); | |
11133 | flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); | |
11134 | flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); | |
11135 | flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); | |
11136 | flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); | |
a9e01311 | 11137 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) |
d87513c0 | 11138 | || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { |
aad821ac | 11139 | flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); |
a9e01311 | 11140 | } |
ea7ac69d PM |
11141 | /* Note that XSCALE_CPAR shares bits with VECSTRIDE */ |
11142 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
11143 | flags = FIELD_DP32(flags, TBFLAG_A32, | |
11144 | XSCALE_CPAR, env->cp15.c15_cpar); | |
11145 | } | |
a9e01311 RH |
11146 | } |
11147 | ||
aad821ac | 11148 | flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); |
a9e01311 RH |
11149 | |
11150 | /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine | |
11151 | * states defined in the ARM ARM for software singlestep: | |
11152 | * SS_ACTIVE PSTATE.SS State | |
11153 | * 0 x Inactive (the TB flag for SS is always 0) | |
11154 | * 1 0 Active-pending | |
11155 | * 1 1 Active-not-pending | |
11156 | */ | |
11157 | if (arm_singlestep_active(env)) { | |
aad821ac | 11158 | flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); |
a9e01311 RH |
11159 | if (is_a64(env)) { |
11160 | if (env->pstate & PSTATE_SS) { | |
aad821ac | 11161 | flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); |
a9e01311 RH |
11162 | } |
11163 | } else { | |
11164 | if (env->uncached_cpsr & PSTATE_SS) { | |
aad821ac | 11165 | flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); |
a9e01311 RH |
11166 | } |
11167 | } | |
11168 | } | |
11169 | if (arm_cpu_data_is_big_endian(env)) { | |
aad821ac | 11170 | flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); |
a9e01311 | 11171 | } |
aad821ac | 11172 | flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); |
a9e01311 RH |
11173 | |
11174 | if (arm_v7m_is_handler_mode(env)) { | |
aad821ac | 11175 | flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); |
a9e01311 RH |
11176 | } |
11177 | ||
4730fb85 PM |
11178 | /* v8M always applies stack limit checks unless CCR.STKOFHFNMIGN is |
11179 | * suppressing them because the requested execution priority is less than 0. | |
11180 | */ | |
11181 | if (arm_feature(env, ARM_FEATURE_V8) && | |
11182 | arm_feature(env, ARM_FEATURE_M) && | |
11183 | !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && | |
11184 | (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) { | |
aad821ac | 11185 | flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); |
4730fb85 PM |
11186 | } |
11187 | ||
6d60c67a PM |
11188 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && |
11189 | FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) { | |
11190 | flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); | |
11191 | } | |
11192 | ||
6000531e PM |
11193 | if (arm_feature(env, ARM_FEATURE_M) && |
11194 | (env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && | |
11195 | (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || | |
11196 | (env->v7m.secure && | |
11197 | !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { | |
11198 | /* | |
11199 | * ASPEN is set, but FPCA/SFPA indicate that there is no active | |
11200 | * FP context; we must create a new FP context before executing | |
11201 | * any FP insn. | |
11202 | */ | |
11203 | flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1); | |
11204 | } | |
11205 | ||
e33cf0f8 PM |
11206 | if (arm_feature(env, ARM_FEATURE_M)) { |
11207 | bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; | |
11208 | ||
11209 | if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { | |
11210 | flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); | |
11211 | } | |
11212 | } | |
11213 | ||
8bd587c1 PM |
11214 | if (!arm_feature(env, ARM_FEATURE_M)) { |
11215 | int target_el = arm_debug_target_el(env); | |
11216 | ||
11217 | flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, target_el); | |
11218 | } | |
11219 | ||
b9adaa70 | 11220 | *pflags = flags; |
a9e01311 RH |
11221 | *cs_base = 0; |
11222 | } | |
0ab5953b RH |
11223 | |
11224 | #ifdef TARGET_AARCH64 | |
11225 | /* | |
11226 | * The manual says that when SVE is enabled and VQ is widened the | |
11227 | * implementation is allowed to zero the previously inaccessible | |
11228 | * portion of the registers. The corollary to that is that when | |
11229 | * SVE is enabled and VQ is narrowed we are also allowed to zero | |
11230 | * the now inaccessible portion of the registers. | |
11231 | * | |
11232 | * The intent of this is that no predicate bit beyond VQ is ever set. | |
11233 | * Which means that some operations on predicate registers themselves | |
11234 | * may operate on full uint64_t or even unrolled across the maximum | |
11235 | * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally | |
11236 | * may well be cheaper than conditionals to restrict the operation | |
11237 | * to the relevant portion of a uint16_t[16]. | |
11238 | */ | |
11239 | void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) | |
11240 | { | |
11241 | int i, j; | |
11242 | uint64_t pmask; | |
11243 | ||
11244 | assert(vq >= 1 && vq <= ARM_MAX_VQ); | |
2fc0cc0e | 11245 | assert(vq <= env_archcpu(env)->sve_max_vq); |
0ab5953b RH |
11246 | |
11247 | /* Zap the high bits of the zregs. */ | |
11248 | for (i = 0; i < 32; i++) { | |
11249 | memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)); | |
11250 | } | |
11251 | ||
11252 | /* Zap the high bits of the pregs and ffr. */ | |
11253 | pmask = 0; | |
11254 | if (vq & 3) { | |
11255 | pmask = ~(-1ULL << (16 * (vq & 3))); | |
11256 | } | |
11257 | for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) { | |
11258 | for (i = 0; i < 17; ++i) { | |
11259 | env->vfp.pregs[i].p[j] &= pmask; | |
11260 | } | |
11261 | pmask = 0; | |
11262 | } | |
11263 | } | |
11264 | ||
11265 | /* | |
11266 | * Notice a change in SVE vector size when changing EL. | |
11267 | */ | |
9a05f7b6 RH |
11268 | void aarch64_sve_change_el(CPUARMState *env, int old_el, |
11269 | int new_el, bool el0_a64) | |
0ab5953b | 11270 | { |
2fc0cc0e | 11271 | ARMCPU *cpu = env_archcpu(env); |
0ab5953b | 11272 | int old_len, new_len; |
9a05f7b6 | 11273 | bool old_a64, new_a64; |
0ab5953b RH |
11274 | |
11275 | /* Nothing to do if no SVE. */ | |
cd208a1c | 11276 | if (!cpu_isar_feature(aa64_sve, cpu)) { |
0ab5953b RH |
11277 | return; |
11278 | } | |
11279 | ||
11280 | /* Nothing to do if FP is disabled in either EL. */ | |
11281 | if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) { | |
11282 | return; | |
11283 | } | |
11284 | ||
11285 | /* | |
11286 | * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped | |
11287 | * at ELx, or not available because the EL is in AArch32 state, then | |
11288 | * for all purposes other than a direct read, the ZCR_ELx.LEN field | |
11289 | * has an effective value of 0". | |
11290 | * | |
11291 | * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0). | |
11292 | * If we ignore aa32 state, we would fail to see the vq4->vq0 transition | |
11293 | * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that | |
11294 | * we already have the correct register contents when encountering the | |
11295 | * vq0->vq0 transition between EL0->EL1. | |
11296 | */ | |
9a05f7b6 RH |
11297 | old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; |
11298 | old_len = (old_a64 && !sve_exception_el(env, old_el) | |
0ab5953b | 11299 | ? sve_zcr_len_for_el(env, old_el) : 0); |
9a05f7b6 RH |
11300 | new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; |
11301 | new_len = (new_a64 && !sve_exception_el(env, new_el) | |
0ab5953b RH |
11302 | ? sve_zcr_len_for_el(env, new_el) : 0); |
11303 | ||
11304 | /* When changing vector length, clear inaccessible state. */ | |
11305 | if (new_len < old_len) { | |
11306 | aarch64_sve_narrow_vq(env, new_len + 1); | |
11307 | } | |
11308 | } | |
11309 | #endif |