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Commit | Line | Data |
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ed3baad1 PMD |
1 | /* |
2 | * ARM generic helpers. | |
3 | * | |
4 | * This code is licensed under the GNU GPL v2 or later. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0-or-later | |
7 | */ | |
db725815 | 8 | |
74c21bd0 | 9 | #include "qemu/osdep.h" |
cd617484 | 10 | #include "qemu/log.h" |
194cbc49 | 11 | #include "trace.h" |
b5ff1b31 | 12 | #include "cpu.h" |
ccd38087 | 13 | #include "internals.h" |
5a534314 | 14 | #include "cpu-features.h" |
2ef6175a | 15 | #include "exec/helper-proto.h" |
db725815 | 16 | #include "qemu/main-loop.h" |
b8012ecf | 17 | #include "qemu/timer.h" |
1de7afc9 | 18 | #include "qemu/bitops.h" |
eb0ecd5a | 19 | #include "qemu/crc32c.h" |
0442428a | 20 | #include "qemu/qemu-print.h" |
63c91552 | 21 | #include "exec/exec-all.h" |
eb0ecd5a | 22 | #include <zlib.h> /* For crc32 */ |
64552b6b | 23 | #include "hw/irq.h" |
740b1759 | 24 | #include "sysemu/cpu-timers.h" |
f3a9b694 | 25 | #include "sysemu/kvm.h" |
0c1aaa66 | 26 | #include "sysemu/tcg.h" |
de390645 RH |
27 | #include "qapi/error.h" |
28 | #include "qemu/guest-random.h" | |
91f78c58 | 29 | #ifdef CONFIG_TCG |
6b5fe137 | 30 | #include "semihosting/common-semi.h" |
91f78c58 | 31 | #endif |
cf7c6d10 | 32 | #include "cpregs.h" |
0b03bdfc | 33 | |
352c98e5 LV |
34 | #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ |
35 | ||
affdb64d PM |
36 | static void switch_mode(CPUARMState *env, int mode); |
37 | ||
c4241c7d | 38 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) |
d4e6df63 | 39 | { |
375421cc | 40 | assert(ri->fieldoffset); |
67ed771d | 41 | if (cpreg_field_is_64bit(ri)) { |
c4241c7d | 42 | return CPREG_FIELD64(env, ri); |
22d9e1a9 | 43 | } else { |
c4241c7d | 44 | return CPREG_FIELD32(env, ri); |
22d9e1a9 | 45 | } |
d4e6df63 PM |
46 | } |
47 | ||
f43ee493 | 48 | void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
d4e6df63 | 49 | { |
375421cc | 50 | assert(ri->fieldoffset); |
67ed771d | 51 | if (cpreg_field_is_64bit(ri)) { |
22d9e1a9 PM |
52 | CPREG_FIELD64(env, ri) = value; |
53 | } else { | |
54 | CPREG_FIELD32(env, ri) = value; | |
55 | } | |
d4e6df63 PM |
56 | } |
57 | ||
11f136ee FA |
58 | static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) |
59 | { | |
60 | return (char *)env + ri->fieldoffset; | |
61 | } | |
62 | ||
49a66191 | 63 | uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) |
721fae12 | 64 | { |
59a1c327 | 65 | /* Raw read of a coprocessor register (as needed for migration, etc). */ |
721fae12 | 66 | if (ri->type & ARM_CP_CONST) { |
59a1c327 | 67 | return ri->resetvalue; |
721fae12 | 68 | } else if (ri->raw_readfn) { |
59a1c327 | 69 | return ri->raw_readfn(env, ri); |
721fae12 | 70 | } else if (ri->readfn) { |
59a1c327 | 71 | return ri->readfn(env, ri); |
721fae12 | 72 | } else { |
59a1c327 | 73 | return raw_read(env, ri); |
721fae12 | 74 | } |
721fae12 PM |
75 | } |
76 | ||
59a1c327 | 77 | static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, |
7900e9f1 | 78 | uint64_t v) |
721fae12 | 79 | { |
9b37a28c FR |
80 | /* |
81 | * Raw write of a coprocessor register (as needed for migration, etc). | |
721fae12 PM |
82 | * Note that constant registers are treated as write-ignored; the |
83 | * caller should check for success by whether a readback gives the | |
84 | * value written. | |
85 | */ | |
86 | if (ri->type & ARM_CP_CONST) { | |
59a1c327 | 87 | return; |
721fae12 | 88 | } else if (ri->raw_writefn) { |
c4241c7d | 89 | ri->raw_writefn(env, ri, v); |
721fae12 | 90 | } else if (ri->writefn) { |
c4241c7d | 91 | ri->writefn(env, ri, v); |
721fae12 | 92 | } else { |
afb2530f | 93 | raw_write(env, ri, v); |
721fae12 | 94 | } |
721fae12 PM |
95 | } |
96 | ||
375421cc PM |
97 | static bool raw_accessors_invalid(const ARMCPRegInfo *ri) |
98 | { | |
9b37a28c FR |
99 | /* |
100 | * Return true if the regdef would cause an assertion if you called | |
375421cc PM |
101 | * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a |
102 | * program bug for it not to have the NO_RAW flag). | |
103 | * NB that returning false here doesn't necessarily mean that calling | |
104 | * read/write_raw_cp_reg() is safe, because we can't distinguish "has | |
105 | * read/write access functions which are safe for raw use" from "has | |
106 | * read/write access functions which have side effects but has forgotten | |
107 | * to provide raw access functions". | |
108 | * The tests here line up with the conditions in read/write_raw_cp_reg() | |
109 | * and assertions in raw_read()/raw_write(). | |
110 | */ | |
111 | if ((ri->type & ARM_CP_CONST) || | |
112 | ri->fieldoffset || | |
113 | ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) { | |
114 | return false; | |
115 | } | |
116 | return true; | |
117 | } | |
118 | ||
b698e4ee | 119 | bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync) |
721fae12 PM |
120 | { |
121 | /* Write the coprocessor state from cpu->env to the (index,value) list. */ | |
122 | int i; | |
123 | bool ok = true; | |
124 | ||
125 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
126 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
127 | const ARMCPRegInfo *ri; | |
b698e4ee | 128 | uint64_t newval; |
59a1c327 | 129 | |
60322b39 | 130 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
131 | if (!ri) { |
132 | ok = false; | |
133 | continue; | |
134 | } | |
7a0e58fa | 135 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
136 | continue; |
137 | } | |
b698e4ee PM |
138 | |
139 | newval = read_raw_cp_reg(&cpu->env, ri); | |
140 | if (kvm_sync) { | |
141 | /* | |
142 | * Only sync if the previous list->cpustate sync succeeded. | |
143 | * Rather than tracking the success/failure state for every | |
144 | * item in the list, we just recheck "does the raw write we must | |
145 | * have made in write_list_to_cpustate() read back OK" here. | |
146 | */ | |
147 | uint64_t oldval = cpu->cpreg_values[i]; | |
148 | ||
149 | if (oldval == newval) { | |
150 | continue; | |
151 | } | |
152 | ||
153 | write_raw_cp_reg(&cpu->env, ri, oldval); | |
154 | if (read_raw_cp_reg(&cpu->env, ri) != oldval) { | |
155 | continue; | |
156 | } | |
157 | ||
158 | write_raw_cp_reg(&cpu->env, ri, newval); | |
159 | } | |
160 | cpu->cpreg_values[i] = newval; | |
721fae12 PM |
161 | } |
162 | return ok; | |
163 | } | |
164 | ||
165 | bool write_list_to_cpustate(ARMCPU *cpu) | |
166 | { | |
167 | int i; | |
168 | bool ok = true; | |
169 | ||
170 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
171 | uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]); | |
172 | uint64_t v = cpu->cpreg_values[i]; | |
721fae12 PM |
173 | const ARMCPRegInfo *ri; |
174 | ||
60322b39 | 175 | ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); |
721fae12 PM |
176 | if (!ri) { |
177 | ok = false; | |
178 | continue; | |
179 | } | |
7a0e58fa | 180 | if (ri->type & ARM_CP_NO_RAW) { |
721fae12 PM |
181 | continue; |
182 | } | |
9b37a28c FR |
183 | /* |
184 | * Write value and confirm it reads back as written | |
721fae12 PM |
185 | * (to catch read-only registers and partially read-only |
186 | * registers where the incoming migration value doesn't match) | |
187 | */ | |
59a1c327 PM |
188 | write_raw_cp_reg(&cpu->env, ri, v); |
189 | if (read_raw_cp_reg(&cpu->env, ri) != v) { | |
721fae12 PM |
190 | ok = false; |
191 | } | |
192 | } | |
193 | return ok; | |
194 | } | |
195 | ||
196 | static void add_cpreg_to_list(gpointer key, gpointer opaque) | |
197 | { | |
198 | ARMCPU *cpu = opaque; | |
5860362d RH |
199 | uint32_t regidx = (uintptr_t)key; |
200 | const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx); | |
721fae12 | 201 | |
04215eb1 | 202 | if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { |
721fae12 PM |
203 | cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx); |
204 | /* The value array need not be initialized at this point */ | |
205 | cpu->cpreg_array_len++; | |
206 | } | |
207 | } | |
208 | ||
209 | static void count_cpreg(gpointer key, gpointer opaque) | |
210 | { | |
211 | ARMCPU *cpu = opaque; | |
721fae12 PM |
212 | const ARMCPRegInfo *ri; |
213 | ||
5860362d | 214 | ri = g_hash_table_lookup(cpu->cp_regs, key); |
721fae12 | 215 | |
04215eb1 | 216 | if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { |
721fae12 PM |
217 | cpu->cpreg_array_len++; |
218 | } | |
219 | } | |
220 | ||
221 | static gint cpreg_key_compare(gconstpointer a, gconstpointer b) | |
222 | { | |
5860362d RH |
223 | uint64_t aidx = cpreg_to_kvm_id((uintptr_t)a); |
224 | uint64_t bidx = cpreg_to_kvm_id((uintptr_t)b); | |
721fae12 | 225 | |
cbf239b7 AR |
226 | if (aidx > bidx) { |
227 | return 1; | |
228 | } | |
229 | if (aidx < bidx) { | |
230 | return -1; | |
231 | } | |
232 | return 0; | |
721fae12 PM |
233 | } |
234 | ||
235 | void init_cpreg_list(ARMCPU *cpu) | |
236 | { | |
9b37a28c FR |
237 | /* |
238 | * Initialise the cpreg_tuples[] array based on the cp_regs hash. | |
721fae12 PM |
239 | * Note that we require cpreg_tuples[] to be sorted by key ID. |
240 | */ | |
57b6d95e | 241 | GList *keys; |
721fae12 PM |
242 | int arraylen; |
243 | ||
57b6d95e | 244 | keys = g_hash_table_get_keys(cpu->cp_regs); |
721fae12 PM |
245 | keys = g_list_sort(keys, cpreg_key_compare); |
246 | ||
247 | cpu->cpreg_array_len = 0; | |
248 | ||
249 | g_list_foreach(keys, count_cpreg, cpu); | |
250 | ||
251 | arraylen = cpu->cpreg_array_len; | |
252 | cpu->cpreg_indexes = g_new(uint64_t, arraylen); | |
253 | cpu->cpreg_values = g_new(uint64_t, arraylen); | |
254 | cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen); | |
255 | cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen); | |
256 | cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; | |
257 | cpu->cpreg_array_len = 0; | |
258 | ||
259 | g_list_foreach(keys, add_cpreg_to_list, cpu); | |
260 | ||
261 | assert(cpu->cpreg_array_len == arraylen); | |
262 | ||
263 | g_list_free(keys); | |
264 | } | |
265 | ||
68e9c2fe | 266 | /* |
93dd1e61 | 267 | * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0. |
68e9c2fe EI |
268 | */ |
269 | static CPAccessResult access_el3_aa32ns(CPUARMState *env, | |
3f208fd7 PM |
270 | const ARMCPRegInfo *ri, |
271 | bool isread) | |
68e9c2fe | 272 | { |
93dd1e61 EI |
273 | if (!is_a64(env) && arm_current_el(env) == 3 && |
274 | arm_is_secure_below_el3(env)) { | |
68e9c2fe EI |
275 | return CP_ACCESS_TRAP_UNCATEGORIZED; |
276 | } | |
277 | return CP_ACCESS_OK; | |
278 | } | |
279 | ||
9b37a28c FR |
280 | /* |
281 | * Some secure-only AArch32 registers trap to EL3 if used from | |
5513c3ab PM |
282 | * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). |
283 | * Note that an access from Secure EL1 can only happen if EL3 is AArch64. | |
284 | * We assume that the .access field is set to PL1_RW. | |
285 | */ | |
286 | static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, | |
3f208fd7 PM |
287 | const ARMCPRegInfo *ri, |
288 | bool isread) | |
5513c3ab PM |
289 | { |
290 | if (arm_current_el(env) == 3) { | |
291 | return CP_ACCESS_OK; | |
292 | } | |
293 | if (arm_is_secure_below_el3(env)) { | |
926c1b97 RDC |
294 | if (env->cp15.scr_el3 & SCR_EEL2) { |
295 | return CP_ACCESS_TRAP_EL2; | |
296 | } | |
5513c3ab PM |
297 | return CP_ACCESS_TRAP_EL3; |
298 | } | |
299 | /* This will be EL1 NS and EL2 NS, which just UNDEF */ | |
300 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
301 | } | |
302 | ||
9b37a28c FR |
303 | /* |
304 | * Check for traps to performance monitor registers, which are controlled | |
1fce1ba9 PM |
305 | * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. |
306 | */ | |
307 | static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, | |
308 | bool isread) | |
309 | { | |
310 | int el = arm_current_el(env); | |
59dd089c | 311 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
1fce1ba9 | 312 | |
59dd089c | 313 | if (el < 2 && (mdcr_el2 & MDCR_TPM)) { |
1fce1ba9 PM |
314 | return CP_ACCESS_TRAP_EL2; |
315 | } | |
316 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
317 | return CP_ACCESS_TRAP_EL3; | |
318 | } | |
319 | return CP_ACCESS_OK; | |
320 | } | |
321 | ||
84929218 | 322 | /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ |
6d482423 RH |
323 | CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, |
324 | bool isread) | |
84929218 RH |
325 | { |
326 | if (arm_current_el(env) == 1) { | |
327 | uint64_t trap = isread ? HCR_TRVM : HCR_TVM; | |
328 | if (arm_hcr_el2_eff(env) & trap) { | |
329 | return CP_ACCESS_TRAP_EL2; | |
330 | } | |
331 | } | |
332 | return CP_ACCESS_OK; | |
333 | } | |
334 | ||
1803d271 RH |
335 | /* Check for traps from EL1 due to HCR_EL2.TSW. */ |
336 | static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri, | |
337 | bool isread) | |
338 | { | |
339 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) { | |
340 | return CP_ACCESS_TRAP_EL2; | |
341 | } | |
342 | return CP_ACCESS_OK; | |
343 | } | |
344 | ||
99602377 RH |
345 | /* Check for traps from EL1 due to HCR_EL2.TACR. */ |
346 | static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri, | |
347 | bool isread) | |
348 | { | |
349 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TACR)) { | |
350 | return CP_ACCESS_TRAP_EL2; | |
351 | } | |
352 | return CP_ACCESS_OK; | |
353 | } | |
354 | ||
30881b73 RH |
355 | /* Check for traps from EL1 due to HCR_EL2.TTLB. */ |
356 | static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri, | |
357 | bool isread) | |
358 | { | |
359 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TTLB)) { | |
360 | return CP_ACCESS_TRAP_EL2; | |
361 | } | |
362 | return CP_ACCESS_OK; | |
363 | } | |
364 | ||
0f66d223 PM |
365 | /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */ |
366 | static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri, | |
367 | bool isread) | |
368 | { | |
369 | if (arm_current_el(env) == 1 && | |
370 | (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBIS))) { | |
371 | return CP_ACCESS_TRAP_EL2; | |
372 | } | |
373 | return CP_ACCESS_OK; | |
374 | } | |
375 | ||
fe3ca86c PM |
376 | #ifdef TARGET_AARCH64 |
377 | /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */ | |
378 | static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri, | |
379 | bool isread) | |
380 | { | |
381 | if (arm_current_el(env) == 1 && | |
382 | (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBOS))) { | |
383 | return CP_ACCESS_TRAP_EL2; | |
384 | } | |
385 | return CP_ACCESS_OK; | |
386 | } | |
387 | #endif | |
388 | ||
c4241c7d | 389 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
c983fe6c | 390 | { |
2fc0cc0e | 391 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 392 | |
8d5c773e | 393 | raw_write(env, ri, value); |
d10eb08f | 394 | tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ |
c983fe6c PM |
395 | } |
396 | ||
c4241c7d | 397 | static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
08de207b | 398 | { |
2fc0cc0e | 399 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 400 | |
8d5c773e | 401 | if (raw_read(env, ri) != value) { |
9b37a28c FR |
402 | /* |
403 | * Unlike real hardware the qemu TLB uses virtual addresses, | |
08de207b PM |
404 | * not modified virtual addresses, so this causes a TLB flush. |
405 | */ | |
d10eb08f | 406 | tlb_flush(CPU(cpu)); |
8d5c773e | 407 | raw_write(env, ri, value); |
08de207b | 408 | } |
08de207b | 409 | } |
c4241c7d PM |
410 | |
411 | static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
412 | uint64_t value) | |
08de207b | 413 | { |
2fc0cc0e | 414 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 415 | |
452a0955 | 416 | if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) |
014406b5 | 417 | && !extended_addresses_enabled(env)) { |
9b37a28c FR |
418 | /* |
419 | * For VMSA (when not using the LPAE long descriptor page table | |
08de207b PM |
420 | * format) this register includes the ASID, so do a TLB flush. |
421 | * For PMSA it is purely a process ID and no action is needed. | |
422 | */ | |
d10eb08f | 423 | tlb_flush(CPU(cpu)); |
08de207b | 424 | } |
8d5c773e | 425 | raw_write(env, ri, value); |
08de207b PM |
426 | } |
427 | ||
575a94af RH |
428 | static int alle1_tlbmask(CPUARMState *env) |
429 | { | |
430 | /* | |
431 | * Note that the 'ALL' scope must invalidate both stage 1 and | |
432 | * stage 2 translations, whereas most other scopes only invalidate | |
433 | * stage 1 translations. | |
434 | */ | |
435 | return (ARMMMUIdxBit_E10_1 | | |
436 | ARMMMUIdxBit_E10_1_PAN | | |
437 | ARMMMUIdxBit_E10_0 | | |
438 | ARMMMUIdxBit_Stage2 | | |
439 | ARMMMUIdxBit_Stage2_S); | |
440 | } | |
441 | ||
442 | ||
b4ab8ce9 PM |
443 | /* IS variants of TLB operations must affect all cores */ |
444 | static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
445 | uint64_t value) | |
446 | { | |
29a0af61 | 447 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
448 | |
449 | tlb_flush_all_cpus_synced(cs); | |
450 | } | |
451 | ||
452 | static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
453 | uint64_t value) | |
454 | { | |
29a0af61 | 455 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
456 | |
457 | tlb_flush_all_cpus_synced(cs); | |
458 | } | |
459 | ||
460 | static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
461 | uint64_t value) | |
462 | { | |
29a0af61 | 463 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
464 | |
465 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
466 | } | |
467 | ||
468 | static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
469 | uint64_t value) | |
470 | { | |
29a0af61 | 471 | CPUState *cs = env_cpu(env); |
b4ab8ce9 PM |
472 | |
473 | tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); | |
474 | } | |
475 | ||
476 | /* | |
477 | * Non-IS variants of TLB operations are upgraded to | |
373e7ffd | 478 | * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to |
b4ab8ce9 PM |
479 | * force broadcast of these operations. |
480 | */ | |
481 | static bool tlb_force_broadcast(CPUARMState *env) | |
482 | { | |
373e7ffd | 483 | return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB); |
b4ab8ce9 PM |
484 | } |
485 | ||
c4241c7d PM |
486 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, |
487 | uint64_t value) | |
d929823f PM |
488 | { |
489 | /* Invalidate all (TLBIALL) */ | |
527db2be | 490 | CPUState *cs = env_cpu(env); |
00c8cb0a | 491 | |
b4ab8ce9 | 492 | if (tlb_force_broadcast(env)) { |
527db2be RH |
493 | tlb_flush_all_cpus_synced(cs); |
494 | } else { | |
495 | tlb_flush(cs); | |
b4ab8ce9 | 496 | } |
d929823f PM |
497 | } |
498 | ||
c4241c7d PM |
499 | static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, |
500 | uint64_t value) | |
d929823f PM |
501 | { |
502 | /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ | |
527db2be | 503 | CPUState *cs = env_cpu(env); |
31b030d4 | 504 | |
527db2be | 505 | value &= TARGET_PAGE_MASK; |
b4ab8ce9 | 506 | if (tlb_force_broadcast(env)) { |
527db2be RH |
507 | tlb_flush_page_all_cpus_synced(cs, value); |
508 | } else { | |
509 | tlb_flush_page(cs, value); | |
b4ab8ce9 | 510 | } |
d929823f PM |
511 | } |
512 | ||
c4241c7d PM |
513 | static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
514 | uint64_t value) | |
d929823f PM |
515 | { |
516 | /* Invalidate by ASID (TLBIASID) */ | |
527db2be | 517 | CPUState *cs = env_cpu(env); |
00c8cb0a | 518 | |
b4ab8ce9 | 519 | if (tlb_force_broadcast(env)) { |
527db2be RH |
520 | tlb_flush_all_cpus_synced(cs); |
521 | } else { | |
522 | tlb_flush(cs); | |
b4ab8ce9 | 523 | } |
d929823f PM |
524 | } |
525 | ||
c4241c7d PM |
526 | static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, |
527 | uint64_t value) | |
d929823f PM |
528 | { |
529 | /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ | |
527db2be | 530 | CPUState *cs = env_cpu(env); |
31b030d4 | 531 | |
527db2be | 532 | value &= TARGET_PAGE_MASK; |
b4ab8ce9 | 533 | if (tlb_force_broadcast(env)) { |
527db2be RH |
534 | tlb_flush_page_all_cpus_synced(cs, value); |
535 | } else { | |
536 | tlb_flush_page(cs, value); | |
b4ab8ce9 | 537 | } |
fa439fc5 PM |
538 | } |
539 | ||
541ef8c2 SS |
540 | static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, |
541 | uint64_t value) | |
542 | { | |
29a0af61 | 543 | CPUState *cs = env_cpu(env); |
541ef8c2 | 544 | |
575a94af | 545 | tlb_flush_by_mmuidx(cs, alle1_tlbmask(env)); |
541ef8c2 SS |
546 | } |
547 | ||
548 | static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
549 | uint64_t value) | |
550 | { | |
29a0af61 | 551 | CPUState *cs = env_cpu(env); |
541ef8c2 | 552 | |
575a94af | 553 | tlb_flush_by_mmuidx_all_cpus_synced(cs, alle1_tlbmask(env)); |
541ef8c2 SS |
554 | } |
555 | ||
541ef8c2 SS |
556 | |
557 | static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
558 | uint64_t value) | |
559 | { | |
29a0af61 | 560 | CPUState *cs = env_cpu(env); |
541ef8c2 | 561 | |
e013b741 | 562 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); |
541ef8c2 SS |
563 | } |
564 | ||
565 | static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
566 | uint64_t value) | |
567 | { | |
29a0af61 | 568 | CPUState *cs = env_cpu(env); |
541ef8c2 | 569 | |
e013b741 | 570 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); |
541ef8c2 SS |
571 | } |
572 | ||
573 | static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
574 | uint64_t value) | |
575 | { | |
29a0af61 | 576 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
577 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
578 | ||
e013b741 | 579 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); |
541ef8c2 SS |
580 | } |
581 | ||
582 | static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
583 | uint64_t value) | |
584 | { | |
29a0af61 | 585 | CPUState *cs = env_cpu(env); |
541ef8c2 SS |
586 | uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); |
587 | ||
a67cf277 | 588 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, |
e013b741 | 589 | ARMMMUIdxBit_E2); |
541ef8c2 SS |
590 | } |
591 | ||
575a94af RH |
592 | static void tlbiipas2_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, |
593 | uint64_t value) | |
594 | { | |
595 | CPUState *cs = env_cpu(env); | |
596 | uint64_t pageaddr = (value & MAKE_64BIT_MASK(0, 28)) << 12; | |
597 | ||
598 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2); | |
599 | } | |
600 | ||
601 | static void tlbiipas2is_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
602 | uint64_t value) | |
603 | { | |
604 | CPUState *cs = env_cpu(env); | |
605 | uint64_t pageaddr = (value & MAKE_64BIT_MASK(0, 28)) << 12; | |
606 | ||
607 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, ARMMMUIdxBit_Stage2); | |
608 | } | |
609 | ||
e9aa6c21 | 610 | static const ARMCPRegInfo cp_reginfo[] = { |
9b37a28c FR |
611 | /* |
612 | * Define the secure and non-secure FCSE identifier CP registers | |
54bf36ed FA |
613 | * separately because there is no secure bank in V8 (no _EL3). This allows |
614 | * the secure register to be properly reset and migrated. There is also no | |
615 | * v8 EL1 version of the register so the non-secure instance stands alone. | |
616 | */ | |
9c513e78 | 617 | { .name = "FCSEIDR", |
54bf36ed FA |
618 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
619 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS, | |
620 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns), | |
621 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, | |
9c513e78 | 622 | { .name = "FCSEIDR_S", |
54bf36ed FA |
623 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0, |
624 | .access = PL1_RW, .secure = ARM_CP_SECSTATE_S, | |
625 | .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s), | |
d4e6df63 | 626 | .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, }, |
9b37a28c FR |
627 | /* |
628 | * Define the secure and non-secure context identifier CP registers | |
54bf36ed FA |
629 | * separately because there is no secure bank in V8 (no _EL3). This allows |
630 | * the secure register to be properly reset and migrated. In the | |
631 | * non-secure case, the 32-bit register will have reset and migration | |
632 | * disabled during registration as it is handled by the 64-bit instance. | |
633 | */ | |
634 | { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
014406b5 | 635 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
84929218 | 636 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
158c276c | 637 | .fgt = FGT_CONTEXTIDR_EL1, |
84929218 | 638 | .secure = ARM_CP_SECSTATE_NS, |
54bf36ed FA |
639 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), |
640 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, | |
9c513e78 | 641 | { .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32, |
54bf36ed | 642 | .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
84929218 RH |
643 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
644 | .secure = ARM_CP_SECSTATE_S, | |
54bf36ed | 645 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s), |
d4e6df63 | 646 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, |
9449fdf6 PM |
647 | }; |
648 | ||
649 | static const ARMCPRegInfo not_v8_cp_reginfo[] = { | |
9b37a28c FR |
650 | /* |
651 | * NB: Some of these registers exist in v8 but with more precise | |
9449fdf6 PM |
652 | * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]). |
653 | */ | |
654 | /* MMU Domain access control / MPU write buffer control */ | |
0c17d68c FA |
655 | { .name = "DACR", |
656 | .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY, | |
84929218 | 657 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
0c17d68c FA |
658 | .writefn = dacr_write, .raw_writefn = raw_write, |
659 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
660 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
9b37a28c FR |
661 | /* |
662 | * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. | |
a903c449 | 663 | * For v6 and v5, these mappings are overly broad. |
4fdd17dd | 664 | */ |
a903c449 EI |
665 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0, |
666 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
667 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1, | |
668 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
669 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4, | |
670 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, | |
671 | { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8, | |
4fdd17dd | 672 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP }, |
c4804214 PM |
673 | /* Cache maintenance ops; some of this space may be overridden later. */ |
674 | { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, | |
675 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, | |
676 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE }, | |
e9aa6c21 PM |
677 | }; |
678 | ||
7d57f408 | 679 | static const ARMCPRegInfo not_v6_cp_reginfo[] = { |
9b37a28c FR |
680 | /* |
681 | * Not all pre-v6 cores implemented this WFI, so this is slightly | |
7d57f408 PM |
682 | * over-broad. |
683 | */ | |
684 | { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2, | |
685 | .access = PL1_W, .type = ARM_CP_WFI }, | |
7d57f408 PM |
686 | }; |
687 | ||
688 | static const ARMCPRegInfo not_v7_cp_reginfo[] = { | |
9b37a28c FR |
689 | /* |
690 | * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which | |
7d57f408 PM |
691 | * is UNPREDICTABLE; we choose to NOP as most implementations do). |
692 | */ | |
693 | { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
694 | .access = PL1_W, .type = ARM_CP_WFI }, | |
9b37a28c FR |
695 | /* |
696 | * L1 cache lockdown. Not architectural in v6 and earlier but in practice | |
34f90529 PM |
697 | * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and |
698 | * OMAPCP will override this space. | |
699 | */ | |
700 | { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0, | |
701 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data), | |
702 | .resetvalue = 0 }, | |
703 | { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1, | |
704 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn), | |
705 | .resetvalue = 0 }, | |
776d4e5c PM |
706 | /* v6 doesn't have the cache ID registers but Linux reads them anyway */ |
707 | { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY, | |
7a0e58fa | 708 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 709 | .resetvalue = 0 }, |
9b37a28c FR |
710 | /* |
711 | * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR; | |
50300698 PM |
712 | * implementing it as RAZ means the "debug architecture version" bits |
713 | * will read as a reserved value, which should cause Linux to not try | |
714 | * to use the debug hardware. | |
715 | */ | |
716 | { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, | |
717 | .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
9b37a28c FR |
718 | /* |
719 | * MMU TLB control. Note that the wildcarding means we cover not just | |
995939a6 PM |
720 | * the unified TLB ops but also the dside/iside/inner-shareable variants. |
721 | */ | |
722 | { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY, | |
723 | .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, | |
7a0e58fa | 724 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
725 | { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY, |
726 | .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, | |
7a0e58fa | 727 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
728 | { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY, |
729 | .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, | |
7a0e58fa | 730 | .type = ARM_CP_NO_RAW }, |
995939a6 PM |
731 | { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY, |
732 | .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, | |
7a0e58fa | 733 | .type = ARM_CP_NO_RAW }, |
a903c449 EI |
734 | { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2, |
735 | .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, | |
736 | { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2, | |
737 | .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP }, | |
7d57f408 PM |
738 | }; |
739 | ||
c4241c7d PM |
740 | static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
741 | uint64_t value) | |
2771db27 | 742 | { |
f0aff255 FA |
743 | uint32_t mask = 0; |
744 | ||
745 | /* In ARMv8 most bits of CPACR_EL1 are RES0. */ | |
746 | if (!arm_feature(env, ARM_FEATURE_V8)) { | |
9b37a28c FR |
747 | /* |
748 | * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. | |
f0aff255 FA |
749 | * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. |
750 | * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. | |
751 | */ | |
7fbc6a40 | 752 | if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { |
f0aff255 | 753 | /* VFP coprocessor: cp10 & cp11 [23:20] */ |
fab8ad39 RH |
754 | mask |= R_CPACR_ASEDIS_MASK | |
755 | R_CPACR_D32DIS_MASK | | |
756 | R_CPACR_CP11_MASK | | |
757 | R_CPACR_CP10_MASK; | |
f0aff255 FA |
758 | |
759 | if (!arm_feature(env, ARM_FEATURE_NEON)) { | |
760 | /* ASEDIS [31] bit is RAO/WI */ | |
fab8ad39 | 761 | value |= R_CPACR_ASEDIS_MASK; |
f0aff255 FA |
762 | } |
763 | ||
9b37a28c FR |
764 | /* |
765 | * VFPv3 and upwards with NEON implement 32 double precision | |
f0aff255 FA |
766 | * registers (D0-D31). |
767 | */ | |
a6627f5f | 768 | if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { |
f0aff255 | 769 | /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ |
fab8ad39 | 770 | value |= R_CPACR_D32DIS_MASK; |
f0aff255 FA |
771 | } |
772 | } | |
773 | value &= mask; | |
2771db27 | 774 | } |
fc1120a7 PM |
775 | |
776 | /* | |
777 | * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 | |
778 | * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. | |
779 | */ | |
780 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
781 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
fab8ad39 RH |
782 | mask = R_CPACR_CP11_MASK | R_CPACR_CP10_MASK; |
783 | value = (value & ~mask) | (env->cp15.cpacr_el1 & mask); | |
fc1120a7 PM |
784 | } |
785 | ||
7ebd5f2e | 786 | env->cp15.cpacr_el1 = value; |
2771db27 PM |
787 | } |
788 | ||
fc1120a7 PM |
789 | static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
790 | { | |
791 | /* | |
792 | * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10 | |
793 | * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. | |
794 | */ | |
795 | uint64_t value = env->cp15.cpacr_el1; | |
796 | ||
797 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
798 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
fab8ad39 | 799 | value = ~(R_CPACR_CP11_MASK | R_CPACR_CP10_MASK); |
fc1120a7 PM |
800 | } |
801 | return value; | |
802 | } | |
803 | ||
804 | ||
5deac39c PM |
805 | static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
806 | { | |
9b37a28c FR |
807 | /* |
808 | * Call cpacr_write() so that we reset with the correct RAO bits set | |
5deac39c PM |
809 | * for our CPU features. |
810 | */ | |
811 | cpacr_write(env, ri, 0); | |
812 | } | |
813 | ||
3f208fd7 PM |
814 | static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
815 | bool isread) | |
c6f19164 GB |
816 | { |
817 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
818 | /* Check if CPACR accesses are to be trapped to EL2 */ | |
e6ef0169 | 819 | if (arm_current_el(env) == 1 && arm_is_el2_enabled(env) && |
fab8ad39 | 820 | FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TCPAC)) { |
c6f19164 GB |
821 | return CP_ACCESS_TRAP_EL2; |
822 | /* Check if CPACR accesses are to be trapped to EL3 */ | |
823 | } else if (arm_current_el(env) < 3 && | |
fab8ad39 | 824 | FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { |
c6f19164 GB |
825 | return CP_ACCESS_TRAP_EL3; |
826 | } | |
827 | } | |
828 | ||
829 | return CP_ACCESS_OK; | |
830 | } | |
831 | ||
3f208fd7 PM |
832 | static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
833 | bool isread) | |
c6f19164 GB |
834 | { |
835 | /* Check if CPTR accesses are set to trap to EL3 */ | |
fab8ad39 RH |
836 | if (arm_current_el(env) == 2 && |
837 | FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { | |
c6f19164 GB |
838 | return CP_ACCESS_TRAP_EL3; |
839 | } | |
840 | ||
841 | return CP_ACCESS_OK; | |
842 | } | |
843 | ||
7d57f408 PM |
844 | static const ARMCPRegInfo v6_cp_reginfo[] = { |
845 | /* prefetch by MVA in v6, NOP in v7 */ | |
846 | { .name = "MVA_prefetch", | |
847 | .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1, | |
848 | .access = PL1_W, .type = ARM_CP_NOP }, | |
9b37a28c FR |
849 | /* |
850 | * We need to break the TB after ISB to execute self-modifying code | |
6df99dec SS |
851 | * correctly and also to take any pending interrupts immediately. |
852 | * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. | |
853 | */ | |
7d57f408 | 854 | { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, |
6df99dec | 855 | .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore }, |
091fd17c | 856 | { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, |
7d57f408 | 857 | .access = PL0_W, .type = ARM_CP_NOP }, |
091fd17c | 858 | { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, |
7d57f408 | 859 | .access = PL0_W, .type = ARM_CP_NOP }, |
06d76f31 | 860 | { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, |
84929218 | 861 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
b848ce2b FA |
862 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s), |
863 | offsetof(CPUARMState, cp15.ifar_ns) }, | |
06d76f31 | 864 | .resetvalue = 0, }, |
9b37a28c FR |
865 | /* |
866 | * Watchpoint Fault Address Register : should actually only be present | |
06d76f31 PM |
867 | * for 1136, 1176, 11MPCore. |
868 | */ | |
869 | { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
870 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, | |
34222fb8 | 871 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, |
c6f19164 | 872 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, |
b19ed03c | 873 | .fgt = FGT_CPACR_EL1, |
7ebd5f2e | 874 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), |
fc1120a7 | 875 | .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read }, |
7d57f408 PM |
876 | }; |
877 | ||
57a4a11b AL |
878 | typedef struct pm_event { |
879 | uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ | |
880 | /* If the event is supported on this CPU (used to generate PMCEID[01]) */ | |
881 | bool (*supported)(CPUARMState *); | |
882 | /* | |
883 | * Retrieve the current count of the underlying event. The programmed | |
884 | * counters hold a difference from the return value from this function | |
885 | */ | |
886 | uint64_t (*get_count)(CPUARMState *); | |
4e7beb0c AL |
887 | /* |
888 | * Return how many nanoseconds it will take (at a minimum) for count events | |
889 | * to occur. A negative value indicates the counter will never overflow, or | |
890 | * that the counter has otherwise arranged for the overflow bit to be set | |
891 | * and the PMU interrupt to be raised on overflow. | |
892 | */ | |
893 | int64_t (*ns_per_count)(uint64_t); | |
57a4a11b AL |
894 | } pm_event; |
895 | ||
b2e23725 AL |
896 | static bool event_always_supported(CPUARMState *env) |
897 | { | |
898 | return true; | |
899 | } | |
900 | ||
0d4bfd7d AL |
901 | static uint64_t swinc_get_count(CPUARMState *env) |
902 | { | |
903 | /* | |
904 | * SW_INCR events are written directly to the pmevcntr's by writes to | |
905 | * PMSWINC, so there is no underlying count maintained by the PMU itself | |
906 | */ | |
907 | return 0; | |
908 | } | |
909 | ||
4e7beb0c AL |
910 | static int64_t swinc_ns_per(uint64_t ignored) |
911 | { | |
912 | return -1; | |
913 | } | |
914 | ||
b2e23725 AL |
915 | /* |
916 | * Return the underlying cycle count for the PMU cycle counters. If we're in | |
917 | * usermode, simply return 0. | |
918 | */ | |
919 | static uint64_t cycles_get_count(CPUARMState *env) | |
920 | { | |
921 | #ifndef CONFIG_USER_ONLY | |
922 | return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
923 | ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); | |
924 | #else | |
925 | return cpu_get_host_ticks(); | |
926 | #endif | |
927 | } | |
928 | ||
929 | #ifndef CONFIG_USER_ONLY | |
4e7beb0c AL |
930 | static int64_t cycles_ns_per(uint64_t cycles) |
931 | { | |
932 | return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles; | |
933 | } | |
934 | ||
b2e23725 AL |
935 | static bool instructions_supported(CPUARMState *env) |
936 | { | |
740b1759 | 937 | return icount_enabled() == 1; /* Precise instruction counting */ |
b2e23725 AL |
938 | } |
939 | ||
940 | static uint64_t instructions_get_count(CPUARMState *env) | |
941 | { | |
8191d368 | 942 | return (uint64_t)icount_get_raw(); |
b2e23725 | 943 | } |
4e7beb0c AL |
944 | |
945 | static int64_t instructions_ns_per(uint64_t icount) | |
946 | { | |
8191d368 | 947 | return icount_to_ns((int64_t)icount); |
4e7beb0c | 948 | } |
b2e23725 AL |
949 | #endif |
950 | ||
a793bcd0 | 951 | static bool pmuv3p1_events_supported(CPUARMState *env) |
0727f63b PM |
952 | { |
953 | /* For events which are supported in any v8.1 PMU */ | |
a793bcd0 | 954 | return cpu_isar_feature(any_pmuv3p1, env_archcpu(env)); |
0727f63b PM |
955 | } |
956 | ||
a793bcd0 | 957 | static bool pmuv3p4_events_supported(CPUARMState *env) |
15dd1ebd PM |
958 | { |
959 | /* For events which are supported in any v8.1 PMU */ | |
a793bcd0 | 960 | return cpu_isar_feature(any_pmuv3p4, env_archcpu(env)); |
15dd1ebd PM |
961 | } |
962 | ||
0727f63b PM |
963 | static uint64_t zero_event_get_count(CPUARMState *env) |
964 | { | |
965 | /* For events which on QEMU never fire, so their count is always zero */ | |
966 | return 0; | |
967 | } | |
968 | ||
969 | static int64_t zero_event_ns_per(uint64_t cycles) | |
970 | { | |
971 | /* An event which never fires can never overflow */ | |
972 | return -1; | |
973 | } | |
974 | ||
57a4a11b | 975 | static const pm_event pm_events[] = { |
0d4bfd7d AL |
976 | { .number = 0x000, /* SW_INCR */ |
977 | .supported = event_always_supported, | |
978 | .get_count = swinc_get_count, | |
4e7beb0c | 979 | .ns_per_count = swinc_ns_per, |
0d4bfd7d | 980 | }, |
b2e23725 AL |
981 | #ifndef CONFIG_USER_ONLY |
982 | { .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */ | |
983 | .supported = instructions_supported, | |
984 | .get_count = instructions_get_count, | |
4e7beb0c | 985 | .ns_per_count = instructions_ns_per, |
b2e23725 AL |
986 | }, |
987 | { .number = 0x011, /* CPU_CYCLES, Cycle */ | |
988 | .supported = event_always_supported, | |
989 | .get_count = cycles_get_count, | |
4e7beb0c | 990 | .ns_per_count = cycles_ns_per, |
0727f63b | 991 | }, |
b2e23725 | 992 | #endif |
0727f63b | 993 | { .number = 0x023, /* STALL_FRONTEND */ |
a793bcd0 | 994 | .supported = pmuv3p1_events_supported, |
0727f63b PM |
995 | .get_count = zero_event_get_count, |
996 | .ns_per_count = zero_event_ns_per, | |
997 | }, | |
998 | { .number = 0x024, /* STALL_BACKEND */ | |
a793bcd0 | 999 | .supported = pmuv3p1_events_supported, |
0727f63b PM |
1000 | .get_count = zero_event_get_count, |
1001 | .ns_per_count = zero_event_ns_per, | |
1002 | }, | |
15dd1ebd | 1003 | { .number = 0x03c, /* STALL */ |
a793bcd0 | 1004 | .supported = pmuv3p4_events_supported, |
15dd1ebd PM |
1005 | .get_count = zero_event_get_count, |
1006 | .ns_per_count = zero_event_ns_per, | |
1007 | }, | |
57a4a11b AL |
1008 | }; |
1009 | ||
1010 | /* | |
1011 | * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of | |
1012 | * events (i.e. the statistical profiling extension), this implementation | |
1013 | * should first be updated to something sparse instead of the current | |
1014 | * supported_event_map[] array. | |
1015 | */ | |
15dd1ebd | 1016 | #define MAX_EVENT_ID 0x3c |
57a4a11b AL |
1017 | #define UNSUPPORTED_EVENT UINT16_MAX |
1018 | static uint16_t supported_event_map[MAX_EVENT_ID + 1]; | |
1019 | ||
1020 | /* | |
bf8d0969 AL |
1021 | * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map |
1022 | * of ARM event numbers to indices in our pm_events array. | |
57a4a11b AL |
1023 | * |
1024 | * Note: Events in the 0x40XX range are not currently supported. | |
1025 | */ | |
bf8d0969 | 1026 | void pmu_init(ARMCPU *cpu) |
57a4a11b | 1027 | { |
57a4a11b AL |
1028 | unsigned int i; |
1029 | ||
bf8d0969 AL |
1030 | /* |
1031 | * Empty supported_event_map and cpu->pmceid[01] before adding supported | |
1032 | * events to them | |
1033 | */ | |
57a4a11b AL |
1034 | for (i = 0; i < ARRAY_SIZE(supported_event_map); i++) { |
1035 | supported_event_map[i] = UNSUPPORTED_EVENT; | |
1036 | } | |
bf8d0969 AL |
1037 | cpu->pmceid0 = 0; |
1038 | cpu->pmceid1 = 0; | |
57a4a11b AL |
1039 | |
1040 | for (i = 0; i < ARRAY_SIZE(pm_events); i++) { | |
1041 | const pm_event *cnt = &pm_events[i]; | |
1042 | assert(cnt->number <= MAX_EVENT_ID); | |
1043 | /* We do not currently support events in the 0x40xx range */ | |
1044 | assert(cnt->number <= 0x3f); | |
1045 | ||
bf8d0969 | 1046 | if (cnt->supported(&cpu->env)) { |
57a4a11b | 1047 | supported_event_map[cnt->number] = i; |
67da43d6 | 1048 | uint64_t event_mask = 1ULL << (cnt->number & 0x1f); |
bf8d0969 AL |
1049 | if (cnt->number & 0x20) { |
1050 | cpu->pmceid1 |= event_mask; | |
1051 | } else { | |
1052 | cpu->pmceid0 |= event_mask; | |
1053 | } | |
57a4a11b AL |
1054 | } |
1055 | } | |
57a4a11b AL |
1056 | } |
1057 | ||
5ecdd3e4 AL |
1058 | /* |
1059 | * Check at runtime whether a PMU event is supported for the current machine | |
1060 | */ | |
1061 | static bool event_supported(uint16_t number) | |
1062 | { | |
1063 | if (number > MAX_EVENT_ID) { | |
1064 | return false; | |
1065 | } | |
1066 | return supported_event_map[number] != UNSUPPORTED_EVENT; | |
1067 | } | |
1068 | ||
3f208fd7 PM |
1069 | static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri, |
1070 | bool isread) | |
200ac0ef | 1071 | { |
9b37a28c FR |
1072 | /* |
1073 | * Performance monitor registers user accessibility is controlled | |
1fce1ba9 PM |
1074 | * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable |
1075 | * trapping to EL2 or EL3 for other accesses. | |
200ac0ef | 1076 | */ |
1fce1ba9 | 1077 | int el = arm_current_el(env); |
59dd089c | 1078 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
1fce1ba9 | 1079 | |
6ecd0b6b | 1080 | if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) { |
fcd25206 | 1081 | return CP_ACCESS_TRAP; |
200ac0ef | 1082 | } |
59dd089c | 1083 | if (el < 2 && (mdcr_el2 & MDCR_TPM)) { |
1fce1ba9 PM |
1084 | return CP_ACCESS_TRAP_EL2; |
1085 | } | |
1086 | if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { | |
1087 | return CP_ACCESS_TRAP_EL3; | |
1088 | } | |
1089 | ||
fcd25206 | 1090 | return CP_ACCESS_OK; |
200ac0ef PM |
1091 | } |
1092 | ||
6ecd0b6b AB |
1093 | static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, |
1094 | const ARMCPRegInfo *ri, | |
1095 | bool isread) | |
1096 | { | |
1097 | /* ER: event counter read trap control */ | |
1098 | if (arm_feature(env, ARM_FEATURE_V8) | |
1099 | && arm_current_el(env) == 0 | |
1100 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0 | |
1101 | && isread) { | |
1102 | return CP_ACCESS_OK; | |
1103 | } | |
1104 | ||
1105 | return pmreg_access(env, ri, isread); | |
1106 | } | |
1107 | ||
1108 | static CPAccessResult pmreg_access_swinc(CPUARMState *env, | |
1109 | const ARMCPRegInfo *ri, | |
1110 | bool isread) | |
1111 | { | |
1112 | /* SW: software increment write trap control */ | |
1113 | if (arm_feature(env, ARM_FEATURE_V8) | |
1114 | && arm_current_el(env) == 0 | |
1115 | && (env->cp15.c9_pmuserenr & (1 << 1)) != 0 | |
1116 | && !isread) { | |
1117 | return CP_ACCESS_OK; | |
1118 | } | |
1119 | ||
1120 | return pmreg_access(env, ri, isread); | |
1121 | } | |
1122 | ||
6ecd0b6b AB |
1123 | static CPAccessResult pmreg_access_selr(CPUARMState *env, |
1124 | const ARMCPRegInfo *ri, | |
1125 | bool isread) | |
1126 | { | |
1127 | /* ER: event counter read trap control */ | |
1128 | if (arm_feature(env, ARM_FEATURE_V8) | |
1129 | && arm_current_el(env) == 0 | |
1130 | && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) { | |
1131 | return CP_ACCESS_OK; | |
1132 | } | |
1133 | ||
1134 | return pmreg_access(env, ri, isread); | |
1135 | } | |
1136 | ||
1137 | static CPAccessResult pmreg_access_ccntr(CPUARMState *env, | |
1138 | const ARMCPRegInfo *ri, | |
1139 | bool isread) | |
1140 | { | |
1141 | /* CR: cycle counter read trap control */ | |
1142 | if (arm_feature(env, ARM_FEATURE_V8) | |
1143 | && arm_current_el(env) == 0 | |
1144 | && (env->cp15.c9_pmuserenr & (1 << 2)) != 0 | |
1145 | && isread) { | |
1146 | return CP_ACCESS_OK; | |
1147 | } | |
1148 | ||
1149 | return pmreg_access(env, ri, isread); | |
1150 | } | |
1151 | ||
01765386 PM |
1152 | /* |
1153 | * Bits in MDCR_EL2 and MDCR_EL3 which pmu_counter_enabled() looks at. | |
1154 | * We use these to decide whether we need to wrap a write to MDCR_EL2 | |
1155 | * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls. | |
1156 | */ | |
47b385da PM |
1157 | #define MDCR_EL2_PMU_ENABLE_BITS \ |
1158 | (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP) | |
0b42f4fa | 1159 | #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD) |
01765386 | 1160 | |
9b37a28c FR |
1161 | /* |
1162 | * Returns true if the counter (pass 31 for PMCCNTR) should count events using | |
033614c4 AL |
1163 | * the current EL, security state, and register configuration. |
1164 | */ | |
1165 | static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) | |
87124fde | 1166 | { |
033614c4 AL |
1167 | uint64_t filter; |
1168 | bool e, p, u, nsk, nsu, nsh, m; | |
872d2034 | 1169 | bool enabled, prohibited = false, filtered; |
033614c4 AL |
1170 | bool secure = arm_is_secure(env); |
1171 | int el = arm_current_el(env); | |
59dd089c RDC |
1172 | uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
1173 | uint8_t hpmn = mdcr_el2 & MDCR_HPMN; | |
87124fde | 1174 | |
cbbb3041 AJ |
1175 | if (!arm_feature(env, ARM_FEATURE_PMU)) { |
1176 | return false; | |
1177 | } | |
1178 | ||
033614c4 AL |
1179 | if (!arm_feature(env, ARM_FEATURE_EL2) || |
1180 | (counter < hpmn || counter == 31)) { | |
1181 | e = env->cp15.c9_pmcr & PMCRE; | |
1182 | } else { | |
59dd089c | 1183 | e = mdcr_el2 & MDCR_HPME; |
87124fde | 1184 | } |
033614c4 | 1185 | enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); |
87124fde | 1186 | |
872d2034 PM |
1187 | /* Is event counting prohibited? */ |
1188 | if (el == 2 && (counter < hpmn || counter == 31)) { | |
1189 | prohibited = mdcr_el2 & MDCR_HPMD; | |
1190 | } | |
1191 | if (secure) { | |
1192 | prohibited = prohibited || !(env->cp15.mdcr_el3 & MDCR_SPME); | |
033614c4 AL |
1193 | } |
1194 | ||
0b42f4fa PM |
1195 | if (counter == 31) { |
1196 | /* | |
1197 | * The cycle counter defaults to running. PMCR.DP says "disable | |
1198 | * the cycle counter when event counting is prohibited". | |
1199 | * Some MDCR bits disable the cycle counter specifically. | |
1200 | */ | |
1201 | prohibited = prohibited && env->cp15.c9_pmcr & PMCRDP; | |
1202 | if (cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { | |
1203 | if (secure) { | |
1204 | prohibited = prohibited || (env->cp15.mdcr_el3 & MDCR_SCCD); | |
1205 | } | |
1206 | if (el == 2) { | |
1207 | prohibited = prohibited || (mdcr_el2 & MDCR_HCCD); | |
1208 | } | |
1209 | } | |
033614c4 AL |
1210 | } |
1211 | ||
5ecdd3e4 AL |
1212 | if (counter == 31) { |
1213 | filter = env->cp15.pmccfiltr_el0; | |
1214 | } else { | |
1215 | filter = env->cp15.c14_pmevtyper[counter]; | |
1216 | } | |
033614c4 AL |
1217 | |
1218 | p = filter & PMXEVTYPER_P; | |
1219 | u = filter & PMXEVTYPER_U; | |
1220 | nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); | |
1221 | nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); | |
1222 | nsh = arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); | |
1223 | m = arm_el_is_aa64(env, 1) && | |
1224 | arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); | |
1225 | ||
1226 | if (el == 0) { | |
1227 | filtered = secure ? u : u != nsu; | |
1228 | } else if (el == 1) { | |
1229 | filtered = secure ? p : p != nsk; | |
1230 | } else if (el == 2) { | |
1231 | filtered = !nsh; | |
1232 | } else { /* EL3 */ | |
1233 | filtered = m != p; | |
1234 | } | |
1235 | ||
5ecdd3e4 AL |
1236 | if (counter != 31) { |
1237 | /* | |
1238 | * If not checking PMCCNTR, ensure the counter is setup to an event we | |
1239 | * support | |
1240 | */ | |
1241 | uint16_t event = filter & PMXEVTYPER_EVTCOUNT; | |
1242 | if (!event_supported(event)) { | |
1243 | return false; | |
1244 | } | |
1245 | } | |
1246 | ||
033614c4 | 1247 | return enabled && !prohibited && !filtered; |
87124fde | 1248 | } |
033614c4 | 1249 | |
f4efb4b2 AL |
1250 | static void pmu_update_irq(CPUARMState *env) |
1251 | { | |
2fc0cc0e | 1252 | ARMCPU *cpu = env_archcpu(env); |
f4efb4b2 AL |
1253 | qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && |
1254 | (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); | |
1255 | } | |
1256 | ||
b57aa7bd PM |
1257 | static bool pmccntr_clockdiv_enabled(CPUARMState *env) |
1258 | { | |
1259 | /* | |
1260 | * Return true if the clock divider is enabled and the cycle counter | |
1261 | * is supposed to tick only once every 64 clock cycles. This is | |
1262 | * controlled by PMCR.D, but if PMCR.LC is set to enable the long | |
1263 | * (64-bit) cycle counter PMCR.D has no effect. | |
1264 | */ | |
1265 | return (env->cp15.c9_pmcr & (PMCRD | PMCRLC)) == PMCRD; | |
1266 | } | |
1267 | ||
47b385da PM |
1268 | static bool pmevcntr_is_64_bit(CPUARMState *env, int counter) |
1269 | { | |
1270 | /* Return true if the specified event counter is configured to be 64 bit */ | |
1271 | ||
1272 | /* This isn't intended to be used with the cycle counter */ | |
1273 | assert(counter < 31); | |
1274 | ||
1275 | if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { | |
1276 | return false; | |
1277 | } | |
1278 | ||
1279 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
1280 | /* | |
1281 | * MDCR_EL2.HLP still applies even when EL2 is disabled in the | |
1282 | * current security state, so we don't use arm_mdcr_el2_eff() here. | |
1283 | */ | |
1284 | bool hlp = env->cp15.mdcr_el2 & MDCR_HLP; | |
1285 | int hpmn = env->cp15.mdcr_el2 & MDCR_HPMN; | |
1286 | ||
3d80bbf1 | 1287 | if (counter >= hpmn) { |
47b385da PM |
1288 | return hlp; |
1289 | } | |
1290 | } | |
1291 | return env->cp15.c9_pmcr & PMCRLP; | |
1292 | } | |
1293 | ||
5d05b9d4 AL |
1294 | /* |
1295 | * Ensure c15_ccnt is the guest-visible count so that operations such as | |
1296 | * enabling/disabling the counter or filtering, modifying the count itself, | |
1297 | * etc. can be done logically. This is essentially a no-op if the counter is | |
1298 | * not enabled at the time of the call. | |
1299 | */ | |
f2b2f53f | 1300 | static void pmccntr_op_start(CPUARMState *env) |
ec7b4ce4 | 1301 | { |
b2e23725 | 1302 | uint64_t cycles = cycles_get_count(env); |
ec7b4ce4 | 1303 | |
033614c4 | 1304 | if (pmu_counter_enabled(env, 31)) { |
5d05b9d4 | 1305 | uint64_t eff_cycles = cycles; |
b57aa7bd | 1306 | if (pmccntr_clockdiv_enabled(env)) { |
5d05b9d4 AL |
1307 | eff_cycles /= 64; |
1308 | } | |
1309 | ||
f4efb4b2 AL |
1310 | uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta; |
1311 | ||
1312 | uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \ | |
1313 | 1ull << 63 : 1ull << 31; | |
1314 | if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { | |
76e25d41 | 1315 | env->cp15.c9_pmovsr |= (1ULL << 31); |
f4efb4b2 AL |
1316 | pmu_update_irq(env); |
1317 | } | |
1318 | ||
1319 | env->cp15.c15_ccnt = new_pmccntr; | |
ec7b4ce4 | 1320 | } |
5d05b9d4 AL |
1321 | env->cp15.c15_ccnt_delta = cycles; |
1322 | } | |
ec7b4ce4 | 1323 | |
5d05b9d4 AL |
1324 | /* |
1325 | * If PMCCNTR is enabled, recalculate the delta between the clock and the | |
1326 | * guest-visible count. A call to pmccntr_op_finish should follow every call to | |
1327 | * pmccntr_op_start. | |
1328 | */ | |
f2b2f53f | 1329 | static void pmccntr_op_finish(CPUARMState *env) |
5d05b9d4 | 1330 | { |
033614c4 | 1331 | if (pmu_counter_enabled(env, 31)) { |
4e7beb0c AL |
1332 | #ifndef CONFIG_USER_ONLY |
1333 | /* Calculate when the counter will next overflow */ | |
1334 | uint64_t remaining_cycles = -env->cp15.c15_ccnt; | |
1335 | if (!(env->cp15.c9_pmcr & PMCRLC)) { | |
1336 | remaining_cycles = (uint32_t)remaining_cycles; | |
1337 | } | |
1338 | int64_t overflow_in = cycles_ns_per(remaining_cycles); | |
1339 | ||
1340 | if (overflow_in > 0) { | |
f1dd2506 PM |
1341 | int64_t overflow_at; |
1342 | ||
1343 | if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
1344 | overflow_in, &overflow_at)) { | |
1345 | ARMCPU *cpu = env_archcpu(env); | |
1346 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); | |
1347 | } | |
4e7beb0c AL |
1348 | } |
1349 | #endif | |
5d05b9d4 | 1350 | |
4e7beb0c | 1351 | uint64_t prev_cycles = env->cp15.c15_ccnt_delta; |
b57aa7bd | 1352 | if (pmccntr_clockdiv_enabled(env)) { |
5d05b9d4 AL |
1353 | prev_cycles /= 64; |
1354 | } | |
5d05b9d4 | 1355 | env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt; |
ec7b4ce4 AF |
1356 | } |
1357 | } | |
1358 | ||
5ecdd3e4 AL |
1359 | static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) |
1360 | { | |
1361 | ||
1362 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; | |
1363 | uint64_t count = 0; | |
1364 | if (event_supported(event)) { | |
1365 | uint16_t event_idx = supported_event_map[event]; | |
1366 | count = pm_events[event_idx].get_count(env); | |
1367 | } | |
1368 | ||
1369 | if (pmu_counter_enabled(env, counter)) { | |
47b385da PM |
1370 | uint64_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter]; |
1371 | uint64_t overflow_mask = pmevcntr_is_64_bit(env, counter) ? | |
1372 | 1ULL << 63 : 1ULL << 31; | |
f4efb4b2 | 1373 | |
47b385da | 1374 | if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & overflow_mask) { |
f4efb4b2 AL |
1375 | env->cp15.c9_pmovsr |= (1 << counter); |
1376 | pmu_update_irq(env); | |
1377 | } | |
1378 | env->cp15.c14_pmevcntr[counter] = new_pmevcntr; | |
5ecdd3e4 AL |
1379 | } |
1380 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1381 | } | |
1382 | ||
1383 | static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) | |
1384 | { | |
1385 | if (pmu_counter_enabled(env, counter)) { | |
4e7beb0c AL |
1386 | #ifndef CONFIG_USER_ONLY |
1387 | uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; | |
1388 | uint16_t event_idx = supported_event_map[event]; | |
47b385da PM |
1389 | uint64_t delta = -(env->cp15.c14_pmevcntr[counter] + 1); |
1390 | int64_t overflow_in; | |
1391 | ||
1392 | if (!pmevcntr_is_64_bit(env, counter)) { | |
1393 | delta = (uint32_t)delta; | |
1394 | } | |
1395 | overflow_in = pm_events[event_idx].ns_per_count(delta); | |
4e7beb0c AL |
1396 | |
1397 | if (overflow_in > 0) { | |
f1dd2506 PM |
1398 | int64_t overflow_at; |
1399 | ||
1400 | if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), | |
1401 | overflow_in, &overflow_at)) { | |
1402 | ARMCPU *cpu = env_archcpu(env); | |
1403 | timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); | |
1404 | } | |
4e7beb0c AL |
1405 | } |
1406 | #endif | |
1407 | ||
5ecdd3e4 AL |
1408 | env->cp15.c14_pmevcntr_delta[counter] -= |
1409 | env->cp15.c14_pmevcntr[counter]; | |
1410 | } | |
1411 | } | |
1412 | ||
5d05b9d4 AL |
1413 | void pmu_op_start(CPUARMState *env) |
1414 | { | |
5ecdd3e4 | 1415 | unsigned int i; |
5d05b9d4 | 1416 | pmccntr_op_start(env); |
5ecdd3e4 AL |
1417 | for (i = 0; i < pmu_num_counters(env); i++) { |
1418 | pmevcntr_op_start(env, i); | |
1419 | } | |
5d05b9d4 AL |
1420 | } |
1421 | ||
1422 | void pmu_op_finish(CPUARMState *env) | |
1423 | { | |
5ecdd3e4 | 1424 | unsigned int i; |
5d05b9d4 | 1425 | pmccntr_op_finish(env); |
5ecdd3e4 AL |
1426 | for (i = 0; i < pmu_num_counters(env); i++) { |
1427 | pmevcntr_op_finish(env, i); | |
1428 | } | |
5d05b9d4 AL |
1429 | } |
1430 | ||
033614c4 AL |
1431 | void pmu_pre_el_change(ARMCPU *cpu, void *ignored) |
1432 | { | |
1433 | pmu_op_start(&cpu->env); | |
1434 | } | |
1435 | ||
1436 | void pmu_post_el_change(ARMCPU *cpu, void *ignored) | |
1437 | { | |
1438 | pmu_op_finish(&cpu->env); | |
1439 | } | |
1440 | ||
4e7beb0c AL |
1441 | void arm_pmu_timer_cb(void *opaque) |
1442 | { | |
1443 | ARMCPU *cpu = opaque; | |
1444 | ||
1445 | /* | |
1446 | * Update all the counter values based on the current underlying counts, | |
1447 | * triggering interrupts to be raised, if necessary. pmu_op_finish() also | |
1448 | * has the effect of setting the cpu->pmu_timer to the next earliest time a | |
1449 | * counter may expire. | |
1450 | */ | |
1451 | pmu_op_start(&cpu->env); | |
1452 | pmu_op_finish(&cpu->env); | |
1453 | } | |
1454 | ||
c4241c7d PM |
1455 | static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1456 | uint64_t value) | |
200ac0ef | 1457 | { |
5d05b9d4 | 1458 | pmu_op_start(env); |
7c2cb42b AF |
1459 | |
1460 | if (value & PMCRC) { | |
1461 | /* The counter has been reset */ | |
1462 | env->cp15.c15_ccnt = 0; | |
1463 | } | |
1464 | ||
5ecdd3e4 AL |
1465 | if (value & PMCRP) { |
1466 | unsigned int i; | |
1467 | for (i = 0; i < pmu_num_counters(env); i++) { | |
1468 | env->cp15.c14_pmevcntr[i] = 0; | |
1469 | } | |
1470 | } | |
1471 | ||
9323e79f PM |
1472 | env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; |
1473 | env->cp15.c9_pmcr |= (value & PMCR_WRITABLE_MASK); | |
7c2cb42b | 1474 | |
5d05b9d4 | 1475 | pmu_op_finish(env); |
7c2cb42b AF |
1476 | } |
1477 | ||
6980c31d JPB |
1478 | static uint64_t pmcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1479 | { | |
1480 | uint64_t pmcr = env->cp15.c9_pmcr; | |
1481 | ||
1482 | /* | |
1483 | * If EL2 is implemented and enabled for the current security state, reads | |
1484 | * of PMCR.N from EL1 or EL0 return the value of MDCR_EL2.HPMN or HDCR.HPMN. | |
1485 | */ | |
1486 | if (arm_current_el(env) <= 1 && arm_is_el2_enabled(env)) { | |
1487 | pmcr &= ~PMCRN_MASK; | |
1488 | pmcr |= (env->cp15.mdcr_el2 & MDCR_HPMN) << PMCRN_SHIFT; | |
1489 | } | |
1490 | ||
1491 | return pmcr; | |
1492 | } | |
1493 | ||
0d4bfd7d AL |
1494 | static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1495 | uint64_t value) | |
1496 | { | |
1497 | unsigned int i; | |
47b385da PM |
1498 | uint64_t overflow_mask, new_pmswinc; |
1499 | ||
0d4bfd7d AL |
1500 | for (i = 0; i < pmu_num_counters(env); i++) { |
1501 | /* Increment a counter's count iff: */ | |
1502 | if ((value & (1 << i)) && /* counter's bit is set */ | |
1503 | /* counter is enabled and not filtered */ | |
1504 | pmu_counter_enabled(env, i) && | |
1505 | /* counter is SW_INCR */ | |
1506 | (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) { | |
1507 | pmevcntr_op_start(env, i); | |
f4efb4b2 AL |
1508 | |
1509 | /* | |
1510 | * Detect if this write causes an overflow since we can't predict | |
1511 | * PMSWINC overflows like we can for other events | |
1512 | */ | |
47b385da PM |
1513 | new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; |
1514 | ||
1515 | overflow_mask = pmevcntr_is_64_bit(env, i) ? | |
1516 | 1ULL << 63 : 1ULL << 31; | |
f4efb4b2 | 1517 | |
47b385da | 1518 | if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & overflow_mask) { |
f4efb4b2 AL |
1519 | env->cp15.c9_pmovsr |= (1 << i); |
1520 | pmu_update_irq(env); | |
1521 | } | |
1522 | ||
1523 | env->cp15.c14_pmevcntr[i] = new_pmswinc; | |
1524 | ||
0d4bfd7d AL |
1525 | pmevcntr_op_finish(env, i); |
1526 | } | |
1527 | } | |
1528 | } | |
1529 | ||
7c2cb42b AF |
1530 | static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1531 | { | |
5d05b9d4 AL |
1532 | uint64_t ret; |
1533 | pmccntr_op_start(env); | |
1534 | ret = env->cp15.c15_ccnt; | |
1535 | pmccntr_op_finish(env); | |
1536 | return ret; | |
7c2cb42b AF |
1537 | } |
1538 | ||
6b040780 WH |
1539 | static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1540 | uint64_t value) | |
1541 | { | |
9b37a28c FR |
1542 | /* |
1543 | * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and | |
6b040780 WH |
1544 | * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the |
1545 | * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are | |
1546 | * accessed. | |
1547 | */ | |
1548 | env->cp15.c9_pmselr = value & 0x1f; | |
1549 | } | |
1550 | ||
7c2cb42b AF |
1551 | static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1552 | uint64_t value) | |
1553 | { | |
5d05b9d4 AL |
1554 | pmccntr_op_start(env); |
1555 | env->cp15.c15_ccnt = value; | |
1556 | pmccntr_op_finish(env); | |
200ac0ef | 1557 | } |
421c7ebd PC |
1558 | |
1559 | static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1560 | uint64_t value) | |
1561 | { | |
1562 | uint64_t cur_val = pmccntr_read(env, NULL); | |
1563 | ||
1564 | pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); | |
1565 | } | |
1566 | ||
0614601c AF |
1567 | static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1568 | uint64_t value) | |
1569 | { | |
5d05b9d4 | 1570 | pmccntr_op_start(env); |
4b8afa1f AL |
1571 | env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0; |
1572 | pmccntr_op_finish(env); | |
1573 | } | |
1574 | ||
1575 | static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, | |
1576 | uint64_t value) | |
1577 | { | |
1578 | pmccntr_op_start(env); | |
1579 | /* M is not accessible from AArch32 */ | |
1580 | env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | | |
1581 | (value & PMCCFILTR); | |
5d05b9d4 | 1582 | pmccntr_op_finish(env); |
0614601c AF |
1583 | } |
1584 | ||
4b8afa1f AL |
1585 | static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri) |
1586 | { | |
1587 | /* M is not visible in AArch32 */ | |
1588 | return env->cp15.pmccfiltr_el0 & PMCCFILTR; | |
1589 | } | |
1590 | ||
c4241c7d | 1591 | static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1592 | uint64_t value) |
1593 | { | |
01765386 | 1594 | pmu_op_start(env); |
7ece99b1 | 1595 | value &= pmu_counter_mask(env); |
200ac0ef | 1596 | env->cp15.c9_pmcnten |= value; |
01765386 | 1597 | pmu_op_finish(env); |
200ac0ef PM |
1598 | } |
1599 | ||
c4241c7d PM |
1600 | static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1601 | uint64_t value) | |
200ac0ef | 1602 | { |
01765386 | 1603 | pmu_op_start(env); |
7ece99b1 | 1604 | value &= pmu_counter_mask(env); |
200ac0ef | 1605 | env->cp15.c9_pmcnten &= ~value; |
01765386 | 1606 | pmu_op_finish(env); |
200ac0ef PM |
1607 | } |
1608 | ||
c4241c7d PM |
1609 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1610 | uint64_t value) | |
200ac0ef | 1611 | { |
599b71e2 | 1612 | value &= pmu_counter_mask(env); |
200ac0ef | 1613 | env->cp15.c9_pmovsr &= ~value; |
f4efb4b2 | 1614 | pmu_update_irq(env); |
200ac0ef PM |
1615 | } |
1616 | ||
327dd510 AL |
1617 | static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1618 | uint64_t value) | |
1619 | { | |
1620 | value &= pmu_counter_mask(env); | |
1621 | env->cp15.c9_pmovsr |= value; | |
f4efb4b2 | 1622 | pmu_update_irq(env); |
327dd510 AL |
1623 | } |
1624 | ||
5ecdd3e4 AL |
1625 | static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1626 | uint64_t value, const uint8_t counter) | |
200ac0ef | 1627 | { |
5ecdd3e4 AL |
1628 | if (counter == 31) { |
1629 | pmccfiltr_write(env, ri, value); | |
1630 | } else if (counter < pmu_num_counters(env)) { | |
1631 | pmevcntr_op_start(env, counter); | |
1632 | ||
1633 | /* | |
1634 | * If this counter's event type is changing, store the current | |
1635 | * underlying count for the new type in c14_pmevcntr_delta[counter] so | |
1636 | * pmevcntr_op_finish has the correct baseline when it converts back to | |
1637 | * a delta. | |
1638 | */ | |
1639 | uint16_t old_event = env->cp15.c14_pmevtyper[counter] & | |
1640 | PMXEVTYPER_EVTCOUNT; | |
1641 | uint16_t new_event = value & PMXEVTYPER_EVTCOUNT; | |
1642 | if (old_event != new_event) { | |
1643 | uint64_t count = 0; | |
1644 | if (event_supported(new_event)) { | |
1645 | uint16_t event_idx = supported_event_map[new_event]; | |
1646 | count = pm_events[event_idx].get_count(env); | |
1647 | } | |
1648 | env->cp15.c14_pmevcntr_delta[counter] = count; | |
1649 | } | |
1650 | ||
1651 | env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK; | |
1652 | pmevcntr_op_finish(env, counter); | |
1653 | } | |
9b37a28c FR |
1654 | /* |
1655 | * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when | |
fdb86656 WH |
1656 | * PMSELR value is equal to or greater than the number of implemented |
1657 | * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. | |
1658 | */ | |
5ecdd3e4 AL |
1659 | } |
1660 | ||
1661 | static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1662 | const uint8_t counter) | |
1663 | { | |
1664 | if (counter == 31) { | |
1665 | return env->cp15.pmccfiltr_el0; | |
1666 | } else if (counter < pmu_num_counters(env)) { | |
1667 | return env->cp15.c14_pmevtyper[counter]; | |
1668 | } else { | |
1669 | /* | |
1670 | * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER | |
1671 | * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). | |
1672 | */ | |
1673 | return 0; | |
1674 | } | |
1675 | } | |
1676 | ||
1677 | static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, | |
1678 | uint64_t value) | |
1679 | { | |
1680 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1681 | pmevtyper_write(env, ri, value, counter); | |
1682 | } | |
1683 | ||
1684 | static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1685 | uint64_t value) | |
1686 | { | |
1687 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1688 | env->cp15.c14_pmevtyper[counter] = value; | |
1689 | ||
1690 | /* | |
1691 | * pmevtyper_rawwrite is called between a pair of pmu_op_start and | |
1692 | * pmu_op_finish calls when loading saved state for a migration. Because | |
1693 | * we're potentially updating the type of event here, the value written to | |
673d8215 | 1694 | * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a |
5ecdd3e4 AL |
1695 | * different counter type. Therefore, we need to set this value to the |
1696 | * current count for the counter type we're writing so that pmu_op_finish | |
1697 | * has the correct count for its calculation. | |
1698 | */ | |
1699 | uint16_t event = value & PMXEVTYPER_EVTCOUNT; | |
1700 | if (event_supported(event)) { | |
1701 | uint16_t event_idx = supported_event_map[event]; | |
1702 | env->cp15.c14_pmevcntr_delta[counter] = | |
1703 | pm_events[event_idx].get_count(env); | |
fdb86656 WH |
1704 | } |
1705 | } | |
1706 | ||
5ecdd3e4 AL |
1707 | static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) |
1708 | { | |
1709 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1710 | return pmevtyper_read(env, ri, counter); | |
1711 | } | |
1712 | ||
1713 | static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1714 | uint64_t value) | |
1715 | { | |
1716 | pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1717 | } | |
1718 | ||
fdb86656 WH |
1719 | static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1720 | { | |
5ecdd3e4 AL |
1721 | return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); |
1722 | } | |
1723 | ||
1724 | static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1725 | uint64_t value, uint8_t counter) | |
1726 | { | |
47b385da PM |
1727 | if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { |
1728 | /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */ | |
1729 | value &= MAKE_64BIT_MASK(0, 32); | |
1730 | } | |
5ecdd3e4 AL |
1731 | if (counter < pmu_num_counters(env)) { |
1732 | pmevcntr_op_start(env, counter); | |
1733 | env->cp15.c14_pmevcntr[counter] = value; | |
1734 | pmevcntr_op_finish(env, counter); | |
1735 | } | |
1736 | /* | |
1737 | * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR | |
1738 | * are CONSTRAINED UNPREDICTABLE. | |
fdb86656 | 1739 | */ |
5ecdd3e4 AL |
1740 | } |
1741 | ||
1742 | static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, | |
1743 | uint8_t counter) | |
1744 | { | |
1745 | if (counter < pmu_num_counters(env)) { | |
1746 | uint64_t ret; | |
1747 | pmevcntr_op_start(env, counter); | |
1748 | ret = env->cp15.c14_pmevcntr[counter]; | |
1749 | pmevcntr_op_finish(env, counter); | |
47b385da PM |
1750 | if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { |
1751 | /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */ | |
1752 | ret &= MAKE_64BIT_MASK(0, 32); | |
1753 | } | |
5ecdd3e4 | 1754 | return ret; |
fdb86656 | 1755 | } else { |
9b37a28c FR |
1756 | /* |
1757 | * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR | |
1758 | * are CONSTRAINED UNPREDICTABLE. | |
1759 | */ | |
fdb86656 WH |
1760 | return 0; |
1761 | } | |
200ac0ef PM |
1762 | } |
1763 | ||
5ecdd3e4 AL |
1764 | static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, |
1765 | uint64_t value) | |
1766 | { | |
1767 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1768 | pmevcntr_write(env, ri, value, counter); | |
1769 | } | |
1770 | ||
1771 | static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) | |
1772 | { | |
1773 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1774 | return pmevcntr_read(env, ri, counter); | |
1775 | } | |
1776 | ||
1777 | static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, | |
1778 | uint64_t value) | |
1779 | { | |
1780 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1781 | assert(counter < pmu_num_counters(env)); | |
1782 | env->cp15.c14_pmevcntr[counter] = value; | |
1783 | pmevcntr_write(env, ri, value, counter); | |
1784 | } | |
1785 | ||
1786 | static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri) | |
1787 | { | |
1788 | uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); | |
1789 | assert(counter < pmu_num_counters(env)); | |
1790 | return env->cp15.c14_pmevcntr[counter]; | |
1791 | } | |
1792 | ||
1793 | static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
1794 | uint64_t value) | |
1795 | { | |
1796 | pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); | |
1797 | } | |
1798 | ||
1799 | static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
1800 | { | |
1801 | return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); | |
1802 | } | |
1803 | ||
c4241c7d | 1804 | static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
200ac0ef PM |
1805 | uint64_t value) |
1806 | { | |
6ecd0b6b AB |
1807 | if (arm_feature(env, ARM_FEATURE_V8)) { |
1808 | env->cp15.c9_pmuserenr = value & 0xf; | |
1809 | } else { | |
1810 | env->cp15.c9_pmuserenr = value & 1; | |
1811 | } | |
200ac0ef PM |
1812 | } |
1813 | ||
c4241c7d PM |
1814 | static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1815 | uint64_t value) | |
200ac0ef PM |
1816 | { |
1817 | /* We have no event counters so only the C bit can be changed */ | |
7ece99b1 | 1818 | value &= pmu_counter_mask(env); |
200ac0ef | 1819 | env->cp15.c9_pminten |= value; |
f4efb4b2 | 1820 | pmu_update_irq(env); |
200ac0ef PM |
1821 | } |
1822 | ||
c4241c7d PM |
1823 | static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1824 | uint64_t value) | |
200ac0ef | 1825 | { |
7ece99b1 | 1826 | value &= pmu_counter_mask(env); |
200ac0ef | 1827 | env->cp15.c9_pminten &= ~value; |
f4efb4b2 | 1828 | pmu_update_irq(env); |
200ac0ef PM |
1829 | } |
1830 | ||
c4241c7d PM |
1831 | static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1832 | uint64_t value) | |
8641136c | 1833 | { |
9b37a28c FR |
1834 | /* |
1835 | * Note that even though the AArch64 view of this register has bits | |
a505d7fe PM |
1836 | * [10:0] all RES0 we can only mask the bottom 5, to comply with the |
1837 | * architectural requirements for bits which are RES0 only in some | |
1838 | * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 | |
1839 | * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) | |
1840 | */ | |
855ea66d | 1841 | raw_write(env, ri, value & ~0x1FULL); |
8641136c NR |
1842 | } |
1843 | ||
64e0e2de EI |
1844 | static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
1845 | { | |
ea22747c | 1846 | /* Begin with base v8.0 state. */ |
06f2adcc | 1847 | uint64_t valid_mask = 0x3fff; |
2fc0cc0e | 1848 | ARMCPU *cpu = env_archcpu(env); |
d902ae75 | 1849 | uint64_t changed; |
ea22747c | 1850 | |
bfe43e3d RH |
1851 | /* |
1852 | * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always | |
1853 | * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64. | |
1854 | * Instead, choose the format based on the mode of EL3. | |
1855 | */ | |
1856 | if (arm_el_is_aa64(env, 3)) { | |
1857 | value |= SCR_FW | SCR_AW; /* RES1 */ | |
1858 | valid_mask &= ~SCR_NET; /* RES0 */ | |
252e8c69 | 1859 | |
6bcbb07a RH |
1860 | if (!cpu_isar_feature(aa64_aa32_el1, cpu) && |
1861 | !cpu_isar_feature(aa64_aa32_el2, cpu)) { | |
1862 | value |= SCR_RW; /* RAO/WI */ | |
1863 | } | |
da3d8b13 RH |
1864 | if (cpu_isar_feature(aa64_ras, cpu)) { |
1865 | valid_mask |= SCR_TERR; | |
1866 | } | |
252e8c69 RH |
1867 | if (cpu_isar_feature(aa64_lor, cpu)) { |
1868 | valid_mask |= SCR_TLOR; | |
1869 | } | |
1870 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
1871 | valid_mask |= SCR_API | SCR_APK; | |
1872 | } | |
926c1b97 RDC |
1873 | if (cpu_isar_feature(aa64_sel2, cpu)) { |
1874 | valid_mask |= SCR_EEL2; | |
87bfbfe7 RH |
1875 | } else if (cpu_isar_feature(aa64_rme, cpu)) { |
1876 | /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */ | |
1877 | value |= SCR_NS; | |
926c1b97 | 1878 | } |
8ddb300b RH |
1879 | if (cpu_isar_feature(aa64_mte, cpu)) { |
1880 | valid_mask |= SCR_ATA; | |
1881 | } | |
7cb1e618 RH |
1882 | if (cpu_isar_feature(aa64_scxtnum, cpu)) { |
1883 | valid_mask |= SCR_ENSCXT; | |
1884 | } | |
7ac61020 PM |
1885 | if (cpu_isar_feature(aa64_doublefault, cpu)) { |
1886 | valid_mask |= SCR_EASE | SCR_NMEA; | |
1887 | } | |
06f2adcc JF |
1888 | if (cpu_isar_feature(aa64_sme, cpu)) { |
1889 | valid_mask |= SCR_ENTP2; | |
1890 | } | |
08899b5c EI |
1891 | if (cpu_isar_feature(aa64_hcx, cpu)) { |
1892 | valid_mask |= SCR_HXEN; | |
1893 | } | |
15126d9c PM |
1894 | if (cpu_isar_feature(aa64_fgt, cpu)) { |
1895 | valid_mask |= SCR_FGTEN; | |
1896 | } | |
aa3cc42c RH |
1897 | if (cpu_isar_feature(aa64_rme, cpu)) { |
1898 | valid_mask |= SCR_NSE | SCR_GPF; | |
1899 | } | |
ea22747c RH |
1900 | } else { |
1901 | valid_mask &= ~(SCR_RW | SCR_ST); | |
da3d8b13 RH |
1902 | if (cpu_isar_feature(aa32_ras, cpu)) { |
1903 | valid_mask |= SCR_TERR; | |
1904 | } | |
ea22747c | 1905 | } |
64e0e2de EI |
1906 | |
1907 | if (!arm_feature(env, ARM_FEATURE_EL2)) { | |
1908 | valid_mask &= ~SCR_HCE; | |
1909 | ||
9b37a28c FR |
1910 | /* |
1911 | * On ARMv7, SMD (or SCD as it is called in v7) is only | |
64e0e2de EI |
1912 | * supported if EL2 exists. The bit is UNK/SBZP when |
1913 | * EL2 is unavailable. In QEMU ARMv7, we force it to always zero | |
1914 | * when EL2 is unavailable. | |
4eb27640 | 1915 | * On ARMv8, this bit is always available. |
64e0e2de | 1916 | */ |
4eb27640 GB |
1917 | if (arm_feature(env, ARM_FEATURE_V7) && |
1918 | !arm_feature(env, ARM_FEATURE_V8)) { | |
64e0e2de EI |
1919 | valid_mask &= ~SCR_SMD; |
1920 | } | |
1921 | } | |
1922 | ||
1923 | /* Clear all-context RES0 bits. */ | |
1924 | value &= valid_mask; | |
d902ae75 RH |
1925 | changed = env->cp15.scr_el3 ^ value; |
1926 | env->cp15.scr_el3 = value; | |
1927 | ||
1928 | /* | |
aa3cc42c | 1929 | * If SCR_EL3.{NS,NSE} changes, i.e. change of security state, |
d902ae75 RH |
1930 | * we must invalidate all TLBs below EL3. |
1931 | */ | |
aa3cc42c | 1932 | if (changed & (SCR_NS | SCR_NSE)) { |
d902ae75 RH |
1933 | tlb_flush_by_mmuidx(env_cpu(env), (ARMMMUIdxBit_E10_0 | |
1934 | ARMMMUIdxBit_E20_0 | | |
1935 | ARMMMUIdxBit_E10_1 | | |
1936 | ARMMMUIdxBit_E20_2 | | |
1937 | ARMMMUIdxBit_E10_1_PAN | | |
1938 | ARMMMUIdxBit_E20_2_PAN | | |
1939 | ARMMMUIdxBit_E2)); | |
1940 | } | |
64e0e2de EI |
1941 | } |
1942 | ||
10d0ef3e MN |
1943 | static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
1944 | { | |
1945 | /* | |
1946 | * scr_write will set the RES1 bits on an AArch64-only CPU. | |
1947 | * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise. | |
1948 | */ | |
1949 | scr_write(env, ri, 0); | |
1950 | } | |
1951 | ||
e2ce5fcd PM |
1952 | static CPAccessResult access_tid4(CPUARMState *env, |
1953 | const ARMCPRegInfo *ri, | |
1954 | bool isread) | |
630fcd4d | 1955 | { |
e2ce5fcd PM |
1956 | if (arm_current_el(env) == 1 && |
1957 | (arm_hcr_el2_eff(env) & (HCR_TID2 | HCR_TID4))) { | |
630fcd4d MZ |
1958 | return CP_ACCESS_TRAP_EL2; |
1959 | } | |
1960 | ||
1961 | return CP_ACCESS_OK; | |
1962 | } | |
1963 | ||
c4241c7d | 1964 | static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
776d4e5c | 1965 | { |
2fc0cc0e | 1966 | ARMCPU *cpu = env_archcpu(env); |
b85a1fd6 | 1967 | |
9b37a28c FR |
1968 | /* |
1969 | * Acquire the CSSELR index from the bank corresponding to the CCSIDR | |
b85a1fd6 FA |
1970 | * bank |
1971 | */ | |
1972 | uint32_t index = A32_BANKED_REG_GET(env, csselr, | |
1973 | ri->secure & ARM_CP_SECSTATE_S); | |
1974 | ||
1975 | return cpu->ccsidr[index]; | |
776d4e5c PM |
1976 | } |
1977 | ||
c4241c7d PM |
1978 | static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
1979 | uint64_t value) | |
776d4e5c | 1980 | { |
8d5c773e | 1981 | raw_write(env, ri, value & 0xf); |
776d4e5c PM |
1982 | } |
1983 | ||
1090b9c6 PM |
1984 | static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
1985 | { | |
29a0af61 | 1986 | CPUState *cs = env_cpu(env); |
cc974d5c RDC |
1987 | bool el1 = arm_current_el(env) == 1; |
1988 | uint64_t hcr_el2 = el1 ? arm_hcr_el2_eff(env) : 0; | |
1090b9c6 PM |
1989 | uint64_t ret = 0; |
1990 | ||
cc974d5c | 1991 | if (hcr_el2 & HCR_IMO) { |
636540e9 PM |
1992 | if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { |
1993 | ret |= CPSR_I; | |
1994 | } | |
1995 | } else { | |
1996 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { | |
1997 | ret |= CPSR_I; | |
1998 | } | |
1090b9c6 | 1999 | } |
636540e9 | 2000 | |
cc974d5c | 2001 | if (hcr_el2 & HCR_FMO) { |
636540e9 PM |
2002 | if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { |
2003 | ret |= CPSR_F; | |
2004 | } | |
2005 | } else { | |
2006 | if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { | |
2007 | ret |= CPSR_F; | |
2008 | } | |
1090b9c6 | 2009 | } |
636540e9 | 2010 | |
3c29632f RH |
2011 | if (hcr_el2 & HCR_AMO) { |
2012 | if (cs->interrupt_request & CPU_INTERRUPT_VSERR) { | |
2013 | ret |= CPSR_A; | |
2014 | } | |
2015 | } | |
2016 | ||
1090b9c6 PM |
2017 | return ret; |
2018 | } | |
2019 | ||
93fbc983 MZ |
2020 | static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInfo *ri, |
2021 | bool isread) | |
2022 | { | |
2023 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID1)) { | |
2024 | return CP_ACCESS_TRAP_EL2; | |
2025 | } | |
2026 | ||
2027 | return CP_ACCESS_OK; | |
2028 | } | |
2029 | ||
2030 | static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInfo *ri, | |
2031 | bool isread) | |
2032 | { | |
2033 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
2034 | return access_aa64_tid1(env, ri, isread); | |
2035 | } | |
2036 | ||
2037 | return CP_ACCESS_OK; | |
2038 | } | |
2039 | ||
e9aa6c21 | 2040 | static const ARMCPRegInfo v7_cp_reginfo[] = { |
7d57f408 PM |
2041 | /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ |
2042 | { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4, | |
2043 | .access = PL1_W, .type = ARM_CP_NOP }, | |
9b37a28c FR |
2044 | /* |
2045 | * Performance monitors are implementation defined in v7, | |
200ac0ef | 2046 | * but with an ARM recommended set of registers, which we |
ac689a2e | 2047 | * follow. |
200ac0ef PM |
2048 | * |
2049 | * Performance registers fall into three categories: | |
2050 | * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) | |
2051 | * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) | |
2052 | * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others) | |
2053 | * For the cases controlled by PMUSERENR we must set .access to PL0_RW | |
2054 | * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. | |
2055 | */ | |
2056 | { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1, | |
7f4fbfb5 | 2057 | .access = PL0_RW, .type = ARM_CP_ALIAS | ARM_CP_IO, |
8521466b | 2058 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), |
fcd25206 PM |
2059 | .writefn = pmcntenset_write, |
2060 | .accessfn = pmreg_access, | |
dc780233 | 2061 | .fgt = FGT_PMCNTEN, |
fcd25206 | 2062 | .raw_writefn = raw_write }, |
7f4fbfb5 | 2063 | { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO, |
8521466b AF |
2064 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, |
2065 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 2066 | .fgt = FGT_PMCNTEN, |
8521466b AF |
2067 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, |
2068 | .writefn = pmcntenset_write, .raw_writefn = raw_write }, | |
200ac0ef | 2069 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
8521466b AF |
2070 | .access = PL0_RW, |
2071 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), | |
fcd25206 | 2072 | .accessfn = pmreg_access, |
dc780233 | 2073 | .fgt = FGT_PMCNTEN, |
fcd25206 | 2074 | .writefn = pmcntenclr_write, |
7f4fbfb5 | 2075 | .type = ARM_CP_ALIAS | ARM_CP_IO }, |
8521466b AF |
2076 | { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, |
2077 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, | |
2078 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 2079 | .fgt = FGT_PMCNTEN, |
7f4fbfb5 | 2080 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
8521466b AF |
2081 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), |
2082 | .writefn = pmcntenclr_write }, | |
200ac0ef | 2083 | { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3, |
f4efb4b2 | 2084 | .access = PL0_RW, .type = ARM_CP_IO, |
e4e91a21 | 2085 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
fcd25206 | 2086 | .accessfn = pmreg_access, |
dc780233 | 2087 | .fgt = FGT_PMOVS, |
fcd25206 PM |
2088 | .writefn = pmovsr_write, |
2089 | .raw_writefn = raw_write }, | |
978364f1 AF |
2090 | { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, |
2091 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, | |
2092 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 2093 | .fgt = FGT_PMOVS, |
f4efb4b2 | 2094 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
978364f1 AF |
2095 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
2096 | .writefn = pmovsr_write, | |
2097 | .raw_writefn = raw_write }, | |
200ac0ef | 2098 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, |
f4efb4b2 | 2099 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
dc780233 | 2100 | .fgt = FGT_PMSWINC_EL0, |
f4efb4b2 | 2101 | .type = ARM_CP_NO_RAW | ARM_CP_IO, |
0d4bfd7d AL |
2102 | .writefn = pmswinc_write }, |
2103 | { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64, | |
2104 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4, | |
f4efb4b2 | 2105 | .access = PL0_W, .accessfn = pmreg_access_swinc, |
dc780233 | 2106 | .fgt = FGT_PMSWINC_EL0, |
f4efb4b2 | 2107 | .type = ARM_CP_NO_RAW | ARM_CP_IO, |
0d4bfd7d | 2108 | .writefn = pmswinc_write }, |
6b040780 WH |
2109 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, |
2110 | .access = PL0_RW, .type = ARM_CP_ALIAS, | |
dc780233 | 2111 | .fgt = FGT_PMSELR_EL0, |
6b040780 | 2112 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), |
6ecd0b6b | 2113 | .accessfn = pmreg_access_selr, .writefn = pmselr_write, |
6b040780 WH |
2114 | .raw_writefn = raw_write}, |
2115 | { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, | |
2116 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, | |
6ecd0b6b | 2117 | .access = PL0_RW, .accessfn = pmreg_access_selr, |
dc780233 | 2118 | .fgt = FGT_PMSELR_EL0, |
6b040780 WH |
2119 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), |
2120 | .writefn = pmselr_write, .raw_writefn = raw_write, }, | |
200ac0ef | 2121 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, |
169c8938 | 2122 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO, |
dc780233 | 2123 | .fgt = FGT_PMCCNTR_EL0, |
421c7ebd | 2124 | .readfn = pmccntr_read, .writefn = pmccntr_write32, |
6ecd0b6b | 2125 | .accessfn = pmreg_access_ccntr }, |
8521466b AF |
2126 | { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, |
2127 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, | |
6ecd0b6b | 2128 | .access = PL0_RW, .accessfn = pmreg_access_ccntr, |
dc780233 | 2129 | .fgt = FGT_PMCCNTR_EL0, |
8521466b | 2130 | .type = ARM_CP_IO, |
980ebe87 AL |
2131 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt), |
2132 | .readfn = pmccntr_read, .writefn = pmccntr_write, | |
2133 | .raw_readfn = raw_read, .raw_writefn = raw_write, }, | |
4b8afa1f AL |
2134 | { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7, |
2135 | .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32, | |
2136 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 2137 | .fgt = FGT_PMCCFILTR_EL0, |
4b8afa1f AL |
2138 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
2139 | .resetvalue = 0, }, | |
8521466b AF |
2140 | { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, |
2141 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, | |
980ebe87 | 2142 | .writefn = pmccfiltr_write, .raw_writefn = raw_write, |
8521466b | 2143 | .access = PL0_RW, .accessfn = pmreg_access, |
dc780233 | 2144 | .fgt = FGT_PMCCFILTR_EL0, |
8521466b AF |
2145 | .type = ARM_CP_IO, |
2146 | .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), | |
2147 | .resetvalue = 0, }, | |
200ac0ef | 2148 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |
5ecdd3e4 AL |
2149 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
2150 | .accessfn = pmreg_access, | |
dc780233 | 2151 | .fgt = FGT_PMEVTYPERN_EL0, |
fdb86656 WH |
2152 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
2153 | { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, | |
2154 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, | |
5ecdd3e4 AL |
2155 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
2156 | .accessfn = pmreg_access, | |
dc780233 | 2157 | .fgt = FGT_PMEVTYPERN_EL0, |
fdb86656 | 2158 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, |
200ac0ef | 2159 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, |
5ecdd3e4 AL |
2160 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
2161 | .accessfn = pmreg_access_xevcntr, | |
dc780233 | 2162 | .fgt = FGT_PMEVCNTRN_EL0, |
5ecdd3e4 AL |
2163 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, |
2164 | { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64, | |
2165 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2, | |
2166 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
2167 | .accessfn = pmreg_access_xevcntr, | |
dc780233 | 2168 | .fgt = FGT_PMEVCNTRN_EL0, |
5ecdd3e4 | 2169 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, |
200ac0ef | 2170 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, |
1fce1ba9 | 2171 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, |
e4e91a21 | 2172 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr), |
200ac0ef | 2173 | .resetvalue = 0, |
d4e6df63 | 2174 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, |
8a83ffc2 AF |
2175 | { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, |
2176 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, | |
1fce1ba9 | 2177 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, |
8a83ffc2 AF |
2178 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), |
2179 | .resetvalue = 0, | |
2180 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, | |
200ac0ef | 2181 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, |
1fce1ba9 | 2182 | .access = PL1_RW, .accessfn = access_tpm, |
dc780233 | 2183 | .fgt = FGT_PMINTEN, |
b7d793ad | 2184 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
e6ec5457 | 2185 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), |
200ac0ef | 2186 | .resetvalue = 0, |
d4e6df63 | 2187 | .writefn = pmintenset_write, .raw_writefn = raw_write }, |
e6ec5457 WH |
2188 | { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, |
2189 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, | |
2190 | .access = PL1_RW, .accessfn = access_tpm, | |
dc780233 | 2191 | .fgt = FGT_PMINTEN, |
e6ec5457 WH |
2192 | .type = ARM_CP_IO, |
2193 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | |
2194 | .writefn = pmintenset_write, .raw_writefn = raw_write, | |
2195 | .resetvalue = 0x0 }, | |
200ac0ef | 2196 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, |
fc5f6856 | 2197 | .access = PL1_RW, .accessfn = access_tpm, |
dc780233 | 2198 | .fgt = FGT_PMINTEN, |
887c0f15 | 2199 | .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, |
200ac0ef | 2200 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
b061a82b | 2201 | .writefn = pmintenclr_write, }, |
978364f1 AF |
2202 | { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, |
2203 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, | |
fc5f6856 | 2204 | .access = PL1_RW, .accessfn = access_tpm, |
dc780233 | 2205 | .fgt = FGT_PMINTEN, |
887c0f15 | 2206 | .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, |
978364f1 AF |
2207 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), |
2208 | .writefn = pmintenclr_write }, | |
7da845b0 PM |
2209 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, |
2210 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | |
630fcd4d | 2211 | .access = PL1_R, |
e2ce5fcd | 2212 | .accessfn = access_tid4, |
158c276c | 2213 | .fgt = FGT_CCSIDR_EL1, |
630fcd4d | 2214 | .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, |
7da845b0 PM |
2215 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, |
2216 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | |
630fcd4d | 2217 | .access = PL1_RW, |
e2ce5fcd | 2218 | .accessfn = access_tid4, |
b19ed03c | 2219 | .fgt = FGT_CSSELR_EL1, |
630fcd4d | 2220 | .writefn = csselr_write, .resetvalue = 0, |
b85a1fd6 FA |
2221 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), |
2222 | offsetof(CPUARMState, cp15.csselr_ns) } }, | |
9b37a28c FR |
2223 | /* |
2224 | * Auxiliary ID register: this actually has an IMPDEF value but for now | |
776d4e5c PM |
2225 | * just RAZ for all cores: |
2226 | */ | |
0ff644a7 PM |
2227 | { .name = "AIDR", .state = ARM_CP_STATE_BOTH, |
2228 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, | |
93fbc983 MZ |
2229 | .access = PL1_R, .type = ARM_CP_CONST, |
2230 | .accessfn = access_aa64_tid1, | |
158c276c | 2231 | .fgt = FGT_AIDR_EL1, |
93fbc983 | 2232 | .resetvalue = 0 }, |
9b37a28c FR |
2233 | /* |
2234 | * Auxiliary fault status registers: these also are IMPDEF, and we | |
f32cdad5 PM |
2235 | * choose to RAZ/WI for all cores. |
2236 | */ | |
2237 | { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, | |
2238 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, | |
84929218 | 2239 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
158c276c | 2240 | .fgt = FGT_AFSR0_EL1, |
84929218 | 2241 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
f32cdad5 PM |
2242 | { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, |
2243 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, | |
84929218 | 2244 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
158c276c | 2245 | .fgt = FGT_AFSR1_EL1, |
84929218 | 2246 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
9b37a28c FR |
2247 | /* |
2248 | * MAIR can just read-as-written because we don't implement caches | |
b0fe2427 PM |
2249 | * and so don't need to care about memory attributes. |
2250 | */ | |
2251 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | |
2252 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | |
84929218 | 2253 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
67dd8030 | 2254 | .fgt = FGT_MAIR_EL1, |
84929218 | 2255 | .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), |
b0fe2427 | 2256 | .resetvalue = 0 }, |
4cfb8ad8 PM |
2257 | { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, |
2258 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0, | |
2259 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]), | |
2260 | .resetvalue = 0 }, | |
9b37a28c FR |
2261 | /* |
2262 | * For non-long-descriptor page tables these are PRRR and NMRR; | |
b0fe2427 | 2263 | * regardless they still act as reads-as-written for QEMU. |
b0fe2427 | 2264 | */ |
9b37a28c FR |
2265 | /* |
2266 | * MAIR0/1 are defined separately from their 64-bit counterpart which | |
be693c87 GB |
2267 | * allows them to assign the correct fieldoffset based on the endianness |
2268 | * handled in the field definitions. | |
2269 | */ | |
a903c449 | 2270 | { .name = "MAIR0", .state = ARM_CP_STATE_AA32, |
84929218 RH |
2271 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, |
2272 | .access = PL1_RW, .accessfn = access_tvm_trvm, | |
be693c87 GB |
2273 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), |
2274 | offsetof(CPUARMState, cp15.mair0_ns) }, | |
b0fe2427 | 2275 | .resetfn = arm_cp_reset_ignore }, |
a903c449 | 2276 | { .name = "MAIR1", .state = ARM_CP_STATE_AA32, |
84929218 RH |
2277 | .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, |
2278 | .access = PL1_RW, .accessfn = access_tvm_trvm, | |
be693c87 GB |
2279 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), |
2280 | offsetof(CPUARMState, cp15.mair1_ns) }, | |
b0fe2427 | 2281 | .resetfn = arm_cp_reset_ignore }, |
1090b9c6 PM |
2282 | { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, |
2283 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, | |
b19ed03c | 2284 | .fgt = FGT_ISR_EL1, |
7a0e58fa | 2285 | .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, |
995939a6 PM |
2286 | /* 32 bit ITLB invalidates */ |
2287 | { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, | |
30881b73 RH |
2288 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2289 | .writefn = tlbiall_write }, | |
995939a6 | 2290 | { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, |
30881b73 RH |
2291 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2292 | .writefn = tlbimva_write }, | |
995939a6 | 2293 | { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2, |
30881b73 RH |
2294 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2295 | .writefn = tlbiasid_write }, | |
995939a6 PM |
2296 | /* 32 bit DTLB invalidates */ |
2297 | { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0, | |
30881b73 RH |
2298 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2299 | .writefn = tlbiall_write }, | |
995939a6 | 2300 | { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, |
30881b73 RH |
2301 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2302 | .writefn = tlbimva_write }, | |
995939a6 | 2303 | { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2, |
30881b73 RH |
2304 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2305 | .writefn = tlbiasid_write }, | |
995939a6 PM |
2306 | /* 32 bit TLB invalidates */ |
2307 | { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | |
30881b73 RH |
2308 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2309 | .writefn = tlbiall_write }, | |
995939a6 | 2310 | { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
30881b73 RH |
2311 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2312 | .writefn = tlbimva_write }, | |
995939a6 | 2313 | { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
30881b73 RH |
2314 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2315 | .writefn = tlbiasid_write }, | |
995939a6 | 2316 | { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
30881b73 RH |
2317 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
2318 | .writefn = tlbimvaa_write }, | |
995939a6 PM |
2319 | }; |
2320 | ||
2321 | static const ARMCPRegInfo v7mp_cp_reginfo[] = { | |
2322 | /* 32 bit TLB invalidates, Inner Shareable */ | |
2323 | { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | |
0f66d223 | 2324 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, |
30881b73 | 2325 | .writefn = tlbiall_is_write }, |
995939a6 | 2326 | { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
0f66d223 | 2327 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, |
30881b73 | 2328 | .writefn = tlbimva_is_write }, |
995939a6 | 2329 | { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
0f66d223 | 2330 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, |
fa439fc5 | 2331 | .writefn = tlbiasid_is_write }, |
995939a6 | 2332 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
0f66d223 | 2333 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, |
fa439fc5 | 2334 | .writefn = tlbimvaa_is_write }, |
e9aa6c21 PM |
2335 | }; |
2336 | ||
327dd510 AL |
2337 | static const ARMCPRegInfo pmovsset_cp_reginfo[] = { |
2338 | /* PMOVSSET is not implemented in v7 before v7ve */ | |
2339 | { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3, | |
2340 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 2341 | .fgt = FGT_PMOVS, |
f4efb4b2 | 2342 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
327dd510 AL |
2343 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), |
2344 | .writefn = pmovsset_write, | |
2345 | .raw_writefn = raw_write }, | |
2346 | { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64, | |
2347 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3, | |
2348 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 2349 | .fgt = FGT_PMOVS, |
f4efb4b2 | 2350 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
327dd510 AL |
2351 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), |
2352 | .writefn = pmovsset_write, | |
2353 | .raw_writefn = raw_write }, | |
327dd510 AL |
2354 | }; |
2355 | ||
c4241c7d PM |
2356 | static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2357 | uint64_t value) | |
c326b979 PM |
2358 | { |
2359 | value &= 1; | |
2360 | env->teecr = value; | |
c326b979 PM |
2361 | } |
2362 | ||
cc7613bf PM |
2363 | static CPAccessResult teecr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2364 | bool isread) | |
2365 | { | |
2366 | /* | |
2367 | * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE | |
2368 | * at all, so we don't need to check whether we're v8A. | |
2369 | */ | |
2370 | if (arm_current_el(env) < 2 && !arm_is_secure_below_el3(env) && | |
2371 | (env->cp15.hstr_el2 & HSTR_TTEE)) { | |
2372 | return CP_ACCESS_TRAP_EL2; | |
2373 | } | |
2374 | return CP_ACCESS_OK; | |
2375 | } | |
2376 | ||
3f208fd7 PM |
2377 | static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2378 | bool isread) | |
c326b979 | 2379 | { |
dcbff19b | 2380 | if (arm_current_el(env) == 0 && (env->teecr & 1)) { |
92611c00 | 2381 | return CP_ACCESS_TRAP; |
c326b979 | 2382 | } |
cc7613bf | 2383 | return teecr_access(env, ri, isread); |
c326b979 PM |
2384 | } |
2385 | ||
2386 | static const ARMCPRegInfo t2ee_cp_reginfo[] = { | |
2387 | { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0, | |
2388 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr), | |
2389 | .resetvalue = 0, | |
cc7613bf | 2390 | .writefn = teecr_write, .accessfn = teecr_access }, |
c326b979 PM |
2391 | { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0, |
2392 | .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr), | |
92611c00 | 2393 | .accessfn = teehbr_access, .resetvalue = 0 }, |
c326b979 PM |
2394 | }; |
2395 | ||
4d31c596 | 2396 | static const ARMCPRegInfo v6k_cp_reginfo[] = { |
e4fe830b PM |
2397 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, |
2398 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | |
2399 | .access = PL0_RW, | |
67dd8030 | 2400 | .fgt = FGT_TPIDR_EL0, |
54bf36ed | 2401 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, |
4d31c596 PM |
2402 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, |
2403 | .access = PL0_RW, | |
67dd8030 | 2404 | .fgt = FGT_TPIDR_EL0, |
54bf36ed FA |
2405 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), |
2406 | offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, | |
e4fe830b PM |
2407 | .resetfn = arm_cp_reset_ignore }, |
2408 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | |
2409 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | |
04215eb1 | 2410 | .access = PL0_R | PL1_W, |
67dd8030 | 2411 | .fgt = FGT_TPIDRRO_EL0, |
54bf36ed FA |
2412 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), |
2413 | .resetvalue = 0}, | |
4d31c596 | 2414 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, |
04215eb1 | 2415 | .access = PL0_R | PL1_W, |
67dd8030 | 2416 | .fgt = FGT_TPIDRRO_EL0, |
54bf36ed FA |
2417 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), |
2418 | offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, | |
e4fe830b | 2419 | .resetfn = arm_cp_reset_ignore }, |
54bf36ed | 2420 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, |
e4fe830b | 2421 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, |
4d31c596 | 2422 | .access = PL1_RW, |
67dd8030 | 2423 | .fgt = FGT_TPIDR_EL1, |
54bf36ed FA |
2424 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, |
2425 | { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, | |
2426 | .access = PL1_RW, | |
2427 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s), | |
2428 | offsetoflow32(CPUARMState, cp15.tpidrprw_ns) }, | |
2429 | .resetvalue = 0 }, | |
4d31c596 PM |
2430 | }; |
2431 | ||
55d284af PM |
2432 | #ifndef CONFIG_USER_ONLY |
2433 | ||
3f208fd7 PM |
2434 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2435 | bool isread) | |
00108f2d | 2436 | { |
9b37a28c FR |
2437 | /* |
2438 | * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. | |
75502672 PM |
2439 | * Writable only at the highest implemented exception level. |
2440 | */ | |
2441 | int el = arm_current_el(env); | |
5bc84371 RH |
2442 | uint64_t hcr; |
2443 | uint32_t cntkctl; | |
75502672 PM |
2444 | |
2445 | switch (el) { | |
2446 | case 0: | |
5bc84371 RH |
2447 | hcr = arm_hcr_el2_eff(env); |
2448 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2449 | cntkctl = env->cp15.cnthctl_el2; | |
2450 | } else { | |
2451 | cntkctl = env->cp15.c14_cntkctl; | |
2452 | } | |
2453 | if (!extract32(cntkctl, 0, 2)) { | |
75502672 PM |
2454 | return CP_ACCESS_TRAP; |
2455 | } | |
2456 | break; | |
2457 | case 1: | |
2458 | if (!isread && ri->state == ARM_CP_STATE_AA32 && | |
2459 | arm_is_secure_below_el3(env)) { | |
2460 | /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */ | |
2461 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2462 | } | |
2463 | break; | |
2464 | case 2: | |
2465 | case 3: | |
2466 | break; | |
00108f2d | 2467 | } |
75502672 PM |
2468 | |
2469 | if (!isread && el < arm_highest_el(env)) { | |
2470 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
2471 | } | |
2472 | ||
00108f2d PM |
2473 | return CP_ACCESS_OK; |
2474 | } | |
2475 | ||
3f208fd7 PM |
2476 | static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, |
2477 | bool isread) | |
00108f2d | 2478 | { |
0b6440af | 2479 | unsigned int cur_el = arm_current_el(env); |
e6ef0169 | 2480 | bool has_el2 = arm_is_el2_enabled(env); |
5bc84371 | 2481 | uint64_t hcr = arm_hcr_el2_eff(env); |
0b6440af | 2482 | |
5bc84371 RH |
2483 | switch (cur_el) { |
2484 | case 0: | |
2485 | /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */ | |
2486 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2487 | return (extract32(env->cp15.cnthctl_el2, timeridx, 1) | |
2488 | ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); | |
2489 | } | |
0b6440af | 2490 | |
5bc84371 RH |
2491 | /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */ |
2492 | if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) { | |
2493 | return CP_ACCESS_TRAP; | |
2494 | } | |
d01448c7 | 2495 | /* fall through */ |
5bc84371 RH |
2496 | case 1: |
2497 | /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */ | |
e6ef0169 | 2498 | if (has_el2 && timeridx == GTIMER_PHYS && |
5bc84371 RH |
2499 | (hcr & HCR_E2H |
2500 | ? !extract32(env->cp15.cnthctl_el2, 10, 1) | |
2501 | : !extract32(env->cp15.cnthctl_el2, 0, 1))) { | |
2502 | return CP_ACCESS_TRAP_EL2; | |
2503 | } | |
2504 | break; | |
0b6440af | 2505 | } |
00108f2d PM |
2506 | return CP_ACCESS_OK; |
2507 | } | |
2508 | ||
3f208fd7 PM |
2509 | static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, |
2510 | bool isread) | |
00108f2d | 2511 | { |
0b6440af | 2512 | unsigned int cur_el = arm_current_el(env); |
e6ef0169 | 2513 | bool has_el2 = arm_is_el2_enabled(env); |
5bc84371 | 2514 | uint64_t hcr = arm_hcr_el2_eff(env); |
0b6440af | 2515 | |
5bc84371 RH |
2516 | switch (cur_el) { |
2517 | case 0: | |
2518 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2519 | /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */ | |
2520 | return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1) | |
2521 | ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); | |
2522 | } | |
0b6440af | 2523 | |
5bc84371 RH |
2524 | /* |
2525 | * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from | |
2526 | * EL0 if EL0[PV]TEN is zero. | |
2527 | */ | |
2528 | if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { | |
2529 | return CP_ACCESS_TRAP; | |
2530 | } | |
2531 | /* fall through */ | |
2532 | ||
2533 | case 1: | |
e6ef0169 | 2534 | if (has_el2 && timeridx == GTIMER_PHYS) { |
5bc84371 RH |
2535 | if (hcr & HCR_E2H) { |
2536 | /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */ | |
2537 | if (!extract32(env->cp15.cnthctl_el2, 11, 1)) { | |
2538 | return CP_ACCESS_TRAP_EL2; | |
2539 | } | |
2540 | } else { | |
2541 | /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */ | |
2542 | if (!extract32(env->cp15.cnthctl_el2, 1, 1)) { | |
2543 | return CP_ACCESS_TRAP_EL2; | |
2544 | } | |
2545 | } | |
2546 | } | |
2547 | break; | |
0b6440af | 2548 | } |
00108f2d PM |
2549 | return CP_ACCESS_OK; |
2550 | } | |
2551 | ||
2552 | static CPAccessResult gt_pct_access(CPUARMState *env, | |
3f208fd7 PM |
2553 | const ARMCPRegInfo *ri, |
2554 | bool isread) | |
00108f2d | 2555 | { |
3f208fd7 | 2556 | return gt_counter_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2557 | } |
2558 | ||
2559 | static CPAccessResult gt_vct_access(CPUARMState *env, | |
3f208fd7 PM |
2560 | const ARMCPRegInfo *ri, |
2561 | bool isread) | |
00108f2d | 2562 | { |
3f208fd7 | 2563 | return gt_counter_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2564 | } |
2565 | ||
3f208fd7 PM |
2566 | static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2567 | bool isread) | |
00108f2d | 2568 | { |
3f208fd7 | 2569 | return gt_timer_access(env, GTIMER_PHYS, isread); |
00108f2d PM |
2570 | } |
2571 | ||
3f208fd7 PM |
2572 | static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri, |
2573 | bool isread) | |
00108f2d | 2574 | { |
3f208fd7 | 2575 | return gt_timer_access(env, GTIMER_VIRT, isread); |
00108f2d PM |
2576 | } |
2577 | ||
b4d3978c | 2578 | static CPAccessResult gt_stimer_access(CPUARMState *env, |
3f208fd7 PM |
2579 | const ARMCPRegInfo *ri, |
2580 | bool isread) | |
b4d3978c | 2581 | { |
9b37a28c FR |
2582 | /* |
2583 | * The AArch64 register view of the secure physical timer is | |
b4d3978c PM |
2584 | * always accessible from EL3, and configurably accessible from |
2585 | * Secure EL1. | |
2586 | */ | |
2587 | switch (arm_current_el(env)) { | |
2588 | case 1: | |
2589 | if (!arm_is_secure(env)) { | |
2590 | return CP_ACCESS_TRAP; | |
2591 | } | |
2592 | if (!(env->cp15.scr_el3 & SCR_ST)) { | |
2593 | return CP_ACCESS_TRAP_EL3; | |
2594 | } | |
2595 | return CP_ACCESS_OK; | |
2596 | case 0: | |
2597 | case 2: | |
2598 | return CP_ACCESS_TRAP; | |
2599 | case 3: | |
2600 | return CP_ACCESS_OK; | |
2601 | default: | |
2602 | g_assert_not_reached(); | |
2603 | } | |
2604 | } | |
2605 | ||
55d284af PM |
2606 | static uint64_t gt_get_countervalue(CPUARMState *env) |
2607 | { | |
7def8754 AJ |
2608 | ARMCPU *cpu = env_archcpu(env); |
2609 | ||
2610 | return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu); | |
55d284af PM |
2611 | } |
2612 | ||
f6fc36de JPB |
2613 | static void gt_update_irq(ARMCPU *cpu, int timeridx) |
2614 | { | |
2615 | CPUARMState *env = &cpu->env; | |
2616 | uint64_t cnthctl = env->cp15.cnthctl_el2; | |
2617 | ARMSecuritySpace ss = arm_security_space(env); | |
2618 | /* ISTATUS && !IMASK */ | |
2619 | int irqstate = (env->cp15.c14_timer[timeridx].ctl & 6) == 4; | |
2620 | ||
2621 | /* | |
2622 | * If bit CNTHCTL_EL2.CNT[VP]MASK is set, it overrides IMASK. | |
2623 | * It is RES0 in Secure and NonSecure state. | |
2624 | */ | |
2625 | if ((ss == ARMSS_Root || ss == ARMSS_Realm) && | |
2626 | ((timeridx == GTIMER_VIRT && (cnthctl & CNTHCTL_CNTVMASK)) || | |
2627 | (timeridx == GTIMER_PHYS && (cnthctl & CNTHCTL_CNTPMASK)))) { | |
2628 | irqstate = 0; | |
2629 | } | |
2630 | ||
2631 | qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); | |
2632 | trace_arm_gt_update_irq(timeridx, irqstate); | |
2633 | } | |
2634 | ||
2635 | void gt_rme_post_el_change(ARMCPU *cpu, void *ignored) | |
2636 | { | |
2637 | /* | |
2638 | * Changing security state between Root and Secure/NonSecure, which may | |
2639 | * happen when switching EL, can change the effective value of CNTHCTL_EL2 | |
2640 | * mask bits. Update the IRQ state accordingly. | |
2641 | */ | |
2642 | gt_update_irq(cpu, GTIMER_VIRT); | |
2643 | gt_update_irq(cpu, GTIMER_PHYS); | |
2644 | } | |
2645 | ||
55d284af PM |
2646 | static void gt_recalc_timer(ARMCPU *cpu, int timeridx) |
2647 | { | |
2648 | ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx]; | |
2649 | ||
2650 | if (gt->ctl & 1) { | |
9b37a28c FR |
2651 | /* |
2652 | * Timer enabled: calculate and set current ISTATUS, irq, and | |
55d284af PM |
2653 | * reset timer to when ISTATUS next has to change |
2654 | */ | |
edac4d8a EI |
2655 | uint64_t offset = timeridx == GTIMER_VIRT ? |
2656 | cpu->env.cp15.cntvoff_el2 : 0; | |
55d284af PM |
2657 | uint64_t count = gt_get_countervalue(&cpu->env); |
2658 | /* Note that this must be unsigned 64 bit arithmetic: */ | |
edac4d8a | 2659 | int istatus = count - offset >= gt->cval; |
55d284af PM |
2660 | uint64_t nexttick; |
2661 | ||
2662 | gt->ctl = deposit32(gt->ctl, 2, 1, istatus); | |
194cbc49 | 2663 | |
55d284af | 2664 | if (istatus) { |
8d37a142 PM |
2665 | /* |
2666 | * Next transition is when (count - offset) rolls back over to 0. | |
2667 | * If offset > count then this is when count == offset; | |
2668 | * if offset <= count then this is when count == offset + 2^64 | |
2669 | * For the latter case we set nexttick to an "as far in future | |
2670 | * as possible" value and let the code below handle it. | |
2671 | */ | |
2672 | if (offset > count) { | |
2673 | nexttick = offset; | |
2674 | } else { | |
2675 | nexttick = UINT64_MAX; | |
2676 | } | |
55d284af | 2677 | } else { |
8d37a142 PM |
2678 | /* |
2679 | * Next transition is when (count - offset) == cval, i.e. | |
2680 | * when count == (cval + offset). | |
2681 | * If that would overflow, then again we set up the next interrupt | |
2682 | * for "as far in the future as possible" for the code below. | |
2683 | */ | |
2684 | if (uadd64_overflow(gt->cval, offset, &nexttick)) { | |
2685 | nexttick = UINT64_MAX; | |
2686 | } | |
55d284af | 2687 | } |
9b37a28c FR |
2688 | /* |
2689 | * Note that the desired next expiry time might be beyond the | |
55d284af PM |
2690 | * signed-64-bit range of a QEMUTimer -- in this case we just |
2691 | * set the timer for as far in the future as possible. When the | |
2692 | * timer expires we will reset the timer for any remaining period. | |
2693 | */ | |
7def8754 | 2694 | if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { |
4a0245b6 AJ |
2695 | timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX); |
2696 | } else { | |
2697 | timer_mod(cpu->gt_timer[timeridx], nexttick); | |
55d284af | 2698 | } |
f6fc36de | 2699 | trace_arm_gt_recalc(timeridx, nexttick); |
55d284af PM |
2700 | } else { |
2701 | /* Timer disabled: ISTATUS and timer output always clear */ | |
2702 | gt->ctl &= ~4; | |
bc72ad67 | 2703 | timer_del(cpu->gt_timer[timeridx]); |
194cbc49 | 2704 | trace_arm_gt_recalc_disabled(timeridx); |
55d284af | 2705 | } |
f6fc36de | 2706 | gt_update_irq(cpu, timeridx); |
55d284af PM |
2707 | } |
2708 | ||
0e3eca4c EI |
2709 | static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, |
2710 | int timeridx) | |
55d284af | 2711 | { |
2fc0cc0e | 2712 | ARMCPU *cpu = env_archcpu(env); |
55d284af | 2713 | |
bc72ad67 | 2714 | timer_del(cpu->gt_timer[timeridx]); |
55d284af PM |
2715 | } |
2716 | ||
c4241c7d | 2717 | static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
55d284af | 2718 | { |
c4241c7d | 2719 | return gt_get_countervalue(env); |
55d284af PM |
2720 | } |
2721 | ||
53d1f856 RH |
2722 | static uint64_t gt_virt_cnt_offset(CPUARMState *env) |
2723 | { | |
2724 | uint64_t hcr; | |
2725 | ||
2726 | switch (arm_current_el(env)) { | |
2727 | case 2: | |
2728 | hcr = arm_hcr_el2_eff(env); | |
2729 | if (hcr & HCR_E2H) { | |
2730 | return 0; | |
2731 | } | |
2732 | break; | |
2733 | case 0: | |
2734 | hcr = arm_hcr_el2_eff(env); | |
2735 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
2736 | return 0; | |
2737 | } | |
2738 | break; | |
2739 | } | |
2740 | ||
2741 | return env->cp15.cntvoff_el2; | |
2742 | } | |
2743 | ||
edac4d8a EI |
2744 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) |
2745 | { | |
53d1f856 | 2746 | return gt_get_countervalue(env) - gt_virt_cnt_offset(env); |
edac4d8a EI |
2747 | } |
2748 | ||
c4241c7d | 2749 | static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2750 | int timeridx, |
c4241c7d | 2751 | uint64_t value) |
55d284af | 2752 | { |
194cbc49 | 2753 | trace_arm_gt_cval_write(timeridx, value); |
55d284af | 2754 | env->cp15.c14_timer[timeridx].cval = value; |
2fc0cc0e | 2755 | gt_recalc_timer(env_archcpu(env), timeridx); |
55d284af | 2756 | } |
c4241c7d | 2757 | |
0e3eca4c EI |
2758 | static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, |
2759 | int timeridx) | |
55d284af | 2760 | { |
53d1f856 RH |
2761 | uint64_t offset = 0; |
2762 | ||
2763 | switch (timeridx) { | |
2764 | case GTIMER_VIRT: | |
8c94b071 | 2765 | case GTIMER_HYPVIRT: |
53d1f856 RH |
2766 | offset = gt_virt_cnt_offset(env); |
2767 | break; | |
2768 | } | |
55d284af | 2769 | |
c4241c7d | 2770 | return (uint32_t)(env->cp15.c14_timer[timeridx].cval - |
edac4d8a | 2771 | (gt_get_countervalue(env) - offset)); |
55d284af PM |
2772 | } |
2773 | ||
c4241c7d | 2774 | static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2775 | int timeridx, |
c4241c7d | 2776 | uint64_t value) |
55d284af | 2777 | { |
53d1f856 RH |
2778 | uint64_t offset = 0; |
2779 | ||
2780 | switch (timeridx) { | |
2781 | case GTIMER_VIRT: | |
8c94b071 | 2782 | case GTIMER_HYPVIRT: |
53d1f856 RH |
2783 | offset = gt_virt_cnt_offset(env); |
2784 | break; | |
2785 | } | |
55d284af | 2786 | |
194cbc49 | 2787 | trace_arm_gt_tval_write(timeridx, value); |
edac4d8a | 2788 | env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + |
18084b2f | 2789 | sextract64(value, 0, 32); |
2fc0cc0e | 2790 | gt_recalc_timer(env_archcpu(env), timeridx); |
55d284af PM |
2791 | } |
2792 | ||
c4241c7d | 2793 | static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
0e3eca4c | 2794 | int timeridx, |
c4241c7d | 2795 | uint64_t value) |
55d284af | 2796 | { |
2fc0cc0e | 2797 | ARMCPU *cpu = env_archcpu(env); |
55d284af PM |
2798 | uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; |
2799 | ||
194cbc49 | 2800 | trace_arm_gt_ctl_write(timeridx, value); |
d3afacc7 | 2801 | env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value); |
55d284af PM |
2802 | if ((oldval ^ value) & 1) { |
2803 | /* Enable toggled */ | |
2804 | gt_recalc_timer(cpu, timeridx); | |
d3afacc7 | 2805 | } else if ((oldval ^ value) & 2) { |
9b37a28c FR |
2806 | /* |
2807 | * IMASK toggled: don't need to recalculate, | |
55d284af PM |
2808 | * just set the interrupt line based on ISTATUS |
2809 | */ | |
f6fc36de JPB |
2810 | trace_arm_gt_imask_toggle(timeridx); |
2811 | gt_update_irq(cpu, timeridx); | |
55d284af | 2812 | } |
55d284af PM |
2813 | } |
2814 | ||
0e3eca4c EI |
2815 | static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2816 | { | |
2817 | gt_timer_reset(env, ri, GTIMER_PHYS); | |
2818 | } | |
2819 | ||
2820 | static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2821 | uint64_t value) | |
2822 | { | |
2823 | gt_cval_write(env, ri, GTIMER_PHYS, value); | |
2824 | } | |
2825 | ||
2826 | static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2827 | { | |
2828 | return gt_tval_read(env, ri, GTIMER_PHYS); | |
2829 | } | |
2830 | ||
2831 | static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2832 | uint64_t value) | |
2833 | { | |
2834 | gt_tval_write(env, ri, GTIMER_PHYS, value); | |
2835 | } | |
2836 | ||
2837 | static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2838 | uint64_t value) | |
2839 | { | |
2840 | gt_ctl_write(env, ri, GTIMER_PHYS, value); | |
2841 | } | |
2842 | ||
bb5972e4 RH |
2843 | static int gt_phys_redir_timeridx(CPUARMState *env) |
2844 | { | |
2845 | switch (arm_mmu_idx(env)) { | |
2846 | case ARMMMUIdx_E20_0: | |
2847 | case ARMMMUIdx_E20_2: | |
452ef8cb | 2848 | case ARMMMUIdx_E20_2_PAN: |
bb5972e4 RH |
2849 | return GTIMER_HYP; |
2850 | default: | |
2851 | return GTIMER_PHYS; | |
2852 | } | |
2853 | } | |
2854 | ||
2855 | static int gt_virt_redir_timeridx(CPUARMState *env) | |
2856 | { | |
2857 | switch (arm_mmu_idx(env)) { | |
2858 | case ARMMMUIdx_E20_0: | |
2859 | case ARMMMUIdx_E20_2: | |
452ef8cb | 2860 | case ARMMMUIdx_E20_2_PAN: |
bb5972e4 RH |
2861 | return GTIMER_HYPVIRT; |
2862 | default: | |
2863 | return GTIMER_VIRT; | |
2864 | } | |
2865 | } | |
2866 | ||
2867 | static uint64_t gt_phys_redir_cval_read(CPUARMState *env, | |
2868 | const ARMCPRegInfo *ri) | |
2869 | { | |
2870 | int timeridx = gt_phys_redir_timeridx(env); | |
2871 | return env->cp15.c14_timer[timeridx].cval; | |
2872 | } | |
2873 | ||
2874 | static void gt_phys_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2875 | uint64_t value) | |
2876 | { | |
2877 | int timeridx = gt_phys_redir_timeridx(env); | |
2878 | gt_cval_write(env, ri, timeridx, value); | |
2879 | } | |
2880 | ||
2881 | static uint64_t gt_phys_redir_tval_read(CPUARMState *env, | |
2882 | const ARMCPRegInfo *ri) | |
2883 | { | |
2884 | int timeridx = gt_phys_redir_timeridx(env); | |
2885 | return gt_tval_read(env, ri, timeridx); | |
2886 | } | |
2887 | ||
2888 | static void gt_phys_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2889 | uint64_t value) | |
2890 | { | |
2891 | int timeridx = gt_phys_redir_timeridx(env); | |
2892 | gt_tval_write(env, ri, timeridx, value); | |
2893 | } | |
2894 | ||
2895 | static uint64_t gt_phys_redir_ctl_read(CPUARMState *env, | |
2896 | const ARMCPRegInfo *ri) | |
2897 | { | |
2898 | int timeridx = gt_phys_redir_timeridx(env); | |
2899 | return env->cp15.c14_timer[timeridx].ctl; | |
2900 | } | |
2901 | ||
2902 | static void gt_phys_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2903 | uint64_t value) | |
2904 | { | |
2905 | int timeridx = gt_phys_redir_timeridx(env); | |
2906 | gt_ctl_write(env, ri, timeridx, value); | |
2907 | } | |
2908 | ||
0e3eca4c EI |
2909 | static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
2910 | { | |
2911 | gt_timer_reset(env, ri, GTIMER_VIRT); | |
2912 | } | |
2913 | ||
2914 | static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2915 | uint64_t value) | |
2916 | { | |
2917 | gt_cval_write(env, ri, GTIMER_VIRT, value); | |
2918 | } | |
2919 | ||
2920 | static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
2921 | { | |
2922 | return gt_tval_read(env, ri, GTIMER_VIRT); | |
2923 | } | |
2924 | ||
2925 | static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2926 | uint64_t value) | |
2927 | { | |
2928 | gt_tval_write(env, ri, GTIMER_VIRT, value); | |
2929 | } | |
2930 | ||
2931 | static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2932 | uint64_t value) | |
2933 | { | |
2934 | gt_ctl_write(env, ri, GTIMER_VIRT, value); | |
2935 | } | |
2936 | ||
f6fc36de JPB |
2937 | static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2938 | uint64_t value) | |
2939 | { | |
2940 | ARMCPU *cpu = env_archcpu(env); | |
2941 | uint32_t oldval = env->cp15.cnthctl_el2; | |
2942 | ||
2943 | raw_write(env, ri, value); | |
2944 | ||
2945 | if ((oldval ^ value) & CNTHCTL_CNTVMASK) { | |
2946 | gt_update_irq(cpu, GTIMER_VIRT); | |
2947 | } else if ((oldval ^ value) & CNTHCTL_CNTPMASK) { | |
2948 | gt_update_irq(cpu, GTIMER_PHYS); | |
2949 | } | |
2950 | } | |
2951 | ||
edac4d8a EI |
2952 | static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, |
2953 | uint64_t value) | |
2954 | { | |
2fc0cc0e | 2955 | ARMCPU *cpu = env_archcpu(env); |
edac4d8a | 2956 | |
194cbc49 | 2957 | trace_arm_gt_cntvoff_write(value); |
edac4d8a EI |
2958 | raw_write(env, ri, value); |
2959 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
2960 | } | |
2961 | ||
bb5972e4 RH |
2962 | static uint64_t gt_virt_redir_cval_read(CPUARMState *env, |
2963 | const ARMCPRegInfo *ri) | |
2964 | { | |
2965 | int timeridx = gt_virt_redir_timeridx(env); | |
2966 | return env->cp15.c14_timer[timeridx].cval; | |
2967 | } | |
2968 | ||
2969 | static void gt_virt_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2970 | uint64_t value) | |
2971 | { | |
2972 | int timeridx = gt_virt_redir_timeridx(env); | |
2973 | gt_cval_write(env, ri, timeridx, value); | |
2974 | } | |
2975 | ||
2976 | static uint64_t gt_virt_redir_tval_read(CPUARMState *env, | |
2977 | const ARMCPRegInfo *ri) | |
2978 | { | |
2979 | int timeridx = gt_virt_redir_timeridx(env); | |
2980 | return gt_tval_read(env, ri, timeridx); | |
2981 | } | |
2982 | ||
2983 | static void gt_virt_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2984 | uint64_t value) | |
2985 | { | |
2986 | int timeridx = gt_virt_redir_timeridx(env); | |
2987 | gt_tval_write(env, ri, timeridx, value); | |
2988 | } | |
2989 | ||
2990 | static uint64_t gt_virt_redir_ctl_read(CPUARMState *env, | |
2991 | const ARMCPRegInfo *ri) | |
2992 | { | |
2993 | int timeridx = gt_virt_redir_timeridx(env); | |
2994 | return env->cp15.c14_timer[timeridx].ctl; | |
2995 | } | |
2996 | ||
2997 | static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
2998 | uint64_t value) | |
2999 | { | |
3000 | int timeridx = gt_virt_redir_timeridx(env); | |
3001 | gt_ctl_write(env, ri, timeridx, value); | |
3002 | } | |
3003 | ||
b0e66d95 EI |
3004 | static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
3005 | { | |
3006 | gt_timer_reset(env, ri, GTIMER_HYP); | |
3007 | } | |
3008 | ||
3009 | static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3010 | uint64_t value) | |
3011 | { | |
3012 | gt_cval_write(env, ri, GTIMER_HYP, value); | |
3013 | } | |
3014 | ||
3015 | static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3016 | { | |
3017 | return gt_tval_read(env, ri, GTIMER_HYP); | |
3018 | } | |
3019 | ||
3020 | static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3021 | uint64_t value) | |
3022 | { | |
3023 | gt_tval_write(env, ri, GTIMER_HYP, value); | |
3024 | } | |
3025 | ||
3026 | static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3027 | uint64_t value) | |
3028 | { | |
3029 | gt_ctl_write(env, ri, GTIMER_HYP, value); | |
3030 | } | |
3031 | ||
b4d3978c PM |
3032 | static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
3033 | { | |
3034 | gt_timer_reset(env, ri, GTIMER_SEC); | |
3035 | } | |
3036 | ||
3037 | static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3038 | uint64_t value) | |
3039 | { | |
3040 | gt_cval_write(env, ri, GTIMER_SEC, value); | |
3041 | } | |
3042 | ||
3043 | static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3044 | { | |
3045 | return gt_tval_read(env, ri, GTIMER_SEC); | |
3046 | } | |
3047 | ||
3048 | static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3049 | uint64_t value) | |
3050 | { | |
3051 | gt_tval_write(env, ri, GTIMER_SEC, value); | |
3052 | } | |
3053 | ||
3054 | static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3055 | uint64_t value) | |
3056 | { | |
3057 | gt_ctl_write(env, ri, GTIMER_SEC, value); | |
3058 | } | |
3059 | ||
8c94b071 RH |
3060 | static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) |
3061 | { | |
3062 | gt_timer_reset(env, ri, GTIMER_HYPVIRT); | |
3063 | } | |
3064 | ||
3065 | static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3066 | uint64_t value) | |
3067 | { | |
3068 | gt_cval_write(env, ri, GTIMER_HYPVIRT, value); | |
3069 | } | |
3070 | ||
3071 | static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3072 | { | |
3073 | return gt_tval_read(env, ri, GTIMER_HYPVIRT); | |
3074 | } | |
3075 | ||
3076 | static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3077 | uint64_t value) | |
3078 | { | |
3079 | gt_tval_write(env, ri, GTIMER_HYPVIRT, value); | |
3080 | } | |
3081 | ||
3082 | static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3083 | uint64_t value) | |
3084 | { | |
3085 | gt_ctl_write(env, ri, GTIMER_HYPVIRT, value); | |
3086 | } | |
3087 | ||
55d284af PM |
3088 | void arm_gt_ptimer_cb(void *opaque) |
3089 | { | |
3090 | ARMCPU *cpu = opaque; | |
3091 | ||
3092 | gt_recalc_timer(cpu, GTIMER_PHYS); | |
3093 | } | |
3094 | ||
3095 | void arm_gt_vtimer_cb(void *opaque) | |
3096 | { | |
3097 | ARMCPU *cpu = opaque; | |
3098 | ||
3099 | gt_recalc_timer(cpu, GTIMER_VIRT); | |
3100 | } | |
3101 | ||
b0e66d95 EI |
3102 | void arm_gt_htimer_cb(void *opaque) |
3103 | { | |
3104 | ARMCPU *cpu = opaque; | |
3105 | ||
3106 | gt_recalc_timer(cpu, GTIMER_HYP); | |
3107 | } | |
3108 | ||
b4d3978c PM |
3109 | void arm_gt_stimer_cb(void *opaque) |
3110 | { | |
3111 | ARMCPU *cpu = opaque; | |
3112 | ||
3113 | gt_recalc_timer(cpu, GTIMER_SEC); | |
3114 | } | |
3115 | ||
8c94b071 RH |
3116 | void arm_gt_hvtimer_cb(void *opaque) |
3117 | { | |
3118 | ARMCPU *cpu = opaque; | |
3119 | ||
3120 | gt_recalc_timer(cpu, GTIMER_HYPVIRT); | |
3121 | } | |
3122 | ||
96eec6b2 AJ |
3123 | static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque) |
3124 | { | |
3125 | ARMCPU *cpu = env_archcpu(env); | |
3126 | ||
3127 | cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz; | |
3128 | } | |
3129 | ||
55d284af | 3130 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
9b37a28c FR |
3131 | /* |
3132 | * Note that CNTFRQ is purely reads-as-written for the benefit | |
55d284af PM |
3133 | * of software; writing it doesn't actually change the timer frequency. |
3134 | * Our reset value matches the fixed frequency we implement the timer at. | |
3135 | */ | |
3136 | { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 3137 | .type = ARM_CP_ALIAS, |
a7adc4b7 PM |
3138 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, |
3139 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq), | |
a7adc4b7 PM |
3140 | }, |
3141 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, | |
3142 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
3143 | .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access, | |
55d284af | 3144 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), |
96eec6b2 | 3145 | .resetfn = arm_gt_cntfrq_reset, |
55d284af PM |
3146 | }, |
3147 | /* overall control: mostly access permissions */ | |
a7adc4b7 PM |
3148 | { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH, |
3149 | .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0, | |
55d284af PM |
3150 | .access = PL1_RW, |
3151 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl), | |
3152 | .resetvalue = 0, | |
3153 | }, | |
3154 | /* per-timer control */ | |
3155 | { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, | |
9ff9dd3c | 3156 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 3157 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
a7adc4b7 PM |
3158 | .accessfn = gt_ptimer_access, |
3159 | .fieldoffset = offsetoflow32(CPUARMState, | |
3160 | cp15.c14_timer[GTIMER_PHYS].ctl), | |
bb5972e4 RH |
3161 | .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read, |
3162 | .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write, | |
a7adc4b7 | 3163 | }, |
9c513e78 | 3164 | { .name = "CNTP_CTL_S", |
9ff9dd3c PM |
3165 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1, |
3166 | .secure = ARM_CP_SECSTATE_S, | |
daf1dc5f | 3167 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
9ff9dd3c PM |
3168 | .accessfn = gt_ptimer_access, |
3169 | .fieldoffset = offsetoflow32(CPUARMState, | |
3170 | cp15.c14_timer[GTIMER_SEC].ctl), | |
3171 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
3172 | }, | |
a7adc4b7 PM |
3173 | { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64, |
3174 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1, | |
daf1dc5f | 3175 | .type = ARM_CP_IO, .access = PL0_RW, |
a7adc4b7 | 3176 | .accessfn = gt_ptimer_access, |
55d284af PM |
3177 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), |
3178 | .resetvalue = 0, | |
bb5972e4 RH |
3179 | .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read, |
3180 | .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write, | |
55d284af PM |
3181 | }, |
3182 | { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1, | |
daf1dc5f | 3183 | .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW, |
a7adc4b7 PM |
3184 | .accessfn = gt_vtimer_access, |
3185 | .fieldoffset = offsetoflow32(CPUARMState, | |
3186 | cp15.c14_timer[GTIMER_VIRT].ctl), | |
bb5972e4 RH |
3187 | .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read, |
3188 | .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write, | |
a7adc4b7 PM |
3189 | }, |
3190 | { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64, | |
3191 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1, | |
daf1dc5f | 3192 | .type = ARM_CP_IO, .access = PL0_RW, |
a7adc4b7 | 3193 | .accessfn = gt_vtimer_access, |
55d284af PM |
3194 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), |
3195 | .resetvalue = 0, | |
bb5972e4 RH |
3196 | .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read, |
3197 | .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write, | |
55d284af PM |
3198 | }, |
3199 | /* TimerValue views: a 32 bit downcounting view of the underlying state */ | |
3200 | { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, | |
9ff9dd3c | 3201 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 3202 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
00108f2d | 3203 | .accessfn = gt_ptimer_access, |
bb5972e4 | 3204 | .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write, |
55d284af | 3205 | }, |
9c513e78 | 3206 | { .name = "CNTP_TVAL_S", |
9ff9dd3c PM |
3207 | .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0, |
3208 | .secure = ARM_CP_SECSTATE_S, | |
daf1dc5f | 3209 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
9ff9dd3c PM |
3210 | .accessfn = gt_ptimer_access, |
3211 | .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write, | |
3212 | }, | |
a7adc4b7 PM |
3213 | { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
3214 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0, | |
daf1dc5f | 3215 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
0e3eca4c | 3216 | .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset, |
bb5972e4 | 3217 | .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write, |
a7adc4b7 | 3218 | }, |
55d284af | 3219 | { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0, |
daf1dc5f | 3220 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
00108f2d | 3221 | .accessfn = gt_vtimer_access, |
bb5972e4 | 3222 | .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write, |
55d284af | 3223 | }, |
a7adc4b7 PM |
3224 | { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64, |
3225 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0, | |
daf1dc5f | 3226 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW, |
0e3eca4c | 3227 | .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset, |
bb5972e4 | 3228 | .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write, |
a7adc4b7 | 3229 | }, |
55d284af PM |
3230 | /* The counter itself */ |
3231 | { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0, | |
7a0e58fa | 3232 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 3233 | .accessfn = gt_pct_access, |
a7adc4b7 PM |
3234 | .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, |
3235 | }, | |
3236 | { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64, | |
3237 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1, | |
7a0e58fa | 3238 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 3239 | .accessfn = gt_pct_access, .readfn = gt_cnt_read, |
55d284af PM |
3240 | }, |
3241 | { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, | |
7a0e58fa | 3242 | .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, |
00108f2d | 3243 | .accessfn = gt_vct_access, |
edac4d8a | 3244 | .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, |
a7adc4b7 PM |
3245 | }, |
3246 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
3247 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
7a0e58fa | 3248 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, |
d57b9ee8 | 3249 | .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read, |
55d284af PM |
3250 | }, |
3251 | /* Comparison value, indicating when the timer goes off */ | |
3252 | { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, | |
9ff9dd3c | 3253 | .secure = ARM_CP_SECSTATE_NS, |
daf1dc5f | 3254 | .access = PL0_RW, |
7a0e58fa | 3255 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 3256 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), |
b061a82b | 3257 | .accessfn = gt_ptimer_access, |
bb5972e4 RH |
3258 | .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read, |
3259 | .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write, | |
a7adc4b7 | 3260 | }, |
9c513e78 | 3261 | { .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2, |
9ff9dd3c | 3262 | .secure = ARM_CP_SECSTATE_S, |
daf1dc5f | 3263 | .access = PL0_RW, |
9ff9dd3c PM |
3264 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
3265 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
3266 | .accessfn = gt_ptimer_access, | |
3267 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
3268 | }, | |
a7adc4b7 PM |
3269 | { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64, |
3270 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2, | |
daf1dc5f | 3271 | .access = PL0_RW, |
a7adc4b7 PM |
3272 | .type = ARM_CP_IO, |
3273 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
12cde08a | 3274 | .resetvalue = 0, .accessfn = gt_ptimer_access, |
bb5972e4 RH |
3275 | .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read, |
3276 | .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write, | |
55d284af PM |
3277 | }, |
3278 | { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3, | |
daf1dc5f | 3279 | .access = PL0_RW, |
7a0e58fa | 3280 | .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, |
55d284af | 3281 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), |
b061a82b | 3282 | .accessfn = gt_vtimer_access, |
bb5972e4 RH |
3283 | .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read, |
3284 | .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write, | |
a7adc4b7 PM |
3285 | }, |
3286 | { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64, | |
3287 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2, | |
daf1dc5f | 3288 | .access = PL0_RW, |
a7adc4b7 PM |
3289 | .type = ARM_CP_IO, |
3290 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
3291 | .resetvalue = 0, .accessfn = gt_vtimer_access, | |
bb5972e4 RH |
3292 | .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read, |
3293 | .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write, | |
55d284af | 3294 | }, |
9b37a28c FR |
3295 | /* |
3296 | * Secure timer -- this is actually restricted to only EL3 | |
b4d3978c PM |
3297 | * and configurably Secure-EL1 via the accessfn. |
3298 | */ | |
3299 | { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64, | |
3300 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0, | |
3301 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW, | |
3302 | .accessfn = gt_stimer_access, | |
3303 | .readfn = gt_sec_tval_read, | |
3304 | .writefn = gt_sec_tval_write, | |
3305 | .resetfn = gt_sec_timer_reset, | |
3306 | }, | |
3307 | { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64, | |
3308 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1, | |
3309 | .type = ARM_CP_IO, .access = PL1_RW, | |
3310 | .accessfn = gt_stimer_access, | |
3311 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl), | |
3312 | .resetvalue = 0, | |
3313 | .writefn = gt_sec_ctl_write, .raw_writefn = raw_write, | |
3314 | }, | |
3315 | { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64, | |
3316 | .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2, | |
3317 | .type = ARM_CP_IO, .access = PL1_RW, | |
3318 | .accessfn = gt_stimer_access, | |
3319 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval), | |
3320 | .writefn = gt_sec_cval_write, .raw_writefn = raw_write, | |
3321 | }, | |
55d284af PM |
3322 | }; |
3323 | ||
bb5972e4 RH |
3324 | static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3325 | bool isread) | |
3326 | { | |
3327 | if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { | |
3328 | return CP_ACCESS_TRAP; | |
3329 | } | |
3330 | return CP_ACCESS_OK; | |
3331 | } | |
3332 | ||
55d284af | 3333 | #else |
26c4a83b | 3334 | |
9b37a28c FR |
3335 | /* |
3336 | * In user-mode most of the generic timer registers are inaccessible | |
26c4a83b | 3337 | * however modern kernels (4.12+) allow access to cntvct_el0 |
55d284af | 3338 | */ |
26c4a83b AB |
3339 | |
3340 | static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3341 | { | |
7def8754 AJ |
3342 | ARMCPU *cpu = env_archcpu(env); |
3343 | ||
9b37a28c FR |
3344 | /* |
3345 | * Currently we have no support for QEMUTimer in linux-user so we | |
26c4a83b AB |
3346 | * can't call gt_get_countervalue(env), instead we directly |
3347 | * call the lower level functions. | |
3348 | */ | |
7def8754 | 3349 | return cpu_get_clock() / gt_cntfrq_period_ns(cpu); |
26c4a83b AB |
3350 | } |
3351 | ||
6cc7a3ae | 3352 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
26c4a83b AB |
3353 | { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64, |
3354 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, | |
3355 | .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */, | |
3356 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), | |
3357 | .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE, | |
3358 | }, | |
3359 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, | |
3360 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, | |
3361 | .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, | |
3362 | .readfn = gt_virt_cnt_read, | |
3363 | }, | |
6cc7a3ae PM |
3364 | }; |
3365 | ||
55d284af PM |
3366 | #endif |
3367 | ||
c4241c7d | 3368 | static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
4a501606 | 3369 | { |
891a2fe7 | 3370 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
8d5c773e | 3371 | raw_write(env, ri, value); |
891a2fe7 | 3372 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
8d5c773e | 3373 | raw_write(env, ri, value & 0xfffff6ff); |
4a501606 | 3374 | } else { |
8d5c773e | 3375 | raw_write(env, ri, value & 0xfffff1ff); |
4a501606 | 3376 | } |
4a501606 PM |
3377 | } |
3378 | ||
3379 | #ifndef CONFIG_USER_ONLY | |
3380 | /* get_phys_addr() isn't present for user-mode-only targets */ | |
702a9357 | 3381 | |
3f208fd7 PM |
3382 | static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3383 | bool isread) | |
92611c00 PM |
3384 | { |
3385 | if (ri->opc2 & 4) { | |
9b37a28c FR |
3386 | /* |
3387 | * The ATS12NSO* operations must trap to EL3 or EL2 if executed in | |
87562e4f PM |
3388 | * Secure EL1 (which can only happen if EL3 is AArch64). |
3389 | * They are simply UNDEF if executed from NS EL1. | |
3390 | * They function normally from EL2 or EL3. | |
92611c00 | 3391 | */ |
87562e4f PM |
3392 | if (arm_current_el(env) == 1) { |
3393 | if (arm_is_secure_below_el3(env)) { | |
926c1b97 | 3394 | if (env->cp15.scr_el3 & SCR_EEL2) { |
ce9a8863 | 3395 | return CP_ACCESS_TRAP_EL2; |
926c1b97 | 3396 | } |
ce9a8863 | 3397 | return CP_ACCESS_TRAP_EL3; |
87562e4f PM |
3398 | } |
3399 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
3400 | } | |
92611c00 PM |
3401 | } |
3402 | return CP_ACCESS_OK; | |
3403 | } | |
3404 | ||
9fb005b0 | 3405 | #ifdef CONFIG_TCG |
b17d86eb PM |
3406 | static int par_el1_shareability(GetPhysAddrResult *res) |
3407 | { | |
3408 | /* | |
3409 | * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC | |
3410 | * memory -- see pseudocode PAREncodeShareability(). | |
3411 | */ | |
3412 | if (((res->cacheattrs.attrs & 0xf0) == 0) || | |
3413 | res->cacheattrs.attrs == 0x44 || res->cacheattrs.attrs == 0x40) { | |
3414 | return 2; | |
3415 | } | |
3416 | return res->cacheattrs.shareability; | |
3417 | } | |
3418 | ||
060e8a48 | 3419 | static uint64_t do_ats_write(CPUARMState *env, uint64_t value, |
7aee3cb9 | 3420 | MMUAccessType access_type, ARMMMUIdx mmu_idx, |
e1ee56ec | 3421 | ARMSecuritySpace ss) |
4a501606 | 3422 | { |
b7cc4e82 | 3423 | bool ret; |
01c097f7 | 3424 | uint64_t par64; |
1313e2d7 | 3425 | bool format64 = false; |
e14b5a23 | 3426 | ARMMMUFaultInfo fi = {}; |
de05a709 | 3427 | GetPhysAddrResult res = {}; |
4a501606 | 3428 | |
f1269a98 JPB |
3429 | /* |
3430 | * I_MXTJT: Granule protection checks are not performed on the final address | |
3431 | * of a successful translation. | |
3432 | */ | |
e1ee56ec JPB |
3433 | ret = get_phys_addr_with_space_nogpc(env, value, access_type, mmu_idx, ss, |
3434 | &res, &fi); | |
1313e2d7 | 3435 | |
9f225e60 PM |
3436 | /* |
3437 | * ATS operations only do S1 or S1+S2 translations, so we never | |
3438 | * have to deal with the ARMCacheAttrs format for S2 only. | |
3439 | */ | |
de05a709 | 3440 | assert(!res.cacheattrs.is_s2_format); |
9f225e60 | 3441 | |
0710b2fa PM |
3442 | if (ret) { |
3443 | /* | |
3444 | * Some kinds of translation fault must cause exceptions rather | |
3445 | * than being reported in the PAR. | |
3446 | */ | |
3447 | int current_el = arm_current_el(env); | |
3448 | int target_el; | |
3449 | uint32_t syn, fsr, fsc; | |
3450 | bool take_exc = false; | |
3451 | ||
b1a10c86 | 3452 | if (fi.s1ptw && current_el == 1 |
fee7aa46 | 3453 | && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { |
0710b2fa PM |
3454 | /* |
3455 | * Synchronous stage 2 fault on an access made as part of the | |
3456 | * translation table walk for AT S1E0* or AT S1E1* insn | |
3457 | * executed from NS EL1. If this is a synchronous external abort | |
3458 | * and SCR_EL3.EA == 1, then we take a synchronous external abort | |
3459 | * to EL3. Otherwise the fault is taken as an exception to EL2, | |
3460 | * and HPFAR_EL2 holds the faulting IPA. | |
3461 | */ | |
3462 | if (fi.type == ARMFault_SyncExternalOnWalk && | |
3463 | (env->cp15.scr_el3 & SCR_EA)) { | |
3464 | target_el = 3; | |
3465 | } else { | |
3466 | env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4; | |
9861248f RDC |
3467 | if (arm_is_secure_below_el3(env) && fi.s1ns) { |
3468 | env->cp15.hpfar_el2 |= HPFAR_NS; | |
3469 | } | |
0710b2fa PM |
3470 | target_el = 2; |
3471 | } | |
3472 | take_exc = true; | |
3473 | } else if (fi.type == ARMFault_SyncExternalOnWalk) { | |
3474 | /* | |
3475 | * Synchronous external aborts during a translation table walk | |
3476 | * are taken as Data Abort exceptions. | |
3477 | */ | |
3478 | if (fi.stage2) { | |
3479 | if (current_el == 3) { | |
3480 | target_el = 3; | |
3481 | } else { | |
3482 | target_el = 2; | |
3483 | } | |
3484 | } else { | |
3485 | target_el = exception_target_el(env); | |
3486 | } | |
3487 | take_exc = true; | |
3488 | } | |
3489 | ||
3490 | if (take_exc) { | |
3491 | /* Construct FSR and FSC using same logic as arm_deliver_fault() */ | |
3492 | if (target_el == 2 || arm_el_is_aa64(env, target_el) || | |
3493 | arm_s1_regime_using_lpae_format(env, mmu_idx)) { | |
3494 | fsr = arm_fi_to_lfsc(&fi); | |
3495 | fsc = extract32(fsr, 0, 6); | |
3496 | } else { | |
3497 | fsr = arm_fi_to_sfsc(&fi); | |
3498 | fsc = 0x3f; | |
3499 | } | |
3500 | /* | |
3501 | * Report exception with ESR indicating a fault due to a | |
3502 | * translation table walk for a cache maintenance instruction. | |
3503 | */ | |
e24fd076 | 3504 | syn = syn_data_abort_no_iss(current_el == target_el, 0, |
0710b2fa PM |
3505 | fi.ea, 1, fi.s1ptw, 1, fsc); |
3506 | env->exception.vaddress = value; | |
3507 | env->exception.fsr = fsr; | |
3508 | raise_exception(env, EXCP_DATA_ABORT, syn, target_el); | |
3509 | } | |
3510 | } | |
3511 | ||
1313e2d7 EI |
3512 | if (is_a64(env)) { |
3513 | format64 = true; | |
3514 | } else if (arm_feature(env, ARM_FEATURE_LPAE)) { | |
3515 | /* | |
3516 | * ATS1Cxx: | |
3517 | * * TTBCR.EAE determines whether the result is returned using the | |
3518 | * 32-bit or the 64-bit PAR format | |
3519 | * * Instructions executed in Hyp mode always use the 64bit format | |
3520 | * | |
3521 | * ATS1S2NSOxx uses the 64bit format if any of the following is true: | |
3522 | * * The Non-secure TTBCR.EAE bit is set to 1 | |
3523 | * * The implementation includes EL2, and the value of HCR.VM is 1 | |
3524 | * | |
9d1bab33 PM |
3525 | * (Note that HCR.DC makes HCR.VM behave as if it is 1.) |
3526 | * | |
23463e0e | 3527 | * ATS1Hx always uses the 64bit format. |
1313e2d7 EI |
3528 | */ |
3529 | format64 = arm_s1_regime_using_lpae_format(env, mmu_idx); | |
3530 | ||
3531 | if (arm_feature(env, ARM_FEATURE_EL2)) { | |
452ef8cb RH |
3532 | if (mmu_idx == ARMMMUIdx_E10_0 || |
3533 | mmu_idx == ARMMMUIdx_E10_1 || | |
3534 | mmu_idx == ARMMMUIdx_E10_1_PAN) { | |
9d1bab33 | 3535 | format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC); |
1313e2d7 EI |
3536 | } else { |
3537 | format64 |= arm_current_el(env) == 2; | |
3538 | } | |
3539 | } | |
3540 | } | |
3541 | ||
3542 | if (format64) { | |
5efe9ed4 | 3543 | /* Create a 64-bit PAR */ |
01c097f7 | 3544 | par64 = (1 << 11); /* LPAE bit always set */ |
b7cc4e82 | 3545 | if (!ret) { |
7fa7ea8f RH |
3546 | par64 |= res.f.phys_addr & ~0xfffULL; |
3547 | if (!res.f.attrs.secure) { | |
8bf5b6a9 PM |
3548 | par64 |= (1 << 9); /* NS */ |
3549 | } | |
de05a709 | 3550 | par64 |= (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */ |
b17d86eb | 3551 | par64 |= par_el1_shareability(&res) << 7; /* SH */ |
4a501606 | 3552 | } else { |
5efe9ed4 PM |
3553 | uint32_t fsr = arm_fi_to_lfsc(&fi); |
3554 | ||
702a9357 | 3555 | par64 |= 1; /* F */ |
b7cc4e82 | 3556 | par64 |= (fsr & 0x3f) << 1; /* FS */ |
0f7b791b PM |
3557 | if (fi.stage2) { |
3558 | par64 |= (1 << 9); /* S */ | |
3559 | } | |
3560 | if (fi.s1ptw) { | |
3561 | par64 |= (1 << 8); /* PTW */ | |
3562 | } | |
4a501606 PM |
3563 | } |
3564 | } else { | |
9b37a28c FR |
3565 | /* |
3566 | * fsr is a DFSR/IFSR value for the short descriptor | |
702a9357 PM |
3567 | * translation table format (with WnR always clear). |
3568 | * Convert it to a 32-bit PAR. | |
3569 | */ | |
b7cc4e82 | 3570 | if (!ret) { |
702a9357 | 3571 | /* We do not set any attribute bits in the PAR */ |
7fa7ea8f | 3572 | if (res.f.lg_page_size == 24 |
702a9357 | 3573 | && arm_feature(env, ARM_FEATURE_V7)) { |
7fa7ea8f | 3574 | par64 = (res.f.phys_addr & 0xff000000) | (1 << 1); |
702a9357 | 3575 | } else { |
7fa7ea8f | 3576 | par64 = res.f.phys_addr & 0xfffff000; |
702a9357 | 3577 | } |
7fa7ea8f | 3578 | if (!res.f.attrs.secure) { |
8bf5b6a9 PM |
3579 | par64 |= (1 << 9); /* NS */ |
3580 | } | |
702a9357 | 3581 | } else { |
5efe9ed4 PM |
3582 | uint32_t fsr = arm_fi_to_sfsc(&fi); |
3583 | ||
b7cc4e82 PC |
3584 | par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | |
3585 | ((fsr & 0xf) << 1) | 1; | |
702a9357 | 3586 | } |
4a501606 | 3587 | } |
060e8a48 PM |
3588 | return par64; |
3589 | } | |
9fb005b0 | 3590 | #endif /* CONFIG_TCG */ |
060e8a48 PM |
3591 | |
3592 | static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | |
3593 | { | |
9fb005b0 | 3594 | #ifdef CONFIG_TCG |
03ae85f8 | 3595 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
060e8a48 | 3596 | uint64_t par64; |
d3649702 PM |
3597 | ARMMMUIdx mmu_idx; |
3598 | int el = arm_current_el(env); | |
e1ee56ec | 3599 | ARMSecuritySpace ss = arm_security_space(env); |
060e8a48 | 3600 | |
d3649702 PM |
3601 | switch (ri->opc2 & 6) { |
3602 | case 0: | |
04b07d29 | 3603 | /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */ |
d3649702 PM |
3604 | switch (el) { |
3605 | case 3: | |
d902ae75 | 3606 | mmu_idx = ARMMMUIdx_E3; |
d3649702 PM |
3607 | break; |
3608 | case 2: | |
e1ee56ec | 3609 | g_assert(ss != ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit only */ |
04b07d29 | 3610 | /* fall through */ |
d3649702 | 3611 | case 1: |
04b07d29 | 3612 | if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) { |
d902ae75 | 3613 | mmu_idx = ARMMMUIdx_Stage1_E1_PAN; |
04b07d29 | 3614 | } else { |
d902ae75 | 3615 | mmu_idx = ARMMMUIdx_Stage1_E1; |
04b07d29 | 3616 | } |
d3649702 PM |
3617 | break; |
3618 | default: | |
3619 | g_assert_not_reached(); | |
3620 | } | |
3621 | break; | |
3622 | case 2: | |
3623 | /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ | |
3624 | switch (el) { | |
3625 | case 3: | |
d902ae75 | 3626 | mmu_idx = ARMMMUIdx_E10_0; |
d3649702 PM |
3627 | break; |
3628 | case 2: | |
e1ee56ec | 3629 | g_assert(ss != ARMSS_Secure); /* ARMv8.4-SecEL2 is 64-bit only */ |
2859d7b5 | 3630 | mmu_idx = ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3631 | break; |
3632 | case 1: | |
d902ae75 | 3633 | mmu_idx = ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3634 | break; |
3635 | default: | |
3636 | g_assert_not_reached(); | |
3637 | } | |
3638 | break; | |
3639 | case 4: | |
3640 | /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ | |
01b98b68 | 3641 | mmu_idx = ARMMMUIdx_E10_1; |
e1ee56ec | 3642 | ss = ARMSS_NonSecure; |
d3649702 PM |
3643 | break; |
3644 | case 6: | |
3645 | /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ | |
01b98b68 | 3646 | mmu_idx = ARMMMUIdx_E10_0; |
e1ee56ec | 3647 | ss = ARMSS_NonSecure; |
d3649702 PM |
3648 | break; |
3649 | default: | |
3650 | g_assert_not_reached(); | |
3651 | } | |
3652 | ||
e1ee56ec | 3653 | par64 = do_ats_write(env, value, access_type, mmu_idx, ss); |
01c097f7 FA |
3654 | |
3655 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
9fb005b0 PMD |
3656 | #else |
3657 | /* Handled by hardware accelerator. */ | |
3658 | g_assert_not_reached(); | |
3659 | #endif /* CONFIG_TCG */ | |
4a501606 | 3660 | } |
060e8a48 | 3661 | |
14db7fe0 PM |
3662 | static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3663 | uint64_t value) | |
3664 | { | |
9fb005b0 | 3665 | #ifdef CONFIG_TCG |
03ae85f8 | 3666 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
14db7fe0 PM |
3667 | uint64_t par64; |
3668 | ||
7aee3cb9 | 3669 | /* There is no SecureEL2 for AArch32. */ |
e1ee56ec JPB |
3670 | par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2, |
3671 | ARMSS_NonSecure); | |
14db7fe0 PM |
3672 | |
3673 | A32_BANKED_CURRENT_REG_SET(env, par, par64); | |
9fb005b0 PMD |
3674 | #else |
3675 | /* Handled by hardware accelerator. */ | |
3676 | g_assert_not_reached(); | |
3677 | #endif /* CONFIG_TCG */ | |
14db7fe0 PM |
3678 | } |
3679 | ||
1acd00ef JPB |
3680 | static CPAccessResult at_e012_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3681 | bool isread) | |
3682 | { | |
3683 | /* | |
3684 | * R_NYXTL: instruction is UNDEFINED if it applies to an Exception level | |
3685 | * lower than EL3 and the combination SCR_EL3.{NSE,NS} is reserved. This can | |
3686 | * only happen when executing at EL3 because that combination also causes an | |
3687 | * illegal exception return. We don't need to check FEAT_RME either, because | |
3688 | * scr_write() ensures that the NSE bit is not set otherwise. | |
3689 | */ | |
3690 | if ((env->cp15.scr_el3 & (SCR_NSE | SCR_NS)) == SCR_NSE) { | |
3691 | return CP_ACCESS_TRAP; | |
3692 | } | |
3693 | return CP_ACCESS_OK; | |
3694 | } | |
3695 | ||
3f208fd7 PM |
3696 | static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3697 | bool isread) | |
2a47df95 | 3698 | { |
926c1b97 RDC |
3699 | if (arm_current_el(env) == 3 && |
3700 | !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) { | |
2a47df95 PM |
3701 | return CP_ACCESS_TRAP; |
3702 | } | |
1acd00ef | 3703 | return at_e012_access(env, ri, isread); |
2a47df95 PM |
3704 | } |
3705 | ||
57259779 PM |
3706 | static CPAccessResult at_s1e01_access(CPUARMState *env, const ARMCPRegInfo *ri, |
3707 | bool isread) | |
3708 | { | |
3709 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_AT)) { | |
3710 | return CP_ACCESS_TRAP_EL2; | |
3711 | } | |
3712 | return at_e012_access(env, ri, isread); | |
3713 | } | |
3714 | ||
060e8a48 PM |
3715 | static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, |
3716 | uint64_t value) | |
3717 | { | |
9fb005b0 | 3718 | #ifdef CONFIG_TCG |
03ae85f8 | 3719 | MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD; |
d3649702 | 3720 | ARMMMUIdx mmu_idx; |
638d5dbd AK |
3721 | uint64_t hcr_el2 = arm_hcr_el2_eff(env); |
3722 | bool regime_e20 = (hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE); | |
d3649702 PM |
3723 | |
3724 | switch (ri->opc2 & 6) { | |
3725 | case 0: | |
3726 | switch (ri->opc1) { | |
04b07d29 RH |
3727 | case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ |
3728 | if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) { | |
638d5dbd AK |
3729 | mmu_idx = regime_e20 ? |
3730 | ARMMMUIdx_E20_2_PAN : ARMMMUIdx_Stage1_E1_PAN; | |
04b07d29 | 3731 | } else { |
638d5dbd | 3732 | mmu_idx = regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_Stage1_E1; |
04b07d29 | 3733 | } |
d3649702 PM |
3734 | break; |
3735 | case 4: /* AT S1E2R, AT S1E2W */ | |
638d5dbd | 3736 | mmu_idx = hcr_el2 & HCR_E2H ? ARMMMUIdx_E20_2 : ARMMMUIdx_E2; |
d3649702 PM |
3737 | break; |
3738 | case 6: /* AT S1E3R, AT S1E3W */ | |
d902ae75 | 3739 | mmu_idx = ARMMMUIdx_E3; |
d3649702 PM |
3740 | break; |
3741 | default: | |
3742 | g_assert_not_reached(); | |
3743 | } | |
3744 | break; | |
3745 | case 2: /* AT S1E0R, AT S1E0W */ | |
638d5dbd | 3746 | mmu_idx = regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_Stage1_E0; |
d3649702 PM |
3747 | break; |
3748 | case 4: /* AT S12E1R, AT S12E1W */ | |
638d5dbd | 3749 | mmu_idx = regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_E10_1; |
d3649702 PM |
3750 | break; |
3751 | case 6: /* AT S12E0R, AT S12E0W */ | |
638d5dbd | 3752 | mmu_idx = regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_E10_0; |
d3649702 PM |
3753 | break; |
3754 | default: | |
3755 | g_assert_not_reached(); | |
3756 | } | |
060e8a48 | 3757 | |
7aee3cb9 | 3758 | env->cp15.par_el[1] = do_ats_write(env, value, access_type, |
e1ee56ec | 3759 | mmu_idx, arm_security_space(env)); |
9fb005b0 PMD |
3760 | #else |
3761 | /* Handled by hardware accelerator. */ | |
3762 | g_assert_not_reached(); | |
3763 | #endif /* CONFIG_TCG */ | |
060e8a48 | 3764 | } |
4a501606 PM |
3765 | #endif |
3766 | ||
18032bec PM |
3767 | /* Return basic MPU access permission bits. */ |
3768 | static uint32_t simple_mpu_ap_bits(uint32_t val) | |
3769 | { | |
3770 | uint32_t ret; | |
3771 | uint32_t mask; | |
3772 | int i; | |
3773 | ret = 0; | |
3774 | mask = 3; | |
3775 | for (i = 0; i < 16; i += 2) { | |
3776 | ret |= (val >> i) & mask; | |
3777 | mask <<= 2; | |
3778 | } | |
3779 | return ret; | |
3780 | } | |
3781 | ||
3782 | /* Pad basic MPU access permission bits to extended format. */ | |
3783 | static uint32_t extended_mpu_ap_bits(uint32_t val) | |
3784 | { | |
3785 | uint32_t ret; | |
3786 | uint32_t mask; | |
3787 | int i; | |
3788 | ret = 0; | |
3789 | mask = 3; | |
3790 | for (i = 0; i < 16; i += 2) { | |
3791 | ret |= (val & mask) << i; | |
3792 | mask <<= 2; | |
3793 | } | |
3794 | return ret; | |
3795 | } | |
3796 | ||
c4241c7d PM |
3797 | static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3798 | uint64_t value) | |
18032bec | 3799 | { |
7e09797c | 3800 | env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3801 | } |
3802 | ||
c4241c7d | 3803 | static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3804 | { |
7e09797c | 3805 | return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); |
18032bec PM |
3806 | } |
3807 | ||
c4241c7d PM |
3808 | static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3809 | uint64_t value) | |
18032bec | 3810 | { |
7e09797c | 3811 | env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value); |
18032bec PM |
3812 | } |
3813 | ||
c4241c7d | 3814 | static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) |
18032bec | 3815 | { |
7e09797c | 3816 | return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); |
18032bec PM |
3817 | } |
3818 | ||
6cb0b013 PC |
3819 | static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) |
3820 | { | |
3821 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); | |
3822 | ||
3823 | if (!u32p) { | |
3824 | return 0; | |
3825 | } | |
3826 | ||
1bc04a88 | 3827 | u32p += env->pmsav7.rnr[M_REG_NS]; |
6cb0b013 PC |
3828 | return *u32p; |
3829 | } | |
3830 | ||
3831 | static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3832 | uint64_t value) | |
3833 | { | |
2fc0cc0e | 3834 | ARMCPU *cpu = env_archcpu(env); |
6cb0b013 PC |
3835 | uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); |
3836 | ||
3837 | if (!u32p) { | |
3838 | return; | |
3839 | } | |
3840 | ||
1bc04a88 | 3841 | u32p += env->pmsav7.rnr[M_REG_NS]; |
d10eb08f | 3842 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ |
6cb0b013 PC |
3843 | *u32p = value; |
3844 | } | |
3845 | ||
6cb0b013 PC |
3846 | static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3847 | uint64_t value) | |
3848 | { | |
2fc0cc0e | 3849 | ARMCPU *cpu = env_archcpu(env); |
6cb0b013 PC |
3850 | uint32_t nrgs = cpu->pmsav7_dregion; |
3851 | ||
3852 | if (value >= nrgs) { | |
3853 | qemu_log_mask(LOG_GUEST_ERROR, | |
3854 | "PMSAv7 RGNR write >= # supported regions, %" PRIu32 | |
3855 | " > %" PRIu32 "\n", (uint32_t)value, nrgs); | |
3856 | return; | |
3857 | } | |
3858 | ||
3859 | raw_write(env, ri, value); | |
3860 | } | |
3861 | ||
761c4642 TR |
3862 | static void prbar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
3863 | uint64_t value) | |
3864 | { | |
3865 | ARMCPU *cpu = env_archcpu(env); | |
3866 | ||
3867 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | |
3868 | env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value; | |
3869 | } | |
3870 | ||
3871 | static uint64_t prbar_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3872 | { | |
3873 | return env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; | |
3874 | } | |
3875 | ||
3876 | static void prlar_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3877 | uint64_t value) | |
3878 | { | |
3879 | ARMCPU *cpu = env_archcpu(env); | |
3880 | ||
3881 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | |
3882 | env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value; | |
3883 | } | |
3884 | ||
3885 | static uint64_t prlar_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3886 | { | |
3887 | return env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]]; | |
3888 | } | |
3889 | ||
3890 | static void prselr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3891 | uint64_t value) | |
3892 | { | |
3893 | ARMCPU *cpu = env_archcpu(env); | |
3894 | ||
3895 | /* | |
3896 | * Ignore writes that would select not implemented region. | |
3897 | * This is architecturally UNPREDICTABLE. | |
3898 | */ | |
3899 | if (value >= cpu->pmsav7_dregion) { | |
3900 | return; | |
3901 | } | |
3902 | ||
3903 | env->pmsav7.rnr[M_REG_NS] = value; | |
3904 | } | |
3905 | ||
3906 | static void hprbar_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3907 | uint64_t value) | |
3908 | { | |
3909 | ARMCPU *cpu = env_archcpu(env); | |
3910 | ||
3911 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | |
3912 | env->pmsav8.hprbar[env->pmsav8.hprselr] = value; | |
3913 | } | |
3914 | ||
3915 | static uint64_t hprbar_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3916 | { | |
3917 | return env->pmsav8.hprbar[env->pmsav8.hprselr]; | |
3918 | } | |
3919 | ||
3920 | static void hprlar_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3921 | uint64_t value) | |
3922 | { | |
3923 | ARMCPU *cpu = env_archcpu(env); | |
3924 | ||
3925 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | |
3926 | env->pmsav8.hprlar[env->pmsav8.hprselr] = value; | |
3927 | } | |
3928 | ||
3929 | static uint64_t hprlar_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3930 | { | |
3931 | return env->pmsav8.hprlar[env->pmsav8.hprselr]; | |
3932 | } | |
3933 | ||
3934 | static void hprenr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3935 | uint64_t value) | |
3936 | { | |
3937 | uint32_t n; | |
3938 | uint32_t bit; | |
3939 | ARMCPU *cpu = env_archcpu(env); | |
3940 | ||
3941 | /* Ignore writes to unimplemented regions */ | |
3942 | int rmax = MIN(cpu->pmsav8r_hdregion, 32); | |
3943 | value &= MAKE_64BIT_MASK(0, rmax); | |
3944 | ||
3945 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | |
3946 | ||
3947 | /* Register alias is only valid for first 32 indexes */ | |
3948 | for (n = 0; n < rmax; ++n) { | |
3949 | bit = extract32(value, n, 1); | |
3950 | env->pmsav8.hprlar[n] = deposit32( | |
3951 | env->pmsav8.hprlar[n], 0, 1, bit); | |
3952 | } | |
3953 | } | |
3954 | ||
3955 | static uint64_t hprenr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
3956 | { | |
3957 | uint32_t n; | |
3958 | uint32_t result = 0x0; | |
3959 | ARMCPU *cpu = env_archcpu(env); | |
3960 | ||
3961 | /* Register alias is only valid for first 32 indexes */ | |
3962 | for (n = 0; n < MIN(cpu->pmsav8r_hdregion, 32); ++n) { | |
3963 | if (env->pmsav8.hprlar[n] & 0x1) { | |
3964 | result |= (0x1 << n); | |
3965 | } | |
3966 | } | |
3967 | return result; | |
3968 | } | |
3969 | ||
3970 | static void hprselr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3971 | uint64_t value) | |
3972 | { | |
3973 | ARMCPU *cpu = env_archcpu(env); | |
3974 | ||
3975 | /* | |
3976 | * Ignore writes that would select not implemented region. | |
3977 | * This is architecturally UNPREDICTABLE. | |
3978 | */ | |
3979 | if (value >= cpu->pmsav8r_hdregion) { | |
3980 | return; | |
3981 | } | |
3982 | ||
3983 | env->pmsav8.hprselr = value; | |
3984 | } | |
3985 | ||
3986 | static void pmsav8r_regn_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
3987 | uint64_t value) | |
3988 | { | |
3989 | ARMCPU *cpu = env_archcpu(env); | |
3990 | uint8_t index = (extract32(ri->opc0, 0, 1) << 4) | | |
3991 | (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1); | |
3992 | ||
3993 | tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ | |
3994 | ||
3995 | if (ri->opc1 & 4) { | |
3996 | if (index >= cpu->pmsav8r_hdregion) { | |
3997 | return; | |
3998 | } | |
3999 | if (ri->opc2 & 0x1) { | |
4000 | env->pmsav8.hprlar[index] = value; | |
4001 | } else { | |
4002 | env->pmsav8.hprbar[index] = value; | |
4003 | } | |
4004 | } else { | |
4005 | if (index >= cpu->pmsav7_dregion) { | |
4006 | return; | |
4007 | } | |
4008 | if (ri->opc2 & 0x1) { | |
4009 | env->pmsav8.rlar[M_REG_NS][index] = value; | |
4010 | } else { | |
4011 | env->pmsav8.rbar[M_REG_NS][index] = value; | |
4012 | } | |
4013 | } | |
4014 | } | |
4015 | ||
4016 | static uint64_t pmsav8r_regn_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
4017 | { | |
4018 | ARMCPU *cpu = env_archcpu(env); | |
4019 | uint8_t index = (extract32(ri->opc0, 0, 1) << 4) | | |
4020 | (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1); | |
4021 | ||
4022 | if (ri->opc1 & 4) { | |
4023 | if (index >= cpu->pmsav8r_hdregion) { | |
4024 | return 0x0; | |
4025 | } | |
4026 | if (ri->opc2 & 0x1) { | |
4027 | return env->pmsav8.hprlar[index]; | |
4028 | } else { | |
4029 | return env->pmsav8.hprbar[index]; | |
4030 | } | |
4031 | } else { | |
4032 | if (index >= cpu->pmsav7_dregion) { | |
4033 | return 0x0; | |
4034 | } | |
4035 | if (ri->opc2 & 0x1) { | |
4036 | return env->pmsav8.rlar[M_REG_NS][index]; | |
4037 | } else { | |
4038 | return env->pmsav8.rbar[M_REG_NS][index]; | |
4039 | } | |
4040 | } | |
4041 | } | |
4042 | ||
4043 | static const ARMCPRegInfo pmsav8r_cp_reginfo[] = { | |
4044 | { .name = "PRBAR", | |
4045 | .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 0, | |
4046 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
4047 | .accessfn = access_tvm_trvm, | |
4048 | .readfn = prbar_read, .writefn = prbar_write }, | |
4049 | { .name = "PRLAR", | |
4050 | .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 1, | |
4051 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
4052 | .accessfn = access_tvm_trvm, | |
4053 | .readfn = prlar_read, .writefn = prlar_write }, | |
4054 | { .name = "PRSELR", .resetvalue = 0, | |
4055 | .cp = 15, .opc1 = 0, .crn = 6, .crm = 2, .opc2 = 1, | |
4056 | .access = PL1_RW, .accessfn = access_tvm_trvm, | |
4057 | .writefn = prselr_write, | |
4058 | .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]) }, | |
4059 | { .name = "HPRBAR", .resetvalue = 0, | |
4060 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 0, | |
4061 | .access = PL2_RW, .type = ARM_CP_NO_RAW, | |
4062 | .readfn = hprbar_read, .writefn = hprbar_write }, | |
4063 | { .name = "HPRLAR", | |
4064 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 1, | |
4065 | .access = PL2_RW, .type = ARM_CP_NO_RAW, | |
4066 | .readfn = hprlar_read, .writefn = hprlar_write }, | |
4067 | { .name = "HPRSELR", .resetvalue = 0, | |
4068 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 2, .opc2 = 1, | |
4069 | .access = PL2_RW, | |
4070 | .writefn = hprselr_write, | |
4071 | .fieldoffset = offsetof(CPUARMState, pmsav8.hprselr) }, | |
4072 | { .name = "HPRENR", | |
4073 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 1, .opc2 = 1, | |
4074 | .access = PL2_RW, .type = ARM_CP_NO_RAW, | |
4075 | .readfn = hprenr_read, .writefn = hprenr_write }, | |
4076 | }; | |
4077 | ||
6cb0b013 | 4078 | static const ARMCPRegInfo pmsav7_cp_reginfo[] = { |
9b37a28c FR |
4079 | /* |
4080 | * Reset for all these registers is handled in arm_cpu_reset(), | |
69ceea64 PM |
4081 | * because the PMSAv7 is also used by M-profile CPUs, which do |
4082 | * not register cpregs but still need the state to be reset. | |
4083 | */ | |
6cb0b013 PC |
4084 | { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0, |
4085 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
4086 | .fieldoffset = offsetof(CPUARMState, pmsav7.drbar), | |
69ceea64 PM |
4087 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
4088 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
4089 | { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2, |
4090 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
4091 | .fieldoffset = offsetof(CPUARMState, pmsav7.drsr), | |
69ceea64 PM |
4092 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
4093 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
4094 | { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4, |
4095 | .access = PL1_RW, .type = ARM_CP_NO_RAW, | |
4096 | .fieldoffset = offsetof(CPUARMState, pmsav7.dracr), | |
69ceea64 PM |
4097 | .readfn = pmsav7_read, .writefn = pmsav7_write, |
4098 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
4099 | { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0, |
4100 | .access = PL1_RW, | |
1bc04a88 | 4101 | .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), |
69ceea64 PM |
4102 | .writefn = pmsav7_rgnr_write, |
4103 | .resetfn = arm_cp_reset_ignore }, | |
6cb0b013 PC |
4104 | }; |
4105 | ||
18032bec PM |
4106 | static const ARMCPRegInfo pmsav5_cp_reginfo[] = { |
4107 | { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, | |
7a0e58fa | 4108 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 4109 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
18032bec PM |
4110 | .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, }, |
4111 | { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, | |
7a0e58fa | 4112 | .access = PL1_RW, .type = ARM_CP_ALIAS, |
7e09797c | 4113 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
18032bec PM |
4114 | .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, }, |
4115 | { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2, | |
4116 | .access = PL1_RW, | |
7e09797c PM |
4117 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap), |
4118 | .resetvalue = 0, }, | |
18032bec PM |
4119 | { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, |
4120 | .access = PL1_RW, | |
7e09797c PM |
4121 | .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap), |
4122 | .resetvalue = 0, }, | |
ecce5c3c PM |
4123 | { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, |
4124 | .access = PL1_RW, | |
4125 | .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, | |
4126 | { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, | |
4127 | .access = PL1_RW, | |
4128 | .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, | |
06d76f31 | 4129 | /* Protection region base and size registers */ |
e508a92b PM |
4130 | { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, |
4131 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4132 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) }, | |
4133 | { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0, | |
4134 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4135 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) }, | |
4136 | { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0, | |
4137 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4138 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) }, | |
4139 | { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0, | |
4140 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4141 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) }, | |
4142 | { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0, | |
4143 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4144 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) }, | |
4145 | { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0, | |
4146 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4147 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) }, | |
4148 | { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0, | |
4149 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4150 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) }, | |
4151 | { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0, | |
4152 | .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0, | |
4153 | .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) }, | |
18032bec PM |
4154 | }; |
4155 | ||
cb4a0a34 PM |
4156 | static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4157 | uint64_t value) | |
ecce5c3c | 4158 | { |
cb4a0a34 | 4159 | ARMCPU *cpu = env_archcpu(env); |
2ebcebe2 | 4160 | |
e389be16 FA |
4161 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
4162 | if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { | |
cb4a0a34 PM |
4163 | /* |
4164 | * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when | |
4165 | * using Long-descriptor translation table format | |
4166 | */ | |
e389be16 FA |
4167 | value &= ~((7 << 19) | (3 << 14) | (0xf << 3)); |
4168 | } else if (arm_feature(env, ARM_FEATURE_EL3)) { | |
cb4a0a34 PM |
4169 | /* |
4170 | * In an implementation that includes the Security Extensions | |
e389be16 FA |
4171 | * TTBCR has additional fields PD0 [4] and PD1 [5] for |
4172 | * Short-descriptor translation table format. | |
4173 | */ | |
4174 | value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; | |
4175 | } else { | |
4176 | value &= TTBCR_N; | |
4177 | } | |
e42c4db3 | 4178 | } |
e389be16 | 4179 | |
d4e6df63 | 4180 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
9b37a28c FR |
4181 | /* |
4182 | * With LPAE the TTBCR could result in a change of ASID | |
d4e6df63 PM |
4183 | * via the TTBCR.A1 bit, so do a TLB flush. |
4184 | */ | |
d10eb08f | 4185 | tlb_flush(CPU(cpu)); |
d4e6df63 | 4186 | } |
cb4a0a34 | 4187 | raw_write(env, ri, value); |
ecce5c3c PM |
4188 | } |
4189 | ||
d06dc933 | 4190 | static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, |
cb2e37df PM |
4191 | uint64_t value) |
4192 | { | |
2fc0cc0e | 4193 | ARMCPU *cpu = env_archcpu(env); |
00c8cb0a | 4194 | |
cb2e37df | 4195 | /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ |
d10eb08f | 4196 | tlb_flush(CPU(cpu)); |
cb4a0a34 | 4197 | raw_write(env, ri, value); |
cb2e37df PM |
4198 | } |
4199 | ||
327ed10f PM |
4200 | static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4201 | uint64_t value) | |
4202 | { | |
93f379b0 RH |
4203 | /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ |
4204 | if (cpreg_field_is_64bit(ri) && | |
4205 | extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { | |
2fc0cc0e | 4206 | ARMCPU *cpu = env_archcpu(env); |
d10eb08f | 4207 | tlb_flush(CPU(cpu)); |
327ed10f PM |
4208 | } |
4209 | raw_write(env, ri, value); | |
4210 | } | |
4211 | ||
ed30da8e RH |
4212 | static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4213 | uint64_t value) | |
4214 | { | |
d06dc933 RH |
4215 | /* |
4216 | * If we are running with E2&0 regime, then an ASID is active. | |
4217 | * Flush if that might be changing. Note we're not checking | |
4218 | * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that | |
4219 | * holds the active ASID, only checking the field that might. | |
4220 | */ | |
4221 | if (extract64(raw_read(env, ri) ^ value, 48, 16) && | |
4222 | (arm_hcr_el2_eff(env) & HCR_E2H)) { | |
b6ad6062 RDC |
4223 | uint16_t mask = ARMMMUIdxBit_E20_2 | |
4224 | ARMMMUIdxBit_E20_2_PAN | | |
4225 | ARMMMUIdxBit_E20_0; | |
b6ad6062 | 4226 | tlb_flush_by_mmuidx(env_cpu(env), mask); |
d06dc933 | 4227 | } |
ed30da8e RH |
4228 | raw_write(env, ri, value); |
4229 | } | |
4230 | ||
b698e9cf EI |
4231 | static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4232 | uint64_t value) | |
4233 | { | |
2fc0cc0e | 4234 | ARMCPU *cpu = env_archcpu(env); |
b698e9cf EI |
4235 | CPUState *cs = CPU(cpu); |
4236 | ||
97fa9350 RH |
4237 | /* |
4238 | * A change in VMID to the stage2 page table (Stage2) invalidates | |
575a94af | 4239 | * the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0). |
97fa9350 | 4240 | */ |
00b20ee4 | 4241 | if (extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { |
575a94af | 4242 | tlb_flush_by_mmuidx(cs, alle1_tlbmask(env)); |
b698e9cf | 4243 | } |
00b20ee4 | 4244 | raw_write(env, ri, value); |
b698e9cf EI |
4245 | } |
4246 | ||
8e5d75c9 | 4247 | static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { |
18032bec | 4248 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, |
84929218 | 4249 | .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS, |
4a7e2d73 | 4250 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s), |
b061a82b | 4251 | offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, |
18032bec | 4252 | { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, |
84929218 | 4253 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
88ca1c2d FA |
4254 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), |
4255 | offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, | |
8e5d75c9 | 4256 | { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0, |
84929218 | 4257 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
8e5d75c9 PC |
4258 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s), |
4259 | offsetof(CPUARMState, cp15.dfar_ns) } }, | |
4260 | { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, | |
4261 | .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, | |
84929218 | 4262 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
b19ed03c | 4263 | .fgt = FGT_FAR_EL1, |
84929218 | 4264 | .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), |
8e5d75c9 | 4265 | .resetvalue = 0, }, |
8e5d75c9 PC |
4266 | }; |
4267 | ||
4268 | static const ARMCPRegInfo vmsa_cp_reginfo[] = { | |
6cd8a264 RH |
4269 | { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, |
4270 | .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, | |
84929218 | 4271 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
b19ed03c | 4272 | .fgt = FGT_ESR_EL1, |
d81c519c | 4273 | .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, |
327ed10f | 4274 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af | 4275 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, |
84929218 | 4276 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
bd8db7d9 | 4277 | .fgt = FGT_TTBR0_EL1, |
587f8b33 | 4278 | .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write, |
7dd8c9af FA |
4279 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
4280 | offsetof(CPUARMState, cp15.ttbr0_ns) } }, | |
327ed10f | 4281 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, |
7dd8c9af | 4282 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, |
84929218 | 4283 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
bd8db7d9 | 4284 | .fgt = FGT_TTBR1_EL1, |
587f8b33 | 4285 | .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write, |
7dd8c9af FA |
4286 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
4287 | offsetof(CPUARMState, cp15.ttbr1_ns) } }, | |
cb2e37df PM |
4288 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, |
4289 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | |
84929218 | 4290 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
67dd8030 | 4291 | .fgt = FGT_TCR_EL1, |
84929218 | 4292 | .writefn = vmsa_tcr_el12_write, |
cb4a0a34 PM |
4293 | .raw_writefn = raw_write, |
4294 | .resetvalue = 0, | |
11f136ee | 4295 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, |
cb2e37df | 4296 | { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, |
84929218 RH |
4297 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4298 | .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, | |
cb4a0a34 PM |
4299 | .raw_writefn = raw_write, |
4300 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), | |
4301 | offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, | |
18032bec PM |
4302 | }; |
4303 | ||
9b37a28c FR |
4304 | /* |
4305 | * Note that unlike TTBCR, writing to TTBCR2 does not require flushing | |
ab638a32 RH |
4306 | * qemu tlbs nor adjusting cached masks. |
4307 | */ | |
4308 | static const ARMCPRegInfo ttbcr2_reginfo = { | |
4309 | .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3, | |
84929218 RH |
4310 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4311 | .type = ARM_CP_ALIAS, | |
d102058e | 4312 | .bank_fieldoffsets = { |
cb4a0a34 PM |
4313 | offsetofhigh32(CPUARMState, cp15.tcr_el[3]), |
4314 | offsetofhigh32(CPUARMState, cp15.tcr_el[1]), | |
d102058e | 4315 | }, |
ab638a32 RH |
4316 | }; |
4317 | ||
c4241c7d PM |
4318 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4319 | uint64_t value) | |
1047b9d7 PM |
4320 | { |
4321 | env->cp15.c15_ticonfig = value & 0xe7; | |
4322 | /* The OS_TYPE bit in this register changes the reported CPUID! */ | |
4323 | env->cp15.c0_cpuid = (value & (1 << 5)) ? | |
4324 | ARM_CPUID_TI915T : ARM_CPUID_TI925T; | |
1047b9d7 PM |
4325 | } |
4326 | ||
c4241c7d PM |
4327 | static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4328 | uint64_t value) | |
1047b9d7 PM |
4329 | { |
4330 | env->cp15.c15_threadid = value & 0xffff; | |
1047b9d7 PM |
4331 | } |
4332 | ||
c4241c7d PM |
4333 | static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4334 | uint64_t value) | |
1047b9d7 PM |
4335 | { |
4336 | /* Wait-for-interrupt (deprecated) */ | |
2fc0cc0e | 4337 | cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); |
1047b9d7 PM |
4338 | } |
4339 | ||
c4241c7d PM |
4340 | static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4341 | uint64_t value) | |
c4804214 | 4342 | { |
9b37a28c FR |
4343 | /* |
4344 | * On OMAP there are registers indicating the max/min index of dcache lines | |
c4804214 PM |
4345 | * containing a dirty line; cache flush operations have to reset these. |
4346 | */ | |
4347 | env->cp15.c15_i_max = 0x000; | |
4348 | env->cp15.c15_i_min = 0xff0; | |
c4804214 PM |
4349 | } |
4350 | ||
18032bec PM |
4351 | static const ARMCPRegInfo omap_cp_reginfo[] = { |
4352 | { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, | |
4353 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, | |
d81c519c | 4354 | .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), |
6cd8a264 | 4355 | .resetvalue = 0, }, |
1047b9d7 PM |
4356 | { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
4357 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
4358 | { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
4359 | .access = PL1_RW, | |
4360 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0, | |
4361 | .writefn = omap_ticonfig_write }, | |
4362 | { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0, | |
4363 | .access = PL1_RW, | |
4364 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, }, | |
4365 | { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0, | |
4366 | .access = PL1_RW, .resetvalue = 0xff0, | |
4367 | .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) }, | |
4368 | { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0, | |
4369 | .access = PL1_RW, | |
4370 | .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0, | |
4371 | .writefn = omap_threadid_write }, | |
4372 | { .name = "TI925T_STATUS", .cp = 15, .crn = 15, | |
4373 | .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
7a0e58fa | 4374 | .type = ARM_CP_NO_RAW, |
1047b9d7 | 4375 | .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, }, |
9b37a28c FR |
4376 | /* |
4377 | * TODO: Peripheral port remap register: | |
1047b9d7 PM |
4378 | * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller |
4379 | * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), | |
4380 | * when MMU is off. | |
4381 | */ | |
c4804214 | 4382 | { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY, |
d4e6df63 | 4383 | .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, |
7a0e58fa | 4384 | .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW, |
c4804214 | 4385 | .writefn = omap_cachemaint_write }, |
34f90529 PM |
4386 | { .name = "C9", .cp = 15, .crn = 9, |
4387 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, | |
4388 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, | |
1047b9d7 PM |
4389 | }; |
4390 | ||
c4241c7d PM |
4391 | static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4392 | uint64_t value) | |
1047b9d7 | 4393 | { |
c0f4af17 | 4394 | env->cp15.c15_cpar = value & 0x3fff; |
1047b9d7 PM |
4395 | } |
4396 | ||
4397 | static const ARMCPRegInfo xscale_cp_reginfo[] = { | |
4398 | { .name = "XSCALE_CPAR", | |
4399 | .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, | |
4400 | .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0, | |
4401 | .writefn = xscale_cpar_write, }, | |
2771db27 PM |
4402 | { .name = "XSCALE_AUXCR", |
4403 | .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, | |
4404 | .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), | |
4405 | .resetvalue = 0, }, | |
9b37a28c FR |
4406 | /* |
4407 | * XScale specific cache-lockdown: since we have no cache we NOP these | |
3b771579 PM |
4408 | * and hope the guest does not really rely on cache behaviour. |
4409 | */ | |
4410 | { .name = "XSCALE_LOCK_ICACHE_LINE", | |
4411 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, | |
4412 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4413 | { .name = "XSCALE_UNLOCK_ICACHE", | |
4414 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, | |
4415 | .access = PL1_W, .type = ARM_CP_NOP }, | |
4416 | { .name = "XSCALE_DCACHE_LOCK", | |
4417 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, | |
4418 | .access = PL1_RW, .type = ARM_CP_NOP }, | |
4419 | { .name = "XSCALE_UNLOCK_DCACHE", | |
4420 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, | |
4421 | .access = PL1_W, .type = ARM_CP_NOP }, | |
1047b9d7 PM |
4422 | }; |
4423 | ||
4424 | static const ARMCPRegInfo dummy_c15_cp_reginfo[] = { | |
9b37a28c FR |
4425 | /* |
4426 | * RAZ/WI the whole crn=15 space, when we don't have a more specific | |
1047b9d7 PM |
4427 | * implementation of this implementation-defined space. |
4428 | * Ideally this should eventually disappear in favour of actually | |
4429 | * implementing the correct behaviour for all cores. | |
4430 | */ | |
4431 | { .name = "C15_IMPDEF", .cp = 15, .crn = 15, | |
4432 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
3671cd87 | 4433 | .access = PL1_RW, |
7a0e58fa | 4434 | .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, |
d4e6df63 | 4435 | .resetvalue = 0 }, |
18032bec PM |
4436 | }; |
4437 | ||
c4804214 PM |
4438 | static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = { |
4439 | /* Cache status: RAZ because we have no cache so it's always clean */ | |
4440 | { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6, | |
7a0e58fa | 4441 | .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4442 | .resetvalue = 0 }, |
c4804214 PM |
4443 | }; |
4444 | ||
4445 | static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { | |
a07d9df0 | 4446 | /* We never have a block transfer operation in progress */ |
c4804214 | 4447 | { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, |
7a0e58fa | 4448 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4449 | .resetvalue = 0 }, |
30b05bba PM |
4450 | /* The cache ops themselves: these all NOP for QEMU */ |
4451 | { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, | |
04215eb1 | 4452 | .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, |
30b05bba | 4453 | { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, |
04215eb1 | 4454 | .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, |
30b05bba | 4455 | { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, |
04215eb1 | 4456 | .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, |
30b05bba | 4457 | { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, |
04215eb1 | 4458 | .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, |
30b05bba | 4459 | { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, |
04215eb1 | 4460 | .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, |
30b05bba | 4461 | { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, |
04215eb1 | 4462 | .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT }, |
c4804214 PM |
4463 | }; |
4464 | ||
4465 | static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = { | |
9b37a28c FR |
4466 | /* |
4467 | * The cache test-and-clean instructions always return (1 << 30) | |
c4804214 PM |
4468 | * to indicate that there are no dirty cache lines. |
4469 | */ | |
4470 | { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3, | |
7a0e58fa | 4471 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4472 | .resetvalue = (1 << 30) }, |
c4804214 | 4473 | { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3, |
7a0e58fa | 4474 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW, |
d4e6df63 | 4475 | .resetvalue = (1 << 30) }, |
c4804214 PM |
4476 | }; |
4477 | ||
34f90529 PM |
4478 | static const ARMCPRegInfo strongarm_cp_reginfo[] = { |
4479 | /* Ignore ReadBuffer accesses */ | |
4480 | { .name = "C9_READBUFFER", .cp = 15, .crn = 9, | |
4481 | .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, | |
d4e6df63 | 4482 | .access = PL1_RW, .resetvalue = 0, |
7a0e58fa | 4483 | .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, |
34f90529 PM |
4484 | }; |
4485 | ||
731de9e6 EI |
4486 | static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4487 | { | |
731de9e6 | 4488 | unsigned int cur_el = arm_current_el(env); |
731de9e6 | 4489 | |
e6ef0169 | 4490 | if (arm_is_el2_enabled(env) && cur_el == 1) { |
731de9e6 EI |
4491 | return env->cp15.vpidr_el2; |
4492 | } | |
4493 | return raw_read(env, ri); | |
4494 | } | |
4495 | ||
06a7e647 | 4496 | static uint64_t mpidr_read_val(CPUARMState *env) |
81bdde9d | 4497 | { |
2fc0cc0e | 4498 | ARMCPU *cpu = env_archcpu(env); |
eb5e1d3c PF |
4499 | uint64_t mpidr = cpu->mp_affinity; |
4500 | ||
81bdde9d | 4501 | if (arm_feature(env, ARM_FEATURE_V7MP)) { |
78dbbbe4 | 4502 | mpidr |= (1U << 31); |
9b37a28c FR |
4503 | /* |
4504 | * Cores which are uniprocessor (non-coherent) | |
81bdde9d | 4505 | * but still implement the MP extensions set |
a8e81b31 | 4506 | * bit 30. (For instance, Cortex-R5). |
81bdde9d | 4507 | */ |
a8e81b31 PC |
4508 | if (cpu->mp_is_up) { |
4509 | mpidr |= (1u << 30); | |
4510 | } | |
81bdde9d | 4511 | } |
c4241c7d | 4512 | return mpidr; |
81bdde9d PM |
4513 | } |
4514 | ||
06a7e647 EI |
4515 | static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4516 | { | |
f0d574d6 | 4517 | unsigned int cur_el = arm_current_el(env); |
f0d574d6 | 4518 | |
e6ef0169 | 4519 | if (arm_is_el2_enabled(env) && cur_el == 1) { |
f0d574d6 EI |
4520 | return env->cp15.vmpidr_el2; |
4521 | } | |
06a7e647 EI |
4522 | return mpidr_read_val(env); |
4523 | } | |
4524 | ||
7ac681cf | 4525 | static const ARMCPRegInfo lpae_cp_reginfo[] = { |
a903c449 | 4526 | /* NOP AMAIR0/1 */ |
b0fe2427 PM |
4527 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, |
4528 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, | |
84929218 | 4529 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
158c276c | 4530 | .fgt = FGT_AMAIR_EL1, |
84929218 | 4531 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
b0fe2427 | 4532 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ |
7ac681cf | 4533 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
84929218 RH |
4534 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4535 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
891a2fe7 | 4536 | { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, |
01c097f7 FA |
4537 | .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, |
4538 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), | |
4539 | offsetof(CPUARMState, cp15.par_ns)} }, | |
891a2fe7 | 4540 | { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, |
84929218 RH |
4541 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4542 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
7dd8c9af FA |
4543 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), |
4544 | offsetof(CPUARMState, cp15.ttbr0_ns) }, | |
587f8b33 | 4545 | .writefn = vmsa_ttbr_write, .raw_writefn = raw_write }, |
891a2fe7 | 4546 | { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, |
84929218 RH |
4547 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
4548 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
7dd8c9af FA |
4549 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), |
4550 | offsetof(CPUARMState, cp15.ttbr1_ns) }, | |
587f8b33 | 4551 | .writefn = vmsa_ttbr_write, .raw_writefn = raw_write }, |
7ac681cf PM |
4552 | }; |
4553 | ||
c4241c7d | 4554 | static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 4555 | { |
c4241c7d | 4556 | return vfp_get_fpcr(env); |
b0d2b7d0 PM |
4557 | } |
4558 | ||
c4241c7d PM |
4559 | static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4560 | uint64_t value) | |
b0d2b7d0 PM |
4561 | { |
4562 | vfp_set_fpcr(env, value); | |
b0d2b7d0 PM |
4563 | } |
4564 | ||
c4241c7d | 4565 | static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
b0d2b7d0 | 4566 | { |
c4241c7d | 4567 | return vfp_get_fpsr(env); |
b0d2b7d0 PM |
4568 | } |
4569 | ||
c4241c7d PM |
4570 | static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4571 | uint64_t value) | |
b0d2b7d0 PM |
4572 | { |
4573 | vfp_set_fpsr(env, value); | |
b0d2b7d0 PM |
4574 | } |
4575 | ||
3f208fd7 PM |
4576 | static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri, |
4577 | bool isread) | |
c2b820fe | 4578 | { |
aaec1432 | 4579 | if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { |
c2b820fe PM |
4580 | return CP_ACCESS_TRAP; |
4581 | } | |
4582 | return CP_ACCESS_OK; | |
4583 | } | |
4584 | ||
4585 | static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4586 | uint64_t value) | |
4587 | { | |
4588 | env->daif = value & PSTATE_DAIF; | |
4589 | } | |
4590 | ||
220f508f RH |
4591 | static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4592 | { | |
4593 | return env->pstate & PSTATE_PAN; | |
4594 | } | |
4595 | ||
4596 | static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4597 | uint64_t value) | |
4598 | { | |
4599 | env->pstate = (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN); | |
4600 | } | |
4601 | ||
4602 | static const ARMCPRegInfo pan_reginfo = { | |
4603 | .name = "PAN", .state = ARM_CP_STATE_AA64, | |
4604 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 3, | |
4605 | .type = ARM_CP_NO_RAW, .access = PL1_RW, | |
4606 | .readfn = aa64_pan_read, .writefn = aa64_pan_write | |
4607 | }; | |
4608 | ||
9eeb7a1c RH |
4609 | static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4610 | { | |
4611 | return env->pstate & PSTATE_UAO; | |
4612 | } | |
4613 | ||
4614 | static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4615 | uint64_t value) | |
4616 | { | |
4617 | env->pstate = (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO); | |
4618 | } | |
4619 | ||
4620 | static const ARMCPRegInfo uao_reginfo = { | |
4621 | .name = "UAO", .state = ARM_CP_STATE_AA64, | |
4622 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4, | |
4623 | .type = ARM_CP_NO_RAW, .access = PL1_RW, | |
4624 | .readfn = aa64_uao_read, .writefn = aa64_uao_write | |
4625 | }; | |
4626 | ||
dc8b1853 RC |
4627 | static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4628 | { | |
4629 | return env->pstate & PSTATE_DIT; | |
4630 | } | |
4631 | ||
4632 | static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4633 | uint64_t value) | |
4634 | { | |
4635 | env->pstate = (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT); | |
4636 | } | |
4637 | ||
4638 | static const ARMCPRegInfo dit_reginfo = { | |
4639 | .name = "DIT", .state = ARM_CP_STATE_AA64, | |
4640 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 5, | |
4641 | .type = ARM_CP_NO_RAW, .access = PL0_RW, | |
4642 | .readfn = aa64_dit_read, .writefn = aa64_dit_write | |
4643 | }; | |
4644 | ||
f2f68a78 RC |
4645 | static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri) |
4646 | { | |
4647 | return env->pstate & PSTATE_SSBS; | |
4648 | } | |
4649 | ||
4650 | static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4651 | uint64_t value) | |
4652 | { | |
4653 | env->pstate = (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS); | |
4654 | } | |
4655 | ||
4656 | static const ARMCPRegInfo ssbs_reginfo = { | |
4657 | .name = "SSBS", .state = ARM_CP_STATE_AA64, | |
4658 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 6, | |
4659 | .type = ARM_CP_NO_RAW, .access = PL0_RW, | |
4660 | .readfn = aa64_ssbs_read, .writefn = aa64_ssbs_write | |
4661 | }; | |
4662 | ||
38262d8a RH |
4663 | static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, |
4664 | const ARMCPRegInfo *ri, | |
4665 | bool isread) | |
8af35c37 | 4666 | { |
38262d8a RH |
4667 | /* Cache invalidate/clean to Point of Coherency or Persistence... */ |
4668 | switch (arm_current_el(env)) { | |
4669 | case 0: | |
4670 | /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ | |
4671 | if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { | |
4672 | return CP_ACCESS_TRAP; | |
4673 | } | |
4674 | /* fall through */ | |
4675 | case 1: | |
4676 | /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */ | |
4677 | if (arm_hcr_el2_eff(env) & HCR_TPCP) { | |
4678 | return CP_ACCESS_TRAP_EL2; | |
4679 | } | |
4680 | break; | |
8af35c37 PM |
4681 | } |
4682 | return CP_ACCESS_OK; | |
4683 | } | |
4684 | ||
2d3ce4c6 | 4685 | static CPAccessResult do_cacheop_pou_access(CPUARMState *env, uint64_t hcrflags) |
1bed4d2e | 4686 | { |
38262d8a | 4687 | /* Cache invalidate/clean to Point of Unification... */ |
1bed4d2e RH |
4688 | switch (arm_current_el(env)) { |
4689 | case 0: | |
4690 | /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ | |
4691 | if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { | |
4692 | return CP_ACCESS_TRAP; | |
4693 | } | |
4694 | /* fall through */ | |
4695 | case 1: | |
2d3ce4c6 PM |
4696 | /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */ |
4697 | if (arm_hcr_el2_eff(env) & hcrflags) { | |
1bed4d2e RH |
4698 | return CP_ACCESS_TRAP_EL2; |
4699 | } | |
4700 | break; | |
4701 | } | |
4702 | return CP_ACCESS_OK; | |
4703 | } | |
4704 | ||
2d3ce4c6 PM |
4705 | static CPAccessResult access_ticab(CPUARMState *env, const ARMCPRegInfo *ri, |
4706 | bool isread) | |
4707 | { | |
4708 | return do_cacheop_pou_access(env, HCR_TICAB | HCR_TPU); | |
4709 | } | |
4710 | ||
4711 | static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri, | |
4712 | bool isread) | |
4713 | { | |
4714 | return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU); | |
4715 | } | |
4716 | ||
9b37a28c FR |
4717 | /* |
4718 | * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions | |
dbb1fb27 AB |
4719 | * Page D4-1736 (DDI0487A.b) |
4720 | */ | |
4721 | ||
b7e0730d RH |
4722 | static int vae1_tlbmask(CPUARMState *env) |
4723 | { | |
e04a5752 | 4724 | uint64_t hcr = arm_hcr_el2_eff(env); |
bc944d3a | 4725 | uint16_t mask; |
e04a5752 RDC |
4726 | |
4727 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
bc944d3a RDC |
4728 | mask = ARMMMUIdxBit_E20_2 | |
4729 | ARMMMUIdxBit_E20_2_PAN | | |
4730 | ARMMMUIdxBit_E20_0; | |
b7e0730d | 4731 | } else { |
bc944d3a | 4732 | mask = ARMMMUIdxBit_E10_1 | |
452ef8cb RH |
4733 | ARMMMUIdxBit_E10_1_PAN | |
4734 | ARMMMUIdxBit_E10_0; | |
b7e0730d | 4735 | } |
bc944d3a | 4736 | return mask; |
b7e0730d RH |
4737 | } |
4738 | ||
ceaa9746 JPB |
4739 | static int vae2_tlbmask(CPUARMState *env) |
4740 | { | |
4741 | uint64_t hcr = arm_hcr_el2_eff(env); | |
4742 | uint16_t mask; | |
4743 | ||
4744 | if (hcr & HCR_E2H) { | |
4745 | mask = ARMMMUIdxBit_E20_2 | | |
4746 | ARMMMUIdxBit_E20_2_PAN | | |
4747 | ARMMMUIdxBit_E20_0; | |
4748 | } else { | |
4749 | mask = ARMMMUIdxBit_E2; | |
4750 | } | |
4751 | return mask; | |
4752 | } | |
4753 | ||
ea04dce7 RH |
4754 | /* Return 56 if TBI is enabled, 64 otherwise. */ |
4755 | static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, | |
4756 | uint64_t addr) | |
4757 | { | |
c1547bba | 4758 | uint64_t tcr = regime_tcr(env, mmu_idx); |
ea04dce7 RH |
4759 | int tbi = aa64_va_parameter_tbi(tcr, mmu_idx); |
4760 | int select = extract64(addr, 55, 1); | |
4761 | ||
4762 | return (tbi >> select) & 1 ? 56 : 64; | |
4763 | } | |
4764 | ||
4765 | static int vae1_tlbbits(CPUARMState *env, uint64_t addr) | |
4766 | { | |
b6ad6062 | 4767 | uint64_t hcr = arm_hcr_el2_eff(env); |
ea04dce7 RH |
4768 | ARMMMUIdx mmu_idx; |
4769 | ||
4770 | /* Only the regime of the mmu_idx below is significant. */ | |
b6ad6062 | 4771 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { |
ea04dce7 RH |
4772 | mmu_idx = ARMMMUIdx_E20_0; |
4773 | } else { | |
4774 | mmu_idx = ARMMMUIdx_E10_0; | |
4775 | } | |
b6ad6062 | 4776 | |
ea04dce7 RH |
4777 | return tlbbits_for_regime(env, mmu_idx, addr); |
4778 | } | |
4779 | ||
ceaa9746 JPB |
4780 | static int vae2_tlbbits(CPUARMState *env, uint64_t addr) |
4781 | { | |
4782 | uint64_t hcr = arm_hcr_el2_eff(env); | |
4783 | ARMMMUIdx mmu_idx; | |
4784 | ||
4785 | /* | |
4786 | * Only the regime of the mmu_idx below is significant. | |
4787 | * Regime EL2&0 has two ranges with separate TBI configuration, while EL2 | |
4788 | * only has one. | |
4789 | */ | |
4790 | if (hcr & HCR_E2H) { | |
4791 | mmu_idx = ARMMMUIdx_E20_2; | |
4792 | } else { | |
4793 | mmu_idx = ARMMMUIdx_E2; | |
4794 | } | |
4795 | ||
4796 | return tlbbits_for_regime(env, mmu_idx, addr); | |
4797 | } | |
4798 | ||
fd3ed969 PM |
4799 | static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4800 | uint64_t value) | |
168aa23b | 4801 | { |
29a0af61 | 4802 | CPUState *cs = env_cpu(env); |
b7e0730d | 4803 | int mask = vae1_tlbmask(env); |
dbb1fb27 | 4804 | |
b7e0730d | 4805 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
168aa23b PM |
4806 | } |
4807 | ||
b4ab8ce9 PM |
4808 | static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4809 | uint64_t value) | |
4810 | { | |
29a0af61 | 4811 | CPUState *cs = env_cpu(env); |
b7e0730d | 4812 | int mask = vae1_tlbmask(env); |
b4ab8ce9 PM |
4813 | |
4814 | if (tlb_force_broadcast(env)) { | |
527db2be RH |
4815 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
4816 | } else { | |
4817 | tlb_flush_by_mmuidx(cs, mask); | |
b4ab8ce9 | 4818 | } |
b4ab8ce9 PM |
4819 | } |
4820 | ||
85d0dc9f RH |
4821 | static int e2_tlbmask(CPUARMState *env) |
4822 | { | |
d902ae75 RH |
4823 | return (ARMMMUIdxBit_E20_0 | |
4824 | ARMMMUIdxBit_E20_2 | | |
4825 | ARMMMUIdxBit_E20_2_PAN | | |
4826 | ARMMMUIdxBit_E2); | |
85d0dc9f RH |
4827 | } |
4828 | ||
90c19cdf RH |
4829 | static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4830 | uint64_t value) | |
4831 | { | |
4832 | CPUState *cs = env_cpu(env); | |
4833 | int mask = alle1_tlbmask(env); | |
4834 | ||
4835 | tlb_flush_by_mmuidx(cs, mask); | |
4836 | } | |
4837 | ||
fd3ed969 | 4838 | static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
fa439fc5 PM |
4839 | uint64_t value) |
4840 | { | |
85d0dc9f RH |
4841 | CPUState *cs = env_cpu(env); |
4842 | int mask = e2_tlbmask(env); | |
fd3ed969 | 4843 | |
85d0dc9f | 4844 | tlb_flush_by_mmuidx(cs, mask); |
fd3ed969 PM |
4845 | } |
4846 | ||
43efaa33 PM |
4847 | static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4848 | uint64_t value) | |
4849 | { | |
2fc0cc0e | 4850 | ARMCPU *cpu = env_archcpu(env); |
43efaa33 PM |
4851 | CPUState *cs = CPU(cpu); |
4852 | ||
d902ae75 | 4853 | tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E3); |
43efaa33 PM |
4854 | } |
4855 | ||
fd3ed969 PM |
4856 | static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4857 | uint64_t value) | |
4858 | { | |
29a0af61 | 4859 | CPUState *cs = env_cpu(env); |
90c19cdf RH |
4860 | int mask = alle1_tlbmask(env); |
4861 | ||
4862 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); | |
fa439fc5 PM |
4863 | } |
4864 | ||
2bfb9d75 PM |
4865 | static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4866 | uint64_t value) | |
4867 | { | |
29a0af61 | 4868 | CPUState *cs = env_cpu(env); |
85d0dc9f | 4869 | int mask = e2_tlbmask(env); |
2bfb9d75 | 4870 | |
85d0dc9f | 4871 | tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); |
2bfb9d75 PM |
4872 | } |
4873 | ||
43efaa33 PM |
4874 | static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4875 | uint64_t value) | |
4876 | { | |
29a0af61 | 4877 | CPUState *cs = env_cpu(env); |
43efaa33 | 4878 | |
d902ae75 | 4879 | tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E3); |
43efaa33 PM |
4880 | } |
4881 | ||
fd3ed969 PM |
4882 | static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4883 | uint64_t value) | |
fa439fc5 | 4884 | { |
9b37a28c FR |
4885 | /* |
4886 | * Invalidate by VA, EL2 | |
fd3ed969 PM |
4887 | * Currently handles both VAE2 and VALE2, since we don't support |
4888 | * flush-last-level-only. | |
4889 | */ | |
85d0dc9f | 4890 | CPUState *cs = env_cpu(env); |
ceaa9746 | 4891 | int mask = vae2_tlbmask(env); |
fd3ed969 | 4892 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ceaa9746 | 4893 | int bits = vae2_tlbbits(env, pageaddr); |
fd3ed969 | 4894 | |
ceaa9746 | 4895 | tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits); |
fd3ed969 PM |
4896 | } |
4897 | ||
43efaa33 PM |
4898 | static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4899 | uint64_t value) | |
4900 | { | |
9b37a28c FR |
4901 | /* |
4902 | * Invalidate by VA, EL3 | |
43efaa33 PM |
4903 | * Currently handles both VAE3 and VALE3, since we don't support |
4904 | * flush-last-level-only. | |
4905 | */ | |
2fc0cc0e | 4906 | ARMCPU *cpu = env_archcpu(env); |
43efaa33 PM |
4907 | CPUState *cs = CPU(cpu); |
4908 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
4909 | ||
d902ae75 | 4910 | tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E3); |
43efaa33 PM |
4911 | } |
4912 | ||
fd3ed969 PM |
4913 | static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4914 | uint64_t value) | |
4915 | { | |
90c19cdf RH |
4916 | CPUState *cs = env_cpu(env); |
4917 | int mask = vae1_tlbmask(env); | |
fa439fc5 | 4918 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ea04dce7 | 4919 | int bits = vae1_tlbbits(env, pageaddr); |
fa439fc5 | 4920 | |
ea04dce7 | 4921 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); |
fa439fc5 PM |
4922 | } |
4923 | ||
b4ab8ce9 PM |
4924 | static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4925 | uint64_t value) | |
4926 | { | |
9b37a28c FR |
4927 | /* |
4928 | * Invalidate by VA, EL1&0 (AArch64 version). | |
b4ab8ce9 PM |
4929 | * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, |
4930 | * since we don't support flush-for-specific-ASID-only or | |
4931 | * flush-last-level-only. | |
4932 | */ | |
90c19cdf RH |
4933 | CPUState *cs = env_cpu(env); |
4934 | int mask = vae1_tlbmask(env); | |
b4ab8ce9 | 4935 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ea04dce7 | 4936 | int bits = vae1_tlbbits(env, pageaddr); |
b4ab8ce9 PM |
4937 | |
4938 | if (tlb_force_broadcast(env)) { | |
ea04dce7 | 4939 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); |
527db2be | 4940 | } else { |
ea04dce7 | 4941 | tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits); |
b4ab8ce9 | 4942 | } |
b4ab8ce9 PM |
4943 | } |
4944 | ||
fd3ed969 PM |
4945 | static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4946 | uint64_t value) | |
fa439fc5 | 4947 | { |
29a0af61 | 4948 | CPUState *cs = env_cpu(env); |
ceaa9746 | 4949 | int mask = vae2_tlbmask(env); |
fd3ed969 | 4950 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
ceaa9746 | 4951 | int bits = vae2_tlbbits(env, pageaddr); |
fa439fc5 | 4952 | |
ceaa9746 | 4953 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); |
fa439fc5 PM |
4954 | } |
4955 | ||
43efaa33 PM |
4956 | static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, |
4957 | uint64_t value) | |
4958 | { | |
29a0af61 | 4959 | CPUState *cs = env_cpu(env); |
43efaa33 | 4960 | uint64_t pageaddr = sextract64(value << 12, 0, 56); |
d902ae75 | 4961 | int bits = tlbbits_for_regime(env, ARMMMUIdx_E3, pageaddr); |
43efaa33 | 4962 | |
ea04dce7 | 4963 | tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, |
d902ae75 | 4964 | ARMMMUIdxBit_E3, bits); |
43efaa33 PM |
4965 | } |
4966 | ||
575a94af RH |
4967 | static int ipas2e1_tlbmask(CPUARMState *env, int64_t value) |
4968 | { | |
4969 | /* | |
4970 | * The MSB of value is the NS field, which only applies if SEL2 | |
4971 | * is implemented and SCR_EL3.NS is not set (i.e. in secure mode). | |
4972 | */ | |
4973 | return (value >= 0 | |
4974 | && cpu_isar_feature(aa64_sel2, env_archcpu(env)) | |
4975 | && arm_is_secure_below_el3(env) | |
4976 | ? ARMMMUIdxBit_Stage2_S | |
4977 | : ARMMMUIdxBit_Stage2); | |
4978 | } | |
4979 | ||
4980 | static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4981 | uint64_t value) | |
4982 | { | |
4983 | CPUState *cs = env_cpu(env); | |
4984 | int mask = ipas2e1_tlbmask(env, value); | |
4985 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
4986 | ||
4987 | if (tlb_force_broadcast(env)) { | |
4988 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); | |
4989 | } else { | |
4990 | tlb_flush_page_by_mmuidx(cs, pageaddr, mask); | |
4991 | } | |
4992 | } | |
4993 | ||
4994 | static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
4995 | uint64_t value) | |
4996 | { | |
4997 | CPUState *cs = env_cpu(env); | |
4998 | int mask = ipas2e1_tlbmask(env, value); | |
4999 | uint64_t pageaddr = sextract64(value << 12, 0, 56); | |
5000 | ||
5001 | tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); | |
5002 | } | |
5003 | ||
84940ed8 | 5004 | #ifdef TARGET_AARCH64 |
ab1cdb47 RH |
5005 | typedef struct { |
5006 | uint64_t base; | |
84940ed8 | 5007 | uint64_t length; |
ab1cdb47 RH |
5008 | } TLBIRange; |
5009 | ||
3c003f70 PM |
5010 | static ARMGranuleSize tlbi_range_tg_to_gran_size(int tg) |
5011 | { | |
5012 | /* | |
5013 | * Note that the TLBI range TG field encoding differs from both | |
5014 | * TG0 and TG1 encodings. | |
5015 | */ | |
5016 | switch (tg) { | |
5017 | case 1: | |
5018 | return Gran4K; | |
5019 | case 2: | |
5020 | return Gran16K; | |
5021 | case 3: | |
5022 | return Gran64K; | |
5023 | default: | |
5024 | return GranInvalid; | |
5025 | } | |
5026 | } | |
5027 | ||
ab1cdb47 RH |
5028 | static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, |
5029 | uint64_t value) | |
5030 | { | |
5031 | unsigned int page_size_granule, page_shift, num, scale, exponent; | |
3974ff93 RH |
5032 | /* Extract one bit to represent the va selector in use. */ |
5033 | uint64_t select = sextract64(value, 36, 1); | |
478dccbb | 5034 | ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true, false); |
ab1cdb47 | 5035 | TLBIRange ret = { }; |
3c003f70 | 5036 | ARMGranuleSize gran; |
84940ed8 | 5037 | |
84940ed8 | 5038 | page_size_granule = extract64(value, 46, 2); |
3c003f70 | 5039 | gran = tlbi_range_tg_to_gran_size(page_size_granule); |
84940ed8 | 5040 | |
3974ff93 | 5041 | /* The granule encoded in value must match the granule in use. */ |
3c003f70 | 5042 | if (gran != param.gran) { |
3974ff93 | 5043 | qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\n", |
84940ed8 | 5044 | page_size_granule); |
ab1cdb47 | 5045 | return ret; |
84940ed8 RC |
5046 | } |
5047 | ||
3c003f70 | 5048 | page_shift = arm_granule_bits(gran); |
ab1cdb47 RH |
5049 | num = extract64(value, 39, 5); |
5050 | scale = extract64(value, 44, 2); | |
84940ed8 | 5051 | exponent = (5 * scale) + 1; |
84940ed8 | 5052 | |
ab1cdb47 | 5053 | ret.length = (num + 1) << (exponent + page_shift); |
84940ed8 | 5054 | |
3974ff93 | 5055 | if (param.select) { |
d976de21 | 5056 | ret.base = sextract64(value, 0, 37); |
84940ed8 | 5057 | } else { |
d976de21 | 5058 | ret.base = extract64(value, 0, 37); |
84940ed8 | 5059 | } |
ef56c242 RH |
5060 | if (param.ds) { |
5061 | /* | |
5062 | * With DS=1, BaseADDR is always shifted 16 so that it is able | |
5063 | * to address all 52 va bits. The input address is perforce | |
5064 | * aligned on a 64k boundary regardless of translation granule. | |
5065 | */ | |
5066 | page_shift = 16; | |
5067 | } | |
d976de21 | 5068 | ret.base <<= page_shift; |
84940ed8 | 5069 | |
ab1cdb47 | 5070 | return ret; |
84940ed8 RC |
5071 | } |
5072 | ||
5073 | static void do_rvae_write(CPUARMState *env, uint64_t value, | |
5074 | int idxmap, bool synced) | |
5075 | { | |
5076 | ARMMMUIdx one_idx = ARM_MMU_IDX_A | ctz32(idxmap); | |
ab1cdb47 | 5077 | TLBIRange range; |
84940ed8 RC |
5078 | int bits; |
5079 | ||
ab1cdb47 RH |
5080 | range = tlbi_aa64_get_range(env, one_idx, value); |
5081 | bits = tlbbits_for_regime(env, one_idx, range.base); | |
84940ed8 RC |
5082 | |
5083 | if (synced) { | |
5084 | tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env), | |
ab1cdb47 RH |
5085 | range.base, |
5086 | range.length, | |
84940ed8 RC |
5087 | idxmap, |
5088 | bits); | |
5089 | } else { | |
ab1cdb47 RH |
5090 | tlb_flush_range_by_mmuidx(env_cpu(env), range.base, |
5091 | range.length, idxmap, bits); | |
84940ed8 RC |
5092 | } |
5093 | } | |
5094 | ||
5095 | static void tlbi_aa64_rvae1_write(CPUARMState *env, | |
5096 | const ARMCPRegInfo *ri, | |
5097 | uint64_t value) | |
5098 | { | |
5099 | /* | |
5100 | * Invalidate by VA range, EL1&0. | |
5101 | * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1, | |
5102 | * since we don't support flush-for-specific-ASID-only or | |
5103 | * flush-last-level-only. | |
5104 | */ | |
5105 | ||
5106 | do_rvae_write(env, value, vae1_tlbmask(env), | |
5107 | tlb_force_broadcast(env)); | |
5108 | } | |
5109 | ||
5110 | static void tlbi_aa64_rvae1is_write(CPUARMState *env, | |
5111 | const ARMCPRegInfo *ri, | |
5112 | uint64_t value) | |
5113 | { | |
5114 | /* | |
5115 | * Invalidate by VA range, Inner/Outer Shareable EL1&0. | |
5116 | * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS, | |
5117 | * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support | |
5118 | * flush-for-specific-ASID-only, flush-last-level-only or inner/outer | |
5119 | * shareable specific flushes. | |
5120 | */ | |
5121 | ||
5122 | do_rvae_write(env, value, vae1_tlbmask(env), true); | |
5123 | } | |
5124 | ||
84940ed8 RC |
5125 | static void tlbi_aa64_rvae2_write(CPUARMState *env, |
5126 | const ARMCPRegInfo *ri, | |
5127 | uint64_t value) | |
5128 | { | |
5129 | /* | |
5130 | * Invalidate by VA range, EL2. | |
5131 | * Currently handles all of RVAE2 and RVALE2, | |
5132 | * since we don't support flush-for-specific-ASID-only or | |
5133 | * flush-last-level-only. | |
5134 | */ | |
5135 | ||
5136 | do_rvae_write(env, value, vae2_tlbmask(env), | |
5137 | tlb_force_broadcast(env)); | |
5138 | ||
5139 | ||
5140 | } | |
5141 | ||
5142 | static void tlbi_aa64_rvae2is_write(CPUARMState *env, | |
5143 | const ARMCPRegInfo *ri, | |
5144 | uint64_t value) | |
5145 | { | |
5146 | /* | |
5147 | * Invalidate by VA range, Inner/Outer Shareable, EL2. | |
5148 | * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS, | |
5149 | * since we don't support flush-for-specific-ASID-only, | |
5150 | * flush-last-level-only or inner/outer shareable specific flushes. | |
5151 | */ | |
5152 | ||
5153 | do_rvae_write(env, value, vae2_tlbmask(env), true); | |
5154 | ||
5155 | } | |
5156 | ||
5157 | static void tlbi_aa64_rvae3_write(CPUARMState *env, | |
5158 | const ARMCPRegInfo *ri, | |
5159 | uint64_t value) | |
5160 | { | |
5161 | /* | |
5162 | * Invalidate by VA range, EL3. | |
5163 | * Currently handles all of RVAE3 and RVALE3, | |
5164 | * since we don't support flush-for-specific-ASID-only or | |
5165 | * flush-last-level-only. | |
5166 | */ | |
5167 | ||
d902ae75 | 5168 | do_rvae_write(env, value, ARMMMUIdxBit_E3, tlb_force_broadcast(env)); |
84940ed8 RC |
5169 | } |
5170 | ||
5171 | static void tlbi_aa64_rvae3is_write(CPUARMState *env, | |
5172 | const ARMCPRegInfo *ri, | |
5173 | uint64_t value) | |
5174 | { | |
5175 | /* | |
5176 | * Invalidate by VA range, EL3, Inner/Outer Shareable. | |
5177 | * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS, | |
5178 | * since we don't support flush-for-specific-ASID-only, | |
5179 | * flush-last-level-only or inner/outer specific flushes. | |
5180 | */ | |
5181 | ||
d902ae75 | 5182 | do_rvae_write(env, value, ARMMMUIdxBit_E3, true); |
84940ed8 | 5183 | } |
575a94af RH |
5184 | |
5185 | static void tlbi_aa64_ripas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5186 | uint64_t value) | |
5187 | { | |
5188 | do_rvae_write(env, value, ipas2e1_tlbmask(env, value), | |
5189 | tlb_force_broadcast(env)); | |
5190 | } | |
5191 | ||
5192 | static void tlbi_aa64_ripas2e1is_write(CPUARMState *env, | |
5193 | const ARMCPRegInfo *ri, | |
5194 | uint64_t value) | |
5195 | { | |
5196 | do_rvae_write(env, value, ipas2e1_tlbmask(env, value), true); | |
5197 | } | |
84940ed8 RC |
5198 | #endif |
5199 | ||
3f208fd7 PM |
5200 | static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5201 | bool isread) | |
aca3f40b | 5202 | { |
4351cb72 RH |
5203 | int cur_el = arm_current_el(env); |
5204 | ||
5205 | if (cur_el < 2) { | |
5206 | uint64_t hcr = arm_hcr_el2_eff(env); | |
5207 | ||
5208 | if (cur_el == 0) { | |
5209 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
5210 | if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) { | |
5211 | return CP_ACCESS_TRAP_EL2; | |
5212 | } | |
5213 | } else { | |
5214 | if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) { | |
5215 | return CP_ACCESS_TRAP; | |
5216 | } | |
5217 | if (hcr & HCR_TDZ) { | |
5218 | return CP_ACCESS_TRAP_EL2; | |
5219 | } | |
5220 | } | |
5221 | } else if (hcr & HCR_TDZ) { | |
5222 | return CP_ACCESS_TRAP_EL2; | |
5223 | } | |
aca3f40b PM |
5224 | } |
5225 | return CP_ACCESS_OK; | |
5226 | } | |
5227 | ||
5228 | static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5229 | { | |
2fc0cc0e | 5230 | ARMCPU *cpu = env_archcpu(env); |
aca3f40b PM |
5231 | int dzp_bit = 1 << 4; |
5232 | ||
5233 | /* DZP indicates whether DC ZVA access is allowed */ | |
3f208fd7 | 5234 | if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) { |
aca3f40b PM |
5235 | dzp_bit = 0; |
5236 | } | |
5237 | return cpu->dcz_blocksize | dzp_bit; | |
5238 | } | |
5239 | ||
3f208fd7 PM |
5240 | static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
5241 | bool isread) | |
f502cfc2 | 5242 | { |
cdcf1405 | 5243 | if (!(env->pstate & PSTATE_SP)) { |
9b37a28c FR |
5244 | /* |
5245 | * Access to SP_EL0 is undefined if it's being used as | |
f502cfc2 PM |
5246 | * the stack pointer. |
5247 | */ | |
5248 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
5249 | } | |
5250 | return CP_ACCESS_OK; | |
5251 | } | |
5252 | ||
5253 | static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
5254 | { | |
5255 | return env->pstate & PSTATE_SP; | |
5256 | } | |
5257 | ||
5258 | static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
5259 | { | |
5260 | update_spsel(env, val); | |
5261 | } | |
5262 | ||
137feaa9 FA |
5263 | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5264 | uint64_t value) | |
5265 | { | |
2fc0cc0e | 5266 | ARMCPU *cpu = env_archcpu(env); |
137feaa9 | 5267 | |
f00faf13 RH |
5268 | if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { |
5269 | /* M bit is RAZ/WI for PMSA with no MPU implemented */ | |
5270 | value &= ~SCTLR_M; | |
5271 | } | |
5272 | ||
5273 | /* ??? Lots of these bits are not implemented. */ | |
5274 | ||
5275 | if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) { | |
5276 | if (ri->opc1 == 6) { /* SCTLR_EL3 */ | |
5277 | value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); | |
5278 | } else { | |
5279 | value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | | |
5280 | SCTLR_ATA0 | SCTLR_ATA); | |
5281 | } | |
5282 | } | |
5283 | ||
137feaa9 | 5284 | if (raw_read(env, ri) == value) { |
9b37a28c FR |
5285 | /* |
5286 | * Skip the TLB flush if nothing actually changed; Linux likes | |
137feaa9 FA |
5287 | * to do a lot of pointless SCTLR writes. |
5288 | */ | |
5289 | return; | |
5290 | } | |
5291 | ||
5292 | raw_write(env, ri, value); | |
f00faf13 | 5293 | |
137feaa9 | 5294 | /* This may enable/disable the MMU, so do a TLB flush. */ |
d10eb08f | 5295 | tlb_flush(CPU(cpu)); |
2e5dcf36 | 5296 | |
2b77ad4d | 5297 | if (tcg_enabled() && ri->type & ARM_CP_SUPPRESS_TB_END) { |
2e5dcf36 RH |
5298 | /* |
5299 | * Normally we would always end the TB on an SCTLR write; see the | |
5300 | * comment in ARMCPRegInfo sctlr initialization below for why Xscale | |
5301 | * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild | |
5302 | * of hflags from the translator, so do it here. | |
5303 | */ | |
5304 | arm_rebuild_hflags(env); | |
5305 | } | |
137feaa9 FA |
5306 | } |
5307 | ||
80d2b43b PM |
5308 | static void mdcr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5309 | uint64_t value) | |
a8d64e73 | 5310 | { |
01765386 PM |
5311 | /* |
5312 | * Some MDCR_EL3 bits affect whether PMU counters are running: | |
5313 | * if we are trying to change any of those then we must | |
5314 | * bracket this update with PMU start/finish calls. | |
5315 | */ | |
5316 | bool pmu_op = (env->cp15.mdcr_el3 ^ value) & MDCR_EL3_PMU_ENABLE_BITS; | |
5317 | ||
5318 | if (pmu_op) { | |
5319 | pmu_op_start(env); | |
5320 | } | |
80d2b43b | 5321 | env->cp15.mdcr_el3 = value; |
01765386 PM |
5322 | if (pmu_op) { |
5323 | pmu_op_finish(env); | |
5324 | } | |
5325 | } | |
5326 | ||
80d2b43b PM |
5327 | static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5328 | uint64_t value) | |
5329 | { | |
5330 | /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */ | |
5331 | mdcr_el3_write(env, ri, value & SDCR_VALID_MASK); | |
5332 | } | |
5333 | ||
01765386 PM |
5334 | static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
5335 | uint64_t value) | |
5336 | { | |
5337 | /* | |
5338 | * Some MDCR_EL2 bits affect whether PMU counters are running: | |
5339 | * if we are trying to change any of those then we must | |
5340 | * bracket this update with PMU start/finish calls. | |
5341 | */ | |
5342 | bool pmu_op = (env->cp15.mdcr_el2 ^ value) & MDCR_EL2_PMU_ENABLE_BITS; | |
5343 | ||
5344 | if (pmu_op) { | |
5345 | pmu_op_start(env); | |
5346 | } | |
5347 | env->cp15.mdcr_el2 = value; | |
5348 | if (pmu_op) { | |
5349 | pmu_op_finish(env); | |
5350 | } | |
a8d64e73 PM |
5351 | } |
5352 | ||
9719f125 JH |
5353 | #ifdef CONFIG_USER_ONLY |
5354 | /* | |
5355 | * `IC IVAU` is handled to improve compatibility with JITs that dual-map their | |
5356 | * code to get around W^X restrictions, where one region is writable and the | |
5357 | * other is executable. | |
5358 | * | |
5359 | * Since the executable region is never written to we cannot detect code | |
5360 | * changes when running in user mode, and rely on the emulated JIT telling us | |
5361 | * that the code has changed by executing this instruction. | |
5362 | */ | |
5363 | static void ic_ivau_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
5364 | uint64_t value) | |
5365 | { | |
5366 | uint64_t icache_line_mask, start_address, end_address; | |
5367 | const ARMCPU *cpu; | |
5368 | ||
5369 | cpu = env_archcpu(env); | |
5370 | ||
5371 | icache_line_mask = (4 << extract32(cpu->ctr, 0, 4)) - 1; | |
5372 | start_address = value & ~icache_line_mask; | |
5373 | end_address = value | icache_line_mask; | |
5374 | ||
5375 | mmap_lock(); | |
5376 | ||
5377 | tb_invalidate_phys_range(start_address, end_address); | |
5378 | ||
5379 | mmap_unlock(); | |
5380 | } | |
5381 | #endif | |
5382 | ||
b0d2b7d0 | 5383 | static const ARMCPRegInfo v8_cp_reginfo[] = { |
9b37a28c FR |
5384 | /* |
5385 | * Minimal set of EL0-visible registers. This will need to be expanded | |
b0d2b7d0 PM |
5386 | * significantly for system emulation of AArch64 CPUs. |
5387 | */ | |
5388 | { .name = "NZCV", .state = ARM_CP_STATE_AA64, | |
5389 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, | |
5390 | .access = PL0_RW, .type = ARM_CP_NZCV }, | |
c2b820fe PM |
5391 | { .name = "DAIF", .state = ARM_CP_STATE_AA64, |
5392 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, | |
7a0e58fa | 5393 | .type = ARM_CP_NO_RAW, |
c2b820fe PM |
5394 | .access = PL0_RW, .accessfn = aa64_daif_access, |
5395 | .fieldoffset = offsetof(CPUARMState, daif), | |
5396 | .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, | |
b0d2b7d0 PM |
5397 | { .name = "FPCR", .state = ARM_CP_STATE_AA64, |
5398 | .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, | |
b916c9c3 | 5399 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 5400 | .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, |
b0d2b7d0 PM |
5401 | { .name = "FPSR", .state = ARM_CP_STATE_AA64, |
5402 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4, | |
b916c9c3 | 5403 | .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, |
fe03d45f | 5404 | .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write }, |
b0d2b7d0 PM |
5405 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, |
5406 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, | |
7a0e58fa | 5407 | .access = PL0_R, .type = ARM_CP_NO_RAW, |
b19ed03c | 5408 | .fgt = FGT_DCZID_EL0, |
aca3f40b PM |
5409 | .readfn = aa64_dczid_read }, |
5410 | { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, | |
5411 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, | |
5412 | .access = PL0_W, .type = ARM_CP_DC_ZVA, | |
5413 | #ifndef CONFIG_USER_ONLY | |
5414 | /* Avoid overhead of an access check that always passes in user-mode */ | |
5415 | .accessfn = aa64_zva_access, | |
dd345653 | 5416 | .fgt = FGT_DCZVA, |
aca3f40b PM |
5417 | #endif |
5418 | }, | |
0eef9d98 PM |
5419 | { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, |
5420 | .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, | |
5421 | .access = PL1_R, .type = ARM_CP_CURRENTEL }, | |
9719f125 JH |
5422 | /* |
5423 | * Instruction cache ops. All of these except `IC IVAU` NOP because we | |
5424 | * don't emulate caches. | |
5425 | */ | |
8af35c37 PM |
5426 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, |
5427 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
38262d8a | 5428 | .access = PL1_W, .type = ARM_CP_NOP, |
dd345653 | 5429 | .fgt = FGT_ICIALLUIS, |
2d3ce4c6 | 5430 | .accessfn = access_ticab }, |
8af35c37 PM |
5431 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, |
5432 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
38262d8a | 5433 | .access = PL1_W, .type = ARM_CP_NOP, |
dd345653 | 5434 | .fgt = FGT_ICIALLU, |
2d3ce4c6 | 5435 | .accessfn = access_tocu }, |
8af35c37 PM |
5436 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, |
5437 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | |
9719f125 | 5438 | .access = PL0_W, |
dd345653 | 5439 | .fgt = FGT_ICIVAU, |
9719f125 JH |
5440 | .accessfn = access_tocu, |
5441 | #ifdef CONFIG_USER_ONLY | |
5442 | .type = ARM_CP_NO_RAW, | |
5443 | .writefn = ic_ivau_write | |
5444 | #else | |
5445 | .type = ARM_CP_NOP | |
5446 | #endif | |
5447 | }, | |
5448 | /* Cache ops: all NOPs since we don't emulate caches */ | |
8af35c37 PM |
5449 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, |
5450 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
1bed4d2e | 5451 | .access = PL1_W, .accessfn = aa64_cacheop_poc_access, |
dd345653 | 5452 | .fgt = FGT_DCIVAC, |
1bed4d2e | 5453 | .type = ARM_CP_NOP }, |
8af35c37 PM |
5454 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, |
5455 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, | |
dd345653 | 5456 | .fgt = FGT_DCISW, |
1803d271 | 5457 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
8af35c37 PM |
5458 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, |
5459 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | |
5460 | .access = PL0_W, .type = ARM_CP_NOP, | |
950037e2 | 5461 | .fgt = FGT_DCCVAC, |
1bed4d2e | 5462 | .accessfn = aa64_cacheop_poc_access }, |
8af35c37 PM |
5463 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, |
5464 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | |
dd345653 | 5465 | .fgt = FGT_DCCSW, |
1803d271 | 5466 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
8af35c37 PM |
5467 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, |
5468 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | |
5469 | .access = PL0_W, .type = ARM_CP_NOP, | |
dd345653 | 5470 | .fgt = FGT_DCCVAU, |
2d3ce4c6 | 5471 | .accessfn = access_tocu }, |
8af35c37 PM |
5472 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, |
5473 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | |
5474 | .access = PL0_W, .type = ARM_CP_NOP, | |
dd345653 | 5475 | .fgt = FGT_DCCIVAC, |
1bed4d2e | 5476 | .accessfn = aa64_cacheop_poc_access }, |
8af35c37 PM |
5477 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, |
5478 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | |
dd345653 | 5479 | .fgt = FGT_DCCISW, |
1803d271 | 5480 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
168aa23b PM |
5481 | /* TLBI operations */ |
5482 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | |
6ab9f499 | 5483 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, |
0f66d223 | 5484 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5485 | .fgt = FGT_TLBIVMALLE1IS, |
fd3ed969 | 5486 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 5487 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5488 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, |
0f66d223 | 5489 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5490 | .fgt = FGT_TLBIVAE1IS, |
fd3ed969 | 5491 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 5492 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5493 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, |
0f66d223 | 5494 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5495 | .fgt = FGT_TLBIASIDE1IS, |
fd3ed969 | 5496 | .writefn = tlbi_aa64_vmalle1is_write }, |
168aa23b | 5497 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5498 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, |
0f66d223 | 5499 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5500 | .fgt = FGT_TLBIVAAE1IS, |
fd3ed969 | 5501 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 5502 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5503 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
0f66d223 | 5504 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5505 | .fgt = FGT_TLBIVALE1IS, |
fd3ed969 | 5506 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 5507 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5508 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
0f66d223 | 5509 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5510 | .fgt = FGT_TLBIVAALE1IS, |
fd3ed969 | 5511 | .writefn = tlbi_aa64_vae1is_write }, |
168aa23b | 5512 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5513 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, |
30881b73 | 5514 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5515 | .fgt = FGT_TLBIVMALLE1, |
fd3ed969 | 5516 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 5517 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5518 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, |
30881b73 | 5519 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5520 | .fgt = FGT_TLBIVAE1, |
fd3ed969 | 5521 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 5522 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5523 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, |
30881b73 | 5524 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5525 | .fgt = FGT_TLBIASIDE1, |
fd3ed969 | 5526 | .writefn = tlbi_aa64_vmalle1_write }, |
168aa23b | 5527 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5528 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, |
30881b73 | 5529 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5530 | .fgt = FGT_TLBIVAAE1, |
fd3ed969 | 5531 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 5532 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5533 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
30881b73 | 5534 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5535 | .fgt = FGT_TLBIVALE1, |
fd3ed969 | 5536 | .writefn = tlbi_aa64_vae1_write }, |
168aa23b | 5537 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, |
6ab9f499 | 5538 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
30881b73 | 5539 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 5540 | .fgt = FGT_TLBIVAALE1, |
fd3ed969 | 5541 | .writefn = tlbi_aa64_vae1_write }, |
cea66e91 PM |
5542 | { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, |
5543 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
575a94af RH |
5544 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
5545 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
cea66e91 PM |
5546 | { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, |
5547 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
575a94af RH |
5548 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
5549 | .writefn = tlbi_aa64_ipas2e1is_write }, | |
83ddf975 PM |
5550 | { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, |
5551 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
5552 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 5553 | .writefn = tlbi_aa64_alle1is_write }, |
43efaa33 PM |
5554 | { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64, |
5555 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6, | |
5556 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
5557 | .writefn = tlbi_aa64_alle1is_write }, | |
cea66e91 PM |
5558 | { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, |
5559 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
575a94af RH |
5560 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
5561 | .writefn = tlbi_aa64_ipas2e1_write }, | |
cea66e91 PM |
5562 | { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, |
5563 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
575a94af RH |
5564 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
5565 | .writefn = tlbi_aa64_ipas2e1_write }, | |
83ddf975 PM |
5566 | { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, |
5567 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
5568 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
fd3ed969 | 5569 | .writefn = tlbi_aa64_alle1_write }, |
43efaa33 PM |
5570 | { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64, |
5571 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6, | |
5572 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
5573 | .writefn = tlbi_aa64_alle1is_write }, | |
19525524 PM |
5574 | #ifndef CONFIG_USER_ONLY |
5575 | /* 64 bit address translation operations */ | |
5576 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | |
5577 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, | |
0710b2fa | 5578 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
132c98cd | 5579 | .fgt = FGT_ATS1E1R, |
57259779 | 5580 | .accessfn = at_s1e01_access, .writefn = ats_write64 }, |
19525524 PM |
5581 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, |
5582 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, | |
0710b2fa | 5583 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
132c98cd | 5584 | .fgt = FGT_ATS1E1W, |
57259779 | 5585 | .accessfn = at_s1e01_access, .writefn = ats_write64 }, |
19525524 PM |
5586 | { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, |
5587 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, | |
0710b2fa | 5588 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
132c98cd | 5589 | .fgt = FGT_ATS1E0R, |
57259779 | 5590 | .accessfn = at_s1e01_access, .writefn = ats_write64 }, |
19525524 PM |
5591 | { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, |
5592 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, | |
0710b2fa | 5593 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
132c98cd | 5594 | .fgt = FGT_ATS1E0W, |
57259779 | 5595 | .accessfn = at_s1e01_access, .writefn = ats_write64 }, |
2a47df95 | 5596 | { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 5597 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, |
0710b2fa | 5598 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
1acd00ef | 5599 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
2a47df95 | 5600 | { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64, |
7a379c7e | 5601 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5, |
0710b2fa | 5602 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
1acd00ef | 5603 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
2a47df95 | 5604 | { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64, |
7a379c7e | 5605 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6, |
0710b2fa | 5606 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
1acd00ef | 5607 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
2a47df95 | 5608 | { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64, |
7a379c7e | 5609 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7, |
0710b2fa | 5610 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
1acd00ef | 5611 | .accessfn = at_e012_access, .writefn = ats_write64 }, |
2a47df95 PM |
5612 | /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */ |
5613 | { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64, | |
5614 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0, | |
0710b2fa PM |
5615 | .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
5616 | .writefn = ats_write64 }, | |
2a47df95 PM |
5617 | { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64, |
5618 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1, | |
0710b2fa PM |
5619 | .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
5620 | .writefn = ats_write64 }, | |
c96fc9b5 EI |
5621 | { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, |
5622 | .type = ARM_CP_ALIAS, | |
5623 | .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, | |
5624 | .access = PL1_RW, .resetvalue = 0, | |
67dd8030 | 5625 | .fgt = FGT_PAR_EL1, |
c96fc9b5 EI |
5626 | .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), |
5627 | .writefn = par_write }, | |
19525524 | 5628 | #endif |
995939a6 | 5629 | /* TLB invalidate last level of translation table walk */ |
9449fdf6 | 5630 | { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, |
0f66d223 | 5631 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, |
30881b73 | 5632 | .writefn = tlbimva_is_write }, |
9449fdf6 | 5633 | { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, |
0f66d223 | 5634 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, |
fa439fc5 | 5635 | .writefn = tlbimvaa_is_write }, |
9449fdf6 | 5636 | { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, |
30881b73 RH |
5637 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
5638 | .writefn = tlbimva_write }, | |
9449fdf6 | 5639 | { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, |
30881b73 RH |
5640 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, |
5641 | .writefn = tlbimvaa_write }, | |
541ef8c2 SS |
5642 | { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, |
5643 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5644 | .writefn = tlbimva_hyp_write }, | |
5645 | { .name = "TLBIMVALHIS", | |
5646 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
5647 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
5648 | .writefn = tlbimva_hyp_is_write }, | |
5649 | { .name = "TLBIIPAS2", | |
5650 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | |
575a94af RH |
5651 | .type = ARM_CP_NO_RAW, .access = PL2_W, |
5652 | .writefn = tlbiipas2_hyp_write }, | |
541ef8c2 SS |
5653 | { .name = "TLBIIPAS2IS", |
5654 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | |
575a94af RH |
5655 | .type = ARM_CP_NO_RAW, .access = PL2_W, |
5656 | .writefn = tlbiipas2is_hyp_write }, | |
541ef8c2 SS |
5657 | { .name = "TLBIIPAS2L", |
5658 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | |
575a94af RH |
5659 | .type = ARM_CP_NO_RAW, .access = PL2_W, |
5660 | .writefn = tlbiipas2_hyp_write }, | |
541ef8c2 SS |
5661 | { .name = "TLBIIPAS2LIS", |
5662 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | |
575a94af RH |
5663 | .type = ARM_CP_NO_RAW, .access = PL2_W, |
5664 | .writefn = tlbiipas2is_hyp_write }, | |
9449fdf6 PM |
5665 | /* 32 bit cache operations */ |
5666 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | |
2d3ce4c6 | 5667 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_ticab }, |
9449fdf6 PM |
5668 | { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, |
5669 | .type = ARM_CP_NOP, .access = PL1_W }, | |
5670 | { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | |
2d3ce4c6 | 5671 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu }, |
9449fdf6 | 5672 | { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, |
2d3ce4c6 | 5673 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu }, |
9449fdf6 PM |
5674 | { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, |
5675 | .type = ARM_CP_NOP, .access = PL1_W }, | |
5676 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | |
5677 | .type = ARM_CP_NOP, .access = PL1_W }, | |
5678 | { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | |
1bed4d2e | 5679 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 5680 | { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, |
1803d271 | 5681 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 5682 | { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, |
1bed4d2e | 5683 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 5684 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, |
1803d271 | 5685 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 5686 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, |
2d3ce4c6 | 5687 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu }, |
9449fdf6 | 5688 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, |
1bed4d2e | 5689 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, |
9449fdf6 | 5690 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, |
1803d271 | 5691 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
9449fdf6 | 5692 | /* MMU Domain access control / MPU write buffer control */ |
0c17d68c | 5693 | { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, |
84929218 | 5694 | .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0, |
0c17d68c FA |
5695 | .writefn = dacr_write, .raw_writefn = raw_write, |
5696 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s), | |
5697 | offsetoflow32(CPUARMState, cp15.dacr_ns) } }, | |
a0618a19 | 5698 | { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5699 | .type = ARM_CP_ALIAS, |
a0618a19 | 5700 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, |
6947f059 EI |
5701 | .access = PL1_RW, |
5702 | .fieldoffset = offsetof(CPUARMState, elr_el[1]) }, | |
a65f1de9 | 5703 | { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 5704 | .type = ARM_CP_ALIAS, |
a65f1de9 | 5705 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
5706 | .access = PL1_RW, |
5707 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, | |
9b37a28c FR |
5708 | /* |
5709 | * We rely on the access checks not allowing the guest to write to the | |
f502cfc2 PM |
5710 | * state field when SPSel indicates that it's being used as the stack |
5711 | * pointer. | |
5712 | */ | |
5713 | { .name = "SP_EL0", .state = ARM_CP_STATE_AA64, | |
5714 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0, | |
5715 | .access = PL1_RW, .accessfn = sp_el0_access, | |
7a0e58fa | 5716 | .type = ARM_CP_ALIAS, |
f502cfc2 | 5717 | .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, |
884b4dee GB |
5718 | { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, |
5719 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, | |
beeec926 | 5720 | .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_KEEP, |
884b4dee | 5721 | .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, |
f502cfc2 PM |
5722 | { .name = "SPSel", .state = ARM_CP_STATE_AA64, |
5723 | .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, | |
7a0e58fa | 5724 | .type = ARM_CP_NO_RAW, |
f502cfc2 | 5725 | .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, |
6a43e0b6 PM |
5726 | { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64, |
5727 | .type = ARM_CP_ALIAS, | |
5728 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0, | |
5729 | .access = PL2_RW, | |
5730 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, | |
5731 | { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64, | |
5732 | .type = ARM_CP_ALIAS, | |
5733 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1, | |
5734 | .access = PL2_RW, | |
5735 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, | |
5736 | { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64, | |
5737 | .type = ARM_CP_ALIAS, | |
5738 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2, | |
5739 | .access = PL2_RW, | |
5740 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) }, | |
5741 | { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64, | |
5742 | .type = ARM_CP_ALIAS, | |
5743 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3, | |
5744 | .access = PL2_RW, | |
5745 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, | |
a8d64e73 | 5746 | { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, |
80d2b43b | 5747 | .type = ARM_CP_IO, |
a8d64e73 PM |
5748 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, |
5749 | .resetvalue = 0, | |
80d2b43b PM |
5750 | .access = PL3_RW, |
5751 | .writefn = mdcr_el3_write, | |
5752 | .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) }, | |
7f4fbfb5 | 5753 | { .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO, |
a8d64e73 PM |
5754 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1, |
5755 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, | |
5756 | .writefn = sdcr_write, | |
5757 | .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) }, | |
b0d2b7d0 PM |
5758 | }; |
5759 | ||
c36a0d57 PM |
5760 | /* These are present only when EL1 supports AArch32 */ |
5761 | static const ARMCPRegInfo v8_aa32_el1_reginfo[] = { | |
5762 | { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, | |
5763 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, | |
5764 | .access = PL2_RW, | |
5765 | .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, | |
5766 | .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, | |
5767 | { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64, | |
5768 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0, | |
5769 | .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, | |
5770 | .writefn = dacr_write, .raw_writefn = raw_write, | |
5771 | .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) }, | |
5772 | { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, | |
5773 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, | |
5774 | .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP, | |
5775 | .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, | |
5776 | }; | |
5777 | ||
d1fb4da2 | 5778 | static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) |
f149e3e8 | 5779 | { |
2fc0cc0e | 5780 | ARMCPU *cpu = env_archcpu(env); |
d1fb4da2 RH |
5781 | |
5782 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
5783 | valid_mask |= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */ | |
5784 | } else { | |
5785 | valid_mask |= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */ | |
5786 | } | |
f149e3e8 EI |
5787 | |
5788 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
5789 | valid_mask &= ~HCR_HCD; | |
77077a83 | 5790 | } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) { |
9b37a28c FR |
5791 | /* |
5792 | * Architecturally HCR.TSC is RES0 if EL3 is not implemented. | |
77077a83 JK |
5793 | * However, if we're using the SMC PSCI conduit then QEMU is |
5794 | * effectively acting like EL3 firmware and so the guest at | |
5795 | * EL2 should retain the ability to prevent EL1 from being | |
5796 | * able to make SMC calls into the ersatz firmware, so in | |
5797 | * that case HCR.TSC should be read/write. | |
5798 | */ | |
f149e3e8 EI |
5799 | valid_mask &= ~HCR_TSC; |
5800 | } | |
d1fb4da2 RH |
5801 | |
5802 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
5803 | if (cpu_isar_feature(aa64_vh, cpu)) { | |
5804 | valid_mask |= HCR_E2H; | |
5805 | } | |
da3d8b13 RH |
5806 | if (cpu_isar_feature(aa64_ras, cpu)) { |
5807 | valid_mask |= HCR_TERR | HCR_TEA; | |
5808 | } | |
d1fb4da2 RH |
5809 | if (cpu_isar_feature(aa64_lor, cpu)) { |
5810 | valid_mask |= HCR_TLOR; | |
5811 | } | |
5812 | if (cpu_isar_feature(aa64_pauth, cpu)) { | |
5813 | valid_mask |= HCR_API | HCR_APK; | |
5814 | } | |
8ddb300b RH |
5815 | if (cpu_isar_feature(aa64_mte, cpu)) { |
5816 | valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5; | |
5817 | } | |
7cb1e618 RH |
5818 | if (cpu_isar_feature(aa64_scxtnum, cpu)) { |
5819 | valid_mask |= HCR_ENSCXT; | |
5820 | } | |
8c7e17ef PM |
5821 | if (cpu_isar_feature(aa64_fwb, cpu)) { |
5822 | valid_mask |= HCR_FWB; | |
5823 | } | |
aa3cc42c RH |
5824 | if (cpu_isar_feature(aa64_rme, cpu)) { |
5825 | valid_mask |= HCR_GPF; | |
5826 | } | |
67e55c73 PM |
5827 | if (cpu_isar_feature(aa64_nv, cpu)) { |
5828 | valid_mask |= HCR_NV | HCR_NV1 | HCR_AT; | |
5829 | } | |
ef682cdb | 5830 | } |
f149e3e8 | 5831 | |
d2fd9313 PM |
5832 | if (cpu_isar_feature(any_evt, cpu)) { |
5833 | valid_mask |= HCR_TTLBIS | HCR_TTLBOS | HCR_TICAB | HCR_TOCU | HCR_TID4; | |
5834 | } else if (cpu_isar_feature(any_half_evt, cpu)) { | |
5835 | valid_mask |= HCR_TICAB | HCR_TOCU | HCR_TID4; | |
5836 | } | |
5837 | ||
f149e3e8 EI |
5838 | /* Clear RES0 bits. */ |
5839 | value &= valid_mask; | |
5840 | ||
8ddb300b RH |
5841 | /* |
5842 | * These bits change the MMU setup: | |
f149e3e8 EI |
5843 | * HCR_VM enables stage 2 translation |
5844 | * HCR_PTW forbids certain page-table setups | |
8ddb300b RH |
5845 | * HCR_DC disables stage1 and enables stage2 translation |
5846 | * HCR_DCT enables tagging on (disabled) stage1 translation | |
8c7e17ef | 5847 | * HCR_FWB changes the interpretation of stage2 descriptor bits |
67e55c73 | 5848 | * HCR_NV and HCR_NV1 affect interpretation of descriptor bits |
f149e3e8 | 5849 | */ |
8c7e17ef | 5850 | if ((env->cp15.hcr_el2 ^ value) & |
67e55c73 | 5851 | (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT | HCR_FWB | HCR_NV | HCR_NV1)) { |
d10eb08f | 5852 | tlb_flush(CPU(cpu)); |
f149e3e8 | 5853 | } |
ce4afed8 | 5854 | env->cp15.hcr_el2 = value; |
89430fc6 PM |
5855 | |
5856 | /* | |
5857 | * Updates to VI and VF require us to update the status of | |
5858 | * virtual interrupts, which are the logical OR of these bits | |
5859 | * and the state of the input lines from the GIC. (This requires | |
a4a411fb | 5860 | * that we have the BQL, which is done by marking the |
89430fc6 PM |
5861 | * reginfo structs as ARM_CP_IO.) |
5862 | * Note that if a write to HCR pends a VIRQ or VFIQ it is never | |
5863 | * possible for it to be taken immediately, because VIRQ and | |
5864 | * VFIQ are masked unless running at EL0 or EL1, and HCR | |
5865 | * can only be written at EL2. | |
5866 | */ | |
195801d7 | 5867 | g_assert(bql_locked()); |
89430fc6 PM |
5868 | arm_cpu_update_virq(cpu); |
5869 | arm_cpu_update_vfiq(cpu); | |
3c29632f | 5870 | arm_cpu_update_vserr(cpu); |
ce4afed8 PM |
5871 | } |
5872 | ||
d1fb4da2 RH |
5873 | static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
5874 | { | |
5875 | do_hcr_write(env, value, 0); | |
5876 | } | |
5877 | ||
ce4afed8 PM |
5878 | static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, |
5879 | uint64_t value) | |
5880 | { | |
5881 | /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */ | |
5882 | value = deposit64(env->cp15.hcr_el2, 32, 32, value); | |
d1fb4da2 | 5883 | do_hcr_write(env, value, MAKE_64BIT_MASK(0, 32)); |
ce4afed8 PM |
5884 | } |
5885 | ||
5886 | static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, | |
5887 | uint64_t value) | |
5888 | { | |
5889 | /* Handle HCR write, i.e. write to low half of HCR_EL2 */ | |
5890 | value = deposit64(env->cp15.hcr_el2, 0, 32, value); | |
d1fb4da2 | 5891 | do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32)); |
f149e3e8 EI |
5892 | } |
5893 | ||
f7778444 | 5894 | /* |
b74c0443 | 5895 | * Return the effective value of HCR_EL2, at the given security state. |
f7778444 RH |
5896 | * Bits that are not included here: |
5897 | * RW (read from SCR_EL3.RW as needed) | |
5898 | */ | |
2d12bb96 | 5899 | uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space) |
f7778444 RH |
5900 | { |
5901 | uint64_t ret = env->cp15.hcr_el2; | |
5902 | ||
2d12bb96 PM |
5903 | assert(space != ARMSS_Root); |
5904 | ||
4477020d | 5905 | if (!arm_is_el2_enabled_secstate(env, space)) { |
f7778444 RH |
5906 | /* |
5907 | * "This register has no effect if EL2 is not enabled in the | |
5908 | * current Security state". This is ARMv8.4-SecEL2 speak for | |
5909 | * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1). | |
5910 | * | |
5911 | * Prior to that, the language was "In an implementation that | |
5912 | * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves | |
5913 | * as if this field is 0 for all purposes other than a direct | |
5914 | * read or write access of HCR_EL2". With lots of enumeration | |
5915 | * on a per-field basis. In current QEMU, this is condition | |
5916 | * is arm_is_secure_below_el3. | |
5917 | * | |
5918 | * Since the v8.4 language applies to the entire register, and | |
5919 | * appears to be backward compatible, use that. | |
5920 | */ | |
4990e1d3 RH |
5921 | return 0; |
5922 | } | |
5923 | ||
5924 | /* | |
5925 | * For a cpu that supports both aarch64 and aarch32, we can set bits | |
5926 | * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32. | |
5927 | * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32. | |
5928 | */ | |
5929 | if (!arm_el_is_aa64(env, 2)) { | |
5930 | uint64_t aa32_valid; | |
5931 | ||
5932 | /* | |
5933 | * These bits are up-to-date as of ARMv8.6. | |
5934 | * For HCR, it's easiest to list just the 2 bits that are invalid. | |
5935 | * For HCR2, list those that are valid. | |
5936 | */ | |
5937 | aa32_valid = MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ); | |
5938 | aa32_valid |= (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNCE | | |
5939 | HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS); | |
5940 | ret &= aa32_valid; | |
5941 | } | |
5942 | ||
5943 | if (ret & HCR_TGE) { | |
5944 | /* These bits are up-to-date as of ARMv8.6. */ | |
f7778444 RH |
5945 | if (ret & HCR_E2H) { |
5946 | ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | | |
5947 | HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | | |
5948 | HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | | |
4990e1d3 RH |
5949 | HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE | |
5950 | HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT | | |
5951 | HCR_TTLBIS | HCR_TTLBOS | HCR_TID5); | |
f7778444 RH |
5952 | } else { |
5953 | ret |= HCR_FMO | HCR_IMO | HCR_AMO; | |
5954 | } | |
5955 | ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | | |
5956 | HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | | |
5957 | HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | | |
5958 | HCR_TLOR); | |
5959 | } | |
5960 | ||
5961 | return ret; | |
5962 | } | |
5963 | ||
b74c0443 RH |
5964 | uint64_t arm_hcr_el2_eff(CPUARMState *env) |
5965 | { | |
a0262ba6 RH |
5966 | if (arm_feature(env, ARM_FEATURE_M)) { |
5967 | return 0; | |
5968 | } | |
2d12bb96 | 5969 | return arm_hcr_el2_eff_secstate(env, arm_security_space_below_el3(env)); |
b74c0443 RH |
5970 | } |
5971 | ||
19668718 RH |
5972 | /* |
5973 | * Corresponds to ARM pseudocode function ELIsInHost(). | |
5974 | */ | |
5975 | bool el_is_in_host(CPUARMState *env, int el) | |
5976 | { | |
5977 | uint64_t mask; | |
5978 | ||
5979 | /* | |
5980 | * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff(). | |
5981 | * Perform the simplest bit tests first, and validate EL2 afterward. | |
5982 | */ | |
5983 | if (el & 1) { | |
5984 | return false; /* EL1 or EL3 */ | |
5985 | } | |
5986 | ||
5987 | /* | |
5988 | * Note that hcr_write() checks isar_feature_aa64_vh(), | |
5989 | * aka HaveVirtHostExt(), in allowing HCR_E2H to be set. | |
5990 | */ | |
5991 | mask = el ? HCR_E2H : HCR_E2H | HCR_TGE; | |
5992 | if ((env->cp15.hcr_el2 & mask) != mask) { | |
5993 | return false; | |
5994 | } | |
5995 | ||
5996 | /* TGE and/or E2H set: double check those bits are currently legal. */ | |
5997 | return arm_is_el2_enabled(env) && arm_el_is_aa64(env, 2); | |
5998 | } | |
5999 | ||
5814d587 RH |
6000 | static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri, |
6001 | uint64_t value) | |
6002 | { | |
6003 | uint64_t valid_mask = 0; | |
6004 | ||
dbc678f9 PM |
6005 | /* FEAT_MOPS adds MSCEn and MCE2 */ |
6006 | if (cpu_isar_feature(aa64_mops, env_archcpu(env))) { | |
6007 | valid_mask |= HCRX_MSCEN | HCRX_MCE2; | |
6008 | } | |
5814d587 RH |
6009 | |
6010 | /* Clear RES0 bits. */ | |
6011 | env->cp15.hcrx_el2 = value & valid_mask; | |
6012 | } | |
6013 | ||
6014 | static CPAccessResult access_hxen(CPUARMState *env, const ARMCPRegInfo *ri, | |
6015 | bool isread) | |
6016 | { | |
6017 | if (arm_current_el(env) < 3 | |
6018 | && arm_feature(env, ARM_FEATURE_EL3) | |
6019 | && !(env->cp15.scr_el3 & SCR_HXEN)) { | |
6020 | return CP_ACCESS_TRAP_EL3; | |
6021 | } | |
6022 | return CP_ACCESS_OK; | |
6023 | } | |
6024 | ||
6025 | static const ARMCPRegInfo hcrx_el2_reginfo = { | |
6026 | .name = "HCRX_EL2", .state = ARM_CP_STATE_AA64, | |
6027 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 2, | |
6028 | .access = PL2_RW, .writefn = hcrx_write, .accessfn = access_hxen, | |
6029 | .fieldoffset = offsetof(CPUARMState, cp15.hcrx_el2), | |
6030 | }; | |
6031 | ||
6032 | /* Return the effective value of HCRX_EL2. */ | |
6033 | uint64_t arm_hcrx_el2_eff(CPUARMState *env) | |
6034 | { | |
6035 | /* | |
6036 | * The bits in this register behave as 0 for all purposes other than | |
dbc678f9 PM |
6037 | * direct reads of the register if SCR_EL3.HXEn is 0. |
6038 | * If EL2 is not enabled in the current security state, then the | |
6039 | * bit may behave as if 0, or as if 1, depending on the bit. | |
6040 | * For the moment, we treat the EL2-disabled case as taking | |
6041 | * priority over the HXEn-disabled case. This is true for the only | |
6042 | * bit for a feature which we implement where the answer is different | |
6043 | * for the two cases (MSCEn for FEAT_MOPS). | |
6044 | * This may need to be revisited for future bits. | |
5814d587 | 6045 | */ |
dbc678f9 PM |
6046 | if (!arm_is_el2_enabled(env)) { |
6047 | uint64_t hcrx = 0; | |
6048 | if (cpu_isar_feature(aa64_mops, env_archcpu(env))) { | |
6049 | /* MSCEn behaves as 1 if EL2 is not enabled */ | |
6050 | hcrx |= HCRX_MSCEN; | |
6051 | } | |
6052 | return hcrx; | |
6053 | } | |
6054 | if (arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_HXEN)) { | |
5814d587 RH |
6055 | return 0; |
6056 | } | |
6057 | return env->cp15.hcrx_el2; | |
6058 | } | |
6059 | ||
fc1120a7 PM |
6060 | static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, |
6061 | uint64_t value) | |
6062 | { | |
6063 | /* | |
6064 | * For A-profile AArch32 EL3, if NSACR.CP10 | |
6065 | * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. | |
6066 | */ | |
6067 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
6068 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
fab8ad39 RH |
6069 | uint64_t mask = R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; |
6070 | value = (value & ~mask) | (env->cp15.cptr_el[2] & mask); | |
fc1120a7 PM |
6071 | } |
6072 | env->cp15.cptr_el[2] = value; | |
6073 | } | |
6074 | ||
6075 | static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
6076 | { | |
6077 | /* | |
6078 | * For A-profile AArch32 EL3, if NSACR.CP10 | |
6079 | * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. | |
6080 | */ | |
6081 | uint64_t value = env->cp15.cptr_el[2]; | |
6082 | ||
6083 | if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
6084 | !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { | |
fab8ad39 | 6085 | value |= R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; |
fc1120a7 PM |
6086 | } |
6087 | return value; | |
6088 | } | |
6089 | ||
4771cd01 | 6090 | static const ARMCPRegInfo el2_cp_reginfo[] = { |
f149e3e8 | 6091 | { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, |
89430fc6 | 6092 | .type = ARM_CP_IO, |
f149e3e8 EI |
6093 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
6094 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
587f8b33 | 6095 | .writefn = hcr_write, .raw_writefn = raw_write }, |
ce4afed8 | 6096 | { .name = "HCR", .state = ARM_CP_STATE_AA32, |
89430fc6 | 6097 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
6098 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, |
6099 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), | |
c624ea0f | 6100 | .writefn = hcr_writelow }, |
831a2fca PM |
6101 | { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH, |
6102 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7, | |
6103 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
3b685ba7 | 6104 | { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 6105 | .type = ARM_CP_ALIAS, |
3b685ba7 EI |
6106 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, |
6107 | .access = PL2_RW, | |
6108 | .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, | |
68e78e33 | 6109 | { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, |
f2c30f42 EI |
6110 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, |
6111 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, | |
cba517c3 | 6112 | { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, |
63b60551 EI |
6113 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, |
6114 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, | |
cba517c3 PM |
6115 | { .name = "HIFAR", .state = ARM_CP_STATE_AA32, |
6116 | .type = ARM_CP_ALIAS, | |
6117 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | |
6118 | .access = PL2_RW, | |
6119 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) }, | |
3b685ba7 | 6120 | { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 6121 | .type = ARM_CP_ALIAS, |
3b685ba7 | 6122 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
6123 | .access = PL2_RW, |
6124 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, | |
d79e0c06 | 6125 | { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, |
d42e3c26 EI |
6126 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, |
6127 | .access = PL2_RW, .writefn = vbar_write, | |
6128 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), | |
6129 | .resetvalue = 0 }, | |
884b4dee GB |
6130 | { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, |
6131 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, | |
7a0e58fa | 6132 | .access = PL3_RW, .type = ARM_CP_ALIAS, |
884b4dee | 6133 | .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, |
c6f19164 GB |
6134 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, |
6135 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | |
6136 | .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, | |
fc1120a7 PM |
6137 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]), |
6138 | .readfn = cptr_el2_read, .writefn = cptr_el2_write }, | |
95f949ac EI |
6139 | { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH, |
6140 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, | |
6141 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), | |
6142 | .resetvalue = 0 }, | |
6143 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | |
b5ede85b | 6144 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, |
95f949ac EI |
6145 | .access = PL2_RW, .type = ARM_CP_ALIAS, |
6146 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, | |
2179ef95 PM |
6147 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, |
6148 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | |
6149 | .access = PL2_RW, .type = ARM_CP_CONST, | |
6150 | .resetvalue = 0 }, | |
6151 | /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ | |
55b53c71 | 6152 | { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, |
b5ede85b | 6153 | .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, |
2179ef95 PM |
6154 | .access = PL2_RW, .type = ARM_CP_CONST, |
6155 | .resetvalue = 0 }, | |
37cd6c24 PM |
6156 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, |
6157 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0, | |
6158 | .access = PL2_RW, .type = ARM_CP_CONST, | |
6159 | .resetvalue = 0 }, | |
6160 | { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH, | |
6161 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1, | |
6162 | .access = PL2_RW, .type = ARM_CP_CONST, | |
6163 | .resetvalue = 0 }, | |
06ec4c8c EI |
6164 | { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, |
6165 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, | |
d06dc933 | 6166 | .access = PL2_RW, .writefn = vmsa_tcr_el12_write, |
587f8b33 | 6167 | .raw_writefn = raw_write, |
06ec4c8c | 6168 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, |
68e9c2fe EI |
6169 | { .name = "VTCR", .state = ARM_CP_STATE_AA32, |
6170 | .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 | 6171 | .type = ARM_CP_ALIAS, |
68e9c2fe | 6172 | .access = PL2_RW, .accessfn = access_el3_aa32ns, |
afbb181c | 6173 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vtcr_el2) }, |
68e9c2fe EI |
6174 | { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64, |
6175 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, | |
bf06c112 | 6176 | .access = PL2_RW, |
988cc190 | 6177 | /* no .writefn needed as this can't cause an ASID change */ |
68e9c2fe | 6178 | .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) }, |
b698e9cf EI |
6179 | { .name = "VTTBR", .state = ARM_CP_STATE_AA32, |
6180 | .cp = 15, .opc1 = 6, .crm = 2, | |
6181 | .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
6182 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
6183 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), | |
587f8b33 | 6184 | .writefn = vttbr_write, .raw_writefn = raw_write }, |
b698e9cf EI |
6185 | { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, |
6186 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, | |
587f8b33 | 6187 | .access = PL2_RW, .writefn = vttbr_write, .raw_writefn = raw_write, |
b698e9cf | 6188 | .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, |
b9cb5323 EI |
6189 | { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, |
6190 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, | |
6191 | .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, | |
6192 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, | |
ff05f37b EI |
6193 | { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH, |
6194 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2, | |
6195 | .access = PL2_RW, .resetvalue = 0, | |
6196 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, | |
a57633c0 EI |
6197 | { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, |
6198 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
587f8b33 EA |
6199 | .access = PL2_RW, .resetvalue = 0, |
6200 | .writefn = vmsa_tcr_ttbr_el2_write, .raw_writefn = raw_write, | |
a57633c0 EI |
6201 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
6202 | { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, | |
6203 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, | |
a57633c0 | 6204 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, |
541ef8c2 SS |
6205 | { .name = "TLBIALLNSNH", |
6206 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | |
6207 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
6208 | .writefn = tlbiall_nsnh_write }, | |
6209 | { .name = "TLBIALLNSNHIS", | |
6210 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | |
6211 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
6212 | .writefn = tlbiall_nsnh_is_write }, | |
6213 | { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
6214 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
6215 | .writefn = tlbiall_hyp_write }, | |
6216 | { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
6217 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
6218 | .writefn = tlbiall_hyp_is_write }, | |
6219 | { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
6220 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
6221 | .writefn = tlbimva_hyp_write }, | |
6222 | { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
6223 | .type = ARM_CP_NO_RAW, .access = PL2_W, | |
6224 | .writefn = tlbimva_hyp_is_write }, | |
51da9014 EI |
6225 | { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64, |
6226 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0, | |
696ba377 | 6227 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
fd3ed969 | 6228 | .writefn = tlbi_aa64_alle2_write }, |
8742d49d EI |
6229 | { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64, |
6230 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1, | |
696ba377 | 6231 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
fd3ed969 | 6232 | .writefn = tlbi_aa64_vae2_write }, |
2bfb9d75 PM |
6233 | { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64, |
6234 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5, | |
696ba377 | 6235 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
2bfb9d75 PM |
6236 | .writefn = tlbi_aa64_vae2_write }, |
6237 | { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64, | |
6238 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0, | |
696ba377 | 6239 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
2bfb9d75 | 6240 | .writefn = tlbi_aa64_alle2is_write }, |
8742d49d EI |
6241 | { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64, |
6242 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1, | |
696ba377 | 6243 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
fd3ed969 | 6244 | .writefn = tlbi_aa64_vae2is_write }, |
2bfb9d75 PM |
6245 | { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64, |
6246 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5, | |
696ba377 | 6247 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
2bfb9d75 | 6248 | .writefn = tlbi_aa64_vae2is_write }, |
edac4d8a | 6249 | #ifndef CONFIG_USER_ONLY |
9b37a28c FR |
6250 | /* |
6251 | * Unlike the other EL2-related AT operations, these must | |
2a47df95 PM |
6252 | * UNDEF from EL3 if EL2 is not implemented, which is why we |
6253 | * define them here rather than with the rest of the AT ops. | |
6254 | */ | |
6255 | { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64, | |
6256 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
6257 | .access = PL2_W, .accessfn = at_s1e2_access, | |
696ba377 RH |
6258 | .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, |
6259 | .writefn = ats_write64 }, | |
2a47df95 PM |
6260 | { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64, |
6261 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, | |
6262 | .access = PL2_W, .accessfn = at_s1e2_access, | |
696ba377 RH |
6263 | .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF, |
6264 | .writefn = ats_write64 }, | |
9b37a28c FR |
6265 | /* |
6266 | * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE | |
14db7fe0 PM |
6267 | * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 |
6268 | * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose | |
6269 | * to behave as if SCR.NS was 1. | |
6270 | */ | |
6271 | { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0, | |
6272 | .access = PL2_W, | |
0710b2fa | 6273 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
14db7fe0 PM |
6274 | { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1, |
6275 | .access = PL2_W, | |
0710b2fa | 6276 | .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, |
0b6440af EI |
6277 | { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH, |
6278 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, | |
9b37a28c FR |
6279 | /* |
6280 | * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the | |
0b6440af EI |
6281 | * reset values as IMPDEF. We choose to reset to 3 to comply with |
6282 | * both ARMv7 and ARMv8. | |
6283 | */ | |
f6fc36de JPB |
6284 | .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 3, |
6285 | .writefn = gt_cnthctl_write, .raw_writefn = raw_write, | |
0b6440af | 6286 | .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, |
edac4d8a EI |
6287 | { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, |
6288 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, | |
6289 | .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0, | |
6290 | .writefn = gt_cntvoff_write, | |
6291 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
6292 | { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14, | |
6293 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO, | |
6294 | .writefn = gt_cntvoff_write, | |
6295 | .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, | |
b0e66d95 EI |
6296 | { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64, |
6297 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2, | |
6298 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
6299 | .type = ARM_CP_IO, .access = PL2_RW, | |
6300 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
6301 | { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14, | |
6302 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), | |
6303 | .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO, | |
6304 | .writefn = gt_hyp_cval_write, .raw_writefn = raw_write }, | |
6305 | { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
6306 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0, | |
d44ec156 | 6307 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, |
b0e66d95 EI |
6308 | .resetfn = gt_hyp_timer_reset, |
6309 | .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write }, | |
6310 | { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
6311 | .type = ARM_CP_IO, | |
6312 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, | |
6313 | .access = PL2_RW, | |
6314 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), | |
6315 | .resetvalue = 0, | |
6316 | .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, | |
edac4d8a | 6317 | #endif |
59e05530 EI |
6318 | { .name = "HPFAR", .state = ARM_CP_STATE_AA32, |
6319 | .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
6320 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
6321 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
6322 | { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, | |
6323 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, | |
6324 | .access = PL2_RW, | |
6325 | .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, | |
2a5a9abd AF |
6326 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, |
6327 | .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | |
6328 | .access = PL2_RW, | |
6329 | .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) }, | |
3b685ba7 EI |
6330 | }; |
6331 | ||
ce4afed8 PM |
6332 | static const ARMCPRegInfo el2_v8_cp_reginfo[] = { |
6333 | { .name = "HCR2", .state = ARM_CP_STATE_AA32, | |
89430fc6 | 6334 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
ce4afed8 PM |
6335 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, |
6336 | .access = PL2_RW, | |
6337 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2), | |
6338 | .writefn = hcr_writehigh }, | |
ce4afed8 PM |
6339 | }; |
6340 | ||
e9152ee9 RDC |
6341 | static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, |
6342 | bool isread) | |
6343 | { | |
6344 | if (arm_current_el(env) == 3 || arm_is_secure_below_el3(env)) { | |
6345 | return CP_ACCESS_OK; | |
6346 | } | |
6347 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
6348 | } | |
6349 | ||
6350 | static const ARMCPRegInfo el2_sec_cp_reginfo[] = { | |
6351 | { .name = "VSTTBR_EL2", .state = ARM_CP_STATE_AA64, | |
6352 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 0, | |
6353 | .access = PL2_RW, .accessfn = sel2_access, | |
6354 | .fieldoffset = offsetof(CPUARMState, cp15.vsttbr_el2) }, | |
6355 | { .name = "VSTCR_EL2", .state = ARM_CP_STATE_AA64, | |
6356 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 6, .opc2 = 2, | |
6357 | .access = PL2_RW, .accessfn = sel2_access, | |
6358 | .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) }, | |
e9152ee9 RDC |
6359 | }; |
6360 | ||
2f027fc5 PM |
6361 | static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri, |
6362 | bool isread) | |
6363 | { | |
9b37a28c FR |
6364 | /* |
6365 | * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. | |
926c1b97 | 6366 | * At Secure EL1 it traps to EL3 or EL2. |
2f027fc5 PM |
6367 | */ |
6368 | if (arm_current_el(env) == 3) { | |
6369 | return CP_ACCESS_OK; | |
6370 | } | |
6371 | if (arm_is_secure_below_el3(env)) { | |
926c1b97 RDC |
6372 | if (env->cp15.scr_el3 & SCR_EEL2) { |
6373 | return CP_ACCESS_TRAP_EL2; | |
6374 | } | |
2f027fc5 PM |
6375 | return CP_ACCESS_TRAP_EL3; |
6376 | } | |
6377 | /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */ | |
6378 | if (isread) { | |
6379 | return CP_ACCESS_OK; | |
6380 | } | |
6381 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
6382 | } | |
6383 | ||
60fb1a87 GB |
6384 | static const ARMCPRegInfo el3_cp_reginfo[] = { |
6385 | { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, | |
6386 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, | |
6387 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), | |
587f8b33 | 6388 | .resetfn = scr_reset, .writefn = scr_write, .raw_writefn = raw_write }, |
f80741d1 | 6389 | { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL, |
60fb1a87 | 6390 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, |
efe4a274 PM |
6391 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
6392 | .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), | |
587f8b33 | 6393 | .writefn = scr_write, .raw_writefn = raw_write }, |
60fb1a87 GB |
6394 | { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, |
6395 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, | |
6396 | .access = PL3_RW, .resetvalue = 0, | |
6397 | .fieldoffset = offsetof(CPUARMState, cp15.sder) }, | |
6398 | { .name = "SDER", | |
6399 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, | |
6400 | .access = PL3_RW, .resetvalue = 0, | |
6401 | .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, | |
60fb1a87 | 6402 | { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, |
efe4a274 PM |
6403 | .access = PL1_RW, .accessfn = access_trap_aa32s_el1, |
6404 | .writefn = vbar_write, .resetvalue = 0, | |
60fb1a87 | 6405 | .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, |
7dd8c9af FA |
6406 | { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, |
6407 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, | |
f478847f | 6408 | .access = PL3_RW, .resetvalue = 0, |
7dd8c9af | 6409 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) }, |
11f136ee FA |
6410 | { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64, |
6411 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2, | |
6459b94c | 6412 | .access = PL3_RW, |
cb4a0a34 PM |
6413 | /* no .writefn needed as this can't cause an ASID change */ |
6414 | .resetvalue = 0, | |
11f136ee | 6415 | .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) }, |
81547d66 | 6416 | { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 6417 | .type = ARM_CP_ALIAS, |
81547d66 EI |
6418 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, |
6419 | .access = PL3_RW, | |
6420 | .fieldoffset = offsetof(CPUARMState, elr_el[3]) }, | |
f2c30f42 | 6421 | { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64, |
f2c30f42 EI |
6422 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0, |
6423 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) }, | |
63b60551 EI |
6424 | { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64, |
6425 | .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0, | |
6426 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) }, | |
81547d66 | 6427 | { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, |
7a0e58fa | 6428 | .type = ARM_CP_ALIAS, |
81547d66 | 6429 | .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, |
99a99c1f SB |
6430 | .access = PL3_RW, |
6431 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) }, | |
a1ba125c EI |
6432 | { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64, |
6433 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0, | |
6434 | .access = PL3_RW, .writefn = vbar_write, | |
6435 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), | |
6436 | .resetvalue = 0 }, | |
c6f19164 GB |
6437 | { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, |
6438 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, | |
6439 | .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, | |
6440 | .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, | |
4cfb8ad8 PM |
6441 | { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64, |
6442 | .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2, | |
6443 | .access = PL3_RW, .resetvalue = 0, | |
6444 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) }, | |
2179ef95 PM |
6445 | { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64, |
6446 | .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0, | |
6447 | .access = PL3_RW, .type = ARM_CP_CONST, | |
6448 | .resetvalue = 0 }, | |
37cd6c24 PM |
6449 | { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH, |
6450 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0, | |
6451 | .access = PL3_RW, .type = ARM_CP_CONST, | |
6452 | .resetvalue = 0 }, | |
6453 | { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH, | |
6454 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1, | |
6455 | .access = PL3_RW, .type = ARM_CP_CONST, | |
6456 | .resetvalue = 0 }, | |
43efaa33 PM |
6457 | { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64, |
6458 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0, | |
6459 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6460 | .writefn = tlbi_aa64_alle3is_write }, | |
6461 | { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64, | |
6462 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1, | |
6463 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6464 | .writefn = tlbi_aa64_vae3is_write }, | |
6465 | { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64, | |
6466 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5, | |
6467 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6468 | .writefn = tlbi_aa64_vae3is_write }, | |
6469 | { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64, | |
6470 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0, | |
6471 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6472 | .writefn = tlbi_aa64_alle3_write }, | |
6473 | { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64, | |
6474 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1, | |
6475 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6476 | .writefn = tlbi_aa64_vae3_write }, | |
6477 | { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64, | |
6478 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5, | |
6479 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
6480 | .writefn = tlbi_aa64_vae3_write }, | |
0f1a3b24 FA |
6481 | }; |
6482 | ||
e2cce18f RH |
6483 | #ifndef CONFIG_USER_ONLY |
6484 | /* Test if system register redirection is to occur in the current state. */ | |
6485 | static bool redirect_for_e2h(CPUARMState *env) | |
6486 | { | |
6487 | return arm_current_el(env) == 2 && (arm_hcr_el2_eff(env) & HCR_E2H); | |
6488 | } | |
6489 | ||
6490 | static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
6491 | { | |
6492 | CPReadFn *readfn; | |
6493 | ||
6494 | if (redirect_for_e2h(env)) { | |
6495 | /* Switch to the saved EL2 version of the register. */ | |
6496 | ri = ri->opaque; | |
6497 | readfn = ri->readfn; | |
6498 | } else { | |
6499 | readfn = ri->orig_readfn; | |
6500 | } | |
6501 | if (readfn == NULL) { | |
6502 | readfn = raw_read; | |
6503 | } | |
6504 | return readfn(env, ri); | |
6505 | } | |
6506 | ||
6507 | static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6508 | uint64_t value) | |
6509 | { | |
6510 | CPWriteFn *writefn; | |
6511 | ||
6512 | if (redirect_for_e2h(env)) { | |
6513 | /* Switch to the saved EL2 version of the register. */ | |
6514 | ri = ri->opaque; | |
6515 | writefn = ri->writefn; | |
6516 | } else { | |
6517 | writefn = ri->orig_writefn; | |
6518 | } | |
6519 | if (writefn == NULL) { | |
6520 | writefn = raw_write; | |
6521 | } | |
6522 | writefn(env, ri, value); | |
6523 | } | |
6524 | ||
6f53b126 PM |
6525 | static uint64_t el2_e2h_e12_read(CPUARMState *env, const ARMCPRegInfo *ri) |
6526 | { | |
6527 | /* Pass the EL1 register accessor its ri, not the EL12 alias ri */ | |
6528 | return ri->orig_readfn(env, ri->opaque); | |
6529 | } | |
6530 | ||
6531 | static void el2_e2h_e12_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
6532 | uint64_t value) | |
6533 | { | |
6534 | /* Pass the EL1 register accessor its ri, not the EL12 alias ri */ | |
6535 | return ri->orig_writefn(env, ri->opaque, value); | |
6536 | } | |
6537 | ||
e730287c PM |
6538 | static CPAccessResult el2_e2h_e12_access(CPUARMState *env, |
6539 | const ARMCPRegInfo *ri, | |
6540 | bool isread) | |
6541 | { | |
6542 | /* FOO_EL12 aliases only exist when E2H is 1; otherwise they UNDEF */ | |
6543 | if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { | |
6544 | return CP_ACCESS_TRAP_UNCATEGORIZED; | |
6545 | } | |
6546 | if (ri->orig_accessfn) { | |
6547 | return ri->orig_accessfn(env, ri->opaque, isread); | |
6548 | } | |
6549 | return CP_ACCESS_OK; | |
6550 | } | |
6551 | ||
e2cce18f RH |
6552 | static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) |
6553 | { | |
6554 | struct E2HAlias { | |
6555 | uint32_t src_key, dst_key, new_key; | |
6556 | const char *src_name, *dst_name, *new_name; | |
6557 | bool (*feature)(const ARMISARegisters *id); | |
6558 | }; | |
6559 | ||
6560 | #define K(op0, op1, crn, crm, op2) \ | |
6561 | ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) | |
6562 | ||
6563 | static const struct E2HAlias aliases[] = { | |
6564 | { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), | |
6565 | "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, | |
6566 | { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), | |
6567 | "CPACR", "CPTR_EL2", "CPACR_EL12" }, | |
6568 | { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), | |
6569 | "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, | |
6570 | { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), | |
6571 | "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, | |
6572 | { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), | |
6573 | "TCR_EL1", "TCR_EL2", "TCR_EL12" }, | |
6574 | { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), | |
6575 | "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, | |
6576 | { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), | |
6577 | "ELR_EL1", "ELR_EL2", "ELR_EL12" }, | |
6578 | { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0), | |
6579 | "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" }, | |
6580 | { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1), | |
6581 | "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" }, | |
6582 | { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0), | |
6583 | "ESR_EL1", "ESR_EL2", "ESR_EL12" }, | |
6584 | { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0), | |
6585 | "FAR_EL1", "FAR_EL2", "FAR_EL12" }, | |
6586 | { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), | |
6587 | "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, | |
6588 | { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), | |
6589 | "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" }, | |
6590 | { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), | |
6591 | "VBAR", "VBAR_EL2", "VBAR_EL12" }, | |
6592 | { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), | |
6593 | "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, | |
6594 | { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), | |
6595 | "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" }, | |
6596 | ||
6597 | /* | |
6598 | * Note that redirection of ZCR is mentioned in the description | |
6599 | * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but | |
6600 | * not in the summary table. | |
6601 | */ | |
6602 | { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), | |
6603 | "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, | |
de561988 RH |
6604 | { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6), |
6605 | "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme }, | |
e2cce18f | 6606 | |
4b779ceb RH |
6607 | { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), |
6608 | "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, | |
6609 | ||
7cb1e618 RH |
6610 | { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), |
6611 | "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", | |
6612 | isar_feature_aa64_scxtnum }, | |
6613 | ||
e2cce18f RH |
6614 | /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ |
6615 | /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ | |
6616 | }; | |
6617 | #undef K | |
6618 | ||
6619 | size_t i; | |
6620 | ||
6621 | for (i = 0; i < ARRAY_SIZE(aliases); i++) { | |
6622 | const struct E2HAlias *a = &aliases[i]; | |
9da35a40 | 6623 | ARMCPRegInfo *src_reg, *dst_reg, *new_reg; |
9da35a40 | 6624 | bool ok; |
e2cce18f RH |
6625 | |
6626 | if (a->feature && !a->feature(&cpu->isar)) { | |
6627 | continue; | |
6628 | } | |
6629 | ||
5860362d RH |
6630 | src_reg = g_hash_table_lookup(cpu->cp_regs, |
6631 | (gpointer)(uintptr_t)a->src_key); | |
6632 | dst_reg = g_hash_table_lookup(cpu->cp_regs, | |
6633 | (gpointer)(uintptr_t)a->dst_key); | |
e2cce18f RH |
6634 | g_assert(src_reg != NULL); |
6635 | g_assert(dst_reg != NULL); | |
6636 | ||
6637 | /* Cross-compare names to detect typos in the keys. */ | |
6638 | g_assert(strcmp(src_reg->name, a->src_name) == 0); | |
6639 | g_assert(strcmp(dst_reg->name, a->dst_name) == 0); | |
6640 | ||
6641 | /* None of the core system registers use opaque; we will. */ | |
6642 | g_assert(src_reg->opaque == NULL); | |
6643 | ||
6644 | /* Create alias before redirection so we dup the right data. */ | |
9da35a40 | 6645 | new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo)); |
9da35a40 RH |
6646 | |
6647 | new_reg->name = a->new_name; | |
6648 | new_reg->type |= ARM_CP_ALIAS; | |
6649 | /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ | |
6650 | new_reg->access &= PL2_RW | PL3_RW; | |
6f53b126 PM |
6651 | /* The new_reg op fields are as per new_key, not the target reg */ |
6652 | new_reg->crn = (a->new_key & CP_REG_ARM64_SYSREG_CRN_MASK) | |
6653 | >> CP_REG_ARM64_SYSREG_CRN_SHIFT; | |
6654 | new_reg->crm = (a->new_key & CP_REG_ARM64_SYSREG_CRM_MASK) | |
6655 | >> CP_REG_ARM64_SYSREG_CRM_SHIFT; | |
6656 | new_reg->opc0 = (a->new_key & CP_REG_ARM64_SYSREG_OP0_MASK) | |
6657 | >> CP_REG_ARM64_SYSREG_OP0_SHIFT; | |
6658 | new_reg->opc1 = (a->new_key & CP_REG_ARM64_SYSREG_OP1_MASK) | |
6659 | >> CP_REG_ARM64_SYSREG_OP1_SHIFT; | |
6660 | new_reg->opc2 = (a->new_key & CP_REG_ARM64_SYSREG_OP2_MASK) | |
6661 | >> CP_REG_ARM64_SYSREG_OP2_SHIFT; | |
6662 | new_reg->opaque = src_reg; | |
6663 | new_reg->orig_readfn = src_reg->readfn ?: raw_read; | |
6664 | new_reg->orig_writefn = src_reg->writefn ?: raw_write; | |
e730287c | 6665 | new_reg->orig_accessfn = src_reg->accessfn; |
6f53b126 PM |
6666 | if (!new_reg->raw_readfn) { |
6667 | new_reg->raw_readfn = raw_read; | |
6668 | } | |
6669 | if (!new_reg->raw_writefn) { | |
6670 | new_reg->raw_writefn = raw_write; | |
6671 | } | |
6672 | new_reg->readfn = el2_e2h_e12_read; | |
6673 | new_reg->writefn = el2_e2h_e12_write; | |
e730287c | 6674 | new_reg->accessfn = el2_e2h_e12_access; |
9da35a40 | 6675 | |
5860362d RH |
6676 | ok = g_hash_table_insert(cpu->cp_regs, |
6677 | (gpointer)(uintptr_t)a->new_key, new_reg); | |
9da35a40 | 6678 | g_assert(ok); |
e2cce18f RH |
6679 | |
6680 | src_reg->opaque = dst_reg; | |
6681 | src_reg->orig_readfn = src_reg->readfn ?: raw_read; | |
6682 | src_reg->orig_writefn = src_reg->writefn ?: raw_write; | |
6683 | if (!src_reg->raw_readfn) { | |
6684 | src_reg->raw_readfn = raw_read; | |
6685 | } | |
6686 | if (!src_reg->raw_writefn) { | |
6687 | src_reg->raw_writefn = raw_write; | |
6688 | } | |
6689 | src_reg->readfn = el2_e2h_read; | |
6690 | src_reg->writefn = el2_e2h_write; | |
6691 | } | |
6692 | } | |
6693 | #endif | |
6694 | ||
3f208fd7 PM |
6695 | static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
6696 | bool isread) | |
7da845b0 | 6697 | { |
97475a89 RH |
6698 | int cur_el = arm_current_el(env); |
6699 | ||
6700 | if (cur_el < 2) { | |
6701 | uint64_t hcr = arm_hcr_el2_eff(env); | |
6702 | ||
6703 | if (cur_el == 0) { | |
6704 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
6705 | if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) { | |
6706 | return CP_ACCESS_TRAP_EL2; | |
6707 | } | |
6708 | } else { | |
6709 | if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) { | |
6710 | return CP_ACCESS_TRAP; | |
6711 | } | |
6712 | if (hcr & HCR_TID2) { | |
6713 | return CP_ACCESS_TRAP_EL2; | |
6714 | } | |
6715 | } | |
6716 | } else if (hcr & HCR_TID2) { | |
6717 | return CP_ACCESS_TRAP_EL2; | |
6718 | } | |
7da845b0 | 6719 | } |
630fcd4d MZ |
6720 | |
6721 | if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) { | |
6722 | return CP_ACCESS_TRAP_EL2; | |
6723 | } | |
6724 | ||
7da845b0 PM |
6725 | return CP_ACCESS_OK; |
6726 | } | |
6727 | ||
58e93b48 RH |
6728 | /* |
6729 | * Check for traps to RAS registers, which are controlled | |
6730 | * by HCR_EL2.TERR and SCR_EL3.TERR. | |
6731 | */ | |
6732 | static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri, | |
6733 | bool isread) | |
6734 | { | |
6735 | int el = arm_current_el(env); | |
6736 | ||
6737 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) { | |
6738 | return CP_ACCESS_TRAP_EL2; | |
6739 | } | |
6740 | if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) { | |
6741 | return CP_ACCESS_TRAP_EL3; | |
6742 | } | |
6743 | return CP_ACCESS_OK; | |
6744 | } | |
6745 | ||
6746 | static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
6747 | { | |
6748 | int el = arm_current_el(env); | |
6749 | ||
6750 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { | |
6751 | return env->cp15.vdisr_el2; | |
6752 | } | |
6753 | if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { | |
6754 | return 0; /* RAZ/WI */ | |
6755 | } | |
6756 | return env->cp15.disr_el1; | |
6757 | } | |
6758 | ||
6759 | static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
6760 | { | |
6761 | int el = arm_current_el(env); | |
6762 | ||
6763 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { | |
6764 | env->cp15.vdisr_el2 = val; | |
6765 | return; | |
6766 | } | |
6767 | if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { | |
6768 | return; /* RAZ/WI */ | |
6769 | } | |
6770 | env->cp15.disr_el1 = val; | |
6771 | } | |
6772 | ||
6773 | /* | |
6774 | * Minimal RAS implementation with no Error Records. | |
6775 | * Which means that all of the Error Record registers: | |
6776 | * ERXADDR_EL1 | |
6777 | * ERXCTLR_EL1 | |
6778 | * ERXFR_EL1 | |
6779 | * ERXMISC0_EL1 | |
6780 | * ERXMISC1_EL1 | |
6781 | * ERXMISC2_EL1 | |
6782 | * ERXMISC3_EL1 | |
6783 | * ERXPFGCDN_EL1 (RASv1p1) | |
6784 | * ERXPFGCTL_EL1 (RASv1p1) | |
6785 | * ERXPFGF_EL1 (RASv1p1) | |
6786 | * ERXSTATUS_EL1 | |
6787 | * and | |
6788 | * ERRSELR_EL1 | |
6789 | * may generate UNDEFINED, which is the effect we get by not | |
6790 | * listing them at all. | |
bd8db7d9 PM |
6791 | * |
6792 | * These registers have fine-grained trap bits, but UNDEF-to-EL1 | |
6793 | * is higher priority than FGT-to-EL2 so we do not need to list them | |
6794 | * in order to check for an FGT. | |
58e93b48 RH |
6795 | */ |
6796 | static const ARMCPRegInfo minimal_ras_reginfo[] = { | |
6797 | { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH, | |
6798 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1, | |
6799 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1), | |
6800 | .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write }, | |
6801 | { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
6802 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0, | |
6803 | .access = PL1_R, .accessfn = access_terr, | |
bd8db7d9 | 6804 | .fgt = FGT_ERRIDR_EL1, |
58e93b48 RH |
6805 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
6806 | { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH, | |
6807 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1, | |
6808 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) }, | |
6809 | { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH, | |
6810 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3, | |
6811 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) }, | |
6812 | }; | |
6813 | ||
397d922c RH |
6814 | /* |
6815 | * Return the exception level to which exceptions should be taken | |
6816 | * via SVEAccessTrap. This excludes the check for whether the exception | |
6817 | * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily | |
6818 | * be found by testing 0 < fp_exception_el < sve_exception_el. | |
6819 | * | |
6820 | * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the | |
6821 | * pseudocode does *not* separate out the FP trap checks, but has them | |
6822 | * all in one function. | |
5be5e8ed | 6823 | */ |
ced31551 | 6824 | int sve_exception_el(CPUARMState *env, int el) |
5be5e8ed RH |
6825 | { |
6826 | #ifndef CONFIG_USER_ONLY | |
aa4451b6 | 6827 | if (el <= 1 && !el_is_in_host(env, el)) { |
fab8ad39 | 6828 | switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, ZEN)) { |
7701cee5 RH |
6829 | case 1: |
6830 | if (el != 0) { | |
6831 | break; | |
6832 | } | |
6833 | /* fall through */ | |
6834 | case 0: | |
6835 | case 2: | |
61a8c23a | 6836 | return 1; |
5be5e8ed | 6837 | } |
5be5e8ed RH |
6838 | } |
6839 | ||
7d38cb92 RH |
6840 | if (el <= 2 && arm_is_el2_enabled(env)) { |
6841 | /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */ | |
6842 | if (env->cp15.hcr_el2 & HCR_E2H) { | |
fab8ad39 | 6843 | switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, ZEN)) { |
d5a6fa2d | 6844 | case 1: |
7d38cb92 | 6845 | if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) { |
d5a6fa2d RH |
6846 | break; |
6847 | } | |
6848 | /* fall through */ | |
6849 | case 0: | |
6850 | case 2: | |
6851 | return 2; | |
6852 | } | |
7d38cb92 | 6853 | } else { |
fab8ad39 | 6854 | if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) { |
d5a6fa2d RH |
6855 | return 2; |
6856 | } | |
60eed086 | 6857 | } |
5be5e8ed RH |
6858 | } |
6859 | ||
60eed086 RH |
6860 | /* CPTR_EL3. Since EZ is negative we must check for EL3. */ |
6861 | if (arm_feature(env, ARM_FEATURE_EL3) | |
fab8ad39 | 6862 | && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, EZ)) { |
5be5e8ed RH |
6863 | return 3; |
6864 | } | |
6865 | #endif | |
6866 | return 0; | |
6867 | } | |
6868 | ||
6b2ca83e RH |
6869 | /* |
6870 | * Return the exception level to which exceptions should be taken for SME. | |
6871 | * C.f. the ARM pseudocode function CheckSMEAccess. | |
6872 | */ | |
6873 | int sme_exception_el(CPUARMState *env, int el) | |
6874 | { | |
6875 | #ifndef CONFIG_USER_ONLY | |
6876 | if (el <= 1 && !el_is_in_host(env, el)) { | |
6877 | switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, SMEN)) { | |
6878 | case 1: | |
6879 | if (el != 0) { | |
6880 | break; | |
6881 | } | |
6882 | /* fall through */ | |
6883 | case 0: | |
6884 | case 2: | |
6885 | return 1; | |
6886 | } | |
6887 | } | |
6888 | ||
6889 | if (el <= 2 && arm_is_el2_enabled(env)) { | |
6890 | /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */ | |
6891 | if (env->cp15.hcr_el2 & HCR_E2H) { | |
6892 | switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, SMEN)) { | |
6893 | case 1: | |
6894 | if (el != 0 || !(env->cp15.hcr_el2 & HCR_TGE)) { | |
6895 | break; | |
6896 | } | |
6897 | /* fall through */ | |
6898 | case 0: | |
6899 | case 2: | |
6900 | return 2; | |
6901 | } | |
6902 | } else { | |
6903 | if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TSM)) { | |
6904 | return 2; | |
6905 | } | |
6906 | } | |
6907 | } | |
6908 | ||
6909 | /* CPTR_EL3. Since ESM is negative we must check for EL3. */ | |
6910 | if (arm_feature(env, ARM_FEATURE_EL3) | |
6911 | && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { | |
6912 | return 3; | |
6913 | } | |
6914 | #endif | |
6915 | return 0; | |
6916 | } | |
6917 | ||
0ab5953b RH |
6918 | /* |
6919 | * Given that SVE is enabled, return the vector length for EL. | |
6920 | */ | |
6ca54aa9 | 6921 | uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm) |
0ab5953b | 6922 | { |
2fc0cc0e | 6923 | ARMCPU *cpu = env_archcpu(env); |
6ca54aa9 RH |
6924 | uint64_t *cr = env->vfp.zcr_el; |
6925 | uint32_t map = cpu->sve_vq.map; | |
6926 | uint32_t len = ARM_MAX_VQ - 1; | |
6927 | ||
6928 | if (sm) { | |
6929 | cr = env->vfp.smcr_el; | |
6930 | map = cpu->sme_vq.map; | |
6931 | } | |
0ab5953b | 6932 | |
c6225beb | 6933 | if (el <= 1 && !el_is_in_host(env, el)) { |
6ca54aa9 | 6934 | len = MIN(len, 0xf & (uint32_t)cr[1]); |
0ab5953b | 6935 | } |
6a02a732 | 6936 | if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) { |
6ca54aa9 | 6937 | len = MIN(len, 0xf & (uint32_t)cr[2]); |
0ab5953b | 6938 | } |
6a02a732 | 6939 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
6ca54aa9 RH |
6940 | len = MIN(len, 0xf & (uint32_t)cr[3]); |
6941 | } | |
6942 | ||
6943 | map &= MAKE_64BIT_MASK(0, len + 1); | |
6944 | if (map != 0) { | |
6945 | return 31 - clz32(map); | |
0ab5953b | 6946 | } |
0df9142d | 6947 | |
6ca54aa9 RH |
6948 | /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */ |
6949 | assert(sm); | |
6950 | return ctz32(cpu->sme_vq.map); | |
6951 | } | |
6952 | ||
6953 | uint32_t sve_vqm1_for_el(CPUARMState *env, int el) | |
6954 | { | |
6955 | return sve_vqm1_for_el_sm(env, el, FIELD_EX64(env->svcr, SVCR, SM)); | |
0ab5953b RH |
6956 | } |
6957 | ||
5be5e8ed RH |
6958 | static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
6959 | uint64_t value) | |
6960 | { | |
0ab5953b | 6961 | int cur_el = arm_current_el(env); |
5ef3cc56 | 6962 | int old_len = sve_vqm1_for_el(env, cur_el); |
0ab5953b RH |
6963 | int new_len; |
6964 | ||
5be5e8ed | 6965 | /* Bits other than [3:0] are RAZ/WI. */ |
7b351d98 | 6966 | QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16); |
5be5e8ed | 6967 | raw_write(env, ri, value & 0xf); |
0ab5953b RH |
6968 | |
6969 | /* | |
6970 | * Because we arrived here, we know both FP and SVE are enabled; | |
6971 | * otherwise we would have trapped access to the ZCR_ELn register. | |
6972 | */ | |
5ef3cc56 | 6973 | new_len = sve_vqm1_for_el(env, cur_el); |
0ab5953b RH |
6974 | if (new_len < old_len) { |
6975 | aarch64_sve_narrow_vq(env, new_len + 1); | |
6976 | } | |
5be5e8ed RH |
6977 | } |
6978 | ||
60360d82 RH |
6979 | static const ARMCPRegInfo zcr_reginfo[] = { |
6980 | { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64, | |
6981 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0, | |
6982 | .access = PL1_RW, .type = ARM_CP_SVE, | |
6983 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]), | |
6984 | .writefn = zcr_write, .raw_writefn = raw_write }, | |
6985 | { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64, | |
6986 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0, | |
6987 | .access = PL2_RW, .type = ARM_CP_SVE, | |
6988 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]), | |
6989 | .writefn = zcr_write, .raw_writefn = raw_write }, | |
6990 | { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64, | |
6991 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0, | |
6992 | .access = PL3_RW, .type = ARM_CP_SVE, | |
6993 | .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]), | |
6994 | .writefn = zcr_write, .raw_writefn = raw_write }, | |
5be5e8ed RH |
6995 | }; |
6996 | ||
9e5ec745 RH |
6997 | #ifdef TARGET_AARCH64 |
6998 | static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri, | |
6999 | bool isread) | |
7000 | { | |
7001 | int el = arm_current_el(env); | |
7002 | ||
7003 | if (el == 0) { | |
7004 | uint64_t sctlr = arm_sctlr(env, el); | |
7005 | if (!(sctlr & SCTLR_EnTP2)) { | |
7006 | return CP_ACCESS_TRAP; | |
7007 | } | |
7008 | } | |
7009 | /* TODO: FEAT_FGT */ | |
7010 | if (el < 3 | |
7011 | && arm_feature(env, ARM_FEATURE_EL3) | |
7012 | && !(env->cp15.scr_el3 & SCR_ENTP2)) { | |
7013 | return CP_ACCESS_TRAP_EL3; | |
7014 | } | |
7015 | return CP_ACCESS_OK; | |
7016 | } | |
7017 | ||
d5b1223a RH |
7018 | static CPAccessResult access_esm(CPUARMState *env, const ARMCPRegInfo *ri, |
7019 | bool isread) | |
7020 | { | |
7021 | /* TODO: FEAT_FGT for SMPRI_EL1 but not SMPRIMAP_EL2 */ | |
7022 | if (arm_current_el(env) < 3 | |
7023 | && arm_feature(env, ARM_FEATURE_EL3) | |
7024 | && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, ESM)) { | |
7025 | return CP_ACCESS_TRAP_EL3; | |
7026 | } | |
7027 | return CP_ACCESS_OK; | |
7028 | } | |
7029 | ||
7f2a01e7 RH |
7030 | /* ResetSVEState */ |
7031 | static void arm_reset_sve_state(CPUARMState *env) | |
7032 | { | |
7033 | memset(env->vfp.zregs, 0, sizeof(env->vfp.zregs)); | |
7034 | /* Recall that FFR is stored as pregs[16]. */ | |
7035 | memset(env->vfp.pregs, 0, sizeof(env->vfp.pregs)); | |
7036 | vfp_set_fpcr(env, 0x0800009f); | |
7037 | } | |
7038 | ||
2a8af382 RH |
7039 | void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask) |
7040 | { | |
7041 | uint64_t change = (env->svcr ^ new) & mask; | |
7042 | ||
f4318557 RH |
7043 | if (change == 0) { |
7044 | return; | |
7045 | } | |
2a8af382 | 7046 | env->svcr ^= change; |
7f2a01e7 RH |
7047 | |
7048 | if (change & R_SVCR_SM_MASK) { | |
7049 | arm_reset_sve_state(env); | |
7050 | } | |
fccb4918 RH |
7051 | |
7052 | /* | |
7053 | * ResetSMEState. | |
7054 | * | |
7055 | * SetPSTATE_ZA zeros on enable and disable. We can zero this only | |
7056 | * on enable: while disabled, the storage is inaccessible and the | |
7057 | * value does not matter. We're not saving the storage in vmstate | |
7058 | * when disabled either. | |
7059 | */ | |
7060 | if (change & new & R_SVCR_ZA_MASK) { | |
7061 | memset(env->zarray, 0, sizeof(env->zarray)); | |
7062 | } | |
f4318557 | 7063 | |
2b77ad4d FR |
7064 | if (tcg_enabled()) { |
7065 | arm_rebuild_hflags(env); | |
7066 | } | |
2a8af382 RH |
7067 | } |
7068 | ||
c37e6ac9 RH |
7069 | static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
7070 | uint64_t value) | |
7071 | { | |
2a8af382 | 7072 | aarch64_set_svcr(env, value, -1); |
c37e6ac9 RH |
7073 | } |
7074 | ||
de561988 RH |
7075 | static void smcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
7076 | uint64_t value) | |
7077 | { | |
7078 | int cur_el = arm_current_el(env); | |
7079 | int old_len = sve_vqm1_for_el(env, cur_el); | |
7080 | int new_len; | |
7081 | ||
7082 | QEMU_BUILD_BUG_ON(ARM_MAX_VQ > R_SMCR_LEN_MASK + 1); | |
7083 | value &= R_SMCR_LEN_MASK | R_SMCR_FA64_MASK; | |
7084 | raw_write(env, ri, value); | |
7085 | ||
7086 | /* | |
7087 | * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage | |
7088 | * when SVL is widened (old values kept, or zeros). Choose to keep the | |
7089 | * current values for simplicity. But for QEMU internals, we must still | |
7090 | * apply the narrower SVL to the Zregs and Pregs -- see the comment | |
7091 | * above aarch64_sve_narrow_vq. | |
7092 | */ | |
7093 | new_len = sve_vqm1_for_el(env, cur_el); | |
7094 | if (new_len < old_len) { | |
7095 | aarch64_sve_narrow_vq(env, new_len + 1); | |
7096 | } | |
7097 | } | |
7098 | ||
9e5ec745 RH |
7099 | static const ARMCPRegInfo sme_reginfo[] = { |
7100 | { .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64, | |
7101 | .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5, | |
7102 | .access = PL0_RW, .accessfn = access_tpidr2, | |
bd8db7d9 | 7103 | .fgt = FGT_NTPIDR2_EL0, |
9e5ec745 | 7104 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) }, |
c37e6ac9 RH |
7105 | { .name = "SVCR", .state = ARM_CP_STATE_AA64, |
7106 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 2, | |
7107 | .access = PL0_RW, .type = ARM_CP_SME, | |
7108 | .fieldoffset = offsetof(CPUARMState, svcr), | |
7109 | .writefn = svcr_write, .raw_writefn = raw_write }, | |
de561988 RH |
7110 | { .name = "SMCR_EL1", .state = ARM_CP_STATE_AA64, |
7111 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 6, | |
7112 | .access = PL1_RW, .type = ARM_CP_SME, | |
7113 | .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[1]), | |
7114 | .writefn = smcr_write, .raw_writefn = raw_write }, | |
7115 | { .name = "SMCR_EL2", .state = ARM_CP_STATE_AA64, | |
7116 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 6, | |
7117 | .access = PL2_RW, .type = ARM_CP_SME, | |
7118 | .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[2]), | |
7119 | .writefn = smcr_write, .raw_writefn = raw_write }, | |
7120 | { .name = "SMCR_EL3", .state = ARM_CP_STATE_AA64, | |
7121 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 6, | |
7122 | .access = PL3_RW, .type = ARM_CP_SME, | |
7123 | .fieldoffset = offsetof(CPUARMState, vfp.smcr_el[3]), | |
7124 | .writefn = smcr_write, .raw_writefn = raw_write }, | |
d5b1223a RH |
7125 | { .name = "SMIDR_EL1", .state = ARM_CP_STATE_AA64, |
7126 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 6, | |
7127 | .access = PL1_R, .accessfn = access_aa64_tid1, | |
7128 | /* | |
7129 | * IMPLEMENTOR = 0 (software) | |
7130 | * REVISION = 0 (implementation defined) | |
7131 | * SMPS = 0 (no streaming execution priority in QEMU) | |
7132 | * AFFINITY = 0 (streaming sve mode not shared with other PEs) | |
7133 | */ | |
7134 | .type = ARM_CP_CONST, .resetvalue = 0, }, | |
7135 | /* | |
7136 | * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0. | |
7137 | */ | |
7138 | { .name = "SMPRI_EL1", .state = ARM_CP_STATE_AA64, | |
7139 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 4, | |
7140 | .access = PL1_RW, .accessfn = access_esm, | |
bd8db7d9 | 7141 | .fgt = FGT_NSMPRI_EL1, |
d5b1223a RH |
7142 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
7143 | { .name = "SMPRIMAP_EL2", .state = ARM_CP_STATE_AA64, | |
7144 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 5, | |
7145 | .access = PL2_RW, .accessfn = access_esm, | |
7146 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
9e5ec745 | 7147 | }; |
ef1febe7 RH |
7148 | |
7149 | static void tlbi_aa64_paall_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
7150 | uint64_t value) | |
7151 | { | |
7152 | CPUState *cs = env_cpu(env); | |
7153 | ||
7154 | tlb_flush(cs); | |
7155 | } | |
7156 | ||
7157 | static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
7158 | uint64_t value) | |
7159 | { | |
7160 | /* L0GPTSZ is RO; other bits not mentioned are RES0. */ | |
7161 | uint64_t rw_mask = R_GPCCR_PPS_MASK | R_GPCCR_IRGN_MASK | | |
7162 | R_GPCCR_ORGN_MASK | R_GPCCR_SH_MASK | R_GPCCR_PGS_MASK | | |
7163 | R_GPCCR_GPC_MASK | R_GPCCR_GPCP_MASK; | |
7164 | ||
7165 | env->cp15.gpccr_el3 = (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw_mask); | |
7166 | } | |
7167 | ||
7168 | static void gpccr_reset(CPUARMState *env, const ARMCPRegInfo *ri) | |
7169 | { | |
7170 | env->cp15.gpccr_el3 = FIELD_DP64(0, GPCCR, L0GPTSZ, | |
7171 | env_archcpu(env)->reset_l0gptsz); | |
7172 | } | |
7173 | ||
7174 | static void tlbi_aa64_paallos_write(CPUARMState *env, const ARMCPRegInfo *ri, | |
7175 | uint64_t value) | |
7176 | { | |
7177 | CPUState *cs = env_cpu(env); | |
7178 | ||
7179 | tlb_flush_all_cpus_synced(cs); | |
7180 | } | |
7181 | ||
7182 | static const ARMCPRegInfo rme_reginfo[] = { | |
7183 | { .name = "GPCCR_EL3", .state = ARM_CP_STATE_AA64, | |
7184 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 6, | |
7185 | .access = PL3_RW, .writefn = gpccr_write, .resetfn = gpccr_reset, | |
7186 | .fieldoffset = offsetof(CPUARMState, cp15.gpccr_el3) }, | |
7187 | { .name = "GPTBR_EL3", .state = ARM_CP_STATE_AA64, | |
7188 | .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 4, | |
7189 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.gptbr_el3) }, | |
7190 | { .name = "MFAR_EL3", .state = ARM_CP_STATE_AA64, | |
7191 | .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 5, | |
7192 | .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mfar_el3) }, | |
7193 | { .name = "TLBI_PAALL", .state = ARM_CP_STATE_AA64, | |
7194 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 4, | |
7195 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7196 | .writefn = tlbi_aa64_paall_write }, | |
7197 | { .name = "TLBI_PAALLOS", .state = ARM_CP_STATE_AA64, | |
7198 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 4, | |
7199 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7200 | .writefn = tlbi_aa64_paallos_write }, | |
7201 | /* | |
7202 | * QEMU does not have a way to invalidate by physical address, thus | |
7203 | * invalidating a range of physical addresses is accomplished by | |
673d8215 | 7204 | * flushing all tlb entries in the outer shareable domain, |
ef1febe7 RH |
7205 | * just like PAALLOS. |
7206 | */ | |
7207 | { .name = "TLBI_RPALOS", .state = ARM_CP_STATE_AA64, | |
7208 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 7, | |
7209 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7210 | .writefn = tlbi_aa64_paallos_write }, | |
7211 | { .name = "TLBI_RPAOS", .state = ARM_CP_STATE_AA64, | |
7212 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 3, | |
7213 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7214 | .writefn = tlbi_aa64_paallos_write }, | |
7215 | { .name = "DC_CIPAPA", .state = ARM_CP_STATE_AA64, | |
7216 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 1, | |
7217 | .access = PL3_W, .type = ARM_CP_NOP }, | |
7218 | }; | |
7219 | ||
7220 | static const ARMCPRegInfo rme_mte_reginfo[] = { | |
7221 | { .name = "DC_CIGDPAPA", .state = ARM_CP_STATE_AA64, | |
7222 | .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 5, | |
7223 | .access = PL3_W, .type = ARM_CP_NOP }, | |
7224 | }; | |
9e5ec745 RH |
7225 | #endif /* TARGET_AARCH64 */ |
7226 | ||
24183fb6 PM |
7227 | static void define_pmu_regs(ARMCPU *cpu) |
7228 | { | |
7229 | /* | |
7230 | * v7 performance monitor control register: same implementor | |
7231 | * field as main ID register, and we implement four counters in | |
7232 | * addition to the cycle count register. | |
7233 | */ | |
24526bb9 | 7234 | unsigned int i, pmcrn = pmu_num_counters(&cpu->env); |
24183fb6 PM |
7235 | ARMCPRegInfo pmcr = { |
7236 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | |
7237 | .access = PL0_RW, | |
dc780233 | 7238 | .fgt = FGT_PMCR_EL0, |
24183fb6 PM |
7239 | .type = ARM_CP_IO | ARM_CP_ALIAS, |
7240 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), | |
6980c31d JPB |
7241 | .accessfn = pmreg_access, |
7242 | .readfn = pmcr_read, .raw_readfn = raw_read, | |
7243 | .writefn = pmcr_write, .raw_writefn = raw_write, | |
24183fb6 PM |
7244 | }; |
7245 | ARMCPRegInfo pmcr64 = { | |
7246 | .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, | |
7247 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, | |
7248 | .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 7249 | .fgt = FGT_PMCR_EL0, |
24183fb6 PM |
7250 | .type = ARM_CP_IO, |
7251 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), | |
24526bb9 | 7252 | .resetvalue = cpu->isar.reset_pmcr_el0, |
6980c31d | 7253 | .readfn = pmcr_read, .raw_readfn = raw_read, |
24183fb6 PM |
7254 | .writefn = pmcr_write, .raw_writefn = raw_write, |
7255 | }; | |
24526bb9 | 7256 | |
24183fb6 PM |
7257 | define_one_arm_cp_reg(cpu, &pmcr); |
7258 | define_one_arm_cp_reg(cpu, &pmcr64); | |
7259 | for (i = 0; i < pmcrn; i++) { | |
7260 | char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i); | |
7261 | char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i); | |
7262 | char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i); | |
7263 | char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i); | |
7264 | ARMCPRegInfo pmev_regs[] = { | |
7265 | { .name = pmevcntr_name, .cp = 15, .crn = 14, | |
7266 | .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, | |
7267 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
dc780233 | 7268 | .fgt = FGT_PMEVCNTRN_EL0, |
24183fb6 | 7269 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, |
99a50d1a | 7270 | .accessfn = pmreg_access_xevcntr }, |
24183fb6 PM |
7271 | { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64, |
7272 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)), | |
99a50d1a | 7273 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr, |
24183fb6 | 7274 | .type = ARM_CP_IO, |
dc780233 | 7275 | .fgt = FGT_PMEVCNTRN_EL0, |
24183fb6 PM |
7276 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, |
7277 | .raw_readfn = pmevcntr_rawread, | |
7278 | .raw_writefn = pmevcntr_rawwrite }, | |
7279 | { .name = pmevtyper_name, .cp = 15, .crn = 14, | |
7280 | .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, | |
7281 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | |
dc780233 | 7282 | .fgt = FGT_PMEVTYPERN_EL0, |
24183fb6 PM |
7283 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, |
7284 | .accessfn = pmreg_access }, | |
7285 | { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64, | |
7286 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)), | |
7287 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, | |
dc780233 | 7288 | .fgt = FGT_PMEVTYPERN_EL0, |
24183fb6 PM |
7289 | .type = ARM_CP_IO, |
7290 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | |
7291 | .raw_writefn = pmevtyper_rawwrite }, | |
24183fb6 PM |
7292 | }; |
7293 | define_arm_cp_regs(cpu, pmev_regs); | |
7294 | g_free(pmevcntr_name); | |
7295 | g_free(pmevcntr_el0_name); | |
7296 | g_free(pmevtyper_name); | |
7297 | g_free(pmevtyper_el0_name); | |
7298 | } | |
a793bcd0 | 7299 | if (cpu_isar_feature(aa32_pmuv3p1, cpu)) { |
24183fb6 PM |
7300 | ARMCPRegInfo v81_pmu_regs[] = { |
7301 | { .name = "PMCEID2", .state = ARM_CP_STATE_AA32, | |
7302 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4, | |
7303 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 7304 | .fgt = FGT_PMCEIDN_EL0, |
24183fb6 PM |
7305 | .resetvalue = extract64(cpu->pmceid0, 32, 32) }, |
7306 | { .name = "PMCEID3", .state = ARM_CP_STATE_AA32, | |
7307 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5, | |
7308 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 7309 | .fgt = FGT_PMCEIDN_EL0, |
24183fb6 | 7310 | .resetvalue = extract64(cpu->pmceid1, 32, 32) }, |
24183fb6 PM |
7311 | }; |
7312 | define_arm_cp_regs(cpu, v81_pmu_regs); | |
7313 | } | |
a793bcd0 | 7314 | if (cpu_isar_feature(any_pmuv3p4, cpu)) { |
15dd1ebd PM |
7315 | static const ARMCPRegInfo v84_pmmir = { |
7316 | .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH, | |
7317 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6, | |
7318 | .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 7319 | .fgt = FGT_PMMIR_EL1, |
15dd1ebd PM |
7320 | .resetvalue = 0 |
7321 | }; | |
7322 | define_one_arm_cp_reg(cpu, &v84_pmmir); | |
7323 | } | |
24183fb6 PM |
7324 | } |
7325 | ||
0f150c84 | 7326 | #ifndef CONFIG_USER_ONLY |
9b37a28c FR |
7327 | /* |
7328 | * We don't know until after realize whether there's a GICv3 | |
96a8b92e PM |
7329 | * attached, and that is what registers the gicv3 sysregs. |
7330 | * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1 | |
7331 | * at runtime. | |
7332 | */ | |
7333 | static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
7334 | { | |
2fc0cc0e | 7335 | ARMCPU *cpu = env_archcpu(env); |
8a130a7b | 7336 | uint64_t pfr1 = cpu->isar.id_pfr1; |
96a8b92e PM |
7337 | |
7338 | if (env->gicv3state) { | |
7339 | pfr1 |= 1 << 28; | |
7340 | } | |
7341 | return pfr1; | |
7342 | } | |
7343 | ||
7344 | static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
7345 | { | |
2fc0cc0e | 7346 | ARMCPU *cpu = env_archcpu(env); |
47576b94 | 7347 | uint64_t pfr0 = cpu->isar.id_aa64pfr0; |
96a8b92e PM |
7348 | |
7349 | if (env->gicv3state) { | |
7350 | pfr0 |= 1 << 24; | |
7351 | } | |
7352 | return pfr0; | |
7353 | } | |
976b99b6 | 7354 | #endif |
96a8b92e | 7355 | |
9b37a28c FR |
7356 | /* |
7357 | * Shared logic between LORID and the rest of the LOR* registers. | |
9bd268ba | 7358 | * Secure state exclusion has already been dealt with. |
2d7137c1 | 7359 | */ |
9bd268ba RDC |
7360 | static CPAccessResult access_lor_ns(CPUARMState *env, |
7361 | const ARMCPRegInfo *ri, bool isread) | |
2d7137c1 RH |
7362 | { |
7363 | int el = arm_current_el(env); | |
7364 | ||
7365 | if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) { | |
7366 | return CP_ACCESS_TRAP_EL2; | |
7367 | } | |
7368 | if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { | |
7369 | return CP_ACCESS_TRAP_EL3; | |
7370 | } | |
7371 | return CP_ACCESS_OK; | |
7372 | } | |
7373 | ||
2d7137c1 RH |
7374 | static CPAccessResult access_lor_other(CPUARMState *env, |
7375 | const ARMCPRegInfo *ri, bool isread) | |
7376 | { | |
7377 | if (arm_is_secure_below_el3(env)) { | |
7378 | /* Access denied in secure mode. */ | |
7379 | return CP_ACCESS_TRAP; | |
7380 | } | |
9bd268ba | 7381 | return access_lor_ns(env, ri, isread); |
2d7137c1 RH |
7382 | } |
7383 | ||
d8564ee4 RH |
7384 | /* |
7385 | * A trivial implementation of ARMv8.1-LOR leaves all of these | |
7386 | * registers fixed at 0, which indicates that there are zero | |
7387 | * supported Limited Ordering regions. | |
7388 | */ | |
7389 | static const ARMCPRegInfo lor_reginfo[] = { | |
7390 | { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, | |
7391 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, | |
7392 | .access = PL1_RW, .accessfn = access_lor_other, | |
b19ed03c | 7393 | .fgt = FGT_LORSA_EL1, |
d8564ee4 RH |
7394 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
7395 | { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, | |
7396 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, | |
7397 | .access = PL1_RW, .accessfn = access_lor_other, | |
b19ed03c | 7398 | .fgt = FGT_LOREA_EL1, |
d8564ee4 RH |
7399 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
7400 | { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, | |
7401 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, | |
7402 | .access = PL1_RW, .accessfn = access_lor_other, | |
b19ed03c | 7403 | .fgt = FGT_LORN_EL1, |
d8564ee4 RH |
7404 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
7405 | { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, | |
7406 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, | |
7407 | .access = PL1_RW, .accessfn = access_lor_other, | |
b19ed03c | 7408 | .fgt = FGT_LORC_EL1, |
d8564ee4 RH |
7409 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
7410 | { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, | |
7411 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, | |
9bd268ba | 7412 | .access = PL1_R, .accessfn = access_lor_ns, |
b19ed03c | 7413 | .fgt = FGT_LORID_EL1, |
d8564ee4 | 7414 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
d8564ee4 RH |
7415 | }; |
7416 | ||
967aa94f RH |
7417 | #ifdef TARGET_AARCH64 |
7418 | static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, | |
7419 | bool isread) | |
7420 | { | |
7421 | int el = arm_current_el(env); | |
7422 | ||
7423 | if (el < 2 && | |
07b034ea | 7424 | arm_is_el2_enabled(env) && |
967aa94f RH |
7425 | !(arm_hcr_el2_eff(env) & HCR_APK)) { |
7426 | return CP_ACCESS_TRAP_EL2; | |
7427 | } | |
7428 | if (el < 3 && | |
7429 | arm_feature(env, ARM_FEATURE_EL3) && | |
7430 | !(env->cp15.scr_el3 & SCR_APK)) { | |
7431 | return CP_ACCESS_TRAP_EL3; | |
7432 | } | |
7433 | return CP_ACCESS_OK; | |
7434 | } | |
7435 | ||
7436 | static const ARMCPRegInfo pauth_reginfo[] = { | |
7437 | { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64, | |
7438 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0, | |
7439 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7440 | .fgt = FGT_APDAKEY, |
108b3ba8 | 7441 | .fieldoffset = offsetof(CPUARMState, keys.apda.lo) }, |
967aa94f RH |
7442 | { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
7443 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1, | |
7444 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7445 | .fgt = FGT_APDAKEY, |
108b3ba8 | 7446 | .fieldoffset = offsetof(CPUARMState, keys.apda.hi) }, |
967aa94f RH |
7447 | { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
7448 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2, | |
7449 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7450 | .fgt = FGT_APDBKEY, |
108b3ba8 | 7451 | .fieldoffset = offsetof(CPUARMState, keys.apdb.lo) }, |
967aa94f RH |
7452 | { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
7453 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3, | |
7454 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7455 | .fgt = FGT_APDBKEY, |
108b3ba8 | 7456 | .fieldoffset = offsetof(CPUARMState, keys.apdb.hi) }, |
967aa94f RH |
7457 | { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
7458 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0, | |
7459 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7460 | .fgt = FGT_APGAKEY, |
108b3ba8 | 7461 | .fieldoffset = offsetof(CPUARMState, keys.apga.lo) }, |
967aa94f RH |
7462 | { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
7463 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1, | |
7464 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7465 | .fgt = FGT_APGAKEY, |
108b3ba8 | 7466 | .fieldoffset = offsetof(CPUARMState, keys.apga.hi) }, |
967aa94f RH |
7467 | { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
7468 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0, | |
7469 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7470 | .fgt = FGT_APIAKEY, |
108b3ba8 | 7471 | .fieldoffset = offsetof(CPUARMState, keys.apia.lo) }, |
967aa94f RH |
7472 | { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
7473 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1, | |
7474 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7475 | .fgt = FGT_APIAKEY, |
108b3ba8 | 7476 | .fieldoffset = offsetof(CPUARMState, keys.apia.hi) }, |
967aa94f RH |
7477 | { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
7478 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2, | |
7479 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7480 | .fgt = FGT_APIBKEY, |
108b3ba8 | 7481 | .fieldoffset = offsetof(CPUARMState, keys.apib.lo) }, |
967aa94f RH |
7482 | { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
7483 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3, | |
7484 | .access = PL1_RW, .accessfn = access_pauth, | |
158c276c | 7485 | .fgt = FGT_APIBKEY, |
108b3ba8 | 7486 | .fieldoffset = offsetof(CPUARMState, keys.apib.hi) }, |
967aa94f | 7487 | }; |
de390645 | 7488 | |
84940ed8 RC |
7489 | static const ARMCPRegInfo tlbirange_reginfo[] = { |
7490 | { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64, | |
7491 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1, | |
0f66d223 | 7492 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7493 | .fgt = FGT_TLBIRVAE1IS, |
84940ed8 RC |
7494 | .writefn = tlbi_aa64_rvae1is_write }, |
7495 | { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64, | |
7496 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3, | |
0f66d223 | 7497 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7498 | .fgt = FGT_TLBIRVAAE1IS, |
84940ed8 RC |
7499 | .writefn = tlbi_aa64_rvae1is_write }, |
7500 | { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64, | |
7501 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5, | |
0f66d223 | 7502 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7503 | .fgt = FGT_TLBIRVALE1IS, |
84940ed8 RC |
7504 | .writefn = tlbi_aa64_rvae1is_write }, |
7505 | { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64, | |
7506 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7, | |
0f66d223 | 7507 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7508 | .fgt = FGT_TLBIRVAALE1IS, |
84940ed8 RC |
7509 | .writefn = tlbi_aa64_rvae1is_write }, |
7510 | { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64, | |
7511 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, | |
fe3ca86c | 7512 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7513 | .fgt = FGT_TLBIRVAE1OS, |
84940ed8 RC |
7514 | .writefn = tlbi_aa64_rvae1is_write }, |
7515 | { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64, | |
7516 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3, | |
fe3ca86c | 7517 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7518 | .fgt = FGT_TLBIRVAAE1OS, |
84940ed8 RC |
7519 | .writefn = tlbi_aa64_rvae1is_write }, |
7520 | { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64, | |
7521 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5, | |
fe3ca86c | 7522 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7523 | .fgt = FGT_TLBIRVALE1OS, |
84940ed8 RC |
7524 | .writefn = tlbi_aa64_rvae1is_write }, |
7525 | { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64, | |
7526 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7, | |
fe3ca86c | 7527 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7528 | .fgt = FGT_TLBIRVAALE1OS, |
84940ed8 RC |
7529 | .writefn = tlbi_aa64_rvae1is_write }, |
7530 | { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64, | |
7531 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, | |
4870f38b | 7532 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7533 | .fgt = FGT_TLBIRVAE1, |
84940ed8 RC |
7534 | .writefn = tlbi_aa64_rvae1_write }, |
7535 | { .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64, | |
7536 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3, | |
4870f38b | 7537 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7538 | .fgt = FGT_TLBIRVAAE1, |
84940ed8 RC |
7539 | .writefn = tlbi_aa64_rvae1_write }, |
7540 | { .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64, | |
7541 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5, | |
4870f38b | 7542 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7543 | .fgt = FGT_TLBIRVALE1, |
84940ed8 RC |
7544 | .writefn = tlbi_aa64_rvae1_write }, |
7545 | { .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64, | |
7546 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7, | |
4870f38b | 7547 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7548 | .fgt = FGT_TLBIRVAALE1, |
84940ed8 RC |
7549 | .writefn = tlbi_aa64_rvae1_write }, |
7550 | { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64, | |
7551 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2, | |
575a94af RH |
7552 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
7553 | .writefn = tlbi_aa64_ripas2e1is_write }, | |
84940ed8 RC |
7554 | { .name = "TLBI_RIPAS2LE1IS", .state = ARM_CP_STATE_AA64, |
7555 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 6, | |
575a94af RH |
7556 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
7557 | .writefn = tlbi_aa64_ripas2e1is_write }, | |
84940ed8 RC |
7558 | { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64, |
7559 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1, | |
696ba377 | 7560 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
7561 | .writefn = tlbi_aa64_rvae2is_write }, |
7562 | { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64, | |
7563 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5, | |
696ba377 | 7564 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
7565 | .writefn = tlbi_aa64_rvae2is_write }, |
7566 | { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64, | |
7567 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2, | |
575a94af RH |
7568 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
7569 | .writefn = tlbi_aa64_ripas2e1_write }, | |
7570 | { .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64, | |
84940ed8 | 7571 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 6, |
575a94af RH |
7572 | .access = PL2_W, .type = ARM_CP_NO_RAW, |
7573 | .writefn = tlbi_aa64_ripas2e1_write }, | |
84940ed8 RC |
7574 | { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64, |
7575 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1, | |
696ba377 | 7576 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
7577 | .writefn = tlbi_aa64_rvae2is_write }, |
7578 | { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64, | |
7579 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5, | |
696ba377 | 7580 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
7581 | .writefn = tlbi_aa64_rvae2is_write }, |
7582 | { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64, | |
7583 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1, | |
696ba377 | 7584 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
7585 | .writefn = tlbi_aa64_rvae2_write }, |
7586 | { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64, | |
7587 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5, | |
696ba377 | 7588 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
84940ed8 RC |
7589 | .writefn = tlbi_aa64_rvae2_write }, |
7590 | { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64, | |
7591 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1, | |
7592 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7593 | .writefn = tlbi_aa64_rvae3is_write }, | |
7594 | { .name = "TLBI_RVALE3IS", .state = ARM_CP_STATE_AA64, | |
7595 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 5, | |
7596 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7597 | .writefn = tlbi_aa64_rvae3is_write }, | |
7598 | { .name = "TLBI_RVAE3OS", .state = ARM_CP_STATE_AA64, | |
7599 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 1, | |
7600 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7601 | .writefn = tlbi_aa64_rvae3is_write }, | |
7602 | { .name = "TLBI_RVALE3OS", .state = ARM_CP_STATE_AA64, | |
7603 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 5, | |
7604 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7605 | .writefn = tlbi_aa64_rvae3is_write }, | |
7606 | { .name = "TLBI_RVAE3", .state = ARM_CP_STATE_AA64, | |
7607 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 1, | |
7608 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7609 | .writefn = tlbi_aa64_rvae3_write }, | |
7610 | { .name = "TLBI_RVALE3", .state = ARM_CP_STATE_AA64, | |
7611 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5, | |
7612 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7613 | .writefn = tlbi_aa64_rvae3_write }, | |
84940ed8 RC |
7614 | }; |
7615 | ||
7113d618 RC |
7616 | static const ARMCPRegInfo tlbios_reginfo[] = { |
7617 | { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64, | |
7618 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0, | |
fe3ca86c | 7619 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7620 | .fgt = FGT_TLBIVMALLE1OS, |
7113d618 | 7621 | .writefn = tlbi_aa64_vmalle1is_write }, |
b7469ef9 IH |
7622 | { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64, |
7623 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1, | |
bf2f0625 | 7624 | .fgt = FGT_TLBIVAE1OS, |
fe3ca86c | 7625 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
b7469ef9 | 7626 | .writefn = tlbi_aa64_vae1is_write }, |
7113d618 RC |
7627 | { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64, |
7628 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2, | |
fe3ca86c | 7629 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7630 | .fgt = FGT_TLBIASIDE1OS, |
7113d618 | 7631 | .writefn = tlbi_aa64_vmalle1is_write }, |
b7469ef9 IH |
7632 | { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64, |
7633 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3, | |
fe3ca86c | 7634 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7635 | .fgt = FGT_TLBIVAAE1OS, |
b7469ef9 IH |
7636 | .writefn = tlbi_aa64_vae1is_write }, |
7637 | { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64, | |
7638 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5, | |
fe3ca86c | 7639 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7640 | .fgt = FGT_TLBIVALE1OS, |
b7469ef9 IH |
7641 | .writefn = tlbi_aa64_vae1is_write }, |
7642 | { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64, | |
7643 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7, | |
fe3ca86c | 7644 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, |
bf2f0625 | 7645 | .fgt = FGT_TLBIVAALE1OS, |
b7469ef9 | 7646 | .writefn = tlbi_aa64_vae1is_write }, |
7113d618 RC |
7647 | { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64, |
7648 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0, | |
696ba377 | 7649 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
7113d618 | 7650 | .writefn = tlbi_aa64_alle2is_write }, |
b7469ef9 IH |
7651 | { .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64, |
7652 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1, | |
696ba377 | 7653 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
b7469ef9 | 7654 | .writefn = tlbi_aa64_vae2is_write }, |
7113d618 RC |
7655 | { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64, |
7656 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4, | |
7657 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
7658 | .writefn = tlbi_aa64_alle1is_write }, | |
b7469ef9 IH |
7659 | { .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64, |
7660 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5, | |
696ba377 | 7661 | .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, |
b7469ef9 | 7662 | .writefn = tlbi_aa64_vae2is_write }, |
7113d618 RC |
7663 | { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64, |
7664 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6, | |
7665 | .access = PL2_W, .type = ARM_CP_NO_RAW, | |
7666 | .writefn = tlbi_aa64_alle1is_write }, | |
7667 | { .name = "TLBI_IPAS2E1OS", .state = ARM_CP_STATE_AA64, | |
7668 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 0, | |
7669 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7670 | { .name = "TLBI_RIPAS2E1OS", .state = ARM_CP_STATE_AA64, | |
7671 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 3, | |
7672 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7673 | { .name = "TLBI_IPAS2LE1OS", .state = ARM_CP_STATE_AA64, | |
7674 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 4, | |
7675 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7676 | { .name = "TLBI_RIPAS2LE1OS", .state = ARM_CP_STATE_AA64, | |
7677 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 7, | |
7678 | .access = PL2_W, .type = ARM_CP_NOP }, | |
7679 | { .name = "TLBI_ALLE3OS", .state = ARM_CP_STATE_AA64, | |
7680 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 0, | |
7681 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7682 | .writefn = tlbi_aa64_alle3is_write }, | |
b7469ef9 IH |
7683 | { .name = "TLBI_VAE3OS", .state = ARM_CP_STATE_AA64, |
7684 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 1, | |
7685 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7686 | .writefn = tlbi_aa64_vae3is_write }, | |
7687 | { .name = "TLBI_VALE3OS", .state = ARM_CP_STATE_AA64, | |
7688 | .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 5, | |
7689 | .access = PL3_W, .type = ARM_CP_NO_RAW, | |
7690 | .writefn = tlbi_aa64_vae3is_write }, | |
7113d618 RC |
7691 | }; |
7692 | ||
de390645 RH |
7693 | static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) |
7694 | { | |
7695 | Error *err = NULL; | |
7696 | uint64_t ret; | |
7697 | ||
7698 | /* Success sets NZCV = 0000. */ | |
7699 | env->NF = env->CF = env->VF = 0, env->ZF = 1; | |
7700 | ||
7701 | if (qemu_guest_getrandom(&ret, sizeof(ret), &err) < 0) { | |
7702 | /* | |
7703 | * ??? Failed, for unknown reasons in the crypto subsystem. | |
7704 | * The best we can do is log the reason and return the | |
7705 | * timed-out indication to the guest. There is no reason | |
7706 | * we know to expect this failure to be transitory, so the | |
7707 | * guest may well hang retrying the operation. | |
7708 | */ | |
7709 | qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", | |
7710 | ri->name, error_get_pretty(err)); | |
7711 | error_free(err); | |
7712 | ||
7713 | env->ZF = 0; /* NZCF = 0100 */ | |
7714 | return 0; | |
7715 | } | |
7716 | return ret; | |
7717 | } | |
7718 | ||
7719 | /* We do not support re-seeding, so the two registers operate the same. */ | |
7720 | static const ARMCPRegInfo rndr_reginfo[] = { | |
7721 | { .name = "RNDR", .state = ARM_CP_STATE_AA64, | |
7722 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | |
7723 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 0, | |
7724 | .access = PL0_R, .readfn = rndr_readfn }, | |
7725 | { .name = "RNDRRS", .state = ARM_CP_STATE_AA64, | |
7726 | .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, | |
7727 | .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1, | |
7728 | .access = PL0_R, .readfn = rndr_readfn }, | |
de390645 | 7729 | }; |
0d57b499 | 7730 | |
0d57b499 BM |
7731 | static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, |
7732 | uint64_t value) | |
7733 | { | |
7a3014a9 | 7734 | #ifdef CONFIG_TCG |
0d57b499 BM |
7735 | ARMCPU *cpu = env_archcpu(env); |
7736 | /* CTR_EL0 System register -> DminLine, bits [19:16] */ | |
7737 | uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF); | |
7738 | uint64_t vaddr_in = (uint64_t) value; | |
7739 | uint64_t vaddr = vaddr_in & ~(dline_size - 1); | |
7740 | void *haddr; | |
7741 | int mem_idx = cpu_mmu_index(env, false); | |
7742 | ||
7743 | /* This won't be crossing page boundaries */ | |
7744 | haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC()); | |
7745 | if (haddr) { | |
cd4a47f9 | 7746 | #ifndef CONFIG_USER_ONLY |
0d57b499 BM |
7747 | |
7748 | ram_addr_t offset; | |
7749 | MemoryRegion *mr; | |
7750 | ||
7751 | /* RCU lock is already being held */ | |
7752 | mr = memory_region_from_host(haddr, &offset); | |
7753 | ||
7754 | if (mr) { | |
4dfe59d1 | 7755 | memory_region_writeback(mr, offset, dline_size); |
0d57b499 | 7756 | } |
cd4a47f9 | 7757 | #endif /*CONFIG_USER_ONLY*/ |
0d57b499 | 7758 | } |
7a3014a9 PMD |
7759 | #else |
7760 | /* Handled by hardware accelerator. */ | |
7761 | g_assert_not_reached(); | |
7762 | #endif /* CONFIG_TCG */ | |
0d57b499 BM |
7763 | } |
7764 | ||
7765 | static const ARMCPRegInfo dcpop_reg[] = { | |
7766 | { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64, | |
7767 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1, | |
7768 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | |
dd345653 | 7769 | .fgt = FGT_DCCVAP, |
1bed4d2e | 7770 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, |
0d57b499 BM |
7771 | }; |
7772 | ||
7773 | static const ARMCPRegInfo dcpodp_reg[] = { | |
7774 | { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64, | |
7775 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1, | |
7776 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | |
dd345653 | 7777 | .fgt = FGT_DCCVADP, |
1bed4d2e | 7778 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, |
0d57b499 | 7779 | }; |
0d57b499 | 7780 | |
4b779ceb RH |
7781 | static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInfo *ri, |
7782 | bool isread) | |
7783 | { | |
7784 | if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID5)) { | |
7785 | return CP_ACCESS_TRAP_EL2; | |
7786 | } | |
7787 | ||
7788 | return CP_ACCESS_OK; | |
7789 | } | |
7790 | ||
7791 | static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri, | |
7792 | bool isread) | |
7793 | { | |
7794 | int el = arm_current_el(env); | |
7795 | ||
0da067f2 | 7796 | if (el < 2 && arm_is_el2_enabled(env)) { |
4301acd7 RH |
7797 | uint64_t hcr = arm_hcr_el2_eff(env); |
7798 | if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { | |
7799 | return CP_ACCESS_TRAP_EL2; | |
7800 | } | |
4b779ceb RH |
7801 | } |
7802 | if (el < 3 && | |
7803 | arm_feature(env, ARM_FEATURE_EL3) && | |
7804 | !(env->cp15.scr_el3 & SCR_ATA)) { | |
7805 | return CP_ACCESS_TRAP_EL3; | |
7806 | } | |
7807 | return CP_ACCESS_OK; | |
7808 | } | |
7809 | ||
7810 | static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
7811 | { | |
7812 | return env->pstate & PSTATE_TCO; | |
7813 | } | |
7814 | ||
7815 | static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | |
7816 | { | |
7817 | env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); | |
7818 | } | |
7819 | ||
7820 | static const ARMCPRegInfo mte_reginfo[] = { | |
7821 | { .name = "TFSRE0_EL1", .state = ARM_CP_STATE_AA64, | |
7822 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 1, | |
7823 | .access = PL1_RW, .accessfn = access_mte, | |
7824 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) }, | |
7825 | { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64, | |
7826 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 0, | |
7827 | .access = PL1_RW, .accessfn = access_mte, | |
7828 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) }, | |
7829 | { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64, | |
7830 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 6, .opc2 = 0, | |
7831 | .access = PL2_RW, .accessfn = access_mte, | |
7832 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) }, | |
7833 | { .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64, | |
7834 | .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 6, .opc2 = 0, | |
7835 | .access = PL3_RW, | |
7836 | .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) }, | |
7837 | { .name = "RGSR_EL1", .state = ARM_CP_STATE_AA64, | |
7838 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5, | |
7839 | .access = PL1_RW, .accessfn = access_mte, | |
7840 | .fieldoffset = offsetof(CPUARMState, cp15.rgsr_el1) }, | |
7841 | { .name = "GCR_EL1", .state = ARM_CP_STATE_AA64, | |
7842 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6, | |
7843 | .access = PL1_RW, .accessfn = access_mte, | |
7844 | .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, | |
4b779ceb RH |
7845 | { .name = "TCO", .state = ARM_CP_STATE_AA64, |
7846 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | |
7847 | .type = ARM_CP_NO_RAW, | |
7848 | .access = PL0_RW, .readfn = tco_read, .writefn = tco_write }, | |
5463df16 RH |
7849 | { .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64, |
7850 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3, | |
7851 | .type = ARM_CP_NOP, .access = PL1_W, | |
dd345653 | 7852 | .fgt = FGT_DCIVAC, |
5463df16 RH |
7853 | .accessfn = aa64_cacheop_poc_access }, |
7854 | { .name = "DC_IGSW", .state = ARM_CP_STATE_AA64, | |
7855 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4, | |
dd345653 | 7856 | .fgt = FGT_DCISW, |
5463df16 RH |
7857 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
7858 | { .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64, | |
7859 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5, | |
7860 | .type = ARM_CP_NOP, .access = PL1_W, | |
dd345653 | 7861 | .fgt = FGT_DCIVAC, |
5463df16 RH |
7862 | .accessfn = aa64_cacheop_poc_access }, |
7863 | { .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64, | |
7864 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6, | |
dd345653 | 7865 | .fgt = FGT_DCISW, |
5463df16 RH |
7866 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
7867 | { .name = "DC_CGSW", .state = ARM_CP_STATE_AA64, | |
7868 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4, | |
dd345653 | 7869 | .fgt = FGT_DCCSW, |
5463df16 RH |
7870 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
7871 | { .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64, | |
7872 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6, | |
dd345653 | 7873 | .fgt = FGT_DCCSW, |
5463df16 RH |
7874 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
7875 | { .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64, | |
7876 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4, | |
dd345653 | 7877 | .fgt = FGT_DCCISW, |
5463df16 RH |
7878 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
7879 | { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64, | |
7880 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6, | |
dd345653 | 7881 | .fgt = FGT_DCCISW, |
5463df16 | 7882 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, |
4b779ceb RH |
7883 | }; |
7884 | ||
7885 | static const ARMCPRegInfo mte_tco_ro_reginfo[] = { | |
7886 | { .name = "TCO", .state = ARM_CP_STATE_AA64, | |
7887 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | |
7888 | .type = ARM_CP_CONST, .access = PL0_RW, }, | |
4b779ceb | 7889 | }; |
5463df16 RH |
7890 | |
7891 | static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | |
7892 | { .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64, | |
7893 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3, | |
7894 | .type = ARM_CP_NOP, .access = PL0_W, | |
950037e2 | 7895 | .fgt = FGT_DCCVAC, |
5463df16 RH |
7896 | .accessfn = aa64_cacheop_poc_access }, |
7897 | { .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64, | |
7898 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5, | |
7899 | .type = ARM_CP_NOP, .access = PL0_W, | |
950037e2 | 7900 | .fgt = FGT_DCCVAC, |
5463df16 RH |
7901 | .accessfn = aa64_cacheop_poc_access }, |
7902 | { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64, | |
7903 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3, | |
7904 | .type = ARM_CP_NOP, .access = PL0_W, | |
dd345653 | 7905 | .fgt = FGT_DCCVAP, |
5463df16 RH |
7906 | .accessfn = aa64_cacheop_poc_access }, |
7907 | { .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64, | |
7908 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5, | |
7909 | .type = ARM_CP_NOP, .access = PL0_W, | |
dd345653 | 7910 | .fgt = FGT_DCCVAP, |
5463df16 RH |
7911 | .accessfn = aa64_cacheop_poc_access }, |
7912 | { .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64, | |
7913 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3, | |
7914 | .type = ARM_CP_NOP, .access = PL0_W, | |
dd345653 | 7915 | .fgt = FGT_DCCVADP, |
5463df16 RH |
7916 | .accessfn = aa64_cacheop_poc_access }, |
7917 | { .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64, | |
7918 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5, | |
7919 | .type = ARM_CP_NOP, .access = PL0_W, | |
dd345653 | 7920 | .fgt = FGT_DCCVADP, |
5463df16 RH |
7921 | .accessfn = aa64_cacheop_poc_access }, |
7922 | { .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64, | |
7923 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3, | |
7924 | .type = ARM_CP_NOP, .access = PL0_W, | |
dd345653 | 7925 | .fgt = FGT_DCCIVAC, |
5463df16 RH |
7926 | .accessfn = aa64_cacheop_poc_access }, |
7927 | { .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64, | |
7928 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, | |
7929 | .type = ARM_CP_NOP, .access = PL0_W, | |
dd345653 | 7930 | .fgt = FGT_DCCIVAC, |
5463df16 | 7931 | .accessfn = aa64_cacheop_poc_access }, |
eb821168 RH |
7932 | { .name = "DC_GVA", .state = ARM_CP_STATE_AA64, |
7933 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3, | |
7934 | .access = PL0_W, .type = ARM_CP_DC_GVA, | |
7935 | #ifndef CONFIG_USER_ONLY | |
7936 | /* Avoid overhead of an access check that always passes in user-mode */ | |
7937 | .accessfn = aa64_zva_access, | |
dd345653 | 7938 | .fgt = FGT_DCZVA, |
eb821168 RH |
7939 | #endif |
7940 | }, | |
7941 | { .name = "DC_GZVA", .state = ARM_CP_STATE_AA64, | |
7942 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 4, | |
7943 | .access = PL0_W, .type = ARM_CP_DC_GZVA, | |
7944 | #ifndef CONFIG_USER_ONLY | |
7945 | /* Avoid overhead of an access check that always passes in user-mode */ | |
7946 | .accessfn = aa64_zva_access, | |
dd345653 | 7947 | .fgt = FGT_DCZVA, |
eb821168 RH |
7948 | #endif |
7949 | }, | |
5463df16 RH |
7950 | }; |
7951 | ||
7cb1e618 RH |
7952 | static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri, |
7953 | bool isread) | |
7954 | { | |
7955 | uint64_t hcr = arm_hcr_el2_eff(env); | |
7956 | int el = arm_current_el(env); | |
7957 | ||
7958 | if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) { | |
7959 | if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { | |
7960 | if (hcr & HCR_TGE) { | |
7961 | return CP_ACCESS_TRAP_EL2; | |
7962 | } | |
7963 | return CP_ACCESS_TRAP; | |
7964 | } | |
7965 | } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { | |
7966 | return CP_ACCESS_TRAP_EL2; | |
7967 | } | |
7968 | if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) { | |
7969 | return CP_ACCESS_TRAP_EL2; | |
7970 | } | |
7971 | if (el < 3 | |
7972 | && arm_feature(env, ARM_FEATURE_EL3) | |
7973 | && !(env->cp15.scr_el3 & SCR_ENSCXT)) { | |
7974 | return CP_ACCESS_TRAP_EL3; | |
7975 | } | |
7976 | return CP_ACCESS_OK; | |
7977 | } | |
7978 | ||
7979 | static const ARMCPRegInfo scxtnum_reginfo[] = { | |
7980 | { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64, | |
7981 | .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7, | |
7982 | .access = PL0_RW, .accessfn = access_scxtnum, | |
67dd8030 | 7983 | .fgt = FGT_SCXTNUM_EL0, |
7cb1e618 RH |
7984 | .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) }, |
7985 | { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64, | |
7986 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7, | |
7987 | .access = PL1_RW, .accessfn = access_scxtnum, | |
67dd8030 | 7988 | .fgt = FGT_SCXTNUM_EL1, |
7cb1e618 RH |
7989 | .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) }, |
7990 | { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64, | |
7991 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7, | |
7992 | .access = PL2_RW, .accessfn = access_scxtnum, | |
7993 | .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) }, | |
7994 | { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64, | |
7995 | .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7, | |
7996 | .access = PL3_RW, | |
7997 | .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) }, | |
7998 | }; | |
15126d9c PM |
7999 | |
8000 | static CPAccessResult access_fgt(CPUARMState *env, const ARMCPRegInfo *ri, | |
8001 | bool isread) | |
8002 | { | |
8003 | if (arm_current_el(env) == 2 && | |
8004 | arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_FGTEN)) { | |
8005 | return CP_ACCESS_TRAP_EL3; | |
8006 | } | |
8007 | return CP_ACCESS_OK; | |
8008 | } | |
8009 | ||
8010 | static const ARMCPRegInfo fgt_reginfo[] = { | |
8011 | { .name = "HFGRTR_EL2", .state = ARM_CP_STATE_AA64, | |
8012 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, | |
8013 | .access = PL2_RW, .accessfn = access_fgt, | |
8014 | .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HFGRTR]) }, | |
8015 | { .name = "HFGWTR_EL2", .state = ARM_CP_STATE_AA64, | |
8016 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 5, | |
8017 | .access = PL2_RW, .accessfn = access_fgt, | |
8018 | .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HFGWTR]) }, | |
8019 | { .name = "HDFGRTR_EL2", .state = ARM_CP_STATE_AA64, | |
8020 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 4, | |
8021 | .access = PL2_RW, .accessfn = access_fgt, | |
8022 | .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HDFGRTR]) }, | |
8023 | { .name = "HDFGWTR_EL2", .state = ARM_CP_STATE_AA64, | |
8024 | .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 5, | |
8025 | .access = PL2_RW, .accessfn = access_fgt, | |
8026 | .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HDFGWTR]) }, | |
8027 | { .name = "HFGITR_EL2", .state = ARM_CP_STATE_AA64, | |
8028 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 6, | |
8029 | .access = PL2_RW, .accessfn = access_fgt, | |
8030 | .fieldoffset = offsetof(CPUARMState, cp15.fgt_exec[FGTREG_HFGITR]) }, | |
8031 | }; | |
7cb1e618 | 8032 | #endif /* TARGET_AARCH64 */ |
967aa94f | 8033 | |
cb570bd3 RH |
8034 | static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, |
8035 | bool isread) | |
8036 | { | |
8037 | int el = arm_current_el(env); | |
8038 | ||
8039 | if (el == 0) { | |
8040 | uint64_t sctlr = arm_sctlr(env, el); | |
8041 | if (!(sctlr & SCTLR_EnRCTX)) { | |
8042 | return CP_ACCESS_TRAP; | |
8043 | } | |
8044 | } else if (el == 1) { | |
8045 | uint64_t hcr = arm_hcr_el2_eff(env); | |
8046 | if (hcr & HCR_NV) { | |
8047 | return CP_ACCESS_TRAP_EL2; | |
8048 | } | |
8049 | } | |
8050 | return CP_ACCESS_OK; | |
8051 | } | |
8052 | ||
8053 | static const ARMCPRegInfo predinv_reginfo[] = { | |
8054 | { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64, | |
8055 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4, | |
950037e2 | 8056 | .fgt = FGT_CFPRCTX, |
cb570bd3 RH |
8057 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, |
8058 | { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64, | |
8059 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5, | |
950037e2 | 8060 | .fgt = FGT_DVPRCTX, |
cb570bd3 RH |
8061 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, |
8062 | { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64, | |
8063 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7, | |
950037e2 | 8064 | .fgt = FGT_CPPRCTX, |
cb570bd3 RH |
8065 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, |
8066 | /* | |
8067 | * Note the AArch32 opcodes have a different OPC1. | |
8068 | */ | |
8069 | { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32, | |
8070 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4, | |
950037e2 | 8071 | .fgt = FGT_CFPRCTX, |
cb570bd3 RH |
8072 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, |
8073 | { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32, | |
8074 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5, | |
950037e2 | 8075 | .fgt = FGT_DVPRCTX, |
cb570bd3 RH |
8076 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, |
8077 | { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32, | |
8078 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7, | |
950037e2 | 8079 | .fgt = FGT_CPPRCTX, |
cb570bd3 | 8080 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, |
cb570bd3 RH |
8081 | }; |
8082 | ||
957e6155 PM |
8083 | static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri) |
8084 | { | |
8085 | /* Read the high 32 bits of the current CCSIDR */ | |
8086 | return extract64(ccsidr_read(env, ri), 32, 32); | |
8087 | } | |
8088 | ||
8089 | static const ARMCPRegInfo ccsidr2_reginfo[] = { | |
8090 | { .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH, | |
8091 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2, | |
8092 | .access = PL1_R, | |
e2ce5fcd | 8093 | .accessfn = access_tid4, |
957e6155 | 8094 | .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW }, |
957e6155 PM |
8095 | }; |
8096 | ||
6a4ef4e5 MZ |
8097 | static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri, |
8098 | bool isread) | |
8099 | { | |
8100 | if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) { | |
8101 | return CP_ACCESS_TRAP_EL2; | |
8102 | } | |
8103 | ||
8104 | return CP_ACCESS_OK; | |
8105 | } | |
8106 | ||
8107 | static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri, | |
8108 | bool isread) | |
8109 | { | |
8110 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
8111 | return access_aa64_tid3(env, ri, isread); | |
8112 | } | |
8113 | ||
8114 | return CP_ACCESS_OK; | |
8115 | } | |
8116 | ||
f96f3d5f MZ |
8117 | static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri, |
8118 | bool isread) | |
8119 | { | |
8120 | if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID0)) { | |
8121 | return CP_ACCESS_TRAP_EL2; | |
8122 | } | |
8123 | ||
8124 | return CP_ACCESS_OK; | |
8125 | } | |
8126 | ||
8e228c9e PM |
8127 | static CPAccessResult access_joscr_jmcr(CPUARMState *env, |
8128 | const ARMCPRegInfo *ri, bool isread) | |
8129 | { | |
8130 | /* | |
8131 | * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only | |
8132 | * in v7A, not in v8A. | |
8133 | */ | |
8134 | if (!arm_feature(env, ARM_FEATURE_V8) && | |
8135 | arm_current_el(env) < 2 && !arm_is_secure_below_el3(env) && | |
8136 | (env->cp15.hstr_el2 & HSTR_TJDBX)) { | |
8137 | return CP_ACCESS_TRAP_EL2; | |
8138 | } | |
8139 | return CP_ACCESS_OK; | |
8140 | } | |
8141 | ||
f96f3d5f MZ |
8142 | static const ARMCPRegInfo jazelle_regs[] = { |
8143 | { .name = "JIDR", | |
8144 | .cp = 14, .crn = 0, .crm = 0, .opc1 = 7, .opc2 = 0, | |
8145 | .access = PL1_R, .accessfn = access_jazelle, | |
8146 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
8147 | { .name = "JOSCR", | |
8148 | .cp = 14, .crn = 1, .crm = 0, .opc1 = 7, .opc2 = 0, | |
8e228c9e | 8149 | .accessfn = access_joscr_jmcr, |
f96f3d5f MZ |
8150 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
8151 | { .name = "JMCR", | |
8152 | .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0, | |
8e228c9e | 8153 | .accessfn = access_joscr_jmcr, |
f96f3d5f | 8154 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
f96f3d5f MZ |
8155 | }; |
8156 | ||
52d18727 RH |
8157 | static const ARMCPRegInfo contextidr_el2 = { |
8158 | .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64, | |
8159 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1, | |
8160 | .access = PL2_RW, | |
8161 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) | |
8162 | }; | |
8163 | ||
e2a1a461 | 8164 | static const ARMCPRegInfo vhe_reginfo[] = { |
ed30da8e RH |
8165 | { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, |
8166 | .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, | |
8167 | .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, | |
587f8b33 | 8168 | .raw_writefn = raw_write, |
ed30da8e | 8169 | .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) }, |
8c94b071 RH |
8170 | #ifndef CONFIG_USER_ONLY |
8171 | { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64, | |
8172 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 2, | |
8173 | .fieldoffset = | |
8174 | offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval), | |
8175 | .type = ARM_CP_IO, .access = PL2_RW, | |
8176 | .writefn = gt_hv_cval_write, .raw_writefn = raw_write }, | |
8177 | { .name = "CNTHV_TVAL_EL2", .state = ARM_CP_STATE_BOTH, | |
8178 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 0, | |
8179 | .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, | |
8180 | .resetfn = gt_hv_timer_reset, | |
8181 | .readfn = gt_hv_tval_read, .writefn = gt_hv_tval_write }, | |
8182 | { .name = "CNTHV_CTL_EL2", .state = ARM_CP_STATE_BOTH, | |
8183 | .type = ARM_CP_IO, | |
8184 | .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 1, | |
8185 | .access = PL2_RW, | |
8186 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].ctl), | |
8187 | .writefn = gt_hv_ctl_write, .raw_writefn = raw_write }, | |
bb5972e4 RH |
8188 | { .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64, |
8189 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1, | |
8190 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
8191 | .access = PL2_RW, .accessfn = e2h_access, | |
8192 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl), | |
8193 | .writefn = gt_phys_ctl_write, .raw_writefn = raw_write }, | |
8194 | { .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64, | |
8195 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1, | |
8196 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
8197 | .access = PL2_RW, .accessfn = e2h_access, | |
8198 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl), | |
8199 | .writefn = gt_virt_ctl_write, .raw_writefn = raw_write }, | |
8200 | { .name = "CNTP_TVAL_EL02", .state = ARM_CP_STATE_AA64, | |
8201 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 0, | |
8202 | .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, | |
8203 | .access = PL2_RW, .accessfn = e2h_access, | |
8204 | .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write }, | |
8205 | { .name = "CNTV_TVAL_EL02", .state = ARM_CP_STATE_AA64, | |
8206 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 0, | |
8207 | .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, | |
8208 | .access = PL2_RW, .accessfn = e2h_access, | |
8209 | .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write }, | |
8210 | { .name = "CNTP_CVAL_EL02", .state = ARM_CP_STATE_AA64, | |
8211 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 2, | |
8212 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
8213 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), | |
8214 | .access = PL2_RW, .accessfn = e2h_access, | |
8215 | .writefn = gt_phys_cval_write, .raw_writefn = raw_write }, | |
8216 | { .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64, | |
8217 | .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2, | |
8218 | .type = ARM_CP_IO | ARM_CP_ALIAS, | |
8219 | .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), | |
8220 | .access = PL2_RW, .accessfn = e2h_access, | |
8221 | .writefn = gt_virt_cval_write, .raw_writefn = raw_write }, | |
8c94b071 | 8222 | #endif |
e2a1a461 RH |
8223 | }; |
8224 | ||
04b07d29 RH |
8225 | #ifndef CONFIG_USER_ONLY |
8226 | static const ARMCPRegInfo ats1e1_reginfo[] = { | |
3999d2d2 | 8227 | { .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64, |
04b07d29 RH |
8228 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, |
8229 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
132c98cd | 8230 | .fgt = FGT_ATS1E1RP, |
57259779 | 8231 | .accessfn = at_s1e01_access, .writefn = ats_write64 }, |
3999d2d2 | 8232 | { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64, |
04b07d29 RH |
8233 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, |
8234 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
132c98cd | 8235 | .fgt = FGT_ATS1E1WP, |
57259779 | 8236 | .accessfn = at_s1e01_access, .writefn = ats_write64 }, |
04b07d29 RH |
8237 | }; |
8238 | ||
8239 | static const ARMCPRegInfo ats1cp_reginfo[] = { | |
8240 | { .name = "ATS1CPRP", | |
8241 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, | |
8242 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
8243 | .writefn = ats_write }, | |
8244 | { .name = "ATS1CPWP", | |
8245 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, | |
8246 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | |
8247 | .writefn = ats_write }, | |
04b07d29 RH |
8248 | }; |
8249 | #endif | |
8250 | ||
f6287c24 PM |
8251 | /* |
8252 | * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and | |
8253 | * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field | |
8254 | * is non-zero, which is never for ARMv7, optionally in ARMv8 | |
8255 | * and mandatorily for ARMv8.2 and up. | |
8256 | * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's | |
8257 | * implementation is RAZ/WI we can ignore this detail, as we | |
8258 | * do for ACTLR. | |
8259 | */ | |
8260 | static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = { | |
8261 | { .name = "ACTLR2", .state = ARM_CP_STATE_AA32, | |
8262 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 3, | |
99602377 RH |
8263 | .access = PL1_RW, .accessfn = access_tacr, |
8264 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
f6287c24 PM |
8265 | { .name = "HACTLR2", .state = ARM_CP_STATE_AA32, |
8266 | .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3, | |
8267 | .access = PL2_RW, .type = ARM_CP_CONST, | |
8268 | .resetvalue = 0 }, | |
f6287c24 PM |
8269 | }; |
8270 | ||
2ceb98c0 PM |
8271 | void register_cp_regs_for_features(ARMCPU *cpu) |
8272 | { | |
8273 | /* Register all the coprocessor registers based on feature bits */ | |
8274 | CPUARMState *env = &cpu->env; | |
8275 | if (arm_feature(env, ARM_FEATURE_M)) { | |
8276 | /* M profile has no coprocessor registers */ | |
8277 | return; | |
8278 | } | |
8279 | ||
e9aa6c21 | 8280 | define_arm_cp_regs(cpu, cp_reginfo); |
9449fdf6 | 8281 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
9b37a28c FR |
8282 | /* |
8283 | * Must go early as it is full of wildcards that may be | |
9449fdf6 PM |
8284 | * overridden by later definitions. |
8285 | */ | |
8286 | define_arm_cp_regs(cpu, not_v8_cp_reginfo); | |
8287 | } | |
8288 | ||
7d57f408 | 8289 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8515a092 PM |
8290 | /* The ID registers all have impdef reset values */ |
8291 | ARMCPRegInfo v6_idregs[] = { | |
0ff644a7 PM |
8292 | { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, |
8293 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
8294 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8295 | .accessfn = access_aa32_tid3, |
8a130a7b | 8296 | .resetvalue = cpu->isar.id_pfr0 }, |
9b37a28c FR |
8297 | /* |
8298 | * ID_PFR1 is not a plain ARM_CP_CONST because we don't know | |
96a8b92e PM |
8299 | * the value of the GIC field until after we define these regs. |
8300 | */ | |
0ff644a7 PM |
8301 | { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, |
8302 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | |
96a8b92e | 8303 | .access = PL1_R, .type = ARM_CP_NO_RAW, |
6a4ef4e5 | 8304 | .accessfn = access_aa32_tid3, |
0f150c84 PMD |
8305 | #ifdef CONFIG_USER_ONLY |
8306 | .type = ARM_CP_CONST, | |
8307 | .resetvalue = cpu->isar.id_pfr1, | |
8308 | #else | |
8309 | .type = ARM_CP_NO_RAW, | |
8310 | .accessfn = access_aa32_tid3, | |
96a8b92e | 8311 | .readfn = id_pfr1_read, |
0f150c84 PMD |
8312 | .writefn = arm_cp_write_ignore |
8313 | #endif | |
8314 | }, | |
0ff644a7 PM |
8315 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, |
8316 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | |
8317 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8318 | .accessfn = access_aa32_tid3, |
a6179538 | 8319 | .resetvalue = cpu->isar.id_dfr0 }, |
0ff644a7 PM |
8320 | { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, |
8321 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, | |
8322 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8323 | .accessfn = access_aa32_tid3, |
8515a092 | 8324 | .resetvalue = cpu->id_afr0 }, |
0ff644a7 PM |
8325 | { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, |
8326 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, | |
8327 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8328 | .accessfn = access_aa32_tid3, |
10054016 | 8329 | .resetvalue = cpu->isar.id_mmfr0 }, |
0ff644a7 PM |
8330 | { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, |
8331 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, | |
8332 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8333 | .accessfn = access_aa32_tid3, |
10054016 | 8334 | .resetvalue = cpu->isar.id_mmfr1 }, |
0ff644a7 PM |
8335 | { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, |
8336 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, | |
8337 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8338 | .accessfn = access_aa32_tid3, |
10054016 | 8339 | .resetvalue = cpu->isar.id_mmfr2 }, |
0ff644a7 PM |
8340 | { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, |
8341 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, | |
8342 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8343 | .accessfn = access_aa32_tid3, |
10054016 | 8344 | .resetvalue = cpu->isar.id_mmfr3 }, |
0ff644a7 PM |
8345 | { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, |
8346 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | |
8347 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8348 | .accessfn = access_aa32_tid3, |
47576b94 | 8349 | .resetvalue = cpu->isar.id_isar0 }, |
0ff644a7 PM |
8350 | { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, |
8351 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, | |
8352 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8353 | .accessfn = access_aa32_tid3, |
47576b94 | 8354 | .resetvalue = cpu->isar.id_isar1 }, |
0ff644a7 PM |
8355 | { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, |
8356 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | |
8357 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8358 | .accessfn = access_aa32_tid3, |
47576b94 | 8359 | .resetvalue = cpu->isar.id_isar2 }, |
0ff644a7 PM |
8360 | { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, |
8361 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, | |
8362 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8363 | .accessfn = access_aa32_tid3, |
47576b94 | 8364 | .resetvalue = cpu->isar.id_isar3 }, |
0ff644a7 PM |
8365 | { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, |
8366 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, | |
8367 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8368 | .accessfn = access_aa32_tid3, |
47576b94 | 8369 | .resetvalue = cpu->isar.id_isar4 }, |
0ff644a7 PM |
8370 | { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, |
8371 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, | |
8372 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8373 | .accessfn = access_aa32_tid3, |
47576b94 | 8374 | .resetvalue = cpu->isar.id_isar5 }, |
e20d84c1 PM |
8375 | { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, |
8376 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, | |
8377 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8378 | .accessfn = access_aa32_tid3, |
10054016 | 8379 | .resetvalue = cpu->isar.id_mmfr4 }, |
802abf40 | 8380 | { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
8381 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, |
8382 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8383 | .accessfn = access_aa32_tid3, |
47576b94 | 8384 | .resetvalue = cpu->isar.id_isar6 }, |
8515a092 PM |
8385 | }; |
8386 | define_arm_cp_regs(cpu, v6_idregs); | |
7d57f408 PM |
8387 | define_arm_cp_regs(cpu, v6_cp_reginfo); |
8388 | } else { | |
8389 | define_arm_cp_regs(cpu, not_v6_cp_reginfo); | |
8390 | } | |
4d31c596 PM |
8391 | if (arm_feature(env, ARM_FEATURE_V6K)) { |
8392 | define_arm_cp_regs(cpu, v6k_cp_reginfo); | |
8393 | } | |
5e5cf9e3 | 8394 | if (arm_feature(env, ARM_FEATURE_V7MP) && |
452a0955 | 8395 | !arm_feature(env, ARM_FEATURE_PMSA)) { |
995939a6 PM |
8396 | define_arm_cp_regs(cpu, v7mp_cp_reginfo); |
8397 | } | |
327dd510 AL |
8398 | if (arm_feature(env, ARM_FEATURE_V7VE)) { |
8399 | define_arm_cp_regs(cpu, pmovsset_cp_reginfo); | |
8400 | } | |
e9aa6c21 | 8401 | if (arm_feature(env, ARM_FEATURE_V7)) { |
776d4e5c | 8402 | ARMCPRegInfo clidr = { |
7da845b0 PM |
8403 | .name = "CLIDR", .state = ARM_CP_STATE_BOTH, |
8404 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | |
630fcd4d | 8405 | .access = PL1_R, .type = ARM_CP_CONST, |
e2ce5fcd | 8406 | .accessfn = access_tid4, |
158c276c | 8407 | .fgt = FGT_CLIDR_EL1, |
630fcd4d | 8408 | .resetvalue = cpu->clidr |
776d4e5c | 8409 | }; |
776d4e5c | 8410 | define_one_arm_cp_reg(cpu, &clidr); |
e9aa6c21 | 8411 | define_arm_cp_regs(cpu, v7_cp_reginfo); |
50300698 | 8412 | define_debug_regs(cpu); |
24183fb6 | 8413 | define_pmu_regs(cpu); |
7d57f408 PM |
8414 | } else { |
8415 | define_arm_cp_regs(cpu, not_v7_cp_reginfo); | |
e9aa6c21 | 8416 | } |
b0d2b7d0 | 8417 | if (arm_feature(env, ARM_FEATURE_V8)) { |
dde4d028 PM |
8418 | /* |
8419 | * v8 ID registers, which all have impdef reset values. | |
e20d84c1 PM |
8420 | * Note that within the ID register ranges the unused slots |
8421 | * must all RAZ, not UNDEF; future architecture versions may | |
8422 | * define new registers here. | |
dde4d028 PM |
8423 | * ID registers which are AArch64 views of the AArch32 ID registers |
8424 | * which already existed in v6 and v7 are handled elsewhere, | |
8425 | * in v6_idregs[]. | |
e20d84c1 | 8426 | */ |
dde4d028 | 8427 | int i; |
e60cef86 | 8428 | ARMCPRegInfo v8_idregs[] = { |
976b99b6 AB |
8429 | /* |
8430 | * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system | |
8431 | * emulation because we don't know the right value for the | |
8432 | * GIC field until after we define these regs. | |
96a8b92e | 8433 | */ |
e60cef86 PM |
8434 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, |
8435 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | |
976b99b6 AB |
8436 | .access = PL1_R, |
8437 | #ifdef CONFIG_USER_ONLY | |
8438 | .type = ARM_CP_CONST, | |
8439 | .resetvalue = cpu->isar.id_aa64pfr0 | |
8440 | #else | |
8441 | .type = ARM_CP_NO_RAW, | |
6a4ef4e5 | 8442 | .accessfn = access_aa64_tid3, |
96a8b92e | 8443 | .readfn = id_aa64pfr0_read, |
976b99b6 AB |
8444 | .writefn = arm_cp_write_ignore |
8445 | #endif | |
8446 | }, | |
e60cef86 PM |
8447 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, |
8448 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | |
8449 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8450 | .accessfn = access_aa64_tid3, |
47576b94 | 8451 | .resetvalue = cpu->isar.id_aa64pfr1}, |
e20d84c1 PM |
8452 | { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
8453 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, | |
8454 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8455 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8456 | .resetvalue = 0 }, |
8457 | { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8458 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, | |
8459 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8460 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8461 | .resetvalue = 0 }, |
9516d772 | 8462 | { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
8463 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, |
8464 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8465 | .accessfn = access_aa64_tid3, |
2dc10fa2 | 8466 | .resetvalue = cpu->isar.id_aa64zfr0 }, |
414c54d5 | 8467 | { .name = "ID_AA64SMFR0_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
8468 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, |
8469 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8470 | .accessfn = access_aa64_tid3, |
414c54d5 | 8471 | .resetvalue = cpu->isar.id_aa64smfr0 }, |
e20d84c1 PM |
8472 | { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
8473 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, | |
8474 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8475 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8476 | .resetvalue = 0 }, |
8477 | { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8478 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, | |
8479 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8480 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8481 | .resetvalue = 0 }, |
e60cef86 PM |
8482 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, |
8483 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | |
8484 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8485 | .accessfn = access_aa64_tid3, |
2a609df8 | 8486 | .resetvalue = cpu->isar.id_aa64dfr0 }, |
e60cef86 PM |
8487 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, |
8488 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | |
8489 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8490 | .accessfn = access_aa64_tid3, |
2a609df8 | 8491 | .resetvalue = cpu->isar.id_aa64dfr1 }, |
e20d84c1 PM |
8492 | { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
8493 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, | |
8494 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8495 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8496 | .resetvalue = 0 }, |
8497 | { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8498 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, | |
8499 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8500 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8501 | .resetvalue = 0 }, |
e60cef86 PM |
8502 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, |
8503 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | |
8504 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8505 | .accessfn = access_aa64_tid3, |
e60cef86 PM |
8506 | .resetvalue = cpu->id_aa64afr0 }, |
8507 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | |
8508 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | |
8509 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8510 | .accessfn = access_aa64_tid3, |
e60cef86 | 8511 | .resetvalue = cpu->id_aa64afr1 }, |
e20d84c1 PM |
8512 | { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
8513 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, | |
8514 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8515 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8516 | .resetvalue = 0 }, |
8517 | { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8518 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, | |
8519 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8520 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8521 | .resetvalue = 0 }, |
e60cef86 PM |
8522 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, |
8523 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | |
8524 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8525 | .accessfn = access_aa64_tid3, |
47576b94 | 8526 | .resetvalue = cpu->isar.id_aa64isar0 }, |
e60cef86 PM |
8527 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, |
8528 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | |
8529 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8530 | .accessfn = access_aa64_tid3, |
47576b94 | 8531 | .resetvalue = cpu->isar.id_aa64isar1 }, |
a969fe97 | 8532 | { .name = "ID_AA64ISAR2_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
8533 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, |
8534 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8535 | .accessfn = access_aa64_tid3, |
a969fe97 | 8536 | .resetvalue = cpu->isar.id_aa64isar2 }, |
e20d84c1 PM |
8537 | { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
8538 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, | |
8539 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8540 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8541 | .resetvalue = 0 }, |
8542 | { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8543 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, | |
8544 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8545 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8546 | .resetvalue = 0 }, |
8547 | { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8548 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, | |
8549 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8550 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8551 | .resetvalue = 0 }, |
8552 | { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8553 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, | |
8554 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8555 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8556 | .resetvalue = 0 }, |
8557 | { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8558 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, | |
8559 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8560 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8561 | .resetvalue = 0 }, |
e60cef86 PM |
8562 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, |
8563 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | |
8564 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8565 | .accessfn = access_aa64_tid3, |
3dc91ddb | 8566 | .resetvalue = cpu->isar.id_aa64mmfr0 }, |
e60cef86 PM |
8567 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, |
8568 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | |
8569 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8570 | .accessfn = access_aa64_tid3, |
3dc91ddb | 8571 | .resetvalue = cpu->isar.id_aa64mmfr1 }, |
64761e10 | 8572 | { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64, |
e20d84c1 PM |
8573 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, |
8574 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8575 | .accessfn = access_aa64_tid3, |
64761e10 | 8576 | .resetvalue = cpu->isar.id_aa64mmfr2 }, |
e20d84c1 PM |
8577 | { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, |
8578 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, | |
8579 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8580 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8581 | .resetvalue = 0 }, |
8582 | { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8583 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, | |
8584 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8585 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8586 | .resetvalue = 0 }, |
8587 | { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8588 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, | |
8589 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8590 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8591 | .resetvalue = 0 }, |
8592 | { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8593 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, | |
8594 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8595 | .accessfn = access_aa64_tid3, |
e20d84c1 PM |
8596 | .resetvalue = 0 }, |
8597 | { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | |
8598 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, | |
8599 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8600 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8601 | .resetvalue = 0 }, |
a50c0f51 PM |
8602 | { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, |
8603 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
8604 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8605 | .accessfn = access_aa64_tid3, |
47576b94 | 8606 | .resetvalue = cpu->isar.mvfr0 }, |
a50c0f51 PM |
8607 | { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, |
8608 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
8609 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8610 | .accessfn = access_aa64_tid3, |
47576b94 | 8611 | .resetvalue = cpu->isar.mvfr1 }, |
a50c0f51 PM |
8612 | { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, |
8613 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
8614 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8615 | .accessfn = access_aa64_tid3, |
47576b94 | 8616 | .resetvalue = cpu->isar.mvfr2 }, |
dde4d028 PM |
8617 | /* |
8618 | * "0, c0, c3, {0,1,2}" are the encodings corresponding to | |
8619 | * AArch64 MVFR[012]_EL1. Define the STATE_AA32 encoding | |
8620 | * as RAZ, since it is in the "reserved for future ID | |
8621 | * registers, RAZ" part of the AArch32 encoding space. | |
8622 | */ | |
8623 | { .name = "RES_0_C0_C3_0", .state = ARM_CP_STATE_AA32, | |
8624 | .cp = 15, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | |
8625 | .access = PL1_R, .type = ARM_CP_CONST, | |
8626 | .accessfn = access_aa64_tid3, | |
8627 | .resetvalue = 0 }, | |
8628 | { .name = "RES_0_C0_C3_1", .state = ARM_CP_STATE_AA32, | |
8629 | .cp = 15, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | |
8630 | .access = PL1_R, .type = ARM_CP_CONST, | |
8631 | .accessfn = access_aa64_tid3, | |
8632 | .resetvalue = 0 }, | |
8633 | { .name = "RES_0_C0_C3_2", .state = ARM_CP_STATE_AA32, | |
8634 | .cp = 15, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | |
8635 | .access = PL1_R, .type = ARM_CP_CONST, | |
8636 | .accessfn = access_aa64_tid3, | |
8637 | .resetvalue = 0 }, | |
8638 | /* | |
8639 | * Other encodings in "0, c0, c3, ..." are STATE_BOTH because | |
8640 | * they're also RAZ for AArch64, and in v8 are gradually | |
8641 | * being filled with AArch64-view-of-AArch32-ID-register | |
8642 | * for new ID registers. | |
8643 | */ | |
8644 | { .name = "RES_0_C0_C3_3", .state = ARM_CP_STATE_BOTH, | |
e20d84c1 PM |
8645 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, |
8646 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8647 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8648 | .resetvalue = 0 }, |
1d51bc96 | 8649 | { .name = "ID_PFR2", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
8650 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, |
8651 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8652 | .accessfn = access_aa64_tid3, |
1d51bc96 | 8653 | .resetvalue = cpu->isar.id_pfr2 }, |
d22c5649 | 8654 | { .name = "ID_DFR1", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
8655 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, |
8656 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8657 | .accessfn = access_aa64_tid3, |
d22c5649 | 8658 | .resetvalue = cpu->isar.id_dfr1 }, |
32957aad | 8659 | { .name = "ID_MMFR5", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
8660 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, |
8661 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8662 | .accessfn = access_aa64_tid3, |
32957aad | 8663 | .resetvalue = cpu->isar.id_mmfr5 }, |
dde4d028 | 8664 | { .name = "RES_0_C0_C3_7", .state = ARM_CP_STATE_BOTH, |
e20d84c1 PM |
8665 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, |
8666 | .access = PL1_R, .type = ARM_CP_CONST, | |
6a4ef4e5 | 8667 | .accessfn = access_aa64_tid3, |
e20d84c1 | 8668 | .resetvalue = 0 }, |
4054bfa9 AF |
8669 | { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, |
8670 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, | |
8671 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 8672 | .fgt = FGT_PMCEIDN_EL0, |
cad86737 | 8673 | .resetvalue = extract64(cpu->pmceid0, 0, 32) }, |
4054bfa9 AF |
8674 | { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, |
8675 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, | |
8676 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 8677 | .fgt = FGT_PMCEIDN_EL0, |
4054bfa9 AF |
8678 | .resetvalue = cpu->pmceid0 }, |
8679 | { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, | |
8680 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, | |
8681 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 8682 | .fgt = FGT_PMCEIDN_EL0, |
cad86737 | 8683 | .resetvalue = extract64(cpu->pmceid1, 0, 32) }, |
4054bfa9 AF |
8684 | { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, |
8685 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, | |
8686 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | |
dc780233 | 8687 | .fgt = FGT_PMCEIDN_EL0, |
4054bfa9 | 8688 | .resetvalue = cpu->pmceid1 }, |
e60cef86 | 8689 | }; |
6c5c0fec | 8690 | #ifdef CONFIG_USER_ONLY |
10b0220e | 8691 | static const ARMCPRegUserSpaceInfo v8_user_idregs[] = { |
6c5c0fec | 8692 | { .name = "ID_AA64PFR0_EL1", |
bc6bd20e ZS |
8693 | .exported_bits = R_ID_AA64PFR0_FP_MASK | |
8694 | R_ID_AA64PFR0_ADVSIMD_MASK | | |
8695 | R_ID_AA64PFR0_SVE_MASK | | |
8696 | R_ID_AA64PFR0_DIT_MASK, | |
8697 | .fixed_bits = (0x1u << R_ID_AA64PFR0_EL0_SHIFT) | | |
8698 | (0x1u << R_ID_AA64PFR0_EL1_SHIFT) }, | |
6c5c0fec | 8699 | { .name = "ID_AA64PFR1_EL1", |
bc6bd20e ZS |
8700 | .exported_bits = R_ID_AA64PFR1_BT_MASK | |
8701 | R_ID_AA64PFR1_SSBS_MASK | | |
8702 | R_ID_AA64PFR1_MTE_MASK | | |
8703 | R_ID_AA64PFR1_SME_MASK }, | |
d040242e | 8704 | { .name = "ID_AA64PFR*_EL1_RESERVED", |
bc6bd20e ZS |
8705 | .is_glob = true }, |
8706 | { .name = "ID_AA64ZFR0_EL1", | |
8707 | .exported_bits = R_ID_AA64ZFR0_SVEVER_MASK | | |
8708 | R_ID_AA64ZFR0_AES_MASK | | |
8709 | R_ID_AA64ZFR0_BITPERM_MASK | | |
8710 | R_ID_AA64ZFR0_BFLOAT16_MASK | | |
8711 | R_ID_AA64ZFR0_SHA3_MASK | | |
8712 | R_ID_AA64ZFR0_SM4_MASK | | |
8713 | R_ID_AA64ZFR0_I8MM_MASK | | |
8714 | R_ID_AA64ZFR0_F32MM_MASK | | |
8715 | R_ID_AA64ZFR0_F64MM_MASK }, | |
8716 | { .name = "ID_AA64SMFR0_EL1", | |
8717 | .exported_bits = R_ID_AA64SMFR0_F32F32_MASK | | |
5f7b71fb | 8718 | R_ID_AA64SMFR0_BI32I32_MASK | |
bc6bd20e ZS |
8719 | R_ID_AA64SMFR0_B16F32_MASK | |
8720 | R_ID_AA64SMFR0_F16F32_MASK | | |
8721 | R_ID_AA64SMFR0_I8I32_MASK | | |
5f7b71fb PM |
8722 | R_ID_AA64SMFR0_F16F16_MASK | |
8723 | R_ID_AA64SMFR0_B16B16_MASK | | |
8724 | R_ID_AA64SMFR0_I16I32_MASK | | |
bc6bd20e ZS |
8725 | R_ID_AA64SMFR0_F64F64_MASK | |
8726 | R_ID_AA64SMFR0_I16I64_MASK | | |
5f7b71fb | 8727 | R_ID_AA64SMFR0_SMEVER_MASK | |
bc6bd20e | 8728 | R_ID_AA64SMFR0_FA64_MASK }, |
6c5c0fec | 8729 | { .name = "ID_AA64MMFR0_EL1", |
bc6bd20e ZS |
8730 | .exported_bits = R_ID_AA64MMFR0_ECV_MASK, |
8731 | .fixed_bits = (0xfu << R_ID_AA64MMFR0_TGRAN64_SHIFT) | | |
8732 | (0xfu << R_ID_AA64MMFR0_TGRAN4_SHIFT) }, | |
8733 | { .name = "ID_AA64MMFR1_EL1", | |
8734 | .exported_bits = R_ID_AA64MMFR1_AFP_MASK }, | |
8735 | { .name = "ID_AA64MMFR2_EL1", | |
8736 | .exported_bits = R_ID_AA64MMFR2_AT_MASK }, | |
d040242e | 8737 | { .name = "ID_AA64MMFR*_EL1_RESERVED", |
bc6bd20e | 8738 | .is_glob = true }, |
6c5c0fec | 8739 | { .name = "ID_AA64DFR0_EL1", |
bc6bd20e ZS |
8740 | .fixed_bits = (0x6u << R_ID_AA64DFR0_DEBUGVER_SHIFT) }, |
8741 | { .name = "ID_AA64DFR1_EL1" }, | |
d040242e | 8742 | { .name = "ID_AA64DFR*_EL1_RESERVED", |
bc6bd20e | 8743 | .is_glob = true }, |
d040242e | 8744 | { .name = "ID_AA64AFR*", |
bc6bd20e | 8745 | .is_glob = true }, |
6c5c0fec | 8746 | { .name = "ID_AA64ISAR0_EL1", |
bc6bd20e ZS |
8747 | .exported_bits = R_ID_AA64ISAR0_AES_MASK | |
8748 | R_ID_AA64ISAR0_SHA1_MASK | | |
8749 | R_ID_AA64ISAR0_SHA2_MASK | | |
8750 | R_ID_AA64ISAR0_CRC32_MASK | | |
8751 | R_ID_AA64ISAR0_ATOMIC_MASK | | |
8752 | R_ID_AA64ISAR0_RDM_MASK | | |
8753 | R_ID_AA64ISAR0_SHA3_MASK | | |
8754 | R_ID_AA64ISAR0_SM3_MASK | | |
8755 | R_ID_AA64ISAR0_SM4_MASK | | |
8756 | R_ID_AA64ISAR0_DP_MASK | | |
8757 | R_ID_AA64ISAR0_FHM_MASK | | |
8758 | R_ID_AA64ISAR0_TS_MASK | | |
8759 | R_ID_AA64ISAR0_RNDR_MASK }, | |
6c5c0fec | 8760 | { .name = "ID_AA64ISAR1_EL1", |
bc6bd20e ZS |
8761 | .exported_bits = R_ID_AA64ISAR1_DPB_MASK | |
8762 | R_ID_AA64ISAR1_APA_MASK | | |
8763 | R_ID_AA64ISAR1_API_MASK | | |
8764 | R_ID_AA64ISAR1_JSCVT_MASK | | |
8765 | R_ID_AA64ISAR1_FCMA_MASK | | |
8766 | R_ID_AA64ISAR1_LRCPC_MASK | | |
8767 | R_ID_AA64ISAR1_GPA_MASK | | |
8768 | R_ID_AA64ISAR1_GPI_MASK | | |
8769 | R_ID_AA64ISAR1_FRINTTS_MASK | | |
8770 | R_ID_AA64ISAR1_SB_MASK | | |
8771 | R_ID_AA64ISAR1_BF16_MASK | | |
8772 | R_ID_AA64ISAR1_DGH_MASK | | |
8773 | R_ID_AA64ISAR1_I8MM_MASK }, | |
8774 | { .name = "ID_AA64ISAR2_EL1", | |
8775 | .exported_bits = R_ID_AA64ISAR2_WFXT_MASK | | |
8776 | R_ID_AA64ISAR2_RPRES_MASK | | |
8777 | R_ID_AA64ISAR2_GPA3_MASK | | |
5f7b71fb PM |
8778 | R_ID_AA64ISAR2_APA3_MASK | |
8779 | R_ID_AA64ISAR2_MOPS_MASK | | |
8780 | R_ID_AA64ISAR2_BC_MASK | | |
8781 | R_ID_AA64ISAR2_RPRFM_MASK | | |
8782 | R_ID_AA64ISAR2_CSSC_MASK }, | |
d040242e | 8783 | { .name = "ID_AA64ISAR*_EL1_RESERVED", |
bc6bd20e | 8784 | .is_glob = true }, |
6c5c0fec AB |
8785 | }; |
8786 | modify_arm_cp_regs(v8_idregs, v8_user_idregs); | |
8787 | #endif | |
97198a7d RH |
8788 | /* |
8789 | * RVBAR_EL1 and RMR_EL1 only implemented if EL1 is the highest EL. | |
8790 | * TODO: For RMR, a write with bit 1 set should do something with | |
8791 | * cpu_reset(). In the meantime, "the bit is strictly a request", | |
8792 | * so we are in spec just ignoring writes. | |
8793 | */ | |
be8e8128 GB |
8794 | if (!arm_feature(env, ARM_FEATURE_EL3) && |
8795 | !arm_feature(env, ARM_FEATURE_EL2)) { | |
97198a7d RH |
8796 | ARMCPRegInfo el1_reset_regs[] = { |
8797 | { .name = "RVBAR_EL1", .state = ARM_CP_STATE_BOTH, | |
8798 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, | |
8799 | .access = PL1_R, | |
8800 | .fieldoffset = offsetof(CPUARMState, cp15.rvbar) }, | |
8801 | { .name = "RMR_EL1", .state = ARM_CP_STATE_BOTH, | |
8802 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2, | |
8803 | .access = PL1_RW, .type = ARM_CP_CONST, | |
8804 | .resetvalue = arm_feature(env, ARM_FEATURE_AARCH64) } | |
be8e8128 | 8805 | }; |
97198a7d | 8806 | define_arm_cp_regs(cpu, el1_reset_regs); |
be8e8128 | 8807 | } |
e60cef86 | 8808 | define_arm_cp_regs(cpu, v8_idregs); |
b0d2b7d0 | 8809 | define_arm_cp_regs(cpu, v8_cp_reginfo); |
c36a0d57 PM |
8810 | if (cpu_isar_feature(aa64_aa32_el1, cpu)) { |
8811 | define_arm_cp_regs(cpu, v8_aa32_el1_reginfo); | |
8812 | } | |
dde4d028 PM |
8813 | |
8814 | for (i = 4; i < 16; i++) { | |
8815 | /* | |
8816 | * Encodings in "0, c0, {c4-c7}, {0-7}" are RAZ for AArch32. | |
8817 | * For pre-v8 cores there are RAZ patterns for these in | |
8818 | * id_pre_v8_midr_cp_reginfo[]; for v8 we do that here. | |
8819 | * v8 extends the "must RAZ" part of the ID register space | |
8820 | * to also cover c0, 0, c{8-15}, {0-7}. | |
8821 | * These are STATE_AA32 because in the AArch64 sysreg space | |
8822 | * c4-c7 is where the AArch64 ID registers live (and we've | |
8823 | * already defined those in v8_idregs[]), and c8-c15 are not | |
8824 | * "must RAZ" for AArch64. | |
8825 | */ | |
8826 | g_autofree char *name = g_strdup_printf("RES_0_C0_C%d_X", i); | |
8827 | ARMCPRegInfo v8_aa32_raz_idregs = { | |
8828 | .name = name, | |
8829 | .state = ARM_CP_STATE_AA32, | |
8830 | .cp = 15, .opc1 = 0, .crn = 0, .crm = i, .opc2 = CP_ANY, | |
8831 | .access = PL1_R, .type = ARM_CP_CONST, | |
8832 | .accessfn = access_aa64_tid3, | |
8833 | .resetvalue = 0 }; | |
8834 | define_one_arm_cp_reg(cpu, &v8_aa32_raz_idregs); | |
8835 | } | |
b0d2b7d0 | 8836 | } |
99a90811 RH |
8837 | |
8838 | /* | |
8839 | * Register the base EL2 cpregs. | |
8840 | * Pre v8, these registers are implemented only as part of the | |
8841 | * Virtualization Extensions (EL2 present). Beginning with v8, | |
8842 | * if EL2 is missing but EL3 is enabled, mostly these become | |
8843 | * RES0 from EL3, with some specific exceptions. | |
8844 | */ | |
8845 | if (arm_feature(env, ARM_FEATURE_EL2) | |
8846 | || (arm_feature(env, ARM_FEATURE_EL3) | |
8847 | && arm_feature(env, ARM_FEATURE_V8))) { | |
f0d574d6 | 8848 | uint64_t vmpidr_def = mpidr_read_val(env); |
731de9e6 EI |
8849 | ARMCPRegInfo vpidr_regs[] = { |
8850 | { .name = "VPIDR", .state = ARM_CP_STATE_AA32, | |
8851 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
8852 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
696ba377 RH |
8853 | .resetvalue = cpu->midr, |
8854 | .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, | |
36476562 | 8855 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) }, |
731de9e6 EI |
8856 | { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64, |
8857 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0, | |
8858 | .access = PL2_RW, .resetvalue = cpu->midr, | |
696ba377 | 8859 | .type = ARM_CP_EL3_NO_EL2_C_NZ, |
731de9e6 | 8860 | .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) }, |
f0d574d6 EI |
8861 | { .name = "VMPIDR", .state = ARM_CP_STATE_AA32, |
8862 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
8863 | .access = PL2_RW, .accessfn = access_el3_aa32ns, | |
696ba377 RH |
8864 | .resetvalue = vmpidr_def, |
8865 | .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, | |
36476562 | 8866 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) }, |
f0d574d6 EI |
8867 | { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64, |
8868 | .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5, | |
696ba377 RH |
8869 | .access = PL2_RW, .resetvalue = vmpidr_def, |
8870 | .type = ARM_CP_EL3_NO_EL2_C_NZ, | |
f0d574d6 | 8871 | .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) }, |
731de9e6 | 8872 | }; |
24526bb9 PM |
8873 | /* |
8874 | * The only field of MDCR_EL2 that has a defined architectural reset | |
8875 | * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N. | |
8876 | */ | |
8877 | ARMCPRegInfo mdcr_el2 = { | |
7f4fbfb5 | 8878 | .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, .type = ARM_CP_IO, |
24526bb9 | 8879 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, |
01765386 | 8880 | .writefn = mdcr_el2_write, |
24526bb9 PM |
8881 | .access = PL2_RW, .resetvalue = pmu_num_counters(env), |
8882 | .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), | |
8883 | }; | |
8884 | define_one_arm_cp_reg(cpu, &mdcr_el2); | |
731de9e6 | 8885 | define_arm_cp_regs(cpu, vpidr_regs); |
4771cd01 | 8886 | define_arm_cp_regs(cpu, el2_cp_reginfo); |
ce4afed8 PM |
8887 | if (arm_feature(env, ARM_FEATURE_V8)) { |
8888 | define_arm_cp_regs(cpu, el2_v8_cp_reginfo); | |
8889 | } | |
e9152ee9 RDC |
8890 | if (cpu_isar_feature(aa64_sel2, cpu)) { |
8891 | define_arm_cp_regs(cpu, el2_sec_cp_reginfo); | |
8892 | } | |
97198a7d RH |
8893 | /* |
8894 | * RVBAR_EL2 and RMR_EL2 only implemented if EL2 is the highest EL. | |
8895 | * See commentary near RMR_EL1. | |
8896 | */ | |
be8e8128 | 8897 | if (!arm_feature(env, ARM_FEATURE_EL3)) { |
97198a7d RH |
8898 | static const ARMCPRegInfo el2_reset_regs[] = { |
8899 | { .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, | |
8900 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, | |
8901 | .access = PL2_R, | |
8902 | .fieldoffset = offsetof(CPUARMState, cp15.rvbar) }, | |
8903 | { .name = "RVBAR", .type = ARM_CP_ALIAS, | |
8904 | .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, | |
8905 | .access = PL2_R, | |
8906 | .fieldoffset = offsetof(CPUARMState, cp15.rvbar) }, | |
8907 | { .name = "RMR_EL2", .state = ARM_CP_STATE_AA64, | |
8908 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 2, | |
8909 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 1 }, | |
be8e8128 | 8910 | }; |
97198a7d | 8911 | define_arm_cp_regs(cpu, el2_reset_regs); |
be8e8128 | 8912 | } |
3b685ba7 | 8913 | } |
99a90811 RH |
8914 | |
8915 | /* Register the base EL3 cpregs. */ | |
81547d66 | 8916 | if (arm_feature(env, ARM_FEATURE_EL3)) { |
0f1a3b24 | 8917 | define_arm_cp_regs(cpu, el3_cp_reginfo); |
e24fdd23 PM |
8918 | ARMCPRegInfo el3_regs[] = { |
8919 | { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, | |
8920 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, | |
4a7319b7 | 8921 | .access = PL3_R, |
97198a7d RH |
8922 | .fieldoffset = offsetof(CPUARMState, cp15.rvbar), }, |
8923 | { .name = "RMR_EL3", .state = ARM_CP_STATE_AA64, | |
8924 | .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 2, | |
8925 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 1 }, | |
8926 | { .name = "RMR", .state = ARM_CP_STATE_AA32, | |
8927 | .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2, | |
8928 | .access = PL3_RW, .type = ARM_CP_CONST, | |
8929 | .resetvalue = arm_feature(env, ARM_FEATURE_AARCH64) }, | |
e24fdd23 PM |
8930 | { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, |
8931 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, | |
8932 | .access = PL3_RW, | |
8933 | .raw_writefn = raw_write, .writefn = sctlr_write, | |
8934 | .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]), | |
8935 | .resetvalue = cpu->reset_sctlr }, | |
be8e8128 | 8936 | }; |
e24fdd23 PM |
8937 | |
8938 | define_arm_cp_regs(cpu, el3_regs); | |
81547d66 | 8939 | } |
9b37a28c FR |
8940 | /* |
8941 | * The behaviour of NSACR is sufficiently various that we don't | |
2f027fc5 PM |
8942 | * try to describe it in a single reginfo: |
8943 | * if EL3 is 64 bit, then trap to EL3 from S EL1, | |
8944 | * reads as constant 0xc00 from NS EL1 and NS EL2 | |
8945 | * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 | |
8946 | * if v7 without EL3, register doesn't exist | |
8947 | * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 | |
8948 | */ | |
8949 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
8950 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
10b0220e | 8951 | static const ARMCPRegInfo nsacr = { |
2f027fc5 PM |
8952 | .name = "NSACR", .type = ARM_CP_CONST, |
8953 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
8954 | .access = PL1_RW, .accessfn = nsacr_access, | |
8955 | .resetvalue = 0xc00 | |
8956 | }; | |
8957 | define_one_arm_cp_reg(cpu, &nsacr); | |
8958 | } else { | |
10b0220e | 8959 | static const ARMCPRegInfo nsacr = { |
2f027fc5 PM |
8960 | .name = "NSACR", |
8961 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
8962 | .access = PL3_RW | PL1_R, | |
8963 | .resetvalue = 0, | |
8964 | .fieldoffset = offsetof(CPUARMState, cp15.nsacr) | |
8965 | }; | |
8966 | define_one_arm_cp_reg(cpu, &nsacr); | |
8967 | } | |
8968 | } else { | |
8969 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
10b0220e | 8970 | static const ARMCPRegInfo nsacr = { |
2f027fc5 PM |
8971 | .name = "NSACR", .type = ARM_CP_CONST, |
8972 | .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, | |
8973 | .access = PL1_R, | |
8974 | .resetvalue = 0xc00 | |
8975 | }; | |
8976 | define_one_arm_cp_reg(cpu, &nsacr); | |
8977 | } | |
8978 | } | |
8979 | ||
452a0955 | 8980 | if (arm_feature(env, ARM_FEATURE_PMSA)) { |
6cb0b013 PC |
8981 | if (arm_feature(env, ARM_FEATURE_V6)) { |
8982 | /* PMSAv6 not implemented */ | |
8983 | assert(arm_feature(env, ARM_FEATURE_V7)); | |
8984 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); | |
8985 | define_arm_cp_regs(cpu, pmsav7_cp_reginfo); | |
8986 | } else { | |
8987 | define_arm_cp_regs(cpu, pmsav5_cp_reginfo); | |
8988 | } | |
18032bec | 8989 | } else { |
8e5d75c9 | 8990 | define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); |
18032bec | 8991 | define_arm_cp_regs(cpu, vmsa_cp_reginfo); |
4036b7d1 PM |
8992 | /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */ |
8993 | if (cpu_isar_feature(aa32_hpd, cpu)) { | |
ab638a32 RH |
8994 | define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); |
8995 | } | |
18032bec | 8996 | } |
c326b979 PM |
8997 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
8998 | define_arm_cp_regs(cpu, t2ee_cp_reginfo); | |
8999 | } | |
6cc7a3ae PM |
9000 | if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { |
9001 | define_arm_cp_regs(cpu, generic_timer_cp_reginfo); | |
9002 | } | |
4a501606 | 9003 | if (arm_feature(env, ARM_FEATURE_VAPA)) { |
8ce4d441 AB |
9004 | ARMCPRegInfo vapa_cp_reginfo[] = { |
9005 | { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, | |
9006 | .access = PL1_RW, .resetvalue = 0, | |
9007 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), | |
9008 | offsetoflow32(CPUARMState, cp15.par_ns) }, | |
9009 | .writefn = par_write}, | |
9010 | #ifndef CONFIG_USER_ONLY | |
9011 | /* This underdecoding is safe because the reginfo is NO_RAW. */ | |
9012 | { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, | |
9013 | .access = PL1_W, .accessfn = ats_access, | |
9014 | .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC }, | |
9015 | #endif | |
9016 | }; | |
9017 | ||
9018 | /* | |
9019 | * When LPAE exists this 32-bit PAR register is an alias of the | |
9020 | * 64-bit AArch32 PAR register defined in lpae_cp_reginfo[] | |
9021 | */ | |
9022 | if (arm_feature(env, ARM_FEATURE_LPAE)) { | |
9023 | vapa_cp_reginfo[0].type = ARM_CP_ALIAS | ARM_CP_NO_GDB; | |
9024 | } | |
4a501606 PM |
9025 | define_arm_cp_regs(cpu, vapa_cp_reginfo); |
9026 | } | |
c4804214 PM |
9027 | if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { |
9028 | define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); | |
9029 | } | |
9030 | if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { | |
9031 | define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); | |
9032 | } | |
9033 | if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { | |
9034 | define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); | |
9035 | } | |
18032bec PM |
9036 | if (arm_feature(env, ARM_FEATURE_OMAPCP)) { |
9037 | define_arm_cp_regs(cpu, omap_cp_reginfo); | |
9038 | } | |
34f90529 PM |
9039 | if (arm_feature(env, ARM_FEATURE_STRONGARM)) { |
9040 | define_arm_cp_regs(cpu, strongarm_cp_reginfo); | |
9041 | } | |
1047b9d7 PM |
9042 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
9043 | define_arm_cp_regs(cpu, xscale_cp_reginfo); | |
9044 | } | |
9045 | if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { | |
9046 | define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); | |
9047 | } | |
7ac681cf PM |
9048 | if (arm_feature(env, ARM_FEATURE_LPAE)) { |
9049 | define_arm_cp_regs(cpu, lpae_cp_reginfo); | |
9050 | } | |
873b73c0 | 9051 | if (cpu_isar_feature(aa32_jazelle, cpu)) { |
f96f3d5f MZ |
9052 | define_arm_cp_regs(cpu, jazelle_regs); |
9053 | } | |
9b37a28c FR |
9054 | /* |
9055 | * Slightly awkwardly, the OMAP and StrongARM cores need all of | |
7884849c PM |
9056 | * cp15 crn=0 to be writes-ignored, whereas for other cores they should |
9057 | * be read-only (ie write causes UNDEF exception). | |
9058 | */ | |
9059 | { | |
00a29f3d | 9060 | ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = { |
9b37a28c FR |
9061 | /* |
9062 | * Pre-v8 MIDR space. | |
00a29f3d | 9063 | * Note that the MIDR isn't a simple constant register because |
7884849c PM |
9064 | * of the TI925 behaviour where writes to another register can |
9065 | * cause the MIDR value to change. | |
97ce8d61 PC |
9066 | * |
9067 | * Unimplemented registers in the c15 0 0 0 space default to | |
9068 | * MIDR. Define MIDR first as this entire space, then CTR, TCMTR | |
9069 | * and friends override accordingly. | |
7884849c PM |
9070 | */ |
9071 | { .name = "MIDR", | |
97ce8d61 | 9072 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, |
7884849c | 9073 | .access = PL1_R, .resetvalue = cpu->midr, |
d4e6df63 | 9074 | .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, |
731de9e6 | 9075 | .readfn = midr_read, |
97ce8d61 PC |
9076 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
9077 | .type = ARM_CP_OVERRIDE }, | |
7884849c PM |
9078 | /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ |
9079 | { .name = "DUMMY", | |
9080 | .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, | |
9081 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
9082 | { .name = "DUMMY", | |
9083 | .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, | |
9084 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
9085 | { .name = "DUMMY", | |
9086 | .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, | |
9087 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
9088 | { .name = "DUMMY", | |
9089 | .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, | |
9090 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
9091 | { .name = "DUMMY", | |
9092 | .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, | |
9093 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
7884849c | 9094 | }; |
00a29f3d | 9095 | ARMCPRegInfo id_v8_midr_cp_reginfo[] = { |
00a29f3d PM |
9096 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, |
9097 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, | |
731de9e6 | 9098 | .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, |
67dd8030 | 9099 | .fgt = FGT_MIDR_EL1, |
731de9e6 EI |
9100 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), |
9101 | .readfn = midr_read }, | |
c7f786ab | 9102 | /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */ |
ac00c79f SF |
9103 | { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, |
9104 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, | |
9105 | .access = PL1_R, .resetvalue = cpu->midr }, | |
00a29f3d PM |
9106 | { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH, |
9107 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, | |
93fbc983 MZ |
9108 | .access = PL1_R, |
9109 | .accessfn = access_aa64_tid1, | |
67dd8030 | 9110 | .fgt = FGT_REVIDR_EL1, |
93fbc983 | 9111 | .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, |
00a29f3d | 9112 | }; |
c7f786ab | 9113 | ARMCPRegInfo id_v8_midr_alias_cp_reginfo = { |
acd8e83a | 9114 | .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST | ARM_CP_NO_GDB, |
c7f786ab TR |
9115 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, |
9116 | .access = PL1_R, .resetvalue = cpu->midr | |
9117 | }; | |
00a29f3d PM |
9118 | ARMCPRegInfo id_cp_reginfo[] = { |
9119 | /* These are common to v8 and pre-v8 */ | |
9120 | { .name = "CTR", | |
9121 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, | |
630fcd4d MZ |
9122 | .access = PL1_R, .accessfn = ctr_el0_access, |
9123 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, | |
00a29f3d PM |
9124 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, |
9125 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, | |
9126 | .access = PL0_R, .accessfn = ctr_el0_access, | |
b19ed03c | 9127 | .fgt = FGT_CTR_EL0, |
00a29f3d PM |
9128 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, |
9129 | /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ | |
9130 | { .name = "TCMTR", | |
9131 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, | |
93fbc983 MZ |
9132 | .access = PL1_R, |
9133 | .accessfn = access_aa32_tid1, | |
9134 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
00a29f3d | 9135 | }; |
8085ce63 PC |
9136 | /* TLBTR is specific to VMSA */ |
9137 | ARMCPRegInfo id_tlbtr_reginfo = { | |
9138 | .name = "TLBTR", | |
9139 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, | |
93fbc983 MZ |
9140 | .access = PL1_R, |
9141 | .accessfn = access_aa32_tid1, | |
9142 | .type = ARM_CP_CONST, .resetvalue = 0, | |
8085ce63 | 9143 | }; |
3281af81 PC |
9144 | /* MPUIR is specific to PMSA V6+ */ |
9145 | ARMCPRegInfo id_mpuir_reginfo = { | |
9146 | .name = "MPUIR", | |
9147 | .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, | |
9148 | .access = PL1_R, .type = ARM_CP_CONST, | |
9149 | .resetvalue = cpu->pmsav7_dregion << 8 | |
9150 | }; | |
761c4642 TR |
9151 | /* HMPUIR is specific to PMSA V8 */ |
9152 | ARMCPRegInfo id_hmpuir_reginfo = { | |
9153 | .name = "HMPUIR", | |
9154 | .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 4, | |
9155 | .access = PL2_R, .type = ARM_CP_CONST, | |
9156 | .resetvalue = cpu->pmsav8r_hdregion | |
9157 | }; | |
10b0220e | 9158 | static const ARMCPRegInfo crn0_wi_reginfo = { |
7884849c PM |
9159 | .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, |
9160 | .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, | |
9161 | .type = ARM_CP_NOP | ARM_CP_OVERRIDE | |
9162 | }; | |
6c5c0fec | 9163 | #ifdef CONFIG_USER_ONLY |
10b0220e | 9164 | static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = { |
6c5c0fec | 9165 | { .name = "MIDR_EL1", |
bc6bd20e ZS |
9166 | .exported_bits = R_MIDR_EL1_REVISION_MASK | |
9167 | R_MIDR_EL1_PARTNUM_MASK | | |
9168 | R_MIDR_EL1_ARCHITECTURE_MASK | | |
9169 | R_MIDR_EL1_VARIANT_MASK | | |
9170 | R_MIDR_EL1_IMPLEMENTER_MASK }, | |
9171 | { .name = "REVIDR_EL1" }, | |
6c5c0fec AB |
9172 | }; |
9173 | modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo); | |
9174 | #endif | |
7884849c PM |
9175 | if (arm_feature(env, ARM_FEATURE_OMAPCP) || |
9176 | arm_feature(env, ARM_FEATURE_STRONGARM)) { | |
5809ac57 | 9177 | size_t i; |
9b37a28c FR |
9178 | /* |
9179 | * Register the blanket "writes ignored" value first to cover the | |
a703eda1 PC |
9180 | * whole space. Then update the specific ID registers to allow write |
9181 | * access, so that they ignore writes rather than causing them to | |
9182 | * UNDEF. | |
7884849c PM |
9183 | */ |
9184 | define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); | |
5809ac57 RH |
9185 | for (i = 0; i < ARRAY_SIZE(id_pre_v8_midr_cp_reginfo); ++i) { |
9186 | id_pre_v8_midr_cp_reginfo[i].access = PL1_RW; | |
00a29f3d | 9187 | } |
5809ac57 RH |
9188 | for (i = 0; i < ARRAY_SIZE(id_cp_reginfo); ++i) { |
9189 | id_cp_reginfo[i].access = PL1_RW; | |
7884849c | 9190 | } |
10006112 | 9191 | id_mpuir_reginfo.access = PL1_RW; |
3281af81 | 9192 | id_tlbtr_reginfo.access = PL1_RW; |
7884849c | 9193 | } |
00a29f3d PM |
9194 | if (arm_feature(env, ARM_FEATURE_V8)) { |
9195 | define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); | |
c7f786ab TR |
9196 | if (!arm_feature(env, ARM_FEATURE_PMSA)) { |
9197 | define_one_arm_cp_reg(cpu, &id_v8_midr_alias_cp_reginfo); | |
9198 | } | |
00a29f3d PM |
9199 | } else { |
9200 | define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); | |
9201 | } | |
a703eda1 | 9202 | define_arm_cp_regs(cpu, id_cp_reginfo); |
452a0955 | 9203 | if (!arm_feature(env, ARM_FEATURE_PMSA)) { |
8085ce63 | 9204 | define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); |
761c4642 TR |
9205 | } else if (arm_feature(env, ARM_FEATURE_PMSA) && |
9206 | arm_feature(env, ARM_FEATURE_V8)) { | |
9207 | uint32_t i = 0; | |
9208 | char *tmp_string; | |
9209 | ||
9210 | define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); | |
9211 | define_one_arm_cp_reg(cpu, &id_hmpuir_reginfo); | |
9212 | define_arm_cp_regs(cpu, pmsav8r_cp_reginfo); | |
9213 | ||
9214 | /* Register alias is only valid for first 32 indexes */ | |
9215 | for (i = 0; i < MIN(cpu->pmsav7_dregion, 32); ++i) { | |
9216 | uint8_t crm = 0b1000 | extract32(i, 1, 3); | |
9217 | uint8_t opc1 = extract32(i, 4, 1); | |
9218 | uint8_t opc2 = extract32(i, 0, 1) << 2; | |
9219 | ||
9220 | tmp_string = g_strdup_printf("PRBAR%u", i); | |
9221 | ARMCPRegInfo tmp_prbarn_reginfo = { | |
9222 | .name = tmp_string, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW, | |
9223 | .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, | |
9224 | .access = PL1_RW, .resetvalue = 0, | |
9225 | .accessfn = access_tvm_trvm, | |
9226 | .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read | |
9227 | }; | |
9228 | define_one_arm_cp_reg(cpu, &tmp_prbarn_reginfo); | |
9229 | g_free(tmp_string); | |
9230 | ||
9231 | opc2 = extract32(i, 0, 1) << 2 | 0x1; | |
9232 | tmp_string = g_strdup_printf("PRLAR%u", i); | |
9233 | ARMCPRegInfo tmp_prlarn_reginfo = { | |
9234 | .name = tmp_string, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW, | |
9235 | .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, | |
9236 | .access = PL1_RW, .resetvalue = 0, | |
9237 | .accessfn = access_tvm_trvm, | |
9238 | .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read | |
9239 | }; | |
9240 | define_one_arm_cp_reg(cpu, &tmp_prlarn_reginfo); | |
9241 | g_free(tmp_string); | |
9242 | } | |
9243 | ||
9244 | /* Register alias is only valid for first 32 indexes */ | |
9245 | for (i = 0; i < MIN(cpu->pmsav8r_hdregion, 32); ++i) { | |
9246 | uint8_t crm = 0b1000 | extract32(i, 1, 3); | |
9247 | uint8_t opc1 = 0b100 | extract32(i, 4, 1); | |
9248 | uint8_t opc2 = extract32(i, 0, 1) << 2; | |
9249 | ||
9250 | tmp_string = g_strdup_printf("HPRBAR%u", i); | |
9251 | ARMCPRegInfo tmp_hprbarn_reginfo = { | |
9252 | .name = tmp_string, | |
9253 | .type = ARM_CP_NO_RAW, | |
9254 | .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, | |
9255 | .access = PL2_RW, .resetvalue = 0, | |
9256 | .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read | |
9257 | }; | |
9258 | define_one_arm_cp_reg(cpu, &tmp_hprbarn_reginfo); | |
9259 | g_free(tmp_string); | |
9260 | ||
9261 | opc2 = extract32(i, 0, 1) << 2 | 0x1; | |
9262 | tmp_string = g_strdup_printf("HPRLAR%u", i); | |
9263 | ARMCPRegInfo tmp_hprlarn_reginfo = { | |
9264 | .name = tmp_string, | |
9265 | .type = ARM_CP_NO_RAW, | |
9266 | .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, | |
9267 | .access = PL2_RW, .resetvalue = 0, | |
9268 | .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read | |
9269 | }; | |
9270 | define_one_arm_cp_reg(cpu, &tmp_hprlarn_reginfo); | |
9271 | g_free(tmp_string); | |
9272 | } | |
3281af81 PC |
9273 | } else if (arm_feature(env, ARM_FEATURE_V7)) { |
9274 | define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); | |
8085ce63 | 9275 | } |
7884849c PM |
9276 | } |
9277 | ||
97ce8d61 | 9278 | if (arm_feature(env, ARM_FEATURE_MPIDR)) { |
52264166 AB |
9279 | ARMCPRegInfo mpidr_cp_reginfo[] = { |
9280 | { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
9281 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | |
67dd8030 | 9282 | .fgt = FGT_MPIDR_EL1, |
52264166 | 9283 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, |
52264166 AB |
9284 | }; |
9285 | #ifdef CONFIG_USER_ONLY | |
10b0220e | 9286 | static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = { |
52264166 AB |
9287 | { .name = "MPIDR_EL1", |
9288 | .fixed_bits = 0x0000000080000000 }, | |
52264166 AB |
9289 | }; |
9290 | modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); | |
9291 | #endif | |
97ce8d61 PC |
9292 | define_arm_cp_regs(cpu, mpidr_cp_reginfo); |
9293 | } | |
9294 | ||
2771db27 | 9295 | if (arm_feature(env, ARM_FEATURE_AUXCR)) { |
834a6c69 PM |
9296 | ARMCPRegInfo auxcr_reginfo[] = { |
9297 | { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, | |
9298 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, | |
99602377 RH |
9299 | .access = PL1_RW, .accessfn = access_tacr, |
9300 | .type = ARM_CP_CONST, .resetvalue = cpu->reset_auxcr }, | |
834a6c69 PM |
9301 | { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, |
9302 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, | |
9303 | .access = PL2_RW, .type = ARM_CP_CONST, | |
9304 | .resetvalue = 0 }, | |
9305 | { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, | |
9306 | .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, | |
9307 | .access = PL3_RW, .type = ARM_CP_CONST, | |
9308 | .resetvalue = 0 }, | |
2771db27 | 9309 | }; |
834a6c69 | 9310 | define_arm_cp_regs(cpu, auxcr_reginfo); |
f6287c24 PM |
9311 | if (cpu_isar_feature(aa32_ac2, cpu)) { |
9312 | define_arm_cp_regs(cpu, actlr2_hactlr2_reginfo); | |
0e0456ab | 9313 | } |
2771db27 PM |
9314 | } |
9315 | ||
d8ba780b | 9316 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
d56974af LM |
9317 | /* |
9318 | * CBAR is IMPDEF, but common on Arm Cortex-A implementations. | |
9319 | * There are two flavours: | |
9320 | * (1) older 32-bit only cores have a simple 32-bit CBAR | |
9321 | * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a | |
9322 | * 32-bit register visible to AArch32 at a different encoding | |
9323 | * to the "flavour 1" register and with the bits rearranged to | |
9324 | * be able to squash a 64-bit address into the 32-bit view. | |
9325 | * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but | |
9326 | * in future if we support AArch32-only configs of some of the | |
9327 | * AArch64 cores we might need to add a specific feature flag | |
9328 | * to indicate cores with "flavour 2" CBAR. | |
9329 | */ | |
f318cec6 PM |
9330 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { |
9331 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | |
9332 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | |
9333 | | extract64(cpu->reset_cbar, 32, 12); | |
9334 | ARMCPRegInfo cbar_reginfo[] = { | |
9335 | { .name = "CBAR", | |
9336 | .type = ARM_CP_CONST, | |
d56974af LM |
9337 | .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0, |
9338 | .access = PL1_R, .resetvalue = cbar32 }, | |
f318cec6 PM |
9339 | { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, |
9340 | .type = ARM_CP_CONST, | |
9341 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | |
d56974af | 9342 | .access = PL1_R, .resetvalue = cpu->reset_cbar }, |
f318cec6 PM |
9343 | }; |
9344 | /* We don't implement a r/w 64 bit CBAR currently */ | |
9345 | assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); | |
9346 | define_arm_cp_regs(cpu, cbar_reginfo); | |
9347 | } else { | |
9348 | ARMCPRegInfo cbar = { | |
9349 | .name = "CBAR", | |
9350 | .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | |
04215eb1 | 9351 | .access = PL1_R | PL3_W, .resetvalue = cpu->reset_cbar, |
f318cec6 PM |
9352 | .fieldoffset = offsetof(CPUARMState, |
9353 | cp15.c15_config_base_address) | |
9354 | }; | |
9355 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | |
9356 | cbar.access = PL1_R; | |
9357 | cbar.fieldoffset = 0; | |
9358 | cbar.type = ARM_CP_CONST; | |
9359 | } | |
9360 | define_one_arm_cp_reg(cpu, &cbar); | |
9361 | } | |
d8ba780b PC |
9362 | } |
9363 | ||
91db4642 | 9364 | if (arm_feature(env, ARM_FEATURE_VBAR)) { |
10b0220e | 9365 | static const ARMCPRegInfo vbar_cp_reginfo[] = { |
91db4642 CLG |
9366 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, |
9367 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | |
9368 | .access = PL1_RW, .writefn = vbar_write, | |
bd8db7d9 | 9369 | .fgt = FGT_VBAR_EL1, |
91db4642 CLG |
9370 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), |
9371 | offsetof(CPUARMState, cp15.vbar_ns) }, | |
9372 | .resetvalue = 0 }, | |
91db4642 CLG |
9373 | }; |
9374 | define_arm_cp_regs(cpu, vbar_cp_reginfo); | |
9375 | } | |
9376 | ||
2771db27 PM |
9377 | /* Generic registers whose values depend on the implementation */ |
9378 | { | |
9379 | ARMCPRegInfo sctlr = { | |
5ebafdf3 | 9380 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, |
137feaa9 | 9381 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, |
84929218 | 9382 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
67dd8030 | 9383 | .fgt = FGT_SCTLR_EL1, |
137feaa9 FA |
9384 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), |
9385 | offsetof(CPUARMState, cp15.sctlr_ns) }, | |
d4e6df63 PM |
9386 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, |
9387 | .raw_writefn = raw_write, | |
2771db27 PM |
9388 | }; |
9389 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
9b37a28c FR |
9390 | /* |
9391 | * Normally we would always end the TB on an SCTLR write, but Linux | |
2771db27 PM |
9392 | * arch/arm/mach-pxa/sleep.S expects two instructions following |
9393 | * an MMU enable to execute from cache. Imitate this behaviour. | |
9394 | */ | |
9395 | sctlr.type |= ARM_CP_SUPPRESS_TB_END; | |
9396 | } | |
9397 | define_one_arm_cp_reg(cpu, &sctlr); | |
761c4642 TR |
9398 | |
9399 | if (arm_feature(env, ARM_FEATURE_PMSA) && | |
9400 | arm_feature(env, ARM_FEATURE_V8)) { | |
9401 | ARMCPRegInfo vsctlr = { | |
9402 | .name = "VSCTLR", .state = ARM_CP_STATE_AA32, | |
9403 | .cp = 15, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, | |
9404 | .access = PL2_RW, .resetvalue = 0x0, | |
9405 | .fieldoffset = offsetoflow32(CPUARMState, cp15.vsctlr), | |
9406 | }; | |
9407 | define_one_arm_cp_reg(cpu, &vsctlr); | |
9408 | } | |
2771db27 | 9409 | } |
5be5e8ed | 9410 | |
2d7137c1 | 9411 | if (cpu_isar_feature(aa64_lor, cpu)) { |
2d7137c1 RH |
9412 | define_arm_cp_regs(cpu, lor_reginfo); |
9413 | } | |
220f508f RH |
9414 | if (cpu_isar_feature(aa64_pan, cpu)) { |
9415 | define_one_arm_cp_reg(cpu, &pan_reginfo); | |
9416 | } | |
04b07d29 RH |
9417 | #ifndef CONFIG_USER_ONLY |
9418 | if (cpu_isar_feature(aa64_ats1e1, cpu)) { | |
9419 | define_arm_cp_regs(cpu, ats1e1_reginfo); | |
9420 | } | |
9421 | if (cpu_isar_feature(aa32_ats1e1, cpu)) { | |
9422 | define_arm_cp_regs(cpu, ats1cp_reginfo); | |
9423 | } | |
9424 | #endif | |
9eeb7a1c RH |
9425 | if (cpu_isar_feature(aa64_uao, cpu)) { |
9426 | define_one_arm_cp_reg(cpu, &uao_reginfo); | |
9427 | } | |
2d7137c1 | 9428 | |
dc8b1853 RC |
9429 | if (cpu_isar_feature(aa64_dit, cpu)) { |
9430 | define_one_arm_cp_reg(cpu, &dit_reginfo); | |
9431 | } | |
f2f68a78 RC |
9432 | if (cpu_isar_feature(aa64_ssbs, cpu)) { |
9433 | define_one_arm_cp_reg(cpu, &ssbs_reginfo); | |
9434 | } | |
58e93b48 RH |
9435 | if (cpu_isar_feature(any_ras, cpu)) { |
9436 | define_arm_cp_regs(cpu, minimal_ras_reginfo); | |
9437 | } | |
dc8b1853 | 9438 | |
52d18727 RH |
9439 | if (cpu_isar_feature(aa64_vh, cpu) || |
9440 | cpu_isar_feature(aa64_debugv8p2, cpu)) { | |
9441 | define_one_arm_cp_reg(cpu, &contextidr_el2); | |
9442 | } | |
e2a1a461 RH |
9443 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { |
9444 | define_arm_cp_regs(cpu, vhe_reginfo); | |
9445 | } | |
9446 | ||
cd208a1c | 9447 | if (cpu_isar_feature(aa64_sve, cpu)) { |
60360d82 | 9448 | define_arm_cp_regs(cpu, zcr_reginfo); |
5be5e8ed | 9449 | } |
967aa94f | 9450 | |
5814d587 RH |
9451 | if (cpu_isar_feature(aa64_hcx, cpu)) { |
9452 | define_one_arm_cp_reg(cpu, &hcrx_el2_reginfo); | |
9453 | } | |
9454 | ||
967aa94f | 9455 | #ifdef TARGET_AARCH64 |
9e5ec745 RH |
9456 | if (cpu_isar_feature(aa64_sme, cpu)) { |
9457 | define_arm_cp_regs(cpu, sme_reginfo); | |
9458 | } | |
967aa94f RH |
9459 | if (cpu_isar_feature(aa64_pauth, cpu)) { |
9460 | define_arm_cp_regs(cpu, pauth_reginfo); | |
9461 | } | |
de390645 RH |
9462 | if (cpu_isar_feature(aa64_rndr, cpu)) { |
9463 | define_arm_cp_regs(cpu, rndr_reginfo); | |
9464 | } | |
84940ed8 RC |
9465 | if (cpu_isar_feature(aa64_tlbirange, cpu)) { |
9466 | define_arm_cp_regs(cpu, tlbirange_reginfo); | |
9467 | } | |
7113d618 RC |
9468 | if (cpu_isar_feature(aa64_tlbios, cpu)) { |
9469 | define_arm_cp_regs(cpu, tlbios_reginfo); | |
9470 | } | |
0d57b499 BM |
9471 | /* Data Cache clean instructions up to PoP */ |
9472 | if (cpu_isar_feature(aa64_dcpop, cpu)) { | |
9473 | define_one_arm_cp_reg(cpu, dcpop_reg); | |
9474 | ||
9475 | if (cpu_isar_feature(aa64_dcpodp, cpu)) { | |
9476 | define_one_arm_cp_reg(cpu, dcpodp_reg); | |
9477 | } | |
9478 | } | |
4b779ceb RH |
9479 | |
9480 | /* | |
9481 | * If full MTE is enabled, add all of the system registers. | |
9482 | * If only "instructions available at EL0" are enabled, | |
9483 | * then define only a RAZ/WI version of PSTATE.TCO. | |
9484 | */ | |
9485 | if (cpu_isar_feature(aa64_mte, cpu)) { | |
851ec6eb RH |
9486 | ARMCPRegInfo gmid_reginfo = { |
9487 | .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, | |
9488 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, | |
9489 | .access = PL1_R, .accessfn = access_aa64_tid5, | |
9490 | .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize, | |
9491 | }; | |
9492 | define_one_arm_cp_reg(cpu, &gmid_reginfo); | |
4b779ceb | 9493 | define_arm_cp_regs(cpu, mte_reginfo); |
5463df16 | 9494 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); |
4b779ceb RH |
9495 | } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { |
9496 | define_arm_cp_regs(cpu, mte_tco_ro_reginfo); | |
5463df16 | 9497 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); |
4b779ceb | 9498 | } |
7cb1e618 RH |
9499 | |
9500 | if (cpu_isar_feature(aa64_scxtnum, cpu)) { | |
9501 | define_arm_cp_regs(cpu, scxtnum_reginfo); | |
9502 | } | |
15126d9c PM |
9503 | |
9504 | if (cpu_isar_feature(aa64_fgt, cpu)) { | |
9505 | define_arm_cp_regs(cpu, fgt_reginfo); | |
9506 | } | |
ef1febe7 RH |
9507 | |
9508 | if (cpu_isar_feature(aa64_rme, cpu)) { | |
9509 | define_arm_cp_regs(cpu, rme_reginfo); | |
9510 | if (cpu_isar_feature(aa64_mte, cpu)) { | |
9511 | define_arm_cp_regs(cpu, rme_mte_reginfo); | |
9512 | } | |
9513 | } | |
967aa94f | 9514 | #endif |
cb570bd3 | 9515 | |
22e57073 | 9516 | if (cpu_isar_feature(any_predinv, cpu)) { |
cb570bd3 RH |
9517 | define_arm_cp_regs(cpu, predinv_reginfo); |
9518 | } | |
e2cce18f | 9519 | |
957e6155 PM |
9520 | if (cpu_isar_feature(any_ccidx, cpu)) { |
9521 | define_arm_cp_regs(cpu, ccsidr2_reginfo); | |
9522 | } | |
9523 | ||
e2cce18f RH |
9524 | #ifndef CONFIG_USER_ONLY |
9525 | /* | |
9526 | * Register redirections and aliases must be done last, | |
9527 | * after the registers from the other extensions have been defined. | |
9528 | */ | |
9529 | if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { | |
9530 | define_arm_vh_e2h_redirects_aliases(cpu); | |
9531 | } | |
9532 | #endif | |
2ceb98c0 PM |
9533 | } |
9534 | ||
1859f8c3 RH |
9535 | /* |
9536 | * Private utility function for define_one_arm_cp_reg_with_opaque(): | |
9537 | * add a single reginfo struct to the hash table. | |
9538 | */ | |
6e6efd61 | 9539 | static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, |
cbe64585 RH |
9540 | void *opaque, CPState state, |
9541 | CPSecureState secstate, | |
9c513e78 AB |
9542 | int crm, int opc1, int opc2, |
9543 | const char *name) | |
6e6efd61 | 9544 | { |
696ba377 | 9545 | CPUARMState *env = &cpu->env; |
5860362d | 9546 | uint32_t key; |
c27f5d3a | 9547 | ARMCPRegInfo *r2; |
4c8c4541 RH |
9548 | bool is64 = r->type & ARM_CP_64BIT; |
9549 | bool ns = secstate & ARM_CP_SECSTATE_NS; | |
cac65299 | 9550 | int cp = r->cp; |
c27f5d3a | 9551 | size_t name_len; |
696ba377 | 9552 | bool make_const; |
c27f5d3a | 9553 | |
cac65299 RH |
9554 | switch (state) { |
9555 | case ARM_CP_STATE_AA32: | |
9556 | /* We assume it is a cp15 register if the .cp field is left unset. */ | |
9557 | if (cp == 0 && r->state == ARM_CP_STATE_BOTH) { | |
9558 | cp = 15; | |
9559 | } | |
9560 | key = ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2); | |
9561 | break; | |
9562 | case ARM_CP_STATE_AA64: | |
9563 | /* | |
9564 | * To allow abbreviation of ARMCPRegInfo definitions, we treat | |
9565 | * cp == 0 as equivalent to the value for "standard guest-visible | |
9566 | * sysreg". STATE_BOTH definitions are also always "standard sysreg" | |
9567 | * in their AArch64 view (the .cp value may be non-zero for the | |
9568 | * benefit of the AArch32 view). | |
9569 | */ | |
9570 | if (cp == 0 || r->state == ARM_CP_STATE_BOTH) { | |
9571 | cp = CP_REG_ARM64_SYSREG_CP; | |
9572 | } | |
9573 | key = ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2); | |
9574 | break; | |
9575 | default: | |
9576 | g_assert_not_reached(); | |
9577 | } | |
9578 | ||
dc44545b RH |
9579 | /* Overriding of an existing definition must be explicitly requested. */ |
9580 | if (!(r->type & ARM_CP_OVERRIDE)) { | |
9581 | const ARMCPRegInfo *oldreg = get_arm_cp_reginfo(cpu->cp_regs, key); | |
9582 | if (oldreg) { | |
9583 | assert(oldreg->type & ARM_CP_OVERRIDE); | |
9584 | } | |
9585 | } | |
9586 | ||
696ba377 RH |
9587 | /* |
9588 | * Eliminate registers that are not present because the EL is missing. | |
9589 | * Doing this here makes it easier to put all registers for a given | |
9590 | * feature into the same ARMCPRegInfo array and define them all at once. | |
9591 | */ | |
9592 | make_const = false; | |
9593 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
9594 | /* | |
9595 | * An EL2 register without EL2 but with EL3 is (usually) RES0. | |
9596 | * See rule RJFFP in section D1.1.3 of DDI0487H.a. | |
9597 | */ | |
9598 | int min_el = ctz32(r->access) / 2; | |
9599 | if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) { | |
9600 | if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { | |
9601 | return; | |
9602 | } | |
9603 | make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP); | |
9604 | } | |
9605 | } else { | |
9606 | CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2) | |
9607 | ? PL2_RW : PL1_RW); | |
9608 | if ((r->access & max_el) == 0) { | |
9609 | return; | |
9610 | } | |
9611 | } | |
9612 | ||
c27f5d3a RH |
9613 | /* Combine cpreg and name into one allocation. */ |
9614 | name_len = strlen(name) + 1; | |
9615 | r2 = g_malloc(sizeof(*r2) + name_len); | |
9616 | *r2 = *r; | |
9617 | r2->name = memcpy(r2 + 1, name, name_len); | |
3f3c82a5 | 9618 | |
cc946d96 RH |
9619 | /* |
9620 | * Update fields to match the instantiation, overwiting wildcards | |
9621 | * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH. | |
3f3c82a5 | 9622 | */ |
cc946d96 RH |
9623 | r2->cp = cp; |
9624 | r2->crm = crm; | |
9625 | r2->opc1 = opc1; | |
9626 | r2->opc2 = opc2; | |
9627 | r2->state = state; | |
3f3c82a5 | 9628 | r2->secure = secstate; |
cc946d96 RH |
9629 | if (opaque) { |
9630 | r2->opaque = opaque; | |
9631 | } | |
3f3c82a5 | 9632 | |
696ba377 RH |
9633 | if (make_const) { |
9634 | /* This should not have been a very special register to begin. */ | |
9635 | int old_special = r2->type & ARM_CP_SPECIAL_MASK; | |
9636 | assert(old_special == 0 || old_special == ARM_CP_NOP); | |
1859f8c3 | 9637 | /* |
696ba377 RH |
9638 | * Set the special function to CONST, retaining the other flags. |
9639 | * This is important for e.g. ARM_CP_SVE so that we still | |
9640 | * take the SVE trap if CPTR_EL3.EZ == 0. | |
f5a0a5a5 | 9641 | */ |
696ba377 RH |
9642 | r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST; |
9643 | /* | |
9644 | * Usually, these registers become RES0, but there are a few | |
9645 | * special cases like VPIDR_EL2 which have a constant non-zero | |
9646 | * value with writes ignored. | |
9647 | */ | |
9648 | if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { | |
9649 | r2->resetvalue = 0; | |
9650 | } | |
9651 | /* | |
9652 | * ARM_CP_CONST has precedence, so removing the callbacks and | |
9653 | * offsets are not strictly necessary, but it is potentially | |
9654 | * less confusing to debug later. | |
9655 | */ | |
9656 | r2->readfn = NULL; | |
9657 | r2->writefn = NULL; | |
9658 | r2->raw_readfn = NULL; | |
9659 | r2->raw_writefn = NULL; | |
9660 | r2->resetfn = NULL; | |
9661 | r2->fieldoffset = 0; | |
9662 | r2->bank_fieldoffsets[0] = 0; | |
9663 | r2->bank_fieldoffsets[1] = 0; | |
9664 | } else { | |
9665 | bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; | |
3f3c82a5 | 9666 | |
10748a96 | 9667 | if (isbanked) { |
1859f8c3 | 9668 | /* |
696ba377 RH |
9669 | * Register is banked (using both entries in array). |
9670 | * Overwriting fieldoffset as the array is only used to define | |
9671 | * banked registers but later only fieldoffset is used. | |
3f3c82a5 | 9672 | */ |
696ba377 RH |
9673 | r2->fieldoffset = r->bank_fieldoffsets[ns]; |
9674 | } | |
9675 | if (state == ARM_CP_STATE_AA32) { | |
9676 | if (isbanked) { | |
9677 | /* | |
9678 | * If the register is banked then we don't need to migrate or | |
9679 | * reset the 32-bit instance in certain cases: | |
9680 | * | |
9681 | * 1) If the register has both 32-bit and 64-bit instances | |
9682 | * then we can count on the 64-bit instance taking care | |
9683 | * of the non-secure bank. | |
9684 | * 2) If ARMv8 is enabled then we can count on a 64-bit | |
9685 | * version taking care of the secure bank. This requires | |
9686 | * that separate 32 and 64-bit definitions are provided. | |
9687 | */ | |
9688 | if ((r->state == ARM_CP_STATE_BOTH && ns) || | |
9689 | (arm_feature(env, ARM_FEATURE_V8) && !ns)) { | |
9690 | r2->type |= ARM_CP_ALIAS; | |
9691 | } | |
9692 | } else if ((secstate != r->secure) && !ns) { | |
9693 | /* | |
9694 | * The register is not banked so we only want to allow | |
9695 | * migration of the non-secure instance. | |
9696 | */ | |
7a0e58fa | 9697 | r2->type |= ARM_CP_ALIAS; |
3f3c82a5 | 9698 | } |
3f3c82a5 | 9699 | |
696ba377 RH |
9700 | if (HOST_BIG_ENDIAN && |
9701 | r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) { | |
9702 | r2->fieldoffset += sizeof(uint32_t); | |
9703 | } | |
3f3c82a5 | 9704 | } |
f5a0a5a5 | 9705 | } |
cc946d96 | 9706 | |
1859f8c3 RH |
9707 | /* |
9708 | * By convention, for wildcarded registers only the first | |
6e6efd61 | 9709 | * entry is used for migration; the others are marked as |
7a0e58fa | 9710 | * ALIAS so we don't try to transfer the register |
6e6efd61 | 9711 | * multiple times. Special registers (ie NOP/WFI) are |
7a0e58fa | 9712 | * never migratable and not even raw-accessible. |
6e6efd61 | 9713 | */ |
696ba377 | 9714 | if (r2->type & ARM_CP_SPECIAL_MASK) { |
7a0e58fa PM |
9715 | r2->type |= ARM_CP_NO_RAW; |
9716 | } | |
9717 | if (((r->crm == CP_ANY) && crm != 0) || | |
6e6efd61 PM |
9718 | ((r->opc1 == CP_ANY) && opc1 != 0) || |
9719 | ((r->opc2 == CP_ANY) && opc2 != 0)) { | |
1f163787 | 9720 | r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB; |
6e6efd61 PM |
9721 | } |
9722 | ||
1859f8c3 RH |
9723 | /* |
9724 | * Check that raw accesses are either forbidden or handled. Note that | |
375421cc PM |
9725 | * we can't assert this earlier because the setup of fieldoffset for |
9726 | * banked registers has to be done first. | |
9727 | */ | |
9728 | if (!(r2->type & ARM_CP_NO_RAW)) { | |
9729 | assert(!raw_accessors_invalid(r2)); | |
9730 | } | |
9731 | ||
5860362d | 9732 | g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); |
6e6efd61 PM |
9733 | } |
9734 | ||
9735 | ||
4b6a83fb PM |
9736 | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, |
9737 | const ARMCPRegInfo *r, void *opaque) | |
9738 | { | |
9b37a28c FR |
9739 | /* |
9740 | * Define implementations of coprocessor registers. | |
4b6a83fb PM |
9741 | * We store these in a hashtable because typically |
9742 | * there are less than 150 registers in a space which | |
9743 | * is 16*16*16*8*8 = 262144 in size. | |
9744 | * Wildcarding is supported for the crm, opc1 and opc2 fields. | |
9745 | * If a register is defined twice then the second definition is | |
9746 | * used, so this can be used to define some generic registers and | |
9747 | * then override them with implementation specific variations. | |
9748 | * At least one of the original and the second definition should | |
9749 | * include ARM_CP_OVERRIDE in its type bits -- this is just a guard | |
9750 | * against accidental use. | |
f5a0a5a5 PM |
9751 | * |
9752 | * The state field defines whether the register is to be | |
9753 | * visible in the AArch32 or AArch64 execution state. If the | |
9754 | * state is set to ARM_CP_STATE_BOTH then we synthesise a | |
9755 | * reginfo structure for the AArch32 view, which sees the lower | |
9756 | * 32 bits of the 64 bit register. | |
9757 | * | |
9758 | * Only registers visible in AArch64 may set r->opc0; opc0 cannot | |
9759 | * be wildcarded. AArch64 registers are always considered to be 64 | |
9760 | * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of | |
9761 | * the register, if any. | |
4b6a83fb | 9762 | */ |
d95101d6 | 9763 | int crm, opc1, opc2; |
4b6a83fb PM |
9764 | int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; |
9765 | int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; | |
9766 | int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; | |
9767 | int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; | |
9768 | int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; | |
9769 | int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; | |
d95101d6 RH |
9770 | CPState state; |
9771 | ||
4b6a83fb PM |
9772 | /* 64 bit registers have only CRm and Opc1 fields */ |
9773 | assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); | |
f5a0a5a5 PM |
9774 | /* op0 only exists in the AArch64 encodings */ |
9775 | assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0)); | |
9776 | /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ | |
9777 | assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); | |
cd8be50e PM |
9778 | /* |
9779 | * This API is only for Arm's system coprocessors (14 and 15) or | |
9780 | * (M-profile or v7A-and-earlier only) for implementation defined | |
9781 | * coprocessors in the range 0..7. Our decode assumes this, since | |
9782 | * 8..13 can be used for other insns including VFP and Neon. See | |
9783 | * valid_cp() in translate.c. Assert here that we haven't tried | |
9784 | * to use an invalid coprocessor number. | |
9785 | */ | |
9786 | switch (r->state) { | |
9787 | case ARM_CP_STATE_BOTH: | |
9788 | /* 0 has a special meaning, but otherwise the same rules as AA32. */ | |
9789 | if (r->cp == 0) { | |
9790 | break; | |
9791 | } | |
9792 | /* fall through */ | |
9793 | case ARM_CP_STATE_AA32: | |
9794 | if (arm_feature(&cpu->env, ARM_FEATURE_V8) && | |
9795 | !arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
9796 | assert(r->cp >= 14 && r->cp <= 15); | |
9797 | } else { | |
9798 | assert(r->cp < 8 || (r->cp >= 14 && r->cp <= 15)); | |
9799 | } | |
9800 | break; | |
9801 | case ARM_CP_STATE_AA64: | |
9802 | assert(r->cp == 0 || r->cp == CP_REG_ARM64_SYSREG_CP); | |
9803 | break; | |
9804 | default: | |
9805 | g_assert_not_reached(); | |
9806 | } | |
9b37a28c FR |
9807 | /* |
9808 | * The AArch64 pseudocode CheckSystemAccess() specifies that op1 | |
f5a0a5a5 PM |
9809 | * encodes a minimum access level for the register. We roll this |
9810 | * runtime check into our general permission check code, so check | |
9811 | * here that the reginfo's specified permissions are strict enough | |
9812 | * to encompass the generic architectural permission check. | |
9813 | */ | |
9814 | if (r->state != ARM_CP_STATE_AA32) { | |
39107337 | 9815 | CPAccessRights mask; |
f5a0a5a5 | 9816 | switch (r->opc1) { |
b5bd7440 AB |
9817 | case 0: |
9818 | /* min_EL EL1, but some accessible to EL0 via kernel ABI */ | |
9819 | mask = PL0U_R | PL1_RW; | |
9820 | break; | |
9821 | case 1: case 2: | |
f5a0a5a5 PM |
9822 | /* min_EL EL1 */ |
9823 | mask = PL1_RW; | |
9824 | break; | |
9825 | case 3: | |
9826 | /* min_EL EL0 */ | |
9827 | mask = PL0_RW; | |
9828 | break; | |
9829 | case 4: | |
b4ecf60f | 9830 | case 5: |
f5a0a5a5 PM |
9831 | /* min_EL EL2 */ |
9832 | mask = PL2_RW; | |
9833 | break; | |
f5a0a5a5 PM |
9834 | case 6: |
9835 | /* min_EL EL3 */ | |
9836 | mask = PL3_RW; | |
9837 | break; | |
9838 | case 7: | |
9839 | /* min_EL EL1, secure mode only (we don't check the latter) */ | |
9840 | mask = PL1_RW; | |
9841 | break; | |
9842 | default: | |
9843 | /* broken reginfo with out-of-range opc1 */ | |
d385a605 | 9844 | g_assert_not_reached(); |
f5a0a5a5 PM |
9845 | } |
9846 | /* assert our permissions are not too lax (stricter is fine) */ | |
9847 | assert((r->access & ~mask) == 0); | |
9848 | } | |
9849 | ||
9b37a28c FR |
9850 | /* |
9851 | * Check that the register definition has enough info to handle | |
4b6a83fb PM |
9852 | * reads and writes if they are permitted. |
9853 | */ | |
87c3f0f2 | 9854 | if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) { |
4b6a83fb | 9855 | if (r->access & PL3_R) { |
3f3c82a5 FA |
9856 | assert((r->fieldoffset || |
9857 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
9858 | r->readfn); | |
4b6a83fb PM |
9859 | } |
9860 | if (r->access & PL3_W) { | |
3f3c82a5 FA |
9861 | assert((r->fieldoffset || |
9862 | (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || | |
9863 | r->writefn); | |
4b6a83fb PM |
9864 | } |
9865 | } | |
5809ac57 | 9866 | |
4b6a83fb PM |
9867 | for (crm = crmmin; crm <= crmmax; crm++) { |
9868 | for (opc1 = opc1min; opc1 <= opc1max; opc1++) { | |
9869 | for (opc2 = opc2min; opc2 <= opc2max; opc2++) { | |
f5a0a5a5 PM |
9870 | for (state = ARM_CP_STATE_AA32; |
9871 | state <= ARM_CP_STATE_AA64; state++) { | |
9872 | if (r->state != state && r->state != ARM_CP_STATE_BOTH) { | |
9873 | continue; | |
9874 | } | |
3f3c82a5 | 9875 | if (state == ARM_CP_STATE_AA32) { |
9b37a28c FR |
9876 | /* |
9877 | * Under AArch32 CP registers can be common | |
3f3c82a5 FA |
9878 | * (same for secure and non-secure world) or banked. |
9879 | */ | |
9c513e78 AB |
9880 | char *name; |
9881 | ||
3f3c82a5 FA |
9882 | switch (r->secure) { |
9883 | case ARM_CP_SECSTATE_S: | |
9884 | case ARM_CP_SECSTATE_NS: | |
9885 | add_cpreg_to_hashtable(cpu, r, opaque, state, | |
9c513e78 AB |
9886 | r->secure, crm, opc1, opc2, |
9887 | r->name); | |
3f3c82a5 | 9888 | break; |
cbe64585 | 9889 | case ARM_CP_SECSTATE_BOTH: |
9c513e78 | 9890 | name = g_strdup_printf("%s_S", r->name); |
3f3c82a5 FA |
9891 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
9892 | ARM_CP_SECSTATE_S, | |
9c513e78 AB |
9893 | crm, opc1, opc2, name); |
9894 | g_free(name); | |
3f3c82a5 FA |
9895 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
9896 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 9897 | crm, opc1, opc2, r->name); |
3f3c82a5 | 9898 | break; |
cbe64585 RH |
9899 | default: |
9900 | g_assert_not_reached(); | |
3f3c82a5 FA |
9901 | } |
9902 | } else { | |
9b37a28c FR |
9903 | /* |
9904 | * AArch64 registers get mapped to non-secure instance | |
9905 | * of AArch32 | |
9906 | */ | |
3f3c82a5 FA |
9907 | add_cpreg_to_hashtable(cpu, r, opaque, state, |
9908 | ARM_CP_SECSTATE_NS, | |
9c513e78 | 9909 | crm, opc1, opc2, r->name); |
3f3c82a5 | 9910 | } |
f5a0a5a5 | 9911 | } |
4b6a83fb PM |
9912 | } |
9913 | } | |
9914 | } | |
9915 | } | |
9916 | ||
5809ac57 RH |
9917 | /* Define a whole list of registers */ |
9918 | void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs, | |
9919 | void *opaque, size_t len) | |
4b6a83fb | 9920 | { |
5809ac57 RH |
9921 | size_t i; |
9922 | for (i = 0; i < len; ++i) { | |
9923 | define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque); | |
4b6a83fb PM |
9924 | } |
9925 | } | |
9926 | ||
6c5c0fec AB |
9927 | /* |
9928 | * Modify ARMCPRegInfo for access from userspace. | |
9929 | * | |
9930 | * This is a data driven modification directed by | |
9931 | * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as | |
9932 | * user-space cannot alter any values and dynamic values pertaining to | |
9933 | * execution state are hidden from user space view anyway. | |
9934 | */ | |
5809ac57 RH |
9935 | void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, |
9936 | const ARMCPRegUserSpaceInfo *mods, | |
9937 | size_t mods_len) | |
6c5c0fec | 9938 | { |
5809ac57 RH |
9939 | for (size_t mi = 0; mi < mods_len; ++mi) { |
9940 | const ARMCPRegUserSpaceInfo *m = mods + mi; | |
d040242e | 9941 | GPatternSpec *pat = NULL; |
5809ac57 | 9942 | |
d040242e AB |
9943 | if (m->is_glob) { |
9944 | pat = g_pattern_spec_new(m->name); | |
9945 | } | |
5809ac57 RH |
9946 | for (size_t ri = 0; ri < regs_len; ++ri) { |
9947 | ARMCPRegInfo *r = regs + ri; | |
9948 | ||
d040242e AB |
9949 | if (pat && g_pattern_match_string(pat, r->name)) { |
9950 | r->type = ARM_CP_CONST; | |
9951 | r->access = PL0U_R; | |
9952 | r->resetvalue = 0; | |
9953 | /* continue */ | |
9954 | } else if (strcmp(r->name, m->name) == 0) { | |
6c5c0fec AB |
9955 | r->type = ARM_CP_CONST; |
9956 | r->access = PL0U_R; | |
9957 | r->resetvalue &= m->exported_bits; | |
9958 | r->resetvalue |= m->fixed_bits; | |
9959 | break; | |
9960 | } | |
9961 | } | |
d040242e AB |
9962 | if (pat) { |
9963 | g_pattern_spec_free(pat); | |
9964 | } | |
6c5c0fec AB |
9965 | } |
9966 | } | |
9967 | ||
60322b39 | 9968 | const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) |
4b6a83fb | 9969 | { |
5860362d | 9970 | return g_hash_table_lookup(cpregs, (gpointer)(uintptr_t)encoded_cp); |
4b6a83fb PM |
9971 | } |
9972 | ||
c4241c7d PM |
9973 | void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
9974 | uint64_t value) | |
4b6a83fb PM |
9975 | { |
9976 | /* Helper coprocessor write function for write-ignore registers */ | |
4b6a83fb PM |
9977 | } |
9978 | ||
c4241c7d | 9979 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) |
4b6a83fb PM |
9980 | { |
9981 | /* Helper coprocessor write function for read-as-zero registers */ | |
4b6a83fb PM |
9982 | return 0; |
9983 | } | |
9984 | ||
f5a0a5a5 PM |
9985 | void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) |
9986 | { | |
9987 | /* Helper coprocessor reset function for do-nothing-on-reset registers */ | |
9988 | } | |
9989 | ||
af393ffc | 9990 | static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) |
37064a8b | 9991 | { |
9b37a28c FR |
9992 | /* |
9993 | * Return true if it is not valid for us to switch to | |
37064a8b PM |
9994 | * this CPU mode (ie all the UNPREDICTABLE cases in |
9995 | * the ARM ARM CPSRWriteByInstr pseudocode). | |
9996 | */ | |
af393ffc PM |
9997 | |
9998 | /* Changes to or from Hyp via MSR and CPS are illegal. */ | |
9999 | if (write_type == CPSRWriteByInstr && | |
10000 | ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP || | |
10001 | mode == ARM_CPU_MODE_HYP)) { | |
10002 | return 1; | |
10003 | } | |
10004 | ||
37064a8b PM |
10005 | switch (mode) { |
10006 | case ARM_CPU_MODE_USR: | |
10eacda7 | 10007 | return 0; |
37064a8b PM |
10008 | case ARM_CPU_MODE_SYS: |
10009 | case ARM_CPU_MODE_SVC: | |
10010 | case ARM_CPU_MODE_ABT: | |
10011 | case ARM_CPU_MODE_UND: | |
10012 | case ARM_CPU_MODE_IRQ: | |
10013 | case ARM_CPU_MODE_FIQ: | |
9b37a28c FR |
10014 | /* |
10015 | * Note that we don't implement the IMPDEF NSACR.RFR which in v7 | |
52ff951b PM |
10016 | * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) |
10017 | */ | |
9b37a28c FR |
10018 | /* |
10019 | * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR | |
10eacda7 PM |
10020 | * and CPS are treated as illegal mode changes. |
10021 | */ | |
10022 | if (write_type == CPSRWriteByInstr && | |
10eacda7 | 10023 | (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && |
7c208e0f | 10024 | (arm_hcr_el2_eff(env) & HCR_TGE)) { |
10eacda7 PM |
10025 | return 1; |
10026 | } | |
37064a8b | 10027 | return 0; |
e6c8fc07 | 10028 | case ARM_CPU_MODE_HYP: |
e6ef0169 | 10029 | return !arm_is_el2_enabled(env) || arm_current_el(env) < 2; |
027fc527 | 10030 | case ARM_CPU_MODE_MON: |
58ae2d1f | 10031 | return arm_current_el(env) < 3; |
37064a8b PM |
10032 | default: |
10033 | return 1; | |
10034 | } | |
10035 | } | |
10036 | ||
2f4a40e5 AZ |
10037 | uint32_t cpsr_read(CPUARMState *env) |
10038 | { | |
10039 | int ZF; | |
6fbe23d5 PB |
10040 | ZF = (env->ZF == 0); |
10041 | return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | | |
2f4a40e5 AZ |
10042 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
10043 | | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) | |
10044 | | ((env->condexec_bits & 0xfc) << 8) | |
af519934 | 10045 | | (env->GE << 16) | (env->daif & CPSR_AIF); |
2f4a40e5 AZ |
10046 | } |
10047 | ||
50866ba5 PM |
10048 | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, |
10049 | CPSRWriteType write_type) | |
2f4a40e5 | 10050 | { |
6e8801f9 | 10051 | uint32_t changed_daif; |
e784807c PM |
10052 | bool rebuild_hflags = (write_type != CPSRWriteRaw) && |
10053 | (mask & (CPSR_M | CPSR_E | CPSR_IL)); | |
6e8801f9 | 10054 | |
2f4a40e5 | 10055 | if (mask & CPSR_NZCV) { |
6fbe23d5 PB |
10056 | env->ZF = (~val) & CPSR_Z; |
10057 | env->NF = val; | |
2f4a40e5 AZ |
10058 | env->CF = (val >> 29) & 1; |
10059 | env->VF = (val << 3) & 0x80000000; | |
10060 | } | |
f927dbda | 10061 | if (mask & CPSR_Q) { |
2f4a40e5 | 10062 | env->QF = ((val & CPSR_Q) != 0); |
f927dbda FR |
10063 | } |
10064 | if (mask & CPSR_T) { | |
2f4a40e5 | 10065 | env->thumb = ((val & CPSR_T) != 0); |
f927dbda | 10066 | } |
2f4a40e5 AZ |
10067 | if (mask & CPSR_IT_0_1) { |
10068 | env->condexec_bits &= ~3; | |
10069 | env->condexec_bits |= (val >> 25) & 3; | |
10070 | } | |
10071 | if (mask & CPSR_IT_2_7) { | |
10072 | env->condexec_bits &= 3; | |
10073 | env->condexec_bits |= (val >> 8) & 0xfc; | |
10074 | } | |
10075 | if (mask & CPSR_GE) { | |
10076 | env->GE = (val >> 16) & 0xf; | |
10077 | } | |
10078 | ||
9b37a28c FR |
10079 | /* |
10080 | * In a V7 implementation that includes the security extensions but does | |
6e8801f9 FA |
10081 | * not include Virtualization Extensions the SCR.FW and SCR.AW bits control |
10082 | * whether non-secure software is allowed to change the CPSR_F and CPSR_A | |
10083 | * bits respectively. | |
10084 | * | |
10085 | * In a V8 implementation, it is permitted for privileged software to | |
10086 | * change the CPSR A/F bits regardless of the SCR.AW/FW bits. | |
10087 | */ | |
f8c88bbc | 10088 | if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && |
6e8801f9 FA |
10089 | arm_feature(env, ARM_FEATURE_EL3) && |
10090 | !arm_feature(env, ARM_FEATURE_EL2) && | |
10091 | !arm_is_secure(env)) { | |
10092 | ||
10093 | changed_daif = (env->daif ^ val) & mask; | |
10094 | ||
10095 | if (changed_daif & CPSR_A) { | |
9b37a28c FR |
10096 | /* |
10097 | * Check to see if we are allowed to change the masking of async | |
6e8801f9 FA |
10098 | * abort exceptions from a non-secure state. |
10099 | */ | |
10100 | if (!(env->cp15.scr_el3 & SCR_AW)) { | |
10101 | qemu_log_mask(LOG_GUEST_ERROR, | |
10102 | "Ignoring attempt to switch CPSR_A flag from " | |
10103 | "non-secure world with SCR.AW bit clear\n"); | |
10104 | mask &= ~CPSR_A; | |
10105 | } | |
10106 | } | |
10107 | ||
10108 | if (changed_daif & CPSR_F) { | |
9b37a28c FR |
10109 | /* |
10110 | * Check to see if we are allowed to change the masking of FIQ | |
6e8801f9 FA |
10111 | * exceptions from a non-secure state. |
10112 | */ | |
10113 | if (!(env->cp15.scr_el3 & SCR_FW)) { | |
10114 | qemu_log_mask(LOG_GUEST_ERROR, | |
10115 | "Ignoring attempt to switch CPSR_F flag from " | |
10116 | "non-secure world with SCR.FW bit clear\n"); | |
10117 | mask &= ~CPSR_F; | |
10118 | } | |
10119 | ||
9b37a28c FR |
10120 | /* |
10121 | * Check whether non-maskable FIQ (NMFI) support is enabled. | |
6e8801f9 FA |
10122 | * If this bit is set software is not allowed to mask |
10123 | * FIQs, but is allowed to set CPSR_F to 0. | |
10124 | */ | |
10125 | if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && | |
10126 | (val & CPSR_F)) { | |
10127 | qemu_log_mask(LOG_GUEST_ERROR, | |
10128 | "Ignoring attempt to enable CPSR_F flag " | |
10129 | "(non-maskable FIQ [NMFI] support enabled)\n"); | |
10130 | mask &= ~CPSR_F; | |
10131 | } | |
10132 | } | |
10133 | } | |
10134 | ||
4cc35614 PM |
10135 | env->daif &= ~(CPSR_AIF & mask); |
10136 | env->daif |= val & CPSR_AIF & mask; | |
10137 | ||
f8c88bbc PM |
10138 | if (write_type != CPSRWriteRaw && |
10139 | ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { | |
8c4f0eb9 | 10140 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) { |
9b37a28c FR |
10141 | /* |
10142 | * Note that we can only get here in USR mode if this is a | |
8c4f0eb9 PM |
10143 | * gdb stub write; for this case we follow the architectural |
10144 | * behaviour for guest writes in USR mode of ignoring an attempt | |
10145 | * to switch mode. (Those are caught by translate.c for writes | |
10146 | * triggered by guest instructions.) | |
10147 | */ | |
10148 | mask &= ~CPSR_M; | |
10149 | } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { | |
9b37a28c FR |
10150 | /* |
10151 | * Attempt to switch to an invalid mode: this is UNPREDICTABLE in | |
81907a58 PM |
10152 | * v7, and has defined behaviour in v8: |
10153 | * + leave CPSR.M untouched | |
10154 | * + allow changes to the other CPSR fields | |
10155 | * + set PSTATE.IL | |
10156 | * For user changes via the GDB stub, we don't set PSTATE.IL, | |
10157 | * as this would be unnecessarily harsh for a user error. | |
37064a8b PM |
10158 | */ |
10159 | mask &= ~CPSR_M; | |
81907a58 PM |
10160 | if (write_type != CPSRWriteByGDBStub && |
10161 | arm_feature(env, ARM_FEATURE_V8)) { | |
10162 | mask |= CPSR_IL; | |
10163 | val |= CPSR_IL; | |
10164 | } | |
81e37284 PM |
10165 | qemu_log_mask(LOG_GUEST_ERROR, |
10166 | "Illegal AArch32 mode switch attempt from %s to %s\n", | |
10167 | aarch32_mode_name(env->uncached_cpsr), | |
10168 | aarch32_mode_name(val)); | |
37064a8b | 10169 | } else { |
81e37284 PM |
10170 | qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n", |
10171 | write_type == CPSRWriteExceptionReturn ? | |
10172 | "Exception return from AArch32" : | |
10173 | "AArch32 mode switch from", | |
10174 | aarch32_mode_name(env->uncached_cpsr), | |
10175 | aarch32_mode_name(val), env->regs[15]); | |
37064a8b PM |
10176 | switch_mode(env, val & CPSR_M); |
10177 | } | |
2f4a40e5 AZ |
10178 | } |
10179 | mask &= ~CACHED_CPSR_BITS; | |
10180 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); | |
2b77ad4d | 10181 | if (tcg_enabled() && rebuild_hflags) { |
e784807c PM |
10182 | arm_rebuild_hflags(env); |
10183 | } | |
2f4a40e5 AZ |
10184 | } |
10185 | ||
c47eaf9f | 10186 | #ifdef CONFIG_USER_ONLY |
b5ff1b31 | 10187 | |
affdb64d | 10188 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 | 10189 | { |
2fc0cc0e | 10190 | ARMCPU *cpu = env_archcpu(env); |
a47dddd7 AF |
10191 | |
10192 | if (mode != ARM_CPU_MODE_USR) { | |
10193 | cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); | |
10194 | } | |
b5ff1b31 FB |
10195 | } |
10196 | ||
012a906b GB |
10197 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
10198 | uint32_t cur_el, bool secure) | |
9e729b57 EI |
10199 | { |
10200 | return 1; | |
10201 | } | |
10202 | ||
ce02049d GB |
10203 | void aarch64_sync_64_to_32(CPUARMState *env) |
10204 | { | |
10205 | g_assert_not_reached(); | |
10206 | } | |
10207 | ||
b5ff1b31 FB |
10208 | #else |
10209 | ||
affdb64d | 10210 | static void switch_mode(CPUARMState *env, int mode) |
b5ff1b31 FB |
10211 | { |
10212 | int old_mode; | |
10213 | int i; | |
10214 | ||
10215 | old_mode = env->uncached_cpsr & CPSR_M; | |
f927dbda | 10216 | if (mode == old_mode) { |
b5ff1b31 | 10217 | return; |
f927dbda | 10218 | } |
b5ff1b31 FB |
10219 | |
10220 | if (old_mode == ARM_CPU_MODE_FIQ) { | |
04215eb1 FR |
10221 | memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); |
10222 | memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); | |
b5ff1b31 | 10223 | } else if (mode == ARM_CPU_MODE_FIQ) { |
04215eb1 FR |
10224 | memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); |
10225 | memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); | |
b5ff1b31 FB |
10226 | } |
10227 | ||
f5206413 | 10228 | i = bank_number(old_mode); |
b5ff1b31 | 10229 | env->banked_r13[i] = env->regs[13]; |
b5ff1b31 FB |
10230 | env->banked_spsr[i] = env->spsr; |
10231 | ||
f5206413 | 10232 | i = bank_number(mode); |
b5ff1b31 | 10233 | env->regs[13] = env->banked_r13[i]; |
b5ff1b31 | 10234 | env->spsr = env->banked_spsr[i]; |
593cfa2b PM |
10235 | |
10236 | env->banked_r14[r14_bank_number(old_mode)] = env->regs[14]; | |
10237 | env->regs[14] = env->banked_r14[r14_bank_number(mode)]; | |
b5ff1b31 FB |
10238 | } |
10239 | ||
9b37a28c FR |
10240 | /* |
10241 | * Physical Interrupt Target EL Lookup Table | |
0eeb17d6 GB |
10242 | * |
10243 | * [ From ARM ARM section G1.13.4 (Table G1-15) ] | |
10244 | * | |
10245 | * The below multi-dimensional table is used for looking up the target | |
10246 | * exception level given numerous condition criteria. Specifically, the | |
10247 | * target EL is based on SCR and HCR routing controls as well as the | |
10248 | * currently executing EL and secure state. | |
10249 | * | |
10250 | * Dimensions: | |
10251 | * target_el_table[2][2][2][2][2][4] | |
10252 | * | | | | | +--- Current EL | |
10253 | * | | | | +------ Non-secure(0)/Secure(1) | |
10254 | * | | | +--------- HCR mask override | |
10255 | * | | +------------ SCR exec state control | |
10256 | * | +--------------- SCR mask override | |
10257 | * +------------------ 32-bit(0)/64-bit(1) EL3 | |
10258 | * | |
10259 | * The table values are as such: | |
10260 | * 0-3 = EL0-EL3 | |
10261 | * -1 = Cannot occur | |
10262 | * | |
10263 | * The ARM ARM target EL table includes entries indicating that an "exception | |
10264 | * is not taken". The two cases where this is applicable are: | |
10265 | * 1) An exception is taken from EL3 but the SCR does not have the exception | |
10266 | * routed to EL3. | |
10267 | * 2) An exception is taken from EL2 but the HCR does not have the exception | |
10268 | * routed to EL2. | |
10269 | * In these two cases, the below table contain a target of EL1. This value is | |
10270 | * returned as it is expected that the consumer of the table data will check | |
10271 | * for "target EL >= current EL" to ensure the exception is not taken. | |
10272 | * | |
10273 | * SCR HCR | |
10274 | * 64 EA AMO From | |
10275 | * BIT IRQ IMO Non-secure Secure | |
10276 | * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3 | |
10277 | */ | |
82c39f6a | 10278 | static const int8_t target_el_table[2][2][2][2][2][4] = { |
0eeb17d6 GB |
10279 | {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, |
10280 | {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},}, | |
10281 | {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },}, | |
10282 | {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},}, | |
10283 | {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
10284 | {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},}, | |
10285 | {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },}, | |
10286 | {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},}, | |
10287 | {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },}, | |
6c85f906 RDC |
10288 | {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},}, |
10289 | {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },}, | |
10290 | {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},}, | |
0eeb17d6 GB |
10291 | {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },}, |
10292 | {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},}, | |
6c85f906 RDC |
10293 | {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },}, |
10294 | {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},}, | |
0eeb17d6 GB |
10295 | }; |
10296 | ||
10297 | /* | |
10298 | * Determine the target EL for physical exceptions | |
10299 | */ | |
012a906b GB |
10300 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, |
10301 | uint32_t cur_el, bool secure) | |
0eeb17d6 | 10302 | { |
b77af26e | 10303 | CPUARMState *env = cpu_env(cs); |
f7778444 RH |
10304 | bool rw; |
10305 | bool scr; | |
10306 | bool hcr; | |
0eeb17d6 | 10307 | int target_el; |
2cde031f | 10308 | /* Is the highest EL AArch64? */ |
f7778444 RH |
10309 | bool is64 = arm_feature(env, ARM_FEATURE_AARCH64); |
10310 | uint64_t hcr_el2; | |
2cde031f SS |
10311 | |
10312 | if (arm_feature(env, ARM_FEATURE_EL3)) { | |
10313 | rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); | |
10314 | } else { | |
9b37a28c FR |
10315 | /* |
10316 | * Either EL2 is the highest EL (and so the EL2 register width | |
2cde031f SS |
10317 | * is given by is64); or there is no EL2 or EL3, in which case |
10318 | * the value of 'rw' does not affect the table lookup anyway. | |
10319 | */ | |
10320 | rw = is64; | |
10321 | } | |
0eeb17d6 | 10322 | |
f7778444 | 10323 | hcr_el2 = arm_hcr_el2_eff(env); |
0eeb17d6 GB |
10324 | switch (excp_idx) { |
10325 | case EXCP_IRQ: | |
10326 | scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); | |
f7778444 | 10327 | hcr = hcr_el2 & HCR_IMO; |
0eeb17d6 GB |
10328 | break; |
10329 | case EXCP_FIQ: | |
10330 | scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); | |
f7778444 | 10331 | hcr = hcr_el2 & HCR_FMO; |
0eeb17d6 GB |
10332 | break; |
10333 | default: | |
10334 | scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); | |
f7778444 | 10335 | hcr = hcr_el2 & HCR_AMO; |
0eeb17d6 GB |
10336 | break; |
10337 | }; | |
10338 | ||
d1b31428 RH |
10339 | /* |
10340 | * For these purposes, TGE and AMO/IMO/FMO both force the | |
10341 | * interrupt to EL2. Fold TGE into the bit extracted above. | |
10342 | */ | |
10343 | hcr |= (hcr_el2 & HCR_TGE) != 0; | |
10344 | ||
0eeb17d6 GB |
10345 | /* Perform a table-lookup for the target EL given the current state */ |
10346 | target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; | |
10347 | ||
10348 | assert(target_el > 0); | |
10349 | ||
10350 | return target_el; | |
10351 | } | |
10352 | ||
fc6177af | 10353 | void arm_log_exception(CPUState *cs) |
b59f479b | 10354 | { |
fc6177af PM |
10355 | int idx = cs->exception_index; |
10356 | ||
b59f479b PMD |
10357 | if (qemu_loglevel_mask(CPU_LOG_INT)) { |
10358 | const char *exc = NULL; | |
10359 | static const char * const excnames[] = { | |
10360 | [EXCP_UDEF] = "Undefined Instruction", | |
10361 | [EXCP_SWI] = "SVC", | |
10362 | [EXCP_PREFETCH_ABORT] = "Prefetch Abort", | |
10363 | [EXCP_DATA_ABORT] = "Data Abort", | |
10364 | [EXCP_IRQ] = "IRQ", | |
10365 | [EXCP_FIQ] = "FIQ", | |
10366 | [EXCP_BKPT] = "Breakpoint", | |
10367 | [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit", | |
10368 | [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage", | |
10369 | [EXCP_HVC] = "Hypervisor Call", | |
10370 | [EXCP_HYP_TRAP] = "Hypervisor Trap", | |
10371 | [EXCP_SMC] = "Secure Monitor Call", | |
10372 | [EXCP_VIRQ] = "Virtual IRQ", | |
10373 | [EXCP_VFIQ] = "Virtual FIQ", | |
10374 | [EXCP_SEMIHOST] = "Semihosting call", | |
10375 | [EXCP_NOCP] = "v7M NOCP UsageFault", | |
10376 | [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", | |
10377 | [EXCP_STKOF] = "v8M STKOF UsageFault", | |
10378 | [EXCP_LAZYFP] = "v7M exception during lazy FP stacking", | |
10379 | [EXCP_LSERR] = "v8M LSERR UsageFault", | |
10380 | [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", | |
e5346292 | 10381 | [EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault", |
3c29632f | 10382 | [EXCP_VSERR] = "Virtual SERR", |
11b76fda | 10383 | [EXCP_GPC] = "Granule Protection Check", |
b59f479b PMD |
10384 | }; |
10385 | ||
10386 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | |
10387 | exc = excnames[idx]; | |
10388 | } | |
10389 | if (!exc) { | |
10390 | exc = "unknown"; | |
10391 | } | |
fc6177af PM |
10392 | qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s] on CPU %d\n", |
10393 | idx, exc, cs->cpu_index); | |
b59f479b PMD |
10394 | } |
10395 | } | |
10396 | ||
a356dacf | 10397 | /* |
7aab5a8c PMD |
10398 | * Function used to synchronize QEMU's AArch64 register set with AArch32 |
10399 | * register set. This is necessary when switching between AArch32 and AArch64 | |
10400 | * execution state. | |
a356dacf | 10401 | */ |
7aab5a8c | 10402 | void aarch64_sync_32_to_64(CPUARMState *env) |
9ee6e8bb | 10403 | { |
7aab5a8c PMD |
10404 | int i; |
10405 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
10406 | ||
10407 | /* We can blanket copy R[0:7] to X[0:7] */ | |
10408 | for (i = 0; i < 8; i++) { | |
10409 | env->xregs[i] = env->regs[i]; | |
fd592d89 | 10410 | } |
70d74660 | 10411 | |
9a223097 | 10412 | /* |
7aab5a8c PMD |
10413 | * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12. |
10414 | * Otherwise, they come from the banked user regs. | |
fd592d89 | 10415 | */ |
7aab5a8c PMD |
10416 | if (mode == ARM_CPU_MODE_FIQ) { |
10417 | for (i = 8; i < 13; i++) { | |
10418 | env->xregs[i] = env->usr_regs[i - 8]; | |
10419 | } | |
10420 | } else { | |
10421 | for (i = 8; i < 13; i++) { | |
10422 | env->xregs[i] = env->regs[i]; | |
10423 | } | |
fd592d89 | 10424 | } |
9ee6e8bb | 10425 | |
7aab5a8c PMD |
10426 | /* |
10427 | * Registers x13-x23 are the various mode SP and FP registers. Registers | |
10428 | * r13 and r14 are only copied if we are in that mode, otherwise we copy | |
10429 | * from the mode banked register. | |
10430 | */ | |
10431 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { | |
10432 | env->xregs[13] = env->regs[13]; | |
10433 | env->xregs[14] = env->regs[14]; | |
10434 | } else { | |
10435 | env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; | |
10436 | /* HYP is an exception in that it is copied from r14 */ | |
10437 | if (mode == ARM_CPU_MODE_HYP) { | |
10438 | env->xregs[14] = env->regs[14]; | |
95695eff | 10439 | } else { |
7aab5a8c | 10440 | env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)]; |
95695eff | 10441 | } |
95695eff PM |
10442 | } |
10443 | ||
7aab5a8c PMD |
10444 | if (mode == ARM_CPU_MODE_HYP) { |
10445 | env->xregs[15] = env->regs[13]; | |
10446 | } else { | |
10447 | env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; | |
95695eff PM |
10448 | } |
10449 | ||
7aab5a8c PMD |
10450 | if (mode == ARM_CPU_MODE_IRQ) { |
10451 | env->xregs[16] = env->regs[14]; | |
10452 | env->xregs[17] = env->regs[13]; | |
10453 | } else { | |
10454 | env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)]; | |
10455 | env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; | |
10456 | } | |
95695eff | 10457 | |
7aab5a8c PMD |
10458 | if (mode == ARM_CPU_MODE_SVC) { |
10459 | env->xregs[18] = env->regs[14]; | |
10460 | env->xregs[19] = env->regs[13]; | |
10461 | } else { | |
10462 | env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)]; | |
10463 | env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; | |
10464 | } | |
95695eff | 10465 | |
7aab5a8c PMD |
10466 | if (mode == ARM_CPU_MODE_ABT) { |
10467 | env->xregs[20] = env->regs[14]; | |
10468 | env->xregs[21] = env->regs[13]; | |
10469 | } else { | |
10470 | env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)]; | |
10471 | env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; | |
10472 | } | |
e33cf0f8 | 10473 | |
7aab5a8c PMD |
10474 | if (mode == ARM_CPU_MODE_UND) { |
10475 | env->xregs[22] = env->regs[14]; | |
10476 | env->xregs[23] = env->regs[13]; | |
10477 | } else { | |
10478 | env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)]; | |
10479 | env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; | |
e33cf0f8 PM |
10480 | } |
10481 | ||
10482 | /* | |
7aab5a8c PMD |
10483 | * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ |
10484 | * mode, then we can copy from r8-r14. Otherwise, we copy from the | |
10485 | * FIQ bank for r8-r14. | |
e33cf0f8 | 10486 | */ |
7aab5a8c PMD |
10487 | if (mode == ARM_CPU_MODE_FIQ) { |
10488 | for (i = 24; i < 31; i++) { | |
10489 | env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */ | |
10490 | } | |
10491 | } else { | |
10492 | for (i = 24; i < 29; i++) { | |
10493 | env->xregs[i] = env->fiq_regs[i - 24]; | |
e33cf0f8 | 10494 | } |
7aab5a8c PMD |
10495 | env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; |
10496 | env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)]; | |
e33cf0f8 | 10497 | } |
7aab5a8c PMD |
10498 | |
10499 | env->pc = env->regs[15]; | |
e33cf0f8 PM |
10500 | } |
10501 | ||
9a223097 | 10502 | /* |
7aab5a8c PMD |
10503 | * Function used to synchronize QEMU's AArch32 register set with AArch64 |
10504 | * register set. This is necessary when switching between AArch32 and AArch64 | |
10505 | * execution state. | |
de2db7ec | 10506 | */ |
7aab5a8c | 10507 | void aarch64_sync_64_to_32(CPUARMState *env) |
9ee6e8bb | 10508 | { |
7aab5a8c PMD |
10509 | int i; |
10510 | uint32_t mode = env->uncached_cpsr & CPSR_M; | |
abc24d86 | 10511 | |
7aab5a8c PMD |
10512 | /* We can blanket copy X[0:7] to R[0:7] */ |
10513 | for (i = 0; i < 8; i++) { | |
10514 | env->regs[i] = env->xregs[i]; | |
de2db7ec | 10515 | } |
3f0cddee | 10516 | |
9a223097 | 10517 | /* |
7aab5a8c PMD |
10518 | * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12. |
10519 | * Otherwise, we copy x8-x12 into the banked user regs. | |
de2db7ec | 10520 | */ |
7aab5a8c PMD |
10521 | if (mode == ARM_CPU_MODE_FIQ) { |
10522 | for (i = 8; i < 13; i++) { | |
10523 | env->usr_regs[i - 8] = env->xregs[i]; | |
10524 | } | |
10525 | } else { | |
10526 | for (i = 8; i < 13; i++) { | |
10527 | env->regs[i] = env->xregs[i]; | |
10528 | } | |
fb602cb7 PM |
10529 | } |
10530 | ||
9a223097 | 10531 | /* |
7aab5a8c PMD |
10532 | * Registers r13 & r14 depend on the current mode. |
10533 | * If we are in a given mode, we copy the corresponding x registers to r13 | |
10534 | * and r14. Otherwise, we copy the x register to the banked r13 and r14 | |
10535 | * for the mode. | |
fb602cb7 | 10536 | */ |
7aab5a8c PMD |
10537 | if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) { |
10538 | env->regs[13] = env->xregs[13]; | |
10539 | env->regs[14] = env->xregs[14]; | |
fb602cb7 | 10540 | } else { |
7aab5a8c | 10541 | env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13]; |
fb602cb7 | 10542 | |
7aab5a8c PMD |
10543 | /* |
10544 | * HYP is an exception in that it does not have its own banked r14 but | |
10545 | * shares the USR r14 | |
10546 | */ | |
10547 | if (mode == ARM_CPU_MODE_HYP) { | |
10548 | env->regs[14] = env->xregs[14]; | |
10549 | } else { | |
10550 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14]; | |
10551 | } | |
10552 | } | |
fb602cb7 | 10553 | |
7aab5a8c PMD |
10554 | if (mode == ARM_CPU_MODE_HYP) { |
10555 | env->regs[13] = env->xregs[15]; | |
fb602cb7 | 10556 | } else { |
7aab5a8c | 10557 | env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15]; |
fb602cb7 | 10558 | } |
d02a8698 | 10559 | |
7aab5a8c PMD |
10560 | if (mode == ARM_CPU_MODE_IRQ) { |
10561 | env->regs[14] = env->xregs[16]; | |
10562 | env->regs[13] = env->xregs[17]; | |
d02a8698 | 10563 | } else { |
7aab5a8c PMD |
10564 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16]; |
10565 | env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17]; | |
d02a8698 PM |
10566 | } |
10567 | ||
7aab5a8c PMD |
10568 | if (mode == ARM_CPU_MODE_SVC) { |
10569 | env->regs[14] = env->xregs[18]; | |
10570 | env->regs[13] = env->xregs[19]; | |
10571 | } else { | |
10572 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18]; | |
10573 | env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19]; | |
fb602cb7 PM |
10574 | } |
10575 | ||
7aab5a8c PMD |
10576 | if (mode == ARM_CPU_MODE_ABT) { |
10577 | env->regs[14] = env->xregs[20]; | |
10578 | env->regs[13] = env->xregs[21]; | |
10579 | } else { | |
10580 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20]; | |
10581 | env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21]; | |
ce02049d GB |
10582 | } |
10583 | ||
10584 | if (mode == ARM_CPU_MODE_UND) { | |
3a9148d0 SS |
10585 | env->regs[14] = env->xregs[22]; |
10586 | env->regs[13] = env->xregs[23]; | |
ce02049d | 10587 | } else { |
593cfa2b | 10588 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22]; |
3a9148d0 | 10589 | env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23]; |
ce02049d GB |
10590 | } |
10591 | ||
9b37a28c FR |
10592 | /* |
10593 | * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ | |
ce02049d GB |
10594 | * mode, then we can copy to r8-r14. Otherwise, we copy to the |
10595 | * FIQ bank for r8-r14. | |
10596 | */ | |
10597 | if (mode == ARM_CPU_MODE_FIQ) { | |
10598 | for (i = 24; i < 31; i++) { | |
10599 | env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */ | |
10600 | } | |
10601 | } else { | |
10602 | for (i = 24; i < 29; i++) { | |
10603 | env->fiq_regs[i - 24] = env->xregs[i]; | |
10604 | } | |
10605 | env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29]; | |
593cfa2b | 10606 | env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30]; |
ce02049d GB |
10607 | } |
10608 | ||
10609 | env->regs[15] = env->pc; | |
10610 | } | |
10611 | ||
dea8378b PM |
10612 | static void take_aarch32_exception(CPUARMState *env, int new_mode, |
10613 | uint32_t mask, uint32_t offset, | |
10614 | uint32_t newpc) | |
10615 | { | |
4a2696c0 RH |
10616 | int new_el; |
10617 | ||
dea8378b PM |
10618 | /* Change the CPU state so as to actually take the exception. */ |
10619 | switch_mode(env, new_mode); | |
4a2696c0 | 10620 | |
dea8378b PM |
10621 | /* |
10622 | * For exceptions taken to AArch32 we must clear the SS bit in both | |
10623 | * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. | |
10624 | */ | |
f944a854 | 10625 | env->pstate &= ~PSTATE_SS; |
dea8378b PM |
10626 | env->spsr = cpsr_read(env); |
10627 | /* Clear IT bits. */ | |
10628 | env->condexec_bits = 0; | |
10629 | /* Switch to the new mode, and to the correct instruction set. */ | |
10630 | env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; | |
88828bf1 CD |
10631 | |
10632 | /* This must be after mode switching. */ | |
10633 | new_el = arm_current_el(env); | |
10634 | ||
dea8378b PM |
10635 | /* Set new mode endianness */ |
10636 | env->uncached_cpsr &= ~CPSR_E; | |
4a2696c0 | 10637 | if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { |
dea8378b PM |
10638 | env->uncached_cpsr |= CPSR_E; |
10639 | } | |
829f9fd3 PM |
10640 | /* J and IL must always be cleared for exception entry */ |
10641 | env->uncached_cpsr &= ~(CPSR_IL | CPSR_J); | |
dea8378b PM |
10642 | env->daif |= mask; |
10643 | ||
f2f68a78 RC |
10644 | if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) { |
10645 | if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) { | |
10646 | env->uncached_cpsr |= CPSR_SSBS; | |
10647 | } else { | |
10648 | env->uncached_cpsr &= ~CPSR_SSBS; | |
10649 | } | |
10650 | } | |
10651 | ||
dea8378b PM |
10652 | if (new_mode == ARM_CPU_MODE_HYP) { |
10653 | env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0; | |
10654 | env->elr_el[2] = env->regs[15]; | |
10655 | } else { | |
4a2696c0 | 10656 | /* CPSR.PAN is normally preserved preserved unless... */ |
f8af1143 | 10657 | if (cpu_isar_feature(aa32_pan, env_archcpu(env))) { |
4a2696c0 RH |
10658 | switch (new_el) { |
10659 | case 3: | |
10660 | if (!arm_is_secure_below_el3(env)) { | |
10661 | /* ... the target is EL3, from non-secure state. */ | |
10662 | env->uncached_cpsr &= ~CPSR_PAN; | |
10663 | break; | |
10664 | } | |
10665 | /* ... the target is EL3, from secure state ... */ | |
10666 | /* fall through */ | |
10667 | case 1: | |
10668 | /* ... the target is EL1 and SCTLR.SPAN is 0. */ | |
10669 | if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { | |
10670 | env->uncached_cpsr |= CPSR_PAN; | |
10671 | } | |
10672 | break; | |
10673 | } | |
10674 | } | |
dea8378b PM |
10675 | /* |
10676 | * this is a lie, as there was no c1_sys on V4T/V5, but who cares | |
10677 | * and we should just guard the thumb mode on V4 | |
10678 | */ | |
10679 | if (arm_feature(env, ARM_FEATURE_V4T)) { | |
10680 | env->thumb = | |
10681 | (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0; | |
10682 | } | |
10683 | env->regs[14] = env->regs[15] + offset; | |
10684 | } | |
10685 | env->regs[15] = newpc; | |
2b77ad4d FR |
10686 | |
10687 | if (tcg_enabled()) { | |
10688 | arm_rebuild_hflags(env); | |
10689 | } | |
dea8378b PM |
10690 | } |
10691 | ||
b9bc21ff PM |
10692 | static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) |
10693 | { | |
10694 | /* | |
10695 | * Handle exception entry to Hyp mode; this is sufficiently | |
10696 | * different to entry to other AArch32 modes that we handle it | |
10697 | * separately here. | |
10698 | * | |
10699 | * The vector table entry used is always the 0x14 Hyp mode entry point, | |
2c023d36 | 10700 | * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp. |
b9bc21ff PM |
10701 | * The offset applied to the preferred return address is always zero |
10702 | * (see DDI0487C.a section G1.12.3). | |
10703 | * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. | |
10704 | */ | |
10705 | uint32_t addr, mask; | |
10706 | ARMCPU *cpu = ARM_CPU(cs); | |
10707 | CPUARMState *env = &cpu->env; | |
10708 | ||
10709 | switch (cs->exception_index) { | |
10710 | case EXCP_UDEF: | |
10711 | addr = 0x04; | |
10712 | break; | |
10713 | case EXCP_SWI: | |
2c023d36 | 10714 | addr = 0x08; |
b9bc21ff PM |
10715 | break; |
10716 | case EXCP_BKPT: | |
10717 | /* Fall through to prefetch abort. */ | |
10718 | case EXCP_PREFETCH_ABORT: | |
10719 | env->cp15.ifar_s = env->exception.vaddress; | |
10720 | qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n", | |
10721 | (uint32_t)env->exception.vaddress); | |
10722 | addr = 0x0c; | |
10723 | break; | |
10724 | case EXCP_DATA_ABORT: | |
10725 | env->cp15.dfar_s = env->exception.vaddress; | |
10726 | qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n", | |
10727 | (uint32_t)env->exception.vaddress); | |
10728 | addr = 0x10; | |
10729 | break; | |
10730 | case EXCP_IRQ: | |
10731 | addr = 0x18; | |
10732 | break; | |
10733 | case EXCP_FIQ: | |
10734 | addr = 0x1c; | |
10735 | break; | |
10736 | case EXCP_HVC: | |
10737 | addr = 0x08; | |
10738 | break; | |
10739 | case EXCP_HYP_TRAP: | |
10740 | addr = 0x14; | |
9bbb4ef9 | 10741 | break; |
b9bc21ff PM |
10742 | default: |
10743 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
10744 | } | |
10745 | ||
10746 | if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) { | |
2ed08180 PM |
10747 | if (!arm_feature(env, ARM_FEATURE_V8)) { |
10748 | /* | |
10749 | * QEMU syndrome values are v8-style. v7 has the IL bit | |
10750 | * UNK/SBZP for "field not valid" cases, where v8 uses RES1. | |
10751 | * If this is a v7 CPU, squash the IL bit in those cases. | |
10752 | */ | |
10753 | if (cs->exception_index == EXCP_PREFETCH_ABORT || | |
10754 | (cs->exception_index == EXCP_DATA_ABORT && | |
10755 | !(env->exception.syndrome & ARM_EL_ISV)) || | |
10756 | syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) { | |
10757 | env->exception.syndrome &= ~ARM_EL_IL; | |
10758 | } | |
10759 | } | |
b9bc21ff PM |
10760 | env->cp15.esr_el[2] = env->exception.syndrome; |
10761 | } | |
10762 | ||
10763 | if (arm_current_el(env) != 2 && addr < 0x14) { | |
10764 | addr = 0x14; | |
10765 | } | |
10766 | ||
10767 | mask = 0; | |
10768 | if (!(env->cp15.scr_el3 & SCR_EA)) { | |
10769 | mask |= CPSR_A; | |
10770 | } | |
10771 | if (!(env->cp15.scr_el3 & SCR_IRQ)) { | |
10772 | mask |= CPSR_I; | |
10773 | } | |
10774 | if (!(env->cp15.scr_el3 & SCR_FIQ)) { | |
10775 | mask |= CPSR_F; | |
10776 | } | |
10777 | ||
10778 | addr += env->cp15.hvbar; | |
10779 | ||
10780 | take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr); | |
10781 | } | |
10782 | ||
966f758c | 10783 | static void arm_cpu_do_interrupt_aarch32(CPUState *cs) |
b5ff1b31 | 10784 | { |
97a8ea5a AF |
10785 | ARMCPU *cpu = ARM_CPU(cs); |
10786 | CPUARMState *env = &cpu->env; | |
b5ff1b31 FB |
10787 | uint32_t addr; |
10788 | uint32_t mask; | |
10789 | int new_mode; | |
10790 | uint32_t offset; | |
16a906fd | 10791 | uint32_t moe; |
b5ff1b31 | 10792 | |
16a906fd | 10793 | /* If this is a debug exception we must update the DBGDSCR.MOE bits */ |
64b91e3f | 10794 | switch (syn_get_ec(env->exception.syndrome)) { |
16a906fd PM |
10795 | case EC_BREAKPOINT: |
10796 | case EC_BREAKPOINT_SAME_EL: | |
10797 | moe = 1; | |
10798 | break; | |
10799 | case EC_WATCHPOINT: | |
10800 | case EC_WATCHPOINT_SAME_EL: | |
10801 | moe = 10; | |
10802 | break; | |
10803 | case EC_AA32_BKPT: | |
10804 | moe = 3; | |
10805 | break; | |
10806 | case EC_VECTORCATCH: | |
10807 | moe = 5; | |
10808 | break; | |
10809 | default: | |
10810 | moe = 0; | |
10811 | break; | |
10812 | } | |
10813 | ||
10814 | if (moe) { | |
10815 | env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe); | |
10816 | } | |
10817 | ||
b9bc21ff PM |
10818 | if (env->exception.target_el == 2) { |
10819 | arm_cpu_do_interrupt_aarch32_hyp(cs); | |
10820 | return; | |
10821 | } | |
10822 | ||
27103424 | 10823 | switch (cs->exception_index) { |
b5ff1b31 FB |
10824 | case EXCP_UDEF: |
10825 | new_mode = ARM_CPU_MODE_UND; | |
10826 | addr = 0x04; | |
10827 | mask = CPSR_I; | |
f927dbda | 10828 | if (env->thumb) { |
b5ff1b31 | 10829 | offset = 2; |
f927dbda | 10830 | } else { |
b5ff1b31 | 10831 | offset = 4; |
f927dbda | 10832 | } |
b5ff1b31 FB |
10833 | break; |
10834 | case EXCP_SWI: | |
10835 | new_mode = ARM_CPU_MODE_SVC; | |
10836 | addr = 0x08; | |
10837 | mask = CPSR_I; | |
601d70b9 | 10838 | /* The PC already points to the next instruction. */ |
b5ff1b31 FB |
10839 | offset = 0; |
10840 | break; | |
06c949e6 | 10841 | case EXCP_BKPT: |
9ee6e8bb PB |
10842 | /* Fall through to prefetch abort. */ |
10843 | case EXCP_PREFETCH_ABORT: | |
88ca1c2d | 10844 | A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); |
b848ce2b | 10845 | A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); |
3f1beaca | 10846 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", |
88ca1c2d | 10847 | env->exception.fsr, (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
10848 | new_mode = ARM_CPU_MODE_ABT; |
10849 | addr = 0x0c; | |
10850 | mask = CPSR_A | CPSR_I; | |
10851 | offset = 4; | |
10852 | break; | |
10853 | case EXCP_DATA_ABORT: | |
4a7e2d73 | 10854 | A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); |
b848ce2b | 10855 | A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); |
3f1beaca | 10856 | qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", |
4a7e2d73 | 10857 | env->exception.fsr, |
6cd8a264 | 10858 | (uint32_t)env->exception.vaddress); |
b5ff1b31 FB |
10859 | new_mode = ARM_CPU_MODE_ABT; |
10860 | addr = 0x10; | |
10861 | mask = CPSR_A | CPSR_I; | |
10862 | offset = 8; | |
10863 | break; | |
10864 | case EXCP_IRQ: | |
10865 | new_mode = ARM_CPU_MODE_IRQ; | |
10866 | addr = 0x18; | |
10867 | /* Disable IRQ and imprecise data aborts. */ | |
10868 | mask = CPSR_A | CPSR_I; | |
10869 | offset = 4; | |
de38d23b FA |
10870 | if (env->cp15.scr_el3 & SCR_IRQ) { |
10871 | /* IRQ routed to monitor mode */ | |
10872 | new_mode = ARM_CPU_MODE_MON; | |
10873 | mask |= CPSR_F; | |
10874 | } | |
b5ff1b31 FB |
10875 | break; |
10876 | case EXCP_FIQ: | |
10877 | new_mode = ARM_CPU_MODE_FIQ; | |
10878 | addr = 0x1c; | |
10879 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
10880 | mask = CPSR_A | CPSR_I | CPSR_F; | |
de38d23b FA |
10881 | if (env->cp15.scr_el3 & SCR_FIQ) { |
10882 | /* FIQ routed to monitor mode */ | |
10883 | new_mode = ARM_CPU_MODE_MON; | |
10884 | } | |
b5ff1b31 FB |
10885 | offset = 4; |
10886 | break; | |
87a4b270 PM |
10887 | case EXCP_VIRQ: |
10888 | new_mode = ARM_CPU_MODE_IRQ; | |
10889 | addr = 0x18; | |
10890 | /* Disable IRQ and imprecise data aborts. */ | |
10891 | mask = CPSR_A | CPSR_I; | |
10892 | offset = 4; | |
10893 | break; | |
10894 | case EXCP_VFIQ: | |
10895 | new_mode = ARM_CPU_MODE_FIQ; | |
10896 | addr = 0x1c; | |
10897 | /* Disable FIQ, IRQ and imprecise data aborts. */ | |
10898 | mask = CPSR_A | CPSR_I | CPSR_F; | |
10899 | offset = 4; | |
10900 | break; | |
3c29632f RH |
10901 | case EXCP_VSERR: |
10902 | { | |
10903 | /* | |
10904 | * Note that this is reported as a data abort, but the DFAR | |
10905 | * has an UNKNOWN value. Construct the SError syndrome from | |
10906 | * AET and ExT fields. | |
10907 | */ | |
10908 | ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, }; | |
10909 | ||
10910 | if (extended_addresses_enabled(env)) { | |
10911 | env->exception.fsr = arm_fi_to_lfsc(&fi); | |
10912 | } else { | |
10913 | env->exception.fsr = arm_fi_to_sfsc(&fi); | |
10914 | } | |
10915 | env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000; | |
10916 | A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); | |
10917 | qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n", | |
10918 | env->exception.fsr); | |
10919 | ||
10920 | new_mode = ARM_CPU_MODE_ABT; | |
10921 | addr = 0x10; | |
10922 | mask = CPSR_A | CPSR_I; | |
10923 | offset = 8; | |
10924 | } | |
10925 | break; | |
dbe9d163 FA |
10926 | case EXCP_SMC: |
10927 | new_mode = ARM_CPU_MODE_MON; | |
10928 | addr = 0x08; | |
10929 | mask = CPSR_A | CPSR_I | CPSR_F; | |
10930 | offset = 0; | |
10931 | break; | |
b5ff1b31 | 10932 | default: |
a47dddd7 | 10933 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); |
b5ff1b31 FB |
10934 | return; /* Never happens. Keep compiler happy. */ |
10935 | } | |
e89e51a1 FA |
10936 | |
10937 | if (new_mode == ARM_CPU_MODE_MON) { | |
10938 | addr += env->cp15.mvbar; | |
137feaa9 | 10939 | } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { |
e89e51a1 | 10940 | /* High vectors. When enabled, base address cannot be remapped. */ |
b5ff1b31 | 10941 | addr += 0xffff0000; |
8641136c | 10942 | } else { |
9b37a28c FR |
10943 | /* |
10944 | * ARM v7 architectures provide a vector base address register to remap | |
8641136c | 10945 | * the interrupt vector table. |
e89e51a1 | 10946 | * This register is only followed in non-monitor mode, and is banked. |
8641136c NR |
10947 | * Note: only bits 31:5 are valid. |
10948 | */ | |
fb6c91ba | 10949 | addr += A32_BANKED_CURRENT_REG_GET(env, vbar); |
b5ff1b31 | 10950 | } |
dbe9d163 FA |
10951 | |
10952 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
10953 | env->cp15.scr_el3 &= ~SCR_NS; | |
10954 | } | |
10955 | ||
dea8378b | 10956 | take_aarch32_exception(env, new_mode, mask, offset, addr); |
b5ff1b31 FB |
10957 | } |
10958 | ||
a65dabf7 PM |
10959 | static int aarch64_regnum(CPUARMState *env, int aarch32_reg) |
10960 | { | |
10961 | /* | |
10962 | * Return the register number of the AArch64 view of the AArch32 | |
10963 | * register @aarch32_reg. The CPUARMState CPSR is assumed to still | |
10964 | * be that of the AArch32 mode the exception came from. | |
10965 | */ | |
10966 | int mode = env->uncached_cpsr & CPSR_M; | |
10967 | ||
10968 | switch (aarch32_reg) { | |
10969 | case 0 ... 7: | |
10970 | return aarch32_reg; | |
10971 | case 8 ... 12: | |
10972 | return mode == ARM_CPU_MODE_FIQ ? aarch32_reg + 16 : aarch32_reg; | |
10973 | case 13: | |
10974 | switch (mode) { | |
10975 | case ARM_CPU_MODE_USR: | |
10976 | case ARM_CPU_MODE_SYS: | |
10977 | return 13; | |
10978 | case ARM_CPU_MODE_HYP: | |
10979 | return 15; | |
10980 | case ARM_CPU_MODE_IRQ: | |
10981 | return 17; | |
10982 | case ARM_CPU_MODE_SVC: | |
10983 | return 19; | |
10984 | case ARM_CPU_MODE_ABT: | |
10985 | return 21; | |
10986 | case ARM_CPU_MODE_UND: | |
10987 | return 23; | |
10988 | case ARM_CPU_MODE_FIQ: | |
10989 | return 29; | |
10990 | default: | |
10991 | g_assert_not_reached(); | |
10992 | } | |
10993 | case 14: | |
10994 | switch (mode) { | |
10995 | case ARM_CPU_MODE_USR: | |
10996 | case ARM_CPU_MODE_SYS: | |
10997 | case ARM_CPU_MODE_HYP: | |
10998 | return 14; | |
10999 | case ARM_CPU_MODE_IRQ: | |
11000 | return 16; | |
11001 | case ARM_CPU_MODE_SVC: | |
11002 | return 18; | |
11003 | case ARM_CPU_MODE_ABT: | |
11004 | return 20; | |
11005 | case ARM_CPU_MODE_UND: | |
11006 | return 22; | |
11007 | case ARM_CPU_MODE_FIQ: | |
11008 | return 30; | |
11009 | default: | |
11010 | g_assert_not_reached(); | |
11011 | } | |
11012 | case 15: | |
11013 | return 31; | |
11014 | default: | |
11015 | g_assert_not_reached(); | |
11016 | } | |
11017 | } | |
11018 | ||
f944a854 RC |
11019 | static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env) |
11020 | { | |
11021 | uint32_t ret = cpsr_read(env); | |
11022 | ||
11023 | /* Move DIT to the correct location for SPSR_ELx */ | |
11024 | if (ret & CPSR_DIT) { | |
11025 | ret &= ~CPSR_DIT; | |
11026 | ret |= PSTATE_DIT; | |
11027 | } | |
11028 | /* Merge PSTATE.SS into SPSR_ELx */ | |
11029 | ret |= env->pstate & PSTATE_SS; | |
11030 | ||
11031 | return ret; | |
11032 | } | |
11033 | ||
7ac61020 PM |
11034 | static bool syndrome_is_sync_extabt(uint32_t syndrome) |
11035 | { | |
11036 | /* Return true if this syndrome value is a synchronous external abort */ | |
11037 | switch (syn_get_ec(syndrome)) { | |
11038 | case EC_INSNABORT: | |
11039 | case EC_INSNABORT_SAME_EL: | |
11040 | case EC_DATAABORT: | |
11041 | case EC_DATAABORT_SAME_EL: | |
11042 | /* Look at fault status code for all the synchronous ext abort cases */ | |
11043 | switch (syndrome & 0x3f) { | |
11044 | case 0x10: | |
11045 | case 0x13: | |
11046 | case 0x14: | |
11047 | case 0x15: | |
11048 | case 0x16: | |
11049 | case 0x17: | |
11050 | return true; | |
11051 | default: | |
11052 | return false; | |
11053 | } | |
11054 | default: | |
11055 | return false; | |
11056 | } | |
11057 | } | |
11058 | ||
966f758c PM |
11059 | /* Handle exception entry to a target EL which is using AArch64 */ |
11060 | static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | |
f3a9b694 PM |
11061 | { |
11062 | ARMCPU *cpu = ARM_CPU(cs); | |
11063 | CPUARMState *env = &cpu->env; | |
11064 | unsigned int new_el = env->exception.target_el; | |
11065 | target_ulong addr = env->cp15.vbar_el[new_el]; | |
11066 | unsigned int new_mode = aarch64_pstate_mode(new_el, true); | |
4a2696c0 | 11067 | unsigned int old_mode; |
0ab5953b | 11068 | unsigned int cur_el = arm_current_el(env); |
a65dabf7 | 11069 | int rt; |
0ab5953b | 11070 | |
d55b2a2a CF |
11071 | if (tcg_enabled()) { |
11072 | /* | |
11073 | * Note that new_el can never be 0. If cur_el is 0, then | |
11074 | * el0_a64 is is_a64(), else el0_a64 is ignored. | |
11075 | */ | |
11076 | aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); | |
11077 | } | |
f3a9b694 | 11078 | |
0ab5953b | 11079 | if (cur_el < new_el) { |
9b37a28c FR |
11080 | /* |
11081 | * Entry vector offset depends on whether the implemented EL | |
3d6f7617 PM |
11082 | * immediately lower than the target level is using AArch32 or AArch64 |
11083 | */ | |
11084 | bool is_aa64; | |
cb092fbb | 11085 | uint64_t hcr; |
3d6f7617 PM |
11086 | |
11087 | switch (new_el) { | |
11088 | case 3: | |
11089 | is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0; | |
11090 | break; | |
11091 | case 2: | |
cb092fbb RH |
11092 | hcr = arm_hcr_el2_eff(env); |
11093 | if ((hcr & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { | |
11094 | is_aa64 = (hcr & HCR_RW) != 0; | |
11095 | break; | |
11096 | } | |
11097 | /* fall through */ | |
3d6f7617 PM |
11098 | case 1: |
11099 | is_aa64 = is_a64(env); | |
11100 | break; | |
11101 | default: | |
11102 | g_assert_not_reached(); | |
11103 | } | |
11104 | ||
11105 | if (is_aa64) { | |
f3a9b694 PM |
11106 | addr += 0x400; |
11107 | } else { | |
11108 | addr += 0x600; | |
11109 | } | |
11110 | } else if (pstate_read(env) & PSTATE_SP) { | |
11111 | addr += 0x200; | |
11112 | } | |
11113 | ||
f3a9b694 | 11114 | switch (cs->exception_index) { |
11b76fda RH |
11115 | case EXCP_GPC: |
11116 | qemu_log_mask(CPU_LOG_INT, "...with MFAR 0x%" PRIx64 "\n", | |
11117 | env->cp15.mfar_el3); | |
11118 | /* fall through */ | |
f3a9b694 PM |
11119 | case EXCP_PREFETCH_ABORT: |
11120 | case EXCP_DATA_ABORT: | |
7ac61020 PM |
11121 | /* |
11122 | * FEAT_DoubleFault allows synchronous external aborts taken to EL3 | |
11123 | * to be taken to the SError vector entrypoint. | |
11124 | */ | |
11125 | if (new_el == 3 && (env->cp15.scr_el3 & SCR_EASE) && | |
11126 | syndrome_is_sync_extabt(env->exception.syndrome)) { | |
11127 | addr += 0x180; | |
11128 | } | |
f3a9b694 PM |
11129 | env->cp15.far_el[new_el] = env->exception.vaddress; |
11130 | qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", | |
11131 | env->cp15.far_el[new_el]); | |
11132 | /* fall through */ | |
11133 | case EXCP_BKPT: | |
11134 | case EXCP_UDEF: | |
11135 | case EXCP_SWI: | |
11136 | case EXCP_HVC: | |
11137 | case EXCP_HYP_TRAP: | |
11138 | case EXCP_SMC: | |
a65dabf7 PM |
11139 | switch (syn_get_ec(env->exception.syndrome)) { |
11140 | case EC_ADVSIMDFPACCESSTRAP: | |
4be42f40 PM |
11141 | /* |
11142 | * QEMU internal FP/SIMD syndromes from AArch32 include the | |
11143 | * TA and coproc fields which are only exposed if the exception | |
11144 | * is taken to AArch32 Hyp mode. Mask them out to get a valid | |
11145 | * AArch64 format syndrome. | |
11146 | */ | |
11147 | env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20); | |
a65dabf7 PM |
11148 | break; |
11149 | case EC_CP14RTTRAP: | |
11150 | case EC_CP15RTTRAP: | |
11151 | case EC_CP14DTTRAP: | |
11152 | /* | |
11153 | * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently | |
11154 | * the raw register field from the insn; when taking this to | |
11155 | * AArch64 we must convert it to the AArch64 view of the register | |
11156 | * number. Notice that we read a 4-bit AArch32 register number and | |
11157 | * write back a 5-bit AArch64 one. | |
11158 | */ | |
11159 | rt = extract32(env->exception.syndrome, 5, 4); | |
11160 | rt = aarch64_regnum(env, rt); | |
11161 | env->exception.syndrome = deposit32(env->exception.syndrome, | |
11162 | 5, 5, rt); | |
11163 | break; | |
11164 | case EC_CP15RRTTRAP: | |
11165 | case EC_CP14RRTTRAP: | |
11166 | /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */ | |
11167 | rt = extract32(env->exception.syndrome, 5, 4); | |
11168 | rt = aarch64_regnum(env, rt); | |
11169 | env->exception.syndrome = deposit32(env->exception.syndrome, | |
11170 | 5, 5, rt); | |
11171 | rt = extract32(env->exception.syndrome, 10, 4); | |
11172 | rt = aarch64_regnum(env, rt); | |
11173 | env->exception.syndrome = deposit32(env->exception.syndrome, | |
11174 | 10, 5, rt); | |
11175 | break; | |
4be42f40 | 11176 | } |
f3a9b694 PM |
11177 | env->cp15.esr_el[new_el] = env->exception.syndrome; |
11178 | break; | |
11179 | case EXCP_IRQ: | |
11180 | case EXCP_VIRQ: | |
11181 | addr += 0x80; | |
11182 | break; | |
11183 | case EXCP_FIQ: | |
11184 | case EXCP_VFIQ: | |
11185 | addr += 0x100; | |
11186 | break; | |
3c29632f RH |
11187 | case EXCP_VSERR: |
11188 | addr += 0x180; | |
11189 | /* Construct the SError syndrome from IDS and ISS fields. */ | |
11190 | env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff); | |
11191 | env->cp15.esr_el[new_el] = env->exception.syndrome; | |
11192 | break; | |
f3a9b694 PM |
11193 | default: |
11194 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | |
11195 | } | |
11196 | ||
11197 | if (is_a64(env)) { | |
4a2696c0 | 11198 | old_mode = pstate_read(env); |
f3a9b694 PM |
11199 | aarch64_save_sp(env, arm_current_el(env)); |
11200 | env->elr_el[new_el] = env->pc; | |
11201 | } else { | |
f944a854 | 11202 | old_mode = cpsr_read_for_spsr_elx(env); |
f3a9b694 PM |
11203 | env->elr_el[new_el] = env->regs[15]; |
11204 | ||
11205 | aarch64_sync_32_to_64(env); | |
11206 | ||
11207 | env->condexec_bits = 0; | |
11208 | } | |
4a2696c0 RH |
11209 | env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode; |
11210 | ||
f3a9b694 PM |
11211 | qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", |
11212 | env->elr_el[new_el]); | |
11213 | ||
4a2696c0 RH |
11214 | if (cpu_isar_feature(aa64_pan, cpu)) { |
11215 | /* The value of PSTATE.PAN is normally preserved, except when ... */ | |
11216 | new_mode |= old_mode & PSTATE_PAN; | |
11217 | switch (new_el) { | |
11218 | case 2: | |
11219 | /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */ | |
11220 | if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) | |
11221 | != (HCR_E2H | HCR_TGE)) { | |
11222 | break; | |
11223 | } | |
11224 | /* fall through */ | |
11225 | case 1: | |
11226 | /* ... the target is EL1 ... */ | |
11227 | /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */ | |
11228 | if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) == 0) { | |
11229 | new_mode |= PSTATE_PAN; | |
11230 | } | |
11231 | break; | |
11232 | } | |
11233 | } | |
34669338 RH |
11234 | if (cpu_isar_feature(aa64_mte, cpu)) { |
11235 | new_mode |= PSTATE_TCO; | |
11236 | } | |
4a2696c0 | 11237 | |
f2f68a78 RC |
11238 | if (cpu_isar_feature(aa64_ssbs, cpu)) { |
11239 | if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) { | |
11240 | new_mode |= PSTATE_SSBS; | |
11241 | } else { | |
11242 | new_mode &= ~PSTATE_SSBS; | |
11243 | } | |
11244 | } | |
11245 | ||
f3a9b694 | 11246 | pstate_write(env, PSTATE_DAIF | new_mode); |
53221552 | 11247 | env->aarch64 = true; |
f3a9b694 | 11248 | aarch64_restore_sp(env, new_el); |
2b77ad4d FR |
11249 | |
11250 | if (tcg_enabled()) { | |
11251 | helper_rebuild_hflags_a64(env, new_el); | |
11252 | } | |
f3a9b694 PM |
11253 | |
11254 | env->pc = addr; | |
11255 | ||
11256 | qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", | |
11257 | new_el, env->pc, pstate_read(env)); | |
966f758c PM |
11258 | } |
11259 | ||
ed6e6ba9 AB |
11260 | /* |
11261 | * Do semihosting call and set the appropriate return value. All the | |
11262 | * permission and validity checks have been done at translate time. | |
11263 | * | |
11264 | * We only see semihosting exceptions in TCG only as they are not | |
11265 | * trapped to the hypervisor in KVM. | |
11266 | */ | |
91f78c58 | 11267 | #ifdef CONFIG_TCG |
a06e3a68 | 11268 | static void tcg_handle_semihosting(CPUState *cs) |
ed6e6ba9 | 11269 | { |
904c04de PM |
11270 | ARMCPU *cpu = ARM_CPU(cs); |
11271 | CPUARMState *env = &cpu->env; | |
11272 | ||
11273 | if (is_a64(env)) { | |
ed6e6ba9 AB |
11274 | qemu_log_mask(CPU_LOG_INT, |
11275 | "...handling as semihosting call 0x%" PRIx64 "\n", | |
11276 | env->xregs[0]); | |
ed3a06b1 | 11277 | do_common_semihosting(cs); |
4ff5ef9e | 11278 | env->pc += 4; |
904c04de | 11279 | } else { |
904c04de PM |
11280 | qemu_log_mask(CPU_LOG_INT, |
11281 | "...handling as semihosting call 0x%x\n", | |
11282 | env->regs[0]); | |
ed3a06b1 | 11283 | do_common_semihosting(cs); |
4ff5ef9e | 11284 | env->regs[15] += env->thumb ? 2 : 4; |
904c04de PM |
11285 | } |
11286 | } | |
ed6e6ba9 | 11287 | #endif |
904c04de | 11288 | |
9b37a28c FR |
11289 | /* |
11290 | * Handle a CPU exception for A and R profile CPUs. | |
966f758c PM |
11291 | * Do any appropriate logging, handle PSCI calls, and then hand off |
11292 | * to the AArch64-entry or AArch32-entry function depending on the | |
11293 | * target exception level's register width. | |
853bfef4 CF |
11294 | * |
11295 | * Note: this is used for both TCG (as the do_interrupt tcg op), | |
11296 | * and KVM to re-inject guest debug exceptions, and to | |
11297 | * inject a Synchronous-External-Abort. | |
966f758c PM |
11298 | */ |
11299 | void arm_cpu_do_interrupt(CPUState *cs) | |
11300 | { | |
11301 | ARMCPU *cpu = ARM_CPU(cs); | |
11302 | CPUARMState *env = &cpu->env; | |
11303 | unsigned int new_el = env->exception.target_el; | |
11304 | ||
531c60a9 | 11305 | assert(!arm_feature(env, ARM_FEATURE_M)); |
966f758c | 11306 | |
fc6177af | 11307 | arm_log_exception(cs); |
966f758c PM |
11308 | qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), |
11309 | new_el); | |
11310 | if (qemu_loglevel_mask(CPU_LOG_INT) | |
11311 | && !excp_is_internal(cs->exception_index)) { | |
6568da45 | 11312 | qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", |
64b91e3f | 11313 | syn_get_ec(env->exception.syndrome), |
966f758c PM |
11314 | env->exception.syndrome); |
11315 | } | |
11316 | ||
0c1aaa66 | 11317 | if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) { |
966f758c PM |
11318 | arm_handle_psci_call(cpu); |
11319 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | |
11320 | return; | |
11321 | } | |
11322 | ||
ed6e6ba9 AB |
11323 | /* |
11324 | * Semihosting semantics depend on the register width of the code | |
11325 | * that caused the exception, not the target exception level, so | |
11326 | * must be handled here. | |
966f758c | 11327 | */ |
ed6e6ba9 AB |
11328 | #ifdef CONFIG_TCG |
11329 | if (cs->exception_index == EXCP_SEMIHOST) { | |
a06e3a68 | 11330 | tcg_handle_semihosting(cs); |
904c04de PM |
11331 | return; |
11332 | } | |
ed6e6ba9 | 11333 | #endif |
904c04de | 11334 | |
9b37a28c FR |
11335 | /* |
11336 | * Hooks may change global state so BQL should be held, also the | |
b5c53d1b AL |
11337 | * BQL needs to be held for any modification of |
11338 | * cs->interrupt_request. | |
11339 | */ | |
195801d7 | 11340 | g_assert(bql_locked()); |
b5c53d1b AL |
11341 | |
11342 | arm_call_pre_el_change_hook(cpu); | |
11343 | ||
904c04de PM |
11344 | assert(!excp_is_internal(cs->exception_index)); |
11345 | if (arm_el_is_aa64(env, new_el)) { | |
966f758c PM |
11346 | arm_cpu_do_interrupt_aarch64(cs); |
11347 | } else { | |
11348 | arm_cpu_do_interrupt_aarch32(cs); | |
11349 | } | |
f3a9b694 | 11350 | |
bd7d00fc PM |
11351 | arm_call_el_change_hook(cpu); |
11352 | ||
f3a9b694 PM |
11353 | if (!kvm_enabled()) { |
11354 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
11355 | } | |
11356 | } | |
c47eaf9f | 11357 | #endif /* !CONFIG_USER_ONLY */ |
0480f69a | 11358 | |
aaec1432 RH |
11359 | uint64_t arm_sctlr(CPUARMState *env, int el) |
11360 | { | |
11361 | /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ | |
11362 | if (el == 0) { | |
11363 | ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0); | |
d902ae75 | 11364 | el = mmu_idx == ARMMMUIdx_E20_0 ? 2 : 1; |
aaec1432 RH |
11365 | } |
11366 | return env->cp15.sctlr_el[el]; | |
11367 | } | |
c47eaf9f | 11368 | |
8ae08860 | 11369 | int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) |
b830a5ee RH |
11370 | { |
11371 | if (regime_has_2_ranges(mmu_idx)) { | |
11372 | return extract64(tcr, 37, 2); | |
edc05dd4 | 11373 | } else if (regime_is_stage2(mmu_idx)) { |
b830a5ee RH |
11374 | return 0; /* VTCR_EL2 */ |
11375 | } else { | |
3e270f67 RH |
11376 | /* Replicate the single TBI bit so we always have 2 bits. */ |
11377 | return extract32(tcr, 20, 1) * 3; | |
b830a5ee RH |
11378 | } |
11379 | } | |
11380 | ||
8ae08860 | 11381 | int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) |
b830a5ee RH |
11382 | { |
11383 | if (regime_has_2_ranges(mmu_idx)) { | |
11384 | return extract64(tcr, 51, 2); | |
edc05dd4 | 11385 | } else if (regime_is_stage2(mmu_idx)) { |
b830a5ee RH |
11386 | return 0; /* VTCR_EL2 */ |
11387 | } else { | |
3e270f67 RH |
11388 | /* Replicate the single TBID bit so we always have 2 bits. */ |
11389 | return extract32(tcr, 29, 1) * 3; | |
b830a5ee RH |
11390 | } |
11391 | } | |
11392 | ||
671efad1 | 11393 | int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx) |
81ae05fa RH |
11394 | { |
11395 | if (regime_has_2_ranges(mmu_idx)) { | |
11396 | return extract64(tcr, 57, 2); | |
11397 | } else { | |
11398 | /* Replicate the single TCMA bit so we always have 2 bits. */ | |
11399 | return extract32(tcr, 30, 1) * 3; | |
11400 | } | |
11401 | } | |
11402 | ||
104f703d PM |
11403 | static ARMGranuleSize tg0_to_gran_size(int tg) |
11404 | { | |
11405 | switch (tg) { | |
11406 | case 0: | |
11407 | return Gran4K; | |
11408 | case 1: | |
11409 | return Gran64K; | |
11410 | case 2: | |
11411 | return Gran16K; | |
11412 | default: | |
11413 | return GranInvalid; | |
11414 | } | |
11415 | } | |
11416 | ||
11417 | static ARMGranuleSize tg1_to_gran_size(int tg) | |
11418 | { | |
11419 | switch (tg) { | |
11420 | case 1: | |
11421 | return Gran16K; | |
11422 | case 2: | |
11423 | return Gran4K; | |
11424 | case 3: | |
11425 | return Gran64K; | |
11426 | default: | |
11427 | return GranInvalid; | |
11428 | } | |
11429 | } | |
11430 | ||
11431 | static inline bool have4k(ARMCPU *cpu, bool stage2) | |
11432 | { | |
11433 | return stage2 ? cpu_isar_feature(aa64_tgran4_2, cpu) | |
11434 | : cpu_isar_feature(aa64_tgran4, cpu); | |
11435 | } | |
11436 | ||
11437 | static inline bool have16k(ARMCPU *cpu, bool stage2) | |
11438 | { | |
11439 | return stage2 ? cpu_isar_feature(aa64_tgran16_2, cpu) | |
11440 | : cpu_isar_feature(aa64_tgran16, cpu); | |
11441 | } | |
11442 | ||
11443 | static inline bool have64k(ARMCPU *cpu, bool stage2) | |
11444 | { | |
11445 | return stage2 ? cpu_isar_feature(aa64_tgran64_2, cpu) | |
11446 | : cpu_isar_feature(aa64_tgran64, cpu); | |
11447 | } | |
11448 | ||
11449 | static ARMGranuleSize sanitize_gran_size(ARMCPU *cpu, ARMGranuleSize gran, | |
11450 | bool stage2) | |
11451 | { | |
11452 | switch (gran) { | |
11453 | case Gran4K: | |
11454 | if (have4k(cpu, stage2)) { | |
11455 | return gran; | |
11456 | } | |
11457 | break; | |
11458 | case Gran16K: | |
11459 | if (have16k(cpu, stage2)) { | |
11460 | return gran; | |
11461 | } | |
11462 | break; | |
11463 | case Gran64K: | |
11464 | if (have64k(cpu, stage2)) { | |
11465 | return gran; | |
11466 | } | |
11467 | break; | |
11468 | case GranInvalid: | |
11469 | break; | |
11470 | } | |
11471 | /* | |
11472 | * If the guest selects a granule size that isn't implemented, | |
11473 | * the architecture requires that we behave as if it selected one | |
11474 | * that is (with an IMPDEF choice of which one to pick). We choose | |
11475 | * to implement the smallest supported granule size. | |
11476 | */ | |
11477 | if (have4k(cpu, stage2)) { | |
11478 | return Gran4K; | |
11479 | } | |
11480 | if (have16k(cpu, stage2)) { | |
11481 | return Gran16K; | |
11482 | } | |
11483 | assert(have64k(cpu, stage2)); | |
11484 | return Gran64K; | |
11485 | } | |
11486 | ||
b830a5ee | 11487 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, |
478dccbb PM |
11488 | ARMMMUIdx mmu_idx, bool data, |
11489 | bool el1_is_aa32) | |
ba97be9f | 11490 | { |
c1547bba | 11491 | uint64_t tcr = regime_tcr(env, mmu_idx); |
89739227 | 11492 | bool epd, hpd, tsz_oob, ds, ha, hd; |
ef56c242 | 11493 | int select, tsz, tbi, max_tsz, min_tsz, ps, sh; |
104f703d | 11494 | ARMGranuleSize gran; |
ef56c242 | 11495 | ARMCPU *cpu = env_archcpu(env); |
edc05dd4 | 11496 | bool stage2 = regime_is_stage2(mmu_idx); |
ba97be9f | 11497 | |
339370b9 | 11498 | if (!regime_has_2_ranges(mmu_idx)) { |
71d18164 | 11499 | select = 0; |
ba97be9f | 11500 | tsz = extract32(tcr, 0, 6); |
104f703d PM |
11501 | gran = tg0_to_gran_size(extract32(tcr, 14, 2)); |
11502 | if (stage2) { | |
ba97be9f | 11503 | /* VTCR_EL2 */ |
b830a5ee | 11504 | hpd = false; |
ba97be9f | 11505 | } else { |
ba97be9f RH |
11506 | hpd = extract32(tcr, 24, 1); |
11507 | } | |
11508 | epd = false; | |
ef56c242 | 11509 | sh = extract32(tcr, 12, 2); |
f4ecc015 | 11510 | ps = extract32(tcr, 16, 3); |
89739227 RH |
11511 | ha = extract32(tcr, 21, 1) && cpu_isar_feature(aa64_hafs, cpu); |
11512 | hd = extract32(tcr, 22, 1) && cpu_isar_feature(aa64_hdbs, cpu); | |
ef56c242 | 11513 | ds = extract64(tcr, 32, 1); |
ba97be9f | 11514 | } else { |
e4c93e44 PM |
11515 | bool e0pd; |
11516 | ||
71d18164 RH |
11517 | /* |
11518 | * Bit 55 is always between the two regions, and is canonical for | |
11519 | * determining if address tagging is enabled. | |
11520 | */ | |
11521 | select = extract64(va, 55, 1); | |
11522 | if (!select) { | |
11523 | tsz = extract32(tcr, 0, 6); | |
104f703d | 11524 | gran = tg0_to_gran_size(extract32(tcr, 14, 2)); |
71d18164 | 11525 | epd = extract32(tcr, 7, 1); |
ef56c242 | 11526 | sh = extract32(tcr, 12, 2); |
71d18164 | 11527 | hpd = extract64(tcr, 41, 1); |
e4c93e44 | 11528 | e0pd = extract64(tcr, 55, 1); |
71d18164 | 11529 | } else { |
71d18164 | 11530 | tsz = extract32(tcr, 16, 6); |
104f703d | 11531 | gran = tg1_to_gran_size(extract32(tcr, 30, 2)); |
71d18164 | 11532 | epd = extract32(tcr, 23, 1); |
ef56c242 | 11533 | sh = extract32(tcr, 28, 2); |
71d18164 | 11534 | hpd = extract64(tcr, 42, 1); |
e4c93e44 | 11535 | e0pd = extract64(tcr, 56, 1); |
71d18164 | 11536 | } |
f4ecc015 | 11537 | ps = extract64(tcr, 32, 3); |
89739227 RH |
11538 | ha = extract64(tcr, 39, 1) && cpu_isar_feature(aa64_hafs, cpu); |
11539 | hd = extract64(tcr, 40, 1) && cpu_isar_feature(aa64_hdbs, cpu); | |
ef56c242 | 11540 | ds = extract64(tcr, 59, 1); |
e4c93e44 PM |
11541 | |
11542 | if (e0pd && cpu_isar_feature(aa64_e0pd, cpu) && | |
11543 | regime_is_user(env, mmu_idx)) { | |
11544 | epd = true; | |
11545 | } | |
ba97be9f | 11546 | } |
c36c65ea | 11547 | |
104f703d | 11548 | gran = sanitize_gran_size(cpu, gran, stage2); |
104f703d | 11549 | |
ef56c242 | 11550 | if (cpu_isar_feature(aa64_st, cpu)) { |
3c003f70 | 11551 | max_tsz = 48 - (gran == Gran64K); |
c36c65ea RDC |
11552 | } else { |
11553 | max_tsz = 39; | |
11554 | } | |
0af312b6 | 11555 | |
ef56c242 RH |
11556 | /* |
11557 | * DS is RES0 unless FEAT_LPA2 is supported for the given page size; | |
11558 | * adjust the effective value of DS, as documented. | |
11559 | */ | |
0af312b6 | 11560 | min_tsz = 16; |
3c003f70 | 11561 | if (gran == Gran64K) { |
ef56c242 RH |
11562 | if (cpu_isar_feature(aa64_lva, cpu)) { |
11563 | min_tsz = 12; | |
11564 | } | |
11565 | ds = false; | |
11566 | } else if (ds) { | |
edc05dd4 | 11567 | if (regime_is_stage2(mmu_idx)) { |
3c003f70 | 11568 | if (gran == Gran16K) { |
ef56c242 RH |
11569 | ds = cpu_isar_feature(aa64_tgran16_2_lpa2, cpu); |
11570 | } else { | |
11571 | ds = cpu_isar_feature(aa64_tgran4_2_lpa2, cpu); | |
11572 | } | |
edc05dd4 | 11573 | } else { |
3c003f70 | 11574 | if (gran == Gran16K) { |
ef56c242 RH |
11575 | ds = cpu_isar_feature(aa64_tgran16_lpa2, cpu); |
11576 | } else { | |
11577 | ds = cpu_isar_feature(aa64_tgran4_lpa2, cpu); | |
11578 | } | |
ef56c242 RH |
11579 | } |
11580 | if (ds) { | |
0af312b6 RH |
11581 | min_tsz = 12; |
11582 | } | |
11583 | } | |
c36c65ea | 11584 | |
478dccbb PM |
11585 | if (stage2 && el1_is_aa32) { |
11586 | /* | |
11587 | * For AArch32 EL1 the min txsz (and thus max IPA size) requirements | |
11588 | * are loosened: a configured IPA of 40 bits is permitted even if | |
11589 | * the implemented PA is less than that (and so a 40 bit IPA would | |
11590 | * fault for an AArch64 EL1). See R_DTLMN. | |
11591 | */ | |
11592 | min_tsz = MIN(min_tsz, 24); | |
11593 | } | |
11594 | ||
ebf93ce7 RH |
11595 | if (tsz > max_tsz) { |
11596 | tsz = max_tsz; | |
11597 | tsz_oob = true; | |
11598 | } else if (tsz < min_tsz) { | |
11599 | tsz = min_tsz; | |
11600 | tsz_oob = true; | |
11601 | } else { | |
11602 | tsz_oob = false; | |
11603 | } | |
ba97be9f | 11604 | |
b830a5ee RH |
11605 | /* Present TBI as a composite with TBID. */ |
11606 | tbi = aa64_va_parameter_tbi(tcr, mmu_idx); | |
11607 | if (!data) { | |
11608 | tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx); | |
11609 | } | |
11610 | tbi = (tbi >> select) & 1; | |
11611 | ||
ba97be9f RH |
11612 | return (ARMVAParameters) { |
11613 | .tsz = tsz, | |
f4ecc015 | 11614 | .ps = ps, |
ef56c242 | 11615 | .sh = sh, |
ba97be9f RH |
11616 | .select = select, |
11617 | .tbi = tbi, | |
11618 | .epd = epd, | |
11619 | .hpd = hpd, | |
ebf93ce7 | 11620 | .tsz_oob = tsz_oob, |
ef56c242 | 11621 | .ds = ds, |
89739227 RH |
11622 | .ha = ha, |
11623 | .hd = ha && hd, | |
3c003f70 | 11624 | .gran = gran, |
ba97be9f RH |
11625 | }; |
11626 | } | |
11627 | ||
9b37a28c FR |
11628 | /* |
11629 | * Note that signed overflow is undefined in C. The following routines are | |
11630 | * careful to use unsigned types where modulo arithmetic is required. | |
11631 | * Failure to do so _will_ break on newer gcc. | |
11632 | */ | |
6ddbc6e4 PB |
11633 | |
11634 | /* Signed saturating arithmetic. */ | |
11635 | ||
1654b2d6 | 11636 | /* Perform 16-bit signed saturating addition. */ |
6ddbc6e4 PB |
11637 | static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
11638 | { | |
11639 | uint16_t res; | |
11640 | ||
11641 | res = a + b; | |
11642 | if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | |
f927dbda | 11643 | if (a & 0x8000) { |
6ddbc6e4 | 11644 | res = 0x8000; |
f927dbda | 11645 | } else { |
6ddbc6e4 | 11646 | res = 0x7fff; |
f927dbda | 11647 | } |
6ddbc6e4 PB |
11648 | } |
11649 | return res; | |
11650 | } | |
11651 | ||
1654b2d6 | 11652 | /* Perform 8-bit signed saturating addition. */ |
6ddbc6e4 PB |
11653 | static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
11654 | { | |
11655 | uint8_t res; | |
11656 | ||
11657 | res = a + b; | |
11658 | if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | |
f927dbda | 11659 | if (a & 0x80) { |
6ddbc6e4 | 11660 | res = 0x80; |
f927dbda | 11661 | } else { |
6ddbc6e4 | 11662 | res = 0x7f; |
f927dbda | 11663 | } |
6ddbc6e4 PB |
11664 | } |
11665 | return res; | |
11666 | } | |
11667 | ||
1654b2d6 | 11668 | /* Perform 16-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
11669 | static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
11670 | { | |
11671 | uint16_t res; | |
11672 | ||
11673 | res = a - b; | |
11674 | if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | |
f927dbda | 11675 | if (a & 0x8000) { |
6ddbc6e4 | 11676 | res = 0x8000; |
f927dbda | 11677 | } else { |
6ddbc6e4 | 11678 | res = 0x7fff; |
f927dbda | 11679 | } |
6ddbc6e4 PB |
11680 | } |
11681 | return res; | |
11682 | } | |
11683 | ||
1654b2d6 | 11684 | /* Perform 8-bit signed saturating subtraction. */ |
6ddbc6e4 PB |
11685 | static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
11686 | { | |
11687 | uint8_t res; | |
11688 | ||
11689 | res = a - b; | |
11690 | if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | |
f927dbda | 11691 | if (a & 0x80) { |
6ddbc6e4 | 11692 | res = 0x80; |
f927dbda | 11693 | } else { |
6ddbc6e4 | 11694 | res = 0x7f; |
f927dbda | 11695 | } |
6ddbc6e4 PB |
11696 | } |
11697 | return res; | |
11698 | } | |
11699 | ||
11700 | #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | |
11701 | #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | |
11702 | #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | |
11703 | #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | |
11704 | #define PFX q | |
11705 | ||
11706 | #include "op_addsub.h" | |
11707 | ||
11708 | /* Unsigned saturating arithmetic. */ | |
460a09c1 | 11709 | static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 PB |
11710 | { |
11711 | uint16_t res; | |
11712 | res = a + b; | |
f927dbda | 11713 | if (res < a) { |
6ddbc6e4 | 11714 | res = 0xffff; |
f927dbda | 11715 | } |
6ddbc6e4 PB |
11716 | return res; |
11717 | } | |
11718 | ||
460a09c1 | 11719 | static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
6ddbc6e4 | 11720 | { |
f927dbda | 11721 | if (a > b) { |
6ddbc6e4 | 11722 | return a - b; |
f927dbda | 11723 | } else { |
6ddbc6e4 | 11724 | return 0; |
f927dbda | 11725 | } |
6ddbc6e4 PB |
11726 | } |
11727 | ||
11728 | static inline uint8_t add8_usat(uint8_t a, uint8_t b) | |
11729 | { | |
11730 | uint8_t res; | |
11731 | res = a + b; | |
f927dbda | 11732 | if (res < a) { |
6ddbc6e4 | 11733 | res = 0xff; |
f927dbda | 11734 | } |
6ddbc6e4 PB |
11735 | return res; |
11736 | } | |
11737 | ||
11738 | static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | |
11739 | { | |
f927dbda | 11740 | if (a > b) { |
6ddbc6e4 | 11741 | return a - b; |
f927dbda | 11742 | } else { |
6ddbc6e4 | 11743 | return 0; |
f927dbda | 11744 | } |
6ddbc6e4 PB |
11745 | } |
11746 | ||
11747 | #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | |
11748 | #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | |
11749 | #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | |
11750 | #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | |
11751 | #define PFX uq | |
11752 | ||
11753 | #include "op_addsub.h" | |
11754 | ||
11755 | /* Signed modulo arithmetic. */ | |
11756 | #define SARITH16(a, b, n, op) do { \ | |
11757 | int32_t sum; \ | |
db6e2e65 | 11758 | sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ |
6ddbc6e4 PB |
11759 | RESULT(sum, n, 16); \ |
11760 | if (sum >= 0) \ | |
11761 | ge |= 3 << (n * 2); \ | |
04215eb1 | 11762 | } while (0) |
6ddbc6e4 PB |
11763 | |
11764 | #define SARITH8(a, b, n, op) do { \ | |
11765 | int32_t sum; \ | |
db6e2e65 | 11766 | sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ |
6ddbc6e4 PB |
11767 | RESULT(sum, n, 8); \ |
11768 | if (sum >= 0) \ | |
11769 | ge |= 1 << n; \ | |
04215eb1 | 11770 | } while (0) |
6ddbc6e4 PB |
11771 | |
11772 | ||
11773 | #define ADD16(a, b, n) SARITH16(a, b, n, +) | |
11774 | #define SUB16(a, b, n) SARITH16(a, b, n, -) | |
11775 | #define ADD8(a, b, n) SARITH8(a, b, n, +) | |
11776 | #define SUB8(a, b, n) SARITH8(a, b, n, -) | |
11777 | #define PFX s | |
11778 | #define ARITH_GE | |
11779 | ||
11780 | #include "op_addsub.h" | |
11781 | ||
11782 | /* Unsigned modulo arithmetic. */ | |
11783 | #define ADD16(a, b, n) do { \ | |
11784 | uint32_t sum; \ | |
11785 | sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | |
11786 | RESULT(sum, n, 16); \ | |
a87aa10b | 11787 | if ((sum >> 16) == 1) \ |
6ddbc6e4 | 11788 | ge |= 3 << (n * 2); \ |
04215eb1 | 11789 | } while (0) |
6ddbc6e4 PB |
11790 | |
11791 | #define ADD8(a, b, n) do { \ | |
11792 | uint32_t sum; \ | |
11793 | sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | |
11794 | RESULT(sum, n, 8); \ | |
a87aa10b AZ |
11795 | if ((sum >> 8) == 1) \ |
11796 | ge |= 1 << n; \ | |
04215eb1 | 11797 | } while (0) |
6ddbc6e4 PB |
11798 | |
11799 | #define SUB16(a, b, n) do { \ | |
11800 | uint32_t sum; \ | |
11801 | sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | |
11802 | RESULT(sum, n, 16); \ | |
11803 | if ((sum >> 16) == 0) \ | |
11804 | ge |= 3 << (n * 2); \ | |
04215eb1 | 11805 | } while (0) |
6ddbc6e4 PB |
11806 | |
11807 | #define SUB8(a, b, n) do { \ | |
11808 | uint32_t sum; \ | |
11809 | sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | |
11810 | RESULT(sum, n, 8); \ | |
11811 | if ((sum >> 8) == 0) \ | |
a87aa10b | 11812 | ge |= 1 << n; \ |
04215eb1 | 11813 | } while (0) |
6ddbc6e4 PB |
11814 | |
11815 | #define PFX u | |
11816 | #define ARITH_GE | |
11817 | ||
11818 | #include "op_addsub.h" | |
11819 | ||
11820 | /* Halved signed arithmetic. */ | |
11821 | #define ADD16(a, b, n) \ | |
11822 | RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | |
11823 | #define SUB16(a, b, n) \ | |
11824 | RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | |
11825 | #define ADD8(a, b, n) \ | |
11826 | RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | |
11827 | #define SUB8(a, b, n) \ | |
11828 | RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | |
11829 | #define PFX sh | |
11830 | ||
11831 | #include "op_addsub.h" | |
11832 | ||
11833 | /* Halved unsigned arithmetic. */ | |
11834 | #define ADD16(a, b, n) \ | |
11835 | RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
11836 | #define SUB16(a, b, n) \ | |
11837 | RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | |
11838 | #define ADD8(a, b, n) \ | |
11839 | RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
11840 | #define SUB8(a, b, n) \ | |
11841 | RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | |
11842 | #define PFX uh | |
11843 | ||
11844 | #include "op_addsub.h" | |
11845 | ||
11846 | static inline uint8_t do_usad(uint8_t a, uint8_t b) | |
11847 | { | |
f927dbda | 11848 | if (a > b) { |
6ddbc6e4 | 11849 | return a - b; |
f927dbda | 11850 | } else { |
6ddbc6e4 | 11851 | return b - a; |
f927dbda | 11852 | } |
6ddbc6e4 PB |
11853 | } |
11854 | ||
11855 | /* Unsigned sum of absolute byte differences. */ | |
11856 | uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | |
11857 | { | |
11858 | uint32_t sum; | |
11859 | sum = do_usad(a, b); | |
11860 | sum += do_usad(a >> 8, b >> 8); | |
bdc3b6f5 | 11861 | sum += do_usad(a >> 16, b >> 16); |
6ddbc6e4 PB |
11862 | sum += do_usad(a >> 24, b >> 24); |
11863 | return sum; | |
11864 | } | |
11865 | ||
11866 | /* For ARMv6 SEL instruction. */ | |
11867 | uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | |
11868 | { | |
11869 | uint32_t mask; | |
11870 | ||
11871 | mask = 0; | |
f927dbda | 11872 | if (flags & 1) { |
6ddbc6e4 | 11873 | mask |= 0xff; |
f927dbda FR |
11874 | } |
11875 | if (flags & 2) { | |
6ddbc6e4 | 11876 | mask |= 0xff00; |
f927dbda FR |
11877 | } |
11878 | if (flags & 4) { | |
6ddbc6e4 | 11879 | mask |= 0xff0000; |
f927dbda FR |
11880 | } |
11881 | if (flags & 8) { | |
6ddbc6e4 | 11882 | mask |= 0xff000000; |
f927dbda | 11883 | } |
6ddbc6e4 PB |
11884 | return (a & mask) | (b & ~mask); |
11885 | } | |
11886 | ||
9b37a28c FR |
11887 | /* |
11888 | * CRC helpers. | |
aa633469 PM |
11889 | * The upper bytes of val (above the number specified by 'bytes') must have |
11890 | * been zeroed out by the caller. | |
11891 | */ | |
eb0ecd5a WN |
11892 | uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) |
11893 | { | |
11894 | uint8_t buf[4]; | |
11895 | ||
aa633469 | 11896 | stl_le_p(buf, val); |
eb0ecd5a WN |
11897 | |
11898 | /* zlib crc32 converts the accumulator and output to one's complement. */ | |
11899 | return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | |
11900 | } | |
11901 | ||
11902 | uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | |
11903 | { | |
11904 | uint8_t buf[4]; | |
11905 | ||
aa633469 | 11906 | stl_le_p(buf, val); |
eb0ecd5a WN |
11907 | |
11908 | /* Linux crc32c converts the output to one's complement. */ | |
11909 | return crc32c(acc, buf, bytes) ^ 0xffffffff; | |
11910 | } | |
a9e01311 | 11911 | |
9b37a28c FR |
11912 | /* |
11913 | * Return the exception level to which FP-disabled exceptions should | |
a9e01311 RH |
11914 | * be taken, or 0 if FP is enabled. |
11915 | */ | |
ced31551 | 11916 | int fp_exception_el(CPUARMState *env, int cur_el) |
a9e01311 | 11917 | { |
55faa212 | 11918 | #ifndef CONFIG_USER_ONLY |
d5a6fa2d RH |
11919 | uint64_t hcr_el2; |
11920 | ||
9b37a28c FR |
11921 | /* |
11922 | * CPACR and the CPTR registers don't exist before v6, so FP is | |
a9e01311 RH |
11923 | * always accessible |
11924 | */ | |
11925 | if (!arm_feature(env, ARM_FEATURE_V6)) { | |
11926 | return 0; | |
11927 | } | |
11928 | ||
d87513c0 PM |
11929 | if (arm_feature(env, ARM_FEATURE_M)) { |
11930 | /* CPACR can cause a NOCP UsageFault taken to current security state */ | |
11931 | if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) { | |
11932 | return 1; | |
11933 | } | |
11934 | ||
11935 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) { | |
11936 | if (!extract32(env->v7m.nsacr, 10, 1)) { | |
11937 | /* FP insns cause a NOCP UsageFault taken to Secure */ | |
11938 | return 3; | |
11939 | } | |
11940 | } | |
11941 | ||
11942 | return 0; | |
11943 | } | |
11944 | ||
d5a6fa2d RH |
11945 | hcr_el2 = arm_hcr_el2_eff(env); |
11946 | ||
9b37a28c FR |
11947 | /* |
11948 | * The CPACR controls traps to EL1, or PL1 if we're 32 bit: | |
a9e01311 RH |
11949 | * 0, 2 : trap EL0 and EL1/PL1 accesses |
11950 | * 1 : trap only EL0 accesses | |
11951 | * 3 : trap no accesses | |
c2ddb7cf | 11952 | * This register is ignored if E2H+TGE are both set. |
a9e01311 | 11953 | */ |
d5a6fa2d | 11954 | if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { |
fab8ad39 | 11955 | int fpen = FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN); |
c2ddb7cf RH |
11956 | |
11957 | switch (fpen) { | |
02e1de14 RH |
11958 | case 1: |
11959 | if (cur_el != 0) { | |
11960 | break; | |
11961 | } | |
11962 | /* fall through */ | |
c2ddb7cf RH |
11963 | case 0: |
11964 | case 2: | |
02e1de14 RH |
11965 | /* Trap from Secure PL0 or PL1 to Secure PL1. */ |
11966 | if (!arm_el_is_aa64(env, 3) | |
11967 | && (cur_el == 3 || arm_is_secure_below_el3(env))) { | |
a9e01311 RH |
11968 | return 3; |
11969 | } | |
02e1de14 | 11970 | if (cur_el <= 1) { |
c2ddb7cf RH |
11971 | return 1; |
11972 | } | |
11973 | break; | |
a9e01311 | 11974 | } |
a9e01311 RH |
11975 | } |
11976 | ||
fc1120a7 PM |
11977 | /* |
11978 | * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode | |
11979 | * to control non-secure access to the FPU. It doesn't have any | |
11980 | * effect if EL3 is AArch64 or if EL3 doesn't exist at all. | |
11981 | */ | |
11982 | if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && | |
11983 | cur_el <= 2 && !arm_is_secure_below_el3(env))) { | |
11984 | if (!extract32(env->cp15.nsacr, 10, 1)) { | |
11985 | /* FP insns act as UNDEF */ | |
11986 | return cur_el == 2 ? 2 : 1; | |
11987 | } | |
11988 | } | |
11989 | ||
d5a6fa2d RH |
11990 | /* |
11991 | * CPTR_EL2 is present in v7VE or v8, and changes format | |
11992 | * with HCR_EL2.E2H (regardless of TGE). | |
a9e01311 | 11993 | */ |
d5a6fa2d RH |
11994 | if (cur_el <= 2) { |
11995 | if (hcr_el2 & HCR_E2H) { | |
fab8ad39 | 11996 | switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) { |
d5a6fa2d RH |
11997 | case 1: |
11998 | if (cur_el != 0 || !(hcr_el2 & HCR_TGE)) { | |
11999 | break; | |
12000 | } | |
12001 | /* fall through */ | |
12002 | case 0: | |
12003 | case 2: | |
12004 | return 2; | |
12005 | } | |
12006 | } else if (arm_is_el2_enabled(env)) { | |
fab8ad39 | 12007 | if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) { |
d5a6fa2d RH |
12008 | return 2; |
12009 | } | |
12010 | } | |
a9e01311 RH |
12011 | } |
12012 | ||
12013 | /* CPTR_EL3 : present in v8 */ | |
fab8ad39 | 12014 | if (FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TFP)) { |
a9e01311 RH |
12015 | /* Trap all FP ops to EL3 */ |
12016 | return 3; | |
12017 | } | |
55faa212 | 12018 | #endif |
a9e01311 RH |
12019 | return 0; |
12020 | } | |
12021 | ||
b9f6033c RH |
12022 | /* Return the exception level we're running at if this is our mmu_idx */ |
12023 | int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) | |
12024 | { | |
12025 | if (mmu_idx & ARM_MMU_IDX_M) { | |
12026 | return mmu_idx & ARM_MMU_IDX_M_PRIV; | |
12027 | } | |
12028 | ||
12029 | switch (mmu_idx) { | |
12030 | case ARMMMUIdx_E10_0: | |
12031 | case ARMMMUIdx_E20_0: | |
b9f6033c RH |
12032 | return 0; |
12033 | case ARMMMUIdx_E10_1: | |
452ef8cb | 12034 | case ARMMMUIdx_E10_1_PAN: |
b9f6033c RH |
12035 | return 1; |
12036 | case ARMMMUIdx_E2: | |
12037 | case ARMMMUIdx_E20_2: | |
452ef8cb | 12038 | case ARMMMUIdx_E20_2_PAN: |
b9f6033c | 12039 | return 2; |
d902ae75 | 12040 | case ARMMMUIdx_E3: |
b9f6033c RH |
12041 | return 3; |
12042 | default: | |
12043 | g_assert_not_reached(); | |
12044 | } | |
12045 | } | |
12046 | ||
7aab5a8c | 12047 | #ifndef CONFIG_TCG |
65e4655c RH |
12048 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
12049 | { | |
7aab5a8c | 12050 | g_assert_not_reached(); |
65e4655c | 12051 | } |
7aab5a8c | 12052 | #endif |
65e4655c | 12053 | |
6f2d9d74 TK |
12054 | static bool arm_pan_enabled(CPUARMState *env) |
12055 | { | |
12056 | if (is_a64(env)) { | |
12057 | return env->pstate & PSTATE_PAN; | |
12058 | } else { | |
12059 | return env->uncached_cpsr & CPSR_PAN; | |
12060 | } | |
12061 | } | |
12062 | ||
164690b2 | 12063 | ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) |
65e4655c | 12064 | { |
b6ad6062 RDC |
12065 | ARMMMUIdx idx; |
12066 | uint64_t hcr; | |
12067 | ||
65e4655c | 12068 | if (arm_feature(env, ARM_FEATURE_M)) { |
50494a27 | 12069 | return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); |
65e4655c RH |
12070 | } |
12071 | ||
6003d980 | 12072 | /* See ARM pseudo-function ELIsInHost. */ |
b9f6033c RH |
12073 | switch (el) { |
12074 | case 0: | |
b6ad6062 RDC |
12075 | hcr = arm_hcr_el2_eff(env); |
12076 | if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { | |
12077 | idx = ARMMMUIdx_E20_0; | |
12078 | } else { | |
12079 | idx = ARMMMUIdx_E10_0; | |
6003d980 | 12080 | } |
b6ad6062 | 12081 | break; |
b9f6033c | 12082 | case 1: |
6f2d9d74 | 12083 | if (arm_pan_enabled(env)) { |
b6ad6062 RDC |
12084 | idx = ARMMMUIdx_E10_1_PAN; |
12085 | } else { | |
12086 | idx = ARMMMUIdx_E10_1; | |
66412260 | 12087 | } |
b6ad6062 | 12088 | break; |
b9f6033c | 12089 | case 2: |
6003d980 | 12090 | /* Note that TGE does not apply at EL2. */ |
b6ad6062 | 12091 | if (arm_hcr_el2_eff(env) & HCR_E2H) { |
6f2d9d74 | 12092 | if (arm_pan_enabled(env)) { |
b6ad6062 RDC |
12093 | idx = ARMMMUIdx_E20_2_PAN; |
12094 | } else { | |
12095 | idx = ARMMMUIdx_E20_2; | |
66412260 | 12096 | } |
b6ad6062 RDC |
12097 | } else { |
12098 | idx = ARMMMUIdx_E2; | |
6003d980 | 12099 | } |
b6ad6062 | 12100 | break; |
b9f6033c | 12101 | case 3: |
d902ae75 | 12102 | return ARMMMUIdx_E3; |
b9f6033c RH |
12103 | default: |
12104 | g_assert_not_reached(); | |
65e4655c | 12105 | } |
b6ad6062 | 12106 | |
b6ad6062 | 12107 | return idx; |
50494a27 RH |
12108 | } |
12109 | ||
164690b2 RH |
12110 | ARMMMUIdx arm_mmu_idx(CPUARMState *env) |
12111 | { | |
12112 | return arm_mmu_idx_el(env, arm_current_el(env)); | |
12113 | } | |
12114 | ||
26702213 PM |
12115 | static bool mve_no_pred(CPUARMState *env) |
12116 | { | |
12117 | /* | |
12118 | * Return true if there is definitely no predication of MVE | |
12119 | * instructions by VPR or LTPSIZE. (Returning false even if there | |
12120 | * isn't any predication is OK; generated code will just be | |
12121 | * a little worse.) | |
12122 | * If the CPU does not implement MVE then this TB flag is always 0. | |
12123 | * | |
12124 | * NOTE: if you change this logic, the "recalculate s->mve_no_pred" | |
12125 | * logic in gen_update_fp_context() needs to be updated to match. | |
12126 | * | |
12127 | * We do not include the effect of the ECI bits here -- they are | |
12128 | * tracked in other TB flags. This simplifies the logic for | |
12129 | * "when did we emit code that changes the MVE_NO_PRED TB flag | |
12130 | * and thus need to end the TB?". | |
12131 | */ | |
12132 | if (cpu_isar_feature(aa32_mve, env_archcpu(env))) { | |
12133 | return false; | |
12134 | } | |
12135 | if (env->v7m.vpr) { | |
12136 | return false; | |
12137 | } | |
12138 | if (env->v7m.ltpsize < 4) { | |
12139 | return false; | |
12140 | } | |
12141 | return true; | |
12142 | } | |
12143 | ||
bb5de525 AJ |
12144 | void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, |
12145 | uint64_t *cs_base, uint32_t *pflags) | |
d4d7503a | 12146 | { |
3902bfc6 | 12147 | CPUARMTBFlags flags; |
d4d7503a | 12148 | |
0ee8b24a | 12149 | assert_hflags_rebuild_correctly(env); |
3902bfc6 | 12150 | flags = env->hflags; |
3d74e2e9 | 12151 | |
a729a46b | 12152 | if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) { |
d4d7503a | 12153 | *pc = env->pc; |
d4d7503a | 12154 | if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { |
a729a46b | 12155 | DP_TBFLAG_A64(flags, BTYPE, env->btype); |
08f1434a | 12156 | } |
a9e01311 RH |
12157 | } else { |
12158 | *pc = env->regs[15]; | |
6e33ced5 RH |
12159 | |
12160 | if (arm_feature(env, ARM_FEATURE_M)) { | |
9550d1bd RH |
12161 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && |
12162 | FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) | |
12163 | != env->v7m.secure) { | |
a729a46b | 12164 | DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1); |
9550d1bd RH |
12165 | } |
12166 | ||
12167 | if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && | |
12168 | (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || | |
12169 | (env->v7m.secure && | |
12170 | !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { | |
12171 | /* | |
12172 | * ASPEN is set, but FPCA/SFPA indicate that there is no | |
12173 | * active FP context; we must create a new FP context before | |
12174 | * executing any FP insn. | |
12175 | */ | |
a729a46b | 12176 | DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1); |
9550d1bd RH |
12177 | } |
12178 | ||
12179 | bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; | |
12180 | if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { | |
a729a46b | 12181 | DP_TBFLAG_M32(flags, LSPACT, 1); |
9550d1bd | 12182 | } |
26702213 PM |
12183 | |
12184 | if (mve_no_pred(env)) { | |
12185 | DP_TBFLAG_M32(flags, MVE_NO_PRED, 1); | |
12186 | } | |
6e33ced5 | 12187 | } else { |
bbad7c62 RH |
12188 | /* |
12189 | * Note that XSCALE_CPAR shares bits with VECSTRIDE. | |
12190 | * Note that VECLEN+VECSTRIDE are RES0 for M-profile. | |
12191 | */ | |
12192 | if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
a729a46b | 12193 | DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar); |
bbad7c62 | 12194 | } else { |
a729a46b RH |
12195 | DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len); |
12196 | DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride); | |
bbad7c62 | 12197 | } |
0a54d68e | 12198 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { |
a729a46b | 12199 | DP_TBFLAG_A32(flags, VFPEN, 1); |
0a54d68e | 12200 | } |
6e33ced5 RH |
12201 | } |
12202 | ||
a729a46b RH |
12203 | DP_TBFLAG_AM32(flags, THUMB, env->thumb); |
12204 | DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits); | |
d4d7503a | 12205 | } |
a9e01311 | 12206 | |
60e12c37 RH |
12207 | /* |
12208 | * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine | |
a9e01311 RH |
12209 | * states defined in the ARM ARM for software singlestep: |
12210 | * SS_ACTIVE PSTATE.SS State | |
12211 | * 0 x Inactive (the TB flag for SS is always 0) | |
12212 | * 1 0 Active-pending | |
12213 | * 1 1 Active-not-pending | |
ae6eb1e9 | 12214 | * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB. |
a9e01311 | 12215 | */ |
a729a46b RH |
12216 | if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) { |
12217 | DP_TBFLAG_ANY(flags, PSTATE__SS, 1); | |
a9e01311 | 12218 | } |
a9e01311 | 12219 | |
3902bfc6 | 12220 | *pflags = flags.flags; |
a378206a | 12221 | *cs_base = flags.flags2; |
a9e01311 | 12222 | } |
0ab5953b RH |
12223 | |
12224 | #ifdef TARGET_AARCH64 | |
12225 | /* | |
12226 | * The manual says that when SVE is enabled and VQ is widened the | |
12227 | * implementation is allowed to zero the previously inaccessible | |
12228 | * portion of the registers. The corollary to that is that when | |
12229 | * SVE is enabled and VQ is narrowed we are also allowed to zero | |
12230 | * the now inaccessible portion of the registers. | |
12231 | * | |
12232 | * The intent of this is that no predicate bit beyond VQ is ever set. | |
12233 | * Which means that some operations on predicate registers themselves | |
12234 | * may operate on full uint64_t or even unrolled across the maximum | |
12235 | * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally | |
12236 | * may well be cheaper than conditionals to restrict the operation | |
12237 | * to the relevant portion of a uint16_t[16]. | |
12238 | */ | |
12239 | void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) | |
12240 | { | |
12241 | int i, j; | |
12242 | uint64_t pmask; | |
12243 | ||
12244 | assert(vq >= 1 && vq <= ARM_MAX_VQ); | |
2fc0cc0e | 12245 | assert(vq <= env_archcpu(env)->sve_max_vq); |
0ab5953b RH |
12246 | |
12247 | /* Zap the high bits of the zregs. */ | |
12248 | for (i = 0; i < 32; i++) { | |
12249 | memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)); | |
12250 | } | |
12251 | ||
12252 | /* Zap the high bits of the pregs and ffr. */ | |
12253 | pmask = 0; | |
12254 | if (vq & 3) { | |
12255 | pmask = ~(-1ULL << (16 * (vq & 3))); | |
12256 | } | |
12257 | for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) { | |
12258 | for (i = 0; i < 17; ++i) { | |
12259 | env->vfp.pregs[i].p[j] &= pmask; | |
12260 | } | |
12261 | pmask = 0; | |
12262 | } | |
12263 | } | |
12264 | ||
6a775fd6 RH |
12265 | static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState *env, int el, bool sm) |
12266 | { | |
12267 | int exc_el; | |
12268 | ||
12269 | if (sm) { | |
12270 | exc_el = sme_exception_el(env, el); | |
12271 | } else { | |
12272 | exc_el = sve_exception_el(env, el); | |
12273 | } | |
12274 | if (exc_el) { | |
12275 | return 0; /* disabled */ | |
12276 | } | |
12277 | return sve_vqm1_for_el_sm(env, el, sm); | |
12278 | } | |
12279 | ||
0ab5953b RH |
12280 | /* |
12281 | * Notice a change in SVE vector size when changing EL. | |
12282 | */ | |
9a05f7b6 RH |
12283 | void aarch64_sve_change_el(CPUARMState *env, int old_el, |
12284 | int new_el, bool el0_a64) | |
0ab5953b | 12285 | { |
2fc0cc0e | 12286 | ARMCPU *cpu = env_archcpu(env); |
0ab5953b | 12287 | int old_len, new_len; |
6a775fd6 | 12288 | bool old_a64, new_a64, sm; |
0ab5953b RH |
12289 | |
12290 | /* Nothing to do if no SVE. */ | |
cd208a1c | 12291 | if (!cpu_isar_feature(aa64_sve, cpu)) { |
0ab5953b RH |
12292 | return; |
12293 | } | |
12294 | ||
12295 | /* Nothing to do if FP is disabled in either EL. */ | |
12296 | if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) { | |
12297 | return; | |
12298 | } | |
12299 | ||
04fbce76 RH |
12300 | old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; |
12301 | new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; | |
12302 | ||
12303 | /* | |
12304 | * Both AArch64.TakeException and AArch64.ExceptionReturn | |
12305 | * invoke ResetSVEState when taking an exception from, or | |
12306 | * returning to, AArch32 state when PSTATE.SM is enabled. | |
12307 | */ | |
6a775fd6 RH |
12308 | sm = FIELD_EX64(env->svcr, SVCR, SM); |
12309 | if (old_a64 != new_a64 && sm) { | |
04fbce76 RH |
12310 | arm_reset_sve_state(env); |
12311 | return; | |
12312 | } | |
12313 | ||
0ab5953b RH |
12314 | /* |
12315 | * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped | |
12316 | * at ELx, or not available because the EL is in AArch32 state, then | |
12317 | * for all purposes other than a direct read, the ZCR_ELx.LEN field | |
12318 | * has an effective value of 0". | |
12319 | * | |
12320 | * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0). | |
12321 | * If we ignore aa32 state, we would fail to see the vq4->vq0 transition | |
12322 | * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that | |
12323 | * we already have the correct register contents when encountering the | |
12324 | * vq0->vq0 transition between EL0->EL1. | |
12325 | */ | |
6a775fd6 RH |
12326 | old_len = new_len = 0; |
12327 | if (old_a64) { | |
12328 | old_len = sve_vqm1_for_el_sm_ena(env, old_el, sm); | |
12329 | } | |
12330 | if (new_a64) { | |
12331 | new_len = sve_vqm1_for_el_sm_ena(env, new_el, sm); | |
12332 | } | |
0ab5953b RH |
12333 | |
12334 | /* When changing vector length, clear inaccessible state. */ | |
12335 | if (new_len < old_len) { | |
12336 | aarch64_sve_narrow_vq(env, new_len + 1); | |
12337 | } | |
12338 | } | |
12339 | #endif | |
5d28ac0c RH |
12340 | |
12341 | #ifndef CONFIG_USER_ONLY | |
12342 | ARMSecuritySpace arm_security_space(CPUARMState *env) | |
12343 | { | |
12344 | if (arm_feature(env, ARM_FEATURE_M)) { | |
12345 | return arm_secure_to_space(env->v7m.secure); | |
12346 | } | |
12347 | ||
12348 | /* | |
12349 | * If EL3 is not supported then the secure state is implementation | |
12350 | * defined, in which case QEMU defaults to non-secure. | |
12351 | */ | |
12352 | if (!arm_feature(env, ARM_FEATURE_EL3)) { | |
12353 | return ARMSS_NonSecure; | |
12354 | } | |
12355 | ||
12356 | /* Check for AArch64 EL3 or AArch32 Mon. */ | |
12357 | if (is_a64(env)) { | |
12358 | if (extract32(env->pstate, 2, 2) == 3) { | |
12359 | if (cpu_isar_feature(aa64_rme, env_archcpu(env))) { | |
12360 | return ARMSS_Root; | |
12361 | } else { | |
12362 | return ARMSS_Secure; | |
12363 | } | |
12364 | } | |
12365 | } else { | |
12366 | if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { | |
12367 | return ARMSS_Secure; | |
12368 | } | |
12369 | } | |
12370 | ||
12371 | return arm_security_space_below_el3(env); | |
12372 | } | |
12373 | ||
12374 | ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) | |
12375 | { | |
12376 | assert(!arm_feature(env, ARM_FEATURE_M)); | |
12377 | ||
12378 | /* | |
12379 | * If EL3 is not supported then the secure state is implementation | |
12380 | * defined, in which case QEMU defaults to non-secure. | |
12381 | */ | |
12382 | if (!arm_feature(env, ARM_FEATURE_EL3)) { | |
12383 | return ARMSS_NonSecure; | |
12384 | } | |
12385 | ||
12386 | /* | |
12387 | * Note NSE cannot be set without RME, and NSE & !NS is Reserved. | |
12388 | * Ignoring NSE when !NS retains consistency without having to | |
12389 | * modify other predicates. | |
12390 | */ | |
12391 | if (!(env->cp15.scr_el3 & SCR_NS)) { | |
12392 | return ARMSS_Secure; | |
12393 | } else if (env->cp15.scr_el3 & SCR_NSE) { | |
12394 | return ARMSS_Realm; | |
12395 | } else { | |
12396 | return ARMSS_NonSecure; | |
12397 | } | |
12398 | } | |
12399 | #endif /* !CONFIG_USER_ONLY */ |