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target/arm: add arm_is_el2_enabled() helper
[mirror_qemu.git] / target / arm / helper.c
CommitLineData
ed3baad1
PMD		 1/*
2 * ARM generic helpers.
3 *
4 * This code is licensed under the GNU GPL v2 or later.
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
db725815 8
74c21bd0 9#include "qemu/osdep.h"
63159601 10#include "qemu/units.h"
181962fd 11#include "target/arm/idau.h"
194cbc49 12#include "trace.h"
b5ff1b31 13#include "cpu.h"
ccd38087 14#include "internals.h"
022c62cb 15#include "exec/gdbstub.h"
2ef6175a 16#include "exec/helper-proto.h"
1de7afc9 17#include "qemu/host-utils.h"
db725815 18#include "qemu/main-loop.h"
1de7afc9 19#include "qemu/bitops.h"
eb0ecd5a 20#include "qemu/crc32c.h"
0442428a 21#include "qemu/qemu-print.h"
63c91552 22#include "exec/exec-all.h"
eb0ecd5a 23#include <zlib.h> /* For crc32 */
64552b6b 24#include "hw/irq.h"
f1672e6f 25#include "hw/semihosting/semihost.h"
b2e23725 26#include "sysemu/cpus.h"
740b1759 27#include "sysemu/cpu-timers.h"
f3a9b694 28#include "sysemu/kvm.h"
2a609df8 29#include "sysemu/tcg.h"
9d2b5a58 30#include "qemu/range.h"
7f7b4e7a 31#include "qapi/qapi-commands-machine-target.h"
de390645
RH		 32#include "qapi/error.h"
33#include "qemu/guest-random.h"
91f78c58
PMD		 34#ifdef CONFIG_TCG
35#include "arm_ldst.h"
7aab5a8c 36#include "exec/cpu_ldst.h"
0bb446d8 37#include "hw/semihosting/common-semi.h"
91f78c58 38#endif
0b03bdfc 39
352c98e5
LV		 40#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
41
4a501606 42#ifndef CONFIG_USER_ONLY
7c2cb42b 43
98e87797 44static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
03ae85f8 45 MMUAccessType access_type, ARMMMUIdx mmu_idx,
ff7de2fc 46 bool s1_is_el0,
37785977 47 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
da909b2c 48 target_ulong *page_size_ptr,
7e98e21c
RH		 49 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
50 __attribute__((nonnull));
4a501606
PM		 51#endif
52
affdb64d 53static void switch_mode(CPUARMState *env, int mode);
ea04dce7 54static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);
affdb64d 55
a010bdbe 56static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
56aebc89 57{
a6627f5f
RH		 58 ARMCPU *cpu = env_archcpu(env);
59 int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
56aebc89
PB		 60
61 /* VFP data registers are always little-endian. */
56aebc89 62 if (reg < nregs) {
a010bdbe 63 return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg));
56aebc89
PB		 64 }
65 if (arm_feature(env, ARM_FEATURE_NEON)) {
66 /* Aliases for Q regs. */
67 nregs += 16;
68 if (reg < nregs) {
9a2b5256 69 uint64_t *q = aa32_vfp_qreg(env, reg - 32);
a010bdbe 70 return gdb_get_reg128(buf, q[0], q[1]);
56aebc89
PB		 71 }
72 }
73 switch (reg - nregs) {
a010bdbe
AB		 74 case 0: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); break;
75 case 1: return gdb_get_reg32(buf, vfp_get_fpscr(env)); break;
76 case 2: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); break;
56aebc89
PB		 77 }
78 return 0;
79}
80
0ecb72a5 81static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89 82{
a6627f5f
RH		 83 ARMCPU *cpu = env_archcpu(env);
84 int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
56aebc89 85
56aebc89 86 if (reg < nregs) {
9a2b5256 87 *aa32_vfp_dreg(env, reg) = ldq_le_p(buf);
56aebc89
PB		 88 return 8;
89 }
90 if (arm_feature(env, ARM_FEATURE_NEON)) {
91 nregs += 16;
92 if (reg < nregs) {
9a2b5256
RH		 93 uint64_t *q = aa32_vfp_qreg(env, reg - 32);
94 q[0] = ldq_le_p(buf);
95 q[1] = ldq_le_p(buf + 8);
56aebc89
PB		 96 return 16;
97 }
98 }
99 switch (reg - nregs) {
100 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
b0a909a4 101 case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
71b3c3de 102 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 103 }
104 return 0;
105}
106
a010bdbe 107static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
6a669427
PM		 108{
109 switch (reg) {
110 case 0 ... 31:
8b1ca58c
AB		 111 {
112 /* 128 bit FP register - quads are in LE order */
113 uint64_t *q = aa64_vfp_qreg(env, reg);
114 return gdb_get_reg128(buf, q[1], q[0]);
115 }
6a669427
PM		 116 case 32:
117 /* FPSR */
8b1ca58c 118 return gdb_get_reg32(buf, vfp_get_fpsr(env));
6a669427
PM		 119 case 33:
120 /* FPCR */
8b1ca58c 121 return gdb_get_reg32(buf,vfp_get_fpcr(env));
6a669427
PM		 122 default:
123 return 0;
124 }
125}
126
127static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
128{
129 switch (reg) {
130 case 0 ... 31:
131 /* 128 bit FP register */
9a2b5256
RH		 132 {
133 uint64_t *q = aa64_vfp_qreg(env, reg);
134 q[0] = ldq_le_p(buf);
135 q[1] = ldq_le_p(buf + 8);
136 return 16;
137 }
6a669427
PM		 138 case 32:
139 /* FPSR */
140 vfp_set_fpsr(env, ldl_p(buf));
141 return 4;
142 case 33:
143 /* FPCR */
144 vfp_set_fpcr(env, ldl_p(buf));
145 return 4;
146 default:
147 return 0;
148 }
149}
150
c4241c7d 151static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
d4e6df63 152{
375421cc 153 assert(ri->fieldoffset);
67ed771d 154 if (cpreg_field_is_64bit(ri)) {
c4241c7d 155 return CPREG_FIELD64(env, ri);
22d9e1a9 156 } else {
c4241c7d 157 return CPREG_FIELD32(env, ri);
22d9e1a9 158 }
d4e6df63
PM		 159}
160
c4241c7d
PM		 161static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
162 uint64_t value)
d4e6df63 163{
375421cc 164 assert(ri->fieldoffset);
67ed771d 165 if (cpreg_field_is_64bit(ri)) {
22d9e1a9
PM		 166 CPREG_FIELD64(env, ri) = value;
167 } else {
168 CPREG_FIELD32(env, ri) = value;
169 }
d4e6df63
PM		 170}
171
11f136ee
FA		 172static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
173{
174 return (char *)env + ri->fieldoffset;
175}
176
49a66191 177uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
721fae12 178{
59a1c327 179 /* Raw read of a coprocessor register (as needed for migration, etc). */
721fae12 180 if (ri->type & ARM_CP_CONST) {
59a1c327 181 return ri->resetvalue;
721fae12 182 } else if (ri->raw_readfn) {
59a1c327 183 return ri->raw_readfn(env, ri);
721fae12 184 } else if (ri->readfn) {
59a1c327 185 return ri->readfn(env, ri);
721fae12 186 } else {
59a1c327 187 return raw_read(env, ri);
721fae12 188 }
721fae12
PM		 189}
190
59a1c327 191static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
7900e9f1 192 uint64_t v)
721fae12
PM		 193{
194 /* Raw write of a coprocessor register (as needed for migration, etc).
721fae12
PM		 195 * Note that constant registers are treated as write-ignored; the
196 * caller should check for success by whether a readback gives the
197 * value written.
198 */
199 if (ri->type & ARM_CP_CONST) {
59a1c327 200 return;
721fae12 201 } else if (ri->raw_writefn) {
c4241c7d 202 ri->raw_writefn(env, ri, v);
721fae12 203 } else if (ri->writefn) {
c4241c7d 204 ri->writefn(env, ri, v);
721fae12 205 } else {
afb2530f 206 raw_write(env, ri, v);
721fae12 207 }
721fae12
PM		 208}
209
d12379c5
AB		 210/**
211 * arm_get/set_gdb_*: get/set a gdb register
212 * @env: the CPU state
213 * @buf: a buffer to copy to/from
214 * @reg: register number (offset from start of group)
215 *
216 * We return the number of bytes copied
217 */
218
a010bdbe 219static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
200bf5b7 220{
2fc0cc0e 221 ARMCPU *cpu = env_archcpu(env);
200bf5b7
AB		 222 const ARMCPRegInfo *ri;
223 uint32_t key;
224
448d4d14 225 key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg];
200bf5b7
AB		 226 ri = get_arm_cp_reginfo(cpu->cp_regs, key);
227 if (ri) {
228 if (cpreg_field_is_64bit(ri)) {
229 return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));
230 } else {
231 return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri));
232 }
233 }
234 return 0;
235}
236
237static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
238{
239 return 0;
240}
241
d12379c5
AB		 242#ifdef TARGET_AARCH64
243static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
244{
245 ARMCPU *cpu = env_archcpu(env);
246
247 switch (reg) {
248 /* The first 32 registers are the zregs */
249 case 0 ... 31:
250 {
251 int vq, len = 0;
252 for (vq = 0; vq < cpu->sve_max_vq; vq++) {
253 len += gdb_get_reg128(buf,
254 env->vfp.zregs[reg].d[vq * 2 + 1],
255 env->vfp.zregs[reg].d[vq * 2]);
256 }
257 return len;
258 }
259 case 32:
260 return gdb_get_reg32(buf, vfp_get_fpsr(env));
261 case 33:
262 return gdb_get_reg32(buf, vfp_get_fpcr(env));
263 /* then 16 predicates and the ffr */
264 case 34 ... 50:
265 {
266 int preg = reg - 34;
267 int vq, len = 0;
268 for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
269 len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]);
270 }
271 return len;
272 }
273 case 51:
274 {
275 /*
276 * We report in Vector Granules (VG) which is 64bit in a Z reg
277 * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
278 */
279 int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1;
797920b9 280 return gdb_get_reg64(buf, vq * 2);
d12379c5
AB		 281 }
282 default:
283 /* gdbstub asked for something out our range */
284 qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);
285 break;
286 }
287
288 return 0;
289}
290
291static int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
292{
293 ARMCPU *cpu = env_archcpu(env);
294
295 /* The first 32 registers are the zregs */
296 switch (reg) {
297 /* The first 32 registers are the zregs */
298 case 0 ... 31:
299 {
300 int vq, len = 0;
301 uint64_t *p = (uint64_t *) buf;
302 for (vq = 0; vq < cpu->sve_max_vq; vq++) {
303 env->vfp.zregs[reg].d[vq * 2 + 1] = *p++;
304 env->vfp.zregs[reg].d[vq * 2] = *p++;
305 len += 16;
306 }
307 return len;
308 }
309 case 32:
310 vfp_set_fpsr(env, *(uint32_t *)buf);
311 return 4;
312 case 33:
313 vfp_set_fpcr(env, *(uint32_t *)buf);
314 return 4;
315 case 34 ... 50:
316 {
317 int preg = reg - 34;
318 int vq, len = 0;
319 uint64_t *p = (uint64_t *) buf;
320 for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
321 env->vfp.pregs[preg].p[vq / 4] = *p++;
322 len += 8;
323 }
324 return len;
325 }
326 case 51:
327 /* cannot set vg via gdbstub */
328 return 0;
329 default:
330 /* gdbstub asked for something out our range */
331 break;
332 }
333
334 return 0;
335}
336#endif /* TARGET_AARCH64 */
337
375421cc
PM		 338static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
339{
340 /* Return true if the regdef would cause an assertion if you called
341 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
342 * program bug for it not to have the NO_RAW flag).
343 * NB that returning false here doesn't necessarily mean that calling
344 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
345 * read/write access functions which are safe for raw use" from "has
346 * read/write access functions which have side effects but has forgotten
347 * to provide raw access functions".
348 * The tests here line up with the conditions in read/write_raw_cp_reg()
349 * and assertions in raw_read()/raw_write().
350 */
351 if ((ri->type & ARM_CP_CONST) ||
352 ri->fieldoffset ||
353 ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
354 return false;
355 }
356 return true;
357}
358
b698e4ee 359bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
721fae12
PM		 360{
361 /* Write the coprocessor state from cpu->env to the (index,value) list. */
362 int i;
363 bool ok = true;
364
365 for (i = 0; i < cpu->cpreg_array_len; i++) {
366 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
367 const ARMCPRegInfo *ri;
b698e4ee 368 uint64_t newval;
59a1c327 369
60322b39 370 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
721fae12
PM		 371 if (!ri) {
372 ok = false;
373 continue;
374 }
7a0e58fa 375 if (ri->type & ARM_CP_NO_RAW) {
721fae12
PM		 376 continue;
377 }
b698e4ee
PM		 378
379 newval = read_raw_cp_reg(&cpu->env, ri);
380 if (kvm_sync) {
381 /*
382 * Only sync if the previous list->cpustate sync succeeded.
383 * Rather than tracking the success/failure state for every
384 * item in the list, we just recheck "does the raw write we must
385 * have made in write_list_to_cpustate() read back OK" here.
386 */
387 uint64_t oldval = cpu->cpreg_values[i];
388
389 if (oldval == newval) {
390 continue;
391 }
392
393 write_raw_cp_reg(&cpu->env, ri, oldval);
394 if (read_raw_cp_reg(&cpu->env, ri) != oldval) {
395 continue;
396 }
397
398 write_raw_cp_reg(&cpu->env, ri, newval);
399 }
400 cpu->cpreg_values[i] = newval;
721fae12
PM		 401 }
402 return ok;
403}
404
405bool write_list_to_cpustate(ARMCPU *cpu)
406{
407 int i;
408 bool ok = true;
409
410 for (i = 0; i < cpu->cpreg_array_len; i++) {
411 uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
412 uint64_t v = cpu->cpreg_values[i];
721fae12
PM		 413 const ARMCPRegInfo *ri;
414
60322b39 415 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
721fae12
PM		 416 if (!ri) {
417 ok = false;
418 continue;
419 }
7a0e58fa 420 if (ri->type & ARM_CP_NO_RAW) {
721fae12
PM		 421 continue;
422 }
423 /* Write value and confirm it reads back as written
424 * (to catch read-only registers and partially read-only
425 * registers where the incoming migration value doesn't match)
426 */
59a1c327
PM		 427 write_raw_cp_reg(&cpu->env, ri, v);
428 if (read_raw_cp_reg(&cpu->env, ri) != v) {
721fae12
PM		 429 ok = false;
430 }
431 }
432 return ok;
433}
434
435static void add_cpreg_to_list(gpointer key, gpointer opaque)
436{
437 ARMCPU *cpu = opaque;
438 uint64_t regidx;
439 const ARMCPRegInfo *ri;
440
441 regidx = *(uint32_t *)key;
60322b39 442 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
721fae12 443
7a0e58fa 444 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
721fae12
PM		 445 cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
446 /* The value array need not be initialized at this point */
447 cpu->cpreg_array_len++;
448 }
449}
450
451static void count_cpreg(gpointer key, gpointer opaque)
452{
453 ARMCPU *cpu = opaque;
454 uint64_t regidx;
455 const ARMCPRegInfo *ri;
456
457 regidx = *(uint32_t *)key;
60322b39 458 ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
721fae12 459
7a0e58fa 460 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
721fae12
PM		 461 cpu->cpreg_array_len++;
462 }
463}
464
465static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
466{
cbf239b7
AR		 467 uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
468 uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
721fae12 469
cbf239b7
AR		 470 if (aidx > bidx) {
471 return 1;
472 }
473 if (aidx < bidx) {
474 return -1;
475 }
476 return 0;
721fae12
PM		 477}
478
479void init_cpreg_list(ARMCPU *cpu)
480{
481 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
482 * Note that we require cpreg_tuples[] to be sorted by key ID.
483 */
57b6d95e 484 GList *keys;
721fae12
PM		 485 int arraylen;
486
57b6d95e 487 keys = g_hash_table_get_keys(cpu->cp_regs);
721fae12
PM		 488 keys = g_list_sort(keys, cpreg_key_compare);
489
490 cpu->cpreg_array_len = 0;
491
492 g_list_foreach(keys, count_cpreg, cpu);
493
494 arraylen = cpu->cpreg_array_len;
495 cpu->cpreg_indexes = g_new(uint64_t, arraylen);
496 cpu->cpreg_values = g_new(uint64_t, arraylen);
497 cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
498 cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
499 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
500 cpu->cpreg_array_len = 0;
501
502 g_list_foreach(keys, add_cpreg_to_list, cpu);
503
504 assert(cpu->cpreg_array_len == arraylen);
505
506 g_list_free(keys);
507}
508
68e9c2fe 509/*
93dd1e61 510 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
68e9c2fe
EI		 511 */
512static CPAccessResult access_el3_aa32ns(CPUARMState *env,
3f208fd7
PM		 513 const ARMCPRegInfo *ri,
514 bool isread)
68e9c2fe 515{
93dd1e61
EI		 516 if (!is_a64(env) && arm_current_el(env) == 3 &&
517 arm_is_secure_below_el3(env)) {
68e9c2fe
EI		 518 return CP_ACCESS_TRAP_UNCATEGORIZED;
519 }
520 return CP_ACCESS_OK;
521}
522
5513c3ab
PM		 523/* Some secure-only AArch32 registers trap to EL3 if used from
524 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
525 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
526 * We assume that the .access field is set to PL1_RW.
527 */
528static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
3f208fd7
PM		 529 const ARMCPRegInfo *ri,
530 bool isread)
5513c3ab
PM		 531{
532 if (arm_current_el(env) == 3) {
533 return CP_ACCESS_OK;
534 }
535 if (arm_is_secure_below_el3(env)) {
536 return CP_ACCESS_TRAP_EL3;
537 }
538 /* This will be EL1 NS and EL2 NS, which just UNDEF */
539 return CP_ACCESS_TRAP_UNCATEGORIZED;
540}
541
187f678d
PM		 542/* Check for traps to "powerdown debug" registers, which are controlled
543 * by MDCR.TDOSA
544 */
545static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri,
546 bool isread)
547{
548 int el = arm_current_el(env);
30ac6339
PM		 549 bool mdcr_el2_tdosa = (env->cp15.mdcr_el2 & MDCR_TDOSA) ||
550 (env->cp15.mdcr_el2 & MDCR_TDE) ||
7c208e0f 551 (arm_hcr_el2_eff(env) & HCR_TGE);
187f678d 552
30ac6339 553 if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) {
187f678d
PM		 554 return CP_ACCESS_TRAP_EL2;
555 }
556 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) {
557 return CP_ACCESS_TRAP_EL3;
558 }
559 return CP_ACCESS_OK;
560}
561
91b0a238
PM		 562/* Check for traps to "debug ROM" registers, which are controlled
563 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
564 */
565static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri,
566 bool isread)
567{
568 int el = arm_current_el(env);
30ac6339
PM		 569 bool mdcr_el2_tdra = (env->cp15.mdcr_el2 & MDCR_TDRA) ||
570 (env->cp15.mdcr_el2 & MDCR_TDE) ||
7c208e0f 571 (arm_hcr_el2_eff(env) & HCR_TGE);
91b0a238 572
30ac6339 573 if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) {
91b0a238
PM		 574 return CP_ACCESS_TRAP_EL2;
575 }
576 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
577 return CP_ACCESS_TRAP_EL3;
578 }
579 return CP_ACCESS_OK;
580}
581
d6c8cf81
PM		 582/* Check for traps to general debug registers, which are controlled
583 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
584 */
585static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
586 bool isread)
587{
588 int el = arm_current_el(env);
30ac6339
PM		 589 bool mdcr_el2_tda = (env->cp15.mdcr_el2 & MDCR_TDA) ||
590 (env->cp15.mdcr_el2 & MDCR_TDE) ||
7c208e0f 591 (arm_hcr_el2_eff(env) & HCR_TGE);
d6c8cf81 592
30ac6339 593 if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) {
d6c8cf81
PM		 594 return CP_ACCESS_TRAP_EL2;
595 }
596 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
597 return CP_ACCESS_TRAP_EL3;
598 }
599 return CP_ACCESS_OK;
600}
601
1fce1ba9
PM		 602/* Check for traps to performance monitor registers, which are controlled
603 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
604 */
605static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
606 bool isread)
607{
608 int el = arm_current_el(env);
609
610 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
611 && !arm_is_secure_below_el3(env)) {
612 return CP_ACCESS_TRAP_EL2;
613 }
614 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
615 return CP_ACCESS_TRAP_EL3;
616 }
617 return CP_ACCESS_OK;
618}
619
84929218
RH		 620/* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
621static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
622 bool isread)
623{
624 if (arm_current_el(env) == 1) {
625 uint64_t trap = isread ? HCR_TRVM : HCR_TVM;
626 if (arm_hcr_el2_eff(env) & trap) {
627 return CP_ACCESS_TRAP_EL2;
628 }
629 }
630 return CP_ACCESS_OK;
631}
632
1803d271
RH		 633/* Check for traps from EL1 due to HCR_EL2.TSW. */
634static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri,
635 bool isread)
636{
637 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) {
638 return CP_ACCESS_TRAP_EL2;
639 }
640 return CP_ACCESS_OK;
641}
642
99602377
RH		 643/* Check for traps from EL1 due to HCR_EL2.TACR. */
644static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri,
645 bool isread)
646{
647 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TACR)) {
648 return CP_ACCESS_TRAP_EL2;
649 }
650 return CP_ACCESS_OK;
651}
652
30881b73
RH		 653/* Check for traps from EL1 due to HCR_EL2.TTLB. */
654static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
655 bool isread)
656{
657 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TTLB)) {
658 return CP_ACCESS_TRAP_EL2;
659 }
660 return CP_ACCESS_OK;
661}
662
c4241c7d 663static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
c983fe6c 664{
2fc0cc0e 665 ARMCPU *cpu = env_archcpu(env);
00c8cb0a 666
8d5c773e 667 raw_write(env, ri, value);
d10eb08f 668 tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */
c983fe6c
PM		 669}
670
c4241c7d 671static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
08de207b 672{
2fc0cc0e 673 ARMCPU *cpu = env_archcpu(env);
00c8cb0a 674
8d5c773e 675 if (raw_read(env, ri) != value) {
08de207b
PM		 676 /* Unlike real hardware the qemu TLB uses virtual addresses,
677 * not modified virtual addresses, so this causes a TLB flush.
678 */
d10eb08f 679 tlb_flush(CPU(cpu));
8d5c773e 680 raw_write(env, ri, value);
08de207b 681 }
08de207b 682}
c4241c7d
PM		 683
684static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
685 uint64_t value)
08de207b 686{
2fc0cc0e 687 ARMCPU *cpu = env_archcpu(env);
00c8cb0a 688
452a0955 689 if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA)
014406b5 690 && !extended_addresses_enabled(env)) {
08de207b
PM		 691 /* For VMSA (when not using the LPAE long descriptor page table
692 * format) this register includes the ASID, so do a TLB flush.
693 * For PMSA it is purely a process ID and no action is needed.
694 */
d10eb08f 695 tlb_flush(CPU(cpu));
08de207b 696 }
8d5c773e 697 raw_write(env, ri, value);
08de207b
PM		 698}
699
b4ab8ce9
PM		 700/* IS variants of TLB operations must affect all cores */
701static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
702 uint64_t value)
703{
29a0af61 704 CPUState *cs = env_cpu(env);
b4ab8ce9
PM		 705
706 tlb_flush_all_cpus_synced(cs);
707}
708
709static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
710 uint64_t value)
711{
29a0af61 712 CPUState *cs = env_cpu(env);
b4ab8ce9
PM		 713
714 tlb_flush_all_cpus_synced(cs);
715}
716
717static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
718 uint64_t value)
719{
29a0af61 720 CPUState *cs = env_cpu(env);
b4ab8ce9
PM		 721
722 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
723}
724
725static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
726 uint64_t value)
727{
29a0af61 728 CPUState *cs = env_cpu(env);
b4ab8ce9
PM		 729
730 tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
731}
732
733/*
734 * Non-IS variants of TLB operations are upgraded to
373e7ffd 735 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
b4ab8ce9
PM		 736 * force broadcast of these operations.
737 */
738static bool tlb_force_broadcast(CPUARMState *env)
739{
373e7ffd 740 return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB);
b4ab8ce9
PM		 741}
742
c4241c7d
PM		 743static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
744 uint64_t value)
d929823f
PM		 745{
746 /* Invalidate all (TLBIALL) */
527db2be 747 CPUState *cs = env_cpu(env);
00c8cb0a 748
b4ab8ce9 749 if (tlb_force_broadcast(env)) {
527db2be
RH		 750 tlb_flush_all_cpus_synced(cs);
751 } else {
752 tlb_flush(cs);
b4ab8ce9 753 }
d929823f
PM		 754}
755
c4241c7d
PM		 756static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
757 uint64_t value)
d929823f
PM		 758{
759 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
527db2be 760 CPUState *cs = env_cpu(env);
31b030d4 761
527db2be 762 value &= TARGET_PAGE_MASK;
b4ab8ce9 763 if (tlb_force_broadcast(env)) {
527db2be
RH		 764 tlb_flush_page_all_cpus_synced(cs, value);
765 } else {
766 tlb_flush_page(cs, value);
b4ab8ce9 767 }
d929823f
PM		 768}
769
c4241c7d
PM		 770static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
771 uint64_t value)
d929823f
PM		 772{
773 /* Invalidate by ASID (TLBIASID) */
527db2be 774 CPUState *cs = env_cpu(env);
00c8cb0a 775
b4ab8ce9 776 if (tlb_force_broadcast(env)) {
527db2be
RH		 777 tlb_flush_all_cpus_synced(cs);
778 } else {
779 tlb_flush(cs);
b4ab8ce9 780 }
d929823f
PM		 781}
782
c4241c7d
PM		 783static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
784 uint64_t value)
d929823f
PM		 785{
786 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
527db2be 787 CPUState *cs = env_cpu(env);
31b030d4 788
527db2be 789 value &= TARGET_PAGE_MASK;
b4ab8ce9 790 if (tlb_force_broadcast(env)) {
527db2be
RH		 791 tlb_flush_page_all_cpus_synced(cs, value);
792 } else {
793 tlb_flush_page(cs, value);
b4ab8ce9 794 }
fa439fc5
PM		 795}
796
541ef8c2
SS		 797static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
798 uint64_t value)
799{
29a0af61 800 CPUState *cs = env_cpu(env);
541ef8c2 801
0336cbf8 802 tlb_flush_by_mmuidx(cs,
01b98b68 803 ARMMMUIdxBit_E10_1 |
452ef8cb 804 ARMMMUIdxBit_E10_1_PAN |
bf05340c 805 ARMMMUIdxBit_E10_0);
541ef8c2
SS		 806}
807
808static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
809 uint64_t value)
810{
29a0af61 811 CPUState *cs = env_cpu(env);
541ef8c2 812
a67cf277 813 tlb_flush_by_mmuidx_all_cpus_synced(cs,
01b98b68 814 ARMMMUIdxBit_E10_1 |
452ef8cb 815 ARMMMUIdxBit_E10_1_PAN |
bf05340c 816 ARMMMUIdxBit_E10_0);
541ef8c2
SS		 817}
818
541ef8c2
SS		 819
820static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
821 uint64_t value)
822{
29a0af61 823 CPUState *cs = env_cpu(env);
541ef8c2 824
e013b741 825 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);
541ef8c2
SS		 826}
827
828static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
829 uint64_t value)
830{
29a0af61 831 CPUState *cs = env_cpu(env);
541ef8c2 832
e013b741 833 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
541ef8c2
SS		 834}
835
836static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
837 uint64_t value)
838{
29a0af61 839 CPUState *cs = env_cpu(env);
541ef8c2
SS		 840 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
841
e013b741 842 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
541ef8c2
SS		 843}
844
845static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
846 uint64_t value)
847{
29a0af61 848 CPUState *cs = env_cpu(env);
541ef8c2
SS		 849 uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
850
a67cf277 851 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
e013b741 852 ARMMMUIdxBit_E2);
541ef8c2
SS		 853}
854
e9aa6c21 855static const ARMCPRegInfo cp_reginfo[] = {
54bf36ed
FA		 856 /* Define the secure and non-secure FCSE identifier CP registers
857 * separately because there is no secure bank in V8 (no _EL3). This allows
858 * the secure register to be properly reset and migrated. There is also no
859 * v8 EL1 version of the register so the non-secure instance stands alone.
860 */
9c513e78 861 { .name = "FCSEIDR",
54bf36ed
FA		 862 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
863 .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
864 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
865 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
9c513e78 866 { .name = "FCSEIDR_S",
54bf36ed
FA		 867 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
868 .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
869 .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
d4e6df63 870 .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
54bf36ed
FA		 871 /* Define the secure and non-secure context identifier CP registers
872 * separately because there is no secure bank in V8 (no _EL3). This allows
873 * the secure register to be properly reset and migrated. In the
874 * non-secure case, the 32-bit register will have reset and migration
875 * disabled during registration as it is handled by the 64-bit instance.
876 */
877 { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
014406b5 878 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
84929218
RH		 879 .access = PL1_RW, .accessfn = access_tvm_trvm,
880 .secure = ARM_CP_SECSTATE_NS,
54bf36ed
FA		 881 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
882 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
9c513e78 883 { .name = "CONTEXTIDR_S", .state = ARM_CP_STATE_AA32,
54bf36ed 884 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
84929218
RH		 885 .access = PL1_RW, .accessfn = access_tvm_trvm,
886 .secure = ARM_CP_SECSTATE_S,
54bf36ed 887 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
d4e6df63 888 .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
9449fdf6
PM		 889 REGINFO_SENTINEL
890};
891
892static const ARMCPRegInfo not_v8_cp_reginfo[] = {
893 /* NB: Some of these registers exist in v8 but with more precise
894 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
895 */
896 /* MMU Domain access control / MPU write buffer control */
0c17d68c
FA		 897 { .name = "DACR",
898 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
84929218 899 .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
0c17d68c
FA		 900 .writefn = dacr_write, .raw_writefn = raw_write,
901 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
902 offsetoflow32(CPUARMState, cp15.dacr_ns) } },
a903c449
EI		 903 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
904 * For v6 and v5, these mappings are overly broad.
4fdd17dd 905 */
a903c449
EI		 906 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
907 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
908 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
909 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
910 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
911 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
912 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
4fdd17dd 913 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
c4804214
PM		 914 /* Cache maintenance ops; some of this space may be overridden later. */
915 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
916 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
917 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
e9aa6c21
PM		 918 REGINFO_SENTINEL
919};
920
7d57f408
PM		 921static const ARMCPRegInfo not_v6_cp_reginfo[] = {
922 /* Not all pre-v6 cores implemented this WFI, so this is slightly
923 * over-broad.
924 */
925 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
926 .access = PL1_W, .type = ARM_CP_WFI },
927 REGINFO_SENTINEL
928};
929
930static const ARMCPRegInfo not_v7_cp_reginfo[] = {
931 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
932 * is UNPREDICTABLE; we choose to NOP as most implementations do).
933 */
934 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
935 .access = PL1_W, .type = ARM_CP_WFI },
34f90529
PM		 936 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
937 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
938 * OMAPCP will override this space.
939 */
940 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
941 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
942 .resetvalue = 0 },
943 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
944 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
945 .resetvalue = 0 },
776d4e5c
PM		 946 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
947 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
7a0e58fa 948 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
d4e6df63 949 .resetvalue = 0 },
50300698
PM		 950 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
951 * implementing it as RAZ means the "debug architecture version" bits
952 * will read as a reserved value, which should cause Linux to not try
953 * to use the debug hardware.
954 */
955 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
956 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
995939a6
PM		 957 /* MMU TLB control. Note that the wildcarding means we cover not just
958 * the unified TLB ops but also the dside/iside/inner-shareable variants.
959 */
960 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
961 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
7a0e58fa 962 .type = ARM_CP_NO_RAW },
995939a6
PM		 963 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
964 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
7a0e58fa 965 .type = ARM_CP_NO_RAW },
995939a6
PM		 966 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
967 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
7a0e58fa 968 .type = ARM_CP_NO_RAW },
995939a6
PM		 969 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
970 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
7a0e58fa 971 .type = ARM_CP_NO_RAW },
a903c449
EI		 972 { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2,
973 .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
974 { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
975 .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
7d57f408
PM		 976 REGINFO_SENTINEL
977};
978
c4241c7d
PM		 979static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
980 uint64_t value)
2771db27 981{
f0aff255
FA		 982 uint32_t mask = 0;
983
984 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
985 if (!arm_feature(env, ARM_FEATURE_V8)) {
986 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
987 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
988 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
989 */
7fbc6a40 990 if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
f0aff255
FA		 991 /* VFP coprocessor: cp10 & cp11 [23:20] */
992 mask |= (1 << 31) | (1 << 30) | (0xf << 20);
993
994 if (!arm_feature(env, ARM_FEATURE_NEON)) {
995 /* ASEDIS [31] bit is RAO/WI */
996 value |= (1 << 31);
997 }
998
999 /* VFPv3 and upwards with NEON implement 32 double precision
1000 * registers (D0-D31).
1001 */
a6627f5f 1002 if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) {
f0aff255
FA		 1003 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
1004 value |= (1 << 30);
1005 }
1006 }
1007 value &= mask;
2771db27 1008 }
fc1120a7
PM		 1009
1010 /*
1011 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
1012 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
1013 */
1014 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
1015 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
1016 value &= ~(0xf << 20);
1017 value |= env->cp15.cpacr_el1 & (0xf << 20);
1018 }
1019
7ebd5f2e 1020 env->cp15.cpacr_el1 = value;
2771db27
PM		 1021}
1022
fc1120a7
PM		 1023static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1024{
1025 /*
1026 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
1027 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
1028 */
1029 uint64_t value = env->cp15.cpacr_el1;
1030
1031 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
1032 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
1033 value &= ~(0xf << 20);
1034 }
1035 return value;
1036}
1037
1038
5deac39c
PM		 1039static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1040{
1041 /* Call cpacr_write() so that we reset with the correct RAO bits set
1042 * for our CPU features.
1043 */
1044 cpacr_write(env, ri, 0);
1045}
1046
3f208fd7
PM		 1047static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
1048 bool isread)
c6f19164
GB		 1049{
1050 if (arm_feature(env, ARM_FEATURE_V8)) {
1051 /* Check if CPACR accesses are to be trapped to EL2 */
1052 if (arm_current_el(env) == 1 &&
1053 (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
1054 return CP_ACCESS_TRAP_EL2;
1055 /* Check if CPACR accesses are to be trapped to EL3 */
1056 } else if (arm_current_el(env) < 3 &&
1057 (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
1058 return CP_ACCESS_TRAP_EL3;
1059 }
1060 }
1061
1062 return CP_ACCESS_OK;
1063}
1064
3f208fd7
PM		 1065static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri,
1066 bool isread)
c6f19164
GB		 1067{
1068 /* Check if CPTR accesses are set to trap to EL3 */
1069 if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
1070 return CP_ACCESS_TRAP_EL3;
1071 }
1072
1073 return CP_ACCESS_OK;
1074}
1075
7d57f408
PM		 1076static const ARMCPRegInfo v6_cp_reginfo[] = {
1077 /* prefetch by MVA in v6, NOP in v7 */
1078 { .name = "MVA_prefetch",
1079 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
1080 .access = PL1_W, .type = ARM_CP_NOP },
6df99dec
SS		 1081 /* We need to break the TB after ISB to execute self-modifying code
1082 * correctly and also to take any pending interrupts immediately.
1083 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
1084 */
7d57f408 1085 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
6df99dec 1086 .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
091fd17c 1087 { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
7d57f408 1088 .access = PL0_W, .type = ARM_CP_NOP },
091fd17c 1089 { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
7d57f408 1090 .access = PL0_W, .type = ARM_CP_NOP },
06d76f31 1091 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
84929218 1092 .access = PL1_RW, .accessfn = access_tvm_trvm,
b848ce2b
FA		 1093 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
1094 offsetof(CPUARMState, cp15.ifar_ns) },
06d76f31
PM		 1095 .resetvalue = 0, },
1096 /* Watchpoint Fault Address Register : should actually only be present
1097 * for 1136, 1176, 11MPCore.
1098 */
1099 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
1100 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
34222fb8 1101 { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
c6f19164 1102 .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
7ebd5f2e 1103 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
fc1120a7 1104 .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read },
7d57f408
PM		 1105 REGINFO_SENTINEL
1106};
1107
7ece99b1
AL		 1108/* Definitions for the PMU registers */
1109#define PMCRN_MASK 0xf800
1110#define PMCRN_SHIFT 11
f4efb4b2 1111#define PMCRLC 0x40
a1ed04dd
PM		 1112#define PMCRDP 0x20
1113#define PMCRX 0x10
7ece99b1
AL		 1114#define PMCRD 0x8
1115#define PMCRC 0x4
5ecdd3e4 1116#define PMCRP 0x2
7ece99b1 1117#define PMCRE 0x1
62d96ff4
PM		 1118/*
1119 * Mask of PMCR bits writeable by guest (not including WO bits like C, P,
1120 * which can be written as 1 to trigger behaviour but which stay RAZ).
1121 */
1122#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
7ece99b1 1123
033614c4
AL		 1124#define PMXEVTYPER_P 0x80000000
1125#define PMXEVTYPER_U 0x40000000
1126#define PMXEVTYPER_NSK 0x20000000
1127#define PMXEVTYPER_NSU 0x10000000
1128#define PMXEVTYPER_NSH 0x08000000
1129#define PMXEVTYPER_M 0x04000000
1130#define PMXEVTYPER_MT 0x02000000
1131#define PMXEVTYPER_EVTCOUNT 0x0000ffff
1132#define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
1133 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
1134 PMXEVTYPER_M | PMXEVTYPER_MT | \
1135 PMXEVTYPER_EVTCOUNT)
1136
4b8afa1f
AL		 1137#define PMCCFILTR 0xf8000000
1138#define PMCCFILTR_M PMXEVTYPER_M
1139#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
1140
7ece99b1
AL		 1141static inline uint32_t pmu_num_counters(CPUARMState *env)
1142{
1143 return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
1144}
1145
1146/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
1147static inline uint64_t pmu_counter_mask(CPUARMState *env)
1148{
1149 return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
1150}
1151
57a4a11b
AL		 1152typedef struct pm_event {
1153 uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */
1154 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
1155 bool (*supported)(CPUARMState *);
1156 /*
1157 * Retrieve the current count of the underlying event. The programmed
1158 * counters hold a difference from the return value from this function
1159 */
1160 uint64_t (*get_count)(CPUARMState *);
4e7beb0c
AL		 1161 /*
1162 * Return how many nanoseconds it will take (at a minimum) for count events
1163 * to occur. A negative value indicates the counter will never overflow, or
1164 * that the counter has otherwise arranged for the overflow bit to be set
1165 * and the PMU interrupt to be raised on overflow.
1166 */
1167 int64_t (*ns_per_count)(uint64_t);
57a4a11b
AL		 1168} pm_event;
1169
b2e23725
AL		 1170static bool event_always_supported(CPUARMState *env)
1171{
1172 return true;
1173}
1174
0d4bfd7d
AL		 1175static uint64_t swinc_get_count(CPUARMState *env)
1176{
1177 /*
1178 * SW_INCR events are written directly to the pmevcntr's by writes to
1179 * PMSWINC, so there is no underlying count maintained by the PMU itself
1180 */
1181 return 0;
1182}
1183
4e7beb0c
AL		 1184static int64_t swinc_ns_per(uint64_t ignored)
1185{
1186 return -1;
1187}
1188
b2e23725
AL		 1189/*
1190 * Return the underlying cycle count for the PMU cycle counters. If we're in
1191 * usermode, simply return 0.
1192 */
1193static uint64_t cycles_get_count(CPUARMState *env)
1194{
1195#ifndef CONFIG_USER_ONLY
1196 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
1197 ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
1198#else
1199 return cpu_get_host_ticks();
1200#endif
1201}
1202
1203#ifndef CONFIG_USER_ONLY
4e7beb0c
AL		 1204static int64_t cycles_ns_per(uint64_t cycles)
1205{
1206 return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles;
1207}
1208
b2e23725
AL		 1209static bool instructions_supported(CPUARMState *env)
1210{
740b1759 1211 return icount_enabled() == 1; /* Precise instruction counting */
b2e23725
AL		 1212}
1213
1214static uint64_t instructions_get_count(CPUARMState *env)
1215{
8191d368 1216 return (uint64_t)icount_get_raw();
b2e23725 1217}
4e7beb0c
AL		 1218
1219static int64_t instructions_ns_per(uint64_t icount)
1220{
8191d368 1221 return icount_to_ns((int64_t)icount);
4e7beb0c 1222}
b2e23725
AL		 1223#endif
1224
0727f63b
PM		 1225static bool pmu_8_1_events_supported(CPUARMState *env)
1226{
1227 /* For events which are supported in any v8.1 PMU */
1228 return cpu_isar_feature(any_pmu_8_1, env_archcpu(env));
1229}
1230
15dd1ebd
PM		 1231static bool pmu_8_4_events_supported(CPUARMState *env)
1232{
1233 /* For events which are supported in any v8.1 PMU */
1234 return cpu_isar_feature(any_pmu_8_4, env_archcpu(env));
1235}
1236
0727f63b
PM		 1237static uint64_t zero_event_get_count(CPUARMState *env)
1238{
1239 /* For events which on QEMU never fire, so their count is always zero */
1240 return 0;
1241}
1242
1243static int64_t zero_event_ns_per(uint64_t cycles)
1244{
1245 /* An event which never fires can never overflow */
1246 return -1;
1247}
1248
57a4a11b 1249static const pm_event pm_events[] = {
0d4bfd7d
AL		 1250 { .number = 0x000, /* SW_INCR */
1251 .supported = event_always_supported,
1252 .get_count = swinc_get_count,
4e7beb0c 1253 .ns_per_count = swinc_ns_per,
0d4bfd7d 1254 },
b2e23725
AL		 1255#ifndef CONFIG_USER_ONLY
1256 { .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */
1257 .supported = instructions_supported,
1258 .get_count = instructions_get_count,
4e7beb0c 1259 .ns_per_count = instructions_ns_per,
b2e23725
AL		 1260 },
1261 { .number = 0x011, /* CPU_CYCLES, Cycle */
1262 .supported = event_always_supported,
1263 .get_count = cycles_get_count,
4e7beb0c 1264 .ns_per_count = cycles_ns_per,
0727f63b 1265 },
b2e23725 1266#endif
0727f63b
PM		 1267 { .number = 0x023, /* STALL_FRONTEND */
1268 .supported = pmu_8_1_events_supported,
1269 .get_count = zero_event_get_count,
1270 .ns_per_count = zero_event_ns_per,
1271 },
1272 { .number = 0x024, /* STALL_BACKEND */
1273 .supported = pmu_8_1_events_supported,
1274 .get_count = zero_event_get_count,
1275 .ns_per_count = zero_event_ns_per,
1276 },
15dd1ebd
PM		 1277 { .number = 0x03c, /* STALL */
1278 .supported = pmu_8_4_events_supported,
1279 .get_count = zero_event_get_count,
1280 .ns_per_count = zero_event_ns_per,
1281 },
57a4a11b
AL		 1282};
1283
1284/*
1285 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1286 * events (i.e. the statistical profiling extension), this implementation
1287 * should first be updated to something sparse instead of the current
1288 * supported_event_map[] array.
1289 */
15dd1ebd 1290#define MAX_EVENT_ID 0x3c
57a4a11b
AL		 1291#define UNSUPPORTED_EVENT UINT16_MAX
1292static uint16_t supported_event_map[MAX_EVENT_ID + 1];
1293
1294/*
bf8d0969
AL		 1295 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1296 * of ARM event numbers to indices in our pm_events array.
57a4a11b
AL		 1297 *
1298 * Note: Events in the 0x40XX range are not currently supported.
1299 */
bf8d0969 1300void pmu_init(ARMCPU *cpu)
57a4a11b 1301{
57a4a11b
AL		 1302 unsigned int i;
1303
bf8d0969
AL		 1304 /*
1305 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1306 * events to them
1307 */
57a4a11b
AL		 1308 for (i = 0; i < ARRAY_SIZE(supported_event_map); i++) {
1309 supported_event_map[i] = UNSUPPORTED_EVENT;
1310 }
bf8d0969
AL		 1311 cpu->pmceid0 = 0;
1312 cpu->pmceid1 = 0;
57a4a11b
AL		 1313
1314 for (i = 0; i < ARRAY_SIZE(pm_events); i++) {
1315 const pm_event *cnt = &pm_events[i];
1316 assert(cnt->number <= MAX_EVENT_ID);
1317 /* We do not currently support events in the 0x40xx range */
1318 assert(cnt->number <= 0x3f);
1319
bf8d0969 1320 if (cnt->supported(&cpu->env)) {
57a4a11b 1321 supported_event_map[cnt->number] = i;
67da43d6 1322 uint64_t event_mask = 1ULL << (cnt->number & 0x1f);
bf8d0969
AL		 1323 if (cnt->number & 0x20) {
1324 cpu->pmceid1 |= event_mask;
1325 } else {
1326 cpu->pmceid0 |= event_mask;
1327 }
57a4a11b
AL		 1328 }
1329 }
57a4a11b
AL		 1330}
1331
5ecdd3e4
AL		 1332/*
1333 * Check at runtime whether a PMU event is supported for the current machine
1334 */
1335static bool event_supported(uint16_t number)
1336{
1337 if (number > MAX_EVENT_ID) {
1338 return false;
1339 }
1340 return supported_event_map[number] != UNSUPPORTED_EVENT;
1341}
1342
3f208fd7
PM		 1343static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
1344 bool isread)
200ac0ef 1345{
3b163b01 1346 /* Performance monitor registers user accessibility is controlled
1fce1ba9
PM		 1347 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1348 * trapping to EL2 or EL3 for other accesses.
200ac0ef 1349 */
1fce1ba9
PM		 1350 int el = arm_current_el(env);
1351
6ecd0b6b 1352 if (el == 0 && !(env->cp15.c9_pmuserenr & 1)) {
fcd25206 1353 return CP_ACCESS_TRAP;
200ac0ef 1354 }
1fce1ba9
PM		 1355 if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
1356 && !arm_is_secure_below_el3(env)) {
1357 return CP_ACCESS_TRAP_EL2;
1358 }
1359 if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
1360 return CP_ACCESS_TRAP_EL3;
1361 }
1362
fcd25206 1363 return CP_ACCESS_OK;
200ac0ef
PM		 1364}
1365
6ecd0b6b
AB		 1366static CPAccessResult pmreg_access_xevcntr(CPUARMState *env,
1367 const ARMCPRegInfo *ri,
1368 bool isread)
1369{
1370 /* ER: event counter read trap control */
1371 if (arm_feature(env, ARM_FEATURE_V8)
1372 && arm_current_el(env) == 0
1373 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0
1374 && isread) {
1375 return CP_ACCESS_OK;
1376 }
1377
1378 return pmreg_access(env, ri, isread);
1379}
1380
1381static CPAccessResult pmreg_access_swinc(CPUARMState *env,
1382 const ARMCPRegInfo *ri,
1383 bool isread)
1384{
1385 /* SW: software increment write trap control */
1386 if (arm_feature(env, ARM_FEATURE_V8)
1387 && arm_current_el(env) == 0
1388 && (env->cp15.c9_pmuserenr & (1 << 1)) != 0
1389 && !isread) {
1390 return CP_ACCESS_OK;
1391 }
1392
1393 return pmreg_access(env, ri, isread);
1394}
1395
6ecd0b6b
AB		 1396static CPAccessResult pmreg_access_selr(CPUARMState *env,
1397 const ARMCPRegInfo *ri,
1398 bool isread)
1399{
1400 /* ER: event counter read trap control */
1401 if (arm_feature(env, ARM_FEATURE_V8)
1402 && arm_current_el(env) == 0
1403 && (env->cp15.c9_pmuserenr & (1 << 3)) != 0) {
1404 return CP_ACCESS_OK;
1405 }
1406
1407 return pmreg_access(env, ri, isread);
1408}
1409
1410static CPAccessResult pmreg_access_ccntr(CPUARMState *env,
1411 const ARMCPRegInfo *ri,
1412 bool isread)
1413{
1414 /* CR: cycle counter read trap control */
1415 if (arm_feature(env, ARM_FEATURE_V8)
1416 && arm_current_el(env) == 0
1417 && (env->cp15.c9_pmuserenr & (1 << 2)) != 0
1418 && isread) {
1419 return CP_ACCESS_OK;
1420 }
1421
1422 return pmreg_access(env, ri, isread);
1423}
1424
033614c4
AL		 1425/* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1426 * the current EL, security state, and register configuration.
1427 */
1428static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
87124fde 1429{
033614c4
AL		 1430 uint64_t filter;
1431 bool e, p, u, nsk, nsu, nsh, m;
1432 bool enabled, prohibited, filtered;
1433 bool secure = arm_is_secure(env);
1434 int el = arm_current_el(env);
1435 uint8_t hpmn = env->cp15.mdcr_el2 & MDCR_HPMN;
87124fde 1436
cbbb3041
AJ		 1437 if (!arm_feature(env, ARM_FEATURE_PMU)) {
1438 return false;
1439 }
1440
033614c4
AL		 1441 if (!arm_feature(env, ARM_FEATURE_EL2) ||
1442 (counter < hpmn || counter == 31)) {
1443 e = env->cp15.c9_pmcr & PMCRE;
1444 } else {
1445 e = env->cp15.mdcr_el2 & MDCR_HPME;
87124fde 1446 }
033614c4 1447 enabled = e && (env->cp15.c9_pmcnten & (1 << counter));
87124fde 1448
033614c4
AL		 1449 if (!secure) {
1450 if (el == 2 && (counter < hpmn || counter == 31)) {
1451 prohibited = env->cp15.mdcr_el2 & MDCR_HPMD;
1452 } else {
1453 prohibited = false;
1454 }
1455 } else {
1456 prohibited = arm_feature(env, ARM_FEATURE_EL3) &&
db1f3afb 1457 !(env->cp15.mdcr_el3 & MDCR_SPME);
033614c4
AL		 1458 }
1459
1460 if (prohibited && counter == 31) {
1461 prohibited = env->cp15.c9_pmcr & PMCRDP;
1462 }
1463
5ecdd3e4
AL		 1464 if (counter == 31) {
1465 filter = env->cp15.pmccfiltr_el0;
1466 } else {
1467 filter = env->cp15.c14_pmevtyper[counter];
1468 }
033614c4
AL		 1469
1470 p = filter & PMXEVTYPER_P;
1471 u = filter & PMXEVTYPER_U;
1472 nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK);
1473 nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU);
1474 nsh = arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH);
1475 m = arm_el_is_aa64(env, 1) &&
1476 arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M);
1477
1478 if (el == 0) {
1479 filtered = secure ? u : u != nsu;
1480 } else if (el == 1) {
1481 filtered = secure ? p : p != nsk;
1482 } else if (el == 2) {
1483 filtered = !nsh;
1484 } else { /* EL3 */
1485 filtered = m != p;
1486 }
1487
5ecdd3e4
AL		 1488 if (counter != 31) {
1489 /*
1490 * If not checking PMCCNTR, ensure the counter is setup to an event we
1491 * support
1492 */
1493 uint16_t event = filter & PMXEVTYPER_EVTCOUNT;
1494 if (!event_supported(event)) {
1495 return false;
1496 }
1497 }
1498
033614c4 1499 return enabled && !prohibited && !filtered;
87124fde 1500}
033614c4 1501
f4efb4b2
AL		 1502static void pmu_update_irq(CPUARMState *env)
1503{
2fc0cc0e 1504 ARMCPU *cpu = env_archcpu(env);
f4efb4b2
AL		 1505 qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) &&
1506 (env->cp15.c9_pminten & env->cp15.c9_pmovsr));
1507}
1508
5d05b9d4
AL		 1509/*
1510 * Ensure c15_ccnt is the guest-visible count so that operations such as
1511 * enabling/disabling the counter or filtering, modifying the count itself,
1512 * etc. can be done logically. This is essentially a no-op if the counter is
1513 * not enabled at the time of the call.
1514 */
f2b2f53f 1515static void pmccntr_op_start(CPUARMState *env)
ec7b4ce4 1516{
b2e23725 1517 uint64_t cycles = cycles_get_count(env);
ec7b4ce4 1518
033614c4 1519 if (pmu_counter_enabled(env, 31)) {
5d05b9d4
AL		 1520 uint64_t eff_cycles = cycles;
1521 if (env->cp15.c9_pmcr & PMCRD) {
1522 /* Increment once every 64 processor clock cycles */
1523 eff_cycles /= 64;
1524 }
1525
f4efb4b2
AL		 1526 uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta;
1527
1528 uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \
1529 1ull << 63 : 1ull << 31;
1530 if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) {
1531 env->cp15.c9_pmovsr |= (1 << 31);
1532 pmu_update_irq(env);
1533 }
1534
1535 env->cp15.c15_ccnt = new_pmccntr;
ec7b4ce4 1536 }
5d05b9d4
AL		 1537 env->cp15.c15_ccnt_delta = cycles;
1538}
ec7b4ce4 1539
5d05b9d4
AL		 1540/*
1541 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1542 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1543 * pmccntr_op_start.
1544 */
f2b2f53f 1545static void pmccntr_op_finish(CPUARMState *env)
5d05b9d4 1546{
033614c4 1547 if (pmu_counter_enabled(env, 31)) {
4e7beb0c
AL		 1548#ifndef CONFIG_USER_ONLY
1549 /* Calculate when the counter will next overflow */
1550 uint64_t remaining_cycles = -env->cp15.c15_ccnt;
1551 if (!(env->cp15.c9_pmcr & PMCRLC)) {
1552 remaining_cycles = (uint32_t)remaining_cycles;
1553 }
1554 int64_t overflow_in = cycles_ns_per(remaining_cycles);
1555
1556 if (overflow_in > 0) {
1557 int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1558 overflow_in;
2fc0cc0e 1559 ARMCPU *cpu = env_archcpu(env);
4e7beb0c
AL		 1560 timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at);
1561 }
1562#endif
5d05b9d4 1563
4e7beb0c 1564 uint64_t prev_cycles = env->cp15.c15_ccnt_delta;
5d05b9d4
AL		 1565 if (env->cp15.c9_pmcr & PMCRD) {
1566 /* Increment once every 64 processor clock cycles */
1567 prev_cycles /= 64;
1568 }
5d05b9d4 1569 env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt;
ec7b4ce4
AF		 1570 }
1571}
1572
5ecdd3e4
AL		 1573static void pmevcntr_op_start(CPUARMState *env, uint8_t counter)
1574{
1575
1576 uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT;
1577 uint64_t count = 0;
1578 if (event_supported(event)) {
1579 uint16_t event_idx = supported_event_map[event];
1580 count = pm_events[event_idx].get_count(env);
1581 }
1582
1583 if (pmu_counter_enabled(env, counter)) {
f4efb4b2
AL		 1584 uint32_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter];
1585
1586 if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & INT32_MIN) {
1587 env->cp15.c9_pmovsr |= (1 << counter);
1588 pmu_update_irq(env);
1589 }
1590 env->cp15.c14_pmevcntr[counter] = new_pmevcntr;
5ecdd3e4
AL		 1591 }
1592 env->cp15.c14_pmevcntr_delta[counter] = count;
1593}
1594
1595static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter)
1596{
1597 if (pmu_counter_enabled(env, counter)) {
4e7beb0c
AL		 1598#ifndef CONFIG_USER_ONLY
1599 uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT;
1600 uint16_t event_idx = supported_event_map[event];
1601 uint64_t delta = UINT32_MAX -
1602 (uint32_t)env->cp15.c14_pmevcntr[counter] + 1;
1603 int64_t overflow_in = pm_events[event_idx].ns_per_count(delta);
1604
1605 if (overflow_in > 0) {
1606 int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1607 overflow_in;
2fc0cc0e 1608 ARMCPU *cpu = env_archcpu(env);
4e7beb0c
AL		 1609 timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at);
1610 }
1611#endif
1612
5ecdd3e4
AL		 1613 env->cp15.c14_pmevcntr_delta[counter] -=
1614 env->cp15.c14_pmevcntr[counter];
1615 }
1616}
1617
5d05b9d4
AL		 1618void pmu_op_start(CPUARMState *env)
1619{
5ecdd3e4 1620 unsigned int i;
5d05b9d4 1621 pmccntr_op_start(env);
5ecdd3e4
AL		 1622 for (i = 0; i < pmu_num_counters(env); i++) {
1623 pmevcntr_op_start(env, i);
1624 }
5d05b9d4
AL		 1625}
1626
1627void pmu_op_finish(CPUARMState *env)
1628{
5ecdd3e4 1629 unsigned int i;
5d05b9d4 1630 pmccntr_op_finish(env);
5ecdd3e4
AL		 1631 for (i = 0; i < pmu_num_counters(env); i++) {
1632 pmevcntr_op_finish(env, i);
1633 }
5d05b9d4
AL		 1634}
1635
033614c4
AL		 1636void pmu_pre_el_change(ARMCPU *cpu, void *ignored)
1637{
1638 pmu_op_start(&cpu->env);
1639}
1640
1641void pmu_post_el_change(ARMCPU *cpu, void *ignored)
1642{
1643 pmu_op_finish(&cpu->env);
1644}
1645
4e7beb0c
AL		 1646void arm_pmu_timer_cb(void *opaque)
1647{
1648 ARMCPU *cpu = opaque;
1649
1650 /*
1651 * Update all the counter values based on the current underlying counts,
1652 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1653 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1654 * counter may expire.
1655 */
1656 pmu_op_start(&cpu->env);
1657 pmu_op_finish(&cpu->env);
1658}
1659
c4241c7d
PM		 1660static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1661 uint64_t value)
200ac0ef 1662{
5d05b9d4 1663 pmu_op_start(env);
7c2cb42b
AF		 1664
1665 if (value & PMCRC) {
1666 /* The counter has been reset */
1667 env->cp15.c15_ccnt = 0;
1668 }
1669
5ecdd3e4
AL		 1670 if (value & PMCRP) {
1671 unsigned int i;
1672 for (i = 0; i < pmu_num_counters(env); i++) {
1673 env->cp15.c14_pmevcntr[i] = 0;
1674 }
1675 }
1676
62d96ff4
PM		 1677 env->cp15.c9_pmcr &= ~PMCR_WRITEABLE_MASK;
1678 env->cp15.c9_pmcr |= (value & PMCR_WRITEABLE_MASK);
7c2cb42b 1679
5d05b9d4 1680 pmu_op_finish(env);
7c2cb42b
AF		 1681}
1682
0d4bfd7d
AL		 1683static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri,
1684 uint64_t value)
1685{
1686 unsigned int i;
1687 for (i = 0; i < pmu_num_counters(env); i++) {
1688 /* Increment a counter's count iff: */
1689 if ((value & (1 << i)) && /* counter's bit is set */
1690 /* counter is enabled and not filtered */
1691 pmu_counter_enabled(env, i) &&
1692 /* counter is SW_INCR */
1693 (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) {
1694 pmevcntr_op_start(env, i);
f4efb4b2
AL		 1695
1696 /*
1697 * Detect if this write causes an overflow since we can't predict
1698 * PMSWINC overflows like we can for other events
1699 */
1700 uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1;
1701
1702 if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) {
1703 env->cp15.c9_pmovsr |= (1 << i);
1704 pmu_update_irq(env);
1705 }
1706
1707 env->cp15.c14_pmevcntr[i] = new_pmswinc;
1708
0d4bfd7d
AL		 1709 pmevcntr_op_finish(env, i);
1710 }
1711 }
1712}
1713
7c2cb42b
AF		 1714static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1715{
5d05b9d4
AL		 1716 uint64_t ret;
1717 pmccntr_op_start(env);
1718 ret = env->cp15.c15_ccnt;
1719 pmccntr_op_finish(env);
1720 return ret;
7c2cb42b
AF		 1721}
1722
6b040780
WH		 1723static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1724 uint64_t value)
1725{
1726 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1727 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1728 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1729 * accessed.
1730 */
1731 env->cp15.c9_pmselr = value & 0x1f;
1732}
1733
7c2cb42b
AF		 1734static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1735 uint64_t value)
1736{
5d05b9d4
AL		 1737 pmccntr_op_start(env);
1738 env->cp15.c15_ccnt = value;
1739 pmccntr_op_finish(env);
200ac0ef 1740}
421c7ebd
PC		 1741
1742static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
1743 uint64_t value)
1744{
1745 uint64_t cur_val = pmccntr_read(env, NULL);
1746
1747 pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
1748}
1749
0614601c
AF		 1750static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1751 uint64_t value)
1752{
5d05b9d4 1753 pmccntr_op_start(env);
4b8afa1f
AL		 1754 env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0;
1755 pmccntr_op_finish(env);
1756}
1757
1758static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri,
1759 uint64_t value)
1760{
1761 pmccntr_op_start(env);
1762 /* M is not accessible from AArch32 */
1763 env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) |
1764 (value & PMCCFILTR);
5d05b9d4 1765 pmccntr_op_finish(env);
0614601c
AF		 1766}
1767
4b8afa1f
AL		 1768static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri)
1769{
1770 /* M is not visible in AArch32 */
1771 return env->cp15.pmccfiltr_el0 & PMCCFILTR;
1772}
1773
c4241c7d 1774static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
200ac0ef
PM		 1775 uint64_t value)
1776{
7ece99b1 1777 value &= pmu_counter_mask(env);
200ac0ef 1778 env->cp15.c9_pmcnten |= value;
200ac0ef
PM		 1779}
1780
c4241c7d
PM		 1781static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1782 uint64_t value)
200ac0ef 1783{
7ece99b1 1784 value &= pmu_counter_mask(env);
200ac0ef 1785 env->cp15.c9_pmcnten &= ~value;
200ac0ef
PM		 1786}
1787
c4241c7d
PM		 1788static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1789 uint64_t value)
200ac0ef 1790{
599b71e2 1791 value &= pmu_counter_mask(env);
200ac0ef 1792 env->cp15.c9_pmovsr &= ~value;
f4efb4b2 1793 pmu_update_irq(env);
200ac0ef
PM		 1794}
1795
327dd510
AL		 1796static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri,
1797 uint64_t value)
1798{
1799 value &= pmu_counter_mask(env);
1800 env->cp15.c9_pmovsr |= value;
f4efb4b2 1801 pmu_update_irq(env);
327dd510
AL		 1802}
1803
5ecdd3e4
AL		 1804static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
1805 uint64_t value, const uint8_t counter)
200ac0ef 1806{
5ecdd3e4
AL		 1807 if (counter == 31) {
1808 pmccfiltr_write(env, ri, value);
1809 } else if (counter < pmu_num_counters(env)) {
1810 pmevcntr_op_start(env, counter);
1811
1812 /*
1813 * If this counter's event type is changing, store the current
1814 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1815 * pmevcntr_op_finish has the correct baseline when it converts back to
1816 * a delta.
1817 */
1818 uint16_t old_event = env->cp15.c14_pmevtyper[counter] &
1819 PMXEVTYPER_EVTCOUNT;
1820 uint16_t new_event = value & PMXEVTYPER_EVTCOUNT;
1821 if (old_event != new_event) {
1822 uint64_t count = 0;
1823 if (event_supported(new_event)) {
1824 uint16_t event_idx = supported_event_map[new_event];
1825 count = pm_events[event_idx].get_count(env);
1826 }
1827 env->cp15.c14_pmevcntr_delta[counter] = count;
1828 }
1829
1830 env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK;
1831 pmevcntr_op_finish(env, counter);
1832 }
fdb86656
WH		 1833 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1834 * PMSELR value is equal to or greater than the number of implemented
1835 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1836 */
5ecdd3e4
AL		 1837}
1838
1839static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri,
1840 const uint8_t counter)
1841{
1842 if (counter == 31) {
1843 return env->cp15.pmccfiltr_el0;
1844 } else if (counter < pmu_num_counters(env)) {
1845 return env->cp15.c14_pmevtyper[counter];
1846 } else {
1847 /*
1848 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1849 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1850 */
1851 return 0;
1852 }
1853}
1854
1855static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri,
1856 uint64_t value)
1857{
1858 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1859 pmevtyper_write(env, ri, value, counter);
1860}
1861
1862static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri,
1863 uint64_t value)
1864{
1865 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1866 env->cp15.c14_pmevtyper[counter] = value;
1867
1868 /*
1869 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1870 * pmu_op_finish calls when loading saved state for a migration. Because
1871 * we're potentially updating the type of event here, the value written to
1872 * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
1873 * different counter type. Therefore, we need to set this value to the
1874 * current count for the counter type we're writing so that pmu_op_finish
1875 * has the correct count for its calculation.
1876 */
1877 uint16_t event = value & PMXEVTYPER_EVTCOUNT;
1878 if (event_supported(event)) {
1879 uint16_t event_idx = supported_event_map[event];
1880 env->cp15.c14_pmevcntr_delta[counter] =
1881 pm_events[event_idx].get_count(env);
fdb86656
WH		 1882 }
1883}
1884
5ecdd3e4
AL		 1885static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
1886{
1887 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1888 return pmevtyper_read(env, ri, counter);
1889}
1890
1891static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
1892 uint64_t value)
1893{
1894 pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31);
1895}
1896
fdb86656
WH		 1897static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri)
1898{
5ecdd3e4
AL		 1899 return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31);
1900}
1901
1902static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1903 uint64_t value, uint8_t counter)
1904{
1905 if (counter < pmu_num_counters(env)) {
1906 pmevcntr_op_start(env, counter);
1907 env->cp15.c14_pmevcntr[counter] = value;
1908 pmevcntr_op_finish(env, counter);
1909 }
1910 /*
1911 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1912 * are CONSTRAINED UNPREDICTABLE.
fdb86656 1913 */
5ecdd3e4
AL		 1914}
1915
1916static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri,
1917 uint8_t counter)
1918{
1919 if (counter < pmu_num_counters(env)) {
1920 uint64_t ret;
1921 pmevcntr_op_start(env, counter);
1922 ret = env->cp15.c14_pmevcntr[counter];
1923 pmevcntr_op_finish(env, counter);
1924 return ret;
fdb86656 1925 } else {
5ecdd3e4
AL		 1926 /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1927 * are CONSTRAINED UNPREDICTABLE. */
fdb86656
WH		 1928 return 0;
1929 }
200ac0ef
PM		 1930}
1931
5ecdd3e4
AL		 1932static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri,
1933 uint64_t value)
1934{
1935 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1936 pmevcntr_write(env, ri, value, counter);
1937}
1938
1939static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
1940{
1941 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1942 return pmevcntr_read(env, ri, counter);
1943}
1944
1945static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri,
1946 uint64_t value)
1947{
1948 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1949 assert(counter < pmu_num_counters(env));
1950 env->cp15.c14_pmevcntr[counter] = value;
1951 pmevcntr_write(env, ri, value, counter);
1952}
1953
1954static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri)
1955{
1956 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
1957 assert(counter < pmu_num_counters(env));
1958 return env->cp15.c14_pmevcntr[counter];
1959}
1960
1961static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1962 uint64_t value)
1963{
1964 pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31);
1965}
1966
1967static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1968{
1969 return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31);
1970}
1971
c4241c7d 1972static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
200ac0ef
PM		 1973 uint64_t value)
1974{
6ecd0b6b
AB		 1975 if (arm_feature(env, ARM_FEATURE_V8)) {
1976 env->cp15.c9_pmuserenr = value & 0xf;
1977 } else {
1978 env->cp15.c9_pmuserenr = value & 1;
1979 }
200ac0ef
PM		 1980}
1981
c4241c7d
PM		 1982static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
1983 uint64_t value)
200ac0ef
PM		 1984{
1985 /* We have no event counters so only the C bit can be changed */
7ece99b1 1986 value &= pmu_counter_mask(env);
200ac0ef 1987 env->cp15.c9_pminten |= value;
f4efb4b2 1988 pmu_update_irq(env);
200ac0ef
PM		 1989}
1990
c4241c7d
PM		 1991static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1992 uint64_t value)
200ac0ef 1993{
7ece99b1 1994 value &= pmu_counter_mask(env);
200ac0ef 1995 env->cp15.c9_pminten &= ~value;
f4efb4b2 1996 pmu_update_irq(env);
200ac0ef
PM		 1997}
1998
c4241c7d
PM		 1999static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2000 uint64_t value)
8641136c 2001{
a505d7fe
PM		 2002 /* Note that even though the AArch64 view of this register has bits
2003 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
2004 * architectural requirements for bits which are RES0 only in some
2005 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
2006 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
2007 */
855ea66d 2008 raw_write(env, ri, value & ~0x1FULL);
8641136c
NR		 2009}
2010
64e0e2de
EI		 2011static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
2012{
ea22747c
RH		 2013 /* Begin with base v8.0 state. */
2014 uint32_t valid_mask = 0x3fff;
2fc0cc0e 2015 ARMCPU *cpu = env_archcpu(env);
ea22747c 2016
252e8c69 2017 if (ri->state == ARM_CP_STATE_AA64) {
ea22747c
RH		 2018 value |= SCR_FW | SCR_AW; /* these two bits are RES1. */
2019 valid_mask &= ~SCR_NET;
252e8c69
RH		 2020
2021 if (cpu_isar_feature(aa64_lor, cpu)) {
2022 valid_mask |= SCR_TLOR;
2023 }
2024 if (cpu_isar_feature(aa64_pauth, cpu)) {
2025 valid_mask |= SCR_API | SCR_APK;
2026 }
8ddb300b
RH		 2027 if (cpu_isar_feature(aa64_mte, cpu)) {
2028 valid_mask |= SCR_ATA;
2029 }
ea22747c
RH		 2030 } else {
2031 valid_mask &= ~(SCR_RW | SCR_ST);
2032 }
64e0e2de
EI		 2033
2034 if (!arm_feature(env, ARM_FEATURE_EL2)) {
2035 valid_mask &= ~SCR_HCE;
2036
2037 /* On ARMv7, SMD (or SCD as it is called in v7) is only
2038 * supported if EL2 exists. The bit is UNK/SBZP when
2039 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
2040 * when EL2 is unavailable.
4eb27640 2041 * On ARMv8, this bit is always available.
64e0e2de 2042 */
4eb27640
GB		 2043 if (arm_feature(env, ARM_FEATURE_V7) &&
2044 !arm_feature(env, ARM_FEATURE_V8)) {
64e0e2de
EI		 2045 valid_mask &= ~SCR_SMD;
2046 }
2047 }
2048
2049 /* Clear all-context RES0 bits. */
2050 value &= valid_mask;
2051 raw_write(env, ri, value);
2052}
2053
630fcd4d
MZ		 2054static CPAccessResult access_aa64_tid2(CPUARMState *env,
2055 const ARMCPRegInfo *ri,
2056 bool isread)
2057{
2058 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) {
2059 return CP_ACCESS_TRAP_EL2;
2060 }
2061
2062 return CP_ACCESS_OK;
2063}
2064
c4241c7d 2065static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
776d4e5c 2066{
2fc0cc0e 2067 ARMCPU *cpu = env_archcpu(env);
b85a1fd6
FA		 2068
2069 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
2070 * bank
2071 */
2072 uint32_t index = A32_BANKED_REG_GET(env, csselr,
2073 ri->secure & ARM_CP_SECSTATE_S);
2074
2075 return cpu->ccsidr[index];
776d4e5c
PM		 2076}
2077
c4241c7d
PM		 2078static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2079 uint64_t value)
776d4e5c 2080{
8d5c773e 2081 raw_write(env, ri, value & 0xf);
776d4e5c
PM		 2082}
2083
1090b9c6
PM		 2084static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2085{
29a0af61 2086 CPUState *cs = env_cpu(env);
cc974d5c
RDC		 2087 bool el1 = arm_current_el(env) == 1;
2088 uint64_t hcr_el2 = el1 ? arm_hcr_el2_eff(env) : 0;
1090b9c6
PM		 2089 uint64_t ret = 0;
2090
cc974d5c 2091 if (hcr_el2 & HCR_IMO) {
636540e9
PM		 2092 if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
2093 ret |= CPSR_I;
2094 }
2095 } else {
2096 if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
2097 ret |= CPSR_I;
2098 }
1090b9c6 2099 }
636540e9 2100
cc974d5c 2101 if (hcr_el2 & HCR_FMO) {
636540e9
PM		 2102 if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
2103 ret |= CPSR_F;
2104 }
2105 } else {
2106 if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
2107 ret |= CPSR_F;
2108 }
1090b9c6 2109 }
636540e9 2110
1090b9c6
PM		 2111 /* External aborts are not possible in QEMU so A bit is always clear */
2112 return ret;
2113}
2114
93fbc983
MZ		 2115static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInfo *ri,
2116 bool isread)
2117{
2118 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID1)) {
2119 return CP_ACCESS_TRAP_EL2;
2120 }
2121
2122 return CP_ACCESS_OK;
2123}
2124
2125static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInfo *ri,
2126 bool isread)
2127{
2128 if (arm_feature(env, ARM_FEATURE_V8)) {
2129 return access_aa64_tid1(env, ri, isread);
2130 }
2131
2132 return CP_ACCESS_OK;
2133}
2134
e9aa6c21 2135static const ARMCPRegInfo v7_cp_reginfo[] = {
7d57f408
PM		 2136 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
2137 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
2138 .access = PL1_W, .type = ARM_CP_NOP },
200ac0ef
PM		 2139 /* Performance monitors are implementation defined in v7,
2140 * but with an ARM recommended set of registers, which we
ac689a2e 2141 * follow.
200ac0ef
PM		 2142 *
2143 * Performance registers fall into three categories:
2144 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2145 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2146 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2147 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2148 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2149 */
2150 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
7a0e58fa 2151 .access = PL0_RW, .type = ARM_CP_ALIAS,
8521466b 2152 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
fcd25206
PM		 2153 .writefn = pmcntenset_write,
2154 .accessfn = pmreg_access,
2155 .raw_writefn = raw_write },
8521466b
AF		 2156 { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
2157 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
2158 .access = PL0_RW, .accessfn = pmreg_access,
2159 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
2160 .writefn = pmcntenset_write, .raw_writefn = raw_write },
200ac0ef 2161 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
8521466b
AF		 2162 .access = PL0_RW,
2163 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
fcd25206
PM		 2164 .accessfn = pmreg_access,
2165 .writefn = pmcntenclr_write,
7a0e58fa 2166 .type = ARM_CP_ALIAS },
8521466b
AF		 2167 { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
2168 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
2169 .access = PL0_RW, .accessfn = pmreg_access,
7a0e58fa 2170 .type = ARM_CP_ALIAS,
8521466b
AF		 2171 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
2172 .writefn = pmcntenclr_write },
200ac0ef 2173 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
f4efb4b2 2174 .access = PL0_RW, .type = ARM_CP_IO,
e4e91a21 2175 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
fcd25206
PM		 2176 .accessfn = pmreg_access,
2177 .writefn = pmovsr_write,
2178 .raw_writefn = raw_write },
978364f1
AF		 2179 { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
2180 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
2181 .access = PL0_RW, .accessfn = pmreg_access,
f4efb4b2 2182 .type = ARM_CP_ALIAS | ARM_CP_IO,
978364f1
AF		 2183 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
2184 .writefn = pmovsr_write,
2185 .raw_writefn = raw_write },
200ac0ef 2186 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
f4efb4b2
AL		 2187 .access = PL0_W, .accessfn = pmreg_access_swinc,
2188 .type = ARM_CP_NO_RAW | ARM_CP_IO,
0d4bfd7d
AL		 2189 .writefn = pmswinc_write },
2190 { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64,
2191 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4,
f4efb4b2
AL		 2192 .access = PL0_W, .accessfn = pmreg_access_swinc,
2193 .type = ARM_CP_NO_RAW | ARM_CP_IO,
0d4bfd7d 2194 .writefn = pmswinc_write },
6b040780
WH		 2195 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
2196 .access = PL0_RW, .type = ARM_CP_ALIAS,
2197 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
6ecd0b6b 2198 .accessfn = pmreg_access_selr, .writefn = pmselr_write,
6b040780
WH		 2199 .raw_writefn = raw_write},
2200 { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
2201 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
6ecd0b6b 2202 .access = PL0_RW, .accessfn = pmreg_access_selr,
6b040780
WH		 2203 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
2204 .writefn = pmselr_write, .raw_writefn = raw_write, },
200ac0ef 2205 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
169c8938 2206 .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO,
421c7ebd 2207 .readfn = pmccntr_read, .writefn = pmccntr_write32,
6ecd0b6b 2208 .accessfn = pmreg_access_ccntr },
8521466b
AF		 2209 { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
2210 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
6ecd0b6b 2211 .access = PL0_RW, .accessfn = pmreg_access_ccntr,
8521466b 2212 .type = ARM_CP_IO,
980ebe87
AL		 2213 .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt),
2214 .readfn = pmccntr_read, .writefn = pmccntr_write,
2215 .raw_readfn = raw_read, .raw_writefn = raw_write, },
4b8afa1f
AL		 2216 { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7,
2217 .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32,
2218 .access = PL0_RW, .accessfn = pmreg_access,
2219 .type = ARM_CP_ALIAS | ARM_CP_IO,
2220 .resetvalue = 0, },
8521466b
AF		 2221 { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
2222 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
980ebe87 2223 .writefn = pmccfiltr_write, .raw_writefn = raw_write,
8521466b
AF		 2224 .access = PL0_RW, .accessfn = pmreg_access,
2225 .type = ARM_CP_IO,
2226 .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
2227 .resetvalue = 0, },
200ac0ef 2228 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
5ecdd3e4
AL		 2229 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2230 .accessfn = pmreg_access,
fdb86656
WH		 2231 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
2232 { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
2233 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1,
5ecdd3e4
AL		 2234 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2235 .accessfn = pmreg_access,
fdb86656 2236 .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
200ac0ef 2237 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
5ecdd3e4
AL		 2238 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2239 .accessfn = pmreg_access_xevcntr,
2240 .writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
2241 { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64,
2242 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2,
2243 .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
2244 .accessfn = pmreg_access_xevcntr,
2245 .writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
200ac0ef 2246 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
1fce1ba9 2247 .access = PL0_R | PL1_RW, .accessfn = access_tpm,
e4e91a21 2248 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr),
200ac0ef 2249 .resetvalue = 0,
d4e6df63 2250 .writefn = pmuserenr_write, .raw_writefn = raw_write },
8a83ffc2
AF		 2251 { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
2252 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0,
1fce1ba9 2253 .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
8a83ffc2
AF		 2254 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
2255 .resetvalue = 0,
2256 .writefn = pmuserenr_write, .raw_writefn = raw_write },
200ac0ef 2257 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
1fce1ba9 2258 .access = PL1_RW, .accessfn = access_tpm,
b7d793ad 2259 .type = ARM_CP_ALIAS | ARM_CP_IO,
e6ec5457 2260 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten),
200ac0ef 2261 .resetvalue = 0,
d4e6df63 2262 .writefn = pmintenset_write, .raw_writefn = raw_write },
e6ec5457
WH		 2263 { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64,
2264 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1,
2265 .access = PL1_RW, .accessfn = access_tpm,
2266 .type = ARM_CP_IO,
2267 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
2268 .writefn = pmintenset_write, .raw_writefn = raw_write,
2269 .resetvalue = 0x0 },
200ac0ef 2270 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
fc5f6856 2271 .access = PL1_RW, .accessfn = access_tpm,
887c0f15 2272 .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
200ac0ef 2273 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
b061a82b 2274 .writefn = pmintenclr_write, },
978364f1
AF		 2275 { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
2276 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
fc5f6856 2277 .access = PL1_RW, .accessfn = access_tpm,
887c0f15 2278 .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
978364f1
AF		 2279 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
2280 .writefn = pmintenclr_write },
7da845b0
PM		 2281 { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
2282 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
630fcd4d
MZ		 2283 .access = PL1_R,
2284 .accessfn = access_aa64_tid2,
2285 .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
7da845b0
PM		 2286 { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
2287 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
630fcd4d
MZ		 2288 .access = PL1_RW,
2289 .accessfn = access_aa64_tid2,
2290 .writefn = csselr_write, .resetvalue = 0,
b85a1fd6
FA		 2291 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
2292 offsetof(CPUARMState, cp15.csselr_ns) } },
776d4e5c
PM		 2293 /* Auxiliary ID register: this actually has an IMPDEF value but for now
2294 * just RAZ for all cores:
2295 */
0ff644a7
PM		 2296 { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
2297 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
93fbc983
MZ		 2298 .access = PL1_R, .type = ARM_CP_CONST,
2299 .accessfn = access_aa64_tid1,
2300 .resetvalue = 0 },
f32cdad5
PM		 2301 /* Auxiliary fault status registers: these also are IMPDEF, and we
2302 * choose to RAZ/WI for all cores.
2303 */
2304 { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
2305 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
84929218
RH		 2306 .access = PL1_RW, .accessfn = access_tvm_trvm,
2307 .type = ARM_CP_CONST, .resetvalue = 0 },
f32cdad5
PM		 2308 { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
2309 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
84929218
RH		 2310 .access = PL1_RW, .accessfn = access_tvm_trvm,
2311 .type = ARM_CP_CONST, .resetvalue = 0 },
b0fe2427
PM		 2312 /* MAIR can just read-as-written because we don't implement caches
2313 * and so don't need to care about memory attributes.
2314 */
2315 { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
2316 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
84929218
RH		 2317 .access = PL1_RW, .accessfn = access_tvm_trvm,
2318 .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
b0fe2427 2319 .resetvalue = 0 },
4cfb8ad8
PM		 2320 { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
2321 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
2322 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
2323 .resetvalue = 0 },
b0fe2427
PM		 2324 /* For non-long-descriptor page tables these are PRRR and NMRR;
2325 * regardless they still act as reads-as-written for QEMU.
b0fe2427 2326 */
1281f8e3 2327 /* MAIR0/1 are defined separately from their 64-bit counterpart which
be693c87
GB		 2328 * allows them to assign the correct fieldoffset based on the endianness
2329 * handled in the field definitions.
2330 */
a903c449 2331 { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
84929218
RH		 2332 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
2333 .access = PL1_RW, .accessfn = access_tvm_trvm,
be693c87
GB		 2334 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
2335 offsetof(CPUARMState, cp15.mair0_ns) },
b0fe2427 2336 .resetfn = arm_cp_reset_ignore },
a903c449 2337 { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
84929218
RH		 2338 .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1,
2339 .access = PL1_RW, .accessfn = access_tvm_trvm,
be693c87
GB		 2340 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
2341 offsetof(CPUARMState, cp15.mair1_ns) },
b0fe2427 2342 .resetfn = arm_cp_reset_ignore },
1090b9c6
PM		 2343 { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
2344 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
7a0e58fa 2345 .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
995939a6
PM		 2346 /* 32 bit ITLB invalidates */
2347 { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
30881b73
RH		 2348 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2349 .writefn = tlbiall_write },
995939a6 2350 { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
30881b73
RH		 2351 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2352 .writefn = tlbimva_write },
995939a6 2353 { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
30881b73
RH		 2354 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2355 .writefn = tlbiasid_write },
995939a6
PM		 2356 /* 32 bit DTLB invalidates */
2357 { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
30881b73
RH		 2358 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2359 .writefn = tlbiall_write },
995939a6 2360 { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
30881b73
RH		 2361 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2362 .writefn = tlbimva_write },
995939a6 2363 { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
30881b73
RH		 2364 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2365 .writefn = tlbiasid_write },
995939a6
PM		 2366 /* 32 bit TLB invalidates */
2367 { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
30881b73
RH		 2368 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2369 .writefn = tlbiall_write },
995939a6 2370 { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
30881b73
RH		 2371 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2372 .writefn = tlbimva_write },
995939a6 2373 { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
30881b73
RH		 2374 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2375 .writefn = tlbiasid_write },
995939a6 2376 { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
30881b73
RH		 2377 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2378 .writefn = tlbimvaa_write },
995939a6
PM		 2379 REGINFO_SENTINEL
2380};
2381
2382static const ARMCPRegInfo v7mp_cp_reginfo[] = {
2383 /* 32 bit TLB invalidates, Inner Shareable */
2384 { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
30881b73
RH		 2385 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2386 .writefn = tlbiall_is_write },
995939a6 2387 { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
30881b73
RH		 2388 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
2389 .writefn = tlbimva_is_write },
995939a6 2390 { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
30881b73 2391 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
fa439fc5 2392 .writefn = tlbiasid_is_write },
995939a6 2393 { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
30881b73 2394 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
fa439fc5 2395 .writefn = tlbimvaa_is_write },
e9aa6c21
PM		 2396 REGINFO_SENTINEL
2397};
2398
327dd510
AL		 2399static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
2400 /* PMOVSSET is not implemented in v7 before v7ve */
2401 { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3,
2402 .access = PL0_RW, .accessfn = pmreg_access,
f4efb4b2 2403 .type = ARM_CP_ALIAS | ARM_CP_IO,
327dd510
AL		 2404 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
2405 .writefn = pmovsset_write,
2406 .raw_writefn = raw_write },
2407 { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64,
2408 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3,
2409 .access = PL0_RW, .accessfn = pmreg_access,
f4efb4b2 2410 .type = ARM_CP_ALIAS | ARM_CP_IO,
327dd510
AL		 2411 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
2412 .writefn = pmovsset_write,
2413 .raw_writefn = raw_write },
2414 REGINFO_SENTINEL
2415};
2416
c4241c7d
PM		 2417static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2418 uint64_t value)
c326b979
PM		 2419{
2420 value &= 1;
2421 env->teecr = value;
c326b979
PM		 2422}
2423
3f208fd7
PM		 2424static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri,
2425 bool isread)
c326b979 2426{
dcbff19b 2427 if (arm_current_el(env) == 0 && (env->teecr & 1)) {
92611c00 2428 return CP_ACCESS_TRAP;
c326b979 2429 }
92611c00 2430 return CP_ACCESS_OK;
c326b979
PM		 2431}
2432
2433static const ARMCPRegInfo t2ee_cp_reginfo[] = {
2434 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
2435 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
2436 .resetvalue = 0,
2437 .writefn = teecr_write },
2438 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
2439 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
92611c00 2440 .accessfn = teehbr_access, .resetvalue = 0 },
c326b979
PM		 2441 REGINFO_SENTINEL
2442};
2443
4d31c596 2444static const ARMCPRegInfo v6k_cp_reginfo[] = {
e4fe830b
PM		 2445 { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
2446 .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
2447 .access = PL0_RW,
54bf36ed 2448 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
4d31c596
PM		 2449 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
2450 .access = PL0_RW,
54bf36ed
FA		 2451 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
2452 offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
e4fe830b
PM		 2453 .resetfn = arm_cp_reset_ignore },
2454 { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
2455 .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
2456 .access = PL0_R|PL1_W,
54bf36ed
FA		 2457 .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
2458 .resetvalue = 0},
4d31c596
PM		 2459 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
2460 .access = PL0_R|PL1_W,
54bf36ed
FA		 2461 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
2462 offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
e4fe830b 2463 .resetfn = arm_cp_reset_ignore },
54bf36ed 2464 { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
e4fe830b 2465 .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
4d31c596 2466 .access = PL1_RW,
54bf36ed
FA		 2467 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
2468 { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
2469 .access = PL1_RW,
2470 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
2471 offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
2472 .resetvalue = 0 },
4d31c596
PM		 2473 REGINFO_SENTINEL
2474};
2475
55d284af
PM		 2476#ifndef CONFIG_USER_ONLY
2477
3f208fd7
PM		 2478static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
2479 bool isread)
00108f2d 2480{
75502672
PM		 2481 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2482 * Writable only at the highest implemented exception level.
2483 */
2484 int el = arm_current_el(env);
5bc84371
RH		 2485 uint64_t hcr;
2486 uint32_t cntkctl;
75502672
PM		 2487
2488 switch (el) {
2489 case 0:
5bc84371
RH		 2490 hcr = arm_hcr_el2_eff(env);
2491 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
2492 cntkctl = env->cp15.cnthctl_el2;
2493 } else {
2494 cntkctl = env->cp15.c14_cntkctl;
2495 }
2496 if (!extract32(cntkctl, 0, 2)) {
75502672
PM		 2497 return CP_ACCESS_TRAP;
2498 }
2499 break;
2500 case 1:
2501 if (!isread && ri->state == ARM_CP_STATE_AA32 &&
2502 arm_is_secure_below_el3(env)) {
2503 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2504 return CP_ACCESS_TRAP_UNCATEGORIZED;
2505 }
2506 break;
2507 case 2:
2508 case 3:
2509 break;
00108f2d 2510 }
75502672
PM		 2511
2512 if (!isread && el < arm_highest_el(env)) {
2513 return CP_ACCESS_TRAP_UNCATEGORIZED;
2514 }
2515
00108f2d
PM		 2516 return CP_ACCESS_OK;
2517}
2518
3f208fd7
PM		 2519static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
2520 bool isread)
00108f2d 2521{
0b6440af
EI		 2522 unsigned int cur_el = arm_current_el(env);
2523 bool secure = arm_is_secure(env);
5bc84371 2524 uint64_t hcr = arm_hcr_el2_eff(env);
0b6440af 2525
5bc84371
RH		 2526 switch (cur_el) {
2527 case 0:
2528 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2529 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
2530 return (extract32(env->cp15.cnthctl_el2, timeridx, 1)
2531 ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2);
2532 }
0b6440af 2533
5bc84371
RH		 2534 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2535 if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
2536 return CP_ACCESS_TRAP;
2537 }
2538
2539 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PCTEN. */
2540 if (hcr & HCR_E2H) {
2541 if (timeridx == GTIMER_PHYS &&
2542 !extract32(env->cp15.cnthctl_el2, 10, 1)) {
2543 return CP_ACCESS_TRAP_EL2;
2544 }
2545 } else {
2546 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2547 if (arm_feature(env, ARM_FEATURE_EL2) &&
2548 timeridx == GTIMER_PHYS && !secure &&
2549 !extract32(env->cp15.cnthctl_el2, 1, 1)) {
2550 return CP_ACCESS_TRAP_EL2;
2551 }
2552 }
2553 break;
2554
2555 case 1:
2556 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2557 if (arm_feature(env, ARM_FEATURE_EL2) &&
2558 timeridx == GTIMER_PHYS && !secure &&
2559 (hcr & HCR_E2H
2560 ? !extract32(env->cp15.cnthctl_el2, 10, 1)
2561 : !extract32(env->cp15.cnthctl_el2, 0, 1))) {
2562 return CP_ACCESS_TRAP_EL2;
2563 }
2564 break;
0b6440af 2565 }
00108f2d
PM		 2566 return CP_ACCESS_OK;
2567}
2568
3f208fd7
PM		 2569static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
2570 bool isread)
00108f2d 2571{
0b6440af
EI		 2572 unsigned int cur_el = arm_current_el(env);
2573 bool secure = arm_is_secure(env);
5bc84371 2574 uint64_t hcr = arm_hcr_el2_eff(env);
0b6440af 2575
5bc84371
RH		 2576 switch (cur_el) {
2577 case 0:
2578 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
2579 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2580 return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1)
2581 ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2);
2582 }
0b6440af 2583
5bc84371
RH		 2584 /*
2585 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2586 * EL0 if EL0[PV]TEN is zero.
2587 */
2588 if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
2589 return CP_ACCESS_TRAP;
2590 }
2591 /* fall through */
2592
2593 case 1:
2594 if (arm_feature(env, ARM_FEATURE_EL2) &&
2595 timeridx == GTIMER_PHYS && !secure) {
2596 if (hcr & HCR_E2H) {
2597 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2598 if (!extract32(env->cp15.cnthctl_el2, 11, 1)) {
2599 return CP_ACCESS_TRAP_EL2;
2600 }
2601 } else {
2602 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2603 if (!extract32(env->cp15.cnthctl_el2, 1, 1)) {
2604 return CP_ACCESS_TRAP_EL2;
2605 }
2606 }
2607 }
2608 break;
0b6440af 2609 }
00108f2d
PM		 2610 return CP_ACCESS_OK;
2611}
2612
2613static CPAccessResult gt_pct_access(CPUARMState *env,
3f208fd7
PM		 2614 const ARMCPRegInfo *ri,
2615 bool isread)
00108f2d 2616{
3f208fd7 2617 return gt_counter_access(env, GTIMER_PHYS, isread);
00108f2d
PM		 2618}
2619
2620static CPAccessResult gt_vct_access(CPUARMState *env,
3f208fd7
PM		 2621 const ARMCPRegInfo *ri,
2622 bool isread)
00108f2d 2623{
3f208fd7 2624 return gt_counter_access(env, GTIMER_VIRT, isread);
00108f2d
PM		 2625}
2626
3f208fd7
PM		 2627static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
2628 bool isread)
00108f2d 2629{
3f208fd7 2630 return gt_timer_access(env, GTIMER_PHYS, isread);
00108f2d
PM		 2631}
2632
3f208fd7
PM		 2633static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
2634 bool isread)
00108f2d 2635{
3f208fd7 2636 return gt_timer_access(env, GTIMER_VIRT, isread);
00108f2d
PM		 2637}
2638
b4d3978c 2639static CPAccessResult gt_stimer_access(CPUARMState *env,
3f208fd7
PM		 2640 const ARMCPRegInfo *ri,
2641 bool isread)
b4d3978c
PM		 2642{
2643 /* The AArch64 register view of the secure physical timer is
2644 * always accessible from EL3, and configurably accessible from
2645 * Secure EL1.
2646 */
2647 switch (arm_current_el(env)) {
2648 case 1:
2649 if (!arm_is_secure(env)) {
2650 return CP_ACCESS_TRAP;
2651 }
2652 if (!(env->cp15.scr_el3 & SCR_ST)) {
2653 return CP_ACCESS_TRAP_EL3;
2654 }
2655 return CP_ACCESS_OK;
2656 case 0:
2657 case 2:
2658 return CP_ACCESS_TRAP;
2659 case 3:
2660 return CP_ACCESS_OK;
2661 default:
2662 g_assert_not_reached();
2663 }
2664}
2665
55d284af
PM		 2666static uint64_t gt_get_countervalue(CPUARMState *env)
2667{
7def8754
AJ		 2668 ARMCPU *cpu = env_archcpu(env);
2669
2670 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu);
55d284af
PM		 2671}
2672
2673static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
2674{
2675 ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
2676
2677 if (gt->ctl & 1) {
2678 /* Timer enabled: calculate and set current ISTATUS, irq, and
2679 * reset timer to when ISTATUS next has to change
2680 */
edac4d8a
EI		 2681 uint64_t offset = timeridx == GTIMER_VIRT ?
2682 cpu->env.cp15.cntvoff_el2 : 0;
55d284af
PM		 2683 uint64_t count = gt_get_countervalue(&cpu->env);
2684 /* Note that this must be unsigned 64 bit arithmetic: */
edac4d8a 2685 int istatus = count - offset >= gt->cval;
55d284af 2686 uint64_t nexttick;
194cbc49 2687 int irqstate;
55d284af
PM		 2688
2689 gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
194cbc49
PM		 2690
2691 irqstate = (istatus && !(gt->ctl & 2));
2692 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);
2693
55d284af
PM		 2694 if (istatus) {
2695 /* Next transition is when count rolls back over to zero */
2696 nexttick = UINT64_MAX;
2697 } else {
2698 /* Next transition is when we hit cval */
edac4d8a 2699 nexttick = gt->cval + offset;
55d284af
PM		 2700 }
2701 /* Note that the desired next expiry time might be beyond the
2702 * signed-64-bit range of a QEMUTimer -- in this case we just
2703 * set the timer for as far in the future as possible. When the
2704 * timer expires we will reset the timer for any remaining period.
2705 */
7def8754 2706 if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) {
4a0245b6
AJ		 2707 timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX);
2708 } else {
2709 timer_mod(cpu->gt_timer[timeridx], nexttick);
55d284af 2710 }
194cbc49 2711 trace_arm_gt_recalc(timeridx, irqstate, nexttick);
55d284af
PM		 2712 } else {
2713 /* Timer disabled: ISTATUS and timer output always clear */
2714 gt->ctl &= ~4;
2715 qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
bc72ad67 2716 timer_del(cpu->gt_timer[timeridx]);
194cbc49 2717 trace_arm_gt_recalc_disabled(timeridx);
55d284af
PM		 2718 }
2719}
2720
0e3eca4c
EI		 2721static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
2722 int timeridx)
55d284af 2723{
2fc0cc0e 2724 ARMCPU *cpu = env_archcpu(env);
55d284af 2725
bc72ad67 2726 timer_del(cpu->gt_timer[timeridx]);
55d284af
PM		 2727}
2728
c4241c7d 2729static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
55d284af 2730{
c4241c7d 2731 return gt_get_countervalue(env);
55d284af
PM		 2732}
2733
53d1f856
RH		 2734static uint64_t gt_virt_cnt_offset(CPUARMState *env)
2735{
2736 uint64_t hcr;
2737
2738 switch (arm_current_el(env)) {
2739 case 2:
2740 hcr = arm_hcr_el2_eff(env);
2741 if (hcr & HCR_E2H) {
2742 return 0;
2743 }
2744 break;
2745 case 0:
2746 hcr = arm_hcr_el2_eff(env);
2747 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
2748 return 0;
2749 }
2750 break;
2751 }
2752
2753 return env->cp15.cntvoff_el2;
2754}
2755
edac4d8a
EI		 2756static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
2757{
53d1f856 2758 return gt_get_countervalue(env) - gt_virt_cnt_offset(env);
edac4d8a
EI		 2759}
2760
c4241c7d 2761static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
0e3eca4c 2762 int timeridx,
c4241c7d 2763 uint64_t value)
55d284af 2764{
194cbc49 2765 trace_arm_gt_cval_write(timeridx, value);
55d284af 2766 env->cp15.c14_timer[timeridx].cval = value;
2fc0cc0e 2767 gt_recalc_timer(env_archcpu(env), timeridx);
55d284af 2768}
c4241c7d 2769
0e3eca4c
EI		 2770static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
2771 int timeridx)
55d284af 2772{
53d1f856
RH		 2773 uint64_t offset = 0;
2774
2775 switch (timeridx) {
2776 case GTIMER_VIRT:
8c94b071 2777 case GTIMER_HYPVIRT:
53d1f856
RH		 2778 offset = gt_virt_cnt_offset(env);
2779 break;
2780 }
55d284af 2781
c4241c7d 2782 return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
edac4d8a 2783 (gt_get_countervalue(env) - offset));
55d284af
PM		 2784}
2785
c4241c7d 2786static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
0e3eca4c 2787 int timeridx,
c4241c7d 2788 uint64_t value)
55d284af 2789{
53d1f856
RH		 2790 uint64_t offset = 0;
2791
2792 switch (timeridx) {
2793 case GTIMER_VIRT:
8c94b071 2794 case GTIMER_HYPVIRT:
53d1f856
RH		 2795 offset = gt_virt_cnt_offset(env);
2796 break;
2797 }
55d284af 2798
194cbc49 2799 trace_arm_gt_tval_write(timeridx, value);
edac4d8a 2800 env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
18084b2f 2801 sextract64(value, 0, 32);
2fc0cc0e 2802 gt_recalc_timer(env_archcpu(env), timeridx);
55d284af
PM		 2803}
2804
c4241c7d 2805static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
0e3eca4c 2806 int timeridx,
c4241c7d 2807 uint64_t value)
55d284af 2808{
2fc0cc0e 2809 ARMCPU *cpu = env_archcpu(env);
55d284af
PM		 2810 uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
2811
194cbc49 2812 trace_arm_gt_ctl_write(timeridx, value);
d3afacc7 2813 env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
55d284af
PM		 2814 if ((oldval ^ value) & 1) {
2815 /* Enable toggled */
2816 gt_recalc_timer(cpu, timeridx);
d3afacc7 2817 } else if ((oldval ^ value) & 2) {
55d284af
PM		 2818 /* IMASK toggled: don't need to recalculate,
2819 * just set the interrupt line based on ISTATUS
2820 */
194cbc49
PM		 2821 int irqstate = (oldval & 4) && !(value & 2);
2822
2823 trace_arm_gt_imask_toggle(timeridx, irqstate);
2824 qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);
55d284af 2825 }
55d284af
PM		 2826}
2827
0e3eca4c
EI		 2828static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2829{
2830 gt_timer_reset(env, ri, GTIMER_PHYS);
2831}
2832
2833static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2834 uint64_t value)
2835{
2836 gt_cval_write(env, ri, GTIMER_PHYS, value);
2837}
2838
2839static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
2840{
2841 return gt_tval_read(env, ri, GTIMER_PHYS);
2842}
2843
2844static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2845 uint64_t value)
2846{
2847 gt_tval_write(env, ri, GTIMER_PHYS, value);
2848}
2849
2850static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2851 uint64_t value)
2852{
2853 gt_ctl_write(env, ri, GTIMER_PHYS, value);
2854}
2855
bb5972e4
RH		 2856static int gt_phys_redir_timeridx(CPUARMState *env)
2857{
2858 switch (arm_mmu_idx(env)) {
2859 case ARMMMUIdx_E20_0:
2860 case ARMMMUIdx_E20_2:
452ef8cb 2861 case ARMMMUIdx_E20_2_PAN:
bb5972e4
RH		 2862 return GTIMER_HYP;
2863 default:
2864 return GTIMER_PHYS;
2865 }
2866}
2867
2868static int gt_virt_redir_timeridx(CPUARMState *env)
2869{
2870 switch (arm_mmu_idx(env)) {
2871 case ARMMMUIdx_E20_0:
2872 case ARMMMUIdx_E20_2:
452ef8cb 2873 case ARMMMUIdx_E20_2_PAN:
bb5972e4
RH		 2874 return GTIMER_HYPVIRT;
2875 default:
2876 return GTIMER_VIRT;
2877 }
2878}
2879
2880static uint64_t gt_phys_redir_cval_read(CPUARMState *env,
2881 const ARMCPRegInfo *ri)
2882{
2883 int timeridx = gt_phys_redir_timeridx(env);
2884 return env->cp15.c14_timer[timeridx].cval;
2885}
2886
2887static void gt_phys_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2888 uint64_t value)
2889{
2890 int timeridx = gt_phys_redir_timeridx(env);
2891 gt_cval_write(env, ri, timeridx, value);
2892}
2893
2894static uint64_t gt_phys_redir_tval_read(CPUARMState *env,
2895 const ARMCPRegInfo *ri)
2896{
2897 int timeridx = gt_phys_redir_timeridx(env);
2898 return gt_tval_read(env, ri, timeridx);
2899}
2900
2901static void gt_phys_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2902 uint64_t value)
2903{
2904 int timeridx = gt_phys_redir_timeridx(env);
2905 gt_tval_write(env, ri, timeridx, value);
2906}
2907
2908static uint64_t gt_phys_redir_ctl_read(CPUARMState *env,
2909 const ARMCPRegInfo *ri)
2910{
2911 int timeridx = gt_phys_redir_timeridx(env);
2912 return env->cp15.c14_timer[timeridx].ctl;
2913}
2914
2915static void gt_phys_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2916 uint64_t value)
2917{
2918 int timeridx = gt_phys_redir_timeridx(env);
2919 gt_ctl_write(env, ri, timeridx, value);
2920}
2921
0e3eca4c
EI		 2922static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2923{
2924 gt_timer_reset(env, ri, GTIMER_VIRT);
2925}
2926
2927static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2928 uint64_t value)
2929{
2930 gt_cval_write(env, ri, GTIMER_VIRT, value);
2931}
2932
2933static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
2934{
2935 return gt_tval_read(env, ri, GTIMER_VIRT);
2936}
2937
2938static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2939 uint64_t value)
2940{
2941 gt_tval_write(env, ri, GTIMER_VIRT, value);
2942}
2943
2944static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2945 uint64_t value)
2946{
2947 gt_ctl_write(env, ri, GTIMER_VIRT, value);
2948}
2949
edac4d8a
EI		 2950static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
2951 uint64_t value)
2952{
2fc0cc0e 2953 ARMCPU *cpu = env_archcpu(env);
edac4d8a 2954
194cbc49 2955 trace_arm_gt_cntvoff_write(value);
edac4d8a
EI		 2956 raw_write(env, ri, value);
2957 gt_recalc_timer(cpu, GTIMER_VIRT);
2958}
2959
bb5972e4
RH		 2960static uint64_t gt_virt_redir_cval_read(CPUARMState *env,
2961 const ARMCPRegInfo *ri)
2962{
2963 int timeridx = gt_virt_redir_timeridx(env);
2964 return env->cp15.c14_timer[timeridx].cval;
2965}
2966
2967static void gt_virt_redir_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2968 uint64_t value)
2969{
2970 int timeridx = gt_virt_redir_timeridx(env);
2971 gt_cval_write(env, ri, timeridx, value);
2972}
2973
2974static uint64_t gt_virt_redir_tval_read(CPUARMState *env,
2975 const ARMCPRegInfo *ri)
2976{
2977 int timeridx = gt_virt_redir_timeridx(env);
2978 return gt_tval_read(env, ri, timeridx);
2979}
2980
2981static void gt_virt_redir_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
2982 uint64_t value)
2983{
2984 int timeridx = gt_virt_redir_timeridx(env);
2985 gt_tval_write(env, ri, timeridx, value);
2986}
2987
2988static uint64_t gt_virt_redir_ctl_read(CPUARMState *env,
2989 const ARMCPRegInfo *ri)
2990{
2991 int timeridx = gt_virt_redir_timeridx(env);
2992 return env->cp15.c14_timer[timeridx].ctl;
2993}
2994
2995static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
2996 uint64_t value)
2997{
2998 int timeridx = gt_virt_redir_timeridx(env);
2999 gt_ctl_write(env, ri, timeridx, value);
3000}
3001
b0e66d95
EI		 3002static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
3003{
3004 gt_timer_reset(env, ri, GTIMER_HYP);
3005}
3006
3007static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
3008 uint64_t value)
3009{
3010 gt_cval_write(env, ri, GTIMER_HYP, value);
3011}
3012
3013static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
3014{
3015 return gt_tval_read(env, ri, GTIMER_HYP);
3016}
3017
3018static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
3019 uint64_t value)
3020{
3021 gt_tval_write(env, ri, GTIMER_HYP, value);
3022}
3023
3024static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
3025 uint64_t value)
3026{
3027 gt_ctl_write(env, ri, GTIMER_HYP, value);
3028}
3029
b4d3978c
PM		 3030static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
3031{
3032 gt_timer_reset(env, ri, GTIMER_SEC);
3033}
3034
3035static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
3036 uint64_t value)
3037{
3038 gt_cval_write(env, ri, GTIMER_SEC, value);
3039}
3040
3041static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
3042{
3043 return gt_tval_read(env, ri, GTIMER_SEC);
3044}
3045
3046static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
3047 uint64_t value)
3048{
3049 gt_tval_write(env, ri, GTIMER_SEC, value);
3050}
3051
3052static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
3053 uint64_t value)
3054{
3055 gt_ctl_write(env, ri, GTIMER_SEC, value);
3056}
3057
8c94b071
RH		 3058static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
3059{
3060 gt_timer_reset(env, ri, GTIMER_HYPVIRT);
3061}
3062
3063static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
3064 uint64_t value)
3065{
3066 gt_cval_write(env, ri, GTIMER_HYPVIRT, value);
3067}
3068
3069static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
3070{
3071 return gt_tval_read(env, ri, GTIMER_HYPVIRT);
3072}
3073
3074static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
3075 uint64_t value)
3076{
3077 gt_tval_write(env, ri, GTIMER_HYPVIRT, value);
3078}
3079
3080static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
3081 uint64_t value)
3082{
3083 gt_ctl_write(env, ri, GTIMER_HYPVIRT, value);
3084}
3085
55d284af
PM		 3086void arm_gt_ptimer_cb(void *opaque)
3087{
3088 ARMCPU *cpu = opaque;
3089
3090 gt_recalc_timer(cpu, GTIMER_PHYS);
3091}
3092
3093void arm_gt_vtimer_cb(void *opaque)
3094{
3095 ARMCPU *cpu = opaque;
3096
3097 gt_recalc_timer(cpu, GTIMER_VIRT);
3098}
3099
b0e66d95
EI		 3100void arm_gt_htimer_cb(void *opaque)
3101{
3102 ARMCPU *cpu = opaque;
3103
3104 gt_recalc_timer(cpu, GTIMER_HYP);
3105}
3106
b4d3978c
PM		 3107void arm_gt_stimer_cb(void *opaque)
3108{
3109 ARMCPU *cpu = opaque;
3110
3111 gt_recalc_timer(cpu, GTIMER_SEC);
3112}
3113
8c94b071
RH		 3114void arm_gt_hvtimer_cb(void *opaque)
3115{
3116 ARMCPU *cpu = opaque;
3117
3118 gt_recalc_timer(cpu, GTIMER_HYPVIRT);
3119}
3120
96eec6b2
AJ		 3121static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
3122{
3123 ARMCPU *cpu = env_archcpu(env);
3124
3125 cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz;
3126}
3127
55d284af
PM		 3128static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
3129 /* Note that CNTFRQ is purely reads-as-written for the benefit
3130 * of software; writing it doesn't actually change the timer frequency.
3131 * Our reset value matches the fixed frequency we implement the timer at.
3132 */
3133 { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
7a0e58fa 3134 .type = ARM_CP_ALIAS,
a7adc4b7
PM		 3135 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
3136 .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
a7adc4b7
PM		 3137 },
3138 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
3139 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
3140 .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
55d284af 3141 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
96eec6b2 3142 .resetfn = arm_gt_cntfrq_reset,
55d284af
PM		 3143 },
3144 /* overall control: mostly access permissions */
a7adc4b7
PM		 3145 { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
3146 .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
55d284af
PM		 3147 .access = PL1_RW,
3148 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
3149 .resetvalue = 0,
3150 },
3151 /* per-timer control */
3152 { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
9ff9dd3c 3153 .secure = ARM_CP_SECSTATE_NS,
daf1dc5f 3154 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW,
a7adc4b7
PM		 3155 .accessfn = gt_ptimer_access,
3156 .fieldoffset = offsetoflow32(CPUARMState,
3157 cp15.c14_timer[GTIMER_PHYS].ctl),
bb5972e4
RH		 3158 .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read,
3159 .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write,
a7adc4b7 3160 },
9c513e78 3161 { .name = "CNTP_CTL_S",
9ff9dd3c
PM		 3162 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
3163 .secure = ARM_CP_SECSTATE_S,
daf1dc5f 3164 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW,
9ff9dd3c
PM		 3165 .accessfn = gt_ptimer_access,
3166 .fieldoffset = offsetoflow32(CPUARMState,
3167 cp15.c14_timer[GTIMER_SEC].ctl),
3168 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
3169 },
a7adc4b7
PM		 3170 { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
3171 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
daf1dc5f 3172 .type = ARM_CP_IO, .access = PL0_RW,
a7adc4b7 3173 .accessfn = gt_ptimer_access,
55d284af
PM		 3174 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
3175 .resetvalue = 0,
bb5972e4
RH		 3176 .readfn = gt_phys_redir_ctl_read, .raw_readfn = raw_read,
3177 .writefn = gt_phys_redir_ctl_write, .raw_writefn = raw_write,
55d284af
PM		 3178 },
3179 { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
daf1dc5f 3180 .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW,
a7adc4b7
PM		 3181 .accessfn = gt_vtimer_access,
3182 .fieldoffset = offsetoflow32(CPUARMState,
3183 cp15.c14_timer[GTIMER_VIRT].ctl),
bb5972e4
RH		 3184 .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read,
3185 .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write,
a7adc4b7
PM		 3186 },
3187 { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
3188 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
daf1dc5f 3189 .type = ARM_CP_IO, .access = PL0_RW,
a7adc4b7 3190 .accessfn = gt_vtimer_access,
55d284af
PM		 3191 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
3192 .resetvalue = 0,
bb5972e4
RH		 3193 .readfn = gt_virt_redir_ctl_read, .raw_readfn = raw_read,
3194 .writefn = gt_virt_redir_ctl_write, .raw_writefn = raw_write,
55d284af
PM		 3195 },
3196 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3197 { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
9ff9dd3c 3198 .secure = ARM_CP_SECSTATE_NS,
daf1dc5f 3199 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
00108f2d 3200 .accessfn = gt_ptimer_access,
bb5972e4 3201 .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write,
55d284af 3202 },
9c513e78 3203 { .name = "CNTP_TVAL_S",
9ff9dd3c
PM		 3204 .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
3205 .secure = ARM_CP_SECSTATE_S,
daf1dc5f 3206 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
9ff9dd3c
PM		 3207 .accessfn = gt_ptimer_access,
3208 .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
3209 },
a7adc4b7
PM		 3210 { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
3211 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
daf1dc5f 3212 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
0e3eca4c 3213 .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
bb5972e4 3214 .readfn = gt_phys_redir_tval_read, .writefn = gt_phys_redir_tval_write,
a7adc4b7 3215 },
55d284af 3216 { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
daf1dc5f 3217 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
00108f2d 3218 .accessfn = gt_vtimer_access,
bb5972e4 3219 .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write,
55d284af 3220 },
a7adc4b7
PM		 3221 { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
3222 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
daf1dc5f 3223 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
0e3eca4c 3224 .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
bb5972e4 3225 .readfn = gt_virt_redir_tval_read, .writefn = gt_virt_redir_tval_write,
a7adc4b7 3226 },
55d284af
PM		 3227 /* The counter itself */
3228 { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
7a0e58fa 3229 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
00108f2d 3230 .accessfn = gt_pct_access,
a7adc4b7
PM		 3231 .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
3232 },
3233 { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
3234 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
7a0e58fa 3235 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
d57b9ee8 3236 .accessfn = gt_pct_access, .readfn = gt_cnt_read,
55d284af
PM		 3237 },
3238 { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
7a0e58fa 3239 .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
00108f2d 3240 .accessfn = gt_vct_access,
edac4d8a 3241 .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
a7adc4b7
PM		 3242 },
3243 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
3244 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
7a0e58fa 3245 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
d57b9ee8 3246 .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
55d284af
PM		 3247 },
3248 /* Comparison value, indicating when the timer goes off */
3249 { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
9ff9dd3c 3250 .secure = ARM_CP_SECSTATE_NS,
daf1dc5f 3251 .access = PL0_RW,
7a0e58fa 3252 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
55d284af 3253 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
b061a82b 3254 .accessfn = gt_ptimer_access,
bb5972e4
RH		 3255 .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read,
3256 .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write,
a7adc4b7 3257 },
9c513e78 3258 { .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2,
9ff9dd3c 3259 .secure = ARM_CP_SECSTATE_S,
daf1dc5f 3260 .access = PL0_RW,
9ff9dd3c
PM		 3261 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
3262 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
3263 .accessfn = gt_ptimer_access,
3264 .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
3265 },
a7adc4b7
PM		 3266 { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
3267 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
daf1dc5f 3268 .access = PL0_RW,
a7adc4b7
PM		 3269 .type = ARM_CP_IO,
3270 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
12cde08a 3271 .resetvalue = 0, .accessfn = gt_ptimer_access,
bb5972e4
RH		 3272 .readfn = gt_phys_redir_cval_read, .raw_readfn = raw_read,
3273 .writefn = gt_phys_redir_cval_write, .raw_writefn = raw_write,
55d284af
PM		 3274 },
3275 { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
daf1dc5f 3276 .access = PL0_RW,
7a0e58fa 3277 .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
55d284af 3278 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
b061a82b 3279 .accessfn = gt_vtimer_access,
bb5972e4
RH		 3280 .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read,
3281 .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write,
a7adc4b7
PM		 3282 },
3283 { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
3284 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
daf1dc5f 3285 .access = PL0_RW,
a7adc4b7
PM		 3286 .type = ARM_CP_IO,
3287 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
3288 .resetvalue = 0, .accessfn = gt_vtimer_access,
bb5972e4
RH		 3289 .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read,
3290 .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write,
55d284af 3291 },
b4d3978c
PM		 3292 /* Secure timer -- this is actually restricted to only EL3
3293 * and configurably Secure-EL1 via the accessfn.
3294 */
3295 { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
3296 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0,
3297 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW,
3298 .accessfn = gt_stimer_access,
3299 .readfn = gt_sec_tval_read,
3300 .writefn = gt_sec_tval_write,
3301 .resetfn = gt_sec_timer_reset,
3302 },
3303 { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64,
3304 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1,
3305 .type = ARM_CP_IO, .access = PL1_RW,
3306 .accessfn = gt_stimer_access,
3307 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl),
3308 .resetvalue = 0,
3309 .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
3310 },
3311 { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
3312 .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
3313 .type = ARM_CP_IO, .access = PL1_RW,
3314 .accessfn = gt_stimer_access,
3315 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
3316 .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
3317 },
55d284af
PM		 3318 REGINFO_SENTINEL
3319};
3320
bb5972e4
RH		 3321static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
3322 bool isread)
3323{
3324 if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
3325 return CP_ACCESS_TRAP;
3326 }
3327 return CP_ACCESS_OK;
3328}
3329
55d284af 3330#else
26c4a83b
AB		 3331
3332/* In user-mode most of the generic timer registers are inaccessible
3333 * however modern kernels (4.12+) allow access to cntvct_el0
55d284af 3334 */
26c4a83b
AB		 3335
3336static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
3337{
7def8754
AJ		 3338 ARMCPU *cpu = env_archcpu(env);
3339
26c4a83b
AB		 3340 /* Currently we have no support for QEMUTimer in linux-user so we
3341 * can't call gt_get_countervalue(env), instead we directly
3342 * call the lower level functions.
3343 */
7def8754 3344 return cpu_get_clock() / gt_cntfrq_period_ns(cpu);
26c4a83b
AB		 3345}
3346
6cc7a3ae 3347static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
26c4a83b
AB		 3348 { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
3349 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
3350 .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */,
3351 .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
3352 .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE,
3353 },
3354 { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
3355 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
3356 .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
3357 .readfn = gt_virt_cnt_read,
3358 },
6cc7a3ae
PM		 3359 REGINFO_SENTINEL
3360};
3361
55d284af
PM		 3362#endif
3363
c4241c7d 3364static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
4a501606 3365{
891a2fe7 3366 if (arm_feature(env, ARM_FEATURE_LPAE)) {
8d5c773e 3367 raw_write(env, ri, value);
891a2fe7 3368 } else if (arm_feature(env, ARM_FEATURE_V7)) {
8d5c773e 3369 raw_write(env, ri, value & 0xfffff6ff);
4a501606 3370 } else {
8d5c773e 3371 raw_write(env, ri, value & 0xfffff1ff);
4a501606 3372 }
4a501606
PM		 3373}
3374
3375#ifndef CONFIG_USER_ONLY
3376/* get_phys_addr() isn't present for user-mode-only targets */
702a9357 3377
3f208fd7
PM		 3378static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
3379 bool isread)
92611c00
PM		 3380{
3381 if (ri->opc2 & 4) {
87562e4f
PM		 3382 /* The ATS12NSO* operations must trap to EL3 if executed in
3383 * Secure EL1 (which can only happen if EL3 is AArch64).
3384 * They are simply UNDEF if executed from NS EL1.
3385 * They function normally from EL2 or EL3.
92611c00 3386 */
87562e4f
PM		 3387 if (arm_current_el(env) == 1) {
3388 if (arm_is_secure_below_el3(env)) {
3389 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
3390 }
3391 return CP_ACCESS_TRAP_UNCATEGORIZED;
3392 }
92611c00
PM		 3393 }
3394 return CP_ACCESS_OK;
3395}
3396
9fb005b0 3397#ifdef CONFIG_TCG
060e8a48 3398static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
03ae85f8 3399 MMUAccessType access_type, ARMMMUIdx mmu_idx)
4a501606 3400{
a8170e5e 3401 hwaddr phys_addr;
4a501606
PM		 3402 target_ulong page_size;
3403 int prot;
b7cc4e82 3404 bool ret;
01c097f7 3405 uint64_t par64;
1313e2d7 3406 bool format64 = false;
8bf5b6a9 3407 MemTxAttrs attrs = {};
e14b5a23 3408 ARMMMUFaultInfo fi = {};
5b2d261d 3409 ARMCacheAttrs cacheattrs = {};
4a501606 3410
5b2d261d 3411 ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs,
bc52bfeb 3412 &prot, &page_size, &fi, &cacheattrs);
1313e2d7 3413
0710b2fa
PM		 3414 if (ret) {
3415 /*
3416 * Some kinds of translation fault must cause exceptions rather
3417 * than being reported in the PAR.
3418 */
3419 int current_el = arm_current_el(env);
3420 int target_el;
3421 uint32_t syn, fsr, fsc;
3422 bool take_exc = false;
3423
3424 if (fi.s1ptw && current_el == 1 && !arm_is_secure(env)
fee7aa46 3425 && arm_mmu_idx_is_stage1_of_2(mmu_idx)) {
0710b2fa
PM		 3426 /*
3427 * Synchronous stage 2 fault on an access made as part of the
3428 * translation table walk for AT S1E0* or AT S1E1* insn
3429 * executed from NS EL1. If this is a synchronous external abort
3430 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3431 * to EL3. Otherwise the fault is taken as an exception to EL2,
3432 * and HPFAR_EL2 holds the faulting IPA.
3433 */
3434 if (fi.type == ARMFault_SyncExternalOnWalk &&
3435 (env->cp15.scr_el3 & SCR_EA)) {
3436 target_el = 3;
3437 } else {
3438 env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4;
3439 target_el = 2;
3440 }
3441 take_exc = true;
3442 } else if (fi.type == ARMFault_SyncExternalOnWalk) {
3443 /*
3444 * Synchronous external aborts during a translation table walk
3445 * are taken as Data Abort exceptions.
3446 */
3447 if (fi.stage2) {
3448 if (current_el == 3) {
3449 target_el = 3;
3450 } else {
3451 target_el = 2;
3452 }
3453 } else {
3454 target_el = exception_target_el(env);
3455 }
3456 take_exc = true;
3457 }
3458
3459 if (take_exc) {
3460 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3461 if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
3462 arm_s1_regime_using_lpae_format(env, mmu_idx)) {
3463 fsr = arm_fi_to_lfsc(&fi);
3464 fsc = extract32(fsr, 0, 6);
3465 } else {
3466 fsr = arm_fi_to_sfsc(&fi);
3467 fsc = 0x3f;
3468 }
3469 /*
3470 * Report exception with ESR indicating a fault due to a
3471 * translation table walk for a cache maintenance instruction.
3472 */
e24fd076 3473 syn = syn_data_abort_no_iss(current_el == target_el, 0,
0710b2fa
PM		 3474 fi.ea, 1, fi.s1ptw, 1, fsc);
3475 env->exception.vaddress = value;
3476 env->exception.fsr = fsr;
3477 raise_exception(env, EXCP_DATA_ABORT, syn, target_el);
3478 }
3479 }
3480
1313e2d7
EI		 3481 if (is_a64(env)) {
3482 format64 = true;
3483 } else if (arm_feature(env, ARM_FEATURE_LPAE)) {
3484 /*
3485 * ATS1Cxx:
3486 * * TTBCR.EAE determines whether the result is returned using the
3487 * 32-bit or the 64-bit PAR format
3488 * * Instructions executed in Hyp mode always use the 64bit format
3489 *
3490 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3491 * * The Non-secure TTBCR.EAE bit is set to 1
3492 * * The implementation includes EL2, and the value of HCR.VM is 1
3493 *
9d1bab33
PM		 3494 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3495 *
23463e0e 3496 * ATS1Hx always uses the 64bit format.
1313e2d7
EI		 3497 */
3498 format64 = arm_s1_regime_using_lpae_format(env, mmu_idx);
3499
3500 if (arm_feature(env, ARM_FEATURE_EL2)) {
452ef8cb
RH		 3501 if (mmu_idx == ARMMMUIdx_E10_0 ||
3502 mmu_idx == ARMMMUIdx_E10_1 ||
3503 mmu_idx == ARMMMUIdx_E10_1_PAN) {
9d1bab33 3504 format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC);
1313e2d7
EI		 3505 } else {
3506 format64 |= arm_current_el(env) == 2;
3507 }
3508 }
3509 }
3510
3511 if (format64) {
5efe9ed4 3512 /* Create a 64-bit PAR */
01c097f7 3513 par64 = (1 << 11); /* LPAE bit always set */
b7cc4e82 3514 if (!ret) {
702a9357 3515 par64 |= phys_addr & ~0xfffULL;
8bf5b6a9
PM		 3516 if (!attrs.secure) {
3517 par64 |= (1 << 9); /* NS */
3518 }
5b2d261d
AB		 3519 par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */
3520 par64 |= cacheattrs.shareability << 7; /* SH */
4a501606 3521 } else {
5efe9ed4
PM		 3522 uint32_t fsr = arm_fi_to_lfsc(&fi);
3523
702a9357 3524 par64 |= 1; /* F */
b7cc4e82 3525 par64 |= (fsr & 0x3f) << 1; /* FS */
0f7b791b
PM		 3526 if (fi.stage2) {
3527 par64 |= (1 << 9); /* S */
3528 }
3529 if (fi.s1ptw) {
3530 par64 |= (1 << 8); /* PTW */
3531 }
4a501606
PM		 3532 }
3533 } else {
b7cc4e82 3534 /* fsr is a DFSR/IFSR value for the short descriptor
702a9357
PM		 3535 * translation table format (with WnR always clear).
3536 * Convert it to a 32-bit PAR.
3537 */
b7cc4e82 3538 if (!ret) {
702a9357
PM		 3539 /* We do not set any attribute bits in the PAR */
3540 if (page_size == (1 << 24)
3541 && arm_feature(env, ARM_FEATURE_V7)) {
01c097f7 3542 par64 = (phys_addr & 0xff000000) | (1 << 1);
702a9357 3543 } else {
01c097f7 3544 par64 = phys_addr & 0xfffff000;
702a9357 3545 }
8bf5b6a9
PM		 3546 if (!attrs.secure) {
3547 par64 |= (1 << 9); /* NS */
3548 }
702a9357 3549 } else {
5efe9ed4
PM		 3550 uint32_t fsr = arm_fi_to_sfsc(&fi);
3551
b7cc4e82
PC		 3552 par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
3553 ((fsr & 0xf) << 1) | 1;
702a9357 3554 }
4a501606 3555 }
060e8a48
PM		 3556 return par64;
3557}
9fb005b0 3558#endif /* CONFIG_TCG */
060e8a48
PM		 3559
3560static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3561{
9fb005b0 3562#ifdef CONFIG_TCG
03ae85f8 3563 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
060e8a48 3564 uint64_t par64;
d3649702
PM		 3565 ARMMMUIdx mmu_idx;
3566 int el = arm_current_el(env);
3567 bool secure = arm_is_secure_below_el3(env);
060e8a48 3568
d3649702
PM		 3569 switch (ri->opc2 & 6) {
3570 case 0:
04b07d29 3571 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
d3649702
PM		 3572 switch (el) {
3573 case 3:
127b2b08 3574 mmu_idx = ARMMMUIdx_SE3;
d3649702
PM		 3575 break;
3576 case 2:
04b07d29
RH		 3577 g_assert(!secure); /* TODO: ARMv8.4-SecEL2 */
3578 /* fall through */
d3649702 3579 case 1:
04b07d29
RH		 3580 if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) {
3581 mmu_idx = (secure ? ARMMMUIdx_SE10_1_PAN
3582 : ARMMMUIdx_Stage1_E1_PAN);
3583 } else {
3584 mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1;
3585 }
d3649702
PM		 3586 break;
3587 default:
3588 g_assert_not_reached();
3589 }
3590 break;
3591 case 2:
3592 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3593 switch (el) {
3594 case 3:
fba37aed 3595 mmu_idx = ARMMMUIdx_SE10_0;
d3649702
PM		 3596 break;
3597 case 2:
2859d7b5 3598 mmu_idx = ARMMMUIdx_Stage1_E0;
d3649702
PM		 3599 break;
3600 case 1:
fba37aed 3601 mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0;
d3649702
PM		 3602 break;
3603 default:
3604 g_assert_not_reached();
3605 }
3606 break;
3607 case 4:
3608 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
01b98b68 3609 mmu_idx = ARMMMUIdx_E10_1;
d3649702
PM		 3610 break;
3611 case 6:
3612 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
01b98b68 3613 mmu_idx = ARMMMUIdx_E10_0;
d3649702
PM		 3614 break;
3615 default:
3616 g_assert_not_reached();
3617 }
3618
3619 par64 = do_ats_write(env, value, access_type, mmu_idx);
01c097f7
FA		 3620
3621 A32_BANKED_CURRENT_REG_SET(env, par, par64);
9fb005b0
PMD		 3622#else
3623 /* Handled by hardware accelerator. */
3624 g_assert_not_reached();
3625#endif /* CONFIG_TCG */
4a501606 3626}
060e8a48 3627
14db7fe0
PM		 3628static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
3629 uint64_t value)
3630{
9fb005b0 3631#ifdef CONFIG_TCG
03ae85f8 3632 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
14db7fe0
PM		 3633 uint64_t par64;
3634
e013b741 3635 par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2);
14db7fe0
PM		 3636
3637 A32_BANKED_CURRENT_REG_SET(env, par, par64);
9fb005b0
PMD		 3638#else
3639 /* Handled by hardware accelerator. */
3640 g_assert_not_reached();
3641#endif /* CONFIG_TCG */
14db7fe0
PM		 3642}
3643
3f208fd7
PM		 3644static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
3645 bool isread)
2a47df95
PM		 3646{
3647 if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
3648 return CP_ACCESS_TRAP;
3649 }
3650 return CP_ACCESS_OK;
3651}
3652
060e8a48
PM		 3653static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
3654 uint64_t value)
3655{
9fb005b0 3656#ifdef CONFIG_TCG
03ae85f8 3657 MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
d3649702
PM		 3658 ARMMMUIdx mmu_idx;
3659 int secure = arm_is_secure_below_el3(env);
3660
3661 switch (ri->opc2 & 6) {
3662 case 0:
3663 switch (ri->opc1) {
04b07d29
RH		 3664 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3665 if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) {
3666 mmu_idx = (secure ? ARMMMUIdx_SE10_1_PAN
3667 : ARMMMUIdx_Stage1_E1_PAN);
3668 } else {
3669 mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1;
3670 }
d3649702
PM		 3671 break;
3672 case 4: /* AT S1E2R, AT S1E2W */
e013b741 3673 mmu_idx = ARMMMUIdx_E2;
d3649702
PM		 3674 break;
3675 case 6: /* AT S1E3R, AT S1E3W */
127b2b08 3676 mmu_idx = ARMMMUIdx_SE3;
d3649702
PM		 3677 break;
3678 default:
3679 g_assert_not_reached();
3680 }
3681 break;
3682 case 2: /* AT S1E0R, AT S1E0W */
fba37aed 3683 mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_Stage1_E0;
d3649702
PM		 3684 break;
3685 case 4: /* AT S12E1R, AT S12E1W */
fba37aed 3686 mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1;
d3649702
PM		 3687 break;
3688 case 6: /* AT S12E0R, AT S12E0W */
fba37aed 3689 mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0;
d3649702
PM		 3690 break;
3691 default:
3692 g_assert_not_reached();
3693 }
060e8a48 3694
d3649702 3695 env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
9fb005b0
PMD		 3696#else
3697 /* Handled by hardware accelerator. */
3698 g_assert_not_reached();
3699#endif /* CONFIG_TCG */
060e8a48 3700}
4a501606
PM		 3701#endif
3702
3703static const ARMCPRegInfo vapa_cp_reginfo[] = {
3704 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
3705 .access = PL1_RW, .resetvalue = 0,
01c097f7
FA		 3706 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
3707 offsetoflow32(CPUARMState, cp15.par_ns) },
4a501606
PM		 3708 .writefn = par_write },
3709#ifndef CONFIG_USER_ONLY
87562e4f 3710 /* This underdecoding is safe because the reginfo is NO_RAW. */
4a501606 3711 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
92611c00 3712 .access = PL1_W, .accessfn = ats_access,
0710b2fa 3713 .writefn = ats_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
4a501606
PM		 3714#endif
3715 REGINFO_SENTINEL
3716};
3717
18032bec
PM		 3718/* Return basic MPU access permission bits. */
3719static uint32_t simple_mpu_ap_bits(uint32_t val)
3720{
3721 uint32_t ret;
3722 uint32_t mask;
3723 int i;
3724 ret = 0;
3725 mask = 3;
3726 for (i = 0; i < 16; i += 2) {
3727 ret |= (val >> i) & mask;
3728 mask <<= 2;
3729 }
3730 return ret;
3731}
3732
3733/* Pad basic MPU access permission bits to extended format. */
3734static uint32_t extended_mpu_ap_bits(uint32_t val)
3735{
3736 uint32_t ret;
3737 uint32_t mask;
3738 int i;
3739 ret = 0;
3740 mask = 3;
3741 for (i = 0; i < 16; i += 2) {
3742 ret |= (val & mask) << i;
3743 mask <<= 2;
3744 }
3745 return ret;
3746}
3747
c4241c7d
PM		 3748static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
3749 uint64_t value)
18032bec 3750{
7e09797c 3751 env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
18032bec
PM		 3752}
3753
c4241c7d 3754static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
18032bec 3755{
7e09797c 3756 return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
18032bec
PM		 3757}
3758
c4241c7d
PM		 3759static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
3760 uint64_t value)
18032bec 3761{
7e09797c 3762 env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
18032bec
PM		 3763}
3764
c4241c7d 3765static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
18032bec 3766{
7e09797c 3767 return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
18032bec
PM		 3768}
3769
6cb0b013
PC		 3770static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
3771{
3772 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
3773
3774 if (!u32p) {
3775 return 0;
3776 }
3777
1bc04a88 3778 u32p += env->pmsav7.rnr[M_REG_NS];
6cb0b013
PC		 3779 return *u32p;
3780}
3781
3782static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
3783 uint64_t value)
3784{
2fc0cc0e 3785 ARMCPU *cpu = env_archcpu(env);
6cb0b013
PC		 3786 uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
3787
3788 if (!u32p) {
3789 return;
3790 }
3791
1bc04a88 3792 u32p += env->pmsav7.rnr[M_REG_NS];
d10eb08f 3793 tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
6cb0b013
PC		 3794 *u32p = value;
3795}
3796
6cb0b013
PC		 3797static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3798 uint64_t value)
3799{
2fc0cc0e 3800 ARMCPU *cpu = env_archcpu(env);
6cb0b013
PC		 3801 uint32_t nrgs = cpu->pmsav7_dregion;
3802
3803 if (value >= nrgs) {
3804 qemu_log_mask(LOG_GUEST_ERROR,
3805 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3806 " > %" PRIu32 "\n", (uint32_t)value, nrgs);
3807 return;
3808 }
3809
3810 raw_write(env, ri, value);
3811}
3812
3813static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
69ceea64
PM		 3814 /* Reset for all these registers is handled in arm_cpu_reset(),
3815 * because the PMSAv7 is also used by M-profile CPUs, which do
3816 * not register cpregs but still need the state to be reset.
3817 */
6cb0b013
PC		 3818 { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
3819 .access = PL1_RW, .type = ARM_CP_NO_RAW,
3820 .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
69ceea64
PM		 3821 .readfn = pmsav7_read, .writefn = pmsav7_write,
3822 .resetfn = arm_cp_reset_ignore },
6cb0b013
PC		 3823 { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
3824 .access = PL1_RW, .type = ARM_CP_NO_RAW,
3825 .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
69ceea64
PM		 3826 .readfn = pmsav7_read, .writefn = pmsav7_write,
3827 .resetfn = arm_cp_reset_ignore },
6cb0b013
PC		 3828 { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
3829 .access = PL1_RW, .type = ARM_CP_NO_RAW,
3830 .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
69ceea64
PM		 3831 .readfn = pmsav7_read, .writefn = pmsav7_write,
3832 .resetfn = arm_cp_reset_ignore },
6cb0b013
PC		 3833 { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
3834 .access = PL1_RW,
1bc04a88 3835 .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]),
69ceea64
PM		 3836 .writefn = pmsav7_rgnr_write,
3837 .resetfn = arm_cp_reset_ignore },
6cb0b013
PC		 3838 REGINFO_SENTINEL
3839};
3840
18032bec
PM		 3841static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
3842 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
7a0e58fa 3843 .access = PL1_RW, .type = ARM_CP_ALIAS,
7e09797c 3844 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
18032bec
PM		 3845 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
3846 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
7a0e58fa 3847 .access = PL1_RW, .type = ARM_CP_ALIAS,
7e09797c 3848 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
18032bec
PM		 3849 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
3850 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
3851 .access = PL1_RW,
7e09797c
PM		 3852 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
3853 .resetvalue = 0, },
18032bec
PM		 3854 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
3855 .access = PL1_RW,
7e09797c
PM		 3856 .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
3857 .resetvalue = 0, },
ecce5c3c
PM		 3858 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
3859 .access = PL1_RW,
3860 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
3861 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
3862 .access = PL1_RW,
3863 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
06d76f31 3864 /* Protection region base and size registers */
e508a92b
PM		 3865 { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
3866 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3867 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
3868 { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
3869 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3870 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
3871 { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
3872 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3873 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
3874 { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
3875 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3876 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
3877 { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
3878 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3879 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
3880 { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
3881 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3882 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
3883 { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
3884 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3885 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
3886 { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
3887 .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
3888 .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
18032bec
PM		 3889 REGINFO_SENTINEL
3890};
3891
c4241c7d
PM		 3892static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
3893 uint64_t value)
ecce5c3c 3894{
11f136ee 3895 TCR *tcr = raw_ptr(env, ri);
2ebcebe2
PM		 3896 int maskshift = extract32(value, 0, 3);
3897
e389be16
FA		 3898 if (!arm_feature(env, ARM_FEATURE_V8)) {
3899 if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
3900 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
3901 * using Long-desciptor translation table format */
3902 value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
3903 } else if (arm_feature(env, ARM_FEATURE_EL3)) {
3904 /* In an implementation that includes the Security Extensions
3905 * TTBCR has additional fields PD0 [4] and PD1 [5] for
3906 * Short-descriptor translation table format.
3907 */
3908 value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
3909 } else {
3910 value &= TTBCR_N;
3911 }
e42c4db3 3912 }
e389be16 3913
b6af0975 3914 /* Update the masks corresponding to the TCR bank being written
11f136ee 3915 * Note that we always calculate mask and base_mask, but
e42c4db3 3916 * they are only used for short-descriptor tables (ie if EAE is 0);
11f136ee
FA		 3917 * for long-descriptor tables the TCR fields are used differently
3918 * and the mask and base_mask values are meaningless.
e42c4db3 3919 */
11f136ee
FA		 3920 tcr->raw_tcr = value;
3921 tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
3922 tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
ecce5c3c
PM		 3923}
3924
c4241c7d
PM		 3925static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3926 uint64_t value)
d4e6df63 3927{
2fc0cc0e 3928 ARMCPU *cpu = env_archcpu(env);
ab638a32 3929 TCR *tcr = raw_ptr(env, ri);
00c8cb0a 3930
d4e6df63
PM		 3931 if (arm_feature(env, ARM_FEATURE_LPAE)) {
3932 /* With LPAE the TTBCR could result in a change of ASID
3933 * via the TTBCR.A1 bit, so do a TLB flush.
3934 */
d10eb08f 3935 tlb_flush(CPU(cpu));
d4e6df63 3936 }
ab638a32
RH		 3937 /* Preserve the high half of TCR_EL1, set via TTBCR2. */
3938 value = deposit64(tcr->raw_tcr, 0, 32, value);
c4241c7d 3939 vmsa_ttbcr_raw_write(env, ri, value);
d4e6df63
PM		 3940}
3941
ecce5c3c
PM		 3942static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
3943{
11f136ee
FA		 3944 TCR *tcr = raw_ptr(env, ri);
3945
3946 /* Reset both the TCR as well as the masks corresponding to the bank of
3947 * the TCR being reset.
3948 */
3949 tcr->raw_tcr = 0;
3950 tcr->mask = 0;
3951 tcr->base_mask = 0xffffc000u;
ecce5c3c
PM		 3952}
3953
d06dc933 3954static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri,
cb2e37df
PM		 3955 uint64_t value)
3956{
2fc0cc0e 3957 ARMCPU *cpu = env_archcpu(env);
11f136ee 3958 TCR *tcr = raw_ptr(env, ri);
00c8cb0a 3959
cb2e37df 3960 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
d10eb08f 3961 tlb_flush(CPU(cpu));
11f136ee 3962 tcr->raw_tcr = value;
cb2e37df
PM		 3963}
3964
327ed10f
PM		 3965static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3966 uint64_t value)
3967{
93f379b0
RH		 3968 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
3969 if (cpreg_field_is_64bit(ri) &&
3970 extract64(raw_read(env, ri) ^ value, 48, 16) != 0) {
2fc0cc0e 3971 ARMCPU *cpu = env_archcpu(env);
d10eb08f 3972 tlb_flush(CPU(cpu));
327ed10f
PM		 3973 }
3974 raw_write(env, ri, value);
3975}
3976
ed30da8e
RH		 3977static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
3978 uint64_t value)
3979{
d06dc933
RH		 3980 /*
3981 * If we are running with E2&0 regime, then an ASID is active.
3982 * Flush if that might be changing. Note we're not checking
3983 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
3984 * holds the active ASID, only checking the field that might.
3985 */
3986 if (extract64(raw_read(env, ri) ^ value, 48, 16) &&
3987 (arm_hcr_el2_eff(env) & HCR_E2H)) {
3988 tlb_flush_by_mmuidx(env_cpu(env),
452ef8cb
RH		 3989 ARMMMUIdxBit_E20_2 |
3990 ARMMMUIdxBit_E20_2_PAN |
3991 ARMMMUIdxBit_E20_0);
d06dc933 3992 }
ed30da8e
RH		 3993 raw_write(env, ri, value);
3994}
3995
b698e9cf
EI		 3996static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3997 uint64_t value)
3998{
2fc0cc0e 3999 ARMCPU *cpu = env_archcpu(env);
b698e9cf
EI		 4000 CPUState *cs = CPU(cpu);
4001
97fa9350
RH		 4002 /*
4003 * A change in VMID to the stage2 page table (Stage2) invalidates
4004 * the combined stage 1&2 tlbs (EL10_1 and EL10_0).
4005 */
b698e9cf 4006 if (raw_read(env, ri) != value) {
0336cbf8 4007 tlb_flush_by_mmuidx(cs,
01b98b68 4008 ARMMMUIdxBit_E10_1 |
452ef8cb 4009 ARMMMUIdxBit_E10_1_PAN |
bf05340c 4010 ARMMMUIdxBit_E10_0);
b698e9cf
EI		 4011 raw_write(env, ri, value);
4012 }
4013}
4014
8e5d75c9 4015static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
18032bec 4016 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
84929218 4017 .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS,
4a7e2d73 4018 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
b061a82b 4019 offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
18032bec 4020 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
84929218 4021 .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
88ca1c2d
FA		 4022 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
4023 offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
8e5d75c9 4024 { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
84929218 4025 .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
8e5d75c9
PC		 4026 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
4027 offsetof(CPUARMState, cp15.dfar_ns) } },
4028 { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
4029 .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
84929218
RH		 4030 .access = PL1_RW, .accessfn = access_tvm_trvm,
4031 .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
8e5d75c9
PC		 4032 .resetvalue = 0, },
4033 REGINFO_SENTINEL
4034};
4035
4036static const ARMCPRegInfo vmsa_cp_reginfo[] = {
6cd8a264
RH		 4037 { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
4038 .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
84929218 4039 .access = PL1_RW, .accessfn = access_tvm_trvm,
d81c519c 4040 .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
327ed10f 4041 { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
7dd8c9af 4042 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
84929218
RH		 4043 .access = PL1_RW, .accessfn = access_tvm_trvm,
4044 .writefn = vmsa_ttbr_write, .resetvalue = 0,
7dd8c9af
FA		 4045 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
4046 offsetof(CPUARMState, cp15.ttbr0_ns) } },
327ed10f 4047 { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
7dd8c9af 4048 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
84929218
RH		 4049 .access = PL1_RW, .accessfn = access_tvm_trvm,
4050 .writefn = vmsa_ttbr_write, .resetvalue = 0,
7dd8c9af
FA		 4051 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
4052 offsetof(CPUARMState, cp15.ttbr1_ns) } },
cb2e37df
PM		 4053 { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
4054 .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
84929218
RH		 4055 .access = PL1_RW, .accessfn = access_tvm_trvm,
4056 .writefn = vmsa_tcr_el12_write,
cb2e37df 4057 .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
11f136ee 4058 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
cb2e37df 4059 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
84929218
RH		 4060 .access = PL1_RW, .accessfn = access_tvm_trvm,
4061 .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
b061a82b 4062 .raw_writefn = vmsa_ttbcr_raw_write,
11f136ee
FA		 4063 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
4064 offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
18032bec
PM		 4065 REGINFO_SENTINEL
4066};
4067
ab638a32
RH		 4068/* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
4069 * qemu tlbs nor adjusting cached masks.
4070 */
4071static const ARMCPRegInfo ttbcr2_reginfo = {
4072 .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3,
84929218
RH		 4073 .access = PL1_RW, .accessfn = access_tvm_trvm,
4074 .type = ARM_CP_ALIAS,
ab638a32
RH		 4075 .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]),
4076 offsetofhigh32(CPUARMState, cp15.tcr_el[1]) },
4077};
4078
c4241c7d
PM		 4079static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
4080 uint64_t value)
1047b9d7
PM		 4081{
4082 env->cp15.c15_ticonfig = value & 0xe7;
4083 /* The OS_TYPE bit in this register changes the reported CPUID! */
4084 env->cp15.c0_cpuid = (value & (1 << 5)) ?
4085 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1047b9d7
PM		 4086}
4087
c4241c7d
PM		 4088static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
4089 uint64_t value)
1047b9d7
PM		 4090{
4091 env->cp15.c15_threadid = value & 0xffff;
1047b9d7
PM		 4092}
4093
c4241c7d
PM		 4094static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
4095 uint64_t value)
1047b9d7
PM		 4096{
4097 /* Wait-for-interrupt (deprecated) */
2fc0cc0e 4098 cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT);
1047b9d7
PM		 4099}
4100
c4241c7d
PM		 4101static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
4102 uint64_t value)
c4804214
PM		 4103{
4104 /* On OMAP there are registers indicating the max/min index of dcache lines
4105 * containing a dirty line; cache flush operations have to reset these.
4106 */
4107 env->cp15.c15_i_max = 0x000;
4108 env->cp15.c15_i_min = 0xff0;
c4804214
PM		 4109}
4110
18032bec
PM		 4111static const ARMCPRegInfo omap_cp_reginfo[] = {
4112 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
4113 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
d81c519c 4114 .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
6cd8a264 4115 .resetvalue = 0, },
1047b9d7
PM		 4116 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
4117 .access = PL1_RW, .type = ARM_CP_NOP },
4118 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
4119 .access = PL1_RW,
4120 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
4121 .writefn = omap_ticonfig_write },
4122 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
4123 .access = PL1_RW,
4124 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
4125 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
4126 .access = PL1_RW, .resetvalue = 0xff0,
4127 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
4128 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
4129 .access = PL1_RW,
4130 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
4131 .writefn = omap_threadid_write },
4132 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
4133 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
7a0e58fa 4134 .type = ARM_CP_NO_RAW,
1047b9d7
PM		 4135 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
4136 /* TODO: Peripheral port remap register:
4137 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
4138 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
4139 * when MMU is off.
4140 */
c4804214 4141 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
d4e6df63 4142 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
7a0e58fa 4143 .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
c4804214 4144 .writefn = omap_cachemaint_write },
34f90529
PM		 4145 { .name = "C9", .cp = 15, .crn = 9,
4146 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
4147 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1047b9d7
PM		 4148 REGINFO_SENTINEL
4149};
4150
c4241c7d
PM		 4151static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
4152 uint64_t value)
1047b9d7 4153{
c0f4af17 4154 env->cp15.c15_cpar = value & 0x3fff;
1047b9d7
PM		 4155}
4156
4157static const ARMCPRegInfo xscale_cp_reginfo[] = {
4158 { .name = "XSCALE_CPAR",
4159 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
4160 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
4161 .writefn = xscale_cpar_write, },
2771db27
PM		 4162 { .name = "XSCALE_AUXCR",
4163 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
4164 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
4165 .resetvalue = 0, },
3b771579
PM		 4166 /* XScale specific cache-lockdown: since we have no cache we NOP these
4167 * and hope the guest does not really rely on cache behaviour.
4168 */
4169 { .name = "XSCALE_LOCK_ICACHE_LINE",
4170 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
4171 .access = PL1_W, .type = ARM_CP_NOP },
4172 { .name = "XSCALE_UNLOCK_ICACHE",
4173 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
4174 .access = PL1_W, .type = ARM_CP_NOP },
4175 { .name = "XSCALE_DCACHE_LOCK",
4176 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
4177 .access = PL1_RW, .type = ARM_CP_NOP },
4178 { .name = "XSCALE_UNLOCK_DCACHE",
4179 .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
4180 .access = PL1_W, .type = ARM_CP_NOP },
1047b9d7
PM		 4181 REGINFO_SENTINEL
4182};
4183
4184static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
4185 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
4186 * implementation of this implementation-defined space.
4187 * Ideally this should eventually disappear in favour of actually
4188 * implementing the correct behaviour for all cores.
4189 */
4190 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
4191 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
3671cd87 4192 .access = PL1_RW,
7a0e58fa 4193 .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
d4e6df63 4194 .resetvalue = 0 },
18032bec
PM		 4195 REGINFO_SENTINEL
4196};
4197
c4804214
PM		 4198static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
4199 /* Cache status: RAZ because we have no cache so it's always clean */
4200 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
7a0e58fa 4201 .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
d4e6df63 4202 .resetvalue = 0 },
c4804214
PM		 4203 REGINFO_SENTINEL
4204};
4205
4206static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
4207 /* We never have a a block transfer operation in progress */
4208 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
7a0e58fa 4209 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
d4e6df63 4210 .resetvalue = 0 },
30b05bba
PM		 4211 /* The cache ops themselves: these all NOP for QEMU */
4212 { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
4213 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4214 { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
4215 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4216 { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
4217 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4218 { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
4219 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4220 { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
4221 .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
4222 { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
4223 .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
c4804214
PM		 4224 REGINFO_SENTINEL
4225};
4226
4227static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
4228 /* The cache test-and-clean instructions always return (1 << 30)
4229 * to indicate that there are no dirty cache lines.
4230 */
4231 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
7a0e58fa 4232 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
d4e6df63 4233 .resetvalue = (1 << 30) },
c4804214 4234 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
7a0e58fa 4235 .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
d4e6df63 4236 .resetvalue = (1 << 30) },
c4804214
PM		 4237 REGINFO_SENTINEL
4238};
4239
34f90529
PM		 4240static const ARMCPRegInfo strongarm_cp_reginfo[] = {
4241 /* Ignore ReadBuffer accesses */
4242 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
4243 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
d4e6df63 4244 .access = PL1_RW, .resetvalue = 0,
7a0e58fa 4245 .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
34f90529
PM		 4246 REGINFO_SENTINEL
4247};
4248
731de9e6
EI		 4249static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
4250{
2fc0cc0e 4251 ARMCPU *cpu = env_archcpu(env);
731de9e6
EI		 4252 unsigned int cur_el = arm_current_el(env);
4253 bool secure = arm_is_secure(env);
4254
4255 if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
4256 return env->cp15.vpidr_el2;
4257 }
4258 return raw_read(env, ri);
4259}
4260
06a7e647 4261static uint64_t mpidr_read_val(CPUARMState *env)
81bdde9d 4262{
2fc0cc0e 4263 ARMCPU *cpu = env_archcpu(env);
eb5e1d3c
PF		 4264 uint64_t mpidr = cpu->mp_affinity;
4265
81bdde9d 4266 if (arm_feature(env, ARM_FEATURE_V7MP)) {
78dbbbe4 4267 mpidr |= (1U << 31);
81bdde9d
PM		 4268 /* Cores which are uniprocessor (non-coherent)
4269 * but still implement the MP extensions set
a8e81b31 4270 * bit 30. (For instance, Cortex-R5).
81bdde9d 4271 */
a8e81b31
PC		 4272 if (cpu->mp_is_up) {
4273 mpidr |= (1u << 30);
4274 }
81bdde9d 4275 }
c4241c7d 4276 return mpidr;
81bdde9d
PM		 4277}
4278
06a7e647
EI		 4279static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
4280{
f0d574d6
EI		 4281 unsigned int cur_el = arm_current_el(env);
4282 bool secure = arm_is_secure(env);
4283
4284 if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
4285 return env->cp15.vmpidr_el2;
4286 }
06a7e647
EI		 4287 return mpidr_read_val(env);
4288}
4289
7ac681cf 4290static const ARMCPRegInfo lpae_cp_reginfo[] = {
a903c449 4291 /* NOP AMAIR0/1 */
b0fe2427
PM		 4292 { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
4293 .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
84929218
RH		 4294 .access = PL1_RW, .accessfn = access_tvm_trvm,
4295 .type = ARM_CP_CONST, .resetvalue = 0 },
b0fe2427 4296 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
7ac681cf 4297 { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
84929218
RH		 4298 .access = PL1_RW, .accessfn = access_tvm_trvm,
4299 .type = ARM_CP_CONST, .resetvalue = 0 },
891a2fe7 4300 { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
01c097f7
FA		 4301 .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
4302 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
4303 offsetof(CPUARMState, cp15.par_ns)} },
891a2fe7 4304 { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
84929218
RH		 4305 .access = PL1_RW, .accessfn = access_tvm_trvm,
4306 .type = ARM_CP_64BIT | ARM_CP_ALIAS,
7dd8c9af
FA		 4307 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
4308 offsetof(CPUARMState, cp15.ttbr0_ns) },
b061a82b 4309 .writefn = vmsa_ttbr_write, },
891a2fe7 4310 { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
84929218
RH		 4311 .access = PL1_RW, .accessfn = access_tvm_trvm,
4312 .type = ARM_CP_64BIT | ARM_CP_ALIAS,
7dd8c9af
FA		 4313 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
4314 offsetof(CPUARMState, cp15.ttbr1_ns) },
b061a82b 4315 .writefn = vmsa_ttbr_write, },
7ac681cf
PM		 4316 REGINFO_SENTINEL
4317};
4318
c4241c7d 4319static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
b0d2b7d0 4320{
c4241c7d 4321 return vfp_get_fpcr(env);
b0d2b7d0
PM		 4322}
4323
c4241c7d
PM		 4324static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4325 uint64_t value)
b0d2b7d0
PM		 4326{
4327 vfp_set_fpcr(env, value);
b0d2b7d0
PM		 4328}
4329
c4241c7d 4330static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
b0d2b7d0 4331{
c4241c7d 4332 return vfp_get_fpsr(env);
b0d2b7d0
PM		 4333}
4334
c4241c7d
PM		 4335static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4336 uint64_t value)
b0d2b7d0
PM		 4337{
4338 vfp_set_fpsr(env, value);
b0d2b7d0
PM		 4339}
4340
3f208fd7
PM		 4341static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri,
4342 bool isread)
c2b820fe 4343{
aaec1432 4344 if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) {
c2b820fe
PM		 4345 return CP_ACCESS_TRAP;
4346 }
4347 return CP_ACCESS_OK;
4348}
4349
4350static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
4351 uint64_t value)
4352{
4353 env->daif = value & PSTATE_DAIF;
4354}
4355
220f508f
RH		 4356static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri)
4357{
4358 return env->pstate & PSTATE_PAN;
4359}
4360
4361static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri,
4362 uint64_t value)
4363{
4364 env->pstate = (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN);
4365}
4366
4367static const ARMCPRegInfo pan_reginfo = {
4368 .name = "PAN", .state = ARM_CP_STATE_AA64,
4369 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 3,
4370 .type = ARM_CP_NO_RAW, .access = PL1_RW,
4371 .readfn = aa64_pan_read, .writefn = aa64_pan_write
4372};
4373
9eeb7a1c
RH		 4374static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri)
4375{
4376 return env->pstate & PSTATE_UAO;
4377}
4378
4379static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri,
4380 uint64_t value)
4381{
4382 env->pstate = (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO);
4383}
4384
4385static const ARMCPRegInfo uao_reginfo = {
4386 .name = "UAO", .state = ARM_CP_STATE_AA64,
4387 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4,
4388 .type = ARM_CP_NO_RAW, .access = PL1_RW,
4389 .readfn = aa64_uao_read, .writefn = aa64_uao_write
4390};
4391
38262d8a
RH		 4392static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
4393 const ARMCPRegInfo *ri,
4394 bool isread)
8af35c37 4395{
38262d8a
RH		 4396 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4397 switch (arm_current_el(env)) {
4398 case 0:
4399 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4400 if (!(arm_sctlr(env, 0) & SCTLR_UCI)) {
4401 return CP_ACCESS_TRAP;
4402 }
4403 /* fall through */
4404 case 1:
4405 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4406 if (arm_hcr_el2_eff(env) & HCR_TPCP) {
4407 return CP_ACCESS_TRAP_EL2;
4408 }
4409 break;
8af35c37
PM		 4410 }
4411 return CP_ACCESS_OK;
4412}
4413
38262d8a 4414static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
1bed4d2e
RH		 4415 const ARMCPRegInfo *ri,
4416 bool isread)
4417{
38262d8a 4418 /* Cache invalidate/clean to Point of Unification... */
1bed4d2e
RH		 4419 switch (arm_current_el(env)) {
4420 case 0:
4421 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4422 if (!(arm_sctlr(env, 0) & SCTLR_UCI)) {
4423 return CP_ACCESS_TRAP;
4424 }
4425 /* fall through */
4426 case 1:
38262d8a
RH		 4427 /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */
4428 if (arm_hcr_el2_eff(env) & HCR_TPU) {
1bed4d2e
RH		 4429 return CP_ACCESS_TRAP_EL2;
4430 }
4431 break;
4432 }
4433 return CP_ACCESS_OK;
4434}
4435
dbb1fb27
AB		 4436/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4437 * Page D4-1736 (DDI0487A.b)
4438 */
4439
b7e0730d
RH		 4440static int vae1_tlbmask(CPUARMState *env)
4441{
85d0dc9f 4442 /* Since we exclude secure first, we may read HCR_EL2 directly. */
b7e0730d 4443 if (arm_is_secure_below_el3(env)) {
452ef8cb
RH		 4444 return ARMMMUIdxBit_SE10_1 |
4445 ARMMMUIdxBit_SE10_1_PAN |
4446 ARMMMUIdxBit_SE10_0;
85d0dc9f
RH		 4447 } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE))
4448 == (HCR_E2H | HCR_TGE)) {
452ef8cb
RH		 4449 return ARMMMUIdxBit_E20_2 |
4450 ARMMMUIdxBit_E20_2_PAN |
4451 ARMMMUIdxBit_E20_0;
b7e0730d 4452 } else {
452ef8cb
RH		 4453 return ARMMMUIdxBit_E10_1 |
4454 ARMMMUIdxBit_E10_1_PAN |
4455 ARMMMUIdxBit_E10_0;
b7e0730d
RH		 4456 }
4457}
4458
ea04dce7
RH		 4459/* Return 56 if TBI is enabled, 64 otherwise. */
4460static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx,
4461 uint64_t addr)
4462{
4463 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
4464 int tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
4465 int select = extract64(addr, 55, 1);
4466
4467 return (tbi >> select) & 1 ? 56 : 64;
4468}
4469
4470static int vae1_tlbbits(CPUARMState *env, uint64_t addr)
4471{
4472 ARMMMUIdx mmu_idx;
4473
4474 /* Only the regime of the mmu_idx below is significant. */
4475 if (arm_is_secure_below_el3(env)) {
4476 mmu_idx = ARMMMUIdx_SE10_0;
4477 } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE))
4478 == (HCR_E2H | HCR_TGE)) {
4479 mmu_idx = ARMMMUIdx_E20_0;
4480 } else {
4481 mmu_idx = ARMMMUIdx_E10_0;
4482 }
4483 return tlbbits_for_regime(env, mmu_idx, addr);
4484}
4485
fd3ed969
PM		 4486static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4487 uint64_t value)
168aa23b 4488{
29a0af61 4489 CPUState *cs = env_cpu(env);
b7e0730d 4490 int mask = vae1_tlbmask(env);
dbb1fb27 4491
b7e0730d 4492 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
168aa23b
PM		 4493}
4494
b4ab8ce9
PM		 4495static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
4496 uint64_t value)
4497{
29a0af61 4498 CPUState *cs = env_cpu(env);
b7e0730d 4499 int mask = vae1_tlbmask(env);
b4ab8ce9
PM		 4500
4501 if (tlb_force_broadcast(env)) {
527db2be
RH		 4502 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
4503 } else {
4504 tlb_flush_by_mmuidx(cs, mask);
b4ab8ce9 4505 }
b4ab8ce9
PM		 4506}
4507
90c19cdf 4508static int alle1_tlbmask(CPUARMState *env)
168aa23b 4509{
90c19cdf
RH		 4510 /*
4511 * Note that the 'ALL' scope must invalidate both stage 1 and
fd3ed969
PM		 4512 * stage 2 translations, whereas most other scopes only invalidate
4513 * stage 1 translations.
4514 */
fd3ed969 4515 if (arm_is_secure_below_el3(env)) {
452ef8cb
RH		 4516 return ARMMMUIdxBit_SE10_1 |
4517 ARMMMUIdxBit_SE10_1_PAN |
4518 ARMMMUIdxBit_SE10_0;
fd3ed969 4519 } else {
452ef8cb
RH		 4520 return ARMMMUIdxBit_E10_1 |
4521 ARMMMUIdxBit_E10_1_PAN |
4522 ARMMMUIdxBit_E10_0;
fd3ed969 4523 }
168aa23b
PM		 4524}
4525
85d0dc9f
RH		 4526static int e2_tlbmask(CPUARMState *env)
4527{
4528 /* TODO: ARMv8.4-SecEL2 */
452ef8cb
RH		 4529 return ARMMMUIdxBit_E20_0 |
4530 ARMMMUIdxBit_E20_2 |
4531 ARMMMUIdxBit_E20_2_PAN |
4532 ARMMMUIdxBit_E2;
85d0dc9f
RH		 4533}
4534
90c19cdf
RH		 4535static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
4536 uint64_t value)
4537{
4538 CPUState *cs = env_cpu(env);
4539 int mask = alle1_tlbmask(env);
4540
4541 tlb_flush_by_mmuidx(cs, mask);
4542}
4543
fd3ed969 4544static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
fa439fc5
PM		 4545 uint64_t value)
4546{
85d0dc9f
RH		 4547 CPUState *cs = env_cpu(env);
4548 int mask = e2_tlbmask(env);
fd3ed969 4549
85d0dc9f 4550 tlb_flush_by_mmuidx(cs, mask);
fd3ed969
PM		 4551}
4552
43efaa33
PM		 4553static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
4554 uint64_t value)
4555{
2fc0cc0e 4556 ARMCPU *cpu = env_archcpu(env);
43efaa33
PM		 4557 CPUState *cs = CPU(cpu);
4558
127b2b08 4559 tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3);
43efaa33
PM		 4560}
4561
fd3ed969
PM		 4562static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4563 uint64_t value)
4564{
29a0af61 4565 CPUState *cs = env_cpu(env);
90c19cdf
RH		 4566 int mask = alle1_tlbmask(env);
4567
4568 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
fa439fc5
PM		 4569}
4570
2bfb9d75
PM		 4571static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4572 uint64_t value)
4573{
29a0af61 4574 CPUState *cs = env_cpu(env);
85d0dc9f 4575 int mask = e2_tlbmask(env);
2bfb9d75 4576
85d0dc9f 4577 tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
2bfb9d75
PM		 4578}
4579
43efaa33
PM		 4580static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4581 uint64_t value)
4582{
29a0af61 4583 CPUState *cs = env_cpu(env);
43efaa33 4584
127b2b08 4585 tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3);
43efaa33
PM		 4586}
4587
fd3ed969
PM		 4588static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
4589 uint64_t value)
fa439fc5 4590{
fd3ed969
PM		 4591 /* Invalidate by VA, EL2
4592 * Currently handles both VAE2 and VALE2, since we don't support
4593 * flush-last-level-only.
4594 */
85d0dc9f
RH		 4595 CPUState *cs = env_cpu(env);
4596 int mask = e2_tlbmask(env);
fd3ed969
PM		 4597 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4598
85d0dc9f 4599 tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
fd3ed969
PM		 4600}
4601
43efaa33
PM		 4602static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
4603 uint64_t value)
4604{
4605 /* Invalidate by VA, EL3
4606 * Currently handles both VAE3 and VALE3, since we don't support
4607 * flush-last-level-only.
4608 */
2fc0cc0e 4609 ARMCPU *cpu = env_archcpu(env);
43efaa33
PM		 4610 CPUState *cs = CPU(cpu);
4611 uint64_t pageaddr = sextract64(value << 12, 0, 56);
4612
127b2b08 4613 tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3);
43efaa33
PM		 4614}
4615
fd3ed969
PM		 4616static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4617 uint64_t value)
4618{
90c19cdf
RH		 4619 CPUState *cs = env_cpu(env);
4620 int mask = vae1_tlbmask(env);
fa439fc5 4621 uint64_t pageaddr = sextract64(value << 12, 0, 56);
ea04dce7 4622 int bits = vae1_tlbbits(env, pageaddr);
fa439fc5 4623
ea04dce7 4624 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
fa439fc5
PM		 4625}
4626
b4ab8ce9
PM		 4627static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
4628 uint64_t value)
4629{
4630 /* Invalidate by VA, EL1&0 (AArch64 version).
4631 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4632 * since we don't support flush-for-specific-ASID-only or
4633 * flush-last-level-only.
4634 */
90c19cdf
RH		 4635 CPUState *cs = env_cpu(env);
4636 int mask = vae1_tlbmask(env);
b4ab8ce9 4637 uint64_t pageaddr = sextract64(value << 12, 0, 56);
ea04dce7 4638 int bits = vae1_tlbbits(env, pageaddr);
b4ab8ce9
PM		 4639
4640 if (tlb_force_broadcast(env)) {
ea04dce7 4641 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
527db2be 4642 } else {
ea04dce7 4643 tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits);
b4ab8ce9 4644 }
b4ab8ce9
PM		 4645}
4646
fd3ed969
PM		 4647static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4648 uint64_t value)
fa439fc5 4649{
29a0af61 4650 CPUState *cs = env_cpu(env);
fd3ed969 4651 uint64_t pageaddr = sextract64(value << 12, 0, 56);
ea04dce7 4652 int bits = tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr);
fa439fc5 4653
ea04dce7
RH		 4654 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
4655 ARMMMUIdxBit_E2, bits);
fa439fc5
PM		 4656}
4657
43efaa33
PM		 4658static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
4659 uint64_t value)
4660{
29a0af61 4661 CPUState *cs = env_cpu(env);
43efaa33 4662 uint64_t pageaddr = sextract64(value << 12, 0, 56);
ea04dce7 4663 int bits = tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr);
43efaa33 4664
ea04dce7
RH		 4665 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
4666 ARMMMUIdxBit_SE3, bits);
43efaa33
PM		 4667}
4668
3f208fd7
PM		 4669static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
4670 bool isread)
aca3f40b 4671{
4351cb72
RH		 4672 int cur_el = arm_current_el(env);
4673
4674 if (cur_el < 2) {
4675 uint64_t hcr = arm_hcr_el2_eff(env);
4676
4677 if (cur_el == 0) {
4678 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
4679 if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) {
4680 return CP_ACCESS_TRAP_EL2;
4681 }
4682 } else {
4683 if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
4684 return CP_ACCESS_TRAP;
4685 }
4686 if (hcr & HCR_TDZ) {
4687 return CP_ACCESS_TRAP_EL2;
4688 }
4689 }
4690 } else if (hcr & HCR_TDZ) {
4691 return CP_ACCESS_TRAP_EL2;
4692 }
aca3f40b
PM		 4693 }
4694 return CP_ACCESS_OK;
4695}
4696
4697static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
4698{
2fc0cc0e 4699 ARMCPU *cpu = env_archcpu(env);
aca3f40b
PM		 4700 int dzp_bit = 1 << 4;
4701
4702 /* DZP indicates whether DC ZVA access is allowed */
3f208fd7 4703 if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) {
aca3f40b
PM		 4704 dzp_bit = 0;
4705 }
4706 return cpu->dcz_blocksize | dzp_bit;
4707}
4708
3f208fd7
PM		 4709static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
4710 bool isread)
f502cfc2 4711{
cdcf1405 4712 if (!(env->pstate & PSTATE_SP)) {
f502cfc2
PM		 4713 /* Access to SP_EL0 is undefined if it's being used as
4714 * the stack pointer.
4715 */
4716 return CP_ACCESS_TRAP_UNCATEGORIZED;
4717 }
4718 return CP_ACCESS_OK;
4719}
4720
4721static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
4722{
4723 return env->pstate & PSTATE_SP;
4724}
4725
4726static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
4727{
4728 update_spsel(env, val);
4729}
4730
137feaa9
FA		 4731static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4732 uint64_t value)
4733{
2fc0cc0e 4734 ARMCPU *cpu = env_archcpu(env);
137feaa9 4735
f00faf13
RH		 4736 if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) {
4737 /* M bit is RAZ/WI for PMSA with no MPU implemented */
4738 value &= ~SCTLR_M;
4739 }
4740
4741 /* ??? Lots of these bits are not implemented. */
4742
4743 if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) {
4744 if (ri->opc1 == 6) { /* SCTLR_EL3 */
4745 value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA);
4746 } else {
4747 value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF |
4748 SCTLR_ATA0 | SCTLR_ATA);
4749 }
4750 }
4751
137feaa9
FA		 4752 if (raw_read(env, ri) == value) {
4753 /* Skip the TLB flush if nothing actually changed; Linux likes
4754 * to do a lot of pointless SCTLR writes.
4755 */
4756 return;
4757 }
4758
4759 raw_write(env, ri, value);
f00faf13 4760
137feaa9 4761 /* This may enable/disable the MMU, so do a TLB flush. */
d10eb08f 4762 tlb_flush(CPU(cpu));
2e5dcf36
RH		 4763
4764 if (ri->type & ARM_CP_SUPPRESS_TB_END) {
4765 /*
4766 * Normally we would always end the TB on an SCTLR write; see the
4767 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
4768 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
4769 * of hflags from the translator, so do it here.
4770 */
4771 arm_rebuild_hflags(env);
4772 }
137feaa9
FA		 4773}
4774
3f208fd7
PM		 4775static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
4776 bool isread)
03fbf20f
PM		 4777{
4778 if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) {
f2cae609 4779 return CP_ACCESS_TRAP_FP_EL2;
03fbf20f
PM		 4780 }
4781 if (env->cp15.cptr_el[3] & CPTR_TFP) {
f2cae609 4782 return CP_ACCESS_TRAP_FP_EL3;
03fbf20f
PM		 4783 }
4784 return CP_ACCESS_OK;
4785}
4786
a8d64e73
PM		 4787static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4788 uint64_t value)
4789{
4790 env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
4791}
4792
b0d2b7d0
PM		 4793static const ARMCPRegInfo v8_cp_reginfo[] = {
4794 /* Minimal set of EL0-visible registers. This will need to be expanded
4795 * significantly for system emulation of AArch64 CPUs.
4796 */
4797 { .name = "NZCV", .state = ARM_CP_STATE_AA64,
4798 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
4799 .access = PL0_RW, .type = ARM_CP_NZCV },
c2b820fe
PM		 4800 { .name = "DAIF", .state = ARM_CP_STATE_AA64,
4801 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
7a0e58fa 4802 .type = ARM_CP_NO_RAW,
c2b820fe
PM		 4803 .access = PL0_RW, .accessfn = aa64_daif_access,
4804 .fieldoffset = offsetof(CPUARMState, daif),
4805 .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
b0d2b7d0
PM		 4806 { .name = "FPCR", .state = ARM_CP_STATE_AA64,
4807 .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
b916c9c3 4808 .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END,
fe03d45f 4809 .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
b0d2b7d0
PM		 4810 { .name = "FPSR", .state = ARM_CP_STATE_AA64,
4811 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
b916c9c3 4812 .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END,
fe03d45f 4813 .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
b0d2b7d0
PM		 4814 { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
4815 .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
7a0e58fa 4816 .access = PL0_R, .type = ARM_CP_NO_RAW,
aca3f40b
PM		 4817 .readfn = aa64_dczid_read },
4818 { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
4819 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
4820 .access = PL0_W, .type = ARM_CP_DC_ZVA,
4821#ifndef CONFIG_USER_ONLY
4822 /* Avoid overhead of an access check that always passes in user-mode */
4823 .accessfn = aa64_zva_access,
4824#endif
4825 },
0eef9d98
PM		 4826 { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
4827 .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
4828 .access = PL1_R, .type = ARM_CP_CURRENTEL },
8af35c37
PM		 4829 /* Cache ops: all NOPs since we don't emulate caches */
4830 { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
4831 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
38262d8a
RH		 4832 .access = PL1_W, .type = ARM_CP_NOP,
4833 .accessfn = aa64_cacheop_pou_access },
8af35c37
PM		 4834 { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
4835 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
38262d8a
RH		 4836 .access = PL1_W, .type = ARM_CP_NOP,
4837 .accessfn = aa64_cacheop_pou_access },
8af35c37
PM		 4838 { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
4839 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
4840 .access = PL0_W, .type = ARM_CP_NOP,
38262d8a 4841 .accessfn = aa64_cacheop_pou_access },
8af35c37
PM		 4842 { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
4843 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
1bed4d2e
RH		 4844 .access = PL1_W, .accessfn = aa64_cacheop_poc_access,
4845 .type = ARM_CP_NOP },
8af35c37
PM		 4846 { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
4847 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
1803d271 4848 .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
8af35c37
PM		 4849 { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
4850 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
4851 .access = PL0_W, .type = ARM_CP_NOP,
1bed4d2e 4852 .accessfn = aa64_cacheop_poc_access },
8af35c37
PM		 4853 { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
4854 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
1803d271 4855 .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
8af35c37
PM		 4856 { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
4857 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
4858 .access = PL0_W, .type = ARM_CP_NOP,
38262d8a 4859 .accessfn = aa64_cacheop_pou_access },
8af35c37
PM		 4860 { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
4861 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
4862 .access = PL0_W, .type = ARM_CP_NOP,
1bed4d2e 4863 .accessfn = aa64_cacheop_poc_access },
8af35c37
PM		 4864 { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
4865 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
1803d271 4866 .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
168aa23b
PM		 4867 /* TLBI operations */
4868 { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
6ab9f499 4869 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
30881b73 4870 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
fd3ed969 4871 .writefn = tlbi_aa64_vmalle1is_write },
168aa23b 4872 { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
6ab9f499 4873 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
30881b73 4874 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
fd3ed969 4875 .writefn = tlbi_aa64_vae1is_write },
168aa23b 4876 { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
6ab9f499 4877 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
30881b73 4878 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
fd3ed969 4879 .writefn = tlbi_aa64_vmalle1is_write },
168aa23b 4880 { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
6ab9f499 4881 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
30881b73 4882 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
fd3ed969 4883 .writefn = tlbi_aa64_vae1is_write },
168aa23b 4884 { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
6ab9f499 4885 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
30881b73 4886 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
fd3ed969 4887 .writefn = tlbi_aa64_vae1is_write },
168aa23b 4888 { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
6ab9f499 4889 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
30881b73 4890 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
fd3ed969 4891 .writefn = tlbi_aa64_vae1is_write },
168aa23b 4892 { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
6ab9f499 4893 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
30881b73 4894 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
fd3ed969 4895 .writefn = tlbi_aa64_vmalle1_write },
168aa23b 4896 { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
6ab9f499 4897 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
30881b73 4898 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
fd3ed969 4899 .writefn = tlbi_aa64_vae1_write },
168aa23b 4900 { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
6ab9f499 4901 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
30881b73 4902 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
fd3ed969 4903 .writefn = tlbi_aa64_vmalle1_write },
168aa23b 4904 { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
6ab9f499 4905 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
30881b73 4906 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
fd3ed969 4907 .writefn = tlbi_aa64_vae1_write },
168aa23b 4908 { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
6ab9f499 4909 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
30881b73 4910 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
fd3ed969 4911 .writefn = tlbi_aa64_vae1_write },
168aa23b 4912 { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
6ab9f499 4913 .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
30881b73 4914 .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
fd3ed969 4915 .writefn = tlbi_aa64_vae1_write },
cea66e91
PM		 4916 { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
4917 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
bf05340c 4918 .access = PL2_W, .type = ARM_CP_NOP },
cea66e91
PM		 4919 { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
4920 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
bf05340c 4921 .access = PL2_W, .type = ARM_CP_NOP },
83ddf975
PM		 4922 { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
4923 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
4924 .access = PL2_W, .type = ARM_CP_NO_RAW,
fd3ed969 4925 .writefn = tlbi_aa64_alle1is_write },
43efaa33
PM		 4926 { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
4927 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
4928 .access = PL2_W, .type = ARM_CP_NO_RAW,
4929 .writefn = tlbi_aa64_alle1is_write },
cea66e91
PM		 4930 { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
4931 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
bf05340c 4932 .access = PL2_W, .type = ARM_CP_NOP },
cea66e91
PM		 4933 { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
4934 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
bf05340c 4935 .access = PL2_W, .type = ARM_CP_NOP },
83ddf975
PM		 4936 { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
4937 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
4938 .access = PL2_W, .type = ARM_CP_NO_RAW,
fd3ed969 4939 .writefn = tlbi_aa64_alle1_write },
43efaa33
PM		 4940 { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
4941 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
4942 .access = PL2_W, .type = ARM_CP_NO_RAW,
4943 .writefn = tlbi_aa64_alle1is_write },
19525524
PM		 4944#ifndef CONFIG_USER_ONLY
4945 /* 64 bit address translation operations */
4946 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
4947 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
0710b2fa
PM		 4948 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4949 .writefn = ats_write64 },
19525524
PM		 4950 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
4951 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
0710b2fa
PM		 4952 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4953 .writefn = ats_write64 },
19525524
PM		 4954 { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
4955 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
0710b2fa
PM		 4956 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4957 .writefn = ats_write64 },
19525524
PM		 4958 { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
4959 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
0710b2fa
PM		 4960 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4961 .writefn = ats_write64 },
2a47df95 4962 { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
7a379c7e 4963 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
0710b2fa
PM		 4964 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4965 .writefn = ats_write64 },
2a47df95 4966 { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
7a379c7e 4967 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5,
0710b2fa
PM		 4968 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4969 .writefn = ats_write64 },
2a47df95 4970 { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
7a379c7e 4971 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6,
0710b2fa
PM		 4972 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4973 .writefn = ats_write64 },
2a47df95 4974 { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
7a379c7e 4975 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
0710b2fa
PM		 4976 .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4977 .writefn = ats_write64 },
2a47df95
PM		 4978 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
4979 { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
4980 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
0710b2fa
PM		 4981 .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4982 .writefn = ats_write64 },
2a47df95
PM		 4983 { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
4984 .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
0710b2fa
PM		 4985 .access = PL3_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
4986 .writefn = ats_write64 },
c96fc9b5
EI		 4987 { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
4988 .type = ARM_CP_ALIAS,
4989 .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
4990 .access = PL1_RW, .resetvalue = 0,
4991 .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
4992 .writefn = par_write },
19525524 4993#endif
995939a6 4994 /* TLB invalidate last level of translation table walk */
9449fdf6 4995 { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
30881b73
RH		 4996 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
4997 .writefn = tlbimva_is_write },
9449fdf6 4998 { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
30881b73 4999 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
fa439fc5 5000 .writefn = tlbimvaa_is_write },
9449fdf6 5001 { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
30881b73
RH		 5002 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
5003 .writefn = tlbimva_write },
9449fdf6 5004 { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
30881b73
RH		 5005 .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
5006 .writefn = tlbimvaa_write },
541ef8c2
SS		 5007 { .name = "TLBIMVALH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
5008 .type = ARM_CP_NO_RAW, .access = PL2_W,
5009 .writefn = tlbimva_hyp_write },
5010 { .name = "TLBIMVALHIS",
5011 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
5012 .type = ARM_CP_NO_RAW, .access = PL2_W,
5013 .writefn = tlbimva_hyp_is_write },
5014 { .name = "TLBIIPAS2",
5015 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
bf05340c 5016 .type = ARM_CP_NOP, .access = PL2_W },
541ef8c2
SS		 5017 { .name = "TLBIIPAS2IS",
5018 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
bf05340c 5019 .type = ARM_CP_NOP, .access = PL2_W },
541ef8c2
SS		 5020 { .name = "TLBIIPAS2L",
5021 .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
bf05340c 5022 .type = ARM_CP_NOP, .access = PL2_W },
541ef8c2
SS		 5023 { .name = "TLBIIPAS2LIS",
5024 .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
bf05340c 5025 .type = ARM_CP_NOP, .access = PL2_W },
9449fdf6
PM		 5026 /* 32 bit cache operations */
5027 { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
38262d8a 5028 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
9449fdf6
PM		 5029 { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
5030 .type = ARM_CP_NOP, .access = PL1_W },
5031 { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
38262d8a 5032 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
9449fdf6 5033 { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
38262d8a 5034 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
9449fdf6
PM		 5035 { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
5036 .type = ARM_CP_NOP, .access = PL1_W },
5037 { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
5038 .type = ARM_CP_NOP, .access = PL1_W },
5039 { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
1bed4d2e 5040 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access },
9449fdf6 5041 { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
1803d271 5042 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
9449fdf6 5043 { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
1bed4d2e 5044 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access },
9449fdf6 5045 { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
1803d271 5046 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
9449fdf6 5047 { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
38262d8a 5048 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
9449fdf6 5049 { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
1bed4d2e 5050 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access },
9449fdf6 5051 { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
1803d271 5052 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
9449fdf6 5053 /* MMU Domain access control / MPU write buffer control */
0c17d68c 5054 { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
84929218 5055 .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,
0c17d68c
FA		 5056 .writefn = dacr_write, .raw_writefn = raw_write,
5057 .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
5058 offsetoflow32(CPUARMState, cp15.dacr_ns) } },
a0618a19 5059 { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
7a0e58fa 5060 .type = ARM_CP_ALIAS,
a0618a19 5061 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
6947f059
EI		 5062 .access = PL1_RW,
5063 .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
a65f1de9 5064 { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
7a0e58fa 5065 .type = ARM_CP_ALIAS,
a65f1de9 5066 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
99a99c1f
SB		 5067 .access = PL1_RW,
5068 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
f502cfc2
PM		 5069 /* We rely on the access checks not allowing the guest to write to the
5070 * state field when SPSel indicates that it's being used as the stack
5071 * pointer.
5072 */
5073 { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
5074 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
5075 .access = PL1_RW, .accessfn = sp_el0_access,
7a0e58fa 5076 .type = ARM_CP_ALIAS,
f502cfc2 5077 .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
884b4dee
GB		 5078 { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
5079 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
7a0e58fa 5080 .access = PL2_RW, .type = ARM_CP_ALIAS,
884b4dee 5081 .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
f502cfc2
PM		 5082 { .name = "SPSel", .state = ARM_CP_STATE_AA64,
5083 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
7a0e58fa 5084 .type = ARM_CP_NO_RAW,
f502cfc2 5085 .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
03fbf20f
PM		 5086 { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
5087 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
5088 .type = ARM_CP_ALIAS,
5089 .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]),
5090 .access = PL2_RW, .accessfn = fpexc32_access },
6a43e0b6
PM		 5091 { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
5092 .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
5093 .access = PL2_RW, .resetvalue = 0,
5094 .writefn = dacr_write, .raw_writefn = raw_write,
5095 .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
5096 { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
5097 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
5098 .access = PL2_RW, .resetvalue = 0,
5099 .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
5100 { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
5101 .type = ARM_CP_ALIAS,
5102 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
5103 .access = PL2_RW,
5104 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) },
5105 { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
5106 .type = ARM_CP_ALIAS,
5107 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
5108 .access = PL2_RW,
5109 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) },
5110 { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
5111 .type = ARM_CP_ALIAS,
5112 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
5113 .access = PL2_RW,
5114 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) },
5115 { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
5116 .type = ARM_CP_ALIAS,
5117 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
5118 .access = PL2_RW,
5119 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
a8d64e73
PM		 5120 { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
5121 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
5122 .resetvalue = 0,
5123 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
5124 { .name = "SDCR", .type = ARM_CP_ALIAS,
5125 .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
5126 .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
5127 .writefn = sdcr_write,
5128 .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
b0d2b7d0
PM		 5129 REGINFO_SENTINEL
5130};
5131
d42e3c26 5132/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
4771cd01 5133static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
d79e0c06 5134 { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
d42e3c26
EI		 5135 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
5136 .access = PL2_RW,
5137 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
ce4afed8 5138 { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
f149e3e8
EI		 5139 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
5140 .access = PL2_RW,
ce4afed8 5141 .type = ARM_CP_CONST, .resetvalue = 0 },
831a2fca
PM		 5142 { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
5143 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
5144 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
68e78e33
PM		 5145 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
5146 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
5147 .access = PL2_RW,
5148 .type = ARM_CP_CONST, .resetvalue = 0 },
c6f19164
GB		 5149 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
5150 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
5151 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
95f949ac
EI		 5152 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
5153 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
5154 .access = PL2_RW, .type = ARM_CP_CONST,
5155 .resetvalue = 0 },
5156 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
b5ede85b 5157 .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
95f949ac 5158 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2179ef95
PM		 5159 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
5160 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
5161 .access = PL2_RW, .type = ARM_CP_CONST,
5162 .resetvalue = 0 },
55b53c71 5163 { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
b5ede85b 5164 .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
2179ef95
PM		 5165 .access = PL2_RW, .type = ARM_CP_CONST,
5166 .resetvalue = 0 },
37cd6c24
PM		 5167 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
5168 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
5169 .access = PL2_RW, .type = ARM_CP_CONST,
5170 .resetvalue = 0 },
5171 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
5172 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
5173 .access = PL2_RW, .type = ARM_CP_CONST,
5174 .resetvalue = 0 },
06ec4c8c
EI		 5175 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
5176 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
5177 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
68e9c2fe
EI		 5178 { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
5179 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
93dd1e61 5180 .access = PL2_RW, .accessfn = access_el3_aa32ns,
68e9c2fe 5181 .type = ARM_CP_CONST, .resetvalue = 0 },
b698e9cf
EI		 5182 { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
5183 .cp = 15, .opc1 = 6, .crm = 2,
5184 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5185 .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
5186 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
5187 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
5188 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
b9cb5323
EI		 5189 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
5190 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
5191 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
ff05f37b
EI		 5192 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
5193 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
5194 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
a57633c0
EI		 5195 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
5196 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
5197 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5198 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
5199 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
5200 .resetvalue = 0 },
0b6440af
EI		 5201 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
5202 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
5203 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
edac4d8a
EI		 5204 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
5205 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
5206 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5207 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
5208 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
5209 .resetvalue = 0 },
b0e66d95
EI		 5210 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
5211 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
5212 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5213 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
5214 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
5215 .resetvalue = 0 },
5216 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
5217 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
5218 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5219 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
5220 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
5221 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
14cc7b54
SF		 5222 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
5223 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
d6c8cf81
PM		 5224 .access = PL2_RW, .accessfn = access_tda,
5225 .type = ARM_CP_CONST, .resetvalue = 0 },
59e05530
EI		 5226 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
5227 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
93dd1e61 5228 .access = PL2_RW, .accessfn = access_el3_aa32ns,
59e05530 5229 .type = ARM_CP_CONST, .resetvalue = 0 },
2a5a9abd
AF		 5230 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
5231 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
5232 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
cba517c3
PM		 5233 { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
5234 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
5235 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
5236 { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
5237 .type = ARM_CP_CONST,
5238 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
5239 .access = PL2_RW, .resetvalue = 0 },
d42e3c26
EI		 5240 REGINFO_SENTINEL
5241};
5242
ce4afed8
PM		 5243/* Ditto, but for registers which exist in ARMv8 but not v7 */
5244static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
5245 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
5246 .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
5247 .access = PL2_RW,
5248 .type = ARM_CP_CONST, .resetvalue = 0 },
5249 REGINFO_SENTINEL
5250};
5251
d1fb4da2 5252static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
f149e3e8 5253{
2fc0cc0e 5254 ARMCPU *cpu = env_archcpu(env);
d1fb4da2
RH		 5255
5256 if (arm_feature(env, ARM_FEATURE_V8)) {
5257 valid_mask |= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5258 } else {
5259 valid_mask |= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5260 }
f149e3e8
EI		 5261
5262 if (arm_feature(env, ARM_FEATURE_EL3)) {
5263 valid_mask &= ~HCR_HCD;
77077a83
JK		 5264 } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
5265 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5266 * However, if we're using the SMC PSCI conduit then QEMU is
5267 * effectively acting like EL3 firmware and so the guest at
5268 * EL2 should retain the ability to prevent EL1 from being
5269 * able to make SMC calls into the ersatz firmware, so in
5270 * that case HCR.TSC should be read/write.
5271 */
f149e3e8
EI		 5272 valid_mask &= ~HCR_TSC;
5273 }
d1fb4da2
RH		 5274
5275 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
5276 if (cpu_isar_feature(aa64_vh, cpu)) {
5277 valid_mask |= HCR_E2H;
5278 }
5279 if (cpu_isar_feature(aa64_lor, cpu)) {
5280 valid_mask |= HCR_TLOR;
5281 }
5282 if (cpu_isar_feature(aa64_pauth, cpu)) {
5283 valid_mask |= HCR_API | HCR_APK;
5284 }
8ddb300b
RH		 5285 if (cpu_isar_feature(aa64_mte, cpu)) {
5286 valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5;
5287 }
ef682cdb 5288 }
f149e3e8
EI		 5289
5290 /* Clear RES0 bits. */
5291 value &= valid_mask;
5292
8ddb300b
RH		 5293 /*
5294 * These bits change the MMU setup:
f149e3e8
EI		 5295 * HCR_VM enables stage 2 translation
5296 * HCR_PTW forbids certain page-table setups
8ddb300b
RH		 5297 * HCR_DC disables stage1 and enables stage2 translation
5298 * HCR_DCT enables tagging on (disabled) stage1 translation
f149e3e8 5299 */
8ddb300b 5300 if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT)) {
d10eb08f 5301 tlb_flush(CPU(cpu));
f149e3e8 5302 }
ce4afed8 5303 env->cp15.hcr_el2 = value;
89430fc6
PM		 5304
5305 /*
5306 * Updates to VI and VF require us to update the status of
5307 * virtual interrupts, which are the logical OR of these bits
5308 * and the state of the input lines from the GIC. (This requires
5309 * that we have the iothread lock, which is done by marking the
5310 * reginfo structs as ARM_CP_IO.)
5311 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5312 * possible for it to be taken immediately, because VIRQ and
5313 * VFIQ are masked unless running at EL0 or EL1, and HCR
5314 * can only be written at EL2.
5315 */
5316 g_assert(qemu_mutex_iothread_locked());
5317 arm_cpu_update_virq(cpu);
5318 arm_cpu_update_vfiq(cpu);
ce4afed8
PM		 5319}
5320
d1fb4da2
RH		 5321static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
5322{
5323 do_hcr_write(env, value, 0);
5324}
5325
ce4afed8
PM		 5326static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri,
5327 uint64_t value)
5328{
5329 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5330 value = deposit64(env->cp15.hcr_el2, 32, 32, value);
d1fb4da2 5331 do_hcr_write(env, value, MAKE_64BIT_MASK(0, 32));
ce4afed8
PM		 5332}
5333
5334static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri,
5335 uint64_t value)
5336{
5337 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5338 value = deposit64(env->cp15.hcr_el2, 0, 32, value);
d1fb4da2 5339 do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32));
f149e3e8
EI		 5340}
5341
f7778444
RH		 5342/*
5343 * Return the effective value of HCR_EL2.
5344 * Bits that are not included here:
5345 * RW (read from SCR_EL3.RW as needed)
5346 */
5347uint64_t arm_hcr_el2_eff(CPUARMState *env)
5348{
5349 uint64_t ret = env->cp15.hcr_el2;
5350
5351 if (arm_is_secure_below_el3(env)) {
5352 /*
5353 * "This register has no effect if EL2 is not enabled in the
5354 * current Security state". This is ARMv8.4-SecEL2 speak for
5355 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5356 *
5357 * Prior to that, the language was "In an implementation that
5358 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5359 * as if this field is 0 for all purposes other than a direct
5360 * read or write access of HCR_EL2". With lots of enumeration
5361 * on a per-field basis. In current QEMU, this is condition
5362 * is arm_is_secure_below_el3.
5363 *
5364 * Since the v8.4 language applies to the entire register, and
5365 * appears to be backward compatible, use that.
5366 */
4990e1d3
RH		 5367 return 0;
5368 }
5369
5370 /*
5371 * For a cpu that supports both aarch64 and aarch32, we can set bits
5372 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5373 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5374 */
5375 if (!arm_el_is_aa64(env, 2)) {
5376 uint64_t aa32_valid;
5377
5378 /*
5379 * These bits are up-to-date as of ARMv8.6.
5380 * For HCR, it's easiest to list just the 2 bits that are invalid.
5381 * For HCR2, list those that are valid.
5382 */
5383 aa32_valid = MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ);
5384 aa32_valid |= (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNCE |
5385 HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS);
5386 ret &= aa32_valid;
5387 }
5388
5389 if (ret & HCR_TGE) {
5390 /* These bits are up-to-date as of ARMv8.6. */
f7778444
RH		 5391 if (ret & HCR_E2H) {
5392 ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO |
5393 HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE |
5394 HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU |
4990e1d3
RH		 5395 HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE |
5396 HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT |
5397 HCR_TTLBIS | HCR_TTLBOS | HCR_TID5);
f7778444
RH		 5398 } else {
5399 ret |= HCR_FMO | HCR_IMO | HCR_AMO;
5400 }
5401 ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE |
5402 HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR |
5403 HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM |
5404 HCR_TLOR);
5405 }
5406
5407 return ret;
5408}
5409
fc1120a7
PM		 5410static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
5411 uint64_t value)
5412{
5413 /*
5414 * For A-profile AArch32 EL3, if NSACR.CP10
5415 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5416 */
5417 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
5418 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
5419 value &= ~(0x3 << 10);
5420 value |= env->cp15.cptr_el[2] & (0x3 << 10);
5421 }
5422 env->cp15.cptr_el[2] = value;
5423}
5424
5425static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri)
5426{
5427 /*
5428 * For A-profile AArch32 EL3, if NSACR.CP10
5429 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
5430 */
5431 uint64_t value = env->cp15.cptr_el[2];
5432
5433 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
5434 !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) {
5435 value |= 0x3 << 10;
5436 }
5437 return value;
5438}
5439
4771cd01 5440static const ARMCPRegInfo el2_cp_reginfo[] = {
f149e3e8 5441 { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
89430fc6 5442 .type = ARM_CP_IO,
f149e3e8
EI		 5443 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
5444 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
c624ea0f 5445 .writefn = hcr_write },
ce4afed8 5446 { .name = "HCR", .state = ARM_CP_STATE_AA32,
89430fc6 5447 .type = ARM_CP_ALIAS | ARM_CP_IO,
ce4afed8
PM		 5448 .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
5449 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
c624ea0f 5450 .writefn = hcr_writelow },
831a2fca
PM		 5451 { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
5452 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
5453 .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3b685ba7 5454 { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
7a0e58fa 5455 .type = ARM_CP_ALIAS,
3b685ba7
EI		 5456 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
5457 .access = PL2_RW,
5458 .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
68e78e33 5459 { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
f2c30f42
EI		 5460 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
5461 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
cba517c3 5462 { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
63b60551
EI		 5463 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
5464 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
cba517c3
PM		 5465 { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
5466 .type = ARM_CP_ALIAS,
5467 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
5468 .access = PL2_RW,
5469 .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) },
3b685ba7 5470 { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
7a0e58fa 5471 .type = ARM_CP_ALIAS,
3b685ba7 5472 .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
99a99c1f
SB		 5473 .access = PL2_RW,
5474 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) },
d79e0c06 5475 { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
d42e3c26
EI		 5476 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
5477 .access = PL2_RW, .writefn = vbar_write,
5478 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
5479 .resetvalue = 0 },
884b4dee
GB		 5480 { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
5481 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
7a0e58fa 5482 .access = PL3_RW, .type = ARM_CP_ALIAS,
884b4dee 5483 .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
c6f19164
GB		 5484 { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
5485 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
5486 .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
fc1120a7
PM		 5487 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]),
5488 .readfn = cptr_el2_read, .writefn = cptr_el2_write },
95f949ac
EI		 5489 { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
5490 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
5491 .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
5492 .resetvalue = 0 },
5493 { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
b5ede85b 5494 .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
95f949ac
EI		 5495 .access = PL2_RW, .type = ARM_CP_ALIAS,
5496 .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
2179ef95
PM		 5497 { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
5498 .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
5499 .access = PL2_RW, .type = ARM_CP_CONST,
5500 .resetvalue = 0 },
5501 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
55b53c71 5502 { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
b5ede85b 5503 .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
2179ef95
PM		 5504 .access = PL2_RW, .type = ARM_CP_CONST,
5505 .resetvalue = 0 },
37cd6c24
PM		 5506 { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
5507 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
5508 .access = PL2_RW, .type = ARM_CP_CONST,
5509 .resetvalue = 0 },
5510 { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
5511 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
5512 .access = PL2_RW, .type = ARM_CP_CONST,
5513 .resetvalue = 0 },
06ec4c8c
EI		 5514 { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
5515 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
d06dc933
RH		 5516 .access = PL2_RW, .writefn = vmsa_tcr_el12_write,
5517 /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */
06ec4c8c 5518 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
68e9c2fe
EI		 5519 { .name = "VTCR", .state = ARM_CP_STATE_AA32,
5520 .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
bf06c112 5521 .type = ARM_CP_ALIAS,
68e9c2fe
EI		 5522 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5523 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
5524 { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
5525 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
bf06c112
PM		 5526 .access = PL2_RW,
5527 /* no .writefn needed as this can't cause an ASID change;
5528 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
5529 */
68e9c2fe 5530 .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
b698e9cf
EI		 5531 { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
5532 .cp = 15, .opc1 = 6, .crm = 2,
5533 .type = ARM_CP_64BIT | ARM_CP_ALIAS,
5534 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5535 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
5536 .writefn = vttbr_write },
5537 { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
5538 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
5539 .access = PL2_RW, .writefn = vttbr_write,
5540 .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
b9cb5323
EI		 5541 { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
5542 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
5543 .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
5544 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
ff05f37b
EI		 5545 { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
5546 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
5547 .access = PL2_RW, .resetvalue = 0,
5548 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
a57633c0
EI		 5549 { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
5550 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
ed30da8e 5551 .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write,
a57633c0
EI		 5552 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
5553 { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
5554 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
a57633c0 5555 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
541ef8c2
SS		 5556 { .name = "TLBIALLNSNH",
5557 .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
5558 .type = ARM_CP_NO_RAW, .access = PL2_W,
5559 .writefn = tlbiall_nsnh_write },
5560 { .name = "TLBIALLNSNHIS",
5561 .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
5562 .type = ARM_CP_NO_RAW, .access = PL2_W,
5563 .writefn = tlbiall_nsnh_is_write },
5564 { .name = "TLBIALLH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
5565 .type = ARM_CP_NO_RAW, .access = PL2_W,
5566 .writefn = tlbiall_hyp_write },
5567 { .name = "TLBIALLHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
5568 .type = ARM_CP_NO_RAW, .access = PL2_W,
5569 .writefn = tlbiall_hyp_is_write },
5570 { .name = "TLBIMVAH", .cp = 15, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
5571 .type = ARM_CP_NO_RAW, .access = PL2_W,
5572 .writefn = tlbimva_hyp_write },
5573 { .name = "TLBIMVAHIS", .cp = 15, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
5574 .type = ARM_CP_NO_RAW, .access = PL2_W,
5575 .writefn = tlbimva_hyp_is_write },
51da9014
EI		 5576 { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
5577 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
5578 .type = ARM_CP_NO_RAW, .access = PL2_W,
fd3ed969 5579 .writefn = tlbi_aa64_alle2_write },
8742d49d
EI		 5580 { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
5581 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
5582 .type = ARM_CP_NO_RAW, .access = PL2_W,
fd3ed969 5583 .writefn = tlbi_aa64_vae2_write },
2bfb9d75
PM		 5584 { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
5585 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
5586 .access = PL2_W, .type = ARM_CP_NO_RAW,
5587 .writefn = tlbi_aa64_vae2_write },
5588 { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
5589 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
5590 .access = PL2_W, .type = ARM_CP_NO_RAW,
5591 .writefn = tlbi_aa64_alle2is_write },
8742d49d
EI		 5592 { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
5593 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
5594 .type = ARM_CP_NO_RAW, .access = PL2_W,
fd3ed969 5595 .writefn = tlbi_aa64_vae2is_write },
2bfb9d75
PM		 5596 { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
5597 .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
5598 .access = PL2_W, .type = ARM_CP_NO_RAW,
5599 .writefn = tlbi_aa64_vae2is_write },
edac4d8a 5600#ifndef CONFIG_USER_ONLY
2a47df95
PM		 5601 /* Unlike the other EL2-related AT operations, these must
5602 * UNDEF from EL3 if EL2 is not implemented, which is why we
5603 * define them here rather than with the rest of the AT ops.
5604 */
5605 { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
5606 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
5607 .access = PL2_W, .accessfn = at_s1e2_access,
0710b2fa 5608 .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
2a47df95
PM		 5609 { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
5610 .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
5611 .access = PL2_W, .accessfn = at_s1e2_access,
0710b2fa 5612 .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
14db7fe0
PM		 5613 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
5614 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
5615 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
5616 * to behave as if SCR.NS was 1.
5617 */
5618 { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
5619 .access = PL2_W,
0710b2fa 5620 .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
14db7fe0
PM		 5621 { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
5622 .access = PL2_W,
0710b2fa 5623 .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
0b6440af
EI		 5624 { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
5625 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
5626 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
5627 * reset values as IMPDEF. We choose to reset to 3 to comply with
5628 * both ARMv7 and ARMv8.
5629 */
5630 .access = PL2_RW, .resetvalue = 3,
5631 .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
edac4d8a
EI		 5632 { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
5633 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
5634 .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
5635 .writefn = gt_cntvoff_write,
5636 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
5637 { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
5638 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
5639 .writefn = gt_cntvoff_write,
5640 .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
b0e66d95
EI		 5641 { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
5642 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
5643 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
5644 .type = ARM_CP_IO, .access = PL2_RW,
5645 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
5646 { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
5647 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
5648 .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO,
5649 .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
5650 { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
5651 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
d44ec156 5652 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
b0e66d95
EI		 5653 .resetfn = gt_hyp_timer_reset,
5654 .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write },
5655 { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
5656 .type = ARM_CP_IO,
5657 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
5658 .access = PL2_RW,
5659 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl),
5660 .resetvalue = 0,
5661 .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
edac4d8a 5662#endif
14cc7b54
SF		 5663 /* The only field of MDCR_EL2 that has a defined architectural reset value
5664 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
5ecdd3e4 5665 * don't implement any PMU event counters, so using zero as a reset
14cc7b54
SF		 5666 * value for MDCR_EL2 is okay
5667 */
5668 { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
5669 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
5670 .access = PL2_RW, .resetvalue = 0,
5671 .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
59e05530
EI		 5672 { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
5673 .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
5674 .access = PL2_RW, .accessfn = access_el3_aa32ns,
5675 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
5676 { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
5677 .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
5678 .access = PL2_RW,
5679 .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
2a5a9abd
AF		 5680 { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
5681 .cp = 15, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
5682 .access = PL2_RW,
5683 .fieldoffset = offsetof(CPUARMState, cp15.hstr_el2) },
3b685ba7
EI		 5684 REGINFO_SENTINEL
5685};
5686
ce4afed8
PM		 5687static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
5688 { .name = "HCR2", .state = ARM_CP_STATE_AA32,
89430fc6 5689 .type = ARM_CP_ALIAS | ARM_CP_IO,
ce4afed8
PM		 5690 .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
5691 .access = PL2_RW,
5692 .fieldoffset = offsetofhigh32(CPUARMState, cp15.hcr_el2),
5693 .writefn = hcr_writehigh },
5694 REGINFO_SENTINEL
5695};
5696
2f027fc5
PM		 5697static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
5698 bool isread)
5699{
5700 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
5701 * At Secure EL1 it traps to EL3.
5702 */
5703 if (arm_current_el(env) == 3) {
5704 return CP_ACCESS_OK;
5705 }
5706 if (arm_is_secure_below_el3(env)) {
5707 return CP_ACCESS_TRAP_EL3;
5708 }
5709 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
5710 if (isread) {
5711 return CP_ACCESS_OK;
5712 }
5713 return CP_ACCESS_TRAP_UNCATEGORIZED;
5714}
5715
60fb1a87
GB		 5716static const ARMCPRegInfo el3_cp_reginfo[] = {
5717 { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
5718 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
5719 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
5720 .resetvalue = 0, .writefn = scr_write },
f80741d1 5721 { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL,
60fb1a87 5722 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
efe4a274
PM		 5723 .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
5724 .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
b061a82b 5725 .writefn = scr_write },
60fb1a87
GB		 5726 { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
5727 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
5728 .access = PL3_RW, .resetvalue = 0,
5729 .fieldoffset = offsetof(CPUARMState, cp15.sder) },
5730 { .name = "SDER",
5731 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
5732 .access = PL3_RW, .resetvalue = 0,
5733 .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
60fb1a87 5734 { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
efe4a274
PM		 5735 .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
5736 .writefn = vbar_write, .resetvalue = 0,
60fb1a87 5737 .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
7dd8c9af
FA		 5738 { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
5739 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
f478847f 5740 .access = PL3_RW, .resetvalue = 0,
7dd8c9af 5741 .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
11f136ee
FA		 5742 { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
5743 .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
6459b94c
PM		 5744 .access = PL3_RW,
5745 /* no .writefn needed as this can't cause an ASID change;
811595a2
PM		 5746 * we must provide a .raw_writefn and .resetfn because we handle
5747 * reset and migration for the AArch32 TTBCR(S), which might be
5748 * using mask and base_mask.
6459b94c 5749 */
811595a2 5750 .resetfn = vmsa_ttbcr_reset, .raw_writefn = vmsa_ttbcr_raw_write,
11f136ee 5751 .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
81547d66 5752 { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
7a0e58fa 5753 .type = ARM_CP_ALIAS,
81547d66
EI		 5754 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
5755 .access = PL3_RW,
5756 .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
f2c30f42 5757 { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
f2c30f42
EI		 5758 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
5759 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
63b60551
EI		 5760 { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
5761 .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
5762 .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
81547d66 5763 { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
7a0e58fa 5764 .type = ARM_CP_ALIAS,
81547d66 5765 .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
99a99c1f
SB		 5766 .access = PL3_RW,
5767 .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) },
a1ba125c
EI		 5768 { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
5769 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
5770 .access = PL3_RW, .writefn = vbar_write,
5771 .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
5772 .resetvalue = 0 },
c6f19164
GB		 5773 { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
5774 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
5775 .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
5776 .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
4cfb8ad8
PM		 5777 { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
5778 .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
5779 .access = PL3_RW, .resetvalue = 0,
5780 .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
2179ef95
PM		 5781 { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
5782 .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
5783 .access = PL3_RW, .type = ARM_CP_CONST,
5784 .resetvalue = 0 },
37cd6c24
PM		 5785 { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
5786 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
5787 .access = PL3_RW, .type = ARM_CP_CONST,
5788 .resetvalue = 0 },
5789 { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
5790 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
5791 .access = PL3_RW, .type = ARM_CP_CONST,
5792 .resetvalue = 0 },
43efaa33
PM		 5793 { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
5794 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
5795 .access = PL3_W, .type = ARM_CP_NO_RAW,
5796 .writefn = tlbi_aa64_alle3is_write },
5797 { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
5798 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
5799 .access = PL3_W, .type = ARM_CP_NO_RAW,
5800 .writefn = tlbi_aa64_vae3is_write },
5801 { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
5802 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
5803 .access = PL3_W, .type = ARM_CP_NO_RAW,
5804 .writefn = tlbi_aa64_vae3is_write },
5805 { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
5806 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
5807 .access = PL3_W, .type = ARM_CP_NO_RAW,
5808 .writefn = tlbi_aa64_alle3_write },
5809 { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
5810 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
5811 .access = PL3_W, .type = ARM_CP_NO_RAW,
5812 .writefn = tlbi_aa64_vae3_write },
5813 { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
5814 .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
5815 .access = PL3_W, .type = ARM_CP_NO_RAW,
5816 .writefn = tlbi_aa64_vae3_write },
0f1a3b24
FA		 5817 REGINFO_SENTINEL
5818};
5819
e2cce18f
RH		 5820#ifndef CONFIG_USER_ONLY
5821/* Test if system register redirection is to occur in the current state. */
5822static bool redirect_for_e2h(CPUARMState *env)
5823{
5824 return arm_current_el(env) == 2 && (arm_hcr_el2_eff(env) & HCR_E2H);
5825}
5826
5827static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri)
5828{
5829 CPReadFn *readfn;
5830
5831 if (redirect_for_e2h(env)) {
5832 /* Switch to the saved EL2 version of the register. */
5833 ri = ri->opaque;
5834 readfn = ri->readfn;
5835 } else {
5836 readfn = ri->orig_readfn;
5837 }
5838 if (readfn == NULL) {
5839 readfn = raw_read;
5840 }
5841 return readfn(env, ri);
5842}
5843
5844static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri,
5845 uint64_t value)
5846{
5847 CPWriteFn *writefn;
5848
5849 if (redirect_for_e2h(env)) {
5850 /* Switch to the saved EL2 version of the register. */
5851 ri = ri->opaque;
5852 writefn = ri->writefn;
5853 } else {
5854 writefn = ri->orig_writefn;
5855 }
5856 if (writefn == NULL) {
5857 writefn = raw_write;
5858 }
5859 writefn(env, ri, value);
5860}
5861
5862static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
5863{
5864 struct E2HAlias {
5865 uint32_t src_key, dst_key, new_key;
5866 const char *src_name, *dst_name, *new_name;
5867 bool (*feature)(const ARMISARegisters *id);
5868 };
5869
5870#define K(op0, op1, crn, crm, op2) \
5871 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
5872
5873 static const struct E2HAlias aliases[] = {
5874 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
5875 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
5876 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
5877 "CPACR", "CPTR_EL2", "CPACR_EL12" },
5878 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
5879 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
5880 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
5881 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
5882 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
5883 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
5884 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
5885 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
5886 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
5887 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
5888 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
5889 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
5890 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
5891 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
5892 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
5893 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
5894 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
5895 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
5896 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
5897 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
5898 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
5899 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
5900 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
5901 "VBAR", "VBAR_EL2", "VBAR_EL12" },
5902 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
5903 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
5904 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
5905 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
5906
5907 /*
5908 * Note that redirection of ZCR is mentioned in the description
5909 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
5910 * not in the summary table.
5911 */
5912 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
5913 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve },
5914
4b779ceb
RH		 5915 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
5916 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
5917
e2cce18f
RH		 5918 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
5919 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
5920 };
5921#undef K
5922
5923 size_t i;
5924
5925 for (i = 0; i < ARRAY_SIZE(aliases); i++) {
5926 const struct E2HAlias *a = &aliases[i];
5927 ARMCPRegInfo *src_reg, *dst_reg;
5928
5929 if (a->feature && !a->feature(&cpu->isar)) {
5930 continue;
5931 }
5932
5933 src_reg = g_hash_table_lookup(cpu->cp_regs, &a->src_key);
5934 dst_reg = g_hash_table_lookup(cpu->cp_regs, &a->dst_key);
5935 g_assert(src_reg != NULL);
5936 g_assert(dst_reg != NULL);
5937
5938 /* Cross-compare names to detect typos in the keys. */
5939 g_assert(strcmp(src_reg->name, a->src_name) == 0);
5940 g_assert(strcmp(dst_reg->name, a->dst_name) == 0);
5941
5942 /* None of the core system registers use opaque; we will. */
5943 g_assert(src_reg->opaque == NULL);
5944
5945 /* Create alias before redirection so we dup the right data. */
5946 if (a->new_key) {
5947 ARMCPRegInfo *new_reg = g_memdup(src_reg, sizeof(ARMCPRegInfo));
5948 uint32_t *new_key = g_memdup(&a->new_key, sizeof(uint32_t));
5949 bool ok;
5950
5951 new_reg->name = a->new_name;
5952 new_reg->type |= ARM_CP_ALIAS;
5953 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
5954 new_reg->access &= PL2_RW | PL3_RW;
5955
5956 ok = g_hash_table_insert(cpu->cp_regs, new_key, new_reg);
5957 g_assert(ok);
5958 }
5959
5960 src_reg->opaque = dst_reg;
5961 src_reg->orig_readfn = src_reg->readfn ?: raw_read;
5962 src_reg->orig_writefn = src_reg->writefn ?: raw_write;
5963 if (!src_reg->raw_readfn) {
5964 src_reg->raw_readfn = raw_read;
5965 }
5966 if (!src_reg->raw_writefn) {
5967 src_reg->raw_writefn = raw_write;
5968 }
5969 src_reg->readfn = el2_e2h_read;
5970 src_reg->writefn = el2_e2h_write;
5971 }
5972}
5973#endif
5974
3f208fd7
PM		 5975static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
5976 bool isread)
7da845b0 5977{
97475a89
RH		 5978 int cur_el = arm_current_el(env);
5979
5980 if (cur_el < 2) {
5981 uint64_t hcr = arm_hcr_el2_eff(env);
5982
5983 if (cur_el == 0) {
5984 if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
5985 if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) {
5986 return CP_ACCESS_TRAP_EL2;
5987 }
5988 } else {
5989 if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
5990 return CP_ACCESS_TRAP;
5991 }
5992 if (hcr & HCR_TID2) {
5993 return CP_ACCESS_TRAP_EL2;
5994 }
5995 }
5996 } else if (hcr & HCR_TID2) {
5997 return CP_ACCESS_TRAP_EL2;
5998 }
7da845b0 5999 }
630fcd4d
MZ		 6000
6001 if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) {
6002 return CP_ACCESS_TRAP_EL2;
6003 }
6004
7da845b0
PM		 6005 return CP_ACCESS_OK;
6006}
6007
1424ca8d
DM		 6008static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
6009 uint64_t value)
6010{
6011 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
6012 * read via a bit in OSLSR_EL1.
6013 */
6014 int oslock;
6015
6016 if (ri->state == ARM_CP_STATE_AA32) {
6017 oslock = (value == 0xC5ACCE55);
6018 } else {
6019 oslock = value & 1;
6020 }
6021
6022 env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
6023}
6024
50300698 6025static const ARMCPRegInfo debug_cp_reginfo[] = {
50300698 6026 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
10aae104
PM		 6027 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
6028 * unlike DBGDRAR it is never accessible from EL0.
6029 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
6030 * accessor.
50300698
PM		 6031 */
6032 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
91b0a238
PM		 6033 .access = PL0_R, .accessfn = access_tdra,
6034 .type = ARM_CP_CONST, .resetvalue = 0 },
10aae104
PM		 6035 { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
6036 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
91b0a238
PM		 6037 .access = PL1_R, .accessfn = access_tdra,
6038 .type = ARM_CP_CONST, .resetvalue = 0 },
50300698 6039 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
91b0a238
PM		 6040 .access = PL0_R, .accessfn = access_tdra,
6041 .type = ARM_CP_CONST, .resetvalue = 0 },
17a9eb53 6042 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
10aae104
PM		 6043 { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
6044 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
d6c8cf81 6045 .access = PL1_RW, .accessfn = access_tda,
0e5e8935
PM		 6046 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
6047 .resetvalue = 0 },
5e8b12ff
PM		 6048 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
6049 * We don't implement the configurable EL0 access.
6050 */
6051 { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
6052 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
7a0e58fa 6053 .type = ARM_CP_ALIAS,
d6c8cf81 6054 .access = PL1_R, .accessfn = access_tda,
b061a82b 6055 .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
10aae104
PM		 6056 { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
6057 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
1424ca8d 6058 .access = PL1_W, .type = ARM_CP_NO_RAW,
187f678d 6059 .accessfn = access_tdosa,
1424ca8d
DM		 6060 .writefn = oslar_write },
6061 { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
6062 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
6063 .access = PL1_R, .resetvalue = 10,
187f678d 6064 .accessfn = access_tdosa,
1424ca8d 6065 .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
5e8b12ff
PM		 6066 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
6067 { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
6068 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
187f678d
PM		 6069 .access = PL1_RW, .accessfn = access_tdosa,
6070 .type = ARM_CP_NOP },
5e8b12ff
PM		 6071 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
6072 * implement vector catch debug events yet.
6073 */
6074 { .name = "DBGVCR",
6075 .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
d6c8cf81
PM		 6076 .access = PL1_RW, .accessfn = access_tda,
6077 .type = ARM_CP_NOP },
4d2ec4da
PM		 6078 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
6079 * to save and restore a 32-bit guest's DBGVCR)
6080 */
6081 { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
6082 .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
6083 .access = PL2_RW, .accessfn = access_tda,
6084 .type = ARM_CP_NOP },
5dbdc434
PM		 6085 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
6086 * Channel but Linux may try to access this register. The 32-bit
6087 * alias is DBGDCCINT.
6088 */
6089 { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
6090 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
6091 .access = PL1_RW, .accessfn = access_tda,
6092 .type = ARM_CP_NOP },
50300698
PM		 6093 REGINFO_SENTINEL
6094};
6095
6096static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
6097 /* 64 bit access versions of the (dummy) debug registers */
6098 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
6099 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
6100 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
6101 .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
6102 REGINFO_SENTINEL
6103};
6104
60eed086
RH		 6105/* Return the exception level to which exceptions should be taken
6106 * via SVEAccessTrap. If an exception should be routed through
6107 * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
6108 * take care of raising that exception.
6109 * C.f. the ARM pseudocode function CheckSVEEnabled.
5be5e8ed 6110 */
ced31551 6111int sve_exception_el(CPUARMState *env, int el)
5be5e8ed
RH		 6112{
6113#ifndef CONFIG_USER_ONLY
c2ddb7cf
RH		 6114 uint64_t hcr_el2 = arm_hcr_el2_eff(env);
6115
6116 if (el <= 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
60eed086
RH		 6117 bool disabled = false;
6118
6119 /* The CPACR.ZEN controls traps to EL1:
6120 * 0, 2 : trap EL0 and EL1 accesses
6121 * 1 : trap only EL0 accesses
6122 * 3 : trap no accesses
6123 */
6124 if (!extract32(env->cp15.cpacr_el1, 16, 1)) {
6125 disabled = true;
6126 } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) {
2de7ace2 6127 disabled = el == 0;
5be5e8ed 6128 }
60eed086
RH		 6129 if (disabled) {
6130 /* route_to_el2 */
c2ddb7cf 6131 return hcr_el2 & HCR_TGE ? 2 : 1;
5be5e8ed 6132 }
5be5e8ed 6133
60eed086
RH		 6134 /* Check CPACR.FPEN. */
6135 if (!extract32(env->cp15.cpacr_el1, 20, 1)) {
6136 disabled = true;
6137 } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) {
2de7ace2 6138 disabled = el == 0;
5be5e8ed 6139 }
60eed086
RH		 6140 if (disabled) {
6141 return 0;
5be5e8ed 6142 }
5be5e8ed
RH		 6143 }
6144
60eed086
RH		 6145 /* CPTR_EL2. Since TZ and TFP are positive,
6146 * they will be zero when EL2 is not present.
6147 */
2de7ace2 6148 if (el <= 2 && !arm_is_secure_below_el3(env)) {
60eed086
RH		 6149 if (env->cp15.cptr_el[2] & CPTR_TZ) {
6150 return 2;
6151 }
6152 if (env->cp15.cptr_el[2] & CPTR_TFP) {
6153 return 0;
6154 }
5be5e8ed
RH		 6155 }
6156
60eed086
RH		 6157 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6158 if (arm_feature(env, ARM_FEATURE_EL3)
6159 && !(env->cp15.cptr_el[3] & CPTR_EZ)) {
5be5e8ed
RH		 6160 return 3;
6161 }
6162#endif
6163 return 0;
6164}
6165
0df9142d
AJ		 6166static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
6167{
6e553f2a 6168 uint32_t end_len;
0df9142d 6169
6e553f2a
RH		 6170 end_len = start_len &= 0xf;
6171 if (!test_bit(start_len, cpu->sve_vq_map)) {
6172 end_len = find_last_bit(cpu->sve_vq_map, start_len);
6173 assert(end_len < start_len);
6174 }
6175 return end_len;
0df9142d
AJ		 6176}
6177
0ab5953b
RH		 6178/*
6179 * Given that SVE is enabled, return the vector length for EL.
6180 */
ced31551 6181uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
0ab5953b 6182{
2fc0cc0e 6183 ARMCPU *cpu = env_archcpu(env);
0ab5953b
RH		 6184 uint32_t zcr_len = cpu->sve_max_vq - 1;
6185
6186 if (el <= 1) {
6187 zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
6188 }
6a02a732 6189 if (el <= 2 && arm_feature(env, ARM_FEATURE_EL2)) {
0ab5953b
RH		 6190 zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]);
6191 }
6a02a732 6192 if (arm_feature(env, ARM_FEATURE_EL3)) {
0ab5953b
RH		 6193 zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
6194 }
0df9142d
AJ		 6195
6196 return sve_zcr_get_valid_len(cpu, zcr_len);
0ab5953b
RH		 6197}
6198
5be5e8ed
RH		 6199static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
6200 uint64_t value)
6201{
0ab5953b
RH		 6202 int cur_el = arm_current_el(env);
6203 int old_len = sve_zcr_len_for_el(env, cur_el);
6204 int new_len;
6205
5be5e8ed 6206 /* Bits other than [3:0] are RAZ/WI. */
7b351d98 6207 QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16);
5be5e8ed 6208 raw_write(env, ri, value & 0xf);
0ab5953b
RH		 6209
6210 /*
6211 * Because we arrived here, we know both FP and SVE are enabled;
6212 * otherwise we would have trapped access to the ZCR_ELn register.
6213 */
6214 new_len = sve_zcr_len_for_el(env, cur_el);
6215 if (new_len < old_len) {
6216 aarch64_sve_narrow_vq(env, new_len + 1);
6217 }
5be5e8ed
RH		 6218}
6219
6220static const ARMCPRegInfo zcr_el1_reginfo = {
6221 .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
6222 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
11d7870b 6223 .access = PL1_RW, .type = ARM_CP_SVE,
5be5e8ed
RH		 6224 .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
6225 .writefn = zcr_write, .raw_writefn = raw_write
6226};
6227
6228static const ARMCPRegInfo zcr_el2_reginfo = {
6229 .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
6230 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
11d7870b 6231 .access = PL2_RW, .type = ARM_CP_SVE,
5be5e8ed
RH		 6232 .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
6233 .writefn = zcr_write, .raw_writefn = raw_write
6234};
6235
6236static const ARMCPRegInfo zcr_no_el2_reginfo = {
6237 .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
6238 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
11d7870b 6239 .access = PL2_RW, .type = ARM_CP_SVE,
5be5e8ed
RH		 6240 .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
6241};
6242
6243static const ARMCPRegInfo zcr_el3_reginfo = {
6244 .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
6245 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
11d7870b 6246 .access = PL3_RW, .type = ARM_CP_SVE,
5be5e8ed
RH		 6247 .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
6248 .writefn = zcr_write, .raw_writefn = raw_write
6249};
6250
9ee98ce8
PM		 6251void hw_watchpoint_update(ARMCPU *cpu, int n)
6252{
6253 CPUARMState *env = &cpu->env;
6254 vaddr len = 0;
6255 vaddr wvr = env->cp15.dbgwvr[n];
6256 uint64_t wcr = env->cp15.dbgwcr[n];
6257 int mask;
6258 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
6259
6260 if (env->cpu_watchpoint[n]) {
6261 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
6262 env->cpu_watchpoint[n] = NULL;
6263 }
6264
6265 if (!extract64(wcr, 0, 1)) {
6266 /* E bit clear : watchpoint disabled */
6267 return;
6268 }
6269
6270 switch (extract64(wcr, 3, 2)) {
6271 case 0:
6272 /* LSC 00 is reserved and must behave as if the wp is disabled */
6273 return;
6274 case 1:
6275 flags |= BP_MEM_READ;
6276 break;
6277 case 2:
6278 flags |= BP_MEM_WRITE;
6279 break;
6280 case 3:
6281 flags |= BP_MEM_ACCESS;
6282 break;
6283 }
6284
6285 /* Attempts to use both MASK and BAS fields simultaneously are
6286 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
6287 * thus generating a watchpoint for every byte in the masked region.
6288 */
6289 mask = extract64(wcr, 24, 4);
6290 if (mask == 1 || mask == 2) {
6291 /* Reserved values of MASK; we must act as if the mask value was
6292 * some non-reserved value, or as if the watchpoint were disabled.
6293 * We choose the latter.
6294 */
6295 return;
6296 } else if (mask) {
6297 /* Watchpoint covers an aligned area up to 2GB in size */
6298 len = 1ULL << mask;
6299 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
6300 * whether the watchpoint fires when the unmasked bits match; we opt
6301 * to generate the exceptions.
6302 */
6303 wvr &= ~(len - 1);
6304 } else {
6305 /* Watchpoint covers bytes defined by the byte address select bits */
6306 int bas = extract64(wcr, 5, 8);
6307 int basstart;
6308
9ee98ce8
PM		 6309 if (extract64(wvr, 2, 1)) {
6310 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
6311 * ignored, and BAS[3:0] define which bytes to watch.
6312 */
6313 bas &= 0xf;
6314 }
ae1111d4
RH		 6315
6316 if (bas == 0) {
6317 /* This must act as if the watchpoint is disabled */
6318 return;
6319 }
6320
9ee98ce8
PM		 6321 /* The BAS bits are supposed to be programmed to indicate a contiguous
6322 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
6323 * we fire for each byte in the word/doubleword addressed by the WVR.
6324 * We choose to ignore any non-zero bits after the first range of 1s.
6325 */
6326 basstart = ctz32(bas);
6327 len = cto32(bas >> basstart);
6328 wvr += basstart;
6329 }
6330
6331 cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
6332 &env->cpu_watchpoint[n]);
6333}
6334
6335void hw_watchpoint_update_all(ARMCPU *cpu)
6336{
6337 int i;
6338 CPUARMState *env = &cpu->env;
6339
6340 /* Completely clear out existing QEMU watchpoints and our array, to
6341 * avoid possible stale entries following migration load.
6342 */
6343 cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
6344 memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
6345
6346 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
6347 hw_watchpoint_update(cpu, i);
6348 }
6349}
6350
6351static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
6352 uint64_t value)
6353{
2fc0cc0e 6354 ARMCPU *cpu = env_archcpu(env);
9ee98ce8
PM		 6355 int i = ri->crm;
6356
6357 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
6358 * register reads and behaves as if values written are sign extended.
6359 * Bits [1:0] are RES0.
6360 */
6361 value = sextract64(value, 0, 49) & ~3ULL;
6362
6363 raw_write(env, ri, value);
6364 hw_watchpoint_update(cpu, i);
6365}
6366
6367static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
6368 uint64_t value)
6369{
2fc0cc0e 6370 ARMCPU *cpu = env_archcpu(env);
9ee98ce8
PM		 6371 int i = ri->crm;
6372
6373 raw_write(env, ri, value);
6374 hw_watchpoint_update(cpu, i);
6375}
6376
46747d15
PM		 6377void hw_breakpoint_update(ARMCPU *cpu, int n)
6378{
6379 CPUARMState *env = &cpu->env;
6380 uint64_t bvr = env->cp15.dbgbvr[n];
6381 uint64_t bcr = env->cp15.dbgbcr[n];
6382 vaddr addr;
6383 int bt;
6384 int flags = BP_CPU;
6385
6386 if (env->cpu_breakpoint[n]) {
6387 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
6388 env->cpu_breakpoint[n] = NULL;
6389 }
6390
6391 if (!extract64(bcr, 0, 1)) {
6392 /* E bit clear : watchpoint disabled */
6393 return;
6394 }
6395
6396 bt = extract64(bcr, 20, 4);
6397
6398 switch (bt) {
6399 case 4: /* unlinked address mismatch (reserved if AArch64) */
6400 case 5: /* linked address mismatch (reserved if AArch64) */
6401 qemu_log_mask(LOG_UNIMP,
0221c8fd 6402 "arm: address mismatch breakpoint types not implemented\n");
46747d15
PM		 6403 return;
6404 case 0: /* unlinked address match */
6405 case 1: /* linked address match */
6406 {
6407 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
6408 * we behave as if the register was sign extended. Bits [1:0] are
6409 * RES0. The BAS field is used to allow setting breakpoints on 16
6410 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
6411 * a bp will fire if the addresses covered by the bp and the addresses
6412 * covered by the insn overlap but the insn doesn't start at the
6413 * start of the bp address range. We choose to require the insn and
6414 * the bp to have the same address. The constraints on writing to
6415 * BAS enforced in dbgbcr_write mean we have only four cases:
6416 * 0b0000 => no breakpoint
6417 * 0b0011 => breakpoint on addr
6418 * 0b1100 => breakpoint on addr + 2
6419 * 0b1111 => breakpoint on addr
6420 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
6421 */
6422 int bas = extract64(bcr, 5, 4);
6423 addr = sextract64(bvr, 0, 49) & ~3ULL;
6424 if (bas == 0) {
6425 return;
6426 }
6427 if (bas == 0xc) {
6428 addr += 2;
6429 }
6430 break;
6431 }
6432 case 2: /* unlinked context ID match */
6433 case 8: /* unlinked VMID match (reserved if no EL2) */
6434 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
6435 qemu_log_mask(LOG_UNIMP,
0221c8fd 6436 "arm: unlinked context breakpoint types not implemented\n");
46747d15
PM		 6437 return;
6438 case 9: /* linked VMID match (reserved if no EL2) */
6439 case 11: /* linked context ID and VMID match (reserved if no EL2) */
6440 case 3: /* linked context ID match */
6441 default:
6442 /* We must generate no events for Linked context matches (unless
6443 * they are linked to by some other bp/wp, which is handled in
6444 * updates for the linking bp/wp). We choose to also generate no events
6445 * for reserved values.
6446 */
6447 return;
6448 }
6449
6450 cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
6451}
6452
6453void hw_breakpoint_update_all(ARMCPU *cpu)
6454{
6455 int i;
6456 CPUARMState *env = &cpu->env;
6457
6458 /* Completely clear out existing QEMU breakpoints and our array, to
6459 * avoid possible stale entries following migration load.
6460 */
6461 cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
6462 memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
6463
6464 for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
6465 hw_breakpoint_update(cpu, i);
6466 }
6467}
6468
6469static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
6470 uint64_t value)
6471{
2fc0cc0e 6472 ARMCPU *cpu = env_archcpu(env);
46747d15
PM		 6473 int i = ri->crm;
6474
6475 raw_write(env, ri, value);
6476 hw_breakpoint_update(cpu, i);
6477}
6478
6479static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
6480 uint64_t value)
6481{
2fc0cc0e 6482 ARMCPU *cpu = env_archcpu(env);
46747d15
PM		 6483 int i = ri->crm;
6484
6485 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
6486 * copy of BAS[0].
6487 */
6488 value = deposit64(value, 6, 1, extract64(value, 5, 1));
6489 value = deposit64(value, 8, 1, extract64(value, 7, 1));
6490
6491 raw_write(env, ri, value);
6492 hw_breakpoint_update(cpu, i);
6493}
6494
50300698 6495static void define_debug_regs(ARMCPU *cpu)
0b45451e 6496{
50300698
PM		 6497 /* Define v7 and v8 architectural debug registers.
6498 * These are just dummy implementations for now.
0b45451e
PM		 6499 */
6500 int i;
3ff6fc91 6501 int wrps, brps, ctx_cmps;
48eb3ae6
PM		 6502 ARMCPRegInfo dbgdidr = {
6503 .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
d6c8cf81 6504 .access = PL0_R, .accessfn = access_tda,
4426d361 6505 .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
48eb3ae6
PM		 6506 };
6507
3ff6fc91 6508 /* Note that all these register fields hold "number of Xs minus 1". */
88ce6c6e
PM		 6509 brps = arm_num_brps(cpu);
6510 wrps = arm_num_wrps(cpu);
6511 ctx_cmps = arm_num_ctx_cmps(cpu);
3ff6fc91
PM		 6512
6513 assert(ctx_cmps <= brps);
48eb3ae6 6514
48eb3ae6 6515 define_one_arm_cp_reg(cpu, &dbgdidr);
50300698
PM		 6516 define_arm_cp_regs(cpu, debug_cp_reginfo);
6517
6518 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
6519 define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
6520 }
6521
88ce6c6e 6522 for (i = 0; i < brps; i++) {
0b45451e 6523 ARMCPRegInfo dbgregs[] = {
10aae104
PM		 6524 { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
6525 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
d6c8cf81 6526 .access = PL1_RW, .accessfn = access_tda,
46747d15
PM		 6527 .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
6528 .writefn = dbgbvr_write, .raw_writefn = raw_write
6529 },
10aae104
PM		 6530 { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
6531 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
d6c8cf81 6532 .access = PL1_RW, .accessfn = access_tda,
46747d15
PM		 6533 .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
6534 .writefn = dbgbcr_write, .raw_writefn = raw_write
6535 },
48eb3ae6
PM		 6536 REGINFO_SENTINEL
6537 };
6538 define_arm_cp_regs(cpu, dbgregs);
6539 }
6540
88ce6c6e 6541 for (i = 0; i < wrps; i++) {
48eb3ae6 6542 ARMCPRegInfo dbgregs[] = {
10aae104
PM		 6543 { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
6544 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
d6c8cf81 6545 .access = PL1_RW, .accessfn = access_tda,
9ee98ce8
PM		 6546 .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
6547 .writefn = dbgwvr_write, .raw_writefn = raw_write
6548 },
10aae104
PM		 6549 { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
6550 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
d6c8cf81 6551 .access = PL1_RW, .accessfn = access_tda,
9ee98ce8
PM		 6552 .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
6553 .writefn = dbgwcr_write, .raw_writefn = raw_write
6554 },
6555 REGINFO_SENTINEL
0b45451e
PM		 6556 };
6557 define_arm_cp_regs(cpu, dbgregs);
6558 }
6559}
6560
24183fb6
PM		 6561static void define_pmu_regs(ARMCPU *cpu)
6562{
6563 /*
6564 * v7 performance monitor control register: same implementor
6565 * field as main ID register, and we implement four counters in
6566 * addition to the cycle count register.
6567 */
6568 unsigned int i, pmcrn = 4;
6569 ARMCPRegInfo pmcr = {
6570 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
6571 .access = PL0_RW,
6572 .type = ARM_CP_IO | ARM_CP_ALIAS,
6573 .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
6574 .accessfn = pmreg_access, .writefn = pmcr_write,
6575 .raw_writefn = raw_write,
6576 };
6577 ARMCPRegInfo pmcr64 = {
6578 .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
6579 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
6580 .access = PL0_RW, .accessfn = pmreg_access,
6581 .type = ARM_CP_IO,
6582 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
62d96ff4
PM		 6583 .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) |
6584 PMCRLC,
24183fb6
PM		 6585 .writefn = pmcr_write, .raw_writefn = raw_write,
6586 };
6587 define_one_arm_cp_reg(cpu, &pmcr);
6588 define_one_arm_cp_reg(cpu, &pmcr64);
6589 for (i = 0; i < pmcrn; i++) {
6590 char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i);
6591 char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i);
6592 char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i);
6593 char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i);
6594 ARMCPRegInfo pmev_regs[] = {
6595 { .name = pmevcntr_name, .cp = 15, .crn = 14,
6596 .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
6597 .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
6598 .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
6599 .accessfn = pmreg_access },
6600 { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
6601 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
6602 .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
6603 .type = ARM_CP_IO,
6604 .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
6605 .raw_readfn = pmevcntr_rawread,
6606 .raw_writefn = pmevcntr_rawwrite },
6607 { .name = pmevtyper_name, .cp = 15, .crn = 14,
6608 .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
6609 .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
6610 .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
6611 .accessfn = pmreg_access },
6612 { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,
6613 .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),
6614 .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
6615 .type = ARM_CP_IO,
6616 .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
6617 .raw_writefn = pmevtyper_rawwrite },
6618 REGINFO_SENTINEL
6619 };
6620 define_arm_cp_regs(cpu, pmev_regs);
6621 g_free(pmevcntr_name);
6622 g_free(pmevcntr_el0_name);
6623 g_free(pmevtyper_name);
6624 g_free(pmevtyper_el0_name);
6625 }
a6179538 6626 if (cpu_isar_feature(aa32_pmu_8_1, cpu)) {
24183fb6
PM		 6627 ARMCPRegInfo v81_pmu_regs[] = {
6628 { .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
6629 .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
6630 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
6631 .resetvalue = extract64(cpu->pmceid0, 32, 32) },
6632 { .name = "PMCEID3", .state = ARM_CP_STATE_AA32,
6633 .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
6634 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
6635 .resetvalue = extract64(cpu->pmceid1, 32, 32) },
6636 REGINFO_SENTINEL
6637 };
6638 define_arm_cp_regs(cpu, v81_pmu_regs);
6639 }
15dd1ebd
PM		 6640 if (cpu_isar_feature(any_pmu_8_4, cpu)) {
6641 static const ARMCPRegInfo v84_pmmir = {
6642 .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH,
6643 .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6,
6644 .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
6645 .resetvalue = 0
6646 };
6647 define_one_arm_cp_reg(cpu, &v84_pmmir);
6648 }
24183fb6
PM		 6649}
6650
96a8b92e
PM		 6651/* We don't know until after realize whether there's a GICv3
6652 * attached, and that is what registers the gicv3 sysregs.
6653 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
6654 * at runtime.
6655 */
6656static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
6657{
2fc0cc0e 6658 ARMCPU *cpu = env_archcpu(env);
8a130a7b 6659 uint64_t pfr1 = cpu->isar.id_pfr1;
96a8b92e
PM		 6660
6661 if (env->gicv3state) {
6662 pfr1 |= 1 << 28;
6663 }
6664 return pfr1;
6665}
6666
976b99b6 6667#ifndef CONFIG_USER_ONLY
96a8b92e
PM		 6668static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
6669{
2fc0cc0e 6670 ARMCPU *cpu = env_archcpu(env);
47576b94 6671 uint64_t pfr0 = cpu->isar.id_aa64pfr0;
96a8b92e
PM		 6672
6673 if (env->gicv3state) {
6674 pfr0 |= 1 << 24;
6675 }
6676 return pfr0;
6677}
976b99b6 6678#endif
96a8b92e 6679
2d7137c1 6680/* Shared logic between LORID and the rest of the LOR* registers.
9bd268ba 6681 * Secure state exclusion has already been dealt with.
2d7137c1 6682 */
9bd268ba
RDC		 6683static CPAccessResult access_lor_ns(CPUARMState *env,
6684 const ARMCPRegInfo *ri, bool isread)
2d7137c1
RH		 6685{
6686 int el = arm_current_el(env);
6687
6688 if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) {
6689 return CP_ACCESS_TRAP_EL2;
6690 }
6691 if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) {
6692 return CP_ACCESS_TRAP_EL3;
6693 }
6694 return CP_ACCESS_OK;
6695}
6696
2d7137c1
RH		 6697static CPAccessResult access_lor_other(CPUARMState *env,
6698 const ARMCPRegInfo *ri, bool isread)
6699{
6700 if (arm_is_secure_below_el3(env)) {
6701 /* Access denied in secure mode. */
6702 return CP_ACCESS_TRAP;
6703 }
9bd268ba 6704 return access_lor_ns(env, ri, isread);
2d7137c1
RH		 6705}
6706
d8564ee4
RH		 6707/*
6708 * A trivial implementation of ARMv8.1-LOR leaves all of these
6709 * registers fixed at 0, which indicates that there are zero
6710 * supported Limited Ordering regions.
6711 */
6712static const ARMCPRegInfo lor_reginfo[] = {
6713 { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64,
6714 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0,
6715 .access = PL1_RW, .accessfn = access_lor_other,
6716 .type = ARM_CP_CONST, .resetvalue = 0 },
6717 { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64,
6718 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1,
6719 .access = PL1_RW, .accessfn = access_lor_other,
6720 .type = ARM_CP_CONST, .resetvalue = 0 },
6721 { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64,
6722 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2,
6723 .access = PL1_RW, .accessfn = access_lor_other,
6724 .type = ARM_CP_CONST, .resetvalue = 0 },
6725 { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64,
6726 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3,
6727 .access = PL1_RW, .accessfn = access_lor_other,
6728 .type = ARM_CP_CONST, .resetvalue = 0 },
6729 { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
6730 .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
9bd268ba 6731 .access = PL1_R, .accessfn = access_lor_ns,
d8564ee4
RH		 6732 .type = ARM_CP_CONST, .resetvalue = 0 },
6733 REGINFO_SENTINEL
6734};
6735
967aa94f
RH		 6736#ifdef TARGET_AARCH64
6737static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri,
6738 bool isread)
6739{
6740 int el = arm_current_el(env);
6741
6742 if (el < 2 &&
6743 arm_feature(env, ARM_FEATURE_EL2) &&
6744 !(arm_hcr_el2_eff(env) & HCR_APK)) {
6745 return CP_ACCESS_TRAP_EL2;
6746 }
6747 if (el < 3 &&
6748 arm_feature(env, ARM_FEATURE_EL3) &&
6749 !(env->cp15.scr_el3 & SCR_APK)) {
6750 return CP_ACCESS_TRAP_EL3;
6751 }
6752 return CP_ACCESS_OK;
6753}
6754
6755static const ARMCPRegInfo pauth_reginfo[] = {
6756 { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6757 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0,
6758 .access = PL1_RW, .accessfn = access_pauth,
108b3ba8 6759 .fieldoffset = offsetof(CPUARMState, keys.apda.lo) },
967aa94f
RH		 6760 { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6761 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1,
6762 .access = PL1_RW, .accessfn = access_pauth,
108b3ba8 6763 .fieldoffset = offsetof(CPUARMState, keys.apda.hi) },
967aa94f
RH		 6764 { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6765 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2,
6766 .access = PL1_RW, .accessfn = access_pauth,
108b3ba8 6767 .fieldoffset = offsetof(CPUARMState, keys.apdb.lo) },
967aa94f
RH		 6768 { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6769 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3,
6770 .access = PL1_RW, .accessfn = access_pauth,
108b3ba8 6771 .fieldoffset = offsetof(CPUARMState, keys.apdb.hi) },
967aa94f
RH		 6772 { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6773 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0,
6774 .access = PL1_RW, .accessfn = access_pauth,
108b3ba8 6775 .fieldoffset = offsetof(CPUARMState, keys.apga.lo) },
967aa94f
RH		 6776 { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6777 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1,
6778 .access = PL1_RW, .accessfn = access_pauth,
108b3ba8 6779 .fieldoffset = offsetof(CPUARMState, keys.apga.hi) },
967aa94f
RH		 6780 { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6781 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0,
6782 .access = PL1_RW, .accessfn = access_pauth,
108b3ba8 6783 .fieldoffset = offsetof(CPUARMState, keys.apia.lo) },
967aa94f
RH		 6784 { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6785 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1,
6786 .access = PL1_RW, .accessfn = access_pauth,
108b3ba8 6787 .fieldoffset = offsetof(CPUARMState, keys.apia.hi) },
967aa94f
RH		 6788 { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
6789 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2,
6790 .access = PL1_RW, .accessfn = access_pauth,
108b3ba8 6791 .fieldoffset = offsetof(CPUARMState, keys.apib.lo) },
967aa94f
RH		 6792 { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
6793 .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
6794 .access = PL1_RW, .accessfn = access_pauth,
108b3ba8 6795 .fieldoffset = offsetof(CPUARMState, keys.apib.hi) },
967aa94f
RH		 6796 REGINFO_SENTINEL
6797};
de390645
RH		 6798
6799static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
6800{
6801 Error *err = NULL;
6802 uint64_t ret;
6803
6804 /* Success sets NZCV = 0000. */
6805 env->NF = env->CF = env->VF = 0, env->ZF = 1;
6806
6807 if (qemu_guest_getrandom(&ret, sizeof(ret), &err) < 0) {
6808 /*
6809 * ??? Failed, for unknown reasons in the crypto subsystem.
6810 * The best we can do is log the reason and return the
6811 * timed-out indication to the guest. There is no reason
6812 * we know to expect this failure to be transitory, so the
6813 * guest may well hang retrying the operation.
6814 */
6815 qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
6816 ri->name, error_get_pretty(err));
6817 error_free(err);
6818
6819 env->ZF = 0; /* NZCF = 0100 */
6820 return 0;
6821 }
6822 return ret;
6823}
6824
6825/* We do not support re-seeding, so the two registers operate the same. */
6826static const ARMCPRegInfo rndr_reginfo[] = {
6827 { .name = "RNDR", .state = ARM_CP_STATE_AA64,
6828 .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO,
6829 .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 0,
6830 .access = PL0_R, .readfn = rndr_readfn },
6831 { .name = "RNDRRS", .state = ARM_CP_STATE_AA64,
6832 .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO,
6833 .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1,
6834 .access = PL0_R, .readfn = rndr_readfn },
6835 REGINFO_SENTINEL
6836};
0d57b499
BM		 6837
6838#ifndef CONFIG_USER_ONLY
6839static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque,
6840 uint64_t value)
6841{
6842 ARMCPU *cpu = env_archcpu(env);
6843 /* CTR_EL0 System register -> DminLine, bits [19:16] */
6844 uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF);
6845 uint64_t vaddr_in = (uint64_t) value;
6846 uint64_t vaddr = vaddr_in & ~(dline_size - 1);
6847 void *haddr;
6848 int mem_idx = cpu_mmu_index(env, false);
6849
6850 /* This won't be crossing page boundaries */
6851 haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC());
6852 if (haddr) {
6853
6854 ram_addr_t offset;
6855 MemoryRegion *mr;
6856
6857 /* RCU lock is already being held */
6858 mr = memory_region_from_host(haddr, &offset);
6859
6860 if (mr) {
4dfe59d1 6861 memory_region_writeback(mr, offset, dline_size);
0d57b499
BM		 6862 }
6863 }
6864}
6865
6866static const ARMCPRegInfo dcpop_reg[] = {
6867 { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64,
6868 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
6869 .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
1bed4d2e 6870 .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
0d57b499
BM		 6871 REGINFO_SENTINEL
6872};
6873
6874static const ARMCPRegInfo dcpodp_reg[] = {
6875 { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64,
6876 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
6877 .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
1bed4d2e 6878 .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
0d57b499
BM		 6879 REGINFO_SENTINEL
6880};
6881#endif /*CONFIG_USER_ONLY*/
6882
4b779ceb
RH		 6883static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInfo *ri,
6884 bool isread)
6885{
6886 if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID5)) {
6887 return CP_ACCESS_TRAP_EL2;
6888 }
6889
6890 return CP_ACCESS_OK;
6891}
6892
6893static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri,
6894 bool isread)
6895{
6896 int el = arm_current_el(env);
6897
4301acd7
RH		 6898 if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
6899 uint64_t hcr = arm_hcr_el2_eff(env);
6900 if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) {
6901 return CP_ACCESS_TRAP_EL2;
6902 }
4b779ceb
RH		 6903 }
6904 if (el < 3 &&
6905 arm_feature(env, ARM_FEATURE_EL3) &&
6906 !(env->cp15.scr_el3 & SCR_ATA)) {
6907 return CP_ACCESS_TRAP_EL3;
6908 }
6909 return CP_ACCESS_OK;
6910}
6911
6912static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri)
6913{
6914 return env->pstate & PSTATE_TCO;
6915}
6916
6917static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
6918{
6919 env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO);
6920}
6921
6922static const ARMCPRegInfo mte_reginfo[] = {
6923 { .name = "TFSRE0_EL1", .state = ARM_CP_STATE_AA64,
6924 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 1,
6925 .access = PL1_RW, .accessfn = access_mte,
6926 .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) },
6927 { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64,
6928 .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 0,
6929 .access = PL1_RW, .accessfn = access_mte,
6930 .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) },
6931 { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64,
6932 .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 6, .opc2 = 0,
6933 .access = PL2_RW, .accessfn = access_mte,
6934 .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) },
6935 { .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64,
6936 .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 6, .opc2 = 0,
6937 .access = PL3_RW,
6938 .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) },
6939 { .name = "RGSR_EL1", .state = ARM_CP_STATE_AA64,
6940 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5,
6941 .access = PL1_RW, .accessfn = access_mte,
6942 .fieldoffset = offsetof(CPUARMState, cp15.rgsr_el1) },
6943 { .name = "GCR_EL1", .state = ARM_CP_STATE_AA64,
6944 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6,
6945 .access = PL1_RW, .accessfn = access_mte,
6946 .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) },
6947 { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
6948 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
6949 .access = PL1_R, .accessfn = access_aa64_tid5,
6950 .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
6951 { .name = "TCO", .state = ARM_CP_STATE_AA64,
6952 .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
6953 .type = ARM_CP_NO_RAW,
6954 .access = PL0_RW, .readfn = tco_read, .writefn = tco_write },
5463df16
RH		 6955 { .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64,
6956 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3,
6957 .type = ARM_CP_NOP, .access = PL1_W,
6958 .accessfn = aa64_cacheop_poc_access },
6959 { .name = "DC_IGSW", .state = ARM_CP_STATE_AA64,
6960 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4,
6961 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
6962 { .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64,
6963 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5,
6964 .type = ARM_CP_NOP, .access = PL1_W,
6965 .accessfn = aa64_cacheop_poc_access },
6966 { .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64,
6967 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6,
6968 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
6969 { .name = "DC_CGSW", .state = ARM_CP_STATE_AA64,
6970 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4,
6971 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
6972 { .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64,
6973 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6,
6974 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
6975 { .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64,
6976 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4,
6977 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
6978 { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64,
6979 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
6980 .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
4b779ceb
RH		 6981 REGINFO_SENTINEL
6982};
6983
6984static const ARMCPRegInfo mte_tco_ro_reginfo[] = {
6985 { .name = "TCO", .state = ARM_CP_STATE_AA64,
6986 .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
6987 .type = ARM_CP_CONST, .access = PL0_RW, },
6988 REGINFO_SENTINEL
6989};
5463df16
RH		 6990
6991static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
6992 { .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64,
6993 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3,
6994 .type = ARM_CP_NOP, .access = PL0_W,
6995 .accessfn = aa64_cacheop_poc_access },
6996 { .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64,
6997 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5,
6998 .type = ARM_CP_NOP, .access = PL0_W,
6999 .accessfn = aa64_cacheop_poc_access },
7000 { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64,
7001 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
7002 .type = ARM_CP_NOP, .access = PL0_W,
7003 .accessfn = aa64_cacheop_poc_access },
7004 { .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64,
7005 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5,
7006 .type = ARM_CP_NOP, .access = PL0_W,
7007 .accessfn = aa64_cacheop_poc_access },
7008 { .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64,
7009 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3,
7010 .type = ARM_CP_NOP, .access = PL0_W,
7011 .accessfn = aa64_cacheop_poc_access },
7012 { .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64,
7013 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5,
7014 .type = ARM_CP_NOP, .access = PL0_W,
7015 .accessfn = aa64_cacheop_poc_access },
7016 { .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64,
7017 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3,
7018 .type = ARM_CP_NOP, .access = PL0_W,
7019 .accessfn = aa64_cacheop_poc_access },
7020 { .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64,
7021 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5,
7022 .type = ARM_CP_NOP, .access = PL0_W,
7023 .accessfn = aa64_cacheop_poc_access },
eb821168
RH		 7024 { .name = "DC_GVA", .state = ARM_CP_STATE_AA64,
7025 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3,
7026 .access = PL0_W, .type = ARM_CP_DC_GVA,
7027#ifndef CONFIG_USER_ONLY
7028 /* Avoid overhead of an access check that always passes in user-mode */
7029 .accessfn = aa64_zva_access,
7030#endif
7031 },
7032 { .name = "DC_GZVA", .state = ARM_CP_STATE_AA64,
7033 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 4,
7034 .access = PL0_W, .type = ARM_CP_DC_GZVA,
7035#ifndef CONFIG_USER_ONLY
7036 /* Avoid overhead of an access check that always passes in user-mode */
7037 .accessfn = aa64_zva_access,
7038#endif
7039 },
5463df16
RH		 7040 REGINFO_SENTINEL
7041};
7042
967aa94f
RH		 7043#endif
7044
cb570bd3
RH		 7045static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
7046 bool isread)
7047{
7048 int el = arm_current_el(env);
7049
7050 if (el == 0) {
7051 uint64_t sctlr = arm_sctlr(env, el);
7052 if (!(sctlr & SCTLR_EnRCTX)) {
7053 return CP_ACCESS_TRAP;
7054 }
7055 } else if (el == 1) {
7056 uint64_t hcr = arm_hcr_el2_eff(env);
7057 if (hcr & HCR_NV) {
7058 return CP_ACCESS_TRAP_EL2;
7059 }
7060 }
7061 return CP_ACCESS_OK;
7062}
7063
7064static const ARMCPRegInfo predinv_reginfo[] = {
7065 { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64,
7066 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4,
7067 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
7068 { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64,
7069 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5,
7070 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
7071 { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64,
7072 .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7,
7073 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
7074 /*
7075 * Note the AArch32 opcodes have a different OPC1.
7076 */
7077 { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32,
7078 .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4,
7079 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
7080 { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32,
7081 .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5,
7082 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
7083 { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
7084 .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
7085 .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
7086 REGINFO_SENTINEL
7087};
7088
957e6155
PM		 7089static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri)
7090{
7091 /* Read the high 32 bits of the current CCSIDR */
7092 return extract64(ccsidr_read(env, ri), 32, 32);
7093}
7094
7095static const ARMCPRegInfo ccsidr2_reginfo[] = {
7096 { .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH,
7097 .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2,
7098 .access = PL1_R,
7099 .accessfn = access_aa64_tid2,
7100 .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW },
7101 REGINFO_SENTINEL
7102};
7103
6a4ef4e5
MZ		 7104static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
7105 bool isread)
7106{
7107 if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) {
7108 return CP_ACCESS_TRAP_EL2;
7109 }
7110
7111 return CP_ACCESS_OK;
7112}
7113
7114static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
7115 bool isread)
7116{
7117 if (arm_feature(env, ARM_FEATURE_V8)) {
7118 return access_aa64_tid3(env, ri, isread);
7119 }
7120
7121 return CP_ACCESS_OK;
7122}
7123
f96f3d5f
MZ		 7124static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri,
7125 bool isread)
7126{
7127 if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID0)) {
7128 return CP_ACCESS_TRAP_EL2;
7129 }
7130
7131 return CP_ACCESS_OK;
7132}
7133
7134static const ARMCPRegInfo jazelle_regs[] = {
7135 { .name = "JIDR",
7136 .cp = 14, .crn = 0, .crm = 0, .opc1 = 7, .opc2 = 0,
7137 .access = PL1_R, .accessfn = access_jazelle,
7138 .type = ARM_CP_CONST, .resetvalue = 0 },
7139 { .name = "JOSCR",
7140 .cp = 14, .crn = 1, .crm = 0, .opc1 = 7, .opc2 = 0,
7141 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
7142 { .name = "JMCR",
7143 .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0,
7144 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
7145 REGINFO_SENTINEL
7146};
7147
e2a1a461
RH		 7148static const ARMCPRegInfo vhe_reginfo[] = {
7149 { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
7150 .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
7151 .access = PL2_RW,
7152 .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
ed30da8e
RH		 7153 { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
7154 .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
7155 .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
7156 .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) },
8c94b071
RH		 7157#ifndef CONFIG_USER_ONLY
7158 { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64,
7159 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 2,
7160 .fieldoffset =
7161 offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval),
7162 .type = ARM_CP_IO, .access = PL2_RW,
7163 .writefn = gt_hv_cval_write, .raw_writefn = raw_write },
7164 { .name = "CNTHV_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
7165 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 0,
7166 .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
7167 .resetfn = gt_hv_timer_reset,
7168 .readfn = gt_hv_tval_read, .writefn = gt_hv_tval_write },
7169 { .name = "CNTHV_CTL_EL2", .state = ARM_CP_STATE_BOTH,
7170 .type = ARM_CP_IO,
7171 .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 1,
7172 .access = PL2_RW,
7173 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].ctl),
7174 .writefn = gt_hv_ctl_write, .raw_writefn = raw_write },
bb5972e4
RH		 7175 { .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64,
7176 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1,
7177 .type = ARM_CP_IO | ARM_CP_ALIAS,
7178 .access = PL2_RW, .accessfn = e2h_access,
7179 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
7180 .writefn = gt_phys_ctl_write, .raw_writefn = raw_write },
7181 { .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64,
7182 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1,
7183 .type = ARM_CP_IO | ARM_CP_ALIAS,
7184 .access = PL2_RW, .accessfn = e2h_access,
7185 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
7186 .writefn = gt_virt_ctl_write, .raw_writefn = raw_write },
7187 { .name = "CNTP_TVAL_EL02", .state = ARM_CP_STATE_AA64,
7188 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 0,
7189 .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS,
7190 .access = PL2_RW, .accessfn = e2h_access,
7191 .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write },
7192 { .name = "CNTV_TVAL_EL02", .state = ARM_CP_STATE_AA64,
7193 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 0,
7194 .type = ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS,
7195 .access = PL2_RW, .accessfn = e2h_access,
7196 .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write },
7197 { .name = "CNTP_CVAL_EL02", .state = ARM_CP_STATE_AA64,
7198 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 2,
7199 .type = ARM_CP_IO | ARM_CP_ALIAS,
7200 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
7201 .access = PL2_RW, .accessfn = e2h_access,
7202 .writefn = gt_phys_cval_write, .raw_writefn = raw_write },
7203 { .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64,
7204 .opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2,
7205 .type = ARM_CP_IO | ARM_CP_ALIAS,
7206 .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
7207 .access = PL2_RW, .accessfn = e2h_access,
7208 .writefn = gt_virt_cval_write, .raw_writefn = raw_write },
8c94b071 7209#endif
e2a1a461
RH		 7210 REGINFO_SENTINEL
7211};
7212
04b07d29
RH		 7213#ifndef CONFIG_USER_ONLY
7214static const ARMCPRegInfo ats1e1_reginfo[] = {
7215 { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
7216 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
7217 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
7218 .writefn = ats_write64 },
7219 { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
7220 .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
7221 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
7222 .writefn = ats_write64 },
7223 REGINFO_SENTINEL
7224};
7225
7226static const ARMCPRegInfo ats1cp_reginfo[] = {
7227 { .name = "ATS1CPRP",
7228 .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
7229 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
7230 .writefn = ats_write },
7231 { .name = "ATS1CPWP",
7232 .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
7233 .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
7234 .writefn = ats_write },
7235 REGINFO_SENTINEL
7236};
7237#endif
7238
f6287c24
PM		 7239/*
7240 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
7241 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
7242 * is non-zero, which is never for ARMv7, optionally in ARMv8
7243 * and mandatorily for ARMv8.2 and up.
7244 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
7245 * implementation is RAZ/WI we can ignore this detail, as we
7246 * do for ACTLR.
7247 */
7248static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = {
7249 { .name = "ACTLR2", .state = ARM_CP_STATE_AA32,
7250 .cp = 15, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 3,
99602377
RH		 7251 .access = PL1_RW, .accessfn = access_tacr,
7252 .type = ARM_CP_CONST, .resetvalue = 0 },
f6287c24
PM		 7253 { .name = "HACTLR2", .state = ARM_CP_STATE_AA32,
7254 .cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
7255 .access = PL2_RW, .type = ARM_CP_CONST,
7256 .resetvalue = 0 },
7257 REGINFO_SENTINEL
7258};
7259
2ceb98c0
PM		 7260void register_cp_regs_for_features(ARMCPU *cpu)
7261{
7262 /* Register all the coprocessor registers based on feature bits */
7263 CPUARMState *env = &cpu->env;
7264 if (arm_feature(env, ARM_FEATURE_M)) {
7265 /* M profile has no coprocessor registers */
7266 return;
7267 }
7268
e9aa6c21 7269 define_arm_cp_regs(cpu, cp_reginfo);
9449fdf6
PM		 7270 if (!arm_feature(env, ARM_FEATURE_V8)) {
7271 /* Must go early as it is full of wildcards that may be
7272 * overridden by later definitions.
7273 */
7274 define_arm_cp_regs(cpu, not_v8_cp_reginfo);
7275 }
7276
7d57f408 7277 if (arm_feature(env, ARM_FEATURE_V6)) {
8515a092
PM		 7278 /* The ID registers all have impdef reset values */
7279 ARMCPRegInfo v6_idregs[] = {
0ff644a7
PM		 7280 { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
7281 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
7282 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7283 .accessfn = access_aa32_tid3,
8a130a7b 7284 .resetvalue = cpu->isar.id_pfr0 },
96a8b92e
PM		 7285 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
7286 * the value of the GIC field until after we define these regs.
7287 */
0ff644a7
PM		 7288 { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
7289 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
96a8b92e 7290 .access = PL1_R, .type = ARM_CP_NO_RAW,
6a4ef4e5 7291 .accessfn = access_aa32_tid3,
96a8b92e
PM		 7292 .readfn = id_pfr1_read,
7293 .writefn = arm_cp_write_ignore },
0ff644a7
PM		 7294 { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
7295 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
7296 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7297 .accessfn = access_aa32_tid3,
a6179538 7298 .resetvalue = cpu->isar.id_dfr0 },
0ff644a7
PM		 7299 { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
7300 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
7301 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7302 .accessfn = access_aa32_tid3,
8515a092 7303 .resetvalue = cpu->id_afr0 },
0ff644a7
PM		 7304 { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
7305 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
7306 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7307 .accessfn = access_aa32_tid3,
10054016 7308 .resetvalue = cpu->isar.id_mmfr0 },
0ff644a7
PM		 7309 { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
7310 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
7311 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7312 .accessfn = access_aa32_tid3,
10054016 7313 .resetvalue = cpu->isar.id_mmfr1 },
0ff644a7
PM		 7314 { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
7315 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
7316 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7317 .accessfn = access_aa32_tid3,
10054016 7318 .resetvalue = cpu->isar.id_mmfr2 },
0ff644a7
PM		 7319 { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
7320 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
7321 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7322 .accessfn = access_aa32_tid3,
10054016 7323 .resetvalue = cpu->isar.id_mmfr3 },
0ff644a7
PM		 7324 { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
7325 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
7326 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7327 .accessfn = access_aa32_tid3,
47576b94 7328 .resetvalue = cpu->isar.id_isar0 },
0ff644a7
PM		 7329 { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
7330 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
7331 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7332 .accessfn = access_aa32_tid3,
47576b94 7333 .resetvalue = cpu->isar.id_isar1 },
0ff644a7
PM		 7334 { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
7335 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
7336 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7337 .accessfn = access_aa32_tid3,
47576b94 7338 .resetvalue = cpu->isar.id_isar2 },
0ff644a7
PM		 7339 { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
7340 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
7341 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7342 .accessfn = access_aa32_tid3,
47576b94 7343 .resetvalue = cpu->isar.id_isar3 },
0ff644a7
PM		 7344 { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
7345 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
7346 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7347 .accessfn = access_aa32_tid3,
47576b94 7348 .resetvalue = cpu->isar.id_isar4 },
0ff644a7
PM		 7349 { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
7350 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
7351 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7352 .accessfn = access_aa32_tid3,
47576b94 7353 .resetvalue = cpu->isar.id_isar5 },
e20d84c1
PM		 7354 { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
7355 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
7356 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7357 .accessfn = access_aa32_tid3,
10054016 7358 .resetvalue = cpu->isar.id_mmfr4 },
802abf40 7359 { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
e20d84c1
PM		 7360 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
7361 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7362 .accessfn = access_aa32_tid3,
47576b94 7363 .resetvalue = cpu->isar.id_isar6 },
8515a092
PM		 7364 REGINFO_SENTINEL
7365 };
7366 define_arm_cp_regs(cpu, v6_idregs);
7d57f408
PM		 7367 define_arm_cp_regs(cpu, v6_cp_reginfo);
7368 } else {
7369 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
7370 }
4d31c596
PM		 7371 if (arm_feature(env, ARM_FEATURE_V6K)) {
7372 define_arm_cp_regs(cpu, v6k_cp_reginfo);
7373 }
5e5cf9e3 7374 if (arm_feature(env, ARM_FEATURE_V7MP) &&
452a0955 7375 !arm_feature(env, ARM_FEATURE_PMSA)) {
995939a6
PM		 7376 define_arm_cp_regs(cpu, v7mp_cp_reginfo);
7377 }
327dd510
AL		 7378 if (arm_feature(env, ARM_FEATURE_V7VE)) {
7379 define_arm_cp_regs(cpu, pmovsset_cp_reginfo);
7380 }
e9aa6c21 7381 if (arm_feature(env, ARM_FEATURE_V7)) {
776d4e5c 7382 ARMCPRegInfo clidr = {
7da845b0
PM		 7383 .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
7384 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
630fcd4d
MZ		 7385 .access = PL1_R, .type = ARM_CP_CONST,
7386 .accessfn = access_aa64_tid2,
7387 .resetvalue = cpu->clidr
776d4e5c 7388 };
776d4e5c 7389 define_one_arm_cp_reg(cpu, &clidr);
e9aa6c21 7390 define_arm_cp_regs(cpu, v7_cp_reginfo);
50300698 7391 define_debug_regs(cpu);
24183fb6 7392 define_pmu_regs(cpu);
7d57f408
PM		 7393 } else {
7394 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
e9aa6c21 7395 }
b0d2b7d0 7396 if (arm_feature(env, ARM_FEATURE_V8)) {
e20d84c1
PM		 7397 /* AArch64 ID registers, which all have impdef reset values.
7398 * Note that within the ID register ranges the unused slots
7399 * must all RAZ, not UNDEF; future architecture versions may
7400 * define new registers here.
7401 */
e60cef86 7402 ARMCPRegInfo v8_idregs[] = {
976b99b6
AB		 7403 /*
7404 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
7405 * emulation because we don't know the right value for the
7406 * GIC field until after we define these regs.
96a8b92e 7407 */
e60cef86
PM		 7408 { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
7409 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
976b99b6
AB		 7410 .access = PL1_R,
7411#ifdef CONFIG_USER_ONLY
7412 .type = ARM_CP_CONST,
7413 .resetvalue = cpu->isar.id_aa64pfr0
7414#else
7415 .type = ARM_CP_NO_RAW,
6a4ef4e5 7416 .accessfn = access_aa64_tid3,
96a8b92e 7417 .readfn = id_aa64pfr0_read,
976b99b6
AB		 7418 .writefn = arm_cp_write_ignore
7419#endif
7420 },
e60cef86
PM		 7421 { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
7422 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
7423 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7424 .accessfn = access_aa64_tid3,
47576b94 7425 .resetvalue = cpu->isar.id_aa64pfr1},
e20d84c1
PM		 7426 { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7427 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
7428 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7429 .accessfn = access_aa64_tid3,
e20d84c1
PM		 7430 .resetvalue = 0 },
7431 { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7432 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
7433 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7434 .accessfn = access_aa64_tid3,
e20d84c1 7435 .resetvalue = 0 },
9516d772 7436 { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64,
e20d84c1
PM		 7437 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
7438 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7439 .accessfn = access_aa64_tid3,
9516d772 7440 /* At present, only SVEver == 0 is defined anyway. */
e20d84c1
PM		 7441 .resetvalue = 0 },
7442 { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7443 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
7444 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7445 .accessfn = access_aa64_tid3,
e20d84c1
PM		 7446 .resetvalue = 0 },
7447 { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7448 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
7449 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7450 .accessfn = access_aa64_tid3,
e20d84c1
PM		 7451 .resetvalue = 0 },
7452 { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7453 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
7454 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7455 .accessfn = access_aa64_tid3,
e20d84c1 7456 .resetvalue = 0 },
e60cef86
PM		 7457 { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
7458 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
7459 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7460 .accessfn = access_aa64_tid3,
2a609df8 7461 .resetvalue = cpu->isar.id_aa64dfr0 },
e60cef86
PM		 7462 { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
7463 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
7464 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7465 .accessfn = access_aa64_tid3,
2a609df8 7466 .resetvalue = cpu->isar.id_aa64dfr1 },
e20d84c1
PM		 7467 { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7468 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
7469 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7470 .accessfn = access_aa64_tid3,
e20d84c1
PM		 7471 .resetvalue = 0 },
7472 { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7473 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
7474 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7475 .accessfn = access_aa64_tid3,
e20d84c1 7476 .resetvalue = 0 },
e60cef86
PM		 7477 { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
7478 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
7479 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7480 .accessfn = access_aa64_tid3,
e60cef86
PM		 7481 .resetvalue = cpu->id_aa64afr0 },
7482 { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
7483 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
7484 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7485 .accessfn = access_aa64_tid3,
e60cef86 7486 .resetvalue = cpu->id_aa64afr1 },
e20d84c1
PM		 7487 { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7488 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
7489 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7490 .accessfn = access_aa64_tid3,
e20d84c1
PM		 7491 .resetvalue = 0 },
7492 { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7493 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
7494 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7495 .accessfn = access_aa64_tid3,
e20d84c1 7496 .resetvalue = 0 },
e60cef86
PM		 7497 { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
7498 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
7499 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7500 .accessfn = access_aa64_tid3,
47576b94 7501 .resetvalue = cpu->isar.id_aa64isar0 },
e60cef86
PM		 7502 { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
7503 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
7504 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7505 .accessfn = access_aa64_tid3,
47576b94 7506 .resetvalue = cpu->isar.id_aa64isar1 },
e20d84c1
PM		 7507 { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7508 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
7509 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7510 .accessfn = access_aa64_tid3,
e20d84c1
PM		 7511 .resetvalue = 0 },
7512 { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7513 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
7514 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7515 .accessfn = access_aa64_tid3,
e20d84c1
PM		 7516 .resetvalue = 0 },
7517 { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7518 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
7519 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7520 .accessfn = access_aa64_tid3,
e20d84c1
PM		 7521 .resetvalue = 0 },
7522 { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7523 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
7524 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7525 .accessfn = access_aa64_tid3,
e20d84c1
PM		 7526 .resetvalue = 0 },
7527 { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7528 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
7529 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7530 .accessfn = access_aa64_tid3,
e20d84c1
PM		 7531 .resetvalue = 0 },
7532 { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7533 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
7534 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7535 .accessfn = access_aa64_tid3,
e20d84c1 7536 .resetvalue = 0 },
e60cef86
PM		 7537 { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
7538 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
7539 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7540 .accessfn = access_aa64_tid3,
3dc91ddb 7541 .resetvalue = cpu->isar.id_aa64mmfr0 },
e60cef86
PM		 7542 { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
7543 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
7544 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7545 .accessfn = access_aa64_tid3,
3dc91ddb 7546 .resetvalue = cpu->isar.id_aa64mmfr1 },
64761e10 7547 { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64,
e20d84c1
PM		 7548 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
7549 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7550 .accessfn = access_aa64_tid3,
64761e10 7551 .resetvalue = cpu->isar.id_aa64mmfr2 },
e20d84c1
PM		 7552 { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7553 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
7554 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7555 .accessfn = access_aa64_tid3,
e20d84c1
PM		 7556 .resetvalue = 0 },
7557 { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7558 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
7559 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7560 .accessfn = access_aa64_tid3,
e20d84c1
PM		 7561 .resetvalue = 0 },
7562 { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7563 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
7564 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7565 .accessfn = access_aa64_tid3,
e20d84c1
PM		 7566 .resetvalue = 0 },
7567 { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7568 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
7569 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7570 .accessfn = access_aa64_tid3,
e20d84c1
PM		 7571 .resetvalue = 0 },
7572 { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7573 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
7574 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7575 .accessfn = access_aa64_tid3,
e20d84c1 7576 .resetvalue = 0 },
a50c0f51
PM		 7577 { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
7578 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
7579 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7580 .accessfn = access_aa64_tid3,
47576b94 7581 .resetvalue = cpu->isar.mvfr0 },
a50c0f51
PM		 7582 { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
7583 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
7584 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7585 .accessfn = access_aa64_tid3,
47576b94 7586 .resetvalue = cpu->isar.mvfr1 },
a50c0f51
PM		 7587 { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
7588 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
7589 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7590 .accessfn = access_aa64_tid3,
47576b94 7591 .resetvalue = cpu->isar.mvfr2 },
e20d84c1
PM		 7592 { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7593 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
7594 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7595 .accessfn = access_aa64_tid3,
e20d84c1
PM		 7596 .resetvalue = 0 },
7597 { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7598 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
7599 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7600 .accessfn = access_aa64_tid3,
e20d84c1
PM		 7601 .resetvalue = 0 },
7602 { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7603 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
7604 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7605 .accessfn = access_aa64_tid3,
e20d84c1
PM		 7606 .resetvalue = 0 },
7607 { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7608 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
7609 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7610 .accessfn = access_aa64_tid3,
e20d84c1
PM		 7611 .resetvalue = 0 },
7612 { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
7613 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
7614 .access = PL1_R, .type = ARM_CP_CONST,
6a4ef4e5 7615 .accessfn = access_aa64_tid3,
e20d84c1 7616 .resetvalue = 0 },
4054bfa9
AF		 7617 { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
7618 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
7619 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
cad86737 7620 .resetvalue = extract64(cpu->pmceid0, 0, 32) },
4054bfa9
AF		 7621 { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
7622 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
7623 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
7624 .resetvalue = cpu->pmceid0 },
7625 { .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
7626 .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
7627 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
cad86737 7628 .resetvalue = extract64(cpu->pmceid1, 0, 32) },
4054bfa9
AF		 7629 { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
7630 .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
7631 .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
7632 .resetvalue = cpu->pmceid1 },
e60cef86
PM		 7633 REGINFO_SENTINEL
7634 };
6c5c0fec
AB		 7635#ifdef CONFIG_USER_ONLY
7636 ARMCPRegUserSpaceInfo v8_user_idregs[] = {
7637 { .name = "ID_AA64PFR0_EL1",
7638 .exported_bits = 0x000f000f00ff0000,
7639 .fixed_bits = 0x0000000000000011 },
7640 { .name = "ID_AA64PFR1_EL1",
7641 .exported_bits = 0x00000000000000f0 },
d040242e
AB		 7642 { .name = "ID_AA64PFR*_EL1_RESERVED",
7643 .is_glob = true },
6c5c0fec
AB		 7644 { .name = "ID_AA64ZFR0_EL1" },
7645 { .name = "ID_AA64MMFR0_EL1",
7646 .fixed_bits = 0x00000000ff000000 },
7647 { .name = "ID_AA64MMFR1_EL1" },
d040242e
AB		 7648 { .name = "ID_AA64MMFR*_EL1_RESERVED",
7649 .is_glob = true },
6c5c0fec
AB		 7650 { .name = "ID_AA64DFR0_EL1",
7651 .fixed_bits = 0x0000000000000006 },
7652 { .name = "ID_AA64DFR1_EL1" },
d040242e
AB		 7653 { .name = "ID_AA64DFR*_EL1_RESERVED",
7654 .is_glob = true },
7655 { .name = "ID_AA64AFR*",
7656 .is_glob = true },
6c5c0fec
AB		 7657 { .name = "ID_AA64ISAR0_EL1",
7658 .exported_bits = 0x00fffffff0fffff0 },
7659 { .name = "ID_AA64ISAR1_EL1",
7660 .exported_bits = 0x000000f0ffffffff },
d040242e
AB		 7661 { .name = "ID_AA64ISAR*_EL1_RESERVED",
7662 .is_glob = true },
6c5c0fec
AB		 7663 REGUSERINFO_SENTINEL
7664 };
7665 modify_arm_cp_regs(v8_idregs, v8_user_idregs);
7666#endif
be8e8128
GB		 7667 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
7668 if (!arm_feature(env, ARM_FEATURE_EL3) &&
7669 !arm_feature(env, ARM_FEATURE_EL2)) {
7670 ARMCPRegInfo rvbar = {
7671 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
7672 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
7673 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
7674 };
7675 define_one_arm_cp_reg(cpu, &rvbar);
7676 }
e60cef86 7677 define_arm_cp_regs(cpu, v8_idregs);
b0d2b7d0
PM		 7678 define_arm_cp_regs(cpu, v8_cp_reginfo);
7679 }
3b685ba7 7680 if (arm_feature(env, ARM_FEATURE_EL2)) {
f0d574d6 7681 uint64_t vmpidr_def = mpidr_read_val(env);
731de9e6
EI		 7682 ARMCPRegInfo vpidr_regs[] = {
7683 { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
7684 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
7685 .access = PL2_RW, .accessfn = access_el3_aa32ns,
36476562
PM		 7686 .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
7687 .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
731de9e6
EI		 7688 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
7689 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
7690 .access = PL2_RW, .resetvalue = cpu->midr,
7691 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
f0d574d6
EI		 7692 { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
7693 .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
7694 .access = PL2_RW, .accessfn = access_el3_aa32ns,
36476562
PM		 7695 .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
7696 .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
f0d574d6
EI		 7697 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
7698 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
7699 .access = PL2_RW,
7700 .resetvalue = vmpidr_def,
7701 .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
731de9e6
EI		 7702 REGINFO_SENTINEL
7703 };
7704 define_arm_cp_regs(cpu, vpidr_regs);
4771cd01 7705 define_arm_cp_regs(cpu, el2_cp_reginfo);
ce4afed8
PM		 7706 if (arm_feature(env, ARM_FEATURE_V8)) {
7707 define_arm_cp_regs(cpu, el2_v8_cp_reginfo);
7708 }
be8e8128
GB		 7709 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
7710 if (!arm_feature(env, ARM_FEATURE_EL3)) {
7711 ARMCPRegInfo rvbar = {
7712 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
7713 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
7714 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
7715 };
7716 define_one_arm_cp_reg(cpu, &rvbar);
7717 }
d42e3c26
EI		 7718 } else {
7719 /* If EL2 is missing but higher ELs are enabled, we need to
7720 * register the no_el2 reginfos.
7721 */
7722 if (arm_feature(env, ARM_FEATURE_EL3)) {
f0d574d6
EI		 7723 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
7724 * of MIDR_EL1 and MPIDR_EL1.
731de9e6
EI		 7725 */
7726 ARMCPRegInfo vpidr_regs[] = {
7727 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
7728 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
93dd1e61 7729 .access = PL2_RW, .accessfn = access_el3_aa32ns,
731de9e6
EI		 7730 .type = ARM_CP_CONST, .resetvalue = cpu->midr,
7731 .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
f0d574d6
EI		 7732 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
7733 .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
93dd1e61 7734 .access = PL2_RW, .accessfn = access_el3_aa32ns,
f0d574d6
EI		 7735 .type = ARM_CP_NO_RAW,
7736 .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
731de9e6
EI		 7737 REGINFO_SENTINEL
7738 };
7739 define_arm_cp_regs(cpu, vpidr_regs);
4771cd01 7740 define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
ce4afed8
PM		 7741 if (arm_feature(env, ARM_FEATURE_V8)) {
7742 define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
7743 }
d42e3c26 7744 }
3b685ba7 7745 }
81547d66 7746 if (arm_feature(env, ARM_FEATURE_EL3)) {
0f1a3b24 7747 define_arm_cp_regs(cpu, el3_cp_reginfo);
e24fdd23
PM		 7748 ARMCPRegInfo el3_regs[] = {
7749 { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
7750 .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
7751 .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar },
7752 { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
7753 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
7754 .access = PL3_RW,
7755 .raw_writefn = raw_write, .writefn = sctlr_write,
7756 .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
7757 .resetvalue = cpu->reset_sctlr },
7758 REGINFO_SENTINEL
be8e8128 7759 };
e24fdd23
PM		 7760
7761 define_arm_cp_regs(cpu, el3_regs);
81547d66 7762 }
2f027fc5
PM		 7763 /* The behaviour of NSACR is sufficiently various that we don't
7764 * try to describe it in a single reginfo:
7765 * if EL3 is 64 bit, then trap to EL3 from S EL1,
7766 * reads as constant 0xc00 from NS EL1 and NS EL2
7767 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
7768 * if v7 without EL3, register doesn't exist
7769 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
7770 */
7771 if (arm_feature(env, ARM_FEATURE_EL3)) {
7772 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
7773 ARMCPRegInfo nsacr = {
7774 .name = "NSACR", .type = ARM_CP_CONST,
7775 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
7776 .access = PL1_RW, .accessfn = nsacr_access,
7777 .resetvalue = 0xc00
7778 };
7779 define_one_arm_cp_reg(cpu, &nsacr);
7780 } else {
7781 ARMCPRegInfo nsacr = {
7782 .name = "NSACR",
7783 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
7784 .access = PL3_RW | PL1_R,
7785 .resetvalue = 0,
7786 .fieldoffset = offsetof(CPUARMState, cp15.nsacr)
7787 };
7788 define_one_arm_cp_reg(cpu, &nsacr);
7789 }
7790 } else {
7791 if (arm_feature(env, ARM_FEATURE_V8)) {
7792 ARMCPRegInfo nsacr = {
7793 .name = "NSACR", .type = ARM_CP_CONST,
7794 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
7795 .access = PL1_R,
7796 .resetvalue = 0xc00
7797 };
7798 define_one_arm_cp_reg(cpu, &nsacr);
7799 }
7800 }
7801
452a0955 7802 if (arm_feature(env, ARM_FEATURE_PMSA)) {
6cb0b013
PC		 7803 if (arm_feature(env, ARM_FEATURE_V6)) {
7804 /* PMSAv6 not implemented */
7805 assert(arm_feature(env, ARM_FEATURE_V7));
7806 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
7807 define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
7808 } else {
7809 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
7810 }
18032bec 7811 } else {
8e5d75c9 7812 define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
18032bec 7813 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
4036b7d1
PM		 7814 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
7815 if (cpu_isar_feature(aa32_hpd, cpu)) {
ab638a32
RH		 7816 define_one_arm_cp_reg(cpu, &ttbcr2_reginfo);
7817 }
18032bec 7818 }
c326b979
PM		 7819 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
7820 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
7821 }
6cc7a3ae
PM		 7822 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
7823 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
7824 }
4a501606
PM		 7825 if (arm_feature(env, ARM_FEATURE_VAPA)) {
7826 define_arm_cp_regs(cpu, vapa_cp_reginfo);
7827 }
c4804214
PM		 7828 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
7829 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
7830 }
7831 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
7832 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
7833 }
7834 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
7835 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
7836 }
18032bec
PM		 7837 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
7838 define_arm_cp_regs(cpu, omap_cp_reginfo);
7839 }
34f90529
PM		 7840 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
7841 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
7842 }
1047b9d7
PM		 7843 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
7844 define_arm_cp_regs(cpu, xscale_cp_reginfo);
7845 }
7846 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
7847 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
7848 }
7ac681cf
PM		 7849 if (arm_feature(env, ARM_FEATURE_LPAE)) {
7850 define_arm_cp_regs(cpu, lpae_cp_reginfo);
7851 }
873b73c0 7852 if (cpu_isar_feature(aa32_jazelle, cpu)) {
f96f3d5f
MZ		 7853 define_arm_cp_regs(cpu, jazelle_regs);
7854 }
7884849c
PM		 7855 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
7856 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
7857 * be read-only (ie write causes UNDEF exception).
7858 */
7859 {
00a29f3d
PM		 7860 ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
7861 /* Pre-v8 MIDR space.
7862 * Note that the MIDR isn't a simple constant register because
7884849c
PM		 7863 * of the TI925 behaviour where writes to another register can
7864 * cause the MIDR value to change.
97ce8d61
PC		 7865 *
7866 * Unimplemented registers in the c15 0 0 0 space default to
7867 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
7868 * and friends override accordingly.
7884849c
PM		 7869 */
7870 { .name = "MIDR",
97ce8d61 7871 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
7884849c 7872 .access = PL1_R, .resetvalue = cpu->midr,
d4e6df63 7873 .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
731de9e6 7874 .readfn = midr_read,
97ce8d61
PC		 7875 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
7876 .type = ARM_CP_OVERRIDE },
7884849c
PM		 7877 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
7878 { .name = "DUMMY",
7879 .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
7880 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7881 { .name = "DUMMY",
7882 .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
7883 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7884 { .name = "DUMMY",
7885 .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
7886 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7887 { .name = "DUMMY",
7888 .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
7889 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7890 { .name = "DUMMY",
7891 .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
7892 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7893 REGINFO_SENTINEL
7894 };
00a29f3d 7895 ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
00a29f3d
PM		 7896 { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
7897 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
731de9e6
EI		 7898 .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
7899 .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
7900 .readfn = midr_read },
ac00c79f
SF		 7901 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
7902 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
7903 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
7904 .access = PL1_R, .resetvalue = cpu->midr },
7905 { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
7906 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
7907 .access = PL1_R, .resetvalue = cpu->midr },
00a29f3d
PM		 7908 { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
7909 .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
93fbc983
MZ		 7910 .access = PL1_R,
7911 .accessfn = access_aa64_tid1,
7912 .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
00a29f3d
PM		 7913 REGINFO_SENTINEL
7914 };
7915 ARMCPRegInfo id_cp_reginfo[] = {
7916 /* These are common to v8 and pre-v8 */
7917 { .name = "CTR",
7918 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
630fcd4d
MZ		 7919 .access = PL1_R, .accessfn = ctr_el0_access,
7920 .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
00a29f3d
PM		 7921 { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
7922 .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
7923 .access = PL0_R, .accessfn = ctr_el0_access,
7924 .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
7925 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
7926 { .name = "TCMTR",
7927 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
93fbc983
MZ		 7928 .access = PL1_R,
7929 .accessfn = access_aa32_tid1,
7930 .type = ARM_CP_CONST, .resetvalue = 0 },
00a29f3d
PM		 7931 REGINFO_SENTINEL
7932 };
8085ce63
PC		 7933 /* TLBTR is specific to VMSA */
7934 ARMCPRegInfo id_tlbtr_reginfo = {
7935 .name = "TLBTR",
7936 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
93fbc983
MZ		 7937 .access = PL1_R,
7938 .accessfn = access_aa32_tid1,
7939 .type = ARM_CP_CONST, .resetvalue = 0,
8085ce63 7940 };
3281af81
PC		 7941 /* MPUIR is specific to PMSA V6+ */
7942 ARMCPRegInfo id_mpuir_reginfo = {
7943 .name = "MPUIR",
7944 .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
7945 .access = PL1_R, .type = ARM_CP_CONST,
7946 .resetvalue = cpu->pmsav7_dregion << 8
7947 };
7884849c
PM		 7948 ARMCPRegInfo crn0_wi_reginfo = {
7949 .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
7950 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
7951 .type = ARM_CP_NOP | ARM_CP_OVERRIDE
7952 };
6c5c0fec
AB		 7953#ifdef CONFIG_USER_ONLY
7954 ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
7955 { .name = "MIDR_EL1",
7956 .exported_bits = 0x00000000ffffffff },
7957 { .name = "REVIDR_EL1" },
7958 REGUSERINFO_SENTINEL
7959 };
7960 modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
7961#endif
7884849c
PM		 7962 if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
7963 arm_feature(env, ARM_FEATURE_STRONGARM)) {
7964 ARMCPRegInfo *r;
7965 /* Register the blanket "writes ignored" value first to cover the
a703eda1
PC		 7966 * whole space. Then update the specific ID registers to allow write
7967 * access, so that they ignore writes rather than causing them to
7968 * UNDEF.
7884849c
PM		 7969 */
7970 define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
00a29f3d
PM		 7971 for (r = id_pre_v8_midr_cp_reginfo;
7972 r->type != ARM_CP_SENTINEL; r++) {
7973 r->access = PL1_RW;
7974 }
7884849c
PM		 7975 for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
7976 r->access = PL1_RW;
7884849c 7977 }
10006112 7978 id_mpuir_reginfo.access = PL1_RW;
3281af81 7979 id_tlbtr_reginfo.access = PL1_RW;
7884849c 7980 }
00a29f3d
PM		 7981 if (arm_feature(env, ARM_FEATURE_V8)) {
7982 define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
7983 } else {
7984 define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
7985 }
a703eda1 7986 define_arm_cp_regs(cpu, id_cp_reginfo);
452a0955 7987 if (!arm_feature(env, ARM_FEATURE_PMSA)) {
8085ce63 7988 define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
3281af81
PC		 7989 } else if (arm_feature(env, ARM_FEATURE_V7)) {
7990 define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
8085ce63 7991 }
7884849c
PM		 7992 }
7993
97ce8d61 7994 if (arm_feature(env, ARM_FEATURE_MPIDR)) {
52264166
AB		 7995 ARMCPRegInfo mpidr_cp_reginfo[] = {
7996 { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
7997 .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
7998 .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
7999 REGINFO_SENTINEL
8000 };
8001#ifdef CONFIG_USER_ONLY
8002 ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
8003 { .name = "MPIDR_EL1",
8004 .fixed_bits = 0x0000000080000000 },
8005 REGUSERINFO_SENTINEL
8006 };
8007 modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo);
8008#endif
97ce8d61
PC		 8009 define_arm_cp_regs(cpu, mpidr_cp_reginfo);
8010 }
8011
2771db27 8012 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
834a6c69
PM		 8013 ARMCPRegInfo auxcr_reginfo[] = {
8014 { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
8015 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
99602377
RH		 8016 .access = PL1_RW, .accessfn = access_tacr,
8017 .type = ARM_CP_CONST, .resetvalue = cpu->reset_auxcr },
834a6c69
PM		 8018 { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
8019 .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
8020 .access = PL2_RW, .type = ARM_CP_CONST,
8021 .resetvalue = 0 },
8022 { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
8023 .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
8024 .access = PL3_RW, .type = ARM_CP_CONST,
8025 .resetvalue = 0 },
8026 REGINFO_SENTINEL
2771db27 8027 };
834a6c69 8028 define_arm_cp_regs(cpu, auxcr_reginfo);
f6287c24
PM		 8029 if (cpu_isar_feature(aa32_ac2, cpu)) {
8030 define_arm_cp_regs(cpu, actlr2_hactlr2_reginfo);
0e0456ab 8031 }
2771db27
PM		 8032 }
8033
d8ba780b 8034 if (arm_feature(env, ARM_FEATURE_CBAR)) {
d56974af
LM		 8035 /*
8036 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
8037 * There are two flavours:
8038 * (1) older 32-bit only cores have a simple 32-bit CBAR
8039 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
8040 * 32-bit register visible to AArch32 at a different encoding
8041 * to the "flavour 1" register and with the bits rearranged to
8042 * be able to squash a 64-bit address into the 32-bit view.
8043 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
8044 * in future if we support AArch32-only configs of some of the
8045 * AArch64 cores we might need to add a specific feature flag
8046 * to indicate cores with "flavour 2" CBAR.
8047 */
f318cec6
PM		 8048 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
8049 /* 32 bit view is [31:18] 0...0 [43:32]. */
8050 uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
8051 | extract64(cpu->reset_cbar, 32, 12);
8052 ARMCPRegInfo cbar_reginfo[] = {
8053 { .name = "CBAR",
8054 .type = ARM_CP_CONST,
d56974af
LM		 8055 .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0,
8056 .access = PL1_R, .resetvalue = cbar32 },
f318cec6
PM		 8057 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
8058 .type = ARM_CP_CONST,
8059 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
d56974af 8060 .access = PL1_R, .resetvalue = cpu->reset_cbar },
f318cec6
PM		 8061 REGINFO_SENTINEL
8062 };
8063 /* We don't implement a r/w 64 bit CBAR currently */
8064 assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
8065 define_arm_cp_regs(cpu, cbar_reginfo);
8066 } else {
8067 ARMCPRegInfo cbar = {
8068 .name = "CBAR",
8069 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
8070 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
8071 .fieldoffset = offsetof(CPUARMState,
8072 cp15.c15_config_base_address)
8073 };
8074 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
8075 cbar.access = PL1_R;
8076 cbar.fieldoffset = 0;
8077 cbar.type = ARM_CP_CONST;
8078 }
8079 define_one_arm_cp_reg(cpu, &cbar);
8080 }
d8ba780b
PC		 8081 }
8082
91db4642
CLG		 8083 if (arm_feature(env, ARM_FEATURE_VBAR)) {
8084 ARMCPRegInfo vbar_cp_reginfo[] = {
8085 { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
8086 .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
8087 .access = PL1_RW, .writefn = vbar_write,
8088 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
8089 offsetof(CPUARMState, cp15.vbar_ns) },
8090 .resetvalue = 0 },
8091 REGINFO_SENTINEL
8092 };
8093 define_arm_cp_regs(cpu, vbar_cp_reginfo);
8094 }
8095
2771db27
PM		 8096 /* Generic registers whose values depend on the implementation */
8097 {
8098 ARMCPRegInfo sctlr = {
5ebafdf3 8099 .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
137feaa9 8100 .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
84929218 8101 .access = PL1_RW, .accessfn = access_tvm_trvm,
137feaa9
FA		 8102 .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
8103 offsetof(CPUARMState, cp15.sctlr_ns) },
d4e6df63
PM		 8104 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
8105 .raw_writefn = raw_write,
2771db27
PM		 8106 };
8107 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
8108 /* Normally we would always end the TB on an SCTLR write, but Linux
8109 * arch/arm/mach-pxa/sleep.S expects two instructions following
8110 * an MMU enable to execute from cache. Imitate this behaviour.
8111 */
8112 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
8113 }
8114 define_one_arm_cp_reg(cpu, &sctlr);
8115 }
5be5e8ed 8116
2d7137c1 8117 if (cpu_isar_feature(aa64_lor, cpu)) {
2d7137c1
RH		 8118 define_arm_cp_regs(cpu, lor_reginfo);
8119 }
220f508f
RH		 8120 if (cpu_isar_feature(aa64_pan, cpu)) {
8121 define_one_arm_cp_reg(cpu, &pan_reginfo);
8122 }
04b07d29
RH		 8123#ifndef CONFIG_USER_ONLY
8124 if (cpu_isar_feature(aa64_ats1e1, cpu)) {
8125 define_arm_cp_regs(cpu, ats1e1_reginfo);
8126 }
8127 if (cpu_isar_feature(aa32_ats1e1, cpu)) {
8128 define_arm_cp_regs(cpu, ats1cp_reginfo);
8129 }
8130#endif
9eeb7a1c
RH		 8131 if (cpu_isar_feature(aa64_uao, cpu)) {
8132 define_one_arm_cp_reg(cpu, &uao_reginfo);
8133 }
2d7137c1 8134
e2a1a461
RH		 8135 if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
8136 define_arm_cp_regs(cpu, vhe_reginfo);
8137 }
8138
cd208a1c 8139 if (cpu_isar_feature(aa64_sve, cpu)) {
5be5e8ed
RH		 8140 define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
8141 if (arm_feature(env, ARM_FEATURE_EL2)) {
8142 define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
8143 } else {
8144 define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
8145 }
8146 if (arm_feature(env, ARM_FEATURE_EL3)) {
8147 define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
8148 }
8149 }
967aa94f
RH		 8150
8151#ifdef TARGET_AARCH64
8152 if (cpu_isar_feature(aa64_pauth, cpu)) {
8153 define_arm_cp_regs(cpu, pauth_reginfo);
8154 }
de390645
RH		 8155 if (cpu_isar_feature(aa64_rndr, cpu)) {
8156 define_arm_cp_regs(cpu, rndr_reginfo);
8157 }
0d57b499
BM		 8158#ifndef CONFIG_USER_ONLY
8159 /* Data Cache clean instructions up to PoP */
8160 if (cpu_isar_feature(aa64_dcpop, cpu)) {
8161 define_one_arm_cp_reg(cpu, dcpop_reg);
8162
8163 if (cpu_isar_feature(aa64_dcpodp, cpu)) {
8164 define_one_arm_cp_reg(cpu, dcpodp_reg);
8165 }
8166 }
8167#endif /*CONFIG_USER_ONLY*/
4b779ceb
RH		 8168
8169 /*
8170 * If full MTE is enabled, add all of the system registers.
8171 * If only "instructions available at EL0" are enabled,
8172 * then define only a RAZ/WI version of PSTATE.TCO.
8173 */
8174 if (cpu_isar_feature(aa64_mte, cpu)) {
8175 define_arm_cp_regs(cpu, mte_reginfo);
5463df16 8176 define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
4b779ceb
RH		 8177 } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) {
8178 define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
5463df16 8179 define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
4b779ceb 8180 }
967aa94f 8181#endif
cb570bd3 8182
22e57073 8183 if (cpu_isar_feature(any_predinv, cpu)) {
cb570bd3
RH		 8184 define_arm_cp_regs(cpu, predinv_reginfo);
8185 }
e2cce18f 8186
957e6155
PM		 8187 if (cpu_isar_feature(any_ccidx, cpu)) {
8188 define_arm_cp_regs(cpu, ccsidr2_reginfo);
8189 }
8190
e2cce18f
RH		 8191#ifndef CONFIG_USER_ONLY
8192 /*
8193 * Register redirections and aliases must be done last,
8194 * after the registers from the other extensions have been defined.
8195 */
8196 if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
8197 define_arm_vh_e2h_redirects_aliases(cpu);
8198 }
8199#endif
2ceb98c0
PM		 8200}
8201
14969266
AF		 8202void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
8203{
22169d41 8204 CPUState *cs = CPU(cpu);
14969266
AF		 8205 CPUARMState *env = &cpu->env;
8206
6a669427 8207 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
d12379c5
AB		 8208 /*
8209 * The lower part of each SVE register aliases to the FPU
8210 * registers so we don't need to include both.
8211 */
8212#ifdef TARGET_AARCH64
8213 if (isar_feature_aa64_sve(&cpu->isar)) {
8214 gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
8215 arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
8216 "sve-registers.xml", 0);
8217 } else
8218#endif
8219 {
8220 gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
8221 aarch64_fpu_gdb_set_reg,
8222 34, "aarch64-fpu.xml", 0);
8223 }
6a669427 8224 } else if (arm_feature(env, ARM_FEATURE_NEON)) {
22169d41 8225 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
56aebc89 8226 51, "arm-neon.xml", 0);
a6627f5f 8227 } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
22169d41 8228 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
56aebc89 8229 35, "arm-vfp3.xml", 0);
7fbc6a40 8230 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
22169d41 8231 gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
56aebc89
PB		 8232 19, "arm-vfp.xml", 0);
8233 }
200bf5b7 8234 gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
32d6e32a 8235 arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
200bf5b7 8236 "system-registers.xml", 0);
d12379c5 8237
40f137e1
PB		 8238}
8239
777dc784
PM		 8240/* Sort alphabetically by type name, except for "any". */
8241static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
5adb4839 8242{
777dc784
PM		 8243 ObjectClass *class_a = (ObjectClass *)a;
8244 ObjectClass *class_b = (ObjectClass *)b;
8245 const char *name_a, *name_b;
5adb4839 8246
777dc784
PM		 8247 name_a = object_class_get_name(class_a);
8248 name_b = object_class_get_name(class_b);
51492fd1 8249 if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
777dc784 8250 return 1;
51492fd1 8251 } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
777dc784
PM		 8252 return -1;
8253 } else {
8254 return strcmp(name_a, name_b);
5adb4839
PB		 8255 }
8256}
8257
777dc784 8258static void arm_cpu_list_entry(gpointer data, gpointer user_data)
40f137e1 8259{
777dc784 8260 ObjectClass *oc = data;
51492fd1
AF		 8261 const char *typename;
8262 char *name;
3371d272 8263
51492fd1
AF		 8264 typename = object_class_get_name(oc);
8265 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
0442428a 8266 qemu_printf(" %s\n", name);
51492fd1 8267 g_free(name);
777dc784
PM		 8268}
8269
0442428a 8270void arm_cpu_list(void)
777dc784 8271{
777dc784
PM		 8272 GSList *list;
8273
8274 list = object_class_get_list(TYPE_ARM_CPU, false);
8275 list = g_slist_sort(list, arm_cpu_list_compare);
0442428a
MA		 8276 qemu_printf("Available CPUs:\n");
8277 g_slist_foreach(list, arm_cpu_list_entry, NULL);
777dc784 8278 g_slist_free(list);
40f137e1
PB		 8279}
8280
78027bb6
CR		 8281static void arm_cpu_add_definition(gpointer data, gpointer user_data)
8282{
8283 ObjectClass *oc = data;
8284 CpuDefinitionInfoList **cpu_list = user_data;
78027bb6
CR		 8285 CpuDefinitionInfo *info;
8286 const char *typename;
8287
8288 typename = object_class_get_name(oc);
8289 info = g_malloc0(sizeof(*info));
8290 info->name = g_strndup(typename,
8291 strlen(typename) - strlen("-" TYPE_ARM_CPU));
8ed877b7 8292 info->q_typename = g_strdup(typename);
78027bb6 8293
54aa3de7 8294 QAPI_LIST_PREPEND(*cpu_list, info);
78027bb6
CR		 8295}
8296
25a9d6ca 8297CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
78027bb6
CR		 8298{
8299 CpuDefinitionInfoList *cpu_list = NULL;
8300 GSList *list;
8301
8302 list = object_class_get_list(TYPE_ARM_CPU, false);
8303 g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
8304 g_slist_free(list);
8305
8306 return cpu_list;
8307}
8308
6e6efd61 8309static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
51a79b03 8310 void *opaque, int state, int secstate,
9c513e78
AB		 8311 int crm, int opc1, int opc2,
8312 const char *name)
6e6efd61
PM		 8313{
8314 /* Private utility function for define_one_arm_cp_reg_with_opaque():
8315 * add a single reginfo struct to the hash table.
8316 */
8317 uint32_t *key = g_new(uint32_t, 1);
8318 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
8319 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
3f3c82a5
FA		 8320 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
8321
9c513e78 8322 r2->name = g_strdup(name);
3f3c82a5
FA		 8323 /* Reset the secure state to the specific incoming state. This is
8324 * necessary as the register may have been defined with both states.
8325 */
8326 r2->secure = secstate;
8327
8328 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
8329 /* Register is banked (using both entries in array).
8330 * Overwriting fieldoffset as the array is only used to define
8331 * banked registers but later only fieldoffset is used.
f5a0a5a5 8332 */
3f3c82a5
FA		 8333 r2->fieldoffset = r->bank_fieldoffsets[ns];
8334 }
8335
8336 if (state == ARM_CP_STATE_AA32) {
8337 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
8338 /* If the register is banked then we don't need to migrate or
8339 * reset the 32-bit instance in certain cases:
8340 *
8341 * 1) If the register has both 32-bit and 64-bit instances then we
8342 * can count on the 64-bit instance taking care of the
8343 * non-secure bank.
8344 * 2) If ARMv8 is enabled then we can count on a 64-bit version
8345 * taking care of the secure bank. This requires that separate
8346 * 32 and 64-bit definitions are provided.
8347 */
8348 if ((r->state == ARM_CP_STATE_BOTH && ns) ||
8349 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
7a0e58fa 8350 r2->type |= ARM_CP_ALIAS;
3f3c82a5
FA		 8351 }
8352 } else if ((secstate != r->secure) && !ns) {
8353 /* The register is not banked so we only want to allow migration of
8354 * the non-secure instance.
8355 */
7a0e58fa 8356 r2->type |= ARM_CP_ALIAS;
58a1d8ce 8357 }
3f3c82a5
FA		 8358
8359 if (r->state == ARM_CP_STATE_BOTH) {
8360 /* We assume it is a cp15 register if the .cp field is left unset.
8361 */
8362 if (r2->cp == 0) {
8363 r2->cp = 15;
8364 }
8365
f5a0a5a5 8366#ifdef HOST_WORDS_BIGENDIAN
3f3c82a5
FA		 8367 if (r2->fieldoffset) {
8368 r2->fieldoffset += sizeof(uint32_t);
8369 }
f5a0a5a5 8370#endif
3f3c82a5 8371 }
f5a0a5a5
PM		 8372 }
8373 if (state == ARM_CP_STATE_AA64) {
8374 /* To allow abbreviation of ARMCPRegInfo
8375 * definitions, we treat cp == 0 as equivalent to
8376 * the value for "standard guest-visible sysreg".
58a1d8ce
PM		 8377 * STATE_BOTH definitions are also always "standard
8378 * sysreg" in their AArch64 view (the .cp value may
8379 * be non-zero for the benefit of the AArch32 view).
f5a0a5a5 8380 */
58a1d8ce 8381 if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
f5a0a5a5
PM		 8382 r2->cp = CP_REG_ARM64_SYSREG_CP;
8383 }
8384 *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
8385 r2->opc0, opc1, opc2);
8386 } else {
51a79b03 8387 *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
f5a0a5a5 8388 }
6e6efd61
PM		 8389 if (opaque) {
8390 r2->opaque = opaque;
8391 }
67ed771d
PM		 8392 /* reginfo passed to helpers is correct for the actual access,
8393 * and is never ARM_CP_STATE_BOTH:
8394 */
8395 r2->state = state;
6e6efd61
PM		 8396 /* Make sure reginfo passed to helpers for wildcarded regs
8397 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
8398 */
8399 r2->crm = crm;
8400 r2->opc1 = opc1;
8401 r2->opc2 = opc2;
8402 /* By convention, for wildcarded registers only the first
8403 * entry is used for migration; the others are marked as
7a0e58fa 8404 * ALIAS so we don't try to transfer the register
6e6efd61 8405 * multiple times. Special registers (ie NOP/WFI) are
7a0e58fa 8406 * never migratable and not even raw-accessible.
6e6efd61 8407 */
7a0e58fa
PM		 8408 if ((r->type & ARM_CP_SPECIAL)) {
8409 r2->type |= ARM_CP_NO_RAW;
8410 }
8411 if (((r->crm == CP_ANY) && crm != 0) ||
6e6efd61
PM		 8412 ((r->opc1 == CP_ANY) && opc1 != 0) ||
8413 ((r->opc2 == CP_ANY) && opc2 != 0)) {
1f163787 8414 r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
6e6efd61
PM		 8415 }
8416
375421cc
PM		 8417 /* Check that raw accesses are either forbidden or handled. Note that
8418 * we can't assert this earlier because the setup of fieldoffset for
8419 * banked registers has to be done first.
8420 */
8421 if (!(r2->type & ARM_CP_NO_RAW)) {
8422 assert(!raw_accessors_invalid(r2));
8423 }
8424
6e6efd61
PM		 8425 /* Overriding of an existing definition must be explicitly
8426 * requested.
8427 */
8428 if (!(r->type & ARM_CP_OVERRIDE)) {
8429 ARMCPRegInfo *oldreg;
8430 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
8431 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
8432 fprintf(stderr, "Register redefined: cp=%d %d bit "
8433 "crn=%d crm=%d opc1=%d opc2=%d, "
8434 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
8435 r2->crn, r2->crm, r2->opc1, r2->opc2,
8436 oldreg->name, r2->name);
8437 g_assert_not_reached();
8438 }
8439 }
8440 g_hash_table_insert(cpu->cp_regs, key, r2);
8441}
8442
8443
4b6a83fb
PM		 8444void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
8445 const ARMCPRegInfo *r, void *opaque)
8446{
8447 /* Define implementations of coprocessor registers.
8448 * We store these in a hashtable because typically
8449 * there are less than 150 registers in a space which
8450 * is 16*16*16*8*8 = 262144 in size.
8451 * Wildcarding is supported for the crm, opc1 and opc2 fields.
8452 * If a register is defined twice then the second definition is
8453 * used, so this can be used to define some generic registers and
8454 * then override them with implementation specific variations.
8455 * At least one of the original and the second definition should
8456 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
8457 * against accidental use.
f5a0a5a5
PM		 8458 *
8459 * The state field defines whether the register is to be
8460 * visible in the AArch32 or AArch64 execution state. If the
8461 * state is set to ARM_CP_STATE_BOTH then we synthesise a
8462 * reginfo structure for the AArch32 view, which sees the lower
8463 * 32 bits of the 64 bit register.
8464 *
8465 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
8466 * be wildcarded. AArch64 registers are always considered to be 64
8467 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
8468 * the register, if any.
4b6a83fb 8469 */
f5a0a5a5 8470 int crm, opc1, opc2, state;
4b6a83fb
PM		 8471 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
8472 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
8473 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
8474 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
8475 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
8476 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
8477 /* 64 bit registers have only CRm and Opc1 fields */
8478 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
f5a0a5a5
PM		 8479 /* op0 only exists in the AArch64 encodings */
8480 assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
8481 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
8482 assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
cd8be50e
PM		 8483 /*
8484 * This API is only for Arm's system coprocessors (14 and 15) or
8485 * (M-profile or v7A-and-earlier only) for implementation defined
8486 * coprocessors in the range 0..7. Our decode assumes this, since
8487 * 8..13 can be used for other insns including VFP and Neon. See
8488 * valid_cp() in translate.c. Assert here that we haven't tried
8489 * to use an invalid coprocessor number.
8490 */
8491 switch (r->state) {
8492 case ARM_CP_STATE_BOTH:
8493 /* 0 has a special meaning, but otherwise the same rules as AA32. */
8494 if (r->cp == 0) {
8495 break;
8496 }
8497 /* fall through */
8498 case ARM_CP_STATE_AA32:
8499 if (arm_feature(&cpu->env, ARM_FEATURE_V8) &&
8500 !arm_feature(&cpu->env, ARM_FEATURE_M)) {
8501 assert(r->cp >= 14 && r->cp <= 15);
8502 } else {
8503 assert(r->cp < 8 || (r->cp >= 14 && r->cp <= 15));
8504 }
8505 break;
8506 case ARM_CP_STATE_AA64:
8507 assert(r->cp == 0 || r->cp == CP_REG_ARM64_SYSREG_CP);
8508 break;
8509 default:
8510 g_assert_not_reached();
8511 }
f5a0a5a5
PM		 8512 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
8513 * encodes a minimum access level for the register. We roll this
8514 * runtime check into our general permission check code, so check
8515 * here that the reginfo's specified permissions are strict enough
8516 * to encompass the generic architectural permission check.
8517 */
8518 if (r->state != ARM_CP_STATE_AA32) {
8519 int mask = 0;
8520 switch (r->opc1) {
b5bd7440
AB		 8521 case 0:
8522 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
8523 mask = PL0U_R | PL1_RW;
8524 break;
8525 case 1: case 2:
f5a0a5a5
PM		 8526 /* min_EL EL1 */
8527 mask = PL1_RW;
8528 break;
8529 case 3:
8530 /* min_EL EL0 */
8531 mask = PL0_RW;
8532 break;
8533 case 4:
b4ecf60f 8534 case 5:
f5a0a5a5
PM		 8535 /* min_EL EL2 */
8536 mask = PL2_RW;
8537 break;
f5a0a5a5
PM		 8538 case 6:
8539 /* min_EL EL3 */
8540 mask = PL3_RW;
8541 break;
8542 case 7:
8543 /* min_EL EL1, secure mode only (we don't check the latter) */
8544 mask = PL1_RW;
8545 break;
8546 default:
8547 /* broken reginfo with out-of-range opc1 */
8548 assert(false);
8549 break;
8550 }
8551 /* assert our permissions are not too lax (stricter is fine) */
8552 assert((r->access & ~mask) == 0);
8553 }
8554
4b6a83fb
PM		 8555 /* Check that the register definition has enough info to handle
8556 * reads and writes if they are permitted.
8557 */
8558 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
8559 if (r->access & PL3_R) {
3f3c82a5
FA		 8560 assert((r->fieldoffset ||
8561 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
8562 r->readfn);
4b6a83fb
PM		 8563 }
8564 if (r->access & PL3_W) {
3f3c82a5
FA		 8565 assert((r->fieldoffset ||
8566 (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
8567 r->writefn);
4b6a83fb
PM		 8568 }
8569 }
8570 /* Bad type field probably means missing sentinel at end of reg list */
8571 assert(cptype_valid(r->type));
8572 for (crm = crmmin; crm <= crmmax; crm++) {
8573 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
8574 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
f5a0a5a5
PM		 8575 for (state = ARM_CP_STATE_AA32;
8576 state <= ARM_CP_STATE_AA64; state++) {
8577 if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
8578 continue;
8579 }
3f3c82a5
FA		 8580 if (state == ARM_CP_STATE_AA32) {
8581 /* Under AArch32 CP registers can be common
8582 * (same for secure and non-secure world) or banked.
8583 */
9c513e78
AB		 8584 char *name;
8585
3f3c82a5
FA		 8586 switch (r->secure) {
8587 case ARM_CP_SECSTATE_S:
8588 case ARM_CP_SECSTATE_NS:
8589 add_cpreg_to_hashtable(cpu, r, opaque, state,
9c513e78
AB		 8590 r->secure, crm, opc1, opc2,
8591 r->name);
3f3c82a5
FA		 8592 break;
8593 default:
9c513e78 8594 name = g_strdup_printf("%s_S", r->name);
3f3c82a5
FA		 8595 add_cpreg_to_hashtable(cpu, r, opaque, state,
8596 ARM_CP_SECSTATE_S,
9c513e78
AB		 8597 crm, opc1, opc2, name);
8598 g_free(name);
3f3c82a5
FA		 8599 add_cpreg_to_hashtable(cpu, r, opaque, state,
8600 ARM_CP_SECSTATE_NS,
9c513e78 8601 crm, opc1, opc2, r->name);
3f3c82a5
FA		 8602 break;
8603 }
8604 } else {
8605 /* AArch64 registers get mapped to non-secure instance
8606 * of AArch32 */
8607 add_cpreg_to_hashtable(cpu, r, opaque, state,
8608 ARM_CP_SECSTATE_NS,
9c513e78 8609 crm, opc1, opc2, r->name);
3f3c82a5 8610 }
f5a0a5a5 8611 }
4b6a83fb
PM		 8612 }
8613 }
8614 }
8615}
8616
8617void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
8618 const ARMCPRegInfo *regs, void *opaque)
8619{
8620 /* Define a whole list of registers */
8621 const ARMCPRegInfo *r;
8622 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
8623 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
8624 }
8625}
8626
6c5c0fec
AB		 8627/*
8628 * Modify ARMCPRegInfo for access from userspace.
8629 *
8630 * This is a data driven modification directed by
8631 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
8632 * user-space cannot alter any values and dynamic values pertaining to
8633 * execution state are hidden from user space view anyway.
8634 */
8635void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods)
8636{
8637 const ARMCPRegUserSpaceInfo *m;
8638 ARMCPRegInfo *r;
8639
8640 for (m = mods; m->name; m++) {
d040242e
AB		 8641 GPatternSpec *pat = NULL;
8642 if (m->is_glob) {
8643 pat = g_pattern_spec_new(m->name);
8644 }
6c5c0fec 8645 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
d040242e
AB		 8646 if (pat && g_pattern_match_string(pat, r->name)) {
8647 r->type = ARM_CP_CONST;
8648 r->access = PL0U_R;
8649 r->resetvalue = 0;
8650 /* continue */
8651 } else if (strcmp(r->name, m->name) == 0) {
6c5c0fec
AB		 8652 r->type = ARM_CP_CONST;
8653 r->access = PL0U_R;
8654 r->resetvalue &= m->exported_bits;
8655 r->resetvalue |= m->fixed_bits;
8656 break;
8657 }
8658 }
d040242e
AB		 8659 if (pat) {
8660 g_pattern_spec_free(pat);
8661 }
6c5c0fec
AB		 8662 }
8663}
8664
60322b39 8665const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
4b6a83fb 8666{
60322b39 8667 return g_hash_table_lookup(cpregs, &encoded_cp);
4b6a83fb
PM		 8668}
8669
c4241c7d
PM		 8670void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
8671 uint64_t value)
4b6a83fb
PM		 8672{
8673 /* Helper coprocessor write function for write-ignore registers */
4b6a83fb
PM		 8674}
8675
c4241c7d 8676uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
4b6a83fb
PM		 8677{
8678 /* Helper coprocessor write function for read-as-zero registers */
4b6a83fb
PM		 8679 return 0;
8680}
8681
f5a0a5a5
PM		 8682void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
8683{
8684 /* Helper coprocessor reset function for do-nothing-on-reset registers */
8685}
8686
af393ffc 8687static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
37064a8b
PM		 8688{
8689 /* Return true if it is not valid for us to switch to
8690 * this CPU mode (ie all the UNPREDICTABLE cases in
8691 * the ARM ARM CPSRWriteByInstr pseudocode).
8692 */
af393ffc
PM		 8693
8694 /* Changes to or from Hyp via MSR and CPS are illegal. */
8695 if (write_type == CPSRWriteByInstr &&
8696 ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP ||
8697 mode == ARM_CPU_MODE_HYP)) {
8698 return 1;
8699 }
8700
37064a8b
PM		 8701 switch (mode) {
8702 case ARM_CPU_MODE_USR:
10eacda7 8703 return 0;
37064a8b
PM		 8704 case ARM_CPU_MODE_SYS:
8705 case ARM_CPU_MODE_SVC:
8706 case ARM_CPU_MODE_ABT:
8707 case ARM_CPU_MODE_UND:
8708 case ARM_CPU_MODE_IRQ:
8709 case ARM_CPU_MODE_FIQ:
52ff951b
PM		 8710 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
8711 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
8712 */
10eacda7
PM		 8713 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
8714 * and CPS are treated as illegal mode changes.
8715 */
8716 if (write_type == CPSRWriteByInstr &&
10eacda7 8717 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON &&
7c208e0f 8718 (arm_hcr_el2_eff(env) & HCR_TGE)) {
10eacda7
PM		 8719 return 1;
8720 }
37064a8b 8721 return 0;
e6c8fc07
PM		 8722 case ARM_CPU_MODE_HYP:
8723 return !arm_feature(env, ARM_FEATURE_EL2)
2d2a4549 8724 || arm_current_el(env) < 2 || arm_is_secure_below_el3(env);
027fc527 8725 case ARM_CPU_MODE_MON:
58ae2d1f 8726 return arm_current_el(env) < 3;
37064a8b
PM		 8727 default:
8728 return 1;
8729 }
8730}
8731
2f4a40e5
AZ		 8732uint32_t cpsr_read(CPUARMState *env)
8733{
8734 int ZF;
6fbe23d5
PB		 8735 ZF = (env->ZF == 0);
8736 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 8737 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
8738 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
8739 | ((env->condexec_bits & 0xfc) << 8)
af519934 8740 | (env->GE << 16) | (env->daif & CPSR_AIF);
2f4a40e5
AZ		 8741}
8742
50866ba5
PM		 8743void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
8744 CPSRWriteType write_type)
2f4a40e5 8745{
6e8801f9
FA		 8746 uint32_t changed_daif;
8747
2f4a40e5 8748 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 8749 env->ZF = (~val) & CPSR_Z;
8750 env->NF = val;
2f4a40e5
AZ		 8751 env->CF = (val >> 29) & 1;
8752 env->VF = (val << 3) & 0x80000000;
8753 }
8754 if (mask & CPSR_Q)
8755 env->QF = ((val & CPSR_Q) != 0);
8756 if (mask & CPSR_T)
8757 env->thumb = ((val & CPSR_T) != 0);
8758 if (mask & CPSR_IT_0_1) {
8759 env->condexec_bits &= ~3;
8760 env->condexec_bits |= (val >> 25) & 3;
8761 }
8762 if (mask & CPSR_IT_2_7) {
8763 env->condexec_bits &= 3;
8764 env->condexec_bits |= (val >> 8) & 0xfc;
8765 }
8766 if (mask & CPSR_GE) {
8767 env->GE = (val >> 16) & 0xf;
8768 }
8769
6e8801f9
FA		 8770 /* In a V7 implementation that includes the security extensions but does
8771 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
8772 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
8773 * bits respectively.
8774 *
8775 * In a V8 implementation, it is permitted for privileged software to
8776 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
8777 */
f8c88bbc 8778 if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) &&
6e8801f9
FA		 8779 arm_feature(env, ARM_FEATURE_EL3) &&
8780 !arm_feature(env, ARM_FEATURE_EL2) &&
8781 !arm_is_secure(env)) {
8782
8783 changed_daif = (env->daif ^ val) & mask;
8784
8785 if (changed_daif & CPSR_A) {
8786 /* Check to see if we are allowed to change the masking of async
8787 * abort exceptions from a non-secure state.
8788 */
8789 if (!(env->cp15.scr_el3 & SCR_AW)) {
8790 qemu_log_mask(LOG_GUEST_ERROR,
8791 "Ignoring attempt to switch CPSR_A flag from "
8792 "non-secure world with SCR.AW bit clear\n");
8793 mask &= ~CPSR_A;
8794 }
8795 }
8796
8797 if (changed_daif & CPSR_F) {
8798 /* Check to see if we are allowed to change the masking of FIQ
8799 * exceptions from a non-secure state.
8800 */
8801 if (!(env->cp15.scr_el3 & SCR_FW)) {
8802 qemu_log_mask(LOG_GUEST_ERROR,
8803 "Ignoring attempt to switch CPSR_F flag from "
8804 "non-secure world with SCR.FW bit clear\n");
8805 mask &= ~CPSR_F;
8806 }
8807
8808 /* Check whether non-maskable FIQ (NMFI) support is enabled.
8809 * If this bit is set software is not allowed to mask
8810 * FIQs, but is allowed to set CPSR_F to 0.
8811 */
8812 if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
8813 (val & CPSR_F)) {
8814 qemu_log_mask(LOG_GUEST_ERROR,
8815 "Ignoring attempt to enable CPSR_F flag "
8816 "(non-maskable FIQ [NMFI] support enabled)\n");
8817 mask &= ~CPSR_F;
8818 }
8819 }
8820 }
8821
4cc35614
PM		 8822 env->daif &= ~(CPSR_AIF & mask);
8823 env->daif |= val & CPSR_AIF & mask;
8824
f8c88bbc
PM		 8825 if (write_type != CPSRWriteRaw &&
8826 ((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
8c4f0eb9
PM		 8827 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) {
8828 /* Note that we can only get here in USR mode if this is a
8829 * gdb stub write; for this case we follow the architectural
8830 * behaviour for guest writes in USR mode of ignoring an attempt
8831 * to switch mode. (Those are caught by translate.c for writes
8832 * triggered by guest instructions.)
8833 */
8834 mask &= ~CPSR_M;
8835 } else if (bad_mode_switch(env, val & CPSR_M, write_type)) {
81907a58
PM		 8836 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
8837 * v7, and has defined behaviour in v8:
8838 * + leave CPSR.M untouched
8839 * + allow changes to the other CPSR fields
8840 * + set PSTATE.IL
8841 * For user changes via the GDB stub, we don't set PSTATE.IL,
8842 * as this would be unnecessarily harsh for a user error.
37064a8b
PM		 8843 */
8844 mask &= ~CPSR_M;
81907a58
PM		 8845 if (write_type != CPSRWriteByGDBStub &&
8846 arm_feature(env, ARM_FEATURE_V8)) {
8847 mask |= CPSR_IL;
8848 val |= CPSR_IL;
8849 }
81e37284
PM		 8850 qemu_log_mask(LOG_GUEST_ERROR,
8851 "Illegal AArch32 mode switch attempt from %s to %s\n",
8852 aarch32_mode_name(env->uncached_cpsr),
8853 aarch32_mode_name(val));
37064a8b 8854 } else {
81e37284
PM		 8855 qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n",
8856 write_type == CPSRWriteExceptionReturn ?
8857 "Exception return from AArch32" :
8858 "AArch32 mode switch from",
8859 aarch32_mode_name(env->uncached_cpsr),
8860 aarch32_mode_name(val), env->regs[15]);
37064a8b
PM		 8861 switch_mode(env, val & CPSR_M);
8862 }
2f4a40e5
AZ		 8863 }
8864 mask &= ~CACHED_CPSR_BITS;
8865 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
8866}
8867
b26eefb6
PB		 8868/* Sign/zero extend */
8869uint32_t HELPER(sxtb16)(uint32_t x)
8870{
8871 uint32_t res;
8872 res = (uint16_t)(int8_t)x;
8873 res |= (uint32_t)(int8_t)(x >> 16) << 16;
8874 return res;
8875}
8876
8877uint32_t HELPER(uxtb16)(uint32_t x)
8878{
8879 uint32_t res;
8880 res = (uint16_t)(uint8_t)x;
8881 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
8882 return res;
8883}
8884
3670669c
PB		 8885int32_t HELPER(sdiv)(int32_t num, int32_t den)
8886{
8887 if (den == 0)
8888 return 0;
686eeb93
AJ		 8889 if (num == INT_MIN && den == -1)
8890 return INT_MIN;
3670669c
PB		 8891 return num / den;
8892}
8893
8894uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
8895{
8896 if (den == 0)
8897 return 0;
8898 return num / den;
8899}
8900
8901uint32_t HELPER(rbit)(uint32_t x)
8902{
42fedbca 8903 return revbit32(x);
3670669c
PB		 8904}
8905
c47eaf9f 8906#ifdef CONFIG_USER_ONLY
b5ff1b31 8907
affdb64d 8908static void switch_mode(CPUARMState *env, int mode)
b5ff1b31 8909{
2fc0cc0e 8910 ARMCPU *cpu = env_archcpu(env);
a47dddd7
AF		 8911
8912 if (mode != ARM_CPU_MODE_USR) {
8913 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
8914 }
b5ff1b31
FB		 8915}
8916
012a906b
GB		 8917uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
8918 uint32_t cur_el, bool secure)
9e729b57
EI		 8919{
8920 return 1;
8921}
8922
ce02049d
GB		 8923void aarch64_sync_64_to_32(CPUARMState *env)
8924{
8925 g_assert_not_reached();
8926}
8927
b5ff1b31
FB		 8928#else
8929
affdb64d 8930static void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 8931{
8932 int old_mode;
8933 int i;
8934
8935 old_mode = env->uncached_cpsr & CPSR_M;
8936 if (mode == old_mode)
8937 return;
8938
8939 if (old_mode == ARM_CPU_MODE_FIQ) {
8940 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 8941 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 8942 } else if (mode == ARM_CPU_MODE_FIQ) {
8943 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 8944 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 8945 }
8946
f5206413 8947 i = bank_number(old_mode);
b5ff1b31 8948 env->banked_r13[i] = env->regs[13];
b5ff1b31
FB		 8949 env->banked_spsr[i] = env->spsr;
8950
f5206413 8951 i = bank_number(mode);
b5ff1b31 8952 env->regs[13] = env->banked_r13[i];
b5ff1b31 8953 env->spsr = env->banked_spsr[i];
593cfa2b
PM		 8954
8955 env->banked_r14[r14_bank_number(old_mode)] = env->regs[14];
8956 env->regs[14] = env->banked_r14[r14_bank_number(mode)];
b5ff1b31
FB		 8957}
8958
0eeb17d6
GB		 8959/* Physical Interrupt Target EL Lookup Table
8960 *
8961 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
8962 *
8963 * The below multi-dimensional table is used for looking up the target
8964 * exception level given numerous condition criteria. Specifically, the
8965 * target EL is based on SCR and HCR routing controls as well as the
8966 * currently executing EL and secure state.
8967 *
8968 * Dimensions:
8969 * target_el_table[2][2][2][2][2][4]
8970 * | | | | | +--- Current EL
8971 * | | | | +------ Non-secure(0)/Secure(1)
8972 * | | | +--------- HCR mask override
8973 * | | +------------ SCR exec state control
8974 * | +--------------- SCR mask override
8975 * +------------------ 32-bit(0)/64-bit(1) EL3
8976 *
8977 * The table values are as such:
8978 * 0-3 = EL0-EL3
8979 * -1 = Cannot occur
8980 *
8981 * The ARM ARM target EL table includes entries indicating that an "exception
8982 * is not taken". The two cases where this is applicable are:
8983 * 1) An exception is taken from EL3 but the SCR does not have the exception
8984 * routed to EL3.
8985 * 2) An exception is taken from EL2 but the HCR does not have the exception
8986 * routed to EL2.
8987 * In these two cases, the below table contain a target of EL1. This value is
8988 * returned as it is expected that the consumer of the table data will check
8989 * for "target EL >= current EL" to ensure the exception is not taken.
8990 *
8991 * SCR HCR
8992 * 64 EA AMO From
8993 * BIT IRQ IMO Non-secure Secure
8994 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
8995 */
82c39f6a 8996static const int8_t target_el_table[2][2][2][2][2][4] = {
0eeb17d6
GB		 8997 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
8998 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
8999 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
9000 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
9001 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9002 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
9003 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
9004 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
9005 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
9006 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
9007 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
9008 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
9009 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
9010 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
9011 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
9012 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
9013};
9014
9015/*
9016 * Determine the target EL for physical exceptions
9017 */
012a906b
GB		 9018uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
9019 uint32_t cur_el, bool secure)
0eeb17d6
GB		 9020{
9021 CPUARMState *env = cs->env_ptr;
f7778444
RH		 9022 bool rw;
9023 bool scr;
9024 bool hcr;
0eeb17d6 9025 int target_el;
2cde031f 9026 /* Is the highest EL AArch64? */
f7778444
RH		 9027 bool is64 = arm_feature(env, ARM_FEATURE_AARCH64);
9028 uint64_t hcr_el2;
2cde031f
SS		 9029
9030 if (arm_feature(env, ARM_FEATURE_EL3)) {
9031 rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
9032 } else {
9033 /* Either EL2 is the highest EL (and so the EL2 register width
9034 * is given by is64); or there is no EL2 or EL3, in which case
9035 * the value of 'rw' does not affect the table lookup anyway.
9036 */
9037 rw = is64;
9038 }
0eeb17d6 9039
f7778444 9040 hcr_el2 = arm_hcr_el2_eff(env);
0eeb17d6
GB		 9041 switch (excp_idx) {
9042 case EXCP_IRQ:
9043 scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
f7778444 9044 hcr = hcr_el2 & HCR_IMO;
0eeb17d6
GB		 9045 break;
9046 case EXCP_FIQ:
9047 scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
f7778444 9048 hcr = hcr_el2 & HCR_FMO;
0eeb17d6
GB		 9049 break;
9050 default:
9051 scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
f7778444 9052 hcr = hcr_el2 & HCR_AMO;
0eeb17d6
GB		 9053 break;
9054 };
9055
d1b31428
RH		 9056 /*
9057 * For these purposes, TGE and AMO/IMO/FMO both force the
9058 * interrupt to EL2. Fold TGE into the bit extracted above.
9059 */
9060 hcr |= (hcr_el2 & HCR_TGE) != 0;
9061
0eeb17d6
GB		 9062 /* Perform a table-lookup for the target EL given the current state */
9063 target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
9064
9065 assert(target_el > 0);
9066
9067 return target_el;
9068}
9069
b59f479b
PMD		 9070void arm_log_exception(int idx)
9071{
9072 if (qemu_loglevel_mask(CPU_LOG_INT)) {
9073 const char *exc = NULL;
9074 static const char * const excnames[] = {
9075 [EXCP_UDEF] = "Undefined Instruction",
9076 [EXCP_SWI] = "SVC",
9077 [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
9078 [EXCP_DATA_ABORT] = "Data Abort",
9079 [EXCP_IRQ] = "IRQ",
9080 [EXCP_FIQ] = "FIQ",
9081 [EXCP_BKPT] = "Breakpoint",
9082 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
9083 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
9084 [EXCP_HVC] = "Hypervisor Call",
9085 [EXCP_HYP_TRAP] = "Hypervisor Trap",
9086 [EXCP_SMC] = "Secure Monitor Call",
9087 [EXCP_VIRQ] = "Virtual IRQ",
9088 [EXCP_VFIQ] = "Virtual FIQ",
9089 [EXCP_SEMIHOST] = "Semihosting call",
9090 [EXCP_NOCP] = "v7M NOCP UsageFault",
9091 [EXCP_INVSTATE] = "v7M INVSTATE UsageFault",
9092 [EXCP_STKOF] = "v8M STKOF UsageFault",
9093 [EXCP_LAZYFP] = "v7M exception during lazy FP stacking",
9094 [EXCP_LSERR] = "v8M LSERR UsageFault",
9095 [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
9096 };
9097
9098 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
9099 exc = excnames[idx];
9100 }
9101 if (!exc) {
9102 exc = "unknown";
9103 }
9104 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
9105 }
9106}
9107
a356dacf 9108/*
7aab5a8c
PMD		 9109 * Function used to synchronize QEMU's AArch64 register set with AArch32
9110 * register set. This is necessary when switching between AArch32 and AArch64
9111 * execution state.
a356dacf 9112 */
7aab5a8c 9113void aarch64_sync_32_to_64(CPUARMState *env)
9ee6e8bb 9114{
7aab5a8c
PMD		 9115 int i;
9116 uint32_t mode = env->uncached_cpsr & CPSR_M;
9117
9118 /* We can blanket copy R[0:7] to X[0:7] */
9119 for (i = 0; i < 8; i++) {
9120 env->xregs[i] = env->regs[i];
fd592d89 9121 }
70d74660 9122
9a223097 9123 /*
7aab5a8c
PMD		 9124 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
9125 * Otherwise, they come from the banked user regs.
fd592d89 9126 */
7aab5a8c
PMD		 9127 if (mode == ARM_CPU_MODE_FIQ) {
9128 for (i = 8; i < 13; i++) {
9129 env->xregs[i] = env->usr_regs[i - 8];
9130 }
9131 } else {
9132 for (i = 8; i < 13; i++) {
9133 env->xregs[i] = env->regs[i];
9134 }
fd592d89 9135 }
9ee6e8bb 9136
7aab5a8c
PMD		 9137 /*
9138 * Registers x13-x23 are the various mode SP and FP registers. Registers
9139 * r13 and r14 are only copied if we are in that mode, otherwise we copy
9140 * from the mode banked register.
9141 */
9142 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
9143 env->xregs[13] = env->regs[13];
9144 env->xregs[14] = env->regs[14];
9145 } else {
9146 env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
9147 /* HYP is an exception in that it is copied from r14 */
9148 if (mode == ARM_CPU_MODE_HYP) {
9149 env->xregs[14] = env->regs[14];
95695eff 9150 } else {
7aab5a8c 9151 env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)];
95695eff 9152 }
95695eff
PM		 9153 }
9154
7aab5a8c
PMD		 9155 if (mode == ARM_CPU_MODE_HYP) {
9156 env->xregs[15] = env->regs[13];
9157 } else {
9158 env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
95695eff
PM		 9159 }
9160
7aab5a8c
PMD		 9161 if (mode == ARM_CPU_MODE_IRQ) {
9162 env->xregs[16] = env->regs[14];
9163 env->xregs[17] = env->regs[13];
9164 } else {
9165 env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)];
9166 env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
9167 }
95695eff 9168
7aab5a8c
PMD		 9169 if (mode == ARM_CPU_MODE_SVC) {
9170 env->xregs[18] = env->regs[14];
9171 env->xregs[19] = env->regs[13];
9172 } else {
9173 env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)];
9174 env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
9175 }
95695eff 9176
7aab5a8c
PMD		 9177 if (mode == ARM_CPU_MODE_ABT) {
9178 env->xregs[20] = env->regs[14];
9179 env->xregs[21] = env->regs[13];
9180 } else {
9181 env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)];
9182 env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
9183 }
e33cf0f8 9184
7aab5a8c
PMD		 9185 if (mode == ARM_CPU_MODE_UND) {
9186 env->xregs[22] = env->regs[14];
9187 env->xregs[23] = env->regs[13];
9188 } else {
9189 env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)];
9190 env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
e33cf0f8
PM		 9191 }
9192
9193 /*
7aab5a8c
PMD		 9194 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9195 * mode, then we can copy from r8-r14. Otherwise, we copy from the
9196 * FIQ bank for r8-r14.
e33cf0f8 9197 */
7aab5a8c
PMD		 9198 if (mode == ARM_CPU_MODE_FIQ) {
9199 for (i = 24; i < 31; i++) {
9200 env->xregs[i] = env->regs[i - 16]; /* X[24:30] <- R[8:14] */
9201 }
9202 } else {
9203 for (i = 24; i < 29; i++) {
9204 env->xregs[i] = env->fiq_regs[i - 24];
e33cf0f8 9205 }
7aab5a8c
PMD		 9206 env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
9207 env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)];
e33cf0f8 9208 }
7aab5a8c
PMD		 9209
9210 env->pc = env->regs[15];
e33cf0f8
PM		 9211}
9212
9a223097 9213/*
7aab5a8c
PMD		 9214 * Function used to synchronize QEMU's AArch32 register set with AArch64
9215 * register set. This is necessary when switching between AArch32 and AArch64
9216 * execution state.
de2db7ec 9217 */
7aab5a8c 9218void aarch64_sync_64_to_32(CPUARMState *env)
9ee6e8bb 9219{
7aab5a8c
PMD		 9220 int i;
9221 uint32_t mode = env->uncached_cpsr & CPSR_M;
abc24d86 9222
7aab5a8c
PMD		 9223 /* We can blanket copy X[0:7] to R[0:7] */
9224 for (i = 0; i < 8; i++) {
9225 env->regs[i] = env->xregs[i];
de2db7ec 9226 }
3f0cddee 9227
9a223097 9228 /*
7aab5a8c
PMD		 9229 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
9230 * Otherwise, we copy x8-x12 into the banked user regs.
de2db7ec 9231 */
7aab5a8c
PMD		 9232 if (mode == ARM_CPU_MODE_FIQ) {
9233 for (i = 8; i < 13; i++) {
9234 env->usr_regs[i - 8] = env->xregs[i];
9235 }
9236 } else {
9237 for (i = 8; i < 13; i++) {
9238 env->regs[i] = env->xregs[i];
9239 }
fb602cb7
PM		 9240 }
9241
9a223097 9242 /*
7aab5a8c
PMD		 9243 * Registers r13 & r14 depend on the current mode.
9244 * If we are in a given mode, we copy the corresponding x registers to r13
9245 * and r14. Otherwise, we copy the x register to the banked r13 and r14
9246 * for the mode.
fb602cb7 9247 */
7aab5a8c
PMD		 9248 if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
9249 env->regs[13] = env->xregs[13];
9250 env->regs[14] = env->xregs[14];
fb602cb7 9251 } else {
7aab5a8c 9252 env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
fb602cb7 9253
7aab5a8c
PMD		 9254 /*
9255 * HYP is an exception in that it does not have its own banked r14 but
9256 * shares the USR r14
9257 */
9258 if (mode == ARM_CPU_MODE_HYP) {
9259 env->regs[14] = env->xregs[14];
9260 } else {
9261 env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
9262 }
9263 }
fb602cb7 9264
7aab5a8c
PMD		 9265 if (mode == ARM_CPU_MODE_HYP) {
9266 env->regs[13] = env->xregs[15];
fb602cb7 9267 } else {
7aab5a8c 9268 env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
fb602cb7 9269 }
d02a8698 9270
7aab5a8c
PMD		 9271 if (mode == ARM_CPU_MODE_IRQ) {
9272 env->regs[14] = env->xregs[16];
9273 env->regs[13] = env->xregs[17];
d02a8698 9274 } else {
7aab5a8c
PMD		 9275 env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
9276 env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
d02a8698
PM		 9277 }
9278
7aab5a8c
PMD		 9279 if (mode == ARM_CPU_MODE_SVC) {
9280 env->regs[14] = env->xregs[18];
9281 env->regs[13] = env->xregs[19];
9282 } else {
9283 env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
9284 env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
fb602cb7
PM		 9285 }
9286
7aab5a8c
PMD		 9287 if (mode == ARM_CPU_MODE_ABT) {
9288 env->regs[14] = env->xregs[20];
9289 env->regs[13] = env->xregs[21];
9290 } else {
9291 env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
9292 env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
ce02049d
GB		 9293 }
9294
9295 if (mode == ARM_CPU_MODE_UND) {
3a9148d0
SS		 9296 env->regs[14] = env->xregs[22];
9297 env->regs[13] = env->xregs[23];
ce02049d 9298 } else {
593cfa2b 9299 env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
3a9148d0 9300 env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
ce02049d
GB		 9301 }
9302
9303 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
9304 * mode, then we can copy to r8-r14. Otherwise, we copy to the
9305 * FIQ bank for r8-r14.
9306 */
9307 if (mode == ARM_CPU_MODE_FIQ) {
9308 for (i = 24; i < 31; i++) {
9309 env->regs[i - 16] = env->xregs[i]; /* X[24:30] -> R[8:14] */
9310 }
9311 } else {
9312 for (i = 24; i < 29; i++) {
9313 env->fiq_regs[i - 24] = env->xregs[i];
9314 }
9315 env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
593cfa2b 9316 env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
ce02049d
GB		 9317 }
9318
9319 env->regs[15] = env->pc;
9320}
9321
dea8378b
PM		 9322static void take_aarch32_exception(CPUARMState *env, int new_mode,
9323 uint32_t mask, uint32_t offset,
9324 uint32_t newpc)
9325{
4a2696c0
RH		 9326 int new_el;
9327
dea8378b
PM		 9328 /* Change the CPU state so as to actually take the exception. */
9329 switch_mode(env, new_mode);
4a2696c0 9330
dea8378b
PM		 9331 /*
9332 * For exceptions taken to AArch32 we must clear the SS bit in both
9333 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
9334 */
9335 env->uncached_cpsr &= ~PSTATE_SS;
9336 env->spsr = cpsr_read(env);
9337 /* Clear IT bits. */
9338 env->condexec_bits = 0;
9339 /* Switch to the new mode, and to the correct instruction set. */
9340 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
88828bf1
CD		 9341
9342 /* This must be after mode switching. */
9343 new_el = arm_current_el(env);
9344
dea8378b
PM		 9345 /* Set new mode endianness */
9346 env->uncached_cpsr &= ~CPSR_E;
4a2696c0 9347 if (env->cp15.sctlr_el[new_el] & SCTLR_EE) {
dea8378b
PM		 9348 env->uncached_cpsr |= CPSR_E;
9349 }
829f9fd3
PM		 9350 /* J and IL must always be cleared for exception entry */
9351 env->uncached_cpsr &= ~(CPSR_IL | CPSR_J);
dea8378b
PM		 9352 env->daif |= mask;
9353
9354 if (new_mode == ARM_CPU_MODE_HYP) {
9355 env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0;
9356 env->elr_el[2] = env->regs[15];
9357 } else {
4a2696c0 9358 /* CPSR.PAN is normally preserved preserved unless... */
f8af1143 9359 if (cpu_isar_feature(aa32_pan, env_archcpu(env))) {
4a2696c0
RH		 9360 switch (new_el) {
9361 case 3:
9362 if (!arm_is_secure_below_el3(env)) {
9363 /* ... the target is EL3, from non-secure state. */
9364 env->uncached_cpsr &= ~CPSR_PAN;
9365 break;
9366 }
9367 /* ... the target is EL3, from secure state ... */
9368 /* fall through */
9369 case 1:
9370 /* ... the target is EL1 and SCTLR.SPAN is 0. */
9371 if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) {
9372 env->uncached_cpsr |= CPSR_PAN;
9373 }
9374 break;
9375 }
9376 }
dea8378b
PM		 9377 /*
9378 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
9379 * and we should just guard the thumb mode on V4
9380 */
9381 if (arm_feature(env, ARM_FEATURE_V4T)) {
9382 env->thumb =
9383 (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
9384 }
9385 env->regs[14] = env->regs[15] + offset;
9386 }
9387 env->regs[15] = newpc;
a8a79c7a 9388 arm_rebuild_hflags(env);
dea8378b
PM		 9389}
9390
b9bc21ff
PM		 9391static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
9392{
9393 /*
9394 * Handle exception entry to Hyp mode; this is sufficiently
9395 * different to entry to other AArch32 modes that we handle it
9396 * separately here.
9397 *
9398 * The vector table entry used is always the 0x14 Hyp mode entry point,
9399 * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp.
9400 * The offset applied to the preferred return address is always zero
9401 * (see DDI0487C.a section G1.12.3).
9402 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
9403 */
9404 uint32_t addr, mask;
9405 ARMCPU *cpu = ARM_CPU(cs);
9406 CPUARMState *env = &cpu->env;
9407
9408 switch (cs->exception_index) {
9409 case EXCP_UDEF:
9410 addr = 0x04;
9411 break;
9412 case EXCP_SWI:
9413 addr = 0x14;
9414 break;
9415 case EXCP_BKPT:
9416 /* Fall through to prefetch abort. */
9417 case EXCP_PREFETCH_ABORT:
9418 env->cp15.ifar_s = env->exception.vaddress;
9419 qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n",
9420 (uint32_t)env->exception.vaddress);
9421 addr = 0x0c;
9422 break;
9423 case EXCP_DATA_ABORT:
9424 env->cp15.dfar_s = env->exception.vaddress;
9425 qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n",
9426 (uint32_t)env->exception.vaddress);
9427 addr = 0x10;
9428 break;
9429 case EXCP_IRQ:
9430 addr = 0x18;
9431 break;
9432 case EXCP_FIQ:
9433 addr = 0x1c;
9434 break;
9435 case EXCP_HVC:
9436 addr = 0x08;
9437 break;
9438 case EXCP_HYP_TRAP:
9439 addr = 0x14;
9bbb4ef9 9440 break;
b9bc21ff
PM		 9441 default:
9442 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
9443 }
9444
9445 if (cs->exception_index != EXCP_IRQ && cs->exception_index != EXCP_FIQ) {
2ed08180
PM		 9446 if (!arm_feature(env, ARM_FEATURE_V8)) {
9447 /*
9448 * QEMU syndrome values are v8-style. v7 has the IL bit
9449 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
9450 * If this is a v7 CPU, squash the IL bit in those cases.
9451 */
9452 if (cs->exception_index == EXCP_PREFETCH_ABORT ||
9453 (cs->exception_index == EXCP_DATA_ABORT &&
9454 !(env->exception.syndrome & ARM_EL_ISV)) ||
9455 syn_get_ec(env->exception.syndrome) == EC_UNCATEGORIZED) {
9456 env->exception.syndrome &= ~ARM_EL_IL;
9457 }
9458 }
b9bc21ff
PM		 9459 env->cp15.esr_el[2] = env->exception.syndrome;
9460 }
9461
9462 if (arm_current_el(env) != 2 && addr < 0x14) {
9463 addr = 0x14;
9464 }
9465
9466 mask = 0;
9467 if (!(env->cp15.scr_el3 & SCR_EA)) {
9468 mask |= CPSR_A;
9469 }
9470 if (!(env->cp15.scr_el3 & SCR_IRQ)) {
9471 mask |= CPSR_I;
9472 }
9473 if (!(env->cp15.scr_el3 & SCR_FIQ)) {
9474 mask |= CPSR_F;
9475 }
9476
9477 addr += env->cp15.hvbar;
9478
9479 take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr);
9480}
9481
966f758c 9482static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
b5ff1b31 9483{
97a8ea5a
AF		 9484 ARMCPU *cpu = ARM_CPU(cs);
9485 CPUARMState *env = &cpu->env;
b5ff1b31
FB		 9486 uint32_t addr;
9487 uint32_t mask;
9488 int new_mode;
9489 uint32_t offset;
16a906fd 9490 uint32_t moe;
b5ff1b31 9491
16a906fd 9492 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
64b91e3f 9493 switch (syn_get_ec(env->exception.syndrome)) {
16a906fd
PM		 9494 case EC_BREAKPOINT:
9495 case EC_BREAKPOINT_SAME_EL:
9496 moe = 1;
9497 break;
9498 case EC_WATCHPOINT:
9499 case EC_WATCHPOINT_SAME_EL:
9500 moe = 10;
9501 break;
9502 case EC_AA32_BKPT:
9503 moe = 3;
9504 break;
9505 case EC_VECTORCATCH:
9506 moe = 5;
9507 break;
9508 default:
9509 moe = 0;
9510 break;
9511 }
9512
9513 if (moe) {
9514 env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
9515 }
9516
b9bc21ff
PM		 9517 if (env->exception.target_el == 2) {
9518 arm_cpu_do_interrupt_aarch32_hyp(cs);
9519 return;
9520 }
9521
27103424 9522 switch (cs->exception_index) {
b5ff1b31
FB		 9523 case EXCP_UDEF:
9524 new_mode = ARM_CPU_MODE_UND;
9525 addr = 0x04;
9526 mask = CPSR_I;
9527 if (env->thumb)
9528 offset = 2;
9529 else
9530 offset = 4;
9531 break;
9532 case EXCP_SWI:
9533 new_mode = ARM_CPU_MODE_SVC;
9534 addr = 0x08;
9535 mask = CPSR_I;
601d70b9 9536 /* The PC already points to the next instruction. */
b5ff1b31
FB		 9537 offset = 0;
9538 break;
06c949e6 9539 case EXCP_BKPT:
9ee6e8bb
PB		 9540 /* Fall through to prefetch abort. */
9541 case EXCP_PREFETCH_ABORT:
88ca1c2d 9542 A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
b848ce2b 9543 A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
3f1beaca 9544 qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
88ca1c2d 9545 env->exception.fsr, (uint32_t)env->exception.vaddress);
b5ff1b31
FB		 9546 new_mode = ARM_CPU_MODE_ABT;
9547 addr = 0x0c;
9548 mask = CPSR_A | CPSR_I;
9549 offset = 4;
9550 break;
9551 case EXCP_DATA_ABORT:
4a7e2d73 9552 A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
b848ce2b 9553 A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
3f1beaca 9554 qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
4a7e2d73 9555 env->exception.fsr,
6cd8a264 9556 (uint32_t)env->exception.vaddress);
b5ff1b31
FB		 9557 new_mode = ARM_CPU_MODE_ABT;
9558 addr = 0x10;
9559 mask = CPSR_A | CPSR_I;
9560 offset = 8;
9561 break;
9562 case EXCP_IRQ:
9563 new_mode = ARM_CPU_MODE_IRQ;
9564 addr = 0x18;
9565 /* Disable IRQ and imprecise data aborts. */
9566 mask = CPSR_A | CPSR_I;
9567 offset = 4;
de38d23b
FA		 9568 if (env->cp15.scr_el3 & SCR_IRQ) {
9569 /* IRQ routed to monitor mode */
9570 new_mode = ARM_CPU_MODE_MON;
9571 mask |= CPSR_F;
9572 }
b5ff1b31
FB		 9573 break;
9574 case EXCP_FIQ:
9575 new_mode = ARM_CPU_MODE_FIQ;
9576 addr = 0x1c;
9577 /* Disable FIQ, IRQ and imprecise data aborts. */
9578 mask = CPSR_A | CPSR_I | CPSR_F;
de38d23b
FA		 9579 if (env->cp15.scr_el3 & SCR_FIQ) {
9580 /* FIQ routed to monitor mode */
9581 new_mode = ARM_CPU_MODE_MON;
9582 }
b5ff1b31
FB		 9583 offset = 4;
9584 break;
87a4b270
PM		 9585 case EXCP_VIRQ:
9586 new_mode = ARM_CPU_MODE_IRQ;
9587 addr = 0x18;
9588 /* Disable IRQ and imprecise data aborts. */
9589 mask = CPSR_A | CPSR_I;
9590 offset = 4;
9591 break;
9592 case EXCP_VFIQ:
9593 new_mode = ARM_CPU_MODE_FIQ;
9594 addr = 0x1c;
9595 /* Disable FIQ, IRQ and imprecise data aborts. */
9596 mask = CPSR_A | CPSR_I | CPSR_F;
9597 offset = 4;
9598 break;
dbe9d163
FA		 9599 case EXCP_SMC:
9600 new_mode = ARM_CPU_MODE_MON;
9601 addr = 0x08;
9602 mask = CPSR_A | CPSR_I | CPSR_F;
9603 offset = 0;
9604 break;
b5ff1b31 9605 default:
a47dddd7 9606 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
b5ff1b31
FB		 9607 return; /* Never happens. Keep compiler happy. */
9608 }
e89e51a1
FA		 9609
9610 if (new_mode == ARM_CPU_MODE_MON) {
9611 addr += env->cp15.mvbar;
137feaa9 9612 } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
e89e51a1 9613 /* High vectors. When enabled, base address cannot be remapped. */
b5ff1b31 9614 addr += 0xffff0000;
8641136c
NR		 9615 } else {
9616 /* ARM v7 architectures provide a vector base address register to remap
9617 * the interrupt vector table.
e89e51a1 9618 * This register is only followed in non-monitor mode, and is banked.
8641136c
NR		 9619 * Note: only bits 31:5 are valid.
9620 */
fb6c91ba 9621 addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
b5ff1b31 9622 }
dbe9d163
FA		 9623
9624 if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
9625 env->cp15.scr_el3 &= ~SCR_NS;
9626 }
9627
dea8378b 9628 take_aarch32_exception(env, new_mode, mask, offset, addr);
b5ff1b31
FB		 9629}
9630
a65dabf7
PM		 9631static int aarch64_regnum(CPUARMState *env, int aarch32_reg)
9632{
9633 /*
9634 * Return the register number of the AArch64 view of the AArch32
9635 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
9636 * be that of the AArch32 mode the exception came from.
9637 */
9638 int mode = env->uncached_cpsr & CPSR_M;
9639
9640 switch (aarch32_reg) {
9641 case 0 ... 7:
9642 return aarch32_reg;
9643 case 8 ... 12:
9644 return mode == ARM_CPU_MODE_FIQ ? aarch32_reg + 16 : aarch32_reg;
9645 case 13:
9646 switch (mode) {
9647 case ARM_CPU_MODE_USR:
9648 case ARM_CPU_MODE_SYS:
9649 return 13;
9650 case ARM_CPU_MODE_HYP:
9651 return 15;
9652 case ARM_CPU_MODE_IRQ:
9653 return 17;
9654 case ARM_CPU_MODE_SVC:
9655 return 19;
9656 case ARM_CPU_MODE_ABT:
9657 return 21;
9658 case ARM_CPU_MODE_UND:
9659 return 23;
9660 case ARM_CPU_MODE_FIQ:
9661 return 29;
9662 default:
9663 g_assert_not_reached();
9664 }
9665 case 14:
9666 switch (mode) {
9667 case ARM_CPU_MODE_USR:
9668 case ARM_CPU_MODE_SYS:
9669 case ARM_CPU_MODE_HYP:
9670 return 14;
9671 case ARM_CPU_MODE_IRQ:
9672 return 16;
9673 case ARM_CPU_MODE_SVC:
9674 return 18;
9675 case ARM_CPU_MODE_ABT:
9676 return 20;
9677 case ARM_CPU_MODE_UND:
9678 return 22;
9679 case ARM_CPU_MODE_FIQ:
9680 return 30;
9681 default:
9682 g_assert_not_reached();
9683 }
9684 case 15:
9685 return 31;
9686 default:
9687 g_assert_not_reached();
9688 }
9689}
9690
966f758c
PM		 9691/* Handle exception entry to a target EL which is using AArch64 */
9692static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
f3a9b694
PM		 9693{
9694 ARMCPU *cpu = ARM_CPU(cs);
9695 CPUARMState *env = &cpu->env;
9696 unsigned int new_el = env->exception.target_el;
9697 target_ulong addr = env->cp15.vbar_el[new_el];
9698 unsigned int new_mode = aarch64_pstate_mode(new_el, true);
4a2696c0 9699 unsigned int old_mode;
0ab5953b 9700 unsigned int cur_el = arm_current_el(env);
a65dabf7 9701 int rt;
0ab5953b 9702
9a05f7b6
RH		 9703 /*
9704 * Note that new_el can never be 0. If cur_el is 0, then
9705 * el0_a64 is is_a64(), else el0_a64 is ignored.
9706 */
9707 aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
f3a9b694 9708
0ab5953b 9709 if (cur_el < new_el) {
3d6f7617
PM		 9710 /* Entry vector offset depends on whether the implemented EL
9711 * immediately lower than the target level is using AArch32 or AArch64
9712 */
9713 bool is_aa64;
cb092fbb 9714 uint64_t hcr;
3d6f7617
PM		 9715
9716 switch (new_el) {
9717 case 3:
9718 is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
9719 break;
9720 case 2:
cb092fbb
RH		 9721 hcr = arm_hcr_el2_eff(env);
9722 if ((hcr & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
9723 is_aa64 = (hcr & HCR_RW) != 0;
9724 break;
9725 }
9726 /* fall through */
3d6f7617
PM		 9727 case 1:
9728 is_aa64 = is_a64(env);
9729 break;
9730 default:
9731 g_assert_not_reached();
9732 }
9733
9734 if (is_aa64) {
f3a9b694
PM		 9735 addr += 0x400;
9736 } else {
9737 addr += 0x600;
9738 }
9739 } else if (pstate_read(env) & PSTATE_SP) {
9740 addr += 0x200;
9741 }
9742
f3a9b694
PM		 9743 switch (cs->exception_index) {
9744 case EXCP_PREFETCH_ABORT:
9745 case EXCP_DATA_ABORT:
9746 env->cp15.far_el[new_el] = env->exception.vaddress;
9747 qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
9748 env->cp15.far_el[new_el]);
9749 /* fall through */
9750 case EXCP_BKPT:
9751 case EXCP_UDEF:
9752 case EXCP_SWI:
9753 case EXCP_HVC:
9754 case EXCP_HYP_TRAP:
9755 case EXCP_SMC:
a65dabf7
PM		 9756 switch (syn_get_ec(env->exception.syndrome)) {
9757 case EC_ADVSIMDFPACCESSTRAP:
4be42f40
PM		 9758 /*
9759 * QEMU internal FP/SIMD syndromes from AArch32 include the
9760 * TA and coproc fields which are only exposed if the exception
9761 * is taken to AArch32 Hyp mode. Mask them out to get a valid
9762 * AArch64 format syndrome.
9763 */
9764 env->exception.syndrome &= ~MAKE_64BIT_MASK(0, 20);
a65dabf7
PM		 9765 break;
9766 case EC_CP14RTTRAP:
9767 case EC_CP15RTTRAP:
9768 case EC_CP14DTTRAP:
9769 /*
9770 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
9771 * the raw register field from the insn; when taking this to
9772 * AArch64 we must convert it to the AArch64 view of the register
9773 * number. Notice that we read a 4-bit AArch32 register number and
9774 * write back a 5-bit AArch64 one.
9775 */
9776 rt = extract32(env->exception.syndrome, 5, 4);
9777 rt = aarch64_regnum(env, rt);
9778 env->exception.syndrome = deposit32(env->exception.syndrome,
9779 5, 5, rt);
9780 break;
9781 case EC_CP15RRTTRAP:
9782 case EC_CP14RRTTRAP:
9783 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
9784 rt = extract32(env->exception.syndrome, 5, 4);
9785 rt = aarch64_regnum(env, rt);
9786 env->exception.syndrome = deposit32(env->exception.syndrome,
9787 5, 5, rt);
9788 rt = extract32(env->exception.syndrome, 10, 4);
9789 rt = aarch64_regnum(env, rt);
9790 env->exception.syndrome = deposit32(env->exception.syndrome,
9791 10, 5, rt);
9792 break;
4be42f40 9793 }
f3a9b694
PM		 9794 env->cp15.esr_el[new_el] = env->exception.syndrome;
9795 break;
9796 case EXCP_IRQ:
9797 case EXCP_VIRQ:
9798 addr += 0x80;
9799 break;
9800 case EXCP_FIQ:
9801 case EXCP_VFIQ:
9802 addr += 0x100;
9803 break;
f3a9b694
PM		 9804 default:
9805 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
9806 }
9807
9808 if (is_a64(env)) {
4a2696c0 9809 old_mode = pstate_read(env);
f3a9b694
PM		 9810 aarch64_save_sp(env, arm_current_el(env));
9811 env->elr_el[new_el] = env->pc;
9812 } else {
4a2696c0 9813 old_mode = cpsr_read(env);
f3a9b694
PM		 9814 env->elr_el[new_el] = env->regs[15];
9815
9816 aarch64_sync_32_to_64(env);
9817
9818 env->condexec_bits = 0;
9819 }
4a2696c0
RH		 9820 env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode;
9821
f3a9b694
PM		 9822 qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
9823 env->elr_el[new_el]);
9824
4a2696c0
RH		 9825 if (cpu_isar_feature(aa64_pan, cpu)) {
9826 /* The value of PSTATE.PAN is normally preserved, except when ... */
9827 new_mode |= old_mode & PSTATE_PAN;
9828 switch (new_el) {
9829 case 2:
9830 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
9831 if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE))
9832 != (HCR_E2H | HCR_TGE)) {
9833 break;
9834 }
9835 /* fall through */
9836 case 1:
9837 /* ... the target is EL1 ... */
9838 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
9839 if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) == 0) {
9840 new_mode |= PSTATE_PAN;
9841 }
9842 break;
9843 }
9844 }
34669338
RH		 9845 if (cpu_isar_feature(aa64_mte, cpu)) {
9846 new_mode |= PSTATE_TCO;
9847 }
4a2696c0 9848
f3a9b694
PM		 9849 pstate_write(env, PSTATE_DAIF | new_mode);
9850 env->aarch64 = 1;
9851 aarch64_restore_sp(env, new_el);
a8a79c7a 9852 helper_rebuild_hflags_a64(env, new_el);
f3a9b694
PM		 9853
9854 env->pc = addr;
9855
9856 qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n",
9857 new_el, env->pc, pstate_read(env));
966f758c
PM		 9858}
9859
ed6e6ba9
AB		 9860/*
9861 * Do semihosting call and set the appropriate return value. All the
9862 * permission and validity checks have been done at translate time.
9863 *
9864 * We only see semihosting exceptions in TCG only as they are not
9865 * trapped to the hypervisor in KVM.
9866 */
91f78c58 9867#ifdef CONFIG_TCG
ed6e6ba9
AB		 9868static void handle_semihosting(CPUState *cs)
9869{
904c04de
PM		 9870 ARMCPU *cpu = ARM_CPU(cs);
9871 CPUARMState *env = &cpu->env;
9872
9873 if (is_a64(env)) {
ed6e6ba9
AB		 9874 qemu_log_mask(CPU_LOG_INT,
9875 "...handling as semihosting call 0x%" PRIx64 "\n",
9876 env->xregs[0]);
0bb446d8 9877 env->xregs[0] = do_common_semihosting(cs);
4ff5ef9e 9878 env->pc += 4;
904c04de 9879 } else {
904c04de
PM		 9880 qemu_log_mask(CPU_LOG_INT,
9881 "...handling as semihosting call 0x%x\n",
9882 env->regs[0]);
0bb446d8 9883 env->regs[0] = do_common_semihosting(cs);
4ff5ef9e 9884 env->regs[15] += env->thumb ? 2 : 4;
904c04de
PM		 9885 }
9886}
ed6e6ba9 9887#endif
904c04de 9888
966f758c
PM		 9889/* Handle a CPU exception for A and R profile CPUs.
9890 * Do any appropriate logging, handle PSCI calls, and then hand off
9891 * to the AArch64-entry or AArch32-entry function depending on the
9892 * target exception level's register width.
9893 */
9894void arm_cpu_do_interrupt(CPUState *cs)
9895{
9896 ARMCPU *cpu = ARM_CPU(cs);
9897 CPUARMState *env = &cpu->env;
9898 unsigned int new_el = env->exception.target_el;
9899
531c60a9 9900 assert(!arm_feature(env, ARM_FEATURE_M));
966f758c
PM		 9901
9902 arm_log_exception(cs->exception_index);
9903 qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),
9904 new_el);
9905 if (qemu_loglevel_mask(CPU_LOG_INT)
9906 && !excp_is_internal(cs->exception_index)) {
6568da45 9907 qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n",
64b91e3f 9908 syn_get_ec(env->exception.syndrome),
966f758c
PM		 9909 env->exception.syndrome);
9910 }
9911
9912 if (arm_is_psci_call(cpu, cs->exception_index)) {
9913 arm_handle_psci_call(cpu);
9914 qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
9915 return;
9916 }
9917
ed6e6ba9
AB		 9918 /*
9919 * Semihosting semantics depend on the register width of the code
9920 * that caused the exception, not the target exception level, so
9921 * must be handled here.
966f758c 9922 */
ed6e6ba9
AB		 9923#ifdef CONFIG_TCG
9924 if (cs->exception_index == EXCP_SEMIHOST) {
9925 handle_semihosting(cs);
904c04de
PM		 9926 return;
9927 }
ed6e6ba9 9928#endif
904c04de 9929
b5c53d1b
AL		 9930 /* Hooks may change global state so BQL should be held, also the
9931 * BQL needs to be held for any modification of
9932 * cs->interrupt_request.
9933 */
9934 g_assert(qemu_mutex_iothread_locked());
9935
9936 arm_call_pre_el_change_hook(cpu);
9937
904c04de
PM		 9938 assert(!excp_is_internal(cs->exception_index));
9939 if (arm_el_is_aa64(env, new_el)) {
966f758c
PM		 9940 arm_cpu_do_interrupt_aarch64(cs);
9941 } else {
9942 arm_cpu_do_interrupt_aarch32(cs);
9943 }
f3a9b694 9944
bd7d00fc
PM		 9945 arm_call_el_change_hook(cpu);
9946
f3a9b694
PM		 9947 if (!kvm_enabled()) {
9948 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
9949 }
9950}
c47eaf9f 9951#endif /* !CONFIG_USER_ONLY */
0480f69a 9952
aaec1432
RH		 9953uint64_t arm_sctlr(CPUARMState *env, int el)
9954{
9955 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
9956 if (el == 0) {
9957 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0);
9958 el = (mmu_idx == ARMMMUIdx_E20_0 ? 2 : 1);
9959 }
9960 return env->cp15.sctlr_el[el];
9961}
c47eaf9f 9962
0480f69a 9963/* Return the SCTLR value which controls this address translation regime */
aaec1432 9964static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
0480f69a
PM		 9965{
9966 return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
9967}
9968
aaec1432
RH		 9969#ifndef CONFIG_USER_ONLY
9970
0480f69a
PM		 9971/* Return true if the specified stage of address translation is disabled */
9972static inline bool regime_translation_disabled(CPUARMState *env,
9973 ARMMMUIdx mmu_idx)
9974{
29c483a5 9975 if (arm_feature(env, ARM_FEATURE_M)) {
ecf5e8ea 9976 switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] &
3bef7012
PM		 9977 (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) {
9978 case R_V7M_MPU_CTRL_ENABLE_MASK:
9979 /* Enabled, but not for HardFault and NMI */
62593718 9980 return mmu_idx & ARM_MMU_IDX_M_NEGPRI;
3bef7012
PM		 9981 case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK:
9982 /* Enabled for all cases */
9983 return false;
9984 case 0:
9985 default:
9986 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
9987 * we warned about that in armv7m_nvic.c when the guest set it.
9988 */
9989 return true;
9990 }
29c483a5
MD		 9991 }
9992
97fa9350 9993 if (mmu_idx == ARMMMUIdx_Stage2) {
9d1bab33
PM		 9994 /* HCR.DC means HCR.VM behaves as 1 */
9995 return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) == 0;
0480f69a 9996 }
3d0e3080
PM		 9997
9998 if (env->cp15.hcr_el2 & HCR_TGE) {
9999 /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
10000 if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) {
10001 return true;
10002 }
10003 }
10004
fee7aa46 10005 if ((env->cp15.hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) {
9d1bab33
PM		 10006 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
10007 return true;
10008 }
10009
0480f69a
PM		 10010 return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
10011}
10012
73462ddd
PC		 10013static inline bool regime_translation_big_endian(CPUARMState *env,
10014 ARMMMUIdx mmu_idx)
10015{
10016 return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0;
10017}
10018
c47eaf9f
PM		 10019/* Return the TTBR associated with this translation regime */
10020static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
10021 int ttbrn)
10022{
97fa9350 10023 if (mmu_idx == ARMMMUIdx_Stage2) {
c47eaf9f
PM		 10024 return env->cp15.vttbr_el2;
10025 }
10026 if (ttbrn == 0) {
10027 return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
10028 } else {
10029 return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
10030 }
10031}
10032
10033#endif /* !CONFIG_USER_ONLY */
10034
8bd5c820
PM		 10035/* Convert a possible stage1+2 MMU index into the appropriate
10036 * stage 1 MMU index
10037 */
10038static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
10039{
b9f6033c
RH		 10040 switch (mmu_idx) {
10041 case ARMMMUIdx_E10_0:
10042 return ARMMMUIdx_Stage1_E0;
10043 case ARMMMUIdx_E10_1:
10044 return ARMMMUIdx_Stage1_E1;
452ef8cb
RH		 10045 case ARMMMUIdx_E10_1_PAN:
10046 return ARMMMUIdx_Stage1_E1_PAN;
b9f6033c
RH		 10047 default:
10048 return mmu_idx;
8bd5c820 10049 }
8bd5c820
PM		 10050}
10051
0480f69a
PM		 10052/* Return true if the translation regime is using LPAE format page tables */
10053static inline bool regime_using_lpae_format(CPUARMState *env,
10054 ARMMMUIdx mmu_idx)
10055{
10056 int el = regime_el(env, mmu_idx);
10057 if (el == 2 || arm_el_is_aa64(env, el)) {
10058 return true;
10059 }
10060 if (arm_feature(env, ARM_FEATURE_LPAE)
10061 && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
10062 return true;
10063 }
10064 return false;
10065}
10066
deb2db99
AR		 10067/* Returns true if the stage 1 translation regime is using LPAE format page
10068 * tables. Used when raising alignment exceptions, whose FSR changes depending
10069 * on whether the long or short descriptor format is in use. */
10070bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
30901475 10071{
8bd5c820 10072 mmu_idx = stage_1_mmu_idx(mmu_idx);
deb2db99 10073
30901475
AB		 10074 return regime_using_lpae_format(env, mmu_idx);
10075}
10076
c47eaf9f 10077#ifndef CONFIG_USER_ONLY
0480f69a
PM		 10078static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
10079{
10080 switch (mmu_idx) {
fba37aed 10081 case ARMMMUIdx_SE10_0:
b9f6033c 10082 case ARMMMUIdx_E20_0:
2859d7b5 10083 case ARMMMUIdx_Stage1_E0:
e7b921c2 10084 case ARMMMUIdx_MUser:
871bec7c 10085 case ARMMMUIdx_MSUser:
62593718
PM		 10086 case ARMMMUIdx_MUserNegPri:
10087 case ARMMMUIdx_MSUserNegPri:
0480f69a
PM		 10088 return true;
10089 default:
10090 return false;
01b98b68
RH		 10091 case ARMMMUIdx_E10_0:
10092 case ARMMMUIdx_E10_1:
452ef8cb 10093 case ARMMMUIdx_E10_1_PAN:
0480f69a
PM		 10094 g_assert_not_reached();
10095 }
10096}
10097
0fbf5238
AJ		 10098/* Translate section/page access permissions to page
10099 * R/W protection flags
d76951b6
AJ		 10100 *
10101 * @env: CPUARMState
10102 * @mmu_idx: MMU index indicating required translation regime
10103 * @ap: The 3-bit access permissions (AP[2:0])
10104 * @domain_prot: The 2-bit domain access permissions
0fbf5238
AJ		 10105 */
10106static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
10107 int ap, int domain_prot)
10108{
554b0b09
PM		 10109 bool is_user = regime_is_user(env, mmu_idx);
10110
10111 if (domain_prot == 3) {
10112 return PAGE_READ | PAGE_WRITE;
10113 }
10114
554b0b09
PM		 10115 switch (ap) {
10116 case 0:
10117 if (arm_feature(env, ARM_FEATURE_V7)) {
10118 return 0;
10119 }
554b0b09
PM		 10120 switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
10121 case SCTLR_S:
10122 return is_user ? 0 : PAGE_READ;
10123 case SCTLR_R:
10124 return PAGE_READ;
10125 default:
10126 return 0;
10127 }
10128 case 1:
10129 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
10130 case 2:
87c3d486 10131 if (is_user) {
0fbf5238 10132 return PAGE_READ;
87c3d486 10133 } else {
554b0b09 10134 return PAGE_READ | PAGE_WRITE;
87c3d486 10135 }
554b0b09
PM		 10136 case 3:
10137 return PAGE_READ | PAGE_WRITE;
10138 case 4: /* Reserved. */
10139 return 0;
10140 case 5:
0fbf5238 10141 return is_user ? 0 : PAGE_READ;
554b0b09 10142 case 6:
0fbf5238 10143 return PAGE_READ;
554b0b09 10144 case 7:
87c3d486 10145 if (!arm_feature(env, ARM_FEATURE_V6K)) {
554b0b09 10146 return 0;
87c3d486 10147 }
0fbf5238 10148 return PAGE_READ;
554b0b09 10149 default:
0fbf5238 10150 g_assert_not_reached();
554b0b09 10151 }
b5ff1b31
FB		 10152}
10153
d76951b6
AJ		 10154/* Translate section/page access permissions to page
10155 * R/W protection flags.
10156 *
d76951b6 10157 * @ap: The 2-bit simple AP (AP[2:1])
d8e052b3 10158 * @is_user: TRUE if accessing from PL0
d76951b6 10159 */
d8e052b3 10160static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
d76951b6 10161{
d76951b6
AJ		 10162 switch (ap) {
10163 case 0:
10164 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
10165 case 1:
10166 return PAGE_READ | PAGE_WRITE;
10167 case 2:
10168 return is_user ? 0 : PAGE_READ;
10169 case 3:
10170 return PAGE_READ;
10171 default:
10172 g_assert_not_reached();
10173 }
10174}
10175
d8e052b3
AJ		 10176static inline int
10177simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
10178{
10179 return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
10180}
10181
6ab1a5ee
EI		 10182/* Translate S2 section/page access permissions to protection flags
10183 *
10184 * @env: CPUARMState
10185 * @s2ap: The 2-bit stage2 access permissions (S2AP)
ce3125be
PM		 10186 * @xn: XN (execute-never) bits
10187 * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
6ab1a5ee 10188 */
ce3125be 10189static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0)
6ab1a5ee
EI		 10190{
10191 int prot = 0;
10192
10193 if (s2ap & 1) {
10194 prot |= PAGE_READ;
10195 }
10196 if (s2ap & 2) {
10197 prot |= PAGE_WRITE;
10198 }
ce3125be
PM		 10199
10200 if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) {
10201 switch (xn) {
10202 case 0:
dfda6837 10203 prot |= PAGE_EXEC;
ce3125be
PM		 10204 break;
10205 case 1:
10206 if (s1_is_el0) {
10207 prot |= PAGE_EXEC;
10208 }
10209 break;
10210 case 2:
10211 break;
10212 case 3:
10213 if (!s1_is_el0) {
10214 prot |= PAGE_EXEC;
10215 }
10216 break;
10217 default:
10218 g_assert_not_reached();
10219 }
10220 } else {
10221 if (!extract32(xn, 1, 1)) {
10222 if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {
10223 prot |= PAGE_EXEC;
10224 }
dfda6837 10225 }
6ab1a5ee
EI		 10226 }
10227 return prot;
10228}
10229
d8e052b3
AJ		 10230/* Translate section/page access permissions to protection flags
10231 *
10232 * @env: CPUARMState
10233 * @mmu_idx: MMU index indicating required translation regime
10234 * @is_aa64: TRUE if AArch64
10235 * @ap: The 2-bit simple AP (AP[2:1])
10236 * @ns: NS (non-secure) bit
10237 * @xn: XN (execute-never) bit
10238 * @pxn: PXN (privileged execute-never) bit
10239 */
10240static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
10241 int ap, int ns, int xn, int pxn)
10242{
10243 bool is_user = regime_is_user(env, mmu_idx);
10244 int prot_rw, user_rw;
10245 bool have_wxn;
10246 int wxn = 0;
10247
97fa9350 10248 assert(mmu_idx != ARMMMUIdx_Stage2);
d8e052b3
AJ		 10249
10250 user_rw = simple_ap_to_rw_prot_is_user(ap, true);
10251 if (is_user) {
10252 prot_rw = user_rw;
10253 } else {
81636b70 10254 if (user_rw && regime_is_pan(env, mmu_idx)) {
f4e1dbc5
PM		 10255 /* PAN forbids data accesses but doesn't affect insn fetch */
10256 prot_rw = 0;
10257 } else {
10258 prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
81636b70 10259 }
d8e052b3
AJ		 10260 }
10261
10262 if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
10263 return prot_rw;
10264 }
10265
10266 /* TODO have_wxn should be replaced with
10267 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
10268 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
10269 * compatible processors have EL2, which is required for [U]WXN.
10270 */
10271 have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
10272
10273 if (have_wxn) {
10274 wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
10275 }
10276
10277 if (is_aa64) {
339370b9
RH		 10278 if (regime_has_2_ranges(mmu_idx) && !is_user) {
10279 xn = pxn || (user_rw & PAGE_WRITE);
d8e052b3
AJ		 10280 }
10281 } else if (arm_feature(env, ARM_FEATURE_V7)) {
10282 switch (regime_el(env, mmu_idx)) {
10283 case 1:
10284 case 3:
10285 if (is_user) {
10286 xn = xn || !(user_rw & PAGE_READ);
10287 } else {
10288 int uwxn = 0;
10289 if (have_wxn) {
10290 uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
10291 }
10292 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
10293 (uwxn && (user_rw & PAGE_WRITE));
10294 }
10295 break;
10296 case 2:
10297 break;
10298 }
10299 } else {
10300 xn = wxn = 0;
10301 }
10302
10303 if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
10304 return prot_rw;
10305 }
10306 return prot_rw | PAGE_EXEC;
10307}
10308
0480f69a
PM		 10309static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
10310 uint32_t *table, uint32_t address)
b2fa1797 10311{
0480f69a 10312 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
0480f69a 10313 TCR *tcr = regime_tcr(env, mmu_idx);
11f136ee 10314
11f136ee
FA		 10315 if (address & tcr->mask) {
10316 if (tcr->raw_tcr & TTBCR_PD1) {
e389be16
FA		 10317 /* Translation table walk disabled for TTBR1 */
10318 return false;
10319 }
aef878be 10320 *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
e389be16 10321 } else {
11f136ee 10322 if (tcr->raw_tcr & TTBCR_PD0) {
e389be16
FA		 10323 /* Translation table walk disabled for TTBR0 */
10324 return false;
10325 }
aef878be 10326 *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
e389be16
FA		 10327 }
10328 *table |= (address >> 18) & 0x3ffc;
10329 return true;
b2fa1797
PB		 10330}
10331
37785977
EI		 10332/* Translate a S1 pagetable walk through S2 if needed. */
10333static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
10334 hwaddr addr, MemTxAttrs txattrs,
37785977
EI		 10335 ARMMMUFaultInfo *fi)
10336{
fee7aa46 10337 if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
97fa9350 10338 !regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
37785977
EI		 10339 target_ulong s2size;
10340 hwaddr s2pa;
10341 int s2prot;
10342 int ret;
eadb2feb 10343 ARMCacheAttrs cacheattrs = {};
37785977 10344
59dff859 10345 ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,
ff7de2fc 10346 false,
59dff859 10347 &s2pa, &txattrs, &s2prot, &s2size, fi,
a6d6f37a 10348 &cacheattrs);
37785977 10349 if (ret) {
3b39d734 10350 assert(fi->type != ARMFault_None);
37785977
EI		 10351 fi->s2addr = addr;
10352 fi->stage2 = true;
10353 fi->s1ptw = true;
10354 return ~0;
10355 }
a6d6f37a
RH		 10356 if ((env->cp15.hcr_el2 & HCR_PTW) && (cacheattrs.attrs & 0xf0) == 0) {
10357 /*
10358 * PTW set and S1 walk touched S2 Device memory:
10359 * generate Permission fault.
10360 */
eadb2feb
PM		 10361 fi->type = ARMFault_Permission;
10362 fi->s2addr = addr;
10363 fi->stage2 = true;
10364 fi->s1ptw = true;
10365 return ~0;
10366 }
37785977
EI		 10367 addr = s2pa;
10368 }
10369 return addr;
10370}
10371
14577270 10372/* All loads done in the course of a page table walk go through here. */
a614e698 10373static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
3795a6de 10374 ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
ebca90e4 10375{
a614e698
EI		 10376 ARMCPU *cpu = ARM_CPU(cs);
10377 CPUARMState *env = &cpu->env;
ebca90e4 10378 MemTxAttrs attrs = {};
3b39d734 10379 MemTxResult result = MEMTX_OK;
5ce4ff65 10380 AddressSpace *as;
3b39d734 10381 uint32_t data;
ebca90e4
PM		 10382
10383 attrs.secure = is_secure;
5ce4ff65 10384 as = arm_addressspace(cs, attrs);
3795a6de 10385 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi);
a614e698
EI		 10386 if (fi->s1ptw) {
10387 return 0;
10388 }
73462ddd 10389 if (regime_translation_big_endian(env, mmu_idx)) {
3b39d734 10390 data = address_space_ldl_be(as, addr, attrs, &result);
73462ddd 10391 } else {
3b39d734 10392 data = address_space_ldl_le(as, addr, attrs, &result);
73462ddd 10393 }
3b39d734
PM		 10394 if (result == MEMTX_OK) {
10395 return data;
10396 }
10397 fi->type = ARMFault_SyncExternalOnWalk;
10398 fi->ea = arm_extabort_type(result);
10399 return 0;
ebca90e4
PM		 10400}
10401
37785977 10402static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
3795a6de 10403 ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi)
ebca90e4 10404{
37785977
EI		 10405 ARMCPU *cpu = ARM_CPU(cs);
10406 CPUARMState *env = &cpu->env;
ebca90e4 10407 MemTxAttrs attrs = {};
3b39d734 10408 MemTxResult result = MEMTX_OK;
5ce4ff65 10409 AddressSpace *as;
9aea1ea3 10410 uint64_t data;
ebca90e4
PM		 10411
10412 attrs.secure = is_secure;
5ce4ff65 10413 as = arm_addressspace(cs, attrs);
3795a6de 10414 addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi);
37785977
EI		 10415 if (fi->s1ptw) {
10416 return 0;
10417 }
73462ddd 10418 if (regime_translation_big_endian(env, mmu_idx)) {
3b39d734 10419 data = address_space_ldq_be(as, addr, attrs, &result);
73462ddd 10420 } else {
3b39d734
PM		 10421 data = address_space_ldq_le(as, addr, attrs, &result);
10422 }
10423 if (result == MEMTX_OK) {
10424 return data;
73462ddd 10425 }
3b39d734
PM		 10426 fi->type = ARMFault_SyncExternalOnWalk;
10427 fi->ea = arm_extabort_type(result);
10428 return 0;
ebca90e4
PM		 10429}
10430
b7cc4e82 10431static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
03ae85f8 10432 MMUAccessType access_type, ARMMMUIdx mmu_idx,
b7cc4e82 10433 hwaddr *phys_ptr, int *prot,
f989983e 10434 target_ulong *page_size,
e14b5a23 10435 ARMMMUFaultInfo *fi)
b5ff1b31 10436{
2fc0cc0e 10437 CPUState *cs = env_cpu(env);
f989983e 10438 int level = 1;
b5ff1b31
FB		 10439 uint32_t table;
10440 uint32_t desc;
10441 int type;
10442 int ap;
e389be16 10443 int domain = 0;
dd4ebc2e 10444 int domain_prot;
a8170e5e 10445 hwaddr phys_addr;
0480f69a 10446 uint32_t dacr;
b5ff1b31 10447
9ee6e8bb
PB		 10448 /* Pagetable walk. */
10449 /* Lookup l1 descriptor. */
0480f69a 10450 if (!get_level1_table_address(env, mmu_idx, &table, address)) {
e389be16 10451 /* Section translation fault if page walk is disabled by PD0 or PD1 */
f989983e 10452 fi->type = ARMFault_Translation;
e389be16
FA		 10453 goto do_fault;
10454 }
a614e698 10455 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
3795a6de 10456 mmu_idx, fi);
3b39d734
PM		 10457 if (fi->type != ARMFault_None) {
10458 goto do_fault;
10459 }
9ee6e8bb 10460 type = (desc & 3);
dd4ebc2e 10461 domain = (desc >> 5) & 0x0f;
0480f69a
PM		 10462 if (regime_el(env, mmu_idx) == 1) {
10463 dacr = env->cp15.dacr_ns;
10464 } else {
10465 dacr = env->cp15.dacr_s;
10466 }
10467 domain_prot = (dacr >> (domain * 2)) & 3;
9ee6e8bb 10468 if (type == 0) {
601d70b9 10469 /* Section translation fault. */
f989983e 10470 fi->type = ARMFault_Translation;
9ee6e8bb
PB		 10471 goto do_fault;
10472 }
f989983e
PM		 10473 if (type != 2) {
10474 level = 2;
10475 }
dd4ebc2e 10476 if (domain_prot == 0 || domain_prot == 2) {
f989983e 10477 fi->type = ARMFault_Domain;
9ee6e8bb
PB		 10478 goto do_fault;
10479 }
10480 if (type == 2) {
10481 /* 1Mb section. */
10482 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
10483 ap = (desc >> 10) & 3;
d4c430a8 10484 *page_size = 1024 * 1024;
9ee6e8bb
PB		 10485 } else {
10486 /* Lookup l2 entry. */
554b0b09
PM		 10487 if (type == 1) {
10488 /* Coarse pagetable. */
10489 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
10490 } else {
10491 /* Fine pagetable. */
10492 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
10493 }
a614e698 10494 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
3795a6de 10495 mmu_idx, fi);
3b39d734
PM		 10496 if (fi->type != ARMFault_None) {
10497 goto do_fault;
10498 }
9ee6e8bb
PB		 10499 switch (desc & 3) {
10500 case 0: /* Page translation fault. */
f989983e 10501 fi->type = ARMFault_Translation;
9ee6e8bb
PB		 10502 goto do_fault;
10503 case 1: /* 64k page. */
10504 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
10505 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 10506 *page_size = 0x10000;
ce819861 10507 break;
9ee6e8bb
PB		 10508 case 2: /* 4k page. */
10509 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
c10f7fc3 10510 ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
d4c430a8 10511 *page_size = 0x1000;
ce819861 10512 break;
fc1891c7 10513 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
554b0b09 10514 if (type == 1) {
fc1891c7
PM		 10515 /* ARMv6/XScale extended small page format */
10516 if (arm_feature(env, ARM_FEATURE_XSCALE)
10517 || arm_feature(env, ARM_FEATURE_V6)) {
554b0b09 10518 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
fc1891c7 10519 *page_size = 0x1000;
554b0b09 10520 } else {
fc1891c7
PM		 10521 /* UNPREDICTABLE in ARMv5; we choose to take a
10522 * page translation fault.
10523 */
f989983e 10524 fi->type = ARMFault_Translation;
554b0b09
PM		 10525 goto do_fault;
10526 }
10527 } else {
10528 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
fc1891c7 10529 *page_size = 0x400;
554b0b09 10530 }
9ee6e8bb 10531 ap = (desc >> 4) & 3;
ce819861
PB		 10532 break;
10533 default:
9ee6e8bb
PB		 10534 /* Never happens, but compiler isn't smart enough to tell. */
10535 abort();
ce819861 10536 }
9ee6e8bb 10537 }
0fbf5238
AJ		 10538 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
10539 *prot |= *prot ? PAGE_EXEC : 0;
10540 if (!(*prot & (1 << access_type))) {
9ee6e8bb 10541 /* Access permission fault. */
f989983e 10542 fi->type = ARMFault_Permission;
9ee6e8bb
PB		 10543 goto do_fault;
10544 }
10545 *phys_ptr = phys_addr;
b7cc4e82 10546 return false;
9ee6e8bb 10547do_fault:
f989983e
PM		 10548 fi->domain = domain;
10549 fi->level = level;
b7cc4e82 10550 return true;
9ee6e8bb
PB		 10551}
10552
b7cc4e82 10553static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
03ae85f8 10554 MMUAccessType access_type, ARMMMUIdx mmu_idx,
b7cc4e82 10555 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
f06cf243 10556 target_ulong *page_size, ARMMMUFaultInfo *fi)
9ee6e8bb 10557{
2fc0cc0e 10558 CPUState *cs = env_cpu(env);
0ae0326b 10559 ARMCPU *cpu = env_archcpu(env);
f06cf243 10560 int level = 1;
9ee6e8bb
PB		 10561 uint32_t table;
10562 uint32_t desc;
10563 uint32_t xn;
de9b05b8 10564 uint32_t pxn = 0;
9ee6e8bb
PB		 10565 int type;
10566 int ap;
de9b05b8 10567 int domain = 0;
dd4ebc2e 10568 int domain_prot;
a8170e5e 10569 hwaddr phys_addr;
0480f69a 10570 uint32_t dacr;
8bf5b6a9 10571 bool ns;
9ee6e8bb
PB		 10572
10573 /* Pagetable walk. */
10574 /* Lookup l1 descriptor. */
0480f69a 10575 if (!get_level1_table_address(env, mmu_idx, &table, address)) {
e389be16 10576 /* Section translation fault if page walk is disabled by PD0 or PD1 */
f06cf243 10577 fi->type = ARMFault_Translation;
e389be16
FA		 10578 goto do_fault;
10579 }
a614e698 10580 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
3795a6de 10581 mmu_idx, fi);
3b39d734
PM		 10582 if (fi->type != ARMFault_None) {
10583 goto do_fault;
10584 }
9ee6e8bb 10585 type = (desc & 3);
0ae0326b 10586 if (type == 0 || (type == 3 && !cpu_isar_feature(aa32_pxn, cpu))) {
de9b05b8
PM		 10587 /* Section translation fault, or attempt to use the encoding
10588 * which is Reserved on implementations without PXN.
10589 */
f06cf243 10590 fi->type = ARMFault_Translation;
9ee6e8bb 10591 goto do_fault;
de9b05b8
PM		 10592 }
10593 if ((type == 1) || !(desc & (1 << 18))) {
10594 /* Page or Section. */
dd4ebc2e 10595 domain = (desc >> 5) & 0x0f;
9ee6e8bb 10596 }
0480f69a
PM		 10597 if (regime_el(env, mmu_idx) == 1) {
10598 dacr = env->cp15.dacr_ns;
10599 } else {
10600 dacr = env->cp15.dacr_s;
10601 }
f06cf243
PM		 10602 if (type == 1) {
10603 level = 2;
10604 }
0480f69a 10605 domain_prot = (dacr >> (domain * 2)) & 3;
dd4ebc2e 10606 if (domain_prot == 0 || domain_prot == 2) {
f06cf243
PM		 10607 /* Section or Page domain fault */
10608 fi->type = ARMFault_Domain;
9ee6e8bb
PB		 10609 goto do_fault;
10610 }
de9b05b8 10611 if (type != 1) {
9ee6e8bb
PB		 10612 if (desc & (1 << 18)) {
10613 /* Supersection. */
10614 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
4e42a6ca
SF		 10615 phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
10616 phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
d4c430a8 10617 *page_size = 0x1000000;
b5ff1b31 10618 } else {
9ee6e8bb
PB		 10619 /* Section. */
10620 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 10621 *page_size = 0x100000;
b5ff1b31 10622 }
9ee6e8bb
PB		 10623 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
10624 xn = desc & (1 << 4);
de9b05b8 10625 pxn = desc & 1;
8bf5b6a9 10626 ns = extract32(desc, 19, 1);
9ee6e8bb 10627 } else {
0ae0326b 10628 if (cpu_isar_feature(aa32_pxn, cpu)) {
de9b05b8
PM		 10629 pxn = (desc >> 2) & 1;
10630 }
8bf5b6a9 10631 ns = extract32(desc, 3, 1);
9ee6e8bb
PB		 10632 /* Lookup l2 entry. */
10633 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
a614e698 10634 desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
3795a6de 10635 mmu_idx, fi);
3b39d734
PM		 10636 if (fi->type != ARMFault_None) {
10637 goto do_fault;
10638 }
9ee6e8bb
PB		 10639 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
10640 switch (desc & 3) {
10641 case 0: /* Page translation fault. */
f06cf243 10642 fi->type = ARMFault_Translation;
b5ff1b31 10643 goto do_fault;
9ee6e8bb
PB		 10644 case 1: /* 64k page. */
10645 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
10646 xn = desc & (1 << 15);
d4c430a8 10647 *page_size = 0x10000;
9ee6e8bb
PB		 10648 break;
10649 case 2: case 3: /* 4k page. */
10650 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
10651 xn = desc & 1;
d4c430a8 10652 *page_size = 0x1000;
9ee6e8bb
PB		 10653 break;
10654 default:
10655 /* Never happens, but compiler isn't smart enough to tell. */
10656 abort();
b5ff1b31 10657 }
9ee6e8bb 10658 }
dd4ebc2e 10659 if (domain_prot == 3) {
c0034328
JR		 10660 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
10661 } else {
0480f69a 10662 if (pxn && !regime_is_user(env, mmu_idx)) {
de9b05b8
PM		 10663 xn = 1;
10664 }
f06cf243
PM		 10665 if (xn && access_type == MMU_INST_FETCH) {
10666 fi->type = ARMFault_Permission;
c0034328 10667 goto do_fault;
f06cf243 10668 }
9ee6e8bb 10669
d76951b6
AJ		 10670 if (arm_feature(env, ARM_FEATURE_V6K) &&
10671 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
10672 /* The simplified model uses AP[0] as an access control bit. */
10673 if ((ap & 1) == 0) {
10674 /* Access flag fault. */
f06cf243 10675 fi->type = ARMFault_AccessFlag;
d76951b6
AJ		 10676 goto do_fault;
10677 }
10678 *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
10679 } else {
10680 *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
c0034328 10681 }
0fbf5238
AJ		 10682 if (*prot && !xn) {
10683 *prot |= PAGE_EXEC;
10684 }
10685 if (!(*prot & (1 << access_type))) {
c0034328 10686 /* Access permission fault. */
f06cf243 10687 fi->type = ARMFault_Permission;
c0034328
JR		 10688 goto do_fault;
10689 }
3ad493fc 10690 }
8bf5b6a9
PM		 10691 if (ns) {
10692 /* The NS bit will (as required by the architecture) have no effect if
10693 * the CPU doesn't support TZ or this is a non-secure translation
10694 * regime, because the attribute will already be non-secure.
10695 */
10696 attrs->secure = false;
10697 }
9ee6e8bb 10698 *phys_ptr = phys_addr;
b7cc4e82 10699 return false;
b5ff1b31 10700do_fault:
f06cf243
PM		 10701 fi->domain = domain;
10702 fi->level = level;
b7cc4e82 10703 return true;
b5ff1b31
FB		 10704}
10705
1853d5a9 10706/*
a0e966c9 10707 * check_s2_mmu_setup
1853d5a9
EI		 10708 * @cpu: ARMCPU
10709 * @is_aa64: True if the translation regime is in AArch64 state
10710 * @startlevel: Suggested starting level
10711 * @inputsize: Bitsize of IPAs
10712 * @stride: Page-table stride (See the ARM ARM)
10713 *
a0e966c9
EI		 10714 * Returns true if the suggested S2 translation parameters are OK and
10715 * false otherwise.
1853d5a9 10716 */
a0e966c9
EI		 10717static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
10718 int inputsize, int stride)
1853d5a9 10719{
98d68ec2
EI		 10720 const int grainsize = stride + 3;
10721 int startsizecheck;
10722
1853d5a9
EI		 10723 /* Negative levels are never allowed. */
10724 if (level < 0) {
10725 return false;
10726 }
10727
98d68ec2
EI		 10728 startsizecheck = inputsize - ((3 - level) * stride + grainsize);
10729 if (startsizecheck < 1 || startsizecheck > stride + 4) {
10730 return false;
10731 }
10732
1853d5a9 10733 if (is_aa64) {
3526423e 10734 CPUARMState *env = &cpu->env;
1853d5a9
EI		 10735 unsigned int pamax = arm_pamax(cpu);
10736
10737 switch (stride) {
10738 case 13: /* 64KB Pages. */
10739 if (level == 0 || (level == 1 && pamax <= 42)) {
10740 return false;
10741 }
10742 break;
10743 case 11: /* 16KB Pages. */
10744 if (level == 0 || (level == 1 && pamax <= 40)) {
10745 return false;
10746 }
10747 break;
10748 case 9: /* 4KB Pages. */
10749 if (level == 0 && pamax <= 42) {
10750 return false;
10751 }
10752 break;
10753 default:
10754 g_assert_not_reached();
10755 }
3526423e
EI		 10756
10757 /* Inputsize checks. */
10758 if (inputsize > pamax &&
10759 (arm_el_is_aa64(env, 1) || inputsize > 40)) {
10760 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
10761 return false;
10762 }
1853d5a9 10763 } else {
1853d5a9
EI		 10764 /* AArch32 only supports 4KB pages. Assert on that. */
10765 assert(stride == 9);
10766
10767 if (level == 0) {
10768 return false;
10769 }
1853d5a9
EI		 10770 }
10771 return true;
10772}
10773
5b2d261d
AB		 10774/* Translate from the 4-bit stage 2 representation of
10775 * memory attributes (without cache-allocation hints) to
10776 * the 8-bit representation of the stage 1 MAIR registers
10777 * (which includes allocation hints).
10778 *
10779 * ref: shared/translation/attrs/S2AttrDecode()
10780 * .../S2ConvertAttrsHints()
10781 */
10782static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
10783{
10784 uint8_t hiattr = extract32(s2attrs, 2, 2);
10785 uint8_t loattr = extract32(s2attrs, 0, 2);
10786 uint8_t hihint = 0, lohint = 0;
10787
10788 if (hiattr != 0) { /* normal memory */
10789 if ((env->cp15.hcr_el2 & HCR_CD) != 0) { /* cache disabled */
10790 hiattr = loattr = 1; /* non-cacheable */
10791 } else {
10792 if (hiattr != 1) { /* Write-through or write-back */
10793 hihint = 3; /* RW allocate */
10794 }
10795 if (loattr != 1) { /* Write-through or write-back */
10796 lohint = 3; /* RW allocate */
10797 }
10798 }
10799 }
10800
10801 return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint;
10802}
c47eaf9f 10803#endif /* !CONFIG_USER_ONLY */
5b2d261d 10804
b830a5ee
RH		 10805static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx)
10806{
10807 if (regime_has_2_ranges(mmu_idx)) {
10808 return extract64(tcr, 37, 2);
10809 } else if (mmu_idx == ARMMMUIdx_Stage2) {
10810 return 0; /* VTCR_EL2 */
10811 } else {
3e270f67
RH		 10812 /* Replicate the single TBI bit so we always have 2 bits. */
10813 return extract32(tcr, 20, 1) * 3;
b830a5ee
RH		 10814 }
10815}
10816
10817static int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx)
10818{
10819 if (regime_has_2_ranges(mmu_idx)) {
10820 return extract64(tcr, 51, 2);
10821 } else if (mmu_idx == ARMMMUIdx_Stage2) {
10822 return 0; /* VTCR_EL2 */
10823 } else {
3e270f67
RH		 10824 /* Replicate the single TBID bit so we always have 2 bits. */
10825 return extract32(tcr, 29, 1) * 3;
b830a5ee
RH		 10826 }
10827}
10828
81ae05fa
RH		 10829static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx)
10830{
10831 if (regime_has_2_ranges(mmu_idx)) {
10832 return extract64(tcr, 57, 2);
10833 } else {
10834 /* Replicate the single TCMA bit so we always have 2 bits. */
10835 return extract32(tcr, 30, 1) * 3;
10836 }
10837}
10838
b830a5ee
RH		 10839ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
10840 ARMMMUIdx mmu_idx, bool data)
ba97be9f
RH		 10841{
10842 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
b830a5ee 10843 bool epd, hpd, using16k, using64k;
c36c65ea 10844 int select, tsz, tbi, max_tsz;
ba97be9f 10845
339370b9 10846 if (!regime_has_2_ranges(mmu_idx)) {
71d18164 10847 select = 0;
ba97be9f
RH		 10848 tsz = extract32(tcr, 0, 6);
10849 using64k = extract32(tcr, 14, 1);
10850 using16k = extract32(tcr, 15, 1);
97fa9350 10851 if (mmu_idx == ARMMMUIdx_Stage2) {
ba97be9f 10852 /* VTCR_EL2 */
b830a5ee 10853 hpd = false;
ba97be9f 10854 } else {
ba97be9f
RH		 10855 hpd = extract32(tcr, 24, 1);
10856 }
10857 epd = false;
ba97be9f 10858 } else {
71d18164
RH		 10859 /*
10860 * Bit 55 is always between the two regions, and is canonical for
10861 * determining if address tagging is enabled.
10862 */
10863 select = extract64(va, 55, 1);
10864 if (!select) {
10865 tsz = extract32(tcr, 0, 6);
10866 epd = extract32(tcr, 7, 1);
10867 using64k = extract32(tcr, 14, 1);
10868 using16k = extract32(tcr, 15, 1);
71d18164 10869 hpd = extract64(tcr, 41, 1);
71d18164
RH		 10870 } else {
10871 int tg = extract32(tcr, 30, 2);
10872 using16k = tg == 1;
10873 using64k = tg == 3;
10874 tsz = extract32(tcr, 16, 6);
10875 epd = extract32(tcr, 23, 1);
71d18164 10876 hpd = extract64(tcr, 42, 1);
71d18164 10877 }
ba97be9f 10878 }
c36c65ea
RDC		 10879
10880 if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
10881 max_tsz = 48 - using64k;
10882 } else {
10883 max_tsz = 39;
10884 }
10885
10886 tsz = MIN(tsz, max_tsz);
ba97be9f
RH		 10887 tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
10888
b830a5ee
RH		 10889 /* Present TBI as a composite with TBID. */
10890 tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
10891 if (!data) {
10892 tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
10893 }
10894 tbi = (tbi >> select) & 1;
10895
ba97be9f
RH		 10896 return (ARMVAParameters) {
10897 .tsz = tsz,
10898 .select = select,
10899 .tbi = tbi,
10900 .epd = epd,
10901 .hpd = hpd,
10902 .using16k = using16k,
10903 .using64k = using64k,
10904 };
10905}
10906
c47eaf9f 10907#ifndef CONFIG_USER_ONLY
ba97be9f
RH		 10908static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
10909 ARMMMUIdx mmu_idx)
10910{
10911 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
10912 uint32_t el = regime_el(env, mmu_idx);
10913 int select, tsz;
10914 bool epd, hpd;
10915
97fa9350 10916 if (mmu_idx == ARMMMUIdx_Stage2) {
ba97be9f
RH		 10917 /* VTCR */
10918 bool sext = extract32(tcr, 4, 1);
10919 bool sign = extract32(tcr, 3, 1);
10920
10921 /*
10922 * If the sign-extend bit is not the same as t0sz[3], the result
10923 * is unpredictable. Flag this as a guest error.
10924 */
10925 if (sign != sext) {
10926 qemu_log_mask(LOG_GUEST_ERROR,
10927 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
10928 }
10929 tsz = sextract32(tcr, 0, 4) + 8;
10930 select = 0;
10931 hpd = false;
10932 epd = false;
10933 } else if (el == 2) {
10934 /* HTCR */
10935 tsz = extract32(tcr, 0, 3);
10936 select = 0;
10937 hpd = extract64(tcr, 24, 1);
10938 epd = false;
10939 } else {
10940 int t0sz = extract32(tcr, 0, 3);
10941 int t1sz = extract32(tcr, 16, 3);
10942
10943 if (t1sz == 0) {
10944 select = va > (0xffffffffu >> t0sz);
10945 } else {
10946 /* Note that we will detect errors later. */
10947 select = va >= ~(0xffffffffu >> t1sz);
10948 }
10949 if (!select) {
10950 tsz = t0sz;
10951 epd = extract32(tcr, 7, 1);
10952 hpd = extract64(tcr, 41, 1);
10953 } else {
10954 tsz = t1sz;
10955 epd = extract32(tcr, 23, 1);
10956 hpd = extract64(tcr, 42, 1);
10957 }
10958 /* For aarch32, hpd0 is not enabled without t2e as well. */
10959 hpd &= extract32(tcr, 6, 1);
10960 }
10961
10962 return (ARMVAParameters) {
10963 .tsz = tsz,
10964 .select = select,
10965 .epd = epd,
10966 .hpd = hpd,
10967 };
10968}
10969
ff7de2fc
PM		 10970/**
10971 * get_phys_addr_lpae: perform one stage of page table walk, LPAE format
10972 *
10973 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
10974 * prot and page_size may not be filled in, and the populated fsr value provides
10975 * information on why the translation aborted, in the format of a long-format
10976 * DFSR/IFSR fault register, with the following caveats:
10977 * * the WnR bit is never set (the caller must do this).
10978 *
10979 * @env: CPUARMState
10980 * @address: virtual address to get physical address for
10981 * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
10982 * @mmu_idx: MMU index indicating required translation regime
10983 * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page table
10984 * walk), must be true if this is stage 2 of a stage 1+2 walk for an
10985 * EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ignored.
10986 * @phys_ptr: set to the physical address corresponding to the virtual address
10987 * @attrs: set to the memory transaction attributes to use
10988 * @prot: set to the permissions for the page containing phys_ptr
10989 * @page_size_ptr: set to the size of the page containing phys_ptr
10990 * @fi: set to fault info if the translation fails
10991 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
10992 */
98e87797 10993static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
03ae85f8 10994 MMUAccessType access_type, ARMMMUIdx mmu_idx,
ff7de2fc 10995 bool s1_is_el0,
b7cc4e82 10996 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
da909b2c 10997 target_ulong *page_size_ptr,
5b2d261d 10998 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
3dde962f 10999{
2fc0cc0e 11000 ARMCPU *cpu = env_archcpu(env);
1853d5a9 11001 CPUState *cs = CPU(cpu);
3dde962f 11002 /* Read an LPAE long-descriptor translation table. */
da909b2c 11003 ARMFaultType fault_type = ARMFault_Translation;
1b4093ea 11004 uint32_t level;
ba97be9f 11005 ARMVAParameters param;
3dde962f 11006 uint64_t ttbr;
dddb5223 11007 hwaddr descaddr, indexmask, indexmask_grainsize;
3dde962f 11008 uint32_t tableattrs;
36d820af 11009 target_ulong page_size;
3dde962f 11010 uint32_t attrs;
ba97be9f
RH		 11011 int32_t stride;
11012 int addrsize, inputsize;
0480f69a 11013 TCR *tcr = regime_tcr(env, mmu_idx);
d8e052b3 11014 int ap, ns, xn, pxn;
88e8add8 11015 uint32_t el = regime_el(env, mmu_idx);
6109769a 11016 uint64_t descaddrmask;
6e99f762 11017 bool aarch64 = arm_el_is_aa64(env, el);
1bafc2ba 11018 bool guarded = false;
0480f69a 11019
07d1be3b 11020 /* TODO: This code does not support shareability levels. */
6e99f762 11021 if (aarch64) {
ba97be9f
RH		 11022 param = aa64_va_parameters(env, address, mmu_idx,
11023 access_type != MMU_INST_FETCH);
1b4093ea 11024 level = 0;
ba97be9f
RH		 11025 addrsize = 64 - 8 * param.tbi;
11026 inputsize = 64 - param.tsz;
d0a2cbce 11027 } else {
ba97be9f 11028 param = aa32_va_parameters(env, address, mmu_idx);
1b4093ea 11029 level = 1;
97fa9350 11030 addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32);
ba97be9f 11031 inputsize = addrsize - param.tsz;
2c8dd318 11032 }
3dde962f 11033
ba97be9f
RH		 11034 /*
11035 * We determined the region when collecting the parameters, but we
11036 * have not yet validated that the address is valid for the region.
11037 * Extract the top bits and verify that they all match select.
36d820af
RH		 11038 *
11039 * For aa32, if inputsize == addrsize, then we have selected the
11040 * region by exclusion in aa32_va_parameters and there is no more
11041 * validation to do here.
11042 */
11043 if (inputsize < addrsize) {
11044 target_ulong top_bits = sextract64(address, inputsize,
11045 addrsize - inputsize);
03f27724 11046 if (-top_bits != param.select) {
36d820af
RH		 11047 /* The gap between the two regions is a Translation fault */
11048 fault_type = ARMFault_Translation;
11049 goto do_fault;
11050 }
3dde962f
PM		 11051 }
11052
ba97be9f
RH		 11053 if (param.using64k) {
11054 stride = 13;
11055 } else if (param.using16k) {
11056 stride = 11;
11057 } else {
11058 stride = 9;
11059 }
11060
3dde962f
PM		 11061 /* Note that QEMU ignores shareability and cacheability attributes,
11062 * so we don't need to do anything with the SH, ORGN, IRGN fields
11063 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
11064 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
11065 * implement any ASID-like capability so we can ignore it (instead
11066 * we will always flush the TLB any time the ASID is changed).
11067 */
ba97be9f 11068 ttbr = regime_ttbr(env, mmu_idx, param.select);
3dde962f 11069
0480f69a 11070 /* Here we should have set up all the parameters for the translation:
6e99f762 11071 * inputsize, ttbr, epd, stride, tbi
0480f69a
PM		 11072 */
11073
ba97be9f 11074 if (param.epd) {
88e8add8
GB		 11075 /* Translation table walk disabled => Translation fault on TLB miss
11076 * Note: This is always 0 on 64-bit EL2 and EL3.
11077 */
3dde962f
PM		 11078 goto do_fault;
11079 }
11080
97fa9350 11081 if (mmu_idx != ARMMMUIdx_Stage2) {
1853d5a9
EI		 11082 /* The starting level depends on the virtual address size (which can
11083 * be up to 48 bits) and the translation granule size. It indicates
11084 * the number of strides (stride bits at a time) needed to
11085 * consume the bits of the input address. In the pseudocode this is:
11086 * level = 4 - RoundUp((inputsize - grainsize) / stride)
11087 * where their 'inputsize' is our 'inputsize', 'grainsize' is
11088 * our 'stride + 3' and 'stride' is our 'stride'.
11089 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
11090 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
11091 * = 4 - (inputsize - 4) / stride;
11092 */
11093 level = 4 - (inputsize - 4) / stride;
11094 } else {
11095 /* For stage 2 translations the starting level is specified by the
11096 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
11097 */
1b4093ea
SS		 11098 uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2);
11099 uint32_t startlevel;
1853d5a9
EI		 11100 bool ok;
11101
6e99f762 11102 if (!aarch64 || stride == 9) {
1853d5a9 11103 /* AArch32 or 4KB pages */
1b4093ea 11104 startlevel = 2 - sl0;
c36c65ea
RDC		 11105
11106 if (cpu_isar_feature(aa64_st, cpu)) {
11107 startlevel &= 3;
11108 }
1853d5a9
EI		 11109 } else {
11110 /* 16KB or 64KB pages */
1b4093ea 11111 startlevel = 3 - sl0;
1853d5a9
EI		 11112 }
11113
11114 /* Check that the starting level is valid. */
6e99f762 11115 ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
1b4093ea 11116 inputsize, stride);
1853d5a9 11117 if (!ok) {
da909b2c 11118 fault_type = ARMFault_Translation;
1853d5a9
EI		 11119 goto do_fault;
11120 }
1b4093ea 11121 level = startlevel;
1853d5a9 11122 }
3dde962f 11123
dddb5223
SS		 11124 indexmask_grainsize = (1ULL << (stride + 3)) - 1;
11125 indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;
3dde962f
PM		 11126
11127 /* Now we can extract the actual base address from the TTBR */
2c8dd318 11128 descaddr = extract64(ttbr, 0, 48);
41a4bf1f
PM		 11129 /*
11130 * We rely on this masking to clear the RES0 bits at the bottom of the TTBR
11131 * and also to mask out CnP (bit 0) which could validly be non-zero.
11132 */
dddb5223 11133 descaddr &= ~indexmask;
3dde962f 11134
6109769a 11135 /* The address field in the descriptor goes up to bit 39 for ARMv7
dddb5223
SS		 11136 * but up to bit 47 for ARMv8, but we use the descaddrmask
11137 * up to bit 39 for AArch32, because we don't need other bits in that case
11138 * to construct next descriptor address (anyway they should be all zeroes).
6109769a 11139 */
6e99f762 11140 descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) &
dddb5223 11141 ~indexmask_grainsize;
6109769a 11142
ebca90e4
PM		 11143 /* Secure accesses start with the page table in secure memory and
11144 * can be downgraded to non-secure at any step. Non-secure accesses
11145 * remain non-secure. We implement this by just ORing in the NSTable/NS
11146 * bits at each step.
11147 */
11148 tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
3dde962f
PM		 11149 for (;;) {
11150 uint64_t descriptor;
ebca90e4 11151 bool nstable;
3dde962f 11152
dddb5223 11153 descaddr |= (address >> (stride * (4 - level))) & indexmask;
2c8dd318 11154 descaddr &= ~7ULL;
ebca90e4 11155 nstable = extract32(tableattrs, 4, 1);
3795a6de 11156 descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi);
3b39d734 11157 if (fi->type != ARMFault_None) {
37785977
EI		 11158 goto do_fault;
11159 }
11160
3dde962f
PM		 11161 if (!(descriptor & 1) ||
11162 (!(descriptor & 2) && (level == 3))) {
11163 /* Invalid, or the Reserved level 3 encoding */
11164 goto do_fault;
11165 }
6109769a 11166 descaddr = descriptor & descaddrmask;
3dde962f
PM		 11167
11168 if ((descriptor & 2) && (level < 3)) {
037c13c5 11169 /* Table entry. The top five bits are attributes which may
3dde962f
PM		 11170 * propagate down through lower levels of the table (and
11171 * which are all arranged so that 0 means "no effect", so
11172 * we can gather them up by ORing in the bits at each level).
11173 */
11174 tableattrs |= extract64(descriptor, 59, 5);
11175 level++;
dddb5223 11176 indexmask = indexmask_grainsize;
3dde962f
PM		 11177 continue;
11178 }
11179 /* Block entry at level 1 or 2, or page entry at level 3.
11180 * These are basically the same thing, although the number
11181 * of bits we pull in from the vaddr varies.
11182 */
973a5434 11183 page_size = (1ULL << ((stride * (4 - level)) + 3));
3dde962f 11184 descaddr |= (address & (page_size - 1));
6ab1a5ee 11185 /* Extract attributes from the descriptor */
d615efac
IC		 11186 attrs = extract64(descriptor, 2, 10)
11187 | (extract64(descriptor, 52, 12) << 10);
6ab1a5ee 11188
97fa9350 11189 if (mmu_idx == ARMMMUIdx_Stage2) {
6ab1a5ee
EI		 11190 /* Stage 2 table descriptors do not include any attribute fields */
11191 break;
11192 }
11193 /* Merge in attributes from table descriptors */
037c13c5 11194 attrs |= nstable << 3; /* NS */
1bafc2ba 11195 guarded = extract64(descriptor, 50, 1); /* GP */
ba97be9f 11196 if (param.hpd) {
037c13c5
RH		 11197 /* HPD disables all the table attributes except NSTable. */
11198 break;
11199 }
11200 attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
3dde962f
PM		 11201 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
11202 * means "force PL1 access only", which means forcing AP[1] to 0.
11203 */
037c13c5
RH		 11204 attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */
11205 attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */
3dde962f
PM		 11206 break;
11207 }
11208 /* Here descaddr is the final physical address, and attributes
11209 * are all in attrs.
11210 */
da909b2c 11211 fault_type = ARMFault_AccessFlag;
3dde962f
PM		 11212 if ((attrs & (1 << 8)) == 0) {
11213 /* Access flag */
11214 goto do_fault;
11215 }
d8e052b3
AJ		 11216
11217 ap = extract32(attrs, 4, 2);
d8e052b3 11218
97fa9350 11219 if (mmu_idx == ARMMMUIdx_Stage2) {
6ab1a5ee 11220 ns = true;
ce3125be
PM		 11221 xn = extract32(attrs, 11, 2);
11222 *prot = get_S2prot(env, ap, xn, s1_is_el0);
6ab1a5ee
EI		 11223 } else {
11224 ns = extract32(attrs, 3, 1);
ce3125be 11225 xn = extract32(attrs, 12, 1);
6ab1a5ee 11226 pxn = extract32(attrs, 11, 1);
6e99f762 11227 *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
6ab1a5ee 11228 }
d8e052b3 11229
da909b2c 11230 fault_type = ARMFault_Permission;
d8e052b3 11231 if (!(*prot & (1 << access_type))) {
3dde962f
PM		 11232 goto do_fault;
11233 }
3dde962f 11234
8bf5b6a9
PM		 11235 if (ns) {
11236 /* The NS bit will (as required by the architecture) have no effect if
11237 * the CPU doesn't support TZ or this is a non-secure translation
11238 * regime, because the attribute will already be non-secure.
11239 */
11240 txattrs->secure = false;
11241 }
1bafc2ba
RH		 11242 /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
11243 if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) {
149d3b31 11244 arm_tlb_bti_gp(txattrs) = true;
1bafc2ba 11245 }
5b2d261d 11246
7e98e21c
RH		 11247 if (mmu_idx == ARMMMUIdx_Stage2) {
11248 cacheattrs->attrs = convert_stage2_attrs(env, extract32(attrs, 0, 4));
11249 } else {
11250 /* Index into MAIR registers for cache attributes */
11251 uint8_t attrindx = extract32(attrs, 0, 3);
11252 uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
11253 assert(attrindx <= 7);
11254 cacheattrs->attrs = extract64(mair, attrindx * 8, 8);
5b2d261d 11255 }
7e98e21c 11256 cacheattrs->shareability = extract32(attrs, 6, 2);
5b2d261d 11257
3dde962f
PM		 11258 *phys_ptr = descaddr;
11259 *page_size_ptr = page_size;
b7cc4e82 11260 return false;
3dde962f
PM		 11261
11262do_fault:
da909b2c
PM		 11263 fi->type = fault_type;
11264 fi->level = level;
37785977 11265 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
97fa9350 11266 fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_Stage2);
b7cc4e82 11267 return true;
3dde962f
PM		 11268}
11269
f6bda88f
PC		 11270static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
11271 ARMMMUIdx mmu_idx,
11272 int32_t address, int *prot)
11273{
3a00d560
MD		 11274 if (!arm_feature(env, ARM_FEATURE_M)) {
11275 *prot = PAGE_READ | PAGE_WRITE;
11276 switch (address) {
11277 case 0xF0000000 ... 0xFFFFFFFF:
11278 if (regime_sctlr(env, mmu_idx) & SCTLR_V) {
11279 /* hivecs execing is ok */
11280 *prot |= PAGE_EXEC;
11281 }
11282 break;
11283 case 0x00000000 ... 0x7FFFFFFF:
f6bda88f 11284 *prot |= PAGE_EXEC;
3a00d560
MD		 11285 break;
11286 }
11287 } else {
11288 /* Default system address map for M profile cores.
11289 * The architecture specifies which regions are execute-never;
11290 * at the MPU level no other checks are defined.
11291 */
11292 switch (address) {
11293 case 0x00000000 ... 0x1fffffff: /* ROM */
11294 case 0x20000000 ... 0x3fffffff: /* SRAM */
11295 case 0x60000000 ... 0x7fffffff: /* RAM */
11296 case 0x80000000 ... 0x9fffffff: /* RAM */
11297 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
11298 break;
11299 case 0x40000000 ... 0x5fffffff: /* Peripheral */
11300 case 0xa0000000 ... 0xbfffffff: /* Device */
11301 case 0xc0000000 ... 0xdfffffff: /* Device */
11302 case 0xe0000000 ... 0xffffffff: /* System */
11303 *prot = PAGE_READ | PAGE_WRITE;
11304 break;
11305 default:
11306 g_assert_not_reached();
f6bda88f 11307 }
f6bda88f 11308 }
f6bda88f
PC		 11309}
11310
29c483a5
MD		 11311static bool pmsav7_use_background_region(ARMCPU *cpu,
11312 ARMMMUIdx mmu_idx, bool is_user)
11313{
11314 /* Return true if we should use the default memory map as a
11315 * "background" region if there are no hits against any MPU regions.
11316 */
11317 CPUARMState *env = &cpu->env;
11318
11319 if (is_user) {
11320 return false;
11321 }
11322
11323 if (arm_feature(env, ARM_FEATURE_M)) {
ecf5e8ea
PM		 11324 return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)]
11325 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
29c483a5
MD		 11326 } else {
11327 return regime_sctlr(env, mmu_idx) & SCTLR_BR;
11328 }
11329}
11330
38aaa60c
PM		 11331static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address)
11332{
11333 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
11334 return arm_feature(env, ARM_FEATURE_M) &&
11335 extract32(address, 20, 12) == 0xe00;
11336}
11337
bf446a11
PM		 11338static inline bool m_is_system_region(CPUARMState *env, uint32_t address)
11339{
11340 /* True if address is in the M profile system region
11341 * 0xe0000000 - 0xffffffff
11342 */
11343 return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7;
11344}
11345
f6bda88f 11346static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
03ae85f8 11347 MMUAccessType access_type, ARMMMUIdx mmu_idx,
9375ad15 11348 hwaddr *phys_ptr, int *prot,
e5e40999 11349 target_ulong *page_size,
9375ad15 11350 ARMMMUFaultInfo *fi)
f6bda88f 11351{
2fc0cc0e 11352 ARMCPU *cpu = env_archcpu(env);
f6bda88f
PC		 11353 int n;
11354 bool is_user = regime_is_user(env, mmu_idx);
11355
11356 *phys_ptr = address;
e5e40999 11357 *page_size = TARGET_PAGE_SIZE;
f6bda88f
PC		 11358 *prot = 0;
11359
38aaa60c
PM		 11360 if (regime_translation_disabled(env, mmu_idx) ||
11361 m_is_ppb_region(env, address)) {
11362 /* MPU disabled or M profile PPB access: use default memory map.
11363 * The other case which uses the default memory map in the
11364 * v7M ARM ARM pseudocode is exception vector reads from the vector
11365 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
11366 * which always does a direct read using address_space_ldl(), rather
11367 * than going via this function, so we don't need to check that here.
11368 */
f6bda88f
PC		 11369 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
11370 } else { /* MPU enabled */
11371 for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
11372 /* region search */
11373 uint32_t base = env->pmsav7.drbar[n];
11374 uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
11375 uint32_t rmask;
11376 bool srdis = false;
11377
11378 if (!(env->pmsav7.drsr[n] & 0x1)) {
11379 continue;
11380 }
11381
11382 if (!rsize) {
c9f9f124
MD		 11383 qemu_log_mask(LOG_GUEST_ERROR,
11384 "DRSR[%d]: Rsize field cannot be 0\n", n);
f6bda88f
PC		 11385 continue;
11386 }
11387 rsize++;
11388 rmask = (1ull << rsize) - 1;
11389
11390 if (base & rmask) {
c9f9f124
MD		 11391 qemu_log_mask(LOG_GUEST_ERROR,
11392 "DRBAR[%d]: 0x%" PRIx32 " misaligned "
11393 "to DRSR region size, mask = 0x%" PRIx32 "\n",
11394 n, base, rmask);
f6bda88f
PC		 11395 continue;
11396 }
11397
11398 if (address < base || address > base + rmask) {
9d2b5a58
PM		 11399 /*
11400 * Address not in this region. We must check whether the
11401 * region covers addresses in the same page as our address.
11402 * In that case we must not report a size that covers the
11403 * whole page for a subsequent hit against a different MPU
11404 * region or the background region, because it would result in
11405 * incorrect TLB hits for subsequent accesses to addresses that
11406 * are in this MPU region.
11407 */
11408 if (ranges_overlap(base, rmask,
11409 address & TARGET_PAGE_MASK,
11410 TARGET_PAGE_SIZE)) {
11411 *page_size = 1;
11412 }
f6bda88f
PC		 11413 continue;
11414 }
11415
11416 /* Region matched */
11417
11418 if (rsize >= 8) { /* no subregions for regions < 256 bytes */
11419 int i, snd;
11420 uint32_t srdis_mask;
11421
11422 rsize -= 3; /* sub region size (power of 2) */
11423 snd = ((address - base) >> rsize) & 0x7;
11424 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
11425
11426 srdis_mask = srdis ? 0x3 : 0x0;
11427 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
11428 /* This will check in groups of 2, 4 and then 8, whether
11429 * the subregion bits are consistent. rsize is incremented
11430 * back up to give the region size, considering consistent
11431 * adjacent subregions as one region. Stop testing if rsize
11432 * is already big enough for an entire QEMU page.
11433 */
11434 int snd_rounded = snd & ~(i - 1);
11435 uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
11436 snd_rounded + 8, i);
11437 if (srdis_mask ^ srdis_multi) {
11438 break;
11439 }
11440 srdis_mask = (srdis_mask << i) | srdis_mask;
11441 rsize++;
11442 }
11443 }
f6bda88f
PC		 11444 if (srdis) {
11445 continue;
11446 }
e5e40999
PM		 11447 if (rsize < TARGET_PAGE_BITS) {
11448 *page_size = 1 << rsize;
11449 }
f6bda88f
PC		 11450 break;
11451 }
11452
11453 if (n == -1) { /* no hits */
29c483a5 11454 if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
f6bda88f 11455 /* background fault */
9375ad15 11456 fi->type = ARMFault_Background;
f6bda88f
PC		 11457 return true;
11458 }
11459 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
11460 } else { /* a MPU hit! */
11461 uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
bf446a11
PM		 11462 uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1);
11463
11464 if (m_is_system_region(env, address)) {
11465 /* System space is always execute never */
11466 xn = 1;
11467 }
f6bda88f
PC		 11468
11469 if (is_user) { /* User mode AP bit decoding */
11470 switch (ap) {
11471 case 0:
11472 case 1:
11473 case 5:
11474 break; /* no access */
11475 case 3:
11476 *prot |= PAGE_WRITE;
11477 /* fall through */
11478 case 2:
11479 case 6:
11480 *prot |= PAGE_READ | PAGE_EXEC;
11481 break;
8638f1ad
PM		 11482 case 7:
11483 /* for v7M, same as 6; for R profile a reserved value */
11484 if (arm_feature(env, ARM_FEATURE_M)) {
11485 *prot |= PAGE_READ | PAGE_EXEC;
11486 break;
11487 }
11488 /* fall through */
f6bda88f
PC		 11489 default:
11490 qemu_log_mask(LOG_GUEST_ERROR,
c9f9f124
MD		 11491 "DRACR[%d]: Bad value for AP bits: 0x%"
11492 PRIx32 "\n", n, ap);
f6bda88f
PC		 11493 }
11494 } else { /* Priv. mode AP bits decoding */
11495 switch (ap) {
11496 case 0:
11497 break; /* no access */
11498 case 1:
11499 case 2:
11500 case 3:
11501 *prot |= PAGE_WRITE;
11502 /* fall through */
11503 case 5:
11504 case 6:
11505 *prot |= PAGE_READ | PAGE_EXEC;
11506 break;
8638f1ad
PM		 11507 case 7:
11508 /* for v7M, same as 6; for R profile a reserved value */
11509 if (arm_feature(env, ARM_FEATURE_M)) {
11510 *prot |= PAGE_READ | PAGE_EXEC;
11511 break;
11512 }
11513 /* fall through */
f6bda88f
PC		 11514 default:
11515 qemu_log_mask(LOG_GUEST_ERROR,
c9f9f124
MD		 11516 "DRACR[%d]: Bad value for AP bits: 0x%"
11517 PRIx32 "\n", n, ap);
f6bda88f
PC		 11518 }
11519 }
11520
11521 /* execute never */
bf446a11 11522 if (xn) {
f6bda88f
PC		 11523 *prot &= ~PAGE_EXEC;
11524 }
11525 }
11526 }
11527
9375ad15
PM		 11528 fi->type = ARMFault_Permission;
11529 fi->level = 1;
f6bda88f
PC		 11530 return !(*prot & (1 << access_type));
11531}
11532
35337cc3
PM		 11533static bool v8m_is_sau_exempt(CPUARMState *env,
11534 uint32_t address, MMUAccessType access_type)
11535{
11536 /* The architecture specifies that certain address ranges are
11537 * exempt from v8M SAU/IDAU checks.
11538 */
11539 return
11540 (access_type == MMU_INST_FETCH && m_is_system_region(env, address)) ||
11541 (address >= 0xe0000000 && address <= 0xe0002fff) ||
11542 (address >= 0xe000e000 && address <= 0xe000efff) ||
11543 (address >= 0xe002e000 && address <= 0xe002efff) ||
11544 (address >= 0xe0040000 && address <= 0xe0041fff) ||
11545 (address >= 0xe00ff000 && address <= 0xe00fffff);
11546}
11547
787a7e76 11548void v8m_security_lookup(CPUARMState *env, uint32_t address,
35337cc3
PM		 11549 MMUAccessType access_type, ARMMMUIdx mmu_idx,
11550 V8M_SAttributes *sattrs)
11551{
11552 /* Look up the security attributes for this address. Compare the
11553 * pseudocode SecurityCheck() function.
11554 * We assume the caller has zero-initialized *sattrs.
11555 */
2fc0cc0e 11556 ARMCPU *cpu = env_archcpu(env);
35337cc3 11557 int r;
181962fd
PM		 11558 bool idau_exempt = false, idau_ns = true, idau_nsc = true;
11559 int idau_region = IREGION_NOTVALID;
72042435
PM		 11560 uint32_t addr_page_base = address & TARGET_PAGE_MASK;
11561 uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
35337cc3 11562
181962fd
PM		 11563 if (cpu->idau) {
11564 IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau);
11565 IDAUInterface *ii = IDAU_INTERFACE(cpu->idau);
11566
11567 iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns,
11568 &idau_nsc);
11569 }
35337cc3
PM		 11570
11571 if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) {
11572 /* 0xf0000000..0xffffffff is always S for insn fetches */
11573 return;
11574 }
11575
181962fd 11576 if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) {
35337cc3
PM		 11577 sattrs->ns = !regime_is_secure(env, mmu_idx);
11578 return;
11579 }
11580
181962fd
PM		 11581 if (idau_region != IREGION_NOTVALID) {
11582 sattrs->irvalid = true;
11583 sattrs->iregion = idau_region;
11584 }
11585
35337cc3
PM		 11586 switch (env->sau.ctrl & 3) {
11587 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
11588 break;
11589 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
11590 sattrs->ns = true;
11591 break;
11592 default: /* SAU.ENABLE == 1 */
11593 for (r = 0; r < cpu->sau_sregion; r++) {
11594 if (env->sau.rlar[r] & 1) {
11595 uint32_t base = env->sau.rbar[r] & ~0x1f;
11596 uint32_t limit = env->sau.rlar[r] | 0x1f;
11597
11598 if (base <= address && limit >= address) {
72042435
PM		 11599 if (base > addr_page_base || limit < addr_page_limit) {
11600 sattrs->subpage = true;
11601 }
35337cc3
PM		 11602 if (sattrs->srvalid) {
11603 /* If we hit in more than one region then we must report
11604 * as Secure, not NS-Callable, with no valid region
11605 * number info.
11606 */
11607 sattrs->ns = false;
11608 sattrs->nsc = false;
11609 sattrs->sregion = 0;
11610 sattrs->srvalid = false;
11611 break;
11612 } else {
11613 if (env->sau.rlar[r] & 2) {
11614 sattrs->nsc = true;
11615 } else {
11616 sattrs->ns = true;
11617 }
11618 sattrs->srvalid = true;
11619 sattrs->sregion = r;
11620 }
9d2b5a58
PM		 11621 } else {
11622 /*
11623 * Address not in this region. We must check whether the
11624 * region covers addresses in the same page as our address.
11625 * In that case we must not report a size that covers the
11626 * whole page for a subsequent hit against a different MPU
11627 * region or the background region, because it would result
11628 * in incorrect TLB hits for subsequent accesses to
11629 * addresses that are in this MPU region.
11630 */
11631 if (limit >= base &&
11632 ranges_overlap(base, limit - base + 1,
11633 addr_page_base,
11634 TARGET_PAGE_SIZE)) {
11635 sattrs->subpage = true;
11636 }
35337cc3
PM		 11637 }
11638 }
11639 }
7e3f1223
TR		 11640 break;
11641 }
35337cc3 11642
7e3f1223
TR		 11643 /*
11644 * The IDAU will override the SAU lookup results if it specifies
11645 * higher security than the SAU does.
11646 */
11647 if (!idau_ns) {
11648 if (sattrs->ns || (!idau_nsc && sattrs->nsc)) {
11649 sattrs->ns = false;
11650 sattrs->nsc = idau_nsc;
181962fd 11651 }
35337cc3
PM		 11652 }
11653}
11654
787a7e76 11655bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
54317c0f
PM		 11656 MMUAccessType access_type, ARMMMUIdx mmu_idx,
11657 hwaddr *phys_ptr, MemTxAttrs *txattrs,
72042435
PM		 11658 int *prot, bool *is_subpage,
11659 ARMMMUFaultInfo *fi, uint32_t *mregion)
54317c0f
PM		 11660{
11661 /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
11662 * that a full phys-to-virt translation does).
11663 * mregion is (if not NULL) set to the region number which matched,
11664 * or -1 if no region number is returned (MPU off, address did not
11665 * hit a region, address hit in multiple regions).
72042435
PM		 11666 * We set is_subpage to true if the region hit doesn't cover the
11667 * entire TARGET_PAGE the address is within.
54317c0f 11668 */
2fc0cc0e 11669 ARMCPU *cpu = env_archcpu(env);
504e3cc3 11670 bool is_user = regime_is_user(env, mmu_idx);
62c58ee0 11671 uint32_t secure = regime_is_secure(env, mmu_idx);
504e3cc3
PM		 11672 int n;
11673 int matchregion = -1;
11674 bool hit = false;
72042435
PM		 11675 uint32_t addr_page_base = address & TARGET_PAGE_MASK;
11676 uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
504e3cc3 11677
72042435 11678 *is_subpage = false;
504e3cc3
PM		 11679 *phys_ptr = address;
11680 *prot = 0;
54317c0f
PM		 11681 if (mregion) {
11682 *mregion = -1;
35337cc3
PM		 11683 }
11684
504e3cc3
PM		 11685 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
11686 * was an exception vector read from the vector table (which is always
11687 * done using the default system address map), because those accesses
11688 * are done in arm_v7m_load_vector(), which always does a direct
11689 * read using address_space_ldl(), rather than going via this function.
11690 */
11691 if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
11692 hit = true;
11693 } else if (m_is_ppb_region(env, address)) {
11694 hit = true;
504e3cc3 11695 } else {
cff21316
PM		 11696 if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) {
11697 hit = true;
11698 }
11699
504e3cc3
PM		 11700 for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
11701 /* region search */
11702 /* Note that the base address is bits [31:5] from the register
11703 * with bits [4:0] all zeroes, but the limit address is bits
11704 * [31:5] from the register with bits [4:0] all ones.
11705 */
62c58ee0
PM		 11706 uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f;
11707 uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f;
504e3cc3 11708
62c58ee0 11709 if (!(env->pmsav8.rlar[secure][n] & 0x1)) {
504e3cc3
PM		 11710 /* Region disabled */
11711 continue;
11712 }
11713
11714 if (address < base || address > limit) {
9d2b5a58
PM		 11715 /*
11716 * Address not in this region. We must check whether the
11717 * region covers addresses in the same page as our address.
11718 * In that case we must not report a size that covers the
11719 * whole page for a subsequent hit against a different MPU
11720 * region or the background region, because it would result in
11721 * incorrect TLB hits for subsequent accesses to addresses that
11722 * are in this MPU region.
11723 */
11724 if (limit >= base &&
11725 ranges_overlap(base, limit - base + 1,
11726 addr_page_base,
11727 TARGET_PAGE_SIZE)) {
11728 *is_subpage = true;
11729 }
504e3cc3
PM		 11730 continue;
11731 }
11732
72042435
PM		 11733 if (base > addr_page_base || limit < addr_page_limit) {
11734 *is_subpage = true;
11735 }
11736
cff21316 11737 if (matchregion != -1) {
504e3cc3
PM		 11738 /* Multiple regions match -- always a failure (unlike
11739 * PMSAv7 where highest-numbered-region wins)
11740 */
3f551b5b
PM		 11741 fi->type = ARMFault_Permission;
11742 fi->level = 1;
504e3cc3
PM		 11743 return true;
11744 }
11745
11746 matchregion = n;
11747 hit = true;
504e3cc3
PM		 11748 }
11749 }
11750
11751 if (!hit) {
11752 /* background fault */
3f551b5b 11753 fi->type = ARMFault_Background;
504e3cc3
PM		 11754 return true;
11755 }
11756
11757 if (matchregion == -1) {
11758 /* hit using the background region */
11759 get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
11760 } else {
62c58ee0
PM		 11761 uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
11762 uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
cad8e2e3
PM		 11763 bool pxn = false;
11764
11765 if (arm_feature(env, ARM_FEATURE_V8_1M)) {
11766 pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1);
11767 }
504e3cc3
PM		 11768
11769 if (m_is_system_region(env, address)) {
11770 /* System space is always execute never */
11771 xn = 1;
11772 }
11773
11774 *prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
cad8e2e3 11775 if (*prot && !xn && !(pxn && !is_user)) {
504e3cc3
PM		 11776 *prot |= PAGE_EXEC;
11777 }
11778 /* We don't need to look the attribute up in the MAIR0/MAIR1
11779 * registers because that only tells us about cacheability.
11780 */
54317c0f
PM		 11781 if (mregion) {
11782 *mregion = matchregion;
11783 }
504e3cc3
PM		 11784 }
11785
3f551b5b
PM		 11786 fi->type = ARMFault_Permission;
11787 fi->level = 1;
504e3cc3
PM		 11788 return !(*prot & (1 << access_type));
11789}
11790
54317c0f
PM		 11791
11792static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
11793 MMUAccessType access_type, ARMMMUIdx mmu_idx,
11794 hwaddr *phys_ptr, MemTxAttrs *txattrs,
72042435
PM		 11795 int *prot, target_ulong *page_size,
11796 ARMMMUFaultInfo *fi)
54317c0f
PM		 11797{
11798 uint32_t secure = regime_is_secure(env, mmu_idx);
11799 V8M_SAttributes sattrs = {};
72042435
PM		 11800 bool ret;
11801 bool mpu_is_subpage;
54317c0f
PM		 11802
11803 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
11804 v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs);
11805 if (access_type == MMU_INST_FETCH) {
11806 /* Instruction fetches always use the MMU bank and the
11807 * transaction attribute determined by the fetch address,
11808 * regardless of CPU state. This is painful for QEMU
11809 * to handle, because it would mean we need to encode
11810 * into the mmu_idx not just the (user, negpri) information
11811 * for the current security state but also that for the
11812 * other security state, which would balloon the number
11813 * of mmu_idx values needed alarmingly.
11814 * Fortunately we can avoid this because it's not actually
11815 * possible to arbitrarily execute code from memory with
11816 * the wrong security attribute: it will always generate
11817 * an exception of some kind or another, apart from the
11818 * special case of an NS CPU executing an SG instruction
11819 * in S&NSC memory. So we always just fail the translation
11820 * here and sort things out in the exception handler
11821 * (including possibly emulating an SG instruction).
11822 */
11823 if (sattrs.ns != !secure) {
3f551b5b
PM		 11824 if (sattrs.nsc) {
11825 fi->type = ARMFault_QEMU_NSCExec;
11826 } else {
11827 fi->type = ARMFault_QEMU_SFault;
11828 }
72042435 11829 *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
54317c0f
PM		 11830 *phys_ptr = address;
11831 *prot = 0;
11832 return true;
11833 }
11834 } else {
11835 /* For data accesses we always use the MMU bank indicated
11836 * by the current CPU state, but the security attributes
11837 * might downgrade a secure access to nonsecure.
11838 */
11839 if (sattrs.ns) {
11840 txattrs->secure = false;
11841 } else if (!secure) {
11842 /* NS access to S memory must fault.
11843 * Architecturally we should first check whether the
11844 * MPU information for this address indicates that we
11845 * are doing an unaligned access to Device memory, which
11846 * should generate a UsageFault instead. QEMU does not
11847 * currently check for that kind of unaligned access though.
11848 * If we added it we would need to do so as a special case
11849 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
11850 */
3f551b5b 11851 fi->type = ARMFault_QEMU_SFault;
72042435 11852 *page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
54317c0f
PM		 11853 *phys_ptr = address;
11854 *prot = 0;
11855 return true;
11856 }
11857 }
11858 }
11859
72042435
PM		 11860 ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr,
11861 txattrs, prot, &mpu_is_subpage, fi, NULL);
72042435
PM		 11862 *page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
11863 return ret;
54317c0f
PM		 11864}
11865
13689d43 11866static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
03ae85f8 11867 MMUAccessType access_type, ARMMMUIdx mmu_idx,
53a4e5c5
PM		 11868 hwaddr *phys_ptr, int *prot,
11869 ARMMMUFaultInfo *fi)
9ee6e8bb
PB		 11870{
11871 int n;
11872 uint32_t mask;
11873 uint32_t base;
0480f69a 11874 bool is_user = regime_is_user(env, mmu_idx);
9ee6e8bb 11875
3279adb9
PM		 11876 if (regime_translation_disabled(env, mmu_idx)) {
11877 /* MPU disabled. */
11878 *phys_ptr = address;
11879 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
11880 return false;
11881 }
11882
9ee6e8bb
PB		 11883 *phys_ptr = address;
11884 for (n = 7; n >= 0; n--) {
554b0b09 11885 base = env->cp15.c6_region[n];
87c3d486 11886 if ((base & 1) == 0) {
554b0b09 11887 continue;
87c3d486 11888 }
554b0b09
PM		 11889 mask = 1 << ((base >> 1) & 0x1f);
11890 /* Keep this shift separate from the above to avoid an
11891 (undefined) << 32. */
11892 mask = (mask << 1) - 1;
87c3d486 11893 if (((base ^ address) & ~mask) == 0) {
554b0b09 11894 break;
87c3d486 11895 }
9ee6e8bb 11896 }
87c3d486 11897 if (n < 0) {
53a4e5c5 11898 fi->type = ARMFault_Background;
b7cc4e82 11899 return true;
87c3d486 11900 }
9ee6e8bb 11901
03ae85f8 11902 if (access_type == MMU_INST_FETCH) {
7e09797c 11903 mask = env->cp15.pmsav5_insn_ap;
9ee6e8bb 11904 } else {
7e09797c 11905 mask = env->cp15.pmsav5_data_ap;
9ee6e8bb
PB		 11906 }
11907 mask = (mask >> (n * 4)) & 0xf;
11908 switch (mask) {
11909 case 0:
53a4e5c5
PM		 11910 fi->type = ARMFault_Permission;
11911 fi->level = 1;
b7cc4e82 11912 return true;
9ee6e8bb 11913 case 1:
87c3d486 11914 if (is_user) {
53a4e5c5
PM		 11915 fi->type = ARMFault_Permission;
11916 fi->level = 1;
b7cc4e82 11917 return true;
87c3d486 11918 }
554b0b09
PM		 11919 *prot = PAGE_READ | PAGE_WRITE;
11920 break;
9ee6e8bb 11921 case 2:
554b0b09 11922 *prot = PAGE_READ;
87c3d486 11923 if (!is_user) {
554b0b09 11924 *prot |= PAGE_WRITE;
87c3d486 11925 }
554b0b09 11926 break;
9ee6e8bb 11927 case 3:
554b0b09
PM		 11928 *prot = PAGE_READ | PAGE_WRITE;
11929 break;
9ee6e8bb 11930 case 5:
87c3d486 11931 if (is_user) {
53a4e5c5
PM		 11932 fi->type = ARMFault_Permission;
11933 fi->level = 1;
b7cc4e82 11934 return true;
87c3d486 11935 }
554b0b09
PM		 11936 *prot = PAGE_READ;
11937 break;
9ee6e8bb 11938 case 6:
554b0b09
PM		 11939 *prot = PAGE_READ;
11940 break;
9ee6e8bb 11941 default:
554b0b09 11942 /* Bad permission. */
53a4e5c5
PM		 11943 fi->type = ARMFault_Permission;
11944 fi->level = 1;
b7cc4e82 11945 return true;
9ee6e8bb 11946 }
3ad493fc 11947 *prot |= PAGE_EXEC;
b7cc4e82 11948 return false;
9ee6e8bb
PB		 11949}
11950
5b2d261d
AB		 11951/* Combine either inner or outer cacheability attributes for normal
11952 * memory, according to table D4-42 and pseudocode procedure
11953 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
11954 *
11955 * NB: only stage 1 includes allocation hints (RW bits), leading to
11956 * some asymmetry.
11957 */
11958static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2)
11959{
11960 if (s1 == 4 || s2 == 4) {
11961 /* non-cacheable has precedence */
11962 return 4;
11963 } else if (extract32(s1, 2, 2) == 0 || extract32(s1, 2, 2) == 2) {
11964 /* stage 1 write-through takes precedence */
11965 return s1;
11966 } else if (extract32(s2, 2, 2) == 2) {
11967 /* stage 2 write-through takes precedence, but the allocation hint
11968 * is still taken from stage 1
11969 */
11970 return (2 << 2) | extract32(s1, 0, 2);
11971 } else { /* write-back */
11972 return s1;
11973 }
11974}
11975
11976/* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
11977 * and CombineS1S2Desc()
11978 *
11979 * @s1: Attributes from stage 1 walk
11980 * @s2: Attributes from stage 2 walk
11981 */
11982static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2)
11983{
337a03f0 11984 uint8_t s1lo, s2lo, s1hi, s2hi;
5b2d261d 11985 ARMCacheAttrs ret;
337a03f0
RH		 11986 bool tagged = false;
11987
11988 if (s1.attrs == 0xf0) {
11989 tagged = true;
11990 s1.attrs = 0xff;
11991 }
11992
11993 s1lo = extract32(s1.attrs, 0, 4);
11994 s2lo = extract32(s2.attrs, 0, 4);
11995 s1hi = extract32(s1.attrs, 4, 4);
11996 s2hi = extract32(s2.attrs, 4, 4);
5b2d261d
AB		 11997
11998 /* Combine shareability attributes (table D4-43) */
11999 if (s1.shareability == 2 || s2.shareability == 2) {
12000 /* if either are outer-shareable, the result is outer-shareable */
12001 ret.shareability = 2;
12002 } else if (s1.shareability == 3 || s2.shareability == 3) {
12003 /* if either are inner-shareable, the result is inner-shareable */
12004 ret.shareability = 3;
12005 } else {
12006 /* both non-shareable */
12007 ret.shareability = 0;
12008 }
12009
12010 /* Combine memory type and cacheability attributes */
12011 if (s1hi == 0 || s2hi == 0) {
12012 /* Device has precedence over normal */
12013 if (s1lo == 0 || s2lo == 0) {
12014 /* nGnRnE has precedence over anything */
12015 ret.attrs = 0;
12016 } else if (s1lo == 4 || s2lo == 4) {
12017 /* non-Reordering has precedence over Reordering */
12018 ret.attrs = 4; /* nGnRE */
12019 } else if (s1lo == 8 || s2lo == 8) {
12020 /* non-Gathering has precedence over Gathering */
12021 ret.attrs = 8; /* nGRE */
12022 } else {
12023 ret.attrs = 0xc; /* GRE */
12024 }
12025
12026 /* Any location for which the resultant memory type is any
12027 * type of Device memory is always treated as Outer Shareable.
12028 */
12029 ret.shareability = 2;
12030 } else { /* Normal memory */
12031 /* Outer/inner cacheability combine independently */
12032 ret.attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4
12033 | combine_cacheattr_nibble(s1lo, s2lo);
12034
12035 if (ret.attrs == 0x44) {
12036 /* Any location for which the resultant memory type is Normal
12037 * Inner Non-cacheable, Outer Non-cacheable is always treated
12038 * as Outer Shareable.
12039 */
12040 ret.shareability = 2;
12041 }
12042 }
12043
337a03f0
RH		 12044 /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */
12045 if (tagged && ret.attrs == 0xff) {
12046 ret.attrs = 0xf0;
12047 }
12048
5b2d261d
AB		 12049 return ret;
12050}
12051
12052
702a9357
PM		 12053/* get_phys_addr - get the physical address for this virtual address
12054 *
12055 * Find the physical address corresponding to the given virtual address,
12056 * by doing a translation table walk on MMU based systems or using the
12057 * MPU state on MPU based systems.
12058 *
b7cc4e82
PC		 12059 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
12060 * prot and page_size may not be filled in, and the populated fsr value provides
702a9357
PM		 12061 * information on why the translation aborted, in the format of a
12062 * DFSR/IFSR fault register, with the following caveats:
12063 * * we honour the short vs long DFSR format differences.
12064 * * the WnR bit is never set (the caller must do this).
f6bda88f 12065 * * for PSMAv5 based systems we don't bother to return a full FSR format
702a9357
PM		 12066 * value.
12067 *
12068 * @env: CPUARMState
12069 * @address: virtual address to get physical address for
12070 * @access_type: 0 for read, 1 for write, 2 for execute
d3649702 12071 * @mmu_idx: MMU index indicating required translation regime
702a9357 12072 * @phys_ptr: set to the physical address corresponding to the virtual address
8bf5b6a9 12073 * @attrs: set to the memory transaction attributes to use
702a9357
PM		 12074 * @prot: set to the permissions for the page containing phys_ptr
12075 * @page_size: set to the size of the page containing phys_ptr
5b2d261d
AB		 12076 * @fi: set to fault info if the translation fails
12077 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
702a9357 12078 */
ebae861f
PMD		 12079bool get_phys_addr(CPUARMState *env, target_ulong address,
12080 MMUAccessType access_type, ARMMMUIdx mmu_idx,
12081 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
12082 target_ulong *page_size,
12083 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
9ee6e8bb 12084{
452ef8cb
RH		 12085 if (mmu_idx == ARMMMUIdx_E10_0 ||
12086 mmu_idx == ARMMMUIdx_E10_1 ||
12087 mmu_idx == ARMMMUIdx_E10_1_PAN) {
9b539263
EI		 12088 /* Call ourselves recursively to do the stage 1 and then stage 2
12089 * translations.
0480f69a 12090 */
9b539263
EI		 12091 if (arm_feature(env, ARM_FEATURE_EL2)) {
12092 hwaddr ipa;
12093 int s2_prot;
12094 int ret;
5b2d261d 12095 ARMCacheAttrs cacheattrs2 = {};
9b539263
EI		 12096
12097 ret = get_phys_addr(env, address, access_type,
8bd5c820 12098 stage_1_mmu_idx(mmu_idx), &ipa, attrs,
bc52bfeb 12099 prot, page_size, fi, cacheattrs);
9b539263
EI		 12100
12101 /* If S1 fails or S2 is disabled, return early. */
97fa9350 12102 if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
9b539263
EI		 12103 *phys_ptr = ipa;
12104 return ret;
12105 }
12106
12107 /* S1 is done. Now do S2 translation. */
97fa9350 12108 ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_Stage2,
ff7de2fc 12109 mmu_idx == ARMMMUIdx_E10_0,
9b539263 12110 phys_ptr, attrs, &s2_prot,
7e98e21c 12111 page_size, fi, &cacheattrs2);
9b539263
EI		 12112 fi->s2addr = ipa;
12113 /* Combine the S1 and S2 perms. */
12114 *prot &= s2_prot;
5b2d261d 12115
7e98e21c
RH		 12116 /* If S2 fails, return early. */
12117 if (ret) {
12118 return ret;
5b2d261d
AB		 12119 }
12120
7e98e21c
RH		 12121 /* Combine the S1 and S2 cache attributes. */
12122 if (env->cp15.hcr_el2 & HCR_DC) {
12123 /*
12124 * HCR.DC forces the first stage attributes to
12125 * Normal Non-Shareable,
12126 * Inner Write-Back Read-Allocate Write-Allocate,
12127 * Outer Write-Back Read-Allocate Write-Allocate.
337a03f0 12128 * Do not overwrite Tagged within attrs.
7e98e21c 12129 */
337a03f0
RH		 12130 if (cacheattrs->attrs != 0xf0) {
12131 cacheattrs->attrs = 0xff;
12132 }
7e98e21c
RH		 12133 cacheattrs->shareability = 0;
12134 }
12135 *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2);
12136 return 0;
9b539263
EI		 12137 } else {
12138 /*
12139 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
12140 */
8bd5c820 12141 mmu_idx = stage_1_mmu_idx(mmu_idx);
9b539263 12142 }
0480f69a 12143 }
d3649702 12144
8bf5b6a9
PM		 12145 /* The page table entries may downgrade secure to non-secure, but
12146 * cannot upgrade an non-secure translation regime's attributes
12147 * to secure.
12148 */
12149 attrs->secure = regime_is_secure(env, mmu_idx);
0995bf8c 12150 attrs->user = regime_is_user(env, mmu_idx);
8bf5b6a9 12151
0480f69a
PM		 12152 /* Fast Context Switch Extension. This doesn't exist at all in v8.
12153 * In v7 and earlier it affects all stage 1 translations.
12154 */
97fa9350 12155 if (address < 0x02000000 && mmu_idx != ARMMMUIdx_Stage2
0480f69a
PM		 12156 && !arm_feature(env, ARM_FEATURE_V8)) {
12157 if (regime_el(env, mmu_idx) == 3) {
12158 address += env->cp15.fcseidr_s;
12159 } else {
12160 address += env->cp15.fcseidr_ns;
12161 }
54bf36ed 12162 }
9ee6e8bb 12163
3279adb9 12164 if (arm_feature(env, ARM_FEATURE_PMSA)) {
c9f9f124 12165 bool ret;
f6bda88f 12166 *page_size = TARGET_PAGE_SIZE;
3279adb9 12167
504e3cc3
PM		 12168 if (arm_feature(env, ARM_FEATURE_V8)) {
12169 /* PMSAv8 */
12170 ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
72042435 12171 phys_ptr, attrs, prot, page_size, fi);
504e3cc3 12172 } else if (arm_feature(env, ARM_FEATURE_V7)) {
3279adb9
PM		 12173 /* PMSAv7 */
12174 ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
e5e40999 12175 phys_ptr, prot, page_size, fi);
3279adb9
PM		 12176 } else {
12177 /* Pre-v7 MPU */
12178 ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
53a4e5c5 12179 phys_ptr, prot, fi);
3279adb9
PM		 12180 }
12181 qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
c9f9f124 12182 " mmu_idx %u -> %s (prot %c%c%c)\n",
709e4407
PM		 12183 access_type == MMU_DATA_LOAD ? "reading" :
12184 (access_type == MMU_DATA_STORE ? "writing" : "execute"),
c9f9f124
MD		 12185 (uint32_t)address, mmu_idx,
12186 ret ? "Miss" : "Hit",
12187 *prot & PAGE_READ ? 'r' : '-',
12188 *prot & PAGE_WRITE ? 'w' : '-',
12189 *prot & PAGE_EXEC ? 'x' : '-');
12190
12191 return ret;
f6bda88f
PC		 12192 }
12193
3279adb9
PM		 12194 /* Definitely a real MMU, not an MPU */
12195
0480f69a 12196 if (regime_translation_disabled(env, mmu_idx)) {
337a03f0
RH		 12197 uint64_t hcr;
12198 uint8_t memattr;
12199
cebfb648
RH		 12200 /*
12201 * MMU disabled. S1 addresses within aa64 translation regimes are
12202 * still checked for bounds -- see AArch64.TranslateAddressS1Off.
12203 */
12204 if (mmu_idx != ARMMMUIdx_Stage2) {
12205 int r_el = regime_el(env, mmu_idx);
12206 if (arm_el_is_aa64(env, r_el)) {
12207 int pamax = arm_pamax(env_archcpu(env));
12208 uint64_t tcr = env->cp15.tcr_el[r_el].raw_tcr;
12209 int addrtop, tbi;
12210
12211 tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
12212 if (access_type == MMU_INST_FETCH) {
12213 tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
12214 }
12215 tbi = (tbi >> extract64(address, 55, 1)) & 1;
12216 addrtop = (tbi ? 55 : 63);
12217
12218 if (extract64(address, pamax, addrtop - pamax + 1) != 0) {
12219 fi->type = ARMFault_AddressSize;
12220 fi->level = 0;
12221 fi->stage2 = false;
12222 return 1;
12223 }
12224
12225 /*
12226 * When TBI is disabled, we've just validated that all of the
12227 * bits above PAMax are zero, so logically we only need to
12228 * clear the top byte for TBI. But it's clearer to follow
12229 * the pseudocode set of addrdesc.paddress.
12230 */
12231 address = extract64(address, 0, 52);
12232 }
12233 }
9ee6e8bb 12234 *phys_ptr = address;
3ad493fc 12235 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 12236 *page_size = TARGET_PAGE_SIZE;
337a03f0
RH		 12237
12238 /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
12239 hcr = arm_hcr_el2_eff(env);
12240 cacheattrs->shareability = 0;
12241 if (hcr & HCR_DC) {
12242 if (hcr & HCR_DCT) {
12243 memattr = 0xf0; /* Tagged, Normal, WB, RWA */
12244 } else {
12245 memattr = 0xff; /* Normal, WB, RWA */
12246 }
12247 } else if (access_type == MMU_INST_FETCH) {
12248 if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
12249 memattr = 0xee; /* Normal, WT, RA, NT */
12250 } else {
12251 memattr = 0x44; /* Normal, NC, No */
12252 }
12253 cacheattrs->shareability = 2; /* outer sharable */
12254 } else {
12255 memattr = 0x00; /* Device, nGnRnE */
12256 }
12257 cacheattrs->attrs = memattr;
9ee6e8bb 12258 return 0;
0480f69a
PM		 12259 }
12260
0480f69a 12261 if (regime_using_lpae_format(env, mmu_idx)) {
ff7de2fc 12262 return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
bc52bfeb
PM		 12263 phys_ptr, attrs, prot, page_size,
12264 fi, cacheattrs);
0480f69a 12265 } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
bc52bfeb
PM		 12266 return get_phys_addr_v6(env, address, access_type, mmu_idx,
12267 phys_ptr, attrs, prot, page_size, fi);
9ee6e8bb 12268 } else {
bc52bfeb 12269 return get_phys_addr_v5(env, address, access_type, mmu_idx,
f989983e 12270 phys_ptr, prot, page_size, fi);
9ee6e8bb
PB		 12271 }
12272}
12273
0faea0c7
PM		 12274hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
12275 MemTxAttrs *attrs)
b5ff1b31 12276{
00b941e5 12277 ARMCPU *cpu = ARM_CPU(cs);
d3649702 12278 CPUARMState *env = &cpu->env;
a8170e5e 12279 hwaddr phys_addr;
d4c430a8 12280 target_ulong page_size;
b5ff1b31 12281 int prot;
b7cc4e82 12282 bool ret;
e14b5a23 12283 ARMMMUFaultInfo fi = {};
50494a27 12284 ARMMMUIdx mmu_idx = arm_mmu_idx(env);
7e98e21c 12285 ARMCacheAttrs cacheattrs = {};
b5ff1b31 12286
0faea0c7
PM		 12287 *attrs = (MemTxAttrs) {};
12288
8bd5c820 12289 ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr,
7e98e21c 12290 attrs, &prot, &page_size, &fi, &cacheattrs);
b5ff1b31 12291
b7cc4e82 12292 if (ret) {
b5ff1b31 12293 return -1;
00b941e5 12294 }
b5ff1b31
FB		 12295 return phys_addr;
12296}
12297
b5ff1b31 12298#endif
6ddbc6e4
PB		 12299
12300/* Note that signed overflow is undefined in C. The following routines are
12301 careful to use unsigned types where modulo arithmetic is required.
12302 Failure to do so _will_ break on newer gcc. */
12303
12304/* Signed saturating arithmetic. */
12305
1654b2d6 12306/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 12307static inline uint16_t add16_sat(uint16_t a, uint16_t b)
12308{
12309 uint16_t res;
12310
12311 res = a + b;
12312 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
12313 if (a & 0x8000)
12314 res = 0x8000;
12315 else
12316 res = 0x7fff;
12317 }
12318 return res;
12319}
12320
1654b2d6 12321/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 12322static inline uint8_t add8_sat(uint8_t a, uint8_t b)
12323{
12324 uint8_t res;
12325
12326 res = a + b;
12327 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
12328 if (a & 0x80)
12329 res = 0x80;
12330 else
12331 res = 0x7f;
12332 }
12333 return res;
12334}
12335
1654b2d6 12336/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 12337static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
12338{
12339 uint16_t res;
12340
12341 res = a - b;
12342 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
12343 if (a & 0x8000)
12344 res = 0x8000;
12345 else
12346 res = 0x7fff;
12347 }
12348 return res;
12349}
12350
1654b2d6 12351/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 12352static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
12353{
12354 uint8_t res;
12355
12356 res = a - b;
12357 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
12358 if (a & 0x80)
12359 res = 0x80;
12360 else
12361 res = 0x7f;
12362 }
12363 return res;
12364}
12365
12366#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
12367#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
12368#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
12369#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
12370#define PFX q
12371
12372#include "op_addsub.h"
12373
12374/* Unsigned saturating arithmetic. */
460a09c1 12375static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 12376{
12377 uint16_t res;
12378 res = a + b;
12379 if (res < a)
12380 res = 0xffff;
12381 return res;
12382}
12383
460a09c1 12384static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 12385{
4c4fd3f8 12386 if (a > b)
6ddbc6e4
PB		 12387 return a - b;
12388 else
12389 return 0;
12390}
12391
12392static inline uint8_t add8_usat(uint8_t a, uint8_t b)
12393{
12394 uint8_t res;
12395 res = a + b;
12396 if (res < a)
12397 res = 0xff;
12398 return res;
12399}
12400
12401static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
12402{
4c4fd3f8 12403 if (a > b)
6ddbc6e4
PB		 12404 return a - b;
12405 else
12406 return 0;
12407}
12408
12409#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
12410#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
12411#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
12412#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
12413#define PFX uq
12414
12415#include "op_addsub.h"
12416
12417/* Signed modulo arithmetic. */
12418#define SARITH16(a, b, n, op) do { \
12419 int32_t sum; \
db6e2e65 12420 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 12421 RESULT(sum, n, 16); \
12422 if (sum >= 0) \
12423 ge |= 3 << (n * 2); \
12424 } while(0)
12425
12426#define SARITH8(a, b, n, op) do { \
12427 int32_t sum; \
db6e2e65 12428 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 12429 RESULT(sum, n, 8); \
12430 if (sum >= 0) \
12431 ge |= 1 << n; \
12432 } while(0)
12433
12434
12435#define ADD16(a, b, n) SARITH16(a, b, n, +)
12436#define SUB16(a, b, n) SARITH16(a, b, n, -)
12437#define ADD8(a, b, n) SARITH8(a, b, n, +)
12438#define SUB8(a, b, n) SARITH8(a, b, n, -)
12439#define PFX s
12440#define ARITH_GE
12441
12442#include "op_addsub.h"
12443
12444/* Unsigned modulo arithmetic. */
12445#define ADD16(a, b, n) do { \
12446 uint32_t sum; \
12447 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
12448 RESULT(sum, n, 16); \
a87aa10b 12449 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 12450 ge |= 3 << (n * 2); \
12451 } while(0)
12452
12453#define ADD8(a, b, n) do { \
12454 uint32_t sum; \
12455 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
12456 RESULT(sum, n, 8); \
a87aa10b
AZ		 12457 if ((sum >> 8) == 1) \
12458 ge |= 1 << n; \
6ddbc6e4
PB		 12459 } while(0)
12460
12461#define SUB16(a, b, n) do { \
12462 uint32_t sum; \
12463 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
12464 RESULT(sum, n, 16); \
12465 if ((sum >> 16) == 0) \
12466 ge |= 3 << (n * 2); \
12467 } while(0)
12468
12469#define SUB8(a, b, n) do { \
12470 uint32_t sum; \
12471 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
12472 RESULT(sum, n, 8); \
12473 if ((sum >> 8) == 0) \
a87aa10b 12474 ge |= 1 << n; \
6ddbc6e4
PB		 12475 } while(0)
12476
12477#define PFX u
12478#define ARITH_GE
12479
12480#include "op_addsub.h"
12481
12482/* Halved signed arithmetic. */
12483#define ADD16(a, b, n) \
12484 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
12485#define SUB16(a, b, n) \
12486 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
12487#define ADD8(a, b, n) \
12488 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
12489#define SUB8(a, b, n) \
12490 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
12491#define PFX sh
12492
12493#include "op_addsub.h"
12494
12495/* Halved unsigned arithmetic. */
12496#define ADD16(a, b, n) \
12497 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
12498#define SUB16(a, b, n) \
12499 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
12500#define ADD8(a, b, n) \
12501 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
12502#define SUB8(a, b, n) \
12503 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
12504#define PFX uh
12505
12506#include "op_addsub.h"
12507
12508static inline uint8_t do_usad(uint8_t a, uint8_t b)
12509{
12510 if (a > b)
12511 return a - b;
12512 else
12513 return b - a;
12514}
12515
12516/* Unsigned sum of absolute byte differences. */
12517uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
12518{
12519 uint32_t sum;
12520 sum = do_usad(a, b);
12521 sum += do_usad(a >> 8, b >> 8);
bdc3b6f5 12522 sum += do_usad(a >> 16, b >> 16);
6ddbc6e4
PB		 12523 sum += do_usad(a >> 24, b >> 24);
12524 return sum;
12525}
12526
12527/* For ARMv6 SEL instruction. */
12528uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
12529{
12530 uint32_t mask;
12531
12532 mask = 0;
12533 if (flags & 1)
12534 mask |= 0xff;
12535 if (flags & 2)
12536 mask |= 0xff00;
12537 if (flags & 4)
12538 mask |= 0xff0000;
12539 if (flags & 8)
12540 mask |= 0xff000000;
12541 return (a & mask) | (b & ~mask);
12542}
12543
aa633469
PM		 12544/* CRC helpers.
12545 * The upper bytes of val (above the number specified by 'bytes') must have
12546 * been zeroed out by the caller.
12547 */
eb0ecd5a
WN		 12548uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
12549{
12550 uint8_t buf[4];
12551
aa633469 12552 stl_le_p(buf, val);
eb0ecd5a
WN		 12553
12554 /* zlib crc32 converts the accumulator and output to one's complement. */
12555 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
12556}
12557
12558uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
12559{
12560 uint8_t buf[4];
12561
aa633469 12562 stl_le_p(buf, val);
eb0ecd5a
WN		 12563
12564 /* Linux crc32c converts the output to one's complement. */
12565 return crc32c(acc, buf, bytes) ^ 0xffffffff;
12566}
a9e01311
RH		 12567
12568/* Return the exception level to which FP-disabled exceptions should
12569 * be taken, or 0 if FP is enabled.
12570 */
ced31551 12571int fp_exception_el(CPUARMState *env, int cur_el)
a9e01311 12572{
55faa212 12573#ifndef CONFIG_USER_ONLY
a9e01311
RH		 12574 /* CPACR and the CPTR registers don't exist before v6, so FP is
12575 * always accessible
12576 */
12577 if (!arm_feature(env, ARM_FEATURE_V6)) {
12578 return 0;
12579 }
12580
d87513c0
PM		 12581 if (arm_feature(env, ARM_FEATURE_M)) {
12582 /* CPACR can cause a NOCP UsageFault taken to current security state */
12583 if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) {
12584 return 1;
12585 }
12586
12587 if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) {
12588 if (!extract32(env->v7m.nsacr, 10, 1)) {
12589 /* FP insns cause a NOCP UsageFault taken to Secure */
12590 return 3;
12591 }
12592 }
12593
12594 return 0;
12595 }
12596
a9e01311
RH		 12597 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
12598 * 0, 2 : trap EL0 and EL1/PL1 accesses
12599 * 1 : trap only EL0 accesses
12600 * 3 : trap no accesses
c2ddb7cf 12601 * This register is ignored if E2H+TGE are both set.
a9e01311 12602 */
c2ddb7cf
RH		 12603 if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
12604 int fpen = extract32(env->cp15.cpacr_el1, 20, 2);
12605
12606 switch (fpen) {
12607 case 0:
12608 case 2:
12609 if (cur_el == 0 || cur_el == 1) {
12610 /* Trap to PL1, which might be EL1 or EL3 */
12611 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
12612 return 3;
12613 }
12614 return 1;
12615 }
12616 if (cur_el == 3 && !is_a64(env)) {
12617 /* Secure PL1 running at EL3 */
a9e01311
RH		 12618 return 3;
12619 }
c2ddb7cf
RH		 12620 break;
12621 case 1:
12622 if (cur_el == 0) {
12623 return 1;
12624 }
12625 break;
12626 case 3:
12627 break;
a9e01311 12628 }
a9e01311
RH		 12629 }
12630
fc1120a7
PM		 12631 /*
12632 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
12633 * to control non-secure access to the FPU. It doesn't have any
12634 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
12635 */
12636 if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) &&
12637 cur_el <= 2 && !arm_is_secure_below_el3(env))) {
12638 if (!extract32(env->cp15.nsacr, 10, 1)) {
12639 /* FP insns act as UNDEF */
12640 return cur_el == 2 ? 2 : 1;
12641 }
12642 }
12643
a9e01311
RH		 12644 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
12645 * check because zero bits in the registers mean "don't trap".
12646 */
12647
12648 /* CPTR_EL2 : present in v7VE or v8 */
12649 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1)
12650 && !arm_is_secure_below_el3(env)) {
12651 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
12652 return 2;
12653 }
12654
12655 /* CPTR_EL3 : present in v8 */
12656 if (extract32(env->cp15.cptr_el[3], 10, 1)) {
12657 /* Trap all FP ops to EL3 */
12658 return 3;
12659 }
55faa212 12660#endif
a9e01311
RH		 12661 return 0;
12662}
12663
b9f6033c
RH		 12664/* Return the exception level we're running at if this is our mmu_idx */
12665int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
12666{
12667 if (mmu_idx & ARM_MMU_IDX_M) {
12668 return mmu_idx & ARM_MMU_IDX_M_PRIV;
12669 }
12670
12671 switch (mmu_idx) {
12672 case ARMMMUIdx_E10_0:
12673 case ARMMMUIdx_E20_0:
12674 case ARMMMUIdx_SE10_0:
12675 return 0;
12676 case ARMMMUIdx_E10_1:
452ef8cb 12677 case ARMMMUIdx_E10_1_PAN:
b9f6033c 12678 case ARMMMUIdx_SE10_1:
452ef8cb 12679 case ARMMMUIdx_SE10_1_PAN:
b9f6033c
RH		 12680 return 1;
12681 case ARMMMUIdx_E2:
12682 case ARMMMUIdx_E20_2:
452ef8cb 12683 case ARMMMUIdx_E20_2_PAN:
b9f6033c
RH		 12684 return 2;
12685 case ARMMMUIdx_SE3:
12686 return 3;
12687 default:
12688 g_assert_not_reached();
12689 }
12690}
12691
7aab5a8c 12692#ifndef CONFIG_TCG
65e4655c
RH		 12693ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
12694{
7aab5a8c 12695 g_assert_not_reached();
65e4655c 12696}
7aab5a8c 12697#endif
65e4655c 12698
164690b2 12699ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
65e4655c 12700{
65e4655c 12701 if (arm_feature(env, ARM_FEATURE_M)) {
50494a27 12702 return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
65e4655c
RH		 12703 }
12704
6003d980 12705 /* See ARM pseudo-function ELIsInHost. */
b9f6033c
RH		 12706 switch (el) {
12707 case 0:
b9f6033c
RH		 12708 if (arm_is_secure_below_el3(env)) {
12709 return ARMMMUIdx_SE10_0;
12710 }
6003d980
RH		 12711 if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)
12712 && arm_el_is_aa64(env, 2)) {
12713 return ARMMMUIdx_E20_0;
12714 }
b9f6033c
RH		 12715 return ARMMMUIdx_E10_0;
12716 case 1:
12717 if (arm_is_secure_below_el3(env)) {
66412260
RH		 12718 if (env->pstate & PSTATE_PAN) {
12719 return ARMMMUIdx_SE10_1_PAN;
12720 }
b9f6033c
RH		 12721 return ARMMMUIdx_SE10_1;
12722 }
66412260
RH		 12723 if (env->pstate & PSTATE_PAN) {
12724 return ARMMMUIdx_E10_1_PAN;
12725 }
b9f6033c
RH		 12726 return ARMMMUIdx_E10_1;
12727 case 2:
b9f6033c 12728 /* TODO: ARMv8.4-SecEL2 */
6003d980
RH		 12729 /* Note that TGE does not apply at EL2. */
12730 if ((env->cp15.hcr_el2 & HCR_E2H) && arm_el_is_aa64(env, 2)) {
66412260
RH		 12731 if (env->pstate & PSTATE_PAN) {
12732 return ARMMMUIdx_E20_2_PAN;
12733 }
6003d980
RH		 12734 return ARMMMUIdx_E20_2;
12735 }
b9f6033c
RH		 12736 return ARMMMUIdx_E2;
12737 case 3:
12738 return ARMMMUIdx_SE3;
12739 default:
12740 g_assert_not_reached();
65e4655c 12741 }
50494a27
RH		 12742}
12743
164690b2
RH		 12744ARMMMUIdx arm_mmu_idx(CPUARMState *env)
12745{
12746 return arm_mmu_idx_el(env, arm_current_el(env));
12747}
12748
64be86ab
RH		 12749#ifndef CONFIG_USER_ONLY
12750ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
12751{
12752 return stage_1_mmu_idx(arm_mmu_idx(env));
12753}
12754#endif
12755
fdd1b228
RH		 12756static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el,
12757 ARMMMUIdx mmu_idx, uint32_t flags)
12758{
12759 flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el);
12760 flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX,
12761 arm_to_core_mmu_idx(mmu_idx));
12762
fdd1b228
RH		 12763 if (arm_singlestep_active(env)) {
12764 flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1);
12765 }
12766 return flags;
12767}
12768
43eccfb6
RH		 12769static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el,
12770 ARMMMUIdx mmu_idx, uint32_t flags)
12771{
8061a649
RH		 12772 bool sctlr_b = arm_sctlr_b(env);
12773
12774 if (sctlr_b) {
12775 flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, 1);
12776 }
12777 if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) {
12778 flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1);
12779 }
43eccfb6
RH		 12780 flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env));
12781
12782 return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
12783}
12784
6e33ced5
RH		 12785static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el,
12786 ARMMMUIdx mmu_idx)
12787{
12788 uint32_t flags = 0;
12789
12790 if (arm_v7m_is_handler_mode(env)) {
79cabf1f 12791 flags = FIELD_DP32(flags, TBFLAG_M32, HANDLER, 1);
6e33ced5
RH		 12792 }
12793
12794 /*
12795 * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
12796 * is suppressing them because the requested execution priority
12797 * is less than 0.
12798 */
12799 if (arm_feature(env, ARM_FEATURE_V8) &&
12800 !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
12801 (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
79cabf1f 12802 flags = FIELD_DP32(flags, TBFLAG_M32, STACKCHECK, 1);
6e33ced5
RH		 12803 }
12804
12805 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
12806}
12807
83f4baef
RH		 12808static uint32_t rebuild_hflags_aprofile(CPUARMState *env)
12809{
12810 int flags = 0;
12811
12812 flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL,
12813 arm_debug_target_el(env));
12814 return flags;
12815}
12816
c747224c
RH		 12817static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el,
12818 ARMMMUIdx mmu_idx)
12819{
83f4baef 12820 uint32_t flags = rebuild_hflags_aprofile(env);
0a54d68e
RH		 12821
12822 if (arm_el_is_aa64(env, 1)) {
12823 flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
12824 }
5bb0a20b
MZ		 12825
12826 if (arm_current_el(env) < 2 && env->cp15.hstr_el2 &&
12827 (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
12828 flags = FIELD_DP32(flags, TBFLAG_A32, HSTR_ACTIVE, 1);
12829 }
12830
83f4baef 12831 return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
c747224c
RH		 12832}
12833
d4d7503a
RH		 12834static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
12835 ARMMMUIdx mmu_idx)
a9e01311 12836{
83f4baef 12837 uint32_t flags = rebuild_hflags_aprofile(env);
d4d7503a 12838 ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
b830a5ee 12839 uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
d4d7503a
RH		 12840 uint64_t sctlr;
12841 int tbii, tbid;
b9adaa70 12842
d4d7503a 12843 flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
cd208a1c 12844
339370b9 12845 /* Get control bits for tagged addresses. */
b830a5ee
RH		 12846 tbid = aa64_va_parameter_tbi(tcr, mmu_idx);
12847 tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx);
5d8634f5 12848
d4d7503a
RH		 12849 flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii);
12850 flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid);
12851
12852 if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
12853 int sve_el = sve_exception_el(env, el);
12854 uint32_t zcr_len;
5d8634f5 12855
d4d7503a
RH		 12856 /*
12857 * If SVE is disabled, but FP is enabled,
12858 * then the effective len is 0.
12859 */
12860 if (sve_el != 0 && fp_el == 0) {
12861 zcr_len = 0;
12862 } else {
12863 zcr_len = sve_zcr_len_for_el(env, el);
5d8634f5 12864 }
d4d7503a
RH		 12865 flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el);
12866 flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
12867 }
1db5e96c 12868
aaec1432 12869 sctlr = regime_sctlr(env, stage1);
1db5e96c 12870
8061a649
RH		 12871 if (arm_cpu_data_is_big_endian_a64(el, sctlr)) {
12872 flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1);
12873 }
12874
d4d7503a
RH		 12875 if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) {
12876 /*
12877 * In order to save space in flags, we record only whether
12878 * pauth is "inactive", meaning all insns are implemented as
12879 * a nop, or "active" when some action must be performed.
12880 * The decision of which action to take is left to a helper.
12881 */
12882 if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
12883 flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1);
1db5e96c 12884 }
d4d7503a 12885 }
0816ef1b 12886
d4d7503a
RH		 12887 if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
12888 /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
12889 if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
12890 flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1);
0816ef1b 12891 }
d4d7503a 12892 }
08f1434a 12893
cc28fc30 12894 /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
7a8014ab
RH		 12895 if (!(env->pstate & PSTATE_UAO)) {
12896 switch (mmu_idx) {
12897 case ARMMMUIdx_E10_1:
12898 case ARMMMUIdx_E10_1_PAN:
12899 case ARMMMUIdx_SE10_1:
12900 case ARMMMUIdx_SE10_1_PAN:
12901 /* TODO: ARMv8.3-NV */
cc28fc30 12902 flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1);
7a8014ab
RH		 12903 break;
12904 case ARMMMUIdx_E20_2:
12905 case ARMMMUIdx_E20_2_PAN:
12906 /* TODO: ARMv8.4-SecEL2 */
12907 /*
12908 * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
12909 * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
12910 */
12911 if (env->cp15.hcr_el2 & HCR_TGE) {
12912 flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1);
12913 }
12914 break;
12915 default:
12916 break;
cc28fc30 12917 }
cc28fc30
RH		 12918 }
12919
81ae05fa
RH		 12920 if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
12921 /*
12922 * Set MTE_ACTIVE if any access may be Checked, and leave clear
12923 * if all accesses must be Unchecked:
12924 * 1) If no TBI, then there are no tags in the address to check,
12925 * 2) If Tag Check Override, then all accesses are Unchecked,
12926 * 3) If Tag Check Fail == 0, then Checked access have no effect,
12927 * 4) If no Allocation Tag Access, then all accesses are Unchecked.
12928 */
12929 if (allocation_tag_access_enabled(env, el, sctlr)) {
12930 flags = FIELD_DP32(flags, TBFLAG_A64, ATA, 1);
12931 if (tbid
12932 && !(env->pstate & PSTATE_TCO)
12933 && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) {
12934 flags = FIELD_DP32(flags, TBFLAG_A64, MTE_ACTIVE, 1);
12935 }
12936 }
12937 /* And again for unprivileged accesses, if required. */
12938 if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV)
12939 && tbid
12940 && !(env->pstate & PSTATE_TCO)
cc97b001 12941 && (sctlr & SCTLR_TCF)
81ae05fa
RH		 12942 && allocation_tag_access_enabled(env, 0, sctlr)) {
12943 flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1);
12944 }
12945 /* Cache TCMA as well as TBI. */
12946 flags = FIELD_DP32(flags, TBFLAG_A64, TCMA,
12947 aa64_va_parameter_tcma(tcr, mmu_idx));
12948 }
12949
d4d7503a
RH		 12950 return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
12951}
12952
3d74e2e9
RH		 12953static uint32_t rebuild_hflags_internal(CPUARMState *env)
12954{
12955 int el = arm_current_el(env);
12956 int fp_el = fp_exception_el(env, el);
164690b2 12957 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
3d74e2e9
RH		 12958
12959 if (is_a64(env)) {
12960 return rebuild_hflags_a64(env, el, fp_el, mmu_idx);
12961 } else if (arm_feature(env, ARM_FEATURE_M)) {
12962 return rebuild_hflags_m32(env, fp_el, mmu_idx);
12963 } else {
12964 return rebuild_hflags_a32(env, fp_el, mmu_idx);
12965 }
12966}
12967
12968void arm_rebuild_hflags(CPUARMState *env)
12969{
12970 env->hflags = rebuild_hflags_internal(env);
12971}
12972
19717e9b
PM		 12973/*
12974 * If we have triggered a EL state change we can't rely on the
12975 * translator having passed it to us, we need to recompute.
12976 */
12977void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env)
12978{
12979 int el = arm_current_el(env);
12980 int fp_el = fp_exception_el(env, el);
12981 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
12982 env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
12983}
12984
14f3c588
RH		 12985void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
12986{
12987 int fp_el = fp_exception_el(env, el);
12988 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
12989
12990 env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
12991}
12992
f80741d1
AB		 12993/*
12994 * If we have triggered a EL state change we can't rely on the
563152e0 12995 * translator having passed it to us, we need to recompute.
f80741d1
AB		 12996 */
12997void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env)
12998{
12999 int el = arm_current_el(env);
13000 int fp_el = fp_exception_el(env, el);
13001 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
13002 env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
13003}
13004
14f3c588
RH		 13005void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el)
13006{
13007 int fp_el = fp_exception_el(env, el);
13008 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
13009
13010 env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
13011}
13012
13013void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el)
13014{
13015 int fp_el = fp_exception_el(env, el);
13016 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
13017
13018 env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx);
13019}
13020
0ee8b24a
PMD		 13021static inline void assert_hflags_rebuild_correctly(CPUARMState *env)
13022{
13023#ifdef CONFIG_DEBUG_TCG
13024 uint32_t env_flags_current = env->hflags;
13025 uint32_t env_flags_rebuilt = rebuild_hflags_internal(env);
13026
13027 if (unlikely(env_flags_current != env_flags_rebuilt)) {
13028 fprintf(stderr, "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n",
13029 env_flags_current, env_flags_rebuilt);
13030 abort();
13031 }
13032#endif
13033}
13034
d4d7503a
RH		 13035void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
13036 target_ulong *cs_base, uint32_t *pflags)
13037{
e979972a
RH		 13038 uint32_t flags = env->hflags;
13039 uint32_t pstate_for_ss;
d4d7503a 13040
9b253fe5 13041 *cs_base = 0;
0ee8b24a 13042 assert_hflags_rebuild_correctly(env);
3d74e2e9 13043
e979972a 13044 if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) {
d4d7503a 13045 *pc = env->pc;
d4d7503a 13046 if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
08f1434a
RH		 13047 flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);
13048 }
60e12c37 13049 pstate_for_ss = env->pstate;
a9e01311
RH		 13050 } else {
13051 *pc = env->regs[15];
6e33ced5
RH		 13052
13053 if (arm_feature(env, ARM_FEATURE_M)) {
9550d1bd
RH		 13054 if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
13055 FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S)
13056 != env->v7m.secure) {
79cabf1f 13057 flags = FIELD_DP32(flags, TBFLAG_M32, FPCCR_S_WRONG, 1);
9550d1bd
RH		 13058 }
13059
13060 if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) &&
13061 (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) ||
13062 (env->v7m.secure &&
13063 !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) {
13064 /*
13065 * ASPEN is set, but FPCA/SFPA indicate that there is no
13066 * active FP context; we must create a new FP context before
13067 * executing any FP insn.
13068 */
79cabf1f 13069 flags = FIELD_DP32(flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED, 1);
9550d1bd
RH		 13070 }
13071
13072 bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK;
13073 if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) {
79cabf1f 13074 flags = FIELD_DP32(flags, TBFLAG_M32, LSPACT, 1);
9550d1bd 13075 }
6e33ced5 13076 } else {
bbad7c62
RH		 13077 /*
13078 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
13079 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
13080 */
13081 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
13082 flags = FIELD_DP32(flags, TBFLAG_A32,
13083 XSCALE_CPAR, env->cp15.c15_cpar);
13084 } else {
13085 flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN,
13086 env->vfp.vec_len);
13087 flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE,
13088 env->vfp.vec_stride);
13089 }
0a54d68e
RH		 13090 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
13091 flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
13092 }
6e33ced5
RH		 13093 }
13094
79cabf1f
RH		 13095 flags = FIELD_DP32(flags, TBFLAG_AM32, THUMB, env->thumb);
13096 flags = FIELD_DP32(flags, TBFLAG_AM32, CONDEXEC, env->condexec_bits);
60e12c37 13097 pstate_for_ss = env->uncached_cpsr;
d4d7503a 13098 }
a9e01311 13099
60e12c37
RH		 13100 /*
13101 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
a9e01311
RH		 13102 * states defined in the ARM ARM for software singlestep:
13103 * SS_ACTIVE PSTATE.SS State
13104 * 0 x Inactive (the TB flag for SS is always 0)
13105 * 1 0 Active-pending
13106 * 1 1 Active-not-pending
fdd1b228 13107 * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB.
a9e01311 13108 */
60e12c37
RH		 13109 if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) &&
13110 (pstate_for_ss & PSTATE_SS)) {
13111 flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1);
a9e01311 13112 }
a9e01311 13113
b9adaa70 13114 *pflags = flags;
a9e01311 13115}
0ab5953b
RH		 13116
13117#ifdef TARGET_AARCH64
13118/*
13119 * The manual says that when SVE is enabled and VQ is widened the
13120 * implementation is allowed to zero the previously inaccessible
13121 * portion of the registers. The corollary to that is that when
13122 * SVE is enabled and VQ is narrowed we are also allowed to zero
13123 * the now inaccessible portion of the registers.
13124 *
13125 * The intent of this is that no predicate bit beyond VQ is ever set.
13126 * Which means that some operations on predicate registers themselves
13127 * may operate on full uint64_t or even unrolled across the maximum
13128 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
13129 * may well be cheaper than conditionals to restrict the operation
13130 * to the relevant portion of a uint16_t[16].
13131 */
13132void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
13133{
13134 int i, j;
13135 uint64_t pmask;
13136
13137 assert(vq >= 1 && vq <= ARM_MAX_VQ);
2fc0cc0e 13138 assert(vq <= env_archcpu(env)->sve_max_vq);
0ab5953b
RH		 13139
13140 /* Zap the high bits of the zregs. */
13141 for (i = 0; i < 32; i++) {
13142 memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq));
13143 }
13144
13145 /* Zap the high bits of the pregs and ffr. */
13146 pmask = 0;
13147 if (vq & 3) {
13148 pmask = ~(-1ULL << (16 * (vq & 3)));
13149 }
13150 for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) {
13151 for (i = 0; i < 17; ++i) {
13152 env->vfp.pregs[i].p[j] &= pmask;
13153 }
13154 pmask = 0;
13155 }
13156}
13157
13158/*
13159 * Notice a change in SVE vector size when changing EL.
13160 */
9a05f7b6
RH		 13161void aarch64_sve_change_el(CPUARMState *env, int old_el,
13162 int new_el, bool el0_a64)
0ab5953b 13163{
2fc0cc0e 13164 ARMCPU *cpu = env_archcpu(env);
0ab5953b 13165 int old_len, new_len;
9a05f7b6 13166 bool old_a64, new_a64;
0ab5953b
RH		 13167
13168 /* Nothing to do if no SVE. */
cd208a1c 13169 if (!cpu_isar_feature(aa64_sve, cpu)) {
0ab5953b
RH		 13170 return;
13171 }
13172
13173 /* Nothing to do if FP is disabled in either EL. */
13174 if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) {
13175 return;
13176 }
13177
13178 /*
13179 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
13180 * at ELx, or not available because the EL is in AArch32 state, then
13181 * for all purposes other than a direct read, the ZCR_ELx.LEN field
13182 * has an effective value of 0".
13183 *
13184 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
13185 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
13186 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
13187 * we already have the correct register contents when encountering the
13188 * vq0->vq0 transition between EL0->EL1.
13189 */
9a05f7b6
RH		 13190 old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64;
13191 old_len = (old_a64 && !sve_exception_el(env, old_el)
0ab5953b 13192 ? sve_zcr_len_for_el(env, old_el) : 0);
9a05f7b6
RH		 13193 new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64;
13194 new_len = (new_a64 && !sve_exception_el(env, new_el)
0ab5953b
RH		 13195 ? sve_zcr_len_for_el(env, new_el) : 0);
13196
13197 /* When changing vector length, clear inaccessible state. */
13198 if (new_len < old_len) {
13199 aarch64_sve_narrow_vq(env, new_len + 1);
13200 }
13201}
13202#endif
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