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target/arm: Rename arm_cpu_mp_affinity
[mirror_qemu.git] / target / arm / hvf / hvf.c
CommitLineData
a1477da3
AG		 1/*
2 * QEMU Hypervisor.framework support for Apple Silicon
3
4 * Copyright 2020 Alexander Graf <agraf@csgraf.de>
219c101f 5 * Copyright 2020 Google LLC
a1477da3
AG		 6 *
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
9 *
10 */
11
12#include "qemu/osdep.h"
a1477da3
AG		 13#include "qemu/error-report.h"
14
15#include "sysemu/runstate.h"
16#include "sysemu/hvf.h"
17#include "sysemu/hvf_int.h"
18#include "sysemu/hw_accel.h"
585df85e 19#include "hvf_arm.h"
b5fb359c 20#include "cpregs.h"
a1477da3
AG		 21
22#include <mach/mach_time.h>
23
24#include "exec/address-spaces.h"
25#include "hw/irq.h"
26#include "qemu/main-loop.h"
27#include "sysemu/cpus.h"
2c9c0bf9 28#include "arm-powerctl.h"
a1477da3
AG		 29#include "target/arm/cpu.h"
30#include "target/arm/internals.h"
31#include "trace/trace-target_arm_hvf.h"
32#include "migration/vmstate.h"
33
f4152040
FC		 34#include "exec/gdbstub.h"
35
eb2edc42
FC		 36#define MDSCR_EL1_SS_SHIFT 0
37#define MDSCR_EL1_MDE_SHIFT 15
38
f49986ae 39static const uint16_t dbgbcr_regs[] = {
eb2edc42
FC		 40 HV_SYS_REG_DBGBCR0_EL1,
41 HV_SYS_REG_DBGBCR1_EL1,
42 HV_SYS_REG_DBGBCR2_EL1,
43 HV_SYS_REG_DBGBCR3_EL1,
44 HV_SYS_REG_DBGBCR4_EL1,
45 HV_SYS_REG_DBGBCR5_EL1,
46 HV_SYS_REG_DBGBCR6_EL1,
47 HV_SYS_REG_DBGBCR7_EL1,
48 HV_SYS_REG_DBGBCR8_EL1,
49 HV_SYS_REG_DBGBCR9_EL1,
50 HV_SYS_REG_DBGBCR10_EL1,
51 HV_SYS_REG_DBGBCR11_EL1,
52 HV_SYS_REG_DBGBCR12_EL1,
53 HV_SYS_REG_DBGBCR13_EL1,
54 HV_SYS_REG_DBGBCR14_EL1,
55 HV_SYS_REG_DBGBCR15_EL1,
56};
f49986ae
RH		 57
58static const uint16_t dbgbvr_regs[] = {
eb2edc42
FC		 59 HV_SYS_REG_DBGBVR0_EL1,
60 HV_SYS_REG_DBGBVR1_EL1,
61 HV_SYS_REG_DBGBVR2_EL1,
62 HV_SYS_REG_DBGBVR3_EL1,
63 HV_SYS_REG_DBGBVR4_EL1,
64 HV_SYS_REG_DBGBVR5_EL1,
65 HV_SYS_REG_DBGBVR6_EL1,
66 HV_SYS_REG_DBGBVR7_EL1,
67 HV_SYS_REG_DBGBVR8_EL1,
68 HV_SYS_REG_DBGBVR9_EL1,
69 HV_SYS_REG_DBGBVR10_EL1,
70 HV_SYS_REG_DBGBVR11_EL1,
71 HV_SYS_REG_DBGBVR12_EL1,
72 HV_SYS_REG_DBGBVR13_EL1,
73 HV_SYS_REG_DBGBVR14_EL1,
74 HV_SYS_REG_DBGBVR15_EL1,
75};
f49986ae
RH		 76
77static const uint16_t dbgwcr_regs[] = {
eb2edc42
FC		 78 HV_SYS_REG_DBGWCR0_EL1,
79 HV_SYS_REG_DBGWCR1_EL1,
80 HV_SYS_REG_DBGWCR2_EL1,
81 HV_SYS_REG_DBGWCR3_EL1,
82 HV_SYS_REG_DBGWCR4_EL1,
83 HV_SYS_REG_DBGWCR5_EL1,
84 HV_SYS_REG_DBGWCR6_EL1,
85 HV_SYS_REG_DBGWCR7_EL1,
86 HV_SYS_REG_DBGWCR8_EL1,
87 HV_SYS_REG_DBGWCR9_EL1,
88 HV_SYS_REG_DBGWCR10_EL1,
89 HV_SYS_REG_DBGWCR11_EL1,
90 HV_SYS_REG_DBGWCR12_EL1,
91 HV_SYS_REG_DBGWCR13_EL1,
92 HV_SYS_REG_DBGWCR14_EL1,
93 HV_SYS_REG_DBGWCR15_EL1,
94};
f49986ae
RH		 95
96static const uint16_t dbgwvr_regs[] = {
eb2edc42
FC		 97 HV_SYS_REG_DBGWVR0_EL1,
98 HV_SYS_REG_DBGWVR1_EL1,
99 HV_SYS_REG_DBGWVR2_EL1,
100 HV_SYS_REG_DBGWVR3_EL1,
101 HV_SYS_REG_DBGWVR4_EL1,
102 HV_SYS_REG_DBGWVR5_EL1,
103 HV_SYS_REG_DBGWVR6_EL1,
104 HV_SYS_REG_DBGWVR7_EL1,
105 HV_SYS_REG_DBGWVR8_EL1,
106 HV_SYS_REG_DBGWVR9_EL1,
107 HV_SYS_REG_DBGWVR10_EL1,
108 HV_SYS_REG_DBGWVR11_EL1,
109 HV_SYS_REG_DBGWVR12_EL1,
110 HV_SYS_REG_DBGWVR13_EL1,
111 HV_SYS_REG_DBGWVR14_EL1,
112 HV_SYS_REG_DBGWVR15_EL1,
113};
114
115static inline int hvf_arm_num_brps(hv_vcpu_config_t config)
116{
117 uint64_t val;
118 hv_return_t ret;
119 ret = hv_vcpu_config_get_feature_reg(config, HV_FEATURE_REG_ID_AA64DFR0_EL1,
120 &val);
121 assert_hvf_ok(ret);
122 return FIELD_EX64(val, ID_AA64DFR0, BRPS) + 1;
123}
124
125static inline int hvf_arm_num_wrps(hv_vcpu_config_t config)
126{
127 uint64_t val;
128 hv_return_t ret;
129 ret = hv_vcpu_config_get_feature_reg(config, HV_FEATURE_REG_ID_AA64DFR0_EL1,
130 &val);
131 assert_hvf_ok(ret);
132 return FIELD_EX64(val, ID_AA64DFR0, WRPS) + 1;
133}
134
135void hvf_arm_init_debug(void)
136{
137 hv_vcpu_config_t config;
138 config = hv_vcpu_config_create();
139
140 max_hw_bps = hvf_arm_num_brps(config);
141 hw_breakpoints =
142 g_array_sized_new(true, true, sizeof(HWBreakpoint), max_hw_bps);
143
144 max_hw_wps = hvf_arm_num_wrps(config);
145 hw_watchpoints =
146 g_array_sized_new(true, true, sizeof(HWWatchpoint), max_hw_wps);
147}
148
a1477da3
AG		 149#define HVF_SYSREG(crn, crm, op0, op1, op2) \
150 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
151#define PL1_WRITE_MASK 0x4
152
ad99f64f
AG		 153#define SYSREG_OP0_SHIFT 20
154#define SYSREG_OP0_MASK 0x3
155#define SYSREG_OP0(sysreg) ((sysreg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK)
156#define SYSREG_OP1_SHIFT 14
157#define SYSREG_OP1_MASK 0x7
158#define SYSREG_OP1(sysreg) ((sysreg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK)
159#define SYSREG_CRN_SHIFT 10
160#define SYSREG_CRN_MASK 0xf
161#define SYSREG_CRN(sysreg) ((sysreg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK)
162#define SYSREG_CRM_SHIFT 1
163#define SYSREG_CRM_MASK 0xf
164#define SYSREG_CRM(sysreg) ((sysreg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK)
165#define SYSREG_OP2_SHIFT 17
166#define SYSREG_OP2_MASK 0x7
167#define SYSREG_OP2(sysreg) ((sysreg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK)
168
a1477da3 169#define SYSREG(op0, op1, crn, crm, op2) \
ad99f64f
AG		 170 ((op0 << SYSREG_OP0_SHIFT) | \
171 (op1 << SYSREG_OP1_SHIFT) | \
172 (crn << SYSREG_CRN_SHIFT) | \
173 (crm << SYSREG_CRM_SHIFT) | \
174 (op2 << SYSREG_OP2_SHIFT))
175#define SYSREG_MASK \
176 SYSREG(SYSREG_OP0_MASK, \
177 SYSREG_OP1_MASK, \
178 SYSREG_CRN_MASK, \
179 SYSREG_CRM_MASK, \
180 SYSREG_OP2_MASK)
a1477da3
AG		 181#define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4)
182#define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4)
183#define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4)
184#define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1)
dd43ac07
AG		 185#define SYSREG_PMCR_EL0 SYSREG(3, 3, 9, 12, 0)
186#define SYSREG_PMUSERENR_EL0 SYSREG(3, 3, 9, 14, 0)
187#define SYSREG_PMCNTENSET_EL0 SYSREG(3, 3, 9, 12, 1)
188#define SYSREG_PMCNTENCLR_EL0 SYSREG(3, 3, 9, 12, 2)
189#define SYSREG_PMINTENCLR_EL1 SYSREG(3, 0, 9, 14, 2)
190#define SYSREG_PMOVSCLR_EL0 SYSREG(3, 3, 9, 12, 3)
191#define SYSREG_PMSWINC_EL0 SYSREG(3, 3, 9, 12, 4)
192#define SYSREG_PMSELR_EL0 SYSREG(3, 3, 9, 12, 5)
193#define SYSREG_PMCEID0_EL0 SYSREG(3, 3, 9, 12, 6)
194#define SYSREG_PMCEID1_EL0 SYSREG(3, 3, 9, 12, 7)
195#define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0)
196#define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7)
a1477da3 197
a2260983
AG		 198#define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 12, 8, 4)
199#define SYSREG_ICC_AP0R1_EL1 SYSREG(3, 0, 12, 8, 5)
200#define SYSREG_ICC_AP0R2_EL1 SYSREG(3, 0, 12, 8, 6)
201#define SYSREG_ICC_AP0R3_EL1 SYSREG(3, 0, 12, 8, 7)
202#define SYSREG_ICC_AP1R0_EL1 SYSREG(3, 0, 12, 9, 0)
203#define SYSREG_ICC_AP1R1_EL1 SYSREG(3, 0, 12, 9, 1)
204#define SYSREG_ICC_AP1R2_EL1 SYSREG(3, 0, 12, 9, 2)
205#define SYSREG_ICC_AP1R3_EL1 SYSREG(3, 0, 12, 9, 3)
206#define SYSREG_ICC_ASGI1R_EL1 SYSREG(3, 0, 12, 11, 6)
207#define SYSREG_ICC_BPR0_EL1 SYSREG(3, 0, 12, 8, 3)
208#define SYSREG_ICC_BPR1_EL1 SYSREG(3, 0, 12, 12, 3)
209#define SYSREG_ICC_CTLR_EL1 SYSREG(3, 0, 12, 12, 4)
210#define SYSREG_ICC_DIR_EL1 SYSREG(3, 0, 12, 11, 1)
211#define SYSREG_ICC_EOIR0_EL1 SYSREG(3, 0, 12, 8, 1)
212#define SYSREG_ICC_EOIR1_EL1 SYSREG(3, 0, 12, 12, 1)
213#define SYSREG_ICC_HPPIR0_EL1 SYSREG(3, 0, 12, 8, 2)
214#define SYSREG_ICC_HPPIR1_EL1 SYSREG(3, 0, 12, 12, 2)
215#define SYSREG_ICC_IAR0_EL1 SYSREG(3, 0, 12, 8, 0)
216#define SYSREG_ICC_IAR1_EL1 SYSREG(3, 0, 12, 12, 0)
217#define SYSREG_ICC_IGRPEN0_EL1 SYSREG(3, 0, 12, 12, 6)
218#define SYSREG_ICC_IGRPEN1_EL1 SYSREG(3, 0, 12, 12, 7)
219#define SYSREG_ICC_PMR_EL1 SYSREG(3, 0, 4, 6, 0)
220#define SYSREG_ICC_RPR_EL1 SYSREG(3, 0, 12, 11, 3)
221#define SYSREG_ICC_SGI0R_EL1 SYSREG(3, 0, 12, 11, 7)
222#define SYSREG_ICC_SGI1R_EL1 SYSREG(3, 0, 12, 11, 5)
223#define SYSREG_ICC_SRE_EL1 SYSREG(3, 0, 12, 12, 5)
224
ce799a04
FC		 225#define SYSREG_MDSCR_EL1 SYSREG(2, 0, 0, 2, 2)
226#define SYSREG_DBGBVR0_EL1 SYSREG(2, 0, 0, 0, 4)
227#define SYSREG_DBGBCR0_EL1 SYSREG(2, 0, 0, 0, 5)
228#define SYSREG_DBGWVR0_EL1 SYSREG(2, 0, 0, 0, 6)
229#define SYSREG_DBGWCR0_EL1 SYSREG(2, 0, 0, 0, 7)
230#define SYSREG_DBGBVR1_EL1 SYSREG(2, 0, 0, 1, 4)
231#define SYSREG_DBGBCR1_EL1 SYSREG(2, 0, 0, 1, 5)
232#define SYSREG_DBGWVR1_EL1 SYSREG(2, 0, 0, 1, 6)
233#define SYSREG_DBGWCR1_EL1 SYSREG(2, 0, 0, 1, 7)
234#define SYSREG_DBGBVR2_EL1 SYSREG(2, 0, 0, 2, 4)
235#define SYSREG_DBGBCR2_EL1 SYSREG(2, 0, 0, 2, 5)
236#define SYSREG_DBGWVR2_EL1 SYSREG(2, 0, 0, 2, 6)
237#define SYSREG_DBGWCR2_EL1 SYSREG(2, 0, 0, 2, 7)
238#define SYSREG_DBGBVR3_EL1 SYSREG(2, 0, 0, 3, 4)
239#define SYSREG_DBGBCR3_EL1 SYSREG(2, 0, 0, 3, 5)
240#define SYSREG_DBGWVR3_EL1 SYSREG(2, 0, 0, 3, 6)
241#define SYSREG_DBGWCR3_EL1 SYSREG(2, 0, 0, 3, 7)
242#define SYSREG_DBGBVR4_EL1 SYSREG(2, 0, 0, 4, 4)
243#define SYSREG_DBGBCR4_EL1 SYSREG(2, 0, 0, 4, 5)
244#define SYSREG_DBGWVR4_EL1 SYSREG(2, 0, 0, 4, 6)
245#define SYSREG_DBGWCR4_EL1 SYSREG(2, 0, 0, 4, 7)
246#define SYSREG_DBGBVR5_EL1 SYSREG(2, 0, 0, 5, 4)
247#define SYSREG_DBGBCR5_EL1 SYSREG(2, 0, 0, 5, 5)
248#define SYSREG_DBGWVR5_EL1 SYSREG(2, 0, 0, 5, 6)
249#define SYSREG_DBGWCR5_EL1 SYSREG(2, 0, 0, 5, 7)
250#define SYSREG_DBGBVR6_EL1 SYSREG(2, 0, 0, 6, 4)
251#define SYSREG_DBGBCR6_EL1 SYSREG(2, 0, 0, 6, 5)
252#define SYSREG_DBGWVR6_EL1 SYSREG(2, 0, 0, 6, 6)
253#define SYSREG_DBGWCR6_EL1 SYSREG(2, 0, 0, 6, 7)
254#define SYSREG_DBGBVR7_EL1 SYSREG(2, 0, 0, 7, 4)
255#define SYSREG_DBGBCR7_EL1 SYSREG(2, 0, 0, 7, 5)
256#define SYSREG_DBGWVR7_EL1 SYSREG(2, 0, 0, 7, 6)
257#define SYSREG_DBGWCR7_EL1 SYSREG(2, 0, 0, 7, 7)
258#define SYSREG_DBGBVR8_EL1 SYSREG(2, 0, 0, 8, 4)
259#define SYSREG_DBGBCR8_EL1 SYSREG(2, 0, 0, 8, 5)
260#define SYSREG_DBGWVR8_EL1 SYSREG(2, 0, 0, 8, 6)
261#define SYSREG_DBGWCR8_EL1 SYSREG(2, 0, 0, 8, 7)
262#define SYSREG_DBGBVR9_EL1 SYSREG(2, 0, 0, 9, 4)
263#define SYSREG_DBGBCR9_EL1 SYSREG(2, 0, 0, 9, 5)
264#define SYSREG_DBGWVR9_EL1 SYSREG(2, 0, 0, 9, 6)
265#define SYSREG_DBGWCR9_EL1 SYSREG(2, 0, 0, 9, 7)
266#define SYSREG_DBGBVR10_EL1 SYSREG(2, 0, 0, 10, 4)
267#define SYSREG_DBGBCR10_EL1 SYSREG(2, 0, 0, 10, 5)
268#define SYSREG_DBGWVR10_EL1 SYSREG(2, 0, 0, 10, 6)
269#define SYSREG_DBGWCR10_EL1 SYSREG(2, 0, 0, 10, 7)
270#define SYSREG_DBGBVR11_EL1 SYSREG(2, 0, 0, 11, 4)
271#define SYSREG_DBGBCR11_EL1 SYSREG(2, 0, 0, 11, 5)
272#define SYSREG_DBGWVR11_EL1 SYSREG(2, 0, 0, 11, 6)
273#define SYSREG_DBGWCR11_EL1 SYSREG(2, 0, 0, 11, 7)
274#define SYSREG_DBGBVR12_EL1 SYSREG(2, 0, 0, 12, 4)
275#define SYSREG_DBGBCR12_EL1 SYSREG(2, 0, 0, 12, 5)
276#define SYSREG_DBGWVR12_EL1 SYSREG(2, 0, 0, 12, 6)
277#define SYSREG_DBGWCR12_EL1 SYSREG(2, 0, 0, 12, 7)
278#define SYSREG_DBGBVR13_EL1 SYSREG(2, 0, 0, 13, 4)
279#define SYSREG_DBGBCR13_EL1 SYSREG(2, 0, 0, 13, 5)
280#define SYSREG_DBGWVR13_EL1 SYSREG(2, 0, 0, 13, 6)
281#define SYSREG_DBGWCR13_EL1 SYSREG(2, 0, 0, 13, 7)
282#define SYSREG_DBGBVR14_EL1 SYSREG(2, 0, 0, 14, 4)
283#define SYSREG_DBGBCR14_EL1 SYSREG(2, 0, 0, 14, 5)
284#define SYSREG_DBGWVR14_EL1 SYSREG(2, 0, 0, 14, 6)
285#define SYSREG_DBGWCR14_EL1 SYSREG(2, 0, 0, 14, 7)
286#define SYSREG_DBGBVR15_EL1 SYSREG(2, 0, 0, 15, 4)
287#define SYSREG_DBGBCR15_EL1 SYSREG(2, 0, 0, 15, 5)
288#define SYSREG_DBGWVR15_EL1 SYSREG(2, 0, 0, 15, 6)
289#define SYSREG_DBGWCR15_EL1 SYSREG(2, 0, 0, 15, 7)
290
a1477da3
AG		 291#define WFX_IS_WFE (1 << 0)
292
293#define TMR_CTL_ENABLE (1 << 0)
294#define TMR_CTL_IMASK (1 << 1)
295#define TMR_CTL_ISTATUS (1 << 2)
296
2c9c0bf9
AG		 297static void hvf_wfi(CPUState *cpu);
298
a1477da3
AG		 299typedef struct HVFVTimer {
300 /* Vtimer value during migration and paused state */
301 uint64_t vtimer_val;
302} HVFVTimer;
303
304static HVFVTimer vtimer;
305
585df85e
PM		 306typedef struct ARMHostCPUFeatures {
307 ARMISARegisters isar;
308 uint64_t features;
309 uint64_t midr;
310 uint32_t reset_sctlr;
311 const char *dtb_compatible;
312} ARMHostCPUFeatures;
313
314static ARMHostCPUFeatures arm_host_cpu_features;
315
a1477da3
AG		 316struct hvf_reg_match {
317 int reg;
318 uint64_t offset;
319};
320
321static const struct hvf_reg_match hvf_reg_match[] = {
322 { HV_REG_X0, offsetof(CPUARMState, xregs[0]) },
323 { HV_REG_X1, offsetof(CPUARMState, xregs[1]) },
324 { HV_REG_X2, offsetof(CPUARMState, xregs[2]) },
325 { HV_REG_X3, offsetof(CPUARMState, xregs[3]) },
326 { HV_REG_X4, offsetof(CPUARMState, xregs[4]) },
327 { HV_REG_X5, offsetof(CPUARMState, xregs[5]) },
328 { HV_REG_X6, offsetof(CPUARMState, xregs[6]) },
329 { HV_REG_X7, offsetof(CPUARMState, xregs[7]) },
330 { HV_REG_X8, offsetof(CPUARMState, xregs[8]) },
331 { HV_REG_X9, offsetof(CPUARMState, xregs[9]) },
332 { HV_REG_X10, offsetof(CPUARMState, xregs[10]) },
333 { HV_REG_X11, offsetof(CPUARMState, xregs[11]) },
334 { HV_REG_X12, offsetof(CPUARMState, xregs[12]) },
335 { HV_REG_X13, offsetof(CPUARMState, xregs[13]) },
336 { HV_REG_X14, offsetof(CPUARMState, xregs[14]) },
337 { HV_REG_X15, offsetof(CPUARMState, xregs[15]) },
338 { HV_REG_X16, offsetof(CPUARMState, xregs[16]) },
339 { HV_REG_X17, offsetof(CPUARMState, xregs[17]) },
340 { HV_REG_X18, offsetof(CPUARMState, xregs[18]) },
341 { HV_REG_X19, offsetof(CPUARMState, xregs[19]) },
342 { HV_REG_X20, offsetof(CPUARMState, xregs[20]) },
343 { HV_REG_X21, offsetof(CPUARMState, xregs[21]) },
344 { HV_REG_X22, offsetof(CPUARMState, xregs[22]) },
345 { HV_REG_X23, offsetof(CPUARMState, xregs[23]) },
346 { HV_REG_X24, offsetof(CPUARMState, xregs[24]) },
347 { HV_REG_X25, offsetof(CPUARMState, xregs[25]) },
348 { HV_REG_X26, offsetof(CPUARMState, xregs[26]) },
349 { HV_REG_X27, offsetof(CPUARMState, xregs[27]) },
350 { HV_REG_X28, offsetof(CPUARMState, xregs[28]) },
351 { HV_REG_X29, offsetof(CPUARMState, xregs[29]) },
352 { HV_REG_X30, offsetof(CPUARMState, xregs[30]) },
353 { HV_REG_PC, offsetof(CPUARMState, pc) },
354};
355
356static const struct hvf_reg_match hvf_fpreg_match[] = {
357 { HV_SIMD_FP_REG_Q0, offsetof(CPUARMState, vfp.zregs[0]) },
358 { HV_SIMD_FP_REG_Q1, offsetof(CPUARMState, vfp.zregs[1]) },
359 { HV_SIMD_FP_REG_Q2, offsetof(CPUARMState, vfp.zregs[2]) },
360 { HV_SIMD_FP_REG_Q3, offsetof(CPUARMState, vfp.zregs[3]) },
361 { HV_SIMD_FP_REG_Q4, offsetof(CPUARMState, vfp.zregs[4]) },
362 { HV_SIMD_FP_REG_Q5, offsetof(CPUARMState, vfp.zregs[5]) },
363 { HV_SIMD_FP_REG_Q6, offsetof(CPUARMState, vfp.zregs[6]) },
364 { HV_SIMD_FP_REG_Q7, offsetof(CPUARMState, vfp.zregs[7]) },
365 { HV_SIMD_FP_REG_Q8, offsetof(CPUARMState, vfp.zregs[8]) },
366 { HV_SIMD_FP_REG_Q9, offsetof(CPUARMState, vfp.zregs[9]) },
367 { HV_SIMD_FP_REG_Q10, offsetof(CPUARMState, vfp.zregs[10]) },
368 { HV_SIMD_FP_REG_Q11, offsetof(CPUARMState, vfp.zregs[11]) },
369 { HV_SIMD_FP_REG_Q12, offsetof(CPUARMState, vfp.zregs[12]) },
370 { HV_SIMD_FP_REG_Q13, offsetof(CPUARMState, vfp.zregs[13]) },
371 { HV_SIMD_FP_REG_Q14, offsetof(CPUARMState, vfp.zregs[14]) },
372 { HV_SIMD_FP_REG_Q15, offsetof(CPUARMState, vfp.zregs[15]) },
373 { HV_SIMD_FP_REG_Q16, offsetof(CPUARMState, vfp.zregs[16]) },
374 { HV_SIMD_FP_REG_Q17, offsetof(CPUARMState, vfp.zregs[17]) },
375 { HV_SIMD_FP_REG_Q18, offsetof(CPUARMState, vfp.zregs[18]) },
376 { HV_SIMD_FP_REG_Q19, offsetof(CPUARMState, vfp.zregs[19]) },
377 { HV_SIMD_FP_REG_Q20, offsetof(CPUARMState, vfp.zregs[20]) },
378 { HV_SIMD_FP_REG_Q21, offsetof(CPUARMState, vfp.zregs[21]) },
379 { HV_SIMD_FP_REG_Q22, offsetof(CPUARMState, vfp.zregs[22]) },
380 { HV_SIMD_FP_REG_Q23, offsetof(CPUARMState, vfp.zregs[23]) },
381 { HV_SIMD_FP_REG_Q24, offsetof(CPUARMState, vfp.zregs[24]) },
382 { HV_SIMD_FP_REG_Q25, offsetof(CPUARMState, vfp.zregs[25]) },
383 { HV_SIMD_FP_REG_Q26, offsetof(CPUARMState, vfp.zregs[26]) },
384 { HV_SIMD_FP_REG_Q27, offsetof(CPUARMState, vfp.zregs[27]) },
385 { HV_SIMD_FP_REG_Q28, offsetof(CPUARMState, vfp.zregs[28]) },
386 { HV_SIMD_FP_REG_Q29, offsetof(CPUARMState, vfp.zregs[29]) },
387 { HV_SIMD_FP_REG_Q30, offsetof(CPUARMState, vfp.zregs[30]) },
388 { HV_SIMD_FP_REG_Q31, offsetof(CPUARMState, vfp.zregs[31]) },
389};
390
391struct hvf_sreg_match {
392 int reg;
393 uint32_t key;
394 uint32_t cp_idx;
395};
396
397static struct hvf_sreg_match hvf_sreg_match[] = {
398 { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 4) },
399 { HV_SYS_REG_DBGBCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 5) },
400 { HV_SYS_REG_DBGWVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 6) },
401 { HV_SYS_REG_DBGWCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 7) },
402
403 { HV_SYS_REG_DBGBVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 4) },
404 { HV_SYS_REG_DBGBCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 5) },
405 { HV_SYS_REG_DBGWVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 6) },
406 { HV_SYS_REG_DBGWCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 7) },
407
408 { HV_SYS_REG_DBGBVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 4) },
409 { HV_SYS_REG_DBGBCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 5) },
410 { HV_SYS_REG_DBGWVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 6) },
411 { HV_SYS_REG_DBGWCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 7) },
412
413 { HV_SYS_REG_DBGBVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 4) },
414 { HV_SYS_REG_DBGBCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 5) },
415 { HV_SYS_REG_DBGWVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 6) },
416 { HV_SYS_REG_DBGWCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 7) },
417
418 { HV_SYS_REG_DBGBVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 4) },
419 { HV_SYS_REG_DBGBCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 5) },
420 { HV_SYS_REG_DBGWVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 6) },
421 { HV_SYS_REG_DBGWCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 7) },
422
423 { HV_SYS_REG_DBGBVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 4) },
424 { HV_SYS_REG_DBGBCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 5) },
425 { HV_SYS_REG_DBGWVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 6) },
426 { HV_SYS_REG_DBGWCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 7) },
427
428 { HV_SYS_REG_DBGBVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 4) },
429 { HV_SYS_REG_DBGBCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 5) },
430 { HV_SYS_REG_DBGWVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 6) },
431 { HV_SYS_REG_DBGWCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 7) },
432
433 { HV_SYS_REG_DBGBVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 4) },
434 { HV_SYS_REG_DBGBCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 5) },
435 { HV_SYS_REG_DBGWVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 6) },
436 { HV_SYS_REG_DBGWCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 7) },
437
438 { HV_SYS_REG_DBGBVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 4) },
439 { HV_SYS_REG_DBGBCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 5) },
440 { HV_SYS_REG_DBGWVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 6) },
441 { HV_SYS_REG_DBGWCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 7) },
442
443 { HV_SYS_REG_DBGBVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 4) },
444 { HV_SYS_REG_DBGBCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 5) },
445 { HV_SYS_REG_DBGWVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 6) },
446 { HV_SYS_REG_DBGWCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 7) },
447
448 { HV_SYS_REG_DBGBVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 4) },
449 { HV_SYS_REG_DBGBCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 5) },
450 { HV_SYS_REG_DBGWVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 6) },
451 { HV_SYS_REG_DBGWCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 7) },
452
453 { HV_SYS_REG_DBGBVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 4) },
454 { HV_SYS_REG_DBGBCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 5) },
455 { HV_SYS_REG_DBGWVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 6) },
456 { HV_SYS_REG_DBGWCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 7) },
457
458 { HV_SYS_REG_DBGBVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 4) },
459 { HV_SYS_REG_DBGBCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 5) },
460 { HV_SYS_REG_DBGWVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 6) },
461 { HV_SYS_REG_DBGWCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 7) },
462
463 { HV_SYS_REG_DBGBVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 4) },
464 { HV_SYS_REG_DBGBCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 5) },
465 { HV_SYS_REG_DBGWVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 6) },
466 { HV_SYS_REG_DBGWCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 7) },
467
468 { HV_SYS_REG_DBGBVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 4) },
469 { HV_SYS_REG_DBGBCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 5) },
470 { HV_SYS_REG_DBGWVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 6) },
471 { HV_SYS_REG_DBGWCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 7) },
472
473 { HV_SYS_REG_DBGBVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 4) },
474 { HV_SYS_REG_DBGBCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 5) },
475 { HV_SYS_REG_DBGWVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 6) },
476 { HV_SYS_REG_DBGWCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 7) },
477
478#ifdef SYNC_NO_RAW_REGS
479 /*
480 * The registers below are manually synced on init because they are
481 * marked as NO_RAW. We still list them to make number space sync easier.
482 */
483 { HV_SYS_REG_MDCCINT_EL1, HVF_SYSREG(0, 2, 2, 0, 0) },
484 { HV_SYS_REG_MIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 0) },
485 { HV_SYS_REG_MPIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 5) },
486 { HV_SYS_REG_ID_AA64PFR0_EL1, HVF_SYSREG(0, 4, 3, 0, 0) },
487#endif
488 { HV_SYS_REG_ID_AA64PFR1_EL1, HVF_SYSREG(0, 4, 3, 0, 2) },
489 { HV_SYS_REG_ID_AA64DFR0_EL1, HVF_SYSREG(0, 5, 3, 0, 0) },
490 { HV_SYS_REG_ID_AA64DFR1_EL1, HVF_SYSREG(0, 5, 3, 0, 1) },
491 { HV_SYS_REG_ID_AA64ISAR0_EL1, HVF_SYSREG(0, 6, 3, 0, 0) },
492 { HV_SYS_REG_ID_AA64ISAR1_EL1, HVF_SYSREG(0, 6, 3, 0, 1) },
493#ifdef SYNC_NO_MMFR0
494 /* We keep the hardware MMFR0 around. HW limits are there anyway */
495 { HV_SYS_REG_ID_AA64MMFR0_EL1, HVF_SYSREG(0, 7, 3, 0, 0) },
496#endif
497 { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) },
498 { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) },
499
500 { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) },
501 { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) },
502 { HV_SYS_REG_CPACR_EL1, HVF_SYSREG(1, 0, 3, 0, 2) },
503 { HV_SYS_REG_TTBR0_EL1, HVF_SYSREG(2, 0, 3, 0, 0) },
504 { HV_SYS_REG_TTBR1_EL1, HVF_SYSREG(2, 0, 3, 0, 1) },
505 { HV_SYS_REG_TCR_EL1, HVF_SYSREG(2, 0, 3, 0, 2) },
506
507 { HV_SYS_REG_APIAKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 0) },
508 { HV_SYS_REG_APIAKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 1) },
509 { HV_SYS_REG_APIBKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 2) },
510 { HV_SYS_REG_APIBKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 3) },
511 { HV_SYS_REG_APDAKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 0) },
512 { HV_SYS_REG_APDAKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 1) },
513 { HV_SYS_REG_APDBKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 2) },
514 { HV_SYS_REG_APDBKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 3) },
515 { HV_SYS_REG_APGAKEYLO_EL1, HVF_SYSREG(2, 3, 3, 0, 0) },
516 { HV_SYS_REG_APGAKEYHI_EL1, HVF_SYSREG(2, 3, 3, 0, 1) },
517
518 { HV_SYS_REG_SPSR_EL1, HVF_SYSREG(4, 0, 3, 0, 0) },
519 { HV_SYS_REG_ELR_EL1, HVF_SYSREG(4, 0, 3, 0, 1) },
520 { HV_SYS_REG_SP_EL0, HVF_SYSREG(4, 1, 3, 0, 0) },
521 { HV_SYS_REG_AFSR0_EL1, HVF_SYSREG(5, 1, 3, 0, 0) },
522 { HV_SYS_REG_AFSR1_EL1, HVF_SYSREG(5, 1, 3, 0, 1) },
523 { HV_SYS_REG_ESR_EL1, HVF_SYSREG(5, 2, 3, 0, 0) },
524 { HV_SYS_REG_FAR_EL1, HVF_SYSREG(6, 0, 3, 0, 0) },
525 { HV_SYS_REG_PAR_EL1, HVF_SYSREG(7, 4, 3, 0, 0) },
526 { HV_SYS_REG_MAIR_EL1, HVF_SYSREG(10, 2, 3, 0, 0) },
527 { HV_SYS_REG_AMAIR_EL1, HVF_SYSREG(10, 3, 3, 0, 0) },
528 { HV_SYS_REG_VBAR_EL1, HVF_SYSREG(12, 0, 3, 0, 0) },
529 { HV_SYS_REG_CONTEXTIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 1) },
530 { HV_SYS_REG_TPIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 4) },
531 { HV_SYS_REG_CNTKCTL_EL1, HVF_SYSREG(14, 1, 3, 0, 0) },
532 { HV_SYS_REG_CSSELR_EL1, HVF_SYSREG(0, 0, 3, 2, 0) },
533 { HV_SYS_REG_TPIDR_EL0, HVF_SYSREG(13, 0, 3, 3, 2) },
534 { HV_SYS_REG_TPIDRRO_EL0, HVF_SYSREG(13, 0, 3, 3, 3) },
535 { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) },
536 { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) },
537 { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) },
538};
539
540int hvf_get_registers(CPUState *cpu)
541{
542 ARMCPU *arm_cpu = ARM_CPU(cpu);
543 CPUARMState *env = &arm_cpu->env;
544 hv_return_t ret;
545 uint64_t val;
546 hv_simd_fp_uchar16_t fpval;
547 int i;
548
549 for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) {
3b295bcb 550 ret = hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val);
a1477da3
AG		 551 *(uint64_t *)((void *)env + hvf_reg_match[i].offset) = val;
552 assert_hvf_ok(ret);
553 }
554
555 for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) {
3b295bcb 556 ret = hv_vcpu_get_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i].reg,
a1477da3
AG		 557 &fpval);
558 memcpy((void *)env + hvf_fpreg_match[i].offset, &fpval, sizeof(fpval));
559 assert_hvf_ok(ret);
560 }
561
562 val = 0;
3b295bcb 563 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPCR, &val);
a1477da3
AG		 564 assert_hvf_ok(ret);
565 vfp_set_fpcr(env, val);
566
567 val = 0;
3b295bcb 568 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_FPSR, &val);
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AG		 569 assert_hvf_ok(ret);
570 vfp_set_fpsr(env, val);
571
3b295bcb 572 ret = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_CPSR, &val);
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AG		 573 assert_hvf_ok(ret);
574 pstate_write(env, val);
575
576 for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) {
577 if (hvf_sreg_match[i].cp_idx == -1) {
578 continue;
579 }
580
3b295bcb 581 if (cpu->accel->guest_debug_enabled) {
eb2edc42
FC		 582 /* Handle debug registers */
583 switch (hvf_sreg_match[i].reg) {
584 case HV_SYS_REG_DBGBVR0_EL1:
585 case HV_SYS_REG_DBGBCR0_EL1:
586 case HV_SYS_REG_DBGWVR0_EL1:
587 case HV_SYS_REG_DBGWCR0_EL1:
588 case HV_SYS_REG_DBGBVR1_EL1:
589 case HV_SYS_REG_DBGBCR1_EL1:
590 case HV_SYS_REG_DBGWVR1_EL1:
591 case HV_SYS_REG_DBGWCR1_EL1:
592 case HV_SYS_REG_DBGBVR2_EL1:
593 case HV_SYS_REG_DBGBCR2_EL1:
594 case HV_SYS_REG_DBGWVR2_EL1:
595 case HV_SYS_REG_DBGWCR2_EL1:
596 case HV_SYS_REG_DBGBVR3_EL1:
597 case HV_SYS_REG_DBGBCR3_EL1:
598 case HV_SYS_REG_DBGWVR3_EL1:
599 case HV_SYS_REG_DBGWCR3_EL1:
600 case HV_SYS_REG_DBGBVR4_EL1:
601 case HV_SYS_REG_DBGBCR4_EL1:
602 case HV_SYS_REG_DBGWVR4_EL1:
603 case HV_SYS_REG_DBGWCR4_EL1:
604 case HV_SYS_REG_DBGBVR5_EL1:
605 case HV_SYS_REG_DBGBCR5_EL1:
606 case HV_SYS_REG_DBGWVR5_EL1:
607 case HV_SYS_REG_DBGWCR5_EL1:
608 case HV_SYS_REG_DBGBVR6_EL1:
609 case HV_SYS_REG_DBGBCR6_EL1:
610 case HV_SYS_REG_DBGWVR6_EL1:
611 case HV_SYS_REG_DBGWCR6_EL1:
612 case HV_SYS_REG_DBGBVR7_EL1:
613 case HV_SYS_REG_DBGBCR7_EL1:
614 case HV_SYS_REG_DBGWVR7_EL1:
615 case HV_SYS_REG_DBGWCR7_EL1:
616 case HV_SYS_REG_DBGBVR8_EL1:
617 case HV_SYS_REG_DBGBCR8_EL1:
618 case HV_SYS_REG_DBGWVR8_EL1:
619 case HV_SYS_REG_DBGWCR8_EL1:
620 case HV_SYS_REG_DBGBVR9_EL1:
621 case HV_SYS_REG_DBGBCR9_EL1:
622 case HV_SYS_REG_DBGWVR9_EL1:
623 case HV_SYS_REG_DBGWCR9_EL1:
624 case HV_SYS_REG_DBGBVR10_EL1:
625 case HV_SYS_REG_DBGBCR10_EL1:
626 case HV_SYS_REG_DBGWVR10_EL1:
627 case HV_SYS_REG_DBGWCR10_EL1:
628 case HV_SYS_REG_DBGBVR11_EL1:
629 case HV_SYS_REG_DBGBCR11_EL1:
630 case HV_SYS_REG_DBGWVR11_EL1:
631 case HV_SYS_REG_DBGWCR11_EL1:
632 case HV_SYS_REG_DBGBVR12_EL1:
633 case HV_SYS_REG_DBGBCR12_EL1:
634 case HV_SYS_REG_DBGWVR12_EL1:
635 case HV_SYS_REG_DBGWCR12_EL1:
636 case HV_SYS_REG_DBGBVR13_EL1:
637 case HV_SYS_REG_DBGBCR13_EL1:
638 case HV_SYS_REG_DBGWVR13_EL1:
639 case HV_SYS_REG_DBGWCR13_EL1:
640 case HV_SYS_REG_DBGBVR14_EL1:
641 case HV_SYS_REG_DBGBCR14_EL1:
642 case HV_SYS_REG_DBGWVR14_EL1:
643 case HV_SYS_REG_DBGWCR14_EL1:
644 case HV_SYS_REG_DBGBVR15_EL1:
645 case HV_SYS_REG_DBGBCR15_EL1:
646 case HV_SYS_REG_DBGWVR15_EL1:
647 case HV_SYS_REG_DBGWCR15_EL1: {
648 /*
649 * If the guest is being debugged, the vCPU's debug registers
650 * are holding the gdbstub's view of the registers (set in
651 * hvf_arch_update_guest_debug()).
652 * Since the environment is used to store only the guest's view
653 * of the registers, don't update it with the values from the
654 * vCPU but simply keep the values from the previous
655 * environment.
656 */
657 const ARMCPRegInfo *ri;
658 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_sreg_match[i].key);
659 val = read_raw_cp_reg(env, ri);
660
661 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val;
662 continue;
663 }
664 }
665 }
666
3b295bcb 667 ret = hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, &val);
a1477da3
AG		 668 assert_hvf_ok(ret);
669
670 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val;
671 }
672 assert(write_list_to_cpustate(arm_cpu));
673
674 aarch64_restore_sp(env, arm_current_el(env));
675
676 return 0;
677}
678
679int hvf_put_registers(CPUState *cpu)
680{
681 ARMCPU *arm_cpu = ARM_CPU(cpu);
682 CPUARMState *env = &arm_cpu->env;
683 hv_return_t ret;
684 uint64_t val;
685 hv_simd_fp_uchar16_t fpval;
686 int i;
687
688 for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) {
689 val = *(uint64_t *)((void *)env + hvf_reg_match[i].offset);
3b295bcb 690 ret = hv_vcpu_set_reg(cpu->accel->fd, hvf_reg_match[i].reg, val);
a1477da3
AG		 691 assert_hvf_ok(ret);
692 }
693
694 for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) {
695 memcpy(&fpval, (void *)env + hvf_fpreg_match[i].offset, sizeof(fpval));
3b295bcb 696 ret = hv_vcpu_set_simd_fp_reg(cpu->accel->fd, hvf_fpreg_match[i].reg,
a1477da3
AG		 697 fpval);
698 assert_hvf_ok(ret);
699 }
700
3b295bcb 701 ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPCR, vfp_get_fpcr(env));
a1477da3
AG		 702 assert_hvf_ok(ret);
703
3b295bcb 704 ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_FPSR, vfp_get_fpsr(env));
a1477da3
AG		 705 assert_hvf_ok(ret);
706
3b295bcb 707 ret = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_CPSR, pstate_read(env));
a1477da3
AG		 708 assert_hvf_ok(ret);
709
710 aarch64_save_sp(env, arm_current_el(env));
711
712 assert(write_cpustate_to_list(arm_cpu, false));
713 for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) {
714 if (hvf_sreg_match[i].cp_idx == -1) {
715 continue;
716 }
717
3b295bcb 718 if (cpu->accel->guest_debug_enabled) {
eb2edc42
FC		 719 /* Handle debug registers */
720 switch (hvf_sreg_match[i].reg) {
721 case HV_SYS_REG_DBGBVR0_EL1:
722 case HV_SYS_REG_DBGBCR0_EL1:
723 case HV_SYS_REG_DBGWVR0_EL1:
724 case HV_SYS_REG_DBGWCR0_EL1:
725 case HV_SYS_REG_DBGBVR1_EL1:
726 case HV_SYS_REG_DBGBCR1_EL1:
727 case HV_SYS_REG_DBGWVR1_EL1:
728 case HV_SYS_REG_DBGWCR1_EL1:
729 case HV_SYS_REG_DBGBVR2_EL1:
730 case HV_SYS_REG_DBGBCR2_EL1:
731 case HV_SYS_REG_DBGWVR2_EL1:
732 case HV_SYS_REG_DBGWCR2_EL1:
733 case HV_SYS_REG_DBGBVR3_EL1:
734 case HV_SYS_REG_DBGBCR3_EL1:
735 case HV_SYS_REG_DBGWVR3_EL1:
736 case HV_SYS_REG_DBGWCR3_EL1:
737 case HV_SYS_REG_DBGBVR4_EL1:
738 case HV_SYS_REG_DBGBCR4_EL1:
739 case HV_SYS_REG_DBGWVR4_EL1:
740 case HV_SYS_REG_DBGWCR4_EL1:
741 case HV_SYS_REG_DBGBVR5_EL1:
742 case HV_SYS_REG_DBGBCR5_EL1:
743 case HV_SYS_REG_DBGWVR5_EL1:
744 case HV_SYS_REG_DBGWCR5_EL1:
745 case HV_SYS_REG_DBGBVR6_EL1:
746 case HV_SYS_REG_DBGBCR6_EL1:
747 case HV_SYS_REG_DBGWVR6_EL1:
748 case HV_SYS_REG_DBGWCR6_EL1:
749 case HV_SYS_REG_DBGBVR7_EL1:
750 case HV_SYS_REG_DBGBCR7_EL1:
751 case HV_SYS_REG_DBGWVR7_EL1:
752 case HV_SYS_REG_DBGWCR7_EL1:
753 case HV_SYS_REG_DBGBVR8_EL1:
754 case HV_SYS_REG_DBGBCR8_EL1:
755 case HV_SYS_REG_DBGWVR8_EL1:
756 case HV_SYS_REG_DBGWCR8_EL1:
757 case HV_SYS_REG_DBGBVR9_EL1:
758 case HV_SYS_REG_DBGBCR9_EL1:
759 case HV_SYS_REG_DBGWVR9_EL1:
760 case HV_SYS_REG_DBGWCR9_EL1:
761 case HV_SYS_REG_DBGBVR10_EL1:
762 case HV_SYS_REG_DBGBCR10_EL1:
763 case HV_SYS_REG_DBGWVR10_EL1:
764 case HV_SYS_REG_DBGWCR10_EL1:
765 case HV_SYS_REG_DBGBVR11_EL1:
766 case HV_SYS_REG_DBGBCR11_EL1:
767 case HV_SYS_REG_DBGWVR11_EL1:
768 case HV_SYS_REG_DBGWCR11_EL1:
769 case HV_SYS_REG_DBGBVR12_EL1:
770 case HV_SYS_REG_DBGBCR12_EL1:
771 case HV_SYS_REG_DBGWVR12_EL1:
772 case HV_SYS_REG_DBGWCR12_EL1:
773 case HV_SYS_REG_DBGBVR13_EL1:
774 case HV_SYS_REG_DBGBCR13_EL1:
775 case HV_SYS_REG_DBGWVR13_EL1:
776 case HV_SYS_REG_DBGWCR13_EL1:
777 case HV_SYS_REG_DBGBVR14_EL1:
778 case HV_SYS_REG_DBGBCR14_EL1:
779 case HV_SYS_REG_DBGWVR14_EL1:
780 case HV_SYS_REG_DBGWCR14_EL1:
781 case HV_SYS_REG_DBGBVR15_EL1:
782 case HV_SYS_REG_DBGBCR15_EL1:
783 case HV_SYS_REG_DBGWVR15_EL1:
784 case HV_SYS_REG_DBGWCR15_EL1:
785 /*
786 * If the guest is being debugged, the vCPU's debug registers
787 * are already holding the gdbstub's view of the registers (set
788 * in hvf_arch_update_guest_debug()).
789 */
790 continue;
791 }
792 }
793
a1477da3 794 val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx];
3b295bcb 795 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_sreg_match[i].reg, val);
a1477da3
AG		 796 assert_hvf_ok(ret);
797 }
798
3b295bcb 799 ret = hv_vcpu_set_vtimer_offset(cpu->accel->fd, hvf_state->vtimer_offset);
a1477da3
AG		 800 assert_hvf_ok(ret);
801
802 return 0;
803}
804
805static void flush_cpu_state(CPUState *cpu)
806{
807 if (cpu->vcpu_dirty) {
808 hvf_put_registers(cpu);
809 cpu->vcpu_dirty = false;
810 }
811}
812
813static void hvf_set_reg(CPUState *cpu, int rt, uint64_t val)
814{
815 hv_return_t r;
816
817 flush_cpu_state(cpu);
818
819 if (rt < 31) {
3b295bcb 820 r = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_X0 + rt, val);
a1477da3
AG		 821 assert_hvf_ok(r);
822 }
823}
824
825static uint64_t hvf_get_reg(CPUState *cpu, int rt)
826{
827 uint64_t val = 0;
828 hv_return_t r;
829
830 flush_cpu_state(cpu);
831
832 if (rt < 31) {
3b295bcb 833 r = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_X0 + rt, &val);
a1477da3
AG		 834 assert_hvf_ok(r);
835 }
836
837 return val;
838}
839
585df85e
PM		 840static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
841{
842 ARMISARegisters host_isar = {};
843 const struct isar_regs {
844 int reg;
845 uint64_t *val;
846 } regs[] = {
847 { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 },
848 { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 },
849 { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 },
850 { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 },
851 { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 },
852 { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 },
a969fe97 853 /* Add ID_AA64ISAR2_EL1 here when HVF supports it */
585df85e
PM		 854 { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 },
855 { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 },
856 { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 },
857 };
858 hv_vcpu_t fd;
859 hv_return_t r = HV_SUCCESS;
860 hv_vcpu_exit_t *exit;
861 int i;
862
863 ahcf->dtb_compatible = "arm,arm-v8";
864 ahcf->features = (1ULL << ARM_FEATURE_V8) |
865 (1ULL << ARM_FEATURE_NEON) |
866 (1ULL << ARM_FEATURE_AARCH64) |
867 (1ULL << ARM_FEATURE_PMU) |
868 (1ULL << ARM_FEATURE_GENERIC_TIMER);
869
870 /* We set up a small vcpu to extract host registers */
871
872 if (hv_vcpu_create(&fd, &exit, NULL) != HV_SUCCESS) {
873 return false;
874 }
875
876 for (i = 0; i < ARRAY_SIZE(regs); i++) {
877 r |= hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val);
878 }
879 r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr);
880 r |= hv_vcpu_destroy(fd);
881
882 ahcf->isar = host_isar;
883
884 /*
885 * A scratch vCPU returns SCTLR 0, so let's fill our default with the M1
886 * boot SCTLR from https://github.com/AsahiLinux/m1n1/issues/97
887 */
888 ahcf->reset_sctlr = 0x30100180;
889 /*
890 * SPAN is disabled by default when SCTLR.SPAN=1. To improve compatibility,
891 * let's disable it on boot and then allow guest software to turn it on by
892 * setting it to 0.
893 */
894 ahcf->reset_sctlr |= 0x00800000;
895
896 /* Make sure we don't advertise AArch32 support for EL0/EL1 */
897 if ((host_isar.id_aa64pfr0 & 0xff) != 0x11) {
898 return false;
899 }
900
901 return r == HV_SUCCESS;
902}
903
904void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu)
905{
906 if (!arm_host_cpu_features.dtb_compatible) {
907 if (!hvf_enabled() ||
908 !hvf_arm_get_host_cpu_features(&arm_host_cpu_features)) {
909 /*
910 * We can't report this error yet, so flag that we need to
911 * in arm_cpu_realizefn().
912 */
913 cpu->host_cpu_probe_failed = true;
914 return;
915 }
916 }
917
918 cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible;
919 cpu->isar = arm_host_cpu_features.isar;
920 cpu->env.features = arm_host_cpu_features.features;
921 cpu->midr = arm_host_cpu_features.midr;
922 cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr;
923}
924
a1477da3
AG		 925void hvf_arch_vcpu_destroy(CPUState *cpu)
926{
927}
928
929int hvf_arch_init_vcpu(CPUState *cpu)
930{
931 ARMCPU *arm_cpu = ARM_CPU(cpu);
932 CPUARMState *env = &arm_cpu->env;
933 uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_match);
934 uint32_t sregs_cnt = 0;
935 uint64_t pfr;
936 hv_return_t ret;
937 int i;
938
53221552 939 env->aarch64 = true;
a1477da3
AG		 940 asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz));
941
942 /* Allocate enough space for our sysreg sync */
943 arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes,
944 sregs_match_len);
945 arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values,
946 sregs_match_len);
947 arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t,
948 arm_cpu->cpreg_vmstate_indexes,
949 sregs_match_len);
950 arm_cpu->cpreg_vmstate_values = g_renew(uint64_t,
951 arm_cpu->cpreg_vmstate_values,
952 sregs_match_len);
953
954 memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t));
955
956 /* Populate cp list for all known sysregs */
957 for (i = 0; i < sregs_match_len; i++) {
958 const ARMCPRegInfo *ri;
959 uint32_t key = hvf_sreg_match[i].key;
960
961 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);
962 if (ri) {
963 assert(!(ri->type & ARM_CP_NO_RAW));
964 hvf_sreg_match[i].cp_idx = sregs_cnt;
965 arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key);
966 } else {
967 hvf_sreg_match[i].cp_idx = -1;
968 }
969 }
970 arm_cpu->cpreg_array_len = sregs_cnt;
971 arm_cpu->cpreg_vmstate_array_len = sregs_cnt;
972
973 assert(write_cpustate_to_list(arm_cpu, false));
974
975 /* Set CP_NO_RAW system registers on init */
3b295bcb 976 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MIDR_EL1,
a1477da3
AG		 977 arm_cpu->midr);
978 assert_hvf_ok(ret);
979
3b295bcb 980 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MPIDR_EL1,
a1477da3
AG		 981 arm_cpu->mp_affinity);
982 assert_hvf_ok(ret);
983
3b295bcb 984 ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr);
a1477da3
AG		 985 assert_hvf_ok(ret);
986 pfr |= env->gicv3state ? (1 << 24) : 0;
3b295bcb 987 ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr);
a1477da3
AG		 988 assert_hvf_ok(ret);
989
990 /* We're limited to underlying hardware caps, override internal versions */
3b295bcb 991 ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL1,
a1477da3
AG		 992 &arm_cpu->isar.id_aa64mmfr0);
993 assert_hvf_ok(ret);
994
995 return 0;
996}
997
998void hvf_kick_vcpu_thread(CPUState *cpu)
999{
219c101f 1000 cpus_kick_thread(cpu);
3b295bcb 1001 hv_vcpus_exit(&cpu->accel->fd, 1);
a1477da3
AG		 1002}
1003
1004static void hvf_raise_exception(CPUState *cpu, uint32_t excp,
1005 uint32_t syndrome)
1006{
1007 ARMCPU *arm_cpu = ARM_CPU(cpu);
1008 CPUARMState *env = &arm_cpu->env;
1009
1010 cpu->exception_index = excp;
1011 env->exception.target_el = 1;
1012 env->exception.syndrome = syndrome;
1013
1014 arm_cpu_do_interrupt(cpu);
1015}
1016
2c9c0bf9
AG		 1017static void hvf_psci_cpu_off(ARMCPU *arm_cpu)
1018{
1019 int32_t ret = arm_set_cpu_off(arm_cpu->mp_affinity);
1020 assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS);
1021}
1022
1023/*
1024 * Handle a PSCI call.
1025 *
1026 * Returns 0 on success
1027 * -1 when the PSCI call is unknown,
1028 */
1029static bool hvf_handle_psci_call(CPUState *cpu)
1030{
1031 ARMCPU *arm_cpu = ARM_CPU(cpu);
1032 CPUARMState *env = &arm_cpu->env;
1033 uint64_t param[4] = {
1034 env->xregs[0],
1035 env->xregs[1],
1036 env->xregs[2],
1037 env->xregs[3]
1038 };
1039 uint64_t context_id, mpidr;
1040 bool target_aarch64 = true;
1041 CPUState *target_cpu_state;
1042 ARMCPU *target_cpu;
1043 target_ulong entry;
1044 int target_el = 1;
1045 int32_t ret = 0;
1046
1047 trace_hvf_psci_call(param[0], param[1], param[2], param[3],
1048 arm_cpu->mp_affinity);
1049
1050 switch (param[0]) {
1051 case QEMU_PSCI_0_2_FN_PSCI_VERSION:
0dc71c70 1052 ret = QEMU_PSCI_VERSION_1_1;
2c9c0bf9
AG		 1053 break;
1054 case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
1055 ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */
1056 break;
1057 case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
1058 case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
1059 mpidr = param[1];
1060
1061 switch (param[2]) {
1062 case 0:
1063 target_cpu_state = arm_get_cpu_by_id(mpidr);
1064 if (!target_cpu_state) {
1065 ret = QEMU_PSCI_RET_INVALID_PARAMS;
1066 break;
1067 }
1068 target_cpu = ARM_CPU(target_cpu_state);
1069
1070 ret = target_cpu->power_state;
1071 break;
1072 default:
1073 /* Everything above affinity level 0 is always on. */
1074 ret = 0;
1075 }
1076 break;
1077 case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
1078 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
1079 /*
1080 * QEMU reset and shutdown are async requests, but PSCI
1081 * mandates that we never return from the reset/shutdown
1082 * call, so power the CPU off now so it doesn't execute
1083 * anything further.
1084 */
1085 hvf_psci_cpu_off(arm_cpu);
1086 break;
1087 case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
1088 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
1089 hvf_psci_cpu_off(arm_cpu);
1090 break;
1091 case QEMU_PSCI_0_1_FN_CPU_ON:
1092 case QEMU_PSCI_0_2_FN_CPU_ON:
1093 case QEMU_PSCI_0_2_FN64_CPU_ON:
1094 mpidr = param[1];
1095 entry = param[2];
1096 context_id = param[3];
1097 ret = arm_set_cpu_on(mpidr, entry, context_id,
1098 target_el, target_aarch64);
1099 break;
1100 case QEMU_PSCI_0_1_FN_CPU_OFF:
1101 case QEMU_PSCI_0_2_FN_CPU_OFF:
1102 hvf_psci_cpu_off(arm_cpu);
1103 break;
1104 case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
1105 case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
1106 case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
1107 /* Affinity levels are not supported in QEMU */
1108 if (param[1] & 0xfffe0000) {
1109 ret = QEMU_PSCI_RET_INVALID_PARAMS;
1110 break;
1111 }
1112 /* Powerdown is not supported, we always go into WFI */
1113 env->xregs[0] = 0;
1114 hvf_wfi(cpu);
1115 break;
1116 case QEMU_PSCI_0_1_FN_MIGRATE:
1117 case QEMU_PSCI_0_2_FN_MIGRATE:
1118 ret = QEMU_PSCI_RET_NOT_SUPPORTED;
1119 break;
0dc71c70
AO		 1120 case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
1121 switch (param[1]) {
1122 case QEMU_PSCI_0_2_FN_PSCI_VERSION:
1123 case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
1124 case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
1125 case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
1126 case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
1127 case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
1128 case QEMU_PSCI_0_1_FN_CPU_ON:
1129 case QEMU_PSCI_0_2_FN_CPU_ON:
1130 case QEMU_PSCI_0_2_FN64_CPU_ON:
1131 case QEMU_PSCI_0_1_FN_CPU_OFF:
1132 case QEMU_PSCI_0_2_FN_CPU_OFF:
1133 case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
1134 case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
1135 case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
1136 case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
1137 ret = 0;
1138 break;
1139 case QEMU_PSCI_0_1_FN_MIGRATE:
1140 case QEMU_PSCI_0_2_FN_MIGRATE:
1141 default:
1142 ret = QEMU_PSCI_RET_NOT_SUPPORTED;
1143 }
1144 break;
2c9c0bf9
AG		 1145 default:
1146 return false;
1147 }
1148
1149 env->xregs[0] = ret;
1150 return true;
1151}
1152
7f6c295c
AG		 1153static bool is_id_sysreg(uint32_t reg)
1154{
1155 return SYSREG_OP0(reg) == 3 &&
1156 SYSREG_OP1(reg) == 0 &&
1157 SYSREG_CRN(reg) == 0 &&
1158 SYSREG_CRM(reg) >= 1 &&
1159 SYSREG_CRM(reg) < 8;
1160}
1161
a2260983
AG		 1162static uint32_t hvf_reg2cp_reg(uint32_t reg)
1163{
1164 return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
1165 (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK,
1166 (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK,
1167 (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK,
1168 (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK,
1169 (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK);
1170}
1171
1172static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val)
1173{
1174 ARMCPU *arm_cpu = ARM_CPU(cpu);
1175 CPUARMState *env = &arm_cpu->env;
1176 const ARMCPRegInfo *ri;
1177
1178 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));
1179 if (ri) {
1180 if (ri->accessfn) {
1181 if (ri->accessfn(env, ri, true) != CP_ACCESS_OK) {
1182 return false;
1183 }
1184 }
1185 if (ri->type & ARM_CP_CONST) {
1186 *val = ri->resetvalue;
1187 } else if (ri->readfn) {
1188 *val = ri->readfn(env, ri);
1189 } else {
1190 *val = CPREG_FIELD64(env, ri);
1191 }
1192 trace_hvf_vgic_read(ri->name, *val);
1193 return true;
1194 }
1195
1196 return false;
1197}
1198
a1477da3
AG		 1199static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
1200{
1201 ARMCPU *arm_cpu = ARM_CPU(cpu);
1202 CPUARMState *env = &arm_cpu->env;
1203 uint64_t val = 0;
1204
1205 switch (reg) {
1206 case SYSREG_CNTPCT_EL0:
1207 val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /
1208 gt_cntfrq_period_ns(arm_cpu);
1209 break;
dd43ac07
AG		 1210 case SYSREG_PMCR_EL0:
1211 val = env->cp15.c9_pmcr;
1212 break;
1213 case SYSREG_PMCCNTR_EL0:
1214 pmu_op_start(env);
1215 val = env->cp15.c15_ccnt;
1216 pmu_op_finish(env);
1217 break;
1218 case SYSREG_PMCNTENCLR_EL0:
1219 val = env->cp15.c9_pmcnten;
1220 break;
1221 case SYSREG_PMOVSCLR_EL0:
1222 val = env->cp15.c9_pmovsr;
1223 break;
1224 case SYSREG_PMSELR_EL0:
1225 val = env->cp15.c9_pmselr;
1226 break;
1227 case SYSREG_PMINTENCLR_EL1:
1228 val = env->cp15.c9_pminten;
1229 break;
1230 case SYSREG_PMCCFILTR_EL0:
1231 val = env->cp15.pmccfiltr_el0;
1232 break;
1233 case SYSREG_PMCNTENSET_EL0:
1234 val = env->cp15.c9_pmcnten;
1235 break;
1236 case SYSREG_PMUSERENR_EL0:
1237 val = env->cp15.c9_pmuserenr;
1238 break;
1239 case SYSREG_PMCEID0_EL0:
1240 case SYSREG_PMCEID1_EL0:
1241 /* We can't really count anything yet, declare all events invalid */
1242 val = 0;
1243 break;
a1477da3
AG		 1244 case SYSREG_OSLSR_EL1:
1245 val = env->cp15.oslsr_el1;
1246 break;
1247 case SYSREG_OSDLR_EL1:
1248 /* Dummy register */
1249 break;
a2260983
AG		 1250 case SYSREG_ICC_AP0R0_EL1:
1251 case SYSREG_ICC_AP0R1_EL1:
1252 case SYSREG_ICC_AP0R2_EL1:
1253 case SYSREG_ICC_AP0R3_EL1:
1254 case SYSREG_ICC_AP1R0_EL1:
1255 case SYSREG_ICC_AP1R1_EL1:
1256 case SYSREG_ICC_AP1R2_EL1:
1257 case SYSREG_ICC_AP1R3_EL1:
1258 case SYSREG_ICC_ASGI1R_EL1:
1259 case SYSREG_ICC_BPR0_EL1:
1260 case SYSREG_ICC_BPR1_EL1:
1261 case SYSREG_ICC_DIR_EL1:
1262 case SYSREG_ICC_EOIR0_EL1:
1263 case SYSREG_ICC_EOIR1_EL1:
1264 case SYSREG_ICC_HPPIR0_EL1:
1265 case SYSREG_ICC_HPPIR1_EL1:
1266 case SYSREG_ICC_IAR0_EL1:
1267 case SYSREG_ICC_IAR1_EL1:
1268 case SYSREG_ICC_IGRPEN0_EL1:
1269 case SYSREG_ICC_IGRPEN1_EL1:
1270 case SYSREG_ICC_PMR_EL1:
1271 case SYSREG_ICC_SGI0R_EL1:
1272 case SYSREG_ICC_SGI1R_EL1:
1273 case SYSREG_ICC_SRE_EL1:
1274 case SYSREG_ICC_CTLR_EL1:
1275 /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */
1276 if (!hvf_sysreg_read_cp(cpu, reg, &val)) {
1277 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
1278 }
1279 break;
ce799a04
FC		 1280 case SYSREG_DBGBVR0_EL1:
1281 case SYSREG_DBGBVR1_EL1:
1282 case SYSREG_DBGBVR2_EL1:
1283 case SYSREG_DBGBVR3_EL1:
1284 case SYSREG_DBGBVR4_EL1:
1285 case SYSREG_DBGBVR5_EL1:
1286 case SYSREG_DBGBVR6_EL1:
1287 case SYSREG_DBGBVR7_EL1:
1288 case SYSREG_DBGBVR8_EL1:
1289 case SYSREG_DBGBVR9_EL1:
1290 case SYSREG_DBGBVR10_EL1:
1291 case SYSREG_DBGBVR11_EL1:
1292 case SYSREG_DBGBVR12_EL1:
1293 case SYSREG_DBGBVR13_EL1:
1294 case SYSREG_DBGBVR14_EL1:
1295 case SYSREG_DBGBVR15_EL1:
1296 val = env->cp15.dbgbvr[SYSREG_CRM(reg)];
1297 break;
1298 case SYSREG_DBGBCR0_EL1:
1299 case SYSREG_DBGBCR1_EL1:
1300 case SYSREG_DBGBCR2_EL1:
1301 case SYSREG_DBGBCR3_EL1:
1302 case SYSREG_DBGBCR4_EL1:
1303 case SYSREG_DBGBCR5_EL1:
1304 case SYSREG_DBGBCR6_EL1:
1305 case SYSREG_DBGBCR7_EL1:
1306 case SYSREG_DBGBCR8_EL1:
1307 case SYSREG_DBGBCR9_EL1:
1308 case SYSREG_DBGBCR10_EL1:
1309 case SYSREG_DBGBCR11_EL1:
1310 case SYSREG_DBGBCR12_EL1:
1311 case SYSREG_DBGBCR13_EL1:
1312 case SYSREG_DBGBCR14_EL1:
1313 case SYSREG_DBGBCR15_EL1:
1314 val = env->cp15.dbgbcr[SYSREG_CRM(reg)];
1315 break;
1316 case SYSREG_DBGWVR0_EL1:
1317 case SYSREG_DBGWVR1_EL1:
1318 case SYSREG_DBGWVR2_EL1:
1319 case SYSREG_DBGWVR3_EL1:
1320 case SYSREG_DBGWVR4_EL1:
1321 case SYSREG_DBGWVR5_EL1:
1322 case SYSREG_DBGWVR6_EL1:
1323 case SYSREG_DBGWVR7_EL1:
1324 case SYSREG_DBGWVR8_EL1:
1325 case SYSREG_DBGWVR9_EL1:
1326 case SYSREG_DBGWVR10_EL1:
1327 case SYSREG_DBGWVR11_EL1:
1328 case SYSREG_DBGWVR12_EL1:
1329 case SYSREG_DBGWVR13_EL1:
1330 case SYSREG_DBGWVR14_EL1:
1331 case SYSREG_DBGWVR15_EL1:
1332 val = env->cp15.dbgwvr[SYSREG_CRM(reg)];
1333 break;
1334 case SYSREG_DBGWCR0_EL1:
1335 case SYSREG_DBGWCR1_EL1:
1336 case SYSREG_DBGWCR2_EL1:
1337 case SYSREG_DBGWCR3_EL1:
1338 case SYSREG_DBGWCR4_EL1:
1339 case SYSREG_DBGWCR5_EL1:
1340 case SYSREG_DBGWCR6_EL1:
1341 case SYSREG_DBGWCR7_EL1:
1342 case SYSREG_DBGWCR8_EL1:
1343 case SYSREG_DBGWCR9_EL1:
1344 case SYSREG_DBGWCR10_EL1:
1345 case SYSREG_DBGWCR11_EL1:
1346 case SYSREG_DBGWCR12_EL1:
1347 case SYSREG_DBGWCR13_EL1:
1348 case SYSREG_DBGWCR14_EL1:
1349 case SYSREG_DBGWCR15_EL1:
1350 val = env->cp15.dbgwcr[SYSREG_CRM(reg)];
1351 break;
a1477da3 1352 default:
7f6c295c
AG		 1353 if (is_id_sysreg(reg)) {
1354 /* ID system registers read as RES0 */
1355 val = 0;
1356 break;
1357 }
a1477da3
AG		 1358 cpu_synchronize_state(cpu);
1359 trace_hvf_unhandled_sysreg_read(env->pc, reg,
ad99f64f
AG		 1360 SYSREG_OP0(reg),
1361 SYSREG_OP1(reg),
1362 SYSREG_CRN(reg),
1363 SYSREG_CRM(reg),
1364 SYSREG_OP2(reg));
a1477da3
AG		 1365 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
1366 return 1;
1367 }
1368
1369 trace_hvf_sysreg_read(reg,
ad99f64f
AG		 1370 SYSREG_OP0(reg),
1371 SYSREG_OP1(reg),
1372 SYSREG_CRN(reg),
1373 SYSREG_CRM(reg),
1374 SYSREG_OP2(reg),
a1477da3
AG		 1375 val);
1376 hvf_set_reg(cpu, rt, val);
1377
1378 return 0;
1379}
1380
dd43ac07
AG		 1381static void pmu_update_irq(CPUARMState *env)
1382{
1383 ARMCPU *cpu = env_archcpu(env);
1384 qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) &&
1385 (env->cp15.c9_pminten & env->cp15.c9_pmovsr));
1386}
1387
1388static bool pmu_event_supported(uint16_t number)
1389{
1390 return false;
1391}
1392
1393/* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1394 * the current EL, security state, and register configuration.
1395 */
1396static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
1397{
1398 uint64_t filter;
1399 bool enabled, filtered = true;
1400 int el = arm_current_el(env);
1401
1402 enabled = (env->cp15.c9_pmcr & PMCRE) &&
1403 (env->cp15.c9_pmcnten & (1 << counter));
1404
1405 if (counter == 31) {
1406 filter = env->cp15.pmccfiltr_el0;
1407 } else {
1408 filter = env->cp15.c14_pmevtyper[counter];
1409 }
1410
1411 if (el == 0) {
1412 filtered = filter & PMXEVTYPER_U;
1413 } else if (el == 1) {
1414 filtered = filter & PMXEVTYPER_P;
1415 }
1416
1417 if (counter != 31) {
1418 /*
1419 * If not checking PMCCNTR, ensure the counter is setup to an event we
1420 * support
1421 */
1422 uint16_t event = filter & PMXEVTYPER_EVTCOUNT;
1423 if (!pmu_event_supported(event)) {
1424 return false;
1425 }
1426 }
1427
1428 return enabled && !filtered;
1429}
1430
1431static void pmswinc_write(CPUARMState *env, uint64_t value)
1432{
1433 unsigned int i;
1434 for (i = 0; i < pmu_num_counters(env); i++) {
1435 /* Increment a counter's count iff: */
1436 if ((value & (1 << i)) && /* counter's bit is set */
1437 /* counter is enabled and not filtered */
1438 pmu_counter_enabled(env, i) &&
1439 /* counter is SW_INCR */
1440 (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) {
1441 /*
1442 * Detect if this write causes an overflow since we can't predict
1443 * PMSWINC overflows like we can for other events
1444 */
1445 uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1;
1446
1447 if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) {
1448 env->cp15.c9_pmovsr |= (1 << i);
1449 pmu_update_irq(env);
1450 }
1451
1452 env->cp15.c14_pmevcntr[i] = new_pmswinc;
1453 }
1454 }
1455}
1456
a2260983
AG		 1457static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val)
1458{
1459 ARMCPU *arm_cpu = ARM_CPU(cpu);
1460 CPUARMState *env = &arm_cpu->env;
1461 const ARMCPRegInfo *ri;
1462
1463 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));
1464
1465 if (ri) {
1466 if (ri->accessfn) {
1467 if (ri->accessfn(env, ri, false) != CP_ACCESS_OK) {
1468 return false;
1469 }
1470 }
1471 if (ri->writefn) {
1472 ri->writefn(env, ri, val);
1473 } else {
1474 CPREG_FIELD64(env, ri) = val;
1475 }
1476
1477 trace_hvf_vgic_write(ri->name, val);
1478 return true;
1479 }
1480
1481 return false;
1482}
1483
a1477da3
AG		 1484static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
1485{
1486 ARMCPU *arm_cpu = ARM_CPU(cpu);
1487 CPUARMState *env = &arm_cpu->env;
1488
1489 trace_hvf_sysreg_write(reg,
ad99f64f
AG		 1490 SYSREG_OP0(reg),
1491 SYSREG_OP1(reg),
1492 SYSREG_CRN(reg),
1493 SYSREG_CRM(reg),
1494 SYSREG_OP2(reg),
a1477da3
AG		 1495 val);
1496
1497 switch (reg) {
dd43ac07
AG		 1498 case SYSREG_PMCCNTR_EL0:
1499 pmu_op_start(env);
1500 env->cp15.c15_ccnt = val;
1501 pmu_op_finish(env);
1502 break;
1503 case SYSREG_PMCR_EL0:
1504 pmu_op_start(env);
1505
1506 if (val & PMCRC) {
1507 /* The counter has been reset */
1508 env->cp15.c15_ccnt = 0;
1509 }
1510
1511 if (val & PMCRP) {
1512 unsigned int i;
1513 for (i = 0; i < pmu_num_counters(env); i++) {
1514 env->cp15.c14_pmevcntr[i] = 0;
1515 }
1516 }
1517
9323e79f
PM		 1518 env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK;
1519 env->cp15.c9_pmcr |= (val & PMCR_WRITABLE_MASK);
dd43ac07
AG		 1520
1521 pmu_op_finish(env);
1522 break;
1523 case SYSREG_PMUSERENR_EL0:
1524 env->cp15.c9_pmuserenr = val & 0xf;
1525 break;
1526 case SYSREG_PMCNTENSET_EL0:
1527 env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env));
1528 break;
1529 case SYSREG_PMCNTENCLR_EL0:
1530 env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env));
1531 break;
1532 case SYSREG_PMINTENCLR_EL1:
1533 pmu_op_start(env);
1534 env->cp15.c9_pminten |= val;
1535 pmu_op_finish(env);
1536 break;
1537 case SYSREG_PMOVSCLR_EL0:
1538 pmu_op_start(env);
1539 env->cp15.c9_pmovsr &= ~val;
1540 pmu_op_finish(env);
1541 break;
1542 case SYSREG_PMSWINC_EL0:
1543 pmu_op_start(env);
1544 pmswinc_write(env, val);
1545 pmu_op_finish(env);
1546 break;
1547 case SYSREG_PMSELR_EL0:
1548 env->cp15.c9_pmselr = val & 0x1f;
1549 break;
1550 case SYSREG_PMCCFILTR_EL0:
1551 pmu_op_start(env);
1552 env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0;
1553 pmu_op_finish(env);
1554 break;
a1477da3
AG		 1555 case SYSREG_OSLAR_EL1:
1556 env->cp15.oslsr_el1 = val & 1;
1557 break;
1558 case SYSREG_OSDLR_EL1:
1559 /* Dummy register */
1560 break;
a2260983
AG		 1561 case SYSREG_ICC_AP0R0_EL1:
1562 case SYSREG_ICC_AP0R1_EL1:
1563 case SYSREG_ICC_AP0R2_EL1:
1564 case SYSREG_ICC_AP0R3_EL1:
1565 case SYSREG_ICC_AP1R0_EL1:
1566 case SYSREG_ICC_AP1R1_EL1:
1567 case SYSREG_ICC_AP1R2_EL1:
1568 case SYSREG_ICC_AP1R3_EL1:
1569 case SYSREG_ICC_ASGI1R_EL1:
1570 case SYSREG_ICC_BPR0_EL1:
1571 case SYSREG_ICC_BPR1_EL1:
1572 case SYSREG_ICC_CTLR_EL1:
1573 case SYSREG_ICC_DIR_EL1:
1574 case SYSREG_ICC_EOIR0_EL1:
1575 case SYSREG_ICC_EOIR1_EL1:
1576 case SYSREG_ICC_HPPIR0_EL1:
1577 case SYSREG_ICC_HPPIR1_EL1:
1578 case SYSREG_ICC_IAR0_EL1:
1579 case SYSREG_ICC_IAR1_EL1:
1580 case SYSREG_ICC_IGRPEN0_EL1:
1581 case SYSREG_ICC_IGRPEN1_EL1:
1582 case SYSREG_ICC_PMR_EL1:
1583 case SYSREG_ICC_SGI0R_EL1:
1584 case SYSREG_ICC_SGI1R_EL1:
1585 case SYSREG_ICC_SRE_EL1:
1586 /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */
1587 if (!hvf_sysreg_write_cp(cpu, reg, val)) {
1588 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
1589 }
1590 break;
ce799a04
FC		 1591 case SYSREG_MDSCR_EL1:
1592 env->cp15.mdscr_el1 = val;
1593 break;
1594 case SYSREG_DBGBVR0_EL1:
1595 case SYSREG_DBGBVR1_EL1:
1596 case SYSREG_DBGBVR2_EL1:
1597 case SYSREG_DBGBVR3_EL1:
1598 case SYSREG_DBGBVR4_EL1:
1599 case SYSREG_DBGBVR5_EL1:
1600 case SYSREG_DBGBVR6_EL1:
1601 case SYSREG_DBGBVR7_EL1:
1602 case SYSREG_DBGBVR8_EL1:
1603 case SYSREG_DBGBVR9_EL1:
1604 case SYSREG_DBGBVR10_EL1:
1605 case SYSREG_DBGBVR11_EL1:
1606 case SYSREG_DBGBVR12_EL1:
1607 case SYSREG_DBGBVR13_EL1:
1608 case SYSREG_DBGBVR14_EL1:
1609 case SYSREG_DBGBVR15_EL1:
1610 env->cp15.dbgbvr[SYSREG_CRM(reg)] = val;
1611 break;
1612 case SYSREG_DBGBCR0_EL1:
1613 case SYSREG_DBGBCR1_EL1:
1614 case SYSREG_DBGBCR2_EL1:
1615 case SYSREG_DBGBCR3_EL1:
1616 case SYSREG_DBGBCR4_EL1:
1617 case SYSREG_DBGBCR5_EL1:
1618 case SYSREG_DBGBCR6_EL1:
1619 case SYSREG_DBGBCR7_EL1:
1620 case SYSREG_DBGBCR8_EL1:
1621 case SYSREG_DBGBCR9_EL1:
1622 case SYSREG_DBGBCR10_EL1:
1623 case SYSREG_DBGBCR11_EL1:
1624 case SYSREG_DBGBCR12_EL1:
1625 case SYSREG_DBGBCR13_EL1:
1626 case SYSREG_DBGBCR14_EL1:
1627 case SYSREG_DBGBCR15_EL1:
1628 env->cp15.dbgbcr[SYSREG_CRM(reg)] = val;
1629 break;
1630 case SYSREG_DBGWVR0_EL1:
1631 case SYSREG_DBGWVR1_EL1:
1632 case SYSREG_DBGWVR2_EL1:
1633 case SYSREG_DBGWVR3_EL1:
1634 case SYSREG_DBGWVR4_EL1:
1635 case SYSREG_DBGWVR5_EL1:
1636 case SYSREG_DBGWVR6_EL1:
1637 case SYSREG_DBGWVR7_EL1:
1638 case SYSREG_DBGWVR8_EL1:
1639 case SYSREG_DBGWVR9_EL1:
1640 case SYSREG_DBGWVR10_EL1:
1641 case SYSREG_DBGWVR11_EL1:
1642 case SYSREG_DBGWVR12_EL1:
1643 case SYSREG_DBGWVR13_EL1:
1644 case SYSREG_DBGWVR14_EL1:
1645 case SYSREG_DBGWVR15_EL1:
1646 env->cp15.dbgwvr[SYSREG_CRM(reg)] = val;
1647 break;
1648 case SYSREG_DBGWCR0_EL1:
1649 case SYSREG_DBGWCR1_EL1:
1650 case SYSREG_DBGWCR2_EL1:
1651 case SYSREG_DBGWCR3_EL1:
1652 case SYSREG_DBGWCR4_EL1:
1653 case SYSREG_DBGWCR5_EL1:
1654 case SYSREG_DBGWCR6_EL1:
1655 case SYSREG_DBGWCR7_EL1:
1656 case SYSREG_DBGWCR8_EL1:
1657 case SYSREG_DBGWCR9_EL1:
1658 case SYSREG_DBGWCR10_EL1:
1659 case SYSREG_DBGWCR11_EL1:
1660 case SYSREG_DBGWCR12_EL1:
1661 case SYSREG_DBGWCR13_EL1:
1662 case SYSREG_DBGWCR14_EL1:
1663 case SYSREG_DBGWCR15_EL1:
1664 env->cp15.dbgwcr[SYSREG_CRM(reg)] = val;
1665 break;
a1477da3
AG		 1666 default:
1667 cpu_synchronize_state(cpu);
1668 trace_hvf_unhandled_sysreg_write(env->pc, reg,
ad99f64f
AG		 1669 SYSREG_OP0(reg),
1670 SYSREG_OP1(reg),
1671 SYSREG_CRN(reg),
1672 SYSREG_CRM(reg),
1673 SYSREG_OP2(reg));
a1477da3
AG		 1674 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
1675 return 1;
1676 }
1677
1678 return 0;
1679}
1680
1681static int hvf_inject_interrupts(CPUState *cpu)
1682{
1683 if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) {
1684 trace_hvf_inject_fiq();
3b295bcb 1685 hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_FIQ,
a1477da3
AG		 1686 true);
1687 }
1688
1689 if (cpu->interrupt_request & CPU_INTERRUPT_HARD) {
1690 trace_hvf_inject_irq();
3b295bcb 1691 hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_IRQ,
a1477da3
AG		 1692 true);
1693 }
1694
1695 return 0;
1696}
1697
1698static uint64_t hvf_vtimer_val_raw(void)
1699{
1700 /*
1701 * mach_absolute_time() returns the vtimer value without the VM
1702 * offset that we define. Add our own offset on top.
1703 */
1704 return mach_absolute_time() - hvf_state->vtimer_offset;
1705}
1706
219c101f
PC		 1707static uint64_t hvf_vtimer_val(void)
1708{
1709 if (!runstate_is_running()) {
1710 /* VM is paused, the vtimer value is in vtimer.vtimer_val */
1711 return vtimer.vtimer_val;
1712 }
1713
1714 return hvf_vtimer_val_raw();
1715}
1716
1717static void hvf_wait_for_ipi(CPUState *cpu, struct timespec *ts)
1718{
1719 /*
1720 * Use pselect to sleep so that other threads can IPI us while we're
1721 * sleeping.
1722 */
06831001 1723 qatomic_set_mb(&cpu->thread_kicked, false);
195801d7 1724 bql_unlock();
3b295bcb 1725 pselect(0, 0, 0, 0, ts, &cpu->accel->unblock_ipi_mask);
195801d7 1726 bql_lock();
219c101f
PC		 1727}
1728
1729static void hvf_wfi(CPUState *cpu)
1730{
1731 ARMCPU *arm_cpu = ARM_CPU(cpu);
1732 struct timespec ts;
1733 hv_return_t r;
1734 uint64_t ctl;
1735 uint64_t cval;
1736 int64_t ticks_to_sleep;
1737 uint64_t seconds;
1738 uint64_t nanos;
1739 uint32_t cntfrq;
1740
1741 if (cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ)) {
1742 /* Interrupt pending, no need to wait */
1743 return;
1744 }
1745
3b295bcb 1746 r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl);
219c101f
PC		 1747 assert_hvf_ok(r);
1748
1749 if (!(ctl & 1) || (ctl & 2)) {
1750 /* Timer disabled or masked, just wait for an IPI. */
1751 hvf_wait_for_ipi(cpu, NULL);
1752 return;
1753 }
1754
3b295bcb 1755 r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CVAL_EL0, &cval);
219c101f
PC		 1756 assert_hvf_ok(r);
1757
1758 ticks_to_sleep = cval - hvf_vtimer_val();
1759 if (ticks_to_sleep < 0) {
1760 return;
1761 }
1762
1763 cntfrq = gt_cntfrq_period_ns(arm_cpu);
1764 seconds = muldiv64(ticks_to_sleep, cntfrq, NANOSECONDS_PER_SECOND);
1765 ticks_to_sleep -= muldiv64(seconds, NANOSECONDS_PER_SECOND, cntfrq);
1766 nanos = ticks_to_sleep * cntfrq;
1767
1768 /*
1769 * Don't sleep for less than the time a context switch would take,
1770 * so that we can satisfy fast timer requests on the same CPU.
1771 * Measurements on M1 show the sweet spot to be ~2ms.
1772 */
1773 if (!seconds && nanos < (2 * SCALE_MS)) {
1774 return;
1775 }
1776
1777 ts = (struct timespec) { seconds, nanos };
1778 hvf_wait_for_ipi(cpu, &ts);
1779}
1780
a1477da3
AG		 1781static void hvf_sync_vtimer(CPUState *cpu)
1782{
1783 ARMCPU *arm_cpu = ARM_CPU(cpu);
1784 hv_return_t r;
1785 uint64_t ctl;
1786 bool irq_state;
1787
3b295bcb 1788 if (!cpu->accel->vtimer_masked) {
a1477da3
AG		 1789 /* We will get notified on vtimer changes by hvf, nothing to do */
1790 return;
1791 }
1792
3b295bcb 1793 r = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl);
a1477da3
AG		 1794 assert_hvf_ok(r);
1795
1796 irq_state = (ctl & (TMR_CTL_ENABLE | TMR_CTL_IMASK | TMR_CTL_ISTATUS)) ==
1797 (TMR_CTL_ENABLE | TMR_CTL_ISTATUS);
1798 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], irq_state);
1799
1800 if (!irq_state) {
1801 /* Timer no longer asserting, we can unmask it */
3b295bcb
PMD		 1802 hv_vcpu_set_vtimer_mask(cpu->accel->fd, false);
1803 cpu->accel->vtimer_masked = false;
a1477da3
AG		 1804 }
1805}
1806
1807int hvf_vcpu_exec(CPUState *cpu)
1808{
1809 ARMCPU *arm_cpu = ARM_CPU(cpu);
1810 CPUARMState *env = &arm_cpu->env;
eb2edc42 1811 int ret;
3b295bcb 1812 hv_vcpu_exit_t *hvf_exit = cpu->accel->exit;
a1477da3
AG		 1813 hv_return_t r;
1814 bool advance_pc = false;
1815
eb2edc42
FC		 1816 if (!(cpu->singlestep_enabled & SSTEP_NOIRQ) &&
1817 hvf_inject_interrupts(cpu)) {
a1477da3
AG		 1818 return EXCP_INTERRUPT;
1819 }
1820
1821 if (cpu->halted) {
1822 return EXCP_HLT;
1823 }
1824
1825 flush_cpu_state(cpu);
1826
195801d7 1827 bql_unlock();
3b295bcb 1828 assert_hvf_ok(hv_vcpu_run(cpu->accel->fd));
a1477da3
AG		 1829
1830 /* handle VMEXIT */
1831 uint64_t exit_reason = hvf_exit->reason;
1832 uint64_t syndrome = hvf_exit->exception.syndrome;
1833 uint32_t ec = syn_get_ec(syndrome);
1834
eb2edc42 1835 ret = 0;
195801d7 1836 bql_lock();
a1477da3
AG		 1837 switch (exit_reason) {
1838 case HV_EXIT_REASON_EXCEPTION:
1839 /* This is the main one, handle below. */
1840 break;
1841 case HV_EXIT_REASON_VTIMER_ACTIVATED:
1842 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1);
3b295bcb 1843 cpu->accel->vtimer_masked = true;
a1477da3
AG		 1844 return 0;
1845 case HV_EXIT_REASON_CANCELED:
1846 /* we got kicked, no exit to process */
1847 return 0;
1848 default:
d385a605 1849 g_assert_not_reached();
a1477da3
AG		 1850 }
1851
1852 hvf_sync_vtimer(cpu);
1853
1854 switch (ec) {
eb2edc42
FC		 1855 case EC_SOFTWARESTEP: {
1856 ret = EXCP_DEBUG;
1857
1858 if (!cpu->singlestep_enabled) {
1859 error_report("EC_SOFTWARESTEP but single-stepping not enabled");
1860 }
1861 break;
1862 }
1863 case EC_AA64_BKPT: {
1864 ret = EXCP_DEBUG;
1865
1866 cpu_synchronize_state(cpu);
1867
1868 if (!hvf_find_sw_breakpoint(cpu, env->pc)) {
1869 /* Re-inject into the guest */
1870 ret = 0;
1871 hvf_raise_exception(cpu, EXCP_BKPT, syn_aa64_bkpt(0));
1872 }
1873 break;
1874 }
1875 case EC_BREAKPOINT: {
1876 ret = EXCP_DEBUG;
1877
1878 cpu_synchronize_state(cpu);
1879
1880 if (!find_hw_breakpoint(cpu, env->pc)) {
1881 error_report("EC_BREAKPOINT but unknown hw breakpoint");
1882 }
1883 break;
1884 }
1885 case EC_WATCHPOINT: {
1886 ret = EXCP_DEBUG;
1887
1888 cpu_synchronize_state(cpu);
1889
1890 CPUWatchpoint *wp =
1891 find_hw_watchpoint(cpu, hvf_exit->exception.virtual_address);
1892 if (!wp) {
1893 error_report("EXCP_DEBUG but unknown hw watchpoint");
1894 }
1895 cpu->watchpoint_hit = wp;
1896 break;
1897 }
a1477da3
AG		 1898 case EC_DATAABORT: {
1899 bool isv = syndrome & ARM_EL_ISV;
1900 bool iswrite = (syndrome >> 6) & 1;
1901 bool s1ptw = (syndrome >> 7) & 1;
1902 uint32_t sas = (syndrome >> 22) & 3;
1903 uint32_t len = 1 << sas;
1904 uint32_t srt = (syndrome >> 16) & 0x1f;
5fd6a3e2 1905 uint32_t cm = (syndrome >> 8) & 0x1;
a1477da3
AG		 1906 uint64_t val = 0;
1907
1908 trace_hvf_data_abort(env->pc, hvf_exit->exception.virtual_address,
1909 hvf_exit->exception.physical_address, isv,
1910 iswrite, s1ptw, len, srt);
1911
5fd6a3e2
AG		 1912 if (cm) {
1913 /* We don't cache MMIO regions */
1914 advance_pc = true;
1915 break;
1916 }
1917
a1477da3
AG		 1918 assert(isv);
1919
1920 if (iswrite) {
1921 val = hvf_get_reg(cpu, srt);
1922 address_space_write(&address_space_memory,
1923 hvf_exit->exception.physical_address,
1924 MEMTXATTRS_UNSPECIFIED, &val, len);
1925 } else {
1926 address_space_read(&address_space_memory,
1927 hvf_exit->exception.physical_address,
1928 MEMTXATTRS_UNSPECIFIED, &val, len);
1929 hvf_set_reg(cpu, srt, val);
1930 }
1931
1932 advance_pc = true;
1933 break;
1934 }
1935 case EC_SYSTEMREGISTERTRAP: {
1936 bool isread = (syndrome >> 0) & 1;
1937 uint32_t rt = (syndrome >> 5) & 0x1f;
1938 uint32_t reg = syndrome & SYSREG_MASK;
1939 uint64_t val;
5a3d2c35 1940 int sysreg_ret = 0;
a1477da3
AG		 1941
1942 if (isread) {
5a3d2c35 1943 sysreg_ret = hvf_sysreg_read(cpu, reg, rt);
a1477da3
AG		 1944 } else {
1945 val = hvf_get_reg(cpu, rt);
5a3d2c35 1946 sysreg_ret = hvf_sysreg_write(cpu, reg, val);
a1477da3
AG		 1947 }
1948
5a3d2c35 1949 advance_pc = !sysreg_ret;
a1477da3
AG		 1950 break;
1951 }
1952 case EC_WFX_TRAP:
1953 advance_pc = true;
219c101f
PC		 1954 if (!(syndrome & WFX_IS_WFE)) {
1955 hvf_wfi(cpu);
1956 }
a1477da3
AG		 1957 break;
1958 case EC_AA64_HVC:
1959 cpu_synchronize_state(cpu);
2c9c0bf9
AG		 1960 if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_HVC) {
1961 if (!hvf_handle_psci_call(cpu)) {
1962 trace_hvf_unknown_hvc(env->xregs[0]);
1963 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */
1964 env->xregs[0] = -1;
1965 }
1966 } else {
1967 trace_hvf_unknown_hvc(env->xregs[0]);
1968 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
1969 }
a1477da3
AG		 1970 break;
1971 case EC_AA64_SMC:
1972 cpu_synchronize_state(cpu);
2c9c0bf9
AG		 1973 if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_SMC) {
1974 advance_pc = true;
1975
1976 if (!hvf_handle_psci_call(cpu)) {
1977 trace_hvf_unknown_smc(env->xregs[0]);
1978 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */
1979 env->xregs[0] = -1;
1980 }
1981 } else {
1982 trace_hvf_unknown_smc(env->xregs[0]);
1983 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
1984 }
a1477da3
AG		 1985 break;
1986 default:
1987 cpu_synchronize_state(cpu);
1988 trace_hvf_exit(syndrome, ec, env->pc);
1989 error_report("0x%llx: unhandled exception ec=0x%x", env->pc, ec);
1990 }
1991
1992 if (advance_pc) {
1993 uint64_t pc;
1994
1995 flush_cpu_state(cpu);
1996
3b295bcb 1997 r = hv_vcpu_get_reg(cpu->accel->fd, HV_REG_PC, &pc);
a1477da3
AG		 1998 assert_hvf_ok(r);
1999 pc += 4;
3b295bcb 2000 r = hv_vcpu_set_reg(cpu->accel->fd, HV_REG_PC, pc);
a1477da3 2001 assert_hvf_ok(r);
eb2edc42
FC		 2002
2003 /* Handle single-stepping over instructions which trigger a VM exit */
2004 if (cpu->singlestep_enabled) {
2005 ret = EXCP_DEBUG;
2006 }
a1477da3
AG		 2007 }
2008
eb2edc42 2009 return ret;
a1477da3
AG		 2010}
2011
2012static const VMStateDescription vmstate_hvf_vtimer = {
2013 .name = "hvf-vtimer",
2014 .version_id = 1,
2015 .minimum_version_id = 1,
f49986ae 2016 .fields = (const VMStateField[]) {
a1477da3
AG		 2017 VMSTATE_UINT64(vtimer_val, HVFVTimer),
2018 VMSTATE_END_OF_LIST()
2019 },
2020};
2021
2022static void hvf_vm_state_change(void *opaque, bool running, RunState state)
2023{
2024 HVFVTimer *s = opaque;
2025
2026 if (running) {
2027 /* Update vtimer offset on all CPUs */
2028 hvf_state->vtimer_offset = mach_absolute_time() - s->vtimer_val;
2029 cpu_synchronize_all_states();
2030 } else {
2031 /* Remember vtimer value on every pause */
2032 s->vtimer_val = hvf_vtimer_val_raw();
2033 }
2034}
2035
2036int hvf_arch_init(void)
2037{
2038 hvf_state->vtimer_offset = mach_absolute_time();
2039 vmstate_register(NULL, 0, &vmstate_hvf_vtimer, &vtimer);
2040 qemu_add_vm_change_state_handler(hvf_vm_state_change, &vtimer);
eb2edc42
FC		 2041
2042 hvf_arm_init_debug();
2043
a1477da3
AG		 2044 return 0;
2045}
f4152040
FC		 2046
2047static const uint32_t brk_insn = 0xd4200000;
2048
2049int hvf_arch_insert_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp)
2050{
2051 if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) ||
2052 cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk_insn, 4, 1)) {
2053 return -EINVAL;
2054 }
a1477da3
AG		 2055 return 0;
2056}
f4152040
FC		 2057
2058int hvf_arch_remove_sw_breakpoint(CPUState *cpu, struct hvf_sw_breakpoint *bp)
2059{
2060 static uint32_t brk;
2061
2062 if (cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&brk, 4, 0) ||
2063 brk != brk_insn ||
2064 cpu_memory_rw_debug(cpu, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) {
2065 return -EINVAL;
2066 }
2067 return 0;
2068}
2069
d447a624 2070int hvf_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type)
f4152040
FC		 2071{
2072 switch (type) {
2073 case GDB_BREAKPOINT_HW:
2074 return insert_hw_breakpoint(addr);
2075 case GDB_WATCHPOINT_READ:
2076 case GDB_WATCHPOINT_WRITE:
2077 case GDB_WATCHPOINT_ACCESS:
2078 return insert_hw_watchpoint(addr, len, type);
2079 default:
2080 return -ENOSYS;
2081 }
2082}
2083
d447a624 2084int hvf_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type)
f4152040
FC		 2085{
2086 switch (type) {
2087 case GDB_BREAKPOINT_HW:
2088 return delete_hw_breakpoint(addr);
2089 case GDB_WATCHPOINT_READ:
2090 case GDB_WATCHPOINT_WRITE:
2091 case GDB_WATCHPOINT_ACCESS:
2092 return delete_hw_watchpoint(addr, len, type);
2093 default:
2094 return -ENOSYS;
2095 }
2096}
2097
2098void hvf_arch_remove_all_hw_breakpoints(void)
2099{
2100 if (cur_hw_wps > 0) {
2101 g_array_remove_range(hw_watchpoints, 0, cur_hw_wps);
2102 }
2103 if (cur_hw_bps > 0) {
2104 g_array_remove_range(hw_breakpoints, 0, cur_hw_bps);
2105 }
2106}
eb2edc42
FC		 2107
2108/*
2109 * Update the vCPU with the gdbstub's view of debug registers. This view
2110 * consists of all hardware breakpoints and watchpoints inserted so far while
2111 * debugging the guest.
2112 */
2113static void hvf_put_gdbstub_debug_registers(CPUState *cpu)
2114{
2115 hv_return_t r = HV_SUCCESS;
2116 int i;
2117
2118 for (i = 0; i < cur_hw_bps; i++) {
2119 HWBreakpoint *bp = get_hw_bp(i);
3b295bcb 2120 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], bp->bcr);
eb2edc42 2121 assert_hvf_ok(r);
3b295bcb 2122 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], bp->bvr);
eb2edc42
FC		 2123 assert_hvf_ok(r);
2124 }
2125 for (i = cur_hw_bps; i < max_hw_bps; i++) {
3b295bcb 2126 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i], 0);
eb2edc42 2127 assert_hvf_ok(r);
3b295bcb 2128 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i], 0);
eb2edc42
FC		 2129 assert_hvf_ok(r);
2130 }
2131
2132 for (i = 0; i < cur_hw_wps; i++) {
2133 HWWatchpoint *wp = get_hw_wp(i);
3b295bcb 2134 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], wp->wcr);
eb2edc42 2135 assert_hvf_ok(r);
3b295bcb 2136 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], wp->wvr);
eb2edc42
FC		 2137 assert_hvf_ok(r);
2138 }
2139 for (i = cur_hw_wps; i < max_hw_wps; i++) {
3b295bcb 2140 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i], 0);
eb2edc42 2141 assert_hvf_ok(r);
3b295bcb 2142 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i], 0);
eb2edc42
FC		 2143 assert_hvf_ok(r);
2144 }
2145}
2146
2147/*
2148 * Update the vCPU with the guest's view of debug registers. This view is kept
2149 * in the environment at all times.
2150 */
2151static void hvf_put_guest_debug_registers(CPUState *cpu)
2152{
2153 ARMCPU *arm_cpu = ARM_CPU(cpu);
2154 CPUARMState *env = &arm_cpu->env;
2155 hv_return_t r = HV_SUCCESS;
2156 int i;
2157
2158 for (i = 0; i < max_hw_bps; i++) {
3b295bcb 2159 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbcr_regs[i],
eb2edc42
FC		 2160 env->cp15.dbgbcr[i]);
2161 assert_hvf_ok(r);
3b295bcb 2162 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgbvr_regs[i],
eb2edc42
FC		 2163 env->cp15.dbgbvr[i]);
2164 assert_hvf_ok(r);
2165 }
2166
2167 for (i = 0; i < max_hw_wps; i++) {
3b295bcb 2168 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwcr_regs[i],
eb2edc42
FC		 2169 env->cp15.dbgwcr[i]);
2170 assert_hvf_ok(r);
3b295bcb 2171 r = hv_vcpu_set_sys_reg(cpu->accel->fd, dbgwvr_regs[i],
eb2edc42
FC		 2172 env->cp15.dbgwvr[i]);
2173 assert_hvf_ok(r);
2174 }
2175}
2176
2177static inline bool hvf_arm_hw_debug_active(CPUState *cpu)
2178{
2179 return ((cur_hw_wps > 0) || (cur_hw_bps > 0));
2180}
2181
2182static void hvf_arch_set_traps(void)
2183{
2184 CPUState *cpu;
2185 bool should_enable_traps = false;
2186 hv_return_t r = HV_SUCCESS;
2187
2188 /* Check whether guest debugging is enabled for at least one vCPU; if it
2189 * is, enable exiting the guest on all vCPUs */
2190 CPU_FOREACH(cpu) {
3b295bcb 2191 should_enable_traps |= cpu->accel->guest_debug_enabled;
eb2edc42
FC		 2192 }
2193 CPU_FOREACH(cpu) {
2194 /* Set whether debug exceptions exit the guest */
3b295bcb 2195 r = hv_vcpu_set_trap_debug_exceptions(cpu->accel->fd,
eb2edc42
FC		 2196 should_enable_traps);
2197 assert_hvf_ok(r);
2198
2199 /* Set whether accesses to debug registers exit the guest */
3b295bcb 2200 r = hv_vcpu_set_trap_debug_reg_accesses(cpu->accel->fd,
eb2edc42
FC		 2201 should_enable_traps);
2202 assert_hvf_ok(r);
2203 }
2204}
2205
2206void hvf_arch_update_guest_debug(CPUState *cpu)
2207{
2208 ARMCPU *arm_cpu = ARM_CPU(cpu);
2209 CPUARMState *env = &arm_cpu->env;
2210
2211 /* Check whether guest debugging is enabled */
3b295bcb 2212 cpu->accel->guest_debug_enabled = cpu->singlestep_enabled ||
eb2edc42
FC		 2213 hvf_sw_breakpoints_active(cpu) ||
2214 hvf_arm_hw_debug_active(cpu);
2215
2216 /* Update debug registers */
3b295bcb 2217 if (cpu->accel->guest_debug_enabled) {
eb2edc42
FC		 2218 hvf_put_gdbstub_debug_registers(cpu);
2219 } else {
2220 hvf_put_guest_debug_registers(cpu);
2221 }
2222
2223 cpu_synchronize_state(cpu);
2224
2225 /* Enable/disable single-stepping */
2226 if (cpu->singlestep_enabled) {
2227 env->cp15.mdscr_el1 =
2228 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 1);
2229 pstate_write(env, pstate_read(env) | PSTATE_SS);
2230 } else {
2231 env->cp15.mdscr_el1 =
2232 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_SS_SHIFT, 1, 0);
2233 }
2234
2235 /* Enable/disable Breakpoint exceptions */
2236 if (hvf_arm_hw_debug_active(cpu)) {
2237 env->cp15.mdscr_el1 =
2238 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 1);
2239 } else {
2240 env->cp15.mdscr_el1 =
2241 deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 0);
2242 }
2243
2244 hvf_arch_set_traps();
2245}
2246
2247inline bool hvf_arch_supports_guest_debug(void)
2248{
2249 return true;
2250}
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