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hvf: handle access for more registers
[mirror_qemu.git] / target / arm / hvf / hvf.c
CommitLineData
a1477da3
AG		 1/*
2 * QEMU Hypervisor.framework support for Apple Silicon
3
4 * Copyright 2020 Alexander Graf <agraf@csgraf.de>
219c101f 5 * Copyright 2020 Google LLC
a1477da3
AG		 6 *
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
9 *
10 */
11
12#include "qemu/osdep.h"
a1477da3
AG		 13#include "qemu/error-report.h"
14
15#include "sysemu/runstate.h"
16#include "sysemu/hvf.h"
17#include "sysemu/hvf_int.h"
18#include "sysemu/hw_accel.h"
585df85e 19#include "hvf_arm.h"
b5fb359c 20#include "cpregs.h"
a1477da3
AG		 21
22#include <mach/mach_time.h>
23
24#include "exec/address-spaces.h"
25#include "hw/irq.h"
26#include "qemu/main-loop.h"
27#include "sysemu/cpus.h"
2c9c0bf9 28#include "arm-powerctl.h"
a1477da3
AG		 29#include "target/arm/cpu.h"
30#include "target/arm/internals.h"
31#include "trace/trace-target_arm_hvf.h"
32#include "migration/vmstate.h"
33
34#define HVF_SYSREG(crn, crm, op0, op1, op2) \
35 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
36#define PL1_WRITE_MASK 0x4
37
ad99f64f
AG		 38#define SYSREG_OP0_SHIFT 20
39#define SYSREG_OP0_MASK 0x3
40#define SYSREG_OP0(sysreg) ((sysreg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK)
41#define SYSREG_OP1_SHIFT 14
42#define SYSREG_OP1_MASK 0x7
43#define SYSREG_OP1(sysreg) ((sysreg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK)
44#define SYSREG_CRN_SHIFT 10
45#define SYSREG_CRN_MASK 0xf
46#define SYSREG_CRN(sysreg) ((sysreg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK)
47#define SYSREG_CRM_SHIFT 1
48#define SYSREG_CRM_MASK 0xf
49#define SYSREG_CRM(sysreg) ((sysreg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK)
50#define SYSREG_OP2_SHIFT 17
51#define SYSREG_OP2_MASK 0x7
52#define SYSREG_OP2(sysreg) ((sysreg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK)
53
a1477da3 54#define SYSREG(op0, op1, crn, crm, op2) \
ad99f64f
AG		 55 ((op0 << SYSREG_OP0_SHIFT) | \
56 (op1 << SYSREG_OP1_SHIFT) | \
57 (crn << SYSREG_CRN_SHIFT) | \
58 (crm << SYSREG_CRM_SHIFT) | \
59 (op2 << SYSREG_OP2_SHIFT))
60#define SYSREG_MASK \
61 SYSREG(SYSREG_OP0_MASK, \
62 SYSREG_OP1_MASK, \
63 SYSREG_CRN_MASK, \
64 SYSREG_CRM_MASK, \
65 SYSREG_OP2_MASK)
a1477da3
AG		 66#define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4)
67#define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4)
68#define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4)
69#define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1)
dd43ac07
AG		 70#define SYSREG_PMCR_EL0 SYSREG(3, 3, 9, 12, 0)
71#define SYSREG_PMUSERENR_EL0 SYSREG(3, 3, 9, 14, 0)
72#define SYSREG_PMCNTENSET_EL0 SYSREG(3, 3, 9, 12, 1)
73#define SYSREG_PMCNTENCLR_EL0 SYSREG(3, 3, 9, 12, 2)
74#define SYSREG_PMINTENCLR_EL1 SYSREG(3, 0, 9, 14, 2)
75#define SYSREG_PMOVSCLR_EL0 SYSREG(3, 3, 9, 12, 3)
76#define SYSREG_PMSWINC_EL0 SYSREG(3, 3, 9, 12, 4)
77#define SYSREG_PMSELR_EL0 SYSREG(3, 3, 9, 12, 5)
78#define SYSREG_PMCEID0_EL0 SYSREG(3, 3, 9, 12, 6)
79#define SYSREG_PMCEID1_EL0 SYSREG(3, 3, 9, 12, 7)
80#define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0)
81#define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7)
a1477da3 82
a2260983
AG		 83#define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 12, 8, 4)
84#define SYSREG_ICC_AP0R1_EL1 SYSREG(3, 0, 12, 8, 5)
85#define SYSREG_ICC_AP0R2_EL1 SYSREG(3, 0, 12, 8, 6)
86#define SYSREG_ICC_AP0R3_EL1 SYSREG(3, 0, 12, 8, 7)
87#define SYSREG_ICC_AP1R0_EL1 SYSREG(3, 0, 12, 9, 0)
88#define SYSREG_ICC_AP1R1_EL1 SYSREG(3, 0, 12, 9, 1)
89#define SYSREG_ICC_AP1R2_EL1 SYSREG(3, 0, 12, 9, 2)
90#define SYSREG_ICC_AP1R3_EL1 SYSREG(3, 0, 12, 9, 3)
91#define SYSREG_ICC_ASGI1R_EL1 SYSREG(3, 0, 12, 11, 6)
92#define SYSREG_ICC_BPR0_EL1 SYSREG(3, 0, 12, 8, 3)
93#define SYSREG_ICC_BPR1_EL1 SYSREG(3, 0, 12, 12, 3)
94#define SYSREG_ICC_CTLR_EL1 SYSREG(3, 0, 12, 12, 4)
95#define SYSREG_ICC_DIR_EL1 SYSREG(3, 0, 12, 11, 1)
96#define SYSREG_ICC_EOIR0_EL1 SYSREG(3, 0, 12, 8, 1)
97#define SYSREG_ICC_EOIR1_EL1 SYSREG(3, 0, 12, 12, 1)
98#define SYSREG_ICC_HPPIR0_EL1 SYSREG(3, 0, 12, 8, 2)
99#define SYSREG_ICC_HPPIR1_EL1 SYSREG(3, 0, 12, 12, 2)
100#define SYSREG_ICC_IAR0_EL1 SYSREG(3, 0, 12, 8, 0)
101#define SYSREG_ICC_IAR1_EL1 SYSREG(3, 0, 12, 12, 0)
102#define SYSREG_ICC_IGRPEN0_EL1 SYSREG(3, 0, 12, 12, 6)
103#define SYSREG_ICC_IGRPEN1_EL1 SYSREG(3, 0, 12, 12, 7)
104#define SYSREG_ICC_PMR_EL1 SYSREG(3, 0, 4, 6, 0)
105#define SYSREG_ICC_RPR_EL1 SYSREG(3, 0, 12, 11, 3)
106#define SYSREG_ICC_SGI0R_EL1 SYSREG(3, 0, 12, 11, 7)
107#define SYSREG_ICC_SGI1R_EL1 SYSREG(3, 0, 12, 11, 5)
108#define SYSREG_ICC_SRE_EL1 SYSREG(3, 0, 12, 12, 5)
109
ce799a04
FC		 110#define SYSREG_MDSCR_EL1 SYSREG(2, 0, 0, 2, 2)
111#define SYSREG_DBGBVR0_EL1 SYSREG(2, 0, 0, 0, 4)
112#define SYSREG_DBGBCR0_EL1 SYSREG(2, 0, 0, 0, 5)
113#define SYSREG_DBGWVR0_EL1 SYSREG(2, 0, 0, 0, 6)
114#define SYSREG_DBGWCR0_EL1 SYSREG(2, 0, 0, 0, 7)
115#define SYSREG_DBGBVR1_EL1 SYSREG(2, 0, 0, 1, 4)
116#define SYSREG_DBGBCR1_EL1 SYSREG(2, 0, 0, 1, 5)
117#define SYSREG_DBGWVR1_EL1 SYSREG(2, 0, 0, 1, 6)
118#define SYSREG_DBGWCR1_EL1 SYSREG(2, 0, 0, 1, 7)
119#define SYSREG_DBGBVR2_EL1 SYSREG(2, 0, 0, 2, 4)
120#define SYSREG_DBGBCR2_EL1 SYSREG(2, 0, 0, 2, 5)
121#define SYSREG_DBGWVR2_EL1 SYSREG(2, 0, 0, 2, 6)
122#define SYSREG_DBGWCR2_EL1 SYSREG(2, 0, 0, 2, 7)
123#define SYSREG_DBGBVR3_EL1 SYSREG(2, 0, 0, 3, 4)
124#define SYSREG_DBGBCR3_EL1 SYSREG(2, 0, 0, 3, 5)
125#define SYSREG_DBGWVR3_EL1 SYSREG(2, 0, 0, 3, 6)
126#define SYSREG_DBGWCR3_EL1 SYSREG(2, 0, 0, 3, 7)
127#define SYSREG_DBGBVR4_EL1 SYSREG(2, 0, 0, 4, 4)
128#define SYSREG_DBGBCR4_EL1 SYSREG(2, 0, 0, 4, 5)
129#define SYSREG_DBGWVR4_EL1 SYSREG(2, 0, 0, 4, 6)
130#define SYSREG_DBGWCR4_EL1 SYSREG(2, 0, 0, 4, 7)
131#define SYSREG_DBGBVR5_EL1 SYSREG(2, 0, 0, 5, 4)
132#define SYSREG_DBGBCR5_EL1 SYSREG(2, 0, 0, 5, 5)
133#define SYSREG_DBGWVR5_EL1 SYSREG(2, 0, 0, 5, 6)
134#define SYSREG_DBGWCR5_EL1 SYSREG(2, 0, 0, 5, 7)
135#define SYSREG_DBGBVR6_EL1 SYSREG(2, 0, 0, 6, 4)
136#define SYSREG_DBGBCR6_EL1 SYSREG(2, 0, 0, 6, 5)
137#define SYSREG_DBGWVR6_EL1 SYSREG(2, 0, 0, 6, 6)
138#define SYSREG_DBGWCR6_EL1 SYSREG(2, 0, 0, 6, 7)
139#define SYSREG_DBGBVR7_EL1 SYSREG(2, 0, 0, 7, 4)
140#define SYSREG_DBGBCR7_EL1 SYSREG(2, 0, 0, 7, 5)
141#define SYSREG_DBGWVR7_EL1 SYSREG(2, 0, 0, 7, 6)
142#define SYSREG_DBGWCR7_EL1 SYSREG(2, 0, 0, 7, 7)
143#define SYSREG_DBGBVR8_EL1 SYSREG(2, 0, 0, 8, 4)
144#define SYSREG_DBGBCR8_EL1 SYSREG(2, 0, 0, 8, 5)
145#define SYSREG_DBGWVR8_EL1 SYSREG(2, 0, 0, 8, 6)
146#define SYSREG_DBGWCR8_EL1 SYSREG(2, 0, 0, 8, 7)
147#define SYSREG_DBGBVR9_EL1 SYSREG(2, 0, 0, 9, 4)
148#define SYSREG_DBGBCR9_EL1 SYSREG(2, 0, 0, 9, 5)
149#define SYSREG_DBGWVR9_EL1 SYSREG(2, 0, 0, 9, 6)
150#define SYSREG_DBGWCR9_EL1 SYSREG(2, 0, 0, 9, 7)
151#define SYSREG_DBGBVR10_EL1 SYSREG(2, 0, 0, 10, 4)
152#define SYSREG_DBGBCR10_EL1 SYSREG(2, 0, 0, 10, 5)
153#define SYSREG_DBGWVR10_EL1 SYSREG(2, 0, 0, 10, 6)
154#define SYSREG_DBGWCR10_EL1 SYSREG(2, 0, 0, 10, 7)
155#define SYSREG_DBGBVR11_EL1 SYSREG(2, 0, 0, 11, 4)
156#define SYSREG_DBGBCR11_EL1 SYSREG(2, 0, 0, 11, 5)
157#define SYSREG_DBGWVR11_EL1 SYSREG(2, 0, 0, 11, 6)
158#define SYSREG_DBGWCR11_EL1 SYSREG(2, 0, 0, 11, 7)
159#define SYSREG_DBGBVR12_EL1 SYSREG(2, 0, 0, 12, 4)
160#define SYSREG_DBGBCR12_EL1 SYSREG(2, 0, 0, 12, 5)
161#define SYSREG_DBGWVR12_EL1 SYSREG(2, 0, 0, 12, 6)
162#define SYSREG_DBGWCR12_EL1 SYSREG(2, 0, 0, 12, 7)
163#define SYSREG_DBGBVR13_EL1 SYSREG(2, 0, 0, 13, 4)
164#define SYSREG_DBGBCR13_EL1 SYSREG(2, 0, 0, 13, 5)
165#define SYSREG_DBGWVR13_EL1 SYSREG(2, 0, 0, 13, 6)
166#define SYSREG_DBGWCR13_EL1 SYSREG(2, 0, 0, 13, 7)
167#define SYSREG_DBGBVR14_EL1 SYSREG(2, 0, 0, 14, 4)
168#define SYSREG_DBGBCR14_EL1 SYSREG(2, 0, 0, 14, 5)
169#define SYSREG_DBGWVR14_EL1 SYSREG(2, 0, 0, 14, 6)
170#define SYSREG_DBGWCR14_EL1 SYSREG(2, 0, 0, 14, 7)
171#define SYSREG_DBGBVR15_EL1 SYSREG(2, 0, 0, 15, 4)
172#define SYSREG_DBGBCR15_EL1 SYSREG(2, 0, 0, 15, 5)
173#define SYSREG_DBGWVR15_EL1 SYSREG(2, 0, 0, 15, 6)
174#define SYSREG_DBGWCR15_EL1 SYSREG(2, 0, 0, 15, 7)
175
a1477da3
AG		 176#define WFX_IS_WFE (1 << 0)
177
178#define TMR_CTL_ENABLE (1 << 0)
179#define TMR_CTL_IMASK (1 << 1)
180#define TMR_CTL_ISTATUS (1 << 2)
181
2c9c0bf9
AG		 182static void hvf_wfi(CPUState *cpu);
183
a1477da3
AG		 184typedef struct HVFVTimer {
185 /* Vtimer value during migration and paused state */
186 uint64_t vtimer_val;
187} HVFVTimer;
188
189static HVFVTimer vtimer;
190
585df85e
PM		 191typedef struct ARMHostCPUFeatures {
192 ARMISARegisters isar;
193 uint64_t features;
194 uint64_t midr;
195 uint32_t reset_sctlr;
196 const char *dtb_compatible;
197} ARMHostCPUFeatures;
198
199static ARMHostCPUFeatures arm_host_cpu_features;
200
a1477da3
AG		 201struct hvf_reg_match {
202 int reg;
203 uint64_t offset;
204};
205
206static const struct hvf_reg_match hvf_reg_match[] = {
207 { HV_REG_X0, offsetof(CPUARMState, xregs[0]) },
208 { HV_REG_X1, offsetof(CPUARMState, xregs[1]) },
209 { HV_REG_X2, offsetof(CPUARMState, xregs[2]) },
210 { HV_REG_X3, offsetof(CPUARMState, xregs[3]) },
211 { HV_REG_X4, offsetof(CPUARMState, xregs[4]) },
212 { HV_REG_X5, offsetof(CPUARMState, xregs[5]) },
213 { HV_REG_X6, offsetof(CPUARMState, xregs[6]) },
214 { HV_REG_X7, offsetof(CPUARMState, xregs[7]) },
215 { HV_REG_X8, offsetof(CPUARMState, xregs[8]) },
216 { HV_REG_X9, offsetof(CPUARMState, xregs[9]) },
217 { HV_REG_X10, offsetof(CPUARMState, xregs[10]) },
218 { HV_REG_X11, offsetof(CPUARMState, xregs[11]) },
219 { HV_REG_X12, offsetof(CPUARMState, xregs[12]) },
220 { HV_REG_X13, offsetof(CPUARMState, xregs[13]) },
221 { HV_REG_X14, offsetof(CPUARMState, xregs[14]) },
222 { HV_REG_X15, offsetof(CPUARMState, xregs[15]) },
223 { HV_REG_X16, offsetof(CPUARMState, xregs[16]) },
224 { HV_REG_X17, offsetof(CPUARMState, xregs[17]) },
225 { HV_REG_X18, offsetof(CPUARMState, xregs[18]) },
226 { HV_REG_X19, offsetof(CPUARMState, xregs[19]) },
227 { HV_REG_X20, offsetof(CPUARMState, xregs[20]) },
228 { HV_REG_X21, offsetof(CPUARMState, xregs[21]) },
229 { HV_REG_X22, offsetof(CPUARMState, xregs[22]) },
230 { HV_REG_X23, offsetof(CPUARMState, xregs[23]) },
231 { HV_REG_X24, offsetof(CPUARMState, xregs[24]) },
232 { HV_REG_X25, offsetof(CPUARMState, xregs[25]) },
233 { HV_REG_X26, offsetof(CPUARMState, xregs[26]) },
234 { HV_REG_X27, offsetof(CPUARMState, xregs[27]) },
235 { HV_REG_X28, offsetof(CPUARMState, xregs[28]) },
236 { HV_REG_X29, offsetof(CPUARMState, xregs[29]) },
237 { HV_REG_X30, offsetof(CPUARMState, xregs[30]) },
238 { HV_REG_PC, offsetof(CPUARMState, pc) },
239};
240
241static const struct hvf_reg_match hvf_fpreg_match[] = {
242 { HV_SIMD_FP_REG_Q0, offsetof(CPUARMState, vfp.zregs[0]) },
243 { HV_SIMD_FP_REG_Q1, offsetof(CPUARMState, vfp.zregs[1]) },
244 { HV_SIMD_FP_REG_Q2, offsetof(CPUARMState, vfp.zregs[2]) },
245 { HV_SIMD_FP_REG_Q3, offsetof(CPUARMState, vfp.zregs[3]) },
246 { HV_SIMD_FP_REG_Q4, offsetof(CPUARMState, vfp.zregs[4]) },
247 { HV_SIMD_FP_REG_Q5, offsetof(CPUARMState, vfp.zregs[5]) },
248 { HV_SIMD_FP_REG_Q6, offsetof(CPUARMState, vfp.zregs[6]) },
249 { HV_SIMD_FP_REG_Q7, offsetof(CPUARMState, vfp.zregs[7]) },
250 { HV_SIMD_FP_REG_Q8, offsetof(CPUARMState, vfp.zregs[8]) },
251 { HV_SIMD_FP_REG_Q9, offsetof(CPUARMState, vfp.zregs[9]) },
252 { HV_SIMD_FP_REG_Q10, offsetof(CPUARMState, vfp.zregs[10]) },
253 { HV_SIMD_FP_REG_Q11, offsetof(CPUARMState, vfp.zregs[11]) },
254 { HV_SIMD_FP_REG_Q12, offsetof(CPUARMState, vfp.zregs[12]) },
255 { HV_SIMD_FP_REG_Q13, offsetof(CPUARMState, vfp.zregs[13]) },
256 { HV_SIMD_FP_REG_Q14, offsetof(CPUARMState, vfp.zregs[14]) },
257 { HV_SIMD_FP_REG_Q15, offsetof(CPUARMState, vfp.zregs[15]) },
258 { HV_SIMD_FP_REG_Q16, offsetof(CPUARMState, vfp.zregs[16]) },
259 { HV_SIMD_FP_REG_Q17, offsetof(CPUARMState, vfp.zregs[17]) },
260 { HV_SIMD_FP_REG_Q18, offsetof(CPUARMState, vfp.zregs[18]) },
261 { HV_SIMD_FP_REG_Q19, offsetof(CPUARMState, vfp.zregs[19]) },
262 { HV_SIMD_FP_REG_Q20, offsetof(CPUARMState, vfp.zregs[20]) },
263 { HV_SIMD_FP_REG_Q21, offsetof(CPUARMState, vfp.zregs[21]) },
264 { HV_SIMD_FP_REG_Q22, offsetof(CPUARMState, vfp.zregs[22]) },
265 { HV_SIMD_FP_REG_Q23, offsetof(CPUARMState, vfp.zregs[23]) },
266 { HV_SIMD_FP_REG_Q24, offsetof(CPUARMState, vfp.zregs[24]) },
267 { HV_SIMD_FP_REG_Q25, offsetof(CPUARMState, vfp.zregs[25]) },
268 { HV_SIMD_FP_REG_Q26, offsetof(CPUARMState, vfp.zregs[26]) },
269 { HV_SIMD_FP_REG_Q27, offsetof(CPUARMState, vfp.zregs[27]) },
270 { HV_SIMD_FP_REG_Q28, offsetof(CPUARMState, vfp.zregs[28]) },
271 { HV_SIMD_FP_REG_Q29, offsetof(CPUARMState, vfp.zregs[29]) },
272 { HV_SIMD_FP_REG_Q30, offsetof(CPUARMState, vfp.zregs[30]) },
273 { HV_SIMD_FP_REG_Q31, offsetof(CPUARMState, vfp.zregs[31]) },
274};
275
276struct hvf_sreg_match {
277 int reg;
278 uint32_t key;
279 uint32_t cp_idx;
280};
281
282static struct hvf_sreg_match hvf_sreg_match[] = {
283 { HV_SYS_REG_DBGBVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 4) },
284 { HV_SYS_REG_DBGBCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 5) },
285 { HV_SYS_REG_DBGWVR0_EL1, HVF_SYSREG(0, 0, 14, 0, 6) },
286 { HV_SYS_REG_DBGWCR0_EL1, HVF_SYSREG(0, 0, 14, 0, 7) },
287
288 { HV_SYS_REG_DBGBVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 4) },
289 { HV_SYS_REG_DBGBCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 5) },
290 { HV_SYS_REG_DBGWVR1_EL1, HVF_SYSREG(0, 1, 14, 0, 6) },
291 { HV_SYS_REG_DBGWCR1_EL1, HVF_SYSREG(0, 1, 14, 0, 7) },
292
293 { HV_SYS_REG_DBGBVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 4) },
294 { HV_SYS_REG_DBGBCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 5) },
295 { HV_SYS_REG_DBGWVR2_EL1, HVF_SYSREG(0, 2, 14, 0, 6) },
296 { HV_SYS_REG_DBGWCR2_EL1, HVF_SYSREG(0, 2, 14, 0, 7) },
297
298 { HV_SYS_REG_DBGBVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 4) },
299 { HV_SYS_REG_DBGBCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 5) },
300 { HV_SYS_REG_DBGWVR3_EL1, HVF_SYSREG(0, 3, 14, 0, 6) },
301 { HV_SYS_REG_DBGWCR3_EL1, HVF_SYSREG(0, 3, 14, 0, 7) },
302
303 { HV_SYS_REG_DBGBVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 4) },
304 { HV_SYS_REG_DBGBCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 5) },
305 { HV_SYS_REG_DBGWVR4_EL1, HVF_SYSREG(0, 4, 14, 0, 6) },
306 { HV_SYS_REG_DBGWCR4_EL1, HVF_SYSREG(0, 4, 14, 0, 7) },
307
308 { HV_SYS_REG_DBGBVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 4) },
309 { HV_SYS_REG_DBGBCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 5) },
310 { HV_SYS_REG_DBGWVR5_EL1, HVF_SYSREG(0, 5, 14, 0, 6) },
311 { HV_SYS_REG_DBGWCR5_EL1, HVF_SYSREG(0, 5, 14, 0, 7) },
312
313 { HV_SYS_REG_DBGBVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 4) },
314 { HV_SYS_REG_DBGBCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 5) },
315 { HV_SYS_REG_DBGWVR6_EL1, HVF_SYSREG(0, 6, 14, 0, 6) },
316 { HV_SYS_REG_DBGWCR6_EL1, HVF_SYSREG(0, 6, 14, 0, 7) },
317
318 { HV_SYS_REG_DBGBVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 4) },
319 { HV_SYS_REG_DBGBCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 5) },
320 { HV_SYS_REG_DBGWVR7_EL1, HVF_SYSREG(0, 7, 14, 0, 6) },
321 { HV_SYS_REG_DBGWCR7_EL1, HVF_SYSREG(0, 7, 14, 0, 7) },
322
323 { HV_SYS_REG_DBGBVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 4) },
324 { HV_SYS_REG_DBGBCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 5) },
325 { HV_SYS_REG_DBGWVR8_EL1, HVF_SYSREG(0, 8, 14, 0, 6) },
326 { HV_SYS_REG_DBGWCR8_EL1, HVF_SYSREG(0, 8, 14, 0, 7) },
327
328 { HV_SYS_REG_DBGBVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 4) },
329 { HV_SYS_REG_DBGBCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 5) },
330 { HV_SYS_REG_DBGWVR9_EL1, HVF_SYSREG(0, 9, 14, 0, 6) },
331 { HV_SYS_REG_DBGWCR9_EL1, HVF_SYSREG(0, 9, 14, 0, 7) },
332
333 { HV_SYS_REG_DBGBVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 4) },
334 { HV_SYS_REG_DBGBCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 5) },
335 { HV_SYS_REG_DBGWVR10_EL1, HVF_SYSREG(0, 10, 14, 0, 6) },
336 { HV_SYS_REG_DBGWCR10_EL1, HVF_SYSREG(0, 10, 14, 0, 7) },
337
338 { HV_SYS_REG_DBGBVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 4) },
339 { HV_SYS_REG_DBGBCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 5) },
340 { HV_SYS_REG_DBGWVR11_EL1, HVF_SYSREG(0, 11, 14, 0, 6) },
341 { HV_SYS_REG_DBGWCR11_EL1, HVF_SYSREG(0, 11, 14, 0, 7) },
342
343 { HV_SYS_REG_DBGBVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 4) },
344 { HV_SYS_REG_DBGBCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 5) },
345 { HV_SYS_REG_DBGWVR12_EL1, HVF_SYSREG(0, 12, 14, 0, 6) },
346 { HV_SYS_REG_DBGWCR12_EL1, HVF_SYSREG(0, 12, 14, 0, 7) },
347
348 { HV_SYS_REG_DBGBVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 4) },
349 { HV_SYS_REG_DBGBCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 5) },
350 { HV_SYS_REG_DBGWVR13_EL1, HVF_SYSREG(0, 13, 14, 0, 6) },
351 { HV_SYS_REG_DBGWCR13_EL1, HVF_SYSREG(0, 13, 14, 0, 7) },
352
353 { HV_SYS_REG_DBGBVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 4) },
354 { HV_SYS_REG_DBGBCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 5) },
355 { HV_SYS_REG_DBGWVR14_EL1, HVF_SYSREG(0, 14, 14, 0, 6) },
356 { HV_SYS_REG_DBGWCR14_EL1, HVF_SYSREG(0, 14, 14, 0, 7) },
357
358 { HV_SYS_REG_DBGBVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 4) },
359 { HV_SYS_REG_DBGBCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 5) },
360 { HV_SYS_REG_DBGWVR15_EL1, HVF_SYSREG(0, 15, 14, 0, 6) },
361 { HV_SYS_REG_DBGWCR15_EL1, HVF_SYSREG(0, 15, 14, 0, 7) },
362
363#ifdef SYNC_NO_RAW_REGS
364 /*
365 * The registers below are manually synced on init because they are
366 * marked as NO_RAW. We still list them to make number space sync easier.
367 */
368 { HV_SYS_REG_MDCCINT_EL1, HVF_SYSREG(0, 2, 2, 0, 0) },
369 { HV_SYS_REG_MIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 0) },
370 { HV_SYS_REG_MPIDR_EL1, HVF_SYSREG(0, 0, 3, 0, 5) },
371 { HV_SYS_REG_ID_AA64PFR0_EL1, HVF_SYSREG(0, 4, 3, 0, 0) },
372#endif
373 { HV_SYS_REG_ID_AA64PFR1_EL1, HVF_SYSREG(0, 4, 3, 0, 2) },
374 { HV_SYS_REG_ID_AA64DFR0_EL1, HVF_SYSREG(0, 5, 3, 0, 0) },
375 { HV_SYS_REG_ID_AA64DFR1_EL1, HVF_SYSREG(0, 5, 3, 0, 1) },
376 { HV_SYS_REG_ID_AA64ISAR0_EL1, HVF_SYSREG(0, 6, 3, 0, 0) },
377 { HV_SYS_REG_ID_AA64ISAR1_EL1, HVF_SYSREG(0, 6, 3, 0, 1) },
378#ifdef SYNC_NO_MMFR0
379 /* We keep the hardware MMFR0 around. HW limits are there anyway */
380 { HV_SYS_REG_ID_AA64MMFR0_EL1, HVF_SYSREG(0, 7, 3, 0, 0) },
381#endif
382 { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) },
383 { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) },
384
385 { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) },
386 { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) },
387 { HV_SYS_REG_CPACR_EL1, HVF_SYSREG(1, 0, 3, 0, 2) },
388 { HV_SYS_REG_TTBR0_EL1, HVF_SYSREG(2, 0, 3, 0, 0) },
389 { HV_SYS_REG_TTBR1_EL1, HVF_SYSREG(2, 0, 3, 0, 1) },
390 { HV_SYS_REG_TCR_EL1, HVF_SYSREG(2, 0, 3, 0, 2) },
391
392 { HV_SYS_REG_APIAKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 0) },
393 { HV_SYS_REG_APIAKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 1) },
394 { HV_SYS_REG_APIBKEYLO_EL1, HVF_SYSREG(2, 1, 3, 0, 2) },
395 { HV_SYS_REG_APIBKEYHI_EL1, HVF_SYSREG(2, 1, 3, 0, 3) },
396 { HV_SYS_REG_APDAKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 0) },
397 { HV_SYS_REG_APDAKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 1) },
398 { HV_SYS_REG_APDBKEYLO_EL1, HVF_SYSREG(2, 2, 3, 0, 2) },
399 { HV_SYS_REG_APDBKEYHI_EL1, HVF_SYSREG(2, 2, 3, 0, 3) },
400 { HV_SYS_REG_APGAKEYLO_EL1, HVF_SYSREG(2, 3, 3, 0, 0) },
401 { HV_SYS_REG_APGAKEYHI_EL1, HVF_SYSREG(2, 3, 3, 0, 1) },
402
403 { HV_SYS_REG_SPSR_EL1, HVF_SYSREG(4, 0, 3, 0, 0) },
404 { HV_SYS_REG_ELR_EL1, HVF_SYSREG(4, 0, 3, 0, 1) },
405 { HV_SYS_REG_SP_EL0, HVF_SYSREG(4, 1, 3, 0, 0) },
406 { HV_SYS_REG_AFSR0_EL1, HVF_SYSREG(5, 1, 3, 0, 0) },
407 { HV_SYS_REG_AFSR1_EL1, HVF_SYSREG(5, 1, 3, 0, 1) },
408 { HV_SYS_REG_ESR_EL1, HVF_SYSREG(5, 2, 3, 0, 0) },
409 { HV_SYS_REG_FAR_EL1, HVF_SYSREG(6, 0, 3, 0, 0) },
410 { HV_SYS_REG_PAR_EL1, HVF_SYSREG(7, 4, 3, 0, 0) },
411 { HV_SYS_REG_MAIR_EL1, HVF_SYSREG(10, 2, 3, 0, 0) },
412 { HV_SYS_REG_AMAIR_EL1, HVF_SYSREG(10, 3, 3, 0, 0) },
413 { HV_SYS_REG_VBAR_EL1, HVF_SYSREG(12, 0, 3, 0, 0) },
414 { HV_SYS_REG_CONTEXTIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 1) },
415 { HV_SYS_REG_TPIDR_EL1, HVF_SYSREG(13, 0, 3, 0, 4) },
416 { HV_SYS_REG_CNTKCTL_EL1, HVF_SYSREG(14, 1, 3, 0, 0) },
417 { HV_SYS_REG_CSSELR_EL1, HVF_SYSREG(0, 0, 3, 2, 0) },
418 { HV_SYS_REG_TPIDR_EL0, HVF_SYSREG(13, 0, 3, 3, 2) },
419 { HV_SYS_REG_TPIDRRO_EL0, HVF_SYSREG(13, 0, 3, 3, 3) },
420 { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) },
421 { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) },
422 { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) },
423};
424
425int hvf_get_registers(CPUState *cpu)
426{
427 ARMCPU *arm_cpu = ARM_CPU(cpu);
428 CPUARMState *env = &arm_cpu->env;
429 hv_return_t ret;
430 uint64_t val;
431 hv_simd_fp_uchar16_t fpval;
432 int i;
433
434 for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) {
435 ret = hv_vcpu_get_reg(cpu->hvf->fd, hvf_reg_match[i].reg, &val);
436 *(uint64_t *)((void *)env + hvf_reg_match[i].offset) = val;
437 assert_hvf_ok(ret);
438 }
439
440 for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) {
441 ret = hv_vcpu_get_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].reg,
442 &fpval);
443 memcpy((void *)env + hvf_fpreg_match[i].offset, &fpval, sizeof(fpval));
444 assert_hvf_ok(ret);
445 }
446
447 val = 0;
448 ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPCR, &val);
449 assert_hvf_ok(ret);
450 vfp_set_fpcr(env, val);
451
452 val = 0;
453 ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_FPSR, &val);
454 assert_hvf_ok(ret);
455 vfp_set_fpsr(env, val);
456
457 ret = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_CPSR, &val);
458 assert_hvf_ok(ret);
459 pstate_write(env, val);
460
461 for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) {
462 if (hvf_sreg_match[i].cp_idx == -1) {
463 continue;
464 }
465
466 ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, &val);
467 assert_hvf_ok(ret);
468
469 arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val;
470 }
471 assert(write_list_to_cpustate(arm_cpu));
472
473 aarch64_restore_sp(env, arm_current_el(env));
474
475 return 0;
476}
477
478int hvf_put_registers(CPUState *cpu)
479{
480 ARMCPU *arm_cpu = ARM_CPU(cpu);
481 CPUARMState *env = &arm_cpu->env;
482 hv_return_t ret;
483 uint64_t val;
484 hv_simd_fp_uchar16_t fpval;
485 int i;
486
487 for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) {
488 val = *(uint64_t *)((void *)env + hvf_reg_match[i].offset);
489 ret = hv_vcpu_set_reg(cpu->hvf->fd, hvf_reg_match[i].reg, val);
490 assert_hvf_ok(ret);
491 }
492
493 for (i = 0; i < ARRAY_SIZE(hvf_fpreg_match); i++) {
494 memcpy(&fpval, (void *)env + hvf_fpreg_match[i].offset, sizeof(fpval));
495 ret = hv_vcpu_set_simd_fp_reg(cpu->hvf->fd, hvf_fpreg_match[i].reg,
496 fpval);
497 assert_hvf_ok(ret);
498 }
499
500 ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPCR, vfp_get_fpcr(env));
501 assert_hvf_ok(ret);
502
503 ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_FPSR, vfp_get_fpsr(env));
504 assert_hvf_ok(ret);
505
506 ret = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_CPSR, pstate_read(env));
507 assert_hvf_ok(ret);
508
509 aarch64_save_sp(env, arm_current_el(env));
510
511 assert(write_cpustate_to_list(arm_cpu, false));
512 for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) {
513 if (hvf_sreg_match[i].cp_idx == -1) {
514 continue;
515 }
516
517 val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx];
518 ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, val);
519 assert_hvf_ok(ret);
520 }
521
522 ret = hv_vcpu_set_vtimer_offset(cpu->hvf->fd, hvf_state->vtimer_offset);
523 assert_hvf_ok(ret);
524
525 return 0;
526}
527
528static void flush_cpu_state(CPUState *cpu)
529{
530 if (cpu->vcpu_dirty) {
531 hvf_put_registers(cpu);
532 cpu->vcpu_dirty = false;
533 }
534}
535
536static void hvf_set_reg(CPUState *cpu, int rt, uint64_t val)
537{
538 hv_return_t r;
539
540 flush_cpu_state(cpu);
541
542 if (rt < 31) {
543 r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_X0 + rt, val);
544 assert_hvf_ok(r);
545 }
546}
547
548static uint64_t hvf_get_reg(CPUState *cpu, int rt)
549{
550 uint64_t val = 0;
551 hv_return_t r;
552
553 flush_cpu_state(cpu);
554
555 if (rt < 31) {
556 r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_X0 + rt, &val);
557 assert_hvf_ok(r);
558 }
559
560 return val;
561}
562
585df85e
PM		 563static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
564{
565 ARMISARegisters host_isar = {};
566 const struct isar_regs {
567 int reg;
568 uint64_t *val;
569 } regs[] = {
570 { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 },
571 { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 },
572 { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 },
573 { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 },
574 { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 },
575 { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 },
576 { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 },
577 { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 },
578 { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 },
579 };
580 hv_vcpu_t fd;
581 hv_return_t r = HV_SUCCESS;
582 hv_vcpu_exit_t *exit;
583 int i;
584
585 ahcf->dtb_compatible = "arm,arm-v8";
586 ahcf->features = (1ULL << ARM_FEATURE_V8) |
587 (1ULL << ARM_FEATURE_NEON) |
588 (1ULL << ARM_FEATURE_AARCH64) |
589 (1ULL << ARM_FEATURE_PMU) |
590 (1ULL << ARM_FEATURE_GENERIC_TIMER);
591
592 /* We set up a small vcpu to extract host registers */
593
594 if (hv_vcpu_create(&fd, &exit, NULL) != HV_SUCCESS) {
595 return false;
596 }
597
598 for (i = 0; i < ARRAY_SIZE(regs); i++) {
599 r |= hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val);
600 }
601 r |= hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr);
602 r |= hv_vcpu_destroy(fd);
603
604 ahcf->isar = host_isar;
605
606 /*
607 * A scratch vCPU returns SCTLR 0, so let's fill our default with the M1
608 * boot SCTLR from https://github.com/AsahiLinux/m1n1/issues/97
609 */
610 ahcf->reset_sctlr = 0x30100180;
611 /*
612 * SPAN is disabled by default when SCTLR.SPAN=1. To improve compatibility,
613 * let's disable it on boot and then allow guest software to turn it on by
614 * setting it to 0.
615 */
616 ahcf->reset_sctlr |= 0x00800000;
617
618 /* Make sure we don't advertise AArch32 support for EL0/EL1 */
619 if ((host_isar.id_aa64pfr0 & 0xff) != 0x11) {
620 return false;
621 }
622
623 return r == HV_SUCCESS;
624}
625
626void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu)
627{
628 if (!arm_host_cpu_features.dtb_compatible) {
629 if (!hvf_enabled() ||
630 !hvf_arm_get_host_cpu_features(&arm_host_cpu_features)) {
631 /*
632 * We can't report this error yet, so flag that we need to
633 * in arm_cpu_realizefn().
634 */
635 cpu->host_cpu_probe_failed = true;
636 return;
637 }
638 }
639
640 cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible;
641 cpu->isar = arm_host_cpu_features.isar;
642 cpu->env.features = arm_host_cpu_features.features;
643 cpu->midr = arm_host_cpu_features.midr;
644 cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr;
645}
646
a1477da3
AG		 647void hvf_arch_vcpu_destroy(CPUState *cpu)
648{
649}
650
651int hvf_arch_init_vcpu(CPUState *cpu)
652{
653 ARMCPU *arm_cpu = ARM_CPU(cpu);
654 CPUARMState *env = &arm_cpu->env;
655 uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_match);
656 uint32_t sregs_cnt = 0;
657 uint64_t pfr;
658 hv_return_t ret;
659 int i;
660
53221552 661 env->aarch64 = true;
a1477da3
AG		 662 asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz));
663
664 /* Allocate enough space for our sysreg sync */
665 arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes,
666 sregs_match_len);
667 arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values,
668 sregs_match_len);
669 arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t,
670 arm_cpu->cpreg_vmstate_indexes,
671 sregs_match_len);
672 arm_cpu->cpreg_vmstate_values = g_renew(uint64_t,
673 arm_cpu->cpreg_vmstate_values,
674 sregs_match_len);
675
676 memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t));
677
678 /* Populate cp list for all known sysregs */
679 for (i = 0; i < sregs_match_len; i++) {
680 const ARMCPRegInfo *ri;
681 uint32_t key = hvf_sreg_match[i].key;
682
683 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);
684 if (ri) {
685 assert(!(ri->type & ARM_CP_NO_RAW));
686 hvf_sreg_match[i].cp_idx = sregs_cnt;
687 arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key);
688 } else {
689 hvf_sreg_match[i].cp_idx = -1;
690 }
691 }
692 arm_cpu->cpreg_array_len = sregs_cnt;
693 arm_cpu->cpreg_vmstate_array_len = sregs_cnt;
694
695 assert(write_cpustate_to_list(arm_cpu, false));
696
697 /* Set CP_NO_RAW system registers on init */
698 ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MIDR_EL1,
699 arm_cpu->midr);
700 assert_hvf_ok(ret);
701
702 ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_MPIDR_EL1,
703 arm_cpu->mp_affinity);
704 assert_hvf_ok(ret);
705
706 ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr);
707 assert_hvf_ok(ret);
708 pfr |= env->gicv3state ? (1 << 24) : 0;
709 ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr);
710 assert_hvf_ok(ret);
711
712 /* We're limited to underlying hardware caps, override internal versions */
713 ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_ID_AA64MMFR0_EL1,
714 &arm_cpu->isar.id_aa64mmfr0);
715 assert_hvf_ok(ret);
716
717 return 0;
718}
719
720void hvf_kick_vcpu_thread(CPUState *cpu)
721{
219c101f 722 cpus_kick_thread(cpu);
a1477da3
AG		 723 hv_vcpus_exit(&cpu->hvf->fd, 1);
724}
725
726static void hvf_raise_exception(CPUState *cpu, uint32_t excp,
727 uint32_t syndrome)
728{
729 ARMCPU *arm_cpu = ARM_CPU(cpu);
730 CPUARMState *env = &arm_cpu->env;
731
732 cpu->exception_index = excp;
733 env->exception.target_el = 1;
734 env->exception.syndrome = syndrome;
735
736 arm_cpu_do_interrupt(cpu);
737}
738
2c9c0bf9
AG		 739static void hvf_psci_cpu_off(ARMCPU *arm_cpu)
740{
741 int32_t ret = arm_set_cpu_off(arm_cpu->mp_affinity);
742 assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS);
743}
744
745/*
746 * Handle a PSCI call.
747 *
748 * Returns 0 on success
749 * -1 when the PSCI call is unknown,
750 */
751static bool hvf_handle_psci_call(CPUState *cpu)
752{
753 ARMCPU *arm_cpu = ARM_CPU(cpu);
754 CPUARMState *env = &arm_cpu->env;
755 uint64_t param[4] = {
756 env->xregs[0],
757 env->xregs[1],
758 env->xregs[2],
759 env->xregs[3]
760 };
761 uint64_t context_id, mpidr;
762 bool target_aarch64 = true;
763 CPUState *target_cpu_state;
764 ARMCPU *target_cpu;
765 target_ulong entry;
766 int target_el = 1;
767 int32_t ret = 0;
768
769 trace_hvf_psci_call(param[0], param[1], param[2], param[3],
770 arm_cpu->mp_affinity);
771
772 switch (param[0]) {
773 case QEMU_PSCI_0_2_FN_PSCI_VERSION:
0dc71c70 774 ret = QEMU_PSCI_VERSION_1_1;
2c9c0bf9
AG		 775 break;
776 case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
777 ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */
778 break;
779 case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
780 case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
781 mpidr = param[1];
782
783 switch (param[2]) {
784 case 0:
785 target_cpu_state = arm_get_cpu_by_id(mpidr);
786 if (!target_cpu_state) {
787 ret = QEMU_PSCI_RET_INVALID_PARAMS;
788 break;
789 }
790 target_cpu = ARM_CPU(target_cpu_state);
791
792 ret = target_cpu->power_state;
793 break;
794 default:
795 /* Everything above affinity level 0 is always on. */
796 ret = 0;
797 }
798 break;
799 case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
800 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
801 /*
802 * QEMU reset and shutdown are async requests, but PSCI
803 * mandates that we never return from the reset/shutdown
804 * call, so power the CPU off now so it doesn't execute
805 * anything further.
806 */
807 hvf_psci_cpu_off(arm_cpu);
808 break;
809 case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
810 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
811 hvf_psci_cpu_off(arm_cpu);
812 break;
813 case QEMU_PSCI_0_1_FN_CPU_ON:
814 case QEMU_PSCI_0_2_FN_CPU_ON:
815 case QEMU_PSCI_0_2_FN64_CPU_ON:
816 mpidr = param[1];
817 entry = param[2];
818 context_id = param[3];
819 ret = arm_set_cpu_on(mpidr, entry, context_id,
820 target_el, target_aarch64);
821 break;
822 case QEMU_PSCI_0_1_FN_CPU_OFF:
823 case QEMU_PSCI_0_2_FN_CPU_OFF:
824 hvf_psci_cpu_off(arm_cpu);
825 break;
826 case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
827 case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
828 case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
829 /* Affinity levels are not supported in QEMU */
830 if (param[1] & 0xfffe0000) {
831 ret = QEMU_PSCI_RET_INVALID_PARAMS;
832 break;
833 }
834 /* Powerdown is not supported, we always go into WFI */
835 env->xregs[0] = 0;
836 hvf_wfi(cpu);
837 break;
838 case QEMU_PSCI_0_1_FN_MIGRATE:
839 case QEMU_PSCI_0_2_FN_MIGRATE:
840 ret = QEMU_PSCI_RET_NOT_SUPPORTED;
841 break;
0dc71c70
AO		 842 case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
843 switch (param[1]) {
844 case QEMU_PSCI_0_2_FN_PSCI_VERSION:
845 case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
846 case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
847 case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
848 case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
849 case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
850 case QEMU_PSCI_0_1_FN_CPU_ON:
851 case QEMU_PSCI_0_2_FN_CPU_ON:
852 case QEMU_PSCI_0_2_FN64_CPU_ON:
853 case QEMU_PSCI_0_1_FN_CPU_OFF:
854 case QEMU_PSCI_0_2_FN_CPU_OFF:
855 case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
856 case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
857 case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
858 case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
859 ret = 0;
860 break;
861 case QEMU_PSCI_0_1_FN_MIGRATE:
862 case QEMU_PSCI_0_2_FN_MIGRATE:
863 default:
864 ret = QEMU_PSCI_RET_NOT_SUPPORTED;
865 }
866 break;
2c9c0bf9
AG		 867 default:
868 return false;
869 }
870
871 env->xregs[0] = ret;
872 return true;
873}
874
7f6c295c
AG		 875static bool is_id_sysreg(uint32_t reg)
876{
877 return SYSREG_OP0(reg) == 3 &&
878 SYSREG_OP1(reg) == 0 &&
879 SYSREG_CRN(reg) == 0 &&
880 SYSREG_CRM(reg) >= 1 &&
881 SYSREG_CRM(reg) < 8;
882}
883
a2260983
AG		 884static uint32_t hvf_reg2cp_reg(uint32_t reg)
885{
886 return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
887 (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK,
888 (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK,
889 (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK,
890 (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK,
891 (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK);
892}
893
894static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val)
895{
896 ARMCPU *arm_cpu = ARM_CPU(cpu);
897 CPUARMState *env = &arm_cpu->env;
898 const ARMCPRegInfo *ri;
899
900 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));
901 if (ri) {
902 if (ri->accessfn) {
903 if (ri->accessfn(env, ri, true) != CP_ACCESS_OK) {
904 return false;
905 }
906 }
907 if (ri->type & ARM_CP_CONST) {
908 *val = ri->resetvalue;
909 } else if (ri->readfn) {
910 *val = ri->readfn(env, ri);
911 } else {
912 *val = CPREG_FIELD64(env, ri);
913 }
914 trace_hvf_vgic_read(ri->name, *val);
915 return true;
916 }
917
918 return false;
919}
920
a1477da3
AG		 921static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
922{
923 ARMCPU *arm_cpu = ARM_CPU(cpu);
924 CPUARMState *env = &arm_cpu->env;
925 uint64_t val = 0;
926
927 switch (reg) {
928 case SYSREG_CNTPCT_EL0:
929 val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /
930 gt_cntfrq_period_ns(arm_cpu);
931 break;
dd43ac07
AG		 932 case SYSREG_PMCR_EL0:
933 val = env->cp15.c9_pmcr;
934 break;
935 case SYSREG_PMCCNTR_EL0:
936 pmu_op_start(env);
937 val = env->cp15.c15_ccnt;
938 pmu_op_finish(env);
939 break;
940 case SYSREG_PMCNTENCLR_EL0:
941 val = env->cp15.c9_pmcnten;
942 break;
943 case SYSREG_PMOVSCLR_EL0:
944 val = env->cp15.c9_pmovsr;
945 break;
946 case SYSREG_PMSELR_EL0:
947 val = env->cp15.c9_pmselr;
948 break;
949 case SYSREG_PMINTENCLR_EL1:
950 val = env->cp15.c9_pminten;
951 break;
952 case SYSREG_PMCCFILTR_EL0:
953 val = env->cp15.pmccfiltr_el0;
954 break;
955 case SYSREG_PMCNTENSET_EL0:
956 val = env->cp15.c9_pmcnten;
957 break;
958 case SYSREG_PMUSERENR_EL0:
959 val = env->cp15.c9_pmuserenr;
960 break;
961 case SYSREG_PMCEID0_EL0:
962 case SYSREG_PMCEID1_EL0:
963 /* We can't really count anything yet, declare all events invalid */
964 val = 0;
965 break;
a1477da3
AG		 966 case SYSREG_OSLSR_EL1:
967 val = env->cp15.oslsr_el1;
968 break;
969 case SYSREG_OSDLR_EL1:
970 /* Dummy register */
971 break;
a2260983
AG		 972 case SYSREG_ICC_AP0R0_EL1:
973 case SYSREG_ICC_AP0R1_EL1:
974 case SYSREG_ICC_AP0R2_EL1:
975 case SYSREG_ICC_AP0R3_EL1:
976 case SYSREG_ICC_AP1R0_EL1:
977 case SYSREG_ICC_AP1R1_EL1:
978 case SYSREG_ICC_AP1R2_EL1:
979 case SYSREG_ICC_AP1R3_EL1:
980 case SYSREG_ICC_ASGI1R_EL1:
981 case SYSREG_ICC_BPR0_EL1:
982 case SYSREG_ICC_BPR1_EL1:
983 case SYSREG_ICC_DIR_EL1:
984 case SYSREG_ICC_EOIR0_EL1:
985 case SYSREG_ICC_EOIR1_EL1:
986 case SYSREG_ICC_HPPIR0_EL1:
987 case SYSREG_ICC_HPPIR1_EL1:
988 case SYSREG_ICC_IAR0_EL1:
989 case SYSREG_ICC_IAR1_EL1:
990 case SYSREG_ICC_IGRPEN0_EL1:
991 case SYSREG_ICC_IGRPEN1_EL1:
992 case SYSREG_ICC_PMR_EL1:
993 case SYSREG_ICC_SGI0R_EL1:
994 case SYSREG_ICC_SGI1R_EL1:
995 case SYSREG_ICC_SRE_EL1:
996 case SYSREG_ICC_CTLR_EL1:
997 /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */
998 if (!hvf_sysreg_read_cp(cpu, reg, &val)) {
999 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
1000 }
1001 break;
ce799a04
FC		 1002 case SYSREG_DBGBVR0_EL1:
1003 case SYSREG_DBGBVR1_EL1:
1004 case SYSREG_DBGBVR2_EL1:
1005 case SYSREG_DBGBVR3_EL1:
1006 case SYSREG_DBGBVR4_EL1:
1007 case SYSREG_DBGBVR5_EL1:
1008 case SYSREG_DBGBVR6_EL1:
1009 case SYSREG_DBGBVR7_EL1:
1010 case SYSREG_DBGBVR8_EL1:
1011 case SYSREG_DBGBVR9_EL1:
1012 case SYSREG_DBGBVR10_EL1:
1013 case SYSREG_DBGBVR11_EL1:
1014 case SYSREG_DBGBVR12_EL1:
1015 case SYSREG_DBGBVR13_EL1:
1016 case SYSREG_DBGBVR14_EL1:
1017 case SYSREG_DBGBVR15_EL1:
1018 val = env->cp15.dbgbvr[SYSREG_CRM(reg)];
1019 break;
1020 case SYSREG_DBGBCR0_EL1:
1021 case SYSREG_DBGBCR1_EL1:
1022 case SYSREG_DBGBCR2_EL1:
1023 case SYSREG_DBGBCR3_EL1:
1024 case SYSREG_DBGBCR4_EL1:
1025 case SYSREG_DBGBCR5_EL1:
1026 case SYSREG_DBGBCR6_EL1:
1027 case SYSREG_DBGBCR7_EL1:
1028 case SYSREG_DBGBCR8_EL1:
1029 case SYSREG_DBGBCR9_EL1:
1030 case SYSREG_DBGBCR10_EL1:
1031 case SYSREG_DBGBCR11_EL1:
1032 case SYSREG_DBGBCR12_EL1:
1033 case SYSREG_DBGBCR13_EL1:
1034 case SYSREG_DBGBCR14_EL1:
1035 case SYSREG_DBGBCR15_EL1:
1036 val = env->cp15.dbgbcr[SYSREG_CRM(reg)];
1037 break;
1038 case SYSREG_DBGWVR0_EL1:
1039 case SYSREG_DBGWVR1_EL1:
1040 case SYSREG_DBGWVR2_EL1:
1041 case SYSREG_DBGWVR3_EL1:
1042 case SYSREG_DBGWVR4_EL1:
1043 case SYSREG_DBGWVR5_EL1:
1044 case SYSREG_DBGWVR6_EL1:
1045 case SYSREG_DBGWVR7_EL1:
1046 case SYSREG_DBGWVR8_EL1:
1047 case SYSREG_DBGWVR9_EL1:
1048 case SYSREG_DBGWVR10_EL1:
1049 case SYSREG_DBGWVR11_EL1:
1050 case SYSREG_DBGWVR12_EL1:
1051 case SYSREG_DBGWVR13_EL1:
1052 case SYSREG_DBGWVR14_EL1:
1053 case SYSREG_DBGWVR15_EL1:
1054 val = env->cp15.dbgwvr[SYSREG_CRM(reg)];
1055 break;
1056 case SYSREG_DBGWCR0_EL1:
1057 case SYSREG_DBGWCR1_EL1:
1058 case SYSREG_DBGWCR2_EL1:
1059 case SYSREG_DBGWCR3_EL1:
1060 case SYSREG_DBGWCR4_EL1:
1061 case SYSREG_DBGWCR5_EL1:
1062 case SYSREG_DBGWCR6_EL1:
1063 case SYSREG_DBGWCR7_EL1:
1064 case SYSREG_DBGWCR8_EL1:
1065 case SYSREG_DBGWCR9_EL1:
1066 case SYSREG_DBGWCR10_EL1:
1067 case SYSREG_DBGWCR11_EL1:
1068 case SYSREG_DBGWCR12_EL1:
1069 case SYSREG_DBGWCR13_EL1:
1070 case SYSREG_DBGWCR14_EL1:
1071 case SYSREG_DBGWCR15_EL1:
1072 val = env->cp15.dbgwcr[SYSREG_CRM(reg)];
1073 break;
a1477da3 1074 default:
7f6c295c
AG		 1075 if (is_id_sysreg(reg)) {
1076 /* ID system registers read as RES0 */
1077 val = 0;
1078 break;
1079 }
a1477da3
AG		 1080 cpu_synchronize_state(cpu);
1081 trace_hvf_unhandled_sysreg_read(env->pc, reg,
ad99f64f
AG		 1082 SYSREG_OP0(reg),
1083 SYSREG_OP1(reg),
1084 SYSREG_CRN(reg),
1085 SYSREG_CRM(reg),
1086 SYSREG_OP2(reg));
a1477da3
AG		 1087 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
1088 return 1;
1089 }
1090
1091 trace_hvf_sysreg_read(reg,
ad99f64f
AG		 1092 SYSREG_OP0(reg),
1093 SYSREG_OP1(reg),
1094 SYSREG_CRN(reg),
1095 SYSREG_CRM(reg),
1096 SYSREG_OP2(reg),
a1477da3
AG		 1097 val);
1098 hvf_set_reg(cpu, rt, val);
1099
1100 return 0;
1101}
1102
dd43ac07
AG		 1103static void pmu_update_irq(CPUARMState *env)
1104{
1105 ARMCPU *cpu = env_archcpu(env);
1106 qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) &&
1107 (env->cp15.c9_pminten & env->cp15.c9_pmovsr));
1108}
1109
1110static bool pmu_event_supported(uint16_t number)
1111{
1112 return false;
1113}
1114
1115/* Returns true if the counter (pass 31 for PMCCNTR) should count events using
1116 * the current EL, security state, and register configuration.
1117 */
1118static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
1119{
1120 uint64_t filter;
1121 bool enabled, filtered = true;
1122 int el = arm_current_el(env);
1123
1124 enabled = (env->cp15.c9_pmcr & PMCRE) &&
1125 (env->cp15.c9_pmcnten & (1 << counter));
1126
1127 if (counter == 31) {
1128 filter = env->cp15.pmccfiltr_el0;
1129 } else {
1130 filter = env->cp15.c14_pmevtyper[counter];
1131 }
1132
1133 if (el == 0) {
1134 filtered = filter & PMXEVTYPER_U;
1135 } else if (el == 1) {
1136 filtered = filter & PMXEVTYPER_P;
1137 }
1138
1139 if (counter != 31) {
1140 /*
1141 * If not checking PMCCNTR, ensure the counter is setup to an event we
1142 * support
1143 */
1144 uint16_t event = filter & PMXEVTYPER_EVTCOUNT;
1145 if (!pmu_event_supported(event)) {
1146 return false;
1147 }
1148 }
1149
1150 return enabled && !filtered;
1151}
1152
1153static void pmswinc_write(CPUARMState *env, uint64_t value)
1154{
1155 unsigned int i;
1156 for (i = 0; i < pmu_num_counters(env); i++) {
1157 /* Increment a counter's count iff: */
1158 if ((value & (1 << i)) && /* counter's bit is set */
1159 /* counter is enabled and not filtered */
1160 pmu_counter_enabled(env, i) &&
1161 /* counter is SW_INCR */
1162 (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) {
1163 /*
1164 * Detect if this write causes an overflow since we can't predict
1165 * PMSWINC overflows like we can for other events
1166 */
1167 uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1;
1168
1169 if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) {
1170 env->cp15.c9_pmovsr |= (1 << i);
1171 pmu_update_irq(env);
1172 }
1173
1174 env->cp15.c14_pmevcntr[i] = new_pmswinc;
1175 }
1176 }
1177}
1178
a2260983
AG		 1179static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val)
1180{
1181 ARMCPU *arm_cpu = ARM_CPU(cpu);
1182 CPUARMState *env = &arm_cpu->env;
1183 const ARMCPRegInfo *ri;
1184
1185 ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));
1186
1187 if (ri) {
1188 if (ri->accessfn) {
1189 if (ri->accessfn(env, ri, false) != CP_ACCESS_OK) {
1190 return false;
1191 }
1192 }
1193 if (ri->writefn) {
1194 ri->writefn(env, ri, val);
1195 } else {
1196 CPREG_FIELD64(env, ri) = val;
1197 }
1198
1199 trace_hvf_vgic_write(ri->name, val);
1200 return true;
1201 }
1202
1203 return false;
1204}
1205
a1477da3
AG		 1206static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
1207{
1208 ARMCPU *arm_cpu = ARM_CPU(cpu);
1209 CPUARMState *env = &arm_cpu->env;
1210
1211 trace_hvf_sysreg_write(reg,
ad99f64f
AG		 1212 SYSREG_OP0(reg),
1213 SYSREG_OP1(reg),
1214 SYSREG_CRN(reg),
1215 SYSREG_CRM(reg),
1216 SYSREG_OP2(reg),
a1477da3
AG		 1217 val);
1218
1219 switch (reg) {
dd43ac07
AG		 1220 case SYSREG_PMCCNTR_EL0:
1221 pmu_op_start(env);
1222 env->cp15.c15_ccnt = val;
1223 pmu_op_finish(env);
1224 break;
1225 case SYSREG_PMCR_EL0:
1226 pmu_op_start(env);
1227
1228 if (val & PMCRC) {
1229 /* The counter has been reset */
1230 env->cp15.c15_ccnt = 0;
1231 }
1232
1233 if (val & PMCRP) {
1234 unsigned int i;
1235 for (i = 0; i < pmu_num_counters(env); i++) {
1236 env->cp15.c14_pmevcntr[i] = 0;
1237 }
1238 }
1239
9323e79f
PM		 1240 env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK;
1241 env->cp15.c9_pmcr |= (val & PMCR_WRITABLE_MASK);
dd43ac07
AG		 1242
1243 pmu_op_finish(env);
1244 break;
1245 case SYSREG_PMUSERENR_EL0:
1246 env->cp15.c9_pmuserenr = val & 0xf;
1247 break;
1248 case SYSREG_PMCNTENSET_EL0:
1249 env->cp15.c9_pmcnten |= (val & pmu_counter_mask(env));
1250 break;
1251 case SYSREG_PMCNTENCLR_EL0:
1252 env->cp15.c9_pmcnten &= ~(val & pmu_counter_mask(env));
1253 break;
1254 case SYSREG_PMINTENCLR_EL1:
1255 pmu_op_start(env);
1256 env->cp15.c9_pminten |= val;
1257 pmu_op_finish(env);
1258 break;
1259 case SYSREG_PMOVSCLR_EL0:
1260 pmu_op_start(env);
1261 env->cp15.c9_pmovsr &= ~val;
1262 pmu_op_finish(env);
1263 break;
1264 case SYSREG_PMSWINC_EL0:
1265 pmu_op_start(env);
1266 pmswinc_write(env, val);
1267 pmu_op_finish(env);
1268 break;
1269 case SYSREG_PMSELR_EL0:
1270 env->cp15.c9_pmselr = val & 0x1f;
1271 break;
1272 case SYSREG_PMCCFILTR_EL0:
1273 pmu_op_start(env);
1274 env->cp15.pmccfiltr_el0 = val & PMCCFILTR_EL0;
1275 pmu_op_finish(env);
1276 break;
a1477da3
AG		 1277 case SYSREG_OSLAR_EL1:
1278 env->cp15.oslsr_el1 = val & 1;
1279 break;
1280 case SYSREG_OSDLR_EL1:
1281 /* Dummy register */
1282 break;
a2260983
AG		 1283 case SYSREG_ICC_AP0R0_EL1:
1284 case SYSREG_ICC_AP0R1_EL1:
1285 case SYSREG_ICC_AP0R2_EL1:
1286 case SYSREG_ICC_AP0R3_EL1:
1287 case SYSREG_ICC_AP1R0_EL1:
1288 case SYSREG_ICC_AP1R1_EL1:
1289 case SYSREG_ICC_AP1R2_EL1:
1290 case SYSREG_ICC_AP1R3_EL1:
1291 case SYSREG_ICC_ASGI1R_EL1:
1292 case SYSREG_ICC_BPR0_EL1:
1293 case SYSREG_ICC_BPR1_EL1:
1294 case SYSREG_ICC_CTLR_EL1:
1295 case SYSREG_ICC_DIR_EL1:
1296 case SYSREG_ICC_EOIR0_EL1:
1297 case SYSREG_ICC_EOIR1_EL1:
1298 case SYSREG_ICC_HPPIR0_EL1:
1299 case SYSREG_ICC_HPPIR1_EL1:
1300 case SYSREG_ICC_IAR0_EL1:
1301 case SYSREG_ICC_IAR1_EL1:
1302 case SYSREG_ICC_IGRPEN0_EL1:
1303 case SYSREG_ICC_IGRPEN1_EL1:
1304 case SYSREG_ICC_PMR_EL1:
1305 case SYSREG_ICC_SGI0R_EL1:
1306 case SYSREG_ICC_SGI1R_EL1:
1307 case SYSREG_ICC_SRE_EL1:
1308 /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */
1309 if (!hvf_sysreg_write_cp(cpu, reg, val)) {
1310 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
1311 }
1312 break;
ce799a04
FC		 1313 case SYSREG_MDSCR_EL1:
1314 env->cp15.mdscr_el1 = val;
1315 break;
1316 case SYSREG_DBGBVR0_EL1:
1317 case SYSREG_DBGBVR1_EL1:
1318 case SYSREG_DBGBVR2_EL1:
1319 case SYSREG_DBGBVR3_EL1:
1320 case SYSREG_DBGBVR4_EL1:
1321 case SYSREG_DBGBVR5_EL1:
1322 case SYSREG_DBGBVR6_EL1:
1323 case SYSREG_DBGBVR7_EL1:
1324 case SYSREG_DBGBVR8_EL1:
1325 case SYSREG_DBGBVR9_EL1:
1326 case SYSREG_DBGBVR10_EL1:
1327 case SYSREG_DBGBVR11_EL1:
1328 case SYSREG_DBGBVR12_EL1:
1329 case SYSREG_DBGBVR13_EL1:
1330 case SYSREG_DBGBVR14_EL1:
1331 case SYSREG_DBGBVR15_EL1:
1332 env->cp15.dbgbvr[SYSREG_CRM(reg)] = val;
1333 break;
1334 case SYSREG_DBGBCR0_EL1:
1335 case SYSREG_DBGBCR1_EL1:
1336 case SYSREG_DBGBCR2_EL1:
1337 case SYSREG_DBGBCR3_EL1:
1338 case SYSREG_DBGBCR4_EL1:
1339 case SYSREG_DBGBCR5_EL1:
1340 case SYSREG_DBGBCR6_EL1:
1341 case SYSREG_DBGBCR7_EL1:
1342 case SYSREG_DBGBCR8_EL1:
1343 case SYSREG_DBGBCR9_EL1:
1344 case SYSREG_DBGBCR10_EL1:
1345 case SYSREG_DBGBCR11_EL1:
1346 case SYSREG_DBGBCR12_EL1:
1347 case SYSREG_DBGBCR13_EL1:
1348 case SYSREG_DBGBCR14_EL1:
1349 case SYSREG_DBGBCR15_EL1:
1350 env->cp15.dbgbcr[SYSREG_CRM(reg)] = val;
1351 break;
1352 case SYSREG_DBGWVR0_EL1:
1353 case SYSREG_DBGWVR1_EL1:
1354 case SYSREG_DBGWVR2_EL1:
1355 case SYSREG_DBGWVR3_EL1:
1356 case SYSREG_DBGWVR4_EL1:
1357 case SYSREG_DBGWVR5_EL1:
1358 case SYSREG_DBGWVR6_EL1:
1359 case SYSREG_DBGWVR7_EL1:
1360 case SYSREG_DBGWVR8_EL1:
1361 case SYSREG_DBGWVR9_EL1:
1362 case SYSREG_DBGWVR10_EL1:
1363 case SYSREG_DBGWVR11_EL1:
1364 case SYSREG_DBGWVR12_EL1:
1365 case SYSREG_DBGWVR13_EL1:
1366 case SYSREG_DBGWVR14_EL1:
1367 case SYSREG_DBGWVR15_EL1:
1368 env->cp15.dbgwvr[SYSREG_CRM(reg)] = val;
1369 break;
1370 case SYSREG_DBGWCR0_EL1:
1371 case SYSREG_DBGWCR1_EL1:
1372 case SYSREG_DBGWCR2_EL1:
1373 case SYSREG_DBGWCR3_EL1:
1374 case SYSREG_DBGWCR4_EL1:
1375 case SYSREG_DBGWCR5_EL1:
1376 case SYSREG_DBGWCR6_EL1:
1377 case SYSREG_DBGWCR7_EL1:
1378 case SYSREG_DBGWCR8_EL1:
1379 case SYSREG_DBGWCR9_EL1:
1380 case SYSREG_DBGWCR10_EL1:
1381 case SYSREG_DBGWCR11_EL1:
1382 case SYSREG_DBGWCR12_EL1:
1383 case SYSREG_DBGWCR13_EL1:
1384 case SYSREG_DBGWCR14_EL1:
1385 case SYSREG_DBGWCR15_EL1:
1386 env->cp15.dbgwcr[SYSREG_CRM(reg)] = val;
1387 break;
a1477da3
AG		 1388 default:
1389 cpu_synchronize_state(cpu);
1390 trace_hvf_unhandled_sysreg_write(env->pc, reg,
ad99f64f
AG		 1391 SYSREG_OP0(reg),
1392 SYSREG_OP1(reg),
1393 SYSREG_CRN(reg),
1394 SYSREG_CRM(reg),
1395 SYSREG_OP2(reg));
a1477da3
AG		 1396 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
1397 return 1;
1398 }
1399
1400 return 0;
1401}
1402
1403static int hvf_inject_interrupts(CPUState *cpu)
1404{
1405 if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) {
1406 trace_hvf_inject_fiq();
1407 hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_FIQ,
1408 true);
1409 }
1410
1411 if (cpu->interrupt_request & CPU_INTERRUPT_HARD) {
1412 trace_hvf_inject_irq();
1413 hv_vcpu_set_pending_interrupt(cpu->hvf->fd, HV_INTERRUPT_TYPE_IRQ,
1414 true);
1415 }
1416
1417 return 0;
1418}
1419
1420static uint64_t hvf_vtimer_val_raw(void)
1421{
1422 /*
1423 * mach_absolute_time() returns the vtimer value without the VM
1424 * offset that we define. Add our own offset on top.
1425 */
1426 return mach_absolute_time() - hvf_state->vtimer_offset;
1427}
1428
219c101f
PC		 1429static uint64_t hvf_vtimer_val(void)
1430{
1431 if (!runstate_is_running()) {
1432 /* VM is paused, the vtimer value is in vtimer.vtimer_val */
1433 return vtimer.vtimer_val;
1434 }
1435
1436 return hvf_vtimer_val_raw();
1437}
1438
1439static void hvf_wait_for_ipi(CPUState *cpu, struct timespec *ts)
1440{
1441 /*
1442 * Use pselect to sleep so that other threads can IPI us while we're
1443 * sleeping.
1444 */
1445 qatomic_mb_set(&cpu->thread_kicked, false);
1446 qemu_mutex_unlock_iothread();
1447 pselect(0, 0, 0, 0, ts, &cpu->hvf->unblock_ipi_mask);
1448 qemu_mutex_lock_iothread();
1449}
1450
1451static void hvf_wfi(CPUState *cpu)
1452{
1453 ARMCPU *arm_cpu = ARM_CPU(cpu);
1454 struct timespec ts;
1455 hv_return_t r;
1456 uint64_t ctl;
1457 uint64_t cval;
1458 int64_t ticks_to_sleep;
1459 uint64_t seconds;
1460 uint64_t nanos;
1461 uint32_t cntfrq;
1462
1463 if (cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ)) {
1464 /* Interrupt pending, no need to wait */
1465 return;
1466 }
1467
1468 r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl);
1469 assert_hvf_ok(r);
1470
1471 if (!(ctl & 1) || (ctl & 2)) {
1472 /* Timer disabled or masked, just wait for an IPI. */
1473 hvf_wait_for_ipi(cpu, NULL);
1474 return;
1475 }
1476
1477 r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CVAL_EL0, &cval);
1478 assert_hvf_ok(r);
1479
1480 ticks_to_sleep = cval - hvf_vtimer_val();
1481 if (ticks_to_sleep < 0) {
1482 return;
1483 }
1484
1485 cntfrq = gt_cntfrq_period_ns(arm_cpu);
1486 seconds = muldiv64(ticks_to_sleep, cntfrq, NANOSECONDS_PER_SECOND);
1487 ticks_to_sleep -= muldiv64(seconds, NANOSECONDS_PER_SECOND, cntfrq);
1488 nanos = ticks_to_sleep * cntfrq;
1489
1490 /*
1491 * Don't sleep for less than the time a context switch would take,
1492 * so that we can satisfy fast timer requests on the same CPU.
1493 * Measurements on M1 show the sweet spot to be ~2ms.
1494 */
1495 if (!seconds && nanos < (2 * SCALE_MS)) {
1496 return;
1497 }
1498
1499 ts = (struct timespec) { seconds, nanos };
1500 hvf_wait_for_ipi(cpu, &ts);
1501}
1502
a1477da3
AG		 1503static void hvf_sync_vtimer(CPUState *cpu)
1504{
1505 ARMCPU *arm_cpu = ARM_CPU(cpu);
1506 hv_return_t r;
1507 uint64_t ctl;
1508 bool irq_state;
1509
1510 if (!cpu->hvf->vtimer_masked) {
1511 /* We will get notified on vtimer changes by hvf, nothing to do */
1512 return;
1513 }
1514
1515 r = hv_vcpu_get_sys_reg(cpu->hvf->fd, HV_SYS_REG_CNTV_CTL_EL0, &ctl);
1516 assert_hvf_ok(r);
1517
1518 irq_state = (ctl & (TMR_CTL_ENABLE | TMR_CTL_IMASK | TMR_CTL_ISTATUS)) ==
1519 (TMR_CTL_ENABLE | TMR_CTL_ISTATUS);
1520 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], irq_state);
1521
1522 if (!irq_state) {
1523 /* Timer no longer asserting, we can unmask it */
1524 hv_vcpu_set_vtimer_mask(cpu->hvf->fd, false);
1525 cpu->hvf->vtimer_masked = false;
1526 }
1527}
1528
1529int hvf_vcpu_exec(CPUState *cpu)
1530{
1531 ARMCPU *arm_cpu = ARM_CPU(cpu);
1532 CPUARMState *env = &arm_cpu->env;
1533 hv_vcpu_exit_t *hvf_exit = cpu->hvf->exit;
1534 hv_return_t r;
1535 bool advance_pc = false;
1536
1537 if (hvf_inject_interrupts(cpu)) {
1538 return EXCP_INTERRUPT;
1539 }
1540
1541 if (cpu->halted) {
1542 return EXCP_HLT;
1543 }
1544
1545 flush_cpu_state(cpu);
1546
1547 qemu_mutex_unlock_iothread();
1548 assert_hvf_ok(hv_vcpu_run(cpu->hvf->fd));
1549
1550 /* handle VMEXIT */
1551 uint64_t exit_reason = hvf_exit->reason;
1552 uint64_t syndrome = hvf_exit->exception.syndrome;
1553 uint32_t ec = syn_get_ec(syndrome);
1554
1555 qemu_mutex_lock_iothread();
1556 switch (exit_reason) {
1557 case HV_EXIT_REASON_EXCEPTION:
1558 /* This is the main one, handle below. */
1559 break;
1560 case HV_EXIT_REASON_VTIMER_ACTIVATED:
1561 qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 1);
1562 cpu->hvf->vtimer_masked = true;
1563 return 0;
1564 case HV_EXIT_REASON_CANCELED:
1565 /* we got kicked, no exit to process */
1566 return 0;
1567 default:
d385a605 1568 g_assert_not_reached();
a1477da3
AG		 1569 }
1570
1571 hvf_sync_vtimer(cpu);
1572
1573 switch (ec) {
1574 case EC_DATAABORT: {
1575 bool isv = syndrome & ARM_EL_ISV;
1576 bool iswrite = (syndrome >> 6) & 1;
1577 bool s1ptw = (syndrome >> 7) & 1;
1578 uint32_t sas = (syndrome >> 22) & 3;
1579 uint32_t len = 1 << sas;
1580 uint32_t srt = (syndrome >> 16) & 0x1f;
5fd6a3e2 1581 uint32_t cm = (syndrome >> 8) & 0x1;
a1477da3
AG		 1582 uint64_t val = 0;
1583
1584 trace_hvf_data_abort(env->pc, hvf_exit->exception.virtual_address,
1585 hvf_exit->exception.physical_address, isv,
1586 iswrite, s1ptw, len, srt);
1587
5fd6a3e2
AG		 1588 if (cm) {
1589 /* We don't cache MMIO regions */
1590 advance_pc = true;
1591 break;
1592 }
1593
a1477da3
AG		 1594 assert(isv);
1595
1596 if (iswrite) {
1597 val = hvf_get_reg(cpu, srt);
1598 address_space_write(&address_space_memory,
1599 hvf_exit->exception.physical_address,
1600 MEMTXATTRS_UNSPECIFIED, &val, len);
1601 } else {
1602 address_space_read(&address_space_memory,
1603 hvf_exit->exception.physical_address,
1604 MEMTXATTRS_UNSPECIFIED, &val, len);
1605 hvf_set_reg(cpu, srt, val);
1606 }
1607
1608 advance_pc = true;
1609 break;
1610 }
1611 case EC_SYSTEMREGISTERTRAP: {
1612 bool isread = (syndrome >> 0) & 1;
1613 uint32_t rt = (syndrome >> 5) & 0x1f;
1614 uint32_t reg = syndrome & SYSREG_MASK;
1615 uint64_t val;
1616 int ret = 0;
1617
1618 if (isread) {
1619 ret = hvf_sysreg_read(cpu, reg, rt);
1620 } else {
1621 val = hvf_get_reg(cpu, rt);
1622 ret = hvf_sysreg_write(cpu, reg, val);
1623 }
1624
1625 advance_pc = !ret;
1626 break;
1627 }
1628 case EC_WFX_TRAP:
1629 advance_pc = true;
219c101f
PC		 1630 if (!(syndrome & WFX_IS_WFE)) {
1631 hvf_wfi(cpu);
1632 }
a1477da3
AG		 1633 break;
1634 case EC_AA64_HVC:
1635 cpu_synchronize_state(cpu);
2c9c0bf9
AG		 1636 if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_HVC) {
1637 if (!hvf_handle_psci_call(cpu)) {
1638 trace_hvf_unknown_hvc(env->xregs[0]);
1639 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */
1640 env->xregs[0] = -1;
1641 }
1642 } else {
1643 trace_hvf_unknown_hvc(env->xregs[0]);
1644 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
1645 }
a1477da3
AG		 1646 break;
1647 case EC_AA64_SMC:
1648 cpu_synchronize_state(cpu);
2c9c0bf9
AG		 1649 if (arm_cpu->psci_conduit == QEMU_PSCI_CONDUIT_SMC) {
1650 advance_pc = true;
1651
1652 if (!hvf_handle_psci_call(cpu)) {
1653 trace_hvf_unknown_smc(env->xregs[0]);
1654 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */
1655 env->xregs[0] = -1;
1656 }
1657 } else {
1658 trace_hvf_unknown_smc(env->xregs[0]);
1659 hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
1660 }
a1477da3
AG		 1661 break;
1662 default:
1663 cpu_synchronize_state(cpu);
1664 trace_hvf_exit(syndrome, ec, env->pc);
1665 error_report("0x%llx: unhandled exception ec=0x%x", env->pc, ec);
1666 }
1667
1668 if (advance_pc) {
1669 uint64_t pc;
1670
1671 flush_cpu_state(cpu);
1672
1673 r = hv_vcpu_get_reg(cpu->hvf->fd, HV_REG_PC, &pc);
1674 assert_hvf_ok(r);
1675 pc += 4;
1676 r = hv_vcpu_set_reg(cpu->hvf->fd, HV_REG_PC, pc);
1677 assert_hvf_ok(r);
1678 }
1679
1680 return 0;
1681}
1682
1683static const VMStateDescription vmstate_hvf_vtimer = {
1684 .name = "hvf-vtimer",
1685 .version_id = 1,
1686 .minimum_version_id = 1,
1687 .fields = (VMStateField[]) {
1688 VMSTATE_UINT64(vtimer_val, HVFVTimer),
1689 VMSTATE_END_OF_LIST()
1690 },
1691};
1692
1693static void hvf_vm_state_change(void *opaque, bool running, RunState state)
1694{
1695 HVFVTimer *s = opaque;
1696
1697 if (running) {
1698 /* Update vtimer offset on all CPUs */
1699 hvf_state->vtimer_offset = mach_absolute_time() - s->vtimer_val;
1700 cpu_synchronize_all_states();
1701 } else {
1702 /* Remember vtimer value on every pause */
1703 s->vtimer_val = hvf_vtimer_val_raw();
1704 }
1705}
1706
1707int hvf_arch_init(void)
1708{
1709 hvf_state->vtimer_offset = mach_absolute_time();
1710 vmstate_register(NULL, 0, &vmstate_hvf_vtimer, &vtimer);
1711 qemu_add_vm_change_state_handler(hvf_vm_state_change, &vtimer);
1712 return 0;
1713}
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