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ccd38087 PM |
1 | /* |
2 | * QEMU ARM CPU -- internal functions and types | |
3 | * | |
4 | * Copyright (c) 2014 Linaro Ltd | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | * | |
20 | * This header defines functions, types, etc which need to be shared | |
fcf5ef2a | 21 | * between different source files within target/arm/ but which are |
ccd38087 PM |
22 | * private to it and not required by the rest of QEMU. |
23 | */ | |
24 | ||
25 | #ifndef TARGET_ARM_INTERNALS_H | |
26 | #define TARGET_ARM_INTERNALS_H | |
27 | ||
abc24d86 MD |
28 | #include "hw/registerfields.h" |
29 | ||
99a99c1f SB |
30 | /* register banks for CPU modes */ |
31 | #define BANK_USRSYS 0 | |
32 | #define BANK_SVC 1 | |
33 | #define BANK_ABT 2 | |
34 | #define BANK_UND 3 | |
35 | #define BANK_IRQ 4 | |
36 | #define BANK_FIQ 5 | |
37 | #define BANK_HYP 6 | |
38 | #define BANK_MON 7 | |
39 | ||
d4a2dc67 PM |
40 | static inline bool excp_is_internal(int excp) |
41 | { | |
42 | /* Return true if this exception number represents a QEMU-internal | |
43 | * exception that will not be passed to the guest. | |
44 | */ | |
45 | return excp == EXCP_INTERRUPT | |
46 | || excp == EXCP_HLT | |
47 | || excp == EXCP_DEBUG | |
48 | || excp == EXCP_HALTED | |
49 | || excp == EXCP_EXCEPTION_EXIT | |
50 | || excp == EXCP_KERNEL_TRAP | |
05188cc7 | 51 | || excp == EXCP_SEMIHOST; |
d4a2dc67 PM |
52 | } |
53 | ||
ccd38087 PM |
54 | /* Scale factor for generic timers, ie number of ns per tick. |
55 | * This gives a 62.5MHz timer. | |
56 | */ | |
57 | #define GTIMER_SCALE 16 | |
58 | ||
abc24d86 MD |
59 | /* Bit definitions for the v7M CONTROL register */ |
60 | FIELD(V7M_CONTROL, NPRIV, 0, 1) | |
61 | FIELD(V7M_CONTROL, SPSEL, 1, 1) | |
62 | FIELD(V7M_CONTROL, FPCA, 2, 1) | |
3e3fa230 | 63 | FIELD(V7M_CONTROL, SFPA, 3, 1) |
abc24d86 | 64 | |
4d1e7a47 PM |
65 | /* Bit definitions for v7M exception return payload */ |
66 | FIELD(V7M_EXCRET, ES, 0, 1) | |
67 | FIELD(V7M_EXCRET, RES0, 1, 1) | |
68 | FIELD(V7M_EXCRET, SPSEL, 2, 1) | |
69 | FIELD(V7M_EXCRET, MODE, 3, 1) | |
70 | FIELD(V7M_EXCRET, FTYPE, 4, 1) | |
71 | FIELD(V7M_EXCRET, DCRS, 5, 1) | |
72 | FIELD(V7M_EXCRET, S, 6, 1) | |
73 | FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ | |
74 | ||
d02a8698 PM |
75 | /* Minimum value which is a magic number for exception return */ |
76 | #define EXC_RETURN_MIN_MAGIC 0xff000000 | |
77 | /* Minimum number which is a magic number for function or exception return | |
78 | * when using v8M security extension | |
79 | */ | |
80 | #define FNC_RETURN_MIN_MAGIC 0xfefffffe | |
81 | ||
35337cc3 PM |
82 | /* We use a few fake FSR values for internal purposes in M profile. |
83 | * M profile cores don't have A/R format FSRs, but currently our | |
84 | * get_phys_addr() code assumes A/R profile and reports failures via | |
85 | * an A/R format FSR value. We then translate that into the proper | |
86 | * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt(). | |
87 | * Mostly the FSR values we use for this are those defined for v7PMSA, | |
88 | * since we share some of that codepath. A few kinds of fault are | |
89 | * only for M profile and have no A/R equivalent, though, so we have | |
90 | * to pick a value from the reserved range (which we never otherwise | |
91 | * generate) to use for these. | |
92 | * These values will never be visible to the guest. | |
93 | */ | |
94 | #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */ | |
95 | #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */ | |
96 | ||
2a923c4d EI |
97 | /* |
98 | * For AArch64, map a given EL to an index in the banked_spsr array. | |
7847f9ea PM |
99 | * Note that this mapping and the AArch32 mapping defined in bank_number() |
100 | * must agree such that the AArch64<->AArch32 SPSRs have the architecturally | |
101 | * mandated mapping between each other. | |
2a923c4d EI |
102 | */ |
103 | static inline unsigned int aarch64_banked_spsr_index(unsigned int el) | |
104 | { | |
105 | static const unsigned int map[4] = { | |
99a99c1f SB |
106 | [1] = BANK_SVC, /* EL1. */ |
107 | [2] = BANK_HYP, /* EL2. */ | |
108 | [3] = BANK_MON, /* EL3. */ | |
2a923c4d EI |
109 | }; |
110 | assert(el >= 1 && el <= 3); | |
111 | return map[el]; | |
112 | } | |
113 | ||
c766568d PM |
114 | /* Map CPU modes onto saved register banks. */ |
115 | static inline int bank_number(int mode) | |
116 | { | |
117 | switch (mode) { | |
118 | case ARM_CPU_MODE_USR: | |
119 | case ARM_CPU_MODE_SYS: | |
120 | return BANK_USRSYS; | |
121 | case ARM_CPU_MODE_SVC: | |
122 | return BANK_SVC; | |
123 | case ARM_CPU_MODE_ABT: | |
124 | return BANK_ABT; | |
125 | case ARM_CPU_MODE_UND: | |
126 | return BANK_UND; | |
127 | case ARM_CPU_MODE_IRQ: | |
128 | return BANK_IRQ; | |
129 | case ARM_CPU_MODE_FIQ: | |
130 | return BANK_FIQ; | |
131 | case ARM_CPU_MODE_HYP: | |
132 | return BANK_HYP; | |
133 | case ARM_CPU_MODE_MON: | |
134 | return BANK_MON; | |
135 | } | |
136 | g_assert_not_reached(); | |
137 | } | |
138 | ||
ccd38087 PM |
139 | void switch_mode(CPUARMState *, int); |
140 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); | |
141 | void arm_translate_init(void); | |
142 | ||
143 | enum arm_fprounding { | |
144 | FPROUNDING_TIEEVEN, | |
145 | FPROUNDING_POSINF, | |
146 | FPROUNDING_NEGINF, | |
147 | FPROUNDING_ZERO, | |
148 | FPROUNDING_TIEAWAY, | |
149 | FPROUNDING_ODD | |
150 | }; | |
151 | ||
152 | int arm_rmode_to_sf(int rmode); | |
153 | ||
9208b961 EI |
154 | static inline void aarch64_save_sp(CPUARMState *env, int el) |
155 | { | |
156 | if (env->pstate & PSTATE_SP) { | |
157 | env->sp_el[el] = env->xregs[31]; | |
158 | } else { | |
159 | env->sp_el[0] = env->xregs[31]; | |
160 | } | |
161 | } | |
162 | ||
163 | static inline void aarch64_restore_sp(CPUARMState *env, int el) | |
164 | { | |
165 | if (env->pstate & PSTATE_SP) { | |
166 | env->xregs[31] = env->sp_el[el]; | |
167 | } else { | |
168 | env->xregs[31] = env->sp_el[0]; | |
169 | } | |
170 | } | |
171 | ||
f502cfc2 PM |
172 | static inline void update_spsel(CPUARMState *env, uint32_t imm) |
173 | { | |
dcbff19b | 174 | unsigned int cur_el = arm_current_el(env); |
f502cfc2 PM |
175 | /* Update PSTATE SPSel bit; this requires us to update the |
176 | * working stack pointer in xregs[31]. | |
177 | */ | |
178 | if (!((imm ^ env->pstate) & PSTATE_SP)) { | |
179 | return; | |
180 | } | |
9208b961 | 181 | aarch64_save_sp(env, cur_el); |
f502cfc2 PM |
182 | env->pstate = deposit32(env->pstate, 0, 1, imm); |
183 | ||
61d4b215 EI |
184 | /* We rely on illegal updates to SPsel from EL0 to get trapped |
185 | * at translation time. | |
f502cfc2 | 186 | */ |
61d4b215 | 187 | assert(cur_el >= 1 && cur_el <= 3); |
9208b961 | 188 | aarch64_restore_sp(env, cur_el); |
f502cfc2 PM |
189 | } |
190 | ||
1853d5a9 EI |
191 | /* |
192 | * arm_pamax | |
193 | * @cpu: ARMCPU | |
194 | * | |
195 | * Returns the implementation defined bit-width of physical addresses. | |
196 | * The ARMv8 reference manuals refer to this as PAMax(). | |
197 | */ | |
198 | static inline unsigned int arm_pamax(ARMCPU *cpu) | |
199 | { | |
200 | static const unsigned int pamax_map[] = { | |
201 | [0] = 32, | |
202 | [1] = 36, | |
203 | [2] = 40, | |
204 | [3] = 42, | |
205 | [4] = 44, | |
206 | [5] = 48, | |
207 | }; | |
208 | unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4); | |
209 | ||
210 | /* id_aa64mmfr0 is a read-only register so values outside of the | |
211 | * supported mappings can be considered an implementation error. */ | |
212 | assert(parange < ARRAY_SIZE(pamax_map)); | |
213 | return pamax_map[parange]; | |
214 | } | |
215 | ||
73c5211b PM |
216 | /* Return true if extended addresses are enabled. |
217 | * This is always the case if our translation regime is 64 bit, | |
218 | * but depends on TTBCR.EAE for 32 bit. | |
219 | */ | |
220 | static inline bool extended_addresses_enabled(CPUARMState *env) | |
221 | { | |
11f136ee FA |
222 | TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; |
223 | return arm_el_is_aa64(env, 1) || | |
224 | (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); | |
73c5211b PM |
225 | } |
226 | ||
8bcbf37c PM |
227 | /* Valid Syndrome Register EC field values */ |
228 | enum arm_exception_class { | |
229 | EC_UNCATEGORIZED = 0x00, | |
230 | EC_WFX_TRAP = 0x01, | |
231 | EC_CP15RTTRAP = 0x03, | |
232 | EC_CP15RRTTRAP = 0x04, | |
233 | EC_CP14RTTRAP = 0x05, | |
234 | EC_CP14DTTRAP = 0x06, | |
235 | EC_ADVSIMDFPACCESSTRAP = 0x07, | |
236 | EC_FPIDTRAP = 0x08, | |
237 | EC_CP14RRTTRAP = 0x0c, | |
238 | EC_ILLEGALSTATE = 0x0e, | |
239 | EC_AA32_SVC = 0x11, | |
240 | EC_AA32_HVC = 0x12, | |
241 | EC_AA32_SMC = 0x13, | |
242 | EC_AA64_SVC = 0x15, | |
243 | EC_AA64_HVC = 0x16, | |
244 | EC_AA64_SMC = 0x17, | |
245 | EC_SYSTEMREGISTERTRAP = 0x18, | |
490aa7f1 | 246 | EC_SVEACCESSTRAP = 0x19, |
8bcbf37c PM |
247 | EC_INSNABORT = 0x20, |
248 | EC_INSNABORT_SAME_EL = 0x21, | |
249 | EC_PCALIGNMENT = 0x22, | |
250 | EC_DATAABORT = 0x24, | |
251 | EC_DATAABORT_SAME_EL = 0x25, | |
252 | EC_SPALIGNMENT = 0x26, | |
253 | EC_AA32_FPTRAP = 0x28, | |
254 | EC_AA64_FPTRAP = 0x2c, | |
255 | EC_SERROR = 0x2f, | |
256 | EC_BREAKPOINT = 0x30, | |
257 | EC_BREAKPOINT_SAME_EL = 0x31, | |
258 | EC_SOFTWARESTEP = 0x32, | |
259 | EC_SOFTWARESTEP_SAME_EL = 0x33, | |
260 | EC_WATCHPOINT = 0x34, | |
261 | EC_WATCHPOINT_SAME_EL = 0x35, | |
262 | EC_AA32_BKPT = 0x38, | |
263 | EC_VECTORCATCH = 0x3a, | |
264 | EC_AA64_BKPT = 0x3c, | |
265 | }; | |
266 | ||
267 | #define ARM_EL_EC_SHIFT 26 | |
268 | #define ARM_EL_IL_SHIFT 25 | |
094d028a | 269 | #define ARM_EL_ISV_SHIFT 24 |
8bcbf37c | 270 | #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT) |
094d028a | 271 | #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT) |
8bcbf37c PM |
272 | |
273 | /* Utility functions for constructing various kinds of syndrome value. | |
274 | * Note that in general we follow the AArch64 syndrome values; in a | |
275 | * few cases the value in HSR for exceptions taken to AArch32 Hyp | |
276 | * mode differs slightly, so if we ever implemented Hyp mode then the | |
277 | * syndrome value would need some massaging on exception entry. | |
278 | * (One example of this is that AArch64 defaults to IL bit set for | |
279 | * exceptions which don't specifically indicate information about the | |
280 | * trapping instruction, whereas AArch32 defaults to IL bit clear.) | |
281 | */ | |
282 | static inline uint32_t syn_uncategorized(void) | |
283 | { | |
284 | return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL; | |
285 | } | |
286 | ||
287 | static inline uint32_t syn_aa64_svc(uint32_t imm16) | |
288 | { | |
289 | return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); | |
290 | } | |
291 | ||
35979d71 EI |
292 | static inline uint32_t syn_aa64_hvc(uint32_t imm16) |
293 | { | |
294 | return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); | |
295 | } | |
296 | ||
e0d6e6a5 EI |
297 | static inline uint32_t syn_aa64_smc(uint32_t imm16) |
298 | { | |
299 | return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); | |
300 | } | |
301 | ||
fc05f4a6 | 302 | static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) |
8bcbf37c PM |
303 | { |
304 | return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) | |
fc05f4a6 | 305 | | (is_16bit ? 0 : ARM_EL_IL); |
8bcbf37c PM |
306 | } |
307 | ||
37e6456e PM |
308 | static inline uint32_t syn_aa32_hvc(uint32_t imm16) |
309 | { | |
310 | return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); | |
311 | } | |
312 | ||
313 | static inline uint32_t syn_aa32_smc(void) | |
314 | { | |
315 | return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL; | |
316 | } | |
317 | ||
8bcbf37c PM |
318 | static inline uint32_t syn_aa64_bkpt(uint32_t imm16) |
319 | { | |
320 | return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); | |
321 | } | |
322 | ||
fc05f4a6 | 323 | static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) |
8bcbf37c PM |
324 | { |
325 | return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) | |
fc05f4a6 | 326 | | (is_16bit ? 0 : ARM_EL_IL); |
8bcbf37c PM |
327 | } |
328 | ||
329 | static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, | |
330 | int crn, int crm, int rt, | |
331 | int isread) | |
332 | { | |
333 | return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | |
334 | | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) | |
335 | | (crm << 1) | isread; | |
336 | } | |
337 | ||
338 | static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, | |
339 | int crn, int crm, int rt, int isread, | |
fc05f4a6 | 340 | bool is_16bit) |
8bcbf37c PM |
341 | { |
342 | return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) | |
fc05f4a6 | 343 | | (is_16bit ? 0 : ARM_EL_IL) |
8bcbf37c PM |
344 | | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) |
345 | | (crn << 10) | (rt << 5) | (crm << 1) | isread; | |
346 | } | |
347 | ||
348 | static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, | |
349 | int crn, int crm, int rt, int isread, | |
fc05f4a6 | 350 | bool is_16bit) |
8bcbf37c PM |
351 | { |
352 | return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) | |
fc05f4a6 | 353 | | (is_16bit ? 0 : ARM_EL_IL) |
8bcbf37c PM |
354 | | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) |
355 | | (crn << 10) | (rt << 5) | (crm << 1) | isread; | |
356 | } | |
357 | ||
358 | static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, | |
359 | int rt, int rt2, int isread, | |
fc05f4a6 | 360 | bool is_16bit) |
8bcbf37c PM |
361 | { |
362 | return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) | |
fc05f4a6 | 363 | | (is_16bit ? 0 : ARM_EL_IL) |
8bcbf37c PM |
364 | | (cv << 24) | (cond << 20) | (opc1 << 16) |
365 | | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; | |
366 | } | |
367 | ||
368 | static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, | |
369 | int rt, int rt2, int isread, | |
fc05f4a6 | 370 | bool is_16bit) |
8bcbf37c PM |
371 | { |
372 | return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) | |
fc05f4a6 | 373 | | (is_16bit ? 0 : ARM_EL_IL) |
8bcbf37c PM |
374 | | (cv << 24) | (cond << 20) | (opc1 << 16) |
375 | | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; | |
376 | } | |
377 | ||
fc05f4a6 | 378 | static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) |
8c6afa6a PM |
379 | { |
380 | return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) | |
fc05f4a6 | 381 | | (is_16bit ? 0 : ARM_EL_IL) |
8c6afa6a PM |
382 | | (cv << 24) | (cond << 20); |
383 | } | |
384 | ||
490aa7f1 RH |
385 | static inline uint32_t syn_sve_access_trap(void) |
386 | { | |
387 | return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; | |
388 | } | |
389 | ||
00892383 RH |
390 | static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) |
391 | { | |
392 | return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | |
04ce861e | 393 | | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc; |
00892383 RH |
394 | } |
395 | ||
094d028a PM |
396 | static inline uint32_t syn_data_abort_no_iss(int same_el, |
397 | int ea, int cm, int s1ptw, | |
398 | int wnr, int fsc) | |
00892383 RH |
399 | { |
400 | return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | |
094d028a PM |
401 | | ARM_EL_IL |
402 | | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; | |
403 | } | |
404 | ||
405 | static inline uint32_t syn_data_abort_with_iss(int same_el, | |
406 | int sas, int sse, int srt, | |
407 | int sf, int ar, | |
408 | int ea, int cm, int s1ptw, | |
409 | int wnr, int fsc, | |
410 | bool is_16bit) | |
411 | { | |
412 | return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | |
413 | | (is_16bit ? 0 : ARM_EL_IL) | |
414 | | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16) | |
415 | | (sf << 15) | (ar << 14) | |
416 | | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; | |
00892383 RH |
417 | } |
418 | ||
7ea47fe7 PM |
419 | static inline uint32_t syn_swstep(int same_el, int isv, int ex) |
420 | { | |
421 | return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | |
04ce861e | 422 | | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22; |
7ea47fe7 PM |
423 | } |
424 | ||
3ff6fc91 PM |
425 | static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr) |
426 | { | |
427 | return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | |
04ce861e | 428 | | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22; |
3ff6fc91 PM |
429 | } |
430 | ||
0eacea70 PM |
431 | static inline uint32_t syn_breakpoint(int same_el) |
432 | { | |
433 | return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | |
434 | | ARM_EL_IL | 0x22; | |
435 | } | |
436 | ||
58803318 | 437 | static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) |
06fbb2fd GB |
438 | { |
439 | return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | | |
58803318 | 440 | (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | |
06fbb2fd GB |
441 | (cv << 24) | (cond << 20) | ti; |
442 | } | |
443 | ||
9ee98ce8 PM |
444 | /* Update a QEMU watchpoint based on the information the guest has set in the |
445 | * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers. | |
446 | */ | |
447 | void hw_watchpoint_update(ARMCPU *cpu, int n); | |
448 | /* Update the QEMU watchpoints for every guest watchpoint. This does a | |
449 | * complete delete-and-reinstate of the QEMU watchpoint list and so is | |
450 | * suitable for use after migration or on reset. | |
451 | */ | |
452 | void hw_watchpoint_update_all(ARMCPU *cpu); | |
46747d15 PM |
453 | /* Update a QEMU breakpoint based on the information the guest has set in the |
454 | * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers. | |
455 | */ | |
456 | void hw_breakpoint_update(ARMCPU *cpu, int n); | |
457 | /* Update the QEMU breakpoints for every guest breakpoint. This does a | |
458 | * complete delete-and-reinstate of the QEMU breakpoint list and so is | |
459 | * suitable for use after migration or on reset. | |
460 | */ | |
461 | void hw_breakpoint_update_all(ARMCPU *cpu); | |
9ee98ce8 | 462 | |
3826121d SF |
463 | /* Callback function for checking if a watchpoint should trigger. */ |
464 | bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); | |
465 | ||
40612000 JB |
466 | /* Adjust addresses (in BE32 mode) before testing against watchpoint |
467 | * addresses. | |
468 | */ | |
469 | vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len); | |
470 | ||
3ff6fc91 PM |
471 | /* Callback function for when a watchpoint or breakpoint triggers. */ |
472 | void arm_debug_excp_handler(CPUState *cs); | |
473 | ||
98128601 RH |
474 | #ifdef CONFIG_USER_ONLY |
475 | static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type) | |
476 | { | |
477 | return false; | |
478 | } | |
479 | #else | |
480 | /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */ | |
481 | bool arm_is_psci_call(ARMCPU *cpu, int excp_type); | |
482 | /* Actually handle a PSCI call */ | |
483 | void arm_handle_psci_call(ARMCPU *cpu); | |
484 | #endif | |
485 | ||
dc3c4c14 PM |
486 | /** |
487 | * arm_clear_exclusive: clear the exclusive monitor | |
488 | * @env: CPU env | |
489 | * Clear the CPU's exclusive monitor, like the guest CLREX instruction. | |
490 | */ | |
491 | static inline void arm_clear_exclusive(CPUARMState *env) | |
492 | { | |
493 | env->exclusive_addr = -1; | |
494 | } | |
495 | ||
1fa498fe PM |
496 | /** |
497 | * ARMFaultType: type of an ARM MMU fault | |
498 | * This corresponds to the v8A pseudocode's Fault enumeration, | |
499 | * with extensions for QEMU internal conditions. | |
500 | */ | |
501 | typedef enum ARMFaultType { | |
502 | ARMFault_None, | |
503 | ARMFault_AccessFlag, | |
504 | ARMFault_Alignment, | |
505 | ARMFault_Background, | |
506 | ARMFault_Domain, | |
507 | ARMFault_Permission, | |
508 | ARMFault_Translation, | |
509 | ARMFault_AddressSize, | |
510 | ARMFault_SyncExternal, | |
511 | ARMFault_SyncExternalOnWalk, | |
512 | ARMFault_SyncParity, | |
513 | ARMFault_SyncParityOnWalk, | |
514 | ARMFault_AsyncParity, | |
515 | ARMFault_AsyncExternal, | |
516 | ARMFault_Debug, | |
517 | ARMFault_TLBConflict, | |
518 | ARMFault_Lockdown, | |
519 | ARMFault_Exclusive, | |
520 | ARMFault_ICacheMaint, | |
521 | ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */ | |
522 | ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */ | |
523 | } ARMFaultType; | |
524 | ||
e14b5a23 EI |
525 | /** |
526 | * ARMMMUFaultInfo: Information describing an ARM MMU Fault | |
1fa498fe PM |
527 | * @type: Type of fault |
528 | * @level: Table walk level (for translation, access flag and permission faults) | |
529 | * @domain: Domain of the fault address (for non-LPAE CPUs only) | |
e14b5a23 EI |
530 | * @s2addr: Address that caused a fault at stage 2 |
531 | * @stage2: True if we faulted at stage 2 | |
532 | * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk | |
c528af7a | 533 | * @ea: True if we should set the EA (external abort type) bit in syndrome |
e14b5a23 EI |
534 | */ |
535 | typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; | |
536 | struct ARMMMUFaultInfo { | |
1fa498fe | 537 | ARMFaultType type; |
e14b5a23 | 538 | target_ulong s2addr; |
1fa498fe PM |
539 | int level; |
540 | int domain; | |
e14b5a23 EI |
541 | bool stage2; |
542 | bool s1ptw; | |
c528af7a | 543 | bool ea; |
e14b5a23 EI |
544 | }; |
545 | ||
1fa498fe PM |
546 | /** |
547 | * arm_fi_to_sfsc: Convert fault info struct to short-format FSC | |
548 | * Compare pseudocode EncodeSDFSC(), though unlike that function | |
549 | * we set up a whole FSR-format code including domain field and | |
550 | * putting the high bit of the FSC into bit 10. | |
551 | */ | |
552 | static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo *fi) | |
553 | { | |
554 | uint32_t fsc; | |
555 | ||
556 | switch (fi->type) { | |
557 | case ARMFault_None: | |
558 | return 0; | |
559 | case ARMFault_AccessFlag: | |
560 | fsc = fi->level == 1 ? 0x3 : 0x6; | |
561 | break; | |
562 | case ARMFault_Alignment: | |
563 | fsc = 0x1; | |
564 | break; | |
565 | case ARMFault_Permission: | |
566 | fsc = fi->level == 1 ? 0xd : 0xf; | |
567 | break; | |
568 | case ARMFault_Domain: | |
569 | fsc = fi->level == 1 ? 0x9 : 0xb; | |
570 | break; | |
571 | case ARMFault_Translation: | |
572 | fsc = fi->level == 1 ? 0x5 : 0x7; | |
573 | break; | |
574 | case ARMFault_SyncExternal: | |
575 | fsc = 0x8 | (fi->ea << 12); | |
576 | break; | |
577 | case ARMFault_SyncExternalOnWalk: | |
578 | fsc = fi->level == 1 ? 0xc : 0xe; | |
579 | fsc |= (fi->ea << 12); | |
580 | break; | |
581 | case ARMFault_SyncParity: | |
582 | fsc = 0x409; | |
583 | break; | |
584 | case ARMFault_SyncParityOnWalk: | |
585 | fsc = fi->level == 1 ? 0x40c : 0x40e; | |
586 | break; | |
587 | case ARMFault_AsyncParity: | |
588 | fsc = 0x408; | |
589 | break; | |
590 | case ARMFault_AsyncExternal: | |
591 | fsc = 0x406 | (fi->ea << 12); | |
592 | break; | |
593 | case ARMFault_Debug: | |
594 | fsc = 0x2; | |
595 | break; | |
596 | case ARMFault_TLBConflict: | |
597 | fsc = 0x400; | |
598 | break; | |
599 | case ARMFault_Lockdown: | |
600 | fsc = 0x404; | |
601 | break; | |
602 | case ARMFault_Exclusive: | |
603 | fsc = 0x405; | |
604 | break; | |
605 | case ARMFault_ICacheMaint: | |
606 | fsc = 0x4; | |
607 | break; | |
608 | case ARMFault_Background: | |
609 | fsc = 0x0; | |
610 | break; | |
611 | case ARMFault_QEMU_NSCExec: | |
612 | fsc = M_FAKE_FSR_NSC_EXEC; | |
613 | break; | |
614 | case ARMFault_QEMU_SFault: | |
615 | fsc = M_FAKE_FSR_SFAULT; | |
616 | break; | |
617 | default: | |
618 | /* Other faults can't occur in a context that requires a | |
619 | * short-format status code. | |
620 | */ | |
621 | g_assert_not_reached(); | |
622 | } | |
623 | ||
624 | fsc |= (fi->domain << 4); | |
625 | return fsc; | |
626 | } | |
627 | ||
628 | /** | |
629 | * arm_fi_to_lfsc: Convert fault info struct to long-format FSC | |
630 | * Compare pseudocode EncodeLDFSC(), though unlike that function | |
631 | * we fill in also the LPAE bit 9 of a DFSR format. | |
632 | */ | |
633 | static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) | |
634 | { | |
635 | uint32_t fsc; | |
636 | ||
637 | switch (fi->type) { | |
638 | case ARMFault_None: | |
639 | return 0; | |
640 | case ARMFault_AddressSize: | |
641 | fsc = fi->level & 3; | |
642 | break; | |
643 | case ARMFault_AccessFlag: | |
644 | fsc = (fi->level & 3) | (0x2 << 2); | |
645 | break; | |
646 | case ARMFault_Permission: | |
647 | fsc = (fi->level & 3) | (0x3 << 2); | |
648 | break; | |
649 | case ARMFault_Translation: | |
650 | fsc = (fi->level & 3) | (0x1 << 2); | |
651 | break; | |
652 | case ARMFault_SyncExternal: | |
653 | fsc = 0x10 | (fi->ea << 12); | |
654 | break; | |
655 | case ARMFault_SyncExternalOnWalk: | |
656 | fsc = (fi->level & 3) | (0x5 << 2) | (fi->ea << 12); | |
657 | break; | |
658 | case ARMFault_SyncParity: | |
659 | fsc = 0x18; | |
660 | break; | |
661 | case ARMFault_SyncParityOnWalk: | |
662 | fsc = (fi->level & 3) | (0x7 << 2); | |
663 | break; | |
664 | case ARMFault_AsyncParity: | |
665 | fsc = 0x19; | |
666 | break; | |
667 | case ARMFault_AsyncExternal: | |
668 | fsc = 0x11 | (fi->ea << 12); | |
669 | break; | |
670 | case ARMFault_Alignment: | |
671 | fsc = 0x21; | |
672 | break; | |
673 | case ARMFault_Debug: | |
674 | fsc = 0x22; | |
675 | break; | |
676 | case ARMFault_TLBConflict: | |
677 | fsc = 0x30; | |
678 | break; | |
679 | case ARMFault_Lockdown: | |
680 | fsc = 0x34; | |
681 | break; | |
682 | case ARMFault_Exclusive: | |
683 | fsc = 0x35; | |
684 | break; | |
685 | default: | |
686 | /* Other faults can't occur in a context that requires a | |
687 | * long-format status code. | |
688 | */ | |
689 | g_assert_not_reached(); | |
690 | } | |
691 | ||
692 | fsc |= 1 << 9; | |
693 | return fsc; | |
694 | } | |
695 | ||
3b39d734 PM |
696 | static inline bool arm_extabort_type(MemTxResult result) |
697 | { | |
698 | /* The EA bit in syndromes and fault status registers is an | |
699 | * IMPDEF classification of external aborts. ARM implementations | |
700 | * usually use this to indicate AXI bus Decode error (0) or | |
701 | * Slave error (1); in QEMU we follow that. | |
702 | */ | |
703 | return result != MEMTX_DECODE_ERROR; | |
704 | } | |
705 | ||
8c6084bf | 706 | /* Do a page table walk and add page to TLB if possible */ |
03ae85f8 PM |
707 | bool arm_tlb_fill(CPUState *cpu, vaddr address, |
708 | MMUAccessType access_type, int mmu_idx, | |
bc52bfeb | 709 | ARMMMUFaultInfo *fi); |
8c6084bf | 710 | |
deb2db99 AR |
711 | /* Return true if the stage 1 translation regime is using LPAE format page |
712 | * tables */ | |
713 | bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); | |
30901475 AB |
714 | |
715 | /* Raise a data fault alignment exception for the specified virtual address */ | |
b35399bb SS |
716 | void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, |
717 | MMUAccessType access_type, | |
718 | int mmu_idx, uintptr_t retaddr); | |
30901475 | 719 | |
c79c0a31 PM |
720 | /* arm_cpu_do_transaction_failed: handle a memory system error response |
721 | * (eg "no device/memory present at address") by raising an external abort | |
722 | * exception | |
723 | */ | |
724 | void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, | |
725 | vaddr addr, unsigned size, | |
726 | MMUAccessType access_type, | |
727 | int mmu_idx, MemTxAttrs attrs, | |
728 | MemTxResult response, uintptr_t retaddr); | |
729 | ||
08267487 | 730 | /* Call any registered EL change hooks */ |
b5c53d1b AL |
731 | static inline void arm_call_pre_el_change_hook(ARMCPU *cpu) |
732 | { | |
733 | ARMELChangeHook *hook, *next; | |
734 | QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { | |
735 | hook->hook(cpu, hook->opaque); | |
736 | } | |
737 | } | |
bd7d00fc PM |
738 | static inline void arm_call_el_change_hook(ARMCPU *cpu) |
739 | { | |
08267487 AL |
740 | ARMELChangeHook *hook, *next; |
741 | QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { | |
742 | hook->hook(cpu, hook->opaque); | |
bd7d00fc PM |
743 | } |
744 | } | |
745 | ||
61fcd69b PM |
746 | /* Return true if this address translation regime is secure */ |
747 | static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) | |
748 | { | |
749 | switch (mmu_idx) { | |
750 | case ARMMMUIdx_S12NSE0: | |
751 | case ARMMMUIdx_S12NSE1: | |
752 | case ARMMMUIdx_S1NSE0: | |
753 | case ARMMMUIdx_S1NSE1: | |
754 | case ARMMMUIdx_S1E2: | |
755 | case ARMMMUIdx_S2NS: | |
62593718 PM |
756 | case ARMMMUIdx_MPrivNegPri: |
757 | case ARMMMUIdx_MUserNegPri: | |
61fcd69b | 758 | case ARMMMUIdx_MPriv: |
61fcd69b PM |
759 | case ARMMMUIdx_MUser: |
760 | return false; | |
761 | case ARMMMUIdx_S1E3: | |
762 | case ARMMMUIdx_S1SE0: | |
763 | case ARMMMUIdx_S1SE1: | |
62593718 PM |
764 | case ARMMMUIdx_MSPrivNegPri: |
765 | case ARMMMUIdx_MSUserNegPri: | |
61fcd69b | 766 | case ARMMMUIdx_MSPriv: |
61fcd69b PM |
767 | case ARMMMUIdx_MSUser: |
768 | return true; | |
769 | default: | |
770 | g_assert_not_reached(); | |
771 | } | |
772 | } | |
773 | ||
81621d9a PM |
774 | /* Return the FSR value for a debug exception (watchpoint, hardware |
775 | * breakpoint or BKPT insn) targeting the specified exception level. | |
776 | */ | |
777 | static inline uint32_t arm_debug_exception_fsr(CPUARMState *env) | |
778 | { | |
779 | ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; | |
780 | int target_el = arm_debug_target_el(env); | |
781 | bool using_lpae = false; | |
782 | ||
783 | if (target_el == 2 || arm_el_is_aa64(env, target_el)) { | |
784 | using_lpae = true; | |
785 | } else { | |
786 | if (arm_feature(env, ARM_FEATURE_LPAE) && | |
787 | (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { | |
788 | using_lpae = true; | |
789 | } | |
790 | } | |
791 | ||
792 | if (using_lpae) { | |
793 | return arm_fi_to_lfsc(&fi); | |
794 | } else { | |
795 | return arm_fi_to_sfsc(&fi); | |
796 | } | |
797 | } | |
798 | ||
500d0484 RH |
799 | /* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3. |
800 | * Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits. | |
801 | */ | |
802 | #define MEMOPIDX_SHIFT 8 | |
803 | ||
5529bf18 PM |
804 | /** |
805 | * v7m_using_psp: Return true if using process stack pointer | |
806 | * Return true if the CPU is currently using the process stack | |
807 | * pointer, or false if it is using the main stack pointer. | |
808 | */ | |
809 | static inline bool v7m_using_psp(CPUARMState *env) | |
810 | { | |
811 | /* Handler mode always uses the main stack; for thread mode | |
812 | * the CONTROL.SPSEL bit determines the answer. | |
813 | * Note that in v7M it is not possible to be in Handler mode with | |
814 | * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both. | |
815 | */ | |
816 | return !arm_v7m_is_handler_mode(env) && | |
817 | env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; | |
818 | } | |
819 | ||
55203189 PM |
820 | /** |
821 | * v7m_sp_limit: Return SP limit for current CPU state | |
822 | * Return the SP limit value for the current CPU security state | |
823 | * and stack pointer. | |
824 | */ | |
825 | static inline uint32_t v7m_sp_limit(CPUARMState *env) | |
826 | { | |
827 | if (v7m_using_psp(env)) { | |
828 | return env->v7m.psplim[env->v7m.secure]; | |
829 | } else { | |
830 | return env->v7m.msplim[env->v7m.secure]; | |
831 | } | |
832 | } | |
833 | ||
ccd38087 | 834 | #endif |