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ccd38087 PM |
1 | /* |
2 | * QEMU ARM CPU -- internal functions and types | |
3 | * | |
4 | * Copyright (c) 2014 Linaro Ltd | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | * | |
20 | * This header defines functions, types, etc which need to be shared | |
fcf5ef2a | 21 | * between different source files within target/arm/ but which are |
ccd38087 PM |
22 | * private to it and not required by the rest of QEMU. |
23 | */ | |
24 | ||
25 | #ifndef TARGET_ARM_INTERNALS_H | |
26 | #define TARGET_ARM_INTERNALS_H | |
27 | ||
abc24d86 | 28 | #include "hw/registerfields.h" |
28f32503 | 29 | #include "tcg/tcg-gvec-desc.h" |
1fe27859 | 30 | #include "syndrome.h" |
abc24d86 | 31 | |
99a99c1f SB |
32 | /* register banks for CPU modes */ |
33 | #define BANK_USRSYS 0 | |
34 | #define BANK_SVC 1 | |
35 | #define BANK_ABT 2 | |
36 | #define BANK_UND 3 | |
37 | #define BANK_IRQ 4 | |
38 | #define BANK_FIQ 5 | |
39 | #define BANK_HYP 6 | |
40 | #define BANK_MON 7 | |
41 | ||
d4a2dc67 PM |
42 | static inline bool excp_is_internal(int excp) |
43 | { | |
44 | /* Return true if this exception number represents a QEMU-internal | |
45 | * exception that will not be passed to the guest. | |
46 | */ | |
47 | return excp == EXCP_INTERRUPT | |
48 | || excp == EXCP_HLT | |
49 | || excp == EXCP_DEBUG | |
50 | || excp == EXCP_HALTED | |
51 | || excp == EXCP_EXCEPTION_EXIT | |
52 | || excp == EXCP_KERNEL_TRAP | |
05188cc7 | 53 | || excp == EXCP_SEMIHOST; |
d4a2dc67 PM |
54 | } |
55 | ||
ccd38087 PM |
56 | /* Scale factor for generic timers, ie number of ns per tick. |
57 | * This gives a 62.5MHz timer. | |
58 | */ | |
59 | #define GTIMER_SCALE 16 | |
60 | ||
abc24d86 MD |
61 | /* Bit definitions for the v7M CONTROL register */ |
62 | FIELD(V7M_CONTROL, NPRIV, 0, 1) | |
63 | FIELD(V7M_CONTROL, SPSEL, 1, 1) | |
64 | FIELD(V7M_CONTROL, FPCA, 2, 1) | |
3e3fa230 | 65 | FIELD(V7M_CONTROL, SFPA, 3, 1) |
abc24d86 | 66 | |
4d1e7a47 PM |
67 | /* Bit definitions for v7M exception return payload */ |
68 | FIELD(V7M_EXCRET, ES, 0, 1) | |
69 | FIELD(V7M_EXCRET, RES0, 1, 1) | |
70 | FIELD(V7M_EXCRET, SPSEL, 2, 1) | |
71 | FIELD(V7M_EXCRET, MODE, 3, 1) | |
72 | FIELD(V7M_EXCRET, FTYPE, 4, 1) | |
73 | FIELD(V7M_EXCRET, DCRS, 5, 1) | |
74 | FIELD(V7M_EXCRET, S, 6, 1) | |
75 | FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ | |
76 | ||
d02a8698 PM |
77 | /* Minimum value which is a magic number for exception return */ |
78 | #define EXC_RETURN_MIN_MAGIC 0xff000000 | |
79 | /* Minimum number which is a magic number for function or exception return | |
80 | * when using v8M security extension | |
81 | */ | |
82 | #define FNC_RETURN_MIN_MAGIC 0xfefffffe | |
83 | ||
8b7a5bbe RH |
84 | /* Bit definitions for DBGWCRn and DBGWCRn_EL1 */ |
85 | FIELD(DBGWCR, E, 0, 1) | |
86 | FIELD(DBGWCR, PAC, 1, 2) | |
87 | FIELD(DBGWCR, LSC, 3, 2) | |
88 | FIELD(DBGWCR, BAS, 5, 8) | |
89 | FIELD(DBGWCR, HMC, 13, 1) | |
90 | FIELD(DBGWCR, SSC, 14, 2) | |
91 | FIELD(DBGWCR, LBN, 16, 4) | |
92 | FIELD(DBGWCR, WT, 20, 1) | |
93 | FIELD(DBGWCR, MASK, 24, 5) | |
94 | FIELD(DBGWCR, SSCE, 29, 1) | |
95 | ||
35337cc3 PM |
96 | /* We use a few fake FSR values for internal purposes in M profile. |
97 | * M profile cores don't have A/R format FSRs, but currently our | |
98 | * get_phys_addr() code assumes A/R profile and reports failures via | |
99 | * an A/R format FSR value. We then translate that into the proper | |
100 | * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt(). | |
101 | * Mostly the FSR values we use for this are those defined for v7PMSA, | |
102 | * since we share some of that codepath. A few kinds of fault are | |
103 | * only for M profile and have no A/R equivalent, though, so we have | |
104 | * to pick a value from the reserved range (which we never otherwise | |
105 | * generate) to use for these. | |
106 | * These values will never be visible to the guest. | |
107 | */ | |
108 | #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */ | |
109 | #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */ | |
110 | ||
597610eb PM |
111 | /** |
112 | * raise_exception: Raise the specified exception. | |
113 | * Raise a guest exception with the specified value, syndrome register | |
114 | * and target exception level. This should be called from helper functions, | |
115 | * and never returns because we will longjump back up to the CPU main loop. | |
116 | */ | |
8905770b MAL |
117 | G_NORETURN void raise_exception(CPUARMState *env, uint32_t excp, |
118 | uint32_t syndrome, uint32_t target_el); | |
597610eb | 119 | |
7469f6c6 RH |
120 | /* |
121 | * Similarly, but also use unwinding to restore cpu state. | |
122 | */ | |
8905770b | 123 | G_NORETURN void raise_exception_ra(CPUARMState *env, uint32_t excp, |
7469f6c6 RH |
124 | uint32_t syndrome, uint32_t target_el, |
125 | uintptr_t ra); | |
126 | ||
2a923c4d EI |
127 | /* |
128 | * For AArch64, map a given EL to an index in the banked_spsr array. | |
7847f9ea PM |
129 | * Note that this mapping and the AArch32 mapping defined in bank_number() |
130 | * must agree such that the AArch64<->AArch32 SPSRs have the architecturally | |
131 | * mandated mapping between each other. | |
2a923c4d EI |
132 | */ |
133 | static inline unsigned int aarch64_banked_spsr_index(unsigned int el) | |
134 | { | |
135 | static const unsigned int map[4] = { | |
99a99c1f SB |
136 | [1] = BANK_SVC, /* EL1. */ |
137 | [2] = BANK_HYP, /* EL2. */ | |
138 | [3] = BANK_MON, /* EL3. */ | |
2a923c4d EI |
139 | }; |
140 | assert(el >= 1 && el <= 3); | |
141 | return map[el]; | |
142 | } | |
143 | ||
c766568d PM |
144 | /* Map CPU modes onto saved register banks. */ |
145 | static inline int bank_number(int mode) | |
146 | { | |
147 | switch (mode) { | |
148 | case ARM_CPU_MODE_USR: | |
149 | case ARM_CPU_MODE_SYS: | |
150 | return BANK_USRSYS; | |
151 | case ARM_CPU_MODE_SVC: | |
152 | return BANK_SVC; | |
153 | case ARM_CPU_MODE_ABT: | |
154 | return BANK_ABT; | |
155 | case ARM_CPU_MODE_UND: | |
156 | return BANK_UND; | |
157 | case ARM_CPU_MODE_IRQ: | |
158 | return BANK_IRQ; | |
159 | case ARM_CPU_MODE_FIQ: | |
160 | return BANK_FIQ; | |
161 | case ARM_CPU_MODE_HYP: | |
162 | return BANK_HYP; | |
163 | case ARM_CPU_MODE_MON: | |
164 | return BANK_MON; | |
165 | } | |
166 | g_assert_not_reached(); | |
167 | } | |
168 | ||
593cfa2b PM |
169 | /** |
170 | * r14_bank_number: Map CPU mode onto register bank for r14 | |
171 | * | |
172 | * Given an AArch32 CPU mode, return the index into the saved register | |
173 | * banks to use for the R14 (LR) in that mode. This is the same as | |
174 | * bank_number(), except for the special case of Hyp mode, where | |
175 | * R14 is shared with USR and SYS, unlike its R13 and SPSR. | |
176 | * This should be used as the index into env->banked_r14[], and | |
177 | * bank_number() used for the index into env->banked_r13[] and | |
178 | * env->banked_spsr[]. | |
179 | */ | |
180 | static inline int r14_bank_number(int mode) | |
181 | { | |
182 | return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode); | |
183 | } | |
184 | ||
ccd38087 PM |
185 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); |
186 | void arm_translate_init(void); | |
187 | ||
78271684 | 188 | #ifdef CONFIG_TCG |
8349d2ae | 189 | void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); |
78271684 CF |
190 | #endif /* CONFIG_TCG */ |
191 | ||
ce440581 RH |
192 | /** |
193 | * aarch64_sve_zcr_get_valid_len: | |
194 | * @cpu: cpu context | |
195 | * @start_len: maximum len to consider | |
196 | * | |
197 | * Return the maximum supported sve vector length <= @start_len. | |
198 | * Note that both @start_len and the return value are in units | |
199 | * of ZCR_ELx.LEN, so the vector bit length is (x + 1) * 128. | |
200 | */ | |
201 | uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len); | |
78271684 | 202 | |
ccd38087 PM |
203 | enum arm_fprounding { |
204 | FPROUNDING_TIEEVEN, | |
205 | FPROUNDING_POSINF, | |
206 | FPROUNDING_NEGINF, | |
207 | FPROUNDING_ZERO, | |
208 | FPROUNDING_TIEAWAY, | |
209 | FPROUNDING_ODD | |
210 | }; | |
211 | ||
212 | int arm_rmode_to_sf(int rmode); | |
213 | ||
9208b961 EI |
214 | static inline void aarch64_save_sp(CPUARMState *env, int el) |
215 | { | |
216 | if (env->pstate & PSTATE_SP) { | |
217 | env->sp_el[el] = env->xregs[31]; | |
218 | } else { | |
219 | env->sp_el[0] = env->xregs[31]; | |
220 | } | |
221 | } | |
222 | ||
223 | static inline void aarch64_restore_sp(CPUARMState *env, int el) | |
224 | { | |
225 | if (env->pstate & PSTATE_SP) { | |
226 | env->xregs[31] = env->sp_el[el]; | |
227 | } else { | |
228 | env->xregs[31] = env->sp_el[0]; | |
229 | } | |
230 | } | |
231 | ||
f502cfc2 PM |
232 | static inline void update_spsel(CPUARMState *env, uint32_t imm) |
233 | { | |
dcbff19b | 234 | unsigned int cur_el = arm_current_el(env); |
f502cfc2 PM |
235 | /* Update PSTATE SPSel bit; this requires us to update the |
236 | * working stack pointer in xregs[31]. | |
237 | */ | |
238 | if (!((imm ^ env->pstate) & PSTATE_SP)) { | |
239 | return; | |
240 | } | |
9208b961 | 241 | aarch64_save_sp(env, cur_el); |
f502cfc2 PM |
242 | env->pstate = deposit32(env->pstate, 0, 1, imm); |
243 | ||
61d4b215 EI |
244 | /* We rely on illegal updates to SPsel from EL0 to get trapped |
245 | * at translation time. | |
f502cfc2 | 246 | */ |
61d4b215 | 247 | assert(cur_el >= 1 && cur_el <= 3); |
9208b961 | 248 | aarch64_restore_sp(env, cur_el); |
f502cfc2 PM |
249 | } |
250 | ||
1853d5a9 EI |
251 | /* |
252 | * arm_pamax | |
253 | * @cpu: ARMCPU | |
254 | * | |
255 | * Returns the implementation defined bit-width of physical addresses. | |
256 | * The ARMv8 reference manuals refer to this as PAMax(). | |
257 | */ | |
71a77257 | 258 | unsigned int arm_pamax(ARMCPU *cpu); |
1853d5a9 | 259 | |
73c5211b PM |
260 | /* Return true if extended addresses are enabled. |
261 | * This is always the case if our translation regime is 64 bit, | |
262 | * but depends on TTBCR.EAE for 32 bit. | |
263 | */ | |
264 | static inline bool extended_addresses_enabled(CPUARMState *env) | |
265 | { | |
11f136ee FA |
266 | TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; |
267 | return arm_el_is_aa64(env, 1) || | |
268 | (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE)); | |
73c5211b PM |
269 | } |
270 | ||
9ee98ce8 PM |
271 | /* Update a QEMU watchpoint based on the information the guest has set in the |
272 | * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers. | |
273 | */ | |
274 | void hw_watchpoint_update(ARMCPU *cpu, int n); | |
275 | /* Update the QEMU watchpoints for every guest watchpoint. This does a | |
276 | * complete delete-and-reinstate of the QEMU watchpoint list and so is | |
277 | * suitable for use after migration or on reset. | |
278 | */ | |
279 | void hw_watchpoint_update_all(ARMCPU *cpu); | |
46747d15 PM |
280 | /* Update a QEMU breakpoint based on the information the guest has set in the |
281 | * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers. | |
282 | */ | |
283 | void hw_breakpoint_update(ARMCPU *cpu, int n); | |
284 | /* Update the QEMU breakpoints for every guest breakpoint. This does a | |
285 | * complete delete-and-reinstate of the QEMU breakpoint list and so is | |
286 | * suitable for use after migration or on reset. | |
287 | */ | |
288 | void hw_breakpoint_update_all(ARMCPU *cpu); | |
9ee98ce8 | 289 | |
b00d86bc RH |
290 | /* Callback function for checking if a breakpoint should trigger. */ |
291 | bool arm_debug_check_breakpoint(CPUState *cs); | |
292 | ||
3826121d SF |
293 | /* Callback function for checking if a watchpoint should trigger. */ |
294 | bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); | |
295 | ||
40612000 JB |
296 | /* Adjust addresses (in BE32 mode) before testing against watchpoint |
297 | * addresses. | |
298 | */ | |
299 | vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len); | |
300 | ||
3ff6fc91 PM |
301 | /* Callback function for when a watchpoint or breakpoint triggers. */ |
302 | void arm_debug_excp_handler(CPUState *cs); | |
303 | ||
21fbea8c | 304 | #if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG) |
98128601 RH |
305 | static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type) |
306 | { | |
307 | return false; | |
308 | } | |
21fbea8c PMD |
309 | static inline void arm_handle_psci_call(ARMCPU *cpu) |
310 | { | |
311 | g_assert_not_reached(); | |
312 | } | |
98128601 RH |
313 | #else |
314 | /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */ | |
315 | bool arm_is_psci_call(ARMCPU *cpu, int excp_type); | |
316 | /* Actually handle a PSCI call */ | |
317 | void arm_handle_psci_call(ARMCPU *cpu); | |
318 | #endif | |
319 | ||
dc3c4c14 PM |
320 | /** |
321 | * arm_clear_exclusive: clear the exclusive monitor | |
322 | * @env: CPU env | |
323 | * Clear the CPU's exclusive monitor, like the guest CLREX instruction. | |
324 | */ | |
325 | static inline void arm_clear_exclusive(CPUARMState *env) | |
326 | { | |
327 | env->exclusive_addr = -1; | |
328 | } | |
329 | ||
1fa498fe PM |
330 | /** |
331 | * ARMFaultType: type of an ARM MMU fault | |
332 | * This corresponds to the v8A pseudocode's Fault enumeration, | |
333 | * with extensions for QEMU internal conditions. | |
334 | */ | |
335 | typedef enum ARMFaultType { | |
336 | ARMFault_None, | |
337 | ARMFault_AccessFlag, | |
338 | ARMFault_Alignment, | |
339 | ARMFault_Background, | |
340 | ARMFault_Domain, | |
341 | ARMFault_Permission, | |
342 | ARMFault_Translation, | |
343 | ARMFault_AddressSize, | |
344 | ARMFault_SyncExternal, | |
345 | ARMFault_SyncExternalOnWalk, | |
346 | ARMFault_SyncParity, | |
347 | ARMFault_SyncParityOnWalk, | |
348 | ARMFault_AsyncParity, | |
349 | ARMFault_AsyncExternal, | |
350 | ARMFault_Debug, | |
351 | ARMFault_TLBConflict, | |
352 | ARMFault_Lockdown, | |
353 | ARMFault_Exclusive, | |
354 | ARMFault_ICacheMaint, | |
355 | ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */ | |
356 | ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */ | |
357 | } ARMFaultType; | |
358 | ||
e14b5a23 EI |
359 | /** |
360 | * ARMMMUFaultInfo: Information describing an ARM MMU Fault | |
1fa498fe PM |
361 | * @type: Type of fault |
362 | * @level: Table walk level (for translation, access flag and permission faults) | |
363 | * @domain: Domain of the fault address (for non-LPAE CPUs only) | |
e14b5a23 EI |
364 | * @s2addr: Address that caused a fault at stage 2 |
365 | * @stage2: True if we faulted at stage 2 | |
366 | * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk | |
9861248f | 367 | * @s1ns: True if we faulted on a non-secure IPA while in secure state |
c528af7a | 368 | * @ea: True if we should set the EA (external abort type) bit in syndrome |
e14b5a23 EI |
369 | */ |
370 | typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; | |
371 | struct ARMMMUFaultInfo { | |
1fa498fe | 372 | ARMFaultType type; |
e14b5a23 | 373 | target_ulong s2addr; |
1fa498fe PM |
374 | int level; |
375 | int domain; | |
e14b5a23 EI |
376 | bool stage2; |
377 | bool s1ptw; | |
9861248f | 378 | bool s1ns; |
c528af7a | 379 | bool ea; |
e14b5a23 EI |
380 | }; |
381 | ||
1fa498fe PM |
382 | /** |
383 | * arm_fi_to_sfsc: Convert fault info struct to short-format FSC | |
384 | * Compare pseudocode EncodeSDFSC(), though unlike that function | |
385 | * we set up a whole FSR-format code including domain field and | |
386 | * putting the high bit of the FSC into bit 10. | |
387 | */ | |
388 | static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo *fi) | |
389 | { | |
390 | uint32_t fsc; | |
391 | ||
392 | switch (fi->type) { | |
393 | case ARMFault_None: | |
394 | return 0; | |
395 | case ARMFault_AccessFlag: | |
396 | fsc = fi->level == 1 ? 0x3 : 0x6; | |
397 | break; | |
398 | case ARMFault_Alignment: | |
399 | fsc = 0x1; | |
400 | break; | |
401 | case ARMFault_Permission: | |
402 | fsc = fi->level == 1 ? 0xd : 0xf; | |
403 | break; | |
404 | case ARMFault_Domain: | |
405 | fsc = fi->level == 1 ? 0x9 : 0xb; | |
406 | break; | |
407 | case ARMFault_Translation: | |
408 | fsc = fi->level == 1 ? 0x5 : 0x7; | |
409 | break; | |
410 | case ARMFault_SyncExternal: | |
411 | fsc = 0x8 | (fi->ea << 12); | |
412 | break; | |
413 | case ARMFault_SyncExternalOnWalk: | |
414 | fsc = fi->level == 1 ? 0xc : 0xe; | |
415 | fsc |= (fi->ea << 12); | |
416 | break; | |
417 | case ARMFault_SyncParity: | |
418 | fsc = 0x409; | |
419 | break; | |
420 | case ARMFault_SyncParityOnWalk: | |
421 | fsc = fi->level == 1 ? 0x40c : 0x40e; | |
422 | break; | |
423 | case ARMFault_AsyncParity: | |
424 | fsc = 0x408; | |
425 | break; | |
426 | case ARMFault_AsyncExternal: | |
427 | fsc = 0x406 | (fi->ea << 12); | |
428 | break; | |
429 | case ARMFault_Debug: | |
430 | fsc = 0x2; | |
431 | break; | |
432 | case ARMFault_TLBConflict: | |
433 | fsc = 0x400; | |
434 | break; | |
435 | case ARMFault_Lockdown: | |
436 | fsc = 0x404; | |
437 | break; | |
438 | case ARMFault_Exclusive: | |
439 | fsc = 0x405; | |
440 | break; | |
441 | case ARMFault_ICacheMaint: | |
442 | fsc = 0x4; | |
443 | break; | |
444 | case ARMFault_Background: | |
445 | fsc = 0x0; | |
446 | break; | |
447 | case ARMFault_QEMU_NSCExec: | |
448 | fsc = M_FAKE_FSR_NSC_EXEC; | |
449 | break; | |
450 | case ARMFault_QEMU_SFault: | |
451 | fsc = M_FAKE_FSR_SFAULT; | |
452 | break; | |
453 | default: | |
454 | /* Other faults can't occur in a context that requires a | |
455 | * short-format status code. | |
456 | */ | |
457 | g_assert_not_reached(); | |
458 | } | |
459 | ||
460 | fsc |= (fi->domain << 4); | |
461 | return fsc; | |
462 | } | |
463 | ||
464 | /** | |
465 | * arm_fi_to_lfsc: Convert fault info struct to long-format FSC | |
466 | * Compare pseudocode EncodeLDFSC(), though unlike that function | |
467 | * we fill in also the LPAE bit 9 of a DFSR format. | |
468 | */ | |
469 | static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) | |
470 | { | |
471 | uint32_t fsc; | |
472 | ||
473 | switch (fi->type) { | |
474 | case ARMFault_None: | |
475 | return 0; | |
476 | case ARMFault_AddressSize: | |
13e481c9 RH |
477 | assert(fi->level >= -1 && fi->level <= 3); |
478 | if (fi->level < 0) { | |
479 | fsc = 0b101001; | |
480 | } else { | |
481 | fsc = fi->level; | |
482 | } | |
1fa498fe PM |
483 | break; |
484 | case ARMFault_AccessFlag: | |
13e481c9 RH |
485 | assert(fi->level >= 0 && fi->level <= 3); |
486 | fsc = 0b001000 | fi->level; | |
1fa498fe PM |
487 | break; |
488 | case ARMFault_Permission: | |
13e481c9 RH |
489 | assert(fi->level >= 0 && fi->level <= 3); |
490 | fsc = 0b001100 | fi->level; | |
1fa498fe PM |
491 | break; |
492 | case ARMFault_Translation: | |
13e481c9 RH |
493 | assert(fi->level >= -1 && fi->level <= 3); |
494 | if (fi->level < 0) { | |
495 | fsc = 0b101011; | |
496 | } else { | |
497 | fsc = 0b000100 | fi->level; | |
498 | } | |
1fa498fe PM |
499 | break; |
500 | case ARMFault_SyncExternal: | |
501 | fsc = 0x10 | (fi->ea << 12); | |
502 | break; | |
503 | case ARMFault_SyncExternalOnWalk: | |
13e481c9 RH |
504 | assert(fi->level >= -1 && fi->level <= 3); |
505 | if (fi->level < 0) { | |
506 | fsc = 0b010011; | |
507 | } else { | |
508 | fsc = 0b010100 | fi->level; | |
509 | } | |
510 | fsc |= fi->ea << 12; | |
1fa498fe PM |
511 | break; |
512 | case ARMFault_SyncParity: | |
513 | fsc = 0x18; | |
514 | break; | |
515 | case ARMFault_SyncParityOnWalk: | |
13e481c9 RH |
516 | assert(fi->level >= -1 && fi->level <= 3); |
517 | if (fi->level < 0) { | |
518 | fsc = 0b011011; | |
519 | } else { | |
520 | fsc = 0b011100 | fi->level; | |
521 | } | |
1fa498fe PM |
522 | break; |
523 | case ARMFault_AsyncParity: | |
524 | fsc = 0x19; | |
525 | break; | |
526 | case ARMFault_AsyncExternal: | |
527 | fsc = 0x11 | (fi->ea << 12); | |
528 | break; | |
529 | case ARMFault_Alignment: | |
530 | fsc = 0x21; | |
531 | break; | |
532 | case ARMFault_Debug: | |
533 | fsc = 0x22; | |
534 | break; | |
535 | case ARMFault_TLBConflict: | |
536 | fsc = 0x30; | |
537 | break; | |
538 | case ARMFault_Lockdown: | |
539 | fsc = 0x34; | |
540 | break; | |
541 | case ARMFault_Exclusive: | |
542 | fsc = 0x35; | |
543 | break; | |
544 | default: | |
545 | /* Other faults can't occur in a context that requires a | |
546 | * long-format status code. | |
547 | */ | |
548 | g_assert_not_reached(); | |
549 | } | |
550 | ||
551 | fsc |= 1 << 9; | |
552 | return fsc; | |
553 | } | |
554 | ||
3b39d734 PM |
555 | static inline bool arm_extabort_type(MemTxResult result) |
556 | { | |
557 | /* The EA bit in syndromes and fault status registers is an | |
558 | * IMPDEF classification of external aborts. ARM implementations | |
559 | * usually use this to indicate AXI bus Decode error (0) or | |
560 | * Slave error (1); in QEMU we follow that. | |
561 | */ | |
562 | return result != MEMTX_DECODE_ERROR; | |
563 | } | |
564 | ||
9b12b6b4 RH |
565 | #ifdef CONFIG_USER_ONLY |
566 | void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, | |
567 | MMUAccessType access_type, | |
568 | bool maperr, uintptr_t ra); | |
39a099ca RH |
569 | void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr, |
570 | MMUAccessType access_type, uintptr_t ra); | |
9b12b6b4 | 571 | #else |
7350d553 RH |
572 | bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
573 | MMUAccessType access_type, int mmu_idx, | |
574 | bool probe, uintptr_t retaddr); | |
9b12b6b4 | 575 | #endif |
7350d553 | 576 | |
b9f6033c RH |
577 | static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) |
578 | { | |
579 | return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; | |
580 | } | |
581 | ||
582 | static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) | |
583 | { | |
584 | if (arm_feature(env, ARM_FEATURE_M)) { | |
585 | return mmu_idx | ARM_MMU_IDX_M; | |
586 | } else { | |
587 | return mmu_idx | ARM_MMU_IDX_A; | |
588 | } | |
589 | } | |
590 | ||
20dc67c9 RH |
591 | static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx) |
592 | { | |
593 | /* AArch64 is always a-profile. */ | |
594 | return mmu_idx | ARM_MMU_IDX_A; | |
595 | } | |
596 | ||
b9f6033c RH |
597 | int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); |
598 | ||
599 | /* | |
600 | * Return the MMU index for a v7M CPU with all relevant information | |
601 | * manually specified. | |
602 | */ | |
603 | ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | |
604 | bool secstate, bool priv, bool negpri); | |
605 | ||
606 | /* | |
607 | * Return the MMU index for a v7M CPU in the specified security and | |
608 | * privilege state. | |
609 | */ | |
610 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, | |
611 | bool secstate, bool priv); | |
612 | ||
613 | /* Return the MMU index for a v7M CPU in the specified security state */ | |
614 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); | |
615 | ||
deb2db99 AR |
616 | /* Return true if the stage 1 translation regime is using LPAE format page |
617 | * tables */ | |
618 | bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); | |
30901475 AB |
619 | |
620 | /* Raise a data fault alignment exception for the specified virtual address */ | |
8905770b MAL |
621 | G_NORETURN void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, |
622 | MMUAccessType access_type, | |
623 | int mmu_idx, uintptr_t retaddr); | |
30901475 | 624 | |
c79c0a31 PM |
625 | /* arm_cpu_do_transaction_failed: handle a memory system error response |
626 | * (eg "no device/memory present at address") by raising an external abort | |
627 | * exception | |
628 | */ | |
629 | void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, | |
630 | vaddr addr, unsigned size, | |
631 | MMUAccessType access_type, | |
632 | int mmu_idx, MemTxAttrs attrs, | |
633 | MemTxResult response, uintptr_t retaddr); | |
634 | ||
08267487 | 635 | /* Call any registered EL change hooks */ |
b5c53d1b AL |
636 | static inline void arm_call_pre_el_change_hook(ARMCPU *cpu) |
637 | { | |
638 | ARMELChangeHook *hook, *next; | |
639 | QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { | |
640 | hook->hook(cpu, hook->opaque); | |
641 | } | |
642 | } | |
bd7d00fc PM |
643 | static inline void arm_call_el_change_hook(ARMCPU *cpu) |
644 | { | |
08267487 AL |
645 | ARMELChangeHook *hook, *next; |
646 | QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { | |
647 | hook->hook(cpu, hook->opaque); | |
bd7d00fc PM |
648 | } |
649 | } | |
650 | ||
339370b9 RH |
651 | /* Return true if this address translation regime has two ranges. */ |
652 | static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) | |
653 | { | |
654 | switch (mmu_idx) { | |
655 | case ARMMMUIdx_Stage1_E0: | |
656 | case ARMMMUIdx_Stage1_E1: | |
452ef8cb | 657 | case ARMMMUIdx_Stage1_E1_PAN: |
b1a10c86 RDC |
658 | case ARMMMUIdx_Stage1_SE0: |
659 | case ARMMMUIdx_Stage1_SE1: | |
660 | case ARMMMUIdx_Stage1_SE1_PAN: | |
339370b9 RH |
661 | case ARMMMUIdx_E10_0: |
662 | case ARMMMUIdx_E10_1: | |
452ef8cb | 663 | case ARMMMUIdx_E10_1_PAN: |
339370b9 RH |
664 | case ARMMMUIdx_E20_0: |
665 | case ARMMMUIdx_E20_2: | |
452ef8cb | 666 | case ARMMMUIdx_E20_2_PAN: |
339370b9 RH |
667 | case ARMMMUIdx_SE10_0: |
668 | case ARMMMUIdx_SE10_1: | |
452ef8cb | 669 | case ARMMMUIdx_SE10_1_PAN: |
b6ad6062 RDC |
670 | case ARMMMUIdx_SE20_0: |
671 | case ARMMMUIdx_SE20_2: | |
672 | case ARMMMUIdx_SE20_2_PAN: | |
339370b9 RH |
673 | return true; |
674 | default: | |
675 | return false; | |
676 | } | |
677 | } | |
678 | ||
61fcd69b PM |
679 | /* Return true if this address translation regime is secure */ |
680 | static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) | |
681 | { | |
682 | switch (mmu_idx) { | |
01b98b68 RH |
683 | case ARMMMUIdx_E10_0: |
684 | case ARMMMUIdx_E10_1: | |
452ef8cb | 685 | case ARMMMUIdx_E10_1_PAN: |
b9f6033c RH |
686 | case ARMMMUIdx_E20_0: |
687 | case ARMMMUIdx_E20_2: | |
452ef8cb | 688 | case ARMMMUIdx_E20_2_PAN: |
2859d7b5 RH |
689 | case ARMMMUIdx_Stage1_E0: |
690 | case ARMMMUIdx_Stage1_E1: | |
452ef8cb | 691 | case ARMMMUIdx_Stage1_E1_PAN: |
e013b741 | 692 | case ARMMMUIdx_E2: |
97fa9350 | 693 | case ARMMMUIdx_Stage2: |
62593718 PM |
694 | case ARMMMUIdx_MPrivNegPri: |
695 | case ARMMMUIdx_MUserNegPri: | |
61fcd69b | 696 | case ARMMMUIdx_MPriv: |
61fcd69b PM |
697 | case ARMMMUIdx_MUser: |
698 | return false; | |
127b2b08 | 699 | case ARMMMUIdx_SE3: |
fba37aed RH |
700 | case ARMMMUIdx_SE10_0: |
701 | case ARMMMUIdx_SE10_1: | |
452ef8cb | 702 | case ARMMMUIdx_SE10_1_PAN: |
b6ad6062 RDC |
703 | case ARMMMUIdx_SE20_0: |
704 | case ARMMMUIdx_SE20_2: | |
705 | case ARMMMUIdx_SE20_2_PAN: | |
b1a10c86 RDC |
706 | case ARMMMUIdx_Stage1_SE0: |
707 | case ARMMMUIdx_Stage1_SE1: | |
708 | case ARMMMUIdx_Stage1_SE1_PAN: | |
b6ad6062 | 709 | case ARMMMUIdx_SE2: |
b1a10c86 | 710 | case ARMMMUIdx_Stage2_S: |
62593718 PM |
711 | case ARMMMUIdx_MSPrivNegPri: |
712 | case ARMMMUIdx_MSUserNegPri: | |
61fcd69b | 713 | case ARMMMUIdx_MSPriv: |
61fcd69b PM |
714 | case ARMMMUIdx_MSUser: |
715 | return true; | |
716 | default: | |
717 | g_assert_not_reached(); | |
718 | } | |
719 | } | |
720 | ||
81636b70 RH |
721 | static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) |
722 | { | |
723 | switch (mmu_idx) { | |
724 | case ARMMMUIdx_Stage1_E1_PAN: | |
b1a10c86 | 725 | case ARMMMUIdx_Stage1_SE1_PAN: |
81636b70 RH |
726 | case ARMMMUIdx_E10_1_PAN: |
727 | case ARMMMUIdx_E20_2_PAN: | |
728 | case ARMMMUIdx_SE10_1_PAN: | |
b6ad6062 | 729 | case ARMMMUIdx_SE20_2_PAN: |
81636b70 RH |
730 | return true; |
731 | default: | |
732 | return false; | |
733 | } | |
734 | } | |
735 | ||
9c7ab8fc RH |
736 | /* Return the exception level which controls this address translation regime */ |
737 | static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) | |
738 | { | |
739 | switch (mmu_idx) { | |
b6ad6062 RDC |
740 | case ARMMMUIdx_SE20_0: |
741 | case ARMMMUIdx_SE20_2: | |
742 | case ARMMMUIdx_SE20_2_PAN: | |
9c7ab8fc RH |
743 | case ARMMMUIdx_E20_0: |
744 | case ARMMMUIdx_E20_2: | |
745 | case ARMMMUIdx_E20_2_PAN: | |
746 | case ARMMMUIdx_Stage2: | |
b1a10c86 | 747 | case ARMMMUIdx_Stage2_S: |
b6ad6062 | 748 | case ARMMMUIdx_SE2: |
9c7ab8fc RH |
749 | case ARMMMUIdx_E2: |
750 | return 2; | |
751 | case ARMMMUIdx_SE3: | |
752 | return 3; | |
753 | case ARMMMUIdx_SE10_0: | |
b1a10c86 | 754 | case ARMMMUIdx_Stage1_SE0: |
9c7ab8fc RH |
755 | return arm_el_is_aa64(env, 3) ? 1 : 3; |
756 | case ARMMMUIdx_SE10_1: | |
757 | case ARMMMUIdx_SE10_1_PAN: | |
758 | case ARMMMUIdx_Stage1_E0: | |
759 | case ARMMMUIdx_Stage1_E1: | |
760 | case ARMMMUIdx_Stage1_E1_PAN: | |
b1a10c86 RDC |
761 | case ARMMMUIdx_Stage1_SE1: |
762 | case ARMMMUIdx_Stage1_SE1_PAN: | |
9c7ab8fc RH |
763 | case ARMMMUIdx_E10_0: |
764 | case ARMMMUIdx_E10_1: | |
765 | case ARMMMUIdx_E10_1_PAN: | |
766 | case ARMMMUIdx_MPrivNegPri: | |
767 | case ARMMMUIdx_MUserNegPri: | |
768 | case ARMMMUIdx_MPriv: | |
769 | case ARMMMUIdx_MUser: | |
770 | case ARMMMUIdx_MSPrivNegPri: | |
771 | case ARMMMUIdx_MSUserNegPri: | |
772 | case ARMMMUIdx_MSPriv: | |
773 | case ARMMMUIdx_MSUser: | |
774 | return 1; | |
775 | default: | |
776 | g_assert_not_reached(); | |
777 | } | |
778 | } | |
779 | ||
38659d31 RH |
780 | /* Return the TCR controlling this translation regime */ |
781 | static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) | |
782 | { | |
783 | if (mmu_idx == ARMMMUIdx_Stage2) { | |
784 | return &env->cp15.vtcr_el2; | |
785 | } | |
b1a10c86 RDC |
786 | if (mmu_idx == ARMMMUIdx_Stage2_S) { |
787 | /* | |
788 | * Note: Secure stage 2 nominally shares fields from VTCR_EL2, but | |
789 | * those are not currently used by QEMU, so just return VSTCR_EL2. | |
790 | */ | |
791 | return &env->cp15.vstcr_el2; | |
792 | } | |
38659d31 RH |
793 | return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; |
794 | } | |
795 | ||
81621d9a PM |
796 | /* Return the FSR value for a debug exception (watchpoint, hardware |
797 | * breakpoint or BKPT insn) targeting the specified exception level. | |
798 | */ | |
799 | static inline uint32_t arm_debug_exception_fsr(CPUARMState *env) | |
800 | { | |
801 | ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; | |
802 | int target_el = arm_debug_target_el(env); | |
803 | bool using_lpae = false; | |
804 | ||
805 | if (target_el == 2 || arm_el_is_aa64(env, target_el)) { | |
806 | using_lpae = true; | |
807 | } else { | |
808 | if (arm_feature(env, ARM_FEATURE_LPAE) && | |
809 | (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { | |
810 | using_lpae = true; | |
811 | } | |
812 | } | |
813 | ||
814 | if (using_lpae) { | |
815 | return arm_fi_to_lfsc(&fi); | |
816 | } else { | |
817 | return arm_fi_to_sfsc(&fi); | |
818 | } | |
819 | } | |
820 | ||
88ce6c6e PM |
821 | /** |
822 | * arm_num_brps: Return number of implemented breakpoints. | |
823 | * Note that the ID register BRPS field is "number of bps - 1", | |
824 | * and we return the actual number of breakpoints. | |
825 | */ | |
826 | static inline int arm_num_brps(ARMCPU *cpu) | |
827 | { | |
828 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
829 | return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1; | |
830 | } else { | |
4426d361 | 831 | return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1; |
88ce6c6e PM |
832 | } |
833 | } | |
834 | ||
835 | /** | |
836 | * arm_num_wrps: Return number of implemented watchpoints. | |
837 | * Note that the ID register WRPS field is "number of wps - 1", | |
838 | * and we return the actual number of watchpoints. | |
839 | */ | |
840 | static inline int arm_num_wrps(ARMCPU *cpu) | |
841 | { | |
842 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
843 | return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1; | |
844 | } else { | |
4426d361 | 845 | return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1; |
88ce6c6e PM |
846 | } |
847 | } | |
848 | ||
849 | /** | |
850 | * arm_num_ctx_cmps: Return number of implemented context comparators. | |
851 | * Note that the ID register CTX_CMPS field is "number of cmps - 1", | |
852 | * and we return the actual number of comparators. | |
853 | */ | |
854 | static inline int arm_num_ctx_cmps(ARMCPU *cpu) | |
855 | { | |
856 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
857 | return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1; | |
858 | } else { | |
4426d361 | 859 | return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1; |
88ce6c6e PM |
860 | } |
861 | } | |
862 | ||
5529bf18 PM |
863 | /** |
864 | * v7m_using_psp: Return true if using process stack pointer | |
865 | * Return true if the CPU is currently using the process stack | |
866 | * pointer, or false if it is using the main stack pointer. | |
867 | */ | |
868 | static inline bool v7m_using_psp(CPUARMState *env) | |
869 | { | |
870 | /* Handler mode always uses the main stack; for thread mode | |
871 | * the CONTROL.SPSEL bit determines the answer. | |
872 | * Note that in v7M it is not possible to be in Handler mode with | |
873 | * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both. | |
874 | */ | |
875 | return !arm_v7m_is_handler_mode(env) && | |
876 | env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; | |
877 | } | |
878 | ||
55203189 PM |
879 | /** |
880 | * v7m_sp_limit: Return SP limit for current CPU state | |
881 | * Return the SP limit value for the current CPU security state | |
882 | * and stack pointer. | |
883 | */ | |
884 | static inline uint32_t v7m_sp_limit(CPUARMState *env) | |
885 | { | |
886 | if (v7m_using_psp(env)) { | |
887 | return env->v7m.psplim[env->v7m.secure]; | |
888 | } else { | |
889 | return env->v7m.msplim[env->v7m.secure]; | |
890 | } | |
891 | } | |
892 | ||
787a7e76 PMD |
893 | /** |
894 | * v7m_cpacr_pass: | |
895 | * Return true if the v7M CPACR permits access to the FPU for the specified | |
896 | * security state and privilege level. | |
897 | */ | |
898 | static inline bool v7m_cpacr_pass(CPUARMState *env, | |
899 | bool is_secure, bool is_priv) | |
900 | { | |
901 | switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { | |
902 | case 0: | |
903 | case 2: /* UNPREDICTABLE: we treat like 0 */ | |
904 | return false; | |
905 | case 1: | |
906 | return is_priv; | |
907 | case 3: | |
908 | return true; | |
909 | default: | |
910 | g_assert_not_reached(); | |
911 | } | |
912 | } | |
913 | ||
81e37284 PM |
914 | /** |
915 | * aarch32_mode_name(): Return name of the AArch32 CPU mode | |
916 | * @psr: Program Status Register indicating CPU mode | |
917 | * | |
918 | * Returns, for debug logging purposes, a printable representation | |
919 | * of the AArch32 CPU mode ("svc", "usr", etc) as indicated by | |
920 | * the low bits of the specified PSR. | |
921 | */ | |
922 | static inline const char *aarch32_mode_name(uint32_t psr) | |
923 | { | |
924 | static const char cpu_mode_names[16][4] = { | |
925 | "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt", | |
926 | "???", "???", "hyp", "und", "???", "???", "???", "sys" | |
927 | }; | |
928 | ||
929 | return cpu_mode_names[psr & 0xf]; | |
930 | } | |
931 | ||
89430fc6 PM |
932 | /** |
933 | * arm_cpu_update_virq: Update CPU_INTERRUPT_VIRQ bit in cs->interrupt_request | |
934 | * | |
935 | * Update the CPU_INTERRUPT_VIRQ bit in cs->interrupt_request, following | |
936 | * a change to either the input VIRQ line from the GIC or the HCR_EL2.VI bit. | |
937 | * Must be called with the iothread lock held. | |
938 | */ | |
939 | void arm_cpu_update_virq(ARMCPU *cpu); | |
940 | ||
941 | /** | |
942 | * arm_cpu_update_vfiq: Update CPU_INTERRUPT_VFIQ bit in cs->interrupt_request | |
943 | * | |
944 | * Update the CPU_INTERRUPT_VFIQ bit in cs->interrupt_request, following | |
945 | * a change to either the input VFIQ line from the GIC or the HCR_EL2.VF bit. | |
946 | * Must be called with the iothread lock held. | |
947 | */ | |
948 | void arm_cpu_update_vfiq(ARMCPU *cpu); | |
949 | ||
164690b2 RH |
950 | /** |
951 | * arm_mmu_idx_el: | |
952 | * @env: The cpu environment | |
953 | * @el: The EL to use. | |
954 | * | |
955 | * Return the full ARMMMUIdx for the translation regime for EL. | |
956 | */ | |
957 | ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el); | |
958 | ||
50494a27 RH |
959 | /** |
960 | * arm_mmu_idx: | |
961 | * @env: The cpu environment | |
962 | * | |
963 | * Return the full ARMMMUIdx for the current translation regime. | |
964 | */ | |
965 | ARMMMUIdx arm_mmu_idx(CPUARMState *env); | |
966 | ||
64be86ab RH |
967 | /** |
968 | * arm_stage1_mmu_idx: | |
969 | * @env: The cpu environment | |
970 | * | |
971 | * Return the ARMMMUIdx for the stage1 traversal for the current regime. | |
972 | */ | |
973 | #ifdef CONFIG_USER_ONLY | |
974 | static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) | |
975 | { | |
2859d7b5 | 976 | return ARMMMUIdx_Stage1_E0; |
64be86ab RH |
977 | } |
978 | #else | |
979 | ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); | |
980 | #endif | |
981 | ||
fee7aa46 RH |
982 | /** |
983 | * arm_mmu_idx_is_stage1_of_2: | |
984 | * @mmu_idx: The ARMMMUIdx to test | |
985 | * | |
986 | * Return true if @mmu_idx is a NOTLB mmu_idx that is the | |
987 | * first stage of a two stage regime. | |
988 | */ | |
989 | static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) | |
990 | { | |
991 | switch (mmu_idx) { | |
992 | case ARMMMUIdx_Stage1_E0: | |
993 | case ARMMMUIdx_Stage1_E1: | |
452ef8cb | 994 | case ARMMMUIdx_Stage1_E1_PAN: |
b1a10c86 RDC |
995 | case ARMMMUIdx_Stage1_SE0: |
996 | case ARMMMUIdx_Stage1_SE1: | |
997 | case ARMMMUIdx_Stage1_SE1_PAN: | |
fee7aa46 RH |
998 | return true; |
999 | default: | |
1000 | return false; | |
1001 | } | |
1002 | } | |
1003 | ||
4f9584ed RH |
1004 | static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, |
1005 | const ARMISARegisters *id) | |
1006 | { | |
f062d144 | 1007 | uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV; |
4f9584ed RH |
1008 | |
1009 | if ((features >> ARM_FEATURE_V4T) & 1) { | |
1010 | valid |= CPSR_T; | |
1011 | } | |
1012 | if ((features >> ARM_FEATURE_V5) & 1) { | |
1013 | valid |= CPSR_Q; /* V5TE in reality*/ | |
1014 | } | |
1015 | if ((features >> ARM_FEATURE_V6) & 1) { | |
1016 | valid |= CPSR_E | CPSR_GE; | |
1017 | } | |
1018 | if ((features >> ARM_FEATURE_THUMB2) & 1) { | |
1019 | valid |= CPSR_IT; | |
1020 | } | |
873b73c0 | 1021 | if (isar_feature_aa32_jazelle(id)) { |
f062d144 RH |
1022 | valid |= CPSR_J; |
1023 | } | |
220f508f RH |
1024 | if (isar_feature_aa32_pan(id)) { |
1025 | valid |= CPSR_PAN; | |
1026 | } | |
dc8b1853 RC |
1027 | if (isar_feature_aa32_dit(id)) { |
1028 | valid |= CPSR_DIT; | |
1029 | } | |
f2f68a78 RC |
1030 | if (isar_feature_aa32_ssbs(id)) { |
1031 | valid |= CPSR_SSBS; | |
1032 | } | |
4f9584ed RH |
1033 | |
1034 | return valid; | |
1035 | } | |
1036 | ||
14084511 RH |
1037 | static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) |
1038 | { | |
1039 | uint32_t valid; | |
1040 | ||
1041 | valid = PSTATE_M | PSTATE_DAIF | PSTATE_IL | PSTATE_SS | PSTATE_NZCV; | |
1042 | if (isar_feature_aa64_bti(id)) { | |
1043 | valid |= PSTATE_BTYPE; | |
1044 | } | |
220f508f RH |
1045 | if (isar_feature_aa64_pan(id)) { |
1046 | valid |= PSTATE_PAN; | |
1047 | } | |
9eeb7a1c RH |
1048 | if (isar_feature_aa64_uao(id)) { |
1049 | valid |= PSTATE_UAO; | |
1050 | } | |
dc8b1853 RC |
1051 | if (isar_feature_aa64_dit(id)) { |
1052 | valid |= PSTATE_DIT; | |
1053 | } | |
f2f68a78 RC |
1054 | if (isar_feature_aa64_ssbs(id)) { |
1055 | valid |= PSTATE_SSBS; | |
1056 | } | |
4b779ceb RH |
1057 | if (isar_feature_aa64_mte(id)) { |
1058 | valid |= PSTATE_TCO; | |
1059 | } | |
14084511 RH |
1060 | |
1061 | return valid; | |
1062 | } | |
1063 | ||
ba97be9f RH |
1064 | /* |
1065 | * Parameters of a given virtual address, as extracted from the | |
1066 | * translation control register (TCR) for a given regime. | |
1067 | */ | |
1068 | typedef struct ARMVAParameters { | |
1069 | unsigned tsz : 8; | |
f4ecc015 | 1070 | unsigned ps : 3; |
ef56c242 | 1071 | unsigned sh : 2; |
ba97be9f RH |
1072 | unsigned select : 1; |
1073 | bool tbi : 1; | |
1074 | bool epd : 1; | |
1075 | bool hpd : 1; | |
1076 | bool using16k : 1; | |
1077 | bool using64k : 1; | |
ebf93ce7 | 1078 | bool tsz_oob : 1; /* tsz has been clamped to legal range */ |
ef56c242 | 1079 | bool ds : 1; |
ba97be9f RH |
1080 | } ARMVAParameters; |
1081 | ||
bf0be433 RH |
1082 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, |
1083 | ARMMMUIdx mmu_idx, bool data); | |
bf0be433 | 1084 | |
ff730e96 RH |
1085 | static inline int exception_target_el(CPUARMState *env) |
1086 | { | |
1087 | int target_el = MAX(1, arm_current_el(env)); | |
1088 | ||
1089 | /* | |
1090 | * No such thing as secure EL1 if EL3 is aarch32, | |
1091 | * so update the target EL to EL3 in this case. | |
1092 | */ | |
1093 | if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { | |
1094 | target_el = 3; | |
1095 | } | |
1096 | ||
1097 | return target_el; | |
1098 | } | |
1099 | ||
81ae05fa RH |
1100 | /* Determine if allocation tags are available. */ |
1101 | static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, | |
1102 | uint64_t sctlr) | |
1103 | { | |
1104 | if (el < 3 | |
1105 | && arm_feature(env, ARM_FEATURE_EL3) | |
1106 | && !(env->cp15.scr_el3 & SCR_ATA)) { | |
1107 | return false; | |
1108 | } | |
0da067f2 | 1109 | if (el < 2 && arm_is_el2_enabled(env)) { |
4301acd7 RH |
1110 | uint64_t hcr = arm_hcr_el2_eff(env); |
1111 | if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { | |
1112 | return false; | |
1113 | } | |
81ae05fa RH |
1114 | } |
1115 | sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA); | |
1116 | return sctlr != 0; | |
1117 | } | |
1118 | ||
ebae861f PMD |
1119 | #ifndef CONFIG_USER_ONLY |
1120 | ||
787a7e76 PMD |
1121 | /* Security attributes for an address, as returned by v8m_security_lookup. */ |
1122 | typedef struct V8M_SAttributes { | |
1123 | bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */ | |
1124 | bool ns; | |
1125 | bool nsc; | |
1126 | uint8_t sregion; | |
1127 | bool srvalid; | |
1128 | uint8_t iregion; | |
1129 | bool irvalid; | |
1130 | } V8M_SAttributes; | |
1131 | ||
1132 | void v8m_security_lookup(CPUARMState *env, uint32_t address, | |
1133 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
1134 | V8M_SAttributes *sattrs); | |
1135 | ||
1136 | bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, | |
1137 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
1138 | hwaddr *phys_ptr, MemTxAttrs *txattrs, | |
1139 | int *prot, bool *is_subpage, | |
1140 | ARMMMUFaultInfo *fi, uint32_t *mregion); | |
1141 | ||
ebae861f PMD |
1142 | /* Cacheability and shareability attributes for a memory access */ |
1143 | typedef struct ARMCacheAttrs { | |
1144 | unsigned int attrs:8; /* as in the MAIR register encoding */ | |
1145 | unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */ | |
1146 | } ARMCacheAttrs; | |
1147 | ||
1148 | bool get_phys_addr(CPUARMState *env, target_ulong address, | |
1149 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
1150 | hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, | |
1151 | target_ulong *page_size, | |
7e98e21c RH |
1152 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) |
1153 | __attribute__((nonnull)); | |
ebae861f | 1154 | |
fc6177af | 1155 | void arm_log_exception(CPUState *cs); |
b59f479b | 1156 | |
ebae861f PMD |
1157 | #endif /* !CONFIG_USER_ONLY */ |
1158 | ||
4b779ceb RH |
1159 | /* |
1160 | * The log2 of the words in the tag block, for GMID_EL1.BS. | |
1161 | * The is the maximum, 256 bytes, which manipulates 64-bits of tags. | |
1162 | */ | |
1163 | #define GMID_EL1_BS 6 | |
1164 | ||
efbc78ad RH |
1165 | /* We associate one allocation tag per 16 bytes, the minimum. */ |
1166 | #define LOG2_TAG_GRANULE 4 | |
1167 | #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) | |
1168 | ||
b64ee454 RH |
1169 | /* |
1170 | * SVE predicates are 1/8 the size of SVE vectors, and cannot use | |
1171 | * the same simd_desc() encoding due to restrictions on size. | |
1172 | * Use these instead. | |
1173 | */ | |
1174 | FIELD(PREDDESC, OPRSZ, 0, 6) | |
1175 | FIELD(PREDDESC, ESZ, 6, 2) | |
1176 | FIELD(PREDDESC, DATA, 8, 24) | |
1177 | ||
206adacf RH |
1178 | /* |
1179 | * The SVE simd_data field, for memory ops, contains either | |
1180 | * rd (5 bits) or a shift count (2 bits). | |
1181 | */ | |
1182 | #define SVE_MTEDESC_SHIFT 5 | |
1183 | ||
0a405be2 RH |
1184 | /* Bits within a descriptor passed to the helper_mte_check* functions. */ |
1185 | FIELD(MTEDESC, MIDX, 0, 4) | |
1186 | FIELD(MTEDESC, TBI, 4, 2) | |
1187 | FIELD(MTEDESC, TCMA, 6, 2) | |
1188 | FIELD(MTEDESC, WRITE, 8, 1) | |
28f32503 | 1189 | FIELD(MTEDESC, SIZEM1, 9, SIMD_DATA_BITS - 9) /* size - 1 */ |
0a405be2 | 1190 | |
d304d280 | 1191 | bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr); |
bd47b61c | 1192 | uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra); |
2e34ff45 | 1193 | |
efbc78ad RH |
1194 | static inline int allocation_tag_from_addr(uint64_t ptr) |
1195 | { | |
1196 | return extract64(ptr, 56, 4); | |
1197 | } | |
1198 | ||
da54941f RH |
1199 | static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) |
1200 | { | |
1201 | return deposit64(ptr, 56, 4, rtag); | |
1202 | } | |
1203 | ||
2e34ff45 RH |
1204 | /* Return true if tbi bits mean that the access is checked. */ |
1205 | static inline bool tbi_check(uint32_t desc, int bit55) | |
1206 | { | |
1207 | return (desc >> (R_MTEDESC_TBI_SHIFT + bit55)) & 1; | |
1208 | } | |
1209 | ||
1210 | /* Return true if tcma bits mean that the access is unchecked. */ | |
1211 | static inline bool tcma_check(uint32_t desc, int bit55, int ptr_tag) | |
1212 | { | |
1213 | /* | |
1214 | * We had extracted bit55 and ptr_tag for other reasons, so fold | |
1215 | * (ptr<59:55> == 00000 || ptr<59:55> == 11111) into a single test. | |
1216 | */ | |
1217 | bool match = ((ptr_tag + bit55) & 0xf) == 0; | |
1218 | bool tcma = (desc >> (R_MTEDESC_TCMA_SHIFT + bit55)) & 1; | |
1219 | return tcma && match; | |
1220 | } | |
1221 | ||
1222 | /* | |
1223 | * For TBI, ideally, we would do nothing. Proper behaviour on fault is | |
1224 | * for the tag to be present in the FAR_ELx register. But for user-only | |
1225 | * mode, we do not have a TLB with which to implement this, so we must | |
1226 | * remove the top byte. | |
1227 | */ | |
1228 | static inline uint64_t useronly_clean_ptr(uint64_t ptr) | |
1229 | { | |
2e34ff45 | 1230 | #ifdef CONFIG_USER_ONLY |
16c84978 RH |
1231 | /* TBI0 is known to be enabled, while TBI1 is disabled. */ |
1232 | ptr &= sextract64(ptr, 0, 56); | |
2e34ff45 RH |
1233 | #endif |
1234 | return ptr; | |
1235 | } | |
1236 | ||
1237 | static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc, uint64_t ptr) | |
1238 | { | |
1239 | #ifdef CONFIG_USER_ONLY | |
1240 | int64_t clean_ptr = sextract64(ptr, 0, 56); | |
1241 | if (tbi_check(desc, clean_ptr < 0)) { | |
1242 | ptr = clean_ptr; | |
1243 | } | |
1244 | #endif | |
1245 | return ptr; | |
1246 | } | |
1247 | ||
507b6a50 PM |
1248 | /* Values for M-profile PSR.ECI for MVE insns */ |
1249 | enum MVEECIState { | |
1250 | ECI_NONE = 0, /* No completed beats */ | |
1251 | ECI_A0 = 1, /* Completed: A0 */ | |
1252 | ECI_A0A1 = 2, /* Completed: A0, A1 */ | |
1253 | /* 3 is reserved */ | |
1254 | ECI_A0A1A2 = 4, /* Completed: A0, A1, A2 */ | |
1255 | ECI_A0A1A2B0 = 5, /* Completed: A0, A1, A2, B0 */ | |
1256 | /* All other values reserved */ | |
1257 | }; | |
1258 | ||
0130895d AG |
1259 | /* Definitions for the PMU registers */ |
1260 | #define PMCRN_MASK 0xf800 | |
1261 | #define PMCRN_SHIFT 11 | |
1262 | #define PMCRLC 0x40 | |
1263 | #define PMCRDP 0x20 | |
1264 | #define PMCRX 0x10 | |
1265 | #define PMCRD 0x8 | |
1266 | #define PMCRC 0x4 | |
1267 | #define PMCRP 0x2 | |
1268 | #define PMCRE 0x1 | |
1269 | /* | |
1270 | * Mask of PMCR bits writeable by guest (not including WO bits like C, P, | |
1271 | * which can be written as 1 to trigger behaviour but which stay RAZ). | |
1272 | */ | |
1273 | #define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) | |
1274 | ||
1275 | #define PMXEVTYPER_P 0x80000000 | |
1276 | #define PMXEVTYPER_U 0x40000000 | |
1277 | #define PMXEVTYPER_NSK 0x20000000 | |
1278 | #define PMXEVTYPER_NSU 0x10000000 | |
1279 | #define PMXEVTYPER_NSH 0x08000000 | |
1280 | #define PMXEVTYPER_M 0x04000000 | |
1281 | #define PMXEVTYPER_MT 0x02000000 | |
1282 | #define PMXEVTYPER_EVTCOUNT 0x0000ffff | |
1283 | #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \ | |
1284 | PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ | |
1285 | PMXEVTYPER_M | PMXEVTYPER_MT | \ | |
1286 | PMXEVTYPER_EVTCOUNT) | |
1287 | ||
1288 | #define PMCCFILTR 0xf8000000 | |
1289 | #define PMCCFILTR_M PMXEVTYPER_M | |
1290 | #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) | |
1291 | ||
1292 | static inline uint32_t pmu_num_counters(CPUARMState *env) | |
1293 | { | |
1294 | return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; | |
1295 | } | |
1296 | ||
1297 | /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ | |
1298 | static inline uint64_t pmu_counter_mask(CPUARMState *env) | |
1299 | { | |
1300 | return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); | |
1301 | } | |
1302 | ||
89f4f20e PM |
1303 | #ifdef TARGET_AARCH64 |
1304 | int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg); | |
1305 | int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg); | |
1306 | int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); | |
1307 | int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); | |
1308 | #endif | |
1309 | ||
7c1aaf98 RH |
1310 | #ifdef CONFIG_USER_ONLY |
1311 | static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } | |
1312 | #else | |
1313 | void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); | |
1314 | #endif | |
1315 | ||
ccd38087 | 1316 | #endif |