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ccd38087 PM |
1 | /* |
2 | * QEMU ARM CPU -- internal functions and types | |
3 | * | |
4 | * Copyright (c) 2014 Linaro Ltd | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | * | |
20 | * This header defines functions, types, etc which need to be shared | |
fcf5ef2a | 21 | * between different source files within target/arm/ but which are |
ccd38087 PM |
22 | * private to it and not required by the rest of QEMU. |
23 | */ | |
24 | ||
25 | #ifndef TARGET_ARM_INTERNALS_H | |
26 | #define TARGET_ARM_INTERNALS_H | |
27 | ||
abc24d86 | 28 | #include "hw/registerfields.h" |
28f32503 | 29 | #include "tcg/tcg-gvec-desc.h" |
1fe27859 | 30 | #include "syndrome.h" |
abc24d86 | 31 | |
99a99c1f SB |
32 | /* register banks for CPU modes */ |
33 | #define BANK_USRSYS 0 | |
34 | #define BANK_SVC 1 | |
35 | #define BANK_ABT 2 | |
36 | #define BANK_UND 3 | |
37 | #define BANK_IRQ 4 | |
38 | #define BANK_FIQ 5 | |
39 | #define BANK_HYP 6 | |
40 | #define BANK_MON 7 | |
41 | ||
d4a2dc67 PM |
42 | static inline bool excp_is_internal(int excp) |
43 | { | |
44 | /* Return true if this exception number represents a QEMU-internal | |
45 | * exception that will not be passed to the guest. | |
46 | */ | |
47 | return excp == EXCP_INTERRUPT | |
48 | || excp == EXCP_HLT | |
49 | || excp == EXCP_DEBUG | |
50 | || excp == EXCP_HALTED | |
51 | || excp == EXCP_EXCEPTION_EXIT | |
52 | || excp == EXCP_KERNEL_TRAP | |
05188cc7 | 53 | || excp == EXCP_SEMIHOST; |
d4a2dc67 PM |
54 | } |
55 | ||
ccd38087 PM |
56 | /* Scale factor for generic timers, ie number of ns per tick. |
57 | * This gives a 62.5MHz timer. | |
58 | */ | |
59 | #define GTIMER_SCALE 16 | |
60 | ||
abc24d86 MD |
61 | /* Bit definitions for the v7M CONTROL register */ |
62 | FIELD(V7M_CONTROL, NPRIV, 0, 1) | |
63 | FIELD(V7M_CONTROL, SPSEL, 1, 1) | |
64 | FIELD(V7M_CONTROL, FPCA, 2, 1) | |
3e3fa230 | 65 | FIELD(V7M_CONTROL, SFPA, 3, 1) |
abc24d86 | 66 | |
4d1e7a47 PM |
67 | /* Bit definitions for v7M exception return payload */ |
68 | FIELD(V7M_EXCRET, ES, 0, 1) | |
69 | FIELD(V7M_EXCRET, RES0, 1, 1) | |
70 | FIELD(V7M_EXCRET, SPSEL, 2, 1) | |
71 | FIELD(V7M_EXCRET, MODE, 3, 1) | |
72 | FIELD(V7M_EXCRET, FTYPE, 4, 1) | |
73 | FIELD(V7M_EXCRET, DCRS, 5, 1) | |
74 | FIELD(V7M_EXCRET, S, 6, 1) | |
75 | FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ | |
76 | ||
d02a8698 PM |
77 | /* Minimum value which is a magic number for exception return */ |
78 | #define EXC_RETURN_MIN_MAGIC 0xff000000 | |
79 | /* Minimum number which is a magic number for function or exception return | |
80 | * when using v8M security extension | |
81 | */ | |
82 | #define FNC_RETURN_MIN_MAGIC 0xfefffffe | |
83 | ||
8b7a5bbe RH |
84 | /* Bit definitions for DBGWCRn and DBGWCRn_EL1 */ |
85 | FIELD(DBGWCR, E, 0, 1) | |
86 | FIELD(DBGWCR, PAC, 1, 2) | |
87 | FIELD(DBGWCR, LSC, 3, 2) | |
88 | FIELD(DBGWCR, BAS, 5, 8) | |
89 | FIELD(DBGWCR, HMC, 13, 1) | |
90 | FIELD(DBGWCR, SSC, 14, 2) | |
91 | FIELD(DBGWCR, LBN, 16, 4) | |
92 | FIELD(DBGWCR, WT, 20, 1) | |
93 | FIELD(DBGWCR, MASK, 24, 5) | |
94 | FIELD(DBGWCR, SSCE, 29, 1) | |
95 | ||
35337cc3 PM |
96 | /* We use a few fake FSR values for internal purposes in M profile. |
97 | * M profile cores don't have A/R format FSRs, but currently our | |
98 | * get_phys_addr() code assumes A/R profile and reports failures via | |
99 | * an A/R format FSR value. We then translate that into the proper | |
100 | * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt(). | |
101 | * Mostly the FSR values we use for this are those defined for v7PMSA, | |
102 | * since we share some of that codepath. A few kinds of fault are | |
103 | * only for M profile and have no A/R equivalent, though, so we have | |
104 | * to pick a value from the reserved range (which we never otherwise | |
105 | * generate) to use for these. | |
106 | * These values will never be visible to the guest. | |
107 | */ | |
108 | #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */ | |
109 | #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */ | |
110 | ||
597610eb PM |
111 | /** |
112 | * raise_exception: Raise the specified exception. | |
113 | * Raise a guest exception with the specified value, syndrome register | |
114 | * and target exception level. This should be called from helper functions, | |
115 | * and never returns because we will longjump back up to the CPU main loop. | |
116 | */ | |
8905770b MAL |
117 | G_NORETURN void raise_exception(CPUARMState *env, uint32_t excp, |
118 | uint32_t syndrome, uint32_t target_el); | |
597610eb | 119 | |
7469f6c6 RH |
120 | /* |
121 | * Similarly, but also use unwinding to restore cpu state. | |
122 | */ | |
8905770b | 123 | G_NORETURN void raise_exception_ra(CPUARMState *env, uint32_t excp, |
7469f6c6 RH |
124 | uint32_t syndrome, uint32_t target_el, |
125 | uintptr_t ra); | |
126 | ||
2a923c4d EI |
127 | /* |
128 | * For AArch64, map a given EL to an index in the banked_spsr array. | |
7847f9ea PM |
129 | * Note that this mapping and the AArch32 mapping defined in bank_number() |
130 | * must agree such that the AArch64<->AArch32 SPSRs have the architecturally | |
131 | * mandated mapping between each other. | |
2a923c4d EI |
132 | */ |
133 | static inline unsigned int aarch64_banked_spsr_index(unsigned int el) | |
134 | { | |
135 | static const unsigned int map[4] = { | |
99a99c1f SB |
136 | [1] = BANK_SVC, /* EL1. */ |
137 | [2] = BANK_HYP, /* EL2. */ | |
138 | [3] = BANK_MON, /* EL3. */ | |
2a923c4d EI |
139 | }; |
140 | assert(el >= 1 && el <= 3); | |
141 | return map[el]; | |
142 | } | |
143 | ||
c766568d PM |
144 | /* Map CPU modes onto saved register banks. */ |
145 | static inline int bank_number(int mode) | |
146 | { | |
147 | switch (mode) { | |
148 | case ARM_CPU_MODE_USR: | |
149 | case ARM_CPU_MODE_SYS: | |
150 | return BANK_USRSYS; | |
151 | case ARM_CPU_MODE_SVC: | |
152 | return BANK_SVC; | |
153 | case ARM_CPU_MODE_ABT: | |
154 | return BANK_ABT; | |
155 | case ARM_CPU_MODE_UND: | |
156 | return BANK_UND; | |
157 | case ARM_CPU_MODE_IRQ: | |
158 | return BANK_IRQ; | |
159 | case ARM_CPU_MODE_FIQ: | |
160 | return BANK_FIQ; | |
161 | case ARM_CPU_MODE_HYP: | |
162 | return BANK_HYP; | |
163 | case ARM_CPU_MODE_MON: | |
164 | return BANK_MON; | |
165 | } | |
166 | g_assert_not_reached(); | |
167 | } | |
168 | ||
593cfa2b PM |
169 | /** |
170 | * r14_bank_number: Map CPU mode onto register bank for r14 | |
171 | * | |
172 | * Given an AArch32 CPU mode, return the index into the saved register | |
173 | * banks to use for the R14 (LR) in that mode. This is the same as | |
174 | * bank_number(), except for the special case of Hyp mode, where | |
175 | * R14 is shared with USR and SYS, unlike its R13 and SPSR. | |
176 | * This should be used as the index into env->banked_r14[], and | |
177 | * bank_number() used for the index into env->banked_r13[] and | |
178 | * env->banked_spsr[]. | |
179 | */ | |
180 | static inline int r14_bank_number(int mode) | |
181 | { | |
182 | return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode); | |
183 | } | |
184 | ||
ccd38087 PM |
185 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); |
186 | void arm_translate_init(void); | |
187 | ||
475e56b6 EE |
188 | void arm_restore_state_to_opc(CPUState *cs, |
189 | const TranslationBlock *tb, | |
190 | const uint64_t *data); | |
191 | ||
78271684 | 192 | #ifdef CONFIG_TCG |
8349d2ae | 193 | void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); |
78271684 CF |
194 | #endif /* CONFIG_TCG */ |
195 | ||
ccd38087 PM |
196 | enum arm_fprounding { |
197 | FPROUNDING_TIEEVEN, | |
198 | FPROUNDING_POSINF, | |
199 | FPROUNDING_NEGINF, | |
200 | FPROUNDING_ZERO, | |
201 | FPROUNDING_TIEAWAY, | |
202 | FPROUNDING_ODD | |
203 | }; | |
204 | ||
205 | int arm_rmode_to_sf(int rmode); | |
206 | ||
9208b961 EI |
207 | static inline void aarch64_save_sp(CPUARMState *env, int el) |
208 | { | |
209 | if (env->pstate & PSTATE_SP) { | |
210 | env->sp_el[el] = env->xregs[31]; | |
211 | } else { | |
212 | env->sp_el[0] = env->xregs[31]; | |
213 | } | |
214 | } | |
215 | ||
216 | static inline void aarch64_restore_sp(CPUARMState *env, int el) | |
217 | { | |
218 | if (env->pstate & PSTATE_SP) { | |
219 | env->xregs[31] = env->sp_el[el]; | |
220 | } else { | |
221 | env->xregs[31] = env->sp_el[0]; | |
222 | } | |
223 | } | |
224 | ||
f502cfc2 PM |
225 | static inline void update_spsel(CPUARMState *env, uint32_t imm) |
226 | { | |
dcbff19b | 227 | unsigned int cur_el = arm_current_el(env); |
f502cfc2 PM |
228 | /* Update PSTATE SPSel bit; this requires us to update the |
229 | * working stack pointer in xregs[31]. | |
230 | */ | |
231 | if (!((imm ^ env->pstate) & PSTATE_SP)) { | |
232 | return; | |
233 | } | |
9208b961 | 234 | aarch64_save_sp(env, cur_el); |
f502cfc2 PM |
235 | env->pstate = deposit32(env->pstate, 0, 1, imm); |
236 | ||
61d4b215 EI |
237 | /* We rely on illegal updates to SPsel from EL0 to get trapped |
238 | * at translation time. | |
f502cfc2 | 239 | */ |
61d4b215 | 240 | assert(cur_el >= 1 && cur_el <= 3); |
9208b961 | 241 | aarch64_restore_sp(env, cur_el); |
f502cfc2 PM |
242 | } |
243 | ||
1853d5a9 EI |
244 | /* |
245 | * arm_pamax | |
246 | * @cpu: ARMCPU | |
247 | * | |
248 | * Returns the implementation defined bit-width of physical addresses. | |
249 | * The ARMv8 reference manuals refer to this as PAMax(). | |
250 | */ | |
71a77257 | 251 | unsigned int arm_pamax(ARMCPU *cpu); |
1853d5a9 | 252 | |
73c5211b PM |
253 | /* Return true if extended addresses are enabled. |
254 | * This is always the case if our translation regime is 64 bit, | |
255 | * but depends on TTBCR.EAE for 32 bit. | |
256 | */ | |
257 | static inline bool extended_addresses_enabled(CPUARMState *env) | |
258 | { | |
cb4a0a34 | 259 | uint64_t tcr = env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1]; |
452c67a4 TR |
260 | if (arm_feature(env, ARM_FEATURE_PMSA) && |
261 | arm_feature(env, ARM_FEATURE_V8)) { | |
262 | return true; | |
263 | } | |
11f136ee | 264 | return arm_el_is_aa64(env, 1) || |
cb4a0a34 | 265 | (arm_feature(env, ARM_FEATURE_LPAE) && (tcr & TTBCR_EAE)); |
73c5211b PM |
266 | } |
267 | ||
9ee98ce8 PM |
268 | /* Update a QEMU watchpoint based on the information the guest has set in the |
269 | * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers. | |
270 | */ | |
271 | void hw_watchpoint_update(ARMCPU *cpu, int n); | |
272 | /* Update the QEMU watchpoints for every guest watchpoint. This does a | |
273 | * complete delete-and-reinstate of the QEMU watchpoint list and so is | |
274 | * suitable for use after migration or on reset. | |
275 | */ | |
276 | void hw_watchpoint_update_all(ARMCPU *cpu); | |
46747d15 PM |
277 | /* Update a QEMU breakpoint based on the information the guest has set in the |
278 | * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers. | |
279 | */ | |
280 | void hw_breakpoint_update(ARMCPU *cpu, int n); | |
281 | /* Update the QEMU breakpoints for every guest breakpoint. This does a | |
282 | * complete delete-and-reinstate of the QEMU breakpoint list and so is | |
283 | * suitable for use after migration or on reset. | |
284 | */ | |
285 | void hw_breakpoint_update_all(ARMCPU *cpu); | |
9ee98ce8 | 286 | |
b00d86bc RH |
287 | /* Callback function for checking if a breakpoint should trigger. */ |
288 | bool arm_debug_check_breakpoint(CPUState *cs); | |
289 | ||
3826121d SF |
290 | /* Callback function for checking if a watchpoint should trigger. */ |
291 | bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); | |
292 | ||
40612000 JB |
293 | /* Adjust addresses (in BE32 mode) before testing against watchpoint |
294 | * addresses. | |
295 | */ | |
296 | vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len); | |
297 | ||
3ff6fc91 PM |
298 | /* Callback function for when a watchpoint or breakpoint triggers. */ |
299 | void arm_debug_excp_handler(CPUState *cs); | |
300 | ||
21fbea8c | 301 | #if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG) |
98128601 RH |
302 | static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type) |
303 | { | |
304 | return false; | |
305 | } | |
21fbea8c PMD |
306 | static inline void arm_handle_psci_call(ARMCPU *cpu) |
307 | { | |
308 | g_assert_not_reached(); | |
309 | } | |
98128601 RH |
310 | #else |
311 | /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */ | |
312 | bool arm_is_psci_call(ARMCPU *cpu, int excp_type); | |
313 | /* Actually handle a PSCI call */ | |
314 | void arm_handle_psci_call(ARMCPU *cpu); | |
315 | #endif | |
316 | ||
dc3c4c14 PM |
317 | /** |
318 | * arm_clear_exclusive: clear the exclusive monitor | |
319 | * @env: CPU env | |
320 | * Clear the CPU's exclusive monitor, like the guest CLREX instruction. | |
321 | */ | |
322 | static inline void arm_clear_exclusive(CPUARMState *env) | |
323 | { | |
324 | env->exclusive_addr = -1; | |
325 | } | |
326 | ||
1fa498fe PM |
327 | /** |
328 | * ARMFaultType: type of an ARM MMU fault | |
329 | * This corresponds to the v8A pseudocode's Fault enumeration, | |
330 | * with extensions for QEMU internal conditions. | |
331 | */ | |
332 | typedef enum ARMFaultType { | |
333 | ARMFault_None, | |
334 | ARMFault_AccessFlag, | |
335 | ARMFault_Alignment, | |
336 | ARMFault_Background, | |
337 | ARMFault_Domain, | |
338 | ARMFault_Permission, | |
339 | ARMFault_Translation, | |
340 | ARMFault_AddressSize, | |
341 | ARMFault_SyncExternal, | |
342 | ARMFault_SyncExternalOnWalk, | |
343 | ARMFault_SyncParity, | |
344 | ARMFault_SyncParityOnWalk, | |
345 | ARMFault_AsyncParity, | |
346 | ARMFault_AsyncExternal, | |
347 | ARMFault_Debug, | |
348 | ARMFault_TLBConflict, | |
f0a398a2 | 349 | ARMFault_UnsuppAtomicUpdate, |
1fa498fe PM |
350 | ARMFault_Lockdown, |
351 | ARMFault_Exclusive, | |
352 | ARMFault_ICacheMaint, | |
353 | ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */ | |
354 | ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */ | |
355 | } ARMFaultType; | |
356 | ||
e14b5a23 EI |
357 | /** |
358 | * ARMMMUFaultInfo: Information describing an ARM MMU Fault | |
1fa498fe PM |
359 | * @type: Type of fault |
360 | * @level: Table walk level (for translation, access flag and permission faults) | |
361 | * @domain: Domain of the fault address (for non-LPAE CPUs only) | |
e14b5a23 EI |
362 | * @s2addr: Address that caused a fault at stage 2 |
363 | * @stage2: True if we faulted at stage 2 | |
364 | * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk | |
9861248f | 365 | * @s1ns: True if we faulted on a non-secure IPA while in secure state |
c528af7a | 366 | * @ea: True if we should set the EA (external abort type) bit in syndrome |
e14b5a23 EI |
367 | */ |
368 | typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; | |
369 | struct ARMMMUFaultInfo { | |
1fa498fe | 370 | ARMFaultType type; |
e14b5a23 | 371 | target_ulong s2addr; |
1fa498fe PM |
372 | int level; |
373 | int domain; | |
e14b5a23 EI |
374 | bool stage2; |
375 | bool s1ptw; | |
9861248f | 376 | bool s1ns; |
c528af7a | 377 | bool ea; |
e14b5a23 EI |
378 | }; |
379 | ||
1fa498fe PM |
380 | /** |
381 | * arm_fi_to_sfsc: Convert fault info struct to short-format FSC | |
382 | * Compare pseudocode EncodeSDFSC(), though unlike that function | |
383 | * we set up a whole FSR-format code including domain field and | |
384 | * putting the high bit of the FSC into bit 10. | |
385 | */ | |
386 | static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo *fi) | |
387 | { | |
388 | uint32_t fsc; | |
389 | ||
390 | switch (fi->type) { | |
391 | case ARMFault_None: | |
392 | return 0; | |
393 | case ARMFault_AccessFlag: | |
394 | fsc = fi->level == 1 ? 0x3 : 0x6; | |
395 | break; | |
396 | case ARMFault_Alignment: | |
397 | fsc = 0x1; | |
398 | break; | |
399 | case ARMFault_Permission: | |
400 | fsc = fi->level == 1 ? 0xd : 0xf; | |
401 | break; | |
402 | case ARMFault_Domain: | |
403 | fsc = fi->level == 1 ? 0x9 : 0xb; | |
404 | break; | |
405 | case ARMFault_Translation: | |
406 | fsc = fi->level == 1 ? 0x5 : 0x7; | |
407 | break; | |
408 | case ARMFault_SyncExternal: | |
409 | fsc = 0x8 | (fi->ea << 12); | |
410 | break; | |
411 | case ARMFault_SyncExternalOnWalk: | |
412 | fsc = fi->level == 1 ? 0xc : 0xe; | |
413 | fsc |= (fi->ea << 12); | |
414 | break; | |
415 | case ARMFault_SyncParity: | |
416 | fsc = 0x409; | |
417 | break; | |
418 | case ARMFault_SyncParityOnWalk: | |
419 | fsc = fi->level == 1 ? 0x40c : 0x40e; | |
420 | break; | |
421 | case ARMFault_AsyncParity: | |
422 | fsc = 0x408; | |
423 | break; | |
424 | case ARMFault_AsyncExternal: | |
425 | fsc = 0x406 | (fi->ea << 12); | |
426 | break; | |
427 | case ARMFault_Debug: | |
428 | fsc = 0x2; | |
429 | break; | |
430 | case ARMFault_TLBConflict: | |
431 | fsc = 0x400; | |
432 | break; | |
433 | case ARMFault_Lockdown: | |
434 | fsc = 0x404; | |
435 | break; | |
436 | case ARMFault_Exclusive: | |
437 | fsc = 0x405; | |
438 | break; | |
439 | case ARMFault_ICacheMaint: | |
440 | fsc = 0x4; | |
441 | break; | |
442 | case ARMFault_Background: | |
443 | fsc = 0x0; | |
444 | break; | |
445 | case ARMFault_QEMU_NSCExec: | |
446 | fsc = M_FAKE_FSR_NSC_EXEC; | |
447 | break; | |
448 | case ARMFault_QEMU_SFault: | |
449 | fsc = M_FAKE_FSR_SFAULT; | |
450 | break; | |
451 | default: | |
452 | /* Other faults can't occur in a context that requires a | |
453 | * short-format status code. | |
454 | */ | |
455 | g_assert_not_reached(); | |
456 | } | |
457 | ||
458 | fsc |= (fi->domain << 4); | |
459 | return fsc; | |
460 | } | |
461 | ||
462 | /** | |
463 | * arm_fi_to_lfsc: Convert fault info struct to long-format FSC | |
464 | * Compare pseudocode EncodeLDFSC(), though unlike that function | |
465 | * we fill in also the LPAE bit 9 of a DFSR format. | |
466 | */ | |
467 | static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) | |
468 | { | |
469 | uint32_t fsc; | |
470 | ||
471 | switch (fi->type) { | |
472 | case ARMFault_None: | |
473 | return 0; | |
474 | case ARMFault_AddressSize: | |
13e481c9 RH |
475 | assert(fi->level >= -1 && fi->level <= 3); |
476 | if (fi->level < 0) { | |
477 | fsc = 0b101001; | |
478 | } else { | |
479 | fsc = fi->level; | |
480 | } | |
1fa498fe PM |
481 | break; |
482 | case ARMFault_AccessFlag: | |
13e481c9 RH |
483 | assert(fi->level >= 0 && fi->level <= 3); |
484 | fsc = 0b001000 | fi->level; | |
1fa498fe PM |
485 | break; |
486 | case ARMFault_Permission: | |
13e481c9 RH |
487 | assert(fi->level >= 0 && fi->level <= 3); |
488 | fsc = 0b001100 | fi->level; | |
1fa498fe PM |
489 | break; |
490 | case ARMFault_Translation: | |
13e481c9 RH |
491 | assert(fi->level >= -1 && fi->level <= 3); |
492 | if (fi->level < 0) { | |
493 | fsc = 0b101011; | |
494 | } else { | |
495 | fsc = 0b000100 | fi->level; | |
496 | } | |
1fa498fe PM |
497 | break; |
498 | case ARMFault_SyncExternal: | |
499 | fsc = 0x10 | (fi->ea << 12); | |
500 | break; | |
501 | case ARMFault_SyncExternalOnWalk: | |
13e481c9 RH |
502 | assert(fi->level >= -1 && fi->level <= 3); |
503 | if (fi->level < 0) { | |
504 | fsc = 0b010011; | |
505 | } else { | |
506 | fsc = 0b010100 | fi->level; | |
507 | } | |
508 | fsc |= fi->ea << 12; | |
1fa498fe PM |
509 | break; |
510 | case ARMFault_SyncParity: | |
511 | fsc = 0x18; | |
512 | break; | |
513 | case ARMFault_SyncParityOnWalk: | |
13e481c9 RH |
514 | assert(fi->level >= -1 && fi->level <= 3); |
515 | if (fi->level < 0) { | |
516 | fsc = 0b011011; | |
517 | } else { | |
518 | fsc = 0b011100 | fi->level; | |
519 | } | |
1fa498fe PM |
520 | break; |
521 | case ARMFault_AsyncParity: | |
522 | fsc = 0x19; | |
523 | break; | |
524 | case ARMFault_AsyncExternal: | |
525 | fsc = 0x11 | (fi->ea << 12); | |
526 | break; | |
527 | case ARMFault_Alignment: | |
528 | fsc = 0x21; | |
529 | break; | |
530 | case ARMFault_Debug: | |
531 | fsc = 0x22; | |
532 | break; | |
533 | case ARMFault_TLBConflict: | |
534 | fsc = 0x30; | |
535 | break; | |
f0a398a2 RH |
536 | case ARMFault_UnsuppAtomicUpdate: |
537 | fsc = 0x31; | |
538 | break; | |
1fa498fe PM |
539 | case ARMFault_Lockdown: |
540 | fsc = 0x34; | |
541 | break; | |
542 | case ARMFault_Exclusive: | |
543 | fsc = 0x35; | |
544 | break; | |
545 | default: | |
546 | /* Other faults can't occur in a context that requires a | |
547 | * long-format status code. | |
548 | */ | |
549 | g_assert_not_reached(); | |
550 | } | |
551 | ||
552 | fsc |= 1 << 9; | |
553 | return fsc; | |
554 | } | |
555 | ||
3b39d734 PM |
556 | static inline bool arm_extabort_type(MemTxResult result) |
557 | { | |
558 | /* The EA bit in syndromes and fault status registers is an | |
559 | * IMPDEF classification of external aborts. ARM implementations | |
560 | * usually use this to indicate AXI bus Decode error (0) or | |
561 | * Slave error (1); in QEMU we follow that. | |
562 | */ | |
563 | return result != MEMTX_DECODE_ERROR; | |
564 | } | |
565 | ||
9b12b6b4 RH |
566 | #ifdef CONFIG_USER_ONLY |
567 | void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr, | |
568 | MMUAccessType access_type, | |
569 | bool maperr, uintptr_t ra); | |
39a099ca RH |
570 | void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr, |
571 | MMUAccessType access_type, uintptr_t ra); | |
9b12b6b4 | 572 | #else |
7350d553 RH |
573 | bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
574 | MMUAccessType access_type, int mmu_idx, | |
575 | bool probe, uintptr_t retaddr); | |
9b12b6b4 | 576 | #endif |
7350d553 | 577 | |
b9f6033c RH |
578 | static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx) |
579 | { | |
580 | return mmu_idx & ARM_MMU_IDX_COREIDX_MASK; | |
581 | } | |
582 | ||
583 | static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) | |
584 | { | |
585 | if (arm_feature(env, ARM_FEATURE_M)) { | |
586 | return mmu_idx | ARM_MMU_IDX_M; | |
587 | } else { | |
588 | return mmu_idx | ARM_MMU_IDX_A; | |
589 | } | |
590 | } | |
591 | ||
20dc67c9 RH |
592 | static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx) |
593 | { | |
594 | /* AArch64 is always a-profile. */ | |
595 | return mmu_idx | ARM_MMU_IDX_A; | |
596 | } | |
597 | ||
b9f6033c RH |
598 | int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); |
599 | ||
b9f6033c RH |
600 | /* Return the MMU index for a v7M CPU in the specified security state */ |
601 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); | |
602 | ||
8ae08860 RH |
603 | /* |
604 | * Return true if the stage 1 translation regime is using LPAE | |
605 | * format page tables | |
606 | */ | |
deb2db99 | 607 | bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); |
30901475 AB |
608 | |
609 | /* Raise a data fault alignment exception for the specified virtual address */ | |
8905770b MAL |
610 | G_NORETURN void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, |
611 | MMUAccessType access_type, | |
612 | int mmu_idx, uintptr_t retaddr); | |
30901475 | 613 | |
d90ebc47 | 614 | #ifndef CONFIG_USER_ONLY |
c79c0a31 PM |
615 | /* arm_cpu_do_transaction_failed: handle a memory system error response |
616 | * (eg "no device/memory present at address") by raising an external abort | |
617 | * exception | |
618 | */ | |
619 | void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, | |
620 | vaddr addr, unsigned size, | |
621 | MMUAccessType access_type, | |
622 | int mmu_idx, MemTxAttrs attrs, | |
623 | MemTxResult response, uintptr_t retaddr); | |
d90ebc47 | 624 | #endif |
c79c0a31 | 625 | |
08267487 | 626 | /* Call any registered EL change hooks */ |
b5c53d1b AL |
627 | static inline void arm_call_pre_el_change_hook(ARMCPU *cpu) |
628 | { | |
629 | ARMELChangeHook *hook, *next; | |
630 | QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) { | |
631 | hook->hook(cpu, hook->opaque); | |
632 | } | |
633 | } | |
bd7d00fc PM |
634 | static inline void arm_call_el_change_hook(ARMCPU *cpu) |
635 | { | |
08267487 AL |
636 | ARMELChangeHook *hook, *next; |
637 | QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) { | |
638 | hook->hook(cpu, hook->opaque); | |
bd7d00fc PM |
639 | } |
640 | } | |
641 | ||
339370b9 RH |
642 | /* Return true if this address translation regime has two ranges. */ |
643 | static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) | |
644 | { | |
645 | switch (mmu_idx) { | |
646 | case ARMMMUIdx_Stage1_E0: | |
647 | case ARMMMUIdx_Stage1_E1: | |
452ef8cb | 648 | case ARMMMUIdx_Stage1_E1_PAN: |
339370b9 RH |
649 | case ARMMMUIdx_E10_0: |
650 | case ARMMMUIdx_E10_1: | |
452ef8cb | 651 | case ARMMMUIdx_E10_1_PAN: |
339370b9 RH |
652 | case ARMMMUIdx_E20_0: |
653 | case ARMMMUIdx_E20_2: | |
452ef8cb | 654 | case ARMMMUIdx_E20_2_PAN: |
339370b9 RH |
655 | return true; |
656 | default: | |
657 | return false; | |
658 | } | |
659 | } | |
660 | ||
81636b70 RH |
661 | static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) |
662 | { | |
663 | switch (mmu_idx) { | |
664 | case ARMMMUIdx_Stage1_E1_PAN: | |
665 | case ARMMMUIdx_E10_1_PAN: | |
666 | case ARMMMUIdx_E20_2_PAN: | |
81636b70 RH |
667 | return true; |
668 | default: | |
669 | return false; | |
670 | } | |
671 | } | |
672 | ||
edc05dd4 RH |
673 | static inline bool regime_is_stage2(ARMMMUIdx mmu_idx) |
674 | { | |
675 | return mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S; | |
676 | } | |
677 | ||
9c7ab8fc RH |
678 | /* Return the exception level which controls this address translation regime */ |
679 | static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) | |
680 | { | |
681 | switch (mmu_idx) { | |
682 | case ARMMMUIdx_E20_0: | |
683 | case ARMMMUIdx_E20_2: | |
684 | case ARMMMUIdx_E20_2_PAN: | |
685 | case ARMMMUIdx_Stage2: | |
b1a10c86 | 686 | case ARMMMUIdx_Stage2_S: |
9c7ab8fc RH |
687 | case ARMMMUIdx_E2: |
688 | return 2; | |
d902ae75 | 689 | case ARMMMUIdx_E3: |
9c7ab8fc | 690 | return 3; |
d902ae75 | 691 | case ARMMMUIdx_E10_0: |
9c7ab8fc | 692 | case ARMMMUIdx_Stage1_E0: |
d902ae75 | 693 | return arm_el_is_aa64(env, 3) || !arm_is_secure_below_el3(env) ? 1 : 3; |
9c7ab8fc RH |
694 | case ARMMMUIdx_Stage1_E1: |
695 | case ARMMMUIdx_Stage1_E1_PAN: | |
9c7ab8fc RH |
696 | case ARMMMUIdx_E10_1: |
697 | case ARMMMUIdx_E10_1_PAN: | |
698 | case ARMMMUIdx_MPrivNegPri: | |
699 | case ARMMMUIdx_MUserNegPri: | |
700 | case ARMMMUIdx_MPriv: | |
701 | case ARMMMUIdx_MUser: | |
702 | case ARMMMUIdx_MSPrivNegPri: | |
703 | case ARMMMUIdx_MSUserNegPri: | |
704 | case ARMMMUIdx_MSPriv: | |
705 | case ARMMMUIdx_MSUser: | |
706 | return 1; | |
707 | default: | |
708 | g_assert_not_reached(); | |
709 | } | |
710 | } | |
711 | ||
e4c93e44 PM |
712 | static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) |
713 | { | |
714 | switch (mmu_idx) { | |
715 | case ARMMMUIdx_E20_0: | |
716 | case ARMMMUIdx_Stage1_E0: | |
717 | case ARMMMUIdx_MUser: | |
718 | case ARMMMUIdx_MSUser: | |
719 | case ARMMMUIdx_MUserNegPri: | |
720 | case ARMMMUIdx_MSUserNegPri: | |
721 | return true; | |
722 | default: | |
723 | return false; | |
724 | case ARMMMUIdx_E10_0: | |
725 | case ARMMMUIdx_E10_1: | |
726 | case ARMMMUIdx_E10_1_PAN: | |
727 | g_assert_not_reached(); | |
728 | } | |
729 | } | |
730 | ||
8ae08860 RH |
731 | /* Return the SCTLR value which controls this address translation regime */ |
732 | static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) | |
733 | { | |
734 | return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; | |
735 | } | |
736 | ||
f04383e7 PM |
737 | /* |
738 | * These are the fields in VTCR_EL2 which affect both the Secure stage 2 | |
739 | * and the Non-Secure stage 2 translation regimes (and hence which are | |
740 | * not present in VSTCR_EL2). | |
741 | */ | |
742 | #define VTCR_SHARED_FIELD_MASK \ | |
743 | (R_VTCR_IRGN0_MASK | R_VTCR_ORGN0_MASK | R_VTCR_SH0_MASK | \ | |
744 | R_VTCR_PS_MASK | R_VTCR_VS_MASK | R_VTCR_HA_MASK | R_VTCR_HD_MASK | \ | |
745 | R_VTCR_DS_MASK) | |
746 | ||
c1547bba PM |
747 | /* Return the value of the TCR controlling this translation regime */ |
748 | static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) | |
38659d31 RH |
749 | { |
750 | if (mmu_idx == ARMMMUIdx_Stage2) { | |
988cc190 | 751 | return env->cp15.vtcr_el2; |
38659d31 | 752 | } |
b1a10c86 RDC |
753 | if (mmu_idx == ARMMMUIdx_Stage2_S) { |
754 | /* | |
f04383e7 PM |
755 | * Secure stage 2 shares fields from VTCR_EL2. We merge those |
756 | * in with the VSTCR_EL2 value to synthesize a single VTCR_EL2 format | |
757 | * value so the callers don't need to special case this. | |
758 | * | |
759 | * If a future architecture change defines bits in VSTCR_EL2 that | |
760 | * overlap with these VTCR_EL2 fields we may need to revisit this. | |
b1a10c86 | 761 | */ |
f04383e7 PM |
762 | uint64_t v = env->cp15.vstcr_el2 & ~VTCR_SHARED_FIELD_MASK; |
763 | v |= env->cp15.vtcr_el2 & VTCR_SHARED_FIELD_MASK; | |
764 | return v; | |
b1a10c86 | 765 | } |
cb4a0a34 | 766 | return env->cp15.tcr_el[regime_el(env, mmu_idx)]; |
dfce4aa8 PM |
767 | } |
768 | ||
2ea2998f FR |
769 | /* Return true if the translation regime is using LPAE format page tables */ |
770 | static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) | |
771 | { | |
772 | int el = regime_el(env, mmu_idx); | |
773 | if (el == 2 || arm_el_is_aa64(env, el)) { | |
774 | return true; | |
775 | } | |
776 | if (arm_feature(env, ARM_FEATURE_PMSA) && | |
777 | arm_feature(env, ARM_FEATURE_V8)) { | |
778 | return true; | |
779 | } | |
780 | if (arm_feature(env, ARM_FEATURE_LPAE) | |
781 | && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) { | |
782 | return true; | |
783 | } | |
784 | return false; | |
785 | } | |
786 | ||
88ce6c6e PM |
787 | /** |
788 | * arm_num_brps: Return number of implemented breakpoints. | |
789 | * Note that the ID register BRPS field is "number of bps - 1", | |
790 | * and we return the actual number of breakpoints. | |
791 | */ | |
792 | static inline int arm_num_brps(ARMCPU *cpu) | |
793 | { | |
794 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
795 | return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1; | |
796 | } else { | |
4426d361 | 797 | return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1; |
88ce6c6e PM |
798 | } |
799 | } | |
800 | ||
801 | /** | |
802 | * arm_num_wrps: Return number of implemented watchpoints. | |
803 | * Note that the ID register WRPS field is "number of wps - 1", | |
804 | * and we return the actual number of watchpoints. | |
805 | */ | |
806 | static inline int arm_num_wrps(ARMCPU *cpu) | |
807 | { | |
808 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
809 | return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1; | |
810 | } else { | |
4426d361 | 811 | return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1; |
88ce6c6e PM |
812 | } |
813 | } | |
814 | ||
815 | /** | |
816 | * arm_num_ctx_cmps: Return number of implemented context comparators. | |
817 | * Note that the ID register CTX_CMPS field is "number of cmps - 1", | |
818 | * and we return the actual number of comparators. | |
819 | */ | |
820 | static inline int arm_num_ctx_cmps(ARMCPU *cpu) | |
821 | { | |
822 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
823 | return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1; | |
824 | } else { | |
4426d361 | 825 | return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1; |
88ce6c6e PM |
826 | } |
827 | } | |
828 | ||
5529bf18 PM |
829 | /** |
830 | * v7m_using_psp: Return true if using process stack pointer | |
831 | * Return true if the CPU is currently using the process stack | |
832 | * pointer, or false if it is using the main stack pointer. | |
833 | */ | |
834 | static inline bool v7m_using_psp(CPUARMState *env) | |
835 | { | |
836 | /* Handler mode always uses the main stack; for thread mode | |
837 | * the CONTROL.SPSEL bit determines the answer. | |
838 | * Note that in v7M it is not possible to be in Handler mode with | |
839 | * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both. | |
840 | */ | |
841 | return !arm_v7m_is_handler_mode(env) && | |
842 | env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; | |
843 | } | |
844 | ||
55203189 PM |
845 | /** |
846 | * v7m_sp_limit: Return SP limit for current CPU state | |
847 | * Return the SP limit value for the current CPU security state | |
848 | * and stack pointer. | |
849 | */ | |
850 | static inline uint32_t v7m_sp_limit(CPUARMState *env) | |
851 | { | |
852 | if (v7m_using_psp(env)) { | |
853 | return env->v7m.psplim[env->v7m.secure]; | |
854 | } else { | |
855 | return env->v7m.msplim[env->v7m.secure]; | |
856 | } | |
857 | } | |
858 | ||
787a7e76 PMD |
859 | /** |
860 | * v7m_cpacr_pass: | |
861 | * Return true if the v7M CPACR permits access to the FPU for the specified | |
862 | * security state and privilege level. | |
863 | */ | |
864 | static inline bool v7m_cpacr_pass(CPUARMState *env, | |
865 | bool is_secure, bool is_priv) | |
866 | { | |
867 | switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { | |
868 | case 0: | |
869 | case 2: /* UNPREDICTABLE: we treat like 0 */ | |
870 | return false; | |
871 | case 1: | |
872 | return is_priv; | |
873 | case 3: | |
874 | return true; | |
875 | default: | |
876 | g_assert_not_reached(); | |
877 | } | |
878 | } | |
879 | ||
81e37284 PM |
880 | /** |
881 | * aarch32_mode_name(): Return name of the AArch32 CPU mode | |
882 | * @psr: Program Status Register indicating CPU mode | |
883 | * | |
884 | * Returns, for debug logging purposes, a printable representation | |
885 | * of the AArch32 CPU mode ("svc", "usr", etc) as indicated by | |
886 | * the low bits of the specified PSR. | |
887 | */ | |
888 | static inline const char *aarch32_mode_name(uint32_t psr) | |
889 | { | |
890 | static const char cpu_mode_names[16][4] = { | |
891 | "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt", | |
892 | "???", "???", "hyp", "und", "???", "???", "???", "sys" | |
893 | }; | |
894 | ||
895 | return cpu_mode_names[psr & 0xf]; | |
896 | } | |
897 | ||
89430fc6 PM |
898 | /** |
899 | * arm_cpu_update_virq: Update CPU_INTERRUPT_VIRQ bit in cs->interrupt_request | |
900 | * | |
901 | * Update the CPU_INTERRUPT_VIRQ bit in cs->interrupt_request, following | |
902 | * a change to either the input VIRQ line from the GIC or the HCR_EL2.VI bit. | |
903 | * Must be called with the iothread lock held. | |
904 | */ | |
905 | void arm_cpu_update_virq(ARMCPU *cpu); | |
906 | ||
907 | /** | |
908 | * arm_cpu_update_vfiq: Update CPU_INTERRUPT_VFIQ bit in cs->interrupt_request | |
909 | * | |
910 | * Update the CPU_INTERRUPT_VFIQ bit in cs->interrupt_request, following | |
911 | * a change to either the input VFIQ line from the GIC or the HCR_EL2.VF bit. | |
912 | * Must be called with the iothread lock held. | |
913 | */ | |
914 | void arm_cpu_update_vfiq(ARMCPU *cpu); | |
915 | ||
3c29632f RH |
916 | /** |
917 | * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit | |
918 | * | |
919 | * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request, | |
920 | * following a change to the HCR_EL2.VSE bit. | |
921 | */ | |
922 | void arm_cpu_update_vserr(ARMCPU *cpu); | |
923 | ||
164690b2 RH |
924 | /** |
925 | * arm_mmu_idx_el: | |
926 | * @env: The cpu environment | |
927 | * @el: The EL to use. | |
928 | * | |
929 | * Return the full ARMMMUIdx for the translation regime for EL. | |
930 | */ | |
931 | ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el); | |
932 | ||
50494a27 RH |
933 | /** |
934 | * arm_mmu_idx: | |
935 | * @env: The cpu environment | |
936 | * | |
937 | * Return the full ARMMMUIdx for the current translation regime. | |
938 | */ | |
939 | ARMMMUIdx arm_mmu_idx(CPUARMState *env); | |
940 | ||
64be86ab RH |
941 | /** |
942 | * arm_stage1_mmu_idx: | |
943 | * @env: The cpu environment | |
944 | * | |
945 | * Return the ARMMMUIdx for the stage1 traversal for the current regime. | |
946 | */ | |
947 | #ifdef CONFIG_USER_ONLY | |
d8cca960 RH |
948 | static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) |
949 | { | |
950 | return ARMMMUIdx_Stage1_E0; | |
951 | } | |
64be86ab RH |
952 | static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) |
953 | { | |
2859d7b5 | 954 | return ARMMMUIdx_Stage1_E0; |
64be86ab RH |
955 | } |
956 | #else | |
d8cca960 | 957 | ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx); |
64be86ab RH |
958 | ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); |
959 | #endif | |
960 | ||
fee7aa46 RH |
961 | /** |
962 | * arm_mmu_idx_is_stage1_of_2: | |
963 | * @mmu_idx: The ARMMMUIdx to test | |
964 | * | |
965 | * Return true if @mmu_idx is a NOTLB mmu_idx that is the | |
966 | * first stage of a two stage regime. | |
967 | */ | |
968 | static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) | |
969 | { | |
970 | switch (mmu_idx) { | |
971 | case ARMMMUIdx_Stage1_E0: | |
972 | case ARMMMUIdx_Stage1_E1: | |
452ef8cb | 973 | case ARMMMUIdx_Stage1_E1_PAN: |
fee7aa46 RH |
974 | return true; |
975 | default: | |
976 | return false; | |
977 | } | |
978 | } | |
979 | ||
4f9584ed RH |
980 | static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, |
981 | const ARMISARegisters *id) | |
982 | { | |
f062d144 | 983 | uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV; |
4f9584ed RH |
984 | |
985 | if ((features >> ARM_FEATURE_V4T) & 1) { | |
986 | valid |= CPSR_T; | |
987 | } | |
988 | if ((features >> ARM_FEATURE_V5) & 1) { | |
989 | valid |= CPSR_Q; /* V5TE in reality*/ | |
990 | } | |
991 | if ((features >> ARM_FEATURE_V6) & 1) { | |
992 | valid |= CPSR_E | CPSR_GE; | |
993 | } | |
994 | if ((features >> ARM_FEATURE_THUMB2) & 1) { | |
995 | valid |= CPSR_IT; | |
996 | } | |
873b73c0 | 997 | if (isar_feature_aa32_jazelle(id)) { |
f062d144 RH |
998 | valid |= CPSR_J; |
999 | } | |
220f508f RH |
1000 | if (isar_feature_aa32_pan(id)) { |
1001 | valid |= CPSR_PAN; | |
1002 | } | |
dc8b1853 RC |
1003 | if (isar_feature_aa32_dit(id)) { |
1004 | valid |= CPSR_DIT; | |
1005 | } | |
f2f68a78 RC |
1006 | if (isar_feature_aa32_ssbs(id)) { |
1007 | valid |= CPSR_SSBS; | |
1008 | } | |
4f9584ed RH |
1009 | |
1010 | return valid; | |
1011 | } | |
1012 | ||
14084511 RH |
1013 | static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) |
1014 | { | |
1015 | uint32_t valid; | |
1016 | ||
1017 | valid = PSTATE_M | PSTATE_DAIF | PSTATE_IL | PSTATE_SS | PSTATE_NZCV; | |
1018 | if (isar_feature_aa64_bti(id)) { | |
1019 | valid |= PSTATE_BTYPE; | |
1020 | } | |
220f508f RH |
1021 | if (isar_feature_aa64_pan(id)) { |
1022 | valid |= PSTATE_PAN; | |
1023 | } | |
9eeb7a1c RH |
1024 | if (isar_feature_aa64_uao(id)) { |
1025 | valid |= PSTATE_UAO; | |
1026 | } | |
dc8b1853 RC |
1027 | if (isar_feature_aa64_dit(id)) { |
1028 | valid |= PSTATE_DIT; | |
1029 | } | |
f2f68a78 RC |
1030 | if (isar_feature_aa64_ssbs(id)) { |
1031 | valid |= PSTATE_SSBS; | |
1032 | } | |
4b779ceb RH |
1033 | if (isar_feature_aa64_mte(id)) { |
1034 | valid |= PSTATE_TCO; | |
1035 | } | |
14084511 RH |
1036 | |
1037 | return valid; | |
1038 | } | |
1039 | ||
104f703d PM |
1040 | /* Granule size (i.e. page size) */ |
1041 | typedef enum ARMGranuleSize { | |
1042 | /* Same order as TG0 encoding */ | |
1043 | Gran4K, | |
1044 | Gran64K, | |
1045 | Gran16K, | |
1046 | GranInvalid, | |
1047 | } ARMGranuleSize; | |
1048 | ||
3c003f70 PM |
1049 | /** |
1050 | * arm_granule_bits: Return address size of the granule in bits | |
1051 | * | |
1052 | * Return the address size of the granule in bits. This corresponds | |
1053 | * to the pseudocode TGxGranuleBits(). | |
1054 | */ | |
1055 | static inline int arm_granule_bits(ARMGranuleSize gran) | |
1056 | { | |
1057 | switch (gran) { | |
1058 | case Gran64K: | |
1059 | return 16; | |
1060 | case Gran16K: | |
1061 | return 14; | |
1062 | case Gran4K: | |
1063 | return 12; | |
1064 | default: | |
1065 | g_assert_not_reached(); | |
1066 | } | |
1067 | } | |
1068 | ||
ba97be9f RH |
1069 | /* |
1070 | * Parameters of a given virtual address, as extracted from the | |
1071 | * translation control register (TCR) for a given regime. | |
1072 | */ | |
1073 | typedef struct ARMVAParameters { | |
1074 | unsigned tsz : 8; | |
f4ecc015 | 1075 | unsigned ps : 3; |
ef56c242 | 1076 | unsigned sh : 2; |
ba97be9f RH |
1077 | unsigned select : 1; |
1078 | bool tbi : 1; | |
1079 | bool epd : 1; | |
1080 | bool hpd : 1; | |
ebf93ce7 | 1081 | bool tsz_oob : 1; /* tsz has been clamped to legal range */ |
ef56c242 | 1082 | bool ds : 1; |
89739227 RH |
1083 | bool ha : 1; |
1084 | bool hd : 1; | |
3c003f70 | 1085 | ARMGranuleSize gran : 2; |
ba97be9f RH |
1086 | } ARMVAParameters; |
1087 | ||
bf0be433 RH |
1088 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, |
1089 | ARMMMUIdx mmu_idx, bool data); | |
bf0be433 | 1090 | |
8ae08860 RH |
1091 | int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); |
1092 | int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx); | |
671efad1 | 1093 | int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx); |
8ae08860 | 1094 | |
81ae05fa RH |
1095 | /* Determine if allocation tags are available. */ |
1096 | static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, | |
1097 | uint64_t sctlr) | |
1098 | { | |
1099 | if (el < 3 | |
1100 | && arm_feature(env, ARM_FEATURE_EL3) | |
1101 | && !(env->cp15.scr_el3 & SCR_ATA)) { | |
1102 | return false; | |
1103 | } | |
0da067f2 | 1104 | if (el < 2 && arm_is_el2_enabled(env)) { |
4301acd7 RH |
1105 | uint64_t hcr = arm_hcr_el2_eff(env); |
1106 | if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { | |
1107 | return false; | |
1108 | } | |
81ae05fa RH |
1109 | } |
1110 | sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA); | |
1111 | return sctlr != 0; | |
1112 | } | |
1113 | ||
ebae861f PMD |
1114 | #ifndef CONFIG_USER_ONLY |
1115 | ||
787a7e76 PMD |
1116 | /* Security attributes for an address, as returned by v8m_security_lookup. */ |
1117 | typedef struct V8M_SAttributes { | |
1118 | bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */ | |
1119 | bool ns; | |
1120 | bool nsc; | |
1121 | uint8_t sregion; | |
1122 | bool srvalid; | |
1123 | uint8_t iregion; | |
1124 | bool irvalid; | |
1125 | } V8M_SAttributes; | |
1126 | ||
1127 | void v8m_security_lookup(CPUARMState *env, uint32_t address, | |
1128 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
dbf2a71a | 1129 | bool secure, V8M_SAttributes *sattrs); |
787a7e76 | 1130 | |
ebae861f PMD |
1131 | /* Cacheability and shareability attributes for a memory access */ |
1132 | typedef struct ARMCacheAttrs { | |
9f225e60 PM |
1133 | /* |
1134 | * If is_s2_format is true, attrs is the S2 descriptor bits [5:2] | |
1135 | * Otherwise, attrs is the same as the MAIR_EL1 8-bit format | |
1136 | */ | |
1137 | unsigned int attrs:8; | |
ebae861f | 1138 | unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */ |
9f225e60 | 1139 | bool is_s2_format:1; |
937f2245 | 1140 | bool guarded:1; /* guarded bit of the v8-64 PTE */ |
ebae861f PMD |
1141 | } ARMCacheAttrs; |
1142 | ||
de05a709 RH |
1143 | /* Fields that are valid upon success. */ |
1144 | typedef struct GetPhysAddrResult { | |
7fa7ea8f | 1145 | CPUTLBEntryFull f; |
de05a709 RH |
1146 | ARMCacheAttrs cacheattrs; |
1147 | } GetPhysAddrResult; | |
1148 | ||
def8aa5b RH |
1149 | /** |
1150 | * get_phys_addr_with_secure: get the physical address for a virtual address | |
1151 | * @env: CPUARMState | |
1152 | * @address: virtual address to get physical address for | |
1153 | * @access_type: 0 for read, 1 for write, 2 for execute | |
1154 | * @mmu_idx: MMU index indicating required translation regime | |
1155 | * @is_secure: security state for the access | |
1156 | * @result: set on translation success. | |
1157 | * @fi: set to fault info if the translation fails | |
1158 | * | |
1159 | * Find the physical address corresponding to the given virtual address, | |
1160 | * by doing a translation table walk on MMU based systems or using the | |
1161 | * MPU state on MPU based systems. | |
1162 | * | |
1163 | * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, | |
1164 | * prot and page_size may not be filled in, and the populated fsr value provides | |
1165 | * information on why the translation aborted, in the format of a | |
1166 | * DFSR/IFSR fault register, with the following caveats: | |
1167 | * * we honour the short vs long DFSR format differences. | |
1168 | * * the WnR bit is never set (the caller must do this). | |
1169 | * * for PSMAv5 based systems we don't bother to return a full FSR format | |
1170 | * value. | |
1171 | */ | |
1172 | bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, | |
1173 | MMUAccessType access_type, | |
1174 | ARMMMUIdx mmu_idx, bool is_secure, | |
1175 | GetPhysAddrResult *result, ARMMMUFaultInfo *fi) | |
1176 | __attribute__((nonnull)); | |
1177 | ||
1178 | /** | |
1179 | * get_phys_addr: get the physical address for a virtual address | |
1180 | * @env: CPUARMState | |
1181 | * @address: virtual address to get physical address for | |
1182 | * @access_type: 0 for read, 1 for write, 2 for execute | |
1183 | * @mmu_idx: MMU index indicating required translation regime | |
1184 | * @result: set on translation success. | |
1185 | * @fi: set to fault info if the translation fails | |
1186 | * | |
1187 | * Similarly, but use the security regime of @mmu_idx. | |
1188 | */ | |
ebae861f PMD |
1189 | bool get_phys_addr(CPUARMState *env, target_ulong address, |
1190 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
de05a709 | 1191 | GetPhysAddrResult *result, ARMMMUFaultInfo *fi) |
7e98e21c | 1192 | __attribute__((nonnull)); |
ebae861f | 1193 | |
d2c92e58 RH |
1194 | bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, |
1195 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | |
e9fb7090 RH |
1196 | bool is_secure, GetPhysAddrResult *result, |
1197 | ARMMMUFaultInfo *fi, uint32_t *mregion); | |
d2c92e58 | 1198 | |
fc6177af | 1199 | void arm_log_exception(CPUState *cs); |
b59f479b | 1200 | |
ebae861f PMD |
1201 | #endif /* !CONFIG_USER_ONLY */ |
1202 | ||
4b779ceb RH |
1203 | /* |
1204 | * The log2 of the words in the tag block, for GMID_EL1.BS. | |
1205 | * The is the maximum, 256 bytes, which manipulates 64-bits of tags. | |
1206 | */ | |
1207 | #define GMID_EL1_BS 6 | |
1208 | ||
b64ee454 RH |
1209 | /* |
1210 | * SVE predicates are 1/8 the size of SVE vectors, and cannot use | |
1211 | * the same simd_desc() encoding due to restrictions on size. | |
1212 | * Use these instead. | |
1213 | */ | |
1214 | FIELD(PREDDESC, OPRSZ, 0, 6) | |
1215 | FIELD(PREDDESC, ESZ, 6, 2) | |
1216 | FIELD(PREDDESC, DATA, 8, 24) | |
1217 | ||
206adacf RH |
1218 | /* |
1219 | * The SVE simd_data field, for memory ops, contains either | |
1220 | * rd (5 bits) or a shift count (2 bits). | |
1221 | */ | |
1222 | #define SVE_MTEDESC_SHIFT 5 | |
1223 | ||
0a405be2 RH |
1224 | /* Bits within a descriptor passed to the helper_mte_check* functions. */ |
1225 | FIELD(MTEDESC, MIDX, 0, 4) | |
1226 | FIELD(MTEDESC, TBI, 4, 2) | |
1227 | FIELD(MTEDESC, TCMA, 6, 2) | |
1228 | FIELD(MTEDESC, WRITE, 8, 1) | |
28f32503 | 1229 | FIELD(MTEDESC, SIZEM1, 9, SIMD_DATA_BITS - 9) /* size - 1 */ |
0a405be2 | 1230 | |
d304d280 | 1231 | bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr); |
bd47b61c | 1232 | uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra); |
2e34ff45 | 1233 | |
efbc78ad RH |
1234 | static inline int allocation_tag_from_addr(uint64_t ptr) |
1235 | { | |
1236 | return extract64(ptr, 56, 4); | |
1237 | } | |
1238 | ||
da54941f RH |
1239 | static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) |
1240 | { | |
1241 | return deposit64(ptr, 56, 4, rtag); | |
1242 | } | |
1243 | ||
2e34ff45 RH |
1244 | /* Return true if tbi bits mean that the access is checked. */ |
1245 | static inline bool tbi_check(uint32_t desc, int bit55) | |
1246 | { | |
1247 | return (desc >> (R_MTEDESC_TBI_SHIFT + bit55)) & 1; | |
1248 | } | |
1249 | ||
1250 | /* Return true if tcma bits mean that the access is unchecked. */ | |
1251 | static inline bool tcma_check(uint32_t desc, int bit55, int ptr_tag) | |
1252 | { | |
1253 | /* | |
1254 | * We had extracted bit55 and ptr_tag for other reasons, so fold | |
1255 | * (ptr<59:55> == 00000 || ptr<59:55> == 11111) into a single test. | |
1256 | */ | |
1257 | bool match = ((ptr_tag + bit55) & 0xf) == 0; | |
1258 | bool tcma = (desc >> (R_MTEDESC_TCMA_SHIFT + bit55)) & 1; | |
1259 | return tcma && match; | |
1260 | } | |
1261 | ||
1262 | /* | |
1263 | * For TBI, ideally, we would do nothing. Proper behaviour on fault is | |
1264 | * for the tag to be present in the FAR_ELx register. But for user-only | |
1265 | * mode, we do not have a TLB with which to implement this, so we must | |
1266 | * remove the top byte. | |
1267 | */ | |
1268 | static inline uint64_t useronly_clean_ptr(uint64_t ptr) | |
1269 | { | |
2e34ff45 | 1270 | #ifdef CONFIG_USER_ONLY |
16c84978 RH |
1271 | /* TBI0 is known to be enabled, while TBI1 is disabled. */ |
1272 | ptr &= sextract64(ptr, 0, 56); | |
2e34ff45 RH |
1273 | #endif |
1274 | return ptr; | |
1275 | } | |
1276 | ||
1277 | static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc, uint64_t ptr) | |
1278 | { | |
1279 | #ifdef CONFIG_USER_ONLY | |
1280 | int64_t clean_ptr = sextract64(ptr, 0, 56); | |
1281 | if (tbi_check(desc, clean_ptr < 0)) { | |
1282 | ptr = clean_ptr; | |
1283 | } | |
1284 | #endif | |
1285 | return ptr; | |
1286 | } | |
1287 | ||
507b6a50 PM |
1288 | /* Values for M-profile PSR.ECI for MVE insns */ |
1289 | enum MVEECIState { | |
1290 | ECI_NONE = 0, /* No completed beats */ | |
1291 | ECI_A0 = 1, /* Completed: A0 */ | |
1292 | ECI_A0A1 = 2, /* Completed: A0, A1 */ | |
1293 | /* 3 is reserved */ | |
1294 | ECI_A0A1A2 = 4, /* Completed: A0, A1, A2 */ | |
1295 | ECI_A0A1A2B0 = 5, /* Completed: A0, A1, A2, B0 */ | |
1296 | /* All other values reserved */ | |
1297 | }; | |
1298 | ||
0130895d AG |
1299 | /* Definitions for the PMU registers */ |
1300 | #define PMCRN_MASK 0xf800 | |
1301 | #define PMCRN_SHIFT 11 | |
47b385da | 1302 | #define PMCRLP 0x80 |
0130895d AG |
1303 | #define PMCRLC 0x40 |
1304 | #define PMCRDP 0x20 | |
1305 | #define PMCRX 0x10 | |
1306 | #define PMCRD 0x8 | |
1307 | #define PMCRC 0x4 | |
1308 | #define PMCRP 0x2 | |
1309 | #define PMCRE 0x1 | |
1310 | /* | |
9323e79f | 1311 | * Mask of PMCR bits writable by guest (not including WO bits like C, P, |
0130895d AG |
1312 | * which can be written as 1 to trigger behaviour but which stay RAZ). |
1313 | */ | |
47b385da | 1314 | #define PMCR_WRITABLE_MASK (PMCRLP | PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) |
0130895d AG |
1315 | |
1316 | #define PMXEVTYPER_P 0x80000000 | |
1317 | #define PMXEVTYPER_U 0x40000000 | |
1318 | #define PMXEVTYPER_NSK 0x20000000 | |
1319 | #define PMXEVTYPER_NSU 0x10000000 | |
1320 | #define PMXEVTYPER_NSH 0x08000000 | |
1321 | #define PMXEVTYPER_M 0x04000000 | |
1322 | #define PMXEVTYPER_MT 0x02000000 | |
1323 | #define PMXEVTYPER_EVTCOUNT 0x0000ffff | |
1324 | #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \ | |
1325 | PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ | |
1326 | PMXEVTYPER_M | PMXEVTYPER_MT | \ | |
1327 | PMXEVTYPER_EVTCOUNT) | |
1328 | ||
1329 | #define PMCCFILTR 0xf8000000 | |
1330 | #define PMCCFILTR_M PMXEVTYPER_M | |
1331 | #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) | |
1332 | ||
1333 | static inline uint32_t pmu_num_counters(CPUARMState *env) | |
1334 | { | |
24526bb9 PM |
1335 | ARMCPU *cpu = env_archcpu(env); |
1336 | ||
1337 | return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT; | |
0130895d AG |
1338 | } |
1339 | ||
1340 | /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ | |
1341 | static inline uint64_t pmu_counter_mask(CPUARMState *env) | |
1342 | { | |
c117c064 | 1343 | return (1ULL << 31) | ((1ULL << pmu_num_counters(env)) - 1); |
0130895d AG |
1344 | } |
1345 | ||
89f4f20e PM |
1346 | #ifdef TARGET_AARCH64 |
1347 | int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg); | |
1348 | int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg); | |
1349 | int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); | |
1350 | int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); | |
07301161 | 1351 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); |
e74c0976 | 1352 | void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); |
07301161 RH |
1353 | void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); |
1354 | void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); | |
89f4f20e PM |
1355 | #endif |
1356 | ||
7c1aaf98 RH |
1357 | #ifdef CONFIG_USER_ONLY |
1358 | static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } | |
1359 | #else | |
1360 | void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); | |
1361 | #endif | |
1362 | ||
19668718 RH |
1363 | bool el_is_in_host(CPUARMState *env, int el); |
1364 | ||
b6f8b358 | 1365 | void aa32_max_features(ARMCPU *cpu); |
57287a6e | 1366 | int exception_target_el(CPUARMState *env); |
55ba15b7 | 1367 | bool arm_singlestep_active(CPUARMState *env); |
31c8df53 | 1368 | bool arm_generate_debug_exceptions(CPUARMState *env); |
b6f8b358 | 1369 | |
f43ee493 PM |
1370 | /* Add the cpreg definitions for debug related system registers */ |
1371 | void define_debug_regs(ARMCPU *cpu); | |
1372 | ||
1373 | /* Effective value of MDCR_EL2 */ | |
1374 | static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env) | |
1375 | { | |
1376 | return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0; | |
1377 | } | |
1378 | ||
886902ec RH |
1379 | /* Powers of 2 for sve_vq_map et al. */ |
1380 | #define SVE_VQ_POW2_MAP \ | |
1381 | ((1 << (1 - 1)) | (1 << (2 - 1)) | \ | |
1382 | (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1))) | |
1383 | ||
361c33f6 PM |
1384 | /* |
1385 | * Return true if it is possible to take a fine-grained-trap to EL2. | |
1386 | */ | |
1387 | static inline bool arm_fgt_active(CPUARMState *env, int el) | |
1388 | { | |
1389 | /* | |
1390 | * The Arm ARM only requires the "{E2H,TGE} != {1,1}" test for traps | |
1391 | * that can affect EL0, but it is harmless to do the test also for | |
1392 | * traps on registers that are only accessible at EL1 because if the test | |
1393 | * returns true then we can't be executing at EL1 anyway. | |
1394 | * FGT traps only happen when EL2 is enabled and EL1 is AArch64; | |
1395 | * traps from AArch32 only happen for the EL0 is AArch32 case. | |
1396 | */ | |
1397 | return cpu_isar_feature(aa64_fgt, env_archcpu(env)) && | |
1398 | el < 2 && arm_is_el2_enabled(env) && | |
1399 | arm_el_is_aa64(env, 1) && | |
1400 | (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE) && | |
1401 | (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN)); | |
1402 | } | |
1403 | ||
671efad1 | 1404 | void assert_hflags_rebuild_correctly(CPUARMState *env); |
ccd38087 | 1405 | #endif |