[mirror_qemu.git] / target / arm / sve.decode

# AArch64 SVE instruction descriptions
#
#  Copyright (c) 2017 Linaro, Ltd
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.

#
# This file is processed by scripts/decodetree.py
#

###########################################################################
# Named fields.  These are primarily for disjoint fields.

%imm4_16_p1             16:4 !function=plus1
%imm6_22_5      22:1 5:5
%imm9_16_10     16:s6 10:3

# A combination of tsz:imm3 -- extract esize.
%tszimm_esz     22:2 5:5 !function=tszimm_esz
# A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3)
%tszimm_shr     22:2 5:5 !function=tszimm_shr
# A combination of tsz:imm3 -- extract (tsz:imm3) - esize
%tszimm_shl     22:2 5:5 !function=tszimm_shl

# Similarly for the tszh/tszl pair at 22/16 for zzi
%tszimm16_esz   22:2 16:5 !function=tszimm_esz
%tszimm16_shr   22:2 16:5 !function=tszimm_shr
%tszimm16_shl   22:2 16:5 !function=tszimm_shl

# Either a copy of rd (at bit 0), or a different source
# as propagated via the MOVPRFX instruction.
%reg_movprfx    0:5

###########################################################################
# Named attribute sets.  These are used to make nice(er) names
# when creating helpers common to those for the individual
# instruction patterns.

&rr_esz         rd rn esz
&rri            rd rn imm
&rrri           rd rn rm imm
&rri_esz        rd rn imm esz
&rrr_esz        rd rn rm esz
&rpr_esz        rd pg rn esz
&rprr_s         rd pg rn rm s
&rprr_esz       rd pg rn rm esz
&rprrr_esz      rd pg rn rm ra esz
&rpri_esz       rd pg rn imm esz
&ptrue          rd esz pat s
&incdec_cnt     rd pat esz imm d u
&incdec2_cnt    rd rn pat esz imm d u

###########################################################################
# Named instruction formats.  These are generally used to
# reduce the amount of duplication between instruction patterns.

# Two operand with unused vector element size
@pd_pn_e0       ........ ........ ....... rn:4 . rd:4           &rr_esz esz=0

# Two operand
@pd_pn          ........ esz:2 .. .... ....... rn:4 . rd:4      &rr_esz
@rd_rn          ........ esz:2 ...... ...... rn:5 rd:5          &rr_esz

# Three operand with unused vector element size
@rd_rn_rm_e0    ........ ... rm:5 ... ... rn:5 rd:5             &rrr_esz esz=0

# Three predicate operand, with governing predicate, flag setting
@pd_pg_pn_pm_s  ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4    &rprr_s

# Three operand, vector element size
@rd_rn_rm       ........ esz:2 . rm:5 ... ... rn:5 rd:5         &rrr_esz

# Three operand with "memory" size, aka immediate left shift
@rd_rn_msz_rm   ........ ... rm:5 .... imm:2 rn:5 rd:5          &rrri

# Two register operand, with governing predicate, vector element size
@rdn_pg_rm      ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
                &rprr_esz rn=%reg_movprfx
@rdm_pg_rn      ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
                &rprr_esz rm=%reg_movprfx

# Three register operand, with governing predicate, vector element size
@rda_pg_rn_rm   ........ esz:2 . rm:5  ... pg:3 rn:5 rd:5 \
                &rprrr_esz ra=%reg_movprfx
@rdn_pg_ra_rm   ........ esz:2 . rm:5  ... pg:3 ra:5 rd:5 \
                &rprrr_esz rn=%reg_movprfx

# One register operand, with governing predicate, vector element size
@rd_pg_rn       ........ esz:2 ... ... ... pg:3 rn:5 rd:5       &rpr_esz

# Two register operands with a 6-bit signed immediate.
@rd_rn_i6       ........ ... rn:5 ..... imm:s6 rd:5             &rri

# Two register operand, one immediate operand, with predicate,
# element size encoded as TSZHL.  User must fill in imm.
@rdn_pg_tszimm  ........ .. ... ... ... pg:3 ..... rd:5 \
                &rpri_esz rn=%reg_movprfx esz=%tszimm_esz

# Similarly without predicate.
@rd_rn_tszimm   ........ .. ... ... ...... rn:5 rd:5 \
                &rri_esz esz=%tszimm16_esz

# Basic Load/Store with 9-bit immediate offset
@pd_rn_i9       ........ ........ ...... rn:5 . rd:4    \
                &rri imm=%imm9_16_10
@rd_rn_i9       ........ ........ ...... rn:5 rd:5      \
                &rri imm=%imm9_16_10

# One register, pattern, and uint4+1.
# User must fill in U and D.
@incdec_cnt     ........ esz:2 .. .... ...... pat:5 rd:5 \
                &incdec_cnt imm=%imm4_16_p1
@incdec2_cnt    ........ esz:2 .. .... ...... pat:5 rd:5 \
                &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx

###########################################################################
# Instruction patterns.  Grouped according to the SVE encodingindex.xhtml.

### SVE Integer Arithmetic - Binary Predicated Group

# SVE bitwise logical vector operations (predicated)
ORR_zpzz        00000100 .. 011 000 000 ... ..... .....   @rdn_pg_rm
EOR_zpzz        00000100 .. 011 001 000 ... ..... .....   @rdn_pg_rm
AND_zpzz        00000100 .. 011 010 000 ... ..... .....   @rdn_pg_rm
BIC_zpzz        00000100 .. 011 011 000 ... ..... .....   @rdn_pg_rm

# SVE integer add/subtract vectors (predicated)
ADD_zpzz        00000100 .. 000 000 000 ... ..... .....   @rdn_pg_rm
SUB_zpzz        00000100 .. 000 001 000 ... ..... .....   @rdn_pg_rm
SUB_zpzz        00000100 .. 000 011 000 ... ..... .....   @rdm_pg_rn # SUBR

# SVE integer min/max/difference (predicated)
SMAX_zpzz       00000100 .. 001 000 000 ... ..... .....   @rdn_pg_rm
UMAX_zpzz       00000100 .. 001 001 000 ... ..... .....   @rdn_pg_rm
SMIN_zpzz       00000100 .. 001 010 000 ... ..... .....   @rdn_pg_rm
UMIN_zpzz       00000100 .. 001 011 000 ... ..... .....   @rdn_pg_rm
SABD_zpzz       00000100 .. 001 100 000 ... ..... .....   @rdn_pg_rm
UABD_zpzz       00000100 .. 001 101 000 ... ..... .....   @rdn_pg_rm

# SVE integer multiply/divide (predicated)
MUL_zpzz        00000100 .. 010 000 000 ... ..... .....   @rdn_pg_rm
SMULH_zpzz      00000100 .. 010 010 000 ... ..... .....   @rdn_pg_rm
UMULH_zpzz      00000100 .. 010 011 000 ... ..... .....   @rdn_pg_rm
# Note that divide requires size >= 2; below 2 is unallocated.
SDIV_zpzz       00000100 .. 010 100 000 ... ..... .....   @rdn_pg_rm
UDIV_zpzz       00000100 .. 010 101 000 ... ..... .....   @rdn_pg_rm
SDIV_zpzz       00000100 .. 010 110 000 ... ..... .....   @rdm_pg_rn # SDIVR
UDIV_zpzz       00000100 .. 010 111 000 ... ..... .....   @rdm_pg_rn # UDIVR

### SVE Integer Reduction Group

# SVE bitwise logical reduction (predicated)
ORV             00000100 .. 011 000 001 ... ..... .....         @rd_pg_rn
EORV            00000100 .. 011 001 001 ... ..... .....         @rd_pg_rn
ANDV            00000100 .. 011 010 001 ... ..... .....         @rd_pg_rn

# SVE integer add reduction (predicated)
# Note that saddv requires size != 3.
UADDV           00000100 .. 000 001 001 ... ..... .....         @rd_pg_rn
SADDV           00000100 .. 000 000 001 ... ..... .....         @rd_pg_rn

# SVE integer min/max reduction (predicated)
SMAXV           00000100 .. 001 000 001 ... ..... .....         @rd_pg_rn
UMAXV           00000100 .. 001 001 001 ... ..... .....         @rd_pg_rn
SMINV           00000100 .. 001 010 001 ... ..... .....         @rd_pg_rn
UMINV           00000100 .. 001 011 001 ... ..... .....         @rd_pg_rn

### SVE Shift by Immediate - Predicated Group

# SVE bitwise shift by immediate (predicated)
ASR_zpzi        00000100 .. 000 000 100 ... .. ... ..... \
                @rdn_pg_tszimm imm=%tszimm_shr
LSR_zpzi        00000100 .. 000 001 100 ... .. ... ..... \
                @rdn_pg_tszimm imm=%tszimm_shr
LSL_zpzi        00000100 .. 000 011 100 ... .. ... ..... \
                @rdn_pg_tszimm imm=%tszimm_shl
ASRD            00000100 .. 000 100 100 ... .. ... ..... \
                @rdn_pg_tszimm imm=%tszimm_shr

# SVE bitwise shift by vector (predicated)
ASR_zpzz        00000100 .. 010 000 100 ... ..... .....   @rdn_pg_rm
LSR_zpzz        00000100 .. 010 001 100 ... ..... .....   @rdn_pg_rm
LSL_zpzz        00000100 .. 010 011 100 ... ..... .....   @rdn_pg_rm
ASR_zpzz        00000100 .. 010 100 100 ... ..... .....   @rdm_pg_rn # ASRR
LSR_zpzz        00000100 .. 010 101 100 ... ..... .....   @rdm_pg_rn # LSRR
LSL_zpzz        00000100 .. 010 111 100 ... ..... .....   @rdm_pg_rn # LSLR

# SVE bitwise shift by wide elements (predicated)
# Note these require size != 3.
ASR_zpzw        00000100 .. 011 000 100 ... ..... .....         @rdn_pg_rm
LSR_zpzw        00000100 .. 011 001 100 ... ..... .....         @rdn_pg_rm
LSL_zpzw        00000100 .. 011 011 100 ... ..... .....         @rdn_pg_rm

### SVE Integer Arithmetic - Unary Predicated Group

# SVE unary bit operations (predicated)
# Note esz != 0 for FABS and FNEG.
CLS             00000100 .. 011 000 101 ... ..... .....         @rd_pg_rn
CLZ             00000100 .. 011 001 101 ... ..... .....         @rd_pg_rn
CNT_zpz         00000100 .. 011 010 101 ... ..... .....         @rd_pg_rn
CNOT            00000100 .. 011 011 101 ... ..... .....         @rd_pg_rn
NOT_zpz         00000100 .. 011 110 101 ... ..... .....         @rd_pg_rn
FABS            00000100 .. 011 100 101 ... ..... .....         @rd_pg_rn
FNEG            00000100 .. 011 101 101 ... ..... .....         @rd_pg_rn

# SVE integer unary operations (predicated)
# Note esz > original size for extensions.
ABS             00000100 .. 010 110 101 ... ..... .....         @rd_pg_rn
NEG             00000100 .. 010 111 101 ... ..... .....         @rd_pg_rn
SXTB            00000100 .. 010 000 101 ... ..... .....         @rd_pg_rn
UXTB            00000100 .. 010 001 101 ... ..... .....         @rd_pg_rn
SXTH            00000100 .. 010 010 101 ... ..... .....         @rd_pg_rn
UXTH            00000100 .. 010 011 101 ... ..... .....         @rd_pg_rn
SXTW            00000100 .. 010 100 101 ... ..... .....         @rd_pg_rn
UXTW            00000100 .. 010 101 101 ... ..... .....         @rd_pg_rn

### SVE Integer Multiply-Add Group

# SVE integer multiply-add writing addend (predicated)
MLA             00000100 .. 0 ..... 010 ... ..... .....   @rda_pg_rn_rm
MLS             00000100 .. 0 ..... 011 ... ..... .....   @rda_pg_rn_rm

# SVE integer multiply-add writing multiplicand (predicated)
MLA             00000100 .. 0 ..... 110 ... ..... .....   @rdn_pg_ra_rm # MAD
MLS             00000100 .. 0 ..... 111 ... ..... .....   @rdn_pg_ra_rm # MSB

### SVE Integer Arithmetic - Unpredicated Group

# SVE integer add/subtract vectors (unpredicated)
ADD_zzz         00000100 .. 1 ..... 000 000 ..... .....         @rd_rn_rm
SUB_zzz         00000100 .. 1 ..... 000 001 ..... .....         @rd_rn_rm
SQADD_zzz       00000100 .. 1 ..... 000 100 ..... .....         @rd_rn_rm
UQADD_zzz       00000100 .. 1 ..... 000 101 ..... .....         @rd_rn_rm
SQSUB_zzz       00000100 .. 1 ..... 000 110 ..... .....         @rd_rn_rm
UQSUB_zzz       00000100 .. 1 ..... 000 111 ..... .....         @rd_rn_rm

### SVE Logical - Unpredicated Group

# SVE bitwise logical operations (unpredicated)
AND_zzz         00000100 00 1 ..... 001 100 ..... .....         @rd_rn_rm_e0
ORR_zzz         00000100 01 1 ..... 001 100 ..... .....         @rd_rn_rm_e0
EOR_zzz         00000100 10 1 ..... 001 100 ..... .....         @rd_rn_rm_e0
BIC_zzz         00000100 11 1 ..... 001 100 ..... .....         @rd_rn_rm_e0

### SVE Index Generation Group

# SVE index generation (immediate start, immediate increment)
INDEX_ii        00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5

# SVE index generation (immediate start, register increment)
INDEX_ir        00000100 esz:2 1 rm:5 010010 imm:s5 rd:5

# SVE index generation (register start, immediate increment)
INDEX_ri        00000100 esz:2 1 imm:s5 010001 rn:5 rd:5

# SVE index generation (register start, register increment)
INDEX_rr        00000100 .. 1 ..... 010011 ..... .....          @rd_rn_rm

### SVE Stack Allocation Group

# SVE stack frame adjustment
ADDVL           00000100 001 ..... 01010 ...... .....           @rd_rn_i6
ADDPL           00000100 011 ..... 01010 ...... .....           @rd_rn_i6

# SVE stack frame size
RDVL            00000100 101 11111 01010 imm:s6 rd:5

### SVE Bitwise Shift - Unpredicated Group

# SVE bitwise shift by immediate (unpredicated)
ASR_zzi         00000100 .. 1 ..... 1001 00 ..... ..... \
                @rd_rn_tszimm imm=%tszimm16_shr
LSR_zzi         00000100 .. 1 ..... 1001 01 ..... ..... \
                @rd_rn_tszimm imm=%tszimm16_shr
LSL_zzi         00000100 .. 1 ..... 1001 11 ..... ..... \
                @rd_rn_tszimm imm=%tszimm16_shl

# SVE bitwise shift by wide elements (unpredicated)
# Note esz != 3
ASR_zzw         00000100 .. 1 ..... 1000 00 ..... .....         @rd_rn_rm
LSR_zzw         00000100 .. 1 ..... 1000 01 ..... .....         @rd_rn_rm
LSL_zzw         00000100 .. 1 ..... 1000 11 ..... .....         @rd_rn_rm

### SVE Compute Vector Address Group

# SVE vector address generation
ADR_s32         00000100 00 1 ..... 1010 .. ..... .....         @rd_rn_msz_rm
ADR_u32         00000100 01 1 ..... 1010 .. ..... .....         @rd_rn_msz_rm
ADR_p32         00000100 10 1 ..... 1010 .. ..... .....         @rd_rn_msz_rm
ADR_p64         00000100 11 1 ..... 1010 .. ..... .....         @rd_rn_msz_rm

### SVE Integer Misc - Unpredicated Group

# SVE floating-point exponential accelerator
# Note esz != 0
FEXPA           00000100 .. 1 00000 101110 ..... .....          @rd_rn

# SVE floating-point trig select coefficient
# Note esz != 0
FTSSEL          00000100 .. 1 ..... 101100 ..... .....          @rd_rn_rm

### SVE Element Count Group

# SVE element count
CNT_r           00000100 .. 10 .... 1110 0 0 ..... .....    @incdec_cnt d=0 u=1

# SVE inc/dec register by element count
INCDEC_r        00000100 .. 11 .... 1110 0 d:1 ..... .....      @incdec_cnt u=1

# SVE saturating inc/dec register by element count
SINCDEC_r_32    00000100 .. 10 .... 1111 d:1 u:1 ..... .....    @incdec_cnt
SINCDEC_r_64    00000100 .. 11 .... 1111 d:1 u:1 ..... .....    @incdec_cnt

# SVE inc/dec vector by element count
# Note this requires esz != 0.
INCDEC_v        00000100 .. 1 1 .... 1100 0 d:1 ..... .....    @incdec2_cnt u=1

# SVE saturating inc/dec vector by element count
# Note these require esz != 0.
SINCDEC_v       00000100 .. 1 0 .... 1100 d:1 u:1 ..... .....   @incdec2_cnt

# SVE predicate logical operations
AND_pppp        00100101 0. 00 .... 01 .... 0 .... 0 ....       @pd_pg_pn_pm_s
BIC_pppp        00100101 0. 00 .... 01 .... 0 .... 1 ....       @pd_pg_pn_pm_s
EOR_pppp        00100101 0. 00 .... 01 .... 1 .... 0 ....       @pd_pg_pn_pm_s
SEL_pppp        00100101 0. 00 .... 01 .... 1 .... 1 ....       @pd_pg_pn_pm_s
ORR_pppp        00100101 1. 00 .... 01 .... 0 .... 0 ....       @pd_pg_pn_pm_s
ORN_pppp        00100101 1. 00 .... 01 .... 0 .... 1 ....       @pd_pg_pn_pm_s
NOR_pppp        00100101 1. 00 .... 01 .... 1 .... 0 ....       @pd_pg_pn_pm_s
NAND_pppp       00100101 1. 00 .... 01 .... 1 .... 1 ....       @pd_pg_pn_pm_s

### SVE Predicate Misc Group

# SVE predicate test
PTEST           00100101 01 010000 11 pg:4 0 rn:4 0 0000

# SVE predicate initialize
PTRUE           00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4

# SVE initialize FFR
SETFFR          00100101 0010 1100 1001 0000 0000 0000

# SVE zero predicate register
PFALSE          00100101 0001 1000 1110 0100 0000 rd:4

# SVE predicate read from FFR (predicated)
RDFFR_p         00100101 0 s:1 0110001111000 pg:4 0 rd:4

# SVE predicate read from FFR (unpredicated)
RDFFR           00100101 0001 1001 1111 0000 0000 rd:4

# SVE FFR write from predicate (WRFFR)
WRFFR           00100101 0010 1000 1001 000 rn:4 00000

# SVE predicate first active
PFIRST          00100101 01 011 000 11000 00 .... 0 ....        @pd_pn_e0

# SVE predicate next active
PNEXT           00100101 .. 011 001 11000 10 .... 0 ....        @pd_pn

### SVE Memory - 32-bit Gather and Unsized Contiguous Group

# SVE load predicate register
LDR_pri         10000101 10 ...... 000 ... ..... 0 ....         @pd_rn_i9

# SVE load vector register
LDR_zri         10000101 10 ...... 010 ... ..... .....          @rd_rn_i9
Commit	Line	Data
38388f7e RH	1	# AArch64 SVE instruction descriptions
	2	#
	3	# Copyright (c) 2017 Linaro, Ltd
	4	#
	5	# This library is free software; you can redistribute it and/or
	6	# modify it under the terms of the GNU Lesser General Public
	7	# License as published by the Free Software Foundation; either
	8	# version 2 of the License, or (at your option) any later version.
	9	#
	10	# This library is distributed in the hope that it will be useful,
	11	# but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	# Lesser General Public License for more details.
	14	#
	15	# You should have received a copy of the GNU Lesser General Public
	16	# License along with this library; if not, see <http://www.gnu.org/licenses/>.
	17
	18	#
	19	# This file is processed by scripts/decodetree.py
	20	#
	21
d1822297 RH	22	###########################################################################
	23	# Named fields. These are primarily for disjoint fields.
	24
24e82e68	25	%imm4_16_p1 16:4 !function=plus1
ccd841c3	26	%imm6_22_5 22:1 5:5
d1822297 RH	27	%imm9_16_10 16:s6 10:3
d1822297 RH	28
ccd841c3 RH	29	# A combination of tsz:imm3 -- extract esize.
	30	%tszimm_esz 22:2 5:5 !function=tszimm_esz
	31	# A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3)
	32	%tszimm_shr 22:2 5:5 !function=tszimm_shr
	33	# A combination of tsz:imm3 -- extract (tsz:imm3) - esize
	34	%tszimm_shl 22:2 5:5 !function=tszimm_shl
	35
d9d78dcc RH	36	# Similarly for the tszh/tszl pair at 22/16 for zzi
	37	%tszimm16_esz 22:2 16:5 !function=tszimm_esz
	38	%tszimm16_shr 22:2 16:5 !function=tszimm_shr
	39	%tszimm16_shl 22:2 16:5 !function=tszimm_shl
	40
f97cfd59 RH	41	# Either a copy of rd (at bit 0), or a different source
	42	# as propagated via the MOVPRFX instruction.
	43	%reg_movprfx 0:5
	44
38388f7e RH	45	###########################################################################
	46	# Named attribute sets. These are used to make nice(er) names
	47	# when creating helpers common to those for the individual
	48	# instruction patterns.
	49
028e2a7b	50	&rr_esz rd rn esz
d1822297	51	&rri rd rn imm
4b242d9c	52	&rrri rd rn rm imm
d9d78dcc	53	&rri_esz rd rn imm esz
38388f7e	54	&rrr_esz rd rn rm esz
047cec97	55	&rpr_esz rd pg rn esz
516e246a	56	&rprr_s rd pg rn rm s
f97cfd59	57	&rprr_esz rd pg rn rm esz
96a36e4a	58	&rprrr_esz rd pg rn rm ra esz
ccd841c3	59	&rpri_esz rd pg rn imm esz
24e82e68 RH	60	&ptrue rd esz pat s
	61	&incdec_cnt rd pat esz imm d u
	62	&incdec2_cnt rd rn pat esz imm d u
38388f7e RH	63
	64	###########################################################################
	65	# Named instruction formats. These are generally used to
	66	# reduce the amount of duplication between instruction patterns.
	67
028e2a7b RH	68	# Two operand with unused vector element size
	69	@pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
	70
	71	# Two operand
	72	@pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
0762cd42	73	@rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz
028e2a7b	74
38388f7e RH	75	# Three operand with unused vector element size
	76	@rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
	77
516e246a RH	78	# Three predicate operand, with governing predicate, flag setting
	79	@pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s
	80
fea98f9c RH	81	# Three operand, vector element size
	82	@rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz
	83
4b242d9c RH	84	# Three operand with "memory" size, aka immediate left shift
	85	@rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri
	86
f97cfd59 RH	87	# Two register operand, with governing predicate, vector element size
	88	@rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
	89	&rprr_esz rn=%reg_movprfx
	90	@rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
	91	&rprr_esz rm=%reg_movprfx
	92
96a36e4a RH	93	# Three register operand, with governing predicate, vector element size
	94	@rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \
	95	&rprrr_esz ra=%reg_movprfx
	96	@rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \
	97	&rprrr_esz rn=%reg_movprfx
	98
047cec97 RH	99	# One register operand, with governing predicate, vector element size
	100	@rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz
	101
96f922cc RH	102	# Two register operands with a 6-bit signed immediate.
	103	@rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
	104
ccd841c3 RH	105	# Two register operand, one immediate operand, with predicate,
	106	# element size encoded as TSZHL. User must fill in imm.
	107	@rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \
	108	&rpri_esz rn=%reg_movprfx esz=%tszimm_esz
	109
d9d78dcc RH	110	# Similarly without predicate.
	111	@rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \
	112	&rri_esz esz=%tszimm16_esz
	113
d1822297 RH	114	# Basic Load/Store with 9-bit immediate offset
	115	@pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \
	116	&rri imm=%imm9_16_10
	117	@rd_rn_i9 ........ ........ ...... rn:5 rd:5 \
	118	&rri imm=%imm9_16_10
	119
24e82e68 RH	120	# One register, pattern, and uint4+1.
	121	# User must fill in U and D.
	122	@incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
	123	&incdec_cnt imm=%imm4_16_p1
	124	@incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
	125	&incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx
	126
38388f7e RH	127	###########################################################################
	128	# Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
	129
f97cfd59 RH	130	### SVE Integer Arithmetic - Binary Predicated Group
	131
	132	# SVE bitwise logical vector operations (predicated)
	133	ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm
	134	EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm
	135	AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm
	136	BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm
	137
	138	# SVE integer add/subtract vectors (predicated)
	139	ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm
	140	SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm
	141	SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR
	142
	143	# SVE integer min/max/difference (predicated)
	144	SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm
	145	UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm
	146	SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm
	147	UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm
	148	SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm
	149	UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm
	150
	151	# SVE integer multiply/divide (predicated)
	152	MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm
	153	SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm
	154	UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm
	155	# Note that divide requires size >= 2; below 2 is unallocated.
	156	SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm
	157	UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm
	158	SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR
	159	UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR
	160
047cec97 RH	161	### SVE Integer Reduction Group
	162
	163	# SVE bitwise logical reduction (predicated)
	164	ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn
	165	EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn
	166	ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn
	167
	168	# SVE integer add reduction (predicated)
	169	# Note that saddv requires size != 3.
	170	UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn
	171	SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn
	172
	173	# SVE integer min/max reduction (predicated)
	174	SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn
	175	UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn
	176	SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn
	177	UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
	178
ccd841c3 RH	179	### SVE Shift by Immediate - Predicated Group
	180
	181	# SVE bitwise shift by immediate (predicated)
	182	ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \
	183	@rdn_pg_tszimm imm=%tszimm_shr
	184	LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \
	185	@rdn_pg_tszimm imm=%tszimm_shr
	186	LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \
	187	@rdn_pg_tszimm imm=%tszimm_shl
	188	ASRD 00000100 .. 000 100 100 ... .. ... ..... \
	189	@rdn_pg_tszimm imm=%tszimm_shr
	190
27721dbb RH	191	# SVE bitwise shift by vector (predicated)
	192	ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
	193	LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm
	194	LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm
	195	ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR
	196	LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR
	197	LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR
	198
fe7f8dfb RH	199	# SVE bitwise shift by wide elements (predicated)
	200	# Note these require size != 3.
	201	ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm
	202	LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm
	203	LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm
	204
afac6d04 RH	205	### SVE Integer Arithmetic - Unary Predicated Group
	206
	207	# SVE unary bit operations (predicated)
	208	# Note esz != 0 for FABS and FNEG.
	209	CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn
	210	CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn
	211	CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn
	212	CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn
	213	NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn
	214	FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn
	215	FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn
	216
	217	# SVE integer unary operations (predicated)
	218	# Note esz > original size for extensions.
	219	ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn
	220	NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn
	221	SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn
	222	UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn
	223	SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn
	224	UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn
	225	SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn
	226	UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn
	227
96a36e4a RH	228	### SVE Integer Multiply-Add Group
	229
	230	# SVE integer multiply-add writing addend (predicated)
	231	MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm
	232	MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm
	233
	234	# SVE integer multiply-add writing multiplicand (predicated)
	235	MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD
	236	MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB
	237
fea98f9c RH	238	### SVE Integer Arithmetic - Unpredicated Group
	239
	240	# SVE integer add/subtract vectors (unpredicated)
	241	ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm
	242	SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm
	243	SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm
	244	UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm
	245	SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm
	246	UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm
	247
38388f7e RH	248	### SVE Logical - Unpredicated Group
	249
	250	# SVE bitwise logical operations (unpredicated)
	251	AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
	252	ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
	253	EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
	254	BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
d1822297	255
9a56c9c3 RH	256	### SVE Index Generation Group
	257
	258	# SVE index generation (immediate start, immediate increment)
	259	INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5
	260
	261	# SVE index generation (immediate start, register increment)
	262	INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5
	263
	264	# SVE index generation (register start, immediate increment)
	265	INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5
	266
	267	# SVE index generation (register start, register increment)
	268	INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm
	269
96f922cc RH	270	### SVE Stack Allocation Group
	271
	272	# SVE stack frame adjustment
	273	ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6
	274	ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6
	275
	276	# SVE stack frame size
	277	RDVL 00000100 101 11111 01010 imm:s6 rd:5
	278
d9d78dcc RH	279	### SVE Bitwise Shift - Unpredicated Group
	280
	281	# SVE bitwise shift by immediate (unpredicated)
	282	ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \
	283	@rd_rn_tszimm imm=%tszimm16_shr
	284	LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \
	285	@rd_rn_tszimm imm=%tszimm16_shr
	286	LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \
	287	@rd_rn_tszimm imm=%tszimm16_shl
	288
	289	# SVE bitwise shift by wide elements (unpredicated)
	290	# Note esz != 3
	291	ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm
	292	LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm
	293	LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm
	294
4b242d9c RH	295	### SVE Compute Vector Address Group
	296
	297	# SVE vector address generation
	298	ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
	299	ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
	300	ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
	301	ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
	302
0762cd42 RH	303	### SVE Integer Misc - Unpredicated Group
	304
	305	# SVE floating-point exponential accelerator
	306	# Note esz != 0
	307	FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn
	308
a1f233f2 RH	309	# SVE floating-point trig select coefficient
	310	# Note esz != 0
	311	FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm
	312
24e82e68 RH	313	### SVE Element Count Group
	314
	315	# SVE element count
	316	CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1
	317
	318	# SVE inc/dec register by element count
	319	INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1
	320
	321	# SVE saturating inc/dec register by element count
	322	SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
	323	SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
	324
	325	# SVE inc/dec vector by element count
	326	# Note this requires esz != 0.
	327	INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1
	328
	329	# SVE saturating inc/dec vector by element count
	330	# Note these require esz != 0.
	331	SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt
516e246a RH	332
	333	# SVE predicate logical operations
	334	AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
	335	BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
	336	EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
	337	SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
	338	ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
	339	ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
	340	NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
	341	NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
	342
9e18d7a6 RH	343	### SVE Predicate Misc Group
	344
	345	# SVE predicate test
	346	PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000
	347
028e2a7b RH	348	# SVE predicate initialize
	349	PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4
	350
	351	# SVE initialize FFR
	352	SETFFR 00100101 0010 1100 1001 0000 0000 0000
	353
	354	# SVE zero predicate register
	355	PFALSE 00100101 0001 1000 1110 0100 0000 rd:4
	356
	357	# SVE predicate read from FFR (predicated)
	358	RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4
	359
	360	# SVE predicate read from FFR (unpredicated)
	361	RDFFR 00100101 0001 1001 1111 0000 0000 rd:4
	362
	363	# SVE FFR write from predicate (WRFFR)
	364	WRFFR 00100101 0010 1000 1001 000 rn:4 00000
	365
	366	# SVE predicate first active
	367	PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0
	368
	369	# SVE predicate next active
	370	PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn
	371
d1822297 RH	372	### SVE Memory - 32-bit Gather and Unsized Contiguous Group
	373
	374	# SVE load predicate register
	375	LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9
	376
	377	# SVE load vector register
	378	LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9