projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 38388f7e RH |
1 | # AArch64 SVE instruction descriptions |
| 2 | # | |
| 3 | # Copyright (c) 2017 Linaro, Ltd | |
| 4 | # | |
| 5 | # This library is free software; you can redistribute it and/or | |
| 6 | # modify it under the terms of the GNU Lesser General Public | |
| 7 | # License as published by the Free Software Foundation; either | |
| 8 | # version 2 of the License, or (at your option) any later version. | |
| 9 | # | |
| 10 | # This library is distributed in the hope that it will be useful, | |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 13 | # Lesser General Public License for more details. | |
| 14 | # | |
| 15 | # You should have received a copy of the GNU Lesser General Public | |
| 16 | # License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
| 17 | ||
| 18 | # | |
| 19 | # This file is processed by scripts/decodetree.py | |
| 20 | # | |
| 21 | ||
| d1822297 RH |
22 | ########################################################################### |
| 23 | # Named fields. These are primarily for disjoint fields. | |
| 24 | ||
| f25a2361 | 25 | %imm4_16_p1 16:4 !function=plus1 |
| ccd841c3 | 26 | %imm6_22_5 22:1 5:5 |
| 30562ab7 | 27 | %imm7_22_16 22:2 16:5 |
| b94f8f60 | 28 | %imm8_16_10 16:5 10:3 |
| d1822297 RH |
29 | %imm9_16_10 16:s6 10:3 |
| 30 | ||
| ccd841c3 RH |
31 | # A combination of tsz:imm3 -- extract esize. |
| 32 | %tszimm_esz 22:2 5:5 !function=tszimm_esz | |
| 33 | # A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3) | |
| 34 | %tszimm_shr 22:2 5:5 !function=tszimm_shr | |
| 35 | # A combination of tsz:imm3 -- extract (tsz:imm3) - esize | |
| 36 | %tszimm_shl 22:2 5:5 !function=tszimm_shl | |
| 37 | ||
| d9d78dcc RH |
38 | # Similarly for the tszh/tszl pair at 22/16 for zzi |
| 39 | %tszimm16_esz 22:2 16:5 !function=tszimm_esz | |
| 40 | %tszimm16_shr 22:2 16:5 !function=tszimm_shr | |
| 41 | %tszimm16_shl 22:2 16:5 !function=tszimm_shl | |
| 42 | ||
| f25a2361 RH |
43 | # Signed 8-bit immediate, optionally shifted left by 8. |
| 44 | %sh8_i8s 5:9 !function=expand_imm_sh8s | |
| 45 | ||
| f97cfd59 RH |
46 | # Either a copy of rd (at bit 0), or a different source |
| 47 | # as propagated via the MOVPRFX instruction. | |
| 48 | %reg_movprfx 0:5 | |
| 49 | ||
| 38388f7e RH |
50 | ########################################################################### |
| 51 | # Named attribute sets. These are used to make nice(er) names | |
| 52 | # when creating helpers common to those for the individual | |
| 53 | # instruction patterns. | |
| 54 | ||
| 028e2a7b | 55 | &rr_esz rd rn esz |
| d1822297 | 56 | &rri rd rn imm |
| e1fa1164 | 57 | &rr_dbm rd rn dbm |
| 4b242d9c | 58 | &rrri rd rn rm imm |
| d9d78dcc | 59 | &rri_esz rd rn imm esz |
| 38388f7e | 60 | &rrr_esz rd rn rm esz |
| 047cec97 | 61 | &rpr_esz rd pg rn esz |
| 516e246a | 62 | &rprr_s rd pg rn rm s |
| f97cfd59 | 63 | &rprr_esz rd pg rn rm esz |
| 96a36e4a | 64 | &rprrr_esz rd pg rn rm ra esz |
| ccd841c3 | 65 | &rpri_esz rd pg rn imm esz |
| 24e82e68 RH |
66 | &ptrue rd esz pat s |
| 67 | &incdec_cnt rd pat esz imm d u | |
| 68 | &incdec2_cnt rd rn pat esz imm d u | |
| 38388f7e RH |
69 | |
| 70 | ########################################################################### | |
| 71 | # Named instruction formats. These are generally used to | |
| 72 | # reduce the amount of duplication between instruction patterns. | |
| 73 | ||
| 028e2a7b RH |
74 | # Two operand with unused vector element size |
| 75 | @pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0 | |
| 76 | ||
| 77 | # Two operand | |
| 78 | @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz | |
| 0762cd42 | 79 | @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz |
| 028e2a7b | 80 | |
| 38388f7e RH |
81 | # Three operand with unused vector element size |
| 82 | @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 | |
| 83 | ||
| 516e246a RH |
84 | # Three predicate operand, with governing predicate, flag setting |
| 85 | @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s | |
| 86 | ||
| fea98f9c RH |
87 | # Three operand, vector element size |
| 88 | @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz | |
| d731d8cb | 89 | @pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz |
| 30562ab7 RH |
90 | @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \ |
| 91 | &rrr_esz rn=%reg_movprfx | |
| fea98f9c | 92 | |
| 4b242d9c RH |
93 | # Three operand with "memory" size, aka immediate left shift |
| 94 | @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri | |
| 95 | ||
| f97cfd59 RH |
96 | # Two register operand, with governing predicate, vector element size |
| 97 | @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \ | |
| 98 | &rprr_esz rn=%reg_movprfx | |
| 99 | @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ | |
| 100 | &rprr_esz rm=%reg_movprfx | |
| d3fe4a29 | 101 | @rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz |
| 757f9cff | 102 | @pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz |
| f97cfd59 | 103 | |
| 96a36e4a RH |
104 | # Three register operand, with governing predicate, vector element size |
| 105 | @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ | |
| 106 | &rprrr_esz ra=%reg_movprfx | |
| 107 | @rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \ | |
| 108 | &rprrr_esz rn=%reg_movprfx | |
| 109 | ||
| 047cec97 RH |
110 | # One register operand, with governing predicate, vector element size |
| 111 | @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz | |
| 112 | ||
| 96f922cc RH |
113 | # Two register operands with a 6-bit signed immediate. |
| 114 | @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri | |
| 115 | ||
| ccd841c3 RH |
116 | # Two register operand, one immediate operand, with predicate, |
| 117 | # element size encoded as TSZHL. User must fill in imm. | |
| 118 | @rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \ | |
| 119 | &rpri_esz rn=%reg_movprfx esz=%tszimm_esz | |
| 120 | ||
| d9d78dcc RH |
121 | # Similarly without predicate. |
| 122 | @rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \ | |
| 123 | &rri_esz esz=%tszimm16_esz | |
| 124 | ||
| f25a2361 RH |
125 | # Two register operand, one immediate operand, with 4-bit predicate. |
| 126 | # User must fill in imm. | |
| 127 | @rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \ | |
| 128 | &rpri_esz rn=%reg_movprfx | |
| 129 | ||
| e1fa1164 RH |
130 | # Two register operand, one encoded bitmask. |
| 131 | @rdn_dbm ........ .. .... dbm:13 rd:5 \ | |
| 132 | &rr_dbm rn=%reg_movprfx | |
| 133 | ||
| 38cadeba RH |
134 | # Predicate output, vector and immediate input, |
| 135 | # controlling predicate, element size. | |
| 136 | @pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz | |
| 137 | @pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz | |
| 138 | ||
| d1822297 RH |
139 | # Basic Load/Store with 9-bit immediate offset |
| 140 | @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ | |
| 141 | &rri imm=%imm9_16_10 | |
| 142 | @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \ | |
| 143 | &rri imm=%imm9_16_10 | |
| 144 | ||
| 24e82e68 RH |
145 | # One register, pattern, and uint4+1. |
| 146 | # User must fill in U and D. | |
| 147 | @incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ | |
| 148 | &incdec_cnt imm=%imm4_16_p1 | |
| 149 | @incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ | |
| 150 | &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx | |
| 151 | ||
| 38388f7e RH |
152 | ########################################################################### |
| 153 | # Instruction patterns. Grouped according to the SVE encodingindex.xhtml. | |
| 154 | ||
| f97cfd59 RH |
155 | ### SVE Integer Arithmetic - Binary Predicated Group |
| 156 | ||
| 157 | # SVE bitwise logical vector operations (predicated) | |
| 158 | ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm | |
| 159 | EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm | |
| 160 | AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm | |
| 161 | BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm | |
| 162 | ||
| 163 | # SVE integer add/subtract vectors (predicated) | |
| 164 | ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm | |
| 165 | SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm | |
| 166 | SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR | |
| 167 | ||
| 168 | # SVE integer min/max/difference (predicated) | |
| 169 | SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm | |
| 170 | UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm | |
| 171 | SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm | |
| 172 | UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm | |
| 173 | SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm | |
| 174 | UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm | |
| 175 | ||
| 176 | # SVE integer multiply/divide (predicated) | |
| 177 | MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm | |
| 178 | SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm | |
| 179 | UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm | |
| 180 | # Note that divide requires size >= 2; below 2 is unallocated. | |
| 181 | SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm | |
| 182 | UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm | |
| 183 | SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR | |
| 184 | UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR | |
| 185 | ||
| 047cec97 RH |
186 | ### SVE Integer Reduction Group |
| 187 | ||
| 188 | # SVE bitwise logical reduction (predicated) | |
| 189 | ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn | |
| 190 | EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn | |
| 191 | ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn | |
| 192 | ||
| 193 | # SVE integer add reduction (predicated) | |
| 194 | # Note that saddv requires size != 3. | |
| 195 | UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn | |
| 196 | SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn | |
| 197 | ||
| 198 | # SVE integer min/max reduction (predicated) | |
| 199 | SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn | |
| 200 | UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn | |
| 201 | SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn | |
| 202 | UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn | |
| 203 | ||
| ccd841c3 RH |
204 | ### SVE Shift by Immediate - Predicated Group |
| 205 | ||
| 206 | # SVE bitwise shift by immediate (predicated) | |
| 207 | ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \ | |
| 208 | @rdn_pg_tszimm imm=%tszimm_shr | |
| 209 | LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \ | |
| 210 | @rdn_pg_tszimm imm=%tszimm_shr | |
| 211 | LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \ | |
| 212 | @rdn_pg_tszimm imm=%tszimm_shl | |
| 213 | ASRD 00000100 .. 000 100 100 ... .. ... ..... \ | |
| 214 | @rdn_pg_tszimm imm=%tszimm_shr | |
| 215 | ||
| 27721dbb RH |
216 | # SVE bitwise shift by vector (predicated) |
| 217 | ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm | |
| 218 | LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm | |
| 219 | LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm | |
| 220 | ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR | |
| 221 | LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR | |
| 222 | LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR | |
| 223 | ||
| fe7f8dfb RH |
224 | # SVE bitwise shift by wide elements (predicated) |
| 225 | # Note these require size != 3. | |
| 226 | ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm | |
| 227 | LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm | |
| 228 | LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm | |
| 229 | ||
| afac6d04 RH |
230 | ### SVE Integer Arithmetic - Unary Predicated Group |
| 231 | ||
| 232 | # SVE unary bit operations (predicated) | |
| 233 | # Note esz != 0 for FABS and FNEG. | |
| 234 | CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn | |
| 235 | CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn | |
| 236 | CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn | |
| 237 | CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn | |
| 238 | NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn | |
| 239 | FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn | |
| 240 | FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn | |
| 241 | ||
| 242 | # SVE integer unary operations (predicated) | |
| 243 | # Note esz > original size for extensions. | |
| 244 | ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn | |
| 245 | NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn | |
| 246 | SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn | |
| 247 | UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn | |
| 248 | SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn | |
| 249 | UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn | |
| 250 | SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn | |
| 251 | UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn | |
| 252 | ||
| 96a36e4a RH |
253 | ### SVE Integer Multiply-Add Group |
| 254 | ||
| 255 | # SVE integer multiply-add writing addend (predicated) | |
| 256 | MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm | |
| 257 | MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm | |
| 258 | ||
| 259 | # SVE integer multiply-add writing multiplicand (predicated) | |
| 260 | MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD | |
| 261 | MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB | |
| 262 | ||
| fea98f9c RH |
263 | ### SVE Integer Arithmetic - Unpredicated Group |
| 264 | ||
| 265 | # SVE integer add/subtract vectors (unpredicated) | |
| 266 | ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm | |
| 267 | SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm | |
| 268 | SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm | |
| 269 | UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm | |
| 270 | SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm | |
| 271 | UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm | |
| 272 | ||
| 38388f7e RH |
273 | ### SVE Logical - Unpredicated Group |
| 274 | ||
| 275 | # SVE bitwise logical operations (unpredicated) | |
| 276 | AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
| 277 | ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
| 278 | EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
| 279 | BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
| d1822297 | 280 | |
| 9a56c9c3 RH |
281 | ### SVE Index Generation Group |
| 282 | ||
| 283 | # SVE index generation (immediate start, immediate increment) | |
| 284 | INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5 | |
| 285 | ||
| 286 | # SVE index generation (immediate start, register increment) | |
| 287 | INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5 | |
| 288 | ||
| 289 | # SVE index generation (register start, immediate increment) | |
| 290 | INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 | |
| 291 | ||
| 292 | # SVE index generation (register start, register increment) | |
| 293 | INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm | |
| 294 | ||
| 96f922cc RH |
295 | ### SVE Stack Allocation Group |
| 296 | ||
| 297 | # SVE stack frame adjustment | |
| 298 | ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 | |
| 299 | ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 | |
| 300 | ||
| 301 | # SVE stack frame size | |
| 302 | RDVL 00000100 101 11111 01010 imm:s6 rd:5 | |
| 303 | ||
| d9d78dcc RH |
304 | ### SVE Bitwise Shift - Unpredicated Group |
| 305 | ||
| 306 | # SVE bitwise shift by immediate (unpredicated) | |
| 307 | ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \ | |
| 308 | @rd_rn_tszimm imm=%tszimm16_shr | |
| 309 | LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \ | |
| 310 | @rd_rn_tszimm imm=%tszimm16_shr | |
| 311 | LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \ | |
| 312 | @rd_rn_tszimm imm=%tszimm16_shl | |
| 313 | ||
| 314 | # SVE bitwise shift by wide elements (unpredicated) | |
| 315 | # Note esz != 3 | |
| 316 | ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm | |
| 317 | LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm | |
| 318 | LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm | |
| 319 | ||
| 4b242d9c RH |
320 | ### SVE Compute Vector Address Group |
| 321 | ||
| 322 | # SVE vector address generation | |
| 323 | ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
| 324 | ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
| 325 | ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
| 326 | ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
| 327 | ||
| 0762cd42 RH |
328 | ### SVE Integer Misc - Unpredicated Group |
| 329 | ||
| 330 | # SVE floating-point exponential accelerator | |
| 331 | # Note esz != 0 | |
| 332 | FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn | |
| 333 | ||
| a1f233f2 RH |
334 | # SVE floating-point trig select coefficient |
| 335 | # Note esz != 0 | |
| 336 | FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm | |
| 337 | ||
| 24e82e68 RH |
338 | ### SVE Element Count Group |
| 339 | ||
| 340 | # SVE element count | |
| 341 | CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1 | |
| 342 | ||
| 343 | # SVE inc/dec register by element count | |
| 344 | INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1 | |
| 345 | ||
| 346 | # SVE saturating inc/dec register by element count | |
| 347 | SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt | |
| 348 | SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt | |
| 349 | ||
| 350 | # SVE inc/dec vector by element count | |
| 351 | # Note this requires esz != 0. | |
| 352 | INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1 | |
| 353 | ||
| 354 | # SVE saturating inc/dec vector by element count | |
| 355 | # Note these require esz != 0. | |
| 356 | SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt | |
| 516e246a | 357 | |
| e1fa1164 RH |
358 | ### SVE Bitwise Immediate Group |
| 359 | ||
| 360 | # SVE bitwise logical with immediate (unpredicated) | |
| 361 | ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm | |
| 362 | EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm | |
| 363 | AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm | |
| 364 | ||
| 365 | # SVE broadcast bitmask immediate | |
| 366 | DUPM 00000101 11 0000 dbm:13 rd:5 | |
| 367 | ||
| f25a2361 RH |
368 | ### SVE Integer Wide Immediate - Predicated Group |
| 369 | ||
| 370 | # SVE copy floating-point immediate (predicated) | |
| 371 | FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4 | |
| 372 | ||
| 373 | # SVE copy integer immediate (predicated) | |
| 374 | CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s | |
| 375 | CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s | |
| 376 | ||
| b94f8f60 RH |
377 | ### SVE Permute - Extract Group |
| 378 | ||
| 379 | # SVE extract vector (immediate offset) | |
| 380 | EXT 00000101 001 ..... 000 ... rm:5 rd:5 \ | |
| 381 | &rrri rn=%reg_movprfx imm=%imm8_16_10 | |
| 382 | ||
| 30562ab7 RH |
383 | ### SVE Permute - Unpredicated Group |
| 384 | ||
| 385 | # SVE broadcast general register | |
| 386 | DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn | |
| 387 | ||
| 388 | # SVE broadcast indexed element | |
| 389 | DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \ | |
| 390 | &rri imm=%imm7_22_16 | |
| 391 | ||
| 392 | # SVE insert SIMD&FP scalar register | |
| 393 | INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm | |
| 394 | ||
| 395 | # SVE insert general register | |
| 396 | INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm | |
| 397 | ||
| 398 | # SVE reverse vector elements | |
| 399 | REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn | |
| 400 | ||
| 401 | # SVE vector table lookup | |
| 402 | TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm | |
| 403 | ||
| 404 | # SVE unpack vector elements | |
| 405 | UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5 | |
| 406 | ||
| d731d8cb RH |
407 | ### SVE Permute - Predicates Group |
| 408 | ||
| 409 | # SVE permute predicate elements | |
| 410 | ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm | |
| 411 | ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm | |
| 412 | UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm | |
| 413 | UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm | |
| 414 | TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm | |
| 415 | TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm | |
| 416 | ||
| 417 | # SVE reverse predicate elements | |
| 418 | REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn | |
| 419 | ||
| 420 | # SVE unpack predicate elements | |
| 421 | PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0 | |
| 422 | PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0 | |
| 423 | ||
| 234b48e9 RH |
424 | ### SVE Permute - Interleaving Group |
| 425 | ||
| 426 | # SVE permute vector elements | |
| 427 | ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm | |
| 428 | ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm | |
| 429 | UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm | |
| 430 | UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm | |
| 431 | TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm | |
| 432 | TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm | |
| 433 | ||
| 3ca879ae RH |
434 | ### SVE Permute - Predicated Group |
| 435 | ||
| 436 | # SVE compress active elements | |
| 437 | # Note esz >= 2 | |
| 438 | COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn | |
| 439 | ||
| ef23cb72 RH |
440 | # SVE conditionally broadcast element to vector |
| 441 | CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm | |
| 442 | CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm | |
| 443 | ||
| 444 | # SVE conditionally copy element to SIMD&FP scalar | |
| 445 | CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn | |
| 446 | CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn | |
| 447 | ||
| 448 | # SVE conditionally copy element to general register | |
| 449 | CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn | |
| 450 | CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn | |
| 451 | ||
| 452 | # SVE copy element to SIMD&FP scalar register | |
| 453 | LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn | |
| 454 | LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn | |
| 455 | ||
| 456 | # SVE copy element to general register | |
| 457 | LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn | |
| 458 | LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn | |
| 459 | ||
| 792a5578 RH |
460 | # SVE copy element from SIMD&FP scalar register |
| 461 | CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn | |
| 462 | ||
| 463 | # SVE copy element from general register to vector (predicated) | |
| 464 | CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn | |
| 465 | ||
| dae8fb90 RH |
466 | # SVE reverse within elements |
| 467 | # Note esz >= operation size | |
| 468 | REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn | |
| 469 | REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn | |
| 470 | REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn | |
| 471 | RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn | |
| 472 | ||
| b48ff240 RH |
473 | # SVE vector splice (predicated) |
| 474 | SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm | |
| 475 | ||
| d3fe4a29 RH |
476 | ### SVE Select Vectors Group |
| 477 | ||
| 478 | # SVE select vector elements (predicated) | |
| 479 | SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm | |
| 480 | ||
| 757f9cff RH |
481 | ### SVE Integer Compare - Vectors Group |
| 482 | ||
| 483 | # SVE integer compare_vectors | |
| 484 | CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm | |
| 485 | CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm | |
| 486 | CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm | |
| 487 | CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm | |
| 488 | CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm | |
| 489 | CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm | |
| 490 | ||
| 491 | # SVE integer compare with wide elements | |
| 492 | # Note these require esz != 3. | |
| 493 | CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm | |
| 494 | CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm | |
| 495 | CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm | |
| 496 | CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm | |
| 497 | CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm | |
| 498 | CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm | |
| 499 | CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm | |
| 500 | CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm | |
| 501 | CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm | |
| 502 | CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm | |
| 503 | ||
| 38cadeba RH |
504 | ### SVE Integer Compare - Unsigned Immediate Group |
| 505 | ||
| 506 | # SVE integer compare with unsigned immediate | |
| 507 | CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7 | |
| 508 | CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7 | |
| 509 | CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7 | |
| 510 | CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7 | |
| 511 | ||
| 512 | ### SVE Integer Compare - Signed Immediate Group | |
| 513 | ||
| 514 | # SVE integer compare with signed immediate | |
| 515 | CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5 | |
| 516 | CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5 | |
| 517 | CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5 | |
| 518 | CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5 | |
| 519 | CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5 | |
| 520 | CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5 | |
| 521 | ||
| e1fa1164 RH |
522 | ### SVE Predicate Logical Operations Group |
| 523 | ||
| 516e246a RH |
524 | # SVE predicate logical operations |
| 525 | AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
| 526 | BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
| 527 | EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s | |
| 528 | SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s | |
| 529 | ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
| 530 | ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
| 531 | NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s | |
| 532 | NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s | |
| 533 | ||
| 9e18d7a6 RH |
534 | ### SVE Predicate Misc Group |
| 535 | ||
| 536 | # SVE predicate test | |
| 537 | PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000 | |
| 538 | ||
| 028e2a7b RH |
539 | # SVE predicate initialize |
| 540 | PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4 | |
| 541 | ||
| 542 | # SVE initialize FFR | |
| 543 | SETFFR 00100101 0010 1100 1001 0000 0000 0000 | |
| 544 | ||
| 545 | # SVE zero predicate register | |
| 546 | PFALSE 00100101 0001 1000 1110 0100 0000 rd:4 | |
| 547 | ||
| 548 | # SVE predicate read from FFR (predicated) | |
| 549 | RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4 | |
| 550 | ||
| 551 | # SVE predicate read from FFR (unpredicated) | |
| 552 | RDFFR 00100101 0001 1001 1111 0000 0000 rd:4 | |
| 553 | ||
| 554 | # SVE FFR write from predicate (WRFFR) | |
| 555 | WRFFR 00100101 0010 1000 1001 000 rn:4 00000 | |
| 556 | ||
| 557 | # SVE predicate first active | |
| 558 | PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0 | |
| 559 | ||
| 560 | # SVE predicate next active | |
| 561 | PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn | |
| 562 | ||
| d1822297 RH |
563 | ### SVE Memory - 32-bit Gather and Unsized Contiguous Group |
| 564 | ||
| 565 | # SVE load predicate register | |
| 566 | LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9 | |
| 567 | ||
| 568 | # SVE load vector register | |
| 569 | LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9 |