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38388f7e RH |
1 | # AArch64 SVE instruction descriptions |
2 | # | |
3 | # Copyright (c) 2017 Linaro, Ltd | |
4 | # | |
5 | # This library is free software; you can redistribute it and/or | |
6 | # modify it under the terms of the GNU Lesser General Public | |
7 | # License as published by the Free Software Foundation; either | |
50f57e09 | 8 | # version 2.1 of the License, or (at your option) any later version. |
38388f7e RH |
9 | # |
10 | # This library is distributed in the hope that it will be useful, | |
11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | # Lesser General Public License for more details. | |
14 | # | |
15 | # You should have received a copy of the GNU Lesser General Public | |
16 | # License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
17 | ||
18 | # | |
19 | # This file is processed by scripts/decodetree.py | |
20 | # | |
21 | ||
d1822297 RH |
22 | ########################################################################### |
23 | # Named fields. These are primarily for disjoint fields. | |
24 | ||
f25a2361 | 25 | %imm4_16_p1 16:4 !function=plus1 |
ccd841c3 | 26 | %imm6_22_5 22:1 5:5 |
30562ab7 | 27 | %imm7_22_16 22:2 16:5 |
b94f8f60 | 28 | %imm8_16_10 16:5 10:3 |
d1822297 | 29 | %imm9_16_10 16:s6 10:3 |
1a039c7e | 30 | %size_23 23:2 |
68459864 | 31 | %dtype_23_13 23:2 13:2 |
ca40a6e6 | 32 | %index3_22_19 22:1 19:2 |
c5c455d7 RH |
33 | %index3_19_11 19:2 11:1 |
34 | %index2_20_11 20:1 11:1 | |
d1822297 | 35 | |
ccd841c3 RH |
36 | # A combination of tsz:imm3 -- extract esize. |
37 | %tszimm_esz 22:2 5:5 !function=tszimm_esz | |
38 | # A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3) | |
39 | %tszimm_shr 22:2 5:5 !function=tszimm_shr | |
40 | # A combination of tsz:imm3 -- extract (tsz:imm3) - esize | |
41 | %tszimm_shl 22:2 5:5 !function=tszimm_shl | |
42 | ||
d9d78dcc RH |
43 | # Similarly for the tszh/tszl pair at 22/16 for zzi |
44 | %tszimm16_esz 22:2 16:5 !function=tszimm_esz | |
45 | %tszimm16_shr 22:2 16:5 !function=tszimm_shr | |
46 | %tszimm16_shl 22:2 16:5 !function=tszimm_shl | |
47 | ||
f25a2361 RH |
48 | # Signed 8-bit immediate, optionally shifted left by 8. |
49 | %sh8_i8s 5:9 !function=expand_imm_sh8s | |
6e6a157d RH |
50 | # Unsigned 8-bit immediate, optionally shifted left by 8. |
51 | %sh8_i8u 5:9 !function=expand_imm_sh8u | |
f25a2361 | 52 | |
c4e7c493 RH |
53 | # Unsigned load of msz into esz=2, represented as a dtype. |
54 | %msz_dtype 23:2 !function=msz_dtype | |
55 | ||
f97cfd59 RH |
56 | # Either a copy of rd (at bit 0), or a different source |
57 | # as propagated via the MOVPRFX instruction. | |
58 | %reg_movprfx 0:5 | |
59 | ||
38388f7e RH |
60 | ########################################################################### |
61 | # Named attribute sets. These are used to make nice(er) names | |
62 | # when creating helpers common to those for the individual | |
63 | # instruction patterns. | |
64 | ||
028e2a7b | 65 | &rr_esz rd rn esz |
d1822297 | 66 | &rri rd rn imm |
e1fa1164 | 67 | &rr_dbm rd rn dbm |
4b242d9c | 68 | &rrri rd rn rm imm |
d9d78dcc | 69 | &rri_esz rd rn imm esz |
e6eba6e5 | 70 | &rrri_esz rd rn rm imm esz |
38388f7e | 71 | &rrr_esz rd rn rm esz |
1c737d9c | 72 | &rrx_esz rd rn rm index esz |
047cec97 | 73 | &rpr_esz rd pg rn esz |
35da316f | 74 | &rpr_s rd pg rn s |
516e246a | 75 | &rprr_s rd pg rn rm s |
f97cfd59 | 76 | &rprr_esz rd pg rn rm esz |
38650638 | 77 | &rrrr_esz rd ra rn rm esz |
0a82d963 | 78 | &rrxr_esz rd rn rm ra index esz |
96a36e4a | 79 | &rprrr_esz rd pg rn rm ra esz |
ccd841c3 | 80 | &rpri_esz rd pg rn imm esz |
24e82e68 RH |
81 | &ptrue rd esz pat s |
82 | &incdec_cnt rd pat esz imm d u | |
83 | &incdec2_cnt rd rn pat esz imm d u | |
9ee3a611 RH |
84 | &incdec_pred rd pg esz d u |
85 | &incdec2_pred rd rn pg esz d u | |
c4e7c493 RH |
86 | &rprr_load rd pg rn rm dtype nreg |
87 | &rpri_load rd pg rn imm dtype nreg | |
1a039c7e RH |
88 | &rprr_store rd pg rn rm msz esz nreg |
89 | &rpri_store rd pg rn imm msz esz nreg | |
673e9fa6 RH |
90 | &rprr_gather_load rd pg rn rm esz msz u ff xs scale |
91 | &rpri_gather_load rd pg rn imm esz msz u ff | |
f6dbf62a | 92 | &rprr_scatter_store rd pg rn rm esz msz xs scale |
408ecde9 | 93 | &rpri_scatter_store rd pg rn imm esz msz |
38388f7e RH |
94 | |
95 | ########################################################################### | |
96 | # Named instruction formats. These are generally used to | |
97 | # reduce the amount of duplication between instruction patterns. | |
98 | ||
028e2a7b RH |
99 | # Two operand with unused vector element size |
100 | @pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0 | |
101 | ||
102 | # Two operand | |
103 | @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz | |
0762cd42 | 104 | @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz |
028e2a7b | 105 | |
35da316f RH |
106 | # Two operand with governing predicate, flags setting |
107 | @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s | |
407e6ce7 | 108 | @pd_pg_pn_s0 ........ . . ...... .. pg:4 . rn:4 . rd:4 &rpr_s s=0 |
35da316f | 109 | |
38388f7e RH |
110 | # Three operand with unused vector element size |
111 | @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 | |
112 | ||
516e246a RH |
113 | # Three predicate operand, with governing predicate, flag setting |
114 | @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s | |
115 | ||
fea98f9c RH |
116 | # Three operand, vector element size |
117 | @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz | |
d731d8cb | 118 | @pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz |
30562ab7 RH |
119 | @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \ |
120 | &rrr_esz rn=%reg_movprfx | |
3cc7a88e RH |
121 | @rdn_rm_e0 ........ .. ...... ...... rm:5 rd:5 \ |
122 | &rrr_esz rn=%reg_movprfx esz=0 | |
6e6a157d RH |
123 | @rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \ |
124 | &rri_esz rn=%reg_movprfx imm=%sh8_i8u | |
125 | @rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \ | |
126 | &rri_esz rn=%reg_movprfx | |
127 | @rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \ | |
128 | &rri_esz rn=%reg_movprfx | |
fea98f9c | 129 | |
38650638 RH |
130 | # Four operand, vector element size |
131 | @rda_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 \ | |
132 | &rrrr_esz ra=%reg_movprfx | |
133 | ||
911cdc6d RH |
134 | # Four operand with unused vector element size |
135 | @rdn_ra_rm_e0 ........ ... rm:5 ... ... ra:5 rd:5 \ | |
136 | &rrrr_esz esz=0 rn=%reg_movprfx | |
137 | ||
4b242d9c RH |
138 | # Three operand with "memory" size, aka immediate left shift |
139 | @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri | |
140 | ||
f97cfd59 RH |
141 | # Two register operand, with governing predicate, vector element size |
142 | @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \ | |
143 | &rprr_esz rn=%reg_movprfx | |
144 | @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ | |
145 | &rprr_esz rm=%reg_movprfx | |
d3fe4a29 | 146 | @rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz |
757f9cff | 147 | @pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz |
f97cfd59 | 148 | |
96a36e4a RH |
149 | # Three register operand, with governing predicate, vector element size |
150 | @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ | |
151 | &rprrr_esz ra=%reg_movprfx | |
152 | @rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \ | |
153 | &rprrr_esz rn=%reg_movprfx | |
6ceabaad RH |
154 | @rdn_pg_rm_ra ........ esz:2 . ra:5 ... pg:3 rm:5 rd:5 \ |
155 | &rprrr_esz rn=%reg_movprfx | |
7d47ac94 | 156 | @rd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 &rprr_esz |
96a36e4a | 157 | |
047cec97 RH |
158 | # One register operand, with governing predicate, vector element size |
159 | @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz | |
9ee3a611 | 160 | @rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz |
4d2e2a03 | 161 | @pd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 . rd:4 &rpr_esz |
047cec97 | 162 | |
8092c6a3 RH |
163 | # One register operand, with governing predicate, no vector element size |
164 | @rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0 | |
165 | ||
96f922cc RH |
166 | # Two register operands with a 6-bit signed immediate. |
167 | @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri | |
168 | ||
ccd841c3 | 169 | # Two register operand, one immediate operand, with predicate, |
830d1a5a RH |
170 | # element size encoded as TSZHL. |
171 | @rdn_pg_tszimm_shl ........ .. ... ... ... pg:3 ..... rd:5 \ | |
172 | &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shl | |
173 | @rdn_pg_tszimm_shr ........ .. ... ... ... pg:3 ..... rd:5 \ | |
174 | &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shr | |
ccd841c3 | 175 | |
d9d78dcc | 176 | # Similarly without predicate. |
830d1a5a RH |
177 | @rd_rn_tszimm_shl ........ .. ... ... ...... rn:5 rd:5 \ |
178 | &rri_esz esz=%tszimm16_esz imm=%tszimm16_shl | |
179 | @rd_rn_tszimm_shr ........ .. ... ... ...... rn:5 rd:5 \ | |
180 | &rri_esz esz=%tszimm16_esz imm=%tszimm16_shr | |
d9d78dcc | 181 | |
f25a2361 RH |
182 | # Two register operand, one immediate operand, with 4-bit predicate. |
183 | # User must fill in imm. | |
184 | @rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \ | |
185 | &rpri_esz rn=%reg_movprfx | |
186 | ||
cc48affe RH |
187 | # Two register operand, one one-bit floating-point operand. |
188 | @rdn_i1 ........ esz:2 ......... pg:3 .... imm:1 rd:5 \ | |
189 | &rpri_esz rn=%reg_movprfx | |
190 | ||
e1fa1164 RH |
191 | # Two register operand, one encoded bitmask. |
192 | @rdn_dbm ........ .. .... dbm:13 rd:5 \ | |
193 | &rr_dbm rn=%reg_movprfx | |
194 | ||
38cadeba RH |
195 | # Predicate output, vector and immediate input, |
196 | # controlling predicate, element size. | |
197 | @pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz | |
198 | @pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz | |
199 | ||
d1822297 RH |
200 | # Basic Load/Store with 9-bit immediate offset |
201 | @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ | |
202 | &rri imm=%imm9_16_10 | |
203 | @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \ | |
204 | &rri imm=%imm9_16_10 | |
205 | ||
24e82e68 RH |
206 | # One register, pattern, and uint4+1. |
207 | # User must fill in U and D. | |
208 | @incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ | |
209 | &incdec_cnt imm=%imm4_16_p1 | |
210 | @incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ | |
211 | &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx | |
212 | ||
9ee3a611 RH |
213 | # One register, predicate. |
214 | # User must fill in U and D. | |
215 | @incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred | |
216 | @incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \ | |
217 | &incdec2_pred rn=%reg_movprfx | |
218 | ||
c4e7c493 RH |
219 | # Loads; user must fill in NREG. |
220 | @rprr_load_dt ....... dtype:4 rm:5 ... pg:3 rn:5 rd:5 &rprr_load | |
221 | @rpri_load_dt ....... dtype:4 . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load | |
222 | ||
223 | @rprr_load_msz ....... .... rm:5 ... pg:3 rn:5 rd:5 \ | |
224 | &rprr_load dtype=%msz_dtype | |
225 | @rpri_load_msz ....... .... . imm:s4 ... pg:3 rn:5 rd:5 \ | |
226 | &rpri_load dtype=%msz_dtype | |
227 | ||
673e9fa6 RH |
228 | # Gather Loads. |
229 | @rprr_g_load_u ....... .. . . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ | |
230 | &rprr_gather_load xs=2 | |
231 | @rprr_g_load_xs_u ....... .. xs:1 . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ | |
232 | &rprr_gather_load | |
233 | @rprr_g_load_xs_u_sc ....... .. xs:1 scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ | |
234 | &rprr_gather_load | |
235 | @rprr_g_load_xs_sc ....... .. xs:1 scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \ | |
236 | &rprr_gather_load | |
237 | @rprr_g_load_u_sc ....... .. . scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ | |
238 | &rprr_gather_load xs=2 | |
239 | @rprr_g_load_sc ....... .. . scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \ | |
240 | &rprr_gather_load xs=2 | |
241 | @rpri_g_load ....... msz:2 .. imm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ | |
242 | &rpri_gather_load | |
243 | ||
1a039c7e RH |
244 | # Stores; user must fill in ESZ, MSZ, NREG as needed. |
245 | @rprr_store ....... .. .. rm:5 ... pg:3 rn:5 rd:5 &rprr_store | |
246 | @rpri_store_msz ....... msz:2 .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store | |
247 | @rprr_store_esz_n0 ....... .. esz:2 rm:5 ... pg:3 rn:5 rd:5 \ | |
248 | &rprr_store nreg=0 | |
f6dbf62a RH |
249 | @rprr_scatter_store ....... msz:2 .. rm:5 ... pg:3 rn:5 rd:5 \ |
250 | &rprr_scatter_store | |
408ecde9 RH |
251 | @rpri_scatter_store ....... msz:2 .. imm:5 ... pg:3 rn:5 rd:5 \ |
252 | &rpri_scatter_store | |
1a039c7e | 253 | |
1c737d9c RH |
254 | # Two registers and a scalar by N-bit index |
255 | @rrx_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \ | |
256 | &rrx_esz index=%index3_22_19 | |
257 | @rrx_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 &rrx_esz | |
258 | @rrx_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 &rrx_esz | |
259 | ||
b95f5eeb RH |
260 | # Two registers and a scalar by N-bit index, alternate |
261 | @rrx_3a ........ .. . .. rm:3 ...... rn:5 rd:5 \ | |
262 | &rrx_esz index=%index3_19_11 | |
263 | @rrx_2a ........ .. . . rm:4 ...... rn:5 rd:5 \ | |
264 | &rrx_esz index=%index2_20_11 | |
265 | ||
0a82d963 RH |
266 | # Three registers and a scalar by N-bit index |
267 | @rrxr_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \ | |
268 | &rrxr_esz ra=%reg_movprfx index=%index3_22_19 | |
269 | @rrxr_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 \ | |
270 | &rrxr_esz ra=%reg_movprfx | |
271 | @rrxr_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 \ | |
272 | &rrxr_esz ra=%reg_movprfx | |
273 | ||
c5c455d7 RH |
274 | # Three registers and a scalar by N-bit index, alternate |
275 | @rrxr_3a ........ .. ... rm:3 ...... rn:5 rd:5 \ | |
276 | &rrxr_esz ra=%reg_movprfx index=%index3_19_11 | |
277 | @rrxr_2a ........ .. .. rm:4 ...... rn:5 rd:5 \ | |
278 | &rrxr_esz ra=%reg_movprfx index=%index2_20_11 | |
279 | ||
38388f7e RH |
280 | ########################################################################### |
281 | # Instruction patterns. Grouped according to the SVE encodingindex.xhtml. | |
282 | ||
f97cfd59 RH |
283 | ### SVE Integer Arithmetic - Binary Predicated Group |
284 | ||
285 | # SVE bitwise logical vector operations (predicated) | |
286 | ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm | |
287 | EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm | |
288 | AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm | |
289 | BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm | |
290 | ||
291 | # SVE integer add/subtract vectors (predicated) | |
292 | ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm | |
293 | SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm | |
294 | SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR | |
295 | ||
296 | # SVE integer min/max/difference (predicated) | |
297 | SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm | |
298 | UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm | |
299 | SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm | |
300 | UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm | |
301 | SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm | |
302 | UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm | |
303 | ||
304 | # SVE integer multiply/divide (predicated) | |
305 | MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm | |
306 | SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm | |
307 | UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm | |
308 | # Note that divide requires size >= 2; below 2 is unallocated. | |
309 | SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm | |
310 | UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm | |
311 | SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR | |
312 | UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR | |
313 | ||
047cec97 RH |
314 | ### SVE Integer Reduction Group |
315 | ||
316 | # SVE bitwise logical reduction (predicated) | |
317 | ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn | |
318 | EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn | |
319 | ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn | |
320 | ||
a2103582 RH |
321 | # SVE constructive prefix (predicated) |
322 | MOVPRFX_z 00000100 .. 010 000 001 ... ..... ..... @rd_pg_rn | |
323 | MOVPRFX_m 00000100 .. 010 001 001 ... ..... ..... @rd_pg_rn | |
324 | ||
047cec97 RH |
325 | # SVE integer add reduction (predicated) |
326 | # Note that saddv requires size != 3. | |
327 | UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn | |
328 | SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn | |
329 | ||
330 | # SVE integer min/max reduction (predicated) | |
331 | SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn | |
332 | UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn | |
333 | SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn | |
334 | UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn | |
335 | ||
ccd841c3 RH |
336 | ### SVE Shift by Immediate - Predicated Group |
337 | ||
338 | # SVE bitwise shift by immediate (predicated) | |
830d1a5a RH |
339 | ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... @rdn_pg_tszimm_shr |
340 | LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... @rdn_pg_tszimm_shr | |
341 | LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... @rdn_pg_tszimm_shl | |
342 | ASRD 00000100 .. 000 100 100 ... .. ... ..... @rdn_pg_tszimm_shr | |
ccd841c3 | 343 | |
27721dbb RH |
344 | # SVE bitwise shift by vector (predicated) |
345 | ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm | |
346 | LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm | |
347 | LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm | |
348 | ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR | |
349 | LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR | |
350 | LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR | |
351 | ||
fe7f8dfb RH |
352 | # SVE bitwise shift by wide elements (predicated) |
353 | # Note these require size != 3. | |
354 | ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm | |
355 | LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm | |
356 | LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm | |
357 | ||
afac6d04 RH |
358 | ### SVE Integer Arithmetic - Unary Predicated Group |
359 | ||
360 | # SVE unary bit operations (predicated) | |
361 | # Note esz != 0 for FABS and FNEG. | |
362 | CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn | |
363 | CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn | |
364 | CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn | |
365 | CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn | |
366 | NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn | |
367 | FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn | |
368 | FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn | |
369 | ||
370 | # SVE integer unary operations (predicated) | |
371 | # Note esz > original size for extensions. | |
372 | ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn | |
373 | NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn | |
374 | SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn | |
375 | UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn | |
376 | SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn | |
377 | UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn | |
378 | SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn | |
379 | UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn | |
380 | ||
abfdefd5 RH |
381 | ### SVE Floating Point Compare - Vectors Group |
382 | ||
383 | # SVE floating-point compare vectors | |
384 | FCMGE_ppzz 01100101 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm | |
385 | FCMGT_ppzz 01100101 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm | |
386 | FCMEQ_ppzz 01100101 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm | |
387 | FCMNE_ppzz 01100101 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm | |
388 | FCMUO_ppzz 01100101 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm | |
389 | FACGE_ppzz 01100101 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm | |
390 | FACGT_ppzz 01100101 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm | |
391 | ||
96a36e4a RH |
392 | ### SVE Integer Multiply-Add Group |
393 | ||
394 | # SVE integer multiply-add writing addend (predicated) | |
395 | MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm | |
396 | MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm | |
397 | ||
398 | # SVE integer multiply-add writing multiplicand (predicated) | |
399 | MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD | |
400 | MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB | |
401 | ||
fea98f9c RH |
402 | ### SVE Integer Arithmetic - Unpredicated Group |
403 | ||
404 | # SVE integer add/subtract vectors (unpredicated) | |
405 | ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm | |
406 | SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm | |
407 | SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm | |
408 | UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm | |
409 | SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm | |
410 | UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm | |
411 | ||
38388f7e RH |
412 | ### SVE Logical - Unpredicated Group |
413 | ||
414 | # SVE bitwise logical operations (unpredicated) | |
415 | AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
416 | ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
417 | EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
418 | BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
d1822297 | 419 | |
e6eba6e5 RH |
420 | XAR 00000100 .. 1 ..... 001 101 rm:5 rd:5 &rrri_esz \ |
421 | rn=%reg_movprfx esz=%tszimm16_esz imm=%tszimm16_shr | |
422 | ||
911cdc6d RH |
423 | # SVE2 bitwise ternary operations |
424 | EOR3 00000100 00 1 ..... 001 110 ..... ..... @rdn_ra_rm_e0 | |
425 | BSL 00000100 00 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0 | |
426 | BCAX 00000100 01 1 ..... 001 110 ..... ..... @rdn_ra_rm_e0 | |
427 | BSL1N 00000100 01 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0 | |
428 | BSL2N 00000100 10 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0 | |
429 | NBSL 00000100 11 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0 | |
430 | ||
9a56c9c3 RH |
431 | ### SVE Index Generation Group |
432 | ||
433 | # SVE index generation (immediate start, immediate increment) | |
434 | INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5 | |
435 | ||
436 | # SVE index generation (immediate start, register increment) | |
437 | INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5 | |
438 | ||
439 | # SVE index generation (register start, immediate increment) | |
440 | INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 | |
441 | ||
442 | # SVE index generation (register start, register increment) | |
443 | INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm | |
444 | ||
96f922cc RH |
445 | ### SVE Stack Allocation Group |
446 | ||
447 | # SVE stack frame adjustment | |
448 | ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 | |
449 | ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 | |
450 | ||
451 | # SVE stack frame size | |
452 | RDVL 00000100 101 11111 01010 imm:s6 rd:5 | |
453 | ||
d9d78dcc RH |
454 | ### SVE Bitwise Shift - Unpredicated Group |
455 | ||
456 | # SVE bitwise shift by immediate (unpredicated) | |
830d1a5a RH |
457 | ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... @rd_rn_tszimm_shr |
458 | LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... @rd_rn_tszimm_shr | |
459 | LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... @rd_rn_tszimm_shl | |
d9d78dcc RH |
460 | |
461 | # SVE bitwise shift by wide elements (unpredicated) | |
462 | # Note esz != 3 | |
463 | ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm | |
464 | LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm | |
465 | LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm | |
466 | ||
4b242d9c RH |
467 | ### SVE Compute Vector Address Group |
468 | ||
469 | # SVE vector address generation | |
470 | ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
471 | ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
472 | ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
473 | ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
474 | ||
0762cd42 RH |
475 | ### SVE Integer Misc - Unpredicated Group |
476 | ||
a2103582 RH |
477 | # SVE constructive prefix (unpredicated) |
478 | MOVPRFX 00000100 00 1 00000 101111 rn:5 rd:5 | |
479 | ||
0762cd42 RH |
480 | # SVE floating-point exponential accelerator |
481 | # Note esz != 0 | |
482 | FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn | |
483 | ||
a1f233f2 RH |
484 | # SVE floating-point trig select coefficient |
485 | # Note esz != 0 | |
486 | FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm | |
487 | ||
24e82e68 RH |
488 | ### SVE Element Count Group |
489 | ||
490 | # SVE element count | |
491 | CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1 | |
492 | ||
493 | # SVE inc/dec register by element count | |
494 | INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1 | |
495 | ||
496 | # SVE saturating inc/dec register by element count | |
497 | SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt | |
498 | SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt | |
499 | ||
500 | # SVE inc/dec vector by element count | |
501 | # Note this requires esz != 0. | |
502 | INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1 | |
503 | ||
504 | # SVE saturating inc/dec vector by element count | |
505 | # Note these require esz != 0. | |
506 | SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt | |
516e246a | 507 | |
e1fa1164 RH |
508 | ### SVE Bitwise Immediate Group |
509 | ||
510 | # SVE bitwise logical with immediate (unpredicated) | |
511 | ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm | |
512 | EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm | |
513 | AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm | |
514 | ||
515 | # SVE broadcast bitmask immediate | |
516 | DUPM 00000101 11 0000 dbm:13 rd:5 | |
517 | ||
f25a2361 RH |
518 | ### SVE Integer Wide Immediate - Predicated Group |
519 | ||
520 | # SVE copy floating-point immediate (predicated) | |
521 | FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4 | |
522 | ||
523 | # SVE copy integer immediate (predicated) | |
524 | CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s | |
525 | CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s | |
526 | ||
b94f8f60 RH |
527 | ### SVE Permute - Extract Group |
528 | ||
75114792 | 529 | # SVE extract vector (destructive) |
b94f8f60 RH |
530 | EXT 00000101 001 ..... 000 ... rm:5 rd:5 \ |
531 | &rrri rn=%reg_movprfx imm=%imm8_16_10 | |
532 | ||
75114792 SL |
533 | # SVE2 extract vector (constructive) |
534 | EXT_sve2 00000101 011 ..... 000 ... rn:5 rd:5 \ | |
535 | &rri imm=%imm8_16_10 | |
536 | ||
30562ab7 RH |
537 | ### SVE Permute - Unpredicated Group |
538 | ||
539 | # SVE broadcast general register | |
540 | DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn | |
541 | ||
542 | # SVE broadcast indexed element | |
543 | DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \ | |
544 | &rri imm=%imm7_22_16 | |
545 | ||
546 | # SVE insert SIMD&FP scalar register | |
547 | INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm | |
548 | ||
549 | # SVE insert general register | |
550 | INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm | |
551 | ||
552 | # SVE reverse vector elements | |
553 | REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn | |
554 | ||
555 | # SVE vector table lookup | |
556 | TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm | |
557 | ||
558 | # SVE unpack vector elements | |
559 | UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5 | |
560 | ||
80a712a2 SL |
561 | # SVE2 Table Lookup (three sources) |
562 | ||
563 | TBL_sve2 00000101 .. 1 ..... 001010 ..... ..... @rd_rn_rm | |
564 | TBX 00000101 .. 1 ..... 001011 ..... ..... @rd_rn_rm | |
565 | ||
d731d8cb RH |
566 | ### SVE Permute - Predicates Group |
567 | ||
568 | # SVE permute predicate elements | |
569 | ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm | |
570 | ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm | |
571 | UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm | |
572 | UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm | |
573 | TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm | |
574 | TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm | |
575 | ||
576 | # SVE reverse predicate elements | |
577 | REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn | |
578 | ||
579 | # SVE unpack predicate elements | |
580 | PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0 | |
581 | PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0 | |
582 | ||
234b48e9 RH |
583 | ### SVE Permute - Interleaving Group |
584 | ||
585 | # SVE permute vector elements | |
586 | ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm | |
587 | ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm | |
588 | UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm | |
589 | UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm | |
590 | TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm | |
591 | TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm | |
592 | ||
3ca879ae RH |
593 | ### SVE Permute - Predicated Group |
594 | ||
595 | # SVE compress active elements | |
596 | # Note esz >= 2 | |
597 | COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn | |
598 | ||
ef23cb72 RH |
599 | # SVE conditionally broadcast element to vector |
600 | CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm | |
601 | CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm | |
602 | ||
603 | # SVE conditionally copy element to SIMD&FP scalar | |
604 | CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn | |
605 | CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn | |
606 | ||
607 | # SVE conditionally copy element to general register | |
608 | CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn | |
609 | CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn | |
610 | ||
611 | # SVE copy element to SIMD&FP scalar register | |
612 | LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn | |
613 | LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn | |
614 | ||
615 | # SVE copy element to general register | |
616 | LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn | |
617 | LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn | |
618 | ||
792a5578 RH |
619 | # SVE copy element from SIMD&FP scalar register |
620 | CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn | |
621 | ||
622 | # SVE copy element from general register to vector (predicated) | |
623 | CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn | |
624 | ||
dae8fb90 RH |
625 | # SVE reverse within elements |
626 | # Note esz >= operation size | |
627 | REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn | |
628 | REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn | |
629 | REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn | |
630 | RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn | |
631 | ||
75114792 | 632 | # SVE vector splice (predicated, destructive) |
b48ff240 RH |
633 | SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm |
634 | ||
75114792 SL |
635 | # SVE2 vector splice (predicated, constructive) |
636 | SPLICE_sve2 00000101 .. 101 101 100 ... ..... ..... @rd_pg_rn | |
637 | ||
d3fe4a29 RH |
638 | ### SVE Select Vectors Group |
639 | ||
640 | # SVE select vector elements (predicated) | |
641 | SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm | |
642 | ||
757f9cff RH |
643 | ### SVE Integer Compare - Vectors Group |
644 | ||
645 | # SVE integer compare_vectors | |
646 | CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm | |
647 | CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm | |
648 | CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm | |
649 | CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm | |
650 | CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm | |
651 | CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm | |
652 | ||
653 | # SVE integer compare with wide elements | |
654 | # Note these require esz != 3. | |
655 | CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm | |
656 | CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm | |
657 | CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm | |
658 | CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm | |
659 | CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm | |
660 | CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm | |
661 | CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm | |
662 | CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm | |
663 | CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm | |
664 | CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm | |
665 | ||
38cadeba RH |
666 | ### SVE Integer Compare - Unsigned Immediate Group |
667 | ||
668 | # SVE integer compare with unsigned immediate | |
669 | CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7 | |
670 | CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7 | |
671 | CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7 | |
672 | CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7 | |
673 | ||
674 | ### SVE Integer Compare - Signed Immediate Group | |
675 | ||
676 | # SVE integer compare with signed immediate | |
677 | CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5 | |
678 | CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5 | |
679 | CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5 | |
680 | CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5 | |
681 | CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5 | |
682 | CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5 | |
683 | ||
e1fa1164 RH |
684 | ### SVE Predicate Logical Operations Group |
685 | ||
516e246a RH |
686 | # SVE predicate logical operations |
687 | AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
688 | BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
689 | EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s | |
690 | SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s | |
691 | ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
692 | ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
693 | NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s | |
694 | NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s | |
695 | ||
9e18d7a6 RH |
696 | ### SVE Predicate Misc Group |
697 | ||
698 | # SVE predicate test | |
699 | PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000 | |
700 | ||
028e2a7b RH |
701 | # SVE predicate initialize |
702 | PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4 | |
703 | ||
704 | # SVE initialize FFR | |
705 | SETFFR 00100101 0010 1100 1001 0000 0000 0000 | |
706 | ||
707 | # SVE zero predicate register | |
708 | PFALSE 00100101 0001 1000 1110 0100 0000 rd:4 | |
709 | ||
710 | # SVE predicate read from FFR (predicated) | |
711 | RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4 | |
712 | ||
713 | # SVE predicate read from FFR (unpredicated) | |
714 | RDFFR 00100101 0001 1001 1111 0000 0000 rd:4 | |
715 | ||
716 | # SVE FFR write from predicate (WRFFR) | |
717 | WRFFR 00100101 0010 1000 1001 000 rn:4 00000 | |
718 | ||
719 | # SVE predicate first active | |
720 | PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0 | |
721 | ||
722 | # SVE predicate next active | |
723 | PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn | |
724 | ||
35da316f RH |
725 | ### SVE Partition Break Group |
726 | ||
727 | # SVE propagate break from previous partition | |
728 | BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
729 | BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
730 | ||
731 | # SVE partition break condition | |
732 | BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s | |
733 | BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s | |
407e6ce7 RH |
734 | BRKA_m 00100101 00 01000001 .... 0 .... 1 .... @pd_pg_pn_s0 |
735 | BRKB_m 00100101 10 01000001 .... 0 .... 1 .... @pd_pg_pn_s0 | |
35da316f RH |
736 | |
737 | # SVE propagate break to next partition | |
738 | BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s | |
739 | ||
9ee3a611 RH |
740 | ### SVE Predicate Count Group |
741 | ||
742 | # SVE predicate count | |
743 | CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn | |
744 | ||
745 | # SVE inc/dec register by predicate count | |
746 | INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1 | |
747 | ||
748 | # SVE inc/dec vector by predicate count | |
749 | INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1 | |
750 | ||
751 | # SVE saturating inc/dec register by predicate count | |
752 | SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred | |
753 | SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred | |
754 | ||
755 | # SVE saturating inc/dec vector by predicate count | |
756 | SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred | |
757 | ||
caf1cefc RH |
758 | ### SVE Integer Compare - Scalars Group |
759 | ||
760 | # SVE conditionally terminate scalars | |
761 | CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000 | |
762 | ||
763 | # SVE integer compare scalar count and limit | |
34688dbc | 764 | WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 lt:1 rn:5 eq:1 rd:4 |
caf1cefc | 765 | |
14f6dad1 RH |
766 | # SVE2 pointer conflict compare |
767 | WHILE_ptr 00100101 esz:2 1 rm:5 001 100 rn:5 rw:1 rd:4 | |
768 | ||
ed491961 RH |
769 | ### SVE Integer Wide Immediate - Unpredicated Group |
770 | ||
771 | # SVE broadcast floating-point immediate (unpredicated) | |
772 | FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5 | |
773 | ||
774 | # SVE broadcast integer immediate (unpredicated) | |
775 | DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s | |
776 | ||
6e6a157d RH |
777 | # SVE integer add/subtract immediate (unpredicated) |
778 | ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u | |
779 | SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u | |
780 | SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u | |
781 | SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u | |
782 | UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u | |
783 | SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u | |
784 | UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u | |
785 | ||
786 | # SVE integer min/max immediate (unpredicated) | |
787 | SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s | |
788 | UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u | |
789 | SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s | |
790 | UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u | |
791 | ||
792 | # SVE integer multiply immediate (unpredicated) | |
793 | MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s | |
794 | ||
d730ecaa | 795 | # SVE integer dot product (unpredicated) |
bc2bd697 RH |
796 | DOT_zzzz 01000100 1 sz:1 0 rm:5 00000 u:1 rn:5 rd:5 \ |
797 | ra=%reg_movprfx | |
d730ecaa | 798 | |
21068f39 RH |
799 | # SVE2 complex dot product (vectors) |
800 | CDOT_zzzz 01000100 esz:2 0 rm:5 0001 rot:2 rn:5 rd:5 ra=%reg_movprfx | |
801 | ||
814d4c52 RH |
802 | #### SVE Multiply - Indexed |
803 | ||
16fcfdc7 | 804 | # SVE integer dot product (indexed) |
0a82d963 RH |
805 | SDOT_zzxw_s 01000100 10 1 ..... 000000 ..... ..... @rrxr_2 esz=2 |
806 | SDOT_zzxw_d 01000100 11 1 ..... 000000 ..... ..... @rrxr_1 esz=3 | |
807 | UDOT_zzxw_s 01000100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2 | |
808 | UDOT_zzxw_d 01000100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3 | |
16fcfdc7 | 809 | |
8a02aac7 RH |
810 | # SVE2 integer multiply-add (indexed) |
811 | MLA_zzxz_h 01000100 0. 1 ..... 000010 ..... ..... @rrxr_3 esz=1 | |
812 | MLA_zzxz_s 01000100 10 1 ..... 000010 ..... ..... @rrxr_2 esz=2 | |
813 | MLA_zzxz_d 01000100 11 1 ..... 000010 ..... ..... @rrxr_1 esz=3 | |
814 | MLS_zzxz_h 01000100 0. 1 ..... 000011 ..... ..... @rrxr_3 esz=1 | |
815 | MLS_zzxz_s 01000100 10 1 ..... 000011 ..... ..... @rrxr_2 esz=2 | |
816 | MLS_zzxz_d 01000100 11 1 ..... 000011 ..... ..... @rrxr_1 esz=3 | |
817 | ||
75d6d5fc RH |
818 | # SVE2 saturating multiply-add high (indexed) |
819 | SQRDMLAH_zzxz_h 01000100 0. 1 ..... 000100 ..... ..... @rrxr_3 esz=1 | |
820 | SQRDMLAH_zzxz_s 01000100 10 1 ..... 000100 ..... ..... @rrxr_2 esz=2 | |
821 | SQRDMLAH_zzxz_d 01000100 11 1 ..... 000100 ..... ..... @rrxr_1 esz=3 | |
822 | SQRDMLSH_zzxz_h 01000100 0. 1 ..... 000101 ..... ..... @rrxr_3 esz=1 | |
823 | SQRDMLSH_zzxz_s 01000100 10 1 ..... 000101 ..... ..... @rrxr_2 esz=2 | |
824 | SQRDMLSH_zzxz_d 01000100 11 1 ..... 000101 ..... ..... @rrxr_1 esz=3 | |
825 | ||
2867039a RH |
826 | # SVE mixed sign dot product (indexed) |
827 | USDOT_zzxw_s 01000100 10 1 ..... 000110 ..... ..... @rrxr_2 esz=2 | |
828 | SUDOT_zzxw_s 01000100 10 1 ..... 000111 ..... ..... @rrxr_2 esz=2 | |
829 | ||
c5c455d7 RH |
830 | # SVE2 saturating multiply-add (indexed) |
831 | SQDMLALB_zzxw_s 01000100 10 1 ..... 0010.0 ..... ..... @rrxr_3a esz=2 | |
832 | SQDMLALB_zzxw_d 01000100 11 1 ..... 0010.0 ..... ..... @rrxr_2a esz=3 | |
833 | SQDMLALT_zzxw_s 01000100 10 1 ..... 0010.1 ..... ..... @rrxr_3a esz=2 | |
834 | SQDMLALT_zzxw_d 01000100 11 1 ..... 0010.1 ..... ..... @rrxr_2a esz=3 | |
835 | SQDMLSLB_zzxw_s 01000100 10 1 ..... 0011.0 ..... ..... @rrxr_3a esz=2 | |
836 | SQDMLSLB_zzxw_d 01000100 11 1 ..... 0011.0 ..... ..... @rrxr_2a esz=3 | |
837 | SQDMLSLT_zzxw_s 01000100 10 1 ..... 0011.1 ..... ..... @rrxr_3a esz=2 | |
838 | SQDMLSLT_zzxw_d 01000100 11 1 ..... 0011.1 ..... ..... @rrxr_2a esz=3 | |
839 | ||
21068f39 RH |
840 | # SVE2 complex integer dot product (indexed) |
841 | CDOT_zzxw_s 01000100 10 1 index:2 rm:3 0100 rot:2 rn:5 rd:5 \ | |
842 | ra=%reg_movprfx | |
843 | CDOT_zzxw_d 01000100 11 1 index:1 rm:4 0100 rot:2 rn:5 rd:5 \ | |
844 | ra=%reg_movprfx | |
845 | ||
3b787ed8 RH |
846 | # SVE2 complex integer multiply-add (indexed) |
847 | CMLA_zzxz_h 01000100 10 1 index:2 rm:3 0110 rot:2 rn:5 rd:5 \ | |
848 | ra=%reg_movprfx | |
849 | CMLA_zzxz_s 01000100 11 1 index:1 rm:4 0110 rot:2 rn:5 rd:5 \ | |
850 | ra=%reg_movprfx | |
851 | ||
852 | # SVE2 complex saturating integer multiply-add (indexed) | |
853 | SQRDCMLAH_zzxz_h 01000100 10 1 index:2 rm:3 0111 rot:2 rn:5 rd:5 \ | |
854 | ra=%reg_movprfx | |
855 | SQRDCMLAH_zzxz_s 01000100 11 1 index:1 rm:4 0111 rot:2 rn:5 rd:5 \ | |
856 | ra=%reg_movprfx | |
857 | ||
d462469f RH |
858 | # SVE2 multiply-add long (indexed) |
859 | SMLALB_zzxw_s 01000100 10 1 ..... 1000.0 ..... ..... @rrxr_3a esz=2 | |
860 | SMLALB_zzxw_d 01000100 11 1 ..... 1000.0 ..... ..... @rrxr_2a esz=3 | |
861 | SMLALT_zzxw_s 01000100 10 1 ..... 1000.1 ..... ..... @rrxr_3a esz=2 | |
862 | SMLALT_zzxw_d 01000100 11 1 ..... 1000.1 ..... ..... @rrxr_2a esz=3 | |
863 | UMLALB_zzxw_s 01000100 10 1 ..... 1001.0 ..... ..... @rrxr_3a esz=2 | |
864 | UMLALB_zzxw_d 01000100 11 1 ..... 1001.0 ..... ..... @rrxr_2a esz=3 | |
865 | UMLALT_zzxw_s 01000100 10 1 ..... 1001.1 ..... ..... @rrxr_3a esz=2 | |
866 | UMLALT_zzxw_d 01000100 11 1 ..... 1001.1 ..... ..... @rrxr_2a esz=3 | |
867 | SMLSLB_zzxw_s 01000100 10 1 ..... 1010.0 ..... ..... @rrxr_3a esz=2 | |
868 | SMLSLB_zzxw_d 01000100 11 1 ..... 1010.0 ..... ..... @rrxr_2a esz=3 | |
869 | SMLSLT_zzxw_s 01000100 10 1 ..... 1010.1 ..... ..... @rrxr_3a esz=2 | |
870 | SMLSLT_zzxw_d 01000100 11 1 ..... 1010.1 ..... ..... @rrxr_2a esz=3 | |
871 | UMLSLB_zzxw_s 01000100 10 1 ..... 1011.0 ..... ..... @rrxr_3a esz=2 | |
872 | UMLSLB_zzxw_d 01000100 11 1 ..... 1011.0 ..... ..... @rrxr_2a esz=3 | |
873 | UMLSLT_zzxw_s 01000100 10 1 ..... 1011.1 ..... ..... @rrxr_3a esz=2 | |
874 | UMLSLT_zzxw_d 01000100 11 1 ..... 1011.1 ..... ..... @rrxr_2a esz=3 | |
875 | ||
d3949c4c RH |
876 | # SVE2 integer multiply long (indexed) |
877 | SMULLB_zzx_s 01000100 10 1 ..... 1100.0 ..... ..... @rrx_3a esz=2 | |
878 | SMULLB_zzx_d 01000100 11 1 ..... 1100.0 ..... ..... @rrx_2a esz=3 | |
879 | SMULLT_zzx_s 01000100 10 1 ..... 1100.1 ..... ..... @rrx_3a esz=2 | |
880 | SMULLT_zzx_d 01000100 11 1 ..... 1100.1 ..... ..... @rrx_2a esz=3 | |
881 | UMULLB_zzx_s 01000100 10 1 ..... 1101.0 ..... ..... @rrx_3a esz=2 | |
882 | UMULLB_zzx_d 01000100 11 1 ..... 1101.0 ..... ..... @rrx_2a esz=3 | |
883 | UMULLT_zzx_s 01000100 10 1 ..... 1101.1 ..... ..... @rrx_3a esz=2 | |
884 | UMULLT_zzx_d 01000100 11 1 ..... 1101.1 ..... ..... @rrx_2a esz=3 | |
885 | ||
b95f5eeb RH |
886 | # SVE2 saturating multiply (indexed) |
887 | SQDMULLB_zzx_s 01000100 10 1 ..... 1110.0 ..... ..... @rrx_3a esz=2 | |
888 | SQDMULLB_zzx_d 01000100 11 1 ..... 1110.0 ..... ..... @rrx_2a esz=3 | |
889 | SQDMULLT_zzx_s 01000100 10 1 ..... 1110.1 ..... ..... @rrx_3a esz=2 | |
890 | SQDMULLT_zzx_d 01000100 11 1 ..... 1110.1 ..... ..... @rrx_2a esz=3 | |
891 | ||
1aee2d70 RH |
892 | # SVE2 saturating multiply high (indexed) |
893 | SQDMULH_zzx_h 01000100 0. 1 ..... 111100 ..... ..... @rrx_3 esz=1 | |
894 | SQDMULH_zzx_s 01000100 10 1 ..... 111100 ..... ..... @rrx_2 esz=2 | |
895 | SQDMULH_zzx_d 01000100 11 1 ..... 111100 ..... ..... @rrx_1 esz=3 | |
896 | SQRDMULH_zzx_h 01000100 0. 1 ..... 111101 ..... ..... @rrx_3 esz=1 | |
897 | SQRDMULH_zzx_s 01000100 10 1 ..... 111101 ..... ..... @rrx_2 esz=2 | |
898 | SQRDMULH_zzx_d 01000100 11 1 ..... 111101 ..... ..... @rrx_1 esz=3 | |
899 | ||
814d4c52 RH |
900 | # SVE2 integer multiply (indexed) |
901 | MUL_zzx_h 01000100 0. 1 ..... 111110 ..... ..... @rrx_3 esz=1 | |
902 | MUL_zzx_s 01000100 10 1 ..... 111110 ..... ..... @rrx_2 esz=2 | |
903 | MUL_zzx_d 01000100 11 1 ..... 111110 ..... ..... @rrx_1 esz=3 | |
904 | ||
76a9d9cd RH |
905 | # SVE floating-point complex add (predicated) |
906 | FCADD 01100100 esz:2 00000 rot:1 100 pg:3 rm:5 rd:5 \ | |
907 | rn=%reg_movprfx | |
908 | ||
05f48bab RH |
909 | # SVE floating-point complex multiply-add (predicated) |
910 | FCMLA_zpzzz 01100100 esz:2 0 rm:5 0 rot:2 pg:3 rn:5 rd:5 \ | |
911 | ra=%reg_movprfx | |
912 | ||
18fc2405 RH |
913 | # SVE floating-point complex multiply-add (indexed) |
914 | FCMLA_zzxz 01100100 10 1 index:2 rm:3 0001 rot:2 rn:5 rd:5 \ | |
915 | ra=%reg_movprfx esz=1 | |
916 | FCMLA_zzxz 01100100 11 1 index:1 rm:4 0001 rot:2 rn:5 rd:5 \ | |
917 | ra=%reg_movprfx esz=2 | |
918 | ||
ca40a6e6 RH |
919 | ### SVE FP Multiply-Add Indexed Group |
920 | ||
921 | # SVE floating-point multiply-add (indexed) | |
0a82d963 RH |
922 | FMLA_zzxz 01100100 0. 1 ..... 000000 ..... ..... @rrxr_3 esz=1 |
923 | FMLA_zzxz 01100100 10 1 ..... 000000 ..... ..... @rrxr_2 esz=2 | |
924 | FMLA_zzxz 01100100 11 1 ..... 000000 ..... ..... @rrxr_1 esz=3 | |
925 | FMLS_zzxz 01100100 0. 1 ..... 000001 ..... ..... @rrxr_3 esz=1 | |
926 | FMLS_zzxz 01100100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2 | |
927 | FMLS_zzxz 01100100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3 | |
ca40a6e6 RH |
928 | |
929 | ### SVE FP Multiply Indexed Group | |
930 | ||
931 | # SVE floating-point multiply (indexed) | |
1c737d9c RH |
932 | FMUL_zzx 01100100 0. 1 ..... 001000 ..... ..... @rrx_3 esz=1 |
933 | FMUL_zzx 01100100 10 1 ..... 001000 ..... ..... @rrx_2 esz=2 | |
934 | FMUL_zzx 01100100 11 1 ..... 001000 ..... ..... @rrx_1 esz=3 | |
ca40a6e6 | 935 | |
23fbe79f RH |
936 | ### SVE FP Fast Reduction Group |
937 | ||
938 | FADDV 01100101 .. 000 000 001 ... ..... ..... @rd_pg_rn | |
939 | FMAXNMV 01100101 .. 000 100 001 ... ..... ..... @rd_pg_rn | |
940 | FMINNMV 01100101 .. 000 101 001 ... ..... ..... @rd_pg_rn | |
941 | FMAXV 01100101 .. 000 110 001 ... ..... ..... @rd_pg_rn | |
942 | FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn | |
943 | ||
3887c038 RH |
944 | ## SVE Floating Point Unary Operations - Unpredicated Group |
945 | ||
946 | FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn | |
947 | FRSQRTE 01100101 .. 001 111 001100 ..... ..... @rd_rn | |
948 | ||
4d2e2a03 RH |
949 | ### SVE FP Compare with Zero Group |
950 | ||
951 | FCMGE_ppz0 01100101 .. 0100 00 001 ... ..... 0 .... @pd_pg_rn | |
952 | FCMGT_ppz0 01100101 .. 0100 00 001 ... ..... 1 .... @pd_pg_rn | |
953 | FCMLT_ppz0 01100101 .. 0100 01 001 ... ..... 0 .... @pd_pg_rn | |
954 | FCMLE_ppz0 01100101 .. 0100 01 001 ... ..... 1 .... @pd_pg_rn | |
955 | FCMEQ_ppz0 01100101 .. 0100 10 001 ... ..... 0 .... @pd_pg_rn | |
956 | FCMNE_ppz0 01100101 .. 0100 11 001 ... ..... 0 .... @pd_pg_rn | |
957 | ||
7f9ddf64 RH |
958 | ### SVE FP Accumulating Reduction Group |
959 | ||
960 | # SVE floating-point serial reduction (predicated) | |
961 | FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm | |
962 | ||
29b80469 RH |
963 | ### SVE Floating Point Arithmetic - Unpredicated Group |
964 | ||
965 | # SVE floating-point arithmetic (unpredicated) | |
966 | FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm | |
967 | FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm | |
968 | FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm | |
969 | FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm | |
970 | FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm | |
971 | FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm | |
972 | ||
ec3b87c2 RH |
973 | ### SVE FP Arithmetic Predicated Group |
974 | ||
975 | # SVE floating-point arithmetic (predicated) | |
976 | FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm | |
977 | FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm | |
978 | FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm | |
979 | FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR | |
980 | FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm | |
981 | FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm | |
982 | FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm | |
983 | FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm | |
984 | FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm | |
985 | FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm | |
986 | FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm | |
987 | FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR | |
988 | FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm | |
989 | ||
cc48affe RH |
990 | # SVE floating-point arithmetic with immediate (predicated) |
991 | FADD_zpzi 01100101 .. 011 000 100 ... 0000 . ..... @rdn_i1 | |
992 | FSUB_zpzi 01100101 .. 011 001 100 ... 0000 . ..... @rdn_i1 | |
993 | FMUL_zpzi 01100101 .. 011 010 100 ... 0000 . ..... @rdn_i1 | |
994 | FSUBR_zpzi 01100101 .. 011 011 100 ... 0000 . ..... @rdn_i1 | |
995 | FMAXNM_zpzi 01100101 .. 011 100 100 ... 0000 . ..... @rdn_i1 | |
996 | FMINNM_zpzi 01100101 .. 011 101 100 ... 0000 . ..... @rdn_i1 | |
997 | FMAX_zpzi 01100101 .. 011 110 100 ... 0000 . ..... @rdn_i1 | |
998 | FMIN_zpzi 01100101 .. 011 111 100 ... 0000 . ..... @rdn_i1 | |
999 | ||
67fcd9ad RH |
1000 | # SVE floating-point trig multiply-add coefficient |
1001 | FTMAD 01100101 esz:2 010 imm:3 100000 rm:5 rd:5 rn=%reg_movprfx | |
1002 | ||
6ceabaad RH |
1003 | ### SVE FP Multiply-Add Group |
1004 | ||
1005 | # SVE floating-point multiply-accumulate writing addend | |
1006 | FMLA_zpzzz 01100101 .. 1 ..... 000 ... ..... ..... @rda_pg_rn_rm | |
1007 | FMLS_zpzzz 01100101 .. 1 ..... 001 ... ..... ..... @rda_pg_rn_rm | |
1008 | FNMLA_zpzzz 01100101 .. 1 ..... 010 ... ..... ..... @rda_pg_rn_rm | |
1009 | FNMLS_zpzzz 01100101 .. 1 ..... 011 ... ..... ..... @rda_pg_rn_rm | |
1010 | ||
1011 | # SVE floating-point multiply-accumulate writing multiplicand | |
1012 | # Alter the operand extraction order and reuse the helpers from above. | |
1013 | # FMAD, FMSB, FNMAD, FNMS | |
1014 | FMLA_zpzzz 01100101 .. 1 ..... 100 ... ..... ..... @rdn_pg_rm_ra | |
1015 | FMLS_zpzzz 01100101 .. 1 ..... 101 ... ..... ..... @rdn_pg_rm_ra | |
1016 | FNMLA_zpzzz 01100101 .. 1 ..... 110 ... ..... ..... @rdn_pg_rm_ra | |
1017 | FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ..... @rdn_pg_rm_ra | |
1018 | ||
8092c6a3 RH |
1019 | ### SVE FP Unary Operations Predicated Group |
1020 | ||
46d33d1e RH |
1021 | # SVE floating-point convert precision |
1022 | FCVT_sh 01100101 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0 | |
1023 | FCVT_hs 01100101 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0 | |
1024 | FCVT_dh 01100101 11 0010 00 101 ... ..... ..... @rd_pg_rn_e0 | |
1025 | FCVT_hd 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_e0 | |
1026 | FCVT_ds 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0 | |
1027 | FCVT_sd 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0 | |
1028 | ||
df4de1af RH |
1029 | # SVE floating-point convert to integer |
1030 | FCVTZS_hh 01100101 01 011 01 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1031 | FCVTZU_hh 01100101 01 011 01 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1032 | FCVTZS_hs 01100101 01 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1033 | FCVTZU_hs 01100101 01 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1034 | FCVTZS_hd 01100101 01 011 11 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1035 | FCVTZU_hd 01100101 01 011 11 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1036 | FCVTZS_ss 01100101 10 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1037 | FCVTZU_ss 01100101 10 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1038 | FCVTZS_ds 01100101 11 011 00 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1039 | FCVTZU_ds 01100101 11 011 00 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1040 | FCVTZS_sd 01100101 11 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1041 | FCVTZU_sd 01100101 11 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1042 | FCVTZS_dd 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1043 | FCVTZU_dd 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1044 | ||
cda3c753 RH |
1045 | # SVE floating-point round to integral value |
1046 | FRINTN 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn | |
1047 | FRINTP 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn | |
1048 | FRINTM 01100101 .. 000 010 101 ... ..... ..... @rd_pg_rn | |
1049 | FRINTZ 01100101 .. 000 011 101 ... ..... ..... @rd_pg_rn | |
1050 | FRINTA 01100101 .. 000 100 101 ... ..... ..... @rd_pg_rn | |
1051 | FRINTX 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn | |
1052 | FRINTI 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn | |
1053 | ||
ec5b375b RH |
1054 | # SVE floating-point unary operations |
1055 | FRECPX 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn | |
1056 | FSQRT 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn | |
1057 | ||
8092c6a3 RH |
1058 | # SVE integer convert to floating-point |
1059 | SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1060 | SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1061 | SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1062 | SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1063 | SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1064 | SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1065 | SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1066 | ||
1067 | UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1068 | UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1069 | UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1070 | UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1071 | UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1072 | UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1073 | UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1074 | ||
d1822297 RH |
1075 | ### SVE Memory - 32-bit Gather and Unsized Contiguous Group |
1076 | ||
1077 | # SVE load predicate register | |
1078 | LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9 | |
1079 | ||
1080 | # SVE load vector register | |
1081 | LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9 | |
c4e7c493 | 1082 | |
68459864 RH |
1083 | # SVE load and broadcast element |
1084 | LD1R_zpri 1000010 .. 1 imm:6 1.. pg:3 rn:5 rd:5 \ | |
1085 | &rpri_load dtype=%dtype_23_13 nreg=0 | |
1086 | ||
673e9fa6 RH |
1087 | # SVE 32-bit gather load (scalar plus 32-bit unscaled offsets) |
1088 | # SVE 32-bit gather load (scalar plus 32-bit scaled offsets) | |
1089 | LD1_zprz 1000010 00 .0 ..... 0.. ... ..... ..... \ | |
1090 | @rprr_g_load_xs_u esz=2 msz=0 scale=0 | |
1091 | LD1_zprz 1000010 01 .. ..... 0.. ... ..... ..... \ | |
1092 | @rprr_g_load_xs_u_sc esz=2 msz=1 | |
1093 | LD1_zprz 1000010 10 .. ..... 01. ... ..... ..... \ | |
1094 | @rprr_g_load_xs_sc esz=2 msz=2 u=1 | |
1095 | ||
1096 | # SVE 32-bit gather load (vector plus immediate) | |
1097 | LD1_zpiz 1000010 .. 01 ..... 1.. ... ..... ..... \ | |
1098 | @rpri_g_load esz=2 | |
1099 | ||
c4e7c493 RH |
1100 | ### SVE Memory Contiguous Load Group |
1101 | ||
1102 | # SVE contiguous load (scalar plus scalar) | |
1103 | LD_zprr 1010010 .... ..... 010 ... ..... ..... @rprr_load_dt nreg=0 | |
1104 | ||
e2654d75 RH |
1105 | # SVE contiguous first-fault load (scalar plus scalar) |
1106 | LDFF1_zprr 1010010 .... ..... 011 ... ..... ..... @rprr_load_dt nreg=0 | |
1107 | ||
c4e7c493 RH |
1108 | # SVE contiguous load (scalar plus immediate) |
1109 | LD_zpri 1010010 .... 0.... 101 ... ..... ..... @rpri_load_dt nreg=0 | |
1110 | ||
e2654d75 RH |
1111 | # SVE contiguous non-fault load (scalar plus immediate) |
1112 | LDNF1_zpri 1010010 .... 1.... 101 ... ..... ..... @rpri_load_dt nreg=0 | |
1113 | ||
c4e7c493 RH |
1114 | # SVE contiguous non-temporal load (scalar plus scalar) |
1115 | # LDNT1B, LDNT1H, LDNT1W, LDNT1D | |
1116 | # SVE load multiple structures (scalar plus scalar) | |
1117 | # LD2B, LD2H, LD2W, LD2D; etc. | |
1118 | LD_zprr 1010010 .. nreg:2 ..... 110 ... ..... ..... @rprr_load_msz | |
1119 | ||
1120 | # SVE contiguous non-temporal load (scalar plus immediate) | |
1121 | # LDNT1B, LDNT1H, LDNT1W, LDNT1D | |
1122 | # SVE load multiple structures (scalar plus immediate) | |
1123 | # LD2B, LD2H, LD2W, LD2D; etc. | |
1124 | LD_zpri 1010010 .. nreg:2 0.... 111 ... ..... ..... @rpri_load_msz | |
1a039c7e | 1125 | |
05abe304 RH |
1126 | # SVE load and broadcast quadword (scalar plus scalar) |
1127 | LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \ | |
1128 | @rprr_load_msz nreg=0 | |
1129 | ||
1130 | # SVE load and broadcast quadword (scalar plus immediate) | |
1131 | # LD1RQB, LD1RQH, LD1RQS, LD1RQD | |
1132 | LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \ | |
1133 | @rpri_load_msz nreg=0 | |
1134 | ||
dec6cf6b RH |
1135 | # SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets) |
1136 | PRF 1000010 00 -1 ----- 0-- --- ----- 0 ---- | |
1137 | ||
1138 | # SVE 32-bit gather prefetch (vector plus immediate) | |
1139 | PRF 1000010 -- 00 ----- 111 --- ----- 0 ---- | |
1140 | ||
1141 | # SVE contiguous prefetch (scalar plus immediate) | |
1142 | PRF 1000010 11 1- ----- 0-- --- ----- 0 ---- | |
1143 | ||
1144 | # SVE contiguous prefetch (scalar plus scalar) | |
1145 | PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ---- | |
1146 | ||
1147 | ### SVE Memory 64-bit Gather Group | |
1148 | ||
673e9fa6 RH |
1149 | # SVE 64-bit gather load (scalar plus 32-bit unpacked unscaled offsets) |
1150 | # SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets) | |
1151 | LD1_zprz 1100010 00 .0 ..... 0.. ... ..... ..... \ | |
1152 | @rprr_g_load_xs_u esz=3 msz=0 scale=0 | |
1153 | LD1_zprz 1100010 01 .. ..... 0.. ... ..... ..... \ | |
1154 | @rprr_g_load_xs_u_sc esz=3 msz=1 | |
1155 | LD1_zprz 1100010 10 .. ..... 0.. ... ..... ..... \ | |
1156 | @rprr_g_load_xs_u_sc esz=3 msz=2 | |
1157 | LD1_zprz 1100010 11 .. ..... 01. ... ..... ..... \ | |
1158 | @rprr_g_load_xs_sc esz=3 msz=3 u=1 | |
1159 | ||
1160 | # SVE 64-bit gather load (scalar plus 64-bit unscaled offsets) | |
1161 | # SVE 64-bit gather load (scalar plus 64-bit scaled offsets) | |
1162 | LD1_zprz 1100010 00 10 ..... 1.. ... ..... ..... \ | |
1163 | @rprr_g_load_u esz=3 msz=0 scale=0 | |
1164 | LD1_zprz 1100010 01 1. ..... 1.. ... ..... ..... \ | |
1165 | @rprr_g_load_u_sc esz=3 msz=1 | |
1166 | LD1_zprz 1100010 10 1. ..... 1.. ... ..... ..... \ | |
1167 | @rprr_g_load_u_sc esz=3 msz=2 | |
1168 | LD1_zprz 1100010 11 1. ..... 11. ... ..... ..... \ | |
1169 | @rprr_g_load_sc esz=3 msz=3 u=1 | |
1170 | ||
1171 | # SVE 64-bit gather load (vector plus immediate) | |
1172 | LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \ | |
1173 | @rpri_g_load esz=3 | |
1174 | ||
dec6cf6b RH |
1175 | # SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets) |
1176 | PRF 1100010 00 11 ----- 1-- --- ----- 0 ---- | |
1177 | ||
1178 | # SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets) | |
1179 | PRF 1100010 00 -1 ----- 0-- --- ----- 0 ---- | |
1180 | ||
1181 | # SVE 64-bit gather prefetch (vector plus immediate) | |
1182 | PRF 1100010 -- 00 ----- 111 --- ----- 0 ---- | |
1183 | ||
1a039c7e RH |
1184 | ### SVE Memory Store Group |
1185 | ||
5047c204 RH |
1186 | # SVE store predicate register |
1187 | STR_pri 1110010 11 0. ..... 000 ... ..... 0 .... @pd_rn_i9 | |
1188 | ||
1189 | # SVE store vector register | |
1190 | STR_zri 1110010 11 0. ..... 010 ... ..... ..... @rd_rn_i9 | |
1191 | ||
1a039c7e RH |
1192 | # SVE contiguous store (scalar plus immediate) |
1193 | # ST1B, ST1H, ST1W, ST1D; require msz <= esz | |
1194 | ST_zpri 1110010 .. esz:2 0.... 111 ... ..... ..... \ | |
1195 | @rpri_store_msz nreg=0 | |
1196 | ||
1197 | # SVE contiguous store (scalar plus scalar) | |
1198 | # ST1B, ST1H, ST1W, ST1D; require msz <= esz | |
1199 | # Enumerate msz lest we conflict with STR_zri. | |
1200 | ST_zprr 1110010 00 .. ..... 010 ... ..... ..... \ | |
1201 | @rprr_store_esz_n0 msz=0 | |
1202 | ST_zprr 1110010 01 .. ..... 010 ... ..... ..... \ | |
1203 | @rprr_store_esz_n0 msz=1 | |
1204 | ST_zprr 1110010 10 .. ..... 010 ... ..... ..... \ | |
1205 | @rprr_store_esz_n0 msz=2 | |
1206 | ST_zprr 1110010 11 11 ..... 010 ... ..... ..... \ | |
1207 | @rprr_store msz=3 esz=3 nreg=0 | |
1208 | ||
1209 | # SVE contiguous non-temporal store (scalar plus immediate) (nreg == 0) | |
1210 | # SVE store multiple structures (scalar plus immediate) (nreg != 0) | |
1211 | ST_zpri 1110010 .. nreg:2 1.... 111 ... ..... ..... \ | |
1212 | @rpri_store_msz esz=%size_23 | |
1213 | ||
1214 | # SVE contiguous non-temporal store (scalar plus scalar) (nreg == 0) | |
1215 | # SVE store multiple structures (scalar plus scalar) (nreg != 0) | |
1216 | ST_zprr 1110010 msz:2 nreg:2 ..... 011 ... ..... ..... \ | |
1217 | @rprr_store esz=%size_23 | |
f6dbf62a RH |
1218 | |
1219 | # SVE 32-bit scatter store (scalar plus 32-bit scaled offsets) | |
1220 | # Require msz > 0 && msz <= esz. | |
1221 | ST1_zprz 1110010 .. 11 ..... 100 ... ..... ..... \ | |
1222 | @rprr_scatter_store xs=0 esz=2 scale=1 | |
1223 | ST1_zprz 1110010 .. 11 ..... 110 ... ..... ..... \ | |
1224 | @rprr_scatter_store xs=1 esz=2 scale=1 | |
1225 | ||
1226 | # SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets) | |
1227 | # Require msz <= esz. | |
1228 | ST1_zprz 1110010 .. 10 ..... 100 ... ..... ..... \ | |
1229 | @rprr_scatter_store xs=0 esz=2 scale=0 | |
1230 | ST1_zprz 1110010 .. 10 ..... 110 ... ..... ..... \ | |
1231 | @rprr_scatter_store xs=1 esz=2 scale=0 | |
1232 | ||
1233 | # SVE 64-bit scatter store (scalar plus 64-bit scaled offset) | |
1234 | # Require msz > 0 | |
1235 | ST1_zprz 1110010 .. 01 ..... 101 ... ..... ..... \ | |
1236 | @rprr_scatter_store xs=2 esz=3 scale=1 | |
1237 | ||
1238 | # SVE 64-bit scatter store (scalar plus 64-bit unscaled offset) | |
1239 | ST1_zprz 1110010 .. 00 ..... 101 ... ..... ..... \ | |
1240 | @rprr_scatter_store xs=2 esz=3 scale=0 | |
1241 | ||
408ecde9 RH |
1242 | # SVE 64-bit scatter store (vector plus immediate) |
1243 | ST1_zpiz 1110010 .. 10 ..... 101 ... ..... ..... \ | |
1244 | @rpri_scatter_store esz=3 | |
1245 | ||
1246 | # SVE 32-bit scatter store (vector plus immediate) | |
1247 | ST1_zpiz 1110010 .. 11 ..... 101 ... ..... ..... \ | |
1248 | @rpri_scatter_store esz=2 | |
1249 | ||
f6dbf62a RH |
1250 | # SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offset) |
1251 | # Require msz > 0 | |
1252 | ST1_zprz 1110010 .. 01 ..... 100 ... ..... ..... \ | |
1253 | @rprr_scatter_store xs=0 esz=3 scale=1 | |
1254 | ST1_zprz 1110010 .. 01 ..... 110 ... ..... ..... \ | |
1255 | @rprr_scatter_store xs=1 esz=3 scale=1 | |
1256 | ||
1257 | # SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offset) | |
1258 | ST1_zprz 1110010 .. 00 ..... 100 ... ..... ..... \ | |
1259 | @rprr_scatter_store xs=0 esz=3 scale=0 | |
1260 | ST1_zprz 1110010 .. 00 ..... 110 ... ..... ..... \ | |
1261 | @rprr_scatter_store xs=1 esz=3 scale=0 | |
5dad1ba5 RH |
1262 | |
1263 | #### SVE2 Support | |
1264 | ||
1265 | ### SVE2 Integer Multiply - Unpredicated | |
1266 | ||
1267 | # SVE2 integer multiply vectors (unpredicated) | |
1268 | MUL_zzz 00000100 .. 1 ..... 0110 00 ..... ..... @rd_rn_rm | |
1269 | SMULH_zzz 00000100 .. 1 ..... 0110 10 ..... ..... @rd_rn_rm | |
1270 | UMULH_zzz 00000100 .. 1 ..... 0110 11 ..... ..... @rd_rn_rm | |
1271 | PMUL_zzz 00000100 00 1 ..... 0110 01 ..... ..... @rd_rn_rm_e0 | |
d4b1e59d | 1272 | |
169d7c58 RH |
1273 | # SVE2 signed saturating doubling multiply high (unpredicated) |
1274 | SQDMULH_zzz 00000100 .. 1 ..... 0111 00 ..... ..... @rd_rn_rm | |
1275 | SQRDMULH_zzz 00000100 .. 1 ..... 0111 01 ..... ..... @rd_rn_rm | |
1276 | ||
d4b1e59d RH |
1277 | ### SVE2 Integer - Predicated |
1278 | ||
1279 | SADALP_zpzz 01000100 .. 000 100 101 ... ..... ..... @rdm_pg_rn | |
1280 | UADALP_zpzz 01000100 .. 000 101 101 ... ..... ..... @rdm_pg_rn | |
db366da8 RH |
1281 | |
1282 | ### SVE2 integer unary operations (predicated) | |
1283 | ||
1284 | URECPE 01000100 .. 000 000 101 ... ..... ..... @rd_pg_rn | |
1285 | URSQRTE 01000100 .. 000 001 101 ... ..... ..... @rd_pg_rn | |
1286 | SQABS 01000100 .. 001 000 101 ... ..... ..... @rd_pg_rn | |
1287 | SQNEG 01000100 .. 001 001 101 ... ..... ..... @rd_pg_rn | |
45d9503d RH |
1288 | |
1289 | ### SVE2 saturating/rounding bitwise shift left (predicated) | |
1290 | ||
1291 | SRSHL 01000100 .. 000 010 100 ... ..... ..... @rdn_pg_rm | |
1292 | URSHL 01000100 .. 000 011 100 ... ..... ..... @rdn_pg_rm | |
1293 | SRSHL 01000100 .. 000 110 100 ... ..... ..... @rdm_pg_rn # SRSHLR | |
1294 | URSHL 01000100 .. 000 111 100 ... ..... ..... @rdm_pg_rn # URSHLR | |
1295 | ||
1296 | SQSHL 01000100 .. 001 000 100 ... ..... ..... @rdn_pg_rm | |
1297 | UQSHL 01000100 .. 001 001 100 ... ..... ..... @rdn_pg_rm | |
1298 | SQSHL 01000100 .. 001 100 100 ... ..... ..... @rdm_pg_rn # SQSHLR | |
1299 | UQSHL 01000100 .. 001 101 100 ... ..... ..... @rdm_pg_rn # UQSHLR | |
1300 | ||
1301 | SQRSHL 01000100 .. 001 010 100 ... ..... ..... @rdn_pg_rm | |
1302 | UQRSHL 01000100 .. 001 011 100 ... ..... ..... @rdn_pg_rm | |
1303 | SQRSHL 01000100 .. 001 110 100 ... ..... ..... @rdm_pg_rn # SQRSHLR | |
1304 | UQRSHL 01000100 .. 001 111 100 ... ..... ..... @rdm_pg_rn # UQRSHLR | |
a47dc220 RH |
1305 | |
1306 | ### SVE2 integer halving add/subtract (predicated) | |
1307 | ||
1308 | SHADD 01000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm | |
1309 | UHADD 01000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm | |
1310 | SHSUB 01000100 .. 010 010 100 ... ..... ..... @rdn_pg_rm | |
1311 | UHSUB 01000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm | |
1312 | SRHADD 01000100 .. 010 100 100 ... ..... ..... @rdn_pg_rm | |
1313 | URHADD 01000100 .. 010 101 100 ... ..... ..... @rdn_pg_rm | |
1314 | SHSUB 01000100 .. 010 110 100 ... ..... ..... @rdm_pg_rn # SHSUBR | |
1315 | UHSUB 01000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # UHSUBR | |
8597dc8b RH |
1316 | |
1317 | ### SVE2 integer pairwise arithmetic | |
1318 | ||
1319 | ADDP 01000100 .. 010 001 101 ... ..... ..... @rdn_pg_rm | |
1320 | SMAXP 01000100 .. 010 100 101 ... ..... ..... @rdn_pg_rm | |
1321 | UMAXP 01000100 .. 010 101 101 ... ..... ..... @rdn_pg_rm | |
1322 | SMINP 01000100 .. 010 110 101 ... ..... ..... @rdn_pg_rm | |
1323 | UMINP 01000100 .. 010 111 101 ... ..... ..... @rdn_pg_rm | |
4f07fbeb RH |
1324 | |
1325 | ### SVE2 saturating add/subtract (predicated) | |
1326 | ||
1327 | SQADD_zpzz 01000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm | |
1328 | UQADD_zpzz 01000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm | |
1329 | SQSUB_zpzz 01000100 .. 011 010 100 ... ..... ..... @rdn_pg_rm | |
1330 | UQSUB_zpzz 01000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm | |
1331 | SUQADD 01000100 .. 011 100 100 ... ..... ..... @rdn_pg_rm | |
1332 | USQADD 01000100 .. 011 101 100 ... ..... ..... @rdn_pg_rm | |
1333 | SQSUB_zpzz 01000100 .. 011 110 100 ... ..... ..... @rdm_pg_rn # SQSUBR | |
1334 | UQSUB_zpzz 01000100 .. 011 111 100 ... ..... ..... @rdm_pg_rn # UQSUBR | |
0ce1dda8 RH |
1335 | |
1336 | #### SVE2 Widening Integer Arithmetic | |
1337 | ||
1338 | ## SVE2 integer add/subtract long | |
1339 | ||
1340 | SADDLB 01000101 .. 0 ..... 00 0000 ..... ..... @rd_rn_rm | |
1341 | SADDLT 01000101 .. 0 ..... 00 0001 ..... ..... @rd_rn_rm | |
1342 | UADDLB 01000101 .. 0 ..... 00 0010 ..... ..... @rd_rn_rm | |
1343 | UADDLT 01000101 .. 0 ..... 00 0011 ..... ..... @rd_rn_rm | |
1344 | ||
1345 | SSUBLB 01000101 .. 0 ..... 00 0100 ..... ..... @rd_rn_rm | |
1346 | SSUBLT 01000101 .. 0 ..... 00 0101 ..... ..... @rd_rn_rm | |
1347 | USUBLB 01000101 .. 0 ..... 00 0110 ..... ..... @rd_rn_rm | |
1348 | USUBLT 01000101 .. 0 ..... 00 0111 ..... ..... @rd_rn_rm | |
1349 | ||
1350 | SABDLB 01000101 .. 0 ..... 00 1100 ..... ..... @rd_rn_rm | |
1351 | SABDLT 01000101 .. 0 ..... 00 1101 ..... ..... @rd_rn_rm | |
1352 | UABDLB 01000101 .. 0 ..... 00 1110 ..... ..... @rd_rn_rm | |
1353 | UABDLT 01000101 .. 0 ..... 00 1111 ..... ..... @rd_rn_rm | |
daec426b RH |
1354 | |
1355 | ## SVE2 integer add/subtract interleaved long | |
1356 | ||
1357 | SADDLBT 01000101 .. 0 ..... 1000 00 ..... ..... @rd_rn_rm | |
1358 | SSUBLBT 01000101 .. 0 ..... 1000 10 ..... ..... @rd_rn_rm | |
1359 | SSUBLTB 01000101 .. 0 ..... 1000 11 ..... ..... @rd_rn_rm | |
81fccf09 RH |
1360 | |
1361 | ## SVE2 integer add/subtract wide | |
1362 | ||
1363 | SADDWB 01000101 .. 0 ..... 010 000 ..... ..... @rd_rn_rm | |
1364 | SADDWT 01000101 .. 0 ..... 010 001 ..... ..... @rd_rn_rm | |
1365 | UADDWB 01000101 .. 0 ..... 010 010 ..... ..... @rd_rn_rm | |
1366 | UADDWT 01000101 .. 0 ..... 010 011 ..... ..... @rd_rn_rm | |
1367 | ||
1368 | SSUBWB 01000101 .. 0 ..... 010 100 ..... ..... @rd_rn_rm | |
1369 | SSUBWT 01000101 .. 0 ..... 010 101 ..... ..... @rd_rn_rm | |
1370 | USUBWB 01000101 .. 0 ..... 010 110 ..... ..... @rd_rn_rm | |
1371 | USUBWT 01000101 .. 0 ..... 010 111 ..... ..... @rd_rn_rm | |
69ccc099 RH |
1372 | |
1373 | ## SVE2 integer multiply long | |
1374 | ||
1375 | SQDMULLB_zzz 01000101 .. 0 ..... 011 000 ..... ..... @rd_rn_rm | |
1376 | SQDMULLT_zzz 01000101 .. 0 ..... 011 001 ..... ..... @rd_rn_rm | |
e3a56131 RH |
1377 | PMULLB 01000101 .. 0 ..... 011 010 ..... ..... @rd_rn_rm |
1378 | PMULLT 01000101 .. 0 ..... 011 011 ..... ..... @rd_rn_rm | |
69ccc099 RH |
1379 | SMULLB_zzz 01000101 .. 0 ..... 011 100 ..... ..... @rd_rn_rm |
1380 | SMULLT_zzz 01000101 .. 0 ..... 011 101 ..... ..... @rd_rn_rm | |
1381 | UMULLB_zzz 01000101 .. 0 ..... 011 110 ..... ..... @rd_rn_rm | |
1382 | UMULLT_zzz 01000101 .. 0 ..... 011 111 ..... ..... @rd_rn_rm | |
4269fef1 RH |
1383 | |
1384 | ## SVE2 bitwise shift left long | |
1385 | ||
1386 | # Note bit23 == 0 is handled by esz > 0 in do_sve2_shll_tb. | |
1387 | SSHLLB 01000101 .. 0 ..... 1010 00 ..... ..... @rd_rn_tszimm_shl | |
1388 | SSHLLT 01000101 .. 0 ..... 1010 01 ..... ..... @rd_rn_tszimm_shl | |
1389 | USHLLB 01000101 .. 0 ..... 1010 10 ..... ..... @rd_rn_tszimm_shl | |
1390 | USHLLT 01000101 .. 0 ..... 1010 11 ..... ..... @rd_rn_tszimm_shl | |
2df3ca55 RH |
1391 | |
1392 | ## SVE2 bitwise exclusive-or interleaved | |
1393 | ||
1394 | EORBT 01000101 .. 0 ..... 10010 0 ..... ..... @rd_rn_rm | |
1395 | EORTB 01000101 .. 0 ..... 10010 1 ..... ..... @rd_rn_rm | |
cb9c33b8 RH |
1396 | |
1397 | ## SVE2 bitwise permute | |
1398 | ||
1399 | BEXT 01000101 .. 0 ..... 1011 00 ..... ..... @rd_rn_rm | |
1400 | BDEP 01000101 .. 0 ..... 1011 01 ..... ..... @rd_rn_rm | |
1401 | BGRP 01000101 .. 0 ..... 1011 10 ..... ..... @rd_rn_rm | |
ed4a6387 RH |
1402 | |
1403 | #### SVE2 Accumulate | |
1404 | ||
1405 | ## SVE2 complex integer add | |
1406 | ||
1407 | CADD_rot90 01000101 .. 00000 0 11011 0 ..... ..... @rdn_rm | |
1408 | CADD_rot270 01000101 .. 00000 0 11011 1 ..... ..... @rdn_rm | |
1409 | SQCADD_rot90 01000101 .. 00000 1 11011 0 ..... ..... @rdn_rm | |
1410 | SQCADD_rot270 01000101 .. 00000 1 11011 1 ..... ..... @rdn_rm | |
38650638 RH |
1411 | |
1412 | ## SVE2 integer absolute difference and accumulate long | |
1413 | ||
1414 | SABALB 01000101 .. 0 ..... 1100 00 ..... ..... @rda_rn_rm | |
1415 | SABALT 01000101 .. 0 ..... 1100 01 ..... ..... @rda_rn_rm | |
1416 | UABALB 01000101 .. 0 ..... 1100 10 ..... ..... @rda_rn_rm | |
1417 | UABALT 01000101 .. 0 ..... 1100 11 ..... ..... @rda_rn_rm | |
b8295dfb RH |
1418 | |
1419 | ## SVE2 integer add/subtract long with carry | |
1420 | ||
1421 | # ADC and SBC decoded via size in helper dispatch. | |
1422 | ADCLB 01000101 .. 0 ..... 11010 0 ..... ..... @rda_rn_rm | |
1423 | ADCLT 01000101 .. 0 ..... 11010 1 ..... ..... @rda_rn_rm | |
a7e3a90e RH |
1424 | |
1425 | ## SVE2 bitwise shift right and accumulate | |
1426 | ||
1427 | # TODO: Use @rda and %reg_movprfx here. | |
1428 | SSRA 01000101 .. 0 ..... 1110 00 ..... ..... @rd_rn_tszimm_shr | |
1429 | USRA 01000101 .. 0 ..... 1110 01 ..... ..... @rd_rn_tszimm_shr | |
1430 | SRSRA 01000101 .. 0 ..... 1110 10 ..... ..... @rd_rn_tszimm_shr | |
1431 | URSRA 01000101 .. 0 ..... 1110 11 ..... ..... @rd_rn_tszimm_shr | |
fc12b46a RH |
1432 | |
1433 | ## SVE2 bitwise shift and insert | |
1434 | ||
1435 | SRI 01000101 .. 0 ..... 11110 0 ..... ..... @rd_rn_tszimm_shr | |
1436 | SLI 01000101 .. 0 ..... 11110 1 ..... ..... @rd_rn_tszimm_shl | |
289a1797 RH |
1437 | |
1438 | ## SVE2 integer absolute difference and accumulate | |
1439 | ||
1440 | # TODO: Use @rda and %reg_movprfx here. | |
1441 | SABA 01000101 .. 0 ..... 11111 0 ..... ..... @rd_rn_rm | |
1442 | UABA 01000101 .. 0 ..... 11111 1 ..... ..... @rd_rn_rm | |
5ff2838d RH |
1443 | |
1444 | #### SVE2 Narrowing | |
1445 | ||
1446 | ## SVE2 saturating extract narrow | |
1447 | ||
1448 | # Bits 23, 18-16 are zero, limited in the translator via esz < 3 & imm == 0. | |
1449 | SQXTNB 01000101 .. 1 ..... 010 000 ..... ..... @rd_rn_tszimm_shl | |
1450 | SQXTNT 01000101 .. 1 ..... 010 001 ..... ..... @rd_rn_tszimm_shl | |
1451 | UQXTNB 01000101 .. 1 ..... 010 010 ..... ..... @rd_rn_tszimm_shl | |
1452 | UQXTNT 01000101 .. 1 ..... 010 011 ..... ..... @rd_rn_tszimm_shl | |
1453 | SQXTUNB 01000101 .. 1 ..... 010 100 ..... ..... @rd_rn_tszimm_shl | |
1454 | SQXTUNT 01000101 .. 1 ..... 010 101 ..... ..... @rd_rn_tszimm_shl | |
b87dbeeb | 1455 | |
46d111b2 RH |
1456 | ## SVE2 bitwise shift right narrow |
1457 | ||
1458 | # Bit 23 == 0 is handled by esz > 0 in the translator. | |
81fd3e6e RH |
1459 | SQSHRUNB 01000101 .. 1 ..... 00 0000 ..... ..... @rd_rn_tszimm_shr |
1460 | SQSHRUNT 01000101 .. 1 ..... 00 0001 ..... ..... @rd_rn_tszimm_shr | |
1461 | SQRSHRUNB 01000101 .. 1 ..... 00 0010 ..... ..... @rd_rn_tszimm_shr | |
1462 | SQRSHRUNT 01000101 .. 1 ..... 00 0011 ..... ..... @rd_rn_tszimm_shr | |
46d111b2 RH |
1463 | SHRNB 01000101 .. 1 ..... 00 0100 ..... ..... @rd_rn_tszimm_shr |
1464 | SHRNT 01000101 .. 1 ..... 00 0101 ..... ..... @rd_rn_tszimm_shr | |
1465 | RSHRNB 01000101 .. 1 ..... 00 0110 ..... ..... @rd_rn_tszimm_shr | |
1466 | RSHRNT 01000101 .. 1 ..... 00 0111 ..... ..... @rd_rn_tszimm_shr | |
743bb147 RH |
1467 | SQSHRNB 01000101 .. 1 ..... 00 1000 ..... ..... @rd_rn_tszimm_shr |
1468 | SQSHRNT 01000101 .. 1 ..... 00 1001 ..... ..... @rd_rn_tszimm_shr | |
1469 | SQRSHRNB 01000101 .. 1 ..... 00 1010 ..... ..... @rd_rn_tszimm_shr | |
1470 | SQRSHRNT 01000101 .. 1 ..... 00 1011 ..... ..... @rd_rn_tszimm_shr | |
c13418da RH |
1471 | UQSHRNB 01000101 .. 1 ..... 00 1100 ..... ..... @rd_rn_tszimm_shr |
1472 | UQSHRNT 01000101 .. 1 ..... 00 1101 ..... ..... @rd_rn_tszimm_shr | |
1473 | UQRSHRNB 01000101 .. 1 ..... 00 1110 ..... ..... @rd_rn_tszimm_shr | |
1474 | UQRSHRNT 01000101 .. 1 ..... 00 1111 ..... ..... @rd_rn_tszimm_shr | |
46d111b2 | 1475 | |
40d5ea50 SL |
1476 | ## SVE2 integer add/subtract narrow high part |
1477 | ||
1478 | ADDHNB 01000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm | |
1479 | ADDHNT 01000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm | |
0ea3ff02 SL |
1480 | RADDHNB 01000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm |
1481 | RADDHNT 01000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm | |
c3cd6766 SL |
1482 | SUBHNB 01000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm |
1483 | SUBHNT 01000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm | |
e9443d10 SL |
1484 | RSUBHNB 01000101 .. 1 ..... 011 110 ..... ..... @rd_rn_rm |
1485 | RSUBHNT 01000101 .. 1 ..... 011 111 ..... ..... @rd_rn_rm | |
40d5ea50 | 1486 | |
e0ae6ec3 SL |
1487 | ### SVE2 Character Match |
1488 | ||
1489 | MATCH 01000101 .. 1 ..... 100 ... ..... 0 .... @pd_pg_rn_rm | |
1490 | NMATCH 01000101 .. 1 ..... 100 ... ..... 1 .... @pd_pg_rn_rm | |
1491 | ||
7d47ac94 SL |
1492 | ### SVE2 Histogram Computation |
1493 | ||
1494 | HISTCNT 01000101 .. 1 ..... 110 ... ..... ..... @rd_pg_rn_rm | |
1495 | HISTSEG 01000101 .. 1 ..... 101 000 ..... ..... @rd_rn_rm | |
1496 | ||
b87dbeeb SL |
1497 | ## SVE2 floating-point pairwise operations |
1498 | ||
1499 | FADDP 01100100 .. 010 00 0 100 ... ..... ..... @rdn_pg_rm | |
1500 | FMAXNMP 01100100 .. 010 10 0 100 ... ..... ..... @rdn_pg_rm | |
1501 | FMINNMP 01100100 .. 010 10 1 100 ... ..... ..... @rdn_pg_rm | |
1502 | FMAXP 01100100 .. 010 11 0 100 ... ..... ..... @rdn_pg_rm | |
1503 | FMINP 01100100 .. 010 11 1 100 ... ..... ..... @rdn_pg_rm | |
bfc9307e RH |
1504 | |
1505 | #### SVE Integer Multiply-Add (unpredicated) | |
1506 | ||
1507 | ## SVE2 saturating multiply-add long | |
1508 | ||
1509 | SQDMLALB_zzzw 01000100 .. 0 ..... 0110 00 ..... ..... @rda_rn_rm | |
1510 | SQDMLALT_zzzw 01000100 .. 0 ..... 0110 01 ..... ..... @rda_rn_rm | |
1511 | SQDMLSLB_zzzw 01000100 .. 0 ..... 0110 10 ..... ..... @rda_rn_rm | |
1512 | SQDMLSLT_zzzw 01000100 .. 0 ..... 0110 11 ..... ..... @rda_rn_rm | |
1513 | ||
1514 | ## SVE2 saturating multiply-add interleaved long | |
1515 | ||
1516 | SQDMLALBT 01000100 .. 0 ..... 00001 0 ..... ..... @rda_rn_rm | |
1517 | SQDMLSLBT 01000100 .. 0 ..... 00001 1 ..... ..... @rda_rn_rm | |
ab3ddf31 RH |
1518 | |
1519 | ## SVE2 saturating multiply-add high | |
1520 | ||
1521 | SQRDMLAH_zzzz 01000100 .. 0 ..... 01110 0 ..... ..... @rda_rn_rm | |
1522 | SQRDMLSH_zzzz 01000100 .. 0 ..... 01110 1 ..... ..... @rda_rn_rm | |
45a32e80 RH |
1523 | |
1524 | ## SVE2 integer multiply-add long | |
1525 | ||
1526 | SMLALB_zzzw 01000100 .. 0 ..... 010 000 ..... ..... @rda_rn_rm | |
1527 | SMLALT_zzzw 01000100 .. 0 ..... 010 001 ..... ..... @rda_rn_rm | |
1528 | UMLALB_zzzw 01000100 .. 0 ..... 010 010 ..... ..... @rda_rn_rm | |
1529 | UMLALT_zzzw 01000100 .. 0 ..... 010 011 ..... ..... @rda_rn_rm | |
1530 | SMLSLB_zzzw 01000100 .. 0 ..... 010 100 ..... ..... @rda_rn_rm | |
1531 | SMLSLT_zzzw 01000100 .. 0 ..... 010 101 ..... ..... @rda_rn_rm | |
1532 | UMLSLB_zzzw 01000100 .. 0 ..... 010 110 ..... ..... @rda_rn_rm | |
1533 | UMLSLT_zzzw 01000100 .. 0 ..... 010 111 ..... ..... @rda_rn_rm | |
d782d3ca RH |
1534 | |
1535 | ## SVE2 complex integer multiply-add | |
1536 | ||
1537 | CMLA_zzzz 01000100 esz:2 0 rm:5 0010 rot:2 rn:5 rd:5 ra=%reg_movprfx | |
1538 | SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx | |
6ebca45f | 1539 | |
6a98cb2a RH |
1540 | ## SVE mixed sign dot product |
1541 | ||
1542 | USDOT_zzzz 01000100 .. 0 ..... 011 110 ..... ..... @rda_rn_rm | |
1543 | ||
4f26756b SL |
1544 | ### SVE2 floating point matrix multiply accumulate |
1545 | ||
1546 | FMMLA 01100100 .. 1 ..... 111001 ..... ..... @rda_rn_rm | |
1547 | ||
cf327449 SL |
1548 | ### SVE2 Memory Gather Load Group |
1549 | ||
1550 | # SVE2 64-bit gather non-temporal load | |
1551 | # (scalar plus unpacked 32-bit unscaled offsets) | |
1552 | LDNT1_zprz 1100010 msz:2 00 rm:5 1 u:1 0 pg:3 rn:5 rd:5 \ | |
1553 | &rprr_gather_load xs=0 esz=3 scale=0 ff=0 | |
1554 | ||
1555 | # SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets) | |
1556 | LDNT1_zprz 1000010 msz:2 00 rm:5 10 u:1 pg:3 rn:5 rd:5 \ | |
1557 | &rprr_gather_load xs=0 esz=2 scale=0 ff=0 | |
1558 | ||
6ebca45f SL |
1559 | ### SVE2 Memory Store Group |
1560 | ||
1561 | # SVE2 64-bit scatter non-temporal store (vector plus scalar) | |
1562 | STNT1_zprz 1110010 .. 00 ..... 001 ... ..... ..... \ | |
1563 | @rprr_scatter_store xs=2 esz=3 scale=0 | |
1564 | ||
1565 | # SVE2 32-bit scatter non-temporal store (vector plus scalar) | |
1566 | STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \ | |
1567 | @rprr_scatter_store xs=0 esz=2 scale=0 | |
b2bcd1be RH |
1568 | |
1569 | ### SVE2 Crypto Extensions | |
1570 | ||
1571 | # SVE2 crypto unary operations | |
1572 | # AESMC and AESIMC | |
1573 | AESMC 01000101 00 10000011100 decrypt:1 00000 rd:5 | |
3cc7a88e RH |
1574 | |
1575 | # SVE2 crypto destructive binary operations | |
1576 | AESE 01000101 00 10001 0 11100 0 ..... ..... @rdn_rm_e0 | |
1577 | AESD 01000101 00 10001 0 11100 1 ..... ..... @rdn_rm_e0 | |
1578 | SM4E 01000101 00 10001 1 11100 0 ..... ..... @rdn_rm_e0 | |
3358eb3f RH |
1579 | |
1580 | # SVE2 crypto constructive binary operations | |
1581 | SM4EKEY 01000101 00 1 ..... 11110 0 ..... ..... @rd_rn_rm_e0 | |
1582 | RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0 | |
5c1b7226 RH |
1583 | |
1584 | ### SVE2 floating-point convert precision odd elements | |
1585 | FCVTNT_sh 01100100 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0 | |
1586 | FCVTNT_ds 01100100 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0 |