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38388f7e RH |
1 | # AArch64 SVE instruction descriptions |
2 | # | |
3 | # Copyright (c) 2017 Linaro, Ltd | |
4 | # | |
5 | # This library is free software; you can redistribute it and/or | |
6 | # modify it under the terms of the GNU Lesser General Public | |
7 | # License as published by the Free Software Foundation; either | |
8 | # version 2 of the License, or (at your option) any later version. | |
9 | # | |
10 | # This library is distributed in the hope that it will be useful, | |
11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | # Lesser General Public License for more details. | |
14 | # | |
15 | # You should have received a copy of the GNU Lesser General Public | |
16 | # License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
17 | ||
18 | # | |
19 | # This file is processed by scripts/decodetree.py | |
20 | # | |
21 | ||
d1822297 RH |
22 | ########################################################################### |
23 | # Named fields. These are primarily for disjoint fields. | |
24 | ||
f25a2361 | 25 | %imm4_16_p1 16:4 !function=plus1 |
ccd841c3 | 26 | %imm6_22_5 22:1 5:5 |
30562ab7 | 27 | %imm7_22_16 22:2 16:5 |
b94f8f60 | 28 | %imm8_16_10 16:5 10:3 |
d1822297 | 29 | %imm9_16_10 16:s6 10:3 |
1a039c7e | 30 | %size_23 23:2 |
d1822297 | 31 | |
ccd841c3 RH |
32 | # A combination of tsz:imm3 -- extract esize. |
33 | %tszimm_esz 22:2 5:5 !function=tszimm_esz | |
34 | # A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3) | |
35 | %tszimm_shr 22:2 5:5 !function=tszimm_shr | |
36 | # A combination of tsz:imm3 -- extract (tsz:imm3) - esize | |
37 | %tszimm_shl 22:2 5:5 !function=tszimm_shl | |
38 | ||
d9d78dcc RH |
39 | # Similarly for the tszh/tszl pair at 22/16 for zzi |
40 | %tszimm16_esz 22:2 16:5 !function=tszimm_esz | |
41 | %tszimm16_shr 22:2 16:5 !function=tszimm_shr | |
42 | %tszimm16_shl 22:2 16:5 !function=tszimm_shl | |
43 | ||
f25a2361 RH |
44 | # Signed 8-bit immediate, optionally shifted left by 8. |
45 | %sh8_i8s 5:9 !function=expand_imm_sh8s | |
6e6a157d RH |
46 | # Unsigned 8-bit immediate, optionally shifted left by 8. |
47 | %sh8_i8u 5:9 !function=expand_imm_sh8u | |
f25a2361 | 48 | |
c4e7c493 RH |
49 | # Unsigned load of msz into esz=2, represented as a dtype. |
50 | %msz_dtype 23:2 !function=msz_dtype | |
51 | ||
f97cfd59 RH |
52 | # Either a copy of rd (at bit 0), or a different source |
53 | # as propagated via the MOVPRFX instruction. | |
54 | %reg_movprfx 0:5 | |
55 | ||
38388f7e RH |
56 | ########################################################################### |
57 | # Named attribute sets. These are used to make nice(er) names | |
58 | # when creating helpers common to those for the individual | |
59 | # instruction patterns. | |
60 | ||
028e2a7b | 61 | &rr_esz rd rn esz |
d1822297 | 62 | &rri rd rn imm |
e1fa1164 | 63 | &rr_dbm rd rn dbm |
4b242d9c | 64 | &rrri rd rn rm imm |
d9d78dcc | 65 | &rri_esz rd rn imm esz |
38388f7e | 66 | &rrr_esz rd rn rm esz |
047cec97 | 67 | &rpr_esz rd pg rn esz |
35da316f | 68 | &rpr_s rd pg rn s |
516e246a | 69 | &rprr_s rd pg rn rm s |
f97cfd59 | 70 | &rprr_esz rd pg rn rm esz |
96a36e4a | 71 | &rprrr_esz rd pg rn rm ra esz |
ccd841c3 | 72 | &rpri_esz rd pg rn imm esz |
24e82e68 RH |
73 | &ptrue rd esz pat s |
74 | &incdec_cnt rd pat esz imm d u | |
75 | &incdec2_cnt rd rn pat esz imm d u | |
9ee3a611 RH |
76 | &incdec_pred rd pg esz d u |
77 | &incdec2_pred rd rn pg esz d u | |
c4e7c493 RH |
78 | &rprr_load rd pg rn rm dtype nreg |
79 | &rpri_load rd pg rn imm dtype nreg | |
1a039c7e RH |
80 | &rprr_store rd pg rn rm msz esz nreg |
81 | &rpri_store rd pg rn imm msz esz nreg | |
38388f7e RH |
82 | |
83 | ########################################################################### | |
84 | # Named instruction formats. These are generally used to | |
85 | # reduce the amount of duplication between instruction patterns. | |
86 | ||
028e2a7b RH |
87 | # Two operand with unused vector element size |
88 | @pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0 | |
89 | ||
90 | # Two operand | |
91 | @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz | |
0762cd42 | 92 | @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz |
028e2a7b | 93 | |
35da316f RH |
94 | # Two operand with governing predicate, flags setting |
95 | @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s | |
96 | ||
38388f7e RH |
97 | # Three operand with unused vector element size |
98 | @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 | |
99 | ||
516e246a RH |
100 | # Three predicate operand, with governing predicate, flag setting |
101 | @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s | |
102 | ||
fea98f9c RH |
103 | # Three operand, vector element size |
104 | @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz | |
d731d8cb | 105 | @pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz |
30562ab7 RH |
106 | @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \ |
107 | &rrr_esz rn=%reg_movprfx | |
6e6a157d RH |
108 | @rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \ |
109 | &rri_esz rn=%reg_movprfx imm=%sh8_i8u | |
110 | @rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \ | |
111 | &rri_esz rn=%reg_movprfx | |
112 | @rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \ | |
113 | &rri_esz rn=%reg_movprfx | |
fea98f9c | 114 | |
4b242d9c RH |
115 | # Three operand with "memory" size, aka immediate left shift |
116 | @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri | |
117 | ||
f97cfd59 RH |
118 | # Two register operand, with governing predicate, vector element size |
119 | @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \ | |
120 | &rprr_esz rn=%reg_movprfx | |
121 | @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ | |
122 | &rprr_esz rm=%reg_movprfx | |
d3fe4a29 | 123 | @rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz |
757f9cff | 124 | @pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz |
f97cfd59 | 125 | |
96a36e4a RH |
126 | # Three register operand, with governing predicate, vector element size |
127 | @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ | |
128 | &rprrr_esz ra=%reg_movprfx | |
129 | @rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \ | |
130 | &rprrr_esz rn=%reg_movprfx | |
6ceabaad RH |
131 | @rdn_pg_rm_ra ........ esz:2 . ra:5 ... pg:3 rm:5 rd:5 \ |
132 | &rprrr_esz rn=%reg_movprfx | |
96a36e4a | 133 | |
047cec97 RH |
134 | # One register operand, with governing predicate, vector element size |
135 | @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz | |
9ee3a611 | 136 | @rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz |
047cec97 | 137 | |
8092c6a3 RH |
138 | # One register operand, with governing predicate, no vector element size |
139 | @rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0 | |
140 | ||
96f922cc RH |
141 | # Two register operands with a 6-bit signed immediate. |
142 | @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri | |
143 | ||
ccd841c3 RH |
144 | # Two register operand, one immediate operand, with predicate, |
145 | # element size encoded as TSZHL. User must fill in imm. | |
146 | @rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \ | |
147 | &rpri_esz rn=%reg_movprfx esz=%tszimm_esz | |
148 | ||
d9d78dcc RH |
149 | # Similarly without predicate. |
150 | @rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \ | |
151 | &rri_esz esz=%tszimm16_esz | |
152 | ||
f25a2361 RH |
153 | # Two register operand, one immediate operand, with 4-bit predicate. |
154 | # User must fill in imm. | |
155 | @rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \ | |
156 | &rpri_esz rn=%reg_movprfx | |
157 | ||
e1fa1164 RH |
158 | # Two register operand, one encoded bitmask. |
159 | @rdn_dbm ........ .. .... dbm:13 rd:5 \ | |
160 | &rr_dbm rn=%reg_movprfx | |
161 | ||
38cadeba RH |
162 | # Predicate output, vector and immediate input, |
163 | # controlling predicate, element size. | |
164 | @pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz | |
165 | @pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz | |
166 | ||
d1822297 RH |
167 | # Basic Load/Store with 9-bit immediate offset |
168 | @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ | |
169 | &rri imm=%imm9_16_10 | |
170 | @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \ | |
171 | &rri imm=%imm9_16_10 | |
172 | ||
24e82e68 RH |
173 | # One register, pattern, and uint4+1. |
174 | # User must fill in U and D. | |
175 | @incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ | |
176 | &incdec_cnt imm=%imm4_16_p1 | |
177 | @incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ | |
178 | &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx | |
179 | ||
9ee3a611 RH |
180 | # One register, predicate. |
181 | # User must fill in U and D. | |
182 | @incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred | |
183 | @incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \ | |
184 | &incdec2_pred rn=%reg_movprfx | |
185 | ||
c4e7c493 RH |
186 | # Loads; user must fill in NREG. |
187 | @rprr_load_dt ....... dtype:4 rm:5 ... pg:3 rn:5 rd:5 &rprr_load | |
188 | @rpri_load_dt ....... dtype:4 . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load | |
189 | ||
190 | @rprr_load_msz ....... .... rm:5 ... pg:3 rn:5 rd:5 \ | |
191 | &rprr_load dtype=%msz_dtype | |
192 | @rpri_load_msz ....... .... . imm:s4 ... pg:3 rn:5 rd:5 \ | |
193 | &rpri_load dtype=%msz_dtype | |
194 | ||
1a039c7e RH |
195 | # Stores; user must fill in ESZ, MSZ, NREG as needed. |
196 | @rprr_store ....... .. .. rm:5 ... pg:3 rn:5 rd:5 &rprr_store | |
197 | @rpri_store_msz ....... msz:2 .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store | |
198 | @rprr_store_esz_n0 ....... .. esz:2 rm:5 ... pg:3 rn:5 rd:5 \ | |
199 | &rprr_store nreg=0 | |
200 | ||
38388f7e RH |
201 | ########################################################################### |
202 | # Instruction patterns. Grouped according to the SVE encodingindex.xhtml. | |
203 | ||
f97cfd59 RH |
204 | ### SVE Integer Arithmetic - Binary Predicated Group |
205 | ||
206 | # SVE bitwise logical vector operations (predicated) | |
207 | ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm | |
208 | EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm | |
209 | AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm | |
210 | BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm | |
211 | ||
212 | # SVE integer add/subtract vectors (predicated) | |
213 | ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm | |
214 | SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm | |
215 | SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR | |
216 | ||
217 | # SVE integer min/max/difference (predicated) | |
218 | SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm | |
219 | UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm | |
220 | SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm | |
221 | UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm | |
222 | SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm | |
223 | UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm | |
224 | ||
225 | # SVE integer multiply/divide (predicated) | |
226 | MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm | |
227 | SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm | |
228 | UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm | |
229 | # Note that divide requires size >= 2; below 2 is unallocated. | |
230 | SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm | |
231 | UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm | |
232 | SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR | |
233 | UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR | |
234 | ||
047cec97 RH |
235 | ### SVE Integer Reduction Group |
236 | ||
237 | # SVE bitwise logical reduction (predicated) | |
238 | ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn | |
239 | EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn | |
240 | ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn | |
241 | ||
242 | # SVE integer add reduction (predicated) | |
243 | # Note that saddv requires size != 3. | |
244 | UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn | |
245 | SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn | |
246 | ||
247 | # SVE integer min/max reduction (predicated) | |
248 | SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn | |
249 | UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn | |
250 | SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn | |
251 | UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn | |
252 | ||
ccd841c3 RH |
253 | ### SVE Shift by Immediate - Predicated Group |
254 | ||
255 | # SVE bitwise shift by immediate (predicated) | |
256 | ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \ | |
257 | @rdn_pg_tszimm imm=%tszimm_shr | |
258 | LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \ | |
259 | @rdn_pg_tszimm imm=%tszimm_shr | |
260 | LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \ | |
261 | @rdn_pg_tszimm imm=%tszimm_shl | |
262 | ASRD 00000100 .. 000 100 100 ... .. ... ..... \ | |
263 | @rdn_pg_tszimm imm=%tszimm_shr | |
264 | ||
27721dbb RH |
265 | # SVE bitwise shift by vector (predicated) |
266 | ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm | |
267 | LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm | |
268 | LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm | |
269 | ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR | |
270 | LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR | |
271 | LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR | |
272 | ||
fe7f8dfb RH |
273 | # SVE bitwise shift by wide elements (predicated) |
274 | # Note these require size != 3. | |
275 | ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm | |
276 | LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm | |
277 | LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm | |
278 | ||
afac6d04 RH |
279 | ### SVE Integer Arithmetic - Unary Predicated Group |
280 | ||
281 | # SVE unary bit operations (predicated) | |
282 | # Note esz != 0 for FABS and FNEG. | |
283 | CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn | |
284 | CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn | |
285 | CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn | |
286 | CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn | |
287 | NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn | |
288 | FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn | |
289 | FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn | |
290 | ||
291 | # SVE integer unary operations (predicated) | |
292 | # Note esz > original size for extensions. | |
293 | ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn | |
294 | NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn | |
295 | SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn | |
296 | UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn | |
297 | SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn | |
298 | UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn | |
299 | SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn | |
300 | UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn | |
301 | ||
96a36e4a RH |
302 | ### SVE Integer Multiply-Add Group |
303 | ||
304 | # SVE integer multiply-add writing addend (predicated) | |
305 | MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm | |
306 | MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm | |
307 | ||
308 | # SVE integer multiply-add writing multiplicand (predicated) | |
309 | MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD | |
310 | MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB | |
311 | ||
fea98f9c RH |
312 | ### SVE Integer Arithmetic - Unpredicated Group |
313 | ||
314 | # SVE integer add/subtract vectors (unpredicated) | |
315 | ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm | |
316 | SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm | |
317 | SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm | |
318 | UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm | |
319 | SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm | |
320 | UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm | |
321 | ||
38388f7e RH |
322 | ### SVE Logical - Unpredicated Group |
323 | ||
324 | # SVE bitwise logical operations (unpredicated) | |
325 | AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
326 | ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
327 | EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
328 | BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
d1822297 | 329 | |
9a56c9c3 RH |
330 | ### SVE Index Generation Group |
331 | ||
332 | # SVE index generation (immediate start, immediate increment) | |
333 | INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5 | |
334 | ||
335 | # SVE index generation (immediate start, register increment) | |
336 | INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5 | |
337 | ||
338 | # SVE index generation (register start, immediate increment) | |
339 | INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 | |
340 | ||
341 | # SVE index generation (register start, register increment) | |
342 | INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm | |
343 | ||
96f922cc RH |
344 | ### SVE Stack Allocation Group |
345 | ||
346 | # SVE stack frame adjustment | |
347 | ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 | |
348 | ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 | |
349 | ||
350 | # SVE stack frame size | |
351 | RDVL 00000100 101 11111 01010 imm:s6 rd:5 | |
352 | ||
d9d78dcc RH |
353 | ### SVE Bitwise Shift - Unpredicated Group |
354 | ||
355 | # SVE bitwise shift by immediate (unpredicated) | |
356 | ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \ | |
357 | @rd_rn_tszimm imm=%tszimm16_shr | |
358 | LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \ | |
359 | @rd_rn_tszimm imm=%tszimm16_shr | |
360 | LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \ | |
361 | @rd_rn_tszimm imm=%tszimm16_shl | |
362 | ||
363 | # SVE bitwise shift by wide elements (unpredicated) | |
364 | # Note esz != 3 | |
365 | ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm | |
366 | LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm | |
367 | LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm | |
368 | ||
4b242d9c RH |
369 | ### SVE Compute Vector Address Group |
370 | ||
371 | # SVE vector address generation | |
372 | ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
373 | ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
374 | ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
375 | ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
376 | ||
0762cd42 RH |
377 | ### SVE Integer Misc - Unpredicated Group |
378 | ||
379 | # SVE floating-point exponential accelerator | |
380 | # Note esz != 0 | |
381 | FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn | |
382 | ||
a1f233f2 RH |
383 | # SVE floating-point trig select coefficient |
384 | # Note esz != 0 | |
385 | FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm | |
386 | ||
24e82e68 RH |
387 | ### SVE Element Count Group |
388 | ||
389 | # SVE element count | |
390 | CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1 | |
391 | ||
392 | # SVE inc/dec register by element count | |
393 | INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1 | |
394 | ||
395 | # SVE saturating inc/dec register by element count | |
396 | SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt | |
397 | SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt | |
398 | ||
399 | # SVE inc/dec vector by element count | |
400 | # Note this requires esz != 0. | |
401 | INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1 | |
402 | ||
403 | # SVE saturating inc/dec vector by element count | |
404 | # Note these require esz != 0. | |
405 | SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt | |
516e246a | 406 | |
e1fa1164 RH |
407 | ### SVE Bitwise Immediate Group |
408 | ||
409 | # SVE bitwise logical with immediate (unpredicated) | |
410 | ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm | |
411 | EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm | |
412 | AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm | |
413 | ||
414 | # SVE broadcast bitmask immediate | |
415 | DUPM 00000101 11 0000 dbm:13 rd:5 | |
416 | ||
f25a2361 RH |
417 | ### SVE Integer Wide Immediate - Predicated Group |
418 | ||
419 | # SVE copy floating-point immediate (predicated) | |
420 | FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4 | |
421 | ||
422 | # SVE copy integer immediate (predicated) | |
423 | CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s | |
424 | CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s | |
425 | ||
b94f8f60 RH |
426 | ### SVE Permute - Extract Group |
427 | ||
428 | # SVE extract vector (immediate offset) | |
429 | EXT 00000101 001 ..... 000 ... rm:5 rd:5 \ | |
430 | &rrri rn=%reg_movprfx imm=%imm8_16_10 | |
431 | ||
30562ab7 RH |
432 | ### SVE Permute - Unpredicated Group |
433 | ||
434 | # SVE broadcast general register | |
435 | DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn | |
436 | ||
437 | # SVE broadcast indexed element | |
438 | DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \ | |
439 | &rri imm=%imm7_22_16 | |
440 | ||
441 | # SVE insert SIMD&FP scalar register | |
442 | INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm | |
443 | ||
444 | # SVE insert general register | |
445 | INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm | |
446 | ||
447 | # SVE reverse vector elements | |
448 | REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn | |
449 | ||
450 | # SVE vector table lookup | |
451 | TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm | |
452 | ||
453 | # SVE unpack vector elements | |
454 | UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5 | |
455 | ||
d731d8cb RH |
456 | ### SVE Permute - Predicates Group |
457 | ||
458 | # SVE permute predicate elements | |
459 | ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm | |
460 | ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm | |
461 | UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm | |
462 | UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm | |
463 | TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm | |
464 | TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm | |
465 | ||
466 | # SVE reverse predicate elements | |
467 | REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn | |
468 | ||
469 | # SVE unpack predicate elements | |
470 | PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0 | |
471 | PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0 | |
472 | ||
234b48e9 RH |
473 | ### SVE Permute - Interleaving Group |
474 | ||
475 | # SVE permute vector elements | |
476 | ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm | |
477 | ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm | |
478 | UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm | |
479 | UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm | |
480 | TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm | |
481 | TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm | |
482 | ||
3ca879ae RH |
483 | ### SVE Permute - Predicated Group |
484 | ||
485 | # SVE compress active elements | |
486 | # Note esz >= 2 | |
487 | COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn | |
488 | ||
ef23cb72 RH |
489 | # SVE conditionally broadcast element to vector |
490 | CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm | |
491 | CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm | |
492 | ||
493 | # SVE conditionally copy element to SIMD&FP scalar | |
494 | CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn | |
495 | CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn | |
496 | ||
497 | # SVE conditionally copy element to general register | |
498 | CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn | |
499 | CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn | |
500 | ||
501 | # SVE copy element to SIMD&FP scalar register | |
502 | LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn | |
503 | LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn | |
504 | ||
505 | # SVE copy element to general register | |
506 | LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn | |
507 | LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn | |
508 | ||
792a5578 RH |
509 | # SVE copy element from SIMD&FP scalar register |
510 | CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn | |
511 | ||
512 | # SVE copy element from general register to vector (predicated) | |
513 | CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn | |
514 | ||
dae8fb90 RH |
515 | # SVE reverse within elements |
516 | # Note esz >= operation size | |
517 | REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn | |
518 | REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn | |
519 | REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn | |
520 | RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn | |
521 | ||
b48ff240 RH |
522 | # SVE vector splice (predicated) |
523 | SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm | |
524 | ||
d3fe4a29 RH |
525 | ### SVE Select Vectors Group |
526 | ||
527 | # SVE select vector elements (predicated) | |
528 | SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm | |
529 | ||
757f9cff RH |
530 | ### SVE Integer Compare - Vectors Group |
531 | ||
532 | # SVE integer compare_vectors | |
533 | CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm | |
534 | CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm | |
535 | CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm | |
536 | CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm | |
537 | CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm | |
538 | CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm | |
539 | ||
540 | # SVE integer compare with wide elements | |
541 | # Note these require esz != 3. | |
542 | CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm | |
543 | CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm | |
544 | CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm | |
545 | CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm | |
546 | CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm | |
547 | CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm | |
548 | CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm | |
549 | CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm | |
550 | CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm | |
551 | CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm | |
552 | ||
38cadeba RH |
553 | ### SVE Integer Compare - Unsigned Immediate Group |
554 | ||
555 | # SVE integer compare with unsigned immediate | |
556 | CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7 | |
557 | CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7 | |
558 | CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7 | |
559 | CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7 | |
560 | ||
561 | ### SVE Integer Compare - Signed Immediate Group | |
562 | ||
563 | # SVE integer compare with signed immediate | |
564 | CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5 | |
565 | CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5 | |
566 | CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5 | |
567 | CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5 | |
568 | CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5 | |
569 | CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5 | |
570 | ||
e1fa1164 RH |
571 | ### SVE Predicate Logical Operations Group |
572 | ||
516e246a RH |
573 | # SVE predicate logical operations |
574 | AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
575 | BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
576 | EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s | |
577 | SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s | |
578 | ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
579 | ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
580 | NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s | |
581 | NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s | |
582 | ||
9e18d7a6 RH |
583 | ### SVE Predicate Misc Group |
584 | ||
585 | # SVE predicate test | |
586 | PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000 | |
587 | ||
028e2a7b RH |
588 | # SVE predicate initialize |
589 | PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4 | |
590 | ||
591 | # SVE initialize FFR | |
592 | SETFFR 00100101 0010 1100 1001 0000 0000 0000 | |
593 | ||
594 | # SVE zero predicate register | |
595 | PFALSE 00100101 0001 1000 1110 0100 0000 rd:4 | |
596 | ||
597 | # SVE predicate read from FFR (predicated) | |
598 | RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4 | |
599 | ||
600 | # SVE predicate read from FFR (unpredicated) | |
601 | RDFFR 00100101 0001 1001 1111 0000 0000 rd:4 | |
602 | ||
603 | # SVE FFR write from predicate (WRFFR) | |
604 | WRFFR 00100101 0010 1000 1001 000 rn:4 00000 | |
605 | ||
606 | # SVE predicate first active | |
607 | PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0 | |
608 | ||
609 | # SVE predicate next active | |
610 | PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn | |
611 | ||
35da316f RH |
612 | ### SVE Partition Break Group |
613 | ||
614 | # SVE propagate break from previous partition | |
615 | BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
616 | BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
617 | ||
618 | # SVE partition break condition | |
619 | BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s | |
620 | BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s | |
621 | BRKA_m 00100101 0. 01000001 .... 0 .... 1 .... @pd_pg_pn_s | |
622 | BRKB_m 00100101 1. 01000001 .... 0 .... 1 .... @pd_pg_pn_s | |
623 | ||
624 | # SVE propagate break to next partition | |
625 | BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s | |
626 | ||
9ee3a611 RH |
627 | ### SVE Predicate Count Group |
628 | ||
629 | # SVE predicate count | |
630 | CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn | |
631 | ||
632 | # SVE inc/dec register by predicate count | |
633 | INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1 | |
634 | ||
635 | # SVE inc/dec vector by predicate count | |
636 | INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1 | |
637 | ||
638 | # SVE saturating inc/dec register by predicate count | |
639 | SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred | |
640 | SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred | |
641 | ||
642 | # SVE saturating inc/dec vector by predicate count | |
643 | SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred | |
644 | ||
caf1cefc RH |
645 | ### SVE Integer Compare - Scalars Group |
646 | ||
647 | # SVE conditionally terminate scalars | |
648 | CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000 | |
649 | ||
650 | # SVE integer compare scalar count and limit | |
651 | WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4 | |
652 | ||
ed491961 RH |
653 | ### SVE Integer Wide Immediate - Unpredicated Group |
654 | ||
655 | # SVE broadcast floating-point immediate (unpredicated) | |
656 | FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5 | |
657 | ||
658 | # SVE broadcast integer immediate (unpredicated) | |
659 | DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s | |
660 | ||
6e6a157d RH |
661 | # SVE integer add/subtract immediate (unpredicated) |
662 | ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u | |
663 | SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u | |
664 | SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u | |
665 | SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u | |
666 | UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u | |
667 | SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u | |
668 | UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u | |
669 | ||
670 | # SVE integer min/max immediate (unpredicated) | |
671 | SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s | |
672 | UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u | |
673 | SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s | |
674 | UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u | |
675 | ||
676 | # SVE integer multiply immediate (unpredicated) | |
677 | MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s | |
678 | ||
7f9ddf64 RH |
679 | ### SVE FP Accumulating Reduction Group |
680 | ||
681 | # SVE floating-point serial reduction (predicated) | |
682 | FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm | |
683 | ||
29b80469 RH |
684 | ### SVE Floating Point Arithmetic - Unpredicated Group |
685 | ||
686 | # SVE floating-point arithmetic (unpredicated) | |
687 | FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm | |
688 | FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm | |
689 | FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm | |
690 | FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm | |
691 | FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm | |
692 | FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm | |
693 | ||
ec3b87c2 RH |
694 | ### SVE FP Arithmetic Predicated Group |
695 | ||
696 | # SVE floating-point arithmetic (predicated) | |
697 | FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm | |
698 | FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm | |
699 | FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm | |
700 | FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR | |
701 | FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm | |
702 | FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm | |
703 | FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm | |
704 | FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm | |
705 | FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm | |
706 | FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm | |
707 | FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm | |
708 | FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR | |
709 | FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm | |
710 | ||
6ceabaad RH |
711 | ### SVE FP Multiply-Add Group |
712 | ||
713 | # SVE floating-point multiply-accumulate writing addend | |
714 | FMLA_zpzzz 01100101 .. 1 ..... 000 ... ..... ..... @rda_pg_rn_rm | |
715 | FMLS_zpzzz 01100101 .. 1 ..... 001 ... ..... ..... @rda_pg_rn_rm | |
716 | FNMLA_zpzzz 01100101 .. 1 ..... 010 ... ..... ..... @rda_pg_rn_rm | |
717 | FNMLS_zpzzz 01100101 .. 1 ..... 011 ... ..... ..... @rda_pg_rn_rm | |
718 | ||
719 | # SVE floating-point multiply-accumulate writing multiplicand | |
720 | # Alter the operand extraction order and reuse the helpers from above. | |
721 | # FMAD, FMSB, FNMAD, FNMS | |
722 | FMLA_zpzzz 01100101 .. 1 ..... 100 ... ..... ..... @rdn_pg_rm_ra | |
723 | FMLS_zpzzz 01100101 .. 1 ..... 101 ... ..... ..... @rdn_pg_rm_ra | |
724 | FNMLA_zpzzz 01100101 .. 1 ..... 110 ... ..... ..... @rdn_pg_rm_ra | |
725 | FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ..... @rdn_pg_rm_ra | |
726 | ||
8092c6a3 RH |
727 | ### SVE FP Unary Operations Predicated Group |
728 | ||
729 | # SVE integer convert to floating-point | |
730 | SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0 | |
731 | SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
732 | SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 | |
733 | SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
734 | SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0 | |
735 | SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
736 | SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 | |
737 | ||
738 | UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0 | |
739 | UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
740 | UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 | |
741 | UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
742 | UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0 | |
743 | UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
744 | UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 | |
745 | ||
d1822297 RH |
746 | ### SVE Memory - 32-bit Gather and Unsized Contiguous Group |
747 | ||
748 | # SVE load predicate register | |
749 | LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9 | |
750 | ||
751 | # SVE load vector register | |
752 | LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9 | |
c4e7c493 RH |
753 | |
754 | ### SVE Memory Contiguous Load Group | |
755 | ||
756 | # SVE contiguous load (scalar plus scalar) | |
757 | LD_zprr 1010010 .... ..... 010 ... ..... ..... @rprr_load_dt nreg=0 | |
758 | ||
e2654d75 RH |
759 | # SVE contiguous first-fault load (scalar plus scalar) |
760 | LDFF1_zprr 1010010 .... ..... 011 ... ..... ..... @rprr_load_dt nreg=0 | |
761 | ||
c4e7c493 RH |
762 | # SVE contiguous load (scalar plus immediate) |
763 | LD_zpri 1010010 .... 0.... 101 ... ..... ..... @rpri_load_dt nreg=0 | |
764 | ||
e2654d75 RH |
765 | # SVE contiguous non-fault load (scalar plus immediate) |
766 | LDNF1_zpri 1010010 .... 1.... 101 ... ..... ..... @rpri_load_dt nreg=0 | |
767 | ||
c4e7c493 RH |
768 | # SVE contiguous non-temporal load (scalar plus scalar) |
769 | # LDNT1B, LDNT1H, LDNT1W, LDNT1D | |
770 | # SVE load multiple structures (scalar plus scalar) | |
771 | # LD2B, LD2H, LD2W, LD2D; etc. | |
772 | LD_zprr 1010010 .. nreg:2 ..... 110 ... ..... ..... @rprr_load_msz | |
773 | ||
774 | # SVE contiguous non-temporal load (scalar plus immediate) | |
775 | # LDNT1B, LDNT1H, LDNT1W, LDNT1D | |
776 | # SVE load multiple structures (scalar plus immediate) | |
777 | # LD2B, LD2H, LD2W, LD2D; etc. | |
778 | LD_zpri 1010010 .. nreg:2 0.... 111 ... ..... ..... @rpri_load_msz | |
1a039c7e | 779 | |
05abe304 RH |
780 | # SVE load and broadcast quadword (scalar plus scalar) |
781 | LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \ | |
782 | @rprr_load_msz nreg=0 | |
783 | ||
784 | # SVE load and broadcast quadword (scalar plus immediate) | |
785 | # LD1RQB, LD1RQH, LD1RQS, LD1RQD | |
786 | LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \ | |
787 | @rpri_load_msz nreg=0 | |
788 | ||
1a039c7e RH |
789 | ### SVE Memory Store Group |
790 | ||
791 | # SVE contiguous store (scalar plus immediate) | |
792 | # ST1B, ST1H, ST1W, ST1D; require msz <= esz | |
793 | ST_zpri 1110010 .. esz:2 0.... 111 ... ..... ..... \ | |
794 | @rpri_store_msz nreg=0 | |
795 | ||
796 | # SVE contiguous store (scalar plus scalar) | |
797 | # ST1B, ST1H, ST1W, ST1D; require msz <= esz | |
798 | # Enumerate msz lest we conflict with STR_zri. | |
799 | ST_zprr 1110010 00 .. ..... 010 ... ..... ..... \ | |
800 | @rprr_store_esz_n0 msz=0 | |
801 | ST_zprr 1110010 01 .. ..... 010 ... ..... ..... \ | |
802 | @rprr_store_esz_n0 msz=1 | |
803 | ST_zprr 1110010 10 .. ..... 010 ... ..... ..... \ | |
804 | @rprr_store_esz_n0 msz=2 | |
805 | ST_zprr 1110010 11 11 ..... 010 ... ..... ..... \ | |
806 | @rprr_store msz=3 esz=3 nreg=0 | |
807 | ||
808 | # SVE contiguous non-temporal store (scalar plus immediate) (nreg == 0) | |
809 | # SVE store multiple structures (scalar plus immediate) (nreg != 0) | |
810 | ST_zpri 1110010 .. nreg:2 1.... 111 ... ..... ..... \ | |
811 | @rpri_store_msz esz=%size_23 | |
812 | ||
813 | # SVE contiguous non-temporal store (scalar plus scalar) (nreg == 0) | |
814 | # SVE store multiple structures (scalar plus scalar) (nreg != 0) | |
815 | ST_zprr 1110010 msz:2 nreg:2 ..... 011 ... ..... ..... \ | |
816 | @rprr_store esz=%size_23 |