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38388f7e RH |
1 | # AArch64 SVE instruction descriptions |
2 | # | |
3 | # Copyright (c) 2017 Linaro, Ltd | |
4 | # | |
5 | # This library is free software; you can redistribute it and/or | |
6 | # modify it under the terms of the GNU Lesser General Public | |
7 | # License as published by the Free Software Foundation; either | |
8 | # version 2 of the License, or (at your option) any later version. | |
9 | # | |
10 | # This library is distributed in the hope that it will be useful, | |
11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | # Lesser General Public License for more details. | |
14 | # | |
15 | # You should have received a copy of the GNU Lesser General Public | |
16 | # License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
17 | ||
18 | # | |
19 | # This file is processed by scripts/decodetree.py | |
20 | # | |
21 | ||
d1822297 RH |
22 | ########################################################################### |
23 | # Named fields. These are primarily for disjoint fields. | |
24 | ||
f25a2361 | 25 | %imm4_16_p1 16:4 !function=plus1 |
ccd841c3 | 26 | %imm6_22_5 22:1 5:5 |
30562ab7 | 27 | %imm7_22_16 22:2 16:5 |
b94f8f60 | 28 | %imm8_16_10 16:5 10:3 |
d1822297 RH |
29 | %imm9_16_10 16:s6 10:3 |
30 | ||
ccd841c3 RH |
31 | # A combination of tsz:imm3 -- extract esize. |
32 | %tszimm_esz 22:2 5:5 !function=tszimm_esz | |
33 | # A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3) | |
34 | %tszimm_shr 22:2 5:5 !function=tszimm_shr | |
35 | # A combination of tsz:imm3 -- extract (tsz:imm3) - esize | |
36 | %tszimm_shl 22:2 5:5 !function=tszimm_shl | |
37 | ||
d9d78dcc RH |
38 | # Similarly for the tszh/tszl pair at 22/16 for zzi |
39 | %tszimm16_esz 22:2 16:5 !function=tszimm_esz | |
40 | %tszimm16_shr 22:2 16:5 !function=tszimm_shr | |
41 | %tszimm16_shl 22:2 16:5 !function=tszimm_shl | |
42 | ||
f25a2361 RH |
43 | # Signed 8-bit immediate, optionally shifted left by 8. |
44 | %sh8_i8s 5:9 !function=expand_imm_sh8s | |
45 | ||
f97cfd59 RH |
46 | # Either a copy of rd (at bit 0), or a different source |
47 | # as propagated via the MOVPRFX instruction. | |
48 | %reg_movprfx 0:5 | |
49 | ||
38388f7e RH |
50 | ########################################################################### |
51 | # Named attribute sets. These are used to make nice(er) names | |
52 | # when creating helpers common to those for the individual | |
53 | # instruction patterns. | |
54 | ||
028e2a7b | 55 | &rr_esz rd rn esz |
d1822297 | 56 | &rri rd rn imm |
e1fa1164 | 57 | &rr_dbm rd rn dbm |
4b242d9c | 58 | &rrri rd rn rm imm |
d9d78dcc | 59 | &rri_esz rd rn imm esz |
38388f7e | 60 | &rrr_esz rd rn rm esz |
047cec97 | 61 | &rpr_esz rd pg rn esz |
35da316f | 62 | &rpr_s rd pg rn s |
516e246a | 63 | &rprr_s rd pg rn rm s |
f97cfd59 | 64 | &rprr_esz rd pg rn rm esz |
96a36e4a | 65 | &rprrr_esz rd pg rn rm ra esz |
ccd841c3 | 66 | &rpri_esz rd pg rn imm esz |
24e82e68 RH |
67 | &ptrue rd esz pat s |
68 | &incdec_cnt rd pat esz imm d u | |
69 | &incdec2_cnt rd rn pat esz imm d u | |
9ee3a611 RH |
70 | &incdec_pred rd pg esz d u |
71 | &incdec2_pred rd rn pg esz d u | |
38388f7e RH |
72 | |
73 | ########################################################################### | |
74 | # Named instruction formats. These are generally used to | |
75 | # reduce the amount of duplication between instruction patterns. | |
76 | ||
028e2a7b RH |
77 | # Two operand with unused vector element size |
78 | @pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0 | |
79 | ||
80 | # Two operand | |
81 | @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz | |
0762cd42 | 82 | @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz |
028e2a7b | 83 | |
35da316f RH |
84 | # Two operand with governing predicate, flags setting |
85 | @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s | |
86 | ||
38388f7e RH |
87 | # Three operand with unused vector element size |
88 | @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 | |
89 | ||
516e246a RH |
90 | # Three predicate operand, with governing predicate, flag setting |
91 | @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s | |
92 | ||
fea98f9c RH |
93 | # Three operand, vector element size |
94 | @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz | |
d731d8cb | 95 | @pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz |
30562ab7 RH |
96 | @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \ |
97 | &rrr_esz rn=%reg_movprfx | |
fea98f9c | 98 | |
4b242d9c RH |
99 | # Three operand with "memory" size, aka immediate left shift |
100 | @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri | |
101 | ||
f97cfd59 RH |
102 | # Two register operand, with governing predicate, vector element size |
103 | @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \ | |
104 | &rprr_esz rn=%reg_movprfx | |
105 | @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ | |
106 | &rprr_esz rm=%reg_movprfx | |
d3fe4a29 | 107 | @rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz |
757f9cff | 108 | @pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz |
f97cfd59 | 109 | |
96a36e4a RH |
110 | # Three register operand, with governing predicate, vector element size |
111 | @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ | |
112 | &rprrr_esz ra=%reg_movprfx | |
113 | @rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \ | |
114 | &rprrr_esz rn=%reg_movprfx | |
115 | ||
047cec97 RH |
116 | # One register operand, with governing predicate, vector element size |
117 | @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz | |
9ee3a611 | 118 | @rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz |
047cec97 | 119 | |
96f922cc RH |
120 | # Two register operands with a 6-bit signed immediate. |
121 | @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri | |
122 | ||
ccd841c3 RH |
123 | # Two register operand, one immediate operand, with predicate, |
124 | # element size encoded as TSZHL. User must fill in imm. | |
125 | @rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \ | |
126 | &rpri_esz rn=%reg_movprfx esz=%tszimm_esz | |
127 | ||
d9d78dcc RH |
128 | # Similarly without predicate. |
129 | @rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \ | |
130 | &rri_esz esz=%tszimm16_esz | |
131 | ||
f25a2361 RH |
132 | # Two register operand, one immediate operand, with 4-bit predicate. |
133 | # User must fill in imm. | |
134 | @rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \ | |
135 | &rpri_esz rn=%reg_movprfx | |
136 | ||
e1fa1164 RH |
137 | # Two register operand, one encoded bitmask. |
138 | @rdn_dbm ........ .. .... dbm:13 rd:5 \ | |
139 | &rr_dbm rn=%reg_movprfx | |
140 | ||
38cadeba RH |
141 | # Predicate output, vector and immediate input, |
142 | # controlling predicate, element size. | |
143 | @pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz | |
144 | @pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz | |
145 | ||
d1822297 RH |
146 | # Basic Load/Store with 9-bit immediate offset |
147 | @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ | |
148 | &rri imm=%imm9_16_10 | |
149 | @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \ | |
150 | &rri imm=%imm9_16_10 | |
151 | ||
24e82e68 RH |
152 | # One register, pattern, and uint4+1. |
153 | # User must fill in U and D. | |
154 | @incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ | |
155 | &incdec_cnt imm=%imm4_16_p1 | |
156 | @incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ | |
157 | &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx | |
158 | ||
9ee3a611 RH |
159 | # One register, predicate. |
160 | # User must fill in U and D. | |
161 | @incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred | |
162 | @incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \ | |
163 | &incdec2_pred rn=%reg_movprfx | |
164 | ||
38388f7e RH |
165 | ########################################################################### |
166 | # Instruction patterns. Grouped according to the SVE encodingindex.xhtml. | |
167 | ||
f97cfd59 RH |
168 | ### SVE Integer Arithmetic - Binary Predicated Group |
169 | ||
170 | # SVE bitwise logical vector operations (predicated) | |
171 | ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm | |
172 | EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm | |
173 | AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm | |
174 | BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm | |
175 | ||
176 | # SVE integer add/subtract vectors (predicated) | |
177 | ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm | |
178 | SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm | |
179 | SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR | |
180 | ||
181 | # SVE integer min/max/difference (predicated) | |
182 | SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm | |
183 | UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm | |
184 | SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm | |
185 | UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm | |
186 | SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm | |
187 | UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm | |
188 | ||
189 | # SVE integer multiply/divide (predicated) | |
190 | MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm | |
191 | SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm | |
192 | UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm | |
193 | # Note that divide requires size >= 2; below 2 is unallocated. | |
194 | SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm | |
195 | UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm | |
196 | SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR | |
197 | UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR | |
198 | ||
047cec97 RH |
199 | ### SVE Integer Reduction Group |
200 | ||
201 | # SVE bitwise logical reduction (predicated) | |
202 | ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn | |
203 | EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn | |
204 | ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn | |
205 | ||
206 | # SVE integer add reduction (predicated) | |
207 | # Note that saddv requires size != 3. | |
208 | UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn | |
209 | SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn | |
210 | ||
211 | # SVE integer min/max reduction (predicated) | |
212 | SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn | |
213 | UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn | |
214 | SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn | |
215 | UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn | |
216 | ||
ccd841c3 RH |
217 | ### SVE Shift by Immediate - Predicated Group |
218 | ||
219 | # SVE bitwise shift by immediate (predicated) | |
220 | ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \ | |
221 | @rdn_pg_tszimm imm=%tszimm_shr | |
222 | LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \ | |
223 | @rdn_pg_tszimm imm=%tszimm_shr | |
224 | LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \ | |
225 | @rdn_pg_tszimm imm=%tszimm_shl | |
226 | ASRD 00000100 .. 000 100 100 ... .. ... ..... \ | |
227 | @rdn_pg_tszimm imm=%tszimm_shr | |
228 | ||
27721dbb RH |
229 | # SVE bitwise shift by vector (predicated) |
230 | ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm | |
231 | LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm | |
232 | LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm | |
233 | ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR | |
234 | LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR | |
235 | LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR | |
236 | ||
fe7f8dfb RH |
237 | # SVE bitwise shift by wide elements (predicated) |
238 | # Note these require size != 3. | |
239 | ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm | |
240 | LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm | |
241 | LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm | |
242 | ||
afac6d04 RH |
243 | ### SVE Integer Arithmetic - Unary Predicated Group |
244 | ||
245 | # SVE unary bit operations (predicated) | |
246 | # Note esz != 0 for FABS and FNEG. | |
247 | CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn | |
248 | CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn | |
249 | CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn | |
250 | CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn | |
251 | NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn | |
252 | FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn | |
253 | FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn | |
254 | ||
255 | # SVE integer unary operations (predicated) | |
256 | # Note esz > original size for extensions. | |
257 | ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn | |
258 | NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn | |
259 | SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn | |
260 | UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn | |
261 | SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn | |
262 | UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn | |
263 | SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn | |
264 | UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn | |
265 | ||
96a36e4a RH |
266 | ### SVE Integer Multiply-Add Group |
267 | ||
268 | # SVE integer multiply-add writing addend (predicated) | |
269 | MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm | |
270 | MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm | |
271 | ||
272 | # SVE integer multiply-add writing multiplicand (predicated) | |
273 | MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD | |
274 | MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB | |
275 | ||
fea98f9c RH |
276 | ### SVE Integer Arithmetic - Unpredicated Group |
277 | ||
278 | # SVE integer add/subtract vectors (unpredicated) | |
279 | ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm | |
280 | SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm | |
281 | SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm | |
282 | UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm | |
283 | SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm | |
284 | UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm | |
285 | ||
38388f7e RH |
286 | ### SVE Logical - Unpredicated Group |
287 | ||
288 | # SVE bitwise logical operations (unpredicated) | |
289 | AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
290 | ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
291 | EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
292 | BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
d1822297 | 293 | |
9a56c9c3 RH |
294 | ### SVE Index Generation Group |
295 | ||
296 | # SVE index generation (immediate start, immediate increment) | |
297 | INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5 | |
298 | ||
299 | # SVE index generation (immediate start, register increment) | |
300 | INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5 | |
301 | ||
302 | # SVE index generation (register start, immediate increment) | |
303 | INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 | |
304 | ||
305 | # SVE index generation (register start, register increment) | |
306 | INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm | |
307 | ||
96f922cc RH |
308 | ### SVE Stack Allocation Group |
309 | ||
310 | # SVE stack frame adjustment | |
311 | ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 | |
312 | ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 | |
313 | ||
314 | # SVE stack frame size | |
315 | RDVL 00000100 101 11111 01010 imm:s6 rd:5 | |
316 | ||
d9d78dcc RH |
317 | ### SVE Bitwise Shift - Unpredicated Group |
318 | ||
319 | # SVE bitwise shift by immediate (unpredicated) | |
320 | ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \ | |
321 | @rd_rn_tszimm imm=%tszimm16_shr | |
322 | LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \ | |
323 | @rd_rn_tszimm imm=%tszimm16_shr | |
324 | LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \ | |
325 | @rd_rn_tszimm imm=%tszimm16_shl | |
326 | ||
327 | # SVE bitwise shift by wide elements (unpredicated) | |
328 | # Note esz != 3 | |
329 | ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm | |
330 | LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm | |
331 | LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm | |
332 | ||
4b242d9c RH |
333 | ### SVE Compute Vector Address Group |
334 | ||
335 | # SVE vector address generation | |
336 | ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
337 | ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
338 | ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
339 | ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
340 | ||
0762cd42 RH |
341 | ### SVE Integer Misc - Unpredicated Group |
342 | ||
343 | # SVE floating-point exponential accelerator | |
344 | # Note esz != 0 | |
345 | FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn | |
346 | ||
a1f233f2 RH |
347 | # SVE floating-point trig select coefficient |
348 | # Note esz != 0 | |
349 | FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm | |
350 | ||
24e82e68 RH |
351 | ### SVE Element Count Group |
352 | ||
353 | # SVE element count | |
354 | CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1 | |
355 | ||
356 | # SVE inc/dec register by element count | |
357 | INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1 | |
358 | ||
359 | # SVE saturating inc/dec register by element count | |
360 | SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt | |
361 | SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt | |
362 | ||
363 | # SVE inc/dec vector by element count | |
364 | # Note this requires esz != 0. | |
365 | INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1 | |
366 | ||
367 | # SVE saturating inc/dec vector by element count | |
368 | # Note these require esz != 0. | |
369 | SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt | |
516e246a | 370 | |
e1fa1164 RH |
371 | ### SVE Bitwise Immediate Group |
372 | ||
373 | # SVE bitwise logical with immediate (unpredicated) | |
374 | ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm | |
375 | EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm | |
376 | AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm | |
377 | ||
378 | # SVE broadcast bitmask immediate | |
379 | DUPM 00000101 11 0000 dbm:13 rd:5 | |
380 | ||
f25a2361 RH |
381 | ### SVE Integer Wide Immediate - Predicated Group |
382 | ||
383 | # SVE copy floating-point immediate (predicated) | |
384 | FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4 | |
385 | ||
386 | # SVE copy integer immediate (predicated) | |
387 | CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s | |
388 | CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s | |
389 | ||
b94f8f60 RH |
390 | ### SVE Permute - Extract Group |
391 | ||
392 | # SVE extract vector (immediate offset) | |
393 | EXT 00000101 001 ..... 000 ... rm:5 rd:5 \ | |
394 | &rrri rn=%reg_movprfx imm=%imm8_16_10 | |
395 | ||
30562ab7 RH |
396 | ### SVE Permute - Unpredicated Group |
397 | ||
398 | # SVE broadcast general register | |
399 | DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn | |
400 | ||
401 | # SVE broadcast indexed element | |
402 | DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \ | |
403 | &rri imm=%imm7_22_16 | |
404 | ||
405 | # SVE insert SIMD&FP scalar register | |
406 | INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm | |
407 | ||
408 | # SVE insert general register | |
409 | INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm | |
410 | ||
411 | # SVE reverse vector elements | |
412 | REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn | |
413 | ||
414 | # SVE vector table lookup | |
415 | TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm | |
416 | ||
417 | # SVE unpack vector elements | |
418 | UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5 | |
419 | ||
d731d8cb RH |
420 | ### SVE Permute - Predicates Group |
421 | ||
422 | # SVE permute predicate elements | |
423 | ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm | |
424 | ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm | |
425 | UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm | |
426 | UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm | |
427 | TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm | |
428 | TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm | |
429 | ||
430 | # SVE reverse predicate elements | |
431 | REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn | |
432 | ||
433 | # SVE unpack predicate elements | |
434 | PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0 | |
435 | PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0 | |
436 | ||
234b48e9 RH |
437 | ### SVE Permute - Interleaving Group |
438 | ||
439 | # SVE permute vector elements | |
440 | ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm | |
441 | ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm | |
442 | UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm | |
443 | UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm | |
444 | TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm | |
445 | TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm | |
446 | ||
3ca879ae RH |
447 | ### SVE Permute - Predicated Group |
448 | ||
449 | # SVE compress active elements | |
450 | # Note esz >= 2 | |
451 | COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn | |
452 | ||
ef23cb72 RH |
453 | # SVE conditionally broadcast element to vector |
454 | CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm | |
455 | CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm | |
456 | ||
457 | # SVE conditionally copy element to SIMD&FP scalar | |
458 | CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn | |
459 | CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn | |
460 | ||
461 | # SVE conditionally copy element to general register | |
462 | CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn | |
463 | CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn | |
464 | ||
465 | # SVE copy element to SIMD&FP scalar register | |
466 | LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn | |
467 | LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn | |
468 | ||
469 | # SVE copy element to general register | |
470 | LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn | |
471 | LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn | |
472 | ||
792a5578 RH |
473 | # SVE copy element from SIMD&FP scalar register |
474 | CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn | |
475 | ||
476 | # SVE copy element from general register to vector (predicated) | |
477 | CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn | |
478 | ||
dae8fb90 RH |
479 | # SVE reverse within elements |
480 | # Note esz >= operation size | |
481 | REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn | |
482 | REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn | |
483 | REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn | |
484 | RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn | |
485 | ||
b48ff240 RH |
486 | # SVE vector splice (predicated) |
487 | SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm | |
488 | ||
d3fe4a29 RH |
489 | ### SVE Select Vectors Group |
490 | ||
491 | # SVE select vector elements (predicated) | |
492 | SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm | |
493 | ||
757f9cff RH |
494 | ### SVE Integer Compare - Vectors Group |
495 | ||
496 | # SVE integer compare_vectors | |
497 | CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm | |
498 | CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm | |
499 | CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm | |
500 | CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm | |
501 | CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm | |
502 | CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm | |
503 | ||
504 | # SVE integer compare with wide elements | |
505 | # Note these require esz != 3. | |
506 | CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm | |
507 | CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm | |
508 | CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm | |
509 | CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm | |
510 | CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm | |
511 | CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm | |
512 | CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm | |
513 | CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm | |
514 | CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm | |
515 | CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm | |
516 | ||
38cadeba RH |
517 | ### SVE Integer Compare - Unsigned Immediate Group |
518 | ||
519 | # SVE integer compare with unsigned immediate | |
520 | CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7 | |
521 | CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7 | |
522 | CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7 | |
523 | CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7 | |
524 | ||
525 | ### SVE Integer Compare - Signed Immediate Group | |
526 | ||
527 | # SVE integer compare with signed immediate | |
528 | CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5 | |
529 | CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5 | |
530 | CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5 | |
531 | CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5 | |
532 | CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5 | |
533 | CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5 | |
534 | ||
e1fa1164 RH |
535 | ### SVE Predicate Logical Operations Group |
536 | ||
516e246a RH |
537 | # SVE predicate logical operations |
538 | AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
539 | BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
540 | EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s | |
541 | SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s | |
542 | ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
543 | ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
544 | NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s | |
545 | NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s | |
546 | ||
9e18d7a6 RH |
547 | ### SVE Predicate Misc Group |
548 | ||
549 | # SVE predicate test | |
550 | PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000 | |
551 | ||
028e2a7b RH |
552 | # SVE predicate initialize |
553 | PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4 | |
554 | ||
555 | # SVE initialize FFR | |
556 | SETFFR 00100101 0010 1100 1001 0000 0000 0000 | |
557 | ||
558 | # SVE zero predicate register | |
559 | PFALSE 00100101 0001 1000 1110 0100 0000 rd:4 | |
560 | ||
561 | # SVE predicate read from FFR (predicated) | |
562 | RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4 | |
563 | ||
564 | # SVE predicate read from FFR (unpredicated) | |
565 | RDFFR 00100101 0001 1001 1111 0000 0000 rd:4 | |
566 | ||
567 | # SVE FFR write from predicate (WRFFR) | |
568 | WRFFR 00100101 0010 1000 1001 000 rn:4 00000 | |
569 | ||
570 | # SVE predicate first active | |
571 | PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0 | |
572 | ||
573 | # SVE predicate next active | |
574 | PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn | |
575 | ||
35da316f RH |
576 | ### SVE Partition Break Group |
577 | ||
578 | # SVE propagate break from previous partition | |
579 | BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
580 | BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
581 | ||
582 | # SVE partition break condition | |
583 | BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s | |
584 | BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s | |
585 | BRKA_m 00100101 0. 01000001 .... 0 .... 1 .... @pd_pg_pn_s | |
586 | BRKB_m 00100101 1. 01000001 .... 0 .... 1 .... @pd_pg_pn_s | |
587 | ||
588 | # SVE propagate break to next partition | |
589 | BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s | |
590 | ||
9ee3a611 RH |
591 | ### SVE Predicate Count Group |
592 | ||
593 | # SVE predicate count | |
594 | CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn | |
595 | ||
596 | # SVE inc/dec register by predicate count | |
597 | INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1 | |
598 | ||
599 | # SVE inc/dec vector by predicate count | |
600 | INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1 | |
601 | ||
602 | # SVE saturating inc/dec register by predicate count | |
603 | SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred | |
604 | SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred | |
605 | ||
606 | # SVE saturating inc/dec vector by predicate count | |
607 | SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred | |
608 | ||
caf1cefc RH |
609 | ### SVE Integer Compare - Scalars Group |
610 | ||
611 | # SVE conditionally terminate scalars | |
612 | CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000 | |
613 | ||
614 | # SVE integer compare scalar count and limit | |
615 | WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4 | |
616 | ||
d1822297 RH |
617 | ### SVE Memory - 32-bit Gather and Unsized Contiguous Group |
618 | ||
619 | # SVE load predicate register | |
620 | LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9 | |
621 | ||
622 | # SVE load vector register | |
623 | LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9 |