projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 38388f7e RH |
1 | # AArch64 SVE instruction descriptions |
| 2 | # | |
| 3 | # Copyright (c) 2017 Linaro, Ltd | |
| 4 | # | |
| 5 | # This library is free software; you can redistribute it and/or | |
| 6 | # modify it under the terms of the GNU Lesser General Public | |
| 7 | # License as published by the Free Software Foundation; either | |
| 50f57e09 | 8 | # version 2.1 of the License, or (at your option) any later version. |
| 38388f7e RH |
9 | # |
| 10 | # This library is distributed in the hope that it will be useful, | |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 13 | # Lesser General Public License for more details. | |
| 14 | # | |
| 15 | # You should have received a copy of the GNU Lesser General Public | |
| 16 | # License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
| 17 | ||
| 18 | # | |
| 19 | # This file is processed by scripts/decodetree.py | |
| 20 | # | |
| 21 | ||
| d1822297 RH |
22 | ########################################################################### |
| 23 | # Named fields. These are primarily for disjoint fields. | |
| 24 | ||
| f25a2361 | 25 | %imm4_16_p1 16:4 !function=plus1 |
| ccd841c3 | 26 | %imm6_22_5 22:1 5:5 |
| 30562ab7 | 27 | %imm7_22_16 22:2 16:5 |
| b94f8f60 | 28 | %imm8_16_10 16:5 10:3 |
| d1822297 | 29 | %imm9_16_10 16:s6 10:3 |
| 1a039c7e | 30 | %size_23 23:2 |
| 68459864 | 31 | %dtype_23_13 23:2 13:2 |
| ca40a6e6 | 32 | %index3_22_19 22:1 19:2 |
| c5c455d7 RH |
33 | %index3_19_11 19:2 11:1 |
| 34 | %index2_20_11 20:1 11:1 | |
| d1822297 | 35 | |
| ccd841c3 RH |
36 | # A combination of tsz:imm3 -- extract esize. |
| 37 | %tszimm_esz 22:2 5:5 !function=tszimm_esz | |
| 38 | # A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3) | |
| 39 | %tszimm_shr 22:2 5:5 !function=tszimm_shr | |
| 40 | # A combination of tsz:imm3 -- extract (tsz:imm3) - esize | |
| 41 | %tszimm_shl 22:2 5:5 !function=tszimm_shl | |
| 42 | ||
| d9d78dcc RH |
43 | # Similarly for the tszh/tszl pair at 22/16 for zzi |
| 44 | %tszimm16_esz 22:2 16:5 !function=tszimm_esz | |
| 45 | %tszimm16_shr 22:2 16:5 !function=tszimm_shr | |
| 46 | %tszimm16_shl 22:2 16:5 !function=tszimm_shl | |
| 47 | ||
| f25a2361 RH |
48 | # Signed 8-bit immediate, optionally shifted left by 8. |
| 49 | %sh8_i8s 5:9 !function=expand_imm_sh8s | |
| 6e6a157d RH |
50 | # Unsigned 8-bit immediate, optionally shifted left by 8. |
| 51 | %sh8_i8u 5:9 !function=expand_imm_sh8u | |
| f25a2361 | 52 | |
| c4e7c493 RH |
53 | # Unsigned load of msz into esz=2, represented as a dtype. |
| 54 | %msz_dtype 23:2 !function=msz_dtype | |
| 55 | ||
| f97cfd59 RH |
56 | # Either a copy of rd (at bit 0), or a different source |
| 57 | # as propagated via the MOVPRFX instruction. | |
| 58 | %reg_movprfx 0:5 | |
| 59 | ||
| 38388f7e RH |
60 | ########################################################################### |
| 61 | # Named attribute sets. These are used to make nice(er) names | |
| 62 | # when creating helpers common to those for the individual | |
| 63 | # instruction patterns. | |
| 64 | ||
| 028e2a7b | 65 | &rr_esz rd rn esz |
| d1822297 | 66 | &rri rd rn imm |
| e1fa1164 | 67 | &rr_dbm rd rn dbm |
| 4b242d9c | 68 | &rrri rd rn rm imm |
| d9d78dcc | 69 | &rri_esz rd rn imm esz |
| e6eba6e5 | 70 | &rrri_esz rd rn rm imm esz |
| 38388f7e | 71 | &rrr_esz rd rn rm esz |
| 1c737d9c | 72 | &rrx_esz rd rn rm index esz |
| 047cec97 | 73 | &rpr_esz rd pg rn esz |
| 35da316f | 74 | &rpr_s rd pg rn s |
| 516e246a | 75 | &rprr_s rd pg rn rm s |
| f97cfd59 | 76 | &rprr_esz rd pg rn rm esz |
| 38650638 | 77 | &rrrr_esz rd ra rn rm esz |
| 0a82d963 | 78 | &rrxr_esz rd rn rm ra index esz |
| 96a36e4a | 79 | &rprrr_esz rd pg rn rm ra esz |
| ccd841c3 | 80 | &rpri_esz rd pg rn imm esz |
| 24e82e68 RH |
81 | &ptrue rd esz pat s |
| 82 | &incdec_cnt rd pat esz imm d u | |
| 83 | &incdec2_cnt rd rn pat esz imm d u | |
| 9ee3a611 RH |
84 | &incdec_pred rd pg esz d u |
| 85 | &incdec2_pred rd rn pg esz d u | |
| c4e7c493 RH |
86 | &rprr_load rd pg rn rm dtype nreg |
| 87 | &rpri_load rd pg rn imm dtype nreg | |
| 1a039c7e RH |
88 | &rprr_store rd pg rn rm msz esz nreg |
| 89 | &rpri_store rd pg rn imm msz esz nreg | |
| 673e9fa6 RH |
90 | &rprr_gather_load rd pg rn rm esz msz u ff xs scale |
| 91 | &rpri_gather_load rd pg rn imm esz msz u ff | |
| f6dbf62a | 92 | &rprr_scatter_store rd pg rn rm esz msz xs scale |
| 408ecde9 | 93 | &rpri_scatter_store rd pg rn imm esz msz |
| 38388f7e RH |
94 | |
| 95 | ########################################################################### | |
| 96 | # Named instruction formats. These are generally used to | |
| 97 | # reduce the amount of duplication between instruction patterns. | |
| 98 | ||
| 028e2a7b RH |
99 | # Two operand with unused vector element size |
| 100 | @pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0 | |
| 101 | ||
| 102 | # Two operand | |
| 103 | @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz | |
| 0762cd42 | 104 | @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz |
| 028e2a7b | 105 | |
| 35da316f RH |
106 | # Two operand with governing predicate, flags setting |
| 107 | @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s | |
| 407e6ce7 | 108 | @pd_pg_pn_s0 ........ . . ...... .. pg:4 . rn:4 . rd:4 &rpr_s s=0 |
| 35da316f | 109 | |
| 38388f7e RH |
110 | # Three operand with unused vector element size |
| 111 | @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 | |
| 112 | ||
| 516e246a RH |
113 | # Three predicate operand, with governing predicate, flag setting |
| 114 | @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s | |
| 115 | ||
| fea98f9c RH |
116 | # Three operand, vector element size |
| 117 | @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz | |
| d731d8cb | 118 | @pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz |
| 30562ab7 RH |
119 | @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \ |
| 120 | &rrr_esz rn=%reg_movprfx | |
| 6e6a157d RH |
121 | @rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \ |
| 122 | &rri_esz rn=%reg_movprfx imm=%sh8_i8u | |
| 123 | @rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \ | |
| 124 | &rri_esz rn=%reg_movprfx | |
| 125 | @rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \ | |
| 126 | &rri_esz rn=%reg_movprfx | |
| fea98f9c | 127 | |
| 38650638 RH |
128 | # Four operand, vector element size |
| 129 | @rda_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 \ | |
| 130 | &rrrr_esz ra=%reg_movprfx | |
| 131 | ||
| 911cdc6d RH |
132 | # Four operand with unused vector element size |
| 133 | @rdn_ra_rm_e0 ........ ... rm:5 ... ... ra:5 rd:5 \ | |
| 134 | &rrrr_esz esz=0 rn=%reg_movprfx | |
| 135 | ||
| 4b242d9c RH |
136 | # Three operand with "memory" size, aka immediate left shift |
| 137 | @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri | |
| 138 | ||
| f97cfd59 RH |
139 | # Two register operand, with governing predicate, vector element size |
| 140 | @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \ | |
| 141 | &rprr_esz rn=%reg_movprfx | |
| 142 | @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ | |
| 143 | &rprr_esz rm=%reg_movprfx | |
| d3fe4a29 | 144 | @rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz |
| 757f9cff | 145 | @pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz |
| f97cfd59 | 146 | |
| 96a36e4a RH |
147 | # Three register operand, with governing predicate, vector element size |
| 148 | @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ | |
| 149 | &rprrr_esz ra=%reg_movprfx | |
| 150 | @rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \ | |
| 151 | &rprrr_esz rn=%reg_movprfx | |
| 6ceabaad RH |
152 | @rdn_pg_rm_ra ........ esz:2 . ra:5 ... pg:3 rm:5 rd:5 \ |
| 153 | &rprrr_esz rn=%reg_movprfx | |
| 7d47ac94 | 154 | @rd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 &rprr_esz |
| 96a36e4a | 155 | |
| 047cec97 RH |
156 | # One register operand, with governing predicate, vector element size |
| 157 | @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz | |
| 9ee3a611 | 158 | @rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz |
| 4d2e2a03 | 159 | @pd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 . rd:4 &rpr_esz |
| 047cec97 | 160 | |
| 8092c6a3 RH |
161 | # One register operand, with governing predicate, no vector element size |
| 162 | @rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0 | |
| 163 | ||
| 96f922cc RH |
164 | # Two register operands with a 6-bit signed immediate. |
| 165 | @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri | |
| 166 | ||
| ccd841c3 | 167 | # Two register operand, one immediate operand, with predicate, |
| 830d1a5a RH |
168 | # element size encoded as TSZHL. |
| 169 | @rdn_pg_tszimm_shl ........ .. ... ... ... pg:3 ..... rd:5 \ | |
| 170 | &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shl | |
| 171 | @rdn_pg_tszimm_shr ........ .. ... ... ... pg:3 ..... rd:5 \ | |
| 172 | &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shr | |
| ccd841c3 | 173 | |
| d9d78dcc | 174 | # Similarly without predicate. |
| 830d1a5a RH |
175 | @rd_rn_tszimm_shl ........ .. ... ... ...... rn:5 rd:5 \ |
| 176 | &rri_esz esz=%tszimm16_esz imm=%tszimm16_shl | |
| 177 | @rd_rn_tszimm_shr ........ .. ... ... ...... rn:5 rd:5 \ | |
| 178 | &rri_esz esz=%tszimm16_esz imm=%tszimm16_shr | |
| d9d78dcc | 179 | |
| f25a2361 RH |
180 | # Two register operand, one immediate operand, with 4-bit predicate. |
| 181 | # User must fill in imm. | |
| 182 | @rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \ | |
| 183 | &rpri_esz rn=%reg_movprfx | |
| 184 | ||
| cc48affe RH |
185 | # Two register operand, one one-bit floating-point operand. |
| 186 | @rdn_i1 ........ esz:2 ......... pg:3 .... imm:1 rd:5 \ | |
| 187 | &rpri_esz rn=%reg_movprfx | |
| 188 | ||
| e1fa1164 RH |
189 | # Two register operand, one encoded bitmask. |
| 190 | @rdn_dbm ........ .. .... dbm:13 rd:5 \ | |
| 191 | &rr_dbm rn=%reg_movprfx | |
| 192 | ||
| 38cadeba RH |
193 | # Predicate output, vector and immediate input, |
| 194 | # controlling predicate, element size. | |
| 195 | @pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz | |
| 196 | @pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz | |
| 197 | ||
| d1822297 RH |
198 | # Basic Load/Store with 9-bit immediate offset |
| 199 | @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ | |
| 200 | &rri imm=%imm9_16_10 | |
| 201 | @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \ | |
| 202 | &rri imm=%imm9_16_10 | |
| 203 | ||
| 24e82e68 RH |
204 | # One register, pattern, and uint4+1. |
| 205 | # User must fill in U and D. | |
| 206 | @incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ | |
| 207 | &incdec_cnt imm=%imm4_16_p1 | |
| 208 | @incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ | |
| 209 | &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx | |
| 210 | ||
| 9ee3a611 RH |
211 | # One register, predicate. |
| 212 | # User must fill in U and D. | |
| 213 | @incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred | |
| 214 | @incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \ | |
| 215 | &incdec2_pred rn=%reg_movprfx | |
| 216 | ||
| c4e7c493 RH |
217 | # Loads; user must fill in NREG. |
| 218 | @rprr_load_dt ....... dtype:4 rm:5 ... pg:3 rn:5 rd:5 &rprr_load | |
| 219 | @rpri_load_dt ....... dtype:4 . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load | |
| 220 | ||
| 221 | @rprr_load_msz ....... .... rm:5 ... pg:3 rn:5 rd:5 \ | |
| 222 | &rprr_load dtype=%msz_dtype | |
| 223 | @rpri_load_msz ....... .... . imm:s4 ... pg:3 rn:5 rd:5 \ | |
| 224 | &rpri_load dtype=%msz_dtype | |
| 225 | ||
| 673e9fa6 RH |
226 | # Gather Loads. |
| 227 | @rprr_g_load_u ....... .. . . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ | |
| 228 | &rprr_gather_load xs=2 | |
| 229 | @rprr_g_load_xs_u ....... .. xs:1 . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ | |
| 230 | &rprr_gather_load | |
| 231 | @rprr_g_load_xs_u_sc ....... .. xs:1 scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ | |
| 232 | &rprr_gather_load | |
| 233 | @rprr_g_load_xs_sc ....... .. xs:1 scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \ | |
| 234 | &rprr_gather_load | |
| 235 | @rprr_g_load_u_sc ....... .. . scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ | |
| 236 | &rprr_gather_load xs=2 | |
| 237 | @rprr_g_load_sc ....... .. . scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \ | |
| 238 | &rprr_gather_load xs=2 | |
| 239 | @rpri_g_load ....... msz:2 .. imm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ | |
| 240 | &rpri_gather_load | |
| 241 | ||
| 1a039c7e RH |
242 | # Stores; user must fill in ESZ, MSZ, NREG as needed. |
| 243 | @rprr_store ....... .. .. rm:5 ... pg:3 rn:5 rd:5 &rprr_store | |
| 244 | @rpri_store_msz ....... msz:2 .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store | |
| 245 | @rprr_store_esz_n0 ....... .. esz:2 rm:5 ... pg:3 rn:5 rd:5 \ | |
| 246 | &rprr_store nreg=0 | |
| f6dbf62a RH |
247 | @rprr_scatter_store ....... msz:2 .. rm:5 ... pg:3 rn:5 rd:5 \ |
| 248 | &rprr_scatter_store | |
| 408ecde9 RH |
249 | @rpri_scatter_store ....... msz:2 .. imm:5 ... pg:3 rn:5 rd:5 \ |
| 250 | &rpri_scatter_store | |
| 1a039c7e | 251 | |
| 1c737d9c RH |
252 | # Two registers and a scalar by N-bit index |
| 253 | @rrx_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \ | |
| 254 | &rrx_esz index=%index3_22_19 | |
| 255 | @rrx_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 &rrx_esz | |
| 256 | @rrx_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 &rrx_esz | |
| 257 | ||
| b95f5eeb RH |
258 | # Two registers and a scalar by N-bit index, alternate |
| 259 | @rrx_3a ........ .. . .. rm:3 ...... rn:5 rd:5 \ | |
| 260 | &rrx_esz index=%index3_19_11 | |
| 261 | @rrx_2a ........ .. . . rm:4 ...... rn:5 rd:5 \ | |
| 262 | &rrx_esz index=%index2_20_11 | |
| 263 | ||
| 0a82d963 RH |
264 | # Three registers and a scalar by N-bit index |
| 265 | @rrxr_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \ | |
| 266 | &rrxr_esz ra=%reg_movprfx index=%index3_22_19 | |
| 267 | @rrxr_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 \ | |
| 268 | &rrxr_esz ra=%reg_movprfx | |
| 269 | @rrxr_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 \ | |
| 270 | &rrxr_esz ra=%reg_movprfx | |
| 271 | ||
| c5c455d7 RH |
272 | # Three registers and a scalar by N-bit index, alternate |
| 273 | @rrxr_3a ........ .. ... rm:3 ...... rn:5 rd:5 \ | |
| 274 | &rrxr_esz ra=%reg_movprfx index=%index3_19_11 | |
| 275 | @rrxr_2a ........ .. .. rm:4 ...... rn:5 rd:5 \ | |
| 276 | &rrxr_esz ra=%reg_movprfx index=%index2_20_11 | |
| 277 | ||
| 38388f7e RH |
278 | ########################################################################### |
| 279 | # Instruction patterns. Grouped according to the SVE encodingindex.xhtml. | |
| 280 | ||
| f97cfd59 RH |
281 | ### SVE Integer Arithmetic - Binary Predicated Group |
| 282 | ||
| 283 | # SVE bitwise logical vector operations (predicated) | |
| 284 | ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm | |
| 285 | EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm | |
| 286 | AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm | |
| 287 | BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm | |
| 288 | ||
| 289 | # SVE integer add/subtract vectors (predicated) | |
| 290 | ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm | |
| 291 | SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm | |
| 292 | SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR | |
| 293 | ||
| 294 | # SVE integer min/max/difference (predicated) | |
| 295 | SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm | |
| 296 | UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm | |
| 297 | SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm | |
| 298 | UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm | |
| 299 | SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm | |
| 300 | UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm | |
| 301 | ||
| 302 | # SVE integer multiply/divide (predicated) | |
| 303 | MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm | |
| 304 | SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm | |
| 305 | UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm | |
| 306 | # Note that divide requires size >= 2; below 2 is unallocated. | |
| 307 | SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm | |
| 308 | UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm | |
| 309 | SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR | |
| 310 | UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR | |
| 311 | ||
| 047cec97 RH |
312 | ### SVE Integer Reduction Group |
| 313 | ||
| 314 | # SVE bitwise logical reduction (predicated) | |
| 315 | ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn | |
| 316 | EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn | |
| 317 | ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn | |
| 318 | ||
| a2103582 RH |
319 | # SVE constructive prefix (predicated) |
| 320 | MOVPRFX_z 00000100 .. 010 000 001 ... ..... ..... @rd_pg_rn | |
| 321 | MOVPRFX_m 00000100 .. 010 001 001 ... ..... ..... @rd_pg_rn | |
| 322 | ||
| 047cec97 RH |
323 | # SVE integer add reduction (predicated) |
| 324 | # Note that saddv requires size != 3. | |
| 325 | UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn | |
| 326 | SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn | |
| 327 | ||
| 328 | # SVE integer min/max reduction (predicated) | |
| 329 | SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn | |
| 330 | UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn | |
| 331 | SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn | |
| 332 | UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn | |
| 333 | ||
| ccd841c3 RH |
334 | ### SVE Shift by Immediate - Predicated Group |
| 335 | ||
| 336 | # SVE bitwise shift by immediate (predicated) | |
| 830d1a5a RH |
337 | ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... @rdn_pg_tszimm_shr |
| 338 | LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... @rdn_pg_tszimm_shr | |
| 339 | LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... @rdn_pg_tszimm_shl | |
| 340 | ASRD 00000100 .. 000 100 100 ... .. ... ..... @rdn_pg_tszimm_shr | |
| ccd841c3 | 341 | |
| 27721dbb RH |
342 | # SVE bitwise shift by vector (predicated) |
| 343 | ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm | |
| 344 | LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm | |
| 345 | LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm | |
| 346 | ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR | |
| 347 | LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR | |
| 348 | LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR | |
| 349 | ||
| fe7f8dfb RH |
350 | # SVE bitwise shift by wide elements (predicated) |
| 351 | # Note these require size != 3. | |
| 352 | ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm | |
| 353 | LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm | |
| 354 | LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm | |
| 355 | ||
| afac6d04 RH |
356 | ### SVE Integer Arithmetic - Unary Predicated Group |
| 357 | ||
| 358 | # SVE unary bit operations (predicated) | |
| 359 | # Note esz != 0 for FABS and FNEG. | |
| 360 | CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn | |
| 361 | CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn | |
| 362 | CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn | |
| 363 | CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn | |
| 364 | NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn | |
| 365 | FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn | |
| 366 | FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn | |
| 367 | ||
| 368 | # SVE integer unary operations (predicated) | |
| 369 | # Note esz > original size for extensions. | |
| 370 | ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn | |
| 371 | NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn | |
| 372 | SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn | |
| 373 | UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn | |
| 374 | SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn | |
| 375 | UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn | |
| 376 | SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn | |
| 377 | UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn | |
| 378 | ||
| abfdefd5 RH |
379 | ### SVE Floating Point Compare - Vectors Group |
| 380 | ||
| 381 | # SVE floating-point compare vectors | |
| 382 | FCMGE_ppzz 01100101 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm | |
| 383 | FCMGT_ppzz 01100101 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm | |
| 384 | FCMEQ_ppzz 01100101 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm | |
| 385 | FCMNE_ppzz 01100101 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm | |
| 386 | FCMUO_ppzz 01100101 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm | |
| 387 | FACGE_ppzz 01100101 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm | |
| 388 | FACGT_ppzz 01100101 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm | |
| 389 | ||
| 96a36e4a RH |
390 | ### SVE Integer Multiply-Add Group |
| 391 | ||
| 392 | # SVE integer multiply-add writing addend (predicated) | |
| 393 | MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm | |
| 394 | MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm | |
| 395 | ||
| 396 | # SVE integer multiply-add writing multiplicand (predicated) | |
| 397 | MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD | |
| 398 | MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB | |
| 399 | ||
| fea98f9c RH |
400 | ### SVE Integer Arithmetic - Unpredicated Group |
| 401 | ||
| 402 | # SVE integer add/subtract vectors (unpredicated) | |
| 403 | ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm | |
| 404 | SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm | |
| 405 | SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm | |
| 406 | UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm | |
| 407 | SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm | |
| 408 | UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm | |
| 409 | ||
| 38388f7e RH |
410 | ### SVE Logical - Unpredicated Group |
| 411 | ||
| 412 | # SVE bitwise logical operations (unpredicated) | |
| 413 | AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
| 414 | ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
| 415 | EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
| 416 | BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
| d1822297 | 417 | |
| e6eba6e5 RH |
418 | XAR 00000100 .. 1 ..... 001 101 rm:5 rd:5 &rrri_esz \ |
| 419 | rn=%reg_movprfx esz=%tszimm16_esz imm=%tszimm16_shr | |
| 420 | ||
| 911cdc6d RH |
421 | # SVE2 bitwise ternary operations |
| 422 | EOR3 00000100 00 1 ..... 001 110 ..... ..... @rdn_ra_rm_e0 | |
| 423 | BSL 00000100 00 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0 | |
| 424 | BCAX 00000100 01 1 ..... 001 110 ..... ..... @rdn_ra_rm_e0 | |
| 425 | BSL1N 00000100 01 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0 | |
| 426 | BSL2N 00000100 10 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0 | |
| 427 | NBSL 00000100 11 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0 | |
| 428 | ||
| 9a56c9c3 RH |
429 | ### SVE Index Generation Group |
| 430 | ||
| 431 | # SVE index generation (immediate start, immediate increment) | |
| 432 | INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5 | |
| 433 | ||
| 434 | # SVE index generation (immediate start, register increment) | |
| 435 | INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5 | |
| 436 | ||
| 437 | # SVE index generation (register start, immediate increment) | |
| 438 | INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 | |
| 439 | ||
| 440 | # SVE index generation (register start, register increment) | |
| 441 | INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm | |
| 442 | ||
| 96f922cc RH |
443 | ### SVE Stack Allocation Group |
| 444 | ||
| 445 | # SVE stack frame adjustment | |
| 446 | ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 | |
| 447 | ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 | |
| 448 | ||
| 449 | # SVE stack frame size | |
| 450 | RDVL 00000100 101 11111 01010 imm:s6 rd:5 | |
| 451 | ||
| d9d78dcc RH |
452 | ### SVE Bitwise Shift - Unpredicated Group |
| 453 | ||
| 454 | # SVE bitwise shift by immediate (unpredicated) | |
| 830d1a5a RH |
455 | ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... @rd_rn_tszimm_shr |
| 456 | LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... @rd_rn_tszimm_shr | |
| 457 | LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... @rd_rn_tszimm_shl | |
| d9d78dcc RH |
458 | |
| 459 | # SVE bitwise shift by wide elements (unpredicated) | |
| 460 | # Note esz != 3 | |
| 461 | ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm | |
| 462 | LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm | |
| 463 | LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm | |
| 464 | ||
| 4b242d9c RH |
465 | ### SVE Compute Vector Address Group |
| 466 | ||
| 467 | # SVE vector address generation | |
| 468 | ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
| 469 | ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
| 470 | ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
| 471 | ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
| 472 | ||
| 0762cd42 RH |
473 | ### SVE Integer Misc - Unpredicated Group |
| 474 | ||
| a2103582 RH |
475 | # SVE constructive prefix (unpredicated) |
| 476 | MOVPRFX 00000100 00 1 00000 101111 rn:5 rd:5 | |
| 477 | ||
| 0762cd42 RH |
478 | # SVE floating-point exponential accelerator |
| 479 | # Note esz != 0 | |
| 480 | FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn | |
| 481 | ||
| a1f233f2 RH |
482 | # SVE floating-point trig select coefficient |
| 483 | # Note esz != 0 | |
| 484 | FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm | |
| 485 | ||
| 24e82e68 RH |
486 | ### SVE Element Count Group |
| 487 | ||
| 488 | # SVE element count | |
| 489 | CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1 | |
| 490 | ||
| 491 | # SVE inc/dec register by element count | |
| 492 | INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1 | |
| 493 | ||
| 494 | # SVE saturating inc/dec register by element count | |
| 495 | SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt | |
| 496 | SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt | |
| 497 | ||
| 498 | # SVE inc/dec vector by element count | |
| 499 | # Note this requires esz != 0. | |
| 500 | INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1 | |
| 501 | ||
| 502 | # SVE saturating inc/dec vector by element count | |
| 503 | # Note these require esz != 0. | |
| 504 | SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt | |
| 516e246a | 505 | |
| e1fa1164 RH |
506 | ### SVE Bitwise Immediate Group |
| 507 | ||
| 508 | # SVE bitwise logical with immediate (unpredicated) | |
| 509 | ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm | |
| 510 | EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm | |
| 511 | AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm | |
| 512 | ||
| 513 | # SVE broadcast bitmask immediate | |
| 514 | DUPM 00000101 11 0000 dbm:13 rd:5 | |
| 515 | ||
| f25a2361 RH |
516 | ### SVE Integer Wide Immediate - Predicated Group |
| 517 | ||
| 518 | # SVE copy floating-point immediate (predicated) | |
| 519 | FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4 | |
| 520 | ||
| 521 | # SVE copy integer immediate (predicated) | |
| 522 | CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s | |
| 523 | CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s | |
| 524 | ||
| b94f8f60 RH |
525 | ### SVE Permute - Extract Group |
| 526 | ||
| 75114792 | 527 | # SVE extract vector (destructive) |
| b94f8f60 RH |
528 | EXT 00000101 001 ..... 000 ... rm:5 rd:5 \ |
| 529 | &rrri rn=%reg_movprfx imm=%imm8_16_10 | |
| 530 | ||
| 75114792 SL |
531 | # SVE2 extract vector (constructive) |
| 532 | EXT_sve2 00000101 011 ..... 000 ... rn:5 rd:5 \ | |
| 533 | &rri imm=%imm8_16_10 | |
| 534 | ||
| 30562ab7 RH |
535 | ### SVE Permute - Unpredicated Group |
| 536 | ||
| 537 | # SVE broadcast general register | |
| 538 | DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn | |
| 539 | ||
| 540 | # SVE broadcast indexed element | |
| 541 | DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \ | |
| 542 | &rri imm=%imm7_22_16 | |
| 543 | ||
| 544 | # SVE insert SIMD&FP scalar register | |
| 545 | INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm | |
| 546 | ||
| 547 | # SVE insert general register | |
| 548 | INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm | |
| 549 | ||
| 550 | # SVE reverse vector elements | |
| 551 | REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn | |
| 552 | ||
| 553 | # SVE vector table lookup | |
| 554 | TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm | |
| 555 | ||
| 556 | # SVE unpack vector elements | |
| 557 | UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5 | |
| 558 | ||
| d731d8cb RH |
559 | ### SVE Permute - Predicates Group |
| 560 | ||
| 561 | # SVE permute predicate elements | |
| 562 | ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm | |
| 563 | ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm | |
| 564 | UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm | |
| 565 | UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm | |
| 566 | TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm | |
| 567 | TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm | |
| 568 | ||
| 569 | # SVE reverse predicate elements | |
| 570 | REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn | |
| 571 | ||
| 572 | # SVE unpack predicate elements | |
| 573 | PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0 | |
| 574 | PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0 | |
| 575 | ||
| 234b48e9 RH |
576 | ### SVE Permute - Interleaving Group |
| 577 | ||
| 578 | # SVE permute vector elements | |
| 579 | ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm | |
| 580 | ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm | |
| 581 | UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm | |
| 582 | UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm | |
| 583 | TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm | |
| 584 | TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm | |
| 585 | ||
| 3ca879ae RH |
586 | ### SVE Permute - Predicated Group |
| 587 | ||
| 588 | # SVE compress active elements | |
| 589 | # Note esz >= 2 | |
| 590 | COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn | |
| 591 | ||
| ef23cb72 RH |
592 | # SVE conditionally broadcast element to vector |
| 593 | CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm | |
| 594 | CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm | |
| 595 | ||
| 596 | # SVE conditionally copy element to SIMD&FP scalar | |
| 597 | CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn | |
| 598 | CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn | |
| 599 | ||
| 600 | # SVE conditionally copy element to general register | |
| 601 | CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn | |
| 602 | CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn | |
| 603 | ||
| 604 | # SVE copy element to SIMD&FP scalar register | |
| 605 | LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn | |
| 606 | LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn | |
| 607 | ||
| 608 | # SVE copy element to general register | |
| 609 | LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn | |
| 610 | LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn | |
| 611 | ||
| 792a5578 RH |
612 | # SVE copy element from SIMD&FP scalar register |
| 613 | CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn | |
| 614 | ||
| 615 | # SVE copy element from general register to vector (predicated) | |
| 616 | CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn | |
| 617 | ||
| dae8fb90 RH |
618 | # SVE reverse within elements |
| 619 | # Note esz >= operation size | |
| 620 | REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn | |
| 621 | REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn | |
| 622 | REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn | |
| 623 | RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn | |
| 624 | ||
| 75114792 | 625 | # SVE vector splice (predicated, destructive) |
| b48ff240 RH |
626 | SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm |
| 627 | ||
| 75114792 SL |
628 | # SVE2 vector splice (predicated, constructive) |
| 629 | SPLICE_sve2 00000101 .. 101 101 100 ... ..... ..... @rd_pg_rn | |
| 630 | ||
| d3fe4a29 RH |
631 | ### SVE Select Vectors Group |
| 632 | ||
| 633 | # SVE select vector elements (predicated) | |
| 634 | SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm | |
| 635 | ||
| 757f9cff RH |
636 | ### SVE Integer Compare - Vectors Group |
| 637 | ||
| 638 | # SVE integer compare_vectors | |
| 639 | CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm | |
| 640 | CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm | |
| 641 | CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm | |
| 642 | CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm | |
| 643 | CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm | |
| 644 | CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm | |
| 645 | ||
| 646 | # SVE integer compare with wide elements | |
| 647 | # Note these require esz != 3. | |
| 648 | CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm | |
| 649 | CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm | |
| 650 | CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm | |
| 651 | CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm | |
| 652 | CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm | |
| 653 | CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm | |
| 654 | CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm | |
| 655 | CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm | |
| 656 | CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm | |
| 657 | CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm | |
| 658 | ||
| 38cadeba RH |
659 | ### SVE Integer Compare - Unsigned Immediate Group |
| 660 | ||
| 661 | # SVE integer compare with unsigned immediate | |
| 662 | CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7 | |
| 663 | CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7 | |
| 664 | CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7 | |
| 665 | CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7 | |
| 666 | ||
| 667 | ### SVE Integer Compare - Signed Immediate Group | |
| 668 | ||
| 669 | # SVE integer compare with signed immediate | |
| 670 | CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5 | |
| 671 | CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5 | |
| 672 | CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5 | |
| 673 | CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5 | |
| 674 | CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5 | |
| 675 | CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5 | |
| 676 | ||
| e1fa1164 RH |
677 | ### SVE Predicate Logical Operations Group |
| 678 | ||
| 516e246a RH |
679 | # SVE predicate logical operations |
| 680 | AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
| 681 | BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
| 682 | EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s | |
| 683 | SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s | |
| 684 | ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
| 685 | ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
| 686 | NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s | |
| 687 | NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s | |
| 688 | ||
| 9e18d7a6 RH |
689 | ### SVE Predicate Misc Group |
| 690 | ||
| 691 | # SVE predicate test | |
| 692 | PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000 | |
| 693 | ||
| 028e2a7b RH |
694 | # SVE predicate initialize |
| 695 | PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4 | |
| 696 | ||
| 697 | # SVE initialize FFR | |
| 698 | SETFFR 00100101 0010 1100 1001 0000 0000 0000 | |
| 699 | ||
| 700 | # SVE zero predicate register | |
| 701 | PFALSE 00100101 0001 1000 1110 0100 0000 rd:4 | |
| 702 | ||
| 703 | # SVE predicate read from FFR (predicated) | |
| 704 | RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4 | |
| 705 | ||
| 706 | # SVE predicate read from FFR (unpredicated) | |
| 707 | RDFFR 00100101 0001 1001 1111 0000 0000 rd:4 | |
| 708 | ||
| 709 | # SVE FFR write from predicate (WRFFR) | |
| 710 | WRFFR 00100101 0010 1000 1001 000 rn:4 00000 | |
| 711 | ||
| 712 | # SVE predicate first active | |
| 713 | PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0 | |
| 714 | ||
| 715 | # SVE predicate next active | |
| 716 | PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn | |
| 717 | ||
| 35da316f RH |
718 | ### SVE Partition Break Group |
| 719 | ||
| 720 | # SVE propagate break from previous partition | |
| 721 | BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
| 722 | BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
| 723 | ||
| 724 | # SVE partition break condition | |
| 725 | BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s | |
| 726 | BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s | |
| 407e6ce7 RH |
727 | BRKA_m 00100101 00 01000001 .... 0 .... 1 .... @pd_pg_pn_s0 |
| 728 | BRKB_m 00100101 10 01000001 .... 0 .... 1 .... @pd_pg_pn_s0 | |
| 35da316f RH |
729 | |
| 730 | # SVE propagate break to next partition | |
| 731 | BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s | |
| 732 | ||
| 9ee3a611 RH |
733 | ### SVE Predicate Count Group |
| 734 | ||
| 735 | # SVE predicate count | |
| 736 | CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn | |
| 737 | ||
| 738 | # SVE inc/dec register by predicate count | |
| 739 | INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1 | |
| 740 | ||
| 741 | # SVE inc/dec vector by predicate count | |
| 742 | INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1 | |
| 743 | ||
| 744 | # SVE saturating inc/dec register by predicate count | |
| 745 | SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred | |
| 746 | SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred | |
| 747 | ||
| 748 | # SVE saturating inc/dec vector by predicate count | |
| 749 | SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred | |
| 750 | ||
| caf1cefc RH |
751 | ### SVE Integer Compare - Scalars Group |
| 752 | ||
| 753 | # SVE conditionally terminate scalars | |
| 754 | CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000 | |
| 755 | ||
| 756 | # SVE integer compare scalar count and limit | |
| 34688dbc | 757 | WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 lt:1 rn:5 eq:1 rd:4 |
| caf1cefc | 758 | |
| 14f6dad1 RH |
759 | # SVE2 pointer conflict compare |
| 760 | WHILE_ptr 00100101 esz:2 1 rm:5 001 100 rn:5 rw:1 rd:4 | |
| 761 | ||
| ed491961 RH |
762 | ### SVE Integer Wide Immediate - Unpredicated Group |
| 763 | ||
| 764 | # SVE broadcast floating-point immediate (unpredicated) | |
| 765 | FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5 | |
| 766 | ||
| 767 | # SVE broadcast integer immediate (unpredicated) | |
| 768 | DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s | |
| 769 | ||
| 6e6a157d RH |
770 | # SVE integer add/subtract immediate (unpredicated) |
| 771 | ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u | |
| 772 | SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u | |
| 773 | SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u | |
| 774 | SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u | |
| 775 | UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u | |
| 776 | SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u | |
| 777 | UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u | |
| 778 | ||
| 779 | # SVE integer min/max immediate (unpredicated) | |
| 780 | SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s | |
| 781 | UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u | |
| 782 | SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s | |
| 783 | UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u | |
| 784 | ||
| 785 | # SVE integer multiply immediate (unpredicated) | |
| 786 | MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s | |
| 787 | ||
| d730ecaa | 788 | # SVE integer dot product (unpredicated) |
| bc2bd697 RH |
789 | DOT_zzzz 01000100 1 sz:1 0 rm:5 00000 u:1 rn:5 rd:5 \ |
| 790 | ra=%reg_movprfx | |
| d730ecaa | 791 | |
| 814d4c52 RH |
792 | #### SVE Multiply - Indexed |
| 793 | ||
| 16fcfdc7 | 794 | # SVE integer dot product (indexed) |
| 0a82d963 RH |
795 | SDOT_zzxw_s 01000100 10 1 ..... 000000 ..... ..... @rrxr_2 esz=2 |
| 796 | SDOT_zzxw_d 01000100 11 1 ..... 000000 ..... ..... @rrxr_1 esz=3 | |
| 797 | UDOT_zzxw_s 01000100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2 | |
| 798 | UDOT_zzxw_d 01000100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3 | |
| 16fcfdc7 | 799 | |
| 8a02aac7 RH |
800 | # SVE2 integer multiply-add (indexed) |
| 801 | MLA_zzxz_h 01000100 0. 1 ..... 000010 ..... ..... @rrxr_3 esz=1 | |
| 802 | MLA_zzxz_s 01000100 10 1 ..... 000010 ..... ..... @rrxr_2 esz=2 | |
| 803 | MLA_zzxz_d 01000100 11 1 ..... 000010 ..... ..... @rrxr_1 esz=3 | |
| 804 | MLS_zzxz_h 01000100 0. 1 ..... 000011 ..... ..... @rrxr_3 esz=1 | |
| 805 | MLS_zzxz_s 01000100 10 1 ..... 000011 ..... ..... @rrxr_2 esz=2 | |
| 806 | MLS_zzxz_d 01000100 11 1 ..... 000011 ..... ..... @rrxr_1 esz=3 | |
| 807 | ||
| 75d6d5fc RH |
808 | # SVE2 saturating multiply-add high (indexed) |
| 809 | SQRDMLAH_zzxz_h 01000100 0. 1 ..... 000100 ..... ..... @rrxr_3 esz=1 | |
| 810 | SQRDMLAH_zzxz_s 01000100 10 1 ..... 000100 ..... ..... @rrxr_2 esz=2 | |
| 811 | SQRDMLAH_zzxz_d 01000100 11 1 ..... 000100 ..... ..... @rrxr_1 esz=3 | |
| 812 | SQRDMLSH_zzxz_h 01000100 0. 1 ..... 000101 ..... ..... @rrxr_3 esz=1 | |
| 813 | SQRDMLSH_zzxz_s 01000100 10 1 ..... 000101 ..... ..... @rrxr_2 esz=2 | |
| 814 | SQRDMLSH_zzxz_d 01000100 11 1 ..... 000101 ..... ..... @rrxr_1 esz=3 | |
| 815 | ||
| c5c455d7 RH |
816 | # SVE2 saturating multiply-add (indexed) |
| 817 | SQDMLALB_zzxw_s 01000100 10 1 ..... 0010.0 ..... ..... @rrxr_3a esz=2 | |
| 818 | SQDMLALB_zzxw_d 01000100 11 1 ..... 0010.0 ..... ..... @rrxr_2a esz=3 | |
| 819 | SQDMLALT_zzxw_s 01000100 10 1 ..... 0010.1 ..... ..... @rrxr_3a esz=2 | |
| 820 | SQDMLALT_zzxw_d 01000100 11 1 ..... 0010.1 ..... ..... @rrxr_2a esz=3 | |
| 821 | SQDMLSLB_zzxw_s 01000100 10 1 ..... 0011.0 ..... ..... @rrxr_3a esz=2 | |
| 822 | SQDMLSLB_zzxw_d 01000100 11 1 ..... 0011.0 ..... ..... @rrxr_2a esz=3 | |
| 823 | SQDMLSLT_zzxw_s 01000100 10 1 ..... 0011.1 ..... ..... @rrxr_3a esz=2 | |
| 824 | SQDMLSLT_zzxw_d 01000100 11 1 ..... 0011.1 ..... ..... @rrxr_2a esz=3 | |
| 825 | ||
| d462469f RH |
826 | # SVE2 multiply-add long (indexed) |
| 827 | SMLALB_zzxw_s 01000100 10 1 ..... 1000.0 ..... ..... @rrxr_3a esz=2 | |
| 828 | SMLALB_zzxw_d 01000100 11 1 ..... 1000.0 ..... ..... @rrxr_2a esz=3 | |
| 829 | SMLALT_zzxw_s 01000100 10 1 ..... 1000.1 ..... ..... @rrxr_3a esz=2 | |
| 830 | SMLALT_zzxw_d 01000100 11 1 ..... 1000.1 ..... ..... @rrxr_2a esz=3 | |
| 831 | UMLALB_zzxw_s 01000100 10 1 ..... 1001.0 ..... ..... @rrxr_3a esz=2 | |
| 832 | UMLALB_zzxw_d 01000100 11 1 ..... 1001.0 ..... ..... @rrxr_2a esz=3 | |
| 833 | UMLALT_zzxw_s 01000100 10 1 ..... 1001.1 ..... ..... @rrxr_3a esz=2 | |
| 834 | UMLALT_zzxw_d 01000100 11 1 ..... 1001.1 ..... ..... @rrxr_2a esz=3 | |
| 835 | SMLSLB_zzxw_s 01000100 10 1 ..... 1010.0 ..... ..... @rrxr_3a esz=2 | |
| 836 | SMLSLB_zzxw_d 01000100 11 1 ..... 1010.0 ..... ..... @rrxr_2a esz=3 | |
| 837 | SMLSLT_zzxw_s 01000100 10 1 ..... 1010.1 ..... ..... @rrxr_3a esz=2 | |
| 838 | SMLSLT_zzxw_d 01000100 11 1 ..... 1010.1 ..... ..... @rrxr_2a esz=3 | |
| 839 | UMLSLB_zzxw_s 01000100 10 1 ..... 1011.0 ..... ..... @rrxr_3a esz=2 | |
| 840 | UMLSLB_zzxw_d 01000100 11 1 ..... 1011.0 ..... ..... @rrxr_2a esz=3 | |
| 841 | UMLSLT_zzxw_s 01000100 10 1 ..... 1011.1 ..... ..... @rrxr_3a esz=2 | |
| 842 | UMLSLT_zzxw_d 01000100 11 1 ..... 1011.1 ..... ..... @rrxr_2a esz=3 | |
| 843 | ||
| b95f5eeb RH |
844 | # SVE2 saturating multiply (indexed) |
| 845 | SQDMULLB_zzx_s 01000100 10 1 ..... 1110.0 ..... ..... @rrx_3a esz=2 | |
| 846 | SQDMULLB_zzx_d 01000100 11 1 ..... 1110.0 ..... ..... @rrx_2a esz=3 | |
| 847 | SQDMULLT_zzx_s 01000100 10 1 ..... 1110.1 ..... ..... @rrx_3a esz=2 | |
| 848 | SQDMULLT_zzx_d 01000100 11 1 ..... 1110.1 ..... ..... @rrx_2a esz=3 | |
| 849 | ||
| 1aee2d70 RH |
850 | # SVE2 saturating multiply high (indexed) |
| 851 | SQDMULH_zzx_h 01000100 0. 1 ..... 111100 ..... ..... @rrx_3 esz=1 | |
| 852 | SQDMULH_zzx_s 01000100 10 1 ..... 111100 ..... ..... @rrx_2 esz=2 | |
| 853 | SQDMULH_zzx_d 01000100 11 1 ..... 111100 ..... ..... @rrx_1 esz=3 | |
| 854 | SQRDMULH_zzx_h 01000100 0. 1 ..... 111101 ..... ..... @rrx_3 esz=1 | |
| 855 | SQRDMULH_zzx_s 01000100 10 1 ..... 111101 ..... ..... @rrx_2 esz=2 | |
| 856 | SQRDMULH_zzx_d 01000100 11 1 ..... 111101 ..... ..... @rrx_1 esz=3 | |
| 857 | ||
| 814d4c52 RH |
858 | # SVE2 integer multiply (indexed) |
| 859 | MUL_zzx_h 01000100 0. 1 ..... 111110 ..... ..... @rrx_3 esz=1 | |
| 860 | MUL_zzx_s 01000100 10 1 ..... 111110 ..... ..... @rrx_2 esz=2 | |
| 861 | MUL_zzx_d 01000100 11 1 ..... 111110 ..... ..... @rrx_1 esz=3 | |
| 862 | ||
| 76a9d9cd RH |
863 | # SVE floating-point complex add (predicated) |
| 864 | FCADD 01100100 esz:2 00000 rot:1 100 pg:3 rm:5 rd:5 \ | |
| 865 | rn=%reg_movprfx | |
| 866 | ||
| 05f48bab RH |
867 | # SVE floating-point complex multiply-add (predicated) |
| 868 | FCMLA_zpzzz 01100100 esz:2 0 rm:5 0 rot:2 pg:3 rn:5 rd:5 \ | |
| 869 | ra=%reg_movprfx | |
| 870 | ||
| 18fc2405 RH |
871 | # SVE floating-point complex multiply-add (indexed) |
| 872 | FCMLA_zzxz 01100100 10 1 index:2 rm:3 0001 rot:2 rn:5 rd:5 \ | |
| 873 | ra=%reg_movprfx esz=1 | |
| 874 | FCMLA_zzxz 01100100 11 1 index:1 rm:4 0001 rot:2 rn:5 rd:5 \ | |
| 875 | ra=%reg_movprfx esz=2 | |
| 876 | ||
| ca40a6e6 RH |
877 | ### SVE FP Multiply-Add Indexed Group |
| 878 | ||
| 879 | # SVE floating-point multiply-add (indexed) | |
| 0a82d963 RH |
880 | FMLA_zzxz 01100100 0. 1 ..... 000000 ..... ..... @rrxr_3 esz=1 |
| 881 | FMLA_zzxz 01100100 10 1 ..... 000000 ..... ..... @rrxr_2 esz=2 | |
| 882 | FMLA_zzxz 01100100 11 1 ..... 000000 ..... ..... @rrxr_1 esz=3 | |
| 883 | FMLS_zzxz 01100100 0. 1 ..... 000001 ..... ..... @rrxr_3 esz=1 | |
| 884 | FMLS_zzxz 01100100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2 | |
| 885 | FMLS_zzxz 01100100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3 | |
| ca40a6e6 RH |
886 | |
| 887 | ### SVE FP Multiply Indexed Group | |
| 888 | ||
| 889 | # SVE floating-point multiply (indexed) | |
| 1c737d9c RH |
890 | FMUL_zzx 01100100 0. 1 ..... 001000 ..... ..... @rrx_3 esz=1 |
| 891 | FMUL_zzx 01100100 10 1 ..... 001000 ..... ..... @rrx_2 esz=2 | |
| 892 | FMUL_zzx 01100100 11 1 ..... 001000 ..... ..... @rrx_1 esz=3 | |
| ca40a6e6 | 893 | |
| 23fbe79f RH |
894 | ### SVE FP Fast Reduction Group |
| 895 | ||
| 896 | FADDV 01100101 .. 000 000 001 ... ..... ..... @rd_pg_rn | |
| 897 | FMAXNMV 01100101 .. 000 100 001 ... ..... ..... @rd_pg_rn | |
| 898 | FMINNMV 01100101 .. 000 101 001 ... ..... ..... @rd_pg_rn | |
| 899 | FMAXV 01100101 .. 000 110 001 ... ..... ..... @rd_pg_rn | |
| 900 | FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn | |
| 901 | ||
| 3887c038 RH |
902 | ## SVE Floating Point Unary Operations - Unpredicated Group |
| 903 | ||
| 904 | FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn | |
| 905 | FRSQRTE 01100101 .. 001 111 001100 ..... ..... @rd_rn | |
| 906 | ||
| 4d2e2a03 RH |
907 | ### SVE FP Compare with Zero Group |
| 908 | ||
| 909 | FCMGE_ppz0 01100101 .. 0100 00 001 ... ..... 0 .... @pd_pg_rn | |
| 910 | FCMGT_ppz0 01100101 .. 0100 00 001 ... ..... 1 .... @pd_pg_rn | |
| 911 | FCMLT_ppz0 01100101 .. 0100 01 001 ... ..... 0 .... @pd_pg_rn | |
| 912 | FCMLE_ppz0 01100101 .. 0100 01 001 ... ..... 1 .... @pd_pg_rn | |
| 913 | FCMEQ_ppz0 01100101 .. 0100 10 001 ... ..... 0 .... @pd_pg_rn | |
| 914 | FCMNE_ppz0 01100101 .. 0100 11 001 ... ..... 0 .... @pd_pg_rn | |
| 915 | ||
| 7f9ddf64 RH |
916 | ### SVE FP Accumulating Reduction Group |
| 917 | ||
| 918 | # SVE floating-point serial reduction (predicated) | |
| 919 | FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm | |
| 920 | ||
| 29b80469 RH |
921 | ### SVE Floating Point Arithmetic - Unpredicated Group |
| 922 | ||
| 923 | # SVE floating-point arithmetic (unpredicated) | |
| 924 | FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm | |
| 925 | FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm | |
| 926 | FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm | |
| 927 | FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm | |
| 928 | FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm | |
| 929 | FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm | |
| 930 | ||
| ec3b87c2 RH |
931 | ### SVE FP Arithmetic Predicated Group |
| 932 | ||
| 933 | # SVE floating-point arithmetic (predicated) | |
| 934 | FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm | |
| 935 | FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm | |
| 936 | FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm | |
| 937 | FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR | |
| 938 | FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm | |
| 939 | FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm | |
| 940 | FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm | |
| 941 | FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm | |
| 942 | FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm | |
| 943 | FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm | |
| 944 | FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm | |
| 945 | FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR | |
| 946 | FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm | |
| 947 | ||
| cc48affe RH |
948 | # SVE floating-point arithmetic with immediate (predicated) |
| 949 | FADD_zpzi 01100101 .. 011 000 100 ... 0000 . ..... @rdn_i1 | |
| 950 | FSUB_zpzi 01100101 .. 011 001 100 ... 0000 . ..... @rdn_i1 | |
| 951 | FMUL_zpzi 01100101 .. 011 010 100 ... 0000 . ..... @rdn_i1 | |
| 952 | FSUBR_zpzi 01100101 .. 011 011 100 ... 0000 . ..... @rdn_i1 | |
| 953 | FMAXNM_zpzi 01100101 .. 011 100 100 ... 0000 . ..... @rdn_i1 | |
| 954 | FMINNM_zpzi 01100101 .. 011 101 100 ... 0000 . ..... @rdn_i1 | |
| 955 | FMAX_zpzi 01100101 .. 011 110 100 ... 0000 . ..... @rdn_i1 | |
| 956 | FMIN_zpzi 01100101 .. 011 111 100 ... 0000 . ..... @rdn_i1 | |
| 957 | ||
| 67fcd9ad RH |
958 | # SVE floating-point trig multiply-add coefficient |
| 959 | FTMAD 01100101 esz:2 010 imm:3 100000 rm:5 rd:5 rn=%reg_movprfx | |
| 960 | ||
| 6ceabaad RH |
961 | ### SVE FP Multiply-Add Group |
| 962 | ||
| 963 | # SVE floating-point multiply-accumulate writing addend | |
| 964 | FMLA_zpzzz 01100101 .. 1 ..... 000 ... ..... ..... @rda_pg_rn_rm | |
| 965 | FMLS_zpzzz 01100101 .. 1 ..... 001 ... ..... ..... @rda_pg_rn_rm | |
| 966 | FNMLA_zpzzz 01100101 .. 1 ..... 010 ... ..... ..... @rda_pg_rn_rm | |
| 967 | FNMLS_zpzzz 01100101 .. 1 ..... 011 ... ..... ..... @rda_pg_rn_rm | |
| 968 | ||
| 969 | # SVE floating-point multiply-accumulate writing multiplicand | |
| 970 | # Alter the operand extraction order and reuse the helpers from above. | |
| 971 | # FMAD, FMSB, FNMAD, FNMS | |
| 972 | FMLA_zpzzz 01100101 .. 1 ..... 100 ... ..... ..... @rdn_pg_rm_ra | |
| 973 | FMLS_zpzzz 01100101 .. 1 ..... 101 ... ..... ..... @rdn_pg_rm_ra | |
| 974 | FNMLA_zpzzz 01100101 .. 1 ..... 110 ... ..... ..... @rdn_pg_rm_ra | |
| 975 | FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ..... @rdn_pg_rm_ra | |
| 976 | ||
| 8092c6a3 RH |
977 | ### SVE FP Unary Operations Predicated Group |
| 978 | ||
| 46d33d1e RH |
979 | # SVE floating-point convert precision |
| 980 | FCVT_sh 01100101 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0 | |
| 981 | FCVT_hs 01100101 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0 | |
| 982 | FCVT_dh 01100101 11 0010 00 101 ... ..... ..... @rd_pg_rn_e0 | |
| 983 | FCVT_hd 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_e0 | |
| 984 | FCVT_ds 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0 | |
| 985 | FCVT_sd 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0 | |
| 986 | ||
| df4de1af RH |
987 | # SVE floating-point convert to integer |
| 988 | FCVTZS_hh 01100101 01 011 01 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 989 | FCVTZU_hh 01100101 01 011 01 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 990 | FCVTZS_hs 01100101 01 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 991 | FCVTZU_hs 01100101 01 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 992 | FCVTZS_hd 01100101 01 011 11 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 993 | FCVTZU_hd 01100101 01 011 11 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 994 | FCVTZS_ss 01100101 10 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 995 | FCVTZU_ss 01100101 10 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 996 | FCVTZS_ds 01100101 11 011 00 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 997 | FCVTZU_ds 01100101 11 011 00 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 998 | FCVTZS_sd 01100101 11 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 999 | FCVTZU_sd 01100101 11 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 1000 | FCVTZS_dd 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 1001 | FCVTZU_dd 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 1002 | ||
| cda3c753 RH |
1003 | # SVE floating-point round to integral value |
| 1004 | FRINTN 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn | |
| 1005 | FRINTP 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn | |
| 1006 | FRINTM 01100101 .. 000 010 101 ... ..... ..... @rd_pg_rn | |
| 1007 | FRINTZ 01100101 .. 000 011 101 ... ..... ..... @rd_pg_rn | |
| 1008 | FRINTA 01100101 .. 000 100 101 ... ..... ..... @rd_pg_rn | |
| 1009 | FRINTX 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn | |
| 1010 | FRINTI 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn | |
| 1011 | ||
| ec5b375b RH |
1012 | # SVE floating-point unary operations |
| 1013 | FRECPX 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn | |
| 1014 | FSQRT 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn | |
| 1015 | ||
| 8092c6a3 RH |
1016 | # SVE integer convert to floating-point |
| 1017 | SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 1018 | SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 1019 | SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 1020 | SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 1021 | SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 1022 | SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 1023 | SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 | |
| 1024 | ||
| 1025 | UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 1026 | UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 1027 | UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 1028 | UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 1029 | UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 1030 | UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 1031 | UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 | |
| 1032 | ||
| d1822297 RH |
1033 | ### SVE Memory - 32-bit Gather and Unsized Contiguous Group |
| 1034 | ||
| 1035 | # SVE load predicate register | |
| 1036 | LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9 | |
| 1037 | ||
| 1038 | # SVE load vector register | |
| 1039 | LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9 | |
| c4e7c493 | 1040 | |
| 68459864 RH |
1041 | # SVE load and broadcast element |
| 1042 | LD1R_zpri 1000010 .. 1 imm:6 1.. pg:3 rn:5 rd:5 \ | |
| 1043 | &rpri_load dtype=%dtype_23_13 nreg=0 | |
| 1044 | ||
| 673e9fa6 RH |
1045 | # SVE 32-bit gather load (scalar plus 32-bit unscaled offsets) |
| 1046 | # SVE 32-bit gather load (scalar plus 32-bit scaled offsets) | |
| 1047 | LD1_zprz 1000010 00 .0 ..... 0.. ... ..... ..... \ | |
| 1048 | @rprr_g_load_xs_u esz=2 msz=0 scale=0 | |
| 1049 | LD1_zprz 1000010 01 .. ..... 0.. ... ..... ..... \ | |
| 1050 | @rprr_g_load_xs_u_sc esz=2 msz=1 | |
| 1051 | LD1_zprz 1000010 10 .. ..... 01. ... ..... ..... \ | |
| 1052 | @rprr_g_load_xs_sc esz=2 msz=2 u=1 | |
| 1053 | ||
| 1054 | # SVE 32-bit gather load (vector plus immediate) | |
| 1055 | LD1_zpiz 1000010 .. 01 ..... 1.. ... ..... ..... \ | |
| 1056 | @rpri_g_load esz=2 | |
| 1057 | ||
| c4e7c493 RH |
1058 | ### SVE Memory Contiguous Load Group |
| 1059 | ||
| 1060 | # SVE contiguous load (scalar plus scalar) | |
| 1061 | LD_zprr 1010010 .... ..... 010 ... ..... ..... @rprr_load_dt nreg=0 | |
| 1062 | ||
| e2654d75 RH |
1063 | # SVE contiguous first-fault load (scalar plus scalar) |
| 1064 | LDFF1_zprr 1010010 .... ..... 011 ... ..... ..... @rprr_load_dt nreg=0 | |
| 1065 | ||
| c4e7c493 RH |
1066 | # SVE contiguous load (scalar plus immediate) |
| 1067 | LD_zpri 1010010 .... 0.... 101 ... ..... ..... @rpri_load_dt nreg=0 | |
| 1068 | ||
| e2654d75 RH |
1069 | # SVE contiguous non-fault load (scalar plus immediate) |
| 1070 | LDNF1_zpri 1010010 .... 1.... 101 ... ..... ..... @rpri_load_dt nreg=0 | |
| 1071 | ||
| c4e7c493 RH |
1072 | # SVE contiguous non-temporal load (scalar plus scalar) |
| 1073 | # LDNT1B, LDNT1H, LDNT1W, LDNT1D | |
| 1074 | # SVE load multiple structures (scalar plus scalar) | |
| 1075 | # LD2B, LD2H, LD2W, LD2D; etc. | |
| 1076 | LD_zprr 1010010 .. nreg:2 ..... 110 ... ..... ..... @rprr_load_msz | |
| 1077 | ||
| 1078 | # SVE contiguous non-temporal load (scalar plus immediate) | |
| 1079 | # LDNT1B, LDNT1H, LDNT1W, LDNT1D | |
| 1080 | # SVE load multiple structures (scalar plus immediate) | |
| 1081 | # LD2B, LD2H, LD2W, LD2D; etc. | |
| 1082 | LD_zpri 1010010 .. nreg:2 0.... 111 ... ..... ..... @rpri_load_msz | |
| 1a039c7e | 1083 | |
| 05abe304 RH |
1084 | # SVE load and broadcast quadword (scalar plus scalar) |
| 1085 | LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \ | |
| 1086 | @rprr_load_msz nreg=0 | |
| 1087 | ||
| 1088 | # SVE load and broadcast quadword (scalar plus immediate) | |
| 1089 | # LD1RQB, LD1RQH, LD1RQS, LD1RQD | |
| 1090 | LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \ | |
| 1091 | @rpri_load_msz nreg=0 | |
| 1092 | ||
| dec6cf6b RH |
1093 | # SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets) |
| 1094 | PRF 1000010 00 -1 ----- 0-- --- ----- 0 ---- | |
| 1095 | ||
| 1096 | # SVE 32-bit gather prefetch (vector plus immediate) | |
| 1097 | PRF 1000010 -- 00 ----- 111 --- ----- 0 ---- | |
| 1098 | ||
| 1099 | # SVE contiguous prefetch (scalar plus immediate) | |
| 1100 | PRF 1000010 11 1- ----- 0-- --- ----- 0 ---- | |
| 1101 | ||
| 1102 | # SVE contiguous prefetch (scalar plus scalar) | |
| 1103 | PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ---- | |
| 1104 | ||
| 1105 | ### SVE Memory 64-bit Gather Group | |
| 1106 | ||
| 673e9fa6 RH |
1107 | # SVE 64-bit gather load (scalar plus 32-bit unpacked unscaled offsets) |
| 1108 | # SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets) | |
| 1109 | LD1_zprz 1100010 00 .0 ..... 0.. ... ..... ..... \ | |
| 1110 | @rprr_g_load_xs_u esz=3 msz=0 scale=0 | |
| 1111 | LD1_zprz 1100010 01 .. ..... 0.. ... ..... ..... \ | |
| 1112 | @rprr_g_load_xs_u_sc esz=3 msz=1 | |
| 1113 | LD1_zprz 1100010 10 .. ..... 0.. ... ..... ..... \ | |
| 1114 | @rprr_g_load_xs_u_sc esz=3 msz=2 | |
| 1115 | LD1_zprz 1100010 11 .. ..... 01. ... ..... ..... \ | |
| 1116 | @rprr_g_load_xs_sc esz=3 msz=3 u=1 | |
| 1117 | ||
| 1118 | # SVE 64-bit gather load (scalar plus 64-bit unscaled offsets) | |
| 1119 | # SVE 64-bit gather load (scalar plus 64-bit scaled offsets) | |
| 1120 | LD1_zprz 1100010 00 10 ..... 1.. ... ..... ..... \ | |
| 1121 | @rprr_g_load_u esz=3 msz=0 scale=0 | |
| 1122 | LD1_zprz 1100010 01 1. ..... 1.. ... ..... ..... \ | |
| 1123 | @rprr_g_load_u_sc esz=3 msz=1 | |
| 1124 | LD1_zprz 1100010 10 1. ..... 1.. ... ..... ..... \ | |
| 1125 | @rprr_g_load_u_sc esz=3 msz=2 | |
| 1126 | LD1_zprz 1100010 11 1. ..... 11. ... ..... ..... \ | |
| 1127 | @rprr_g_load_sc esz=3 msz=3 u=1 | |
| 1128 | ||
| 1129 | # SVE 64-bit gather load (vector plus immediate) | |
| 1130 | LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \ | |
| 1131 | @rpri_g_load esz=3 | |
| 1132 | ||
| dec6cf6b RH |
1133 | # SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets) |
| 1134 | PRF 1100010 00 11 ----- 1-- --- ----- 0 ---- | |
| 1135 | ||
| 1136 | # SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets) | |
| 1137 | PRF 1100010 00 -1 ----- 0-- --- ----- 0 ---- | |
| 1138 | ||
| 1139 | # SVE 64-bit gather prefetch (vector plus immediate) | |
| 1140 | PRF 1100010 -- 00 ----- 111 --- ----- 0 ---- | |
| 1141 | ||
| 1a039c7e RH |
1142 | ### SVE Memory Store Group |
| 1143 | ||
| 5047c204 RH |
1144 | # SVE store predicate register |
| 1145 | STR_pri 1110010 11 0. ..... 000 ... ..... 0 .... @pd_rn_i9 | |
| 1146 | ||
| 1147 | # SVE store vector register | |
| 1148 | STR_zri 1110010 11 0. ..... 010 ... ..... ..... @rd_rn_i9 | |
| 1149 | ||
| 1a039c7e RH |
1150 | # SVE contiguous store (scalar plus immediate) |
| 1151 | # ST1B, ST1H, ST1W, ST1D; require msz <= esz | |
| 1152 | ST_zpri 1110010 .. esz:2 0.... 111 ... ..... ..... \ | |
| 1153 | @rpri_store_msz nreg=0 | |
| 1154 | ||
| 1155 | # SVE contiguous store (scalar plus scalar) | |
| 1156 | # ST1B, ST1H, ST1W, ST1D; require msz <= esz | |
| 1157 | # Enumerate msz lest we conflict with STR_zri. | |
| 1158 | ST_zprr 1110010 00 .. ..... 010 ... ..... ..... \ | |
| 1159 | @rprr_store_esz_n0 msz=0 | |
| 1160 | ST_zprr 1110010 01 .. ..... 010 ... ..... ..... \ | |
| 1161 | @rprr_store_esz_n0 msz=1 | |
| 1162 | ST_zprr 1110010 10 .. ..... 010 ... ..... ..... \ | |
| 1163 | @rprr_store_esz_n0 msz=2 | |
| 1164 | ST_zprr 1110010 11 11 ..... 010 ... ..... ..... \ | |
| 1165 | @rprr_store msz=3 esz=3 nreg=0 | |
| 1166 | ||
| 1167 | # SVE contiguous non-temporal store (scalar plus immediate) (nreg == 0) | |
| 1168 | # SVE store multiple structures (scalar plus immediate) (nreg != 0) | |
| 1169 | ST_zpri 1110010 .. nreg:2 1.... 111 ... ..... ..... \ | |
| 1170 | @rpri_store_msz esz=%size_23 | |
| 1171 | ||
| 1172 | # SVE contiguous non-temporal store (scalar plus scalar) (nreg == 0) | |
| 1173 | # SVE store multiple structures (scalar plus scalar) (nreg != 0) | |
| 1174 | ST_zprr 1110010 msz:2 nreg:2 ..... 011 ... ..... ..... \ | |
| 1175 | @rprr_store esz=%size_23 | |
| f6dbf62a RH |
1176 | |
| 1177 | # SVE 32-bit scatter store (scalar plus 32-bit scaled offsets) | |
| 1178 | # Require msz > 0 && msz <= esz. | |
| 1179 | ST1_zprz 1110010 .. 11 ..... 100 ... ..... ..... \ | |
| 1180 | @rprr_scatter_store xs=0 esz=2 scale=1 | |
| 1181 | ST1_zprz 1110010 .. 11 ..... 110 ... ..... ..... \ | |
| 1182 | @rprr_scatter_store xs=1 esz=2 scale=1 | |
| 1183 | ||
| 1184 | # SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets) | |
| 1185 | # Require msz <= esz. | |
| 1186 | ST1_zprz 1110010 .. 10 ..... 100 ... ..... ..... \ | |
| 1187 | @rprr_scatter_store xs=0 esz=2 scale=0 | |
| 1188 | ST1_zprz 1110010 .. 10 ..... 110 ... ..... ..... \ | |
| 1189 | @rprr_scatter_store xs=1 esz=2 scale=0 | |
| 1190 | ||
| 1191 | # SVE 64-bit scatter store (scalar plus 64-bit scaled offset) | |
| 1192 | # Require msz > 0 | |
| 1193 | ST1_zprz 1110010 .. 01 ..... 101 ... ..... ..... \ | |
| 1194 | @rprr_scatter_store xs=2 esz=3 scale=1 | |
| 1195 | ||
| 1196 | # SVE 64-bit scatter store (scalar plus 64-bit unscaled offset) | |
| 1197 | ST1_zprz 1110010 .. 00 ..... 101 ... ..... ..... \ | |
| 1198 | @rprr_scatter_store xs=2 esz=3 scale=0 | |
| 1199 | ||
| 408ecde9 RH |
1200 | # SVE 64-bit scatter store (vector plus immediate) |
| 1201 | ST1_zpiz 1110010 .. 10 ..... 101 ... ..... ..... \ | |
| 1202 | @rpri_scatter_store esz=3 | |
| 1203 | ||
| 1204 | # SVE 32-bit scatter store (vector plus immediate) | |
| 1205 | ST1_zpiz 1110010 .. 11 ..... 101 ... ..... ..... \ | |
| 1206 | @rpri_scatter_store esz=2 | |
| 1207 | ||
| f6dbf62a RH |
1208 | # SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offset) |
| 1209 | # Require msz > 0 | |
| 1210 | ST1_zprz 1110010 .. 01 ..... 100 ... ..... ..... \ | |
| 1211 | @rprr_scatter_store xs=0 esz=3 scale=1 | |
| 1212 | ST1_zprz 1110010 .. 01 ..... 110 ... ..... ..... \ | |
| 1213 | @rprr_scatter_store xs=1 esz=3 scale=1 | |
| 1214 | ||
| 1215 | # SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offset) | |
| 1216 | ST1_zprz 1110010 .. 00 ..... 100 ... ..... ..... \ | |
| 1217 | @rprr_scatter_store xs=0 esz=3 scale=0 | |
| 1218 | ST1_zprz 1110010 .. 00 ..... 110 ... ..... ..... \ | |
| 1219 | @rprr_scatter_store xs=1 esz=3 scale=0 | |
| 5dad1ba5 RH |
1220 | |
| 1221 | #### SVE2 Support | |
| 1222 | ||
| 1223 | ### SVE2 Integer Multiply - Unpredicated | |
| 1224 | ||
| 1225 | # SVE2 integer multiply vectors (unpredicated) | |
| 1226 | MUL_zzz 00000100 .. 1 ..... 0110 00 ..... ..... @rd_rn_rm | |
| 1227 | SMULH_zzz 00000100 .. 1 ..... 0110 10 ..... ..... @rd_rn_rm | |
| 1228 | UMULH_zzz 00000100 .. 1 ..... 0110 11 ..... ..... @rd_rn_rm | |
| 1229 | PMUL_zzz 00000100 00 1 ..... 0110 01 ..... ..... @rd_rn_rm_e0 | |
| d4b1e59d | 1230 | |
| 169d7c58 RH |
1231 | # SVE2 signed saturating doubling multiply high (unpredicated) |
| 1232 | SQDMULH_zzz 00000100 .. 1 ..... 0111 00 ..... ..... @rd_rn_rm | |
| 1233 | SQRDMULH_zzz 00000100 .. 1 ..... 0111 01 ..... ..... @rd_rn_rm | |
| 1234 | ||
| d4b1e59d RH |
1235 | ### SVE2 Integer - Predicated |
| 1236 | ||
| 1237 | SADALP_zpzz 01000100 .. 000 100 101 ... ..... ..... @rdm_pg_rn | |
| 1238 | UADALP_zpzz 01000100 .. 000 101 101 ... ..... ..... @rdm_pg_rn | |
| db366da8 RH |
1239 | |
| 1240 | ### SVE2 integer unary operations (predicated) | |
| 1241 | ||
| 1242 | URECPE 01000100 .. 000 000 101 ... ..... ..... @rd_pg_rn | |
| 1243 | URSQRTE 01000100 .. 000 001 101 ... ..... ..... @rd_pg_rn | |
| 1244 | SQABS 01000100 .. 001 000 101 ... ..... ..... @rd_pg_rn | |
| 1245 | SQNEG 01000100 .. 001 001 101 ... ..... ..... @rd_pg_rn | |
| 45d9503d RH |
1246 | |
| 1247 | ### SVE2 saturating/rounding bitwise shift left (predicated) | |
| 1248 | ||
| 1249 | SRSHL 01000100 .. 000 010 100 ... ..... ..... @rdn_pg_rm | |
| 1250 | URSHL 01000100 .. 000 011 100 ... ..... ..... @rdn_pg_rm | |
| 1251 | SRSHL 01000100 .. 000 110 100 ... ..... ..... @rdm_pg_rn # SRSHLR | |
| 1252 | URSHL 01000100 .. 000 111 100 ... ..... ..... @rdm_pg_rn # URSHLR | |
| 1253 | ||
| 1254 | SQSHL 01000100 .. 001 000 100 ... ..... ..... @rdn_pg_rm | |
| 1255 | UQSHL 01000100 .. 001 001 100 ... ..... ..... @rdn_pg_rm | |
| 1256 | SQSHL 01000100 .. 001 100 100 ... ..... ..... @rdm_pg_rn # SQSHLR | |
| 1257 | UQSHL 01000100 .. 001 101 100 ... ..... ..... @rdm_pg_rn # UQSHLR | |
| 1258 | ||
| 1259 | SQRSHL 01000100 .. 001 010 100 ... ..... ..... @rdn_pg_rm | |
| 1260 | UQRSHL 01000100 .. 001 011 100 ... ..... ..... @rdn_pg_rm | |
| 1261 | SQRSHL 01000100 .. 001 110 100 ... ..... ..... @rdm_pg_rn # SQRSHLR | |
| 1262 | UQRSHL 01000100 .. 001 111 100 ... ..... ..... @rdm_pg_rn # UQRSHLR | |
| a47dc220 RH |
1263 | |
| 1264 | ### SVE2 integer halving add/subtract (predicated) | |
| 1265 | ||
| 1266 | SHADD 01000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm | |
| 1267 | UHADD 01000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm | |
| 1268 | SHSUB 01000100 .. 010 010 100 ... ..... ..... @rdn_pg_rm | |
| 1269 | UHSUB 01000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm | |
| 1270 | SRHADD 01000100 .. 010 100 100 ... ..... ..... @rdn_pg_rm | |
| 1271 | URHADD 01000100 .. 010 101 100 ... ..... ..... @rdn_pg_rm | |
| 1272 | SHSUB 01000100 .. 010 110 100 ... ..... ..... @rdm_pg_rn # SHSUBR | |
| 1273 | UHSUB 01000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # UHSUBR | |
| 8597dc8b RH |
1274 | |
| 1275 | ### SVE2 integer pairwise arithmetic | |
| 1276 | ||
| 1277 | ADDP 01000100 .. 010 001 101 ... ..... ..... @rdn_pg_rm | |
| 1278 | SMAXP 01000100 .. 010 100 101 ... ..... ..... @rdn_pg_rm | |
| 1279 | UMAXP 01000100 .. 010 101 101 ... ..... ..... @rdn_pg_rm | |
| 1280 | SMINP 01000100 .. 010 110 101 ... ..... ..... @rdn_pg_rm | |
| 1281 | UMINP 01000100 .. 010 111 101 ... ..... ..... @rdn_pg_rm | |
| 4f07fbeb RH |
1282 | |
| 1283 | ### SVE2 saturating add/subtract (predicated) | |
| 1284 | ||
| 1285 | SQADD_zpzz 01000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm | |
| 1286 | UQADD_zpzz 01000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm | |
| 1287 | SQSUB_zpzz 01000100 .. 011 010 100 ... ..... ..... @rdn_pg_rm | |
| 1288 | UQSUB_zpzz 01000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm | |
| 1289 | SUQADD 01000100 .. 011 100 100 ... ..... ..... @rdn_pg_rm | |
| 1290 | USQADD 01000100 .. 011 101 100 ... ..... ..... @rdn_pg_rm | |
| 1291 | SQSUB_zpzz 01000100 .. 011 110 100 ... ..... ..... @rdm_pg_rn # SQSUBR | |
| 1292 | UQSUB_zpzz 01000100 .. 011 111 100 ... ..... ..... @rdm_pg_rn # UQSUBR | |
| 0ce1dda8 RH |
1293 | |
| 1294 | #### SVE2 Widening Integer Arithmetic | |
| 1295 | ||
| 1296 | ## SVE2 integer add/subtract long | |
| 1297 | ||
| 1298 | SADDLB 01000101 .. 0 ..... 00 0000 ..... ..... @rd_rn_rm | |
| 1299 | SADDLT 01000101 .. 0 ..... 00 0001 ..... ..... @rd_rn_rm | |
| 1300 | UADDLB 01000101 .. 0 ..... 00 0010 ..... ..... @rd_rn_rm | |
| 1301 | UADDLT 01000101 .. 0 ..... 00 0011 ..... ..... @rd_rn_rm | |
| 1302 | ||
| 1303 | SSUBLB 01000101 .. 0 ..... 00 0100 ..... ..... @rd_rn_rm | |
| 1304 | SSUBLT 01000101 .. 0 ..... 00 0101 ..... ..... @rd_rn_rm | |
| 1305 | USUBLB 01000101 .. 0 ..... 00 0110 ..... ..... @rd_rn_rm | |
| 1306 | USUBLT 01000101 .. 0 ..... 00 0111 ..... ..... @rd_rn_rm | |
| 1307 | ||
| 1308 | SABDLB 01000101 .. 0 ..... 00 1100 ..... ..... @rd_rn_rm | |
| 1309 | SABDLT 01000101 .. 0 ..... 00 1101 ..... ..... @rd_rn_rm | |
| 1310 | UABDLB 01000101 .. 0 ..... 00 1110 ..... ..... @rd_rn_rm | |
| 1311 | UABDLT 01000101 .. 0 ..... 00 1111 ..... ..... @rd_rn_rm | |
| daec426b RH |
1312 | |
| 1313 | ## SVE2 integer add/subtract interleaved long | |
| 1314 | ||
| 1315 | SADDLBT 01000101 .. 0 ..... 1000 00 ..... ..... @rd_rn_rm | |
| 1316 | SSUBLBT 01000101 .. 0 ..... 1000 10 ..... ..... @rd_rn_rm | |
| 1317 | SSUBLTB 01000101 .. 0 ..... 1000 11 ..... ..... @rd_rn_rm | |
| 81fccf09 RH |
1318 | |
| 1319 | ## SVE2 integer add/subtract wide | |
| 1320 | ||
| 1321 | SADDWB 01000101 .. 0 ..... 010 000 ..... ..... @rd_rn_rm | |
| 1322 | SADDWT 01000101 .. 0 ..... 010 001 ..... ..... @rd_rn_rm | |
| 1323 | UADDWB 01000101 .. 0 ..... 010 010 ..... ..... @rd_rn_rm | |
| 1324 | UADDWT 01000101 .. 0 ..... 010 011 ..... ..... @rd_rn_rm | |
| 1325 | ||
| 1326 | SSUBWB 01000101 .. 0 ..... 010 100 ..... ..... @rd_rn_rm | |
| 1327 | SSUBWT 01000101 .. 0 ..... 010 101 ..... ..... @rd_rn_rm | |
| 1328 | USUBWB 01000101 .. 0 ..... 010 110 ..... ..... @rd_rn_rm | |
| 1329 | USUBWT 01000101 .. 0 ..... 010 111 ..... ..... @rd_rn_rm | |
| 69ccc099 RH |
1330 | |
| 1331 | ## SVE2 integer multiply long | |
| 1332 | ||
| 1333 | SQDMULLB_zzz 01000101 .. 0 ..... 011 000 ..... ..... @rd_rn_rm | |
| 1334 | SQDMULLT_zzz 01000101 .. 0 ..... 011 001 ..... ..... @rd_rn_rm | |
| e3a56131 RH |
1335 | PMULLB 01000101 .. 0 ..... 011 010 ..... ..... @rd_rn_rm |
| 1336 | PMULLT 01000101 .. 0 ..... 011 011 ..... ..... @rd_rn_rm | |
| 69ccc099 RH |
1337 | SMULLB_zzz 01000101 .. 0 ..... 011 100 ..... ..... @rd_rn_rm |
| 1338 | SMULLT_zzz 01000101 .. 0 ..... 011 101 ..... ..... @rd_rn_rm | |
| 1339 | UMULLB_zzz 01000101 .. 0 ..... 011 110 ..... ..... @rd_rn_rm | |
| 1340 | UMULLT_zzz 01000101 .. 0 ..... 011 111 ..... ..... @rd_rn_rm | |
| 4269fef1 RH |
1341 | |
| 1342 | ## SVE2 bitwise shift left long | |
| 1343 | ||
| 1344 | # Note bit23 == 0 is handled by esz > 0 in do_sve2_shll_tb. | |
| 1345 | SSHLLB 01000101 .. 0 ..... 1010 00 ..... ..... @rd_rn_tszimm_shl | |
| 1346 | SSHLLT 01000101 .. 0 ..... 1010 01 ..... ..... @rd_rn_tszimm_shl | |
| 1347 | USHLLB 01000101 .. 0 ..... 1010 10 ..... ..... @rd_rn_tszimm_shl | |
| 1348 | USHLLT 01000101 .. 0 ..... 1010 11 ..... ..... @rd_rn_tszimm_shl | |
| 2df3ca55 RH |
1349 | |
| 1350 | ## SVE2 bitwise exclusive-or interleaved | |
| 1351 | ||
| 1352 | EORBT 01000101 .. 0 ..... 10010 0 ..... ..... @rd_rn_rm | |
| 1353 | EORTB 01000101 .. 0 ..... 10010 1 ..... ..... @rd_rn_rm | |
| cb9c33b8 RH |
1354 | |
| 1355 | ## SVE2 bitwise permute | |
| 1356 | ||
| 1357 | BEXT 01000101 .. 0 ..... 1011 00 ..... ..... @rd_rn_rm | |
| 1358 | BDEP 01000101 .. 0 ..... 1011 01 ..... ..... @rd_rn_rm | |
| 1359 | BGRP 01000101 .. 0 ..... 1011 10 ..... ..... @rd_rn_rm | |
| ed4a6387 RH |
1360 | |
| 1361 | #### SVE2 Accumulate | |
| 1362 | ||
| 1363 | ## SVE2 complex integer add | |
| 1364 | ||
| 1365 | CADD_rot90 01000101 .. 00000 0 11011 0 ..... ..... @rdn_rm | |
| 1366 | CADD_rot270 01000101 .. 00000 0 11011 1 ..... ..... @rdn_rm | |
| 1367 | SQCADD_rot90 01000101 .. 00000 1 11011 0 ..... ..... @rdn_rm | |
| 1368 | SQCADD_rot270 01000101 .. 00000 1 11011 1 ..... ..... @rdn_rm | |
| 38650638 RH |
1369 | |
| 1370 | ## SVE2 integer absolute difference and accumulate long | |
| 1371 | ||
| 1372 | SABALB 01000101 .. 0 ..... 1100 00 ..... ..... @rda_rn_rm | |
| 1373 | SABALT 01000101 .. 0 ..... 1100 01 ..... ..... @rda_rn_rm | |
| 1374 | UABALB 01000101 .. 0 ..... 1100 10 ..... ..... @rda_rn_rm | |
| 1375 | UABALT 01000101 .. 0 ..... 1100 11 ..... ..... @rda_rn_rm | |
| b8295dfb RH |
1376 | |
| 1377 | ## SVE2 integer add/subtract long with carry | |
| 1378 | ||
| 1379 | # ADC and SBC decoded via size in helper dispatch. | |
| 1380 | ADCLB 01000101 .. 0 ..... 11010 0 ..... ..... @rda_rn_rm | |
| 1381 | ADCLT 01000101 .. 0 ..... 11010 1 ..... ..... @rda_rn_rm | |
| a7e3a90e RH |
1382 | |
| 1383 | ## SVE2 bitwise shift right and accumulate | |
| 1384 | ||
| 1385 | # TODO: Use @rda and %reg_movprfx here. | |
| 1386 | SSRA 01000101 .. 0 ..... 1110 00 ..... ..... @rd_rn_tszimm_shr | |
| 1387 | USRA 01000101 .. 0 ..... 1110 01 ..... ..... @rd_rn_tszimm_shr | |
| 1388 | SRSRA 01000101 .. 0 ..... 1110 10 ..... ..... @rd_rn_tszimm_shr | |
| 1389 | URSRA 01000101 .. 0 ..... 1110 11 ..... ..... @rd_rn_tszimm_shr | |
| fc12b46a RH |
1390 | |
| 1391 | ## SVE2 bitwise shift and insert | |
| 1392 | ||
| 1393 | SRI 01000101 .. 0 ..... 11110 0 ..... ..... @rd_rn_tszimm_shr | |
| 1394 | SLI 01000101 .. 0 ..... 11110 1 ..... ..... @rd_rn_tszimm_shl | |
| 289a1797 RH |
1395 | |
| 1396 | ## SVE2 integer absolute difference and accumulate | |
| 1397 | ||
| 1398 | # TODO: Use @rda and %reg_movprfx here. | |
| 1399 | SABA 01000101 .. 0 ..... 11111 0 ..... ..... @rd_rn_rm | |
| 1400 | UABA 01000101 .. 0 ..... 11111 1 ..... ..... @rd_rn_rm | |
| 5ff2838d RH |
1401 | |
| 1402 | #### SVE2 Narrowing | |
| 1403 | ||
| 1404 | ## SVE2 saturating extract narrow | |
| 1405 | ||
| 1406 | # Bits 23, 18-16 are zero, limited in the translator via esz < 3 & imm == 0. | |
| 1407 | SQXTNB 01000101 .. 1 ..... 010 000 ..... ..... @rd_rn_tszimm_shl | |
| 1408 | SQXTNT 01000101 .. 1 ..... 010 001 ..... ..... @rd_rn_tszimm_shl | |
| 1409 | UQXTNB 01000101 .. 1 ..... 010 010 ..... ..... @rd_rn_tszimm_shl | |
| 1410 | UQXTNT 01000101 .. 1 ..... 010 011 ..... ..... @rd_rn_tszimm_shl | |
| 1411 | SQXTUNB 01000101 .. 1 ..... 010 100 ..... ..... @rd_rn_tszimm_shl | |
| 1412 | SQXTUNT 01000101 .. 1 ..... 010 101 ..... ..... @rd_rn_tszimm_shl | |
| b87dbeeb | 1413 | |
| 46d111b2 RH |
1414 | ## SVE2 bitwise shift right narrow |
| 1415 | ||
| 1416 | # Bit 23 == 0 is handled by esz > 0 in the translator. | |
| 81fd3e6e RH |
1417 | SQSHRUNB 01000101 .. 1 ..... 00 0000 ..... ..... @rd_rn_tszimm_shr |
| 1418 | SQSHRUNT 01000101 .. 1 ..... 00 0001 ..... ..... @rd_rn_tszimm_shr | |
| 1419 | SQRSHRUNB 01000101 .. 1 ..... 00 0010 ..... ..... @rd_rn_tszimm_shr | |
| 1420 | SQRSHRUNT 01000101 .. 1 ..... 00 0011 ..... ..... @rd_rn_tszimm_shr | |
| 46d111b2 RH |
1421 | SHRNB 01000101 .. 1 ..... 00 0100 ..... ..... @rd_rn_tszimm_shr |
| 1422 | SHRNT 01000101 .. 1 ..... 00 0101 ..... ..... @rd_rn_tszimm_shr | |
| 1423 | RSHRNB 01000101 .. 1 ..... 00 0110 ..... ..... @rd_rn_tszimm_shr | |
| 1424 | RSHRNT 01000101 .. 1 ..... 00 0111 ..... ..... @rd_rn_tszimm_shr | |
| 743bb147 RH |
1425 | SQSHRNB 01000101 .. 1 ..... 00 1000 ..... ..... @rd_rn_tszimm_shr |
| 1426 | SQSHRNT 01000101 .. 1 ..... 00 1001 ..... ..... @rd_rn_tszimm_shr | |
| 1427 | SQRSHRNB 01000101 .. 1 ..... 00 1010 ..... ..... @rd_rn_tszimm_shr | |
| 1428 | SQRSHRNT 01000101 .. 1 ..... 00 1011 ..... ..... @rd_rn_tszimm_shr | |
| c13418da RH |
1429 | UQSHRNB 01000101 .. 1 ..... 00 1100 ..... ..... @rd_rn_tszimm_shr |
| 1430 | UQSHRNT 01000101 .. 1 ..... 00 1101 ..... ..... @rd_rn_tszimm_shr | |
| 1431 | UQRSHRNB 01000101 .. 1 ..... 00 1110 ..... ..... @rd_rn_tszimm_shr | |
| 1432 | UQRSHRNT 01000101 .. 1 ..... 00 1111 ..... ..... @rd_rn_tszimm_shr | |
| 46d111b2 | 1433 | |
| 40d5ea50 SL |
1434 | ## SVE2 integer add/subtract narrow high part |
| 1435 | ||
| 1436 | ADDHNB 01000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm | |
| 1437 | ADDHNT 01000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm | |
| 0ea3ff02 SL |
1438 | RADDHNB 01000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm |
| 1439 | RADDHNT 01000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm | |
| c3cd6766 SL |
1440 | SUBHNB 01000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm |
| 1441 | SUBHNT 01000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm | |
| e9443d10 SL |
1442 | RSUBHNB 01000101 .. 1 ..... 011 110 ..... ..... @rd_rn_rm |
| 1443 | RSUBHNT 01000101 .. 1 ..... 011 111 ..... ..... @rd_rn_rm | |
| 40d5ea50 | 1444 | |
| e0ae6ec3 SL |
1445 | ### SVE2 Character Match |
| 1446 | ||
| 1447 | MATCH 01000101 .. 1 ..... 100 ... ..... 0 .... @pd_pg_rn_rm | |
| 1448 | NMATCH 01000101 .. 1 ..... 100 ... ..... 1 .... @pd_pg_rn_rm | |
| 1449 | ||
| 7d47ac94 SL |
1450 | ### SVE2 Histogram Computation |
| 1451 | ||
| 1452 | HISTCNT 01000101 .. 1 ..... 110 ... ..... ..... @rd_pg_rn_rm | |
| 1453 | HISTSEG 01000101 .. 1 ..... 101 000 ..... ..... @rd_rn_rm | |
| 1454 | ||
| b87dbeeb SL |
1455 | ## SVE2 floating-point pairwise operations |
| 1456 | ||
| 1457 | FADDP 01100100 .. 010 00 0 100 ... ..... ..... @rdn_pg_rm | |
| 1458 | FMAXNMP 01100100 .. 010 10 0 100 ... ..... ..... @rdn_pg_rm | |
| 1459 | FMINNMP 01100100 .. 010 10 1 100 ... ..... ..... @rdn_pg_rm | |
| 1460 | FMAXP 01100100 .. 010 11 0 100 ... ..... ..... @rdn_pg_rm | |
| 1461 | FMINP 01100100 .. 010 11 1 100 ... ..... ..... @rdn_pg_rm | |
| bfc9307e RH |
1462 | |
| 1463 | #### SVE Integer Multiply-Add (unpredicated) | |
| 1464 | ||
| 1465 | ## SVE2 saturating multiply-add long | |
| 1466 | ||
| 1467 | SQDMLALB_zzzw 01000100 .. 0 ..... 0110 00 ..... ..... @rda_rn_rm | |
| 1468 | SQDMLALT_zzzw 01000100 .. 0 ..... 0110 01 ..... ..... @rda_rn_rm | |
| 1469 | SQDMLSLB_zzzw 01000100 .. 0 ..... 0110 10 ..... ..... @rda_rn_rm | |
| 1470 | SQDMLSLT_zzzw 01000100 .. 0 ..... 0110 11 ..... ..... @rda_rn_rm | |
| 1471 | ||
| 1472 | ## SVE2 saturating multiply-add interleaved long | |
| 1473 | ||
| 1474 | SQDMLALBT 01000100 .. 0 ..... 00001 0 ..... ..... @rda_rn_rm | |
| 1475 | SQDMLSLBT 01000100 .. 0 ..... 00001 1 ..... ..... @rda_rn_rm | |
| ab3ddf31 RH |
1476 | |
| 1477 | ## SVE2 saturating multiply-add high | |
| 1478 | ||
| 1479 | SQRDMLAH_zzzz 01000100 .. 0 ..... 01110 0 ..... ..... @rda_rn_rm | |
| 1480 | SQRDMLSH_zzzz 01000100 .. 0 ..... 01110 1 ..... ..... @rda_rn_rm | |
| 45a32e80 RH |
1481 | |
| 1482 | ## SVE2 integer multiply-add long | |
| 1483 | ||
| 1484 | SMLALB_zzzw 01000100 .. 0 ..... 010 000 ..... ..... @rda_rn_rm | |
| 1485 | SMLALT_zzzw 01000100 .. 0 ..... 010 001 ..... ..... @rda_rn_rm | |
| 1486 | UMLALB_zzzw 01000100 .. 0 ..... 010 010 ..... ..... @rda_rn_rm | |
| 1487 | UMLALT_zzzw 01000100 .. 0 ..... 010 011 ..... ..... @rda_rn_rm | |
| 1488 | SMLSLB_zzzw 01000100 .. 0 ..... 010 100 ..... ..... @rda_rn_rm | |
| 1489 | SMLSLT_zzzw 01000100 .. 0 ..... 010 101 ..... ..... @rda_rn_rm | |
| 1490 | UMLSLB_zzzw 01000100 .. 0 ..... 010 110 ..... ..... @rda_rn_rm | |
| 1491 | UMLSLT_zzzw 01000100 .. 0 ..... 010 111 ..... ..... @rda_rn_rm | |
| d782d3ca RH |
1492 | |
| 1493 | ## SVE2 complex integer multiply-add | |
| 1494 | ||
| 1495 | CMLA_zzzz 01000100 esz:2 0 rm:5 0010 rot:2 rn:5 rd:5 ra=%reg_movprfx | |
| 1496 | SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx | |
| 6ebca45f | 1497 | |
| 4f26756b SL |
1498 | ### SVE2 floating point matrix multiply accumulate |
| 1499 | ||
| 1500 | FMMLA 01100100 .. 1 ..... 111001 ..... ..... @rda_rn_rm | |
| 1501 | ||
| cf327449 SL |
1502 | ### SVE2 Memory Gather Load Group |
| 1503 | ||
| 1504 | # SVE2 64-bit gather non-temporal load | |
| 1505 | # (scalar plus unpacked 32-bit unscaled offsets) | |
| 1506 | LDNT1_zprz 1100010 msz:2 00 rm:5 1 u:1 0 pg:3 rn:5 rd:5 \ | |
| 1507 | &rprr_gather_load xs=0 esz=3 scale=0 ff=0 | |
| 1508 | ||
| 1509 | # SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets) | |
| 1510 | LDNT1_zprz 1000010 msz:2 00 rm:5 10 u:1 pg:3 rn:5 rd:5 \ | |
| 1511 | &rprr_gather_load xs=0 esz=2 scale=0 ff=0 | |
| 1512 | ||
| 6ebca45f SL |
1513 | ### SVE2 Memory Store Group |
| 1514 | ||
| 1515 | # SVE2 64-bit scatter non-temporal store (vector plus scalar) | |
| 1516 | STNT1_zprz 1110010 .. 00 ..... 001 ... ..... ..... \ | |
| 1517 | @rprr_scatter_store xs=2 esz=3 scale=0 | |
| 1518 | ||
| 1519 | # SVE2 32-bit scatter non-temporal store (vector plus scalar) | |
| 1520 | STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \ | |
| 1521 | @rprr_scatter_store xs=0 esz=2 scale=0 |