projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 38388f7e RH |
1 | # AArch64 SVE instruction descriptions |
| 2 | # | |
| 3 | # Copyright (c) 2017 Linaro, Ltd | |
| 4 | # | |
| 5 | # This library is free software; you can redistribute it and/or | |
| 6 | # modify it under the terms of the GNU Lesser General Public | |
| 7 | # License as published by the Free Software Foundation; either | |
| 8 | # version 2 of the License, or (at your option) any later version. | |
| 9 | # | |
| 10 | # This library is distributed in the hope that it will be useful, | |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 13 | # Lesser General Public License for more details. | |
| 14 | # | |
| 15 | # You should have received a copy of the GNU Lesser General Public | |
| 16 | # License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
| 17 | ||
| 18 | # | |
| 19 | # This file is processed by scripts/decodetree.py | |
| 20 | # | |
| 21 | ||
| d1822297 RH |
22 | ########################################################################### |
| 23 | # Named fields. These are primarily for disjoint fields. | |
| 24 | ||
| f25a2361 | 25 | %imm4_16_p1 16:4 !function=plus1 |
| ccd841c3 | 26 | %imm6_22_5 22:1 5:5 |
| 30562ab7 | 27 | %imm7_22_16 22:2 16:5 |
| b94f8f60 | 28 | %imm8_16_10 16:5 10:3 |
| d1822297 RH |
29 | %imm9_16_10 16:s6 10:3 |
| 30 | ||
| ccd841c3 RH |
31 | # A combination of tsz:imm3 -- extract esize. |
| 32 | %tszimm_esz 22:2 5:5 !function=tszimm_esz | |
| 33 | # A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3) | |
| 34 | %tszimm_shr 22:2 5:5 !function=tszimm_shr | |
| 35 | # A combination of tsz:imm3 -- extract (tsz:imm3) - esize | |
| 36 | %tszimm_shl 22:2 5:5 !function=tszimm_shl | |
| 37 | ||
| d9d78dcc RH |
38 | # Similarly for the tszh/tszl pair at 22/16 for zzi |
| 39 | %tszimm16_esz 22:2 16:5 !function=tszimm_esz | |
| 40 | %tszimm16_shr 22:2 16:5 !function=tszimm_shr | |
| 41 | %tszimm16_shl 22:2 16:5 !function=tszimm_shl | |
| 42 | ||
| f25a2361 RH |
43 | # Signed 8-bit immediate, optionally shifted left by 8. |
| 44 | %sh8_i8s 5:9 !function=expand_imm_sh8s | |
| 6e6a157d RH |
45 | # Unsigned 8-bit immediate, optionally shifted left by 8. |
| 46 | %sh8_i8u 5:9 !function=expand_imm_sh8u | |
| f25a2361 | 47 | |
| f97cfd59 RH |
48 | # Either a copy of rd (at bit 0), or a different source |
| 49 | # as propagated via the MOVPRFX instruction. | |
| 50 | %reg_movprfx 0:5 | |
| 51 | ||
| 38388f7e RH |
52 | ########################################################################### |
| 53 | # Named attribute sets. These are used to make nice(er) names | |
| 54 | # when creating helpers common to those for the individual | |
| 55 | # instruction patterns. | |
| 56 | ||
| 028e2a7b | 57 | &rr_esz rd rn esz |
| d1822297 | 58 | &rri rd rn imm |
| e1fa1164 | 59 | &rr_dbm rd rn dbm |
| 4b242d9c | 60 | &rrri rd rn rm imm |
| d9d78dcc | 61 | &rri_esz rd rn imm esz |
| 38388f7e | 62 | &rrr_esz rd rn rm esz |
| 047cec97 | 63 | &rpr_esz rd pg rn esz |
| 35da316f | 64 | &rpr_s rd pg rn s |
| 516e246a | 65 | &rprr_s rd pg rn rm s |
| f97cfd59 | 66 | &rprr_esz rd pg rn rm esz |
| 96a36e4a | 67 | &rprrr_esz rd pg rn rm ra esz |
| ccd841c3 | 68 | &rpri_esz rd pg rn imm esz |
| 24e82e68 RH |
69 | &ptrue rd esz pat s |
| 70 | &incdec_cnt rd pat esz imm d u | |
| 71 | &incdec2_cnt rd rn pat esz imm d u | |
| 9ee3a611 RH |
72 | &incdec_pred rd pg esz d u |
| 73 | &incdec2_pred rd rn pg esz d u | |
| 38388f7e RH |
74 | |
| 75 | ########################################################################### | |
| 76 | # Named instruction formats. These are generally used to | |
| 77 | # reduce the amount of duplication between instruction patterns. | |
| 78 | ||
| 028e2a7b RH |
79 | # Two operand with unused vector element size |
| 80 | @pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0 | |
| 81 | ||
| 82 | # Two operand | |
| 83 | @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz | |
| 0762cd42 | 84 | @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz |
| 028e2a7b | 85 | |
| 35da316f RH |
86 | # Two operand with governing predicate, flags setting |
| 87 | @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s | |
| 88 | ||
| 38388f7e RH |
89 | # Three operand with unused vector element size |
| 90 | @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 | |
| 91 | ||
| 516e246a RH |
92 | # Three predicate operand, with governing predicate, flag setting |
| 93 | @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s | |
| 94 | ||
| fea98f9c RH |
95 | # Three operand, vector element size |
| 96 | @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz | |
| d731d8cb | 97 | @pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz |
| 30562ab7 RH |
98 | @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \ |
| 99 | &rrr_esz rn=%reg_movprfx | |
| 6e6a157d RH |
100 | @rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \ |
| 101 | &rri_esz rn=%reg_movprfx imm=%sh8_i8u | |
| 102 | @rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \ | |
| 103 | &rri_esz rn=%reg_movprfx | |
| 104 | @rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \ | |
| 105 | &rri_esz rn=%reg_movprfx | |
| fea98f9c | 106 | |
| 4b242d9c RH |
107 | # Three operand with "memory" size, aka immediate left shift |
| 108 | @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri | |
| 109 | ||
| f97cfd59 RH |
110 | # Two register operand, with governing predicate, vector element size |
| 111 | @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \ | |
| 112 | &rprr_esz rn=%reg_movprfx | |
| 113 | @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ | |
| 114 | &rprr_esz rm=%reg_movprfx | |
| d3fe4a29 | 115 | @rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz |
| 757f9cff | 116 | @pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz |
| f97cfd59 | 117 | |
| 96a36e4a RH |
118 | # Three register operand, with governing predicate, vector element size |
| 119 | @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ | |
| 120 | &rprrr_esz ra=%reg_movprfx | |
| 121 | @rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \ | |
| 122 | &rprrr_esz rn=%reg_movprfx | |
| 123 | ||
| 047cec97 RH |
124 | # One register operand, with governing predicate, vector element size |
| 125 | @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz | |
| 9ee3a611 | 126 | @rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz |
| 047cec97 | 127 | |
| 96f922cc RH |
128 | # Two register operands with a 6-bit signed immediate. |
| 129 | @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri | |
| 130 | ||
| ccd841c3 RH |
131 | # Two register operand, one immediate operand, with predicate, |
| 132 | # element size encoded as TSZHL. User must fill in imm. | |
| 133 | @rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \ | |
| 134 | &rpri_esz rn=%reg_movprfx esz=%tszimm_esz | |
| 135 | ||
| d9d78dcc RH |
136 | # Similarly without predicate. |
| 137 | @rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \ | |
| 138 | &rri_esz esz=%tszimm16_esz | |
| 139 | ||
| f25a2361 RH |
140 | # Two register operand, one immediate operand, with 4-bit predicate. |
| 141 | # User must fill in imm. | |
| 142 | @rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \ | |
| 143 | &rpri_esz rn=%reg_movprfx | |
| 144 | ||
| e1fa1164 RH |
145 | # Two register operand, one encoded bitmask. |
| 146 | @rdn_dbm ........ .. .... dbm:13 rd:5 \ | |
| 147 | &rr_dbm rn=%reg_movprfx | |
| 148 | ||
| 38cadeba RH |
149 | # Predicate output, vector and immediate input, |
| 150 | # controlling predicate, element size. | |
| 151 | @pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz | |
| 152 | @pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz | |
| 153 | ||
| d1822297 RH |
154 | # Basic Load/Store with 9-bit immediate offset |
| 155 | @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ | |
| 156 | &rri imm=%imm9_16_10 | |
| 157 | @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \ | |
| 158 | &rri imm=%imm9_16_10 | |
| 159 | ||
| 24e82e68 RH |
160 | # One register, pattern, and uint4+1. |
| 161 | # User must fill in U and D. | |
| 162 | @incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ | |
| 163 | &incdec_cnt imm=%imm4_16_p1 | |
| 164 | @incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ | |
| 165 | &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx | |
| 166 | ||
| 9ee3a611 RH |
167 | # One register, predicate. |
| 168 | # User must fill in U and D. | |
| 169 | @incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred | |
| 170 | @incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \ | |
| 171 | &incdec2_pred rn=%reg_movprfx | |
| 172 | ||
| 38388f7e RH |
173 | ########################################################################### |
| 174 | # Instruction patterns. Grouped according to the SVE encodingindex.xhtml. | |
| 175 | ||
| f97cfd59 RH |
176 | ### SVE Integer Arithmetic - Binary Predicated Group |
| 177 | ||
| 178 | # SVE bitwise logical vector operations (predicated) | |
| 179 | ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm | |
| 180 | EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm | |
| 181 | AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm | |
| 182 | BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm | |
| 183 | ||
| 184 | # SVE integer add/subtract vectors (predicated) | |
| 185 | ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm | |
| 186 | SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm | |
| 187 | SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR | |
| 188 | ||
| 189 | # SVE integer min/max/difference (predicated) | |
| 190 | SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm | |
| 191 | UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm | |
| 192 | SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm | |
| 193 | UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm | |
| 194 | SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm | |
| 195 | UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm | |
| 196 | ||
| 197 | # SVE integer multiply/divide (predicated) | |
| 198 | MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm | |
| 199 | SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm | |
| 200 | UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm | |
| 201 | # Note that divide requires size >= 2; below 2 is unallocated. | |
| 202 | SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm | |
| 203 | UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm | |
| 204 | SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR | |
| 205 | UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR | |
| 206 | ||
| 047cec97 RH |
207 | ### SVE Integer Reduction Group |
| 208 | ||
| 209 | # SVE bitwise logical reduction (predicated) | |
| 210 | ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn | |
| 211 | EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn | |
| 212 | ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn | |
| 213 | ||
| 214 | # SVE integer add reduction (predicated) | |
| 215 | # Note that saddv requires size != 3. | |
| 216 | UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn | |
| 217 | SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn | |
| 218 | ||
| 219 | # SVE integer min/max reduction (predicated) | |
| 220 | SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn | |
| 221 | UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn | |
| 222 | SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn | |
| 223 | UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn | |
| 224 | ||
| ccd841c3 RH |
225 | ### SVE Shift by Immediate - Predicated Group |
| 226 | ||
| 227 | # SVE bitwise shift by immediate (predicated) | |
| 228 | ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \ | |
| 229 | @rdn_pg_tszimm imm=%tszimm_shr | |
| 230 | LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \ | |
| 231 | @rdn_pg_tszimm imm=%tszimm_shr | |
| 232 | LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \ | |
| 233 | @rdn_pg_tszimm imm=%tszimm_shl | |
| 234 | ASRD 00000100 .. 000 100 100 ... .. ... ..... \ | |
| 235 | @rdn_pg_tszimm imm=%tszimm_shr | |
| 236 | ||
| 27721dbb RH |
237 | # SVE bitwise shift by vector (predicated) |
| 238 | ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm | |
| 239 | LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm | |
| 240 | LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm | |
| 241 | ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR | |
| 242 | LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR | |
| 243 | LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR | |
| 244 | ||
| fe7f8dfb RH |
245 | # SVE bitwise shift by wide elements (predicated) |
| 246 | # Note these require size != 3. | |
| 247 | ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm | |
| 248 | LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm | |
| 249 | LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm | |
| 250 | ||
| afac6d04 RH |
251 | ### SVE Integer Arithmetic - Unary Predicated Group |
| 252 | ||
| 253 | # SVE unary bit operations (predicated) | |
| 254 | # Note esz != 0 for FABS and FNEG. | |
| 255 | CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn | |
| 256 | CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn | |
| 257 | CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn | |
| 258 | CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn | |
| 259 | NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn | |
| 260 | FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn | |
| 261 | FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn | |
| 262 | ||
| 263 | # SVE integer unary operations (predicated) | |
| 264 | # Note esz > original size for extensions. | |
| 265 | ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn | |
| 266 | NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn | |
| 267 | SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn | |
| 268 | UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn | |
| 269 | SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn | |
| 270 | UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn | |
| 271 | SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn | |
| 272 | UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn | |
| 273 | ||
| 96a36e4a RH |
274 | ### SVE Integer Multiply-Add Group |
| 275 | ||
| 276 | # SVE integer multiply-add writing addend (predicated) | |
| 277 | MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm | |
| 278 | MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm | |
| 279 | ||
| 280 | # SVE integer multiply-add writing multiplicand (predicated) | |
| 281 | MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD | |
| 282 | MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB | |
| 283 | ||
| fea98f9c RH |
284 | ### SVE Integer Arithmetic - Unpredicated Group |
| 285 | ||
| 286 | # SVE integer add/subtract vectors (unpredicated) | |
| 287 | ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm | |
| 288 | SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm | |
| 289 | SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm | |
| 290 | UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm | |
| 291 | SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm | |
| 292 | UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm | |
| 293 | ||
| 38388f7e RH |
294 | ### SVE Logical - Unpredicated Group |
| 295 | ||
| 296 | # SVE bitwise logical operations (unpredicated) | |
| 297 | AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
| 298 | ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
| 299 | EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
| 300 | BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
| d1822297 | 301 | |
| 9a56c9c3 RH |
302 | ### SVE Index Generation Group |
| 303 | ||
| 304 | # SVE index generation (immediate start, immediate increment) | |
| 305 | INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5 | |
| 306 | ||
| 307 | # SVE index generation (immediate start, register increment) | |
| 308 | INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5 | |
| 309 | ||
| 310 | # SVE index generation (register start, immediate increment) | |
| 311 | INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 | |
| 312 | ||
| 313 | # SVE index generation (register start, register increment) | |
| 314 | INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm | |
| 315 | ||
| 96f922cc RH |
316 | ### SVE Stack Allocation Group |
| 317 | ||
| 318 | # SVE stack frame adjustment | |
| 319 | ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 | |
| 320 | ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 | |
| 321 | ||
| 322 | # SVE stack frame size | |
| 323 | RDVL 00000100 101 11111 01010 imm:s6 rd:5 | |
| 324 | ||
| d9d78dcc RH |
325 | ### SVE Bitwise Shift - Unpredicated Group |
| 326 | ||
| 327 | # SVE bitwise shift by immediate (unpredicated) | |
| 328 | ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \ | |
| 329 | @rd_rn_tszimm imm=%tszimm16_shr | |
| 330 | LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \ | |
| 331 | @rd_rn_tszimm imm=%tszimm16_shr | |
| 332 | LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \ | |
| 333 | @rd_rn_tszimm imm=%tszimm16_shl | |
| 334 | ||
| 335 | # SVE bitwise shift by wide elements (unpredicated) | |
| 336 | # Note esz != 3 | |
| 337 | ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm | |
| 338 | LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm | |
| 339 | LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm | |
| 340 | ||
| 4b242d9c RH |
341 | ### SVE Compute Vector Address Group |
| 342 | ||
| 343 | # SVE vector address generation | |
| 344 | ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
| 345 | ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
| 346 | ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
| 347 | ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
| 348 | ||
| 0762cd42 RH |
349 | ### SVE Integer Misc - Unpredicated Group |
| 350 | ||
| 351 | # SVE floating-point exponential accelerator | |
| 352 | # Note esz != 0 | |
| 353 | FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn | |
| 354 | ||
| a1f233f2 RH |
355 | # SVE floating-point trig select coefficient |
| 356 | # Note esz != 0 | |
| 357 | FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm | |
| 358 | ||
| 24e82e68 RH |
359 | ### SVE Element Count Group |
| 360 | ||
| 361 | # SVE element count | |
| 362 | CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1 | |
| 363 | ||
| 364 | # SVE inc/dec register by element count | |
| 365 | INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1 | |
| 366 | ||
| 367 | # SVE saturating inc/dec register by element count | |
| 368 | SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt | |
| 369 | SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt | |
| 370 | ||
| 371 | # SVE inc/dec vector by element count | |
| 372 | # Note this requires esz != 0. | |
| 373 | INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1 | |
| 374 | ||
| 375 | # SVE saturating inc/dec vector by element count | |
| 376 | # Note these require esz != 0. | |
| 377 | SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt | |
| 516e246a | 378 | |
| e1fa1164 RH |
379 | ### SVE Bitwise Immediate Group |
| 380 | ||
| 381 | # SVE bitwise logical with immediate (unpredicated) | |
| 382 | ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm | |
| 383 | EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm | |
| 384 | AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm | |
| 385 | ||
| 386 | # SVE broadcast bitmask immediate | |
| 387 | DUPM 00000101 11 0000 dbm:13 rd:5 | |
| 388 | ||
| f25a2361 RH |
389 | ### SVE Integer Wide Immediate - Predicated Group |
| 390 | ||
| 391 | # SVE copy floating-point immediate (predicated) | |
| 392 | FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4 | |
| 393 | ||
| 394 | # SVE copy integer immediate (predicated) | |
| 395 | CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s | |
| 396 | CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s | |
| 397 | ||
| b94f8f60 RH |
398 | ### SVE Permute - Extract Group |
| 399 | ||
| 400 | # SVE extract vector (immediate offset) | |
| 401 | EXT 00000101 001 ..... 000 ... rm:5 rd:5 \ | |
| 402 | &rrri rn=%reg_movprfx imm=%imm8_16_10 | |
| 403 | ||
| 30562ab7 RH |
404 | ### SVE Permute - Unpredicated Group |
| 405 | ||
| 406 | # SVE broadcast general register | |
| 407 | DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn | |
| 408 | ||
| 409 | # SVE broadcast indexed element | |
| 410 | DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \ | |
| 411 | &rri imm=%imm7_22_16 | |
| 412 | ||
| 413 | # SVE insert SIMD&FP scalar register | |
| 414 | INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm | |
| 415 | ||
| 416 | # SVE insert general register | |
| 417 | INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm | |
| 418 | ||
| 419 | # SVE reverse vector elements | |
| 420 | REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn | |
| 421 | ||
| 422 | # SVE vector table lookup | |
| 423 | TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm | |
| 424 | ||
| 425 | # SVE unpack vector elements | |
| 426 | UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5 | |
| 427 | ||
| d731d8cb RH |
428 | ### SVE Permute - Predicates Group |
| 429 | ||
| 430 | # SVE permute predicate elements | |
| 431 | ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm | |
| 432 | ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm | |
| 433 | UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm | |
| 434 | UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm | |
| 435 | TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm | |
| 436 | TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm | |
| 437 | ||
| 438 | # SVE reverse predicate elements | |
| 439 | REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn | |
| 440 | ||
| 441 | # SVE unpack predicate elements | |
| 442 | PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0 | |
| 443 | PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0 | |
| 444 | ||
| 234b48e9 RH |
445 | ### SVE Permute - Interleaving Group |
| 446 | ||
| 447 | # SVE permute vector elements | |
| 448 | ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm | |
| 449 | ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm | |
| 450 | UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm | |
| 451 | UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm | |
| 452 | TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm | |
| 453 | TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm | |
| 454 | ||
| 3ca879ae RH |
455 | ### SVE Permute - Predicated Group |
| 456 | ||
| 457 | # SVE compress active elements | |
| 458 | # Note esz >= 2 | |
| 459 | COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn | |
| 460 | ||
| ef23cb72 RH |
461 | # SVE conditionally broadcast element to vector |
| 462 | CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm | |
| 463 | CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm | |
| 464 | ||
| 465 | # SVE conditionally copy element to SIMD&FP scalar | |
| 466 | CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn | |
| 467 | CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn | |
| 468 | ||
| 469 | # SVE conditionally copy element to general register | |
| 470 | CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn | |
| 471 | CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn | |
| 472 | ||
| 473 | # SVE copy element to SIMD&FP scalar register | |
| 474 | LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn | |
| 475 | LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn | |
| 476 | ||
| 477 | # SVE copy element to general register | |
| 478 | LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn | |
| 479 | LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn | |
| 480 | ||
| 792a5578 RH |
481 | # SVE copy element from SIMD&FP scalar register |
| 482 | CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn | |
| 483 | ||
| 484 | # SVE copy element from general register to vector (predicated) | |
| 485 | CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn | |
| 486 | ||
| dae8fb90 RH |
487 | # SVE reverse within elements |
| 488 | # Note esz >= operation size | |
| 489 | REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn | |
| 490 | REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn | |
| 491 | REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn | |
| 492 | RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn | |
| 493 | ||
| b48ff240 RH |
494 | # SVE vector splice (predicated) |
| 495 | SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm | |
| 496 | ||
| d3fe4a29 RH |
497 | ### SVE Select Vectors Group |
| 498 | ||
| 499 | # SVE select vector elements (predicated) | |
| 500 | SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm | |
| 501 | ||
| 757f9cff RH |
502 | ### SVE Integer Compare - Vectors Group |
| 503 | ||
| 504 | # SVE integer compare_vectors | |
| 505 | CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm | |
| 506 | CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm | |
| 507 | CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm | |
| 508 | CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm | |
| 509 | CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm | |
| 510 | CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm | |
| 511 | ||
| 512 | # SVE integer compare with wide elements | |
| 513 | # Note these require esz != 3. | |
| 514 | CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm | |
| 515 | CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm | |
| 516 | CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm | |
| 517 | CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm | |
| 518 | CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm | |
| 519 | CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm | |
| 520 | CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm | |
| 521 | CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm | |
| 522 | CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm | |
| 523 | CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm | |
| 524 | ||
| 38cadeba RH |
525 | ### SVE Integer Compare - Unsigned Immediate Group |
| 526 | ||
| 527 | # SVE integer compare with unsigned immediate | |
| 528 | CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7 | |
| 529 | CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7 | |
| 530 | CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7 | |
| 531 | CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7 | |
| 532 | ||
| 533 | ### SVE Integer Compare - Signed Immediate Group | |
| 534 | ||
| 535 | # SVE integer compare with signed immediate | |
| 536 | CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5 | |
| 537 | CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5 | |
| 538 | CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5 | |
| 539 | CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5 | |
| 540 | CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5 | |
| 541 | CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5 | |
| 542 | ||
| e1fa1164 RH |
543 | ### SVE Predicate Logical Operations Group |
| 544 | ||
| 516e246a RH |
545 | # SVE predicate logical operations |
| 546 | AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
| 547 | BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
| 548 | EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s | |
| 549 | SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s | |
| 550 | ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
| 551 | ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
| 552 | NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s | |
| 553 | NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s | |
| 554 | ||
| 9e18d7a6 RH |
555 | ### SVE Predicate Misc Group |
| 556 | ||
| 557 | # SVE predicate test | |
| 558 | PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000 | |
| 559 | ||
| 028e2a7b RH |
560 | # SVE predicate initialize |
| 561 | PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4 | |
| 562 | ||
| 563 | # SVE initialize FFR | |
| 564 | SETFFR 00100101 0010 1100 1001 0000 0000 0000 | |
| 565 | ||
| 566 | # SVE zero predicate register | |
| 567 | PFALSE 00100101 0001 1000 1110 0100 0000 rd:4 | |
| 568 | ||
| 569 | # SVE predicate read from FFR (predicated) | |
| 570 | RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4 | |
| 571 | ||
| 572 | # SVE predicate read from FFR (unpredicated) | |
| 573 | RDFFR 00100101 0001 1001 1111 0000 0000 rd:4 | |
| 574 | ||
| 575 | # SVE FFR write from predicate (WRFFR) | |
| 576 | WRFFR 00100101 0010 1000 1001 000 rn:4 00000 | |
| 577 | ||
| 578 | # SVE predicate first active | |
| 579 | PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0 | |
| 580 | ||
| 581 | # SVE predicate next active | |
| 582 | PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn | |
| 583 | ||
| 35da316f RH |
584 | ### SVE Partition Break Group |
| 585 | ||
| 586 | # SVE propagate break from previous partition | |
| 587 | BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
| 588 | BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
| 589 | ||
| 590 | # SVE partition break condition | |
| 591 | BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s | |
| 592 | BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s | |
| 593 | BRKA_m 00100101 0. 01000001 .... 0 .... 1 .... @pd_pg_pn_s | |
| 594 | BRKB_m 00100101 1. 01000001 .... 0 .... 1 .... @pd_pg_pn_s | |
| 595 | ||
| 596 | # SVE propagate break to next partition | |
| 597 | BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s | |
| 598 | ||
| 9ee3a611 RH |
599 | ### SVE Predicate Count Group |
| 600 | ||
| 601 | # SVE predicate count | |
| 602 | CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn | |
| 603 | ||
| 604 | # SVE inc/dec register by predicate count | |
| 605 | INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1 | |
| 606 | ||
| 607 | # SVE inc/dec vector by predicate count | |
| 608 | INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1 | |
| 609 | ||
| 610 | # SVE saturating inc/dec register by predicate count | |
| 611 | SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred | |
| 612 | SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred | |
| 613 | ||
| 614 | # SVE saturating inc/dec vector by predicate count | |
| 615 | SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred | |
| 616 | ||
| caf1cefc RH |
617 | ### SVE Integer Compare - Scalars Group |
| 618 | ||
| 619 | # SVE conditionally terminate scalars | |
| 620 | CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000 | |
| 621 | ||
| 622 | # SVE integer compare scalar count and limit | |
| 623 | WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4 | |
| 624 | ||
| ed491961 RH |
625 | ### SVE Integer Wide Immediate - Unpredicated Group |
| 626 | ||
| 627 | # SVE broadcast floating-point immediate (unpredicated) | |
| 628 | FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5 | |
| 629 | ||
| 630 | # SVE broadcast integer immediate (unpredicated) | |
| 631 | DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s | |
| 632 | ||
| 6e6a157d RH |
633 | # SVE integer add/subtract immediate (unpredicated) |
| 634 | ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u | |
| 635 | SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u | |
| 636 | SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u | |
| 637 | SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u | |
| 638 | UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u | |
| 639 | SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u | |
| 640 | UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u | |
| 641 | ||
| 642 | # SVE integer min/max immediate (unpredicated) | |
| 643 | SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s | |
| 644 | UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u | |
| 645 | SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s | |
| 646 | UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u | |
| 647 | ||
| 648 | # SVE integer multiply immediate (unpredicated) | |
| 649 | MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s | |
| 650 | ||
| 29b80469 RH |
651 | ### SVE Floating Point Arithmetic - Unpredicated Group |
| 652 | ||
| 653 | # SVE floating-point arithmetic (unpredicated) | |
| 654 | FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm | |
| 655 | FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm | |
| 656 | FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm | |
| 657 | FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm | |
| 658 | FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm | |
| 659 | FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm | |
| 660 | ||
| d1822297 RH |
661 | ### SVE Memory - 32-bit Gather and Unsized Contiguous Group |
| 662 | ||
| 663 | # SVE load predicate register | |
| 664 | LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9 | |
| 665 | ||
| 666 | # SVE load vector register | |
| 667 | LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9 |